diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp index 40a80576ba86b..7f350557692d4 100644 --- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -2056,6 +2056,9 @@ void AsmPrinter::emitDanglingPrefetchTargets() { /// EmitFunctionBody - This method emits the body and trailer for a /// function. void AsmPrinter::emitFunctionBody() { + // Renumber blocks for consistent output of labels. + MF->RenumberBlocks(); + emitFunctionHeader(); // Emit target-specific gunk before the function body. @@ -2068,7 +2071,8 @@ void AsmPrinter::emitFunctionBody() { OwnedMDT = std::make_unique(); OwnedMDT->recalculate(*MF); MDT = OwnedMDT.get(); - } + } else + MDT->updateBlockNumbers(); // We renumbered the function above. // Get MachineLoopInfo or compute it on the fly if it's unavailable MLI = GetMLI(*MF); diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp index 38bc72ff154fa..2a8cda775997f 100644 --- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp @@ -2686,6 +2686,8 @@ static void addMBBNames(const Module &M, const SPIRVInstrInfo &TII, .isValid()) continue; MachineRegisterInfo &MRI = MF->getRegInfo(); + // Ensure that blocks are numbered in a consistent order. + MF->RenumberBlocks(); for (auto &MBB : *MF) { if (!MBB.hasName() || MBB.empty()) continue; diff --git a/llvm/test/CodeGen/AArch64/basic-block-sections-cold.ll b/llvm/test/CodeGen/AArch64/basic-block-sections-cold.ll index 6641ef6a51c14..ed9ab70bd7fe8 100644 --- a/llvm/test/CodeGen/AArch64/basic-block-sections-cold.ll +++ b/llvm/test/CodeGen/AArch64/basic-block-sections-cold.ll @@ -41,11 +41,11 @@ declare i32 @_Z3foov() #1 ; SECTIONS: .section .text.split._Z3bazb,"ax",@progbits ; SECTIONS: _Z3bazb.cold: ; SECTIONS-NOT: .section .text.hot._Z3bazb._Z3bazb.2,"ax",@progbits,unique -; SECTIONS: .LBB0_2: +; SECTIONS: .LBB0_5: ; SECTIONS: .size _Z3bazb, .Lfunc_end{{[0-9]}}-_Z3bazb ; SPLIT: .section .text.unlikely._Z3bazb,"ax",@progbits ; SPLIT-NEXT: _Z3bazb.cold: ; SPLIT-NEXT: bl _Z3barv -; SPLIT: .LBB0_2: -; SPLIT: .LBB_END0_2: +; SPLIT: .LBB0_5: +; SPLIT: .LBB_END0_5: diff --git a/llvm/test/CodeGen/AArch64/basic-block-sections-unsafe.ll b/llvm/test/CodeGen/AArch64/basic-block-sections-unsafe.ll index a83a47c9c129c..20c65463e8075 100644 --- a/llvm/test/CodeGen/AArch64/basic-block-sections-unsafe.ll +++ b/llvm/test/CodeGen/AArch64/basic-block-sections-unsafe.ll @@ -20,9 +20,9 @@ define void @_Z3asm_goto(i1 zeroext %0, i1 zeroext %1) nounwind { ; CHECK: .section .text.unlikely._Z3asm_goto,"ax",@progbits ; CHECK-NEXT: _Z3asm_goto.cold: ; CHECK-NEXT: bl bam - ; CHECK: .LBB0_4: + ; CHECK: .LBB0_7: ; CHECK: ret - ; CHECK: .LBB_END0_4: + ; CHECK: .LBB_END0_7: br i1 %0, label %3, label %5 diff --git a/llvm/test/CodeGen/AArch64/branch-relax-b.ll b/llvm/test/CodeGen/AArch64/branch-relax-b.ll index 44b730f2207ff..04cc98a592728 100644 --- a/llvm/test/CodeGen/AArch64/branch-relax-b.ll +++ b/llvm/test/CodeGen/AArch64/branch-relax-b.ll @@ -4,15 +4,15 @@ define void @relax_b_nospill(i1 zeroext %0) { ; CHECK-LABEL: relax_b_nospill: ; CHECK: // %bb.0: // %entry ; CHECK-NEXT: tbnz w0, -; CHECK-SAME: LBB0_1 -; CHECK-NEXT: // %bb.3: // %entry -; CHECK-NEXT: b .LBB0_2 -; CHECK-NEXT: .LBB0_1: // %iftrue +; CHECK-SAME: LBB0_2 +; CHECK-NEXT: // %bb.1: // %entry +; CHECK-NEXT: b .LBB0_3 +; CHECK-NEXT: .LBB0_2: // %iftrue ; CHECK-NEXT: //APP ; CHECK-NEXT: .zero 2048 ; CHECK-NEXT: //NO_APP ; CHECK-NEXT: ret -; CHECK-NEXT: .LBB0_2: // %iffalse +; CHECK-NEXT: .LBB0_3: // %iffalse ; CHECK-NEXT: //APP ; CHECK-NEXT: .zero 8 ; CHECK-NEXT: //NO_APP @@ -38,25 +38,25 @@ define void @relax_b_spill() { ; CHECK-COUNT-29: mov {{x[0-9]+}}, ; CHECK-NOT: mov {{x[0-9]+}}, ; CHECK-NEXT: //NO_APP -; CHECK-NEXT: b.eq .LBB1_1 -; CHECK-NEXT: // %bb.4: // %entry +; CHECK-NEXT: b.eq .LBB1_2 +; CHECK-NEXT: // %bb.1: // %entry ; CHECK-NEXT: str [[SPILL_REGISTER:x[0-9]+]], [sp, ; CHECK-SAME: -16]! -; CHECK-NEXT: b .LBB1_5 -; CHECK-NEXT: .LBB1_1: // %iftrue +; CHECK-NEXT: b .LBB1_3 +; CHECK-NEXT: .LBB1_2: // %iftrue ; CHECK-NEXT: //APP ; CHECK-NEXT: .zero 2048 ; CHECK-NEXT: //NO_APP -; CHECK-NEXT: b .LBB1_3 -; CHECK-NEXT: .LBB1_5: // %iffalse +; CHECK-NEXT: b .LBB1_5 +; CHECK-NEXT: .LBB1_3: // %iffalse ; CHECK-NEXT: ldr [[SPILL_REGISTER]], [sp], ; CHECK-SAME: 16 -; CHECK-NEXT: // %bb.2: // %iffalse +; CHECK-NEXT: // %bb.4: // %iffalse ; CHECK-NEXT: //APP ; CHECK-COUNT-29: // reg use {{x[0-9]+}} ; CHECK-NOT: // reg use {{x[0-9]+}} ; CHECK-NEXT: //NO_APP -; CHECK-NEXT: .LBB1_3: // %common.ret +; CHECK-NEXT: .LBB1_5: // %common.ret ; CHECK-COUNT-5: // 16-byte Folded Reload ; CHECK-NOT: // 16-byte Folded Reload ; CHECK-NEXT: ret @@ -141,20 +141,20 @@ define void @relax_b_x16_taken() { ; CHECK-NEXT: //APP ; CHECK-NEXT: mov x16, #1 ; CHECK-NEXT: //NO_APP -; CHECK-NEXT: cbnz x16, .LBB2_1 -; CHECK-NEXT: // %bb.3: // %entry +; CHECK-NEXT: cbnz x16, .LBB2_2 +; CHECK-NEXT: // %bb.1: // %entry ; CHECK-NEXT: str [[SPILL_REGISTER]], [sp, ; CHECK-SAME: -16]! -; CHECK-NEXT: b .LBB2_4 -; CHECK-NEXT: .LBB2_1: // %iftrue +; CHECK-NEXT: b .LBB2_3 +; CHECK-NEXT: .LBB2_2: // %iftrue ; CHECK-NEXT: //APP ; CHECK-NEXT: .zero 2048 ; CHECK-NEXT: //NO_APP ; CHECK-NEXT: ret -; CHECK-NEXT: .LBB2_4: // %iffalse +; CHECK-NEXT: .LBB2_3: // %iffalse ; CHECK-NEXT: ldr [[SPILL_REGISTER]], [sp], ; CHECK-SAME: 16 -; CHECK-NEXT: // %bb.2: // %iffalse +; CHECK-NEXT: // %bb.4: // %iffalse ; CHECK-NEXT: //APP ; CHECK-NEXT: // reg use x16 ; CHECK-NEXT: //NO_APP diff --git a/llvm/test/CodeGen/AArch64/branch-relax-bcc.ll b/llvm/test/CodeGen/AArch64/branch-relax-bcc.ll index 1a901dc40f14c..f75a99ceb7d0b 100644 --- a/llvm/test/CodeGen/AArch64/branch-relax-bcc.ll +++ b/llvm/test/CodeGen/AArch64/branch-relax-bcc.ll @@ -7,14 +7,14 @@ define i32 @invert_bcc(float %x, float %y) #0 { ; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: mov w0, wzr ; CHECK-NEXT: mov w8, #42 ; =0x2a -; CHECK-NEXT: b.pl LBB0_3 -; CHECK-NEXT: b LBB0_2 -; CHECK-NEXT: LBB0_3: -; CHECK-NEXT: b.gt LBB0_2 -; CHECK-NEXT: ; %bb.1: ; %common.ret +; CHECK-NEXT: b.pl LBB0_1 +; CHECK-NEXT: b LBB0_3 +; CHECK-NEXT: LBB0_1: +; CHECK-NEXT: b.gt LBB0_3 +; CHECK-NEXT: ; %bb.2: ; %common.ret ; CHECK-NEXT: str w8, [x8] ; CHECK-NEXT: ret -; CHECK-NEXT: LBB0_2: ; %bb2 +; CHECK-NEXT: LBB0_3: ; %bb2 ; CHECK-NEXT: mov w0, #1 ; =0x1 ; CHECK-NEXT: mov w8, #9 ; =0x9 ; CHECK-NEXT: ; InlineAsm Start diff --git a/llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll b/llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll index ab2ad19d0f1bf..dbec0fe3151aa 100644 --- a/llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll +++ b/llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll @@ -323,8 +323,8 @@ define amdgpu_kernel void @spill(ptr addrspace(1) %arg, i32 %cnd) #0 { ; CHECK-NEXT: ;;#ASMSTART ; CHECK-NEXT: s_mov_b32 vcc_hi, 0 ; CHECK-NEXT: ;;#ASMEND -; CHECK-NEXT: s_cbranch_scc0 .LBB0_1 -; CHECK-NEXT: ; %bb.3: ; %entry +; CHECK-NEXT: s_cbranch_scc0 .LBB0_2 +; CHECK-NEXT: ; %bb.1: ; %entry ; CHECK-NEXT: s_not_b64 exec, exec ; CHECK-NEXT: buffer_store_dword v0, off, s[96:99], 0 ; CHECK-NEXT: v_writelane_b32 v0, s0, 0 @@ -334,7 +334,7 @@ define amdgpu_kernel void @spill(ptr addrspace(1) %arg, i32 %cnd) #0 { ; CHECK-NEXT: s_add_u32 s0, s0, (.LBB0_4-.Lpost_getpc0)&4294967295 ; CHECK-NEXT: s_addc_u32 s1, s1, (.LBB0_4-.Lpost_getpc0)>>32 ; CHECK-NEXT: s_setpc_b64 s[0:1] -; CHECK-NEXT: .LBB0_1: ; %bb2 +; CHECK-NEXT: .LBB0_2: ; %bb2 ; CHECK-NEXT: ;;#ASMSTART ; CHECK-NEXT: v_nop_e64 ; CHECK-NEXT: v_nop_e64 @@ -345,13 +345,13 @@ define amdgpu_kernel void @spill(ptr addrspace(1) %arg, i32 %cnd) #0 { ; CHECK-NEXT: v_nop_e64 ; CHECK-NEXT: v_nop_e64 ; CHECK-NEXT: ;;#ASMEND -; CHECK-NEXT: s_branch .LBB0_2 +; CHECK-NEXT: s_branch .LBB0_40 ; CHECK-NEXT: .LBB0_4: ; %bb3 ; CHECK-NEXT: v_readlane_b32 s0, v0, 0 ; CHECK-NEXT: v_readlane_b32 s1, v0, 1 ; CHECK-NEXT: buffer_load_dword v0, off, s[96:99], 0 ; CHECK-NEXT: s_not_b64 exec, exec -; CHECK-NEXT: .LBB0_2: ; %bb3 +; CHECK-NEXT: .LBB0_40: ; %bb3 ; CHECK-NEXT: ;;#ASMSTART ; CHECK-NEXT: ; reg use s0 ; CHECK-NEXT: ;;#ASMEND @@ -1255,8 +1255,8 @@ define void @spill_func(ptr addrspace(1) %arg) #0 { ; CHECK-NEXT: ;;#ASMSTART ; CHECK-NEXT: s_mov_b32 vcc_hi, 0 ; CHECK-NEXT: ;;#ASMEND -; CHECK-NEXT: s_cbranch_scc0 .LBB1_1 -; CHECK-NEXT: ; %bb.3: ; %entry +; CHECK-NEXT: s_cbranch_scc0 .LBB1_2 +; CHECK-NEXT: ; %bb.1: ; %entry ; CHECK-NEXT: s_not_b64 exec, exec ; CHECK-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:4 ; CHECK-NEXT: v_writelane_b32 v1, s0, 0 @@ -1266,7 +1266,7 @@ define void @spill_func(ptr addrspace(1) %arg) #0 { ; CHECK-NEXT: s_add_u32 s0, s0, (.LBB1_4-.Lpost_getpc1)&4294967295 ; CHECK-NEXT: s_addc_u32 s1, s1, (.LBB1_4-.Lpost_getpc1)>>32 ; CHECK-NEXT: s_setpc_b64 s[0:1] -; CHECK-NEXT: .LBB1_1: ; %bb2 +; CHECK-NEXT: .LBB1_2: ; %bb2 ; CHECK-NEXT: ;;#ASMSTART ; CHECK-NEXT: v_nop_e64 ; CHECK-NEXT: v_nop_e64 @@ -1277,13 +1277,13 @@ define void @spill_func(ptr addrspace(1) %arg) #0 { ; CHECK-NEXT: v_nop_e64 ; CHECK-NEXT: v_nop_e64 ; CHECK-NEXT: ;;#ASMEND -; CHECK-NEXT: s_branch .LBB1_2 +; CHECK-NEXT: s_branch .LBB1_40 ; CHECK-NEXT: .LBB1_4: ; %bb3 ; CHECK-NEXT: v_readlane_b32 s0, v1, 0 ; CHECK-NEXT: v_readlane_b32 s1, v1, 1 ; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:4 ; CHECK-NEXT: s_not_b64 exec, exec -; CHECK-NEXT: .LBB1_2: ; %bb3 +; CHECK-NEXT: .LBB1_40: ; %bb3 ; CHECK-NEXT: ;;#ASMSTART ; CHECK-NEXT: ; reg use s0 ; CHECK-NEXT: ;;#ASMEND diff --git a/llvm/test/CodeGen/AMDGPU/branch-relaxation-debug-info.mir b/llvm/test/CodeGen/AMDGPU/branch-relaxation-debug-info.mir index 5f0f2dd1e8b08..e7eac7c837172 100644 --- a/llvm/test/CodeGen/AMDGPU/branch-relaxation-debug-info.mir +++ b/llvm/test/CodeGen/AMDGPU/branch-relaxation-debug-info.mir @@ -4,7 +4,7 @@ # block as the branch expansion. # GCN-LABEL: long_branch_dbg_value: -# GCN: ; %bb.5: ; %bb +# GCN: ; %bb.1: ; %bb # GCN-NEXT: ;DEBUG_VALUE: test_debug_value:globalptr_arg <- [DW_OP_plus_uconst 12, DW_OP_stack_value] # GCN-NEXT: .loc 1 0 42 is_stmt 0 ; /tmp/test_debug_value.cl:0:42 # GCN-NEXT: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]] diff --git a/llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx1250.ll b/llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx1250.ll index 779118bd33027..fadb34646f8c8 100644 --- a/llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx1250.ll +++ b/llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx1250.ll @@ -23,25 +23,25 @@ declare i32 @llvm.amdgcn.workitem.id.x() #1 define amdgpu_kernel void @uniform_conditional_max_short_forward_branch(ptr addrspace(1) %arg, i32 %cnd) #0 { ; GCN-LABEL: uniform_conditional_max_short_forward_branch: ; GCN: ; %bb.0: ; %bb -; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 -; GCN-NEXT: s_load_b32 s0, s[4:5], 0x2c +; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 +; GCN-NEXT: s_load_b32 s0, s[4:5], 0x2c nv ; GCN-NEXT: s_wait_kmcnt 0x0 ; GCN-NEXT: s_cmp_eq_u32 s0, 0 -; GCN-NEXT: s_cbranch_scc0 .LBB0_1 -; GCN-NEXT: ; %bb.3: ; %bb +; GCN-NEXT: s_cbranch_scc0 .LBB0_20 +; GCN-NEXT: ; %bb.1: ; %bb ; GCN-NEXT: s_get_pc_i64 s[2:3] ; GCN-NEXT: .Lpost_getpc0: ; GCN-NEXT: s_add_co_u32 s2, s2, (.LBB0_2-.Lpost_getpc0)&4294967295 ; GCN-NEXT: s_add_co_ci_u32 s3, s3, (.LBB0_2-.Lpost_getpc0)>>32 ; GCN-NEXT: s_set_pc_i64 s[2:3] -; GCN-NEXT: .LBB0_1: ; %bb2 +; GCN-NEXT: .LBB0_20: ; %bb2 ; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: v_nop_e64 ; GCN-NEXT: v_nop_e64 ; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: s_sleep 0 ; GCN-NEXT: .LBB0_2: ; %bb3 -; GCN-NEXT: s_load_b64 s[2:3], s[4:5], 0x24 +; GCN-NEXT: s_load_b64 s[2:3], s[4:5], 0x24 nv ; GCN-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0 ; GCN-NEXT: s_wait_kmcnt 0x0 ; GCN-NEXT: global_store_b32 v0, v1, s[2:3] scope:SCOPE_SYS @@ -50,22 +50,22 @@ define amdgpu_kernel void @uniform_conditional_max_short_forward_branch(ptr addr ; ; GCN-ADD-PC64-LABEL: uniform_conditional_max_short_forward_branch: ; GCN-ADD-PC64: ; %bb.0: ; %bb -; GCN-ADD-PC64-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 -; GCN-ADD-PC64-NEXT: s_load_b32 s0, s[4:5], 0x2c +; GCN-ADD-PC64-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 +; GCN-ADD-PC64-NEXT: s_load_b32 s0, s[4:5], 0x2c nv ; GCN-ADD-PC64-NEXT: s_wait_kmcnt 0x0 ; GCN-ADD-PC64-NEXT: s_cmp_eq_u32 s0, 0 -; GCN-ADD-PC64-NEXT: s_cbranch_scc0 .LBB0_1 -; GCN-ADD-PC64-NEXT: ; %bb.3: ; %bb +; GCN-ADD-PC64-NEXT: s_cbranch_scc0 .LBB0_20 +; GCN-ADD-PC64-NEXT: ; %bb.1: ; %bb ; GCN-ADD-PC64-NEXT: s_add_pc_i64 .LBB0_2-.Lpost_addpc0 ; GCN-ADD-PC64-NEXT: .Lpost_addpc0: -; GCN-ADD-PC64-NEXT: .LBB0_1: ; %bb2 +; GCN-ADD-PC64-NEXT: .LBB0_20: ; %bb2 ; GCN-ADD-PC64-NEXT: ;;#ASMSTART ; GCN-ADD-PC64-NEXT: v_nop_e64 ; GCN-ADD-PC64-NEXT: v_nop_e64 ; GCN-ADD-PC64-NEXT: ;;#ASMEND ; GCN-ADD-PC64-NEXT: s_sleep 0 ; GCN-ADD-PC64-NEXT: .LBB0_2: ; %bb3 -; GCN-ADD-PC64-NEXT: s_load_b64 s[2:3], s[4:5], 0x24 +; GCN-ADD-PC64-NEXT: s_load_b64 s[2:3], s[4:5], 0x24 nv ; GCN-ADD-PC64-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0 ; GCN-ADD-PC64-NEXT: s_wait_kmcnt 0x0 ; GCN-ADD-PC64-NEXT: global_store_b32 v0, v1, s[2:3] scope:SCOPE_SYS @@ -114,18 +114,18 @@ bb3: define amdgpu_kernel void @uniform_conditional_min_long_forward_branch(ptr addrspace(1) %arg, i32 %cnd) #0 { ; GCN-LABEL: uniform_conditional_min_long_forward_branch: ; GCN: ; %bb.0: ; %bb0 -; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 -; GCN-NEXT: s_load_b32 s0, s[4:5], 0x2c +; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 +; GCN-NEXT: s_load_b32 s0, s[4:5], 0x2c nv ; GCN-NEXT: s_wait_kmcnt 0x0 ; GCN-NEXT: s_cmp_eq_u32 s0, 0 -; GCN-NEXT: s_cbranch_scc0 .LBB1_1 -; GCN-NEXT: ; %bb.3: ; %bb0 +; GCN-NEXT: s_cbranch_scc0 .LBB1_20 +; GCN-NEXT: ; %bb.1: ; %bb0 ; GCN-NEXT: s_get_pc_i64 s[2:3] ; GCN-NEXT: .Lpost_getpc1: ; GCN-NEXT: s_add_co_u32 s2, s2, (.LBB1_2-.Lpost_getpc1)&4294967295 ; GCN-NEXT: s_add_co_ci_u32 s3, s3, (.LBB1_2-.Lpost_getpc1)>>32 ; GCN-NEXT: s_set_pc_i64 s[2:3] -; GCN-NEXT: .LBB1_1: ; %bb2 +; GCN-NEXT: .LBB1_20: ; %bb2 ; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: v_nop_e64 ; GCN-NEXT: v_nop_e64 @@ -133,7 +133,7 @@ define amdgpu_kernel void @uniform_conditional_min_long_forward_branch(ptr addrs ; GCN-NEXT: s_sleep 0 ; GCN-NEXT: s_sleep 0 ; GCN-NEXT: .LBB1_2: ; %bb3 -; GCN-NEXT: s_load_b64 s[2:3], s[4:5], 0x24 +; GCN-NEXT: s_load_b64 s[2:3], s[4:5], 0x24 nv ; GCN-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0 ; GCN-NEXT: s_wait_kmcnt 0x0 ; GCN-NEXT: global_store_b32 v0, v1, s[2:3] scope:SCOPE_SYS @@ -142,15 +142,15 @@ define amdgpu_kernel void @uniform_conditional_min_long_forward_branch(ptr addrs ; ; GCN-ADD-PC64-LABEL: uniform_conditional_min_long_forward_branch: ; GCN-ADD-PC64: ; %bb.0: ; %bb0 -; GCN-ADD-PC64-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 -; GCN-ADD-PC64-NEXT: s_load_b32 s0, s[4:5], 0x2c +; GCN-ADD-PC64-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 +; GCN-ADD-PC64-NEXT: s_load_b32 s0, s[4:5], 0x2c nv ; GCN-ADD-PC64-NEXT: s_wait_kmcnt 0x0 ; GCN-ADD-PC64-NEXT: s_cmp_eq_u32 s0, 0 -; GCN-ADD-PC64-NEXT: s_cbranch_scc0 .LBB1_1 -; GCN-ADD-PC64-NEXT: ; %bb.3: ; %bb0 +; GCN-ADD-PC64-NEXT: s_cbranch_scc0 .LBB1_20 +; GCN-ADD-PC64-NEXT: ; %bb.1: ; %bb0 ; GCN-ADD-PC64-NEXT: s_add_pc_i64 .LBB1_2-.Lpost_addpc1 ; GCN-ADD-PC64-NEXT: .Lpost_addpc1: -; GCN-ADD-PC64-NEXT: .LBB1_1: ; %bb2 +; GCN-ADD-PC64-NEXT: .LBB1_20: ; %bb2 ; GCN-ADD-PC64-NEXT: ;;#ASMSTART ; GCN-ADD-PC64-NEXT: v_nop_e64 ; GCN-ADD-PC64-NEXT: v_nop_e64 @@ -158,7 +158,7 @@ define amdgpu_kernel void @uniform_conditional_min_long_forward_branch(ptr addrs ; GCN-ADD-PC64-NEXT: s_sleep 0 ; GCN-ADD-PC64-NEXT: s_sleep 0 ; GCN-ADD-PC64-NEXT: .LBB1_2: ; %bb3 -; GCN-ADD-PC64-NEXT: s_load_b64 s[2:3], s[4:5], 0x24 +; GCN-ADD-PC64-NEXT: s_load_b64 s[2:3], s[4:5], 0x24 nv ; GCN-ADD-PC64-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0 ; GCN-ADD-PC64-NEXT: s_wait_kmcnt 0x0 ; GCN-ADD-PC64-NEXT: global_store_b32 v0, v1, s[2:3] scope:SCOPE_SYS @@ -209,18 +209,18 @@ bb3: define amdgpu_kernel void @uniform_conditional_min_long_forward_vcnd_branch(ptr addrspace(1) %arg, float %cnd) #0 { ; GCN-LABEL: uniform_conditional_min_long_forward_vcnd_branch: ; GCN: ; %bb.0: ; %bb0 -; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 -; GCN-NEXT: s_load_b32 s0, s[4:5], 0x2c +; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 +; GCN-NEXT: s_load_b32 s0, s[4:5], 0x2c nv ; GCN-NEXT: s_wait_kmcnt 0x0 ; GCN-NEXT: s_cmp_eq_f32 s0, 0 -; GCN-NEXT: s_cbranch_scc0 .LBB2_1 -; GCN-NEXT: ; %bb.3: ; %bb0 +; GCN-NEXT: s_cbranch_scc0 .LBB2_20 +; GCN-NEXT: ; %bb.1: ; %bb0 ; GCN-NEXT: s_get_pc_i64 s[2:3] ; GCN-NEXT: .Lpost_getpc2: ; GCN-NEXT: s_add_co_u32 s2, s2, (.LBB2_2-.Lpost_getpc2)&4294967295 ; GCN-NEXT: s_add_co_ci_u32 s3, s3, (.LBB2_2-.Lpost_getpc2)>>32 ; GCN-NEXT: s_set_pc_i64 s[2:3] -; GCN-NEXT: .LBB2_1: ; %bb2 +; GCN-NEXT: .LBB2_20: ; %bb2 ; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: ; 32 bytes ; GCN-NEXT: v_nop_e64 @@ -229,7 +229,7 @@ define amdgpu_kernel void @uniform_conditional_min_long_forward_vcnd_branch(ptr ; GCN-NEXT: s_sleep 0 ; GCN-NEXT: s_sleep 0 ; GCN-NEXT: .LBB2_2: ; %bb3 -; GCN-NEXT: s_load_b64 s[2:3], s[4:5], 0x24 +; GCN-NEXT: s_load_b64 s[2:3], s[4:5], 0x24 nv ; GCN-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0 ; GCN-NEXT: s_wait_kmcnt 0x0 ; GCN-NEXT: global_store_b32 v0, v1, s[2:3] scope:SCOPE_SYS @@ -238,15 +238,15 @@ define amdgpu_kernel void @uniform_conditional_min_long_forward_vcnd_branch(ptr ; ; GCN-ADD-PC64-LABEL: uniform_conditional_min_long_forward_vcnd_branch: ; GCN-ADD-PC64: ; %bb.0: ; %bb0 -; GCN-ADD-PC64-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 -; GCN-ADD-PC64-NEXT: s_load_b32 s0, s[4:5], 0x2c +; GCN-ADD-PC64-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 +; GCN-ADD-PC64-NEXT: s_load_b32 s0, s[4:5], 0x2c nv ; GCN-ADD-PC64-NEXT: s_wait_kmcnt 0x0 ; GCN-ADD-PC64-NEXT: s_cmp_eq_f32 s0, 0 -; GCN-ADD-PC64-NEXT: s_cbranch_scc0 .LBB2_1 -; GCN-ADD-PC64-NEXT: ; %bb.3: ; %bb0 +; GCN-ADD-PC64-NEXT: s_cbranch_scc0 .LBB2_20 +; GCN-ADD-PC64-NEXT: ; %bb.1: ; %bb0 ; GCN-ADD-PC64-NEXT: s_add_pc_i64 .LBB2_2-.Lpost_addpc2 ; GCN-ADD-PC64-NEXT: .Lpost_addpc2: -; GCN-ADD-PC64-NEXT: .LBB2_1: ; %bb2 +; GCN-ADD-PC64-NEXT: .LBB2_20: ; %bb2 ; GCN-ADD-PC64-NEXT: ;;#ASMSTART ; GCN-ADD-PC64-NEXT: ; 32 bytes ; GCN-ADD-PC64-NEXT: v_nop_e64 @@ -255,7 +255,7 @@ define amdgpu_kernel void @uniform_conditional_min_long_forward_vcnd_branch(ptr ; GCN-ADD-PC64-NEXT: s_sleep 0 ; GCN-ADD-PC64-NEXT: s_sleep 0 ; GCN-ADD-PC64-NEXT: .LBB2_2: ; %bb3 -; GCN-ADD-PC64-NEXT: s_load_b64 s[2:3], s[4:5], 0x24 +; GCN-ADD-PC64-NEXT: s_load_b64 s[2:3], s[4:5], 0x24 nv ; GCN-ADD-PC64-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0 ; GCN-ADD-PC64-NEXT: s_wait_kmcnt 0x0 ; GCN-ADD-PC64-NEXT: global_store_b32 v0, v1, s[2:3] scope:SCOPE_SYS @@ -306,8 +306,8 @@ bb3: define amdgpu_kernel void @min_long_forward_vbranch(ptr addrspace(1) %arg) #0 { ; GCN-LABEL: min_long_forward_vbranch: ; GCN: ; %bb.0: ; %bb -; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 -; GCN-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 +; GCN-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv ; GCN-NEXT: v_and_b32_e32 v0, 0x3ff, v0 ; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: s_wait_kmcnt 0x0 @@ -318,14 +318,14 @@ define amdgpu_kernel void @min_long_forward_vbranch(ptr addrspace(1) %arg) #0 { ; GCN-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GCN-NEXT: s_mov_b32 s0, exec_lo ; GCN-NEXT: v_cmpx_ne_u32_e32 0, v2 -; GCN-NEXT: s_cbranch_execnz .LBB3_1 -; GCN-NEXT: ; %bb.3: ; %bb +; GCN-NEXT: s_cbranch_execnz .LBB3_20 +; GCN-NEXT: ; %bb.1: ; %bb ; GCN-NEXT: s_get_pc_i64 s[2:3] ; GCN-NEXT: .Lpost_getpc3: ; GCN-NEXT: s_add_co_u32 s2, s2, (.LBB3_2-.Lpost_getpc3)&4294967295 ; GCN-NEXT: s_add_co_ci_u32 s3, s3, (.LBB3_2-.Lpost_getpc3)>>32 ; GCN-NEXT: s_set_pc_i64 s[2:3] -; GCN-NEXT: .LBB3_1: ; %bb2 +; GCN-NEXT: .LBB3_20: ; %bb2 ; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: ; 32 bytes ; GCN-NEXT: v_nop_e64 @@ -341,8 +341,8 @@ define amdgpu_kernel void @min_long_forward_vbranch(ptr addrspace(1) %arg) #0 { ; ; GCN-ADD-PC64-LABEL: min_long_forward_vbranch: ; GCN-ADD-PC64: ; %bb.0: ; %bb -; GCN-ADD-PC64-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 -; GCN-ADD-PC64-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GCN-ADD-PC64-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 +; GCN-ADD-PC64-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv ; GCN-ADD-PC64-NEXT: v_and_b32_e32 v0, 0x3ff, v0 ; GCN-ADD-PC64-NEXT: v_mov_b32_e32 v1, 0 ; GCN-ADD-PC64-NEXT: s_wait_kmcnt 0x0 @@ -353,11 +353,11 @@ define amdgpu_kernel void @min_long_forward_vbranch(ptr addrspace(1) %arg) #0 { ; GCN-ADD-PC64-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GCN-ADD-PC64-NEXT: s_mov_b32 s0, exec_lo ; GCN-ADD-PC64-NEXT: v_cmpx_ne_u32_e32 0, v2 -; GCN-ADD-PC64-NEXT: s_cbranch_execnz .LBB3_1 -; GCN-ADD-PC64-NEXT: ; %bb.3: ; %bb +; GCN-ADD-PC64-NEXT: s_cbranch_execnz .LBB3_20 +; GCN-ADD-PC64-NEXT: ; %bb.1: ; %bb ; GCN-ADD-PC64-NEXT: s_add_pc_i64 .LBB3_2-.Lpost_addpc3 ; GCN-ADD-PC64-NEXT: .Lpost_addpc3: -; GCN-ADD-PC64-NEXT: .LBB3_1: ; %bb2 +; GCN-ADD-PC64-NEXT: .LBB3_20: ; %bb2 ; GCN-ADD-PC64-NEXT: ;;#ASMSTART ; GCN-ADD-PC64-NEXT: ; 32 bytes ; GCN-ADD-PC64-NEXT: v_nop_e64 @@ -425,7 +425,7 @@ bb3: define amdgpu_kernel void @long_backward_sbranch(ptr addrspace(1) %arg) #0 { ; GCN-LABEL: long_backward_sbranch: ; GCN: ; %bb.0: ; %bb -; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GCN-NEXT: s_mov_b32 s0, 0 ; GCN-NEXT: .LBB4_1: ; %bb2 ; GCN-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -436,20 +436,20 @@ define amdgpu_kernel void @long_backward_sbranch(ptr addrspace(1) %arg) #0 { ; GCN-NEXT: v_nop_e64 ; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: s_cmp_lt_i32 s0, 10 -; GCN-NEXT: s_cbranch_scc0 .LBB4_2 -; GCN-NEXT: ; %bb.3: ; %bb2 +; GCN-NEXT: s_cbranch_scc0 .LBB4_3 +; GCN-NEXT: ; %bb.2: ; %bb2 ; GCN-NEXT: ; in Loop: Header=BB4_1 Depth=1 ; GCN-NEXT: s_get_pc_i64 s[2:3] ; GCN-NEXT: .Lpost_getpc4: ; GCN-NEXT: s_add_co_u32 s2, s2, (.LBB4_1-.Lpost_getpc4)&4294967295 ; GCN-NEXT: s_add_co_ci_u32 s3, s3, (.LBB4_1-.Lpost_getpc4)>>32 ; GCN-NEXT: s_set_pc_i64 s[2:3] -; GCN-NEXT: .LBB4_2: ; %bb3 +; GCN-NEXT: .LBB4_3: ; %bb3 ; GCN-NEXT: s_endpgm ; ; GCN-ADD-PC64-LABEL: long_backward_sbranch: ; GCN-ADD-PC64: ; %bb.0: ; %bb -; GCN-ADD-PC64-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GCN-ADD-PC64-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GCN-ADD-PC64-NEXT: s_mov_b32 s0, 0 ; GCN-ADD-PC64-NEXT: .LBB4_1: ; %bb2 ; GCN-ADD-PC64-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -460,12 +460,12 @@ define amdgpu_kernel void @long_backward_sbranch(ptr addrspace(1) %arg) #0 { ; GCN-ADD-PC64-NEXT: v_nop_e64 ; GCN-ADD-PC64-NEXT: ;;#ASMEND ; GCN-ADD-PC64-NEXT: s_cmp_lt_i32 s0, 10 -; GCN-ADD-PC64-NEXT: s_cbranch_scc0 .LBB4_2 -; GCN-ADD-PC64-NEXT: ; %bb.3: ; %bb2 +; GCN-ADD-PC64-NEXT: s_cbranch_scc0 .LBB4_3 +; GCN-ADD-PC64-NEXT: ; %bb.2: ; %bb2 ; GCN-ADD-PC64-NEXT: ; in Loop: Header=BB4_1 Depth=1 ; GCN-ADD-PC64-NEXT: s_add_pc_i64 .LBB4_1-.Lpost_addpc4 ; GCN-ADD-PC64-NEXT: .Lpost_addpc4: -; GCN-ADD-PC64-NEXT: .LBB4_2: ; %bb3 +; GCN-ADD-PC64-NEXT: .LBB4_3: ; %bb3 ; GCN-ADD-PC64-NEXT: s_endpgm ; GCN-ENABLE-ADD-PC64-LABEL: long_backward_sbranch: ; GCN-ENABLE-ADD-PC64: ; %bb.0: ; %bb @@ -510,19 +510,19 @@ bb3: define amdgpu_kernel void @uniform_unconditional_min_long_forward_branch(ptr addrspace(1) %arg, i32 %arg1) { ; GCN-LABEL: uniform_unconditional_min_long_forward_branch: ; GCN: ; %bb.0: ; %bb0 -; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 -; GCN-NEXT: s_load_b32 s0, s[4:5], 0x2c +; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 +; GCN-NEXT: s_load_b32 s0, s[4:5], 0x2c nv ; GCN-NEXT: s_wait_kmcnt 0x0 ; GCN-NEXT: s_cmp_eq_u32 s0, 0 ; GCN-NEXT: s_mov_b32 s0, -1 -; GCN-NEXT: s_cbranch_scc0 .LBB5_1 -; GCN-NEXT: ; %bb.7: ; %bb0 +; GCN-NEXT: s_cbranch_scc0 .LBB5_20 +; GCN-NEXT: ; %bb.1: ; %bb0 ; GCN-NEXT: s_get_pc_i64 s[0:1] ; GCN-NEXT: .Lpost_getpc6: ; GCN-NEXT: s_add_co_u32 s0, s0, (.LBB5_4-.Lpost_getpc6)&4294967295 ; GCN-NEXT: s_add_co_ci_u32 s1, s1, (.LBB5_4-.Lpost_getpc6)>>32 ; GCN-NEXT: s_set_pc_i64 s[0:1] -; GCN-NEXT: .LBB5_1: ; %Flow +; GCN-NEXT: .LBB5_20: ; %Flow ; GCN-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0 ; GCN-NEXT: s_cbranch_vccnz .LBB5_3 ; GCN-NEXT: .LBB5_2: ; %bb2 @@ -530,7 +530,7 @@ define amdgpu_kernel void @uniform_unconditional_min_long_forward_branch(ptr add ; GCN-NEXT: global_store_b32 v[0:1], v0, off scope:SCOPE_SYS ; GCN-NEXT: s_wait_storecnt 0x0 ; GCN-NEXT: .LBB5_3: ; %bb4 -; GCN-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GCN-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv ; GCN-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 63 ; GCN-NEXT: s_wait_kmcnt 0x0 ; GCN-NEXT: global_store_b32 v0, v1, s[0:1] scope:SCOPE_SYS @@ -543,14 +543,14 @@ define amdgpu_kernel void @uniform_unconditional_min_long_forward_branch(ptr add ; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: s_sleep 0 ; GCN-NEXT: s_sleep 0 -; GCN-NEXT: s_cbranch_execnz .LBB5_5 -; GCN-NEXT: ; %bb.9: ; %bb3 +; GCN-NEXT: s_cbranch_execnz .LBB5_7 +; GCN-NEXT: ; %bb.6: ; %bb3 ; GCN-NEXT: s_get_pc_i64 s[0:1] ; GCN-NEXT: .Lpost_getpc7: ; GCN-NEXT: s_add_co_u32 s0, s0, (.LBB5_2-.Lpost_getpc7)&4294967295 ; GCN-NEXT: s_add_co_ci_u32 s1, s1, (.LBB5_2-.Lpost_getpc7)>>32 ; GCN-NEXT: s_set_pc_i64 s[0:1] -; GCN-NEXT: .LBB5_5: ; %bb3 +; GCN-NEXT: .LBB5_7: ; %bb3 ; GCN-NEXT: s_get_pc_i64 s[0:1] ; GCN-NEXT: .Lpost_getpc5: ; GCN-NEXT: s_add_co_u32 s0, s0, (.LBB5_3-.Lpost_getpc5)&4294967295 @@ -559,16 +559,16 @@ define amdgpu_kernel void @uniform_unconditional_min_long_forward_branch(ptr add ; ; GCN-ADD-PC64-LABEL: uniform_unconditional_min_long_forward_branch: ; GCN-ADD-PC64: ; %bb.0: ; %bb0 -; GCN-ADD-PC64-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 -; GCN-ADD-PC64-NEXT: s_load_b32 s0, s[4:5], 0x2c +; GCN-ADD-PC64-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 +; GCN-ADD-PC64-NEXT: s_load_b32 s0, s[4:5], 0x2c nv ; GCN-ADD-PC64-NEXT: s_wait_kmcnt 0x0 ; GCN-ADD-PC64-NEXT: s_cmp_eq_u32 s0, 0 ; GCN-ADD-PC64-NEXT: s_mov_b32 s0, -1 -; GCN-ADD-PC64-NEXT: s_cbranch_scc0 .LBB5_1 -; GCN-ADD-PC64-NEXT: ; %bb.7: ; %bb0 +; GCN-ADD-PC64-NEXT: s_cbranch_scc0 .LBB5_20 +; GCN-ADD-PC64-NEXT: ; %bb.1: ; %bb0 ; GCN-ADD-PC64-NEXT: s_add_pc_i64 .LBB5_4-.Lpost_addpc6 ; GCN-ADD-PC64-NEXT: .Lpost_addpc6: -; GCN-ADD-PC64-NEXT: .LBB5_1: ; %Flow +; GCN-ADD-PC64-NEXT: .LBB5_20: ; %Flow ; GCN-ADD-PC64-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0 ; GCN-ADD-PC64-NEXT: s_cbranch_vccnz .LBB5_3 ; GCN-ADD-PC64-NEXT: .LBB5_2: ; %bb2 @@ -576,7 +576,7 @@ define amdgpu_kernel void @uniform_unconditional_min_long_forward_branch(ptr add ; GCN-ADD-PC64-NEXT: global_store_b32 v[0:1], v0, off scope:SCOPE_SYS ; GCN-ADD-PC64-NEXT: s_wait_storecnt 0x0 ; GCN-ADD-PC64-NEXT: .LBB5_3: ; %bb4 -; GCN-ADD-PC64-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 +; GCN-ADD-PC64-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv ; GCN-ADD-PC64-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 63 ; GCN-ADD-PC64-NEXT: s_wait_kmcnt 0x0 ; GCN-ADD-PC64-NEXT: global_store_b32 v0, v1, s[0:1] scope:SCOPE_SYS @@ -589,11 +589,11 @@ define amdgpu_kernel void @uniform_unconditional_min_long_forward_branch(ptr add ; GCN-ADD-PC64-NEXT: ;;#ASMEND ; GCN-ADD-PC64-NEXT: s_sleep 0 ; GCN-ADD-PC64-NEXT: s_sleep 0 -; GCN-ADD-PC64-NEXT: s_cbranch_execnz .LBB5_5 -; GCN-ADD-PC64-NEXT: ; %bb.9: ; %bb3 +; GCN-ADD-PC64-NEXT: s_cbranch_execnz .LBB5_7 +; GCN-ADD-PC64-NEXT: ; %bb.6: ; %bb3 ; GCN-ADD-PC64-NEXT: s_add_pc_i64 .LBB5_2-.Lpost_addpc7 ; GCN-ADD-PC64-NEXT: .Lpost_addpc7: -; GCN-ADD-PC64-NEXT: .LBB5_5: ; %bb3 +; GCN-ADD-PC64-NEXT: .LBB5_7: ; %bb3 ; GCN-ADD-PC64-NEXT: s_add_pc_i64 .LBB5_3-.Lpost_addpc5 ; GCN-ADD-PC64-NEXT: .Lpost_addpc5: ; GCN-ENABLE-ADD-PC64-LABEL: uniform_unconditional_min_long_forward_branch: @@ -660,7 +660,7 @@ bb4: define amdgpu_kernel void @uniform_unconditional_min_long_backward_branch(ptr addrspace(1) %arg, i32 %arg1) { ; GCN-LABEL: uniform_unconditional_min_long_backward_branch: ; GCN: ; %bb.0: ; %entry -; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GCN-NEXT: s_mov_b32 vcc_lo, exec_lo ; GCN-NEXT: .LBB6_1: ; %loop ; GCN-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -670,20 +670,20 @@ define amdgpu_kernel void @uniform_unconditional_min_long_backward_branch(ptr ad ; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: s_sleep 0 ; GCN-NEXT: s_sleep 0 -; GCN-NEXT: s_cbranch_vccz .LBB6_2 -; GCN-NEXT: ; %bb.3: ; %loop +; GCN-NEXT: s_cbranch_vccz .LBB6_3 +; GCN-NEXT: ; %bb.2: ; %loop ; GCN-NEXT: ; in Loop: Header=BB6_1 Depth=1 ; GCN-NEXT: s_get_pc_i64 s[0:1] ; GCN-NEXT: .Lpost_getpc8: ; GCN-NEXT: s_add_co_u32 s0, s0, (.LBB6_1-.Lpost_getpc8)&4294967295 ; GCN-NEXT: s_add_co_ci_u32 s1, s1, (.LBB6_1-.Lpost_getpc8)>>32 ; GCN-NEXT: s_set_pc_i64 s[0:1] -; GCN-NEXT: .LBB6_2: ; %DummyReturnBlock +; GCN-NEXT: .LBB6_3: ; %DummyReturnBlock ; GCN-NEXT: s_endpgm ; ; GCN-ADD-PC64-LABEL: uniform_unconditional_min_long_backward_branch: ; GCN-ADD-PC64: ; %bb.0: ; %entry -; GCN-ADD-PC64-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GCN-ADD-PC64-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GCN-ADD-PC64-NEXT: s_mov_b32 vcc_lo, exec_lo ; GCN-ADD-PC64-NEXT: .LBB6_1: ; %loop ; GCN-ADD-PC64-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -693,12 +693,12 @@ define amdgpu_kernel void @uniform_unconditional_min_long_backward_branch(ptr ad ; GCN-ADD-PC64-NEXT: ;;#ASMEND ; GCN-ADD-PC64-NEXT: s_sleep 0 ; GCN-ADD-PC64-NEXT: s_sleep 0 -; GCN-ADD-PC64-NEXT: s_cbranch_vccz .LBB6_2 -; GCN-ADD-PC64-NEXT: ; %bb.3: ; %loop +; GCN-ADD-PC64-NEXT: s_cbranch_vccz .LBB6_3 +; GCN-ADD-PC64-NEXT: ; %bb.2: ; %loop ; GCN-ADD-PC64-NEXT: ; in Loop: Header=BB6_1 Depth=1 ; GCN-ADD-PC64-NEXT: s_add_pc_i64 .LBB6_1-.Lpost_addpc8 ; GCN-ADD-PC64-NEXT: .Lpost_addpc8: -; GCN-ADD-PC64-NEXT: .LBB6_2: ; %DummyReturnBlock +; GCN-ADD-PC64-NEXT: .LBB6_3: ; %DummyReturnBlock ; GCN-ADD-PC64-NEXT: s_endpgm ; GCN-ENABLE-ADD-PC64-LABEL: uniform_unconditional_min_long_backward_branch: ; GCN-ENABLE-ADD-PC64: ; %bb.0: ; %entry @@ -738,8 +738,8 @@ loop: define amdgpu_kernel void @expand_requires_expand(i32 %cond0) #0 { ; GCN-LABEL: expand_requires_expand: ; GCN: ; %bb.0: ; %bb0 -; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 -; GCN-NEXT: s_load_b32 s0, s[4:5], 0x24 +; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 +; GCN-NEXT: s_load_b32 s0, s[4:5], 0x24 nv ; GCN-NEXT: s_wait_kmcnt 0x0 ; GCN-NEXT: s_cmp_lt_i32 s0, 0 ; GCN-NEXT: s_cselect_b32 s0, -1, 0 @@ -754,14 +754,14 @@ define amdgpu_kernel void @expand_requires_expand(i32 %cond0) #0 { ; GCN-NEXT: .LBB7_2: ; %Flow ; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GCN-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0 -; GCN-NEXT: s_cbranch_vccz .LBB7_3 -; GCN-NEXT: ; %bb.5: ; %Flow +; GCN-NEXT: s_cbranch_vccz .LBB7_40 +; GCN-NEXT: ; %bb.3: ; %Flow ; GCN-NEXT: s_get_pc_i64 s[0:1] ; GCN-NEXT: .Lpost_getpc9: ; GCN-NEXT: s_add_co_u32 s0, s0, (.LBB7_4-.Lpost_getpc9)&4294967295 ; GCN-NEXT: s_add_co_ci_u32 s1, s1, (.LBB7_4-.Lpost_getpc9)>>32 ; GCN-NEXT: s_set_pc_i64 s[0:1] -; GCN-NEXT: .LBB7_3: ; %bb2 +; GCN-NEXT: .LBB7_40: ; %bb2 ; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: v_nop_e64 ; GCN-NEXT: v_nop_e64 @@ -779,8 +779,8 @@ define amdgpu_kernel void @expand_requires_expand(i32 %cond0) #0 { ; ; GCN-ADD-PC64-LABEL: expand_requires_expand: ; GCN-ADD-PC64: ; %bb.0: ; %bb0 -; GCN-ADD-PC64-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 -; GCN-ADD-PC64-NEXT: s_load_b32 s0, s[4:5], 0x24 +; GCN-ADD-PC64-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 +; GCN-ADD-PC64-NEXT: s_load_b32 s0, s[4:5], 0x24 nv ; GCN-ADD-PC64-NEXT: s_wait_kmcnt 0x0 ; GCN-ADD-PC64-NEXT: s_cmp_lt_i32 s0, 0 ; GCN-ADD-PC64-NEXT: s_cselect_b32 s0, -1, 0 @@ -795,11 +795,11 @@ define amdgpu_kernel void @expand_requires_expand(i32 %cond0) #0 { ; GCN-ADD-PC64-NEXT: .LBB7_2: ; %Flow ; GCN-ADD-PC64-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GCN-ADD-PC64-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0 -; GCN-ADD-PC64-NEXT: s_cbranch_vccz .LBB7_3 -; GCN-ADD-PC64-NEXT: ; %bb.5: ; %Flow +; GCN-ADD-PC64-NEXT: s_cbranch_vccz .LBB7_40 +; GCN-ADD-PC64-NEXT: ; %bb.3: ; %Flow ; GCN-ADD-PC64-NEXT: s_add_pc_i64 .LBB7_4-.Lpost_addpc9 ; GCN-ADD-PC64-NEXT: .Lpost_addpc9: -; GCN-ADD-PC64-NEXT: .LBB7_3: ; %bb2 +; GCN-ADD-PC64-NEXT: .LBB7_40: ; %bb2 ; GCN-ADD-PC64-NEXT: ;;#ASMSTART ; GCN-ADD-PC64-NEXT: v_nop_e64 ; GCN-ADD-PC64-NEXT: v_nop_e64 @@ -884,26 +884,26 @@ bb3: define amdgpu_kernel void @uniform_inside_divergent(ptr addrspace(1) %out, i32 %cond) #0 { ; GCN-LABEL: uniform_inside_divergent: ; GCN: ; %bb.0: ; %entry -; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GCN-NEXT: v_and_b32_e32 v0, 0x3ff, v0 ; GCN-NEXT: s_mov_b32 s3, exec_lo ; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GCN-NEXT: v_cmpx_gt_u32_e32 16, v0 -; GCN-NEXT: s_cbranch_execnz .LBB8_1 -; GCN-NEXT: ; %bb.4: ; %entry +; GCN-NEXT: s_cbranch_execnz .LBB8_2 +; GCN-NEXT: ; %bb.1: ; %entry ; GCN-NEXT: s_get_pc_i64 s[0:1] ; GCN-NEXT: .Lpost_getpc10: ; GCN-NEXT: s_add_co_u32 s0, s0, (.LBB8_3-.Lpost_getpc10)&4294967295 ; GCN-NEXT: s_add_co_ci_u32 s1, s1, (.LBB8_3-.Lpost_getpc10)>>32 ; GCN-NEXT: s_set_pc_i64 s[0:1] -; GCN-NEXT: .LBB8_1: ; %if -; GCN-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 +; GCN-NEXT: .LBB8_2: ; %if +; GCN-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 nv ; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: s_wait_kmcnt 0x0 ; GCN-NEXT: s_cmp_lg_u32 s2, 0 ; GCN-NEXT: global_store_b32 v0, v0, s[0:1] ; GCN-NEXT: s_cbranch_scc1 .LBB8_3 -; GCN-NEXT: ; %bb.2: ; %if_uniform +; GCN-NEXT: ; %bb.3: ; %if_uniform ; GCN-NEXT: v_mov_b32_e32 v1, 1 ; GCN-NEXT: global_store_b32 v0, v1, s[0:1] ; GCN-NEXT: .LBB8_3: ; %endif @@ -914,23 +914,23 @@ define amdgpu_kernel void @uniform_inside_divergent(ptr addrspace(1) %out, i32 % ; ; GCN-ADD-PC64-LABEL: uniform_inside_divergent: ; GCN-ADD-PC64: ; %bb.0: ; %entry -; GCN-ADD-PC64-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GCN-ADD-PC64-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GCN-ADD-PC64-NEXT: v_and_b32_e32 v0, 0x3ff, v0 ; GCN-ADD-PC64-NEXT: s_mov_b32 s3, exec_lo ; GCN-ADD-PC64-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GCN-ADD-PC64-NEXT: v_cmpx_gt_u32_e32 16, v0 -; GCN-ADD-PC64-NEXT: s_cbranch_execnz .LBB8_1 -; GCN-ADD-PC64-NEXT: ; %bb.4: ; %entry +; GCN-ADD-PC64-NEXT: s_cbranch_execnz .LBB8_2 +; GCN-ADD-PC64-NEXT: ; %bb.1: ; %entry ; GCN-ADD-PC64-NEXT: s_add_pc_i64 .LBB8_3-.Lpost_addpc10 ; GCN-ADD-PC64-NEXT: .Lpost_addpc10: -; GCN-ADD-PC64-NEXT: .LBB8_1: ; %if -; GCN-ADD-PC64-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 +; GCN-ADD-PC64-NEXT: .LBB8_2: ; %if +; GCN-ADD-PC64-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 nv ; GCN-ADD-PC64-NEXT: v_mov_b32_e32 v0, 0 ; GCN-ADD-PC64-NEXT: s_wait_kmcnt 0x0 ; GCN-ADD-PC64-NEXT: s_cmp_lg_u32 s2, 0 ; GCN-ADD-PC64-NEXT: global_store_b32 v0, v0, s[0:1] ; GCN-ADD-PC64-NEXT: s_cbranch_scc1 .LBB8_3 -; GCN-ADD-PC64-NEXT: ; %bb.2: ; %if_uniform +; GCN-ADD-PC64-NEXT: ; %bb.3: ; %if_uniform ; GCN-ADD-PC64-NEXT: v_mov_b32_e32 v1, 1 ; GCN-ADD-PC64-NEXT: global_store_b32 v0, v1, s[0:1] ; GCN-ADD-PC64-NEXT: .LBB8_3: ; %endif @@ -990,7 +990,7 @@ endif: define amdgpu_kernel void @analyze_mask_branch() #0 { ; GCN-LABEL: analyze_mask_branch: ; GCN: ; %bb.0: ; %entry -; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GCN-NEXT: s_mov_b32 s0, exec_lo ; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: v_mov_b32_e64 v0, 0 @@ -1005,14 +1005,14 @@ define amdgpu_kernel void @analyze_mask_branch() #0 { ; GCN-NEXT: .LBB9_2: ; %Flow1 ; GCN-NEXT: s_wait_xcnt 0x0 ; GCN-NEXT: s_and_not1_saveexec_b32 s0, s0 -; GCN-NEXT: s_cbranch_execnz .LBB9_3 -; GCN-NEXT: ; %bb.6: ; %Flow1 +; GCN-NEXT: s_cbranch_execnz .LBB9_40 +; GCN-NEXT: ; %bb.3: ; %Flow1 ; GCN-NEXT: s_get_pc_i64 s[0:1] ; GCN-NEXT: .Lpost_getpc11: ; GCN-NEXT: s_add_co_u32 s0, s0, (.LBB9_5-.Lpost_getpc11)&4294967295 ; GCN-NEXT: s_add_co_ci_u32 s1, s1, (.LBB9_5-.Lpost_getpc11)>>32 ; GCN-NEXT: s_set_pc_i64 s[0:1] -; GCN-NEXT: .LBB9_3: ; %loop.preheader +; GCN-NEXT: .LBB9_40: ; %loop.preheader ; GCN-NEXT: s_mov_b32 vcc_lo, 0 ; GCN-NEXT: .LBB9_4: ; %loop ; GCN-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -1027,8 +1027,8 @@ define amdgpu_kernel void @analyze_mask_branch() #0 { ; GCN-NEXT: s_sleep 0 ; GCN-NEXT: s_sleep 0 ; GCN-NEXT: s_cbranch_vccnz .LBB9_5 -; GCN-NEXT: ; %bb.8: ; %loop -; GCN-NEXT: ; in Loop: Header=BB9_4 Depth=1 +; GCN-NEXT: ; %bb.6: ; %loop +; GCN-NEXT: ; in Loop: Header=BB9_5 Depth=1 ; GCN-NEXT: s_get_pc_i64 s[0:1] ; GCN-NEXT: .Lpost_getpc12: ; GCN-NEXT: s_add_co_u32 s0, s0, (.LBB9_4-.Lpost_getpc12)&4294967295 @@ -1039,7 +1039,7 @@ define amdgpu_kernel void @analyze_mask_branch() #0 { ; ; GCN-ADD-PC64-LABEL: analyze_mask_branch: ; GCN-ADD-PC64: ; %bb.0: ; %entry -; GCN-ADD-PC64-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GCN-ADD-PC64-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GCN-ADD-PC64-NEXT: s_mov_b32 s0, exec_lo ; GCN-ADD-PC64-NEXT: ;;#ASMSTART ; GCN-ADD-PC64-NEXT: v_mov_b32_e64 v0, 0 @@ -1054,11 +1054,11 @@ define amdgpu_kernel void @analyze_mask_branch() #0 { ; GCN-ADD-PC64-NEXT: .LBB9_2: ; %Flow1 ; GCN-ADD-PC64-NEXT: s_wait_xcnt 0x0 ; GCN-ADD-PC64-NEXT: s_and_not1_saveexec_b32 s0, s0 -; GCN-ADD-PC64-NEXT: s_cbranch_execnz .LBB9_3 -; GCN-ADD-PC64-NEXT: ; %bb.6: ; %Flow1 +; GCN-ADD-PC64-NEXT: s_cbranch_execnz .LBB9_40 +; GCN-ADD-PC64-NEXT: ; %bb.3: ; %Flow1 ; GCN-ADD-PC64-NEXT: s_add_pc_i64 .LBB9_5-.Lpost_addpc11 ; GCN-ADD-PC64-NEXT: .Lpost_addpc11: -; GCN-ADD-PC64-NEXT: .LBB9_3: ; %loop.preheader +; GCN-ADD-PC64-NEXT: .LBB9_40: ; %loop.preheader ; GCN-ADD-PC64-NEXT: s_mov_b32 vcc_lo, 0 ; GCN-ADD-PC64-NEXT: .LBB9_4: ; %loop ; GCN-ADD-PC64-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -1073,8 +1073,8 @@ define amdgpu_kernel void @analyze_mask_branch() #0 { ; GCN-ADD-PC64-NEXT: s_sleep 0 ; GCN-ADD-PC64-NEXT: s_sleep 0 ; GCN-ADD-PC64-NEXT: s_cbranch_vccnz .LBB9_5 -; GCN-ADD-PC64-NEXT: ; %bb.8: ; %loop -; GCN-ADD-PC64-NEXT: ; in Loop: Header=BB9_4 Depth=1 +; GCN-ADD-PC64-NEXT: ; %bb.6: ; %loop +; GCN-ADD-PC64-NEXT: ; in Loop: Header=BB9_5 Depth=1 ; GCN-ADD-PC64-NEXT: s_add_pc_i64 .LBB9_4-.Lpost_addpc12 ; GCN-ADD-PC64-NEXT: .Lpost_addpc12: ; GCN-ADD-PC64-NEXT: .LBB9_5: ; %UnifiedReturnBlock @@ -1150,8 +1150,8 @@ ret: define amdgpu_kernel void @long_branch_hang(ptr addrspace(1) nocapture %arg, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i64 %arg5) #0 { ; GCN-LABEL: long_branch_hang: ; GCN: ; %bb.0: ; %bb -; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 -; GCN-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c +; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 +; GCN-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c nv ; GCN-NEXT: s_mov_b32 s7, -1 ; GCN-NEXT: s_wait_kmcnt 0x0 ; GCN-NEXT: s_cmp_eq_u32 s0, 0 @@ -1160,17 +1160,17 @@ define amdgpu_kernel void @long_branch_hang(ptr addrspace(1) nocapture %arg, i32 ; GCN-NEXT: s_mov_b32 s0, 0 ; GCN-NEXT: s_cselect_b32 s8, -1, 0 ; GCN-NEXT: s_cmp_lt_i32 s3, 6 -; GCN-NEXT: s_cbranch_scc0 .LBB10_1 -; GCN-NEXT: ; %bb.10: ; %bb +; GCN-NEXT: s_cbranch_scc0 .LBB10_20 +; GCN-NEXT: ; %bb.1: ; %bb ; GCN-NEXT: s_get_pc_i64 s[10:11] ; GCN-NEXT: .Lpost_getpc14: ; GCN-NEXT: s_add_co_u32 s10, s10, (.LBB10_4-.Lpost_getpc14)&4294967295 ; GCN-NEXT: s_add_co_ci_u32 s11, s11, (.LBB10_4-.Lpost_getpc14)>>32 ; GCN-NEXT: s_set_pc_i64 s[10:11] -; GCN-NEXT: .LBB10_1: ; %Flow +; GCN-NEXT: .LBB10_20: ; %Flow ; GCN-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s7 ; GCN-NEXT: s_cbranch_vccnz .LBB10_2 -; GCN-NEXT: ; %bb.12: ; %Flow +; GCN-NEXT: ; %bb.3: ; %Flow ; GCN-NEXT: s_get_pc_i64 s[8:9] ; GCN-NEXT: .Lpost_getpc15: ; GCN-NEXT: s_add_co_u32 s8, s8, (.LBB10_5-.Lpost_getpc15)&4294967295 @@ -1179,7 +1179,7 @@ define amdgpu_kernel void @long_branch_hang(ptr addrspace(1) nocapture %arg, i32 ; GCN-NEXT: .LBB10_2: ; %Flow5 ; GCN-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0 ; GCN-NEXT: s_cbranch_vccz .LBB10_3 -; GCN-NEXT: ; %bb.14: ; %Flow5 +; GCN-NEXT: ; %bb.5: ; %Flow5 ; GCN-NEXT: s_get_pc_i64 s[0:1] ; GCN-NEXT: .Lpost_getpc16: ; GCN-NEXT: s_add_co_u32 s0, s0, (.LBB10_6-.Lpost_getpc16)&4294967295 @@ -1195,7 +1195,7 @@ define amdgpu_kernel void @long_branch_hang(ptr addrspace(1) nocapture %arg, i32 ; GCN-NEXT: s_and_b32 s0, s6, s0 ; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 -; GCN-NEXT: ; %bb.8: ; %bb14 +; GCN-NEXT: ; %bb.7: ; %bb14 ; GCN-NEXT: s_get_pc_i64 s[0:1] ; GCN-NEXT: .Lpost_getpc13: ; GCN-NEXT: s_add_co_u32 s0, s0, (.LBB10_7-.Lpost_getpc13)&4294967295 @@ -1210,7 +1210,7 @@ define amdgpu_kernel void @long_branch_hang(ptr addrspace(1) nocapture %arg, i32 ; GCN-NEXT: s_mov_b32 s0, s8 ; GCN-NEXT: s_sleep 0 ; GCN-NEXT: s_cbranch_execz .LBB10_5 -; GCN-NEXT: ; %bb.16: ; %bb13 +; GCN-NEXT: ; %bb.9: ; %bb13 ; GCN-NEXT: s_get_pc_i64 s[8:9] ; GCN-NEXT: .Lpost_getpc17: ; GCN-NEXT: s_add_co_u32 s8, s8, (.LBB10_2-.Lpost_getpc17)&4294967295 @@ -1225,7 +1225,7 @@ define amdgpu_kernel void @long_branch_hang(ptr addrspace(1) nocapture %arg, i32 ; GCN-NEXT: s_and_b32 s0, s7, s0 ; GCN-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0 ; GCN-NEXT: s_cbranch_vccnz .LBB10_6 -; GCN-NEXT: ; %bb.18: ; %bb9 +; GCN-NEXT: ; %bb.11: ; %bb9 ; GCN-NEXT: s_get_pc_i64 s[8:9] ; GCN-NEXT: .Lpost_getpc18: ; GCN-NEXT: s_add_co_u32 s8, s8, (.LBB10_3-.Lpost_getpc18)&4294967295 @@ -1235,8 +1235,8 @@ define amdgpu_kernel void @long_branch_hang(ptr addrspace(1) nocapture %arg, i32 ; GCN-NEXT: ; implicit-def: $vgpr0 ; GCN-NEXT: .LBB10_7: ; %bb19 ; GCN-NEXT: s_clause 0x1 -; GCN-NEXT: s_load_b64 s[0:1], s[4:5], 0x3c -; GCN-NEXT: s_load_b64 s[2:3], s[4:5], 0x24 +; GCN-NEXT: s_load_b64 s[0:1], s[4:5], 0x3c nv +; GCN-NEXT: s_load_b64 s[2:3], s[4:5], 0x24 nv ; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: s_wait_kmcnt 0x0 ; GCN-NEXT: s_lshl_b64 s[0:1], s[0:1], 2 @@ -1247,8 +1247,8 @@ define amdgpu_kernel void @long_branch_hang(ptr addrspace(1) nocapture %arg, i32 ; ; GCN-ADD-PC64-LABEL: long_branch_hang: ; GCN-ADD-PC64: ; %bb.0: ; %bb -; GCN-ADD-PC64-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 -; GCN-ADD-PC64-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c +; GCN-ADD-PC64-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 +; GCN-ADD-PC64-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c nv ; GCN-ADD-PC64-NEXT: s_mov_b32 s7, -1 ; GCN-ADD-PC64-NEXT: s_wait_kmcnt 0x0 ; GCN-ADD-PC64-NEXT: s_cmp_eq_u32 s0, 0 @@ -1257,20 +1257,20 @@ define amdgpu_kernel void @long_branch_hang(ptr addrspace(1) nocapture %arg, i32 ; GCN-ADD-PC64-NEXT: s_mov_b32 s0, 0 ; GCN-ADD-PC64-NEXT: s_cselect_b32 s8, -1, 0 ; GCN-ADD-PC64-NEXT: s_cmp_lt_i32 s3, 6 -; GCN-ADD-PC64-NEXT: s_cbranch_scc0 .LBB10_1 -; GCN-ADD-PC64-NEXT: ; %bb.10: ; %bb +; GCN-ADD-PC64-NEXT: s_cbranch_scc0 .LBB10_20 +; GCN-ADD-PC64-NEXT: ; %bb.1: ; %bb ; GCN-ADD-PC64-NEXT: s_add_pc_i64 .LBB10_4-.Lpost_addpc14 ; GCN-ADD-PC64-NEXT: .Lpost_addpc14: -; GCN-ADD-PC64-NEXT: .LBB10_1: ; %Flow +; GCN-ADD-PC64-NEXT: .LBB10_20: ; %Flow ; GCN-ADD-PC64-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s7 ; GCN-ADD-PC64-NEXT: s_cbranch_vccnz .LBB10_2 -; GCN-ADD-PC64-NEXT: ; %bb.12: ; %Flow +; GCN-ADD-PC64-NEXT: ; %bb.3: ; %Flow ; GCN-ADD-PC64-NEXT: s_add_pc_i64 .LBB10_5-.Lpost_addpc15 ; GCN-ADD-PC64-NEXT: .Lpost_addpc15: ; GCN-ADD-PC64-NEXT: .LBB10_2: ; %Flow5 ; GCN-ADD-PC64-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0 ; GCN-ADD-PC64-NEXT: s_cbranch_vccz .LBB10_3 -; GCN-ADD-PC64-NEXT: ; %bb.14: ; %Flow5 +; GCN-ADD-PC64-NEXT: ; %bb.5: ; %Flow5 ; GCN-ADD-PC64-NEXT: s_add_pc_i64 .LBB10_6-.Lpost_addpc16 ; GCN-ADD-PC64-NEXT: .Lpost_addpc16: ; GCN-ADD-PC64-NEXT: .LBB10_3: ; %bb14 @@ -1283,7 +1283,7 @@ define amdgpu_kernel void @long_branch_hang(ptr addrspace(1) nocapture %arg, i32 ; GCN-ADD-PC64-NEXT: s_and_b32 s0, s6, s0 ; GCN-ADD-PC64-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GCN-ADD-PC64-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 -; GCN-ADD-PC64-NEXT: ; %bb.8: ; %bb14 +; GCN-ADD-PC64-NEXT: ; %bb.7: ; %bb14 ; GCN-ADD-PC64-NEXT: s_add_pc_i64 .LBB10_7-.Lpost_addpc13 ; GCN-ADD-PC64-NEXT: .Lpost_addpc13: ; GCN-ADD-PC64-NEXT: .LBB10_4: ; %bb13 @@ -1295,7 +1295,7 @@ define amdgpu_kernel void @long_branch_hang(ptr addrspace(1) nocapture %arg, i32 ; GCN-ADD-PC64-NEXT: s_mov_b32 s0, s8 ; GCN-ADD-PC64-NEXT: s_sleep 0 ; GCN-ADD-PC64-NEXT: s_cbranch_execz .LBB10_5 -; GCN-ADD-PC64-NEXT: ; %bb.16: ; %bb13 +; GCN-ADD-PC64-NEXT: ; %bb.9: ; %bb13 ; GCN-ADD-PC64-NEXT: s_add_pc_i64 .LBB10_2-.Lpost_addpc17 ; GCN-ADD-PC64-NEXT: .Lpost_addpc17: ; GCN-ADD-PC64-NEXT: .LBB10_5: ; %bb9 @@ -1307,15 +1307,15 @@ define amdgpu_kernel void @long_branch_hang(ptr addrspace(1) nocapture %arg, i32 ; GCN-ADD-PC64-NEXT: s_and_b32 s0, s7, s0 ; GCN-ADD-PC64-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0 ; GCN-ADD-PC64-NEXT: s_cbranch_vccnz .LBB10_6 -; GCN-ADD-PC64-NEXT: ; %bb.18: ; %bb9 +; GCN-ADD-PC64-NEXT: ; %bb.11: ; %bb9 ; GCN-ADD-PC64-NEXT: s_add_pc_i64 .LBB10_3-.Lpost_addpc18 ; GCN-ADD-PC64-NEXT: .Lpost_addpc18: ; GCN-ADD-PC64-NEXT: .LBB10_6: ; GCN-ADD-PC64-NEXT: ; implicit-def: $vgpr0 ; GCN-ADD-PC64-NEXT: .LBB10_7: ; %bb19 ; GCN-ADD-PC64-NEXT: s_clause 0x1 -; GCN-ADD-PC64-NEXT: s_load_b64 s[0:1], s[4:5], 0x3c -; GCN-ADD-PC64-NEXT: s_load_b64 s[2:3], s[4:5], 0x24 +; GCN-ADD-PC64-NEXT: s_load_b64 s[0:1], s[4:5], 0x3c nv +; GCN-ADD-PC64-NEXT: s_load_b64 s[2:3], s[4:5], 0x24 nv ; GCN-ADD-PC64-NEXT: v_mov_b32_e32 v1, 0 ; GCN-ADD-PC64-NEXT: s_wait_kmcnt 0x0 ; GCN-ADD-PC64-NEXT: s_lshl_b64 s[0:1], s[0:1], 2 diff --git a/llvm/test/CodeGen/AMDGPU/branch-relaxation-inst-size-gfx11.ll b/llvm/test/CodeGen/AMDGPU/branch-relaxation-inst-size-gfx11.ll index 6bebc8f5d0d18..3b6d19a59b129 100644 --- a/llvm/test/CodeGen/AMDGPU/branch-relaxation-inst-size-gfx11.ll +++ b/llvm/test/CodeGen/AMDGPU/branch-relaxation-inst-size-gfx11.ll @@ -9,14 +9,14 @@ define amdgpu_kernel void @long_forward_branch_gfx11plus(ptr addrspace(1) %in, p ; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x34 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_cmp_eq_u32 s0, 0 -; GFX11-NEXT: s_cbranch_scc0 .LBB0_1 -; GFX11-NEXT: ; %bb.3: ; %bb0 +; GFX11-NEXT: s_cbranch_scc0 .LBB0_20 +; GFX11-NEXT: ; %bb.1: ; %bb0 ; GFX11-NEXT: s_getpc_b64 s[6:7] ; GFX11-NEXT: .Lpost_getpc0: ; GFX11-NEXT: s_add_u32 s6, s6, (.LBB0_2-.Lpost_getpc0)&4294967295 ; GFX11-NEXT: s_addc_u32 s7, s7, (.LBB0_2-.Lpost_getpc0)>>32 ; GFX11-NEXT: s_setpc_b64 s[6:7] -; GFX11-NEXT: .LBB0_1: ; %bb2 +; GFX11-NEXT: .LBB0_20: ; %bb2 ; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 ; GFX11-NEXT: v_mov_b32_e32 v1, 0 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) diff --git a/llvm/test/CodeGen/AMDGPU/branch-relaxation.ll b/llvm/test/CodeGen/AMDGPU/branch-relaxation.ll index 155e54baf15a1..0098a5ff48c0f 100644 --- a/llvm/test/CodeGen/AMDGPU/branch-relaxation.ll +++ b/llvm/test/CodeGen/AMDGPU/branch-relaxation.ll @@ -50,8 +50,8 @@ define amdgpu_kernel void @uniform_conditional_max_short_forward_branch(ptr addr ; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x2c ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_cmp_eq_u32 s0, 0 -; GFX11-NEXT: s_cbranch_scc0 .LBB0_1 -; GFX11-NEXT: ; %bb.3: ; %bb +; GFX11-NEXT: s_cbranch_scc0 .LBB0_20 +; GFX11-NEXT: ; %bb.1: ; %bb ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: .Lpost_getpc0: ; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) @@ -59,7 +59,7 @@ define amdgpu_kernel void @uniform_conditional_max_short_forward_branch(ptr addr ; GFX11-NEXT: s_addc_u32 s3, s3, (.LBB0_2-.Lpost_getpc0)>>32 ; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: s_setpc_b64 s[2:3] -; GFX11-NEXT: .LBB0_1: ; %bb2 +; GFX11-NEXT: .LBB0_20: ; %bb2 ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: v_nop_e64 ; GFX11-NEXT: v_nop_e64 @@ -80,8 +80,8 @@ define amdgpu_kernel void @uniform_conditional_max_short_forward_branch(ptr addr ; GFX12-NEXT: s_load_b32 s0, s[4:5], 0x2c ; GFX12-NEXT: s_wait_kmcnt 0x0 ; GFX12-NEXT: s_cmp_eq_u32 s0, 0 -; GFX12-NEXT: s_cbranch_scc0 .LBB0_1 -; GFX12-NEXT: ; %bb.3: ; %bb +; GFX12-NEXT: s_cbranch_scc0 .LBB0_20 +; GFX12-NEXT: ; %bb.1: ; %bb ; GFX12-NEXT: s_getpc_b64 s[2:3] ; GFX12-NEXT: .Lpost_getpc0: ; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) @@ -89,7 +89,7 @@ define amdgpu_kernel void @uniform_conditional_max_short_forward_branch(ptr addr ; GFX12-NEXT: s_add_co_ci_u32 s3, s3, (.LBB0_2-.Lpost_getpc0)>>32 ; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) ; GFX12-NEXT: s_setpc_b64 s[2:3] -; GFX12-NEXT: .LBB0_1: ; %bb2 +; GFX12-NEXT: .LBB0_20: ; %bb2 ; GFX12-NEXT: ;;#ASMSTART ; GFX12-NEXT: v_nop_e64 ; GFX12-NEXT: v_nop_e64 @@ -127,14 +127,14 @@ define amdgpu_kernel void @uniform_conditional_min_long_forward_branch(ptr addrs ; GCN-NEXT: s_load_dword s0, s[4:5], 0xb ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_cmp_eq_u32 s0, 0 -; GCN-NEXT: s_cbranch_scc0 .LBB1_1 -; GCN-NEXT: ; %bb.3: ; %bb0 +; GCN-NEXT: s_cbranch_scc0 .LBB1_20 +; GCN-NEXT: ; %bb.1: ; %bb0 ; GCN-NEXT: s_getpc_b64 s[2:3] ; GCN-NEXT: .Lpost_getpc0: ; GCN-NEXT: s_add_u32 s2, s2, (.LBB1_2-.Lpost_getpc0)&4294967295 ; GCN-NEXT: s_addc_u32 s3, s3, (.LBB1_2-.Lpost_getpc0)>>32 ; GCN-NEXT: s_setpc_b64 s[2:3] -; GCN-NEXT: .LBB1_1: ; %bb2 +; GCN-NEXT: .LBB1_20: ; %bb2 ; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: v_nop_e64 ; GCN-NEXT: v_nop_e64 @@ -156,8 +156,8 @@ define amdgpu_kernel void @uniform_conditional_min_long_forward_branch(ptr addrs ; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x2c ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_cmp_eq_u32 s0, 0 -; GFX11-NEXT: s_cbranch_scc0 .LBB1_1 -; GFX11-NEXT: ; %bb.3: ; %bb0 +; GFX11-NEXT: s_cbranch_scc0 .LBB1_20 +; GFX11-NEXT: ; %bb.1: ; %bb0 ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: .Lpost_getpc1: ; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) @@ -165,7 +165,7 @@ define amdgpu_kernel void @uniform_conditional_min_long_forward_branch(ptr addrs ; GFX11-NEXT: s_addc_u32 s3, s3, (.LBB1_2-.Lpost_getpc1)>>32 ; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: s_setpc_b64 s[2:3] -; GFX11-NEXT: .LBB1_1: ; %bb2 +; GFX11-NEXT: .LBB1_20: ; %bb2 ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: v_nop_e64 ; GFX11-NEXT: v_nop_e64 @@ -186,8 +186,8 @@ define amdgpu_kernel void @uniform_conditional_min_long_forward_branch(ptr addrs ; GFX12-NEXT: s_load_b32 s0, s[4:5], 0x2c ; GFX12-NEXT: s_wait_kmcnt 0x0 ; GFX12-NEXT: s_cmp_eq_u32 s0, 0 -; GFX12-NEXT: s_cbranch_scc0 .LBB1_1 -; GFX12-NEXT: ; %bb.3: ; %bb0 +; GFX12-NEXT: s_cbranch_scc0 .LBB1_20 +; GFX12-NEXT: ; %bb.1: ; %bb0 ; GFX12-NEXT: s_getpc_b64 s[2:3] ; GFX12-NEXT: .Lpost_getpc1: ; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) @@ -195,7 +195,7 @@ define amdgpu_kernel void @uniform_conditional_min_long_forward_branch(ptr addrs ; GFX12-NEXT: s_add_co_ci_u32 s3, s3, (.LBB1_2-.Lpost_getpc1)>>32 ; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) ; GFX12-NEXT: s_setpc_b64 s[2:3] -; GFX12-NEXT: .LBB1_1: ; %bb2 +; GFX12-NEXT: .LBB1_20: ; %bb2 ; GFX12-NEXT: ;;#ASMSTART ; GFX12-NEXT: v_nop_e64 ; GFX12-NEXT: v_nop_e64 @@ -234,14 +234,14 @@ define amdgpu_kernel void @uniform_conditional_min_long_forward_vcnd_branch(ptr ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: v_cmp_eq_f32_e64 s[2:3], s0, 0 ; GCN-NEXT: s_and_b64 vcc, exec, s[2:3] -; GCN-NEXT: s_cbranch_vccz .LBB2_1 -; GCN-NEXT: ; %bb.3: ; %bb0 +; GCN-NEXT: s_cbranch_vccz .LBB2_20 +; GCN-NEXT: ; %bb.1: ; %bb0 ; GCN-NEXT: s_getpc_b64 s[2:3] ; GCN-NEXT: .Lpost_getpc1: ; GCN-NEXT: s_add_u32 s2, s2, (.LBB2_2-.Lpost_getpc1)&4294967295 ; GCN-NEXT: s_addc_u32 s3, s3, (.LBB2_2-.Lpost_getpc1)>>32 ; GCN-NEXT: s_setpc_b64 s[2:3] -; GCN-NEXT: .LBB2_1: ; %bb2 +; GCN-NEXT: .LBB2_20: ; %bb2 ; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: ; 32 bytes ; GCN-NEXT: v_nop_e64 @@ -265,8 +265,8 @@ define amdgpu_kernel void @uniform_conditional_min_long_forward_vcnd_branch(ptr ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: v_cmp_eq_f32_e64 s[2:3], s0, 0 ; GFX11-NEXT: s_and_b64 vcc, exec, s[2:3] -; GFX11-NEXT: s_cbranch_vccz .LBB2_1 -; GFX11-NEXT: ; %bb.3: ; %bb0 +; GFX11-NEXT: s_cbranch_vccz .LBB2_20 +; GFX11-NEXT: ; %bb.1: ; %bb0 ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: .Lpost_getpc2: ; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) @@ -274,7 +274,7 @@ define amdgpu_kernel void @uniform_conditional_min_long_forward_vcnd_branch(ptr ; GFX11-NEXT: s_addc_u32 s3, s3, (.LBB2_2-.Lpost_getpc2)>>32 ; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: s_setpc_b64 s[2:3] -; GFX11-NEXT: .LBB2_1: ; %bb2 +; GFX11-NEXT: .LBB2_20: ; %bb2 ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; 32 bytes ; GFX11-NEXT: v_nop_e64 @@ -296,8 +296,8 @@ define amdgpu_kernel void @uniform_conditional_min_long_forward_vcnd_branch(ptr ; GFX12-NEXT: s_load_b32 s0, s[4:5], 0x2c ; GFX12-NEXT: s_wait_kmcnt 0x0 ; GFX12-NEXT: s_cmp_eq_f32 s0, 0 -; GFX12-NEXT: s_cbranch_scc0 .LBB2_1 -; GFX12-NEXT: ; %bb.3: ; %bb0 +; GFX12-NEXT: s_cbranch_scc0 .LBB2_20 +; GFX12-NEXT: ; %bb.1: ; %bb0 ; GFX12-NEXT: s_getpc_b64 s[2:3] ; GFX12-NEXT: .Lpost_getpc2: ; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) @@ -305,7 +305,7 @@ define amdgpu_kernel void @uniform_conditional_min_long_forward_vcnd_branch(ptr ; GFX12-NEXT: s_add_co_ci_u32 s3, s3, (.LBB2_2-.Lpost_getpc2)>>32 ; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) ; GFX12-NEXT: s_setpc_b64 s[2:3] -; GFX12-NEXT: .LBB2_1: ; %bb2 +; GFX12-NEXT: .LBB2_20: ; %bb2 ; GFX12-NEXT: ;;#ASMSTART ; GFX12-NEXT: ; 32 bytes ; GFX12-NEXT: v_nop_e64 @@ -353,14 +353,14 @@ define amdgpu_kernel void @min_long_forward_vbranch(ptr addrspace(1) %arg) #0 { ; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; GCN-NEXT: s_and_saveexec_b64 s[0:1], vcc -; GCN-NEXT: s_cbranch_execnz .LBB3_1 -; GCN-NEXT: ; %bb.3: ; %bb +; GCN-NEXT: s_cbranch_execnz .LBB3_20 +; GCN-NEXT: ; %bb.1: ; %bb ; GCN-NEXT: s_getpc_b64 s[4:5] ; GCN-NEXT: .Lpost_getpc2: ; GCN-NEXT: s_add_u32 s4, s4, (.LBB3_2-.Lpost_getpc2)&4294967295 ; GCN-NEXT: s_addc_u32 s5, s5, (.LBB3_2-.Lpost_getpc2)>>32 ; GCN-NEXT: s_setpc_b64 s[4:5] -; GCN-NEXT: .LBB3_1: ; %bb2 +; GCN-NEXT: .LBB3_20: ; %bb2 ; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: ; 32 bytes ; GCN-NEXT: v_nop_e64 @@ -389,8 +389,8 @@ define amdgpu_kernel void @min_long_forward_vbranch(ptr addrspace(1) %arg) #0 { ; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s1, 0, s[2:3] ; GFX11-NEXT: s_mov_b64 s[0:1], exec ; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v2 -; GFX11-NEXT: s_cbranch_execnz .LBB3_1 -; GFX11-NEXT: ; %bb.3: ; %bb +; GFX11-NEXT: s_cbranch_execnz .LBB3_20 +; GFX11-NEXT: ; %bb.1: ; %bb ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: .Lpost_getpc3: ; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) @@ -398,7 +398,7 @@ define amdgpu_kernel void @min_long_forward_vbranch(ptr addrspace(1) %arg) #0 { ; GFX11-NEXT: s_addc_u32 s3, s3, (.LBB3_2-.Lpost_getpc3)>>32 ; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: s_setpc_b64 s[2:3] -; GFX11-NEXT: .LBB3_1: ; %bb2 +; GFX11-NEXT: .LBB3_20: ; %bb2 ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: ; 32 bytes ; GFX11-NEXT: v_nop_e64 @@ -426,8 +426,8 @@ define amdgpu_kernel void @min_long_forward_vbranch(ptr addrspace(1) %arg) #0 { ; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, s1, 0, s0 ; GFX12-NEXT: s_mov_b32 s0, exec_lo ; GFX12-NEXT: v_cmpx_ne_u32_e32 0, v2 -; GFX12-NEXT: s_cbranch_execnz .LBB3_1 -; GFX12-NEXT: ; %bb.3: ; %bb +; GFX12-NEXT: s_cbranch_execnz .LBB3_20 +; GFX12-NEXT: ; %bb.1: ; %bb ; GFX12-NEXT: s_getpc_b64 s[2:3] ; GFX12-NEXT: .Lpost_getpc3: ; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) @@ -435,7 +435,7 @@ define amdgpu_kernel void @min_long_forward_vbranch(ptr addrspace(1) %arg) #0 { ; GFX12-NEXT: s_add_co_ci_u32 s3, s3, (.LBB3_2-.Lpost_getpc3)>>32 ; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) ; GFX12-NEXT: s_setpc_b64 s[2:3] -; GFX12-NEXT: .LBB3_1: ; %bb2 +; GFX12-NEXT: .LBB3_20: ; %bb2 ; GFX12-NEXT: ;;#ASMSTART ; GFX12-NEXT: ; 32 bytes ; GFX12-NEXT: v_nop_e64 @@ -483,15 +483,15 @@ define amdgpu_kernel void @long_backward_sbranch(ptr addrspace(1) %arg) #0 { ; GCN-NEXT: v_nop_e64 ; GCN-NEXT: v_nop_e64 ; GCN-NEXT: ;;#ASMEND -; GCN-NEXT: s_cbranch_scc0 .LBB4_2 -; GCN-NEXT: ; %bb.3: ; %bb2 +; GCN-NEXT: s_cbranch_scc0 .LBB4_3 +; GCN-NEXT: ; %bb.2: ; %bb2 ; GCN-NEXT: ; in Loop: Header=BB4_1 Depth=1 ; GCN-NEXT: s_getpc_b64 s[2:3] ; GCN-NEXT: .Lpost_getpc3: ; GCN-NEXT: s_add_u32 s2, s2, (.LBB4_1-.Lpost_getpc3)&4294967295 ; GCN-NEXT: s_addc_u32 s3, s3, (.LBB4_1-.Lpost_getpc3)>>32 ; GCN-NEXT: s_setpc_b64 s[2:3] -; GCN-NEXT: .LBB4_2: ; %bb3 +; GCN-NEXT: .LBB4_3: ; %bb3 ; GCN-NEXT: s_endpgm ; ; GFX11-LABEL: long_backward_sbranch: @@ -508,8 +508,8 @@ define amdgpu_kernel void @long_backward_sbranch(ptr addrspace(1) %arg) #0 { ; GFX11-NEXT: v_nop_e64 ; GFX11-NEXT: ;;#ASMEND ; GFX11-NEXT: s_cmp_lt_i32 s0, 10 -; GFX11-NEXT: s_cbranch_scc0 .LBB4_2 -; GFX11-NEXT: ; %bb.3: ; %bb2 +; GFX11-NEXT: s_cbranch_scc0 .LBB4_3 +; GFX11-NEXT: ; %bb.2: ; %bb2 ; GFX11-NEXT: ; in Loop: Header=BB4_1 Depth=1 ; GFX11-NEXT: s_getpc_b64 s[2:3] ; GFX11-NEXT: .Lpost_getpc4: @@ -518,7 +518,7 @@ define amdgpu_kernel void @long_backward_sbranch(ptr addrspace(1) %arg) #0 { ; GFX11-NEXT: s_addc_u32 s3, s3, (.LBB4_1-.Lpost_getpc4)>>32 ; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: s_setpc_b64 s[2:3] -; GFX11-NEXT: .LBB4_2: ; %bb3 +; GFX11-NEXT: .LBB4_3: ; %bb3 ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: long_backward_sbranch: @@ -534,8 +534,8 @@ define amdgpu_kernel void @long_backward_sbranch(ptr addrspace(1) %arg) #0 { ; GFX12-NEXT: v_nop_e64 ; GFX12-NEXT: ;;#ASMEND ; GFX12-NEXT: s_cmp_lt_i32 s0, 10 -; GFX12-NEXT: s_cbranch_scc0 .LBB4_2 -; GFX12-NEXT: ; %bb.3: ; %bb2 +; GFX12-NEXT: s_cbranch_scc0 .LBB4_3 +; GFX12-NEXT: ; %bb.2: ; %bb2 ; GFX12-NEXT: ; in Loop: Header=BB4_1 Depth=1 ; GFX12-NEXT: s_getpc_b64 s[2:3] ; GFX12-NEXT: .Lpost_getpc4: @@ -544,7 +544,7 @@ define amdgpu_kernel void @long_backward_sbranch(ptr addrspace(1) %arg) #0 { ; GFX12-NEXT: s_add_co_ci_u32 s3, s3, (.LBB4_1-.Lpost_getpc4)>>32 ; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) ; GFX12-NEXT: s_setpc_b64 s[2:3] -; GFX12-NEXT: .LBB4_2: ; %bb3 +; GFX12-NEXT: .LBB4_3: ; %bb3 ; GFX12-NEXT: s_endpgm bb: br label %bb2 @@ -574,14 +574,14 @@ define amdgpu_kernel void @uniform_unconditional_min_long_forward_branch(ptr add ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_cmp_eq_u32 s0, 0 ; GCN-NEXT: s_mov_b64 s[0:1], -1 -; GCN-NEXT: s_cbranch_scc0 .LBB5_1 -; GCN-NEXT: ; %bb.7: ; %bb0 +; GCN-NEXT: s_cbranch_scc0 .LBB5_20 +; GCN-NEXT: ; %bb.1: ; %bb0 ; GCN-NEXT: s_getpc_b64 s[0:1] ; GCN-NEXT: .Lpost_getpc5: ; GCN-NEXT: s_add_u32 s0, s0, (.LBB5_4-.Lpost_getpc5)&4294967295 ; GCN-NEXT: s_addc_u32 s1, s1, (.LBB5_4-.Lpost_getpc5)>>32 ; GCN-NEXT: s_setpc_b64 s[0:1] -; GCN-NEXT: .LBB5_1: ; %Flow +; GCN-NEXT: .LBB5_20: ; %Flow ; GCN-NEXT: s_andn2_b64 vcc, exec, s[0:1] ; GCN-NEXT: s_cbranch_vccnz .LBB5_3 ; GCN-NEXT: .LBB5_2: ; %bb2 @@ -607,14 +607,14 @@ define amdgpu_kernel void @uniform_unconditional_min_long_forward_branch(ptr add ; GCN-NEXT: v_nop_e64 ; GCN-NEXT: v_nop_e64 ; GCN-NEXT: ;;#ASMEND -; GCN-NEXT: s_cbranch_execnz .LBB5_5 -; GCN-NEXT: ; %bb.9: ; %bb3 +; GCN-NEXT: s_cbranch_execnz .LBB5_7 +; GCN-NEXT: ; %bb.6: ; %bb3 ; GCN-NEXT: s_getpc_b64 s[0:1] ; GCN-NEXT: .Lpost_getpc6: ; GCN-NEXT: s_add_u32 s0, s0, (.LBB5_2-.Lpost_getpc6)&4294967295 ; GCN-NEXT: s_addc_u32 s1, s1, (.LBB5_2-.Lpost_getpc6)>>32 ; GCN-NEXT: s_setpc_b64 s[0:1] -; GCN-NEXT: .LBB5_5: ; %bb3 +; GCN-NEXT: .LBB5_7: ; %bb3 ; GCN-NEXT: s_getpc_b64 s[0:1] ; GCN-NEXT: .Lpost_getpc4: ; GCN-NEXT: s_add_u32 s0, s0, (.LBB5_3-.Lpost_getpc4)&4294967295 @@ -650,8 +650,8 @@ define amdgpu_kernel void @uniform_unconditional_min_long_forward_branch(ptr add ; GFX11-NEXT: v_nop_e64 ; GFX11-NEXT: v_nop_e64 ; GFX11-NEXT: ;;#ASMEND -; GFX11-NEXT: s_cbranch_execnz .LBB5_5 -; GFX11-NEXT: ; %bb.7: ; %bb3 +; GFX11-NEXT: s_cbranch_execnz .LBB5_6 +; GFX11-NEXT: ; %bb.5: ; %bb3 ; GFX11-NEXT: s_getpc_b64 s[0:1] ; GFX11-NEXT: .Lpost_getpc6: ; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) @@ -659,7 +659,7 @@ define amdgpu_kernel void @uniform_unconditional_min_long_forward_branch(ptr add ; GFX11-NEXT: s_addc_u32 s1, s1, (.LBB5_2-.Lpost_getpc6)>>32 ; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: s_setpc_b64 s[0:1] -; GFX11-NEXT: .LBB5_5: ; %bb3 +; GFX11-NEXT: .LBB5_6: ; %bb3 ; GFX11-NEXT: s_getpc_b64 s[0:1] ; GFX11-NEXT: .Lpost_getpc5: ; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) @@ -674,8 +674,8 @@ define amdgpu_kernel void @uniform_unconditional_min_long_forward_branch(ptr add ; GFX12-NEXT: s_wait_kmcnt 0x0 ; GFX12-NEXT: s_cmp_eq_u32 s0, 0 ; GFX12-NEXT: s_mov_b32 s0, -1 -; GFX12-NEXT: s_cbranch_scc0 .LBB5_1 -; GFX12-NEXT: ; %bb.7: ; %bb0 +; GFX12-NEXT: s_cbranch_scc0 .LBB5_20 +; GFX12-NEXT: ; %bb.1: ; %bb0 ; GFX12-NEXT: s_getpc_b64 s[0:1] ; GFX12-NEXT: .Lpost_getpc6: ; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) @@ -683,7 +683,7 @@ define amdgpu_kernel void @uniform_unconditional_min_long_forward_branch(ptr add ; GFX12-NEXT: s_add_co_ci_u32 s1, s1, (.LBB5_4-.Lpost_getpc6)>>32 ; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) ; GFX12-NEXT: s_setpc_b64 s[0:1] -; GFX12-NEXT: .LBB5_1: ; %Flow +; GFX12-NEXT: .LBB5_20: ; %Flow ; GFX12-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0 ; GFX12-NEXT: s_cbranch_vccnz .LBB5_3 ; GFX12-NEXT: .LBB5_2: ; %bb2 @@ -704,8 +704,8 @@ define amdgpu_kernel void @uniform_unconditional_min_long_forward_branch(ptr add ; GFX12-NEXT: v_nop_e64 ; GFX12-NEXT: v_nop_e64 ; GFX12-NEXT: ;;#ASMEND -; GFX12-NEXT: s_cbranch_execnz .LBB5_5 -; GFX12-NEXT: ; %bb.9: ; %bb3 +; GFX12-NEXT: s_cbranch_execnz .LBB5_7 +; GFX12-NEXT: ; %bb.6: ; %bb3 ; GFX12-NEXT: s_getpc_b64 s[0:1] ; GFX12-NEXT: .Lpost_getpc7: ; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) @@ -713,7 +713,7 @@ define amdgpu_kernel void @uniform_unconditional_min_long_forward_branch(ptr add ; GFX12-NEXT: s_add_co_ci_u32 s1, s1, (.LBB5_2-.Lpost_getpc7)>>32 ; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) ; GFX12-NEXT: s_setpc_b64 s[0:1] -; GFX12-NEXT: .LBB5_5: ; %bb3 +; GFX12-NEXT: .LBB5_7: ; %bb3 ; GFX12-NEXT: s_getpc_b64 s[0:1] ; GFX12-NEXT: .Lpost_getpc5: ; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) @@ -756,15 +756,15 @@ define amdgpu_kernel void @uniform_unconditional_min_long_backward_branch(ptr ad ; GCN-NEXT: v_nop_e64 ; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: s_mov_b64 vcc, vcc -; GCN-NEXT: s_cbranch_vccz .LBB6_2 -; GCN-NEXT: ; %bb.3: ; %loop +; GCN-NEXT: s_cbranch_vccz .LBB6_3 +; GCN-NEXT: ; %bb.2: ; %loop ; GCN-NEXT: ; in Loop: Header=BB6_1 Depth=1 ; GCN-NEXT: s_getpc_b64 s[0:1] ; GCN-NEXT: .Lpost_getpc7: ; GCN-NEXT: s_add_u32 s0, s0, (.LBB6_1-.Lpost_getpc7)&4294967295 ; GCN-NEXT: s_addc_u32 s1, s1, (.LBB6_1-.Lpost_getpc7)>>32 ; GCN-NEXT: s_setpc_b64 s[0:1] -; GCN-NEXT: .LBB6_2: ; %DummyReturnBlock +; GCN-NEXT: .LBB6_3: ; %DummyReturnBlock ; GCN-NEXT: s_endpgm ; ; GFX11-LABEL: uniform_unconditional_min_long_backward_branch: @@ -779,8 +779,8 @@ define amdgpu_kernel void @uniform_unconditional_min_long_backward_branch(ptr ad ; GFX11-NEXT: v_nop_e64 ; GFX11-NEXT: v_nop_e64 ; GFX11-NEXT: ;;#ASMEND -; GFX11-NEXT: s_cbranch_vccz .LBB6_2 -; GFX11-NEXT: ; %bb.3: ; %loop +; GFX11-NEXT: s_cbranch_vccz .LBB6_3 +; GFX11-NEXT: ; %bb.2: ; %loop ; GFX11-NEXT: ; in Loop: Header=BB6_1 Depth=1 ; GFX11-NEXT: s_getpc_b64 s[0:1] ; GFX11-NEXT: .Lpost_getpc7: @@ -789,7 +789,7 @@ define amdgpu_kernel void @uniform_unconditional_min_long_backward_branch(ptr ad ; GFX11-NEXT: s_addc_u32 s1, s1, (.LBB6_1-.Lpost_getpc7)>>32 ; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: s_setpc_b64 s[0:1] -; GFX11-NEXT: .LBB6_2: ; %DummyReturnBlock +; GFX11-NEXT: .LBB6_3: ; %DummyReturnBlock ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: uniform_unconditional_min_long_backward_branch: @@ -803,8 +803,8 @@ define amdgpu_kernel void @uniform_unconditional_min_long_backward_branch(ptr ad ; GFX12-NEXT: v_nop_e64 ; GFX12-NEXT: v_nop_e64 ; GFX12-NEXT: ;;#ASMEND -; GFX12-NEXT: s_cbranch_vccz .LBB6_2 -; GFX12-NEXT: ; %bb.3: ; %loop +; GFX12-NEXT: s_cbranch_vccz .LBB6_3 +; GFX12-NEXT: ; %bb.2: ; %loop ; GFX12-NEXT: ; in Loop: Header=BB6_1 Depth=1 ; GFX12-NEXT: s_getpc_b64 s[0:1] ; GFX12-NEXT: .Lpost_getpc8: @@ -813,7 +813,7 @@ define amdgpu_kernel void @uniform_unconditional_min_long_backward_branch(ptr ad ; GFX12-NEXT: s_add_co_ci_u32 s1, s1, (.LBB6_1-.Lpost_getpc8)>>32 ; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) ; GFX12-NEXT: s_setpc_b64 s[0:1] -; GFX12-NEXT: .LBB6_2: ; %DummyReturnBlock +; GFX12-NEXT: .LBB6_3: ; %DummyReturnBlock ; GFX12-NEXT: s_endpgm entry: br label %loop @@ -847,14 +847,14 @@ define amdgpu_kernel void @expand_requires_expand(i32 %cond0) #0 { ; GCN-NEXT: s_cselect_b64 s[0:1], -1, 0 ; GCN-NEXT: .LBB7_2: ; %Flow ; GCN-NEXT: s_andn2_b64 vcc, exec, s[0:1] -; GCN-NEXT: s_cbranch_vccz .LBB7_3 -; GCN-NEXT: ; %bb.5: ; %Flow +; GCN-NEXT: s_cbranch_vccz .LBB7_40 +; GCN-NEXT: ; %bb.3: ; %Flow ; GCN-NEXT: s_getpc_b64 s[0:1] ; GCN-NEXT: .Lpost_getpc8: ; GCN-NEXT: s_add_u32 s0, s0, (.LBB7_4-.Lpost_getpc8)&4294967295 ; GCN-NEXT: s_addc_u32 s1, s1, (.LBB7_4-.Lpost_getpc8)>>32 ; GCN-NEXT: s_setpc_b64 s[0:1] -; GCN-NEXT: .LBB7_3: ; %bb2 +; GCN-NEXT: .LBB7_40: ; %bb2 ; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: v_nop_e64 ; GCN-NEXT: v_nop_e64 @@ -887,8 +887,8 @@ define amdgpu_kernel void @expand_requires_expand(i32 %cond0) #0 { ; GFX11-NEXT: .LBB7_2: ; %Flow ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_and_not1_b64 vcc, exec, s[0:1] -; GFX11-NEXT: s_cbranch_vccz .LBB7_3 -; GFX11-NEXT: ; %bb.5: ; %Flow +; GFX11-NEXT: s_cbranch_vccz .LBB7_40 +; GFX11-NEXT: ; %bb.3: ; %Flow ; GFX11-NEXT: s_getpc_b64 s[0:1] ; GFX11-NEXT: .Lpost_getpc8: ; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) @@ -896,7 +896,7 @@ define amdgpu_kernel void @expand_requires_expand(i32 %cond0) #0 { ; GFX11-NEXT: s_addc_u32 s1, s1, (.LBB7_4-.Lpost_getpc8)>>32 ; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: s_setpc_b64 s[0:1] -; GFX11-NEXT: .LBB7_3: ; %bb2 +; GFX11-NEXT: .LBB7_40: ; %bb2 ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: v_nop_e64 ; GFX11-NEXT: v_nop_e64 @@ -929,8 +929,8 @@ define amdgpu_kernel void @expand_requires_expand(i32 %cond0) #0 { ; GFX12-NEXT: .LBB7_2: ; %Flow ; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX12-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0 -; GFX12-NEXT: s_cbranch_vccz .LBB7_3 -; GFX12-NEXT: ; %bb.5: ; %Flow +; GFX12-NEXT: s_cbranch_vccz .LBB7_40 +; GFX12-NEXT: ; %bb.3: ; %Flow ; GFX12-NEXT: s_getpc_b64 s[0:1] ; GFX12-NEXT: .Lpost_getpc9: ; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) @@ -938,7 +938,7 @@ define amdgpu_kernel void @expand_requires_expand(i32 %cond0) #0 { ; GFX12-NEXT: s_add_co_ci_u32 s1, s1, (.LBB7_4-.Lpost_getpc9)>>32 ; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) ; GFX12-NEXT: s_setpc_b64 s[0:1] -; GFX12-NEXT: .LBB7_3: ; %bb2 +; GFX12-NEXT: .LBB7_40: ; %bb2 ; GFX12-NEXT: ;;#ASMSTART ; GFX12-NEXT: v_nop_e64 ; GFX12-NEXT: v_nop_e64 @@ -988,14 +988,14 @@ define amdgpu_kernel void @uniform_inside_divergent(ptr addrspace(1) %out, i32 % ; GCN: ; %bb.0: ; %entry ; GCN-NEXT: v_cmp_gt_u32_e32 vcc, 16, v0 ; GCN-NEXT: s_and_saveexec_b64 s[6:7], vcc -; GCN-NEXT: s_cbranch_execnz .LBB8_1 -; GCN-NEXT: ; %bb.4: ; %entry +; GCN-NEXT: s_cbranch_execnz .LBB8_2 +; GCN-NEXT: ; %bb.1: ; %entry ; GCN-NEXT: s_getpc_b64 s[0:1] ; GCN-NEXT: .Lpost_getpc9: ; GCN-NEXT: s_add_u32 s0, s0, (.LBB8_3-.Lpost_getpc9)&4294967295 ; GCN-NEXT: s_addc_u32 s1, s1, (.LBB8_3-.Lpost_getpc9)>>32 ; GCN-NEXT: s_setpc_b64 s[0:1] -; GCN-NEXT: .LBB8_1: ; %if +; GCN-NEXT: .LBB8_2: ; %if ; GCN-NEXT: s_load_dword s8, s[4:5], 0xb ; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 ; GCN-NEXT: s_mov_b32 s3, 0xf000 @@ -1005,7 +1005,7 @@ define amdgpu_kernel void @uniform_inside_divergent(ptr addrspace(1) %out, i32 % ; GCN-NEXT: s_cmp_lg_u32 s8, 0 ; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GCN-NEXT: s_cbranch_scc1 .LBB8_3 -; GCN-NEXT: ; %bb.2: ; %if_uniform +; GCN-NEXT: ; %bb.3: ; %if_uniform ; GCN-NEXT: s_waitcnt expcnt(0) ; GCN-NEXT: v_mov_b32_e32 v0, 1 ; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 @@ -1100,14 +1100,14 @@ define amdgpu_kernel void @analyze_mask_branch() #0 { ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: .LBB9_2: ; %Flow1 ; GCN-NEXT: s_andn2_saveexec_b64 s[0:1], s[0:1] -; GCN-NEXT: s_cbranch_execnz .LBB9_3 -; GCN-NEXT: ; %bb.6: ; %Flow1 +; GCN-NEXT: s_cbranch_execnz .LBB9_40 +; GCN-NEXT: ; %bb.3: ; %Flow1 ; GCN-NEXT: s_getpc_b64 s[0:1] ; GCN-NEXT: .Lpost_getpc10: ; GCN-NEXT: s_add_u32 s0, s0, (.LBB9_5-.Lpost_getpc10)&4294967295 ; GCN-NEXT: s_addc_u32 s1, s1, (.LBB9_5-.Lpost_getpc10)>>32 ; GCN-NEXT: s_setpc_b64 s[0:1] -; GCN-NEXT: .LBB9_3: ; %loop.preheader +; GCN-NEXT: .LBB9_40: ; %loop.preheader ; GCN-NEXT: s_and_b64 vcc, exec, 0 ; GCN-NEXT: .LBB9_4: ; %loop ; GCN-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -1123,8 +1123,8 @@ define amdgpu_kernel void @analyze_mask_branch() #0 { ; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: s_mov_b64 vcc, vcc ; GCN-NEXT: s_cbranch_vccnz .LBB9_5 -; GCN-NEXT: ; %bb.8: ; %loop -; GCN-NEXT: ; in Loop: Header=BB9_4 Depth=1 +; GCN-NEXT: ; %bb.6: ; %loop +; GCN-NEXT: ; in Loop: Header=BB9_5 Depth=1 ; GCN-NEXT: s_getpc_b64 s[0:1] ; GCN-NEXT: .Lpost_getpc11: ; GCN-NEXT: s_add_u32 s0, s0, (.LBB9_4-.Lpost_getpc11)&4294967295 @@ -1148,8 +1148,8 @@ define amdgpu_kernel void @analyze_mask_branch() #0 { ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: .LBB9_2: ; %Flow1 ; GFX11-NEXT: s_and_not1_saveexec_b64 s[0:1], s[0:1] -; GFX11-NEXT: s_cbranch_execnz .LBB9_3 -; GFX11-NEXT: ; %bb.6: ; %Flow1 +; GFX11-NEXT: s_cbranch_execnz .LBB9_40 +; GFX11-NEXT: ; %bb.3: ; %Flow1 ; GFX11-NEXT: s_getpc_b64 s[0:1] ; GFX11-NEXT: .Lpost_getpc9: ; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) @@ -1157,7 +1157,7 @@ define amdgpu_kernel void @analyze_mask_branch() #0 { ; GFX11-NEXT: s_addc_u32 s1, s1, (.LBB9_5-.Lpost_getpc9)>>32 ; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: s_setpc_b64 s[0:1] -; GFX11-NEXT: .LBB9_3: ; %loop.preheader +; GFX11-NEXT: .LBB9_40: ; %loop.preheader ; GFX11-NEXT: s_and_b64 vcc, exec, 0 ; GFX11-NEXT: .p2align 6 ; GFX11-NEXT: .LBB9_4: ; %loop @@ -1173,8 +1173,8 @@ define amdgpu_kernel void @analyze_mask_branch() #0 { ; GFX11-NEXT: v_nop_e64 ; GFX11-NEXT: ;;#ASMEND ; GFX11-NEXT: s_cbranch_vccnz .LBB9_5 -; GFX11-NEXT: ; %bb.8: ; %loop -; GFX11-NEXT: ; in Loop: Header=BB9_4 Depth=1 +; GFX11-NEXT: ; %bb.6: ; %loop +; GFX11-NEXT: ; in Loop: Header=BB9_5 Depth=1 ; GFX11-NEXT: s_getpc_b64 s[0:1] ; GFX11-NEXT: .Lpost_getpc10: ; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) @@ -1200,8 +1200,8 @@ define amdgpu_kernel void @analyze_mask_branch() #0 { ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: .LBB9_2: ; %Flow1 ; GFX12-NEXT: s_and_not1_saveexec_b32 s0, s0 -; GFX12-NEXT: s_cbranch_execnz .LBB9_3 -; GFX12-NEXT: ; %bb.6: ; %Flow1 +; GFX12-NEXT: s_cbranch_execnz .LBB9_40 +; GFX12-NEXT: ; %bb.3: ; %Flow1 ; GFX12-NEXT: s_getpc_b64 s[0:1] ; GFX12-NEXT: .Lpost_getpc10: ; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) @@ -1209,7 +1209,7 @@ define amdgpu_kernel void @analyze_mask_branch() #0 { ; GFX12-NEXT: s_add_co_ci_u32 s1, s1, (.LBB9_5-.Lpost_getpc10)>>32 ; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) ; GFX12-NEXT: s_setpc_b64 s[0:1] -; GFX12-NEXT: .LBB9_3: ; %loop.preheader +; GFX12-NEXT: .LBB9_40: ; %loop.preheader ; GFX12-NEXT: s_mov_b32 vcc_lo, 0 ; GFX12-NEXT: .LBB9_4: ; %loop ; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -1224,8 +1224,8 @@ define amdgpu_kernel void @analyze_mask_branch() #0 { ; GFX12-NEXT: v_nop_e64 ; GFX12-NEXT: ;;#ASMEND ; GFX12-NEXT: s_cbranch_vccnz .LBB9_5 -; GFX12-NEXT: ; %bb.8: ; %loop -; GFX12-NEXT: ; in Loop: Header=BB9_4 Depth=1 +; GFX12-NEXT: ; %bb.6: ; %loop +; GFX12-NEXT: ; in Loop: Header=BB9_5 Depth=1 ; GFX12-NEXT: s_getpc_b64 s[0:1] ; GFX12-NEXT: .Lpost_getpc11: ; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) @@ -1271,40 +1271,40 @@ define amdgpu_kernel void @long_branch_hang(ptr addrspace(1) nocapture %arg, i32 ; GCN-NEXT: s_cmp_lg_u32 s0, 0 ; GCN-NEXT: s_cselect_b64 s[8:9], -1, 0 ; GCN-NEXT: s_cmp_lt_i32 s3, 6 -; GCN-NEXT: s_cbranch_scc1 .LBB10_1 -; GCN-NEXT: ; %bb.8: ; %bb +; GCN-NEXT: s_cbranch_scc1 .LBB10_20 +; GCN-NEXT: ; %bb.1: ; %bb ; GCN-NEXT: s_getpc_b64 s[8:9] ; GCN-NEXT: .Lpost_getpc12: ; GCN-NEXT: s_add_u32 s8, s8, (.LBB10_2-.Lpost_getpc12)&4294967295 ; GCN-NEXT: s_addc_u32 s9, s9, (.LBB10_2-.Lpost_getpc12)>>32 ; GCN-NEXT: s_setpc_b64 s[8:9] -; GCN-NEXT: .LBB10_1: ; %bb13 +; GCN-NEXT: .LBB10_20: ; %bb13 ; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: v_nop_e64 ; GCN-NEXT: v_nop_e64 ; GCN-NEXT: v_nop_e64 ; GCN-NEXT: v_nop_e64 ; GCN-NEXT: ;;#ASMEND -; GCN-NEXT: s_cbranch_execz .LBB10_3 -; GCN-NEXT: s_branch .LBB10_4 +; GCN-NEXT: s_cbranch_execz .LBB10_4 +; GCN-NEXT: s_branch .LBB10_5 ; GCN-NEXT: .LBB10_2: ; GCN-NEXT: s_mov_b64 s[8:9], 0 -; GCN-NEXT: .LBB10_3: ; %bb9 +; GCN-NEXT: .LBB10_4: ; %bb9 ; GCN-NEXT: s_cmp_lt_i32 s3, 11 ; GCN-NEXT: s_cselect_b64 s[8:9], -1, 0 ; GCN-NEXT: s_cmp_ge_i32 s2, s3 ; GCN-NEXT: s_cselect_b64 s[10:11], -1, 0 ; GCN-NEXT: s_and_b64 s[8:9], s[10:11], s[8:9] -; GCN-NEXT: .LBB10_4: ; %Flow5 +; GCN-NEXT: .LBB10_5: ; %Flow5 ; GCN-NEXT: s_andn2_b64 vcc, exec, s[8:9] -; GCN-NEXT: s_cbranch_vccz .LBB10_5 -; GCN-NEXT: ; %bb.10: ; %Flow5 +; GCN-NEXT: s_cbranch_vccz .LBB10_7 +; GCN-NEXT: ; %bb.6: ; %Flow5 ; GCN-NEXT: s_getpc_b64 s[0:1] ; GCN-NEXT: .Lpost_getpc13: ; GCN-NEXT: s_add_u32 s0, s0, (.LBB10_6-.Lpost_getpc13)&4294967295 ; GCN-NEXT: s_addc_u32 s1, s1, (.LBB10_6-.Lpost_getpc13)>>32 ; GCN-NEXT: s_setpc_b64 s[0:1] -; GCN-NEXT: .LBB10_5: ; %bb14 +; GCN-NEXT: .LBB10_7: ; %bb14 ; GCN-NEXT: s_cmp_lt_i32 s1, 9 ; GCN-NEXT: s_cselect_b64 s[0:1], -1, 0 ; GCN-NEXT: s_cmp_lt_i32 s2, s3 @@ -1312,10 +1312,10 @@ define amdgpu_kernel void @long_branch_hang(ptr addrspace(1) nocapture %arg, i32 ; GCN-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1] ; GCN-NEXT: s_and_b64 s[0:1], s[6:7], s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] -; GCN-NEXT: s_branch .LBB10_7 +; GCN-NEXT: s_branch .LBB10_9 ; GCN-NEXT: .LBB10_6: ; GCN-NEXT: ; implicit-def: $vgpr0 -; GCN-NEXT: .LBB10_7: ; %bb19 +; GCN-NEXT: .LBB10_9: ; %bb19 ; GCN-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0xf ; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 ; GCN-NEXT: s_mov_b32 s3, 0xf000 @@ -1336,8 +1336,8 @@ define amdgpu_kernel void @long_branch_hang(ptr addrspace(1) nocapture %arg, i32 ; GFX11-NEXT: s_cmp_lg_u32 s0, 0 ; GFX11-NEXT: s_cselect_b64 s[8:9], -1, 0 ; GFX11-NEXT: s_cmp_lt_i32 s3, 6 -; GFX11-NEXT: s_cbranch_scc1 .LBB10_1 -; GFX11-NEXT: ; %bb.8: ; %bb +; GFX11-NEXT: s_cbranch_scc1 .LBB10_20 +; GFX11-NEXT: ; %bb.1: ; %bb ; GFX11-NEXT: s_getpc_b64 s[8:9] ; GFX11-NEXT: .Lpost_getpc11: ; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) @@ -1345,29 +1345,29 @@ define amdgpu_kernel void @long_branch_hang(ptr addrspace(1) nocapture %arg, i32 ; GFX11-NEXT: s_addc_u32 s9, s9, (.LBB10_2-.Lpost_getpc11)>>32 ; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: s_setpc_b64 s[8:9] -; GFX11-NEXT: .LBB10_1: ; %bb13 +; GFX11-NEXT: .LBB10_20: ; %bb13 ; GFX11-NEXT: ;;#ASMSTART ; GFX11-NEXT: v_nop_e64 ; GFX11-NEXT: v_nop_e64 ; GFX11-NEXT: v_nop_e64 ; GFX11-NEXT: v_nop_e64 ; GFX11-NEXT: ;;#ASMEND -; GFX11-NEXT: s_cbranch_execz .LBB10_3 -; GFX11-NEXT: s_branch .LBB10_4 +; GFX11-NEXT: s_cbranch_execz .LBB10_4 +; GFX11-NEXT: s_branch .LBB10_5 ; GFX11-NEXT: .LBB10_2: ; GFX11-NEXT: s_mov_b64 s[8:9], 0 -; GFX11-NEXT: .LBB10_3: ; %bb9 +; GFX11-NEXT: .LBB10_4: ; %bb9 ; GFX11-NEXT: s_cmp_lt_i32 s3, 11 ; GFX11-NEXT: s_cselect_b64 s[8:9], -1, 0 ; GFX11-NEXT: s_cmp_ge_i32 s2, s3 ; GFX11-NEXT: s_cselect_b64 s[10:11], -1, 0 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_and_b64 s[8:9], s[10:11], s[8:9] -; GFX11-NEXT: .LBB10_4: ; %Flow5 +; GFX11-NEXT: .LBB10_5: ; %Flow5 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_and_not1_b64 vcc, exec, s[8:9] -; GFX11-NEXT: s_cbranch_vccnz .LBB10_6 -; GFX11-NEXT: ; %bb.5: ; %bb14 +; GFX11-NEXT: s_cbranch_vccnz .LBB10_7 +; GFX11-NEXT: ; %bb.6: ; %bb14 ; GFX11-NEXT: s_cmp_lt_i32 s1, 9 ; GFX11-NEXT: s_cselect_b64 s[0:1], -1, 0 ; GFX11-NEXT: s_cmp_lt_i32 s2, s3 @@ -1377,10 +1377,10 @@ define amdgpu_kernel void @long_branch_hang(ptr addrspace(1) nocapture %arg, i32 ; GFX11-NEXT: s_and_b64 s[0:1], s[6:7], s[0:1] ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] -; GFX11-NEXT: s_branch .LBB10_7 -; GFX11-NEXT: .LBB10_6: +; GFX11-NEXT: s_branch .LBB10_8 +; GFX11-NEXT: .LBB10_7: ; GFX11-NEXT: ; implicit-def: $vgpr0 -; GFX11-NEXT: .LBB10_7: ; %bb19 +; GFX11-NEXT: .LBB10_8: ; %bb19 ; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x3c ; GFX11-NEXT: s_load_b64 s[2:3], s[4:5], 0x24 @@ -1404,8 +1404,8 @@ define amdgpu_kernel void @long_branch_hang(ptr addrspace(1) nocapture %arg, i32 ; GFX12-NEXT: s_mov_b32 s0, 0 ; GFX12-NEXT: s_cselect_b32 s8, -1, 0 ; GFX12-NEXT: s_cmp_lt_i32 s3, 6 -; GFX12-NEXT: s_cbranch_scc0 .LBB10_1 -; GFX12-NEXT: ; %bb.18: ; %bb +; GFX12-NEXT: s_cbranch_scc0 .LBB10_20 +; GFX12-NEXT: ; %bb.1: ; %bb ; GFX12-NEXT: s_getpc_b64 s[10:11] ; GFX12-NEXT: .Lpost_getpc17: ; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) @@ -1413,10 +1413,10 @@ define amdgpu_kernel void @long_branch_hang(ptr addrspace(1) nocapture %arg, i32 ; GFX12-NEXT: s_add_co_ci_u32 s11, s11, (.LBB10_4-.Lpost_getpc17)>>32 ; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) ; GFX12-NEXT: s_setpc_b64 s[10:11] -; GFX12-NEXT: .LBB10_1: ; %Flow +; GFX12-NEXT: .LBB10_20: ; %Flow ; GFX12-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s7 ; GFX12-NEXT: s_cbranch_vccnz .LBB10_2 -; GFX12-NEXT: ; %bb.10: ; %Flow +; GFX12-NEXT: ; %bb.3: ; %Flow ; GFX12-NEXT: s_getpc_b64 s[8:9] ; GFX12-NEXT: .Lpost_getpc13: ; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) @@ -1427,7 +1427,7 @@ define amdgpu_kernel void @long_branch_hang(ptr addrspace(1) nocapture %arg, i32 ; GFX12-NEXT: .LBB10_2: ; %Flow5 ; GFX12-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0 ; GFX12-NEXT: s_cbranch_vccz .LBB10_3 -; GFX12-NEXT: ; %bb.12: ; %Flow5 +; GFX12-NEXT: ; %bb.5: ; %Flow5 ; GFX12-NEXT: s_getpc_b64 s[0:1] ; GFX12-NEXT: .Lpost_getpc14: ; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) @@ -1445,7 +1445,7 @@ define amdgpu_kernel void @long_branch_hang(ptr addrspace(1) nocapture %arg, i32 ; GFX12-NEXT: s_and_b32 s0, s6, s0 ; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 -; GFX12-NEXT: ; %bb.8: ; %bb14 +; GFX12-NEXT: ; %bb.7: ; %bb14 ; GFX12-NEXT: s_getpc_b64 s[0:1] ; GFX12-NEXT: .Lpost_getpc12: ; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) @@ -1462,7 +1462,7 @@ define amdgpu_kernel void @long_branch_hang(ptr addrspace(1) nocapture %arg, i32 ; GFX12-NEXT: v_nop_e64 ; GFX12-NEXT: ;;#ASMEND ; GFX12-NEXT: s_cbranch_execz .LBB10_5 -; GFX12-NEXT: ; %bb.14: ; %bb13 +; GFX12-NEXT: ; %bb.9: ; %bb13 ; GFX12-NEXT: s_getpc_b64 s[8:9] ; GFX12-NEXT: .Lpost_getpc15: ; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) @@ -1479,7 +1479,7 @@ define amdgpu_kernel void @long_branch_hang(ptr addrspace(1) nocapture %arg, i32 ; GFX12-NEXT: s_and_b32 s0, s7, s0 ; GFX12-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0 ; GFX12-NEXT: s_cbranch_vccnz .LBB10_6 -; GFX12-NEXT: ; %bb.16: ; %bb9 +; GFX12-NEXT: ; %bb.11: ; %bb9 ; GFX12-NEXT: s_getpc_b64 s[8:9] ; GFX12-NEXT: .Lpost_getpc16: ; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-multi-memop.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-multi-memop.ll index 55159634eb4e5..1814bfcc55dde 100644 --- a/llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-multi-memop.ll +++ b/llvm/test/CodeGen/AMDGPU/dagcombine-reassociate-multi-memop.ll @@ -13,13 +13,13 @@ declare i32 @llvm.amdgcn.workitem.id.x() define amdgpu_kernel void @buffer_load_lds_reassociate_offsets(ptr addrspace(1) inreg %ptr) { ; CHECK-LABEL: buffer_load_lds_reassociate_offsets: -; CHECK: ; %bb.1: +; CHECK: ; %bb.0: ; CHECK-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0 ; CHECK-NEXT: s_waitcnt lgkmcnt(0) -; CHECK-NEXT: s_branch .LBB0_0 +; CHECK-NEXT: s_branch .LBB0_2 ; CHECK-NEXT: .p2align 8 -; CHECK-NEXT: ; %bb.2: -; CHECK-NEXT: .LBB0_0: +; CHECK-NEXT: ; %bb.1: +; CHECK-NEXT: .LBB0_2: ; CHECK-NEXT: v_and_b32_e32 v0, 0x3ff, v0 ; CHECK-NEXT: v_mul_u32_u24_e32 v0, 0x600, v0 ; CHECK-NEXT: v_lshlrev_b32_e32 v0, 1, v0 diff --git a/llvm/test/CodeGen/AMDGPU/lds-dma-workgroup-release.ll b/llvm/test/CodeGen/AMDGPU/lds-dma-workgroup-release.ll index f99718de97765..1f38bdc6a94ba 100644 --- a/llvm/test/CodeGen/AMDGPU/lds-dma-workgroup-release.ll +++ b/llvm/test/CodeGen/AMDGPU/lds-dma-workgroup-release.ll @@ -34,14 +34,14 @@ define amdgpu_kernel void @barrier_release(<4 x i32> inreg %rsrc, ; GFX900-NEXT: s_endpgm ; ; GFX90A-LABEL: barrier_release: -; GFX90A: ; %bb.1: +; GFX90A: ; %bb.0: ; GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 ; GFX90A-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10 ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) -; GFX90A-NEXT: s_branch .LBB0_0 +; GFX90A-NEXT: s_branch .LBB0_2 ; GFX90A-NEXT: .p2align 8 -; GFX90A-NEXT: ; %bb.2: -; GFX90A-NEXT: .LBB0_0: ; %main_body +; GFX90A-NEXT: ; %bb.1: +; GFX90A-NEXT: .LBB0_2: ; %main_body ; GFX90A-NEXT: s_mov_b32 m0, s12 ; GFX90A-NEXT: v_mov_b32_e32 v0, 0x800 ; GFX90A-NEXT: buffer_load_dword v0, s[8:11], 0 offen lds @@ -56,14 +56,14 @@ define amdgpu_kernel void @barrier_release(<4 x i32> inreg %rsrc, ; GFX90A-NEXT: s_endpgm ; ; GFX90A-TGSPLIT-LABEL: barrier_release: -; GFX90A-TGSPLIT: ; %bb.1: +; GFX90A-TGSPLIT: ; %bb.0: ; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 ; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10 ; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0) -; GFX90A-TGSPLIT-NEXT: s_branch .LBB0_0 +; GFX90A-TGSPLIT-NEXT: s_branch .LBB0_2 ; GFX90A-TGSPLIT-NEXT: .p2align 8 -; GFX90A-TGSPLIT-NEXT: ; %bb.2: -; GFX90A-TGSPLIT-NEXT: .LBB0_0: ; %main_body +; GFX90A-TGSPLIT-NEXT: ; %bb.1: +; GFX90A-TGSPLIT-NEXT: .LBB0_2: ; %main_body ; GFX90A-TGSPLIT-NEXT: s_mov_b32 m0, s12 ; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, 0x800 ; GFX90A-TGSPLIT-NEXT: buffer_load_dword v0, s[8:11], 0 offen lds @@ -79,14 +79,14 @@ define amdgpu_kernel void @barrier_release(<4 x i32> inreg %rsrc, ; GFX90A-TGSPLIT-NEXT: s_endpgm ; ; GFX942-LABEL: barrier_release: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 ; GFX942-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB0_0 +; GFX942-NEXT: s_branch .LBB0_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB0_0: ; %main_body +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB0_2: ; %main_body ; GFX942-NEXT: s_mov_b32 m0, s12 ; GFX942-NEXT: v_mov_b32_e32 v0, 0x800 ; GFX942-NEXT: buffer_load_dword v0, s[8:11], 0 offen lds @@ -101,14 +101,14 @@ define amdgpu_kernel void @barrier_release(<4 x i32> inreg %rsrc, ; GFX942-NEXT: s_endpgm ; ; GFX942-TGSPLIT-LABEL: barrier_release: -; GFX942-TGSPLIT: ; %bb.1: +; GFX942-TGSPLIT: ; %bb.0: ; GFX942-TGSPLIT-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 ; GFX942-TGSPLIT-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10 ; GFX942-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-TGSPLIT-NEXT: s_branch .LBB0_0 +; GFX942-TGSPLIT-NEXT: s_branch .LBB0_2 ; GFX942-TGSPLIT-NEXT: .p2align 8 -; GFX942-TGSPLIT-NEXT: ; %bb.2: -; GFX942-TGSPLIT-NEXT: .LBB0_0: ; %main_body +; GFX942-TGSPLIT-NEXT: ; %bb.1: +; GFX942-TGSPLIT-NEXT: .LBB0_2: ; %main_body ; GFX942-TGSPLIT-NEXT: s_mov_b32 m0, s12 ; GFX942-TGSPLIT-NEXT: v_mov_b32_e32 v0, 0x800 ; GFX942-TGSPLIT-NEXT: buffer_load_dword v0, s[8:11], 0 offen lds @@ -192,14 +192,14 @@ define amdgpu_kernel void @fence_fence(<4 x i32> inreg %rsrc, ; GFX900-NEXT: s_endpgm ; ; GFX90A-LABEL: fence_fence: -; GFX90A: ; %bb.1: +; GFX90A: ; %bb.0: ; GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 ; GFX90A-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10 ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) -; GFX90A-NEXT: s_branch .LBB1_0 +; GFX90A-NEXT: s_branch .LBB1_2 ; GFX90A-NEXT: .p2align 8 -; GFX90A-NEXT: ; %bb.2: -; GFX90A-NEXT: .LBB1_0: ; %main_body +; GFX90A-NEXT: ; %bb.1: +; GFX90A-NEXT: .LBB1_2: ; %main_body ; GFX90A-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x3c ; GFX90A-NEXT: s_mov_b32 m0, s12 ; GFX90A-NEXT: v_mov_b32_e32 v1, 0x800 @@ -217,14 +217,14 @@ define amdgpu_kernel void @fence_fence(<4 x i32> inreg %rsrc, ; GFX90A-NEXT: s_endpgm ; ; GFX90A-TGSPLIT-LABEL: fence_fence: -; GFX90A-TGSPLIT: ; %bb.1: +; GFX90A-TGSPLIT: ; %bb.0: ; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 ; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10 ; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0) -; GFX90A-TGSPLIT-NEXT: s_branch .LBB1_0 +; GFX90A-TGSPLIT-NEXT: s_branch .LBB1_2 ; GFX90A-TGSPLIT-NEXT: .p2align 8 -; GFX90A-TGSPLIT-NEXT: ; %bb.2: -; GFX90A-TGSPLIT-NEXT: .LBB1_0: ; %main_body +; GFX90A-TGSPLIT-NEXT: ; %bb.1: +; GFX90A-TGSPLIT-NEXT: .LBB1_2: ; %main_body ; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x3c ; GFX90A-TGSPLIT-NEXT: s_mov_b32 m0, s12 ; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, 0x800 @@ -243,14 +243,14 @@ define amdgpu_kernel void @fence_fence(<4 x i32> inreg %rsrc, ; GFX90A-TGSPLIT-NEXT: s_endpgm ; ; GFX942-LABEL: fence_fence: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 ; GFX942-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB1_0 +; GFX942-NEXT: s_branch .LBB1_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB1_0: ; %main_body +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB1_2: ; %main_body ; GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x3c ; GFX942-NEXT: s_mov_b32 m0, s12 ; GFX942-NEXT: v_mov_b32_e32 v1, 0x800 @@ -268,14 +268,14 @@ define amdgpu_kernel void @fence_fence(<4 x i32> inreg %rsrc, ; GFX942-NEXT: s_endpgm ; ; GFX942-TGSPLIT-LABEL: fence_fence: -; GFX942-TGSPLIT: ; %bb.1: +; GFX942-TGSPLIT: ; %bb.0: ; GFX942-TGSPLIT-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 ; GFX942-TGSPLIT-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10 ; GFX942-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-TGSPLIT-NEXT: s_branch .LBB1_0 +; GFX942-TGSPLIT-NEXT: s_branch .LBB1_2 ; GFX942-TGSPLIT-NEXT: .p2align 8 -; GFX942-TGSPLIT-NEXT: ; %bb.2: -; GFX942-TGSPLIT-NEXT: .LBB1_0: ; %main_body +; GFX942-TGSPLIT-NEXT: ; %bb.1: +; GFX942-TGSPLIT-NEXT: .LBB1_2: ; %main_body ; GFX942-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x3c ; GFX942-TGSPLIT-NEXT: s_mov_b32 m0, s12 ; GFX942-TGSPLIT-NEXT: v_mov_b32_e32 v1, 0x800 @@ -377,14 +377,14 @@ define amdgpu_kernel void @release_acquire(<4 x i32> inreg %rsrc, ; GFX900-NEXT: s_endpgm ; ; GFX90A-LABEL: release_acquire: -; GFX90A: ; %bb.1: +; GFX90A: ; %bb.0: ; GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 ; GFX90A-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10 ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) -; GFX90A-NEXT: s_branch .LBB2_0 +; GFX90A-NEXT: s_branch .LBB2_2 ; GFX90A-NEXT: .p2align 8 -; GFX90A-NEXT: ; %bb.2: -; GFX90A-NEXT: .LBB2_0: ; %main_body +; GFX90A-NEXT: ; %bb.1: +; GFX90A-NEXT: .LBB2_2: ; %main_body ; GFX90A-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x3c ; GFX90A-NEXT: s_mov_b32 m0, s12 ; GFX90A-NEXT: v_mov_b32_e32 v1, 0x800 @@ -402,14 +402,14 @@ define amdgpu_kernel void @release_acquire(<4 x i32> inreg %rsrc, ; GFX90A-NEXT: s_endpgm ; ; GFX90A-TGSPLIT-LABEL: release_acquire: -; GFX90A-TGSPLIT: ; %bb.1: +; GFX90A-TGSPLIT: ; %bb.0: ; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 ; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10 ; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0) -; GFX90A-TGSPLIT-NEXT: s_branch .LBB2_0 +; GFX90A-TGSPLIT-NEXT: s_branch .LBB2_2 ; GFX90A-TGSPLIT-NEXT: .p2align 8 -; GFX90A-TGSPLIT-NEXT: ; %bb.2: -; GFX90A-TGSPLIT-NEXT: .LBB2_0: ; %main_body +; GFX90A-TGSPLIT-NEXT: ; %bb.1: +; GFX90A-TGSPLIT-NEXT: .LBB2_2: ; %main_body ; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x3c ; GFX90A-TGSPLIT-NEXT: s_mov_b32 m0, s12 ; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, 0x800 @@ -428,14 +428,14 @@ define amdgpu_kernel void @release_acquire(<4 x i32> inreg %rsrc, ; GFX90A-TGSPLIT-NEXT: s_endpgm ; ; GFX942-LABEL: release_acquire: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 ; GFX942-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB2_0 +; GFX942-NEXT: s_branch .LBB2_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB2_0: ; %main_body +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB2_2: ; %main_body ; GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x3c ; GFX942-NEXT: s_mov_b32 m0, s12 ; GFX942-NEXT: v_mov_b32_e32 v1, 0x800 @@ -453,14 +453,14 @@ define amdgpu_kernel void @release_acquire(<4 x i32> inreg %rsrc, ; GFX942-NEXT: s_endpgm ; ; GFX942-TGSPLIT-LABEL: release_acquire: -; GFX942-TGSPLIT: ; %bb.1: +; GFX942-TGSPLIT: ; %bb.0: ; GFX942-TGSPLIT-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 ; GFX942-TGSPLIT-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10 ; GFX942-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-TGSPLIT-NEXT: s_branch .LBB2_0 +; GFX942-TGSPLIT-NEXT: s_branch .LBB2_2 ; GFX942-TGSPLIT-NEXT: .p2align 8 -; GFX942-TGSPLIT-NEXT: ; %bb.2: -; GFX942-TGSPLIT-NEXT: .LBB2_0: ; %main_body +; GFX942-TGSPLIT-NEXT: ; %bb.1: +; GFX942-TGSPLIT-NEXT: .LBB2_2: ; %main_body ; GFX942-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x3c ; GFX942-TGSPLIT-NEXT: s_mov_b32 m0, s12 ; GFX942-TGSPLIT-NEXT: v_mov_b32_e32 v1, 0x800 diff --git a/llvm/test/CodeGen/AMDGPU/literal-constant-like-operand-instruction-size.ll b/llvm/test/CodeGen/AMDGPU/literal-constant-like-operand-instruction-size.ll index f607385dca542..9a95d9ae62e56 100644 --- a/llvm/test/CodeGen/AMDGPU/literal-constant-like-operand-instruction-size.ll +++ b/llvm/test/CodeGen/AMDGPU/literal-constant-like-operand-instruction-size.ll @@ -11,7 +11,7 @@ declare void @llvm.amdgcn.s.sleep(i32) #0 ; GCN-LABEL: {{^}}branch_offset_test: ; GCN: s_cmp_eq_u32 s{{[0-9]+}}, 0 ; GCN-NEXT: s_cbranch_scc0 [[BB2:.LBB[0-9]+_[0-9]+]] -; GCN-NEXT: ; %bb.3: ; %bb +; GCN-NEXT: ; %bb.1: ; %bb ; GCN-NEXT: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]] ; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}} ; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], ([[BB3:.LBB[0-9]+_[0-9]+]]-[[POST_GETPC]])&4294967295 diff --git a/llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll b/llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll index 4d751f2605c39..bb2ad97ed67a3 100644 --- a/llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll +++ b/llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll @@ -58,14 +58,14 @@ define amdgpu_kernel void @uniform_conditional_min_long_forward_branch(ptr addrs ; GCN-NEXT: s_load_dword s0, s[4:5], 0xb ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_cmp_eq_u32 s0, 0 -; GCN-NEXT: s_cbranch_scc0 .LBB1_1 -; GCN-NEXT: ; %bb.3: ; %bb0 +; GCN-NEXT: s_cbranch_scc0 .LBB1_20 +; GCN-NEXT: ; %bb.1: ; %bb0 ; GCN-NEXT: s_getpc_b64 s[2:3] ; GCN-NEXT: .Lpost_getpc0: ; GCN-NEXT: s_add_u32 s2, s2, (.LBB1_2-.Lpost_getpc0)&4294967295 ; GCN-NEXT: s_addc_u32 s3, s3, (.LBB1_2-.Lpost_getpc0)>>32 ; GCN-NEXT: s_setpc_b64 s[2:3] -; GCN-NEXT: .LBB1_1: ; %bb2 +; GCN-NEXT: .LBB1_20: ; %bb2 ; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: v_nop_e64 ; GCN-NEXT: v_nop_e64 @@ -106,14 +106,14 @@ define amdgpu_kernel void @uniform_conditional_min_long_forward_vcnd_branch(ptr ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: v_cmp_eq_f32_e64 s[2:3], s0, 0 ; GCN-NEXT: s_and_b64 vcc, exec, s[2:3] -; GCN-NEXT: s_cbranch_vccz .LBB2_1 -; GCN-NEXT: ; %bb.3: ; %bb0 +; GCN-NEXT: s_cbranch_vccz .LBB2_20 +; GCN-NEXT: ; %bb.1: ; %bb0 ; GCN-NEXT: s_getpc_b64 s[8:9] ; GCN-NEXT: .Lpost_getpc1: ; GCN-NEXT: s_add_u32 s8, s8, (.LBB2_2-.Lpost_getpc1)&4294967295 ; GCN-NEXT: s_addc_u32 s9, s9, (.LBB2_2-.Lpost_getpc1)>>32 ; GCN-NEXT: s_setpc_b64 s[8:9] -; GCN-NEXT: .LBB2_1: ; %bb2 +; GCN-NEXT: .LBB2_20: ; %bb2 ; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: ; 32 bytes ; GCN-NEXT: v_nop_e64 @@ -163,14 +163,14 @@ define amdgpu_kernel void @min_long_forward_vbranch(ptr addrspace(1) %arg) #0 { ; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; GCN-NEXT: s_and_saveexec_b64 s[0:1], vcc -; GCN-NEXT: s_cbranch_execnz .LBB3_1 -; GCN-NEXT: ; %bb.3: ; %bb +; GCN-NEXT: s_cbranch_execnz .LBB3_20 +; GCN-NEXT: ; %bb.1: ; %bb ; GCN-NEXT: s_getpc_b64 s[6:7] ; GCN-NEXT: .Lpost_getpc2: ; GCN-NEXT: s_add_u32 s6, s6, (.LBB3_2-.Lpost_getpc2)&4294967295 ; GCN-NEXT: s_addc_u32 s7, s7, (.LBB3_2-.Lpost_getpc2)>>32 ; GCN-NEXT: s_setpc_b64 s[6:7] -; GCN-NEXT: .LBB3_1: ; %bb2 +; GCN-NEXT: .LBB3_20: ; %bb2 ; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: ; 32 bytes ; GCN-NEXT: v_nop_e64 @@ -219,15 +219,15 @@ define amdgpu_kernel void @long_backward_sbranch(ptr addrspace(1) %arg) #0 { ; GCN-NEXT: v_nop_e64 ; GCN-NEXT: v_nop_e64 ; GCN-NEXT: ;;#ASMEND -; GCN-NEXT: s_cbranch_scc0 .LBB4_2 -; GCN-NEXT: ; %bb.3: ; %bb2 +; GCN-NEXT: s_cbranch_scc0 .LBB4_3 +; GCN-NEXT: ; %bb.2: ; %bb2 ; GCN-NEXT: ; in Loop: Header=BB4_1 Depth=1 ; GCN-NEXT: s_getpc_b64 s[2:3] ; GCN-NEXT: .Lpost_getpc3: ; GCN-NEXT: s_add_u32 s2, s2, (.LBB4_1-.Lpost_getpc3)&4294967295 ; GCN-NEXT: s_addc_u32 s3, s3, (.LBB4_1-.Lpost_getpc3)>>32 ; GCN-NEXT: s_setpc_b64 s[2:3] -; GCN-NEXT: .LBB4_2: ; %bb3 +; GCN-NEXT: .LBB4_3: ; %bb3 ; GCN-NEXT: s_endpgm bb: @@ -258,14 +258,14 @@ define amdgpu_kernel void @uniform_unconditional_min_long_forward_branch(ptr add ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_cmp_eq_u32 s0, 0 ; GCN-NEXT: s_mov_b64 s[0:1], -1 -; GCN-NEXT: s_cbranch_scc0 .LBB5_1 -; GCN-NEXT: ; %bb.7: ; %bb0 +; GCN-NEXT: s_cbranch_scc0 .LBB5_20 +; GCN-NEXT: ; %bb.1: ; %bb0 ; GCN-NEXT: s_getpc_b64 s[6:7] ; GCN-NEXT: .Lpost_getpc5: ; GCN-NEXT: s_add_u32 s6, s6, (.LBB5_4-.Lpost_getpc5)&4294967295 ; GCN-NEXT: s_addc_u32 s7, s7, (.LBB5_4-.Lpost_getpc5)>>32 ; GCN-NEXT: s_setpc_b64 s[6:7] -; GCN-NEXT: .LBB5_1: ; %Flow +; GCN-NEXT: .LBB5_20: ; %Flow ; GCN-NEXT: s_andn2_b64 vcc, exec, s[0:1] ; GCN-NEXT: s_cbranch_vccnz .LBB5_3 ; GCN-NEXT: .LBB5_2: ; %bb2 @@ -292,14 +292,14 @@ define amdgpu_kernel void @uniform_unconditional_min_long_forward_branch(ptr add ; GCN-NEXT: v_nop_e64 ; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: s_mov_b64 vcc, exec -; GCN-NEXT: s_cbranch_execnz .LBB5_5 -; GCN-NEXT: ; %bb.9: ; %bb3 +; GCN-NEXT: s_cbranch_execnz .LBB5_7 +; GCN-NEXT: ; %bb.6: ; %bb3 ; GCN-NEXT: s_getpc_b64 s[6:7] ; GCN-NEXT: .Lpost_getpc6: ; GCN-NEXT: s_add_u32 s6, s6, (.LBB5_2-.Lpost_getpc6)&4294967295 ; GCN-NEXT: s_addc_u32 s7, s7, (.LBB5_2-.Lpost_getpc6)>>32 ; GCN-NEXT: s_setpc_b64 s[6:7] -; GCN-NEXT: .LBB5_5: ; %bb3 +; GCN-NEXT: .LBB5_7: ; %bb3 ; GCN-NEXT: s_getpc_b64 s[6:7] ; GCN-NEXT: .Lpost_getpc4: ; GCN-NEXT: s_add_u32 s6, s6, (.LBB5_3-.Lpost_getpc4)&4294967295 diff --git a/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll b/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll index 8b37734cfa046..19dbc6540bbdd 100644 --- a/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll +++ b/llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll @@ -5,28 +5,28 @@ define amdgpu_kernel void @preload_block_count_x(ptr addrspace(1) inreg %out) #0 { ; GFX942-LABEL: preload_block_count_x: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dword s4, s[0:1], 0x8 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB0_0 +; GFX942-NEXT: s_branch .LBB0_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB0_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB0_2: ; GFX942-NEXT: v_mov_b32_e32 v0, 0 ; GFX942-NEXT: v_mov_b32_e32 v1, s4 ; GFX942-NEXT: global_store_dword v0, v1, s[2:3] ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: preload_block_count_x: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0 ; GFX90a-NEXT: s_load_dword s10, s[4:5], 0x8 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB0_0 +; GFX90a-NEXT: s_branch .LBB0_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB0_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB0_2: ; GFX90a-NEXT: v_mov_b32_e32 v0, 0 ; GFX90a-NEXT: v_mov_b32_e32 v1, s10 ; GFX90a-NEXT: global_store_dword v0, v1, s[8:9] @@ -34,7 +34,7 @@ define amdgpu_kernel void @preload_block_count_x(ptr addrspace(1) inreg %out) #0 ; ; GFX1250-LABEL: preload_block_count_x: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4 ; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3] ; GFX1250-NEXT: s_endpgm @@ -46,29 +46,29 @@ define amdgpu_kernel void @preload_block_count_x(ptr addrspace(1) inreg %out) #0 define amdgpu_kernel void @preload_unused_arg_block_count_x(ptr addrspace(1) inreg %out, i32 inreg) #0 { ; GFX942-LABEL: preload_unused_arg_block_count_x: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8 ; GFX942-NEXT: s_load_dword s6, s[0:1], 0x10 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB1_0 +; GFX942-NEXT: s_branch .LBB1_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB1_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB1_2: ; GFX942-NEXT: v_mov_b32_e32 v0, 0 ; GFX942-NEXT: v_mov_b32_e32 v1, s6 ; GFX942-NEXT: global_store_dword v0, v1, s[2:3] ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: preload_unused_arg_block_count_x: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 ; GFX90a-NEXT: s_load_dword s12, s[4:5], 0x10 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB1_0 +; GFX90a-NEXT: s_branch .LBB1_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB1_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB1_2: ; GFX90a-NEXT: v_mov_b32_e32 v0, 0 ; GFX90a-NEXT: v_mov_b32_e32 v1, s12 ; GFX90a-NEXT: global_store_dword v0, v1, s[8:9] @@ -76,7 +76,7 @@ define amdgpu_kernel void @preload_unused_arg_block_count_x(ptr addrspace(1) inr ; ; GFX1250-LABEL: preload_unused_arg_block_count_x: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s6 ; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3] ; GFX1250-NEXT: s_endpgm @@ -88,13 +88,13 @@ define amdgpu_kernel void @preload_unused_arg_block_count_x(ptr addrspace(1) inr define amdgpu_kernel void @no_free_sgprs_block_count_x(ptr addrspace(1) inreg %out, i256 inreg) { ; GFX942-LABEL: no_free_sgprs_block_count_x: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB2_0 +; GFX942-NEXT: s_branch .LBB2_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB2_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB2_2: ; GFX942-NEXT: s_load_dword s0, s[4:5], 0x28 ; GFX942-NEXT: v_mov_b32_e32 v0, 0 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) @@ -103,13 +103,13 @@ define amdgpu_kernel void @no_free_sgprs_block_count_x(ptr addrspace(1) inreg %o ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: no_free_sgprs_block_count_x: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx2 s[14:15], s[8:9], 0x0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB2_0 +; GFX90a-NEXT: s_branch .LBB2_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB2_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB2_2: ; GFX90a-NEXT: s_load_dword s0, s[8:9], 0x28 ; GFX90a-NEXT: v_mov_b32_e32 v0, 0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) @@ -119,7 +119,7 @@ define amdgpu_kernel void @no_free_sgprs_block_count_x(ptr addrspace(1) inreg %o ; ; GFX1250-LABEL: no_free_sgprs_block_count_x: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s18 ; GFX1250-NEXT: global_store_b32 v0, v1, s[8:9] ; GFX1250-NEXT: s_endpgm @@ -152,8 +152,8 @@ define amdgpu_kernel void @no_inreg_block_count_x(ptr addrspace(1) %out) #0 { ; ; GFX1250-LABEL: no_inreg_block_count_x: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 -; GFX1250-NEXT: s_load_b96 s[0:2], s[0:1], 0x0 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 +; GFX1250-NEXT: s_load_b96 s[0:2], s[0:1], 0x0 nv ; GFX1250-NEXT: s_wait_kmcnt 0x0 ; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 ; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1] @@ -190,10 +190,10 @@ define amdgpu_kernel void @mixed_inreg_block_count_x(ptr addrspace(1) %out, i32 ; ; GFX1250-LABEL: mixed_inreg_block_count_x: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: s_clause 0x1 -; GFX1250-NEXT: s_load_b32 s4, s[0:1], 0x10 -; GFX1250-NEXT: s_load_b64 s[2:3], s[0:1], 0x0 +; GFX1250-NEXT: s_load_b32 s4, s[0:1], 0x10 nv +; GFX1250-NEXT: s_load_b64 s[2:3], s[0:1], 0x0 nv ; GFX1250-NEXT: s_wait_kmcnt 0x0 ; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4 ; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3] @@ -206,13 +206,13 @@ define amdgpu_kernel void @mixed_inreg_block_count_x(ptr addrspace(1) %out, i32 define amdgpu_kernel void @incorrect_type_i64_block_count_x(ptr addrspace(1) inreg %out) #0 { ; GFX942-LABEL: incorrect_type_i64_block_count_x: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB5_0 +; GFX942-NEXT: s_branch .LBB5_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB5_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB5_2: ; GFX942-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x8 ; GFX942-NEXT: v_mov_b32_e32 v0, 0 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) @@ -221,13 +221,13 @@ define amdgpu_kernel void @incorrect_type_i64_block_count_x(ptr addrspace(1) inr ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: incorrect_type_i64_block_count_x: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB5_0 +; GFX90a-NEXT: s_branch .LBB5_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB5_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB5_2: ; GFX90a-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8 ; GFX90a-NEXT: v_mov_b32_e32 v0, 0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) @@ -237,8 +237,8 @@ define amdgpu_kernel void @incorrect_type_i64_block_count_x(ptr addrspace(1) inr ; ; GFX1250-LABEL: incorrect_type_i64_block_count_x: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 -; GFX1250-NEXT: s_load_b64 s[0:1], s[0:1], 0x8 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 +; GFX1250-NEXT: s_load_b64 s[0:1], s[0:1], 0x8 nv ; GFX1250-NEXT: v_mov_b32_e32 v2, 0 ; GFX1250-NEXT: s_wait_kmcnt 0x0 ; GFX1250-NEXT: v_mov_b64_e32 v[0:1], s[0:1] @@ -252,13 +252,13 @@ define amdgpu_kernel void @incorrect_type_i64_block_count_x(ptr addrspace(1) inr define amdgpu_kernel void @incorrect_type_i16_block_count_x(ptr addrspace(1) inreg %out) #0 { ; GFX942-LABEL: incorrect_type_i16_block_count_x: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB6_0 +; GFX942-NEXT: s_branch .LBB6_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB6_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB6_2: ; GFX942-NEXT: s_load_dword s0, s[0:1], 0x8 ; GFX942-NEXT: v_mov_b32_e32 v0, 0 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) @@ -267,13 +267,13 @@ define amdgpu_kernel void @incorrect_type_i16_block_count_x(ptr addrspace(1) inr ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: incorrect_type_i16_block_count_x: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB6_0 +; GFX90a-NEXT: s_branch .LBB6_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB6_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB6_2: ; GFX90a-NEXT: s_load_dword s0, s[4:5], 0x8 ; GFX90a-NEXT: v_mov_b32_e32 v0, 0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) @@ -283,9 +283,9 @@ define amdgpu_kernel void @incorrect_type_i16_block_count_x(ptr addrspace(1) inr ; ; GFX1250-LABEL: incorrect_type_i16_block_count_x: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: v_mov_b32_e32 v0, 0 -; GFX1250-NEXT: global_load_u16 v1, v0, s[0:1] offset:8 +; GFX1250-NEXT: global_load_u16 v1, v0, s[0:1] offset:8 nv ; GFX1250-NEXT: s_wait_loadcnt 0x0 ; GFX1250-NEXT: global_store_b16 v0, v1, s[2:3] ; GFX1250-NEXT: s_endpgm @@ -297,27 +297,27 @@ define amdgpu_kernel void @incorrect_type_i16_block_count_x(ptr addrspace(1) inr define amdgpu_kernel void @preload_block_count_y(ptr addrspace(1) inreg %out) #0 { ; GFX942-LABEL: preload_block_count_y: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB7_0 +; GFX942-NEXT: s_branch .LBB7_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB7_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB7_2: ; GFX942-NEXT: v_mov_b32_e32 v0, 0 ; GFX942-NEXT: v_mov_b32_e32 v1, s5 ; GFX942-NEXT: global_store_dword v0, v1, s[2:3] ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: preload_block_count_y: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB7_0 +; GFX90a-NEXT: s_branch .LBB7_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB7_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB7_2: ; GFX90a-NEXT: v_mov_b32_e32 v0, 0 ; GFX90a-NEXT: v_mov_b32_e32 v1, s11 ; GFX90a-NEXT: global_store_dword v0, v1, s[8:9] @@ -325,7 +325,7 @@ define amdgpu_kernel void @preload_block_count_y(ptr addrspace(1) inreg %out) #0 ; ; GFX1250-LABEL: preload_block_count_y: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s5 ; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3] ; GFX1250-NEXT: s_endpgm @@ -338,13 +338,13 @@ define amdgpu_kernel void @preload_block_count_y(ptr addrspace(1) inreg %out) #0 define amdgpu_kernel void @random_incorrect_offset(ptr addrspace(1) inreg %out) #0 { ; GFX942-LABEL: random_incorrect_offset: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB8_0 +; GFX942-NEXT: s_branch .LBB8_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB8_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB8_2: ; GFX942-NEXT: s_load_dword s0, s[0:1], 0xa ; GFX942-NEXT: v_mov_b32_e32 v0, 0 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) @@ -353,13 +353,13 @@ define amdgpu_kernel void @random_incorrect_offset(ptr addrspace(1) inreg %out) ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: random_incorrect_offset: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB8_0 +; GFX90a-NEXT: s_branch .LBB8_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB8_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB8_2: ; GFX90a-NEXT: s_load_dword s0, s[4:5], 0xa ; GFX90a-NEXT: v_mov_b32_e32 v0, 0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) @@ -369,8 +369,8 @@ define amdgpu_kernel void @random_incorrect_offset(ptr addrspace(1) inreg %out) ; ; GFX1250-LABEL: random_incorrect_offset: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 -; GFX1250-NEXT: s_load_b32 s0, s[0:1], 0xa +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 +; GFX1250-NEXT: s_load_b32 s0, s[0:1], 0xa nv ; GFX1250-NEXT: s_wait_kmcnt 0x0 ; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0 ; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3] @@ -384,29 +384,29 @@ define amdgpu_kernel void @random_incorrect_offset(ptr addrspace(1) inreg %out) define amdgpu_kernel void @preload_block_count_z(ptr addrspace(1) inreg %out) #0 { ; GFX942-LABEL: preload_block_count_z: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8 ; GFX942-NEXT: s_load_dword s6, s[0:1], 0x10 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB9_0 +; GFX942-NEXT: s_branch .LBB9_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB9_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB9_2: ; GFX942-NEXT: v_mov_b32_e32 v0, 0 ; GFX942-NEXT: v_mov_b32_e32 v1, s6 ; GFX942-NEXT: global_store_dword v0, v1, s[2:3] ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: preload_block_count_z: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 ; GFX90a-NEXT: s_load_dword s12, s[4:5], 0x10 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB9_0 +; GFX90a-NEXT: s_branch .LBB9_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB9_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB9_2: ; GFX90a-NEXT: v_mov_b32_e32 v0, 0 ; GFX90a-NEXT: v_mov_b32_e32 v1, s12 ; GFX90a-NEXT: global_store_dword v0, v1, s[8:9] @@ -414,7 +414,7 @@ define amdgpu_kernel void @preload_block_count_z(ptr addrspace(1) inreg %out) #0 ; ; GFX1250-LABEL: preload_block_count_z: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s6 ; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3] ; GFX1250-NEXT: s_endpgm @@ -427,15 +427,15 @@ define amdgpu_kernel void @preload_block_count_z(ptr addrspace(1) inreg %out) #0 define amdgpu_kernel void @preload_block_count_x_imparg_align_ptr_i8(ptr addrspace(1) inreg %out, i8 inreg %val) #0 { ; GFX942-LABEL: preload_block_count_x_imparg_align_ptr_i8: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8 ; GFX942-NEXT: s_load_dword s6, s[0:1], 0x10 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB10_0 +; GFX942-NEXT: s_branch .LBB10_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB10_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB10_2: ; GFX942-NEXT: s_and_b32 s0, s4, 0xff ; GFX942-NEXT: s_add_i32 s0, s6, s0 ; GFX942-NEXT: v_mov_b32_e32 v0, 0 @@ -444,14 +444,14 @@ define amdgpu_kernel void @preload_block_count_x_imparg_align_ptr_i8(ptr addrspa ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: preload_block_count_x_imparg_align_ptr_i8: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 ; GFX90a-NEXT: s_load_dword s12, s[4:5], 0x10 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB10_0 +; GFX90a-NEXT: s_branch .LBB10_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB10_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB10_2: ; GFX90a-NEXT: s_and_b32 s0, s10, 0xff ; GFX90a-NEXT: s_add_i32 s0, s12, s0 ; GFX90a-NEXT: v_mov_b32_e32 v0, 0 @@ -461,7 +461,7 @@ define amdgpu_kernel void @preload_block_count_x_imparg_align_ptr_i8(ptr addrspa ; ; GFX1250-LABEL: preload_block_count_x_imparg_align_ptr_i8: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: s_and_b32 s0, s4, 0xff ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) ; GFX1250-NEXT: s_add_co_i32 s0, s6, s0 @@ -478,15 +478,15 @@ define amdgpu_kernel void @preload_block_count_x_imparg_align_ptr_i8(ptr addrspa define amdgpu_kernel void @preload_block_count_xyz(ptr addrspace(1) inreg %out) #0 { ; GFX942-LABEL: preload_block_count_xyz: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8 ; GFX942-NEXT: s_load_dword s6, s[0:1], 0x10 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB11_0 +; GFX942-NEXT: s_branch .LBB11_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB11_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB11_2: ; GFX942-NEXT: v_mov_b32_e32 v3, 0 ; GFX942-NEXT: v_mov_b32_e32 v0, s4 ; GFX942-NEXT: v_mov_b32_e32 v1, s5 @@ -495,14 +495,14 @@ define amdgpu_kernel void @preload_block_count_xyz(ptr addrspace(1) inreg %out) ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: preload_block_count_xyz: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 ; GFX90a-NEXT: s_load_dword s12, s[4:5], 0x10 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB11_0 +; GFX90a-NEXT: s_branch .LBB11_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB11_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB11_2: ; GFX90a-NEXT: v_mov_b32_e32 v3, 0 ; GFX90a-NEXT: v_mov_b32_e32 v0, s10 ; GFX90a-NEXT: v_mov_b32_e32 v1, s11 @@ -512,7 +512,7 @@ define amdgpu_kernel void @preload_block_count_xyz(ptr addrspace(1) inreg %out) ; ; GFX1250-LABEL: preload_block_count_xyz: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, s4 ; GFX1250-NEXT: v_dual_mov_b32 v1, s5 :: v_dual_mov_b32 v2, s6 ; GFX1250-NEXT: global_store_b96 v3, v[0:2], s[2:3] @@ -533,14 +533,14 @@ define amdgpu_kernel void @preload_block_count_xyz(ptr addrspace(1) inreg %out) define amdgpu_kernel void @preload_workgroup_size_x(ptr addrspace(1) inreg %out) #0 { ; GFX942-LABEL: preload_workgroup_size_x: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB12_0 +; GFX942-NEXT: s_branch .LBB12_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB12_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB12_2: ; GFX942-NEXT: s_and_b32 s0, s7, 0xffff ; GFX942-NEXT: v_mov_b32_e32 v0, 0 ; GFX942-NEXT: v_mov_b32_e32 v1, s0 @@ -548,14 +548,14 @@ define amdgpu_kernel void @preload_workgroup_size_x(ptr addrspace(1) inreg %out) ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: preload_workgroup_size_x: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 ; GFX90a-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB12_0 +; GFX90a-NEXT: s_branch .LBB12_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB12_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB12_2: ; GFX90a-NEXT: s_and_b32 s0, s13, 0xffff ; GFX90a-NEXT: v_mov_b32_e32 v0, 0 ; GFX90a-NEXT: v_mov_b32_e32 v1, s0 @@ -564,7 +564,7 @@ define amdgpu_kernel void @preload_workgroup_size_x(ptr addrspace(1) inreg %out) ; ; GFX1250-LABEL: preload_workgroup_size_x: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: s_and_b32 s0, s7, 0xffff ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0 @@ -580,14 +580,14 @@ define amdgpu_kernel void @preload_workgroup_size_x(ptr addrspace(1) inreg %out) define amdgpu_kernel void @preload_workgroup_size_y(ptr addrspace(1) inreg %out) #0 { ; GFX942-LABEL: preload_workgroup_size_y: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB13_0 +; GFX942-NEXT: s_branch .LBB13_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB13_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB13_2: ; GFX942-NEXT: s_lshr_b32 s0, s7, 16 ; GFX942-NEXT: v_mov_b32_e32 v0, 0 ; GFX942-NEXT: v_mov_b32_e32 v1, s0 @@ -595,14 +595,14 @@ define amdgpu_kernel void @preload_workgroup_size_y(ptr addrspace(1) inreg %out) ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: preload_workgroup_size_y: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 ; GFX90a-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB13_0 +; GFX90a-NEXT: s_branch .LBB13_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB13_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB13_2: ; GFX90a-NEXT: s_lshr_b32 s0, s13, 16 ; GFX90a-NEXT: v_mov_b32_e32 v0, 0 ; GFX90a-NEXT: v_mov_b32_e32 v1, s0 @@ -611,7 +611,7 @@ define amdgpu_kernel void @preload_workgroup_size_y(ptr addrspace(1) inreg %out) ; ; GFX1250-LABEL: preload_workgroup_size_y: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: s_lshr_b32 s0, s7, 16 ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0 @@ -627,15 +627,15 @@ define amdgpu_kernel void @preload_workgroup_size_y(ptr addrspace(1) inreg %out) define amdgpu_kernel void @preload_workgroup_size_z(ptr addrspace(1) inreg %out) #0 { ; GFX942-LABEL: preload_workgroup_size_z: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8 ; GFX942-NEXT: s_load_dword s8, s[0:1], 0x18 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB14_0 +; GFX942-NEXT: s_branch .LBB14_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB14_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB14_2: ; GFX942-NEXT: s_and_b32 s0, s8, 0xffff ; GFX942-NEXT: v_mov_b32_e32 v0, 0 ; GFX942-NEXT: v_mov_b32_e32 v1, s0 @@ -643,15 +643,15 @@ define amdgpu_kernel void @preload_workgroup_size_z(ptr addrspace(1) inreg %out) ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: preload_workgroup_size_z: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 ; GFX90a-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10 ; GFX90a-NEXT: s_load_dword s14, s[4:5], 0x18 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB14_0 +; GFX90a-NEXT: s_branch .LBB14_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB14_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB14_2: ; GFX90a-NEXT: s_and_b32 s0, s14, 0xffff ; GFX90a-NEXT: v_mov_b32_e32 v0, 0 ; GFX90a-NEXT: v_mov_b32_e32 v1, s0 @@ -660,7 +660,7 @@ define amdgpu_kernel void @preload_workgroup_size_z(ptr addrspace(1) inreg %out) ; ; GFX1250-LABEL: preload_workgroup_size_z: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: s_and_b32 s0, s8, 0xffff ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0 @@ -676,15 +676,15 @@ define amdgpu_kernel void @preload_workgroup_size_z(ptr addrspace(1) inreg %out) define amdgpu_kernel void @preload_workgroup_size_xyz(ptr addrspace(1) inreg %out) #0 { ; GFX942-LABEL: preload_workgroup_size_xyz: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8 ; GFX942-NEXT: s_load_dword s8, s[0:1], 0x18 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB15_0 +; GFX942-NEXT: s_branch .LBB15_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB15_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB15_2: ; GFX942-NEXT: s_lshr_b32 s0, s7, 16 ; GFX942-NEXT: s_and_b32 s1, s7, 0xffff ; GFX942-NEXT: s_and_b32 s4, s8, 0xffff @@ -696,15 +696,15 @@ define amdgpu_kernel void @preload_workgroup_size_xyz(ptr addrspace(1) inreg %ou ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: preload_workgroup_size_xyz: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 ; GFX90a-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10 ; GFX90a-NEXT: s_load_dword s14, s[4:5], 0x18 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB15_0 +; GFX90a-NEXT: s_branch .LBB15_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB15_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB15_2: ; GFX90a-NEXT: s_lshr_b32 s0, s13, 16 ; GFX90a-NEXT: s_and_b32 s1, s13, 0xffff ; GFX90a-NEXT: s_and_b32 s2, s14, 0xffff @@ -717,7 +717,7 @@ define amdgpu_kernel void @preload_workgroup_size_xyz(ptr addrspace(1) inreg %ou ; ; GFX1250-LABEL: preload_workgroup_size_xyz: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: s_lshr_b32 s0, s7, 16 ; GFX1250-NEXT: s_and_b32 s1, s7, 0xffff ; GFX1250-NEXT: s_and_b32 s4, s8, 0xffff @@ -744,15 +744,15 @@ define amdgpu_kernel void @preload_workgroup_size_xyz(ptr addrspace(1) inreg %ou define amdgpu_kernel void @preload_remainder_x(ptr addrspace(1) inreg %out) #0 { ; GFX942-LABEL: preload_remainder_x: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8 ; GFX942-NEXT: s_load_dword s8, s[0:1], 0x18 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB16_0 +; GFX942-NEXT: s_branch .LBB16_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB16_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB16_2: ; GFX942-NEXT: s_lshr_b32 s0, s8, 16 ; GFX942-NEXT: v_mov_b32_e32 v0, 0 ; GFX942-NEXT: v_mov_b32_e32 v1, s0 @@ -760,15 +760,15 @@ define amdgpu_kernel void @preload_remainder_x(ptr addrspace(1) inreg %out) #0 { ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: preload_remainder_x: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 ; GFX90a-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10 ; GFX90a-NEXT: s_load_dword s14, s[4:5], 0x18 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB16_0 +; GFX90a-NEXT: s_branch .LBB16_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB16_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB16_2: ; GFX90a-NEXT: s_lshr_b32 s0, s14, 16 ; GFX90a-NEXT: v_mov_b32_e32 v0, 0 ; GFX90a-NEXT: v_mov_b32_e32 v1, s0 @@ -777,7 +777,7 @@ define amdgpu_kernel void @preload_remainder_x(ptr addrspace(1) inreg %out) #0 { ; ; GFX1250-LABEL: preload_remainder_x: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: s_lshr_b32 s0, s8, 16 ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0 @@ -793,15 +793,15 @@ define amdgpu_kernel void @preload_remainder_x(ptr addrspace(1) inreg %out) #0 { define amdgpu_kernel void @preloadremainder_y(ptr addrspace(1) inreg %out) #0 { ; GFX942-LABEL: preloadremainder_y: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8 ; GFX942-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB17_0 +; GFX942-NEXT: s_branch .LBB17_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB17_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB17_2: ; GFX942-NEXT: s_and_b32 s0, s9, 0xffff ; GFX942-NEXT: v_mov_b32_e32 v0, 0 ; GFX942-NEXT: v_mov_b32_e32 v1, s0 @@ -809,13 +809,13 @@ define amdgpu_kernel void @preloadremainder_y(ptr addrspace(1) inreg %out) #0 { ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: preloadremainder_y: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB17_0 +; GFX90a-NEXT: s_branch .LBB17_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB17_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB17_2: ; GFX90a-NEXT: s_and_b32 s0, s15, 0xffff ; GFX90a-NEXT: v_mov_b32_e32 v0, 0 ; GFX90a-NEXT: v_mov_b32_e32 v1, s0 @@ -824,7 +824,7 @@ define amdgpu_kernel void @preloadremainder_y(ptr addrspace(1) inreg %out) #0 { ; ; GFX1250-LABEL: preloadremainder_y: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: s_and_b32 s0, s9, 0xffff ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0 @@ -840,15 +840,15 @@ define amdgpu_kernel void @preloadremainder_y(ptr addrspace(1) inreg %out) #0 { define amdgpu_kernel void @preloadremainder_z(ptr addrspace(1) inreg %out) #0 { ; GFX942-LABEL: preloadremainder_z: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8 ; GFX942-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB18_0 +; GFX942-NEXT: s_branch .LBB18_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB18_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB18_2: ; GFX942-NEXT: s_lshr_b32 s0, s9, 16 ; GFX942-NEXT: v_mov_b32_e32 v0, 0 ; GFX942-NEXT: v_mov_b32_e32 v1, s0 @@ -856,13 +856,13 @@ define amdgpu_kernel void @preloadremainder_z(ptr addrspace(1) inreg %out) #0 { ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: preloadremainder_z: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB18_0 +; GFX90a-NEXT: s_branch .LBB18_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB18_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB18_2: ; GFX90a-NEXT: s_lshr_b32 s0, s15, 16 ; GFX90a-NEXT: v_mov_b32_e32 v0, 0 ; GFX90a-NEXT: v_mov_b32_e32 v1, s0 @@ -871,7 +871,7 @@ define amdgpu_kernel void @preloadremainder_z(ptr addrspace(1) inreg %out) #0 { ; ; GFX1250-LABEL: preloadremainder_z: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: s_lshr_b32 s0, s9, 16 ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0 @@ -887,15 +887,15 @@ define amdgpu_kernel void @preloadremainder_z(ptr addrspace(1) inreg %out) #0 { define amdgpu_kernel void @preloadremainder_xyz(ptr addrspace(1) inreg %out) #0 { ; GFX942-LABEL: preloadremainder_xyz: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8 ; GFX942-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB19_0 +; GFX942-NEXT: s_branch .LBB19_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB19_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB19_2: ; GFX942-NEXT: s_lshr_b32 s0, s9, 16 ; GFX942-NEXT: s_lshr_b32 s1, s8, 16 ; GFX942-NEXT: s_and_b32 s4, s9, 0xffff @@ -907,13 +907,13 @@ define amdgpu_kernel void @preloadremainder_xyz(ptr addrspace(1) inreg %out) #0 ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: preloadremainder_xyz: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB19_0 +; GFX90a-NEXT: s_branch .LBB19_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB19_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB19_2: ; GFX90a-NEXT: s_lshr_b32 s0, s15, 16 ; GFX90a-NEXT: s_lshr_b32 s1, s14, 16 ; GFX90a-NEXT: s_and_b32 s2, s15, 0xffff @@ -926,7 +926,7 @@ define amdgpu_kernel void @preloadremainder_xyz(ptr addrspace(1) inreg %out) #0 ; ; GFX1250-LABEL: preloadremainder_xyz: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: s_lshr_b32 s0, s9, 16 ; GFX1250-NEXT: s_lshr_b32 s1, s8, 16 ; GFX1250-NEXT: s_and_b32 s4, s9, 0xffff @@ -953,13 +953,13 @@ define amdgpu_kernel void @preloadremainder_xyz(ptr addrspace(1) inreg %out) #0 define amdgpu_kernel void @no_free_sgprs_preloadremainder_z(ptr addrspace(1) inreg %out) { ; GFX942-LABEL: no_free_sgprs_preloadremainder_z: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB20_0 +; GFX942-NEXT: s_branch .LBB20_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB20_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB20_2: ; GFX942-NEXT: s_lshr_b32 s0, s15, 16 ; GFX942-NEXT: v_mov_b32_e32 v0, 0 ; GFX942-NEXT: v_mov_b32_e32 v1, s0 @@ -967,13 +967,13 @@ define amdgpu_kernel void @no_free_sgprs_preloadremainder_z(ptr addrspace(1) inr ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: no_free_sgprs_preloadremainder_z: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx2 s[14:15], s[8:9], 0x0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB20_0 +; GFX90a-NEXT: s_branch .LBB20_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB20_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB20_2: ; GFX90a-NEXT: s_load_dword s0, s[8:9], 0x1c ; GFX90a-NEXT: v_mov_b32_e32 v0, 0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) @@ -984,7 +984,7 @@ define amdgpu_kernel void @no_free_sgprs_preloadremainder_z(ptr addrspace(1) inr ; ; GFX1250-LABEL: no_free_sgprs_preloadremainder_z: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: s_lshr_b32 s0, s15, 16 ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0 @@ -1002,28 +1002,28 @@ define amdgpu_kernel void @no_free_sgprs_preloadremainder_z(ptr addrspace(1) inr define amdgpu_kernel void @preload_block_max_user_sgprs(ptr addrspace(1) inreg %out, i192 inreg %t0, i32 inreg %t1) #0 { ; GFX942-LABEL: preload_block_max_user_sgprs: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x8 ; GFX942-NEXT: s_load_dword s12, s[0:1], 0x28 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB21_0 +; GFX942-NEXT: s_branch .LBB21_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB21_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB21_2: ; GFX942-NEXT: v_mov_b32_e32 v0, 0 ; GFX942-NEXT: v_mov_b32_e32 v1, s12 ; GFX942-NEXT: global_store_dword v0, v1, s[2:3] ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: preload_block_max_user_sgprs: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB21_0 +; GFX90a-NEXT: s_branch .LBB21_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB21_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB21_2: ; GFX90a-NEXT: s_load_dword s0, s[4:5], 0x28 ; GFX90a-NEXT: v_mov_b32_e32 v0, 0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) @@ -1033,7 +1033,7 @@ define amdgpu_kernel void @preload_block_max_user_sgprs(ptr addrspace(1) inreg % ; ; GFX1250-LABEL: preload_block_max_user_sgprs: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s12 ; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3] ; GFX1250-NEXT: s_endpgm @@ -1045,15 +1045,15 @@ define amdgpu_kernel void @preload_block_max_user_sgprs(ptr addrspace(1) inreg % define amdgpu_kernel void @preload_block_count_z_workgroup_size_z_remainder_z(ptr addrspace(1) inreg %out) #0 { ; GFX942-LABEL: preload_block_count_z_workgroup_size_z_remainder_z: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8 ; GFX942-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB22_0 +; GFX942-NEXT: s_branch .LBB22_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB22_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB22_2: ; GFX942-NEXT: s_lshr_b32 s0, s9, 16 ; GFX942-NEXT: s_and_b32 s1, s8, 0xffff ; GFX942-NEXT: v_mov_b32_e32 v3, 0 @@ -1064,13 +1064,13 @@ define amdgpu_kernel void @preload_block_count_z_workgroup_size_z_remainder_z(pt ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: preload_block_count_z_workgroup_size_z_remainder_z: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB22_0 +; GFX90a-NEXT: s_branch .LBB22_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB22_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB22_2: ; GFX90a-NEXT: s_lshr_b32 s0, s15, 16 ; GFX90a-NEXT: s_and_b32 s1, s14, 0xffff ; GFX90a-NEXT: v_mov_b32_e32 v3, 0 @@ -1082,7 +1082,7 @@ define amdgpu_kernel void @preload_block_count_z_workgroup_size_z_remainder_z(pt ; ; GFX1250-LABEL: preload_block_count_z_workgroup_size_z_remainder_z: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: s_lshr_b32 s0, s9, 16 ; GFX1250-NEXT: s_and_b32 s1, s8, 0xffff ; GFX1250-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, s6 diff --git a/llvm/test/CodeGen/AMDGPU/preload-kernarg-header.ll b/llvm/test/CodeGen/AMDGPU/preload-kernarg-header.ll index 84aa948ac11b3..ad76f385f7e6d 100644 --- a/llvm/test/CodeGen/AMDGPU/preload-kernarg-header.ll +++ b/llvm/test/CodeGen/AMDGPU/preload-kernarg-header.ll @@ -9,9 +9,9 @@ define amdgpu_kernel void @preload_ptr_kernarg_header(ptr inreg %arg) { ; ASM-LABEL: preload_ptr_kernarg_header: ; ASM: s_load_dwordx2 s[8:9], s[4:5], 0x0 ; ASM-NEXT: s_waitcnt lgkmcnt(0) -; ASM-NEXT: s_branch .LBB0_0 +; ASM-NEXT: s_branch .LBB0_2 ; ASM-NEXT: .p2align 8 -; ASM-NEXT: .LBB0_0: +; ASM-NEXT: .LBB0_2: ; ASM-NEXT: v_mov_b64_e32 v[0:1], s[8:9] ; ASM-NEXT: v_mov_b64_e32 v[2:3], s[8:9] ; ASM-NEXT: flat_store_dwordx2 v[0:1], v[2:3] @@ -27,9 +27,9 @@ define amdgpu_kernel void @preload_i32_kernarg_header(ptr inreg %arg, i32 inreg ; ASM: s_load_dwordx2 s[8:9], s[4:5], 0x0 ; ASM-NEXT: s_load_dword s10, s[4:5], 0x8 ; ASM-NEXT: s_waitcnt lgkmcnt(0) -; ASM-NEXT: s_branch .LBB1_0 +; ASM-NEXT: s_branch .LBB1_2 ; ASM-NEXT: .p2align 8 -; ASM-NEXT: .LBB1_0: +; ASM-NEXT: .LBB1_2: ; ASM-NEXT: v_mov_b64_e32 v[0:1], s[8:9] ; ASM-NEXT: v_mov_b32_e32 v2, s10 ; ASM-NEXT: flat_store_dword v[0:1], v2 diff --git a/llvm/test/CodeGen/AMDGPU/preload-kernargs.ll b/llvm/test/CodeGen/AMDGPU/preload-kernargs.ll index f899450e383a7..1f257eb5b3224 100644 --- a/llvm/test/CodeGen/AMDGPU/preload-kernargs.ll +++ b/llvm/test/CodeGen/AMDGPU/preload-kernargs.ll @@ -5,14 +5,14 @@ define amdgpu_kernel void @ptr1_i8(ptr addrspace(1) inreg %out, i8 inreg %arg0) #0 { ; GFX942-LABEL: ptr1_i8: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dword s4, s[0:1], 0x8 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB0_0 +; GFX942-NEXT: s_branch .LBB0_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB0_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB0_2: ; GFX942-NEXT: s_and_b32 s0, s4, 0xff ; GFX942-NEXT: v_mov_b32_e32 v0, 0 ; GFX942-NEXT: v_mov_b32_e32 v1, s0 @@ -20,14 +20,14 @@ define amdgpu_kernel void @ptr1_i8(ptr addrspace(1) inreg %out, i8 inreg %arg0) ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: ptr1_i8: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0 ; GFX90a-NEXT: s_load_dword s10, s[4:5], 0x8 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB0_0 +; GFX90a-NEXT: s_branch .LBB0_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB0_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB0_2: ; GFX90a-NEXT: s_and_b32 s0, s10, 0xff ; GFX90a-NEXT: v_mov_b32_e32 v0, 0 ; GFX90a-NEXT: v_mov_b32_e32 v1, s0 @@ -36,7 +36,7 @@ define amdgpu_kernel void @ptr1_i8(ptr addrspace(1) inreg %out, i8 inreg %arg0) ; ; GFX1250-LABEL: ptr1_i8: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: s_and_b32 s0, s4, 0xff ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0 @@ -49,14 +49,14 @@ define amdgpu_kernel void @ptr1_i8(ptr addrspace(1) inreg %out, i8 inreg %arg0) define amdgpu_kernel void @ptr1_i8_zext_arg(ptr addrspace(1) inreg %out, i8 zeroext inreg %arg0) #0 { ; GFX942-LABEL: ptr1_i8_zext_arg: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dword s4, s[0:1], 0x8 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB1_0 +; GFX942-NEXT: s_branch .LBB1_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB1_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB1_2: ; GFX942-NEXT: s_and_b32 s0, s4, 0xff ; GFX942-NEXT: v_mov_b32_e32 v0, 0 ; GFX942-NEXT: v_mov_b32_e32 v1, s0 @@ -64,14 +64,14 @@ define amdgpu_kernel void @ptr1_i8_zext_arg(ptr addrspace(1) inreg %out, i8 zero ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: ptr1_i8_zext_arg: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0 ; GFX90a-NEXT: s_load_dword s10, s[4:5], 0x8 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB1_0 +; GFX90a-NEXT: s_branch .LBB1_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB1_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB1_2: ; GFX90a-NEXT: s_and_b32 s0, s10, 0xff ; GFX90a-NEXT: v_mov_b32_e32 v0, 0 ; GFX90a-NEXT: v_mov_b32_e32 v1, s0 @@ -80,7 +80,7 @@ define amdgpu_kernel void @ptr1_i8_zext_arg(ptr addrspace(1) inreg %out, i8 zero ; ; GFX1250-LABEL: ptr1_i8_zext_arg: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: s_and_b32 s0, s4, 0xff ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0 @@ -93,14 +93,14 @@ define amdgpu_kernel void @ptr1_i8_zext_arg(ptr addrspace(1) inreg %out, i8 zero define amdgpu_kernel void @ptr1_i16_preload_arg(ptr addrspace(1) inreg %out, i16 inreg %arg0) #0 { ; GFX942-LABEL: ptr1_i16_preload_arg: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dword s4, s[0:1], 0x8 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB2_0 +; GFX942-NEXT: s_branch .LBB2_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB2_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB2_2: ; GFX942-NEXT: s_and_b32 s0, s4, 0xffff ; GFX942-NEXT: v_mov_b32_e32 v0, 0 ; GFX942-NEXT: v_mov_b32_e32 v1, s0 @@ -108,14 +108,14 @@ define amdgpu_kernel void @ptr1_i16_preload_arg(ptr addrspace(1) inreg %out, i16 ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: ptr1_i16_preload_arg: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0 ; GFX90a-NEXT: s_load_dword s10, s[4:5], 0x8 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB2_0 +; GFX90a-NEXT: s_branch .LBB2_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB2_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB2_2: ; GFX90a-NEXT: s_and_b32 s0, s10, 0xffff ; GFX90a-NEXT: v_mov_b32_e32 v0, 0 ; GFX90a-NEXT: v_mov_b32_e32 v1, s0 @@ -124,7 +124,7 @@ define amdgpu_kernel void @ptr1_i16_preload_arg(ptr addrspace(1) inreg %out, i16 ; ; GFX1250-LABEL: ptr1_i16_preload_arg: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: s_and_b32 s0, s4, 0xffff ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0 @@ -137,28 +137,28 @@ define amdgpu_kernel void @ptr1_i16_preload_arg(ptr addrspace(1) inreg %out, i16 define amdgpu_kernel void @ptr1_i32_preload_arg(ptr addrspace(1) inreg %out, i32 inreg %arg0) #0 { ; GFX942-LABEL: ptr1_i32_preload_arg: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dword s4, s[0:1], 0x8 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB3_0 +; GFX942-NEXT: s_branch .LBB3_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB3_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB3_2: ; GFX942-NEXT: v_mov_b32_e32 v0, 0 ; GFX942-NEXT: v_mov_b32_e32 v1, s4 ; GFX942-NEXT: global_store_dword v0, v1, s[2:3] ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: ptr1_i32_preload_arg: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0 ; GFX90a-NEXT: s_load_dword s10, s[4:5], 0x8 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB3_0 +; GFX90a-NEXT: s_branch .LBB3_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB3_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB3_2: ; GFX90a-NEXT: v_mov_b32_e32 v0, 0 ; GFX90a-NEXT: v_mov_b32_e32 v1, s10 ; GFX90a-NEXT: global_store_dword v0, v1, s[8:9] @@ -166,7 +166,7 @@ define amdgpu_kernel void @ptr1_i32_preload_arg(ptr addrspace(1) inreg %out, i32 ; ; GFX1250-LABEL: ptr1_i32_preload_arg: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4 ; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3] ; GFX1250-NEXT: s_endpgm @@ -177,15 +177,15 @@ define amdgpu_kernel void @ptr1_i32_preload_arg(ptr addrspace(1) inreg %out, i32 define amdgpu_kernel void @i32_ptr1_i32_preload_arg(i32 inreg %arg0, ptr addrspace(1) inreg %out, i32 inreg %arg1) #0 { ; GFX942-LABEL: i32_ptr1_i32_preload_arg: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8 ; GFX942-NEXT: s_load_dword s6, s[0:1], 0x10 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB4_0 +; GFX942-NEXT: s_branch .LBB4_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB4_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB4_2: ; GFX942-NEXT: s_add_i32 s0, s2, s6 ; GFX942-NEXT: v_mov_b32_e32 v0, 0 ; GFX942-NEXT: v_mov_b32_e32 v1, s0 @@ -193,14 +193,14 @@ define amdgpu_kernel void @i32_ptr1_i32_preload_arg(i32 inreg %arg0, ptr addrspa ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: i32_ptr1_i32_preload_arg: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 ; GFX90a-NEXT: s_load_dword s12, s[4:5], 0x10 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB4_0 +; GFX90a-NEXT: s_branch .LBB4_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB4_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB4_2: ; GFX90a-NEXT: s_add_i32 s0, s8, s12 ; GFX90a-NEXT: v_mov_b32_e32 v0, 0 ; GFX90a-NEXT: v_mov_b32_e32 v1, s0 @@ -209,7 +209,7 @@ define amdgpu_kernel void @i32_ptr1_i32_preload_arg(i32 inreg %arg0, ptr addrspa ; ; GFX1250-LABEL: i32_ptr1_i32_preload_arg: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: s_add_co_i32 s0, s2, s6 ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0 @@ -222,14 +222,14 @@ define amdgpu_kernel void @i32_ptr1_i32_preload_arg(i32 inreg %arg0, ptr addrspa define amdgpu_kernel void @ptr1_i16_i16_preload_arg(ptr addrspace(1) inreg %out, i16 inreg %arg0, i16 inreg %arg1) #0 { ; GFX942-LABEL: ptr1_i16_i16_preload_arg: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dword s4, s[0:1], 0x8 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB5_0 +; GFX942-NEXT: s_branch .LBB5_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB5_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB5_2: ; GFX942-NEXT: s_lshr_b32 s0, s4, 16 ; GFX942-NEXT: s_and_b32 s1, s4, 0xffff ; GFX942-NEXT: s_add_i32 s0, s1, s0 @@ -239,14 +239,14 @@ define amdgpu_kernel void @ptr1_i16_i16_preload_arg(ptr addrspace(1) inreg %out, ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: ptr1_i16_i16_preload_arg: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0 ; GFX90a-NEXT: s_load_dword s10, s[4:5], 0x8 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB5_0 +; GFX90a-NEXT: s_branch .LBB5_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB5_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB5_2: ; GFX90a-NEXT: s_lshr_b32 s0, s10, 16 ; GFX90a-NEXT: s_and_b32 s1, s10, 0xffff ; GFX90a-NEXT: s_add_i32 s0, s1, s0 @@ -257,7 +257,7 @@ define amdgpu_kernel void @ptr1_i16_i16_preload_arg(ptr addrspace(1) inreg %out, ; ; GFX1250-LABEL: ptr1_i16_i16_preload_arg: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: s_lshr_b32 s0, s4, 16 ; GFX1250-NEXT: s_and_b32 s1, s4, 0xffff ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) @@ -274,28 +274,28 @@ define amdgpu_kernel void @ptr1_i16_i16_preload_arg(ptr addrspace(1) inreg %out, define amdgpu_kernel void @ptr1_v2i8_preload_arg(ptr addrspace(1) inreg %out, <2 x i8> inreg %in) #0 { ; GFX942-LABEL: ptr1_v2i8_preload_arg: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dword s4, s[0:1], 0x8 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB6_0 +; GFX942-NEXT: s_branch .LBB6_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB6_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB6_2: ; GFX942-NEXT: v_mov_b32_e32 v0, 0 ; GFX942-NEXT: v_mov_b32_e32 v1, s4 ; GFX942-NEXT: global_store_short v0, v1, s[2:3] ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: ptr1_v2i8_preload_arg: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0 ; GFX90a-NEXT: s_load_dword s10, s[4:5], 0x8 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB6_0 +; GFX90a-NEXT: s_branch .LBB6_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB6_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB6_2: ; GFX90a-NEXT: v_mov_b32_e32 v0, 0 ; GFX90a-NEXT: v_mov_b32_e32 v1, s10 ; GFX90a-NEXT: global_store_short v0, v1, s[8:9] @@ -303,7 +303,7 @@ define amdgpu_kernel void @ptr1_v2i8_preload_arg(ptr addrspace(1) inreg %out, <2 ; ; GFX1250-LABEL: ptr1_v2i8_preload_arg: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4 ; GFX1250-NEXT: global_store_b16 v0, v1, s[2:3] ; GFX1250-NEXT: s_endpgm @@ -314,13 +314,13 @@ define amdgpu_kernel void @ptr1_v2i8_preload_arg(ptr addrspace(1) inreg %out, <2 define amdgpu_kernel void @byref_preload_arg(ptr addrspace(1) inreg %out, ptr addrspace(4) byref(i32) align(256) %in.byref, i32 %after.offset) #0 { ; GFX942-LABEL: byref_preload_arg: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB7_0 +; GFX942-NEXT: s_branch .LBB7_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB7_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB7_2: ; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x100 ; GFX942-NEXT: v_mov_b32_e32 v0, 0 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) @@ -333,13 +333,13 @@ define amdgpu_kernel void @byref_preload_arg(ptr addrspace(1) inreg %out, ptr ad ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: byref_preload_arg: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB7_0 +; GFX90a-NEXT: s_branch .LBB7_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB7_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB7_2: ; GFX90a-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x100 ; GFX90a-NEXT: v_mov_b32_e32 v0, 0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) @@ -353,8 +353,8 @@ define amdgpu_kernel void @byref_preload_arg(ptr addrspace(1) inreg %out, ptr ad ; ; GFX1250-LABEL: byref_preload_arg: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 -; GFX1250-NEXT: s_load_b64 s[4:5], s[0:1], 0x100 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 +; GFX1250-NEXT: s_load_b64 s[4:5], s[0:1], 0x100 nv ; GFX1250-NEXT: s_wait_kmcnt 0x0 ; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4 ; GFX1250-NEXT: v_mov_b32_e32 v2, s5 @@ -374,13 +374,13 @@ define amdgpu_kernel void @byref_preload_arg(ptr addrspace(1) inreg %out, ptr ad define amdgpu_kernel void @byref_staggered_preload_arg(ptr addrspace(1) inreg %out, ptr addrspace(4) byref(i32) align(256) %in.byref, i32 inreg %after.offset) #0 { ; GFX942-LABEL: byref_staggered_preload_arg: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB8_0 +; GFX942-NEXT: s_branch .LBB8_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB8_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB8_2: ; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x100 ; GFX942-NEXT: v_mov_b32_e32 v0, 0 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) @@ -393,13 +393,13 @@ define amdgpu_kernel void @byref_staggered_preload_arg(ptr addrspace(1) inreg %o ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: byref_staggered_preload_arg: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB8_0 +; GFX90a-NEXT: s_branch .LBB8_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB8_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB8_2: ; GFX90a-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x100 ; GFX90a-NEXT: v_mov_b32_e32 v0, 0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) @@ -413,8 +413,8 @@ define amdgpu_kernel void @byref_staggered_preload_arg(ptr addrspace(1) inreg %o ; ; GFX1250-LABEL: byref_staggered_preload_arg: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 -; GFX1250-NEXT: s_load_b64 s[4:5], s[0:1], 0x100 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 +; GFX1250-NEXT: s_load_b64 s[4:5], s[0:1], 0x100 nv ; GFX1250-NEXT: s_wait_kmcnt 0x0 ; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4 ; GFX1250-NEXT: v_mov_b32_e32 v2, s5 @@ -433,13 +433,13 @@ define amdgpu_kernel void @byref_staggered_preload_arg(ptr addrspace(1) inreg %o define amdgpu_kernel void @v8i32_arg(ptr addrspace(1) nocapture inreg %out, <8 x i32> inreg %in) #0 { ; GFX942-LABEL: v8i32_arg: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB9_0 +; GFX942-NEXT: s_branch .LBB9_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB9_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB9_2: ; GFX942-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x20 ; GFX942-NEXT: v_mov_b32_e32 v4, 0 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) @@ -457,13 +457,13 @@ define amdgpu_kernel void @v8i32_arg(ptr addrspace(1) nocapture inreg %out, <8 x ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: v8i32_arg: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB9_0 +; GFX90a-NEXT: s_branch .LBB9_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB9_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB9_2: ; GFX90a-NEXT: s_load_dwordx8 s[12:19], s[4:5], 0x20 ; GFX90a-NEXT: v_mov_b32_e32 v4, 0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) @@ -482,7 +482,7 @@ define amdgpu_kernel void @v8i32_arg(ptr addrspace(1) nocapture inreg %out, <8 x ; ; GFX1250-LABEL: v8i32_arg: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v0, s14 ; GFX1250-NEXT: v_dual_mov_b32 v1, s15 :: v_dual_mov_b32 v2, s16 ; GFX1250-NEXT: v_dual_mov_b32 v3, s17 :: v_dual_mov_b32 v4, s10 @@ -498,14 +498,14 @@ define amdgpu_kernel void @v8i32_arg(ptr addrspace(1) nocapture inreg %out, <8 x define amdgpu_kernel void @v3i16_preload_arg(ptr addrspace(1) nocapture inreg %out, <3 x i16> inreg %in) #0 { ; GFX942-LABEL: v3i16_preload_arg: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB10_0 +; GFX942-NEXT: s_branch .LBB10_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB10_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB10_2: ; GFX942-NEXT: v_mov_b32_e32 v0, 0 ; GFX942-NEXT: v_mov_b32_e32 v1, s5 ; GFX942-NEXT: global_store_short v0, v1, s[2:3] offset:4 @@ -514,13 +514,13 @@ define amdgpu_kernel void @v3i16_preload_arg(ptr addrspace(1) nocapture inreg %o ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: v3i16_preload_arg: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB10_0 +; GFX90a-NEXT: s_branch .LBB10_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB10_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB10_2: ; GFX90a-NEXT: v_mov_b32_e32 v0, 0 ; GFX90a-NEXT: v_mov_b32_e32 v1, s11 ; GFX90a-NEXT: global_store_short v0, v1, s[8:9] offset:4 @@ -530,7 +530,7 @@ define amdgpu_kernel void @v3i16_preload_arg(ptr addrspace(1) nocapture inreg %o ; ; GFX1250-LABEL: v3i16_preload_arg: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s5 ; GFX1250-NEXT: v_mov_b32_e32 v2, s4 ; GFX1250-NEXT: s_clause 0x1 @@ -543,15 +543,15 @@ define amdgpu_kernel void @v3i16_preload_arg(ptr addrspace(1) nocapture inreg %o define amdgpu_kernel void @v3i32_preload_arg(ptr addrspace(1) nocapture inreg %out, <3 x i32> inreg %in) #0 { ; GFX942-LABEL: v3i32_preload_arg: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8 ; GFX942-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB11_0 +; GFX942-NEXT: s_branch .LBB11_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB11_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB11_2: ; GFX942-NEXT: v_mov_b32_e32 v0, s6 ; GFX942-NEXT: v_mov_b32_e32 v1, s7 ; GFX942-NEXT: v_mov_b32_e32 v2, s8 @@ -560,13 +560,13 @@ define amdgpu_kernel void @v3i32_preload_arg(ptr addrspace(1) nocapture inreg %o ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: v3i32_preload_arg: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB11_0 +; GFX90a-NEXT: s_branch .LBB11_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB11_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB11_2: ; GFX90a-NEXT: v_mov_b32_e32 v0, s12 ; GFX90a-NEXT: v_mov_b32_e32 v1, s13 ; GFX90a-NEXT: v_mov_b32_e32 v2, s14 @@ -576,7 +576,7 @@ define amdgpu_kernel void @v3i32_preload_arg(ptr addrspace(1) nocapture inreg %o ; ; GFX1250-LABEL: v3i32_preload_arg: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7 ; GFX1250-NEXT: v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v3, 0 ; GFX1250-NEXT: global_store_b96 v3, v[0:2], s[2:3] @@ -587,15 +587,15 @@ define amdgpu_kernel void @v3i32_preload_arg(ptr addrspace(1) nocapture inreg %o define amdgpu_kernel void @v3f32_preload_arg(ptr addrspace(1) nocapture inreg %out, <3 x float> inreg %in) #0 { ; GFX942-LABEL: v3f32_preload_arg: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8 ; GFX942-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB12_0 +; GFX942-NEXT: s_branch .LBB12_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB12_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB12_2: ; GFX942-NEXT: v_mov_b32_e32 v3, 0 ; GFX942-NEXT: v_mov_b32_e32 v0, s6 ; GFX942-NEXT: v_mov_b32_e32 v1, s7 @@ -604,13 +604,13 @@ define amdgpu_kernel void @v3f32_preload_arg(ptr addrspace(1) nocapture inreg %o ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: v3f32_preload_arg: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB12_0 +; GFX90a-NEXT: s_branch .LBB12_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB12_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB12_2: ; GFX90a-NEXT: v_mov_b32_e32 v3, 0 ; GFX90a-NEXT: v_mov_b32_e32 v0, s12 ; GFX90a-NEXT: v_mov_b32_e32 v1, s13 @@ -620,7 +620,7 @@ define amdgpu_kernel void @v3f32_preload_arg(ptr addrspace(1) nocapture inreg %o ; ; GFX1250-LABEL: v3f32_preload_arg: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, s6 ; GFX1250-NEXT: v_dual_mov_b32 v1, s7 :: v_dual_mov_b32 v2, s8 ; GFX1250-NEXT: global_store_b96 v3, v[0:2], s[2:3] @@ -631,14 +631,14 @@ define amdgpu_kernel void @v3f32_preload_arg(ptr addrspace(1) nocapture inreg %o define amdgpu_kernel void @v5i8_preload_arg(ptr addrspace(1) nocapture inreg %out, <5 x i8> inreg %in) #0 { ; GFX942-LABEL: v5i8_preload_arg: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB13_0 +; GFX942-NEXT: s_branch .LBB13_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB13_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB13_2: ; GFX942-NEXT: s_lshr_b32 s1, s4, 24 ; GFX942-NEXT: s_and_b32 s0, s4, 0xffff ; GFX942-NEXT: s_lshl_b32 s1, s1, 8 @@ -654,13 +654,13 @@ define amdgpu_kernel void @v5i8_preload_arg(ptr addrspace(1) nocapture inreg %ou ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: v5i8_preload_arg: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB13_0 +; GFX90a-NEXT: s_branch .LBB13_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB13_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB13_2: ; GFX90a-NEXT: s_lshr_b32 s1, s10, 24 ; GFX90a-NEXT: s_lshl_b32 s1, s1, 8 ; GFX90a-NEXT: s_bfe_u32 s2, s10, 0x80010 @@ -677,7 +677,7 @@ define amdgpu_kernel void @v5i8_preload_arg(ptr addrspace(1) nocapture inreg %ou ; ; GFX1250-LABEL: v5i8_preload_arg: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: s_pack_lh_b32_b16 s0, 0, s4 ; GFX1250-NEXT: s_and_b32 s1, s4, 0xffff ; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s5 @@ -694,13 +694,13 @@ define amdgpu_kernel void @v5i8_preload_arg(ptr addrspace(1) nocapture inreg %ou define amdgpu_kernel void @v5f64_arg(ptr addrspace(1) nocapture inreg %out, <5 x double> inreg %in) #0 { ; GFX942-LABEL: v5f64_arg: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB14_0 +; GFX942-NEXT: s_branch .LBB14_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB14_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB14_2: ; GFX942-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x60 ; GFX942-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x40 ; GFX942-NEXT: v_mov_b32_e32 v4, 0 @@ -721,13 +721,13 @@ define amdgpu_kernel void @v5f64_arg(ptr addrspace(1) nocapture inreg %out, <5 x ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: v5f64_arg: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB14_0 +; GFX90a-NEXT: s_branch .LBB14_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB14_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB14_2: ; GFX90a-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x60 ; GFX90a-NEXT: s_load_dwordx8 s[12:19], s[4:5], 0x40 ; GFX90a-NEXT: v_mov_b32_e32 v4, 0 @@ -749,10 +749,10 @@ define amdgpu_kernel void @v5f64_arg(ptr addrspace(1) nocapture inreg %out, <5 x ; ; GFX1250-LABEL: v5f64_arg: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: s_clause 0x1 -; GFX1250-NEXT: s_load_b64 s[12:13], s[0:1], 0x60 -; GFX1250-NEXT: s_load_b256 s[4:11], s[0:1], 0x40 +; GFX1250-NEXT: s_load_b64 s[12:13], s[0:1], 0x60 nv +; GFX1250-NEXT: s_load_b256 s[4:11], s[0:1], 0x40 nv ; GFX1250-NEXT: v_mov_b32_e32 v10, 0 ; GFX1250-NEXT: s_wait_kmcnt 0x0 ; GFX1250-NEXT: v_mov_b64_e32 v[8:9], s[12:13] @@ -771,14 +771,14 @@ define amdgpu_kernel void @v5f64_arg(ptr addrspace(1) nocapture inreg %out, <5 x define amdgpu_kernel void @v8i8_preload_arg(ptr addrspace(1) inreg %out, <8 x i8> inreg %in) #0 { ; GFX942-LABEL: v8i8_preload_arg: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB15_0 +; GFX942-NEXT: s_branch .LBB15_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB15_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB15_2: ; GFX942-NEXT: s_lshr_b32 s1, s5, 24 ; GFX942-NEXT: s_and_b32 s0, s5, 0xffff ; GFX942-NEXT: s_lshl_b32 s1, s1, 8 @@ -800,13 +800,13 @@ define amdgpu_kernel void @v8i8_preload_arg(ptr addrspace(1) inreg %out, <8 x i8 ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: v8i8_preload_arg: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB15_0 +; GFX90a-NEXT: s_branch .LBB15_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB15_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB15_2: ; GFX90a-NEXT: s_lshr_b32 s1, s11, 24 ; GFX90a-NEXT: s_lshl_b32 s1, s1, 8 ; GFX90a-NEXT: s_bfe_u32 s2, s11, 0x80010 @@ -829,7 +829,7 @@ define amdgpu_kernel void @v8i8_preload_arg(ptr addrspace(1) inreg %out, <8 x i8 ; ; GFX1250-LABEL: v8i8_preload_arg: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: s_pack_lh_b32_b16 s0, 0, s5 ; GFX1250-NEXT: s_pack_lh_b32_b16 s1, 0, s4 ; GFX1250-NEXT: s_and_b32 s4, s4, 0xffff @@ -847,27 +847,27 @@ define amdgpu_kernel void @v8i8_preload_arg(ptr addrspace(1) inreg %out, <8 x i8 define amdgpu_kernel void @i64_kernel_preload_arg(ptr addrspace(1) inreg %out, i64 inreg %a) #0 { ; GFX942-LABEL: i64_kernel_preload_arg: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB16_0 +; GFX942-NEXT: s_branch .LBB16_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB16_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB16_2: ; GFX942-NEXT: v_mov_b32_e32 v0, 0 ; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[4:5] ; GFX942-NEXT: global_store_dwordx2 v0, v[2:3], s[2:3] ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: i64_kernel_preload_arg: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB16_0 +; GFX90a-NEXT: s_branch .LBB16_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB16_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB16_2: ; GFX90a-NEXT: v_mov_b32_e32 v0, 0 ; GFX90a-NEXT: v_pk_mov_b32 v[2:3], s[10:11], s[10:11] op_sel:[0,1] ; GFX90a-NEXT: global_store_dwordx2 v0, v[2:3], s[8:9] @@ -875,7 +875,7 @@ define amdgpu_kernel void @i64_kernel_preload_arg(ptr addrspace(1) inreg %out, i ; ; GFX1250-LABEL: i64_kernel_preload_arg: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: v_mov_b64_e32 v[0:1], s[4:5] ; GFX1250-NEXT: v_mov_b32_e32 v2, 0 ; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[2:3] @@ -886,27 +886,27 @@ define amdgpu_kernel void @i64_kernel_preload_arg(ptr addrspace(1) inreg %out, i define amdgpu_kernel void @f64_kernel_preload_arg(ptr addrspace(1) inreg %out, double inreg %in) #0 { ; GFX942-LABEL: f64_kernel_preload_arg: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB17_0 +; GFX942-NEXT: s_branch .LBB17_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB17_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB17_2: ; GFX942-NEXT: v_mov_b32_e32 v0, 0 ; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[4:5] ; GFX942-NEXT: global_store_dwordx2 v0, v[2:3], s[2:3] ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: f64_kernel_preload_arg: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB17_0 +; GFX90a-NEXT: s_branch .LBB17_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB17_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB17_2: ; GFX90a-NEXT: v_mov_b32_e32 v0, 0 ; GFX90a-NEXT: v_pk_mov_b32 v[2:3], s[10:11], s[10:11] op_sel:[0,1] ; GFX90a-NEXT: global_store_dwordx2 v0, v[2:3], s[8:9] @@ -914,7 +914,7 @@ define amdgpu_kernel void @f64_kernel_preload_arg(ptr addrspace(1) inreg %out, d ; ; GFX1250-LABEL: f64_kernel_preload_arg: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: v_mov_b64_e32 v[0:1], s[4:5] ; GFX1250-NEXT: v_mov_b32_e32 v2, 0 ; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[2:3] @@ -925,28 +925,28 @@ define amdgpu_kernel void @f64_kernel_preload_arg(ptr addrspace(1) inreg %out, d define amdgpu_kernel void @half_kernel_preload_arg(ptr addrspace(1) inreg %out, half inreg %in) #0 { ; GFX942-LABEL: half_kernel_preload_arg: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dword s4, s[0:1], 0x8 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB18_0 +; GFX942-NEXT: s_branch .LBB18_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB18_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB18_2: ; GFX942-NEXT: v_mov_b32_e32 v0, 0 ; GFX942-NEXT: v_mov_b32_e32 v1, s4 ; GFX942-NEXT: global_store_short v0, v1, s[2:3] ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: half_kernel_preload_arg: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0 ; GFX90a-NEXT: s_load_dword s10, s[4:5], 0x8 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB18_0 +; GFX90a-NEXT: s_branch .LBB18_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB18_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB18_2: ; GFX90a-NEXT: v_mov_b32_e32 v0, 0 ; GFX90a-NEXT: v_mov_b32_e32 v1, s10 ; GFX90a-NEXT: global_store_short v0, v1, s[8:9] @@ -954,7 +954,7 @@ define amdgpu_kernel void @half_kernel_preload_arg(ptr addrspace(1) inreg %out, ; ; GFX1250-LABEL: half_kernel_preload_arg: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4 ; GFX1250-NEXT: global_store_b16 v0, v1, s[2:3] ; GFX1250-NEXT: s_endpgm @@ -964,28 +964,28 @@ define amdgpu_kernel void @half_kernel_preload_arg(ptr addrspace(1) inreg %out, define amdgpu_kernel void @bfloat_kernel_preload_arg(ptr addrspace(1) inreg %out, bfloat inreg %in) #0 { ; GFX942-LABEL: bfloat_kernel_preload_arg: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dword s4, s[0:1], 0x8 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB19_0 +; GFX942-NEXT: s_branch .LBB19_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB19_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB19_2: ; GFX942-NEXT: v_mov_b32_e32 v0, 0 ; GFX942-NEXT: v_mov_b32_e32 v1, s4 ; GFX942-NEXT: global_store_short v0, v1, s[2:3] ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: bfloat_kernel_preload_arg: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0 ; GFX90a-NEXT: s_load_dword s10, s[4:5], 0x8 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB19_0 +; GFX90a-NEXT: s_branch .LBB19_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB19_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB19_2: ; GFX90a-NEXT: v_mov_b32_e32 v0, 0 ; GFX90a-NEXT: v_mov_b32_e32 v1, s10 ; GFX90a-NEXT: global_store_short v0, v1, s[8:9] @@ -993,7 +993,7 @@ define amdgpu_kernel void @bfloat_kernel_preload_arg(ptr addrspace(1) inreg %out ; ; GFX1250-LABEL: bfloat_kernel_preload_arg: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4 ; GFX1250-NEXT: global_store_b16 v0, v1, s[2:3] ; GFX1250-NEXT: s_endpgm @@ -1003,28 +1003,28 @@ define amdgpu_kernel void @bfloat_kernel_preload_arg(ptr addrspace(1) inreg %out define amdgpu_kernel void @v2bfloat_kernel_preload_arg(ptr addrspace(1) inreg %out, <2 x bfloat> inreg %in) #0 { ; GFX942-LABEL: v2bfloat_kernel_preload_arg: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dword s4, s[0:1], 0x8 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB20_0 +; GFX942-NEXT: s_branch .LBB20_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB20_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB20_2: ; GFX942-NEXT: v_mov_b32_e32 v0, 0 ; GFX942-NEXT: v_mov_b32_e32 v1, s4 ; GFX942-NEXT: global_store_dword v0, v1, s[2:3] ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: v2bfloat_kernel_preload_arg: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0 ; GFX90a-NEXT: s_load_dword s10, s[4:5], 0x8 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB20_0 +; GFX90a-NEXT: s_branch .LBB20_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB20_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB20_2: ; GFX90a-NEXT: v_mov_b32_e32 v0, 0 ; GFX90a-NEXT: v_mov_b32_e32 v1, s10 ; GFX90a-NEXT: global_store_dword v0, v1, s[8:9] @@ -1032,7 +1032,7 @@ define amdgpu_kernel void @v2bfloat_kernel_preload_arg(ptr addrspace(1) inreg %o ; ; GFX1250-LABEL: v2bfloat_kernel_preload_arg: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4 ; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3] ; GFX1250-NEXT: s_endpgm @@ -1042,14 +1042,14 @@ define amdgpu_kernel void @v2bfloat_kernel_preload_arg(ptr addrspace(1) inreg %o define amdgpu_kernel void @v3bfloat_kernel_preload_arg(ptr addrspace(1) inreg %out, <3 x bfloat> inreg %in) #0 { ; GFX942-LABEL: v3bfloat_kernel_preload_arg: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB21_0 +; GFX942-NEXT: s_branch .LBB21_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB21_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB21_2: ; GFX942-NEXT: v_mov_b32_e32 v0, 0 ; GFX942-NEXT: v_mov_b32_e32 v1, s5 ; GFX942-NEXT: global_store_short v0, v1, s[2:3] offset:4 @@ -1058,13 +1058,13 @@ define amdgpu_kernel void @v3bfloat_kernel_preload_arg(ptr addrspace(1) inreg %o ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: v3bfloat_kernel_preload_arg: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB21_0 +; GFX90a-NEXT: s_branch .LBB21_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB21_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB21_2: ; GFX90a-NEXT: v_mov_b32_e32 v0, 0 ; GFX90a-NEXT: v_mov_b32_e32 v1, s11 ; GFX90a-NEXT: global_store_short v0, v1, s[8:9] offset:4 @@ -1074,7 +1074,7 @@ define amdgpu_kernel void @v3bfloat_kernel_preload_arg(ptr addrspace(1) inreg %o ; ; GFX1250-LABEL: v3bfloat_kernel_preload_arg: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s5 ; GFX1250-NEXT: v_mov_b32_e32 v2, s4 ; GFX1250-NEXT: s_clause 0x1 @@ -1087,15 +1087,15 @@ define amdgpu_kernel void @v3bfloat_kernel_preload_arg(ptr addrspace(1) inreg %o define amdgpu_kernel void @v6bfloat_kernel_preload_arg(ptr addrspace(1) inreg %out, <6 x bfloat> inreg %in) #0 { ; GFX942-LABEL: v6bfloat_kernel_preload_arg: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8 ; GFX942-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB22_0 +; GFX942-NEXT: s_branch .LBB22_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB22_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB22_2: ; GFX942-NEXT: v_mov_b32_e32 v0, s6 ; GFX942-NEXT: v_mov_b32_e32 v1, s7 ; GFX942-NEXT: v_mov_b32_e32 v2, s8 @@ -1104,13 +1104,13 @@ define amdgpu_kernel void @v6bfloat_kernel_preload_arg(ptr addrspace(1) inreg %o ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: v6bfloat_kernel_preload_arg: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB22_0 +; GFX90a-NEXT: s_branch .LBB22_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB22_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB22_2: ; GFX90a-NEXT: v_mov_b32_e32 v0, s12 ; GFX90a-NEXT: v_mov_b32_e32 v1, s13 ; GFX90a-NEXT: v_mov_b32_e32 v2, s14 @@ -1120,7 +1120,7 @@ define amdgpu_kernel void @v6bfloat_kernel_preload_arg(ptr addrspace(1) inreg %o ; ; GFX1250-LABEL: v6bfloat_kernel_preload_arg: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7 ; GFX1250-NEXT: v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v3, 0 ; GFX1250-NEXT: global_store_b96 v3, v[0:2], s[2:3] @@ -1131,14 +1131,14 @@ define amdgpu_kernel void @v6bfloat_kernel_preload_arg(ptr addrspace(1) inreg %o define amdgpu_kernel void @half_v7bfloat_kernel_preload_arg(ptr addrspace(1) inreg %out, half inreg %in, <7 x bfloat> inreg %in2, ptr addrspace(1) inreg %out2) #0 { ; GFX942-LABEL: half_v7bfloat_kernel_preload_arg: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x8 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB23_0 +; GFX942-NEXT: s_branch .LBB23_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB23_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB23_2: ; GFX942-NEXT: v_mov_b32_e32 v3, 0 ; GFX942-NEXT: v_mov_b32_e32 v0, s4 ; GFX942-NEXT: global_store_short v3, v0, s[2:3] @@ -1151,13 +1151,13 @@ define amdgpu_kernel void @half_v7bfloat_kernel_preload_arg(ptr addrspace(1) inr ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: half_v7bfloat_kernel_preload_arg: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB23_0 +; GFX90a-NEXT: s_branch .LBB23_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB23_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB23_2: ; GFX90a-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x20 ; GFX90a-NEXT: v_mov_b32_e32 v3, 0 ; GFX90a-NEXT: v_mov_b32_e32 v0, s10 @@ -1173,7 +1173,7 @@ define amdgpu_kernel void @half_v7bfloat_kernel_preload_arg(ptr addrspace(1) inr ; ; GFX1250-LABEL: half_v7bfloat_kernel_preload_arg: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, s4 ; GFX1250-NEXT: v_dual_mov_b32 v5, s9 :: v_dual_mov_b32 v2, s8 ; GFX1250-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7 @@ -1189,14 +1189,14 @@ define amdgpu_kernel void @half_v7bfloat_kernel_preload_arg(ptr addrspace(1) inr define amdgpu_kernel void @i1_kernel_preload_arg(ptr addrspace(1) inreg %out, i1 inreg %in) #0 { ; GFX942-LABEL: i1_kernel_preload_arg: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dword s4, s[0:1], 0x8 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB24_0 +; GFX942-NEXT: s_branch .LBB24_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB24_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB24_2: ; GFX942-NEXT: s_and_b32 s0, s4, 1 ; GFX942-NEXT: v_mov_b32_e32 v0, 0 ; GFX942-NEXT: v_mov_b32_e32 v1, s0 @@ -1204,14 +1204,14 @@ define amdgpu_kernel void @i1_kernel_preload_arg(ptr addrspace(1) inreg %out, i1 ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: i1_kernel_preload_arg: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0 ; GFX90a-NEXT: s_load_dword s10, s[4:5], 0x8 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB24_0 +; GFX90a-NEXT: s_branch .LBB24_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB24_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB24_2: ; GFX90a-NEXT: s_and_b32 s0, s10, 1 ; GFX90a-NEXT: v_mov_b32_e32 v0, 0 ; GFX90a-NEXT: v_mov_b32_e32 v1, s0 @@ -1220,7 +1220,7 @@ define amdgpu_kernel void @i1_kernel_preload_arg(ptr addrspace(1) inreg %out, i1 ; ; GFX1250-LABEL: i1_kernel_preload_arg: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: s_and_b32 s0, s4, 1 ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0 @@ -1232,15 +1232,15 @@ define amdgpu_kernel void @i1_kernel_preload_arg(ptr addrspace(1) inreg %out, i1 define amdgpu_kernel void @fp128_kernel_preload_arg(ptr addrspace(1) inreg %out, fp128 inreg %in) #0 { ; GFX942-LABEL: fp128_kernel_preload_arg: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8 ; GFX942-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB25_0 +; GFX942-NEXT: s_branch .LBB25_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB25_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB25_2: ; GFX942-NEXT: v_mov_b32_e32 v4, 0 ; GFX942-NEXT: v_mov_b32_e32 v0, s6 ; GFX942-NEXT: v_mov_b32_e32 v1, s7 @@ -1250,13 +1250,13 @@ define amdgpu_kernel void @fp128_kernel_preload_arg(ptr addrspace(1) inreg %out, ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: fp128_kernel_preload_arg: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB25_0 +; GFX90a-NEXT: s_branch .LBB25_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB25_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB25_2: ; GFX90a-NEXT: v_mov_b32_e32 v4, 0 ; GFX90a-NEXT: v_mov_b32_e32 v0, s12 ; GFX90a-NEXT: v_mov_b32_e32 v1, s13 @@ -1267,7 +1267,7 @@ define amdgpu_kernel void @fp128_kernel_preload_arg(ptr addrspace(1) inreg %out, ; ; GFX1250-LABEL: fp128_kernel_preload_arg: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v0, s6 ; GFX1250-NEXT: v_dual_mov_b32 v1, s7 :: v_dual_mov_b32 v2, s8 ; GFX1250-NEXT: v_mov_b32_e32 v3, s9 @@ -1279,14 +1279,14 @@ define amdgpu_kernel void @fp128_kernel_preload_arg(ptr addrspace(1) inreg %out, define amdgpu_kernel void @v7i8_kernel_preload_arg(ptr addrspace(1) inreg %out, <7 x i8> inreg %in) #0 { ; GFX942-LABEL: v7i8_kernel_preload_arg: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB26_0 +; GFX942-NEXT: s_branch .LBB26_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB26_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB26_2: ; GFX942-NEXT: s_lshr_b32 s1, s4, 24 ; GFX942-NEXT: s_and_b32 s0, s4, 0xffff ; GFX942-NEXT: s_lshl_b32 s1, s1, 8 @@ -1303,13 +1303,13 @@ define amdgpu_kernel void @v7i8_kernel_preload_arg(ptr addrspace(1) inreg %out, ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: v7i8_kernel_preload_arg: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB26_0 +; GFX90a-NEXT: s_branch .LBB26_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB26_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB26_2: ; GFX90a-NEXT: s_lshr_b32 s1, s10, 24 ; GFX90a-NEXT: s_lshl_b32 s1, s1, 8 ; GFX90a-NEXT: s_bfe_u32 s2, s10, 0x80010 @@ -1327,7 +1327,7 @@ define amdgpu_kernel void @v7i8_kernel_preload_arg(ptr addrspace(1) inreg %out, ; ; GFX1250-LABEL: v7i8_kernel_preload_arg: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: s_pack_lh_b32_b16 s0, 0, s4 ; GFX1250-NEXT: s_and_b32 s1, s4, 0xffff ; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s5 @@ -1345,15 +1345,15 @@ define amdgpu_kernel void @v7i8_kernel_preload_arg(ptr addrspace(1) inreg %out, define amdgpu_kernel void @v7half_kernel_preload_arg(ptr addrspace(1) inreg %out, <7 x half> inreg %in) #0 { ; GFX942-LABEL: v7half_kernel_preload_arg: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8 ; GFX942-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB27_0 +; GFX942-NEXT: s_branch .LBB27_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB27_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB27_2: ; GFX942-NEXT: v_mov_b32_e32 v3, 0 ; GFX942-NEXT: v_mov_b32_e32 v0, s9 ; GFX942-NEXT: global_store_short v3, v0, s[2:3] offset:12 @@ -1364,13 +1364,13 @@ define amdgpu_kernel void @v7half_kernel_preload_arg(ptr addrspace(1) inreg %out ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: v7half_kernel_preload_arg: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB27_0 +; GFX90a-NEXT: s_branch .LBB27_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB27_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB27_2: ; GFX90a-NEXT: v_mov_b32_e32 v3, 0 ; GFX90a-NEXT: v_mov_b32_e32 v0, s15 ; GFX90a-NEXT: global_store_short v3, v0, s[8:9] offset:12 @@ -1382,7 +1382,7 @@ define amdgpu_kernel void @v7half_kernel_preload_arg(ptr addrspace(1) inreg %out ; ; GFX1250-LABEL: v7half_kernel_preload_arg: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, s9 ; GFX1250-NEXT: v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v0, s6 ; GFX1250-NEXT: v_mov_b32_e32 v1, s7 @@ -1396,14 +1396,14 @@ define amdgpu_kernel void @v7half_kernel_preload_arg(ptr addrspace(1) inreg %out define amdgpu_kernel void @i16_i32_kernel_preload_arg(ptr addrspace(1) inreg %out, i16 inreg %in, i32 inreg %in2, ptr addrspace(1) inreg %out2) #0 { ; GFX942-LABEL: i16_i32_kernel_preload_arg: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB28_0 +; GFX942-NEXT: s_branch .LBB28_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB28_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB28_2: ; GFX942-NEXT: v_mov_b32_e32 v0, 0 ; GFX942-NEXT: v_mov_b32_e32 v1, s4 ; GFX942-NEXT: global_store_short v0, v1, s[2:3] @@ -1412,14 +1412,14 @@ define amdgpu_kernel void @i16_i32_kernel_preload_arg(ptr addrspace(1) inreg %ou ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: i16_i32_kernel_preload_arg: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 ; GFX90a-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB28_0 +; GFX90a-NEXT: s_branch .LBB28_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB28_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB28_2: ; GFX90a-NEXT: v_mov_b32_e32 v0, 0 ; GFX90a-NEXT: v_mov_b32_e32 v1, s10 ; GFX90a-NEXT: global_store_short v0, v1, s[8:9] @@ -1429,7 +1429,7 @@ define amdgpu_kernel void @i16_i32_kernel_preload_arg(ptr addrspace(1) inreg %ou ; ; GFX1250-LABEL: i16_i32_kernel_preload_arg: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4 ; GFX1250-NEXT: v_mov_b32_e32 v2, s5 ; GFX1250-NEXT: s_clause 0x1 @@ -1443,14 +1443,14 @@ define amdgpu_kernel void @i16_i32_kernel_preload_arg(ptr addrspace(1) inreg %ou define amdgpu_kernel void @i16_v3i32_kernel_preload_arg(ptr addrspace(1) inreg %out, i16 inreg %in, <3 x i32> inreg %in2, ptr addrspace(1) inreg %out2) #0 { ; GFX942-LABEL: i16_v3i32_kernel_preload_arg: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x8 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB29_0 +; GFX942-NEXT: s_branch .LBB29_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB29_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB29_2: ; GFX942-NEXT: v_mov_b32_e32 v3, 0 ; GFX942-NEXT: v_mov_b32_e32 v4, s4 ; GFX942-NEXT: v_mov_b32_e32 v0, s6 @@ -1461,13 +1461,13 @@ define amdgpu_kernel void @i16_v3i32_kernel_preload_arg(ptr addrspace(1) inreg % ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: i16_v3i32_kernel_preload_arg: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB29_0 +; GFX90a-NEXT: s_branch .LBB29_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB29_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB29_2: ; GFX90a-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x20 ; GFX90a-NEXT: v_mov_b32_e32 v3, 0 ; GFX90a-NEXT: v_mov_b32_e32 v4, s10 @@ -1481,7 +1481,7 @@ define amdgpu_kernel void @i16_v3i32_kernel_preload_arg(ptr addrspace(1) inreg % ; ; GFX1250-LABEL: i16_v3i32_kernel_preload_arg: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, s4 ; GFX1250-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7 ; GFX1250-NEXT: v_mov_b32_e32 v2, s8 @@ -1496,14 +1496,14 @@ define amdgpu_kernel void @i16_v3i32_kernel_preload_arg(ptr addrspace(1) inreg % define amdgpu_kernel void @i16_i16_kernel_preload_arg(ptr addrspace(1) inreg %out, i16 inreg %in, i16 inreg %in2, ptr addrspace(1) inreg %out2) #0 { ; GFX942-LABEL: i16_i16_kernel_preload_arg: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB30_0 +; GFX942-NEXT: s_branch .LBB30_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB30_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB30_2: ; GFX942-NEXT: v_mov_b32_e32 v0, 0 ; GFX942-NEXT: v_mov_b32_e32 v1, s4 ; GFX942-NEXT: global_store_short v0, v1, s[2:3] @@ -1511,14 +1511,14 @@ define amdgpu_kernel void @i16_i16_kernel_preload_arg(ptr addrspace(1) inreg %ou ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: i16_i16_kernel_preload_arg: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 ; GFX90a-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB30_0 +; GFX90a-NEXT: s_branch .LBB30_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB30_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB30_2: ; GFX90a-NEXT: v_mov_b32_e32 v0, 0 ; GFX90a-NEXT: v_mov_b32_e32 v1, s10 ; GFX90a-NEXT: global_store_short v0, v1, s[8:9] @@ -1527,7 +1527,7 @@ define amdgpu_kernel void @i16_i16_kernel_preload_arg(ptr addrspace(1) inreg %ou ; ; GFX1250-LABEL: i16_i16_kernel_preload_arg: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4 ; GFX1250-NEXT: s_clause 0x1 ; GFX1250-NEXT: global_store_b16 v0, v1, s[2:3] @@ -1540,14 +1540,14 @@ define amdgpu_kernel void @i16_i16_kernel_preload_arg(ptr addrspace(1) inreg %ou define amdgpu_kernel void @i16_v2i8_kernel_preload_arg(ptr addrspace(1) inreg %out, i16 inreg %in, <2 x i8> inreg %in2, ptr addrspace(1) inreg %out2) #0 { ; GFX942-LABEL: i16_v2i8_kernel_preload_arg: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB31_0 +; GFX942-NEXT: s_branch .LBB31_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB31_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB31_2: ; GFX942-NEXT: s_lshr_b32 s0, s4, 24 ; GFX942-NEXT: s_lshl_b32 s0, s0, 8 ; GFX942-NEXT: s_bfe_u32 s1, s4, 0x80010 @@ -1560,14 +1560,14 @@ define amdgpu_kernel void @i16_v2i8_kernel_preload_arg(ptr addrspace(1) inreg %o ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: i16_v2i8_kernel_preload_arg: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 ; GFX90a-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB31_0 +; GFX90a-NEXT: s_branch .LBB31_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB31_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB31_2: ; GFX90a-NEXT: s_lshr_b32 s0, s10, 24 ; GFX90a-NEXT: s_lshl_b32 s0, s0, 8 ; GFX90a-NEXT: s_bfe_u32 s1, s10, 0x80010 @@ -1581,7 +1581,7 @@ define amdgpu_kernel void @i16_v2i8_kernel_preload_arg(ptr addrspace(1) inreg %o ; ; GFX1250-LABEL: i16_v2i8_kernel_preload_arg: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4 ; GFX1250-NEXT: s_clause 0x1 ; GFX1250-NEXT: global_store_b16 v0, v1, s[2:3] @@ -1596,13 +1596,13 @@ define amdgpu_kernel void @i16_v2i8_kernel_preload_arg(ptr addrspace(1) inreg %o define amdgpu_kernel void @i32_ptr1_i32_staggered_preload_arg(i32 inreg %arg0, ptr addrspace(1) %out, i32 inreg %arg1) #0 { ; GFX942-LABEL: i32_ptr1_i32_staggered_preload_arg: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dword s2, s[0:1], 0x0 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB32_0 +; GFX942-NEXT: s_branch .LBB32_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB32_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB32_2: ; GFX942-NEXT: s_load_dword s3, s[0:1], 0x10 ; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8 ; GFX942-NEXT: v_mov_b32_e32 v0, 0 @@ -1613,13 +1613,13 @@ define amdgpu_kernel void @i32_ptr1_i32_staggered_preload_arg(i32 inreg %arg0, p ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: i32_ptr1_i32_staggered_preload_arg: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dword s8, s[4:5], 0x0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB32_0 +; GFX90a-NEXT: s_branch .LBB32_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB32_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB32_2: ; GFX90a-NEXT: s_load_dword s2, s[4:5], 0x10 ; GFX90a-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8 ; GFX90a-NEXT: v_mov_b32_e32 v0, 0 @@ -1631,8 +1631,8 @@ define amdgpu_kernel void @i32_ptr1_i32_staggered_preload_arg(i32 inreg %arg0, p ; ; GFX1250-LABEL: i32_ptr1_i32_staggered_preload_arg: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 -; GFX1250-NEXT: s_load_b96 s[4:6], s[0:1], 0x8 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 +; GFX1250-NEXT: s_load_b96 s[4:6], s[0:1], 0x8 nv ; GFX1250-NEXT: s_wait_kmcnt 0x0 ; GFX1250-NEXT: s_add_co_i32 s0, s2, s6 ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) @@ -1646,14 +1646,14 @@ define amdgpu_kernel void @i32_ptr1_i32_staggered_preload_arg(i32 inreg %arg0, p define amdgpu_kernel void @ptr1_i8_trailing_unused(ptr addrspace(1) inreg %out, i8 inreg %arg0, i32 inreg %unused) #0 { ; GFX942-LABEL: ptr1_i8_trailing_unused: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0 ; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB33_0 +; GFX942-NEXT: s_branch .LBB33_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB33_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB33_2: ; GFX942-NEXT: s_and_b32 s0, s4, 0xff ; GFX942-NEXT: v_mov_b32_e32 v0, 0 ; GFX942-NEXT: v_mov_b32_e32 v1, s0 @@ -1661,13 +1661,13 @@ define amdgpu_kernel void @ptr1_i8_trailing_unused(ptr addrspace(1) inreg %out, ; GFX942-NEXT: s_endpgm ; ; GFX90a-LABEL: ptr1_i8_trailing_unused: -; GFX90a: ; %bb.1: +; GFX90a: ; %bb.0: ; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 ; GFX90a-NEXT: s_waitcnt lgkmcnt(0) -; GFX90a-NEXT: s_branch .LBB33_0 +; GFX90a-NEXT: s_branch .LBB33_2 ; GFX90a-NEXT: .p2align 8 -; GFX90a-NEXT: ; %bb.2: -; GFX90a-NEXT: .LBB33_0: +; GFX90a-NEXT: ; %bb.1: +; GFX90a-NEXT: .LBB33_2: ; GFX90a-NEXT: s_and_b32 s0, s10, 0xff ; GFX90a-NEXT: v_mov_b32_e32 v0, 0 ; GFX90a-NEXT: v_mov_b32_e32 v1, s0 @@ -1676,7 +1676,7 @@ define amdgpu_kernel void @ptr1_i8_trailing_unused(ptr addrspace(1) inreg %out, ; ; GFX1250-LABEL: ptr1_i8_trailing_unused: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 +; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-NEXT: s_and_b32 s0, s4, 0xff ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0 diff --git a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll index fba7720b37bf6..eac37b7b1361f 100644 --- a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll +++ b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll @@ -413,13 +413,13 @@ define ptr @gep_disjoint_or(ptr %base) { ; taken from preload-implicit-kernargs.ll define amdgpu_kernel void @random_incorrect_offset(ptr addrspace(1) inreg %out) { ; GFX942-LABEL: random_incorrect_offset: -; GFX942: ; %bb.1: +; GFX942: ; %bb.0: ; GFX942-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-NEXT: s_branch .LBB21_0 +; GFX942-NEXT: s_branch .LBB21_2 ; GFX942-NEXT: .p2align 8 -; GFX942-NEXT: ; %bb.2: -; GFX942-NEXT: .LBB21_0: +; GFX942-NEXT: ; %bb.1: +; GFX942-NEXT: .LBB21_2: ; GFX942-NEXT: s_load_dword s0, s[4:5], 0xa ; GFX942-NEXT: v_mov_b32_e32 v0, 0 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) diff --git a/llvm/test/CodeGen/BPF/gotol.ll b/llvm/test/CodeGen/BPF/gotol.ll index 4df6192d0c8ca..e78bbc11e8bd4 100644 --- a/llvm/test/CodeGen/BPF/gotol.ll +++ b/llvm/test/CodeGen/BPF/gotol.ll @@ -49,9 +49,9 @@ begin: ; preds = %next2, %next ; case (2): conditional jmp ; CHECK: w0 *= w1 -; CHECK-NEXT: if w0 > w2 goto LBB0_7 +; CHECK-NEXT: if w0 > w2 goto LBB0_3 ; CHECK: goto LBB0_4 -; CHECK-LABEL: LBB0_7: +; CHECK-LABEL: LBB0_3: ; CHECK: gotol ; CHECK-LABEL: LBB0_4: diff --git a/llvm/test/CodeGen/LoongArch/atomicrmw-cond-sub-clamp.ll b/llvm/test/CodeGen/LoongArch/atomicrmw-cond-sub-clamp.ll index ab09cc9ed50a0..4b950311a3332 100644 --- a/llvm/test/CodeGen/LoongArch/atomicrmw-cond-sub-clamp.ll +++ b/llvm/test/CodeGen/LoongArch/atomicrmw-cond-sub-clamp.ll @@ -15,7 +15,7 @@ define i8 @atomicrmw_usub_cond_i8(ptr %ptr, i8 %val) { ; LA64-NEXT: .p2align 4, , 16 ; LA64-NEXT: .LBB0_1: # %atomicrmw.start ; LA64-NEXT: # =>This Loop Header: Depth=1 -; LA64-NEXT: # Child Loop BB0_3 Depth 2 +; LA64-NEXT: # Child Loop BB0_2 Depth 2 ; LA64-NEXT: move $a6, $a5 ; LA64-NEXT: srl.w $a5, $a5, $a2 ; LA64-NEXT: andi $a7, $a5, 255 @@ -29,24 +29,24 @@ define i8 @atomicrmw_usub_cond_i8(ptr %ptr, i8 %val) { ; LA64-NEXT: sll.w $a5, $a5, $a2 ; LA64-NEXT: and $a7, $a6, $a3 ; LA64-NEXT: or $a7, $a7, $a5 -; LA64-NEXT: .LBB0_3: # %atomicrmw.start +; LA64-NEXT: .LBB0_2: # %atomicrmw.start ; LA64-NEXT: # Parent Loop BB0_1 Depth=1 ; LA64-NEXT: # => This Inner Loop Header: Depth=2 ; LA64-NEXT: ll.w $a5, $a0, 0 -; LA64-NEXT: bne $a5, $a6, .LBB0_5 -; LA64-NEXT: # %bb.4: # %atomicrmw.start -; LA64-NEXT: # in Loop: Header=BB0_3 Depth=2 +; LA64-NEXT: bne $a5, $a6, .LBB0_4 +; LA64-NEXT: # %bb.3: # %atomicrmw.start +; LA64-NEXT: # in Loop: Header=BB0_2 Depth=2 ; LA64-NEXT: move $t0, $a7 ; LA64-NEXT: sc.w $t0, $a0, 0 -; LA64-NEXT: beq $t0, $zero, .LBB0_3 -; LA64-NEXT: b .LBB0_6 -; LA64-NEXT: .LBB0_5: # %atomicrmw.start +; LA64-NEXT: beq $t0, $zero, .LBB0_2 +; LA64-NEXT: b .LBB0_5 +; LA64-NEXT: .LBB0_4: # %atomicrmw.start ; LA64-NEXT: # in Loop: Header=BB0_1 Depth=1 ; LA64-NEXT: dbar 20 -; LA64-NEXT: .LBB0_6: # %atomicrmw.start +; LA64-NEXT: .LBB0_5: # %atomicrmw.start ; LA64-NEXT: # in Loop: Header=BB0_1 Depth=1 ; LA64-NEXT: bne $a5, $a6, .LBB0_1 -; LA64-NEXT: # %bb.2: # %atomicrmw.end +; LA64-NEXT: # %bb.6: # %atomicrmw.end ; LA64-NEXT: srl.w $a0, $a5, $a2 ; LA64-NEXT: ret %result = atomicrmw usub_cond ptr %ptr, i8 %val seq_cst @@ -68,7 +68,7 @@ define i16 @atomicrmw_usub_cond_i16(ptr %ptr, i16 %val) { ; LA64-NEXT: .p2align 4, , 16 ; LA64-NEXT: .LBB1_1: # %atomicrmw.start ; LA64-NEXT: # =>This Loop Header: Depth=1 -; LA64-NEXT: # Child Loop BB1_3 Depth 2 +; LA64-NEXT: # Child Loop BB1_2 Depth 2 ; LA64-NEXT: move $a6, $a5 ; LA64-NEXT: srl.w $a5, $a5, $a2 ; LA64-NEXT: bstrpick.d $a7, $a5, 15, 0 @@ -82,24 +82,24 @@ define i16 @atomicrmw_usub_cond_i16(ptr %ptr, i16 %val) { ; LA64-NEXT: sll.w $a5, $a5, $a2 ; LA64-NEXT: and $a7, $a6, $a3 ; LA64-NEXT: or $a7, $a7, $a5 -; LA64-NEXT: .LBB1_3: # %atomicrmw.start +; LA64-NEXT: .LBB1_2: # %atomicrmw.start ; LA64-NEXT: # Parent Loop BB1_1 Depth=1 ; LA64-NEXT: # => This Inner Loop Header: Depth=2 ; LA64-NEXT: ll.w $a5, $a0, 0 -; LA64-NEXT: bne $a5, $a6, .LBB1_5 -; LA64-NEXT: # %bb.4: # %atomicrmw.start -; LA64-NEXT: # in Loop: Header=BB1_3 Depth=2 +; LA64-NEXT: bne $a5, $a6, .LBB1_4 +; LA64-NEXT: # %bb.3: # %atomicrmw.start +; LA64-NEXT: # in Loop: Header=BB1_2 Depth=2 ; LA64-NEXT: move $t0, $a7 ; LA64-NEXT: sc.w $t0, $a0, 0 -; LA64-NEXT: beq $t0, $zero, .LBB1_3 -; LA64-NEXT: b .LBB1_6 -; LA64-NEXT: .LBB1_5: # %atomicrmw.start +; LA64-NEXT: beq $t0, $zero, .LBB1_2 +; LA64-NEXT: b .LBB1_5 +; LA64-NEXT: .LBB1_4: # %atomicrmw.start ; LA64-NEXT: # in Loop: Header=BB1_1 Depth=1 ; LA64-NEXT: dbar 20 -; LA64-NEXT: .LBB1_6: # %atomicrmw.start +; LA64-NEXT: .LBB1_5: # %atomicrmw.start ; LA64-NEXT: # in Loop: Header=BB1_1 Depth=1 ; LA64-NEXT: bne $a5, $a6, .LBB1_1 -; LA64-NEXT: # %bb.2: # %atomicrmw.end +; LA64-NEXT: # %bb.6: # %atomicrmw.end ; LA64-NEXT: srl.w $a0, $a5, $a2 ; LA64-NEXT: ret %result = atomicrmw usub_cond ptr %ptr, i16 %val seq_cst @@ -114,7 +114,7 @@ define i32 @atomicrmw_usub_cond_i32(ptr %ptr, i32 %val) { ; LA64-NEXT: .p2align 4, , 16 ; LA64-NEXT: .LBB2_1: # %atomicrmw.start ; LA64-NEXT: # =>This Loop Header: Depth=1 -; LA64-NEXT: # Child Loop BB2_3 Depth 2 +; LA64-NEXT: # Child Loop BB2_2 Depth 2 ; LA64-NEXT: move $a4, $a2 ; LA64-NEXT: sltu $a2, $a2, $a3 ; LA64-NEXT: xori $a2, $a2, 1 @@ -122,24 +122,24 @@ define i32 @atomicrmw_usub_cond_i32(ptr %ptr, i32 %val) { ; LA64-NEXT: maskeqz $a5, $a5, $a2 ; LA64-NEXT: masknez $a2, $a4, $a2 ; LA64-NEXT: or $a5, $a5, $a2 -; LA64-NEXT: .LBB2_3: # %atomicrmw.start +; LA64-NEXT: .LBB2_2: # %atomicrmw.start ; LA64-NEXT: # Parent Loop BB2_1 Depth=1 ; LA64-NEXT: # => This Inner Loop Header: Depth=2 ; LA64-NEXT: ll.w $a2, $a0, 0 -; LA64-NEXT: bne $a2, $a4, .LBB2_5 -; LA64-NEXT: # %bb.4: # %atomicrmw.start -; LA64-NEXT: # in Loop: Header=BB2_3 Depth=2 +; LA64-NEXT: bne $a2, $a4, .LBB2_4 +; LA64-NEXT: # %bb.3: # %atomicrmw.start +; LA64-NEXT: # in Loop: Header=BB2_2 Depth=2 ; LA64-NEXT: move $a6, $a5 ; LA64-NEXT: sc.w $a6, $a0, 0 -; LA64-NEXT: beq $a6, $zero, .LBB2_3 -; LA64-NEXT: b .LBB2_6 -; LA64-NEXT: .LBB2_5: # %atomicrmw.start +; LA64-NEXT: beq $a6, $zero, .LBB2_2 +; LA64-NEXT: b .LBB2_5 +; LA64-NEXT: .LBB2_4: # %atomicrmw.start ; LA64-NEXT: # in Loop: Header=BB2_1 Depth=1 ; LA64-NEXT: dbar 20 -; LA64-NEXT: .LBB2_6: # %atomicrmw.start +; LA64-NEXT: .LBB2_5: # %atomicrmw.start ; LA64-NEXT: # in Loop: Header=BB2_1 Depth=1 ; LA64-NEXT: bne $a2, $a4, .LBB2_1 -; LA64-NEXT: # %bb.2: # %atomicrmw.end +; LA64-NEXT: # %bb.6: # %atomicrmw.end ; LA64-NEXT: move $a0, $a2 ; LA64-NEXT: ret %result = atomicrmw usub_cond ptr %ptr, i32 %val seq_cst @@ -153,7 +153,7 @@ define i64 @atomicrmw_usub_cond_i64(ptr %ptr, i64 %val) { ; LA64-NEXT: .p2align 4, , 16 ; LA64-NEXT: .LBB3_1: # %atomicrmw.start ; LA64-NEXT: # =>This Loop Header: Depth=1 -; LA64-NEXT: # Child Loop BB3_3 Depth 2 +; LA64-NEXT: # Child Loop BB3_2 Depth 2 ; LA64-NEXT: move $a3, $a2 ; LA64-NEXT: sltu $a2, $a2, $a1 ; LA64-NEXT: xori $a2, $a2, 1 @@ -161,24 +161,24 @@ define i64 @atomicrmw_usub_cond_i64(ptr %ptr, i64 %val) { ; LA64-NEXT: maskeqz $a4, $a4, $a2 ; LA64-NEXT: masknez $a2, $a3, $a2 ; LA64-NEXT: or $a4, $a4, $a2 -; LA64-NEXT: .LBB3_3: # %atomicrmw.start +; LA64-NEXT: .LBB3_2: # %atomicrmw.start ; LA64-NEXT: # Parent Loop BB3_1 Depth=1 ; LA64-NEXT: # => This Inner Loop Header: Depth=2 ; LA64-NEXT: ll.d $a2, $a0, 0 -; LA64-NEXT: bne $a2, $a3, .LBB3_5 -; LA64-NEXT: # %bb.4: # %atomicrmw.start -; LA64-NEXT: # in Loop: Header=BB3_3 Depth=2 +; LA64-NEXT: bne $a2, $a3, .LBB3_4 +; LA64-NEXT: # %bb.3: # %atomicrmw.start +; LA64-NEXT: # in Loop: Header=BB3_2 Depth=2 ; LA64-NEXT: move $a5, $a4 ; LA64-NEXT: sc.d $a5, $a0, 0 -; LA64-NEXT: beq $a5, $zero, .LBB3_3 -; LA64-NEXT: b .LBB3_6 -; LA64-NEXT: .LBB3_5: # %atomicrmw.start +; LA64-NEXT: beq $a5, $zero, .LBB3_2 +; LA64-NEXT: b .LBB3_5 +; LA64-NEXT: .LBB3_4: # %atomicrmw.start ; LA64-NEXT: # in Loop: Header=BB3_1 Depth=1 ; LA64-NEXT: dbar 20 -; LA64-NEXT: .LBB3_6: # %atomicrmw.start +; LA64-NEXT: .LBB3_5: # %atomicrmw.start ; LA64-NEXT: # in Loop: Header=BB3_1 Depth=1 ; LA64-NEXT: bne $a2, $a3, .LBB3_1 -; LA64-NEXT: # %bb.2: # %atomicrmw.end +; LA64-NEXT: # %bb.6: # %atomicrmw.end ; LA64-NEXT: move $a0, $a2 ; LA64-NEXT: ret %result = atomicrmw usub_cond ptr %ptr, i64 %val seq_cst @@ -199,7 +199,7 @@ define i8 @atomicrmw_usub_sat_i8(ptr %ptr, i8 %val) { ; LA64-NEXT: .p2align 4, , 16 ; LA64-NEXT: .LBB4_1: # %atomicrmw.start ; LA64-NEXT: # =>This Loop Header: Depth=1 -; LA64-NEXT: # Child Loop BB4_3 Depth 2 +; LA64-NEXT: # Child Loop BB4_2 Depth 2 ; LA64-NEXT: move $a5, $a4 ; LA64-NEXT: srl.w $a4, $a4, $a2 ; LA64-NEXT: andi $a4, $a4, 255 @@ -209,24 +209,24 @@ define i8 @atomicrmw_usub_sat_i8(ptr %ptr, i8 %val) { ; LA64-NEXT: sll.w $a4, $a4, $a2 ; LA64-NEXT: and $a6, $a5, $a3 ; LA64-NEXT: or $a6, $a6, $a4 -; LA64-NEXT: .LBB4_3: # %atomicrmw.start +; LA64-NEXT: .LBB4_2: # %atomicrmw.start ; LA64-NEXT: # Parent Loop BB4_1 Depth=1 ; LA64-NEXT: # => This Inner Loop Header: Depth=2 ; LA64-NEXT: ll.w $a4, $a0, 0 -; LA64-NEXT: bne $a4, $a5, .LBB4_5 -; LA64-NEXT: # %bb.4: # %atomicrmw.start -; LA64-NEXT: # in Loop: Header=BB4_3 Depth=2 +; LA64-NEXT: bne $a4, $a5, .LBB4_4 +; LA64-NEXT: # %bb.3: # %atomicrmw.start +; LA64-NEXT: # in Loop: Header=BB4_2 Depth=2 ; LA64-NEXT: move $a7, $a6 ; LA64-NEXT: sc.w $a7, $a0, 0 -; LA64-NEXT: beq $a7, $zero, .LBB4_3 -; LA64-NEXT: b .LBB4_6 -; LA64-NEXT: .LBB4_5: # %atomicrmw.start +; LA64-NEXT: beq $a7, $zero, .LBB4_2 +; LA64-NEXT: b .LBB4_5 +; LA64-NEXT: .LBB4_4: # %atomicrmw.start ; LA64-NEXT: # in Loop: Header=BB4_1 Depth=1 ; LA64-NEXT: dbar 20 -; LA64-NEXT: .LBB4_6: # %atomicrmw.start +; LA64-NEXT: .LBB4_5: # %atomicrmw.start ; LA64-NEXT: # in Loop: Header=BB4_1 Depth=1 ; LA64-NEXT: bne $a4, $a5, .LBB4_1 -; LA64-NEXT: # %bb.2: # %atomicrmw.end +; LA64-NEXT: # %bb.6: # %atomicrmw.end ; LA64-NEXT: srl.w $a0, $a4, $a2 ; LA64-NEXT: ret %result = atomicrmw usub_sat ptr %ptr, i8 %val seq_cst @@ -248,7 +248,7 @@ define i16 @atomicrmw_usub_sat_i16(ptr %ptr, i16 %val) { ; LA64-NEXT: .p2align 4, , 16 ; LA64-NEXT: .LBB5_1: # %atomicrmw.start ; LA64-NEXT: # =>This Loop Header: Depth=1 -; LA64-NEXT: # Child Loop BB5_3 Depth 2 +; LA64-NEXT: # Child Loop BB5_2 Depth 2 ; LA64-NEXT: move $a5, $a4 ; LA64-NEXT: srl.w $a4, $a4, $a2 ; LA64-NEXT: bstrpick.d $a4, $a4, 15, 0 @@ -258,24 +258,24 @@ define i16 @atomicrmw_usub_sat_i16(ptr %ptr, i16 %val) { ; LA64-NEXT: sll.w $a4, $a4, $a2 ; LA64-NEXT: and $a6, $a5, $a3 ; LA64-NEXT: or $a6, $a6, $a4 -; LA64-NEXT: .LBB5_3: # %atomicrmw.start +; LA64-NEXT: .LBB5_2: # %atomicrmw.start ; LA64-NEXT: # Parent Loop BB5_1 Depth=1 ; LA64-NEXT: # => This Inner Loop Header: Depth=2 ; LA64-NEXT: ll.w $a4, $a0, 0 -; LA64-NEXT: bne $a4, $a5, .LBB5_5 -; LA64-NEXT: # %bb.4: # %atomicrmw.start -; LA64-NEXT: # in Loop: Header=BB5_3 Depth=2 +; LA64-NEXT: bne $a4, $a5, .LBB5_4 +; LA64-NEXT: # %bb.3: # %atomicrmw.start +; LA64-NEXT: # in Loop: Header=BB5_2 Depth=2 ; LA64-NEXT: move $a7, $a6 ; LA64-NEXT: sc.w $a7, $a0, 0 -; LA64-NEXT: beq $a7, $zero, .LBB5_3 -; LA64-NEXT: b .LBB5_6 -; LA64-NEXT: .LBB5_5: # %atomicrmw.start +; LA64-NEXT: beq $a7, $zero, .LBB5_2 +; LA64-NEXT: b .LBB5_5 +; LA64-NEXT: .LBB5_4: # %atomicrmw.start ; LA64-NEXT: # in Loop: Header=BB5_1 Depth=1 ; LA64-NEXT: dbar 20 -; LA64-NEXT: .LBB5_6: # %atomicrmw.start +; LA64-NEXT: .LBB5_5: # %atomicrmw.start ; LA64-NEXT: # in Loop: Header=BB5_1 Depth=1 ; LA64-NEXT: bne $a4, $a5, .LBB5_1 -; LA64-NEXT: # %bb.2: # %atomicrmw.end +; LA64-NEXT: # %bb.6: # %atomicrmw.end ; LA64-NEXT: srl.w $a0, $a4, $a2 ; LA64-NEXT: ret %result = atomicrmw usub_sat ptr %ptr, i16 %val seq_cst @@ -290,29 +290,29 @@ define i32 @atomicrmw_usub_sat_i32(ptr %ptr, i32 %val) { ; LA64-NEXT: .p2align 4, , 16 ; LA64-NEXT: .LBB6_1: # %atomicrmw.start ; LA64-NEXT: # =>This Loop Header: Depth=1 -; LA64-NEXT: # Child Loop BB6_3 Depth 2 +; LA64-NEXT: # Child Loop BB6_2 Depth 2 ; LA64-NEXT: move $a3, $a2 ; LA64-NEXT: sub.d $a2, $a2, $a1 ; LA64-NEXT: sltu $a4, $a3, $a2 ; LA64-NEXT: masknez $a4, $a2, $a4 -; LA64-NEXT: .LBB6_3: # %atomicrmw.start +; LA64-NEXT: .LBB6_2: # %atomicrmw.start ; LA64-NEXT: # Parent Loop BB6_1 Depth=1 ; LA64-NEXT: # => This Inner Loop Header: Depth=2 ; LA64-NEXT: ll.w $a2, $a0, 0 -; LA64-NEXT: bne $a2, $a3, .LBB6_5 -; LA64-NEXT: # %bb.4: # %atomicrmw.start -; LA64-NEXT: # in Loop: Header=BB6_3 Depth=2 +; LA64-NEXT: bne $a2, $a3, .LBB6_4 +; LA64-NEXT: # %bb.3: # %atomicrmw.start +; LA64-NEXT: # in Loop: Header=BB6_2 Depth=2 ; LA64-NEXT: move $a5, $a4 ; LA64-NEXT: sc.w $a5, $a0, 0 -; LA64-NEXT: beq $a5, $zero, .LBB6_3 -; LA64-NEXT: b .LBB6_6 -; LA64-NEXT: .LBB6_5: # %atomicrmw.start +; LA64-NEXT: beq $a5, $zero, .LBB6_2 +; LA64-NEXT: b .LBB6_5 +; LA64-NEXT: .LBB6_4: # %atomicrmw.start ; LA64-NEXT: # in Loop: Header=BB6_1 Depth=1 ; LA64-NEXT: dbar 20 -; LA64-NEXT: .LBB6_6: # %atomicrmw.start +; LA64-NEXT: .LBB6_5: # %atomicrmw.start ; LA64-NEXT: # in Loop: Header=BB6_1 Depth=1 ; LA64-NEXT: bne $a2, $a3, .LBB6_1 -; LA64-NEXT: # %bb.2: # %atomicrmw.end +; LA64-NEXT: # %bb.6: # %atomicrmw.end ; LA64-NEXT: move $a0, $a2 ; LA64-NEXT: ret %result = atomicrmw usub_sat ptr %ptr, i32 %val seq_cst @@ -326,29 +326,29 @@ define i64 @atomicrmw_usub_sat_i64(ptr %ptr, i64 %val) { ; LA64-NEXT: .p2align 4, , 16 ; LA64-NEXT: .LBB7_1: # %atomicrmw.start ; LA64-NEXT: # =>This Loop Header: Depth=1 -; LA64-NEXT: # Child Loop BB7_3 Depth 2 +; LA64-NEXT: # Child Loop BB7_2 Depth 2 ; LA64-NEXT: move $a3, $a2 ; LA64-NEXT: sub.d $a2, $a2, $a1 ; LA64-NEXT: sltu $a4, $a3, $a2 ; LA64-NEXT: masknez $a4, $a2, $a4 -; LA64-NEXT: .LBB7_3: # %atomicrmw.start +; LA64-NEXT: .LBB7_2: # %atomicrmw.start ; LA64-NEXT: # Parent Loop BB7_1 Depth=1 ; LA64-NEXT: # => This Inner Loop Header: Depth=2 ; LA64-NEXT: ll.d $a2, $a0, 0 -; LA64-NEXT: bne $a2, $a3, .LBB7_5 -; LA64-NEXT: # %bb.4: # %atomicrmw.start -; LA64-NEXT: # in Loop: Header=BB7_3 Depth=2 +; LA64-NEXT: bne $a2, $a3, .LBB7_4 +; LA64-NEXT: # %bb.3: # %atomicrmw.start +; LA64-NEXT: # in Loop: Header=BB7_2 Depth=2 ; LA64-NEXT: move $a5, $a4 ; LA64-NEXT: sc.d $a5, $a0, 0 -; LA64-NEXT: beq $a5, $zero, .LBB7_3 -; LA64-NEXT: b .LBB7_6 -; LA64-NEXT: .LBB7_5: # %atomicrmw.start +; LA64-NEXT: beq $a5, $zero, .LBB7_2 +; LA64-NEXT: b .LBB7_5 +; LA64-NEXT: .LBB7_4: # %atomicrmw.start ; LA64-NEXT: # in Loop: Header=BB7_1 Depth=1 ; LA64-NEXT: dbar 20 -; LA64-NEXT: .LBB7_6: # %atomicrmw.start +; LA64-NEXT: .LBB7_5: # %atomicrmw.start ; LA64-NEXT: # in Loop: Header=BB7_1 Depth=1 ; LA64-NEXT: bne $a2, $a3, .LBB7_1 -; LA64-NEXT: # %bb.2: # %atomicrmw.end +; LA64-NEXT: # %bb.6: # %atomicrmw.end ; LA64-NEXT: move $a0, $a2 ; LA64-NEXT: ret %result = atomicrmw usub_sat ptr %ptr, i64 %val seq_cst diff --git a/llvm/test/CodeGen/LoongArch/atomicrmw-uinc-udec-wrap.ll b/llvm/test/CodeGen/LoongArch/atomicrmw-uinc-udec-wrap.ll index c9e4a05e838f4..0aaf900377e95 100644 --- a/llvm/test/CodeGen/LoongArch/atomicrmw-uinc-udec-wrap.ll +++ b/llvm/test/CodeGen/LoongArch/atomicrmw-uinc-udec-wrap.ll @@ -15,7 +15,7 @@ define i8 @atomicrmw_uinc_wrap_i8(ptr %ptr, i8 %val) { ; LA64-NEXT: .p2align 4, , 16 ; LA64-NEXT: .LBB0_1: # %atomicrmw.start ; LA64-NEXT: # =>This Loop Header: Depth=1 -; LA64-NEXT: # Child Loop BB0_3 Depth 2 +; LA64-NEXT: # Child Loop BB0_2 Depth 2 ; LA64-NEXT: move $a5, $a4 ; LA64-NEXT: srl.w $a4, $a4, $a2 ; LA64-NEXT: andi $a6, $a4, 255 @@ -27,24 +27,24 @@ define i8 @atomicrmw_uinc_wrap_i8(ptr %ptr, i8 %val) { ; LA64-NEXT: sll.w $a4, $a4, $a2 ; LA64-NEXT: and $a6, $a5, $a3 ; LA64-NEXT: or $a6, $a6, $a4 -; LA64-NEXT: .LBB0_3: # %atomicrmw.start +; LA64-NEXT: .LBB0_2: # %atomicrmw.start ; LA64-NEXT: # Parent Loop BB0_1 Depth=1 ; LA64-NEXT: # => This Inner Loop Header: Depth=2 ; LA64-NEXT: ll.w $a4, $a0, 0 -; LA64-NEXT: bne $a4, $a5, .LBB0_5 -; LA64-NEXT: # %bb.4: # %atomicrmw.start -; LA64-NEXT: # in Loop: Header=BB0_3 Depth=2 +; LA64-NEXT: bne $a4, $a5, .LBB0_4 +; LA64-NEXT: # %bb.3: # %atomicrmw.start +; LA64-NEXT: # in Loop: Header=BB0_2 Depth=2 ; LA64-NEXT: move $a7, $a6 ; LA64-NEXT: sc.w $a7, $a0, 0 -; LA64-NEXT: beq $a7, $zero, .LBB0_3 -; LA64-NEXT: b .LBB0_6 -; LA64-NEXT: .LBB0_5: # %atomicrmw.start +; LA64-NEXT: beq $a7, $zero, .LBB0_2 +; LA64-NEXT: b .LBB0_5 +; LA64-NEXT: .LBB0_4: # %atomicrmw.start ; LA64-NEXT: # in Loop: Header=BB0_1 Depth=1 ; LA64-NEXT: dbar 20 -; LA64-NEXT: .LBB0_6: # %atomicrmw.start +; LA64-NEXT: .LBB0_5: # %atomicrmw.start ; LA64-NEXT: # in Loop: Header=BB0_1 Depth=1 ; LA64-NEXT: bne $a4, $a5, .LBB0_1 -; LA64-NEXT: # %bb.2: # %atomicrmw.end +; LA64-NEXT: # %bb.6: # %atomicrmw.end ; LA64-NEXT: srl.w $a0, $a4, $a2 ; LA64-NEXT: ret %result = atomicrmw uinc_wrap ptr %ptr, i8 %val seq_cst @@ -66,7 +66,7 @@ define i16 @atomicrmw_uinc_wrap_i16(ptr %ptr, i16 %val) { ; LA64-NEXT: .p2align 4, , 16 ; LA64-NEXT: .LBB1_1: # %atomicrmw.start ; LA64-NEXT: # =>This Loop Header: Depth=1 -; LA64-NEXT: # Child Loop BB1_3 Depth 2 +; LA64-NEXT: # Child Loop BB1_2 Depth 2 ; LA64-NEXT: move $a5, $a4 ; LA64-NEXT: srl.w $a4, $a4, $a2 ; LA64-NEXT: bstrpick.d $a6, $a4, 15, 0 @@ -78,24 +78,24 @@ define i16 @atomicrmw_uinc_wrap_i16(ptr %ptr, i16 %val) { ; LA64-NEXT: sll.w $a4, $a4, $a2 ; LA64-NEXT: and $a6, $a5, $a3 ; LA64-NEXT: or $a6, $a6, $a4 -; LA64-NEXT: .LBB1_3: # %atomicrmw.start +; LA64-NEXT: .LBB1_2: # %atomicrmw.start ; LA64-NEXT: # Parent Loop BB1_1 Depth=1 ; LA64-NEXT: # => This Inner Loop Header: Depth=2 ; LA64-NEXT: ll.w $a4, $a0, 0 -; LA64-NEXT: bne $a4, $a5, .LBB1_5 -; LA64-NEXT: # %bb.4: # %atomicrmw.start -; LA64-NEXT: # in Loop: Header=BB1_3 Depth=2 +; LA64-NEXT: bne $a4, $a5, .LBB1_4 +; LA64-NEXT: # %bb.3: # %atomicrmw.start +; LA64-NEXT: # in Loop: Header=BB1_2 Depth=2 ; LA64-NEXT: move $a7, $a6 ; LA64-NEXT: sc.w $a7, $a0, 0 -; LA64-NEXT: beq $a7, $zero, .LBB1_3 -; LA64-NEXT: b .LBB1_6 -; LA64-NEXT: .LBB1_5: # %atomicrmw.start +; LA64-NEXT: beq $a7, $zero, .LBB1_2 +; LA64-NEXT: b .LBB1_5 +; LA64-NEXT: .LBB1_4: # %atomicrmw.start ; LA64-NEXT: # in Loop: Header=BB1_1 Depth=1 ; LA64-NEXT: dbar 20 -; LA64-NEXT: .LBB1_6: # %atomicrmw.start +; LA64-NEXT: .LBB1_5: # %atomicrmw.start ; LA64-NEXT: # in Loop: Header=BB1_1 Depth=1 ; LA64-NEXT: bne $a4, $a5, .LBB1_1 -; LA64-NEXT: # %bb.2: # %atomicrmw.end +; LA64-NEXT: # %bb.6: # %atomicrmw.end ; LA64-NEXT: srl.w $a0, $a4, $a2 ; LA64-NEXT: ret %result = atomicrmw uinc_wrap ptr %ptr, i16 %val seq_cst @@ -110,30 +110,30 @@ define i32 @atomicrmw_uinc_wrap_i32(ptr %ptr, i32 %val) { ; LA64-NEXT: .p2align 4, , 16 ; LA64-NEXT: .LBB2_1: # %atomicrmw.start ; LA64-NEXT: # =>This Loop Header: Depth=1 -; LA64-NEXT: # Child Loop BB2_3 Depth 2 +; LA64-NEXT: # Child Loop BB2_2 Depth 2 ; LA64-NEXT: move $a3, $a2 ; LA64-NEXT: addi.w $a2, $a2, 1 ; LA64-NEXT: sltu $a4, $a3, $a1 ; LA64-NEXT: xori $a4, $a4, 1 ; LA64-NEXT: masknez $a4, $a2, $a4 -; LA64-NEXT: .LBB2_3: # %atomicrmw.start +; LA64-NEXT: .LBB2_2: # %atomicrmw.start ; LA64-NEXT: # Parent Loop BB2_1 Depth=1 ; LA64-NEXT: # => This Inner Loop Header: Depth=2 ; LA64-NEXT: ll.w $a2, $a0, 0 -; LA64-NEXT: bne $a2, $a3, .LBB2_5 -; LA64-NEXT: # %bb.4: # %atomicrmw.start -; LA64-NEXT: # in Loop: Header=BB2_3 Depth=2 +; LA64-NEXT: bne $a2, $a3, .LBB2_4 +; LA64-NEXT: # %bb.3: # %atomicrmw.start +; LA64-NEXT: # in Loop: Header=BB2_2 Depth=2 ; LA64-NEXT: move $a5, $a4 ; LA64-NEXT: sc.w $a5, $a0, 0 -; LA64-NEXT: beq $a5, $zero, .LBB2_3 -; LA64-NEXT: b .LBB2_6 -; LA64-NEXT: .LBB2_5: # %atomicrmw.start +; LA64-NEXT: beq $a5, $zero, .LBB2_2 +; LA64-NEXT: b .LBB2_5 +; LA64-NEXT: .LBB2_4: # %atomicrmw.start ; LA64-NEXT: # in Loop: Header=BB2_1 Depth=1 ; LA64-NEXT: dbar 20 -; LA64-NEXT: .LBB2_6: # %atomicrmw.start +; LA64-NEXT: .LBB2_5: # %atomicrmw.start ; LA64-NEXT: # in Loop: Header=BB2_1 Depth=1 ; LA64-NEXT: bne $a2, $a3, .LBB2_1 -; LA64-NEXT: # %bb.2: # %atomicrmw.end +; LA64-NEXT: # %bb.6: # %atomicrmw.end ; LA64-NEXT: move $a0, $a2 ; LA64-NEXT: ret %result = atomicrmw uinc_wrap ptr %ptr, i32 %val seq_cst @@ -147,30 +147,30 @@ define i64 @atomicrmw_uinc_wrap_i64(ptr %ptr, i64 %val) { ; LA64-NEXT: .p2align 4, , 16 ; LA64-NEXT: .LBB3_1: # %atomicrmw.start ; LA64-NEXT: # =>This Loop Header: Depth=1 -; LA64-NEXT: # Child Loop BB3_3 Depth 2 +; LA64-NEXT: # Child Loop BB3_2 Depth 2 ; LA64-NEXT: move $a3, $a2 ; LA64-NEXT: addi.d $a2, $a2, 1 ; LA64-NEXT: sltu $a4, $a3, $a1 ; LA64-NEXT: xori $a4, $a4, 1 ; LA64-NEXT: masknez $a4, $a2, $a4 -; LA64-NEXT: .LBB3_3: # %atomicrmw.start +; LA64-NEXT: .LBB3_2: # %atomicrmw.start ; LA64-NEXT: # Parent Loop BB3_1 Depth=1 ; LA64-NEXT: # => This Inner Loop Header: Depth=2 ; LA64-NEXT: ll.d $a2, $a0, 0 -; LA64-NEXT: bne $a2, $a3, .LBB3_5 -; LA64-NEXT: # %bb.4: # %atomicrmw.start -; LA64-NEXT: # in Loop: Header=BB3_3 Depth=2 +; LA64-NEXT: bne $a2, $a3, .LBB3_4 +; LA64-NEXT: # %bb.3: # %atomicrmw.start +; LA64-NEXT: # in Loop: Header=BB3_2 Depth=2 ; LA64-NEXT: move $a5, $a4 ; LA64-NEXT: sc.d $a5, $a0, 0 -; LA64-NEXT: beq $a5, $zero, .LBB3_3 -; LA64-NEXT: b .LBB3_6 -; LA64-NEXT: .LBB3_5: # %atomicrmw.start +; LA64-NEXT: beq $a5, $zero, .LBB3_2 +; LA64-NEXT: b .LBB3_5 +; LA64-NEXT: .LBB3_4: # %atomicrmw.start ; LA64-NEXT: # in Loop: Header=BB3_1 Depth=1 ; LA64-NEXT: dbar 20 -; LA64-NEXT: .LBB3_6: # %atomicrmw.start +; LA64-NEXT: .LBB3_5: # %atomicrmw.start ; LA64-NEXT: # in Loop: Header=BB3_1 Depth=1 ; LA64-NEXT: bne $a2, $a3, .LBB3_1 -; LA64-NEXT: # %bb.2: # %atomicrmw.end +; LA64-NEXT: # %bb.6: # %atomicrmw.end ; LA64-NEXT: move $a0, $a2 ; LA64-NEXT: ret %result = atomicrmw uinc_wrap ptr %ptr, i64 %val seq_cst @@ -191,7 +191,7 @@ define i8 @atomicrmw_udec_wrap_i8(ptr %ptr, i8 %val) { ; LA64-NEXT: .p2align 4, , 16 ; LA64-NEXT: .LBB4_1: # %atomicrmw.start ; LA64-NEXT: # =>This Loop Header: Depth=1 -; LA64-NEXT: # Child Loop BB4_3 Depth 2 +; LA64-NEXT: # Child Loop BB4_2 Depth 2 ; LA64-NEXT: move $a6, $a5 ; LA64-NEXT: srl.w $a5, $a5, $a2 ; LA64-NEXT: andi $a7, $a5, 255 @@ -208,24 +208,24 @@ define i8 @atomicrmw_udec_wrap_i8(ptr %ptr, i8 %val) { ; LA64-NEXT: sll.w $a5, $a5, $a2 ; LA64-NEXT: and $a7, $a6, $a3 ; LA64-NEXT: or $a7, $a7, $a5 -; LA64-NEXT: .LBB4_3: # %atomicrmw.start +; LA64-NEXT: .LBB4_2: # %atomicrmw.start ; LA64-NEXT: # Parent Loop BB4_1 Depth=1 ; LA64-NEXT: # => This Inner Loop Header: Depth=2 ; LA64-NEXT: ll.w $a5, $a0, 0 -; LA64-NEXT: bne $a5, $a6, .LBB4_5 -; LA64-NEXT: # %bb.4: # %atomicrmw.start -; LA64-NEXT: # in Loop: Header=BB4_3 Depth=2 +; LA64-NEXT: bne $a5, $a6, .LBB4_4 +; LA64-NEXT: # %bb.3: # %atomicrmw.start +; LA64-NEXT: # in Loop: Header=BB4_2 Depth=2 ; LA64-NEXT: move $t0, $a7 ; LA64-NEXT: sc.w $t0, $a0, 0 -; LA64-NEXT: beq $t0, $zero, .LBB4_3 -; LA64-NEXT: b .LBB4_6 -; LA64-NEXT: .LBB4_5: # %atomicrmw.start +; LA64-NEXT: beq $t0, $zero, .LBB4_2 +; LA64-NEXT: b .LBB4_5 +; LA64-NEXT: .LBB4_4: # %atomicrmw.start ; LA64-NEXT: # in Loop: Header=BB4_1 Depth=1 ; LA64-NEXT: dbar 20 -; LA64-NEXT: .LBB4_6: # %atomicrmw.start +; LA64-NEXT: .LBB4_5: # %atomicrmw.start ; LA64-NEXT: # in Loop: Header=BB4_1 Depth=1 ; LA64-NEXT: bne $a5, $a6, .LBB4_1 -; LA64-NEXT: # %bb.2: # %atomicrmw.end +; LA64-NEXT: # %bb.6: # %atomicrmw.end ; LA64-NEXT: srl.w $a0, $a5, $a2 ; LA64-NEXT: ret %result = atomicrmw udec_wrap ptr %ptr, i8 %val seq_cst @@ -247,7 +247,7 @@ define i16 @atomicrmw_udec_wrap_i16(ptr %ptr, i16 %val) { ; LA64-NEXT: .p2align 4, , 16 ; LA64-NEXT: .LBB5_1: # %atomicrmw.start ; LA64-NEXT: # =>This Loop Header: Depth=1 -; LA64-NEXT: # Child Loop BB5_3 Depth 2 +; LA64-NEXT: # Child Loop BB5_2 Depth 2 ; LA64-NEXT: move $a6, $a5 ; LA64-NEXT: srl.w $a5, $a5, $a2 ; LA64-NEXT: bstrpick.d $a7, $a5, 15, 0 @@ -264,24 +264,24 @@ define i16 @atomicrmw_udec_wrap_i16(ptr %ptr, i16 %val) { ; LA64-NEXT: sll.w $a5, $a5, $a2 ; LA64-NEXT: and $a7, $a6, $a3 ; LA64-NEXT: or $a7, $a7, $a5 -; LA64-NEXT: .LBB5_3: # %atomicrmw.start +; LA64-NEXT: .LBB5_2: # %atomicrmw.start ; LA64-NEXT: # Parent Loop BB5_1 Depth=1 ; LA64-NEXT: # => This Inner Loop Header: Depth=2 ; LA64-NEXT: ll.w $a5, $a0, 0 -; LA64-NEXT: bne $a5, $a6, .LBB5_5 -; LA64-NEXT: # %bb.4: # %atomicrmw.start -; LA64-NEXT: # in Loop: Header=BB5_3 Depth=2 +; LA64-NEXT: bne $a5, $a6, .LBB5_4 +; LA64-NEXT: # %bb.3: # %atomicrmw.start +; LA64-NEXT: # in Loop: Header=BB5_2 Depth=2 ; LA64-NEXT: move $t0, $a7 ; LA64-NEXT: sc.w $t0, $a0, 0 -; LA64-NEXT: beq $t0, $zero, .LBB5_3 -; LA64-NEXT: b .LBB5_6 -; LA64-NEXT: .LBB5_5: # %atomicrmw.start +; LA64-NEXT: beq $t0, $zero, .LBB5_2 +; LA64-NEXT: b .LBB5_5 +; LA64-NEXT: .LBB5_4: # %atomicrmw.start ; LA64-NEXT: # in Loop: Header=BB5_1 Depth=1 ; LA64-NEXT: dbar 20 -; LA64-NEXT: .LBB5_6: # %atomicrmw.start +; LA64-NEXT: .LBB5_5: # %atomicrmw.start ; LA64-NEXT: # in Loop: Header=BB5_1 Depth=1 ; LA64-NEXT: bne $a5, $a6, .LBB5_1 -; LA64-NEXT: # %bb.2: # %atomicrmw.end +; LA64-NEXT: # %bb.6: # %atomicrmw.end ; LA64-NEXT: srl.w $a0, $a5, $a2 ; LA64-NEXT: ret %result = atomicrmw udec_wrap ptr %ptr, i16 %val seq_cst @@ -296,7 +296,7 @@ define i32 @atomicrmw_udec_wrap_i32(ptr %ptr, i32 %val) { ; LA64-NEXT: .p2align 4, , 16 ; LA64-NEXT: .LBB6_1: # %atomicrmw.start ; LA64-NEXT: # =>This Loop Header: Depth=1 -; LA64-NEXT: # Child Loop BB6_3 Depth 2 +; LA64-NEXT: # Child Loop BB6_2 Depth 2 ; LA64-NEXT: move $a4, $a2 ; LA64-NEXT: addi.w $a2, $a2, -1 ; LA64-NEXT: sltui $a5, $a4, 1 @@ -307,24 +307,24 @@ define i32 @atomicrmw_udec_wrap_i32(ptr %ptr, i32 %val) { ; LA64-NEXT: masknez $a2, $a2, $a5 ; LA64-NEXT: maskeqz $a5, $a1, $a5 ; LA64-NEXT: or $a5, $a5, $a2 -; LA64-NEXT: .LBB6_3: # %atomicrmw.start +; LA64-NEXT: .LBB6_2: # %atomicrmw.start ; LA64-NEXT: # Parent Loop BB6_1 Depth=1 ; LA64-NEXT: # => This Inner Loop Header: Depth=2 ; LA64-NEXT: ll.w $a2, $a0, 0 -; LA64-NEXT: bne $a2, $a4, .LBB6_5 -; LA64-NEXT: # %bb.4: # %atomicrmw.start -; LA64-NEXT: # in Loop: Header=BB6_3 Depth=2 +; LA64-NEXT: bne $a2, $a4, .LBB6_4 +; LA64-NEXT: # %bb.3: # %atomicrmw.start +; LA64-NEXT: # in Loop: Header=BB6_2 Depth=2 ; LA64-NEXT: move $a6, $a5 ; LA64-NEXT: sc.w $a6, $a0, 0 -; LA64-NEXT: beq $a6, $zero, .LBB6_3 -; LA64-NEXT: b .LBB6_6 -; LA64-NEXT: .LBB6_5: # %atomicrmw.start +; LA64-NEXT: beq $a6, $zero, .LBB6_2 +; LA64-NEXT: b .LBB6_5 +; LA64-NEXT: .LBB6_4: # %atomicrmw.start ; LA64-NEXT: # in Loop: Header=BB6_1 Depth=1 ; LA64-NEXT: dbar 20 -; LA64-NEXT: .LBB6_6: # %atomicrmw.start +; LA64-NEXT: .LBB6_5: # %atomicrmw.start ; LA64-NEXT: # in Loop: Header=BB6_1 Depth=1 ; LA64-NEXT: bne $a2, $a4, .LBB6_1 -; LA64-NEXT: # %bb.2: # %atomicrmw.end +; LA64-NEXT: # %bb.6: # %atomicrmw.end ; LA64-NEXT: move $a0, $a2 ; LA64-NEXT: ret %result = atomicrmw udec_wrap ptr %ptr, i32 %val seq_cst @@ -338,7 +338,7 @@ define i64 @atomicrmw_udec_wrap_i64(ptr %ptr, i64 %val) { ; LA64-NEXT: .p2align 4, , 16 ; LA64-NEXT: .LBB7_1: # %atomicrmw.start ; LA64-NEXT: # =>This Loop Header: Depth=1 -; LA64-NEXT: # Child Loop BB7_3 Depth 2 +; LA64-NEXT: # Child Loop BB7_2 Depth 2 ; LA64-NEXT: move $a3, $a2 ; LA64-NEXT: addi.d $a2, $a2, -1 ; LA64-NEXT: sltui $a4, $a3, 1 @@ -349,24 +349,24 @@ define i64 @atomicrmw_udec_wrap_i64(ptr %ptr, i64 %val) { ; LA64-NEXT: masknez $a2, $a2, $a4 ; LA64-NEXT: maskeqz $a4, $a1, $a4 ; LA64-NEXT: or $a4, $a4, $a2 -; LA64-NEXT: .LBB7_3: # %atomicrmw.start +; LA64-NEXT: .LBB7_2: # %atomicrmw.start ; LA64-NEXT: # Parent Loop BB7_1 Depth=1 ; LA64-NEXT: # => This Inner Loop Header: Depth=2 ; LA64-NEXT: ll.d $a2, $a0, 0 -; LA64-NEXT: bne $a2, $a3, .LBB7_5 -; LA64-NEXT: # %bb.4: # %atomicrmw.start -; LA64-NEXT: # in Loop: Header=BB7_3 Depth=2 +; LA64-NEXT: bne $a2, $a3, .LBB7_4 +; LA64-NEXT: # %bb.3: # %atomicrmw.start +; LA64-NEXT: # in Loop: Header=BB7_2 Depth=2 ; LA64-NEXT: move $a5, $a4 ; LA64-NEXT: sc.d $a5, $a0, 0 -; LA64-NEXT: beq $a5, $zero, .LBB7_3 -; LA64-NEXT: b .LBB7_6 -; LA64-NEXT: .LBB7_5: # %atomicrmw.start +; LA64-NEXT: beq $a5, $zero, .LBB7_2 +; LA64-NEXT: b .LBB7_5 +; LA64-NEXT: .LBB7_4: # %atomicrmw.start ; LA64-NEXT: # in Loop: Header=BB7_1 Depth=1 ; LA64-NEXT: dbar 20 -; LA64-NEXT: .LBB7_6: # %atomicrmw.start +; LA64-NEXT: .LBB7_5: # %atomicrmw.start ; LA64-NEXT: # in Loop: Header=BB7_1 Depth=1 ; LA64-NEXT: bne $a2, $a3, .LBB7_1 -; LA64-NEXT: # %bb.2: # %atomicrmw.end +; LA64-NEXT: # %bb.6: # %atomicrmw.end ; LA64-NEXT: move $a0, $a2 ; LA64-NEXT: ret %result = atomicrmw udec_wrap ptr %ptr, i64 %val seq_cst diff --git a/llvm/test/CodeGen/LoongArch/branch-relaxation-spill-32.ll b/llvm/test/CodeGen/LoongArch/branch-relaxation-spill-32.ll index e37863efdf5f3..c94dd0bb7691e 100644 --- a/llvm/test/CodeGen/LoongArch/branch-relaxation-spill-32.ll +++ b/llvm/test/CodeGen/LoongArch/branch-relaxation-spill-32.ll @@ -120,21 +120,21 @@ define void @relax_b28_spill() { ; CHECK-NEXT: #APP ; CHECK-NEXT: addi.w $s8, $zero, 1 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: beq $s7, $s8, .LBB0_1 -; CHECK-NEXT: # %bb.4: +; CHECK-NEXT: beq $s7, $s8, .LBB0_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: st.w $t8, $sp, 0 # 4-byte Folded Spill ; CHECK-NEXT: .Lpcadd_hi0: -; CHECK-NEXT: pcaddu12i $t8, %pcadd_hi20(.LBB0_5) +; CHECK-NEXT: pcaddu12i $t8, %pcadd_hi20(.LBB0_3) ; CHECK-NEXT: addi.w $t8, $t8, %pcadd_lo12(.Lpcadd_hi0) ; CHECK-NEXT: jr $t8 -; CHECK-NEXT: .LBB0_1: # %iftrue +; CHECK-NEXT: .LBB0_2: # %iftrue ; CHECK-NEXT: #APP ; CHECK-NEXT: .space 536870912 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: b .LBB0_3 -; CHECK-NEXT: .LBB0_5: # %iffalse +; CHECK-NEXT: b .LBB0_5 +; CHECK-NEXT: .LBB0_3: # %iffalse ; CHECK-NEXT: ld.w $t8, $sp, 0 # 4-byte Folded Reload -; CHECK-NEXT: # %bb.2: # %iffalse +; CHECK-NEXT: # %bb.4: # %iffalse ; CHECK-NEXT: #APP ; CHECK-NEXT: # reg use $zero ; CHECK-NEXT: #NO_APP @@ -225,7 +225,7 @@ define void @relax_b28_spill() { ; CHECK-NEXT: #APP ; CHECK-NEXT: # reg use $s8 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: .LBB0_3: # %iftrue +; CHECK-NEXT: .LBB0_5: # %iftrue ; CHECK-NEXT: ld.w $s8, $sp, 4 # 4-byte Folded Reload ; CHECK-NEXT: ld.w $s7, $sp, 8 # 4-byte Folded Reload ; CHECK-NEXT: ld.w $s6, $sp, 12 # 4-byte Folded Reload diff --git a/llvm/test/CodeGen/LoongArch/branch-relaxation-spill-64.ll b/llvm/test/CodeGen/LoongArch/branch-relaxation-spill-64.ll index a161fe97da9b0..bd7bb4205c3e0 100644 --- a/llvm/test/CodeGen/LoongArch/branch-relaxation-spill-64.ll +++ b/llvm/test/CodeGen/LoongArch/branch-relaxation-spill-64.ll @@ -120,20 +120,20 @@ define void @relax_b28_spill() { ; CHECK-NEXT: #APP ; CHECK-NEXT: addi.d $s8, $zero, 1 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: beq $s7, $s8, .LBB0_1 -; CHECK-NEXT: # %bb.4: -; CHECK-NEXT: st.d $t8, $sp, 0 -; CHECK-NEXT: pcalau12i $t8, %pc_hi20(.LBB0_5) -; CHECK-NEXT: addi.d $t8, $t8, %pc_lo12(.LBB0_5) +; CHECK-NEXT: beq $s7, $s8, .LBB0_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: st.d $t8, $sp, 0 # 8-byte Folded Spill +; CHECK-NEXT: pcalau12i $t8, %pc_hi20(.LBB0_3) +; CHECK-NEXT: addi.d $t8, $t8, %pc_lo12(.LBB0_3) ; CHECK-NEXT: jr $t8 -; CHECK-NEXT: .LBB0_1: # %iftrue +; CHECK-NEXT: .LBB0_2: # %iftrue ; CHECK-NEXT: #APP ; CHECK-NEXT: .space 536870912 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: b .LBB0_3 -; CHECK-NEXT: .LBB0_5: # %iffalse -; CHECK-NEXT: ld.d $t8, $sp, 0 -; CHECK-NEXT: # %bb.2: # %iffalse +; CHECK-NEXT: b .LBB0_5 +; CHECK-NEXT: .LBB0_3: # %iffalse +; CHECK-NEXT: ld.d $t8, $sp, 0 # 8-byte Folded Reload +; CHECK-NEXT: # %bb.4: # %iffalse ; CHECK-NEXT: #APP ; CHECK-NEXT: # reg use $zero ; CHECK-NEXT: #NO_APP @@ -224,7 +224,7 @@ define void @relax_b28_spill() { ; CHECK-NEXT: #APP ; CHECK-NEXT: # reg use $s8 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: .LBB0_3: # %iftrue +; CHECK-NEXT: .LBB0_5: # %iftrue ; CHECK-NEXT: ld.d $s8, $sp, 8 # 8-byte Folded Reload ; CHECK-NEXT: ld.d $s7, $sp, 16 # 8-byte Folded Reload ; CHECK-NEXT: ld.d $s6, $sp, 24 # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/LoongArch/branch-relaxation.ll b/llvm/test/CodeGen/LoongArch/branch-relaxation.ll index ffeaa5283ada8..99ff2917aaa23 100644 --- a/llvm/test/CodeGen/LoongArch/branch-relaxation.ll +++ b/llvm/test/CodeGen/LoongArch/branch-relaxation.ll @@ -117,20 +117,20 @@ define i32 @relax_b28(i1 %a) { ; LA32R-NEXT: addi.w $sp, $sp, -16 ; LA32R-NEXT: .cfi_def_cfa_offset 16 ; LA32R-NEXT: andi $a0, $a0, 1 -; LA32R-NEXT: bne $a0, $zero, .LBB2_1 -; LA32R-NEXT: # %bb.3: +; LA32R-NEXT: bne $a0, $zero, .LBB2_2 +; LA32R-NEXT: # %bb.1: ; LA32R-NEXT: .Lpcadd_hi0: -; LA32R-NEXT: pcaddu12i $a0, %pcadd_hi20(.LBB2_2) +; LA32R-NEXT: pcaddu12i $a0, %pcadd_hi20(.LBB2_3) ; LA32R-NEXT: addi.w $a0, $a0, %pcadd_lo12(.Lpcadd_hi0) ; LA32R-NEXT: jr $a0 -; LA32R-NEXT: .LBB2_1: # %iftrue +; LA32R-NEXT: .LBB2_2: # %iftrue ; LA32R-NEXT: ori $a0, $zero, 1 ; LA32R-NEXT: #APP ; LA32R-NEXT: .space 536870912 ; LA32R-NEXT: #NO_APP ; LA32R-NEXT: addi.w $sp, $sp, 16 ; LA32R-NEXT: ret -; LA32R-NEXT: .LBB2_2: # %iffalse +; LA32R-NEXT: .LBB2_3: # %iffalse ; LA32R-NEXT: move $a0, $zero ; LA32R-NEXT: addi.w $sp, $sp, 16 ; LA32R-NEXT: ret @@ -140,19 +140,19 @@ define i32 @relax_b28(i1 %a) { ; LA32S-NEXT: addi.w $sp, $sp, -16 ; LA32S-NEXT: .cfi_def_cfa_offset 16 ; LA32S-NEXT: andi $a0, $a0, 1 -; LA32S-NEXT: bnez $a0, .LBB2_1 -; LA32S-NEXT: # %bb.3: -; LA32S-NEXT: pcalau12i $a0, %pc_hi20(.LBB2_2) -; LA32S-NEXT: addi.w $a0, $a0, %pc_lo12(.LBB2_2) +; LA32S-NEXT: bnez $a0, .LBB2_2 +; LA32S-NEXT: # %bb.1: +; LA32S-NEXT: pcalau12i $a0, %pc_hi20(.LBB2_3) +; LA32S-NEXT: addi.w $a0, $a0, %pc_lo12(.LBB2_3) ; LA32S-NEXT: jr $a0 -; LA32S-NEXT: .LBB2_1: # %iftrue +; LA32S-NEXT: .LBB2_2: # %iftrue ; LA32S-NEXT: ori $a0, $zero, 1 ; LA32S-NEXT: #APP ; LA32S-NEXT: .space 536870912 ; LA32S-NEXT: #NO_APP ; LA32S-NEXT: addi.w $sp, $sp, 16 ; LA32S-NEXT: ret -; LA32S-NEXT: .LBB2_2: # %iffalse +; LA32S-NEXT: .LBB2_3: # %iffalse ; LA32S-NEXT: move $a0, $zero ; LA32S-NEXT: addi.w $sp, $sp, 16 ; LA32S-NEXT: ret @@ -162,19 +162,19 @@ define i32 @relax_b28(i1 %a) { ; LA64-NEXT: addi.d $sp, $sp, -16 ; LA64-NEXT: .cfi_def_cfa_offset 16 ; LA64-NEXT: andi $a0, $a0, 1 -; LA64-NEXT: bnez $a0, .LBB2_1 -; LA64-NEXT: # %bb.3: -; LA64-NEXT: pcalau12i $a0, %pc_hi20(.LBB2_2) -; LA64-NEXT: addi.d $a0, $a0, %pc_lo12(.LBB2_2) +; LA64-NEXT: bnez $a0, .LBB2_2 +; LA64-NEXT: # %bb.1: +; LA64-NEXT: pcalau12i $a0, %pc_hi20(.LBB2_3) +; LA64-NEXT: addi.d $a0, $a0, %pc_lo12(.LBB2_3) ; LA64-NEXT: jr $a0 -; LA64-NEXT: .LBB2_1: # %iftrue +; LA64-NEXT: .LBB2_2: # %iftrue ; LA64-NEXT: ori $a0, $zero, 1 ; LA64-NEXT: #APP ; LA64-NEXT: .space 536870912 ; LA64-NEXT: #NO_APP ; LA64-NEXT: addi.d $sp, $sp, 16 ; LA64-NEXT: ret -; LA64-NEXT: .LBB2_2: # %iffalse +; LA64-NEXT: .LBB2_3: # %iffalse ; LA64-NEXT: move $a0, $zero ; LA64-NEXT: addi.d $sp, $sp, 16 ; LA64-NEXT: ret diff --git a/llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw-fp.ll b/llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw-fp.ll index 0d0fb213539ab..0e0cbbfcb4af4 100644 --- a/llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw-fp.ll +++ b/llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw-fp.ll @@ -11,29 +11,29 @@ define float @float_fadd_acquire(ptr %p) nounwind { ; LA64F-NEXT: .p2align 4, , 16 ; LA64F-NEXT: .LBB0_1: # %atomicrmw.start ; LA64F-NEXT: # =>This Loop Header: Depth=1 -; LA64F-NEXT: # Child Loop BB0_3 Depth 2 +; LA64F-NEXT: # Child Loop BB0_2 Depth 2 ; LA64F-NEXT: fadd.s $fa2, $fa0, $fa1 ; LA64F-NEXT: movfr2gr.s $a1, $fa2 ; LA64F-NEXT: movfr2gr.s $a2, $fa0 -; LA64F-NEXT: .LBB0_3: # %atomicrmw.start +; LA64F-NEXT: .LBB0_2: # %atomicrmw.start ; LA64F-NEXT: # Parent Loop BB0_1 Depth=1 ; LA64F-NEXT: # => This Inner Loop Header: Depth=2 ; LA64F-NEXT: ll.w $a3, $a0, 0 -; LA64F-NEXT: bne $a3, $a2, .LBB0_5 -; LA64F-NEXT: # %bb.4: # %atomicrmw.start -; LA64F-NEXT: # in Loop: Header=BB0_3 Depth=2 +; LA64F-NEXT: bne $a3, $a2, .LBB0_4 +; LA64F-NEXT: # %bb.3: # %atomicrmw.start +; LA64F-NEXT: # in Loop: Header=BB0_2 Depth=2 ; LA64F-NEXT: move $a4, $a1 ; LA64F-NEXT: sc.w $a4, $a0, 0 -; LA64F-NEXT: beq $a4, $zero, .LBB0_3 -; LA64F-NEXT: b .LBB0_6 -; LA64F-NEXT: .LBB0_5: # %atomicrmw.start +; LA64F-NEXT: beq $a4, $zero, .LBB0_2 +; LA64F-NEXT: b .LBB0_5 +; LA64F-NEXT: .LBB0_4: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB0_1 Depth=1 ; LA64F-NEXT: dbar 20 -; LA64F-NEXT: .LBB0_6: # %atomicrmw.start +; LA64F-NEXT: .LBB0_5: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB0_1 Depth=1 ; LA64F-NEXT: movgr2fr.w $fa0, $a3 ; LA64F-NEXT: bne $a3, $a2, .LBB0_1 -; LA64F-NEXT: # %bb.2: # %atomicrmw.end +; LA64F-NEXT: # %bb.6: # %atomicrmw.end ; LA64F-NEXT: ret ; ; LA64D-LABEL: float_fadd_acquire: @@ -43,29 +43,29 @@ define float @float_fadd_acquire(ptr %p) nounwind { ; LA64D-NEXT: .p2align 4, , 16 ; LA64D-NEXT: .LBB0_1: # %atomicrmw.start ; LA64D-NEXT: # =>This Loop Header: Depth=1 -; LA64D-NEXT: # Child Loop BB0_3 Depth 2 +; LA64D-NEXT: # Child Loop BB0_2 Depth 2 ; LA64D-NEXT: fadd.s $fa2, $fa0, $fa1 ; LA64D-NEXT: movfr2gr.s $a1, $fa2 ; LA64D-NEXT: movfr2gr.s $a2, $fa0 -; LA64D-NEXT: .LBB0_3: # %atomicrmw.start +; LA64D-NEXT: .LBB0_2: # %atomicrmw.start ; LA64D-NEXT: # Parent Loop BB0_1 Depth=1 ; LA64D-NEXT: # => This Inner Loop Header: Depth=2 ; LA64D-NEXT: ll.w $a3, $a0, 0 -; LA64D-NEXT: bne $a3, $a2, .LBB0_5 -; LA64D-NEXT: # %bb.4: # %atomicrmw.start -; LA64D-NEXT: # in Loop: Header=BB0_3 Depth=2 +; LA64D-NEXT: bne $a3, $a2, .LBB0_4 +; LA64D-NEXT: # %bb.3: # %atomicrmw.start +; LA64D-NEXT: # in Loop: Header=BB0_2 Depth=2 ; LA64D-NEXT: move $a4, $a1 ; LA64D-NEXT: sc.w $a4, $a0, 0 -; LA64D-NEXT: beq $a4, $zero, .LBB0_3 -; LA64D-NEXT: b .LBB0_6 -; LA64D-NEXT: .LBB0_5: # %atomicrmw.start +; LA64D-NEXT: beq $a4, $zero, .LBB0_2 +; LA64D-NEXT: b .LBB0_5 +; LA64D-NEXT: .LBB0_4: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB0_1 Depth=1 ; LA64D-NEXT: dbar 20 -; LA64D-NEXT: .LBB0_6: # %atomicrmw.start +; LA64D-NEXT: .LBB0_5: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB0_1 Depth=1 ; LA64D-NEXT: movgr2fr.w $fa0, $a3 ; LA64D-NEXT: bne $a3, $a2, .LBB0_1 -; LA64D-NEXT: # %bb.2: # %atomicrmw.end +; LA64D-NEXT: # %bb.6: # %atomicrmw.end ; LA64D-NEXT: ret %v = atomicrmw fadd ptr %p, float 1.0 acquire, align 4 ret float %v @@ -80,29 +80,29 @@ define float @float_fsub_acquire(ptr %p) nounwind { ; LA64F-NEXT: .p2align 4, , 16 ; LA64F-NEXT: .LBB1_1: # %atomicrmw.start ; LA64F-NEXT: # =>This Loop Header: Depth=1 -; LA64F-NEXT: # Child Loop BB1_3 Depth 2 +; LA64F-NEXT: # Child Loop BB1_2 Depth 2 ; LA64F-NEXT: fadd.s $fa2, $fa0, $fa1 ; LA64F-NEXT: movfr2gr.s $a1, $fa2 ; LA64F-NEXT: movfr2gr.s $a2, $fa0 -; LA64F-NEXT: .LBB1_3: # %atomicrmw.start +; LA64F-NEXT: .LBB1_2: # %atomicrmw.start ; LA64F-NEXT: # Parent Loop BB1_1 Depth=1 ; LA64F-NEXT: # => This Inner Loop Header: Depth=2 ; LA64F-NEXT: ll.w $a3, $a0, 0 -; LA64F-NEXT: bne $a3, $a2, .LBB1_5 -; LA64F-NEXT: # %bb.4: # %atomicrmw.start -; LA64F-NEXT: # in Loop: Header=BB1_3 Depth=2 +; LA64F-NEXT: bne $a3, $a2, .LBB1_4 +; LA64F-NEXT: # %bb.3: # %atomicrmw.start +; LA64F-NEXT: # in Loop: Header=BB1_2 Depth=2 ; LA64F-NEXT: move $a4, $a1 ; LA64F-NEXT: sc.w $a4, $a0, 0 -; LA64F-NEXT: beq $a4, $zero, .LBB1_3 -; LA64F-NEXT: b .LBB1_6 -; LA64F-NEXT: .LBB1_5: # %atomicrmw.start +; LA64F-NEXT: beq $a4, $zero, .LBB1_2 +; LA64F-NEXT: b .LBB1_5 +; LA64F-NEXT: .LBB1_4: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB1_1 Depth=1 ; LA64F-NEXT: dbar 20 -; LA64F-NEXT: .LBB1_6: # %atomicrmw.start +; LA64F-NEXT: .LBB1_5: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB1_1 Depth=1 ; LA64F-NEXT: movgr2fr.w $fa0, $a3 ; LA64F-NEXT: bne $a3, $a2, .LBB1_1 -; LA64F-NEXT: # %bb.2: # %atomicrmw.end +; LA64F-NEXT: # %bb.6: # %atomicrmw.end ; LA64F-NEXT: ret ; ; LA64D-LABEL: float_fsub_acquire: @@ -112,29 +112,29 @@ define float @float_fsub_acquire(ptr %p) nounwind { ; LA64D-NEXT: .p2align 4, , 16 ; LA64D-NEXT: .LBB1_1: # %atomicrmw.start ; LA64D-NEXT: # =>This Loop Header: Depth=1 -; LA64D-NEXT: # Child Loop BB1_3 Depth 2 +; LA64D-NEXT: # Child Loop BB1_2 Depth 2 ; LA64D-NEXT: fadd.s $fa2, $fa0, $fa1 ; LA64D-NEXT: movfr2gr.s $a1, $fa2 ; LA64D-NEXT: movfr2gr.s $a2, $fa0 -; LA64D-NEXT: .LBB1_3: # %atomicrmw.start +; LA64D-NEXT: .LBB1_2: # %atomicrmw.start ; LA64D-NEXT: # Parent Loop BB1_1 Depth=1 ; LA64D-NEXT: # => This Inner Loop Header: Depth=2 ; LA64D-NEXT: ll.w $a3, $a0, 0 -; LA64D-NEXT: bne $a3, $a2, .LBB1_5 -; LA64D-NEXT: # %bb.4: # %atomicrmw.start -; LA64D-NEXT: # in Loop: Header=BB1_3 Depth=2 +; LA64D-NEXT: bne $a3, $a2, .LBB1_4 +; LA64D-NEXT: # %bb.3: # %atomicrmw.start +; LA64D-NEXT: # in Loop: Header=BB1_2 Depth=2 ; LA64D-NEXT: move $a4, $a1 ; LA64D-NEXT: sc.w $a4, $a0, 0 -; LA64D-NEXT: beq $a4, $zero, .LBB1_3 -; LA64D-NEXT: b .LBB1_6 -; LA64D-NEXT: .LBB1_5: # %atomicrmw.start +; LA64D-NEXT: beq $a4, $zero, .LBB1_2 +; LA64D-NEXT: b .LBB1_5 +; LA64D-NEXT: .LBB1_4: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB1_1 Depth=1 ; LA64D-NEXT: dbar 20 -; LA64D-NEXT: .LBB1_6: # %atomicrmw.start +; LA64D-NEXT: .LBB1_5: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB1_1 Depth=1 ; LA64D-NEXT: movgr2fr.w $fa0, $a3 ; LA64D-NEXT: bne $a3, $a2, .LBB1_1 -; LA64D-NEXT: # %bb.2: # %atomicrmw.end +; LA64D-NEXT: # %bb.6: # %atomicrmw.end ; LA64D-NEXT: ret %v = atomicrmw fsub ptr %p, float 1.0 acquire, align 4 ret float %v @@ -149,29 +149,29 @@ define float @float_fmin_acquire(ptr %p) nounwind { ; LA64F-NEXT: .p2align 4, , 16 ; LA64F-NEXT: .LBB2_1: # %atomicrmw.start ; LA64F-NEXT: # =>This Loop Header: Depth=1 -; LA64F-NEXT: # Child Loop BB2_3 Depth 2 +; LA64F-NEXT: # Child Loop BB2_2 Depth 2 ; LA64F-NEXT: fmin.s $fa2, $fa0, $fa1 ; LA64F-NEXT: movfr2gr.s $a1, $fa2 ; LA64F-NEXT: movfr2gr.s $a2, $fa0 -; LA64F-NEXT: .LBB2_3: # %atomicrmw.start +; LA64F-NEXT: .LBB2_2: # %atomicrmw.start ; LA64F-NEXT: # Parent Loop BB2_1 Depth=1 ; LA64F-NEXT: # => This Inner Loop Header: Depth=2 ; LA64F-NEXT: ll.w $a3, $a0, 0 -; LA64F-NEXT: bne $a3, $a2, .LBB2_5 -; LA64F-NEXT: # %bb.4: # %atomicrmw.start -; LA64F-NEXT: # in Loop: Header=BB2_3 Depth=2 +; LA64F-NEXT: bne $a3, $a2, .LBB2_4 +; LA64F-NEXT: # %bb.3: # %atomicrmw.start +; LA64F-NEXT: # in Loop: Header=BB2_2 Depth=2 ; LA64F-NEXT: move $a4, $a1 ; LA64F-NEXT: sc.w $a4, $a0, 0 -; LA64F-NEXT: beq $a4, $zero, .LBB2_3 -; LA64F-NEXT: b .LBB2_6 -; LA64F-NEXT: .LBB2_5: # %atomicrmw.start +; LA64F-NEXT: beq $a4, $zero, .LBB2_2 +; LA64F-NEXT: b .LBB2_5 +; LA64F-NEXT: .LBB2_4: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB2_1 Depth=1 ; LA64F-NEXT: dbar 20 -; LA64F-NEXT: .LBB2_6: # %atomicrmw.start +; LA64F-NEXT: .LBB2_5: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB2_1 Depth=1 ; LA64F-NEXT: movgr2fr.w $fa0, $a3 ; LA64F-NEXT: bne $a3, $a2, .LBB2_1 -; LA64F-NEXT: # %bb.2: # %atomicrmw.end +; LA64F-NEXT: # %bb.6: # %atomicrmw.end ; LA64F-NEXT: ret ; ; LA64D-LABEL: float_fmin_acquire: @@ -181,29 +181,29 @@ define float @float_fmin_acquire(ptr %p) nounwind { ; LA64D-NEXT: .p2align 4, , 16 ; LA64D-NEXT: .LBB2_1: # %atomicrmw.start ; LA64D-NEXT: # =>This Loop Header: Depth=1 -; LA64D-NEXT: # Child Loop BB2_3 Depth 2 +; LA64D-NEXT: # Child Loop BB2_2 Depth 2 ; LA64D-NEXT: fmin.s $fa2, $fa0, $fa1 ; LA64D-NEXT: movfr2gr.s $a1, $fa2 ; LA64D-NEXT: movfr2gr.s $a2, $fa0 -; LA64D-NEXT: .LBB2_3: # %atomicrmw.start +; LA64D-NEXT: .LBB2_2: # %atomicrmw.start ; LA64D-NEXT: # Parent Loop BB2_1 Depth=1 ; LA64D-NEXT: # => This Inner Loop Header: Depth=2 ; LA64D-NEXT: ll.w $a3, $a0, 0 -; LA64D-NEXT: bne $a3, $a2, .LBB2_5 -; LA64D-NEXT: # %bb.4: # %atomicrmw.start -; LA64D-NEXT: # in Loop: Header=BB2_3 Depth=2 +; LA64D-NEXT: bne $a3, $a2, .LBB2_4 +; LA64D-NEXT: # %bb.3: # %atomicrmw.start +; LA64D-NEXT: # in Loop: Header=BB2_2 Depth=2 ; LA64D-NEXT: move $a4, $a1 ; LA64D-NEXT: sc.w $a4, $a0, 0 -; LA64D-NEXT: beq $a4, $zero, .LBB2_3 -; LA64D-NEXT: b .LBB2_6 -; LA64D-NEXT: .LBB2_5: # %atomicrmw.start +; LA64D-NEXT: beq $a4, $zero, .LBB2_2 +; LA64D-NEXT: b .LBB2_5 +; LA64D-NEXT: .LBB2_4: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB2_1 Depth=1 ; LA64D-NEXT: dbar 20 -; LA64D-NEXT: .LBB2_6: # %atomicrmw.start +; LA64D-NEXT: .LBB2_5: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB2_1 Depth=1 ; LA64D-NEXT: movgr2fr.w $fa0, $a3 ; LA64D-NEXT: bne $a3, $a2, .LBB2_1 -; LA64D-NEXT: # %bb.2: # %atomicrmw.end +; LA64D-NEXT: # %bb.6: # %atomicrmw.end ; LA64D-NEXT: ret %v = atomicrmw fmin ptr %p, float 1.0 acquire, align 4 ret float %v @@ -218,29 +218,29 @@ define float @float_fmax_acquire(ptr %p) nounwind { ; LA64F-NEXT: .p2align 4, , 16 ; LA64F-NEXT: .LBB3_1: # %atomicrmw.start ; LA64F-NEXT: # =>This Loop Header: Depth=1 -; LA64F-NEXT: # Child Loop BB3_3 Depth 2 +; LA64F-NEXT: # Child Loop BB3_2 Depth 2 ; LA64F-NEXT: fmax.s $fa2, $fa0, $fa1 ; LA64F-NEXT: movfr2gr.s $a1, $fa2 ; LA64F-NEXT: movfr2gr.s $a2, $fa0 -; LA64F-NEXT: .LBB3_3: # %atomicrmw.start +; LA64F-NEXT: .LBB3_2: # %atomicrmw.start ; LA64F-NEXT: # Parent Loop BB3_1 Depth=1 ; LA64F-NEXT: # => This Inner Loop Header: Depth=2 ; LA64F-NEXT: ll.w $a3, $a0, 0 -; LA64F-NEXT: bne $a3, $a2, .LBB3_5 -; LA64F-NEXT: # %bb.4: # %atomicrmw.start -; LA64F-NEXT: # in Loop: Header=BB3_3 Depth=2 +; LA64F-NEXT: bne $a3, $a2, .LBB3_4 +; LA64F-NEXT: # %bb.3: # %atomicrmw.start +; LA64F-NEXT: # in Loop: Header=BB3_2 Depth=2 ; LA64F-NEXT: move $a4, $a1 ; LA64F-NEXT: sc.w $a4, $a0, 0 -; LA64F-NEXT: beq $a4, $zero, .LBB3_3 -; LA64F-NEXT: b .LBB3_6 -; LA64F-NEXT: .LBB3_5: # %atomicrmw.start +; LA64F-NEXT: beq $a4, $zero, .LBB3_2 +; LA64F-NEXT: b .LBB3_5 +; LA64F-NEXT: .LBB3_4: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB3_1 Depth=1 ; LA64F-NEXT: dbar 20 -; LA64F-NEXT: .LBB3_6: # %atomicrmw.start +; LA64F-NEXT: .LBB3_5: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB3_1 Depth=1 ; LA64F-NEXT: movgr2fr.w $fa0, $a3 ; LA64F-NEXT: bne $a3, $a2, .LBB3_1 -; LA64F-NEXT: # %bb.2: # %atomicrmw.end +; LA64F-NEXT: # %bb.6: # %atomicrmw.end ; LA64F-NEXT: ret ; ; LA64D-LABEL: float_fmax_acquire: @@ -250,29 +250,29 @@ define float @float_fmax_acquire(ptr %p) nounwind { ; LA64D-NEXT: .p2align 4, , 16 ; LA64D-NEXT: .LBB3_1: # %atomicrmw.start ; LA64D-NEXT: # =>This Loop Header: Depth=1 -; LA64D-NEXT: # Child Loop BB3_3 Depth 2 +; LA64D-NEXT: # Child Loop BB3_2 Depth 2 ; LA64D-NEXT: fmax.s $fa2, $fa0, $fa1 ; LA64D-NEXT: movfr2gr.s $a1, $fa2 ; LA64D-NEXT: movfr2gr.s $a2, $fa0 -; LA64D-NEXT: .LBB3_3: # %atomicrmw.start +; LA64D-NEXT: .LBB3_2: # %atomicrmw.start ; LA64D-NEXT: # Parent Loop BB3_1 Depth=1 ; LA64D-NEXT: # => This Inner Loop Header: Depth=2 ; LA64D-NEXT: ll.w $a3, $a0, 0 -; LA64D-NEXT: bne $a3, $a2, .LBB3_5 -; LA64D-NEXT: # %bb.4: # %atomicrmw.start -; LA64D-NEXT: # in Loop: Header=BB3_3 Depth=2 +; LA64D-NEXT: bne $a3, $a2, .LBB3_4 +; LA64D-NEXT: # %bb.3: # %atomicrmw.start +; LA64D-NEXT: # in Loop: Header=BB3_2 Depth=2 ; LA64D-NEXT: move $a4, $a1 ; LA64D-NEXT: sc.w $a4, $a0, 0 -; LA64D-NEXT: beq $a4, $zero, .LBB3_3 -; LA64D-NEXT: b .LBB3_6 -; LA64D-NEXT: .LBB3_5: # %atomicrmw.start +; LA64D-NEXT: beq $a4, $zero, .LBB3_2 +; LA64D-NEXT: b .LBB3_5 +; LA64D-NEXT: .LBB3_4: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB3_1 Depth=1 ; LA64D-NEXT: dbar 20 -; LA64D-NEXT: .LBB3_6: # %atomicrmw.start +; LA64D-NEXT: .LBB3_5: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB3_1 Depth=1 ; LA64D-NEXT: movgr2fr.w $fa0, $a3 ; LA64D-NEXT: bne $a3, $a2, .LBB3_1 -; LA64D-NEXT: # %bb.2: # %atomicrmw.end +; LA64D-NEXT: # %bb.6: # %atomicrmw.end ; LA64D-NEXT: ret %v = atomicrmw fmax ptr %p, float 1.0 acquire, align 4 ret float %v @@ -575,29 +575,29 @@ define float @float_fadd_release(ptr %p) nounwind { ; LA64F-NEXT: .p2align 4, , 16 ; LA64F-NEXT: .LBB8_1: # %atomicrmw.start ; LA64F-NEXT: # =>This Loop Header: Depth=1 -; LA64F-NEXT: # Child Loop BB8_3 Depth 2 +; LA64F-NEXT: # Child Loop BB8_2 Depth 2 ; LA64F-NEXT: fadd.s $fa2, $fa0, $fa1 ; LA64F-NEXT: movfr2gr.s $a1, $fa2 ; LA64F-NEXT: movfr2gr.s $a2, $fa0 -; LA64F-NEXT: .LBB8_3: # %atomicrmw.start +; LA64F-NEXT: .LBB8_2: # %atomicrmw.start ; LA64F-NEXT: # Parent Loop BB8_1 Depth=1 ; LA64F-NEXT: # => This Inner Loop Header: Depth=2 ; LA64F-NEXT: ll.w $a3, $a0, 0 -; LA64F-NEXT: bne $a3, $a2, .LBB8_5 -; LA64F-NEXT: # %bb.4: # %atomicrmw.start -; LA64F-NEXT: # in Loop: Header=BB8_3 Depth=2 +; LA64F-NEXT: bne $a3, $a2, .LBB8_4 +; LA64F-NEXT: # %bb.3: # %atomicrmw.start +; LA64F-NEXT: # in Loop: Header=BB8_2 Depth=2 ; LA64F-NEXT: move $a4, $a1 ; LA64F-NEXT: sc.w $a4, $a0, 0 -; LA64F-NEXT: beq $a4, $zero, .LBB8_3 -; LA64F-NEXT: b .LBB8_6 -; LA64F-NEXT: .LBB8_5: # %atomicrmw.start +; LA64F-NEXT: beq $a4, $zero, .LBB8_2 +; LA64F-NEXT: b .LBB8_5 +; LA64F-NEXT: .LBB8_4: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB8_1 Depth=1 ; LA64F-NEXT: dbar 1792 -; LA64F-NEXT: .LBB8_6: # %atomicrmw.start +; LA64F-NEXT: .LBB8_5: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB8_1 Depth=1 ; LA64F-NEXT: movgr2fr.w $fa0, $a3 ; LA64F-NEXT: bne $a3, $a2, .LBB8_1 -; LA64F-NEXT: # %bb.2: # %atomicrmw.end +; LA64F-NEXT: # %bb.6: # %atomicrmw.end ; LA64F-NEXT: ret ; ; LA64D-LABEL: float_fadd_release: @@ -607,29 +607,29 @@ define float @float_fadd_release(ptr %p) nounwind { ; LA64D-NEXT: .p2align 4, , 16 ; LA64D-NEXT: .LBB8_1: # %atomicrmw.start ; LA64D-NEXT: # =>This Loop Header: Depth=1 -; LA64D-NEXT: # Child Loop BB8_3 Depth 2 +; LA64D-NEXT: # Child Loop BB8_2 Depth 2 ; LA64D-NEXT: fadd.s $fa2, $fa0, $fa1 ; LA64D-NEXT: movfr2gr.s $a1, $fa2 ; LA64D-NEXT: movfr2gr.s $a2, $fa0 -; LA64D-NEXT: .LBB8_3: # %atomicrmw.start +; LA64D-NEXT: .LBB8_2: # %atomicrmw.start ; LA64D-NEXT: # Parent Loop BB8_1 Depth=1 ; LA64D-NEXT: # => This Inner Loop Header: Depth=2 ; LA64D-NEXT: ll.w $a3, $a0, 0 -; LA64D-NEXT: bne $a3, $a2, .LBB8_5 -; LA64D-NEXT: # %bb.4: # %atomicrmw.start -; LA64D-NEXT: # in Loop: Header=BB8_3 Depth=2 +; LA64D-NEXT: bne $a3, $a2, .LBB8_4 +; LA64D-NEXT: # %bb.3: # %atomicrmw.start +; LA64D-NEXT: # in Loop: Header=BB8_2 Depth=2 ; LA64D-NEXT: move $a4, $a1 ; LA64D-NEXT: sc.w $a4, $a0, 0 -; LA64D-NEXT: beq $a4, $zero, .LBB8_3 -; LA64D-NEXT: b .LBB8_6 -; LA64D-NEXT: .LBB8_5: # %atomicrmw.start +; LA64D-NEXT: beq $a4, $zero, .LBB8_2 +; LA64D-NEXT: b .LBB8_5 +; LA64D-NEXT: .LBB8_4: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB8_1 Depth=1 ; LA64D-NEXT: dbar 1792 -; LA64D-NEXT: .LBB8_6: # %atomicrmw.start +; LA64D-NEXT: .LBB8_5: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB8_1 Depth=1 ; LA64D-NEXT: movgr2fr.w $fa0, $a3 ; LA64D-NEXT: bne $a3, $a2, .LBB8_1 -; LA64D-NEXT: # %bb.2: # %atomicrmw.end +; LA64D-NEXT: # %bb.6: # %atomicrmw.end ; LA64D-NEXT: ret %v = atomicrmw fadd ptr %p, float 1.0 release, align 4 ret float %v @@ -644,29 +644,29 @@ define float @float_fsub_release(ptr %p) nounwind { ; LA64F-NEXT: .p2align 4, , 16 ; LA64F-NEXT: .LBB9_1: # %atomicrmw.start ; LA64F-NEXT: # =>This Loop Header: Depth=1 -; LA64F-NEXT: # Child Loop BB9_3 Depth 2 +; LA64F-NEXT: # Child Loop BB9_2 Depth 2 ; LA64F-NEXT: fadd.s $fa2, $fa0, $fa1 ; LA64F-NEXT: movfr2gr.s $a1, $fa2 ; LA64F-NEXT: movfr2gr.s $a2, $fa0 -; LA64F-NEXT: .LBB9_3: # %atomicrmw.start +; LA64F-NEXT: .LBB9_2: # %atomicrmw.start ; LA64F-NEXT: # Parent Loop BB9_1 Depth=1 ; LA64F-NEXT: # => This Inner Loop Header: Depth=2 ; LA64F-NEXT: ll.w $a3, $a0, 0 -; LA64F-NEXT: bne $a3, $a2, .LBB9_5 -; LA64F-NEXT: # %bb.4: # %atomicrmw.start -; LA64F-NEXT: # in Loop: Header=BB9_3 Depth=2 +; LA64F-NEXT: bne $a3, $a2, .LBB9_4 +; LA64F-NEXT: # %bb.3: # %atomicrmw.start +; LA64F-NEXT: # in Loop: Header=BB9_2 Depth=2 ; LA64F-NEXT: move $a4, $a1 ; LA64F-NEXT: sc.w $a4, $a0, 0 -; LA64F-NEXT: beq $a4, $zero, .LBB9_3 -; LA64F-NEXT: b .LBB9_6 -; LA64F-NEXT: .LBB9_5: # %atomicrmw.start +; LA64F-NEXT: beq $a4, $zero, .LBB9_2 +; LA64F-NEXT: b .LBB9_5 +; LA64F-NEXT: .LBB9_4: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB9_1 Depth=1 ; LA64F-NEXT: dbar 1792 -; LA64F-NEXT: .LBB9_6: # %atomicrmw.start +; LA64F-NEXT: .LBB9_5: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB9_1 Depth=1 ; LA64F-NEXT: movgr2fr.w $fa0, $a3 ; LA64F-NEXT: bne $a3, $a2, .LBB9_1 -; LA64F-NEXT: # %bb.2: # %atomicrmw.end +; LA64F-NEXT: # %bb.6: # %atomicrmw.end ; LA64F-NEXT: ret ; ; LA64D-LABEL: float_fsub_release: @@ -676,29 +676,29 @@ define float @float_fsub_release(ptr %p) nounwind { ; LA64D-NEXT: .p2align 4, , 16 ; LA64D-NEXT: .LBB9_1: # %atomicrmw.start ; LA64D-NEXT: # =>This Loop Header: Depth=1 -; LA64D-NEXT: # Child Loop BB9_3 Depth 2 +; LA64D-NEXT: # Child Loop BB9_2 Depth 2 ; LA64D-NEXT: fadd.s $fa2, $fa0, $fa1 ; LA64D-NEXT: movfr2gr.s $a1, $fa2 ; LA64D-NEXT: movfr2gr.s $a2, $fa0 -; LA64D-NEXT: .LBB9_3: # %atomicrmw.start +; LA64D-NEXT: .LBB9_2: # %atomicrmw.start ; LA64D-NEXT: # Parent Loop BB9_1 Depth=1 ; LA64D-NEXT: # => This Inner Loop Header: Depth=2 ; LA64D-NEXT: ll.w $a3, $a0, 0 -; LA64D-NEXT: bne $a3, $a2, .LBB9_5 -; LA64D-NEXT: # %bb.4: # %atomicrmw.start -; LA64D-NEXT: # in Loop: Header=BB9_3 Depth=2 +; LA64D-NEXT: bne $a3, $a2, .LBB9_4 +; LA64D-NEXT: # %bb.3: # %atomicrmw.start +; LA64D-NEXT: # in Loop: Header=BB9_2 Depth=2 ; LA64D-NEXT: move $a4, $a1 ; LA64D-NEXT: sc.w $a4, $a0, 0 -; LA64D-NEXT: beq $a4, $zero, .LBB9_3 -; LA64D-NEXT: b .LBB9_6 -; LA64D-NEXT: .LBB9_5: # %atomicrmw.start +; LA64D-NEXT: beq $a4, $zero, .LBB9_2 +; LA64D-NEXT: b .LBB9_5 +; LA64D-NEXT: .LBB9_4: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB9_1 Depth=1 ; LA64D-NEXT: dbar 1792 -; LA64D-NEXT: .LBB9_6: # %atomicrmw.start +; LA64D-NEXT: .LBB9_5: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB9_1 Depth=1 ; LA64D-NEXT: movgr2fr.w $fa0, $a3 ; LA64D-NEXT: bne $a3, $a2, .LBB9_1 -; LA64D-NEXT: # %bb.2: # %atomicrmw.end +; LA64D-NEXT: # %bb.6: # %atomicrmw.end ; LA64D-NEXT: ret %v = atomicrmw fsub ptr %p, float 1.0 release, align 4 ret float %v @@ -713,29 +713,29 @@ define float @float_fmin_release(ptr %p) nounwind { ; LA64F-NEXT: .p2align 4, , 16 ; LA64F-NEXT: .LBB10_1: # %atomicrmw.start ; LA64F-NEXT: # =>This Loop Header: Depth=1 -; LA64F-NEXT: # Child Loop BB10_3 Depth 2 +; LA64F-NEXT: # Child Loop BB10_2 Depth 2 ; LA64F-NEXT: fmin.s $fa2, $fa0, $fa1 ; LA64F-NEXT: movfr2gr.s $a1, $fa2 ; LA64F-NEXT: movfr2gr.s $a2, $fa0 -; LA64F-NEXT: .LBB10_3: # %atomicrmw.start +; LA64F-NEXT: .LBB10_2: # %atomicrmw.start ; LA64F-NEXT: # Parent Loop BB10_1 Depth=1 ; LA64F-NEXT: # => This Inner Loop Header: Depth=2 ; LA64F-NEXT: ll.w $a3, $a0, 0 -; LA64F-NEXT: bne $a3, $a2, .LBB10_5 -; LA64F-NEXT: # %bb.4: # %atomicrmw.start -; LA64F-NEXT: # in Loop: Header=BB10_3 Depth=2 +; LA64F-NEXT: bne $a3, $a2, .LBB10_4 +; LA64F-NEXT: # %bb.3: # %atomicrmw.start +; LA64F-NEXT: # in Loop: Header=BB10_2 Depth=2 ; LA64F-NEXT: move $a4, $a1 ; LA64F-NEXT: sc.w $a4, $a0, 0 -; LA64F-NEXT: beq $a4, $zero, .LBB10_3 -; LA64F-NEXT: b .LBB10_6 -; LA64F-NEXT: .LBB10_5: # %atomicrmw.start +; LA64F-NEXT: beq $a4, $zero, .LBB10_2 +; LA64F-NEXT: b .LBB10_5 +; LA64F-NEXT: .LBB10_4: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB10_1 Depth=1 ; LA64F-NEXT: dbar 1792 -; LA64F-NEXT: .LBB10_6: # %atomicrmw.start +; LA64F-NEXT: .LBB10_5: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB10_1 Depth=1 ; LA64F-NEXT: movgr2fr.w $fa0, $a3 ; LA64F-NEXT: bne $a3, $a2, .LBB10_1 -; LA64F-NEXT: # %bb.2: # %atomicrmw.end +; LA64F-NEXT: # %bb.6: # %atomicrmw.end ; LA64F-NEXT: ret ; ; LA64D-LABEL: float_fmin_release: @@ -745,29 +745,29 @@ define float @float_fmin_release(ptr %p) nounwind { ; LA64D-NEXT: .p2align 4, , 16 ; LA64D-NEXT: .LBB10_1: # %atomicrmw.start ; LA64D-NEXT: # =>This Loop Header: Depth=1 -; LA64D-NEXT: # Child Loop BB10_3 Depth 2 +; LA64D-NEXT: # Child Loop BB10_2 Depth 2 ; LA64D-NEXT: fmin.s $fa2, $fa0, $fa1 ; LA64D-NEXT: movfr2gr.s $a1, $fa2 ; LA64D-NEXT: movfr2gr.s $a2, $fa0 -; LA64D-NEXT: .LBB10_3: # %atomicrmw.start +; LA64D-NEXT: .LBB10_2: # %atomicrmw.start ; LA64D-NEXT: # Parent Loop BB10_1 Depth=1 ; LA64D-NEXT: # => This Inner Loop Header: Depth=2 ; LA64D-NEXT: ll.w $a3, $a0, 0 -; LA64D-NEXT: bne $a3, $a2, .LBB10_5 -; LA64D-NEXT: # %bb.4: # %atomicrmw.start -; LA64D-NEXT: # in Loop: Header=BB10_3 Depth=2 +; LA64D-NEXT: bne $a3, $a2, .LBB10_4 +; LA64D-NEXT: # %bb.3: # %atomicrmw.start +; LA64D-NEXT: # in Loop: Header=BB10_2 Depth=2 ; LA64D-NEXT: move $a4, $a1 ; LA64D-NEXT: sc.w $a4, $a0, 0 -; LA64D-NEXT: beq $a4, $zero, .LBB10_3 -; LA64D-NEXT: b .LBB10_6 -; LA64D-NEXT: .LBB10_5: # %atomicrmw.start +; LA64D-NEXT: beq $a4, $zero, .LBB10_2 +; LA64D-NEXT: b .LBB10_5 +; LA64D-NEXT: .LBB10_4: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB10_1 Depth=1 ; LA64D-NEXT: dbar 1792 -; LA64D-NEXT: .LBB10_6: # %atomicrmw.start +; LA64D-NEXT: .LBB10_5: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB10_1 Depth=1 ; LA64D-NEXT: movgr2fr.w $fa0, $a3 ; LA64D-NEXT: bne $a3, $a2, .LBB10_1 -; LA64D-NEXT: # %bb.2: # %atomicrmw.end +; LA64D-NEXT: # %bb.6: # %atomicrmw.end ; LA64D-NEXT: ret %v = atomicrmw fmin ptr %p, float 1.0 release, align 4 ret float %v @@ -782,29 +782,29 @@ define float @float_fmax_release(ptr %p) nounwind { ; LA64F-NEXT: .p2align 4, , 16 ; LA64F-NEXT: .LBB11_1: # %atomicrmw.start ; LA64F-NEXT: # =>This Loop Header: Depth=1 -; LA64F-NEXT: # Child Loop BB11_3 Depth 2 +; LA64F-NEXT: # Child Loop BB11_2 Depth 2 ; LA64F-NEXT: fmax.s $fa2, $fa0, $fa1 ; LA64F-NEXT: movfr2gr.s $a1, $fa2 ; LA64F-NEXT: movfr2gr.s $a2, $fa0 -; LA64F-NEXT: .LBB11_3: # %atomicrmw.start +; LA64F-NEXT: .LBB11_2: # %atomicrmw.start ; LA64F-NEXT: # Parent Loop BB11_1 Depth=1 ; LA64F-NEXT: # => This Inner Loop Header: Depth=2 ; LA64F-NEXT: ll.w $a3, $a0, 0 -; LA64F-NEXT: bne $a3, $a2, .LBB11_5 -; LA64F-NEXT: # %bb.4: # %atomicrmw.start -; LA64F-NEXT: # in Loop: Header=BB11_3 Depth=2 +; LA64F-NEXT: bne $a3, $a2, .LBB11_4 +; LA64F-NEXT: # %bb.3: # %atomicrmw.start +; LA64F-NEXT: # in Loop: Header=BB11_2 Depth=2 ; LA64F-NEXT: move $a4, $a1 ; LA64F-NEXT: sc.w $a4, $a0, 0 -; LA64F-NEXT: beq $a4, $zero, .LBB11_3 -; LA64F-NEXT: b .LBB11_6 -; LA64F-NEXT: .LBB11_5: # %atomicrmw.start +; LA64F-NEXT: beq $a4, $zero, .LBB11_2 +; LA64F-NEXT: b .LBB11_5 +; LA64F-NEXT: .LBB11_4: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB11_1 Depth=1 ; LA64F-NEXT: dbar 1792 -; LA64F-NEXT: .LBB11_6: # %atomicrmw.start +; LA64F-NEXT: .LBB11_5: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB11_1 Depth=1 ; LA64F-NEXT: movgr2fr.w $fa0, $a3 ; LA64F-NEXT: bne $a3, $a2, .LBB11_1 -; LA64F-NEXT: # %bb.2: # %atomicrmw.end +; LA64F-NEXT: # %bb.6: # %atomicrmw.end ; LA64F-NEXT: ret ; ; LA64D-LABEL: float_fmax_release: @@ -814,29 +814,29 @@ define float @float_fmax_release(ptr %p) nounwind { ; LA64D-NEXT: .p2align 4, , 16 ; LA64D-NEXT: .LBB11_1: # %atomicrmw.start ; LA64D-NEXT: # =>This Loop Header: Depth=1 -; LA64D-NEXT: # Child Loop BB11_3 Depth 2 +; LA64D-NEXT: # Child Loop BB11_2 Depth 2 ; LA64D-NEXT: fmax.s $fa2, $fa0, $fa1 ; LA64D-NEXT: movfr2gr.s $a1, $fa2 ; LA64D-NEXT: movfr2gr.s $a2, $fa0 -; LA64D-NEXT: .LBB11_3: # %atomicrmw.start +; LA64D-NEXT: .LBB11_2: # %atomicrmw.start ; LA64D-NEXT: # Parent Loop BB11_1 Depth=1 ; LA64D-NEXT: # => This Inner Loop Header: Depth=2 ; LA64D-NEXT: ll.w $a3, $a0, 0 -; LA64D-NEXT: bne $a3, $a2, .LBB11_5 -; LA64D-NEXT: # %bb.4: # %atomicrmw.start -; LA64D-NEXT: # in Loop: Header=BB11_3 Depth=2 +; LA64D-NEXT: bne $a3, $a2, .LBB11_4 +; LA64D-NEXT: # %bb.3: # %atomicrmw.start +; LA64D-NEXT: # in Loop: Header=BB11_2 Depth=2 ; LA64D-NEXT: move $a4, $a1 ; LA64D-NEXT: sc.w $a4, $a0, 0 -; LA64D-NEXT: beq $a4, $zero, .LBB11_3 -; LA64D-NEXT: b .LBB11_6 -; LA64D-NEXT: .LBB11_5: # %atomicrmw.start +; LA64D-NEXT: beq $a4, $zero, .LBB11_2 +; LA64D-NEXT: b .LBB11_5 +; LA64D-NEXT: .LBB11_4: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB11_1 Depth=1 ; LA64D-NEXT: dbar 1792 -; LA64D-NEXT: .LBB11_6: # %atomicrmw.start +; LA64D-NEXT: .LBB11_5: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB11_1 Depth=1 ; LA64D-NEXT: movgr2fr.w $fa0, $a3 ; LA64D-NEXT: bne $a3, $a2, .LBB11_1 -; LA64D-NEXT: # %bb.2: # %atomicrmw.end +; LA64D-NEXT: # %bb.6: # %atomicrmw.end ; LA64D-NEXT: ret %v = atomicrmw fmax ptr %p, float 1.0 release, align 4 ret float %v @@ -1139,29 +1139,29 @@ define float @float_fadd_acq_rel(ptr %p) nounwind { ; LA64F-NEXT: .p2align 4, , 16 ; LA64F-NEXT: .LBB16_1: # %atomicrmw.start ; LA64F-NEXT: # =>This Loop Header: Depth=1 -; LA64F-NEXT: # Child Loop BB16_3 Depth 2 +; LA64F-NEXT: # Child Loop BB16_2 Depth 2 ; LA64F-NEXT: fadd.s $fa2, $fa0, $fa1 ; LA64F-NEXT: movfr2gr.s $a1, $fa2 ; LA64F-NEXT: movfr2gr.s $a2, $fa0 -; LA64F-NEXT: .LBB16_3: # %atomicrmw.start +; LA64F-NEXT: .LBB16_2: # %atomicrmw.start ; LA64F-NEXT: # Parent Loop BB16_1 Depth=1 ; LA64F-NEXT: # => This Inner Loop Header: Depth=2 ; LA64F-NEXT: ll.w $a3, $a0, 0 -; LA64F-NEXT: bne $a3, $a2, .LBB16_5 -; LA64F-NEXT: # %bb.4: # %atomicrmw.start -; LA64F-NEXT: # in Loop: Header=BB16_3 Depth=2 +; LA64F-NEXT: bne $a3, $a2, .LBB16_4 +; LA64F-NEXT: # %bb.3: # %atomicrmw.start +; LA64F-NEXT: # in Loop: Header=BB16_2 Depth=2 ; LA64F-NEXT: move $a4, $a1 ; LA64F-NEXT: sc.w $a4, $a0, 0 -; LA64F-NEXT: beq $a4, $zero, .LBB16_3 -; LA64F-NEXT: b .LBB16_6 -; LA64F-NEXT: .LBB16_5: # %atomicrmw.start +; LA64F-NEXT: beq $a4, $zero, .LBB16_2 +; LA64F-NEXT: b .LBB16_5 +; LA64F-NEXT: .LBB16_4: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB16_1 Depth=1 ; LA64F-NEXT: dbar 20 -; LA64F-NEXT: .LBB16_6: # %atomicrmw.start +; LA64F-NEXT: .LBB16_5: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB16_1 Depth=1 ; LA64F-NEXT: movgr2fr.w $fa0, $a3 ; LA64F-NEXT: bne $a3, $a2, .LBB16_1 -; LA64F-NEXT: # %bb.2: # %atomicrmw.end +; LA64F-NEXT: # %bb.6: # %atomicrmw.end ; LA64F-NEXT: ret ; ; LA64D-LABEL: float_fadd_acq_rel: @@ -1171,29 +1171,29 @@ define float @float_fadd_acq_rel(ptr %p) nounwind { ; LA64D-NEXT: .p2align 4, , 16 ; LA64D-NEXT: .LBB16_1: # %atomicrmw.start ; LA64D-NEXT: # =>This Loop Header: Depth=1 -; LA64D-NEXT: # Child Loop BB16_3 Depth 2 +; LA64D-NEXT: # Child Loop BB16_2 Depth 2 ; LA64D-NEXT: fadd.s $fa2, $fa0, $fa1 ; LA64D-NEXT: movfr2gr.s $a1, $fa2 ; LA64D-NEXT: movfr2gr.s $a2, $fa0 -; LA64D-NEXT: .LBB16_3: # %atomicrmw.start +; LA64D-NEXT: .LBB16_2: # %atomicrmw.start ; LA64D-NEXT: # Parent Loop BB16_1 Depth=1 ; LA64D-NEXT: # => This Inner Loop Header: Depth=2 ; LA64D-NEXT: ll.w $a3, $a0, 0 -; LA64D-NEXT: bne $a3, $a2, .LBB16_5 -; LA64D-NEXT: # %bb.4: # %atomicrmw.start -; LA64D-NEXT: # in Loop: Header=BB16_3 Depth=2 +; LA64D-NEXT: bne $a3, $a2, .LBB16_4 +; LA64D-NEXT: # %bb.3: # %atomicrmw.start +; LA64D-NEXT: # in Loop: Header=BB16_2 Depth=2 ; LA64D-NEXT: move $a4, $a1 ; LA64D-NEXT: sc.w $a4, $a0, 0 -; LA64D-NEXT: beq $a4, $zero, .LBB16_3 -; LA64D-NEXT: b .LBB16_6 -; LA64D-NEXT: .LBB16_5: # %atomicrmw.start +; LA64D-NEXT: beq $a4, $zero, .LBB16_2 +; LA64D-NEXT: b .LBB16_5 +; LA64D-NEXT: .LBB16_4: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB16_1 Depth=1 ; LA64D-NEXT: dbar 20 -; LA64D-NEXT: .LBB16_6: # %atomicrmw.start +; LA64D-NEXT: .LBB16_5: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB16_1 Depth=1 ; LA64D-NEXT: movgr2fr.w $fa0, $a3 ; LA64D-NEXT: bne $a3, $a2, .LBB16_1 -; LA64D-NEXT: # %bb.2: # %atomicrmw.end +; LA64D-NEXT: # %bb.6: # %atomicrmw.end ; LA64D-NEXT: ret %v = atomicrmw fadd ptr %p, float 1.0 acq_rel, align 4 ret float %v @@ -1208,29 +1208,29 @@ define float @float_fsub_acq_rel(ptr %p) nounwind { ; LA64F-NEXT: .p2align 4, , 16 ; LA64F-NEXT: .LBB17_1: # %atomicrmw.start ; LA64F-NEXT: # =>This Loop Header: Depth=1 -; LA64F-NEXT: # Child Loop BB17_3 Depth 2 +; LA64F-NEXT: # Child Loop BB17_2 Depth 2 ; LA64F-NEXT: fadd.s $fa2, $fa0, $fa1 ; LA64F-NEXT: movfr2gr.s $a1, $fa2 ; LA64F-NEXT: movfr2gr.s $a2, $fa0 -; LA64F-NEXT: .LBB17_3: # %atomicrmw.start +; LA64F-NEXT: .LBB17_2: # %atomicrmw.start ; LA64F-NEXT: # Parent Loop BB17_1 Depth=1 ; LA64F-NEXT: # => This Inner Loop Header: Depth=2 ; LA64F-NEXT: ll.w $a3, $a0, 0 -; LA64F-NEXT: bne $a3, $a2, .LBB17_5 -; LA64F-NEXT: # %bb.4: # %atomicrmw.start -; LA64F-NEXT: # in Loop: Header=BB17_3 Depth=2 +; LA64F-NEXT: bne $a3, $a2, .LBB17_4 +; LA64F-NEXT: # %bb.3: # %atomicrmw.start +; LA64F-NEXT: # in Loop: Header=BB17_2 Depth=2 ; LA64F-NEXT: move $a4, $a1 ; LA64F-NEXT: sc.w $a4, $a0, 0 -; LA64F-NEXT: beq $a4, $zero, .LBB17_3 -; LA64F-NEXT: b .LBB17_6 -; LA64F-NEXT: .LBB17_5: # %atomicrmw.start +; LA64F-NEXT: beq $a4, $zero, .LBB17_2 +; LA64F-NEXT: b .LBB17_5 +; LA64F-NEXT: .LBB17_4: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB17_1 Depth=1 ; LA64F-NEXT: dbar 20 -; LA64F-NEXT: .LBB17_6: # %atomicrmw.start +; LA64F-NEXT: .LBB17_5: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB17_1 Depth=1 ; LA64F-NEXT: movgr2fr.w $fa0, $a3 ; LA64F-NEXT: bne $a3, $a2, .LBB17_1 -; LA64F-NEXT: # %bb.2: # %atomicrmw.end +; LA64F-NEXT: # %bb.6: # %atomicrmw.end ; LA64F-NEXT: ret ; ; LA64D-LABEL: float_fsub_acq_rel: @@ -1240,29 +1240,29 @@ define float @float_fsub_acq_rel(ptr %p) nounwind { ; LA64D-NEXT: .p2align 4, , 16 ; LA64D-NEXT: .LBB17_1: # %atomicrmw.start ; LA64D-NEXT: # =>This Loop Header: Depth=1 -; LA64D-NEXT: # Child Loop BB17_3 Depth 2 +; LA64D-NEXT: # Child Loop BB17_2 Depth 2 ; LA64D-NEXT: fadd.s $fa2, $fa0, $fa1 ; LA64D-NEXT: movfr2gr.s $a1, $fa2 ; LA64D-NEXT: movfr2gr.s $a2, $fa0 -; LA64D-NEXT: .LBB17_3: # %atomicrmw.start +; LA64D-NEXT: .LBB17_2: # %atomicrmw.start ; LA64D-NEXT: # Parent Loop BB17_1 Depth=1 ; LA64D-NEXT: # => This Inner Loop Header: Depth=2 ; LA64D-NEXT: ll.w $a3, $a0, 0 -; LA64D-NEXT: bne $a3, $a2, .LBB17_5 -; LA64D-NEXT: # %bb.4: # %atomicrmw.start -; LA64D-NEXT: # in Loop: Header=BB17_3 Depth=2 +; LA64D-NEXT: bne $a3, $a2, .LBB17_4 +; LA64D-NEXT: # %bb.3: # %atomicrmw.start +; LA64D-NEXT: # in Loop: Header=BB17_2 Depth=2 ; LA64D-NEXT: move $a4, $a1 ; LA64D-NEXT: sc.w $a4, $a0, 0 -; LA64D-NEXT: beq $a4, $zero, .LBB17_3 -; LA64D-NEXT: b .LBB17_6 -; LA64D-NEXT: .LBB17_5: # %atomicrmw.start +; LA64D-NEXT: beq $a4, $zero, .LBB17_2 +; LA64D-NEXT: b .LBB17_5 +; LA64D-NEXT: .LBB17_4: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB17_1 Depth=1 ; LA64D-NEXT: dbar 20 -; LA64D-NEXT: .LBB17_6: # %atomicrmw.start +; LA64D-NEXT: .LBB17_5: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB17_1 Depth=1 ; LA64D-NEXT: movgr2fr.w $fa0, $a3 ; LA64D-NEXT: bne $a3, $a2, .LBB17_1 -; LA64D-NEXT: # %bb.2: # %atomicrmw.end +; LA64D-NEXT: # %bb.6: # %atomicrmw.end ; LA64D-NEXT: ret %v = atomicrmw fsub ptr %p, float 1.0 acq_rel, align 4 ret float %v @@ -1277,29 +1277,29 @@ define float @float_fmin_acq_rel(ptr %p) nounwind { ; LA64F-NEXT: .p2align 4, , 16 ; LA64F-NEXT: .LBB18_1: # %atomicrmw.start ; LA64F-NEXT: # =>This Loop Header: Depth=1 -; LA64F-NEXT: # Child Loop BB18_3 Depth 2 +; LA64F-NEXT: # Child Loop BB18_2 Depth 2 ; LA64F-NEXT: fmin.s $fa2, $fa0, $fa1 ; LA64F-NEXT: movfr2gr.s $a1, $fa2 ; LA64F-NEXT: movfr2gr.s $a2, $fa0 -; LA64F-NEXT: .LBB18_3: # %atomicrmw.start +; LA64F-NEXT: .LBB18_2: # %atomicrmw.start ; LA64F-NEXT: # Parent Loop BB18_1 Depth=1 ; LA64F-NEXT: # => This Inner Loop Header: Depth=2 ; LA64F-NEXT: ll.w $a3, $a0, 0 -; LA64F-NEXT: bne $a3, $a2, .LBB18_5 -; LA64F-NEXT: # %bb.4: # %atomicrmw.start -; LA64F-NEXT: # in Loop: Header=BB18_3 Depth=2 +; LA64F-NEXT: bne $a3, $a2, .LBB18_4 +; LA64F-NEXT: # %bb.3: # %atomicrmw.start +; LA64F-NEXT: # in Loop: Header=BB18_2 Depth=2 ; LA64F-NEXT: move $a4, $a1 ; LA64F-NEXT: sc.w $a4, $a0, 0 -; LA64F-NEXT: beq $a4, $zero, .LBB18_3 -; LA64F-NEXT: b .LBB18_6 -; LA64F-NEXT: .LBB18_5: # %atomicrmw.start +; LA64F-NEXT: beq $a4, $zero, .LBB18_2 +; LA64F-NEXT: b .LBB18_5 +; LA64F-NEXT: .LBB18_4: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB18_1 Depth=1 ; LA64F-NEXT: dbar 20 -; LA64F-NEXT: .LBB18_6: # %atomicrmw.start +; LA64F-NEXT: .LBB18_5: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB18_1 Depth=1 ; LA64F-NEXT: movgr2fr.w $fa0, $a3 ; LA64F-NEXT: bne $a3, $a2, .LBB18_1 -; LA64F-NEXT: # %bb.2: # %atomicrmw.end +; LA64F-NEXT: # %bb.6: # %atomicrmw.end ; LA64F-NEXT: ret ; ; LA64D-LABEL: float_fmin_acq_rel: @@ -1309,29 +1309,29 @@ define float @float_fmin_acq_rel(ptr %p) nounwind { ; LA64D-NEXT: .p2align 4, , 16 ; LA64D-NEXT: .LBB18_1: # %atomicrmw.start ; LA64D-NEXT: # =>This Loop Header: Depth=1 -; LA64D-NEXT: # Child Loop BB18_3 Depth 2 +; LA64D-NEXT: # Child Loop BB18_2 Depth 2 ; LA64D-NEXT: fmin.s $fa2, $fa0, $fa1 ; LA64D-NEXT: movfr2gr.s $a1, $fa2 ; LA64D-NEXT: movfr2gr.s $a2, $fa0 -; LA64D-NEXT: .LBB18_3: # %atomicrmw.start +; LA64D-NEXT: .LBB18_2: # %atomicrmw.start ; LA64D-NEXT: # Parent Loop BB18_1 Depth=1 ; LA64D-NEXT: # => This Inner Loop Header: Depth=2 ; LA64D-NEXT: ll.w $a3, $a0, 0 -; LA64D-NEXT: bne $a3, $a2, .LBB18_5 -; LA64D-NEXT: # %bb.4: # %atomicrmw.start -; LA64D-NEXT: # in Loop: Header=BB18_3 Depth=2 +; LA64D-NEXT: bne $a3, $a2, .LBB18_4 +; LA64D-NEXT: # %bb.3: # %atomicrmw.start +; LA64D-NEXT: # in Loop: Header=BB18_2 Depth=2 ; LA64D-NEXT: move $a4, $a1 ; LA64D-NEXT: sc.w $a4, $a0, 0 -; LA64D-NEXT: beq $a4, $zero, .LBB18_3 -; LA64D-NEXT: b .LBB18_6 -; LA64D-NEXT: .LBB18_5: # %atomicrmw.start +; LA64D-NEXT: beq $a4, $zero, .LBB18_2 +; LA64D-NEXT: b .LBB18_5 +; LA64D-NEXT: .LBB18_4: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB18_1 Depth=1 ; LA64D-NEXT: dbar 20 -; LA64D-NEXT: .LBB18_6: # %atomicrmw.start +; LA64D-NEXT: .LBB18_5: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB18_1 Depth=1 ; LA64D-NEXT: movgr2fr.w $fa0, $a3 ; LA64D-NEXT: bne $a3, $a2, .LBB18_1 -; LA64D-NEXT: # %bb.2: # %atomicrmw.end +; LA64D-NEXT: # %bb.6: # %atomicrmw.end ; LA64D-NEXT: ret %v = atomicrmw fmin ptr %p, float 1.0 acq_rel, align 4 ret float %v @@ -1346,29 +1346,29 @@ define float @float_fmax_acq_rel(ptr %p) nounwind { ; LA64F-NEXT: .p2align 4, , 16 ; LA64F-NEXT: .LBB19_1: # %atomicrmw.start ; LA64F-NEXT: # =>This Loop Header: Depth=1 -; LA64F-NEXT: # Child Loop BB19_3 Depth 2 +; LA64F-NEXT: # Child Loop BB19_2 Depth 2 ; LA64F-NEXT: fmax.s $fa2, $fa0, $fa1 ; LA64F-NEXT: movfr2gr.s $a1, $fa2 ; LA64F-NEXT: movfr2gr.s $a2, $fa0 -; LA64F-NEXT: .LBB19_3: # %atomicrmw.start +; LA64F-NEXT: .LBB19_2: # %atomicrmw.start ; LA64F-NEXT: # Parent Loop BB19_1 Depth=1 ; LA64F-NEXT: # => This Inner Loop Header: Depth=2 ; LA64F-NEXT: ll.w $a3, $a0, 0 -; LA64F-NEXT: bne $a3, $a2, .LBB19_5 -; LA64F-NEXT: # %bb.4: # %atomicrmw.start -; LA64F-NEXT: # in Loop: Header=BB19_3 Depth=2 +; LA64F-NEXT: bne $a3, $a2, .LBB19_4 +; LA64F-NEXT: # %bb.3: # %atomicrmw.start +; LA64F-NEXT: # in Loop: Header=BB19_2 Depth=2 ; LA64F-NEXT: move $a4, $a1 ; LA64F-NEXT: sc.w $a4, $a0, 0 -; LA64F-NEXT: beq $a4, $zero, .LBB19_3 -; LA64F-NEXT: b .LBB19_6 -; LA64F-NEXT: .LBB19_5: # %atomicrmw.start +; LA64F-NEXT: beq $a4, $zero, .LBB19_2 +; LA64F-NEXT: b .LBB19_5 +; LA64F-NEXT: .LBB19_4: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB19_1 Depth=1 ; LA64F-NEXT: dbar 20 -; LA64F-NEXT: .LBB19_6: # %atomicrmw.start +; LA64F-NEXT: .LBB19_5: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB19_1 Depth=1 ; LA64F-NEXT: movgr2fr.w $fa0, $a3 ; LA64F-NEXT: bne $a3, $a2, .LBB19_1 -; LA64F-NEXT: # %bb.2: # %atomicrmw.end +; LA64F-NEXT: # %bb.6: # %atomicrmw.end ; LA64F-NEXT: ret ; ; LA64D-LABEL: float_fmax_acq_rel: @@ -1378,29 +1378,29 @@ define float @float_fmax_acq_rel(ptr %p) nounwind { ; LA64D-NEXT: .p2align 4, , 16 ; LA64D-NEXT: .LBB19_1: # %atomicrmw.start ; LA64D-NEXT: # =>This Loop Header: Depth=1 -; LA64D-NEXT: # Child Loop BB19_3 Depth 2 +; LA64D-NEXT: # Child Loop BB19_2 Depth 2 ; LA64D-NEXT: fmax.s $fa2, $fa0, $fa1 ; LA64D-NEXT: movfr2gr.s $a1, $fa2 ; LA64D-NEXT: movfr2gr.s $a2, $fa0 -; LA64D-NEXT: .LBB19_3: # %atomicrmw.start +; LA64D-NEXT: .LBB19_2: # %atomicrmw.start ; LA64D-NEXT: # Parent Loop BB19_1 Depth=1 ; LA64D-NEXT: # => This Inner Loop Header: Depth=2 ; LA64D-NEXT: ll.w $a3, $a0, 0 -; LA64D-NEXT: bne $a3, $a2, .LBB19_5 -; LA64D-NEXT: # %bb.4: # %atomicrmw.start -; LA64D-NEXT: # in Loop: Header=BB19_3 Depth=2 +; LA64D-NEXT: bne $a3, $a2, .LBB19_4 +; LA64D-NEXT: # %bb.3: # %atomicrmw.start +; LA64D-NEXT: # in Loop: Header=BB19_2 Depth=2 ; LA64D-NEXT: move $a4, $a1 ; LA64D-NEXT: sc.w $a4, $a0, 0 -; LA64D-NEXT: beq $a4, $zero, .LBB19_3 -; LA64D-NEXT: b .LBB19_6 -; LA64D-NEXT: .LBB19_5: # %atomicrmw.start +; LA64D-NEXT: beq $a4, $zero, .LBB19_2 +; LA64D-NEXT: b .LBB19_5 +; LA64D-NEXT: .LBB19_4: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB19_1 Depth=1 ; LA64D-NEXT: dbar 20 -; LA64D-NEXT: .LBB19_6: # %atomicrmw.start +; LA64D-NEXT: .LBB19_5: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB19_1 Depth=1 ; LA64D-NEXT: movgr2fr.w $fa0, $a3 ; LA64D-NEXT: bne $a3, $a2, .LBB19_1 -; LA64D-NEXT: # %bb.2: # %atomicrmw.end +; LA64D-NEXT: # %bb.6: # %atomicrmw.end ; LA64D-NEXT: ret %v = atomicrmw fmax ptr %p, float 1.0 acq_rel, align 4 ret float %v @@ -1703,29 +1703,29 @@ define float @float_fadd_seq_cst(ptr %p) nounwind { ; LA64F-NEXT: .p2align 4, , 16 ; LA64F-NEXT: .LBB24_1: # %atomicrmw.start ; LA64F-NEXT: # =>This Loop Header: Depth=1 -; LA64F-NEXT: # Child Loop BB24_3 Depth 2 +; LA64F-NEXT: # Child Loop BB24_2 Depth 2 ; LA64F-NEXT: fadd.s $fa2, $fa0, $fa1 ; LA64F-NEXT: movfr2gr.s $a1, $fa2 ; LA64F-NEXT: movfr2gr.s $a2, $fa0 -; LA64F-NEXT: .LBB24_3: # %atomicrmw.start +; LA64F-NEXT: .LBB24_2: # %atomicrmw.start ; LA64F-NEXT: # Parent Loop BB24_1 Depth=1 ; LA64F-NEXT: # => This Inner Loop Header: Depth=2 ; LA64F-NEXT: ll.w $a3, $a0, 0 -; LA64F-NEXT: bne $a3, $a2, .LBB24_5 -; LA64F-NEXT: # %bb.4: # %atomicrmw.start -; LA64F-NEXT: # in Loop: Header=BB24_3 Depth=2 +; LA64F-NEXT: bne $a3, $a2, .LBB24_4 +; LA64F-NEXT: # %bb.3: # %atomicrmw.start +; LA64F-NEXT: # in Loop: Header=BB24_2 Depth=2 ; LA64F-NEXT: move $a4, $a1 ; LA64F-NEXT: sc.w $a4, $a0, 0 -; LA64F-NEXT: beq $a4, $zero, .LBB24_3 -; LA64F-NEXT: b .LBB24_6 -; LA64F-NEXT: .LBB24_5: # %atomicrmw.start +; LA64F-NEXT: beq $a4, $zero, .LBB24_2 +; LA64F-NEXT: b .LBB24_5 +; LA64F-NEXT: .LBB24_4: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB24_1 Depth=1 ; LA64F-NEXT: dbar 20 -; LA64F-NEXT: .LBB24_6: # %atomicrmw.start +; LA64F-NEXT: .LBB24_5: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB24_1 Depth=1 ; LA64F-NEXT: movgr2fr.w $fa0, $a3 ; LA64F-NEXT: bne $a3, $a2, .LBB24_1 -; LA64F-NEXT: # %bb.2: # %atomicrmw.end +; LA64F-NEXT: # %bb.6: # %atomicrmw.end ; LA64F-NEXT: ret ; ; LA64D-LABEL: float_fadd_seq_cst: @@ -1735,29 +1735,29 @@ define float @float_fadd_seq_cst(ptr %p) nounwind { ; LA64D-NEXT: .p2align 4, , 16 ; LA64D-NEXT: .LBB24_1: # %atomicrmw.start ; LA64D-NEXT: # =>This Loop Header: Depth=1 -; LA64D-NEXT: # Child Loop BB24_3 Depth 2 +; LA64D-NEXT: # Child Loop BB24_2 Depth 2 ; LA64D-NEXT: fadd.s $fa2, $fa0, $fa1 ; LA64D-NEXT: movfr2gr.s $a1, $fa2 ; LA64D-NEXT: movfr2gr.s $a2, $fa0 -; LA64D-NEXT: .LBB24_3: # %atomicrmw.start +; LA64D-NEXT: .LBB24_2: # %atomicrmw.start ; LA64D-NEXT: # Parent Loop BB24_1 Depth=1 ; LA64D-NEXT: # => This Inner Loop Header: Depth=2 ; LA64D-NEXT: ll.w $a3, $a0, 0 -; LA64D-NEXT: bne $a3, $a2, .LBB24_5 -; LA64D-NEXT: # %bb.4: # %atomicrmw.start -; LA64D-NEXT: # in Loop: Header=BB24_3 Depth=2 +; LA64D-NEXT: bne $a3, $a2, .LBB24_4 +; LA64D-NEXT: # %bb.3: # %atomicrmw.start +; LA64D-NEXT: # in Loop: Header=BB24_2 Depth=2 ; LA64D-NEXT: move $a4, $a1 ; LA64D-NEXT: sc.w $a4, $a0, 0 -; LA64D-NEXT: beq $a4, $zero, .LBB24_3 -; LA64D-NEXT: b .LBB24_6 -; LA64D-NEXT: .LBB24_5: # %atomicrmw.start +; LA64D-NEXT: beq $a4, $zero, .LBB24_2 +; LA64D-NEXT: b .LBB24_5 +; LA64D-NEXT: .LBB24_4: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB24_1 Depth=1 ; LA64D-NEXT: dbar 20 -; LA64D-NEXT: .LBB24_6: # %atomicrmw.start +; LA64D-NEXT: .LBB24_5: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB24_1 Depth=1 ; LA64D-NEXT: movgr2fr.w $fa0, $a3 ; LA64D-NEXT: bne $a3, $a2, .LBB24_1 -; LA64D-NEXT: # %bb.2: # %atomicrmw.end +; LA64D-NEXT: # %bb.6: # %atomicrmw.end ; LA64D-NEXT: ret %v = atomicrmw fadd ptr %p, float 1.0 seq_cst, align 4 ret float %v @@ -1772,29 +1772,29 @@ define float @float_fsub_seq_cst(ptr %p) nounwind { ; LA64F-NEXT: .p2align 4, , 16 ; LA64F-NEXT: .LBB25_1: # %atomicrmw.start ; LA64F-NEXT: # =>This Loop Header: Depth=1 -; LA64F-NEXT: # Child Loop BB25_3 Depth 2 +; LA64F-NEXT: # Child Loop BB25_2 Depth 2 ; LA64F-NEXT: fadd.s $fa2, $fa0, $fa1 ; LA64F-NEXT: movfr2gr.s $a1, $fa2 ; LA64F-NEXT: movfr2gr.s $a2, $fa0 -; LA64F-NEXT: .LBB25_3: # %atomicrmw.start +; LA64F-NEXT: .LBB25_2: # %atomicrmw.start ; LA64F-NEXT: # Parent Loop BB25_1 Depth=1 ; LA64F-NEXT: # => This Inner Loop Header: Depth=2 ; LA64F-NEXT: ll.w $a3, $a0, 0 -; LA64F-NEXT: bne $a3, $a2, .LBB25_5 -; LA64F-NEXT: # %bb.4: # %atomicrmw.start -; LA64F-NEXT: # in Loop: Header=BB25_3 Depth=2 +; LA64F-NEXT: bne $a3, $a2, .LBB25_4 +; LA64F-NEXT: # %bb.3: # %atomicrmw.start +; LA64F-NEXT: # in Loop: Header=BB25_2 Depth=2 ; LA64F-NEXT: move $a4, $a1 ; LA64F-NEXT: sc.w $a4, $a0, 0 -; LA64F-NEXT: beq $a4, $zero, .LBB25_3 -; LA64F-NEXT: b .LBB25_6 -; LA64F-NEXT: .LBB25_5: # %atomicrmw.start +; LA64F-NEXT: beq $a4, $zero, .LBB25_2 +; LA64F-NEXT: b .LBB25_5 +; LA64F-NEXT: .LBB25_4: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB25_1 Depth=1 ; LA64F-NEXT: dbar 20 -; LA64F-NEXT: .LBB25_6: # %atomicrmw.start +; LA64F-NEXT: .LBB25_5: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB25_1 Depth=1 ; LA64F-NEXT: movgr2fr.w $fa0, $a3 ; LA64F-NEXT: bne $a3, $a2, .LBB25_1 -; LA64F-NEXT: # %bb.2: # %atomicrmw.end +; LA64F-NEXT: # %bb.6: # %atomicrmw.end ; LA64F-NEXT: ret ; ; LA64D-LABEL: float_fsub_seq_cst: @@ -1804,29 +1804,29 @@ define float @float_fsub_seq_cst(ptr %p) nounwind { ; LA64D-NEXT: .p2align 4, , 16 ; LA64D-NEXT: .LBB25_1: # %atomicrmw.start ; LA64D-NEXT: # =>This Loop Header: Depth=1 -; LA64D-NEXT: # Child Loop BB25_3 Depth 2 +; LA64D-NEXT: # Child Loop BB25_2 Depth 2 ; LA64D-NEXT: fadd.s $fa2, $fa0, $fa1 ; LA64D-NEXT: movfr2gr.s $a1, $fa2 ; LA64D-NEXT: movfr2gr.s $a2, $fa0 -; LA64D-NEXT: .LBB25_3: # %atomicrmw.start +; LA64D-NEXT: .LBB25_2: # %atomicrmw.start ; LA64D-NEXT: # Parent Loop BB25_1 Depth=1 ; LA64D-NEXT: # => This Inner Loop Header: Depth=2 ; LA64D-NEXT: ll.w $a3, $a0, 0 -; LA64D-NEXT: bne $a3, $a2, .LBB25_5 -; LA64D-NEXT: # %bb.4: # %atomicrmw.start -; LA64D-NEXT: # in Loop: Header=BB25_3 Depth=2 +; LA64D-NEXT: bne $a3, $a2, .LBB25_4 +; LA64D-NEXT: # %bb.3: # %atomicrmw.start +; LA64D-NEXT: # in Loop: Header=BB25_2 Depth=2 ; LA64D-NEXT: move $a4, $a1 ; LA64D-NEXT: sc.w $a4, $a0, 0 -; LA64D-NEXT: beq $a4, $zero, .LBB25_3 -; LA64D-NEXT: b .LBB25_6 -; LA64D-NEXT: .LBB25_5: # %atomicrmw.start +; LA64D-NEXT: beq $a4, $zero, .LBB25_2 +; LA64D-NEXT: b .LBB25_5 +; LA64D-NEXT: .LBB25_4: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB25_1 Depth=1 ; LA64D-NEXT: dbar 20 -; LA64D-NEXT: .LBB25_6: # %atomicrmw.start +; LA64D-NEXT: .LBB25_5: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB25_1 Depth=1 ; LA64D-NEXT: movgr2fr.w $fa0, $a3 ; LA64D-NEXT: bne $a3, $a2, .LBB25_1 -; LA64D-NEXT: # %bb.2: # %atomicrmw.end +; LA64D-NEXT: # %bb.6: # %atomicrmw.end ; LA64D-NEXT: ret %v = atomicrmw fsub ptr %p, float 1.0 seq_cst, align 4 ret float %v @@ -1841,29 +1841,29 @@ define float @float_fmin_seq_cst(ptr %p) nounwind { ; LA64F-NEXT: .p2align 4, , 16 ; LA64F-NEXT: .LBB26_1: # %atomicrmw.start ; LA64F-NEXT: # =>This Loop Header: Depth=1 -; LA64F-NEXT: # Child Loop BB26_3 Depth 2 +; LA64F-NEXT: # Child Loop BB26_2 Depth 2 ; LA64F-NEXT: fmin.s $fa2, $fa0, $fa1 ; LA64F-NEXT: movfr2gr.s $a1, $fa2 ; LA64F-NEXT: movfr2gr.s $a2, $fa0 -; LA64F-NEXT: .LBB26_3: # %atomicrmw.start +; LA64F-NEXT: .LBB26_2: # %atomicrmw.start ; LA64F-NEXT: # Parent Loop BB26_1 Depth=1 ; LA64F-NEXT: # => This Inner Loop Header: Depth=2 ; LA64F-NEXT: ll.w $a3, $a0, 0 -; LA64F-NEXT: bne $a3, $a2, .LBB26_5 -; LA64F-NEXT: # %bb.4: # %atomicrmw.start -; LA64F-NEXT: # in Loop: Header=BB26_3 Depth=2 +; LA64F-NEXT: bne $a3, $a2, .LBB26_4 +; LA64F-NEXT: # %bb.3: # %atomicrmw.start +; LA64F-NEXT: # in Loop: Header=BB26_2 Depth=2 ; LA64F-NEXT: move $a4, $a1 ; LA64F-NEXT: sc.w $a4, $a0, 0 -; LA64F-NEXT: beq $a4, $zero, .LBB26_3 -; LA64F-NEXT: b .LBB26_6 -; LA64F-NEXT: .LBB26_5: # %atomicrmw.start +; LA64F-NEXT: beq $a4, $zero, .LBB26_2 +; LA64F-NEXT: b .LBB26_5 +; LA64F-NEXT: .LBB26_4: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB26_1 Depth=1 ; LA64F-NEXT: dbar 20 -; LA64F-NEXT: .LBB26_6: # %atomicrmw.start +; LA64F-NEXT: .LBB26_5: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB26_1 Depth=1 ; LA64F-NEXT: movgr2fr.w $fa0, $a3 ; LA64F-NEXT: bne $a3, $a2, .LBB26_1 -; LA64F-NEXT: # %bb.2: # %atomicrmw.end +; LA64F-NEXT: # %bb.6: # %atomicrmw.end ; LA64F-NEXT: ret ; ; LA64D-LABEL: float_fmin_seq_cst: @@ -1873,29 +1873,29 @@ define float @float_fmin_seq_cst(ptr %p) nounwind { ; LA64D-NEXT: .p2align 4, , 16 ; LA64D-NEXT: .LBB26_1: # %atomicrmw.start ; LA64D-NEXT: # =>This Loop Header: Depth=1 -; LA64D-NEXT: # Child Loop BB26_3 Depth 2 +; LA64D-NEXT: # Child Loop BB26_2 Depth 2 ; LA64D-NEXT: fmin.s $fa2, $fa0, $fa1 ; LA64D-NEXT: movfr2gr.s $a1, $fa2 ; LA64D-NEXT: movfr2gr.s $a2, $fa0 -; LA64D-NEXT: .LBB26_3: # %atomicrmw.start +; LA64D-NEXT: .LBB26_2: # %atomicrmw.start ; LA64D-NEXT: # Parent Loop BB26_1 Depth=1 ; LA64D-NEXT: # => This Inner Loop Header: Depth=2 ; LA64D-NEXT: ll.w $a3, $a0, 0 -; LA64D-NEXT: bne $a3, $a2, .LBB26_5 -; LA64D-NEXT: # %bb.4: # %atomicrmw.start -; LA64D-NEXT: # in Loop: Header=BB26_3 Depth=2 +; LA64D-NEXT: bne $a3, $a2, .LBB26_4 +; LA64D-NEXT: # %bb.3: # %atomicrmw.start +; LA64D-NEXT: # in Loop: Header=BB26_2 Depth=2 ; LA64D-NEXT: move $a4, $a1 ; LA64D-NEXT: sc.w $a4, $a0, 0 -; LA64D-NEXT: beq $a4, $zero, .LBB26_3 -; LA64D-NEXT: b .LBB26_6 -; LA64D-NEXT: .LBB26_5: # %atomicrmw.start +; LA64D-NEXT: beq $a4, $zero, .LBB26_2 +; LA64D-NEXT: b .LBB26_5 +; LA64D-NEXT: .LBB26_4: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB26_1 Depth=1 ; LA64D-NEXT: dbar 20 -; LA64D-NEXT: .LBB26_6: # %atomicrmw.start +; LA64D-NEXT: .LBB26_5: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB26_1 Depth=1 ; LA64D-NEXT: movgr2fr.w $fa0, $a3 ; LA64D-NEXT: bne $a3, $a2, .LBB26_1 -; LA64D-NEXT: # %bb.2: # %atomicrmw.end +; LA64D-NEXT: # %bb.6: # %atomicrmw.end ; LA64D-NEXT: ret %v = atomicrmw fmin ptr %p, float 1.0 seq_cst, align 4 ret float %v @@ -1910,29 +1910,29 @@ define float @float_fmax_seq_cst(ptr %p) nounwind { ; LA64F-NEXT: .p2align 4, , 16 ; LA64F-NEXT: .LBB27_1: # %atomicrmw.start ; LA64F-NEXT: # =>This Loop Header: Depth=1 -; LA64F-NEXT: # Child Loop BB27_3 Depth 2 +; LA64F-NEXT: # Child Loop BB27_2 Depth 2 ; LA64F-NEXT: fmax.s $fa2, $fa0, $fa1 ; LA64F-NEXT: movfr2gr.s $a1, $fa2 ; LA64F-NEXT: movfr2gr.s $a2, $fa0 -; LA64F-NEXT: .LBB27_3: # %atomicrmw.start +; LA64F-NEXT: .LBB27_2: # %atomicrmw.start ; LA64F-NEXT: # Parent Loop BB27_1 Depth=1 ; LA64F-NEXT: # => This Inner Loop Header: Depth=2 ; LA64F-NEXT: ll.w $a3, $a0, 0 -; LA64F-NEXT: bne $a3, $a2, .LBB27_5 -; LA64F-NEXT: # %bb.4: # %atomicrmw.start -; LA64F-NEXT: # in Loop: Header=BB27_3 Depth=2 +; LA64F-NEXT: bne $a3, $a2, .LBB27_4 +; LA64F-NEXT: # %bb.3: # %atomicrmw.start +; LA64F-NEXT: # in Loop: Header=BB27_2 Depth=2 ; LA64F-NEXT: move $a4, $a1 ; LA64F-NEXT: sc.w $a4, $a0, 0 -; LA64F-NEXT: beq $a4, $zero, .LBB27_3 -; LA64F-NEXT: b .LBB27_6 -; LA64F-NEXT: .LBB27_5: # %atomicrmw.start +; LA64F-NEXT: beq $a4, $zero, .LBB27_2 +; LA64F-NEXT: b .LBB27_5 +; LA64F-NEXT: .LBB27_4: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB27_1 Depth=1 ; LA64F-NEXT: dbar 20 -; LA64F-NEXT: .LBB27_6: # %atomicrmw.start +; LA64F-NEXT: .LBB27_5: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB27_1 Depth=1 ; LA64F-NEXT: movgr2fr.w $fa0, $a3 ; LA64F-NEXT: bne $a3, $a2, .LBB27_1 -; LA64F-NEXT: # %bb.2: # %atomicrmw.end +; LA64F-NEXT: # %bb.6: # %atomicrmw.end ; LA64F-NEXT: ret ; ; LA64D-LABEL: float_fmax_seq_cst: @@ -1942,29 +1942,29 @@ define float @float_fmax_seq_cst(ptr %p) nounwind { ; LA64D-NEXT: .p2align 4, , 16 ; LA64D-NEXT: .LBB27_1: # %atomicrmw.start ; LA64D-NEXT: # =>This Loop Header: Depth=1 -; LA64D-NEXT: # Child Loop BB27_3 Depth 2 +; LA64D-NEXT: # Child Loop BB27_2 Depth 2 ; LA64D-NEXT: fmax.s $fa2, $fa0, $fa1 ; LA64D-NEXT: movfr2gr.s $a1, $fa2 ; LA64D-NEXT: movfr2gr.s $a2, $fa0 -; LA64D-NEXT: .LBB27_3: # %atomicrmw.start +; LA64D-NEXT: .LBB27_2: # %atomicrmw.start ; LA64D-NEXT: # Parent Loop BB27_1 Depth=1 ; LA64D-NEXT: # => This Inner Loop Header: Depth=2 ; LA64D-NEXT: ll.w $a3, $a0, 0 -; LA64D-NEXT: bne $a3, $a2, .LBB27_5 -; LA64D-NEXT: # %bb.4: # %atomicrmw.start -; LA64D-NEXT: # in Loop: Header=BB27_3 Depth=2 +; LA64D-NEXT: bne $a3, $a2, .LBB27_4 +; LA64D-NEXT: # %bb.3: # %atomicrmw.start +; LA64D-NEXT: # in Loop: Header=BB27_2 Depth=2 ; LA64D-NEXT: move $a4, $a1 ; LA64D-NEXT: sc.w $a4, $a0, 0 -; LA64D-NEXT: beq $a4, $zero, .LBB27_3 -; LA64D-NEXT: b .LBB27_6 -; LA64D-NEXT: .LBB27_5: # %atomicrmw.start +; LA64D-NEXT: beq $a4, $zero, .LBB27_2 +; LA64D-NEXT: b .LBB27_5 +; LA64D-NEXT: .LBB27_4: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB27_1 Depth=1 ; LA64D-NEXT: dbar 20 -; LA64D-NEXT: .LBB27_6: # %atomicrmw.start +; LA64D-NEXT: .LBB27_5: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB27_1 Depth=1 ; LA64D-NEXT: movgr2fr.w $fa0, $a3 ; LA64D-NEXT: bne $a3, $a2, .LBB27_1 -; LA64D-NEXT: # %bb.2: # %atomicrmw.end +; LA64D-NEXT: # %bb.6: # %atomicrmw.end ; LA64D-NEXT: ret %v = atomicrmw fmax ptr %p, float 1.0 seq_cst, align 4 ret float %v @@ -2267,29 +2267,29 @@ define float @float_fadd_monotonic(ptr %p) nounwind { ; LA64F-NEXT: .p2align 4, , 16 ; LA64F-NEXT: .LBB32_1: # %atomicrmw.start ; LA64F-NEXT: # =>This Loop Header: Depth=1 -; LA64F-NEXT: # Child Loop BB32_3 Depth 2 +; LA64F-NEXT: # Child Loop BB32_2 Depth 2 ; LA64F-NEXT: fadd.s $fa2, $fa0, $fa1 ; LA64F-NEXT: movfr2gr.s $a1, $fa2 ; LA64F-NEXT: movfr2gr.s $a2, $fa0 -; LA64F-NEXT: .LBB32_3: # %atomicrmw.start +; LA64F-NEXT: .LBB32_2: # %atomicrmw.start ; LA64F-NEXT: # Parent Loop BB32_1 Depth=1 ; LA64F-NEXT: # => This Inner Loop Header: Depth=2 ; LA64F-NEXT: ll.w $a3, $a0, 0 -; LA64F-NEXT: bne $a3, $a2, .LBB32_5 -; LA64F-NEXT: # %bb.4: # %atomicrmw.start -; LA64F-NEXT: # in Loop: Header=BB32_3 Depth=2 +; LA64F-NEXT: bne $a3, $a2, .LBB32_4 +; LA64F-NEXT: # %bb.3: # %atomicrmw.start +; LA64F-NEXT: # in Loop: Header=BB32_2 Depth=2 ; LA64F-NEXT: move $a4, $a1 ; LA64F-NEXT: sc.w $a4, $a0, 0 -; LA64F-NEXT: beq $a4, $zero, .LBB32_3 -; LA64F-NEXT: b .LBB32_6 -; LA64F-NEXT: .LBB32_5: # %atomicrmw.start +; LA64F-NEXT: beq $a4, $zero, .LBB32_2 +; LA64F-NEXT: b .LBB32_5 +; LA64F-NEXT: .LBB32_4: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB32_1 Depth=1 ; LA64F-NEXT: dbar 1792 -; LA64F-NEXT: .LBB32_6: # %atomicrmw.start +; LA64F-NEXT: .LBB32_5: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB32_1 Depth=1 ; LA64F-NEXT: movgr2fr.w $fa0, $a3 ; LA64F-NEXT: bne $a3, $a2, .LBB32_1 -; LA64F-NEXT: # %bb.2: # %atomicrmw.end +; LA64F-NEXT: # %bb.6: # %atomicrmw.end ; LA64F-NEXT: ret ; ; LA64D-LABEL: float_fadd_monotonic: @@ -2299,29 +2299,29 @@ define float @float_fadd_monotonic(ptr %p) nounwind { ; LA64D-NEXT: .p2align 4, , 16 ; LA64D-NEXT: .LBB32_1: # %atomicrmw.start ; LA64D-NEXT: # =>This Loop Header: Depth=1 -; LA64D-NEXT: # Child Loop BB32_3 Depth 2 +; LA64D-NEXT: # Child Loop BB32_2 Depth 2 ; LA64D-NEXT: fadd.s $fa2, $fa0, $fa1 ; LA64D-NEXT: movfr2gr.s $a1, $fa2 ; LA64D-NEXT: movfr2gr.s $a2, $fa0 -; LA64D-NEXT: .LBB32_3: # %atomicrmw.start +; LA64D-NEXT: .LBB32_2: # %atomicrmw.start ; LA64D-NEXT: # Parent Loop BB32_1 Depth=1 ; LA64D-NEXT: # => This Inner Loop Header: Depth=2 ; LA64D-NEXT: ll.w $a3, $a0, 0 -; LA64D-NEXT: bne $a3, $a2, .LBB32_5 -; LA64D-NEXT: # %bb.4: # %atomicrmw.start -; LA64D-NEXT: # in Loop: Header=BB32_3 Depth=2 +; LA64D-NEXT: bne $a3, $a2, .LBB32_4 +; LA64D-NEXT: # %bb.3: # %atomicrmw.start +; LA64D-NEXT: # in Loop: Header=BB32_2 Depth=2 ; LA64D-NEXT: move $a4, $a1 ; LA64D-NEXT: sc.w $a4, $a0, 0 -; LA64D-NEXT: beq $a4, $zero, .LBB32_3 -; LA64D-NEXT: b .LBB32_6 -; LA64D-NEXT: .LBB32_5: # %atomicrmw.start +; LA64D-NEXT: beq $a4, $zero, .LBB32_2 +; LA64D-NEXT: b .LBB32_5 +; LA64D-NEXT: .LBB32_4: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB32_1 Depth=1 ; LA64D-NEXT: dbar 1792 -; LA64D-NEXT: .LBB32_6: # %atomicrmw.start +; LA64D-NEXT: .LBB32_5: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB32_1 Depth=1 ; LA64D-NEXT: movgr2fr.w $fa0, $a3 ; LA64D-NEXT: bne $a3, $a2, .LBB32_1 -; LA64D-NEXT: # %bb.2: # %atomicrmw.end +; LA64D-NEXT: # %bb.6: # %atomicrmw.end ; LA64D-NEXT: ret %v = atomicrmw fadd ptr %p, float 1.0 monotonic, align 4 ret float %v @@ -2336,29 +2336,29 @@ define float @float_fsub_monotonic(ptr %p) nounwind { ; LA64F-NEXT: .p2align 4, , 16 ; LA64F-NEXT: .LBB33_1: # %atomicrmw.start ; LA64F-NEXT: # =>This Loop Header: Depth=1 -; LA64F-NEXT: # Child Loop BB33_3 Depth 2 +; LA64F-NEXT: # Child Loop BB33_2 Depth 2 ; LA64F-NEXT: fadd.s $fa2, $fa0, $fa1 ; LA64F-NEXT: movfr2gr.s $a1, $fa2 ; LA64F-NEXT: movfr2gr.s $a2, $fa0 -; LA64F-NEXT: .LBB33_3: # %atomicrmw.start +; LA64F-NEXT: .LBB33_2: # %atomicrmw.start ; LA64F-NEXT: # Parent Loop BB33_1 Depth=1 ; LA64F-NEXT: # => This Inner Loop Header: Depth=2 ; LA64F-NEXT: ll.w $a3, $a0, 0 -; LA64F-NEXT: bne $a3, $a2, .LBB33_5 -; LA64F-NEXT: # %bb.4: # %atomicrmw.start -; LA64F-NEXT: # in Loop: Header=BB33_3 Depth=2 +; LA64F-NEXT: bne $a3, $a2, .LBB33_4 +; LA64F-NEXT: # %bb.3: # %atomicrmw.start +; LA64F-NEXT: # in Loop: Header=BB33_2 Depth=2 ; LA64F-NEXT: move $a4, $a1 ; LA64F-NEXT: sc.w $a4, $a0, 0 -; LA64F-NEXT: beq $a4, $zero, .LBB33_3 -; LA64F-NEXT: b .LBB33_6 -; LA64F-NEXT: .LBB33_5: # %atomicrmw.start +; LA64F-NEXT: beq $a4, $zero, .LBB33_2 +; LA64F-NEXT: b .LBB33_5 +; LA64F-NEXT: .LBB33_4: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB33_1 Depth=1 ; LA64F-NEXT: dbar 1792 -; LA64F-NEXT: .LBB33_6: # %atomicrmw.start +; LA64F-NEXT: .LBB33_5: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB33_1 Depth=1 ; LA64F-NEXT: movgr2fr.w $fa0, $a3 ; LA64F-NEXT: bne $a3, $a2, .LBB33_1 -; LA64F-NEXT: # %bb.2: # %atomicrmw.end +; LA64F-NEXT: # %bb.6: # %atomicrmw.end ; LA64F-NEXT: ret ; ; LA64D-LABEL: float_fsub_monotonic: @@ -2368,29 +2368,29 @@ define float @float_fsub_monotonic(ptr %p) nounwind { ; LA64D-NEXT: .p2align 4, , 16 ; LA64D-NEXT: .LBB33_1: # %atomicrmw.start ; LA64D-NEXT: # =>This Loop Header: Depth=1 -; LA64D-NEXT: # Child Loop BB33_3 Depth 2 +; LA64D-NEXT: # Child Loop BB33_2 Depth 2 ; LA64D-NEXT: fadd.s $fa2, $fa0, $fa1 ; LA64D-NEXT: movfr2gr.s $a1, $fa2 ; LA64D-NEXT: movfr2gr.s $a2, $fa0 -; LA64D-NEXT: .LBB33_3: # %atomicrmw.start +; LA64D-NEXT: .LBB33_2: # %atomicrmw.start ; LA64D-NEXT: # Parent Loop BB33_1 Depth=1 ; LA64D-NEXT: # => This Inner Loop Header: Depth=2 ; LA64D-NEXT: ll.w $a3, $a0, 0 -; LA64D-NEXT: bne $a3, $a2, .LBB33_5 -; LA64D-NEXT: # %bb.4: # %atomicrmw.start -; LA64D-NEXT: # in Loop: Header=BB33_3 Depth=2 +; LA64D-NEXT: bne $a3, $a2, .LBB33_4 +; LA64D-NEXT: # %bb.3: # %atomicrmw.start +; LA64D-NEXT: # in Loop: Header=BB33_2 Depth=2 ; LA64D-NEXT: move $a4, $a1 ; LA64D-NEXT: sc.w $a4, $a0, 0 -; LA64D-NEXT: beq $a4, $zero, .LBB33_3 -; LA64D-NEXT: b .LBB33_6 -; LA64D-NEXT: .LBB33_5: # %atomicrmw.start +; LA64D-NEXT: beq $a4, $zero, .LBB33_2 +; LA64D-NEXT: b .LBB33_5 +; LA64D-NEXT: .LBB33_4: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB33_1 Depth=1 ; LA64D-NEXT: dbar 1792 -; LA64D-NEXT: .LBB33_6: # %atomicrmw.start +; LA64D-NEXT: .LBB33_5: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB33_1 Depth=1 ; LA64D-NEXT: movgr2fr.w $fa0, $a3 ; LA64D-NEXT: bne $a3, $a2, .LBB33_1 -; LA64D-NEXT: # %bb.2: # %atomicrmw.end +; LA64D-NEXT: # %bb.6: # %atomicrmw.end ; LA64D-NEXT: ret %v = atomicrmw fsub ptr %p, float 1.0 monotonic, align 4 ret float %v @@ -2405,29 +2405,29 @@ define float @float_fmin_monotonic(ptr %p) nounwind { ; LA64F-NEXT: .p2align 4, , 16 ; LA64F-NEXT: .LBB34_1: # %atomicrmw.start ; LA64F-NEXT: # =>This Loop Header: Depth=1 -; LA64F-NEXT: # Child Loop BB34_3 Depth 2 +; LA64F-NEXT: # Child Loop BB34_2 Depth 2 ; LA64F-NEXT: fmin.s $fa2, $fa0, $fa1 ; LA64F-NEXT: movfr2gr.s $a1, $fa2 ; LA64F-NEXT: movfr2gr.s $a2, $fa0 -; LA64F-NEXT: .LBB34_3: # %atomicrmw.start +; LA64F-NEXT: .LBB34_2: # %atomicrmw.start ; LA64F-NEXT: # Parent Loop BB34_1 Depth=1 ; LA64F-NEXT: # => This Inner Loop Header: Depth=2 ; LA64F-NEXT: ll.w $a3, $a0, 0 -; LA64F-NEXT: bne $a3, $a2, .LBB34_5 -; LA64F-NEXT: # %bb.4: # %atomicrmw.start -; LA64F-NEXT: # in Loop: Header=BB34_3 Depth=2 +; LA64F-NEXT: bne $a3, $a2, .LBB34_4 +; LA64F-NEXT: # %bb.3: # %atomicrmw.start +; LA64F-NEXT: # in Loop: Header=BB34_2 Depth=2 ; LA64F-NEXT: move $a4, $a1 ; LA64F-NEXT: sc.w $a4, $a0, 0 -; LA64F-NEXT: beq $a4, $zero, .LBB34_3 -; LA64F-NEXT: b .LBB34_6 -; LA64F-NEXT: .LBB34_5: # %atomicrmw.start +; LA64F-NEXT: beq $a4, $zero, .LBB34_2 +; LA64F-NEXT: b .LBB34_5 +; LA64F-NEXT: .LBB34_4: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB34_1 Depth=1 ; LA64F-NEXT: dbar 1792 -; LA64F-NEXT: .LBB34_6: # %atomicrmw.start +; LA64F-NEXT: .LBB34_5: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB34_1 Depth=1 ; LA64F-NEXT: movgr2fr.w $fa0, $a3 ; LA64F-NEXT: bne $a3, $a2, .LBB34_1 -; LA64F-NEXT: # %bb.2: # %atomicrmw.end +; LA64F-NEXT: # %bb.6: # %atomicrmw.end ; LA64F-NEXT: ret ; ; LA64D-LABEL: float_fmin_monotonic: @@ -2437,29 +2437,29 @@ define float @float_fmin_monotonic(ptr %p) nounwind { ; LA64D-NEXT: .p2align 4, , 16 ; LA64D-NEXT: .LBB34_1: # %atomicrmw.start ; LA64D-NEXT: # =>This Loop Header: Depth=1 -; LA64D-NEXT: # Child Loop BB34_3 Depth 2 +; LA64D-NEXT: # Child Loop BB34_2 Depth 2 ; LA64D-NEXT: fmin.s $fa2, $fa0, $fa1 ; LA64D-NEXT: movfr2gr.s $a1, $fa2 ; LA64D-NEXT: movfr2gr.s $a2, $fa0 -; LA64D-NEXT: .LBB34_3: # %atomicrmw.start +; LA64D-NEXT: .LBB34_2: # %atomicrmw.start ; LA64D-NEXT: # Parent Loop BB34_1 Depth=1 ; LA64D-NEXT: # => This Inner Loop Header: Depth=2 ; LA64D-NEXT: ll.w $a3, $a0, 0 -; LA64D-NEXT: bne $a3, $a2, .LBB34_5 -; LA64D-NEXT: # %bb.4: # %atomicrmw.start -; LA64D-NEXT: # in Loop: Header=BB34_3 Depth=2 +; LA64D-NEXT: bne $a3, $a2, .LBB34_4 +; LA64D-NEXT: # %bb.3: # %atomicrmw.start +; LA64D-NEXT: # in Loop: Header=BB34_2 Depth=2 ; LA64D-NEXT: move $a4, $a1 ; LA64D-NEXT: sc.w $a4, $a0, 0 -; LA64D-NEXT: beq $a4, $zero, .LBB34_3 -; LA64D-NEXT: b .LBB34_6 -; LA64D-NEXT: .LBB34_5: # %atomicrmw.start +; LA64D-NEXT: beq $a4, $zero, .LBB34_2 +; LA64D-NEXT: b .LBB34_5 +; LA64D-NEXT: .LBB34_4: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB34_1 Depth=1 ; LA64D-NEXT: dbar 1792 -; LA64D-NEXT: .LBB34_6: # %atomicrmw.start +; LA64D-NEXT: .LBB34_5: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB34_1 Depth=1 ; LA64D-NEXT: movgr2fr.w $fa0, $a3 ; LA64D-NEXT: bne $a3, $a2, .LBB34_1 -; LA64D-NEXT: # %bb.2: # %atomicrmw.end +; LA64D-NEXT: # %bb.6: # %atomicrmw.end ; LA64D-NEXT: ret %v = atomicrmw fmin ptr %p, float 1.0 monotonic, align 4 ret float %v @@ -2474,29 +2474,29 @@ define float @float_fmax_monotonic(ptr %p) nounwind { ; LA64F-NEXT: .p2align 4, , 16 ; LA64F-NEXT: .LBB35_1: # %atomicrmw.start ; LA64F-NEXT: # =>This Loop Header: Depth=1 -; LA64F-NEXT: # Child Loop BB35_3 Depth 2 +; LA64F-NEXT: # Child Loop BB35_2 Depth 2 ; LA64F-NEXT: fmax.s $fa2, $fa0, $fa1 ; LA64F-NEXT: movfr2gr.s $a1, $fa2 ; LA64F-NEXT: movfr2gr.s $a2, $fa0 -; LA64F-NEXT: .LBB35_3: # %atomicrmw.start +; LA64F-NEXT: .LBB35_2: # %atomicrmw.start ; LA64F-NEXT: # Parent Loop BB35_1 Depth=1 ; LA64F-NEXT: # => This Inner Loop Header: Depth=2 ; LA64F-NEXT: ll.w $a3, $a0, 0 -; LA64F-NEXT: bne $a3, $a2, .LBB35_5 -; LA64F-NEXT: # %bb.4: # %atomicrmw.start -; LA64F-NEXT: # in Loop: Header=BB35_3 Depth=2 +; LA64F-NEXT: bne $a3, $a2, .LBB35_4 +; LA64F-NEXT: # %bb.3: # %atomicrmw.start +; LA64F-NEXT: # in Loop: Header=BB35_2 Depth=2 ; LA64F-NEXT: move $a4, $a1 ; LA64F-NEXT: sc.w $a4, $a0, 0 -; LA64F-NEXT: beq $a4, $zero, .LBB35_3 -; LA64F-NEXT: b .LBB35_6 -; LA64F-NEXT: .LBB35_5: # %atomicrmw.start +; LA64F-NEXT: beq $a4, $zero, .LBB35_2 +; LA64F-NEXT: b .LBB35_5 +; LA64F-NEXT: .LBB35_4: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB35_1 Depth=1 ; LA64F-NEXT: dbar 1792 -; LA64F-NEXT: .LBB35_6: # %atomicrmw.start +; LA64F-NEXT: .LBB35_5: # %atomicrmw.start ; LA64F-NEXT: # in Loop: Header=BB35_1 Depth=1 ; LA64F-NEXT: movgr2fr.w $fa0, $a3 ; LA64F-NEXT: bne $a3, $a2, .LBB35_1 -; LA64F-NEXT: # %bb.2: # %atomicrmw.end +; LA64F-NEXT: # %bb.6: # %atomicrmw.end ; LA64F-NEXT: ret ; ; LA64D-LABEL: float_fmax_monotonic: @@ -2506,29 +2506,29 @@ define float @float_fmax_monotonic(ptr %p) nounwind { ; LA64D-NEXT: .p2align 4, , 16 ; LA64D-NEXT: .LBB35_1: # %atomicrmw.start ; LA64D-NEXT: # =>This Loop Header: Depth=1 -; LA64D-NEXT: # Child Loop BB35_3 Depth 2 +; LA64D-NEXT: # Child Loop BB35_2 Depth 2 ; LA64D-NEXT: fmax.s $fa2, $fa0, $fa1 ; LA64D-NEXT: movfr2gr.s $a1, $fa2 ; LA64D-NEXT: movfr2gr.s $a2, $fa0 -; LA64D-NEXT: .LBB35_3: # %atomicrmw.start +; LA64D-NEXT: .LBB35_2: # %atomicrmw.start ; LA64D-NEXT: # Parent Loop BB35_1 Depth=1 ; LA64D-NEXT: # => This Inner Loop Header: Depth=2 ; LA64D-NEXT: ll.w $a3, $a0, 0 -; LA64D-NEXT: bne $a3, $a2, .LBB35_5 -; LA64D-NEXT: # %bb.4: # %atomicrmw.start -; LA64D-NEXT: # in Loop: Header=BB35_3 Depth=2 +; LA64D-NEXT: bne $a3, $a2, .LBB35_4 +; LA64D-NEXT: # %bb.3: # %atomicrmw.start +; LA64D-NEXT: # in Loop: Header=BB35_2 Depth=2 ; LA64D-NEXT: move $a4, $a1 ; LA64D-NEXT: sc.w $a4, $a0, 0 -; LA64D-NEXT: beq $a4, $zero, .LBB35_3 -; LA64D-NEXT: b .LBB35_6 -; LA64D-NEXT: .LBB35_5: # %atomicrmw.start +; LA64D-NEXT: beq $a4, $zero, .LBB35_2 +; LA64D-NEXT: b .LBB35_5 +; LA64D-NEXT: .LBB35_4: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB35_1 Depth=1 ; LA64D-NEXT: dbar 1792 -; LA64D-NEXT: .LBB35_6: # %atomicrmw.start +; LA64D-NEXT: .LBB35_5: # %atomicrmw.start ; LA64D-NEXT: # in Loop: Header=BB35_1 Depth=1 ; LA64D-NEXT: movgr2fr.w $fa0, $a3 ; LA64D-NEXT: bne $a3, $a2, .LBB35_1 -; LA64D-NEXT: # %bb.2: # %atomicrmw.end +; LA64D-NEXT: # %bb.6: # %atomicrmw.end ; LA64D-NEXT: ret %v = atomicrmw fmax ptr %p, float 1.0 monotonic, align 4 ret float %v diff --git a/llvm/test/CodeGen/NVPTX/i128.ll b/llvm/test/CodeGen/NVPTX/i128.ll index 8a5e0a00a20eb..ecef930f98301 100644 --- a/llvm/test/CodeGen/NVPTX/i128.ll +++ b/llvm/test/CodeGen/NVPTX/i128.ll @@ -58,7 +58,7 @@ define i128 @srem_i128(i128 %lhs, i128 %rhs) { ; CHECK-NEXT: selp.b64 %rd77, 0, %rd2, %p13; ; CHECK-NEXT: or.pred %p15, %p13, %p14; ; CHECK-NEXT: @%p15 bra $L__BB0_5; -; CHECK-NEXT: // %bb.3: // %udiv-bb1 +; CHECK-NEXT: // %bb.1: // %udiv-bb1 ; CHECK-NEXT: add.cc.s64 %rd71, %rd27, 1; ; CHECK-NEXT: addc.cc.s64 %rd72, %rd28, 0; ; CHECK-NEXT: or.b64 %rd31, %rd71, %rd72; @@ -77,7 +77,7 @@ define i128 @srem_i128(i128 %lhs, i128 %rhs) { ; CHECK-NEXT: mov.b64 %rd70, 0; ; CHECK-NEXT: mov.b64 %rd69, %rd70; ; CHECK-NEXT: @%p16 bra $L__BB0_4; -; CHECK-NEXT: // %bb.1: // %udiv-preheader +; CHECK-NEXT: // %bb.2: // %udiv-preheader ; CHECK-NEXT: cvt.u32.u64 %r9, %rd71; ; CHECK-NEXT: shr.u64 %rd36, %rd2, %r9; ; CHECK-NEXT: sub.s32 %r10, 64, %r9; @@ -91,7 +91,7 @@ define i128 @srem_i128(i128 %lhs, i128 %rhs) { ; CHECK-NEXT: add.cc.s64 %rd6, %rd4, -1; ; CHECK-NEXT: addc.cc.s64 %rd7, %rd5, -1; ; CHECK-NEXT: mov.b64 %rd69, %rd70; -; CHECK-NEXT: $L__BB0_2: // %udiv-do-while +; CHECK-NEXT: $L__BB0_3: // %udiv-do-while ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: shr.u64 %rd40, %rd73, 63; ; CHECK-NEXT: shl.b64 %rd41, %rd74, 1; @@ -118,7 +118,7 @@ define i128 @srem_i128(i128 %lhs, i128 %rhs) { ; CHECK-NEXT: or.b64 %rd55, %rd71, %rd72; ; CHECK-NEXT: setp.eq.b64 %p19, %rd55, 0; ; CHECK-NEXT: @%p19 bra $L__BB0_4; -; CHECK-NEXT: bra.uni $L__BB0_2; +; CHECK-NEXT: bra.uni $L__BB0_3; ; CHECK-NEXT: $L__BB0_4: // %udiv-loop-exit ; CHECK-NEXT: shr.u64 %rd56, %rd75, 63; ; CHECK-NEXT: shl.b64 %rd57, %rd76, 1; @@ -187,7 +187,7 @@ define i128 @urem_i128(i128 %lhs, i128 %rhs) { ; CHECK-NEXT: selp.b64 %rd64, 0, %rd5, %p11; ; CHECK-NEXT: or.pred %p13, %p11, %p12; ; CHECK-NEXT: @%p13 bra $L__BB1_5; -; CHECK-NEXT: // %bb.3: // %udiv-bb1 +; CHECK-NEXT: // %bb.1: // %udiv-bb1 ; CHECK-NEXT: add.cc.s64 %rd58, %rd18, 1; ; CHECK-NEXT: addc.cc.s64 %rd59, %rd19, 0; ; CHECK-NEXT: or.b64 %rd22, %rd58, %rd59; @@ -206,7 +206,7 @@ define i128 @urem_i128(i128 %lhs, i128 %rhs) { ; CHECK-NEXT: mov.b64 %rd57, 0; ; CHECK-NEXT: mov.b64 %rd56, %rd57; ; CHECK-NEXT: @%p14 bra $L__BB1_4; -; CHECK-NEXT: // %bb.1: // %udiv-preheader +; CHECK-NEXT: // %bb.2: // %udiv-preheader ; CHECK-NEXT: cvt.u32.u64 %r9, %rd58; ; CHECK-NEXT: shr.u64 %rd27, %rd5, %r9; ; CHECK-NEXT: sub.s32 %r10, 64, %r9; @@ -220,7 +220,7 @@ define i128 @urem_i128(i128 %lhs, i128 %rhs) { ; CHECK-NEXT: add.cc.s64 %rd3, %rd1, -1; ; CHECK-NEXT: addc.cc.s64 %rd4, %rd2, -1; ; CHECK-NEXT: mov.b64 %rd56, %rd57; -; CHECK-NEXT: $L__BB1_2: // %udiv-do-while +; CHECK-NEXT: $L__BB1_3: // %udiv-do-while ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: shr.u64 %rd31, %rd60, 63; ; CHECK-NEXT: shl.b64 %rd32, %rd61, 1; @@ -247,7 +247,7 @@ define i128 @urem_i128(i128 %lhs, i128 %rhs) { ; CHECK-NEXT: or.b64 %rd46, %rd58, %rd59; ; CHECK-NEXT: setp.eq.b64 %p17, %rd46, 0; ; CHECK-NEXT: @%p17 bra $L__BB1_4; -; CHECK-NEXT: bra.uni $L__BB1_2; +; CHECK-NEXT: bra.uni $L__BB1_3; ; CHECK-NEXT: $L__BB1_4: // %udiv-loop-exit ; CHECK-NEXT: shr.u64 %rd47, %rd62, 63; ; CHECK-NEXT: shl.b64 %rd48, %rd63, 1; @@ -358,7 +358,7 @@ define i128 @sdiv_i128(i128 %lhs, i128 %rhs) { ; CHECK-NEXT: selp.b64 %rd72, 0, %rd1, %p13; ; CHECK-NEXT: or.pred %p15, %p13, %p14; ; CHECK-NEXT: @%p15 bra $L__BB4_5; -; CHECK-NEXT: // %bb.3: // %udiv-bb1 +; CHECK-NEXT: // %bb.1: // %udiv-bb1 ; CHECK-NEXT: add.cc.s64 %rd66, %rd28, 1; ; CHECK-NEXT: addc.cc.s64 %rd67, %rd29, 0; ; CHECK-NEXT: or.b64 %rd32, %rd66, %rd67; @@ -377,7 +377,7 @@ define i128 @sdiv_i128(i128 %lhs, i128 %rhs) { ; CHECK-NEXT: mov.b64 %rd65, 0; ; CHECK-NEXT: mov.b64 %rd64, %rd65; ; CHECK-NEXT: @%p16 bra $L__BB4_4; -; CHECK-NEXT: // %bb.1: // %udiv-preheader +; CHECK-NEXT: // %bb.2: // %udiv-preheader ; CHECK-NEXT: cvt.u32.u64 %r9, %rd66; ; CHECK-NEXT: shr.u64 %rd37, %rd1, %r9; ; CHECK-NEXT: sub.s32 %r10, 64, %r9; @@ -391,7 +391,7 @@ define i128 @sdiv_i128(i128 %lhs, i128 %rhs) { ; CHECK-NEXT: add.cc.s64 %rd6, %rd3, -1; ; CHECK-NEXT: addc.cc.s64 %rd7, %rd4, -1; ; CHECK-NEXT: mov.b64 %rd64, %rd65; -; CHECK-NEXT: $L__BB4_2: // %udiv-do-while +; CHECK-NEXT: $L__BB4_3: // %udiv-do-while ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: shr.u64 %rd41, %rd68, 63; ; CHECK-NEXT: shl.b64 %rd42, %rd69, 1; @@ -418,7 +418,7 @@ define i128 @sdiv_i128(i128 %lhs, i128 %rhs) { ; CHECK-NEXT: or.b64 %rd56, %rd66, %rd67; ; CHECK-NEXT: setp.eq.b64 %p19, %rd56, 0; ; CHECK-NEXT: @%p19 bra $L__BB4_4; -; CHECK-NEXT: bra.uni $L__BB4_2; +; CHECK-NEXT: bra.uni $L__BB4_3; ; CHECK-NEXT: $L__BB4_4: // %udiv-loop-exit ; CHECK-NEXT: shr.u64 %rd57, %rd70, 63; ; CHECK-NEXT: shl.b64 %rd58, %rd71, 1; @@ -481,7 +481,7 @@ define i128 @udiv_i128(i128 %lhs, i128 %rhs) { ; CHECK-NEXT: selp.b64 %rd58, 0, %rd3, %p11; ; CHECK-NEXT: or.pred %p13, %p11, %p12; ; CHECK-NEXT: @%p13 bra $L__BB5_5; -; CHECK-NEXT: // %bb.3: // %udiv-bb1 +; CHECK-NEXT: // %bb.1: // %udiv-bb1 ; CHECK-NEXT: add.cc.s64 %rd52, %rd18, 1; ; CHECK-NEXT: addc.cc.s64 %rd53, %rd19, 0; ; CHECK-NEXT: or.b64 %rd22, %rd52, %rd53; @@ -500,7 +500,7 @@ define i128 @udiv_i128(i128 %lhs, i128 %rhs) { ; CHECK-NEXT: mov.b64 %rd51, 0; ; CHECK-NEXT: mov.b64 %rd50, %rd51; ; CHECK-NEXT: @%p14 bra $L__BB5_4; -; CHECK-NEXT: // %bb.1: // %udiv-preheader +; CHECK-NEXT: // %bb.2: // %udiv-preheader ; CHECK-NEXT: cvt.u32.u64 %r9, %rd52; ; CHECK-NEXT: shr.u64 %rd27, %rd3, %r9; ; CHECK-NEXT: sub.s32 %r10, 64, %r9; @@ -514,7 +514,7 @@ define i128 @udiv_i128(i128 %lhs, i128 %rhs) { ; CHECK-NEXT: add.cc.s64 %rd1, %rd5, -1; ; CHECK-NEXT: addc.cc.s64 %rd2, %rd6, -1; ; CHECK-NEXT: mov.b64 %rd50, %rd51; -; CHECK-NEXT: $L__BB5_2: // %udiv-do-while +; CHECK-NEXT: $L__BB5_3: // %udiv-do-while ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: shr.u64 %rd31, %rd54, 63; ; CHECK-NEXT: shl.b64 %rd32, %rd55, 1; @@ -541,7 +541,7 @@ define i128 @udiv_i128(i128 %lhs, i128 %rhs) { ; CHECK-NEXT: or.b64 %rd46, %rd52, %rd53; ; CHECK-NEXT: setp.eq.b64 %p17, %rd46, 0; ; CHECK-NEXT: @%p17 bra $L__BB5_4; -; CHECK-NEXT: bra.uni $L__BB5_2; +; CHECK-NEXT: bra.uni $L__BB5_3; ; CHECK-NEXT: $L__BB5_4: // %udiv-loop-exit ; CHECK-NEXT: shr.u64 %rd47, %rd56, 63; ; CHECK-NEXT: shl.b64 %rd48, %rd57, 1; diff --git a/llvm/test/CodeGen/NVPTX/jump-table.ll b/llvm/test/CodeGen/NVPTX/jump-table.ll index 4d391f85e978a..ade9552d6bade 100644 --- a/llvm/test/CodeGen/NVPTX/jump-table.ll +++ b/llvm/test/CodeGen/NVPTX/jump-table.ll @@ -21,20 +21,20 @@ define void @foo(i32 %i) { ; PTX60-NEXT: // %bb.1: // %entry ; PTX60-NEXT: $L_brx_0: .branchtargets ; PTX60-NEXT: $L__BB0_2, +; PTX60-NEXT: $L__BB0_5, ; PTX60-NEXT: $L__BB0_3, -; PTX60-NEXT: $L__BB0_4, -; PTX60-NEXT: $L__BB0_5; +; PTX60-NEXT: $L__BB0_4; ; PTX60-NEXT: brx.idx %r1, $L_brx_0; ; PTX60-NEXT: $L__BB0_2: // %case0 ; PTX60-NEXT: st.global.b32 [out], 0; ; PTX60-NEXT: bra.uni $L__BB0_6; -; PTX60-NEXT: $L__BB0_4: // %case2 +; PTX60-NEXT: $L__BB0_3: // %case2 ; PTX60-NEXT: st.global.b32 [out], 2; ; PTX60-NEXT: bra.uni $L__BB0_6; -; PTX60-NEXT: $L__BB0_5: // %case3 +; PTX60-NEXT: $L__BB0_4: // %case3 ; PTX60-NEXT: st.global.b32 [out], 3; ; PTX60-NEXT: bra.uni $L__BB0_6; -; PTX60-NEXT: $L__BB0_3: // %case1 +; PTX60-NEXT: $L__BB0_5: // %case1 ; PTX60-NEXT: st.global.b32 [out], 1; ; PTX60-NEXT: $L__BB0_6: // %end ; PTX60-NEXT: ret; @@ -113,50 +113,50 @@ define i32 @test2(i32 %tmp158) { ; PTX60-NEXT: // %bb.0: // %entry ; PTX60-NEXT: ld.param.b32 %r1, [test2_param_0]; ; PTX60-NEXT: setp.gt.s32 %p1, %r1, 119; -; PTX60-NEXT: @%p1 bra $L__BB1_4; +; PTX60-NEXT: @%p1 bra $L__BB1_3; ; PTX60-NEXT: // %bb.1: // %entry ; PTX60-NEXT: setp.lt.u32 %p4, %r1, 6; -; PTX60-NEXT: @%p4 bra $L__BB1_3; +; PTX60-NEXT: @%p4 bra $L__BB1_7; ; PTX60-NEXT: // %bb.2: // %entry ; PTX60-NEXT: setp.lt.s32 %p5, %r1, -2147483645; -; PTX60-NEXT: @%p5 bra $L__BB1_3; -; PTX60-NEXT: bra.uni $L__BB1_6; -; PTX60-NEXT: $L__BB1_4: // %entry +; PTX60-NEXT: @%p5 bra $L__BB1_7; +; PTX60-NEXT: bra.uni $L__BB1_9; +; PTX60-NEXT: $L__BB1_3: // %entry ; PTX60-NEXT: add.s32 %r2, %r1, -120; ; PTX60-NEXT: setp.gt.u32 %p2, %r2, 5; -; PTX60-NEXT: @%p2 bra $L__BB1_5; -; PTX60-NEXT: // %bb.12: // %entry +; PTX60-NEXT: @%p2 bra $L__BB1_6; +; PTX60-NEXT: // %bb.4: // %entry ; PTX60-NEXT: $L_brx_0: .branchtargets -; PTX60-NEXT: $L__BB1_3, ; PTX60-NEXT: $L__BB1_7, -; PTX60-NEXT: $L__BB1_8, -; PTX60-NEXT: $L__BB1_9, +; PTX60-NEXT: $L__BB1_5, ; PTX60-NEXT: $L__BB1_10, -; PTX60-NEXT: $L__BB1_11; +; PTX60-NEXT: $L__BB1_11, +; PTX60-NEXT: $L__BB1_8, +; PTX60-NEXT: $L__BB1_12; ; PTX60-NEXT: brx.idx %r2, $L_brx_0; -; PTX60-NEXT: $L__BB1_7: // %bb339 +; PTX60-NEXT: $L__BB1_5: // %bb339 ; PTX60-NEXT: st.param.b32 [func_retval0], 12; ; PTX60-NEXT: ret; -; PTX60-NEXT: $L__BB1_5: // %entry +; PTX60-NEXT: $L__BB1_6: // %entry ; PTX60-NEXT: setp.eq.b32 %p3, %r1, 1024; -; PTX60-NEXT: @%p3 bra $L__BB1_3; -; PTX60-NEXT: bra.uni $L__BB1_6; -; PTX60-NEXT: $L__BB1_3: // %bb338 +; PTX60-NEXT: @%p3 bra $L__BB1_7; +; PTX60-NEXT: bra.uni $L__BB1_9; +; PTX60-NEXT: $L__BB1_7: // %bb338 ; PTX60-NEXT: st.param.b32 [func_retval0], 11; ; PTX60-NEXT: ret; -; PTX60-NEXT: $L__BB1_10: // %bb342 +; PTX60-NEXT: $L__BB1_8: // %bb342 ; PTX60-NEXT: st.param.b32 [func_retval0], 15; ; PTX60-NEXT: ret; -; PTX60-NEXT: $L__BB1_6: // %bb336 +; PTX60-NEXT: $L__BB1_9: // %bb336 ; PTX60-NEXT: st.param.b32 [func_retval0], 10; ; PTX60-NEXT: ret; -; PTX60-NEXT: $L__BB1_8: // %bb340 +; PTX60-NEXT: $L__BB1_10: // %bb340 ; PTX60-NEXT: st.param.b32 [func_retval0], 13; ; PTX60-NEXT: ret; -; PTX60-NEXT: $L__BB1_9: // %bb341 +; PTX60-NEXT: $L__BB1_11: // %bb341 ; PTX60-NEXT: st.param.b32 [func_retval0], 14; ; PTX60-NEXT: ret; -; PTX60-NEXT: $L__BB1_11: // %bb343 +; PTX60-NEXT: $L__BB1_12: // %bb343 ; PTX60-NEXT: st.param.b32 [func_retval0], 18; ; PTX60-NEXT: ret; ; @@ -168,64 +168,64 @@ define i32 @test2(i32 %tmp158) { ; PTX50-NEXT: // %bb.0: // %entry ; PTX50-NEXT: ld.param.b32 %r1, [test2_param_0]; ; PTX50-NEXT: setp.gt.s32 %p1, %r1, 119; -; PTX50-NEXT: @%p1 bra $L__BB1_4; +; PTX50-NEXT: @%p1 bra $L__BB1_3; ; PTX50-NEXT: // %bb.1: // %entry ; PTX50-NEXT: setp.lt.u32 %p11, %r1, 6; -; PTX50-NEXT: @%p11 bra $L__BB1_3; +; PTX50-NEXT: @%p11 bra $L__BB1_14; ; PTX50-NEXT: // %bb.2: // %entry ; PTX50-NEXT: setp.lt.s32 %p12, %r1, -2147483645; -; PTX50-NEXT: @%p12 bra $L__BB1_3; -; PTX50-NEXT: bra.uni $L__BB1_15; -; PTX50-NEXT: $L__BB1_4: // %entry +; PTX50-NEXT: @%p12 bra $L__BB1_14; +; PTX50-NEXT: bra.uni $L__BB1_17; +; PTX50-NEXT: $L__BB1_3: // %entry ; PTX50-NEXT: setp.gt.s32 %p2, %r1, 122; -; PTX50-NEXT: @%p2 bra $L__BB1_9; -; PTX50-NEXT: bra.uni $L__BB1_5; -; PTX50-NEXT: $L__BB1_9: // %entry +; PTX50-NEXT: @%p2 bra $L__BB1_4; +; PTX50-NEXT: bra.uni $L__BB1_8; +; PTX50-NEXT: $L__BB1_4: // %entry ; PTX50-NEXT: setp.gt.s32 %p3, %r1, 124; -; PTX50-NEXT: @%p3 bra $L__BB1_13; -; PTX50-NEXT: // %bb.10: // %entry +; PTX50-NEXT: @%p3 bra $L__BB1_12; +; PTX50-NEXT: // %bb.5: // %entry ; PTX50-NEXT: setp.eq.b32 %p6, %r1, 123; -; PTX50-NEXT: @%p6 bra $L__BB1_17; -; PTX50-NEXT: // %bb.11: // %entry +; PTX50-NEXT: @%p6 bra $L__BB1_15; +; PTX50-NEXT: // %bb.6: // %entry ; PTX50-NEXT: setp.eq.b32 %p7, %r1, 124; -; PTX50-NEXT: @%p7 bra $L__BB1_12; -; PTX50-NEXT: bra.uni $L__BB1_15; -; PTX50-NEXT: $L__BB1_12: // %bb342 +; PTX50-NEXT: @%p7 bra $L__BB1_7; +; PTX50-NEXT: bra.uni $L__BB1_17; +; PTX50-NEXT: $L__BB1_7: // %bb342 ; PTX50-NEXT: st.param.b32 [func_retval0], 15; ; PTX50-NEXT: ret; -; PTX50-NEXT: $L__BB1_5: // %entry +; PTX50-NEXT: $L__BB1_8: // %entry ; PTX50-NEXT: setp.eq.b32 %p8, %r1, 120; -; PTX50-NEXT: @%p8 bra $L__BB1_3; -; PTX50-NEXT: // %bb.6: // %entry +; PTX50-NEXT: @%p8 bra $L__BB1_14; +; PTX50-NEXT: // %bb.9: // %entry ; PTX50-NEXT: setp.eq.b32 %p9, %r1, 121; -; PTX50-NEXT: @%p9 bra $L__BB1_16; -; PTX50-NEXT: // %bb.7: // %entry +; PTX50-NEXT: @%p9 bra $L__BB1_18; +; PTX50-NEXT: // %bb.10: // %entry ; PTX50-NEXT: setp.eq.b32 %p10, %r1, 122; -; PTX50-NEXT: @%p10 bra $L__BB1_8; -; PTX50-NEXT: bra.uni $L__BB1_15; -; PTX50-NEXT: $L__BB1_8: // %bb340 +; PTX50-NEXT: @%p10 bra $L__BB1_11; +; PTX50-NEXT: bra.uni $L__BB1_17; +; PTX50-NEXT: $L__BB1_11: // %bb340 ; PTX50-NEXT: st.param.b32 [func_retval0], 13; ; PTX50-NEXT: ret; -; PTX50-NEXT: $L__BB1_13: // %entry +; PTX50-NEXT: $L__BB1_12: // %entry ; PTX50-NEXT: setp.eq.b32 %p4, %r1, 125; -; PTX50-NEXT: @%p4 bra $L__BB1_18; -; PTX50-NEXT: // %bb.14: // %entry +; PTX50-NEXT: @%p4 bra $L__BB1_16; +; PTX50-NEXT: // %bb.13: // %entry ; PTX50-NEXT: setp.eq.b32 %p5, %r1, 1024; -; PTX50-NEXT: @%p5 bra $L__BB1_3; -; PTX50-NEXT: bra.uni $L__BB1_15; -; PTX50-NEXT: $L__BB1_3: // %bb338 +; PTX50-NEXT: @%p5 bra $L__BB1_14; +; PTX50-NEXT: bra.uni $L__BB1_17; +; PTX50-NEXT: $L__BB1_14: // %bb338 ; PTX50-NEXT: st.param.b32 [func_retval0], 11; ; PTX50-NEXT: ret; -; PTX50-NEXT: $L__BB1_17: // %bb341 +; PTX50-NEXT: $L__BB1_15: // %bb341 ; PTX50-NEXT: st.param.b32 [func_retval0], 14; ; PTX50-NEXT: ret; -; PTX50-NEXT: $L__BB1_18: // %bb343 +; PTX50-NEXT: $L__BB1_16: // %bb343 ; PTX50-NEXT: st.param.b32 [func_retval0], 18; ; PTX50-NEXT: ret; -; PTX50-NEXT: $L__BB1_15: // %bb336 +; PTX50-NEXT: $L__BB1_17: // %bb336 ; PTX50-NEXT: st.param.b32 [func_retval0], 10; ; PTX50-NEXT: ret; -; PTX50-NEXT: $L__BB1_16: // %bb339 +; PTX50-NEXT: $L__BB1_18: // %bb339 ; PTX50-NEXT: st.param.b32 [func_retval0], 12; ; PTX50-NEXT: ret; entry: diff --git a/llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll b/llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll index d427b4435d37d..a327c173e3def 100644 --- a/llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll +++ b/llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll @@ -18,18 +18,18 @@ define void @cmpxchg_and_branch1(ptr %ptr, i32 signext %cmp, i32 signext %val) n ; NOZACAS: # %bb.0: # %entry ; NOZACAS-NEXT: .LBB0_1: # %do_cmpxchg ; NOZACAS-NEXT: # =>This Loop Header: Depth=1 -; NOZACAS-NEXT: # Child Loop BB0_3 Depth 2 -; NOZACAS-NEXT: .LBB0_3: # %do_cmpxchg +; NOZACAS-NEXT: # Child Loop BB0_2 Depth 2 +; NOZACAS-NEXT: .LBB0_2: # %do_cmpxchg ; NOZACAS-NEXT: # Parent Loop BB0_1 Depth=1 ; NOZACAS-NEXT: # => This Inner Loop Header: Depth=2 ; NOZACAS-NEXT: lr.w.aqrl a3, (a0) ; NOZACAS-NEXT: bne a3, a1, .LBB0_1 -; NOZACAS-NEXT: # %bb.4: # %do_cmpxchg -; NOZACAS-NEXT: # in Loop: Header=BB0_3 Depth=2 +; NOZACAS-NEXT: # %bb.3: # %do_cmpxchg +; NOZACAS-NEXT: # in Loop: Header=BB0_2 Depth=2 ; NOZACAS-NEXT: sc.w.rl a4, a2, (a0) -; NOZACAS-NEXT: bnez a4, .LBB0_3 -; NOZACAS-NEXT: # %bb.5: # %do_cmpxchg -; NOZACAS-NEXT: # %bb.2: # %exit +; NOZACAS-NEXT: bnez a4, .LBB0_2 +; NOZACAS-NEXT: # %bb.4: # %do_cmpxchg +; NOZACAS-NEXT: # %bb.5: # %exit ; NOZACAS-NEXT: ret ; ; ZACAS-LABEL: cmpxchg_and_branch1: @@ -57,20 +57,20 @@ define void @cmpxchg_and_branch2(ptr %ptr, i32 signext %cmp, i32 signext %val) n ; NOZACAS: # %bb.0: # %entry ; NOZACAS-NEXT: .LBB1_1: # %do_cmpxchg ; NOZACAS-NEXT: # =>This Loop Header: Depth=1 -; NOZACAS-NEXT: # Child Loop BB1_3 Depth 2 -; NOZACAS-NEXT: .LBB1_3: # %do_cmpxchg +; NOZACAS-NEXT: # Child Loop BB1_2 Depth 2 +; NOZACAS-NEXT: .LBB1_2: # %do_cmpxchg ; NOZACAS-NEXT: # Parent Loop BB1_1 Depth=1 ; NOZACAS-NEXT: # => This Inner Loop Header: Depth=2 ; NOZACAS-NEXT: lr.w.aqrl a3, (a0) -; NOZACAS-NEXT: bne a3, a1, .LBB1_5 -; NOZACAS-NEXT: # %bb.4: # %do_cmpxchg -; NOZACAS-NEXT: # in Loop: Header=BB1_3 Depth=2 +; NOZACAS-NEXT: bne a3, a1, .LBB1_4 +; NOZACAS-NEXT: # %bb.3: # %do_cmpxchg +; NOZACAS-NEXT: # in Loop: Header=BB1_2 Depth=2 ; NOZACAS-NEXT: sc.w.rl a4, a2, (a0) -; NOZACAS-NEXT: bnez a4, .LBB1_3 -; NOZACAS-NEXT: .LBB1_5: # %do_cmpxchg +; NOZACAS-NEXT: bnez a4, .LBB1_2 +; NOZACAS-NEXT: .LBB1_4: # %do_cmpxchg ; NOZACAS-NEXT: # in Loop: Header=BB1_1 Depth=1 ; NOZACAS-NEXT: beq a3, a1, .LBB1_1 -; NOZACAS-NEXT: # %bb.2: # %exit +; NOZACAS-NEXT: # %bb.5: # %exit ; NOZACAS-NEXT: ret ; ; ZACAS-LABEL: cmpxchg_and_branch2: @@ -106,22 +106,22 @@ define void @cmpxchg_masked_and_branch1(ptr %ptr, i8 signext %cmp, i8 signext %v ; RV32IA-NEXT: sll a2, a2, a4 ; RV32IA-NEXT: .LBB2_1: # %do_cmpxchg ; RV32IA-NEXT: # =>This Loop Header: Depth=1 -; RV32IA-NEXT: # Child Loop BB2_3 Depth 2 -; RV32IA-NEXT: .LBB2_3: # %do_cmpxchg +; RV32IA-NEXT: # Child Loop BB2_2 Depth 2 +; RV32IA-NEXT: .LBB2_2: # %do_cmpxchg ; RV32IA-NEXT: # Parent Loop BB2_1 Depth=1 ; RV32IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV32IA-NEXT: lr.w.aqrl a4, (a3) ; RV32IA-NEXT: and a5, a4, a0 ; RV32IA-NEXT: bne a5, a1, .LBB2_1 -; RV32IA-NEXT: # %bb.4: # %do_cmpxchg -; RV32IA-NEXT: # in Loop: Header=BB2_3 Depth=2 +; RV32IA-NEXT: # %bb.3: # %do_cmpxchg +; RV32IA-NEXT: # in Loop: Header=BB2_2 Depth=2 ; RV32IA-NEXT: xor a5, a4, a2 ; RV32IA-NEXT: and a5, a5, a0 ; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: sc.w.rl a5, a5, (a3) -; RV32IA-NEXT: bnez a5, .LBB2_3 -; RV32IA-NEXT: # %bb.5: # %do_cmpxchg -; RV32IA-NEXT: # %bb.2: # %exit +; RV32IA-NEXT: bnez a5, .LBB2_2 +; RV32IA-NEXT: # %bb.4: # %do_cmpxchg +; RV32IA-NEXT: # %bb.5: # %exit ; RV32IA-NEXT: ret ; ; RV32IA-ZACAS-LABEL: cmpxchg_masked_and_branch1: @@ -136,22 +136,22 @@ define void @cmpxchg_masked_and_branch1(ptr %ptr, i8 signext %cmp, i8 signext %v ; RV32IA-ZACAS-NEXT: sll a2, a2, a4 ; RV32IA-ZACAS-NEXT: .LBB2_1: # %do_cmpxchg ; RV32IA-ZACAS-NEXT: # =>This Loop Header: Depth=1 -; RV32IA-ZACAS-NEXT: # Child Loop BB2_3 Depth 2 -; RV32IA-ZACAS-NEXT: .LBB2_3: # %do_cmpxchg +; RV32IA-ZACAS-NEXT: # Child Loop BB2_2 Depth 2 +; RV32IA-ZACAS-NEXT: .LBB2_2: # %do_cmpxchg ; RV32IA-ZACAS-NEXT: # Parent Loop BB2_1 Depth=1 ; RV32IA-ZACAS-NEXT: # => This Inner Loop Header: Depth=2 ; RV32IA-ZACAS-NEXT: lr.w.aqrl a4, (a3) ; RV32IA-ZACAS-NEXT: and a5, a4, a0 ; RV32IA-ZACAS-NEXT: bne a5, a1, .LBB2_1 -; RV32IA-ZACAS-NEXT: # %bb.4: # %do_cmpxchg -; RV32IA-ZACAS-NEXT: # in Loop: Header=BB2_3 Depth=2 +; RV32IA-ZACAS-NEXT: # %bb.3: # %do_cmpxchg +; RV32IA-ZACAS-NEXT: # in Loop: Header=BB2_2 Depth=2 ; RV32IA-ZACAS-NEXT: xor a5, a4, a2 ; RV32IA-ZACAS-NEXT: and a5, a5, a0 ; RV32IA-ZACAS-NEXT: xor a5, a4, a5 ; RV32IA-ZACAS-NEXT: sc.w.rl a5, a5, (a3) -; RV32IA-ZACAS-NEXT: bnez a5, .LBB2_3 -; RV32IA-ZACAS-NEXT: # %bb.5: # %do_cmpxchg -; RV32IA-ZACAS-NEXT: # %bb.2: # %exit +; RV32IA-ZACAS-NEXT: bnez a5, .LBB2_2 +; RV32IA-ZACAS-NEXT: # %bb.4: # %do_cmpxchg +; RV32IA-ZACAS-NEXT: # %bb.5: # %exit ; RV32IA-ZACAS-NEXT: ret ; ; RV64IA-LABEL: cmpxchg_masked_and_branch1: @@ -166,22 +166,22 @@ define void @cmpxchg_masked_and_branch1(ptr %ptr, i8 signext %cmp, i8 signext %v ; RV64IA-NEXT: sllw a2, a2, a4 ; RV64IA-NEXT: .LBB2_1: # %do_cmpxchg ; RV64IA-NEXT: # =>This Loop Header: Depth=1 -; RV64IA-NEXT: # Child Loop BB2_3 Depth 2 -; RV64IA-NEXT: .LBB2_3: # %do_cmpxchg +; RV64IA-NEXT: # Child Loop BB2_2 Depth 2 +; RV64IA-NEXT: .LBB2_2: # %do_cmpxchg ; RV64IA-NEXT: # Parent Loop BB2_1 Depth=1 ; RV64IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV64IA-NEXT: lr.w.aqrl a4, (a3) ; RV64IA-NEXT: and a5, a4, a0 ; RV64IA-NEXT: bne a5, a1, .LBB2_1 -; RV64IA-NEXT: # %bb.4: # %do_cmpxchg -; RV64IA-NEXT: # in Loop: Header=BB2_3 Depth=2 +; RV64IA-NEXT: # %bb.3: # %do_cmpxchg +; RV64IA-NEXT: # in Loop: Header=BB2_2 Depth=2 ; RV64IA-NEXT: xor a5, a4, a2 ; RV64IA-NEXT: and a5, a5, a0 ; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: sc.w.rl a5, a5, (a3) -; RV64IA-NEXT: bnez a5, .LBB2_3 -; RV64IA-NEXT: # %bb.5: # %do_cmpxchg -; RV64IA-NEXT: # %bb.2: # %exit +; RV64IA-NEXT: bnez a5, .LBB2_2 +; RV64IA-NEXT: # %bb.4: # %do_cmpxchg +; RV64IA-NEXT: # %bb.5: # %exit ; RV64IA-NEXT: ret ; ; RV64IA-ZACAS-LABEL: cmpxchg_masked_and_branch1: @@ -196,22 +196,22 @@ define void @cmpxchg_masked_and_branch1(ptr %ptr, i8 signext %cmp, i8 signext %v ; RV64IA-ZACAS-NEXT: sllw a2, a2, a4 ; RV64IA-ZACAS-NEXT: .LBB2_1: # %do_cmpxchg ; RV64IA-ZACAS-NEXT: # =>This Loop Header: Depth=1 -; RV64IA-ZACAS-NEXT: # Child Loop BB2_3 Depth 2 -; RV64IA-ZACAS-NEXT: .LBB2_3: # %do_cmpxchg +; RV64IA-ZACAS-NEXT: # Child Loop BB2_2 Depth 2 +; RV64IA-ZACAS-NEXT: .LBB2_2: # %do_cmpxchg ; RV64IA-ZACAS-NEXT: # Parent Loop BB2_1 Depth=1 ; RV64IA-ZACAS-NEXT: # => This Inner Loop Header: Depth=2 ; RV64IA-ZACAS-NEXT: lr.w.aqrl a4, (a3) ; RV64IA-ZACAS-NEXT: and a5, a4, a0 ; RV64IA-ZACAS-NEXT: bne a5, a1, .LBB2_1 -; RV64IA-ZACAS-NEXT: # %bb.4: # %do_cmpxchg -; RV64IA-ZACAS-NEXT: # in Loop: Header=BB2_3 Depth=2 +; RV64IA-ZACAS-NEXT: # %bb.3: # %do_cmpxchg +; RV64IA-ZACAS-NEXT: # in Loop: Header=BB2_2 Depth=2 ; RV64IA-ZACAS-NEXT: xor a5, a4, a2 ; RV64IA-ZACAS-NEXT: and a5, a5, a0 ; RV64IA-ZACAS-NEXT: xor a5, a4, a5 ; RV64IA-ZACAS-NEXT: sc.w.rl a5, a5, (a3) -; RV64IA-ZACAS-NEXT: bnez a5, .LBB2_3 -; RV64IA-ZACAS-NEXT: # %bb.5: # %do_cmpxchg -; RV64IA-ZACAS-NEXT: # %bb.2: # %exit +; RV64IA-ZACAS-NEXT: bnez a5, .LBB2_2 +; RV64IA-ZACAS-NEXT: # %bb.4: # %do_cmpxchg +; RV64IA-ZACAS-NEXT: # %bb.5: # %exit ; RV64IA-ZACAS-NEXT: ret ; ; RV64IA-ZABHA-LABEL: cmpxchg_masked_and_branch1: @@ -247,25 +247,25 @@ define void @cmpxchg_masked_and_branch2(ptr %ptr, i8 signext %cmp, i8 signext %v ; RV32IA-NEXT: sll a2, a2, a4 ; RV32IA-NEXT: .LBB3_1: # %do_cmpxchg ; RV32IA-NEXT: # =>This Loop Header: Depth=1 -; RV32IA-NEXT: # Child Loop BB3_3 Depth 2 -; RV32IA-NEXT: .LBB3_3: # %do_cmpxchg +; RV32IA-NEXT: # Child Loop BB3_2 Depth 2 +; RV32IA-NEXT: .LBB3_2: # %do_cmpxchg ; RV32IA-NEXT: # Parent Loop BB3_1 Depth=1 ; RV32IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV32IA-NEXT: lr.w.aqrl a4, (a3) ; RV32IA-NEXT: and a5, a4, a0 -; RV32IA-NEXT: bne a5, a1, .LBB3_5 -; RV32IA-NEXT: # %bb.4: # %do_cmpxchg -; RV32IA-NEXT: # in Loop: Header=BB3_3 Depth=2 +; RV32IA-NEXT: bne a5, a1, .LBB3_4 +; RV32IA-NEXT: # %bb.3: # %do_cmpxchg +; RV32IA-NEXT: # in Loop: Header=BB3_2 Depth=2 ; RV32IA-NEXT: xor a5, a4, a2 ; RV32IA-NEXT: and a5, a5, a0 ; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: sc.w.rl a5, a5, (a3) -; RV32IA-NEXT: bnez a5, .LBB3_3 -; RV32IA-NEXT: .LBB3_5: # %do_cmpxchg +; RV32IA-NEXT: bnez a5, .LBB3_2 +; RV32IA-NEXT: .LBB3_4: # %do_cmpxchg ; RV32IA-NEXT: # in Loop: Header=BB3_1 Depth=1 ; RV32IA-NEXT: and a4, a4, a0 ; RV32IA-NEXT: beq a1, a4, .LBB3_1 -; RV32IA-NEXT: # %bb.2: # %exit +; RV32IA-NEXT: # %bb.5: # %exit ; RV32IA-NEXT: ret ; ; RV32IA-ZACAS-LABEL: cmpxchg_masked_and_branch2: @@ -280,25 +280,25 @@ define void @cmpxchg_masked_and_branch2(ptr %ptr, i8 signext %cmp, i8 signext %v ; RV32IA-ZACAS-NEXT: sll a2, a2, a4 ; RV32IA-ZACAS-NEXT: .LBB3_1: # %do_cmpxchg ; RV32IA-ZACAS-NEXT: # =>This Loop Header: Depth=1 -; RV32IA-ZACAS-NEXT: # Child Loop BB3_3 Depth 2 -; RV32IA-ZACAS-NEXT: .LBB3_3: # %do_cmpxchg +; RV32IA-ZACAS-NEXT: # Child Loop BB3_2 Depth 2 +; RV32IA-ZACAS-NEXT: .LBB3_2: # %do_cmpxchg ; RV32IA-ZACAS-NEXT: # Parent Loop BB3_1 Depth=1 ; RV32IA-ZACAS-NEXT: # => This Inner Loop Header: Depth=2 ; RV32IA-ZACAS-NEXT: lr.w.aqrl a4, (a3) ; RV32IA-ZACAS-NEXT: and a5, a4, a0 -; RV32IA-ZACAS-NEXT: bne a5, a1, .LBB3_5 -; RV32IA-ZACAS-NEXT: # %bb.4: # %do_cmpxchg -; RV32IA-ZACAS-NEXT: # in Loop: Header=BB3_3 Depth=2 +; RV32IA-ZACAS-NEXT: bne a5, a1, .LBB3_4 +; RV32IA-ZACAS-NEXT: # %bb.3: # %do_cmpxchg +; RV32IA-ZACAS-NEXT: # in Loop: Header=BB3_2 Depth=2 ; RV32IA-ZACAS-NEXT: xor a5, a4, a2 ; RV32IA-ZACAS-NEXT: and a5, a5, a0 ; RV32IA-ZACAS-NEXT: xor a5, a4, a5 ; RV32IA-ZACAS-NEXT: sc.w.rl a5, a5, (a3) -; RV32IA-ZACAS-NEXT: bnez a5, .LBB3_3 -; RV32IA-ZACAS-NEXT: .LBB3_5: # %do_cmpxchg +; RV32IA-ZACAS-NEXT: bnez a5, .LBB3_2 +; RV32IA-ZACAS-NEXT: .LBB3_4: # %do_cmpxchg ; RV32IA-ZACAS-NEXT: # in Loop: Header=BB3_1 Depth=1 ; RV32IA-ZACAS-NEXT: and a4, a4, a0 ; RV32IA-ZACAS-NEXT: beq a1, a4, .LBB3_1 -; RV32IA-ZACAS-NEXT: # %bb.2: # %exit +; RV32IA-ZACAS-NEXT: # %bb.5: # %exit ; RV32IA-ZACAS-NEXT: ret ; ; RV64IA-LABEL: cmpxchg_masked_and_branch2: @@ -313,25 +313,25 @@ define void @cmpxchg_masked_and_branch2(ptr %ptr, i8 signext %cmp, i8 signext %v ; RV64IA-NEXT: sllw a2, a2, a4 ; RV64IA-NEXT: .LBB3_1: # %do_cmpxchg ; RV64IA-NEXT: # =>This Loop Header: Depth=1 -; RV64IA-NEXT: # Child Loop BB3_3 Depth 2 -; RV64IA-NEXT: .LBB3_3: # %do_cmpxchg +; RV64IA-NEXT: # Child Loop BB3_2 Depth 2 +; RV64IA-NEXT: .LBB3_2: # %do_cmpxchg ; RV64IA-NEXT: # Parent Loop BB3_1 Depth=1 ; RV64IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV64IA-NEXT: lr.w.aqrl a4, (a3) ; RV64IA-NEXT: and a5, a4, a0 -; RV64IA-NEXT: bne a5, a1, .LBB3_5 -; RV64IA-NEXT: # %bb.4: # %do_cmpxchg -; RV64IA-NEXT: # in Loop: Header=BB3_3 Depth=2 +; RV64IA-NEXT: bne a5, a1, .LBB3_4 +; RV64IA-NEXT: # %bb.3: # %do_cmpxchg +; RV64IA-NEXT: # in Loop: Header=BB3_2 Depth=2 ; RV64IA-NEXT: xor a5, a4, a2 ; RV64IA-NEXT: and a5, a5, a0 ; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: sc.w.rl a5, a5, (a3) -; RV64IA-NEXT: bnez a5, .LBB3_3 -; RV64IA-NEXT: .LBB3_5: # %do_cmpxchg +; RV64IA-NEXT: bnez a5, .LBB3_2 +; RV64IA-NEXT: .LBB3_4: # %do_cmpxchg ; RV64IA-NEXT: # in Loop: Header=BB3_1 Depth=1 ; RV64IA-NEXT: and a4, a4, a0 ; RV64IA-NEXT: beq a1, a4, .LBB3_1 -; RV64IA-NEXT: # %bb.2: # %exit +; RV64IA-NEXT: # %bb.5: # %exit ; RV64IA-NEXT: ret ; ; RV64IA-ZACAS-LABEL: cmpxchg_masked_and_branch2: @@ -346,25 +346,25 @@ define void @cmpxchg_masked_and_branch2(ptr %ptr, i8 signext %cmp, i8 signext %v ; RV64IA-ZACAS-NEXT: sllw a2, a2, a4 ; RV64IA-ZACAS-NEXT: .LBB3_1: # %do_cmpxchg ; RV64IA-ZACAS-NEXT: # =>This Loop Header: Depth=1 -; RV64IA-ZACAS-NEXT: # Child Loop BB3_3 Depth 2 -; RV64IA-ZACAS-NEXT: .LBB3_3: # %do_cmpxchg +; RV64IA-ZACAS-NEXT: # Child Loop BB3_2 Depth 2 +; RV64IA-ZACAS-NEXT: .LBB3_2: # %do_cmpxchg ; RV64IA-ZACAS-NEXT: # Parent Loop BB3_1 Depth=1 ; RV64IA-ZACAS-NEXT: # => This Inner Loop Header: Depth=2 ; RV64IA-ZACAS-NEXT: lr.w.aqrl a4, (a3) ; RV64IA-ZACAS-NEXT: and a5, a4, a0 -; RV64IA-ZACAS-NEXT: bne a5, a1, .LBB3_5 -; RV64IA-ZACAS-NEXT: # %bb.4: # %do_cmpxchg -; RV64IA-ZACAS-NEXT: # in Loop: Header=BB3_3 Depth=2 +; RV64IA-ZACAS-NEXT: bne a5, a1, .LBB3_4 +; RV64IA-ZACAS-NEXT: # %bb.3: # %do_cmpxchg +; RV64IA-ZACAS-NEXT: # in Loop: Header=BB3_2 Depth=2 ; RV64IA-ZACAS-NEXT: xor a5, a4, a2 ; RV64IA-ZACAS-NEXT: and a5, a5, a0 ; RV64IA-ZACAS-NEXT: xor a5, a4, a5 ; RV64IA-ZACAS-NEXT: sc.w.rl a5, a5, (a3) -; RV64IA-ZACAS-NEXT: bnez a5, .LBB3_3 -; RV64IA-ZACAS-NEXT: .LBB3_5: # %do_cmpxchg +; RV64IA-ZACAS-NEXT: bnez a5, .LBB3_2 +; RV64IA-ZACAS-NEXT: .LBB3_4: # %do_cmpxchg ; RV64IA-ZACAS-NEXT: # in Loop: Header=BB3_1 Depth=1 ; RV64IA-ZACAS-NEXT: and a4, a4, a0 ; RV64IA-ZACAS-NEXT: beq a1, a4, .LBB3_1 -; RV64IA-ZACAS-NEXT: # %bb.2: # %exit +; RV64IA-ZACAS-NEXT: # %bb.5: # %exit ; RV64IA-ZACAS-NEXT: ret ; ; RV64IA-ZABHA-LABEL: cmpxchg_masked_and_branch2: @@ -392,20 +392,20 @@ define void @cmpxchg_and_irrelevant_branch(ptr %ptr, i32 signext %cmp, i32 signe ; NOZACAS: # %bb.0: # %entry ; NOZACAS-NEXT: .LBB4_1: # %do_cmpxchg ; NOZACAS-NEXT: # =>This Loop Header: Depth=1 -; NOZACAS-NEXT: # Child Loop BB4_3 Depth 2 -; NOZACAS-NEXT: .LBB4_3: # %do_cmpxchg +; NOZACAS-NEXT: # Child Loop BB4_2 Depth 2 +; NOZACAS-NEXT: .LBB4_2: # %do_cmpxchg ; NOZACAS-NEXT: # Parent Loop BB4_1 Depth=1 ; NOZACAS-NEXT: # => This Inner Loop Header: Depth=2 ; NOZACAS-NEXT: lr.w.aqrl a4, (a0) -; NOZACAS-NEXT: bne a4, a1, .LBB4_5 -; NOZACAS-NEXT: # %bb.4: # %do_cmpxchg -; NOZACAS-NEXT: # in Loop: Header=BB4_3 Depth=2 +; NOZACAS-NEXT: bne a4, a1, .LBB4_4 +; NOZACAS-NEXT: # %bb.3: # %do_cmpxchg +; NOZACAS-NEXT: # in Loop: Header=BB4_2 Depth=2 ; NOZACAS-NEXT: sc.w.rl a5, a2, (a0) -; NOZACAS-NEXT: bnez a5, .LBB4_3 -; NOZACAS-NEXT: .LBB4_5: # %do_cmpxchg +; NOZACAS-NEXT: bnez a5, .LBB4_2 +; NOZACAS-NEXT: .LBB4_4: # %do_cmpxchg ; NOZACAS-NEXT: # in Loop: Header=BB4_1 Depth=1 ; NOZACAS-NEXT: beqz a3, .LBB4_1 -; NOZACAS-NEXT: # %bb.2: # %exit +; NOZACAS-NEXT: # %bb.5: # %exit ; NOZACAS-NEXT: ret ; ; ZACAS-LABEL: cmpxchg_and_irrelevant_branch: diff --git a/llvm/test/CodeGen/RISCV/atomic-signext.ll b/llvm/test/CodeGen/RISCV/atomic-signext.ll index 74ff20db12b62..78bc32190d9dd 100644 --- a/llvm/test/CodeGen/RISCV/atomic-signext.ll +++ b/llvm/test/CodeGen/RISCV/atomic-signext.ll @@ -6365,18 +6365,18 @@ define signext i32 @atomicrmw_xchg_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV32I-ZALRSC: # %bb.0: ; RV32I-ZALRSC-NEXT: andi a2, a1, 1 ; RV32I-ZALRSC-NEXT: mv a1, a0 -; RV32I-ZALRSC-NEXT: beqz a2, .LBB53_2 +; RV32I-ZALRSC-NEXT: beqz a2, .LBB53_4 ; RV32I-ZALRSC-NEXT: # %bb.1: # %then ; RV32I-ZALRSC-NEXT: li a2, 1 -; RV32I-ZALRSC-NEXT: .LBB53_3: # %then +; RV32I-ZALRSC-NEXT: .LBB53_2: # %then ; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-ZALRSC-NEXT: lr.w a0, (a1) ; RV32I-ZALRSC-NEXT: mv a3, a2 ; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a1) -; RV32I-ZALRSC-NEXT: bnez a3, .LBB53_3 -; RV32I-ZALRSC-NEXT: # %bb.4: # %then +; RV32I-ZALRSC-NEXT: bnez a3, .LBB53_2 +; RV32I-ZALRSC-NEXT: # %bb.3: # %then ; RV32I-ZALRSC-NEXT: ret -; RV32I-ZALRSC-NEXT: .LBB53_2: # %else +; RV32I-ZALRSC-NEXT: .LBB53_4: # %else ; RV32I-ZALRSC-NEXT: lw a0, 0(a1) ; RV32I-ZALRSC-NEXT: li a2, 1 ; RV32I-ZALRSC-NEXT: sw a2, 0(a1) @@ -6421,19 +6421,19 @@ define signext i32 @atomicrmw_xchg_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV64I-ZALRSC-LABEL: atomicrmw_xchg_i32_monotonic_crossbb: ; RV64I-ZALRSC: # %bb.0: ; RV64I-ZALRSC-NEXT: andi a1, a1, 1 -; RV64I-ZALRSC-NEXT: beqz a1, .LBB53_2 +; RV64I-ZALRSC-NEXT: beqz a1, .LBB53_4 ; RV64I-ZALRSC-NEXT: # %bb.1: # %then ; RV64I-ZALRSC-NEXT: li a2, 1 -; RV64I-ZALRSC-NEXT: .LBB53_3: # %then +; RV64I-ZALRSC-NEXT: .LBB53_2: # %then ; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-ZALRSC-NEXT: lr.w a1, (a0) ; RV64I-ZALRSC-NEXT: mv a3, a2 ; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) -; RV64I-ZALRSC-NEXT: bnez a3, .LBB53_3 -; RV64I-ZALRSC-NEXT: # %bb.4: # %then +; RV64I-ZALRSC-NEXT: bnez a3, .LBB53_2 +; RV64I-ZALRSC-NEXT: # %bb.3: # %then ; RV64I-ZALRSC-NEXT: sext.w a0, a1 ; RV64I-ZALRSC-NEXT: ret -; RV64I-ZALRSC-NEXT: .LBB53_2: # %else +; RV64I-ZALRSC-NEXT: .LBB53_4: # %else ; RV64I-ZALRSC-NEXT: lw a1, 0(a0) ; RV64I-ZALRSC-NEXT: li a2, 1 ; RV64I-ZALRSC-NEXT: sw a2, 0(a0) @@ -6495,18 +6495,18 @@ define signext i32 @atomicrmw_add_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV32I-ZALRSC: # %bb.0: ; RV32I-ZALRSC-NEXT: andi a2, a1, 1 ; RV32I-ZALRSC-NEXT: mv a1, a0 -; RV32I-ZALRSC-NEXT: beqz a2, .LBB54_2 +; RV32I-ZALRSC-NEXT: beqz a2, .LBB54_4 ; RV32I-ZALRSC-NEXT: # %bb.1: # %then ; RV32I-ZALRSC-NEXT: li a2, 1 -; RV32I-ZALRSC-NEXT: .LBB54_3: # %then +; RV32I-ZALRSC-NEXT: .LBB54_2: # %then ; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-ZALRSC-NEXT: lr.w a0, (a1) ; RV32I-ZALRSC-NEXT: add a3, a0, a2 ; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a1) -; RV32I-ZALRSC-NEXT: bnez a3, .LBB54_3 -; RV32I-ZALRSC-NEXT: # %bb.4: # %then +; RV32I-ZALRSC-NEXT: bnez a3, .LBB54_2 +; RV32I-ZALRSC-NEXT: # %bb.3: # %then ; RV32I-ZALRSC-NEXT: ret -; RV32I-ZALRSC-NEXT: .LBB54_2: # %else +; RV32I-ZALRSC-NEXT: .LBB54_4: # %else ; RV32I-ZALRSC-NEXT: lw a0, 0(a1) ; RV32I-ZALRSC-NEXT: addi a2, a0, 1 ; RV32I-ZALRSC-NEXT: sw a2, 0(a1) @@ -6551,19 +6551,19 @@ define signext i32 @atomicrmw_add_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV64I-ZALRSC-LABEL: atomicrmw_add_i32_monotonic_crossbb: ; RV64I-ZALRSC: # %bb.0: ; RV64I-ZALRSC-NEXT: andi a1, a1, 1 -; RV64I-ZALRSC-NEXT: beqz a1, .LBB54_2 +; RV64I-ZALRSC-NEXT: beqz a1, .LBB54_4 ; RV64I-ZALRSC-NEXT: # %bb.1: # %then ; RV64I-ZALRSC-NEXT: li a2, 1 -; RV64I-ZALRSC-NEXT: .LBB54_3: # %then +; RV64I-ZALRSC-NEXT: .LBB54_2: # %then ; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-ZALRSC-NEXT: lr.w a1, (a0) ; RV64I-ZALRSC-NEXT: add a3, a1, a2 ; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) -; RV64I-ZALRSC-NEXT: bnez a3, .LBB54_3 -; RV64I-ZALRSC-NEXT: # %bb.4: # %then +; RV64I-ZALRSC-NEXT: bnez a3, .LBB54_2 +; RV64I-ZALRSC-NEXT: # %bb.3: # %then ; RV64I-ZALRSC-NEXT: sext.w a0, a1 ; RV64I-ZALRSC-NEXT: ret -; RV64I-ZALRSC-NEXT: .LBB54_2: # %else +; RV64I-ZALRSC-NEXT: .LBB54_4: # %else ; RV64I-ZALRSC-NEXT: lw a1, 0(a0) ; RV64I-ZALRSC-NEXT: addi a2, a1, 1 ; RV64I-ZALRSC-NEXT: sw a2, 0(a0) @@ -6626,18 +6626,18 @@ define signext i32 @atomicrmw_sub_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV32I-ZALRSC: # %bb.0: ; RV32I-ZALRSC-NEXT: andi a2, a1, 1 ; RV32I-ZALRSC-NEXT: mv a1, a0 -; RV32I-ZALRSC-NEXT: beqz a2, .LBB55_2 +; RV32I-ZALRSC-NEXT: beqz a2, .LBB55_4 ; RV32I-ZALRSC-NEXT: # %bb.1: # %then ; RV32I-ZALRSC-NEXT: li a2, 1 -; RV32I-ZALRSC-NEXT: .LBB55_3: # %then +; RV32I-ZALRSC-NEXT: .LBB55_2: # %then ; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-ZALRSC-NEXT: lr.w a0, (a1) ; RV32I-ZALRSC-NEXT: sub a3, a0, a2 ; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a1) -; RV32I-ZALRSC-NEXT: bnez a3, .LBB55_3 -; RV32I-ZALRSC-NEXT: # %bb.4: # %then +; RV32I-ZALRSC-NEXT: bnez a3, .LBB55_2 +; RV32I-ZALRSC-NEXT: # %bb.3: # %then ; RV32I-ZALRSC-NEXT: ret -; RV32I-ZALRSC-NEXT: .LBB55_2: # %else +; RV32I-ZALRSC-NEXT: .LBB55_4: # %else ; RV32I-ZALRSC-NEXT: lw a0, 0(a1) ; RV32I-ZALRSC-NEXT: addi a2, a0, -1 ; RV32I-ZALRSC-NEXT: sw a2, 0(a1) @@ -6682,19 +6682,19 @@ define signext i32 @atomicrmw_sub_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV64I-ZALRSC-LABEL: atomicrmw_sub_i32_monotonic_crossbb: ; RV64I-ZALRSC: # %bb.0: ; RV64I-ZALRSC-NEXT: andi a1, a1, 1 -; RV64I-ZALRSC-NEXT: beqz a1, .LBB55_2 +; RV64I-ZALRSC-NEXT: beqz a1, .LBB55_4 ; RV64I-ZALRSC-NEXT: # %bb.1: # %then ; RV64I-ZALRSC-NEXT: li a2, 1 -; RV64I-ZALRSC-NEXT: .LBB55_3: # %then +; RV64I-ZALRSC-NEXT: .LBB55_2: # %then ; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-ZALRSC-NEXT: lr.w a1, (a0) ; RV64I-ZALRSC-NEXT: sub a3, a1, a2 ; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) -; RV64I-ZALRSC-NEXT: bnez a3, .LBB55_3 -; RV64I-ZALRSC-NEXT: # %bb.4: # %then +; RV64I-ZALRSC-NEXT: bnez a3, .LBB55_2 +; RV64I-ZALRSC-NEXT: # %bb.3: # %then ; RV64I-ZALRSC-NEXT: sext.w a0, a1 ; RV64I-ZALRSC-NEXT: ret -; RV64I-ZALRSC-NEXT: .LBB55_2: # %else +; RV64I-ZALRSC-NEXT: .LBB55_4: # %else ; RV64I-ZALRSC-NEXT: lw a1, 0(a0) ; RV64I-ZALRSC-NEXT: addi a2, a1, -1 ; RV64I-ZALRSC-NEXT: sw a2, 0(a0) @@ -6757,18 +6757,18 @@ define signext i32 @atomicrmw_and_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV32I-ZALRSC: # %bb.0: ; RV32I-ZALRSC-NEXT: andi a2, a1, 1 ; RV32I-ZALRSC-NEXT: mv a1, a0 -; RV32I-ZALRSC-NEXT: beqz a2, .LBB56_2 +; RV32I-ZALRSC-NEXT: beqz a2, .LBB56_4 ; RV32I-ZALRSC-NEXT: # %bb.1: # %then ; RV32I-ZALRSC-NEXT: li a2, 1 -; RV32I-ZALRSC-NEXT: .LBB56_3: # %then +; RV32I-ZALRSC-NEXT: .LBB56_2: # %then ; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-ZALRSC-NEXT: lr.w a0, (a1) ; RV32I-ZALRSC-NEXT: and a3, a0, a2 ; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a1) -; RV32I-ZALRSC-NEXT: bnez a3, .LBB56_3 -; RV32I-ZALRSC-NEXT: # %bb.4: # %then +; RV32I-ZALRSC-NEXT: bnez a3, .LBB56_2 +; RV32I-ZALRSC-NEXT: # %bb.3: # %then ; RV32I-ZALRSC-NEXT: ret -; RV32I-ZALRSC-NEXT: .LBB56_2: # %else +; RV32I-ZALRSC-NEXT: .LBB56_4: # %else ; RV32I-ZALRSC-NEXT: lw a0, 0(a1) ; RV32I-ZALRSC-NEXT: andi a2, a0, 1 ; RV32I-ZALRSC-NEXT: sw a2, 0(a1) @@ -6813,19 +6813,19 @@ define signext i32 @atomicrmw_and_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV64I-ZALRSC-LABEL: atomicrmw_and_i32_monotonic_crossbb: ; RV64I-ZALRSC: # %bb.0: ; RV64I-ZALRSC-NEXT: andi a1, a1, 1 -; RV64I-ZALRSC-NEXT: beqz a1, .LBB56_2 +; RV64I-ZALRSC-NEXT: beqz a1, .LBB56_4 ; RV64I-ZALRSC-NEXT: # %bb.1: # %then ; RV64I-ZALRSC-NEXT: li a2, 1 -; RV64I-ZALRSC-NEXT: .LBB56_3: # %then +; RV64I-ZALRSC-NEXT: .LBB56_2: # %then ; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-ZALRSC-NEXT: lr.w a1, (a0) ; RV64I-ZALRSC-NEXT: and a3, a1, a2 ; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) -; RV64I-ZALRSC-NEXT: bnez a3, .LBB56_3 -; RV64I-ZALRSC-NEXT: # %bb.4: # %then +; RV64I-ZALRSC-NEXT: bnez a3, .LBB56_2 +; RV64I-ZALRSC-NEXT: # %bb.3: # %then ; RV64I-ZALRSC-NEXT: sext.w a0, a1 ; RV64I-ZALRSC-NEXT: ret -; RV64I-ZALRSC-NEXT: .LBB56_2: # %else +; RV64I-ZALRSC-NEXT: .LBB56_4: # %else ; RV64I-ZALRSC-NEXT: lw a1, 0(a0) ; RV64I-ZALRSC-NEXT: andi a2, a1, 1 ; RV64I-ZALRSC-NEXT: sw a2, 0(a0) @@ -6873,19 +6873,19 @@ define signext i32 @atomicrmw_nand_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: andi a2, a1, 1 ; RV32IA-NOZACAS-NEXT: mv a1, a0 -; RV32IA-NOZACAS-NEXT: beqz a2, .LBB57_2 +; RV32IA-NOZACAS-NEXT: beqz a2, .LBB57_4 ; RV32IA-NOZACAS-NEXT: # %bb.1: # %then ; RV32IA-NOZACAS-NEXT: li a2, 1 -; RV32IA-NOZACAS-NEXT: .LBB57_3: # %then +; RV32IA-NOZACAS-NEXT: .LBB57_2: # %then ; RV32IA-NOZACAS-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32IA-NOZACAS-NEXT: lr.w a0, (a1) ; RV32IA-NOZACAS-NEXT: and a3, a0, a2 ; RV32IA-NOZACAS-NEXT: not a3, a3 ; RV32IA-NOZACAS-NEXT: sc.w a3, a3, (a1) -; RV32IA-NOZACAS-NEXT: bnez a3, .LBB57_3 -; RV32IA-NOZACAS-NEXT: # %bb.4: # %then +; RV32IA-NOZACAS-NEXT: bnez a3, .LBB57_2 +; RV32IA-NOZACAS-NEXT: # %bb.3: # %then ; RV32IA-NOZACAS-NEXT: ret -; RV32IA-NOZACAS-NEXT: .LBB57_2: # %else +; RV32IA-NOZACAS-NEXT: .LBB57_4: # %else ; RV32IA-NOZACAS-NEXT: lw a0, 0(a1) ; RV32IA-NOZACAS-NEXT: andi a2, a0, 1 ; RV32IA-NOZACAS-NEXT: sw a2, 0(a1) @@ -6918,19 +6918,19 @@ define signext i32 @atomicrmw_nand_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV32I-ZALRSC: # %bb.0: ; RV32I-ZALRSC-NEXT: andi a2, a1, 1 ; RV32I-ZALRSC-NEXT: mv a1, a0 -; RV32I-ZALRSC-NEXT: beqz a2, .LBB57_2 +; RV32I-ZALRSC-NEXT: beqz a2, .LBB57_4 ; RV32I-ZALRSC-NEXT: # %bb.1: # %then ; RV32I-ZALRSC-NEXT: li a2, 1 -; RV32I-ZALRSC-NEXT: .LBB57_3: # %then +; RV32I-ZALRSC-NEXT: .LBB57_2: # %then ; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-ZALRSC-NEXT: lr.w a0, (a1) ; RV32I-ZALRSC-NEXT: and a3, a0, a2 ; RV32I-ZALRSC-NEXT: not a3, a3 ; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a1) -; RV32I-ZALRSC-NEXT: bnez a3, .LBB57_3 -; RV32I-ZALRSC-NEXT: # %bb.4: # %then +; RV32I-ZALRSC-NEXT: bnez a3, .LBB57_2 +; RV32I-ZALRSC-NEXT: # %bb.3: # %then ; RV32I-ZALRSC-NEXT: ret -; RV32I-ZALRSC-NEXT: .LBB57_2: # %else +; RV32I-ZALRSC-NEXT: .LBB57_4: # %else ; RV32I-ZALRSC-NEXT: lw a0, 0(a1) ; RV32I-ZALRSC-NEXT: andi a2, a0, 1 ; RV32I-ZALRSC-NEXT: sw a2, 0(a1) @@ -6961,19 +6961,19 @@ define signext i32 @atomicrmw_nand_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV64IA-NOZACAS: # %bb.0: ; RV64IA-NOZACAS-NEXT: andi a2, a1, 1 ; RV64IA-NOZACAS-NEXT: mv a1, a0 -; RV64IA-NOZACAS-NEXT: beqz a2, .LBB57_2 +; RV64IA-NOZACAS-NEXT: beqz a2, .LBB57_4 ; RV64IA-NOZACAS-NEXT: # %bb.1: # %then ; RV64IA-NOZACAS-NEXT: li a2, 1 -; RV64IA-NOZACAS-NEXT: .LBB57_3: # %then +; RV64IA-NOZACAS-NEXT: .LBB57_2: # %then ; RV64IA-NOZACAS-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64IA-NOZACAS-NEXT: lr.w a0, (a1) ; RV64IA-NOZACAS-NEXT: and a3, a0, a2 ; RV64IA-NOZACAS-NEXT: not a3, a3 ; RV64IA-NOZACAS-NEXT: sc.w a3, a3, (a1) -; RV64IA-NOZACAS-NEXT: bnez a3, .LBB57_3 -; RV64IA-NOZACAS-NEXT: # %bb.4: # %then +; RV64IA-NOZACAS-NEXT: bnez a3, .LBB57_2 +; RV64IA-NOZACAS-NEXT: # %bb.3: # %then ; RV64IA-NOZACAS-NEXT: ret -; RV64IA-NOZACAS-NEXT: .LBB57_2: # %else +; RV64IA-NOZACAS-NEXT: .LBB57_4: # %else ; RV64IA-NOZACAS-NEXT: lw a0, 0(a1) ; RV64IA-NOZACAS-NEXT: andi a2, a0, 1 ; RV64IA-NOZACAS-NEXT: sw a2, 0(a1) @@ -7006,19 +7006,19 @@ define signext i32 @atomicrmw_nand_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV64I-ZALRSC: # %bb.0: ; RV64I-ZALRSC-NEXT: andi a2, a1, 1 ; RV64I-ZALRSC-NEXT: mv a1, a0 -; RV64I-ZALRSC-NEXT: beqz a2, .LBB57_2 +; RV64I-ZALRSC-NEXT: beqz a2, .LBB57_4 ; RV64I-ZALRSC-NEXT: # %bb.1: # %then ; RV64I-ZALRSC-NEXT: li a2, 1 -; RV64I-ZALRSC-NEXT: .LBB57_3: # %then +; RV64I-ZALRSC-NEXT: .LBB57_2: # %then ; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-ZALRSC-NEXT: lr.w a0, (a1) ; RV64I-ZALRSC-NEXT: and a3, a0, a2 ; RV64I-ZALRSC-NEXT: not a3, a3 ; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a1) -; RV64I-ZALRSC-NEXT: bnez a3, .LBB57_3 -; RV64I-ZALRSC-NEXT: # %bb.4: # %then +; RV64I-ZALRSC-NEXT: bnez a3, .LBB57_2 +; RV64I-ZALRSC-NEXT: # %bb.3: # %then ; RV64I-ZALRSC-NEXT: ret -; RV64I-ZALRSC-NEXT: .LBB57_2: # %else +; RV64I-ZALRSC-NEXT: .LBB57_4: # %else ; RV64I-ZALRSC-NEXT: lw a0, 0(a1) ; RV64I-ZALRSC-NEXT: andi a2, a0, 1 ; RV64I-ZALRSC-NEXT: sw a2, 0(a1) @@ -7080,18 +7080,18 @@ define signext i32 @atomicrmw_or_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind { ; RV32I-ZALRSC: # %bb.0: ; RV32I-ZALRSC-NEXT: andi a2, a1, 1 ; RV32I-ZALRSC-NEXT: mv a1, a0 -; RV32I-ZALRSC-NEXT: beqz a2, .LBB58_2 +; RV32I-ZALRSC-NEXT: beqz a2, .LBB58_4 ; RV32I-ZALRSC-NEXT: # %bb.1: # %then ; RV32I-ZALRSC-NEXT: li a2, 1 -; RV32I-ZALRSC-NEXT: .LBB58_3: # %then +; RV32I-ZALRSC-NEXT: .LBB58_2: # %then ; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-ZALRSC-NEXT: lr.w a0, (a1) ; RV32I-ZALRSC-NEXT: or a3, a0, a2 ; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a1) -; RV32I-ZALRSC-NEXT: bnez a3, .LBB58_3 -; RV32I-ZALRSC-NEXT: # %bb.4: # %then +; RV32I-ZALRSC-NEXT: bnez a3, .LBB58_2 +; RV32I-ZALRSC-NEXT: # %bb.3: # %then ; RV32I-ZALRSC-NEXT: ret -; RV32I-ZALRSC-NEXT: .LBB58_2: # %else +; RV32I-ZALRSC-NEXT: .LBB58_4: # %else ; RV32I-ZALRSC-NEXT: lw a0, 0(a1) ; RV32I-ZALRSC-NEXT: ori a2, a0, 1 ; RV32I-ZALRSC-NEXT: sw a2, 0(a1) @@ -7136,19 +7136,19 @@ define signext i32 @atomicrmw_or_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind { ; RV64I-ZALRSC-LABEL: atomicrmw_or_i32_monotonic_crossbb: ; RV64I-ZALRSC: # %bb.0: ; RV64I-ZALRSC-NEXT: andi a1, a1, 1 -; RV64I-ZALRSC-NEXT: beqz a1, .LBB58_2 +; RV64I-ZALRSC-NEXT: beqz a1, .LBB58_4 ; RV64I-ZALRSC-NEXT: # %bb.1: # %then ; RV64I-ZALRSC-NEXT: li a2, 1 -; RV64I-ZALRSC-NEXT: .LBB58_3: # %then +; RV64I-ZALRSC-NEXT: .LBB58_2: # %then ; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-ZALRSC-NEXT: lr.w a1, (a0) ; RV64I-ZALRSC-NEXT: or a3, a1, a2 ; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) -; RV64I-ZALRSC-NEXT: bnez a3, .LBB58_3 -; RV64I-ZALRSC-NEXT: # %bb.4: # %then +; RV64I-ZALRSC-NEXT: bnez a3, .LBB58_2 +; RV64I-ZALRSC-NEXT: # %bb.3: # %then ; RV64I-ZALRSC-NEXT: sext.w a0, a1 ; RV64I-ZALRSC-NEXT: ret -; RV64I-ZALRSC-NEXT: .LBB58_2: # %else +; RV64I-ZALRSC-NEXT: .LBB58_4: # %else ; RV64I-ZALRSC-NEXT: lw a1, 0(a0) ; RV64I-ZALRSC-NEXT: ori a2, a1, 1 ; RV64I-ZALRSC-NEXT: sw a2, 0(a0) @@ -7211,18 +7211,18 @@ define signext i32 @atomicrmw_xor_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV32I-ZALRSC: # %bb.0: ; RV32I-ZALRSC-NEXT: andi a2, a1, 1 ; RV32I-ZALRSC-NEXT: mv a1, a0 -; RV32I-ZALRSC-NEXT: beqz a2, .LBB59_2 +; RV32I-ZALRSC-NEXT: beqz a2, .LBB59_4 ; RV32I-ZALRSC-NEXT: # %bb.1: # %then ; RV32I-ZALRSC-NEXT: li a2, 1 -; RV32I-ZALRSC-NEXT: .LBB59_3: # %then +; RV32I-ZALRSC-NEXT: .LBB59_2: # %then ; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-ZALRSC-NEXT: lr.w a0, (a1) ; RV32I-ZALRSC-NEXT: xor a3, a0, a2 ; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a1) -; RV32I-ZALRSC-NEXT: bnez a3, .LBB59_3 -; RV32I-ZALRSC-NEXT: # %bb.4: # %then +; RV32I-ZALRSC-NEXT: bnez a3, .LBB59_2 +; RV32I-ZALRSC-NEXT: # %bb.3: # %then ; RV32I-ZALRSC-NEXT: ret -; RV32I-ZALRSC-NEXT: .LBB59_2: # %else +; RV32I-ZALRSC-NEXT: .LBB59_4: # %else ; RV32I-ZALRSC-NEXT: lw a0, 0(a1) ; RV32I-ZALRSC-NEXT: xori a2, a0, 1 ; RV32I-ZALRSC-NEXT: sw a2, 0(a1) @@ -7267,19 +7267,19 @@ define signext i32 @atomicrmw_xor_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV64I-ZALRSC-LABEL: atomicrmw_xor_i32_monotonic_crossbb: ; RV64I-ZALRSC: # %bb.0: ; RV64I-ZALRSC-NEXT: andi a1, a1, 1 -; RV64I-ZALRSC-NEXT: beqz a1, .LBB59_2 +; RV64I-ZALRSC-NEXT: beqz a1, .LBB59_4 ; RV64I-ZALRSC-NEXT: # %bb.1: # %then ; RV64I-ZALRSC-NEXT: li a2, 1 -; RV64I-ZALRSC-NEXT: .LBB59_3: # %then +; RV64I-ZALRSC-NEXT: .LBB59_2: # %then ; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-ZALRSC-NEXT: lr.w a1, (a0) ; RV64I-ZALRSC-NEXT: xor a3, a1, a2 ; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) -; RV64I-ZALRSC-NEXT: bnez a3, .LBB59_3 -; RV64I-ZALRSC-NEXT: # %bb.4: # %then +; RV64I-ZALRSC-NEXT: bnez a3, .LBB59_2 +; RV64I-ZALRSC-NEXT: # %bb.3: # %then ; RV64I-ZALRSC-NEXT: sext.w a0, a1 ; RV64I-ZALRSC-NEXT: ret -; RV64I-ZALRSC-NEXT: .LBB59_2: # %else +; RV64I-ZALRSC-NEXT: .LBB59_4: # %else ; RV64I-ZALRSC-NEXT: lw a1, 0(a0) ; RV64I-ZALRSC-NEXT: xori a2, a1, 1 ; RV64I-ZALRSC-NEXT: sw a2, 0(a0) @@ -7370,30 +7370,30 @@ define signext i32 @atomicrmw_max_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV32I-ZALRSC: # %bb.0: ; RV32I-ZALRSC-NEXT: andi a2, a1, 1 ; RV32I-ZALRSC-NEXT: mv a1, a0 -; RV32I-ZALRSC-NEXT: beqz a2, .LBB60_2 +; RV32I-ZALRSC-NEXT: beqz a2, .LBB60_6 ; RV32I-ZALRSC-NEXT: # %bb.1: # %then ; RV32I-ZALRSC-NEXT: li a2, 1 -; RV32I-ZALRSC-NEXT: .LBB60_5: # %then +; RV32I-ZALRSC-NEXT: .LBB60_2: # %then ; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-ZALRSC-NEXT: lr.w a0, (a1) ; RV32I-ZALRSC-NEXT: mv a3, a0 -; RV32I-ZALRSC-NEXT: bge a3, a2, .LBB60_7 -; RV32I-ZALRSC-NEXT: # %bb.6: # %then -; RV32I-ZALRSC-NEXT: # in Loop: Header=BB60_5 Depth=1 +; RV32I-ZALRSC-NEXT: bge a3, a2, .LBB60_4 +; RV32I-ZALRSC-NEXT: # %bb.3: # %then +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB60_2 Depth=1 ; RV32I-ZALRSC-NEXT: mv a3, a2 -; RV32I-ZALRSC-NEXT: .LBB60_7: # %then -; RV32I-ZALRSC-NEXT: # in Loop: Header=BB60_5 Depth=1 +; RV32I-ZALRSC-NEXT: .LBB60_4: # %then +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB60_2 Depth=1 ; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a1) -; RV32I-ZALRSC-NEXT: bnez a3, .LBB60_5 -; RV32I-ZALRSC-NEXT: # %bb.8: # %then +; RV32I-ZALRSC-NEXT: bnez a3, .LBB60_2 +; RV32I-ZALRSC-NEXT: # %bb.5: # %then ; RV32I-ZALRSC-NEXT: ret -; RV32I-ZALRSC-NEXT: .LBB60_2: # %else +; RV32I-ZALRSC-NEXT: .LBB60_6: # %else ; RV32I-ZALRSC-NEXT: lw a0, 0(a1) ; RV32I-ZALRSC-NEXT: mv a2, a0 -; RV32I-ZALRSC-NEXT: bgtz a0, .LBB60_4 -; RV32I-ZALRSC-NEXT: # %bb.3: # %else +; RV32I-ZALRSC-NEXT: bgtz a0, .LBB60_8 +; RV32I-ZALRSC-NEXT: # %bb.7: # %else ; RV32I-ZALRSC-NEXT: li a2, 1 -; RV32I-ZALRSC-NEXT: .LBB60_4: # %else +; RV32I-ZALRSC-NEXT: .LBB60_8: # %else ; RV32I-ZALRSC-NEXT: sw a2, 0(a1) ; RV32I-ZALRSC-NEXT: ret ; @@ -7465,30 +7465,30 @@ define signext i32 @atomicrmw_max_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV64I-ZALRSC: # %bb.0: ; RV64I-ZALRSC-NEXT: andi a2, a1, 1 ; RV64I-ZALRSC-NEXT: mv a1, a0 -; RV64I-ZALRSC-NEXT: beqz a2, .LBB60_2 +; RV64I-ZALRSC-NEXT: beqz a2, .LBB60_6 ; RV64I-ZALRSC-NEXT: # %bb.1: # %then ; RV64I-ZALRSC-NEXT: li a2, 1 -; RV64I-ZALRSC-NEXT: .LBB60_5: # %then +; RV64I-ZALRSC-NEXT: .LBB60_2: # %then ; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-ZALRSC-NEXT: lr.w a0, (a1) ; RV64I-ZALRSC-NEXT: mv a3, a0 -; RV64I-ZALRSC-NEXT: bge a3, a2, .LBB60_7 -; RV64I-ZALRSC-NEXT: # %bb.6: # %then -; RV64I-ZALRSC-NEXT: # in Loop: Header=BB60_5 Depth=1 +; RV64I-ZALRSC-NEXT: bge a3, a2, .LBB60_4 +; RV64I-ZALRSC-NEXT: # %bb.3: # %then +; RV64I-ZALRSC-NEXT: # in Loop: Header=BB60_2 Depth=1 ; RV64I-ZALRSC-NEXT: mv a3, a2 -; RV64I-ZALRSC-NEXT: .LBB60_7: # %then -; RV64I-ZALRSC-NEXT: # in Loop: Header=BB60_5 Depth=1 +; RV64I-ZALRSC-NEXT: .LBB60_4: # %then +; RV64I-ZALRSC-NEXT: # in Loop: Header=BB60_2 Depth=1 ; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a1) -; RV64I-ZALRSC-NEXT: bnez a3, .LBB60_5 -; RV64I-ZALRSC-NEXT: # %bb.8: # %then +; RV64I-ZALRSC-NEXT: bnez a3, .LBB60_2 +; RV64I-ZALRSC-NEXT: # %bb.5: # %then ; RV64I-ZALRSC-NEXT: ret -; RV64I-ZALRSC-NEXT: .LBB60_2: # %else +; RV64I-ZALRSC-NEXT: .LBB60_6: # %else ; RV64I-ZALRSC-NEXT: lw a0, 0(a1) ; RV64I-ZALRSC-NEXT: mv a2, a0 -; RV64I-ZALRSC-NEXT: bgtz a0, .LBB60_4 -; RV64I-ZALRSC-NEXT: # %bb.3: # %else +; RV64I-ZALRSC-NEXT: bgtz a0, .LBB60_8 +; RV64I-ZALRSC-NEXT: # %bb.7: # %else ; RV64I-ZALRSC-NEXT: li a2, 1 -; RV64I-ZALRSC-NEXT: .LBB60_4: # %else +; RV64I-ZALRSC-NEXT: .LBB60_8: # %else ; RV64I-ZALRSC-NEXT: sw a2, 0(a1) ; RV64I-ZALRSC-NEXT: ret br i1 %c, label %then, label %else @@ -7579,30 +7579,30 @@ define signext i32 @atomicrmw_min_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV32I-ZALRSC: # %bb.0: ; RV32I-ZALRSC-NEXT: andi a2, a1, 1 ; RV32I-ZALRSC-NEXT: mv a1, a0 -; RV32I-ZALRSC-NEXT: beqz a2, .LBB61_2 +; RV32I-ZALRSC-NEXT: beqz a2, .LBB61_6 ; RV32I-ZALRSC-NEXT: # %bb.1: # %then ; RV32I-ZALRSC-NEXT: li a2, 1 -; RV32I-ZALRSC-NEXT: .LBB61_5: # %then +; RV32I-ZALRSC-NEXT: .LBB61_2: # %then ; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-ZALRSC-NEXT: lr.w a0, (a1) ; RV32I-ZALRSC-NEXT: mv a3, a0 -; RV32I-ZALRSC-NEXT: bge a2, a3, .LBB61_7 -; RV32I-ZALRSC-NEXT: # %bb.6: # %then -; RV32I-ZALRSC-NEXT: # in Loop: Header=BB61_5 Depth=1 +; RV32I-ZALRSC-NEXT: bge a2, a3, .LBB61_4 +; RV32I-ZALRSC-NEXT: # %bb.3: # %then +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB61_2 Depth=1 ; RV32I-ZALRSC-NEXT: mv a3, a2 -; RV32I-ZALRSC-NEXT: .LBB61_7: # %then -; RV32I-ZALRSC-NEXT: # in Loop: Header=BB61_5 Depth=1 +; RV32I-ZALRSC-NEXT: .LBB61_4: # %then +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB61_2 Depth=1 ; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a1) -; RV32I-ZALRSC-NEXT: bnez a3, .LBB61_5 -; RV32I-ZALRSC-NEXT: # %bb.8: # %then +; RV32I-ZALRSC-NEXT: bnez a3, .LBB61_2 +; RV32I-ZALRSC-NEXT: # %bb.5: # %then ; RV32I-ZALRSC-NEXT: ret -; RV32I-ZALRSC-NEXT: .LBB61_2: # %else +; RV32I-ZALRSC-NEXT: .LBB61_6: # %else ; RV32I-ZALRSC-NEXT: lw a0, 0(a1) ; RV32I-ZALRSC-NEXT: mv a2, a0 -; RV32I-ZALRSC-NEXT: blez a0, .LBB61_4 -; RV32I-ZALRSC-NEXT: # %bb.3: # %else +; RV32I-ZALRSC-NEXT: blez a0, .LBB61_8 +; RV32I-ZALRSC-NEXT: # %bb.7: # %else ; RV32I-ZALRSC-NEXT: li a2, 1 -; RV32I-ZALRSC-NEXT: .LBB61_4: # %else +; RV32I-ZALRSC-NEXT: .LBB61_8: # %else ; RV32I-ZALRSC-NEXT: sw a2, 0(a1) ; RV32I-ZALRSC-NEXT: ret ; @@ -7676,30 +7676,30 @@ define signext i32 @atomicrmw_min_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV64I-ZALRSC: # %bb.0: ; RV64I-ZALRSC-NEXT: andi a2, a1, 1 ; RV64I-ZALRSC-NEXT: mv a1, a0 -; RV64I-ZALRSC-NEXT: beqz a2, .LBB61_2 +; RV64I-ZALRSC-NEXT: beqz a2, .LBB61_6 ; RV64I-ZALRSC-NEXT: # %bb.1: # %then ; RV64I-ZALRSC-NEXT: li a2, 1 -; RV64I-ZALRSC-NEXT: .LBB61_5: # %then +; RV64I-ZALRSC-NEXT: .LBB61_2: # %then ; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-ZALRSC-NEXT: lr.w a0, (a1) ; RV64I-ZALRSC-NEXT: mv a3, a0 -; RV64I-ZALRSC-NEXT: bge a2, a3, .LBB61_7 -; RV64I-ZALRSC-NEXT: # %bb.6: # %then -; RV64I-ZALRSC-NEXT: # in Loop: Header=BB61_5 Depth=1 +; RV64I-ZALRSC-NEXT: bge a2, a3, .LBB61_4 +; RV64I-ZALRSC-NEXT: # %bb.3: # %then +; RV64I-ZALRSC-NEXT: # in Loop: Header=BB61_2 Depth=1 ; RV64I-ZALRSC-NEXT: mv a3, a2 -; RV64I-ZALRSC-NEXT: .LBB61_7: # %then -; RV64I-ZALRSC-NEXT: # in Loop: Header=BB61_5 Depth=1 +; RV64I-ZALRSC-NEXT: .LBB61_4: # %then +; RV64I-ZALRSC-NEXT: # in Loop: Header=BB61_2 Depth=1 ; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a1) -; RV64I-ZALRSC-NEXT: bnez a3, .LBB61_5 -; RV64I-ZALRSC-NEXT: # %bb.8: # %then +; RV64I-ZALRSC-NEXT: bnez a3, .LBB61_2 +; RV64I-ZALRSC-NEXT: # %bb.5: # %then ; RV64I-ZALRSC-NEXT: ret -; RV64I-ZALRSC-NEXT: .LBB61_2: # %else +; RV64I-ZALRSC-NEXT: .LBB61_6: # %else ; RV64I-ZALRSC-NEXT: lw a0, 0(a1) ; RV64I-ZALRSC-NEXT: mv a2, a0 -; RV64I-ZALRSC-NEXT: blez a0, .LBB61_4 -; RV64I-ZALRSC-NEXT: # %bb.3: # %else +; RV64I-ZALRSC-NEXT: blez a0, .LBB61_8 +; RV64I-ZALRSC-NEXT: # %bb.7: # %else ; RV64I-ZALRSC-NEXT: li a2, 1 -; RV64I-ZALRSC-NEXT: .LBB61_4: # %else +; RV64I-ZALRSC-NEXT: .LBB61_8: # %else ; RV64I-ZALRSC-NEXT: sw a2, 0(a1) ; RV64I-ZALRSC-NEXT: ret br i1 %c, label %then, label %else @@ -7775,24 +7775,24 @@ define signext i32 @atomicrmw_umax_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV32I-ZALRSC: # %bb.0: ; RV32I-ZALRSC-NEXT: andi a2, a1, 1 ; RV32I-ZALRSC-NEXT: mv a1, a0 -; RV32I-ZALRSC-NEXT: beqz a2, .LBB62_2 +; RV32I-ZALRSC-NEXT: beqz a2, .LBB62_6 ; RV32I-ZALRSC-NEXT: # %bb.1: # %then ; RV32I-ZALRSC-NEXT: li a2, 1 -; RV32I-ZALRSC-NEXT: .LBB62_3: # %then +; RV32I-ZALRSC-NEXT: .LBB62_2: # %then ; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-ZALRSC-NEXT: lr.w a0, (a1) ; RV32I-ZALRSC-NEXT: mv a3, a0 -; RV32I-ZALRSC-NEXT: bgeu a3, a2, .LBB62_5 -; RV32I-ZALRSC-NEXT: # %bb.4: # %then -; RV32I-ZALRSC-NEXT: # in Loop: Header=BB62_3 Depth=1 +; RV32I-ZALRSC-NEXT: bgeu a3, a2, .LBB62_4 +; RV32I-ZALRSC-NEXT: # %bb.3: # %then +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB62_2 Depth=1 ; RV32I-ZALRSC-NEXT: mv a3, a2 -; RV32I-ZALRSC-NEXT: .LBB62_5: # %then -; RV32I-ZALRSC-NEXT: # in Loop: Header=BB62_3 Depth=1 +; RV32I-ZALRSC-NEXT: .LBB62_4: # %then +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB62_2 Depth=1 ; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a1) -; RV32I-ZALRSC-NEXT: bnez a3, .LBB62_3 -; RV32I-ZALRSC-NEXT: # %bb.6: # %then +; RV32I-ZALRSC-NEXT: bnez a3, .LBB62_2 +; RV32I-ZALRSC-NEXT: # %bb.5: # %then ; RV32I-ZALRSC-NEXT: ret -; RV32I-ZALRSC-NEXT: .LBB62_2: # %else +; RV32I-ZALRSC-NEXT: .LBB62_6: # %else ; RV32I-ZALRSC-NEXT: lw a0, 0(a1) ; RV32I-ZALRSC-NEXT: seqz a2, a0 ; RV32I-ZALRSC-NEXT: add a2, a0, a2 @@ -7860,25 +7860,25 @@ define signext i32 @atomicrmw_umax_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV64I-ZALRSC-LABEL: atomicrmw_umax_i32_monotonic_crossbb: ; RV64I-ZALRSC: # %bb.0: ; RV64I-ZALRSC-NEXT: andi a1, a1, 1 -; RV64I-ZALRSC-NEXT: beqz a1, .LBB62_2 +; RV64I-ZALRSC-NEXT: beqz a1, .LBB62_6 ; RV64I-ZALRSC-NEXT: # %bb.1: # %then ; RV64I-ZALRSC-NEXT: li a2, 1 -; RV64I-ZALRSC-NEXT: .LBB62_3: # %then +; RV64I-ZALRSC-NEXT: .LBB62_2: # %then ; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-ZALRSC-NEXT: lr.w a1, (a0) ; RV64I-ZALRSC-NEXT: mv a3, a1 -; RV64I-ZALRSC-NEXT: bgeu a3, a2, .LBB62_5 -; RV64I-ZALRSC-NEXT: # %bb.4: # %then -; RV64I-ZALRSC-NEXT: # in Loop: Header=BB62_3 Depth=1 +; RV64I-ZALRSC-NEXT: bgeu a3, a2, .LBB62_4 +; RV64I-ZALRSC-NEXT: # %bb.3: # %then +; RV64I-ZALRSC-NEXT: # in Loop: Header=BB62_2 Depth=1 ; RV64I-ZALRSC-NEXT: mv a3, a2 -; RV64I-ZALRSC-NEXT: .LBB62_5: # %then -; RV64I-ZALRSC-NEXT: # in Loop: Header=BB62_3 Depth=1 +; RV64I-ZALRSC-NEXT: .LBB62_4: # %then +; RV64I-ZALRSC-NEXT: # in Loop: Header=BB62_2 Depth=1 ; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a0) -; RV64I-ZALRSC-NEXT: bnez a3, .LBB62_3 -; RV64I-ZALRSC-NEXT: # %bb.6: # %then +; RV64I-ZALRSC-NEXT: bnez a3, .LBB62_2 +; RV64I-ZALRSC-NEXT: # %bb.5: # %then ; RV64I-ZALRSC-NEXT: sext.w a0, a1 ; RV64I-ZALRSC-NEXT: ret -; RV64I-ZALRSC-NEXT: .LBB62_2: # %else +; RV64I-ZALRSC-NEXT: .LBB62_6: # %else ; RV64I-ZALRSC-NEXT: lw a1, 0(a0) ; RV64I-ZALRSC-NEXT: seqz a2, a1 ; RV64I-ZALRSC-NEXT: add a2, a1, a2 @@ -7975,31 +7975,31 @@ define signext i32 @atomicrmw_umin_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV32I-ZALRSC: # %bb.0: ; RV32I-ZALRSC-NEXT: andi a2, a1, 1 ; RV32I-ZALRSC-NEXT: mv a1, a0 -; RV32I-ZALRSC-NEXT: beqz a2, .LBB63_2 +; RV32I-ZALRSC-NEXT: beqz a2, .LBB63_6 ; RV32I-ZALRSC-NEXT: # %bb.1: # %then ; RV32I-ZALRSC-NEXT: li a2, 1 -; RV32I-ZALRSC-NEXT: .LBB63_5: # %then +; RV32I-ZALRSC-NEXT: .LBB63_2: # %then ; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-ZALRSC-NEXT: lr.w a0, (a1) ; RV32I-ZALRSC-NEXT: mv a3, a0 -; RV32I-ZALRSC-NEXT: bgeu a2, a3, .LBB63_7 -; RV32I-ZALRSC-NEXT: # %bb.6: # %then -; RV32I-ZALRSC-NEXT: # in Loop: Header=BB63_5 Depth=1 +; RV32I-ZALRSC-NEXT: bgeu a2, a3, .LBB63_4 +; RV32I-ZALRSC-NEXT: # %bb.3: # %then +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB63_2 Depth=1 ; RV32I-ZALRSC-NEXT: mv a3, a2 -; RV32I-ZALRSC-NEXT: .LBB63_7: # %then -; RV32I-ZALRSC-NEXT: # in Loop: Header=BB63_5 Depth=1 +; RV32I-ZALRSC-NEXT: .LBB63_4: # %then +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB63_2 Depth=1 ; RV32I-ZALRSC-NEXT: sc.w a3, a3, (a1) -; RV32I-ZALRSC-NEXT: bnez a3, .LBB63_5 -; RV32I-ZALRSC-NEXT: # %bb.8: # %then +; RV32I-ZALRSC-NEXT: bnez a3, .LBB63_2 +; RV32I-ZALRSC-NEXT: # %bb.5: # %then ; RV32I-ZALRSC-NEXT: ret -; RV32I-ZALRSC-NEXT: .LBB63_2: # %else +; RV32I-ZALRSC-NEXT: .LBB63_6: # %else ; RV32I-ZALRSC-NEXT: lw a0, 0(a1) ; RV32I-ZALRSC-NEXT: li a3, 1 ; RV32I-ZALRSC-NEXT: mv a2, a0 -; RV32I-ZALRSC-NEXT: bltu a0, a3, .LBB63_4 -; RV32I-ZALRSC-NEXT: # %bb.3: # %else +; RV32I-ZALRSC-NEXT: bltu a0, a3, .LBB63_8 +; RV32I-ZALRSC-NEXT: # %bb.7: # %else ; RV32I-ZALRSC-NEXT: li a2, 1 -; RV32I-ZALRSC-NEXT: .LBB63_4: # %else +; RV32I-ZALRSC-NEXT: .LBB63_8: # %else ; RV32I-ZALRSC-NEXT: sw a2, 0(a1) ; RV32I-ZALRSC-NEXT: ret ; @@ -8075,31 +8075,31 @@ define signext i32 @atomicrmw_umin_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV64I-ZALRSC: # %bb.0: ; RV64I-ZALRSC-NEXT: andi a2, a1, 1 ; RV64I-ZALRSC-NEXT: mv a1, a0 -; RV64I-ZALRSC-NEXT: beqz a2, .LBB63_2 +; RV64I-ZALRSC-NEXT: beqz a2, .LBB63_6 ; RV64I-ZALRSC-NEXT: # %bb.1: # %then ; RV64I-ZALRSC-NEXT: li a2, 1 -; RV64I-ZALRSC-NEXT: .LBB63_5: # %then +; RV64I-ZALRSC-NEXT: .LBB63_2: # %then ; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-ZALRSC-NEXT: lr.w a0, (a1) ; RV64I-ZALRSC-NEXT: mv a3, a0 -; RV64I-ZALRSC-NEXT: bgeu a2, a3, .LBB63_7 -; RV64I-ZALRSC-NEXT: # %bb.6: # %then -; RV64I-ZALRSC-NEXT: # in Loop: Header=BB63_5 Depth=1 +; RV64I-ZALRSC-NEXT: bgeu a2, a3, .LBB63_4 +; RV64I-ZALRSC-NEXT: # %bb.3: # %then +; RV64I-ZALRSC-NEXT: # in Loop: Header=BB63_2 Depth=1 ; RV64I-ZALRSC-NEXT: mv a3, a2 -; RV64I-ZALRSC-NEXT: .LBB63_7: # %then -; RV64I-ZALRSC-NEXT: # in Loop: Header=BB63_5 Depth=1 +; RV64I-ZALRSC-NEXT: .LBB63_4: # %then +; RV64I-ZALRSC-NEXT: # in Loop: Header=BB63_2 Depth=1 ; RV64I-ZALRSC-NEXT: sc.w a3, a3, (a1) -; RV64I-ZALRSC-NEXT: bnez a3, .LBB63_5 -; RV64I-ZALRSC-NEXT: # %bb.8: # %then +; RV64I-ZALRSC-NEXT: bnez a3, .LBB63_2 +; RV64I-ZALRSC-NEXT: # %bb.5: # %then ; RV64I-ZALRSC-NEXT: ret -; RV64I-ZALRSC-NEXT: .LBB63_2: # %else +; RV64I-ZALRSC-NEXT: .LBB63_6: # %else ; RV64I-ZALRSC-NEXT: lw a0, 0(a1) ; RV64I-ZALRSC-NEXT: li a3, 1 ; RV64I-ZALRSC-NEXT: mv a2, a0 -; RV64I-ZALRSC-NEXT: bltu a0, a3, .LBB63_4 -; RV64I-ZALRSC-NEXT: # %bb.3: # %else +; RV64I-ZALRSC-NEXT: bltu a0, a3, .LBB63_8 +; RV64I-ZALRSC-NEXT: # %bb.7: # %else ; RV64I-ZALRSC-NEXT: li a2, 1 -; RV64I-ZALRSC-NEXT: .LBB63_4: # %else +; RV64I-ZALRSC-NEXT: .LBB63_8: # %else ; RV64I-ZALRSC-NEXT: sw a2, 0(a1) ; RV64I-ZALRSC-NEXT: ret br i1 %c, label %then, label %else @@ -8142,19 +8142,19 @@ define signext i32 @cmpxchg_i32_monotonic_crossbb(ptr %ptr, i32 signext %cmp, i3 ; RV32IA-NOZACAS-LABEL: cmpxchg_i32_monotonic_crossbb: ; RV32IA-NOZACAS: # %bb.0: ; RV32IA-NOZACAS-NEXT: mv a4, a0 -; RV32IA-NOZACAS-NEXT: beqz a3, .LBB64_2 +; RV32IA-NOZACAS-NEXT: beqz a3, .LBB64_5 ; RV32IA-NOZACAS-NEXT: # %bb.1: # %then -; RV32IA-NOZACAS-NEXT: .LBB64_3: # %then +; RV32IA-NOZACAS-NEXT: .LBB64_2: # %then ; RV32IA-NOZACAS-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32IA-NOZACAS-NEXT: lr.w.aqrl a0, (a4) -; RV32IA-NOZACAS-NEXT: bne a0, a1, .LBB64_5 -; RV32IA-NOZACAS-NEXT: # %bb.4: # %then -; RV32IA-NOZACAS-NEXT: # in Loop: Header=BB64_3 Depth=1 +; RV32IA-NOZACAS-NEXT: bne a0, a1, .LBB64_4 +; RV32IA-NOZACAS-NEXT: # %bb.3: # %then +; RV32IA-NOZACAS-NEXT: # in Loop: Header=BB64_2 Depth=1 ; RV32IA-NOZACAS-NEXT: sc.w.rl a3, a2, (a4) -; RV32IA-NOZACAS-NEXT: bnez a3, .LBB64_3 -; RV32IA-NOZACAS-NEXT: .LBB64_5: # %then +; RV32IA-NOZACAS-NEXT: bnez a3, .LBB64_2 +; RV32IA-NOZACAS-NEXT: .LBB64_4: # %then ; RV32IA-NOZACAS-NEXT: ret -; RV32IA-NOZACAS-NEXT: .LBB64_2: # %else +; RV32IA-NOZACAS-NEXT: .LBB64_5: # %else ; RV32IA-NOZACAS-NEXT: lw a0, 0(a4) ; RV32IA-NOZACAS-NEXT: ret ; @@ -8173,19 +8173,19 @@ define signext i32 @cmpxchg_i32_monotonic_crossbb(ptr %ptr, i32 signext %cmp, i3 ; RV32I-ZALRSC-LABEL: cmpxchg_i32_monotonic_crossbb: ; RV32I-ZALRSC: # %bb.0: ; RV32I-ZALRSC-NEXT: mv a4, a0 -; RV32I-ZALRSC-NEXT: beqz a3, .LBB64_2 +; RV32I-ZALRSC-NEXT: beqz a3, .LBB64_5 ; RV32I-ZALRSC-NEXT: # %bb.1: # %then -; RV32I-ZALRSC-NEXT: .LBB64_3: # %then +; RV32I-ZALRSC-NEXT: .LBB64_2: # %then ; RV32I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-ZALRSC-NEXT: lr.w.aqrl a0, (a4) -; RV32I-ZALRSC-NEXT: bne a0, a1, .LBB64_5 -; RV32I-ZALRSC-NEXT: # %bb.4: # %then -; RV32I-ZALRSC-NEXT: # in Loop: Header=BB64_3 Depth=1 +; RV32I-ZALRSC-NEXT: bne a0, a1, .LBB64_4 +; RV32I-ZALRSC-NEXT: # %bb.3: # %then +; RV32I-ZALRSC-NEXT: # in Loop: Header=BB64_2 Depth=1 ; RV32I-ZALRSC-NEXT: sc.w.rl a3, a2, (a4) -; RV32I-ZALRSC-NEXT: bnez a3, .LBB64_3 -; RV32I-ZALRSC-NEXT: .LBB64_5: # %then +; RV32I-ZALRSC-NEXT: bnez a3, .LBB64_2 +; RV32I-ZALRSC-NEXT: .LBB64_4: # %then ; RV32I-ZALRSC-NEXT: ret -; RV32I-ZALRSC-NEXT: .LBB64_2: # %else +; RV32I-ZALRSC-NEXT: .LBB64_5: # %else ; RV32I-ZALRSC-NEXT: lw a0, 0(a4) ; RV32I-ZALRSC-NEXT: ret ; @@ -8210,20 +8210,20 @@ define signext i32 @cmpxchg_i32_monotonic_crossbb(ptr %ptr, i32 signext %cmp, i3 ; ; RV64IA-NOZACAS-LABEL: cmpxchg_i32_monotonic_crossbb: ; RV64IA-NOZACAS: # %bb.0: -; RV64IA-NOZACAS-NEXT: beqz a3, .LBB64_2 +; RV64IA-NOZACAS-NEXT: beqz a3, .LBB64_5 ; RV64IA-NOZACAS-NEXT: # %bb.1: # %then -; RV64IA-NOZACAS-NEXT: .LBB64_3: # %then +; RV64IA-NOZACAS-NEXT: .LBB64_2: # %then ; RV64IA-NOZACAS-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64IA-NOZACAS-NEXT: lr.w.aqrl a3, (a0) -; RV64IA-NOZACAS-NEXT: bne a3, a1, .LBB64_5 -; RV64IA-NOZACAS-NEXT: # %bb.4: # %then -; RV64IA-NOZACAS-NEXT: # in Loop: Header=BB64_3 Depth=1 +; RV64IA-NOZACAS-NEXT: bne a3, a1, .LBB64_4 +; RV64IA-NOZACAS-NEXT: # %bb.3: # %then +; RV64IA-NOZACAS-NEXT: # in Loop: Header=BB64_2 Depth=1 ; RV64IA-NOZACAS-NEXT: sc.w.rl a4, a2, (a0) -; RV64IA-NOZACAS-NEXT: bnez a4, .LBB64_3 -; RV64IA-NOZACAS-NEXT: .LBB64_5: # %then +; RV64IA-NOZACAS-NEXT: bnez a4, .LBB64_2 +; RV64IA-NOZACAS-NEXT: .LBB64_4: # %then ; RV64IA-NOZACAS-NEXT: sext.w a0, a3 ; RV64IA-NOZACAS-NEXT: ret -; RV64IA-NOZACAS-NEXT: .LBB64_2: # %else +; RV64IA-NOZACAS-NEXT: .LBB64_5: # %else ; RV64IA-NOZACAS-NEXT: lw a3, 0(a0) ; RV64IA-NOZACAS-NEXT: sext.w a0, a3 ; RV64IA-NOZACAS-NEXT: ret @@ -8242,20 +8242,20 @@ define signext i32 @cmpxchg_i32_monotonic_crossbb(ptr %ptr, i32 signext %cmp, i3 ; ; RV64I-ZALRSC-LABEL: cmpxchg_i32_monotonic_crossbb: ; RV64I-ZALRSC: # %bb.0: -; RV64I-ZALRSC-NEXT: beqz a3, .LBB64_2 +; RV64I-ZALRSC-NEXT: beqz a3, .LBB64_5 ; RV64I-ZALRSC-NEXT: # %bb.1: # %then -; RV64I-ZALRSC-NEXT: .LBB64_3: # %then +; RV64I-ZALRSC-NEXT: .LBB64_2: # %then ; RV64I-ZALRSC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-ZALRSC-NEXT: lr.w.aqrl a3, (a0) -; RV64I-ZALRSC-NEXT: bne a3, a1, .LBB64_5 -; RV64I-ZALRSC-NEXT: # %bb.4: # %then -; RV64I-ZALRSC-NEXT: # in Loop: Header=BB64_3 Depth=1 +; RV64I-ZALRSC-NEXT: bne a3, a1, .LBB64_4 +; RV64I-ZALRSC-NEXT: # %bb.3: # %then +; RV64I-ZALRSC-NEXT: # in Loop: Header=BB64_2 Depth=1 ; RV64I-ZALRSC-NEXT: sc.w.rl a4, a2, (a0) -; RV64I-ZALRSC-NEXT: bnez a4, .LBB64_3 -; RV64I-ZALRSC-NEXT: .LBB64_5: # %then +; RV64I-ZALRSC-NEXT: bnez a4, .LBB64_2 +; RV64I-ZALRSC-NEXT: .LBB64_4: # %then ; RV64I-ZALRSC-NEXT: sext.w a0, a3 ; RV64I-ZALRSC-NEXT: ret -; RV64I-ZALRSC-NEXT: .LBB64_2: # %else +; RV64I-ZALRSC-NEXT: .LBB64_5: # %else ; RV64I-ZALRSC-NEXT: lw a3, 0(a0) ; RV64I-ZALRSC-NEXT: sext.w a0, a3 ; RV64I-ZALRSC-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/atomicrmw-cond-sub-clamp.ll b/llvm/test/CodeGen/RISCV/atomicrmw-cond-sub-clamp.ll index ea9786d0b10b3..c3f72d9199235 100644 --- a/llvm/test/CodeGen/RISCV/atomicrmw-cond-sub-clamp.ll +++ b/llvm/test/CodeGen/RISCV/atomicrmw-cond-sub-clamp.ll @@ -71,7 +71,7 @@ define i8 @atomicrmw_usub_cond_i8(ptr %ptr, i8 %val) { ; RV32IA-NEXT: zext.b a4, a1 ; RV32IA-NEXT: .LBB0_1: # %atomicrmw.start ; RV32IA-NEXT: # =>This Loop Header: Depth=1 -; RV32IA-NEXT: # Child Loop BB0_3 Depth 2 +; RV32IA-NEXT: # Child Loop BB0_2 Depth 2 ; RV32IA-NEXT: mv a6, a5 ; RV32IA-NEXT: srl a5, a5, a0 ; RV32IA-NEXT: zext.b a7, a5 @@ -83,17 +83,17 @@ define i8 @atomicrmw_usub_cond_i8(ptr %ptr, i8 %val) { ; RV32IA-NEXT: sll a5, a5, a0 ; RV32IA-NEXT: and a7, a6, a3 ; RV32IA-NEXT: or a7, a7, a5 -; RV32IA-NEXT: .LBB0_3: # %atomicrmw.start +; RV32IA-NEXT: .LBB0_2: # %atomicrmw.start ; RV32IA-NEXT: # Parent Loop BB0_1 Depth=1 ; RV32IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV32IA-NEXT: lr.w.aqrl a5, (a2) ; RV32IA-NEXT: bne a5, a6, .LBB0_1 -; RV32IA-NEXT: # %bb.4: # %atomicrmw.start -; RV32IA-NEXT: # in Loop: Header=BB0_3 Depth=2 +; RV32IA-NEXT: # %bb.3: # %atomicrmw.start +; RV32IA-NEXT: # in Loop: Header=BB0_2 Depth=2 ; RV32IA-NEXT: sc.w.rl t0, a7, (a2) -; RV32IA-NEXT: bnez t0, .LBB0_3 -; RV32IA-NEXT: # %bb.5: # %atomicrmw.start -; RV32IA-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-NEXT: bnez t0, .LBB0_2 +; RV32IA-NEXT: # %bb.4: # %atomicrmw.start +; RV32IA-NEXT: # %bb.5: # %atomicrmw.end ; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: ret ; @@ -154,7 +154,7 @@ define i8 @atomicrmw_usub_cond_i8(ptr %ptr, i8 %val) { ; RV64IA-NEXT: zext.b a5, a1 ; RV64IA-NEXT: .LBB0_1: # %atomicrmw.start ; RV64IA-NEXT: # =>This Loop Header: Depth=1 -; RV64IA-NEXT: # Child Loop BB0_3 Depth 2 +; RV64IA-NEXT: # Child Loop BB0_2 Depth 2 ; RV64IA-NEXT: srlw a6, a3, a0 ; RV64IA-NEXT: sext.w a7, a3 ; RV64IA-NEXT: zext.b t0, a6 @@ -166,17 +166,17 @@ define i8 @atomicrmw_usub_cond_i8(ptr %ptr, i8 %val) { ; RV64IA-NEXT: sllw a6, a6, a0 ; RV64IA-NEXT: and a3, a3, a4 ; RV64IA-NEXT: or a6, a3, a6 -; RV64IA-NEXT: .LBB0_3: # %atomicrmw.start +; RV64IA-NEXT: .LBB0_2: # %atomicrmw.start ; RV64IA-NEXT: # Parent Loop BB0_1 Depth=1 ; RV64IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV64IA-NEXT: lr.w.aqrl a3, (a2) ; RV64IA-NEXT: bne a3, a7, .LBB0_1 -; RV64IA-NEXT: # %bb.4: # %atomicrmw.start -; RV64IA-NEXT: # in Loop: Header=BB0_3 Depth=2 +; RV64IA-NEXT: # %bb.3: # %atomicrmw.start +; RV64IA-NEXT: # in Loop: Header=BB0_2 Depth=2 ; RV64IA-NEXT: sc.w.rl t0, a6, (a2) -; RV64IA-NEXT: bnez t0, .LBB0_3 -; RV64IA-NEXT: # %bb.5: # %atomicrmw.start -; RV64IA-NEXT: # %bb.2: # %atomicrmw.end +; RV64IA-NEXT: bnez t0, .LBB0_2 +; RV64IA-NEXT: # %bb.4: # %atomicrmw.start +; RV64IA-NEXT: # %bb.5: # %atomicrmw.end ; RV64IA-NEXT: srlw a0, a3, a0 ; RV64IA-NEXT: ret %result = atomicrmw usub_cond ptr %ptr, i8 %val seq_cst @@ -248,7 +248,7 @@ define i16 @atomicrmw_usub_cond_i16(ptr %ptr, i16 %val) { ; RV32IA-NEXT: and a5, a1, a3 ; RV32IA-NEXT: .LBB1_1: # %atomicrmw.start ; RV32IA-NEXT: # =>This Loop Header: Depth=1 -; RV32IA-NEXT: # Child Loop BB1_3 Depth 2 +; RV32IA-NEXT: # Child Loop BB1_2 Depth 2 ; RV32IA-NEXT: mv a7, a6 ; RV32IA-NEXT: srl a6, a6, a0 ; RV32IA-NEXT: and t0, a6, a3 @@ -260,17 +260,17 @@ define i16 @atomicrmw_usub_cond_i16(ptr %ptr, i16 %val) { ; RV32IA-NEXT: sll a6, a6, a0 ; RV32IA-NEXT: and t0, a7, a4 ; RV32IA-NEXT: or t0, t0, a6 -; RV32IA-NEXT: .LBB1_3: # %atomicrmw.start +; RV32IA-NEXT: .LBB1_2: # %atomicrmw.start ; RV32IA-NEXT: # Parent Loop BB1_1 Depth=1 ; RV32IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV32IA-NEXT: lr.w.aqrl a6, (a2) ; RV32IA-NEXT: bne a6, a7, .LBB1_1 -; RV32IA-NEXT: # %bb.4: # %atomicrmw.start -; RV32IA-NEXT: # in Loop: Header=BB1_3 Depth=2 +; RV32IA-NEXT: # %bb.3: # %atomicrmw.start +; RV32IA-NEXT: # in Loop: Header=BB1_2 Depth=2 ; RV32IA-NEXT: sc.w.rl t1, t0, (a2) -; RV32IA-NEXT: bnez t1, .LBB1_3 -; RV32IA-NEXT: # %bb.5: # %atomicrmw.start -; RV32IA-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-NEXT: bnez t1, .LBB1_2 +; RV32IA-NEXT: # %bb.4: # %atomicrmw.start +; RV32IA-NEXT: # %bb.5: # %atomicrmw.end ; RV32IA-NEXT: srl a0, a6, a0 ; RV32IA-NEXT: ret ; @@ -338,7 +338,7 @@ define i16 @atomicrmw_usub_cond_i16(ptr %ptr, i16 %val) { ; RV64IA-NEXT: and a6, a1, a3 ; RV64IA-NEXT: .LBB1_1: # %atomicrmw.start ; RV64IA-NEXT: # =>This Loop Header: Depth=1 -; RV64IA-NEXT: # Child Loop BB1_3 Depth 2 +; RV64IA-NEXT: # Child Loop BB1_2 Depth 2 ; RV64IA-NEXT: srlw a7, a4, a0 ; RV64IA-NEXT: sext.w t0, a4 ; RV64IA-NEXT: and t1, a7, a3 @@ -350,17 +350,17 @@ define i16 @atomicrmw_usub_cond_i16(ptr %ptr, i16 %val) { ; RV64IA-NEXT: sllw a7, a7, a0 ; RV64IA-NEXT: and a4, a4, a5 ; RV64IA-NEXT: or a7, a4, a7 -; RV64IA-NEXT: .LBB1_3: # %atomicrmw.start +; RV64IA-NEXT: .LBB1_2: # %atomicrmw.start ; RV64IA-NEXT: # Parent Loop BB1_1 Depth=1 ; RV64IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV64IA-NEXT: lr.w.aqrl a4, (a2) ; RV64IA-NEXT: bne a4, t0, .LBB1_1 -; RV64IA-NEXT: # %bb.4: # %atomicrmw.start -; RV64IA-NEXT: # in Loop: Header=BB1_3 Depth=2 +; RV64IA-NEXT: # %bb.3: # %atomicrmw.start +; RV64IA-NEXT: # in Loop: Header=BB1_2 Depth=2 ; RV64IA-NEXT: sc.w.rl t1, a7, (a2) -; RV64IA-NEXT: bnez t1, .LBB1_3 -; RV64IA-NEXT: # %bb.5: # %atomicrmw.start -; RV64IA-NEXT: # %bb.2: # %atomicrmw.end +; RV64IA-NEXT: bnez t1, .LBB1_2 +; RV64IA-NEXT: # %bb.4: # %atomicrmw.start +; RV64IA-NEXT: # %bb.5: # %atomicrmw.end ; RV64IA-NEXT: srlw a0, a4, a0 ; RV64IA-NEXT: ret %result = atomicrmw usub_cond ptr %ptr, i16 %val seq_cst @@ -412,23 +412,23 @@ define i32 @atomicrmw_usub_cond_i32(ptr %ptr, i32 %val) { ; RV32IA-NEXT: lw a2, 0(a0) ; RV32IA-NEXT: .LBB2_1: # %atomicrmw.start ; RV32IA-NEXT: # =>This Loop Header: Depth=1 -; RV32IA-NEXT: # Child Loop BB2_3 Depth 2 +; RV32IA-NEXT: # Child Loop BB2_2 Depth 2 ; RV32IA-NEXT: mv a3, a2 ; RV32IA-NEXT: sltu a2, a2, a1 ; RV32IA-NEXT: addi a2, a2, -1 ; RV32IA-NEXT: and a2, a2, a1 ; RV32IA-NEXT: sub a4, a3, a2 -; RV32IA-NEXT: .LBB2_3: # %atomicrmw.start +; RV32IA-NEXT: .LBB2_2: # %atomicrmw.start ; RV32IA-NEXT: # Parent Loop BB2_1 Depth=1 ; RV32IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV32IA-NEXT: lr.w.aqrl a2, (a0) ; RV32IA-NEXT: bne a2, a3, .LBB2_1 -; RV32IA-NEXT: # %bb.4: # %atomicrmw.start -; RV32IA-NEXT: # in Loop: Header=BB2_3 Depth=2 +; RV32IA-NEXT: # %bb.3: # %atomicrmw.start +; RV32IA-NEXT: # in Loop: Header=BB2_2 Depth=2 ; RV32IA-NEXT: sc.w.rl a5, a4, (a0) -; RV32IA-NEXT: bnez a5, .LBB2_3 -; RV32IA-NEXT: # %bb.5: # %atomicrmw.start -; RV32IA-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-NEXT: bnez a5, .LBB2_2 +; RV32IA-NEXT: # %bb.4: # %atomicrmw.start +; RV32IA-NEXT: # %bb.5: # %atomicrmw.end ; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: ret ; @@ -482,23 +482,23 @@ define i32 @atomicrmw_usub_cond_i32(ptr %ptr, i32 %val) { ; RV64IA-NEXT: sext.w a3, a1 ; RV64IA-NEXT: .LBB2_1: # %atomicrmw.start ; RV64IA-NEXT: # =>This Loop Header: Depth=1 -; RV64IA-NEXT: # Child Loop BB2_3 Depth 2 +; RV64IA-NEXT: # Child Loop BB2_2 Depth 2 ; RV64IA-NEXT: sext.w a4, a2 ; RV64IA-NEXT: sltu a5, a4, a3 ; RV64IA-NEXT: addi a5, a5, -1 ; RV64IA-NEXT: and a5, a5, a1 ; RV64IA-NEXT: subw a5, a2, a5 -; RV64IA-NEXT: .LBB2_3: # %atomicrmw.start +; RV64IA-NEXT: .LBB2_2: # %atomicrmw.start ; RV64IA-NEXT: # Parent Loop BB2_1 Depth=1 ; RV64IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV64IA-NEXT: lr.w.aqrl a2, (a0) ; RV64IA-NEXT: bne a2, a4, .LBB2_1 -; RV64IA-NEXT: # %bb.4: # %atomicrmw.start -; RV64IA-NEXT: # in Loop: Header=BB2_3 Depth=2 +; RV64IA-NEXT: # %bb.3: # %atomicrmw.start +; RV64IA-NEXT: # in Loop: Header=BB2_2 Depth=2 ; RV64IA-NEXT: sc.w.rl a6, a5, (a0) -; RV64IA-NEXT: bnez a6, .LBB2_3 -; RV64IA-NEXT: # %bb.5: # %atomicrmw.start -; RV64IA-NEXT: # %bb.2: # %atomicrmw.end +; RV64IA-NEXT: bnez a6, .LBB2_2 +; RV64IA-NEXT: # %bb.4: # %atomicrmw.start +; RV64IA-NEXT: # %bb.5: # %atomicrmw.end ; RV64IA-NEXT: mv a0, a2 ; RV64IA-NEXT: ret %result = atomicrmw usub_cond ptr %ptr, i32 %val seq_cst @@ -674,23 +674,23 @@ define i64 @atomicrmw_usub_cond_i64(ptr %ptr, i64 %val) { ; RV64IA-NEXT: ld a2, 0(a0) ; RV64IA-NEXT: .LBB3_1: # %atomicrmw.start ; RV64IA-NEXT: # =>This Loop Header: Depth=1 -; RV64IA-NEXT: # Child Loop BB3_3 Depth 2 +; RV64IA-NEXT: # Child Loop BB3_2 Depth 2 ; RV64IA-NEXT: mv a3, a2 ; RV64IA-NEXT: sltu a2, a2, a1 ; RV64IA-NEXT: addi a2, a2, -1 ; RV64IA-NEXT: and a2, a2, a1 ; RV64IA-NEXT: sub a4, a3, a2 -; RV64IA-NEXT: .LBB3_3: # %atomicrmw.start +; RV64IA-NEXT: .LBB3_2: # %atomicrmw.start ; RV64IA-NEXT: # Parent Loop BB3_1 Depth=1 ; RV64IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV64IA-NEXT: lr.d.aqrl a2, (a0) ; RV64IA-NEXT: bne a2, a3, .LBB3_1 -; RV64IA-NEXT: # %bb.4: # %atomicrmw.start -; RV64IA-NEXT: # in Loop: Header=BB3_3 Depth=2 +; RV64IA-NEXT: # %bb.3: # %atomicrmw.start +; RV64IA-NEXT: # in Loop: Header=BB3_2 Depth=2 ; RV64IA-NEXT: sc.d.rl a5, a4, (a0) -; RV64IA-NEXT: bnez a5, .LBB3_3 -; RV64IA-NEXT: # %bb.5: # %atomicrmw.start -; RV64IA-NEXT: # %bb.2: # %atomicrmw.end +; RV64IA-NEXT: bnez a5, .LBB3_2 +; RV64IA-NEXT: # %bb.4: # %atomicrmw.start +; RV64IA-NEXT: # %bb.5: # %atomicrmw.end ; RV64IA-NEXT: mv a0, a2 ; RV64IA-NEXT: ret %result = atomicrmw usub_cond ptr %ptr, i64 %val seq_cst @@ -750,7 +750,7 @@ define i8 @atomicrmw_usub_sat_i8(ptr %ptr, i8 %val) { ; RV32IA-NEXT: zext.b a1, a1 ; RV32IA-NEXT: .LBB4_1: # %atomicrmw.start ; RV32IA-NEXT: # =>This Loop Header: Depth=1 -; RV32IA-NEXT: # Child Loop BB4_3 Depth 2 +; RV32IA-NEXT: # Child Loop BB4_2 Depth 2 ; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: srl a4, a4, a0 ; RV32IA-NEXT: zext.b a4, a4 @@ -761,17 +761,17 @@ define i8 @atomicrmw_usub_sat_i8(ptr %ptr, i8 %val) { ; RV32IA-NEXT: sll a4, a4, a0 ; RV32IA-NEXT: and a6, a5, a3 ; RV32IA-NEXT: or a6, a6, a4 -; RV32IA-NEXT: .LBB4_3: # %atomicrmw.start +; RV32IA-NEXT: .LBB4_2: # %atomicrmw.start ; RV32IA-NEXT: # Parent Loop BB4_1 Depth=1 ; RV32IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV32IA-NEXT: lr.w.aqrl a4, (a2) ; RV32IA-NEXT: bne a4, a5, .LBB4_1 -; RV32IA-NEXT: # %bb.4: # %atomicrmw.start -; RV32IA-NEXT: # in Loop: Header=BB4_3 Depth=2 +; RV32IA-NEXT: # %bb.3: # %atomicrmw.start +; RV32IA-NEXT: # in Loop: Header=BB4_2 Depth=2 ; RV32IA-NEXT: sc.w.rl a7, a6, (a2) -; RV32IA-NEXT: bnez a7, .LBB4_3 -; RV32IA-NEXT: # %bb.5: # %atomicrmw.start -; RV32IA-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-NEXT: bnez a7, .LBB4_2 +; RV32IA-NEXT: # %bb.4: # %atomicrmw.start +; RV32IA-NEXT: # %bb.5: # %atomicrmw.end ; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: ret ; @@ -827,7 +827,7 @@ define i8 @atomicrmw_usub_sat_i8(ptr %ptr, i8 %val) { ; RV64IA-NEXT: zext.b a1, a1 ; RV64IA-NEXT: .LBB4_1: # %atomicrmw.start ; RV64IA-NEXT: # =>This Loop Header: Depth=1 -; RV64IA-NEXT: # Child Loop BB4_3 Depth 2 +; RV64IA-NEXT: # Child Loop BB4_2 Depth 2 ; RV64IA-NEXT: srlw a5, a3, a0 ; RV64IA-NEXT: sext.w a6, a3 ; RV64IA-NEXT: zext.b a5, a5 @@ -838,17 +838,17 @@ define i8 @atomicrmw_usub_sat_i8(ptr %ptr, i8 %val) { ; RV64IA-NEXT: sllw a5, a5, a0 ; RV64IA-NEXT: and a3, a3, a4 ; RV64IA-NEXT: or a5, a3, a5 -; RV64IA-NEXT: .LBB4_3: # %atomicrmw.start +; RV64IA-NEXT: .LBB4_2: # %atomicrmw.start ; RV64IA-NEXT: # Parent Loop BB4_1 Depth=1 ; RV64IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV64IA-NEXT: lr.w.aqrl a3, (a2) ; RV64IA-NEXT: bne a3, a6, .LBB4_1 -; RV64IA-NEXT: # %bb.4: # %atomicrmw.start -; RV64IA-NEXT: # in Loop: Header=BB4_3 Depth=2 +; RV64IA-NEXT: # %bb.3: # %atomicrmw.start +; RV64IA-NEXT: # in Loop: Header=BB4_2 Depth=2 ; RV64IA-NEXT: sc.w.rl a7, a5, (a2) -; RV64IA-NEXT: bnez a7, .LBB4_3 -; RV64IA-NEXT: # %bb.5: # %atomicrmw.start -; RV64IA-NEXT: # %bb.2: # %atomicrmw.end +; RV64IA-NEXT: bnez a7, .LBB4_2 +; RV64IA-NEXT: # %bb.4: # %atomicrmw.start +; RV64IA-NEXT: # %bb.5: # %atomicrmw.end ; RV64IA-NEXT: srlw a0, a3, a0 ; RV64IA-NEXT: ret %result = atomicrmw usub_sat ptr %ptr, i8 %val seq_cst @@ -915,7 +915,7 @@ define i16 @atomicrmw_usub_sat_i16(ptr %ptr, i16 %val) { ; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: .LBB5_1: # %atomicrmw.start ; RV32IA-NEXT: # =>This Loop Header: Depth=1 -; RV32IA-NEXT: # Child Loop BB5_3 Depth 2 +; RV32IA-NEXT: # Child Loop BB5_2 Depth 2 ; RV32IA-NEXT: mv a6, a5 ; RV32IA-NEXT: srl a5, a5, a0 ; RV32IA-NEXT: and a5, a5, a3 @@ -926,17 +926,17 @@ define i16 @atomicrmw_usub_sat_i16(ptr %ptr, i16 %val) { ; RV32IA-NEXT: sll a5, a5, a0 ; RV32IA-NEXT: and a7, a6, a4 ; RV32IA-NEXT: or a7, a7, a5 -; RV32IA-NEXT: .LBB5_3: # %atomicrmw.start +; RV32IA-NEXT: .LBB5_2: # %atomicrmw.start ; RV32IA-NEXT: # Parent Loop BB5_1 Depth=1 ; RV32IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV32IA-NEXT: lr.w.aqrl a5, (a2) ; RV32IA-NEXT: bne a5, a6, .LBB5_1 -; RV32IA-NEXT: # %bb.4: # %atomicrmw.start -; RV32IA-NEXT: # in Loop: Header=BB5_3 Depth=2 +; RV32IA-NEXT: # %bb.3: # %atomicrmw.start +; RV32IA-NEXT: # in Loop: Header=BB5_2 Depth=2 ; RV32IA-NEXT: sc.w.rl t0, a7, (a2) -; RV32IA-NEXT: bnez t0, .LBB5_3 -; RV32IA-NEXT: # %bb.5: # %atomicrmw.start -; RV32IA-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-NEXT: bnez t0, .LBB5_2 +; RV32IA-NEXT: # %bb.4: # %atomicrmw.start +; RV32IA-NEXT: # %bb.5: # %atomicrmw.end ; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: ret ; @@ -999,7 +999,7 @@ define i16 @atomicrmw_usub_sat_i16(ptr %ptr, i16 %val) { ; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: .LBB5_1: # %atomicrmw.start ; RV64IA-NEXT: # =>This Loop Header: Depth=1 -; RV64IA-NEXT: # Child Loop BB5_3 Depth 2 +; RV64IA-NEXT: # Child Loop BB5_2 Depth 2 ; RV64IA-NEXT: srlw a6, a4, a0 ; RV64IA-NEXT: sext.w a7, a4 ; RV64IA-NEXT: and a6, a6, a3 @@ -1010,17 +1010,17 @@ define i16 @atomicrmw_usub_sat_i16(ptr %ptr, i16 %val) { ; RV64IA-NEXT: sllw a6, a6, a0 ; RV64IA-NEXT: and a4, a4, a5 ; RV64IA-NEXT: or a6, a4, a6 -; RV64IA-NEXT: .LBB5_3: # %atomicrmw.start +; RV64IA-NEXT: .LBB5_2: # %atomicrmw.start ; RV64IA-NEXT: # Parent Loop BB5_1 Depth=1 ; RV64IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV64IA-NEXT: lr.w.aqrl a4, (a2) ; RV64IA-NEXT: bne a4, a7, .LBB5_1 -; RV64IA-NEXT: # %bb.4: # %atomicrmw.start -; RV64IA-NEXT: # in Loop: Header=BB5_3 Depth=2 +; RV64IA-NEXT: # %bb.3: # %atomicrmw.start +; RV64IA-NEXT: # in Loop: Header=BB5_2 Depth=2 ; RV64IA-NEXT: sc.w.rl t0, a6, (a2) -; RV64IA-NEXT: bnez t0, .LBB5_3 -; RV64IA-NEXT: # %bb.5: # %atomicrmw.start -; RV64IA-NEXT: # %bb.2: # %atomicrmw.end +; RV64IA-NEXT: bnez t0, .LBB5_2 +; RV64IA-NEXT: # %bb.4: # %atomicrmw.start +; RV64IA-NEXT: # %bb.5: # %atomicrmw.end ; RV64IA-NEXT: srlw a0, a4, a0 ; RV64IA-NEXT: ret %result = atomicrmw usub_sat ptr %ptr, i16 %val seq_cst @@ -1072,23 +1072,23 @@ define i32 @atomicrmw_usub_sat_i32(ptr %ptr, i32 %val) { ; RV32IA-NEXT: lw a2, 0(a0) ; RV32IA-NEXT: .LBB6_1: # %atomicrmw.start ; RV32IA-NEXT: # =>This Loop Header: Depth=1 -; RV32IA-NEXT: # Child Loop BB6_3 Depth 2 +; RV32IA-NEXT: # Child Loop BB6_2 Depth 2 ; RV32IA-NEXT: mv a3, a2 ; RV32IA-NEXT: sub a2, a2, a1 ; RV32IA-NEXT: sltu a4, a3, a2 ; RV32IA-NEXT: addi a4, a4, -1 ; RV32IA-NEXT: and a4, a4, a2 -; RV32IA-NEXT: .LBB6_3: # %atomicrmw.start +; RV32IA-NEXT: .LBB6_2: # %atomicrmw.start ; RV32IA-NEXT: # Parent Loop BB6_1 Depth=1 ; RV32IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV32IA-NEXT: lr.w.aqrl a2, (a0) ; RV32IA-NEXT: bne a2, a3, .LBB6_1 -; RV32IA-NEXT: # %bb.4: # %atomicrmw.start -; RV32IA-NEXT: # in Loop: Header=BB6_3 Depth=2 +; RV32IA-NEXT: # %bb.3: # %atomicrmw.start +; RV32IA-NEXT: # in Loop: Header=BB6_2 Depth=2 ; RV32IA-NEXT: sc.w.rl a5, a4, (a0) -; RV32IA-NEXT: bnez a5, .LBB6_3 -; RV32IA-NEXT: # %bb.5: # %atomicrmw.start -; RV32IA-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-NEXT: bnez a5, .LBB6_2 +; RV32IA-NEXT: # %bb.4: # %atomicrmw.start +; RV32IA-NEXT: # %bb.5: # %atomicrmw.end ; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: ret ; @@ -1136,23 +1136,23 @@ define i32 @atomicrmw_usub_sat_i32(ptr %ptr, i32 %val) { ; RV64IA-NEXT: lw a2, 0(a0) ; RV64IA-NEXT: .LBB6_1: # %atomicrmw.start ; RV64IA-NEXT: # =>This Loop Header: Depth=1 -; RV64IA-NEXT: # Child Loop BB6_3 Depth 2 +; RV64IA-NEXT: # Child Loop BB6_2 Depth 2 ; RV64IA-NEXT: subw a3, a2, a1 ; RV64IA-NEXT: sext.w a4, a2 ; RV64IA-NEXT: sltu a2, a4, a3 ; RV64IA-NEXT: addi a2, a2, -1 ; RV64IA-NEXT: and a3, a2, a3 -; RV64IA-NEXT: .LBB6_3: # %atomicrmw.start +; RV64IA-NEXT: .LBB6_2: # %atomicrmw.start ; RV64IA-NEXT: # Parent Loop BB6_1 Depth=1 ; RV64IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV64IA-NEXT: lr.w.aqrl a2, (a0) ; RV64IA-NEXT: bne a2, a4, .LBB6_1 -; RV64IA-NEXT: # %bb.4: # %atomicrmw.start -; RV64IA-NEXT: # in Loop: Header=BB6_3 Depth=2 +; RV64IA-NEXT: # %bb.3: # %atomicrmw.start +; RV64IA-NEXT: # in Loop: Header=BB6_2 Depth=2 ; RV64IA-NEXT: sc.w.rl a5, a3, (a0) -; RV64IA-NEXT: bnez a5, .LBB6_3 -; RV64IA-NEXT: # %bb.5: # %atomicrmw.start -; RV64IA-NEXT: # %bb.2: # %atomicrmw.end +; RV64IA-NEXT: bnez a5, .LBB6_2 +; RV64IA-NEXT: # %bb.4: # %atomicrmw.start +; RV64IA-NEXT: # %bb.5: # %atomicrmw.end ; RV64IA-NEXT: mv a0, a2 ; RV64IA-NEXT: ret %result = atomicrmw usub_sat ptr %ptr, i32 %val seq_cst @@ -1326,23 +1326,23 @@ define i64 @atomicrmw_usub_sat_i64(ptr %ptr, i64 %val) { ; RV64IA-NEXT: ld a2, 0(a0) ; RV64IA-NEXT: .LBB7_1: # %atomicrmw.start ; RV64IA-NEXT: # =>This Loop Header: Depth=1 -; RV64IA-NEXT: # Child Loop BB7_3 Depth 2 +; RV64IA-NEXT: # Child Loop BB7_2 Depth 2 ; RV64IA-NEXT: mv a3, a2 ; RV64IA-NEXT: sub a2, a2, a1 ; RV64IA-NEXT: sltu a4, a3, a2 ; RV64IA-NEXT: addi a4, a4, -1 ; RV64IA-NEXT: and a4, a4, a2 -; RV64IA-NEXT: .LBB7_3: # %atomicrmw.start +; RV64IA-NEXT: .LBB7_2: # %atomicrmw.start ; RV64IA-NEXT: # Parent Loop BB7_1 Depth=1 ; RV64IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV64IA-NEXT: lr.d.aqrl a2, (a0) ; RV64IA-NEXT: bne a2, a3, .LBB7_1 -; RV64IA-NEXT: # %bb.4: # %atomicrmw.start -; RV64IA-NEXT: # in Loop: Header=BB7_3 Depth=2 +; RV64IA-NEXT: # %bb.3: # %atomicrmw.start +; RV64IA-NEXT: # in Loop: Header=BB7_2 Depth=2 ; RV64IA-NEXT: sc.d.rl a5, a4, (a0) -; RV64IA-NEXT: bnez a5, .LBB7_3 -; RV64IA-NEXT: # %bb.5: # %atomicrmw.start -; RV64IA-NEXT: # %bb.2: # %atomicrmw.end +; RV64IA-NEXT: bnez a5, .LBB7_2 +; RV64IA-NEXT: # %bb.4: # %atomicrmw.start +; RV64IA-NEXT: # %bb.5: # %atomicrmw.end ; RV64IA-NEXT: mv a0, a2 ; RV64IA-NEXT: ret %result = atomicrmw usub_sat ptr %ptr, i64 %val seq_cst diff --git a/llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll b/llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll index 4e04f38a6301d..1c4d0343ee5db 100644 --- a/llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll +++ b/llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll @@ -66,7 +66,7 @@ define i8 @atomicrmw_uinc_wrap_i8(ptr %ptr, i8 %val) { ; RV32IA-NEXT: zext.b a1, a1 ; RV32IA-NEXT: .LBB0_1: # %atomicrmw.start ; RV32IA-NEXT: # =>This Loop Header: Depth=1 -; RV32IA-NEXT: # Child Loop BB0_3 Depth 2 +; RV32IA-NEXT: # Child Loop BB0_2 Depth 2 ; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: srl a4, a4, a0 ; RV32IA-NEXT: zext.b a6, a4 @@ -78,17 +78,17 @@ define i8 @atomicrmw_uinc_wrap_i8(ptr %ptr, i8 %val) { ; RV32IA-NEXT: sll a4, a4, a0 ; RV32IA-NEXT: and a6, a5, a3 ; RV32IA-NEXT: or a6, a6, a4 -; RV32IA-NEXT: .LBB0_3: # %atomicrmw.start +; RV32IA-NEXT: .LBB0_2: # %atomicrmw.start ; RV32IA-NEXT: # Parent Loop BB0_1 Depth=1 ; RV32IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV32IA-NEXT: lr.w.aqrl a4, (a2) ; RV32IA-NEXT: bne a4, a5, .LBB0_1 -; RV32IA-NEXT: # %bb.4: # %atomicrmw.start -; RV32IA-NEXT: # in Loop: Header=BB0_3 Depth=2 +; RV32IA-NEXT: # %bb.3: # %atomicrmw.start +; RV32IA-NEXT: # in Loop: Header=BB0_2 Depth=2 ; RV32IA-NEXT: sc.w.rl a7, a6, (a2) -; RV32IA-NEXT: bnez a7, .LBB0_3 -; RV32IA-NEXT: # %bb.5: # %atomicrmw.start -; RV32IA-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-NEXT: bnez a7, .LBB0_2 +; RV32IA-NEXT: # %bb.4: # %atomicrmw.start +; RV32IA-NEXT: # %bb.5: # %atomicrmw.end ; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: ret ; @@ -144,7 +144,7 @@ define i8 @atomicrmw_uinc_wrap_i8(ptr %ptr, i8 %val) { ; RV64IA-NEXT: zext.b a1, a1 ; RV64IA-NEXT: .LBB0_1: # %atomicrmw.start ; RV64IA-NEXT: # =>This Loop Header: Depth=1 -; RV64IA-NEXT: # Child Loop BB0_3 Depth 2 +; RV64IA-NEXT: # Child Loop BB0_2 Depth 2 ; RV64IA-NEXT: srlw a5, a3, a0 ; RV64IA-NEXT: sext.w a6, a3 ; RV64IA-NEXT: zext.b a7, a5 @@ -156,17 +156,17 @@ define i8 @atomicrmw_uinc_wrap_i8(ptr %ptr, i8 %val) { ; RV64IA-NEXT: sllw a5, a5, a0 ; RV64IA-NEXT: and a3, a3, a4 ; RV64IA-NEXT: or a5, a3, a5 -; RV64IA-NEXT: .LBB0_3: # %atomicrmw.start +; RV64IA-NEXT: .LBB0_2: # %atomicrmw.start ; RV64IA-NEXT: # Parent Loop BB0_1 Depth=1 ; RV64IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV64IA-NEXT: lr.w.aqrl a3, (a2) ; RV64IA-NEXT: bne a3, a6, .LBB0_1 -; RV64IA-NEXT: # %bb.4: # %atomicrmw.start -; RV64IA-NEXT: # in Loop: Header=BB0_3 Depth=2 +; RV64IA-NEXT: # %bb.3: # %atomicrmw.start +; RV64IA-NEXT: # in Loop: Header=BB0_2 Depth=2 ; RV64IA-NEXT: sc.w.rl a7, a5, (a2) -; RV64IA-NEXT: bnez a7, .LBB0_3 -; RV64IA-NEXT: # %bb.5: # %atomicrmw.start -; RV64IA-NEXT: # %bb.2: # %atomicrmw.end +; RV64IA-NEXT: bnez a7, .LBB0_2 +; RV64IA-NEXT: # %bb.4: # %atomicrmw.start +; RV64IA-NEXT: # %bb.5: # %atomicrmw.end ; RV64IA-NEXT: srlw a0, a3, a0 ; RV64IA-NEXT: ret %result = atomicrmw uinc_wrap ptr %ptr, i8 %val seq_cst @@ -233,7 +233,7 @@ define i16 @atomicrmw_uinc_wrap_i16(ptr %ptr, i16 %val) { ; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: .LBB1_1: # %atomicrmw.start ; RV32IA-NEXT: # =>This Loop Header: Depth=1 -; RV32IA-NEXT: # Child Loop BB1_3 Depth 2 +; RV32IA-NEXT: # Child Loop BB1_2 Depth 2 ; RV32IA-NEXT: mv a6, a5 ; RV32IA-NEXT: srl a5, a5, a0 ; RV32IA-NEXT: and a7, a5, a3 @@ -245,17 +245,17 @@ define i16 @atomicrmw_uinc_wrap_i16(ptr %ptr, i16 %val) { ; RV32IA-NEXT: sll a5, a5, a0 ; RV32IA-NEXT: and a7, a6, a4 ; RV32IA-NEXT: or a7, a7, a5 -; RV32IA-NEXT: .LBB1_3: # %atomicrmw.start +; RV32IA-NEXT: .LBB1_2: # %atomicrmw.start ; RV32IA-NEXT: # Parent Loop BB1_1 Depth=1 ; RV32IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV32IA-NEXT: lr.w.aqrl a5, (a2) ; RV32IA-NEXT: bne a5, a6, .LBB1_1 -; RV32IA-NEXT: # %bb.4: # %atomicrmw.start -; RV32IA-NEXT: # in Loop: Header=BB1_3 Depth=2 +; RV32IA-NEXT: # %bb.3: # %atomicrmw.start +; RV32IA-NEXT: # in Loop: Header=BB1_2 Depth=2 ; RV32IA-NEXT: sc.w.rl t0, a7, (a2) -; RV32IA-NEXT: bnez t0, .LBB1_3 -; RV32IA-NEXT: # %bb.5: # %atomicrmw.start -; RV32IA-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-NEXT: bnez t0, .LBB1_2 +; RV32IA-NEXT: # %bb.4: # %atomicrmw.start +; RV32IA-NEXT: # %bb.5: # %atomicrmw.end ; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: ret ; @@ -318,7 +318,7 @@ define i16 @atomicrmw_uinc_wrap_i16(ptr %ptr, i16 %val) { ; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: .LBB1_1: # %atomicrmw.start ; RV64IA-NEXT: # =>This Loop Header: Depth=1 -; RV64IA-NEXT: # Child Loop BB1_3 Depth 2 +; RV64IA-NEXT: # Child Loop BB1_2 Depth 2 ; RV64IA-NEXT: srlw a6, a4, a0 ; RV64IA-NEXT: sext.w a7, a4 ; RV64IA-NEXT: and t0, a6, a3 @@ -330,17 +330,17 @@ define i16 @atomicrmw_uinc_wrap_i16(ptr %ptr, i16 %val) { ; RV64IA-NEXT: sllw a6, a6, a0 ; RV64IA-NEXT: and a4, a4, a5 ; RV64IA-NEXT: or a6, a4, a6 -; RV64IA-NEXT: .LBB1_3: # %atomicrmw.start +; RV64IA-NEXT: .LBB1_2: # %atomicrmw.start ; RV64IA-NEXT: # Parent Loop BB1_1 Depth=1 ; RV64IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV64IA-NEXT: lr.w.aqrl a4, (a2) ; RV64IA-NEXT: bne a4, a7, .LBB1_1 -; RV64IA-NEXT: # %bb.4: # %atomicrmw.start -; RV64IA-NEXT: # in Loop: Header=BB1_3 Depth=2 +; RV64IA-NEXT: # %bb.3: # %atomicrmw.start +; RV64IA-NEXT: # in Loop: Header=BB1_2 Depth=2 ; RV64IA-NEXT: sc.w.rl t0, a6, (a2) -; RV64IA-NEXT: bnez t0, .LBB1_3 -; RV64IA-NEXT: # %bb.5: # %atomicrmw.start -; RV64IA-NEXT: # %bb.2: # %atomicrmw.end +; RV64IA-NEXT: bnez t0, .LBB1_2 +; RV64IA-NEXT: # %bb.4: # %atomicrmw.start +; RV64IA-NEXT: # %bb.5: # %atomicrmw.end ; RV64IA-NEXT: srlw a0, a4, a0 ; RV64IA-NEXT: ret %result = atomicrmw uinc_wrap ptr %ptr, i16 %val seq_cst @@ -392,23 +392,23 @@ define i32 @atomicrmw_uinc_wrap_i32(ptr %ptr, i32 %val) { ; RV32IA-NEXT: lw a2, 0(a0) ; RV32IA-NEXT: .LBB2_1: # %atomicrmw.start ; RV32IA-NEXT: # =>This Loop Header: Depth=1 -; RV32IA-NEXT: # Child Loop BB2_3 Depth 2 +; RV32IA-NEXT: # Child Loop BB2_2 Depth 2 ; RV32IA-NEXT: mv a3, a2 ; RV32IA-NEXT: addi a2, a2, 1 ; RV32IA-NEXT: sltu a4, a3, a1 ; RV32IA-NEXT: neg a4, a4 ; RV32IA-NEXT: and a4, a4, a2 -; RV32IA-NEXT: .LBB2_3: # %atomicrmw.start +; RV32IA-NEXT: .LBB2_2: # %atomicrmw.start ; RV32IA-NEXT: # Parent Loop BB2_1 Depth=1 ; RV32IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV32IA-NEXT: lr.w.aqrl a2, (a0) ; RV32IA-NEXT: bne a2, a3, .LBB2_1 -; RV32IA-NEXT: # %bb.4: # %atomicrmw.start -; RV32IA-NEXT: # in Loop: Header=BB2_3 Depth=2 +; RV32IA-NEXT: # %bb.3: # %atomicrmw.start +; RV32IA-NEXT: # in Loop: Header=BB2_2 Depth=2 ; RV32IA-NEXT: sc.w.rl a5, a4, (a0) -; RV32IA-NEXT: bnez a5, .LBB2_3 -; RV32IA-NEXT: # %bb.5: # %atomicrmw.start -; RV32IA-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-NEXT: bnez a5, .LBB2_2 +; RV32IA-NEXT: # %bb.4: # %atomicrmw.start +; RV32IA-NEXT: # %bb.5: # %atomicrmw.end ; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: ret ; @@ -457,23 +457,23 @@ define i32 @atomicrmw_uinc_wrap_i32(ptr %ptr, i32 %val) { ; RV64IA-NEXT: sext.w a1, a1 ; RV64IA-NEXT: .LBB2_1: # %atomicrmw.start ; RV64IA-NEXT: # =>This Loop Header: Depth=1 -; RV64IA-NEXT: # Child Loop BB2_3 Depth 2 +; RV64IA-NEXT: # Child Loop BB2_2 Depth 2 ; RV64IA-NEXT: addiw a3, a2, 1 ; RV64IA-NEXT: sext.w a4, a2 ; RV64IA-NEXT: sltu a2, a4, a1 ; RV64IA-NEXT: neg a2, a2 ; RV64IA-NEXT: and a3, a2, a3 -; RV64IA-NEXT: .LBB2_3: # %atomicrmw.start +; RV64IA-NEXT: .LBB2_2: # %atomicrmw.start ; RV64IA-NEXT: # Parent Loop BB2_1 Depth=1 ; RV64IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV64IA-NEXT: lr.w.aqrl a2, (a0) ; RV64IA-NEXT: bne a2, a4, .LBB2_1 -; RV64IA-NEXT: # %bb.4: # %atomicrmw.start -; RV64IA-NEXT: # in Loop: Header=BB2_3 Depth=2 +; RV64IA-NEXT: # %bb.3: # %atomicrmw.start +; RV64IA-NEXT: # in Loop: Header=BB2_2 Depth=2 ; RV64IA-NEXT: sc.w.rl a5, a3, (a0) -; RV64IA-NEXT: bnez a5, .LBB2_3 -; RV64IA-NEXT: # %bb.5: # %atomicrmw.start -; RV64IA-NEXT: # %bb.2: # %atomicrmw.end +; RV64IA-NEXT: bnez a5, .LBB2_2 +; RV64IA-NEXT: # %bb.4: # %atomicrmw.start +; RV64IA-NEXT: # %bb.5: # %atomicrmw.end ; RV64IA-NEXT: mv a0, a2 ; RV64IA-NEXT: ret %result = atomicrmw uinc_wrap ptr %ptr, i32 %val seq_cst @@ -645,23 +645,23 @@ define i64 @atomicrmw_uinc_wrap_i64(ptr %ptr, i64 %val) { ; RV64IA-NEXT: ld a2, 0(a0) ; RV64IA-NEXT: .LBB3_1: # %atomicrmw.start ; RV64IA-NEXT: # =>This Loop Header: Depth=1 -; RV64IA-NEXT: # Child Loop BB3_3 Depth 2 +; RV64IA-NEXT: # Child Loop BB3_2 Depth 2 ; RV64IA-NEXT: mv a3, a2 ; RV64IA-NEXT: addi a2, a2, 1 ; RV64IA-NEXT: sltu a4, a3, a1 ; RV64IA-NEXT: neg a4, a4 ; RV64IA-NEXT: and a4, a4, a2 -; RV64IA-NEXT: .LBB3_3: # %atomicrmw.start +; RV64IA-NEXT: .LBB3_2: # %atomicrmw.start ; RV64IA-NEXT: # Parent Loop BB3_1 Depth=1 ; RV64IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV64IA-NEXT: lr.d.aqrl a2, (a0) ; RV64IA-NEXT: bne a2, a3, .LBB3_1 -; RV64IA-NEXT: # %bb.4: # %atomicrmw.start -; RV64IA-NEXT: # in Loop: Header=BB3_3 Depth=2 +; RV64IA-NEXT: # %bb.3: # %atomicrmw.start +; RV64IA-NEXT: # in Loop: Header=BB3_2 Depth=2 ; RV64IA-NEXT: sc.d.rl a5, a4, (a0) -; RV64IA-NEXT: bnez a5, .LBB3_3 -; RV64IA-NEXT: # %bb.5: # %atomicrmw.start -; RV64IA-NEXT: # %bb.2: # %atomicrmw.end +; RV64IA-NEXT: bnez a5, .LBB3_2 +; RV64IA-NEXT: # %bb.4: # %atomicrmw.start +; RV64IA-NEXT: # %bb.5: # %atomicrmw.end ; RV64IA-NEXT: mv a0, a2 ; RV64IA-NEXT: ret %result = atomicrmw uinc_wrap ptr %ptr, i64 %val seq_cst @@ -732,28 +732,28 @@ define i8 @atomicrmw_udec_wrap_i8(ptr %ptr, i8 %val) { ; RV32IA-NEXT: sll a3, a4, a3 ; RV32IA-NEXT: not a3, a3 ; RV32IA-NEXT: zext.b a4, a1 -; RV32IA-NEXT: j .LBB4_2 +; RV32IA-NEXT: j .LBB4_5 ; RV32IA-NEXT: .LBB4_1: # %atomicrmw.start -; RV32IA-NEXT: # in Loop: Header=BB4_2 Depth=1 +; RV32IA-NEXT: # in Loop: Header=BB4_5 Depth=1 ; RV32IA-NEXT: zext.b a6, a7 ; RV32IA-NEXT: sll a6, a6, a0 ; RV32IA-NEXT: and a7, a5, a3 ; RV32IA-NEXT: or a7, a7, a6 -; RV32IA-NEXT: .LBB4_5: # %atomicrmw.start -; RV32IA-NEXT: # Parent Loop BB4_2 Depth=1 +; RV32IA-NEXT: .LBB4_2: # %atomicrmw.start +; RV32IA-NEXT: # Parent Loop BB4_5 Depth=1 ; RV32IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV32IA-NEXT: lr.w.aqrl a6, (a2) -; RV32IA-NEXT: bne a6, a5, .LBB4_7 -; RV32IA-NEXT: # %bb.6: # %atomicrmw.start -; RV32IA-NEXT: # in Loop: Header=BB4_5 Depth=2 +; RV32IA-NEXT: bne a6, a5, .LBB4_4 +; RV32IA-NEXT: # %bb.3: # %atomicrmw.start +; RV32IA-NEXT: # in Loop: Header=BB4_2 Depth=2 ; RV32IA-NEXT: sc.w.rl t0, a7, (a2) -; RV32IA-NEXT: bnez t0, .LBB4_5 -; RV32IA-NEXT: .LBB4_7: # %atomicrmw.start -; RV32IA-NEXT: # in Loop: Header=BB4_2 Depth=1 -; RV32IA-NEXT: beq a6, a5, .LBB4_4 -; RV32IA-NEXT: .LBB4_2: # %atomicrmw.start +; RV32IA-NEXT: bnez t0, .LBB4_2 +; RV32IA-NEXT: .LBB4_4: # %atomicrmw.start +; RV32IA-NEXT: # in Loop: Header=BB4_5 Depth=1 +; RV32IA-NEXT: beq a6, a5, .LBB4_7 +; RV32IA-NEXT: .LBB4_5: # %atomicrmw.start ; RV32IA-NEXT: # =>This Loop Header: Depth=1 -; RV32IA-NEXT: # Child Loop BB4_5 Depth 2 +; RV32IA-NEXT: # Child Loop BB4_2 Depth 2 ; RV32IA-NEXT: mv a5, a6 ; RV32IA-NEXT: srl a6, a6, a0 ; RV32IA-NEXT: zext.b a7, a6 @@ -762,11 +762,11 @@ define i8 @atomicrmw_udec_wrap_i8(ptr %ptr, i8 %val) { ; RV32IA-NEXT: or t0, t0, a7 ; RV32IA-NEXT: mv a7, a1 ; RV32IA-NEXT: bnez t0, .LBB4_1 -; RV32IA-NEXT: # %bb.3: # %atomicrmw.start -; RV32IA-NEXT: # in Loop: Header=BB4_2 Depth=1 +; RV32IA-NEXT: # %bb.6: # %atomicrmw.start +; RV32IA-NEXT: # in Loop: Header=BB4_5 Depth=1 ; RV32IA-NEXT: addi a7, a6, -1 ; RV32IA-NEXT: j .LBB4_1 -; RV32IA-NEXT: .LBB4_4: # %atomicrmw.end +; RV32IA-NEXT: .LBB4_7: # %atomicrmw.end ; RV32IA-NEXT: srl a0, a6, a0 ; RV32IA-NEXT: ret ; @@ -833,29 +833,29 @@ define i8 @atomicrmw_udec_wrap_i8(ptr %ptr, i8 %val) { ; RV64IA-NEXT: sllw a4, a5, a4 ; RV64IA-NEXT: not a4, a4 ; RV64IA-NEXT: zext.b a5, a1 -; RV64IA-NEXT: j .LBB4_2 +; RV64IA-NEXT: j .LBB4_5 ; RV64IA-NEXT: .LBB4_1: # %atomicrmw.start -; RV64IA-NEXT: # in Loop: Header=BB4_2 Depth=1 +; RV64IA-NEXT: # in Loop: Header=BB4_5 Depth=1 ; RV64IA-NEXT: sext.w a6, a3 ; RV64IA-NEXT: zext.b a7, a7 ; RV64IA-NEXT: sllw a7, a7, a0 ; RV64IA-NEXT: and a3, a3, a4 ; RV64IA-NEXT: or a7, a3, a7 -; RV64IA-NEXT: .LBB4_5: # %atomicrmw.start -; RV64IA-NEXT: # Parent Loop BB4_2 Depth=1 +; RV64IA-NEXT: .LBB4_2: # %atomicrmw.start +; RV64IA-NEXT: # Parent Loop BB4_5 Depth=1 ; RV64IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV64IA-NEXT: lr.w.aqrl a3, (a2) -; RV64IA-NEXT: bne a3, a6, .LBB4_7 -; RV64IA-NEXT: # %bb.6: # %atomicrmw.start -; RV64IA-NEXT: # in Loop: Header=BB4_5 Depth=2 +; RV64IA-NEXT: bne a3, a6, .LBB4_4 +; RV64IA-NEXT: # %bb.3: # %atomicrmw.start +; RV64IA-NEXT: # in Loop: Header=BB4_2 Depth=2 ; RV64IA-NEXT: sc.w.rl t0, a7, (a2) -; RV64IA-NEXT: bnez t0, .LBB4_5 -; RV64IA-NEXT: .LBB4_7: # %atomicrmw.start -; RV64IA-NEXT: # in Loop: Header=BB4_2 Depth=1 -; RV64IA-NEXT: beq a3, a6, .LBB4_4 -; RV64IA-NEXT: .LBB4_2: # %atomicrmw.start +; RV64IA-NEXT: bnez t0, .LBB4_2 +; RV64IA-NEXT: .LBB4_4: # %atomicrmw.start +; RV64IA-NEXT: # in Loop: Header=BB4_5 Depth=1 +; RV64IA-NEXT: beq a3, a6, .LBB4_7 +; RV64IA-NEXT: .LBB4_5: # %atomicrmw.start ; RV64IA-NEXT: # =>This Loop Header: Depth=1 -; RV64IA-NEXT: # Child Loop BB4_5 Depth 2 +; RV64IA-NEXT: # Child Loop BB4_2 Depth 2 ; RV64IA-NEXT: srlw a6, a3, a0 ; RV64IA-NEXT: zext.b a7, a6 ; RV64IA-NEXT: seqz t0, a7 @@ -863,11 +863,11 @@ define i8 @atomicrmw_udec_wrap_i8(ptr %ptr, i8 %val) { ; RV64IA-NEXT: or t0, t0, a7 ; RV64IA-NEXT: mv a7, a1 ; RV64IA-NEXT: bnez t0, .LBB4_1 -; RV64IA-NEXT: # %bb.3: # %atomicrmw.start -; RV64IA-NEXT: # in Loop: Header=BB4_2 Depth=1 +; RV64IA-NEXT: # %bb.6: # %atomicrmw.start +; RV64IA-NEXT: # in Loop: Header=BB4_5 Depth=1 ; RV64IA-NEXT: addi a7, a6, -1 ; RV64IA-NEXT: j .LBB4_1 -; RV64IA-NEXT: .LBB4_4: # %atomicrmw.end +; RV64IA-NEXT: .LBB4_7: # %atomicrmw.end ; RV64IA-NEXT: srlw a0, a3, a0 ; RV64IA-NEXT: ret %result = atomicrmw udec_wrap ptr %ptr, i8 %val seq_cst @@ -945,28 +945,28 @@ define i16 @atomicrmw_udec_wrap_i16(ptr %ptr, i16 %val) { ; RV32IA-NEXT: sll a4, a3, a4 ; RV32IA-NEXT: not a4, a4 ; RV32IA-NEXT: and a5, a1, a3 -; RV32IA-NEXT: j .LBB5_2 +; RV32IA-NEXT: j .LBB5_5 ; RV32IA-NEXT: .LBB5_1: # %atomicrmw.start -; RV32IA-NEXT: # in Loop: Header=BB5_2 Depth=1 +; RV32IA-NEXT: # in Loop: Header=BB5_5 Depth=1 ; RV32IA-NEXT: and a7, t0, a3 ; RV32IA-NEXT: sll a7, a7, a0 ; RV32IA-NEXT: and t0, a6, a4 ; RV32IA-NEXT: or t0, t0, a7 -; RV32IA-NEXT: .LBB5_5: # %atomicrmw.start -; RV32IA-NEXT: # Parent Loop BB5_2 Depth=1 +; RV32IA-NEXT: .LBB5_2: # %atomicrmw.start +; RV32IA-NEXT: # Parent Loop BB5_5 Depth=1 ; RV32IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV32IA-NEXT: lr.w.aqrl a7, (a2) -; RV32IA-NEXT: bne a7, a6, .LBB5_7 -; RV32IA-NEXT: # %bb.6: # %atomicrmw.start -; RV32IA-NEXT: # in Loop: Header=BB5_5 Depth=2 +; RV32IA-NEXT: bne a7, a6, .LBB5_4 +; RV32IA-NEXT: # %bb.3: # %atomicrmw.start +; RV32IA-NEXT: # in Loop: Header=BB5_2 Depth=2 ; RV32IA-NEXT: sc.w.rl t1, t0, (a2) -; RV32IA-NEXT: bnez t1, .LBB5_5 -; RV32IA-NEXT: .LBB5_7: # %atomicrmw.start -; RV32IA-NEXT: # in Loop: Header=BB5_2 Depth=1 -; RV32IA-NEXT: beq a7, a6, .LBB5_4 -; RV32IA-NEXT: .LBB5_2: # %atomicrmw.start +; RV32IA-NEXT: bnez t1, .LBB5_2 +; RV32IA-NEXT: .LBB5_4: # %atomicrmw.start +; RV32IA-NEXT: # in Loop: Header=BB5_5 Depth=1 +; RV32IA-NEXT: beq a7, a6, .LBB5_7 +; RV32IA-NEXT: .LBB5_5: # %atomicrmw.start ; RV32IA-NEXT: # =>This Loop Header: Depth=1 -; RV32IA-NEXT: # Child Loop BB5_5 Depth 2 +; RV32IA-NEXT: # Child Loop BB5_2 Depth 2 ; RV32IA-NEXT: mv a6, a7 ; RV32IA-NEXT: srl a7, a7, a0 ; RV32IA-NEXT: and t0, a7, a3 @@ -975,11 +975,11 @@ define i16 @atomicrmw_udec_wrap_i16(ptr %ptr, i16 %val) { ; RV32IA-NEXT: or t1, t1, t0 ; RV32IA-NEXT: mv t0, a1 ; RV32IA-NEXT: bnez t1, .LBB5_1 -; RV32IA-NEXT: # %bb.3: # %atomicrmw.start -; RV32IA-NEXT: # in Loop: Header=BB5_2 Depth=1 +; RV32IA-NEXT: # %bb.6: # %atomicrmw.start +; RV32IA-NEXT: # in Loop: Header=BB5_5 Depth=1 ; RV32IA-NEXT: addi t0, a7, -1 ; RV32IA-NEXT: j .LBB5_1 -; RV32IA-NEXT: .LBB5_4: # %atomicrmw.end +; RV32IA-NEXT: .LBB5_7: # %atomicrmw.end ; RV32IA-NEXT: srl a0, a7, a0 ; RV32IA-NEXT: ret ; @@ -1053,29 +1053,29 @@ define i16 @atomicrmw_udec_wrap_i16(ptr %ptr, i16 %val) { ; RV64IA-NEXT: sllw a5, a3, a5 ; RV64IA-NEXT: not a5, a5 ; RV64IA-NEXT: and a6, a1, a3 -; RV64IA-NEXT: j .LBB5_2 +; RV64IA-NEXT: j .LBB5_5 ; RV64IA-NEXT: .LBB5_1: # %atomicrmw.start -; RV64IA-NEXT: # in Loop: Header=BB5_2 Depth=1 +; RV64IA-NEXT: # in Loop: Header=BB5_5 Depth=1 ; RV64IA-NEXT: sext.w a7, a4 ; RV64IA-NEXT: and t0, t0, a3 ; RV64IA-NEXT: sllw t0, t0, a0 ; RV64IA-NEXT: and a4, a4, a5 ; RV64IA-NEXT: or t0, a4, t0 -; RV64IA-NEXT: .LBB5_5: # %atomicrmw.start -; RV64IA-NEXT: # Parent Loop BB5_2 Depth=1 +; RV64IA-NEXT: .LBB5_2: # %atomicrmw.start +; RV64IA-NEXT: # Parent Loop BB5_5 Depth=1 ; RV64IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV64IA-NEXT: lr.w.aqrl a4, (a2) -; RV64IA-NEXT: bne a4, a7, .LBB5_7 -; RV64IA-NEXT: # %bb.6: # %atomicrmw.start -; RV64IA-NEXT: # in Loop: Header=BB5_5 Depth=2 +; RV64IA-NEXT: bne a4, a7, .LBB5_4 +; RV64IA-NEXT: # %bb.3: # %atomicrmw.start +; RV64IA-NEXT: # in Loop: Header=BB5_2 Depth=2 ; RV64IA-NEXT: sc.w.rl t1, t0, (a2) -; RV64IA-NEXT: bnez t1, .LBB5_5 -; RV64IA-NEXT: .LBB5_7: # %atomicrmw.start -; RV64IA-NEXT: # in Loop: Header=BB5_2 Depth=1 -; RV64IA-NEXT: beq a4, a7, .LBB5_4 -; RV64IA-NEXT: .LBB5_2: # %atomicrmw.start +; RV64IA-NEXT: bnez t1, .LBB5_2 +; RV64IA-NEXT: .LBB5_4: # %atomicrmw.start +; RV64IA-NEXT: # in Loop: Header=BB5_5 Depth=1 +; RV64IA-NEXT: beq a4, a7, .LBB5_7 +; RV64IA-NEXT: .LBB5_5: # %atomicrmw.start ; RV64IA-NEXT: # =>This Loop Header: Depth=1 -; RV64IA-NEXT: # Child Loop BB5_5 Depth 2 +; RV64IA-NEXT: # Child Loop BB5_2 Depth 2 ; RV64IA-NEXT: srlw a7, a4, a0 ; RV64IA-NEXT: and t0, a7, a3 ; RV64IA-NEXT: seqz t1, t0 @@ -1083,11 +1083,11 @@ define i16 @atomicrmw_udec_wrap_i16(ptr %ptr, i16 %val) { ; RV64IA-NEXT: or t1, t1, t0 ; RV64IA-NEXT: mv t0, a1 ; RV64IA-NEXT: bnez t1, .LBB5_1 -; RV64IA-NEXT: # %bb.3: # %atomicrmw.start -; RV64IA-NEXT: # in Loop: Header=BB5_2 Depth=1 +; RV64IA-NEXT: # %bb.6: # %atomicrmw.start +; RV64IA-NEXT: # in Loop: Header=BB5_5 Depth=1 ; RV64IA-NEXT: addi t0, a7, -1 ; RV64IA-NEXT: j .LBB5_1 -; RV64IA-NEXT: .LBB5_4: # %atomicrmw.end +; RV64IA-NEXT: .LBB5_7: # %atomicrmw.end ; RV64IA-NEXT: srlw a0, a4, a0 ; RV64IA-NEXT: ret %result = atomicrmw udec_wrap ptr %ptr, i16 %val seq_cst @@ -1145,35 +1145,35 @@ define i32 @atomicrmw_udec_wrap_i32(ptr %ptr, i32 %val) { ; RV32IA-LABEL: atomicrmw_udec_wrap_i32: ; RV32IA: # %bb.0: ; RV32IA-NEXT: lw a2, 0(a0) -; RV32IA-NEXT: j .LBB6_2 +; RV32IA-NEXT: j .LBB6_5 ; RV32IA-NEXT: .LBB6_1: # %atomicrmw.start -; RV32IA-NEXT: # in Loop: Header=BB6_2 Depth=1 -; RV32IA-NEXT: .LBB6_5: # %atomicrmw.start -; RV32IA-NEXT: # Parent Loop BB6_2 Depth=1 +; RV32IA-NEXT: # in Loop: Header=BB6_5 Depth=1 +; RV32IA-NEXT: .LBB6_2: # %atomicrmw.start +; RV32IA-NEXT: # Parent Loop BB6_5 Depth=1 ; RV32IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV32IA-NEXT: lr.w.aqrl a2, (a0) -; RV32IA-NEXT: bne a2, a3, .LBB6_7 -; RV32IA-NEXT: # %bb.6: # %atomicrmw.start -; RV32IA-NEXT: # in Loop: Header=BB6_5 Depth=2 +; RV32IA-NEXT: bne a2, a3, .LBB6_4 +; RV32IA-NEXT: # %bb.3: # %atomicrmw.start +; RV32IA-NEXT: # in Loop: Header=BB6_2 Depth=2 ; RV32IA-NEXT: sc.w.rl a5, a4, (a0) -; RV32IA-NEXT: bnez a5, .LBB6_5 -; RV32IA-NEXT: .LBB6_7: # %atomicrmw.start -; RV32IA-NEXT: # in Loop: Header=BB6_2 Depth=1 -; RV32IA-NEXT: beq a2, a3, .LBB6_4 -; RV32IA-NEXT: .LBB6_2: # %atomicrmw.start +; RV32IA-NEXT: bnez a5, .LBB6_2 +; RV32IA-NEXT: .LBB6_4: # %atomicrmw.start +; RV32IA-NEXT: # in Loop: Header=BB6_5 Depth=1 +; RV32IA-NEXT: beq a2, a3, .LBB6_7 +; RV32IA-NEXT: .LBB6_5: # %atomicrmw.start ; RV32IA-NEXT: # =>This Loop Header: Depth=1 -; RV32IA-NEXT: # Child Loop BB6_5 Depth 2 +; RV32IA-NEXT: # Child Loop BB6_2 Depth 2 ; RV32IA-NEXT: mv a3, a2 ; RV32IA-NEXT: seqz a2, a2 ; RV32IA-NEXT: sltu a4, a1, a3 ; RV32IA-NEXT: or a2, a2, a4 ; RV32IA-NEXT: mv a4, a1 ; RV32IA-NEXT: bnez a2, .LBB6_1 -; RV32IA-NEXT: # %bb.3: # %atomicrmw.start -; RV32IA-NEXT: # in Loop: Header=BB6_2 Depth=1 +; RV32IA-NEXT: # %bb.6: # %atomicrmw.start +; RV32IA-NEXT: # in Loop: Header=BB6_5 Depth=1 ; RV32IA-NEXT: addi a4, a3, -1 ; RV32IA-NEXT: j .LBB6_1 -; RV32IA-NEXT: .LBB6_4: # %atomicrmw.end +; RV32IA-NEXT: .LBB6_7: # %atomicrmw.end ; RV32IA-NEXT: mv a0, a2 ; RV32IA-NEXT: ret ; @@ -1233,35 +1233,35 @@ define i32 @atomicrmw_udec_wrap_i32(ptr %ptr, i32 %val) { ; RV64IA: # %bb.0: ; RV64IA-NEXT: lw a2, 0(a0) ; RV64IA-NEXT: sext.w a3, a1 -; RV64IA-NEXT: j .LBB6_2 +; RV64IA-NEXT: j .LBB6_5 ; RV64IA-NEXT: .LBB6_1: # %atomicrmw.start -; RV64IA-NEXT: # in Loop: Header=BB6_2 Depth=1 -; RV64IA-NEXT: .LBB6_5: # %atomicrmw.start -; RV64IA-NEXT: # Parent Loop BB6_2 Depth=1 +; RV64IA-NEXT: # in Loop: Header=BB6_5 Depth=1 +; RV64IA-NEXT: .LBB6_2: # %atomicrmw.start +; RV64IA-NEXT: # Parent Loop BB6_5 Depth=1 ; RV64IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV64IA-NEXT: lr.w.aqrl a2, (a0) -; RV64IA-NEXT: bne a2, a4, .LBB6_7 -; RV64IA-NEXT: # %bb.6: # %atomicrmw.start -; RV64IA-NEXT: # in Loop: Header=BB6_5 Depth=2 +; RV64IA-NEXT: bne a2, a4, .LBB6_4 +; RV64IA-NEXT: # %bb.3: # %atomicrmw.start +; RV64IA-NEXT: # in Loop: Header=BB6_2 Depth=2 ; RV64IA-NEXT: sc.w.rl a6, a5, (a0) -; RV64IA-NEXT: bnez a6, .LBB6_5 -; RV64IA-NEXT: .LBB6_7: # %atomicrmw.start -; RV64IA-NEXT: # in Loop: Header=BB6_2 Depth=1 -; RV64IA-NEXT: beq a2, a4, .LBB6_4 -; RV64IA-NEXT: .LBB6_2: # %atomicrmw.start +; RV64IA-NEXT: bnez a6, .LBB6_2 +; RV64IA-NEXT: .LBB6_4: # %atomicrmw.start +; RV64IA-NEXT: # in Loop: Header=BB6_5 Depth=1 +; RV64IA-NEXT: beq a2, a4, .LBB6_7 +; RV64IA-NEXT: .LBB6_5: # %atomicrmw.start ; RV64IA-NEXT: # =>This Loop Header: Depth=1 -; RV64IA-NEXT: # Child Loop BB6_5 Depth 2 +; RV64IA-NEXT: # Child Loop BB6_2 Depth 2 ; RV64IA-NEXT: sext.w a4, a2 ; RV64IA-NEXT: seqz a5, a4 ; RV64IA-NEXT: sltu a6, a3, a4 ; RV64IA-NEXT: or a6, a5, a6 ; RV64IA-NEXT: mv a5, a1 ; RV64IA-NEXT: bnez a6, .LBB6_1 -; RV64IA-NEXT: # %bb.3: # %atomicrmw.start -; RV64IA-NEXT: # in Loop: Header=BB6_2 Depth=1 +; RV64IA-NEXT: # %bb.6: # %atomicrmw.start +; RV64IA-NEXT: # in Loop: Header=BB6_5 Depth=1 ; RV64IA-NEXT: addiw a5, a2, -1 ; RV64IA-NEXT: j .LBB6_1 -; RV64IA-NEXT: .LBB6_4: # %atomicrmw.end +; RV64IA-NEXT: .LBB6_7: # %atomicrmw.end ; RV64IA-NEXT: mv a0, a2 ; RV64IA-NEXT: ret %result = atomicrmw udec_wrap ptr %ptr, i32 %val seq_cst @@ -1455,35 +1455,35 @@ define i64 @atomicrmw_udec_wrap_i64(ptr %ptr, i64 %val) { ; RV64IA-LABEL: atomicrmw_udec_wrap_i64: ; RV64IA: # %bb.0: ; RV64IA-NEXT: ld a2, 0(a0) -; RV64IA-NEXT: j .LBB7_2 +; RV64IA-NEXT: j .LBB7_5 ; RV64IA-NEXT: .LBB7_1: # %atomicrmw.start -; RV64IA-NEXT: # in Loop: Header=BB7_2 Depth=1 -; RV64IA-NEXT: .LBB7_5: # %atomicrmw.start -; RV64IA-NEXT: # Parent Loop BB7_2 Depth=1 +; RV64IA-NEXT: # in Loop: Header=BB7_5 Depth=1 +; RV64IA-NEXT: .LBB7_2: # %atomicrmw.start +; RV64IA-NEXT: # Parent Loop BB7_5 Depth=1 ; RV64IA-NEXT: # => This Inner Loop Header: Depth=2 ; RV64IA-NEXT: lr.d.aqrl a2, (a0) -; RV64IA-NEXT: bne a2, a3, .LBB7_7 -; RV64IA-NEXT: # %bb.6: # %atomicrmw.start -; RV64IA-NEXT: # in Loop: Header=BB7_5 Depth=2 +; RV64IA-NEXT: bne a2, a3, .LBB7_4 +; RV64IA-NEXT: # %bb.3: # %atomicrmw.start +; RV64IA-NEXT: # in Loop: Header=BB7_2 Depth=2 ; RV64IA-NEXT: sc.d.rl a5, a4, (a0) -; RV64IA-NEXT: bnez a5, .LBB7_5 -; RV64IA-NEXT: .LBB7_7: # %atomicrmw.start -; RV64IA-NEXT: # in Loop: Header=BB7_2 Depth=1 -; RV64IA-NEXT: beq a2, a3, .LBB7_4 -; RV64IA-NEXT: .LBB7_2: # %atomicrmw.start +; RV64IA-NEXT: bnez a5, .LBB7_2 +; RV64IA-NEXT: .LBB7_4: # %atomicrmw.start +; RV64IA-NEXT: # in Loop: Header=BB7_5 Depth=1 +; RV64IA-NEXT: beq a2, a3, .LBB7_7 +; RV64IA-NEXT: .LBB7_5: # %atomicrmw.start ; RV64IA-NEXT: # =>This Loop Header: Depth=1 -; RV64IA-NEXT: # Child Loop BB7_5 Depth 2 +; RV64IA-NEXT: # Child Loop BB7_2 Depth 2 ; RV64IA-NEXT: mv a3, a2 ; RV64IA-NEXT: seqz a2, a2 ; RV64IA-NEXT: sltu a4, a1, a3 ; RV64IA-NEXT: or a2, a2, a4 ; RV64IA-NEXT: mv a4, a1 ; RV64IA-NEXT: bnez a2, .LBB7_1 -; RV64IA-NEXT: # %bb.3: # %atomicrmw.start -; RV64IA-NEXT: # in Loop: Header=BB7_2 Depth=1 +; RV64IA-NEXT: # %bb.6: # %atomicrmw.start +; RV64IA-NEXT: # in Loop: Header=BB7_5 Depth=1 ; RV64IA-NEXT: addi a4, a3, -1 ; RV64IA-NEXT: j .LBB7_1 -; RV64IA-NEXT: .LBB7_4: # %atomicrmw.end +; RV64IA-NEXT: .LBB7_7: # %atomicrmw.end ; RV64IA-NEXT: mv a0, a2 ; RV64IA-NEXT: ret %result = atomicrmw udec_wrap ptr %ptr, i64 %val seq_cst diff --git a/llvm/test/CodeGen/RISCV/branch-relaxation-rv32.ll b/llvm/test/CodeGen/RISCV/branch-relaxation-rv32.ll index e987923233865..c94b6f3201c8c 100644 --- a/llvm/test/CodeGen/RISCV/branch-relaxation-rv32.ll +++ b/llvm/test/CodeGen/RISCV/branch-relaxation-rv32.ll @@ -50,20 +50,20 @@ define i32 @relax_jal(i1 %a) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: andi a0, a0, 1 -; CHECK-NEXT: bnez a0, .LBB1_1 -; CHECK-NEXT: # %bb.4: -; CHECK-NEXT: jump .LBB1_2, a0 -; CHECK-NEXT: .LBB1_1: # %iftrue +; CHECK-NEXT: bnez a0, .LBB1_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: jump .LBB1_3, a0 +; CHECK-NEXT: .LBB1_2: # %iftrue ; CHECK-NEXT: #APP ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #APP ; CHECK-NEXT: .zero 1048576 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: j .LBB1_3 -; CHECK-NEXT: .LBB1_2: # %jmp +; CHECK-NEXT: j .LBB1_4 +; CHECK-NEXT: .LBB1_3: # %jmp ; CHECK-NEXT: #APP ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: .LBB1_3: # %tail +; CHECK-NEXT: .LBB1_4: # %tail ; CHECK-NEXT: li a0, 1 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret @@ -73,20 +73,20 @@ define i32 @relax_jal(i1 %a) nounwind { ; CHECK-ZICFILP-NEXT: lpad 0 ; CHECK-ZICFILP-NEXT: addi sp, sp, -16 ; CHECK-ZICFILP-NEXT: andi a0, a0, 1 -; CHECK-ZICFILP-NEXT: bnez a0, .LBB1_1 -; CHECK-ZICFILP-NEXT: # %bb.4: -; CHECK-ZICFILP-NEXT: jump .LBB1_2, t2 -; CHECK-ZICFILP-NEXT: .LBB1_1: # %iftrue +; CHECK-ZICFILP-NEXT: bnez a0, .LBB1_2 +; CHECK-ZICFILP-NEXT: # %bb.1: +; CHECK-ZICFILP-NEXT: jump .LBB1_3, t2 +; CHECK-ZICFILP-NEXT: .LBB1_2: # %iftrue ; CHECK-ZICFILP-NEXT: #APP ; CHECK-ZICFILP-NEXT: #NO_APP ; CHECK-ZICFILP-NEXT: #APP ; CHECK-ZICFILP-NEXT: .zero 1048576 ; CHECK-ZICFILP-NEXT: #NO_APP -; CHECK-ZICFILP-NEXT: j .LBB1_3 -; CHECK-ZICFILP-NEXT: .LBB1_2: # %jmp +; CHECK-ZICFILP-NEXT: j .LBB1_4 +; CHECK-ZICFILP-NEXT: .LBB1_3: # %jmp ; CHECK-ZICFILP-NEXT: #APP ; CHECK-ZICFILP-NEXT: #NO_APP -; CHECK-ZICFILP-NEXT: .LBB1_3: # %tail +; CHECK-ZICFILP-NEXT: .LBB1_4: # %tail ; CHECK-ZICFILP-NEXT: li a0, 1 ; CHECK-ZICFILP-NEXT: addi sp, sp, 16 ; CHECK-ZICFILP-NEXT: ret @@ -223,18 +223,18 @@ define void @relax_jal_spill_32() { ; CHECK-NEXT: #APP ; CHECK-NEXT: li t6, 31 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: beq t5, t6, .LBB2_1 -; CHECK-NEXT: # %bb.3: +; CHECK-NEXT: beq t5, t6, .LBB2_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: sw s11, 0(sp) # 4-byte Folded Spill -; CHECK-NEXT: jump .LBB2_4, s11 -; CHECK-NEXT: .LBB2_1: # %branch_1 +; CHECK-NEXT: jump .LBB2_3, s11 +; CHECK-NEXT: .LBB2_2: # %branch_1 ; CHECK-NEXT: #APP ; CHECK-NEXT: .zero 1048576 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: j .LBB2_2 -; CHECK-NEXT: .LBB2_4: # %branch_2 +; CHECK-NEXT: j .LBB2_4 +; CHECK-NEXT: .LBB2_3: # %branch_2 ; CHECK-NEXT: lw s11, 0(sp) # 4-byte Folded Reload -; CHECK-NEXT: .LBB2_2: # %branch_2 +; CHECK-NEXT: .LBB2_4: # %branch_2 ; CHECK-NEXT: #APP ; CHECK-NEXT: # reg use ra ; CHECK-NEXT: #NO_APP @@ -464,18 +464,18 @@ define void @relax_jal_spill_32() { ; CHECK-ZICFILP-NEXT: #APP ; CHECK-ZICFILP-NEXT: li t6, 31 ; CHECK-ZICFILP-NEXT: #NO_APP -; CHECK-ZICFILP-NEXT: beq t5, t6, .LBB2_1 -; CHECK-ZICFILP-NEXT: # %bb.3: +; CHECK-ZICFILP-NEXT: beq t5, t6, .LBB2_2 +; CHECK-ZICFILP-NEXT: # %bb.1: ; CHECK-ZICFILP-NEXT: sw t2, 0(sp) # 4-byte Folded Spill -; CHECK-ZICFILP-NEXT: jump .LBB2_4, t2 -; CHECK-ZICFILP-NEXT: .LBB2_1: # %branch_1 +; CHECK-ZICFILP-NEXT: jump .LBB2_3, t2 +; CHECK-ZICFILP-NEXT: .LBB2_2: # %branch_1 ; CHECK-ZICFILP-NEXT: #APP ; CHECK-ZICFILP-NEXT: .zero 1048576 ; CHECK-ZICFILP-NEXT: #NO_APP -; CHECK-ZICFILP-NEXT: j .LBB2_2 -; CHECK-ZICFILP-NEXT: .LBB2_4: # %branch_2 +; CHECK-ZICFILP-NEXT: j .LBB2_4 +; CHECK-ZICFILP-NEXT: .LBB2_3: # %branch_2 ; CHECK-ZICFILP-NEXT: lw t2, 0(sp) # 4-byte Folded Reload -; CHECK-ZICFILP-NEXT: .LBB2_2: # %branch_2 +; CHECK-ZICFILP-NEXT: .LBB2_4: # %branch_2 ; CHECK-ZICFILP-NEXT: #APP ; CHECK-ZICFILP-NEXT: # reg use ra ; CHECK-ZICFILP-NEXT: #NO_APP @@ -783,18 +783,18 @@ define void @relax_jal_spill_32_adjust_spill_slot() { ; CHECK-NEXT: #APP ; CHECK-NEXT: li t6, 31 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: beq t5, t6, .LBB3_1 -; CHECK-NEXT: # %bb.3: +; CHECK-NEXT: beq t5, t6, .LBB3_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: sw s11, 0(sp) # 4-byte Folded Spill -; CHECK-NEXT: jump .LBB3_4, s11 -; CHECK-NEXT: .LBB3_1: # %branch_1 +; CHECK-NEXT: jump .LBB3_3, s11 +; CHECK-NEXT: .LBB3_2: # %branch_1 ; CHECK-NEXT: #APP ; CHECK-NEXT: .zero 1048576 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: j .LBB3_2 -; CHECK-NEXT: .LBB3_4: # %branch_2 +; CHECK-NEXT: j .LBB3_4 +; CHECK-NEXT: .LBB3_3: # %branch_2 ; CHECK-NEXT: lw s11, 0(sp) # 4-byte Folded Reload -; CHECK-NEXT: .LBB3_2: # %branch_2 +; CHECK-NEXT: .LBB3_4: # %branch_2 ; CHECK-NEXT: #APP ; CHECK-NEXT: # reg use ra ; CHECK-NEXT: #NO_APP @@ -1033,18 +1033,18 @@ define void @relax_jal_spill_32_adjust_spill_slot() { ; CHECK-ZICFILP-NEXT: #APP ; CHECK-ZICFILP-NEXT: li t6, 31 ; CHECK-ZICFILP-NEXT: #NO_APP -; CHECK-ZICFILP-NEXT: beq t5, t6, .LBB3_1 -; CHECK-ZICFILP-NEXT: # %bb.3: +; CHECK-ZICFILP-NEXT: beq t5, t6, .LBB3_2 +; CHECK-ZICFILP-NEXT: # %bb.1: ; CHECK-ZICFILP-NEXT: sw t2, 0(sp) # 4-byte Folded Spill -; CHECK-ZICFILP-NEXT: jump .LBB3_4, t2 -; CHECK-ZICFILP-NEXT: .LBB3_1: # %branch_1 +; CHECK-ZICFILP-NEXT: jump .LBB3_3, t2 +; CHECK-ZICFILP-NEXT: .LBB3_2: # %branch_1 ; CHECK-ZICFILP-NEXT: #APP ; CHECK-ZICFILP-NEXT: .zero 1048576 ; CHECK-ZICFILP-NEXT: #NO_APP -; CHECK-ZICFILP-NEXT: j .LBB3_2 -; CHECK-ZICFILP-NEXT: .LBB3_4: # %branch_2 +; CHECK-ZICFILP-NEXT: j .LBB3_4 +; CHECK-ZICFILP-NEXT: .LBB3_3: # %branch_2 ; CHECK-ZICFILP-NEXT: lw t2, 0(sp) # 4-byte Folded Reload -; CHECK-ZICFILP-NEXT: .LBB3_2: # %branch_2 +; CHECK-ZICFILP-NEXT: .LBB3_4: # %branch_2 ; CHECK-ZICFILP-NEXT: #APP ; CHECK-ZICFILP-NEXT: # reg use ra ; CHECK-ZICFILP-NEXT: #NO_APP @@ -1347,22 +1347,22 @@ define void @relax_jal_spill_32_restore_block_correspondence() { ; CHECK-NEXT: #APP ; CHECK-NEXT: li t6, 31 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: bne t5, t6, .LBB4_2 -; CHECK-NEXT: j .LBB4_1 -; CHECK-NEXT: .LBB4_8: # %dest_1 -; CHECK-NEXT: lw s11, 0(sp) # 4-byte Folded Reload +; CHECK-NEXT: bne t5, t6, .LBB4_3 +; CHECK-NEXT: j .LBB4_2 ; CHECK-NEXT: .LBB4_1: # %dest_1 +; CHECK-NEXT: lw s11, 0(sp) # 4-byte Folded Reload +; CHECK-NEXT: .LBB4_2: # %dest_1 ; CHECK-NEXT: #APP ; CHECK-NEXT: # dest 1 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: j .LBB4_3 -; CHECK-NEXT: .LBB4_2: # %cond_2 -; CHECK-NEXT: bne t3, t4, .LBB4_5 -; CHECK-NEXT: .LBB4_3: # %dest_2 +; CHECK-NEXT: j .LBB4_4 +; CHECK-NEXT: .LBB4_3: # %cond_2 +; CHECK-NEXT: bne t3, t4, .LBB4_6 +; CHECK-NEXT: .LBB4_4: # %dest_2 ; CHECK-NEXT: #APP ; CHECK-NEXT: # dest 2 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: .LBB4_4: # %dest_3 +; CHECK-NEXT: .LBB4_5: # %dest_3 ; CHECK-NEXT: #APP ; CHECK-NEXT: # dest 3 ; CHECK-NEXT: #NO_APP @@ -1479,16 +1479,16 @@ define void @relax_jal_spill_32_restore_block_correspondence() { ; CHECK-NEXT: addi sp, sp, 64 ; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret -; CHECK-NEXT: .LBB4_5: # %cond_3 +; CHECK-NEXT: .LBB4_6: # %cond_3 ; CHECK-NEXT: .cfi_restore_state -; CHECK-NEXT: beq t1, t2, .LBB4_4 -; CHECK-NEXT: # %bb.6: # %space +; CHECK-NEXT: beq t1, t2, .LBB4_5 +; CHECK-NEXT: # %bb.7: # %space ; CHECK-NEXT: #APP ; CHECK-NEXT: .zero 1048576 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: # %bb.7: # %space +; CHECK-NEXT: # %bb.8: # %space ; CHECK-NEXT: sw s11, 0(sp) # 4-byte Folded Spill -; CHECK-NEXT: jump .LBB4_8, s11 +; CHECK-NEXT: jump .LBB4_1, s11 ; ; CHECK-ZICFILP-LABEL: relax_jal_spill_32_restore_block_correspondence: ; CHECK-ZICFILP: # %bb.0: # %entry @@ -1606,22 +1606,22 @@ define void @relax_jal_spill_32_restore_block_correspondence() { ; CHECK-ZICFILP-NEXT: #APP ; CHECK-ZICFILP-NEXT: li t6, 31 ; CHECK-ZICFILP-NEXT: #NO_APP -; CHECK-ZICFILP-NEXT: bne t5, t6, .LBB4_2 -; CHECK-ZICFILP-NEXT: j .LBB4_1 -; CHECK-ZICFILP-NEXT: .LBB4_8: # %dest_1 -; CHECK-ZICFILP-NEXT: lw t2, 0(sp) # 4-byte Folded Reload +; CHECK-ZICFILP-NEXT: bne t5, t6, .LBB4_3 +; CHECK-ZICFILP-NEXT: j .LBB4_2 ; CHECK-ZICFILP-NEXT: .LBB4_1: # %dest_1 +; CHECK-ZICFILP-NEXT: lw t2, 0(sp) # 4-byte Folded Reload +; CHECK-ZICFILP-NEXT: .LBB4_2: # %dest_1 ; CHECK-ZICFILP-NEXT: #APP ; CHECK-ZICFILP-NEXT: # dest 1 ; CHECK-ZICFILP-NEXT: #NO_APP -; CHECK-ZICFILP-NEXT: j .LBB4_3 -; CHECK-ZICFILP-NEXT: .LBB4_2: # %cond_2 -; CHECK-ZICFILP-NEXT: bne t3, t4, .LBB4_5 -; CHECK-ZICFILP-NEXT: .LBB4_3: # %dest_2 +; CHECK-ZICFILP-NEXT: j .LBB4_4 +; CHECK-ZICFILP-NEXT: .LBB4_3: # %cond_2 +; CHECK-ZICFILP-NEXT: bne t3, t4, .LBB4_6 +; CHECK-ZICFILP-NEXT: .LBB4_4: # %dest_2 ; CHECK-ZICFILP-NEXT: #APP ; CHECK-ZICFILP-NEXT: # dest 2 ; CHECK-ZICFILP-NEXT: #NO_APP -; CHECK-ZICFILP-NEXT: .LBB4_4: # %dest_3 +; CHECK-ZICFILP-NEXT: .LBB4_5: # %dest_3 ; CHECK-ZICFILP-NEXT: #APP ; CHECK-ZICFILP-NEXT: # dest 3 ; CHECK-ZICFILP-NEXT: #NO_APP @@ -1738,16 +1738,16 @@ define void @relax_jal_spill_32_restore_block_correspondence() { ; CHECK-ZICFILP-NEXT: addi sp, sp, 64 ; CHECK-ZICFILP-NEXT: .cfi_def_cfa_offset 0 ; CHECK-ZICFILP-NEXT: ret -; CHECK-ZICFILP-NEXT: .LBB4_5: # %cond_3 +; CHECK-ZICFILP-NEXT: .LBB4_6: # %cond_3 ; CHECK-ZICFILP-NEXT: .cfi_restore_state -; CHECK-ZICFILP-NEXT: beq t1, t2, .LBB4_4 -; CHECK-ZICFILP-NEXT: # %bb.6: # %space +; CHECK-ZICFILP-NEXT: beq t1, t2, .LBB4_5 +; CHECK-ZICFILP-NEXT: # %bb.7: # %space ; CHECK-ZICFILP-NEXT: #APP ; CHECK-ZICFILP-NEXT: .zero 1048576 ; CHECK-ZICFILP-NEXT: #NO_APP -; CHECK-ZICFILP-NEXT: # %bb.7: # %space +; CHECK-ZICFILP-NEXT: # %bb.8: # %space ; CHECK-ZICFILP-NEXT: sw t2, 0(sp) # 4-byte Folded Spill -; CHECK-ZICFILP-NEXT: jump .LBB4_8, t2 +; CHECK-ZICFILP-NEXT: jump .LBB4_1, t2 entry: %ra = call i32 asm sideeffect "addi ra, x0, 1", "={ra}"() %t0 = call i32 asm sideeffect "addi t0, x0, 5", "={t0}"() diff --git a/llvm/test/CodeGen/RISCV/branch-relaxation-rv32e.ll b/llvm/test/CodeGen/RISCV/branch-relaxation-rv32e.ll index cd8bc9ba3f34b..25acea28d16f4 100644 --- a/llvm/test/CodeGen/RISCV/branch-relaxation-rv32e.ll +++ b/llvm/test/CodeGen/RISCV/branch-relaxation-rv32e.ll @@ -35,20 +35,20 @@ define i32 @relax_jal(i1 %a) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: addi sp, sp, -4 ; CHECK-NEXT: andi a0, a0, 1 -; CHECK-NEXT: bnez a0, .LBB1_1 -; CHECK-NEXT: # %bb.4: -; CHECK-NEXT: jump .LBB1_2, a0 -; CHECK-NEXT: .LBB1_1: # %iftrue +; CHECK-NEXT: bnez a0, .LBB1_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: jump .LBB1_3, a0 +; CHECK-NEXT: .LBB1_2: # %iftrue ; CHECK-NEXT: #APP ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #APP ; CHECK-NEXT: .zero 1048576 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: j .LBB1_3 -; CHECK-NEXT: .LBB1_2: # %jmp +; CHECK-NEXT: j .LBB1_4 +; CHECK-NEXT: .LBB1_3: # %jmp ; CHECK-NEXT: #APP ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: .LBB1_3: # %tail +; CHECK-NEXT: .LBB1_4: # %tail ; CHECK-NEXT: li a0, 1 ; CHECK-NEXT: addi sp, sp, 4 ; CHECK-NEXT: ret @@ -117,18 +117,18 @@ define void @relax_jal_spill_32() { ; CHECK-NEXT: #APP ; CHECK-NEXT: li a5, 15 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: beq a4, a5, .LBB2_1 -; CHECK-NEXT: # %bb.3: +; CHECK-NEXT: beq a4, a5, .LBB2_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: sw s1, 0(sp) # 4-byte Folded Spill -; CHECK-NEXT: jump .LBB2_4, s1 -; CHECK-NEXT: .LBB2_1: # %branch_1 +; CHECK-NEXT: jump .LBB2_3, s1 +; CHECK-NEXT: .LBB2_2: # %branch_1 ; CHECK-NEXT: #APP ; CHECK-NEXT: .zero 1048576 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: j .LBB2_2 -; CHECK-NEXT: .LBB2_4: # %branch_2 +; CHECK-NEXT: j .LBB2_4 +; CHECK-NEXT: .LBB2_3: # %branch_2 ; CHECK-NEXT: lw s1, 0(sp) # 4-byte Folded Reload -; CHECK-NEXT: .LBB2_2: # %branch_2 +; CHECK-NEXT: .LBB2_4: # %branch_2 ; CHECK-NEXT: #APP ; CHECK-NEXT: # reg use ra ; CHECK-NEXT: #NO_APP @@ -268,18 +268,18 @@ define void @relax_jal_spill_32_adjust_spill_slot() { ; CHECK-NEXT: #APP ; CHECK-NEXT: li a5, 15 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: beq a4, a5, .LBB3_1 -; CHECK-NEXT: # %bb.3: +; CHECK-NEXT: beq a4, a5, .LBB3_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: sw s1, 0(sp) # 4-byte Folded Spill -; CHECK-NEXT: jump .LBB3_4, s1 -; CHECK-NEXT: .LBB3_1: # %branch_1 +; CHECK-NEXT: jump .LBB3_3, s1 +; CHECK-NEXT: .LBB3_2: # %branch_1 ; CHECK-NEXT: #APP ; CHECK-NEXT: .zero 1048576 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: j .LBB3_2 -; CHECK-NEXT: .LBB3_4: # %branch_2 +; CHECK-NEXT: j .LBB3_4 +; CHECK-NEXT: .LBB3_3: # %branch_2 ; CHECK-NEXT: lw s1, 0(sp) # 4-byte Folded Reload -; CHECK-NEXT: .LBB3_2: # %branch_2 +; CHECK-NEXT: .LBB3_4: # %branch_2 ; CHECK-NEXT: #APP ; CHECK-NEXT: # reg use ra ; CHECK-NEXT: #NO_APP @@ -414,22 +414,22 @@ define void @relax_jal_spill_32_restore_block_correspondence() { ; CHECK-NEXT: #APP ; CHECK-NEXT: li a5, 15 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: bne a4, a5, .LBB4_2 -; CHECK-NEXT: j .LBB4_1 -; CHECK-NEXT: .LBB4_8: # %dest_1 -; CHECK-NEXT: lw s1, 0(sp) # 4-byte Folded Reload +; CHECK-NEXT: bne a4, a5, .LBB4_3 +; CHECK-NEXT: j .LBB4_2 ; CHECK-NEXT: .LBB4_1: # %dest_1 +; CHECK-NEXT: lw s1, 0(sp) # 4-byte Folded Reload +; CHECK-NEXT: .LBB4_2: # %dest_1 ; CHECK-NEXT: #APP ; CHECK-NEXT: # dest 1 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: j .LBB4_3 -; CHECK-NEXT: .LBB4_2: # %cond_2 -; CHECK-NEXT: bne a2, a3, .LBB4_5 -; CHECK-NEXT: .LBB4_3: # %dest_2 +; CHECK-NEXT: j .LBB4_4 +; CHECK-NEXT: .LBB4_3: # %cond_2 +; CHECK-NEXT: bne a2, a3, .LBB4_6 +; CHECK-NEXT: .LBB4_4: # %dest_2 ; CHECK-NEXT: #APP ; CHECK-NEXT: # dest 2 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: .LBB4_4: # %dest_3 +; CHECK-NEXT: .LBB4_5: # %dest_3 ; CHECK-NEXT: #APP ; CHECK-NEXT: # dest 3 ; CHECK-NEXT: #NO_APP @@ -478,16 +478,16 @@ define void @relax_jal_spill_32_restore_block_correspondence() { ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret -; CHECK-NEXT: .LBB4_5: # %cond_3 +; CHECK-NEXT: .LBB4_6: # %cond_3 ; CHECK-NEXT: .cfi_restore_state -; CHECK-NEXT: beq t1, t2, .LBB4_4 -; CHECK-NEXT: # %bb.6: # %space +; CHECK-NEXT: beq t1, t2, .LBB4_5 +; CHECK-NEXT: # %bb.7: # %space ; CHECK-NEXT: #APP ; CHECK-NEXT: .zero 1048576 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: # %bb.7: # %space +; CHECK-NEXT: # %bb.8: # %space ; CHECK-NEXT: sw s1, 0(sp) # 4-byte Folded Spill -; CHECK-NEXT: jump .LBB4_8, s1 +; CHECK-NEXT: jump .LBB4_1, s1 entry: %ra = call i32 asm sideeffect "addi ra, x0, 1", "={ra}"() %t0 = call i32 asm sideeffect "addi t0, x0, 5", "={t0}"() diff --git a/llvm/test/CodeGen/RISCV/branch-relaxation-rv64.ll b/llvm/test/CodeGen/RISCV/branch-relaxation-rv64.ll index c54ed1b06b1c8..d2ca8616a187e 100644 --- a/llvm/test/CodeGen/RISCV/branch-relaxation-rv64.ll +++ b/llvm/test/CodeGen/RISCV/branch-relaxation-rv64.ll @@ -50,20 +50,20 @@ define i32 @relax_jal(i1 %a) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: andi a0, a0, 1 -; CHECK-NEXT: bnez a0, .LBB1_1 -; CHECK-NEXT: # %bb.4: -; CHECK-NEXT: jump .LBB1_2, a0 -; CHECK-NEXT: .LBB1_1: # %iftrue +; CHECK-NEXT: bnez a0, .LBB1_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: jump .LBB1_3, a0 +; CHECK-NEXT: .LBB1_2: # %iftrue ; CHECK-NEXT: #APP ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #APP ; CHECK-NEXT: .zero 1048576 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: j .LBB1_3 -; CHECK-NEXT: .LBB1_2: # %jmp +; CHECK-NEXT: j .LBB1_4 +; CHECK-NEXT: .LBB1_3: # %jmp ; CHECK-NEXT: #APP ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: .LBB1_3: # %tail +; CHECK-NEXT: .LBB1_4: # %tail ; CHECK-NEXT: li a0, 1 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret @@ -73,20 +73,20 @@ define i32 @relax_jal(i1 %a) nounwind { ; CHECK-ZICFILP-NEXT: lpad 0 ; CHECK-ZICFILP-NEXT: addi sp, sp, -16 ; CHECK-ZICFILP-NEXT: andi a0, a0, 1 -; CHECK-ZICFILP-NEXT: bnez a0, .LBB1_1 -; CHECK-ZICFILP-NEXT: # %bb.4: -; CHECK-ZICFILP-NEXT: jump .LBB1_2, t2 -; CHECK-ZICFILP-NEXT: .LBB1_1: # %iftrue +; CHECK-ZICFILP-NEXT: bnez a0, .LBB1_2 +; CHECK-ZICFILP-NEXT: # %bb.1: +; CHECK-ZICFILP-NEXT: jump .LBB1_3, t2 +; CHECK-ZICFILP-NEXT: .LBB1_2: # %iftrue ; CHECK-ZICFILP-NEXT: #APP ; CHECK-ZICFILP-NEXT: #NO_APP ; CHECK-ZICFILP-NEXT: #APP ; CHECK-ZICFILP-NEXT: .zero 1048576 ; CHECK-ZICFILP-NEXT: #NO_APP -; CHECK-ZICFILP-NEXT: j .LBB1_3 -; CHECK-ZICFILP-NEXT: .LBB1_2: # %jmp +; CHECK-ZICFILP-NEXT: j .LBB1_4 +; CHECK-ZICFILP-NEXT: .LBB1_3: # %jmp ; CHECK-ZICFILP-NEXT: #APP ; CHECK-ZICFILP-NEXT: #NO_APP -; CHECK-ZICFILP-NEXT: .LBB1_3: # %tail +; CHECK-ZICFILP-NEXT: .LBB1_4: # %tail ; CHECK-ZICFILP-NEXT: li a0, 1 ; CHECK-ZICFILP-NEXT: addi sp, sp, 16 ; CHECK-ZICFILP-NEXT: ret @@ -225,18 +225,18 @@ define void @relax_jal_spill_64() { ; CHECK-NEXT: #APP ; CHECK-NEXT: li t6, 31 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: beq t5, t6, .LBB2_1 -; CHECK-NEXT: # %bb.3: +; CHECK-NEXT: beq t5, t6, .LBB2_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: sd s11, 0(sp) # 8-byte Folded Spill -; CHECK-NEXT: jump .LBB2_4, s11 -; CHECK-NEXT: .LBB2_1: # %branch_1 +; CHECK-NEXT: jump .LBB2_3, s11 +; CHECK-NEXT: .LBB2_2: # %branch_1 ; CHECK-NEXT: #APP ; CHECK-NEXT: .zero 1048576 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: j .LBB2_2 -; CHECK-NEXT: .LBB2_4: # %branch_2 +; CHECK-NEXT: j .LBB2_4 +; CHECK-NEXT: .LBB2_3: # %branch_2 ; CHECK-NEXT: ld s11, 0(sp) # 8-byte Folded Reload -; CHECK-NEXT: .LBB2_2: # %branch_2 +; CHECK-NEXT: .LBB2_4: # %branch_2 ; CHECK-NEXT: #APP ; CHECK-NEXT: # reg use ra ; CHECK-NEXT: #NO_APP @@ -466,18 +466,18 @@ define void @relax_jal_spill_64() { ; CHECK-ZICFILP-NEXT: #APP ; CHECK-ZICFILP-NEXT: li t6, 31 ; CHECK-ZICFILP-NEXT: #NO_APP -; CHECK-ZICFILP-NEXT: beq t5, t6, .LBB2_1 -; CHECK-ZICFILP-NEXT: # %bb.3: +; CHECK-ZICFILP-NEXT: beq t5, t6, .LBB2_2 +; CHECK-ZICFILP-NEXT: # %bb.1: ; CHECK-ZICFILP-NEXT: sd t2, 0(sp) # 8-byte Folded Spill -; CHECK-ZICFILP-NEXT: jump .LBB2_4, t2 -; CHECK-ZICFILP-NEXT: .LBB2_1: # %branch_1 +; CHECK-ZICFILP-NEXT: jump .LBB2_3, t2 +; CHECK-ZICFILP-NEXT: .LBB2_2: # %branch_1 ; CHECK-ZICFILP-NEXT: #APP ; CHECK-ZICFILP-NEXT: .zero 1048576 ; CHECK-ZICFILP-NEXT: #NO_APP -; CHECK-ZICFILP-NEXT: j .LBB2_2 -; CHECK-ZICFILP-NEXT: .LBB2_4: # %branch_2 +; CHECK-ZICFILP-NEXT: j .LBB2_4 +; CHECK-ZICFILP-NEXT: .LBB2_3: # %branch_2 ; CHECK-ZICFILP-NEXT: ld t2, 0(sp) # 8-byte Folded Reload -; CHECK-ZICFILP-NEXT: .LBB2_2: # %branch_2 +; CHECK-ZICFILP-NEXT: .LBB2_4: # %branch_2 ; CHECK-ZICFILP-NEXT: #APP ; CHECK-ZICFILP-NEXT: # reg use ra ; CHECK-ZICFILP-NEXT: #NO_APP @@ -786,18 +786,18 @@ define void @relax_jal_spill_64_adjust_spill_slot() { ; CHECK-NEXT: #APP ; CHECK-NEXT: li t6, 31 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: beq t5, t6, .LBB3_1 -; CHECK-NEXT: # %bb.3: +; CHECK-NEXT: beq t5, t6, .LBB3_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: sd s11, 0(sp) # 8-byte Folded Spill -; CHECK-NEXT: jump .LBB3_4, s11 -; CHECK-NEXT: .LBB3_1: # %branch_1 +; CHECK-NEXT: jump .LBB3_3, s11 +; CHECK-NEXT: .LBB3_2: # %branch_1 ; CHECK-NEXT: #APP ; CHECK-NEXT: .zero 1048576 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: j .LBB3_2 -; CHECK-NEXT: .LBB3_4: # %branch_2 +; CHECK-NEXT: j .LBB3_4 +; CHECK-NEXT: .LBB3_3: # %branch_2 ; CHECK-NEXT: ld s11, 0(sp) # 8-byte Folded Reload -; CHECK-NEXT: .LBB3_2: # %branch_2 +; CHECK-NEXT: .LBB3_4: # %branch_2 ; CHECK-NEXT: #APP ; CHECK-NEXT: # reg use ra ; CHECK-NEXT: #NO_APP @@ -1036,18 +1036,18 @@ define void @relax_jal_spill_64_adjust_spill_slot() { ; CHECK-ZICFILP-NEXT: #APP ; CHECK-ZICFILP-NEXT: li t6, 31 ; CHECK-ZICFILP-NEXT: #NO_APP -; CHECK-ZICFILP-NEXT: beq t5, t6, .LBB3_1 -; CHECK-ZICFILP-NEXT: # %bb.3: +; CHECK-ZICFILP-NEXT: beq t5, t6, .LBB3_2 +; CHECK-ZICFILP-NEXT: # %bb.1: ; CHECK-ZICFILP-NEXT: sd t2, 0(sp) # 8-byte Folded Spill -; CHECK-ZICFILP-NEXT: jump .LBB3_4, t2 -; CHECK-ZICFILP-NEXT: .LBB3_1: # %branch_1 +; CHECK-ZICFILP-NEXT: jump .LBB3_3, t2 +; CHECK-ZICFILP-NEXT: .LBB3_2: # %branch_1 ; CHECK-ZICFILP-NEXT: #APP ; CHECK-ZICFILP-NEXT: .zero 1048576 ; CHECK-ZICFILP-NEXT: #NO_APP -; CHECK-ZICFILP-NEXT: j .LBB3_2 -; CHECK-ZICFILP-NEXT: .LBB3_4: # %branch_2 +; CHECK-ZICFILP-NEXT: j .LBB3_4 +; CHECK-ZICFILP-NEXT: .LBB3_3: # %branch_2 ; CHECK-ZICFILP-NEXT: ld t2, 0(sp) # 8-byte Folded Reload -; CHECK-ZICFILP-NEXT: .LBB3_2: # %branch_2 +; CHECK-ZICFILP-NEXT: .LBB3_4: # %branch_2 ; CHECK-ZICFILP-NEXT: #APP ; CHECK-ZICFILP-NEXT: # reg use ra ; CHECK-ZICFILP-NEXT: #NO_APP @@ -1351,22 +1351,22 @@ define void @relax_jal_spill_64_restore_block_correspondence() { ; CHECK-NEXT: #APP ; CHECK-NEXT: li t6, 31 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: bne t5, t6, .LBB4_2 -; CHECK-NEXT: j .LBB4_1 -; CHECK-NEXT: .LBB4_8: # %dest_1 -; CHECK-NEXT: ld s11, 0(sp) # 8-byte Folded Reload +; CHECK-NEXT: bne t5, t6, .LBB4_3 +; CHECK-NEXT: j .LBB4_2 ; CHECK-NEXT: .LBB4_1: # %dest_1 +; CHECK-NEXT: ld s11, 0(sp) # 8-byte Folded Reload +; CHECK-NEXT: .LBB4_2: # %dest_1 ; CHECK-NEXT: #APP ; CHECK-NEXT: # dest 1 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: j .LBB4_3 -; CHECK-NEXT: .LBB4_2: # %cond_2 -; CHECK-NEXT: bne t3, t4, .LBB4_5 -; CHECK-NEXT: .LBB4_3: # %dest_2 +; CHECK-NEXT: j .LBB4_4 +; CHECK-NEXT: .LBB4_3: # %cond_2 +; CHECK-NEXT: bne t3, t4, .LBB4_6 +; CHECK-NEXT: .LBB4_4: # %dest_2 ; CHECK-NEXT: #APP ; CHECK-NEXT: # dest 2 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: .LBB4_4: # %dest_3 +; CHECK-NEXT: .LBB4_5: # %dest_3 ; CHECK-NEXT: #APP ; CHECK-NEXT: # dest 3 ; CHECK-NEXT: #NO_APP @@ -1483,16 +1483,16 @@ define void @relax_jal_spill_64_restore_block_correspondence() { ; CHECK-NEXT: addi sp, sp, 112 ; CHECK-NEXT: .cfi_def_cfa_offset 0 ; CHECK-NEXT: ret -; CHECK-NEXT: .LBB4_5: # %cond_3 +; CHECK-NEXT: .LBB4_6: # %cond_3 ; CHECK-NEXT: .cfi_restore_state -; CHECK-NEXT: beq t1, t2, .LBB4_4 -; CHECK-NEXT: # %bb.6: # %space +; CHECK-NEXT: beq t1, t2, .LBB4_5 +; CHECK-NEXT: # %bb.7: # %space ; CHECK-NEXT: #APP ; CHECK-NEXT: .zero 1048576 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: # %bb.7: # %space +; CHECK-NEXT: # %bb.8: # %space ; CHECK-NEXT: sd s11, 0(sp) # 8-byte Folded Spill -; CHECK-NEXT: jump .LBB4_8, s11 +; CHECK-NEXT: jump .LBB4_1, s11 ; ; CHECK-ZICFILP-LABEL: relax_jal_spill_64_restore_block_correspondence: ; CHECK-ZICFILP: # %bb.0: # %entry @@ -1610,22 +1610,22 @@ define void @relax_jal_spill_64_restore_block_correspondence() { ; CHECK-ZICFILP-NEXT: #APP ; CHECK-ZICFILP-NEXT: li t6, 31 ; CHECK-ZICFILP-NEXT: #NO_APP -; CHECK-ZICFILP-NEXT: bne t5, t6, .LBB4_2 -; CHECK-ZICFILP-NEXT: j .LBB4_1 -; CHECK-ZICFILP-NEXT: .LBB4_8: # %dest_1 -; CHECK-ZICFILP-NEXT: ld t2, 0(sp) # 8-byte Folded Reload +; CHECK-ZICFILP-NEXT: bne t5, t6, .LBB4_3 +; CHECK-ZICFILP-NEXT: j .LBB4_2 ; CHECK-ZICFILP-NEXT: .LBB4_1: # %dest_1 +; CHECK-ZICFILP-NEXT: ld t2, 0(sp) # 8-byte Folded Reload +; CHECK-ZICFILP-NEXT: .LBB4_2: # %dest_1 ; CHECK-ZICFILP-NEXT: #APP ; CHECK-ZICFILP-NEXT: # dest 1 ; CHECK-ZICFILP-NEXT: #NO_APP -; CHECK-ZICFILP-NEXT: j .LBB4_3 -; CHECK-ZICFILP-NEXT: .LBB4_2: # %cond_2 -; CHECK-ZICFILP-NEXT: bne t3, t4, .LBB4_5 -; CHECK-ZICFILP-NEXT: .LBB4_3: # %dest_2 +; CHECK-ZICFILP-NEXT: j .LBB4_4 +; CHECK-ZICFILP-NEXT: .LBB4_3: # %cond_2 +; CHECK-ZICFILP-NEXT: bne t3, t4, .LBB4_6 +; CHECK-ZICFILP-NEXT: .LBB4_4: # %dest_2 ; CHECK-ZICFILP-NEXT: #APP ; CHECK-ZICFILP-NEXT: # dest 2 ; CHECK-ZICFILP-NEXT: #NO_APP -; CHECK-ZICFILP-NEXT: .LBB4_4: # %dest_3 +; CHECK-ZICFILP-NEXT: .LBB4_5: # %dest_3 ; CHECK-ZICFILP-NEXT: #APP ; CHECK-ZICFILP-NEXT: # dest 3 ; CHECK-ZICFILP-NEXT: #NO_APP @@ -1742,16 +1742,16 @@ define void @relax_jal_spill_64_restore_block_correspondence() { ; CHECK-ZICFILP-NEXT: addi sp, sp, 112 ; CHECK-ZICFILP-NEXT: .cfi_def_cfa_offset 0 ; CHECK-ZICFILP-NEXT: ret -; CHECK-ZICFILP-NEXT: .LBB4_5: # %cond_3 +; CHECK-ZICFILP-NEXT: .LBB4_6: # %cond_3 ; CHECK-ZICFILP-NEXT: .cfi_restore_state -; CHECK-ZICFILP-NEXT: beq t1, t2, .LBB4_4 -; CHECK-ZICFILP-NEXT: # %bb.6: # %space +; CHECK-ZICFILP-NEXT: beq t1, t2, .LBB4_5 +; CHECK-ZICFILP-NEXT: # %bb.7: # %space ; CHECK-ZICFILP-NEXT: #APP ; CHECK-ZICFILP-NEXT: .zero 1048576 ; CHECK-ZICFILP-NEXT: #NO_APP -; CHECK-ZICFILP-NEXT: # %bb.7: # %space +; CHECK-ZICFILP-NEXT: # %bb.8: # %space ; CHECK-ZICFILP-NEXT: sd t2, 0(sp) # 8-byte Folded Spill -; CHECK-ZICFILP-NEXT: jump .LBB4_8, t2 +; CHECK-ZICFILP-NEXT: jump .LBB4_1, t2 entry: %ra = call i64 asm sideeffect "addi ra, x0, 1", "={ra}"() %t0 = call i64 asm sideeffect "addi t0, x0, 5", "={t0}"() diff --git a/llvm/test/CodeGen/RISCV/pr65025.ll b/llvm/test/CodeGen/RISCV/pr65025.ll index 4eb6a478bbbcd..32ddd48e9784a 100644 --- a/llvm/test/CodeGen/RISCV/pr65025.ll +++ b/llvm/test/CodeGen/RISCV/pr65025.ll @@ -12,28 +12,28 @@ define ptr @cmpxchg_masked_and_branch1(ptr %ptr, i8 signext %cmp, i8 signext %va ; CHECK-NEXT: sllw a5, a5, a4 ; CHECK-NEXT: sllw a1, a1, a4 ; CHECK-NEXT: sllw a2, a2, a4 -; CHECK-NEXT: .LBB0_3: # %do_cmpxchg +; CHECK-NEXT: .LBB0_1: # %do_cmpxchg ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: lr.w.aqrl a4, (a3) ; CHECK-NEXT: and a6, a4, a5 -; CHECK-NEXT: bne a6, a1, .LBB0_5 -; CHECK-NEXT: # %bb.4: # %do_cmpxchg -; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1 +; CHECK-NEXT: bne a6, a1, .LBB0_3 +; CHECK-NEXT: # %bb.2: # %do_cmpxchg +; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: xor a6, a4, a2 ; CHECK-NEXT: and a6, a6, a5 ; CHECK-NEXT: xor a6, a4, a6 ; CHECK-NEXT: sc.w.rl a6, a6, (a3) -; CHECK-NEXT: bnez a6, .LBB0_3 -; CHECK-NEXT: .LBB0_5: # %do_cmpxchg +; CHECK-NEXT: bnez a6, .LBB0_1 +; CHECK-NEXT: .LBB0_3: # %do_cmpxchg ; CHECK-NEXT: and a2, a4, a5 -; CHECK-NEXT: bne a1, a2, .LBB0_2 -; CHECK-NEXT: # %bb.1: # %returnptr +; CHECK-NEXT: bne a1, a2, .LBB0_5 +; CHECK-NEXT: # %bb.4: # %returnptr ; CHECK-NEXT: xor a1, a1, a2 ; CHECK-NEXT: snez a1, a1 ; CHECK-NEXT: addi a1, a1, -1 ; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: ret -; CHECK-NEXT: .LBB0_2: # %exit +; CHECK-NEXT: .LBB0_5: # %exit ; CHECK-NEXT: li a0, 0 ; CHECK-NEXT: ret do_cmpxchg: diff --git a/llvm/test/CodeGen/RISCV/rvv/expandload.ll b/llvm/test/CodeGen/RISCV/rvv/expandload.ll index cc1282a9119da..b8e7c82981198 100644 --- a/llvm/test/CodeGen/RISCV/rvv/expandload.ll +++ b/llvm/test/CodeGen/RISCV/rvv/expandload.ll @@ -1681,123 +1681,123 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-RV32-NEXT: vmv.x.s a2, v24 ; CHECK-RV32-NEXT: bgez a3, .LBB61_35 -; CHECK-RV32-NEXT: j .LBB61_572 +; CHECK-RV32-NEXT: j .LBB61_573 ; CHECK-RV32-NEXT: .LBB61_35: # %else122 ; CHECK-RV32-NEXT: andi a3, a2, 1 ; CHECK-RV32-NEXT: beqz a3, .LBB61_36 -; CHECK-RV32-NEXT: j .LBB61_573 +; CHECK-RV32-NEXT: j .LBB61_574 ; CHECK-RV32-NEXT: .LBB61_36: # %else126 ; CHECK-RV32-NEXT: andi a3, a2, 2 ; CHECK-RV32-NEXT: beqz a3, .LBB61_37 -; CHECK-RV32-NEXT: j .LBB61_574 +; CHECK-RV32-NEXT: j .LBB61_575 ; CHECK-RV32-NEXT: .LBB61_37: # %else130 ; CHECK-RV32-NEXT: andi a3, a2, 4 ; CHECK-RV32-NEXT: beqz a3, .LBB61_38 -; CHECK-RV32-NEXT: j .LBB61_575 +; CHECK-RV32-NEXT: j .LBB61_576 ; CHECK-RV32-NEXT: .LBB61_38: # %else134 ; CHECK-RV32-NEXT: andi a3, a2, 8 ; CHECK-RV32-NEXT: beqz a3, .LBB61_39 -; CHECK-RV32-NEXT: j .LBB61_576 +; CHECK-RV32-NEXT: j .LBB61_577 ; CHECK-RV32-NEXT: .LBB61_39: # %else138 ; CHECK-RV32-NEXT: andi a3, a2, 16 ; CHECK-RV32-NEXT: beqz a3, .LBB61_40 -; CHECK-RV32-NEXT: j .LBB61_577 +; CHECK-RV32-NEXT: j .LBB61_578 ; CHECK-RV32-NEXT: .LBB61_40: # %else142 ; CHECK-RV32-NEXT: andi a3, a2, 32 ; CHECK-RV32-NEXT: beqz a3, .LBB61_41 -; CHECK-RV32-NEXT: j .LBB61_578 +; CHECK-RV32-NEXT: j .LBB61_579 ; CHECK-RV32-NEXT: .LBB61_41: # %else146 ; CHECK-RV32-NEXT: andi a3, a2, 64 ; CHECK-RV32-NEXT: beqz a3, .LBB61_42 -; CHECK-RV32-NEXT: j .LBB61_579 +; CHECK-RV32-NEXT: j .LBB61_580 ; CHECK-RV32-NEXT: .LBB61_42: # %else150 ; CHECK-RV32-NEXT: andi a3, a2, 128 ; CHECK-RV32-NEXT: beqz a3, .LBB61_43 -; CHECK-RV32-NEXT: j .LBB61_580 +; CHECK-RV32-NEXT: j .LBB61_581 ; CHECK-RV32-NEXT: .LBB61_43: # %else154 ; CHECK-RV32-NEXT: andi a3, a2, 256 ; CHECK-RV32-NEXT: beqz a3, .LBB61_44 -; CHECK-RV32-NEXT: j .LBB61_581 +; CHECK-RV32-NEXT: j .LBB61_582 ; CHECK-RV32-NEXT: .LBB61_44: # %else158 ; CHECK-RV32-NEXT: andi a3, a2, 512 ; CHECK-RV32-NEXT: beqz a3, .LBB61_45 -; CHECK-RV32-NEXT: j .LBB61_582 +; CHECK-RV32-NEXT: j .LBB61_583 ; CHECK-RV32-NEXT: .LBB61_45: # %else162 ; CHECK-RV32-NEXT: andi a3, a2, 1024 ; CHECK-RV32-NEXT: beqz a3, .LBB61_46 -; CHECK-RV32-NEXT: j .LBB61_583 +; CHECK-RV32-NEXT: j .LBB61_584 ; CHECK-RV32-NEXT: .LBB61_46: # %else166 ; CHECK-RV32-NEXT: slli a3, a2, 20 ; CHECK-RV32-NEXT: bgez a3, .LBB61_47 -; CHECK-RV32-NEXT: j .LBB61_584 +; CHECK-RV32-NEXT: j .LBB61_585 ; CHECK-RV32-NEXT: .LBB61_47: # %else170 ; CHECK-RV32-NEXT: slli a3, a2, 19 ; CHECK-RV32-NEXT: bgez a3, .LBB61_48 -; CHECK-RV32-NEXT: j .LBB61_585 +; CHECK-RV32-NEXT: j .LBB61_586 ; CHECK-RV32-NEXT: .LBB61_48: # %else174 ; CHECK-RV32-NEXT: slli a3, a2, 18 ; CHECK-RV32-NEXT: bgez a3, .LBB61_49 -; CHECK-RV32-NEXT: j .LBB61_586 +; CHECK-RV32-NEXT: j .LBB61_587 ; CHECK-RV32-NEXT: .LBB61_49: # %else178 ; CHECK-RV32-NEXT: slli a3, a2, 17 ; CHECK-RV32-NEXT: bgez a3, .LBB61_50 -; CHECK-RV32-NEXT: j .LBB61_587 +; CHECK-RV32-NEXT: j .LBB61_588 ; CHECK-RV32-NEXT: .LBB61_50: # %else182 ; CHECK-RV32-NEXT: slli a3, a2, 16 ; CHECK-RV32-NEXT: bgez a3, .LBB61_51 -; CHECK-RV32-NEXT: j .LBB61_588 +; CHECK-RV32-NEXT: j .LBB61_589 ; CHECK-RV32-NEXT: .LBB61_51: # %else186 ; CHECK-RV32-NEXT: slli a3, a2, 15 ; CHECK-RV32-NEXT: bgez a3, .LBB61_52 -; CHECK-RV32-NEXT: j .LBB61_589 +; CHECK-RV32-NEXT: j .LBB61_590 ; CHECK-RV32-NEXT: .LBB61_52: # %else190 ; CHECK-RV32-NEXT: slli a3, a2, 14 ; CHECK-RV32-NEXT: bgez a3, .LBB61_53 -; CHECK-RV32-NEXT: j .LBB61_590 +; CHECK-RV32-NEXT: j .LBB61_591 ; CHECK-RV32-NEXT: .LBB61_53: # %else194 ; CHECK-RV32-NEXT: slli a3, a2, 13 ; CHECK-RV32-NEXT: bgez a3, .LBB61_54 -; CHECK-RV32-NEXT: j .LBB61_591 +; CHECK-RV32-NEXT: j .LBB61_592 ; CHECK-RV32-NEXT: .LBB61_54: # %else198 ; CHECK-RV32-NEXT: slli a3, a2, 12 ; CHECK-RV32-NEXT: bgez a3, .LBB61_55 -; CHECK-RV32-NEXT: j .LBB61_592 +; CHECK-RV32-NEXT: j .LBB61_593 ; CHECK-RV32-NEXT: .LBB61_55: # %else202 ; CHECK-RV32-NEXT: slli a3, a2, 11 ; CHECK-RV32-NEXT: bgez a3, .LBB61_56 -; CHECK-RV32-NEXT: j .LBB61_593 +; CHECK-RV32-NEXT: j .LBB61_594 ; CHECK-RV32-NEXT: .LBB61_56: # %else206 ; CHECK-RV32-NEXT: slli a3, a2, 10 ; CHECK-RV32-NEXT: bgez a3, .LBB61_57 -; CHECK-RV32-NEXT: j .LBB61_594 +; CHECK-RV32-NEXT: j .LBB61_595 ; CHECK-RV32-NEXT: .LBB61_57: # %else210 ; CHECK-RV32-NEXT: slli a3, a2, 9 ; CHECK-RV32-NEXT: bgez a3, .LBB61_58 -; CHECK-RV32-NEXT: j .LBB61_595 +; CHECK-RV32-NEXT: j .LBB61_596 ; CHECK-RV32-NEXT: .LBB61_58: # %else214 ; CHECK-RV32-NEXT: slli a3, a2, 8 ; CHECK-RV32-NEXT: bgez a3, .LBB61_59 -; CHECK-RV32-NEXT: j .LBB61_596 +; CHECK-RV32-NEXT: j .LBB61_597 ; CHECK-RV32-NEXT: .LBB61_59: # %else218 ; CHECK-RV32-NEXT: slli a3, a2, 7 ; CHECK-RV32-NEXT: bgez a3, .LBB61_60 -; CHECK-RV32-NEXT: j .LBB61_597 +; CHECK-RV32-NEXT: j .LBB61_598 ; CHECK-RV32-NEXT: .LBB61_60: # %else222 ; CHECK-RV32-NEXT: slli a3, a2, 6 ; CHECK-RV32-NEXT: bgez a3, .LBB61_61 -; CHECK-RV32-NEXT: j .LBB61_598 +; CHECK-RV32-NEXT: j .LBB61_599 ; CHECK-RV32-NEXT: .LBB61_61: # %else226 ; CHECK-RV32-NEXT: slli a3, a2, 5 ; CHECK-RV32-NEXT: bgez a3, .LBB61_62 -; CHECK-RV32-NEXT: j .LBB61_599 +; CHECK-RV32-NEXT: j .LBB61_600 ; CHECK-RV32-NEXT: .LBB61_62: # %else230 ; CHECK-RV32-NEXT: slli a3, a2, 4 ; CHECK-RV32-NEXT: bgez a3, .LBB61_63 -; CHECK-RV32-NEXT: j .LBB61_600 +; CHECK-RV32-NEXT: j .LBB61_601 ; CHECK-RV32-NEXT: .LBB61_63: # %else234 ; CHECK-RV32-NEXT: slli a3, a2, 3 ; CHECK-RV32-NEXT: bgez a3, .LBB61_64 -; CHECK-RV32-NEXT: j .LBB61_601 +; CHECK-RV32-NEXT: j .LBB61_602 ; CHECK-RV32-NEXT: .LBB61_64: # %else238 ; CHECK-RV32-NEXT: slli a3, a2, 2 ; CHECK-RV32-NEXT: bgez a3, .LBB61_66 @@ -1833,123 +1833,123 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-RV32-NEXT: vmv.x.s a3, v24 ; CHECK-RV32-NEXT: bgez a2, .LBB61_69 -; CHECK-RV32-NEXT: j .LBB61_602 +; CHECK-RV32-NEXT: j .LBB61_604 ; CHECK-RV32-NEXT: .LBB61_69: # %else250 ; CHECK-RV32-NEXT: andi a2, a3, 1 ; CHECK-RV32-NEXT: beqz a2, .LBB61_70 -; CHECK-RV32-NEXT: j .LBB61_603 +; CHECK-RV32-NEXT: j .LBB61_605 ; CHECK-RV32-NEXT: .LBB61_70: # %else254 ; CHECK-RV32-NEXT: andi a2, a3, 2 ; CHECK-RV32-NEXT: beqz a2, .LBB61_71 -; CHECK-RV32-NEXT: j .LBB61_604 +; CHECK-RV32-NEXT: j .LBB61_606 ; CHECK-RV32-NEXT: .LBB61_71: # %else258 ; CHECK-RV32-NEXT: andi a2, a3, 4 ; CHECK-RV32-NEXT: beqz a2, .LBB61_72 -; CHECK-RV32-NEXT: j .LBB61_605 +; CHECK-RV32-NEXT: j .LBB61_607 ; CHECK-RV32-NEXT: .LBB61_72: # %else262 ; CHECK-RV32-NEXT: andi a2, a3, 8 ; CHECK-RV32-NEXT: beqz a2, .LBB61_73 -; CHECK-RV32-NEXT: j .LBB61_606 +; CHECK-RV32-NEXT: j .LBB61_608 ; CHECK-RV32-NEXT: .LBB61_73: # %else266 ; CHECK-RV32-NEXT: andi a2, a3, 16 ; CHECK-RV32-NEXT: beqz a2, .LBB61_74 -; CHECK-RV32-NEXT: j .LBB61_607 +; CHECK-RV32-NEXT: j .LBB61_609 ; CHECK-RV32-NEXT: .LBB61_74: # %else270 ; CHECK-RV32-NEXT: andi a2, a3, 32 ; CHECK-RV32-NEXT: beqz a2, .LBB61_75 -; CHECK-RV32-NEXT: j .LBB61_608 +; CHECK-RV32-NEXT: j .LBB61_610 ; CHECK-RV32-NEXT: .LBB61_75: # %else274 ; CHECK-RV32-NEXT: andi a2, a3, 64 ; CHECK-RV32-NEXT: beqz a2, .LBB61_76 -; CHECK-RV32-NEXT: j .LBB61_609 +; CHECK-RV32-NEXT: j .LBB61_611 ; CHECK-RV32-NEXT: .LBB61_76: # %else278 ; CHECK-RV32-NEXT: andi a2, a3, 128 ; CHECK-RV32-NEXT: beqz a2, .LBB61_77 -; CHECK-RV32-NEXT: j .LBB61_610 +; CHECK-RV32-NEXT: j .LBB61_612 ; CHECK-RV32-NEXT: .LBB61_77: # %else282 ; CHECK-RV32-NEXT: andi a2, a3, 256 ; CHECK-RV32-NEXT: beqz a2, .LBB61_78 -; CHECK-RV32-NEXT: j .LBB61_611 +; CHECK-RV32-NEXT: j .LBB61_613 ; CHECK-RV32-NEXT: .LBB61_78: # %else286 ; CHECK-RV32-NEXT: andi a2, a3, 512 ; CHECK-RV32-NEXT: beqz a2, .LBB61_79 -; CHECK-RV32-NEXT: j .LBB61_612 +; CHECK-RV32-NEXT: j .LBB61_614 ; CHECK-RV32-NEXT: .LBB61_79: # %else290 ; CHECK-RV32-NEXT: andi a2, a3, 1024 ; CHECK-RV32-NEXT: beqz a2, .LBB61_80 -; CHECK-RV32-NEXT: j .LBB61_613 +; CHECK-RV32-NEXT: j .LBB61_615 ; CHECK-RV32-NEXT: .LBB61_80: # %else294 ; CHECK-RV32-NEXT: slli a2, a3, 20 ; CHECK-RV32-NEXT: bgez a2, .LBB61_81 -; CHECK-RV32-NEXT: j .LBB61_614 +; CHECK-RV32-NEXT: j .LBB61_616 ; CHECK-RV32-NEXT: .LBB61_81: # %else298 ; CHECK-RV32-NEXT: slli a2, a3, 19 ; CHECK-RV32-NEXT: bgez a2, .LBB61_82 -; CHECK-RV32-NEXT: j .LBB61_615 +; CHECK-RV32-NEXT: j .LBB61_617 ; CHECK-RV32-NEXT: .LBB61_82: # %else302 ; CHECK-RV32-NEXT: slli a2, a3, 18 ; CHECK-RV32-NEXT: bgez a2, .LBB61_83 -; CHECK-RV32-NEXT: j .LBB61_616 +; CHECK-RV32-NEXT: j .LBB61_618 ; CHECK-RV32-NEXT: .LBB61_83: # %else306 ; CHECK-RV32-NEXT: slli a2, a3, 17 ; CHECK-RV32-NEXT: bgez a2, .LBB61_84 -; CHECK-RV32-NEXT: j .LBB61_617 +; CHECK-RV32-NEXT: j .LBB61_619 ; CHECK-RV32-NEXT: .LBB61_84: # %else310 ; CHECK-RV32-NEXT: slli a2, a3, 16 ; CHECK-RV32-NEXT: bgez a2, .LBB61_85 -; CHECK-RV32-NEXT: j .LBB61_618 +; CHECK-RV32-NEXT: j .LBB61_620 ; CHECK-RV32-NEXT: .LBB61_85: # %else314 ; CHECK-RV32-NEXT: slli a2, a3, 15 ; CHECK-RV32-NEXT: bgez a2, .LBB61_86 -; CHECK-RV32-NEXT: j .LBB61_619 +; CHECK-RV32-NEXT: j .LBB61_621 ; CHECK-RV32-NEXT: .LBB61_86: # %else318 ; CHECK-RV32-NEXT: slli a2, a3, 14 ; CHECK-RV32-NEXT: bgez a2, .LBB61_87 -; CHECK-RV32-NEXT: j .LBB61_620 +; CHECK-RV32-NEXT: j .LBB61_622 ; CHECK-RV32-NEXT: .LBB61_87: # %else322 ; CHECK-RV32-NEXT: slli a2, a3, 13 ; CHECK-RV32-NEXT: bgez a2, .LBB61_88 -; CHECK-RV32-NEXT: j .LBB61_621 +; CHECK-RV32-NEXT: j .LBB61_623 ; CHECK-RV32-NEXT: .LBB61_88: # %else326 ; CHECK-RV32-NEXT: slli a2, a3, 12 ; CHECK-RV32-NEXT: bgez a2, .LBB61_89 -; CHECK-RV32-NEXT: j .LBB61_622 +; CHECK-RV32-NEXT: j .LBB61_624 ; CHECK-RV32-NEXT: .LBB61_89: # %else330 ; CHECK-RV32-NEXT: slli a2, a3, 11 ; CHECK-RV32-NEXT: bgez a2, .LBB61_90 -; CHECK-RV32-NEXT: j .LBB61_623 +; CHECK-RV32-NEXT: j .LBB61_625 ; CHECK-RV32-NEXT: .LBB61_90: # %else334 ; CHECK-RV32-NEXT: slli a2, a3, 10 ; CHECK-RV32-NEXT: bgez a2, .LBB61_91 -; CHECK-RV32-NEXT: j .LBB61_624 +; CHECK-RV32-NEXT: j .LBB61_626 ; CHECK-RV32-NEXT: .LBB61_91: # %else338 ; CHECK-RV32-NEXT: slli a2, a3, 9 ; CHECK-RV32-NEXT: bgez a2, .LBB61_92 -; CHECK-RV32-NEXT: j .LBB61_625 +; CHECK-RV32-NEXT: j .LBB61_627 ; CHECK-RV32-NEXT: .LBB61_92: # %else342 ; CHECK-RV32-NEXT: slli a2, a3, 8 ; CHECK-RV32-NEXT: bgez a2, .LBB61_93 -; CHECK-RV32-NEXT: j .LBB61_626 +; CHECK-RV32-NEXT: j .LBB61_628 ; CHECK-RV32-NEXT: .LBB61_93: # %else346 ; CHECK-RV32-NEXT: slli a2, a3, 7 ; CHECK-RV32-NEXT: bgez a2, .LBB61_94 -; CHECK-RV32-NEXT: j .LBB61_627 +; CHECK-RV32-NEXT: j .LBB61_629 ; CHECK-RV32-NEXT: .LBB61_94: # %else350 ; CHECK-RV32-NEXT: slli a2, a3, 6 ; CHECK-RV32-NEXT: bgez a2, .LBB61_95 -; CHECK-RV32-NEXT: j .LBB61_628 +; CHECK-RV32-NEXT: j .LBB61_630 ; CHECK-RV32-NEXT: .LBB61_95: # %else354 ; CHECK-RV32-NEXT: slli a2, a3, 5 ; CHECK-RV32-NEXT: bgez a2, .LBB61_96 -; CHECK-RV32-NEXT: j .LBB61_629 +; CHECK-RV32-NEXT: j .LBB61_631 ; CHECK-RV32-NEXT: .LBB61_96: # %else358 ; CHECK-RV32-NEXT: slli a2, a3, 4 ; CHECK-RV32-NEXT: bgez a2, .LBB61_97 -; CHECK-RV32-NEXT: j .LBB61_630 +; CHECK-RV32-NEXT: j .LBB61_632 ; CHECK-RV32-NEXT: .LBB61_97: # %else362 ; CHECK-RV32-NEXT: slli a2, a3, 3 ; CHECK-RV32-NEXT: bgez a2, .LBB61_98 -; CHECK-RV32-NEXT: j .LBB61_631 +; CHECK-RV32-NEXT: j .LBB61_633 ; CHECK-RV32-NEXT: .LBB61_98: # %else366 ; CHECK-RV32-NEXT: slli a2, a3, 2 ; CHECK-RV32-NEXT: bgez a2, .LBB61_100 @@ -1985,123 +1985,123 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-RV32-NEXT: vmv.x.s a2, v24 ; CHECK-RV32-NEXT: bgez a3, .LBB61_103 -; CHECK-RV32-NEXT: j .LBB61_632 +; CHECK-RV32-NEXT: j .LBB61_635 ; CHECK-RV32-NEXT: .LBB61_103: # %else378 ; CHECK-RV32-NEXT: andi a3, a2, 1 ; CHECK-RV32-NEXT: beqz a3, .LBB61_104 -; CHECK-RV32-NEXT: j .LBB61_633 +; CHECK-RV32-NEXT: j .LBB61_636 ; CHECK-RV32-NEXT: .LBB61_104: # %else382 ; CHECK-RV32-NEXT: andi a3, a2, 2 ; CHECK-RV32-NEXT: beqz a3, .LBB61_105 -; CHECK-RV32-NEXT: j .LBB61_634 +; CHECK-RV32-NEXT: j .LBB61_637 ; CHECK-RV32-NEXT: .LBB61_105: # %else386 ; CHECK-RV32-NEXT: andi a3, a2, 4 ; CHECK-RV32-NEXT: beqz a3, .LBB61_106 -; CHECK-RV32-NEXT: j .LBB61_635 +; CHECK-RV32-NEXT: j .LBB61_638 ; CHECK-RV32-NEXT: .LBB61_106: # %else390 ; CHECK-RV32-NEXT: andi a3, a2, 8 ; CHECK-RV32-NEXT: beqz a3, .LBB61_107 -; CHECK-RV32-NEXT: j .LBB61_636 +; CHECK-RV32-NEXT: j .LBB61_639 ; CHECK-RV32-NEXT: .LBB61_107: # %else394 ; CHECK-RV32-NEXT: andi a3, a2, 16 ; CHECK-RV32-NEXT: beqz a3, .LBB61_108 -; CHECK-RV32-NEXT: j .LBB61_637 +; CHECK-RV32-NEXT: j .LBB61_640 ; CHECK-RV32-NEXT: .LBB61_108: # %else398 ; CHECK-RV32-NEXT: andi a3, a2, 32 ; CHECK-RV32-NEXT: beqz a3, .LBB61_109 -; CHECK-RV32-NEXT: j .LBB61_638 +; CHECK-RV32-NEXT: j .LBB61_641 ; CHECK-RV32-NEXT: .LBB61_109: # %else402 ; CHECK-RV32-NEXT: andi a3, a2, 64 ; CHECK-RV32-NEXT: beqz a3, .LBB61_110 -; CHECK-RV32-NEXT: j .LBB61_639 +; CHECK-RV32-NEXT: j .LBB61_642 ; CHECK-RV32-NEXT: .LBB61_110: # %else406 ; CHECK-RV32-NEXT: andi a3, a2, 128 ; CHECK-RV32-NEXT: beqz a3, .LBB61_111 -; CHECK-RV32-NEXT: j .LBB61_640 +; CHECK-RV32-NEXT: j .LBB61_643 ; CHECK-RV32-NEXT: .LBB61_111: # %else410 ; CHECK-RV32-NEXT: andi a3, a2, 256 ; CHECK-RV32-NEXT: beqz a3, .LBB61_112 -; CHECK-RV32-NEXT: j .LBB61_641 +; CHECK-RV32-NEXT: j .LBB61_644 ; CHECK-RV32-NEXT: .LBB61_112: # %else414 ; CHECK-RV32-NEXT: andi a3, a2, 512 ; CHECK-RV32-NEXT: beqz a3, .LBB61_113 -; CHECK-RV32-NEXT: j .LBB61_642 +; CHECK-RV32-NEXT: j .LBB61_645 ; CHECK-RV32-NEXT: .LBB61_113: # %else418 ; CHECK-RV32-NEXT: andi a3, a2, 1024 ; CHECK-RV32-NEXT: beqz a3, .LBB61_114 -; CHECK-RV32-NEXT: j .LBB61_643 +; CHECK-RV32-NEXT: j .LBB61_646 ; CHECK-RV32-NEXT: .LBB61_114: # %else422 ; CHECK-RV32-NEXT: slli a3, a2, 20 ; CHECK-RV32-NEXT: bgez a3, .LBB61_115 -; CHECK-RV32-NEXT: j .LBB61_644 +; CHECK-RV32-NEXT: j .LBB61_647 ; CHECK-RV32-NEXT: .LBB61_115: # %else426 ; CHECK-RV32-NEXT: slli a3, a2, 19 ; CHECK-RV32-NEXT: bgez a3, .LBB61_116 -; CHECK-RV32-NEXT: j .LBB61_645 +; CHECK-RV32-NEXT: j .LBB61_648 ; CHECK-RV32-NEXT: .LBB61_116: # %else430 ; CHECK-RV32-NEXT: slli a3, a2, 18 ; CHECK-RV32-NEXT: bgez a3, .LBB61_117 -; CHECK-RV32-NEXT: j .LBB61_646 +; CHECK-RV32-NEXT: j .LBB61_649 ; CHECK-RV32-NEXT: .LBB61_117: # %else434 ; CHECK-RV32-NEXT: slli a3, a2, 17 ; CHECK-RV32-NEXT: bgez a3, .LBB61_118 -; CHECK-RV32-NEXT: j .LBB61_647 +; CHECK-RV32-NEXT: j .LBB61_650 ; CHECK-RV32-NEXT: .LBB61_118: # %else438 ; CHECK-RV32-NEXT: slli a3, a2, 16 ; CHECK-RV32-NEXT: bgez a3, .LBB61_119 -; CHECK-RV32-NEXT: j .LBB61_648 +; CHECK-RV32-NEXT: j .LBB61_651 ; CHECK-RV32-NEXT: .LBB61_119: # %else442 ; CHECK-RV32-NEXT: slli a3, a2, 15 ; CHECK-RV32-NEXT: bgez a3, .LBB61_120 -; CHECK-RV32-NEXT: j .LBB61_649 +; CHECK-RV32-NEXT: j .LBB61_652 ; CHECK-RV32-NEXT: .LBB61_120: # %else446 ; CHECK-RV32-NEXT: slli a3, a2, 14 ; CHECK-RV32-NEXT: bgez a3, .LBB61_121 -; CHECK-RV32-NEXT: j .LBB61_650 +; CHECK-RV32-NEXT: j .LBB61_653 ; CHECK-RV32-NEXT: .LBB61_121: # %else450 ; CHECK-RV32-NEXT: slli a3, a2, 13 ; CHECK-RV32-NEXT: bgez a3, .LBB61_122 -; CHECK-RV32-NEXT: j .LBB61_651 +; CHECK-RV32-NEXT: j .LBB61_654 ; CHECK-RV32-NEXT: .LBB61_122: # %else454 ; CHECK-RV32-NEXT: slli a3, a2, 12 ; CHECK-RV32-NEXT: bgez a3, .LBB61_123 -; CHECK-RV32-NEXT: j .LBB61_652 +; CHECK-RV32-NEXT: j .LBB61_655 ; CHECK-RV32-NEXT: .LBB61_123: # %else458 ; CHECK-RV32-NEXT: slli a3, a2, 11 ; CHECK-RV32-NEXT: bgez a3, .LBB61_124 -; CHECK-RV32-NEXT: j .LBB61_653 +; CHECK-RV32-NEXT: j .LBB61_656 ; CHECK-RV32-NEXT: .LBB61_124: # %else462 ; CHECK-RV32-NEXT: slli a3, a2, 10 ; CHECK-RV32-NEXT: bgez a3, .LBB61_125 -; CHECK-RV32-NEXT: j .LBB61_654 +; CHECK-RV32-NEXT: j .LBB61_657 ; CHECK-RV32-NEXT: .LBB61_125: # %else466 ; CHECK-RV32-NEXT: slli a3, a2, 9 ; CHECK-RV32-NEXT: bgez a3, .LBB61_126 -; CHECK-RV32-NEXT: j .LBB61_655 +; CHECK-RV32-NEXT: j .LBB61_658 ; CHECK-RV32-NEXT: .LBB61_126: # %else470 ; CHECK-RV32-NEXT: slli a3, a2, 8 ; CHECK-RV32-NEXT: bgez a3, .LBB61_127 -; CHECK-RV32-NEXT: j .LBB61_656 +; CHECK-RV32-NEXT: j .LBB61_659 ; CHECK-RV32-NEXT: .LBB61_127: # %else474 ; CHECK-RV32-NEXT: slli a3, a2, 7 ; CHECK-RV32-NEXT: bgez a3, .LBB61_128 -; CHECK-RV32-NEXT: j .LBB61_657 +; CHECK-RV32-NEXT: j .LBB61_660 ; CHECK-RV32-NEXT: .LBB61_128: # %else478 ; CHECK-RV32-NEXT: slli a3, a2, 6 ; CHECK-RV32-NEXT: bgez a3, .LBB61_129 -; CHECK-RV32-NEXT: j .LBB61_658 +; CHECK-RV32-NEXT: j .LBB61_661 ; CHECK-RV32-NEXT: .LBB61_129: # %else482 ; CHECK-RV32-NEXT: slli a3, a2, 5 ; CHECK-RV32-NEXT: bgez a3, .LBB61_130 -; CHECK-RV32-NEXT: j .LBB61_659 +; CHECK-RV32-NEXT: j .LBB61_662 ; CHECK-RV32-NEXT: .LBB61_130: # %else486 ; CHECK-RV32-NEXT: slli a3, a2, 4 ; CHECK-RV32-NEXT: bgez a3, .LBB61_131 -; CHECK-RV32-NEXT: j .LBB61_660 +; CHECK-RV32-NEXT: j .LBB61_663 ; CHECK-RV32-NEXT: .LBB61_131: # %else490 ; CHECK-RV32-NEXT: slli a3, a2, 3 ; CHECK-RV32-NEXT: bgez a3, .LBB61_132 -; CHECK-RV32-NEXT: j .LBB61_661 +; CHECK-RV32-NEXT: j .LBB61_664 ; CHECK-RV32-NEXT: .LBB61_132: # %else494 ; CHECK-RV32-NEXT: slli a3, a2, 2 ; CHECK-RV32-NEXT: bgez a3, .LBB61_134 @@ -2137,123 +2137,123 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-RV32-NEXT: vmv.x.s a3, v24 ; CHECK-RV32-NEXT: bgez a2, .LBB61_137 -; CHECK-RV32-NEXT: j .LBB61_662 +; CHECK-RV32-NEXT: j .LBB61_666 ; CHECK-RV32-NEXT: .LBB61_137: # %else506 ; CHECK-RV32-NEXT: andi a2, a3, 1 ; CHECK-RV32-NEXT: beqz a2, .LBB61_138 -; CHECK-RV32-NEXT: j .LBB61_663 +; CHECK-RV32-NEXT: j .LBB61_667 ; CHECK-RV32-NEXT: .LBB61_138: # %else510 ; CHECK-RV32-NEXT: andi a2, a3, 2 ; CHECK-RV32-NEXT: beqz a2, .LBB61_139 -; CHECK-RV32-NEXT: j .LBB61_664 +; CHECK-RV32-NEXT: j .LBB61_668 ; CHECK-RV32-NEXT: .LBB61_139: # %else514 ; CHECK-RV32-NEXT: andi a2, a3, 4 ; CHECK-RV32-NEXT: beqz a2, .LBB61_140 -; CHECK-RV32-NEXT: j .LBB61_665 +; CHECK-RV32-NEXT: j .LBB61_669 ; CHECK-RV32-NEXT: .LBB61_140: # %else518 ; CHECK-RV32-NEXT: andi a2, a3, 8 ; CHECK-RV32-NEXT: beqz a2, .LBB61_141 -; CHECK-RV32-NEXT: j .LBB61_666 +; CHECK-RV32-NEXT: j .LBB61_670 ; CHECK-RV32-NEXT: .LBB61_141: # %else522 ; CHECK-RV32-NEXT: andi a2, a3, 16 ; CHECK-RV32-NEXT: beqz a2, .LBB61_142 -; CHECK-RV32-NEXT: j .LBB61_667 +; CHECK-RV32-NEXT: j .LBB61_671 ; CHECK-RV32-NEXT: .LBB61_142: # %else526 ; CHECK-RV32-NEXT: andi a2, a3, 32 ; CHECK-RV32-NEXT: beqz a2, .LBB61_143 -; CHECK-RV32-NEXT: j .LBB61_668 +; CHECK-RV32-NEXT: j .LBB61_672 ; CHECK-RV32-NEXT: .LBB61_143: # %else530 ; CHECK-RV32-NEXT: andi a2, a3, 64 ; CHECK-RV32-NEXT: beqz a2, .LBB61_144 -; CHECK-RV32-NEXT: j .LBB61_669 +; CHECK-RV32-NEXT: j .LBB61_673 ; CHECK-RV32-NEXT: .LBB61_144: # %else534 ; CHECK-RV32-NEXT: andi a2, a3, 128 ; CHECK-RV32-NEXT: beqz a2, .LBB61_145 -; CHECK-RV32-NEXT: j .LBB61_670 +; CHECK-RV32-NEXT: j .LBB61_674 ; CHECK-RV32-NEXT: .LBB61_145: # %else538 ; CHECK-RV32-NEXT: andi a2, a3, 256 ; CHECK-RV32-NEXT: beqz a2, .LBB61_146 -; CHECK-RV32-NEXT: j .LBB61_671 +; CHECK-RV32-NEXT: j .LBB61_675 ; CHECK-RV32-NEXT: .LBB61_146: # %else542 ; CHECK-RV32-NEXT: andi a2, a3, 512 ; CHECK-RV32-NEXT: beqz a2, .LBB61_147 -; CHECK-RV32-NEXT: j .LBB61_672 +; CHECK-RV32-NEXT: j .LBB61_676 ; CHECK-RV32-NEXT: .LBB61_147: # %else546 ; CHECK-RV32-NEXT: andi a2, a3, 1024 ; CHECK-RV32-NEXT: beqz a2, .LBB61_148 -; CHECK-RV32-NEXT: j .LBB61_673 +; CHECK-RV32-NEXT: j .LBB61_677 ; CHECK-RV32-NEXT: .LBB61_148: # %else550 ; CHECK-RV32-NEXT: slli a2, a3, 20 ; CHECK-RV32-NEXT: bgez a2, .LBB61_149 -; CHECK-RV32-NEXT: j .LBB61_674 +; CHECK-RV32-NEXT: j .LBB61_678 ; CHECK-RV32-NEXT: .LBB61_149: # %else554 ; CHECK-RV32-NEXT: slli a2, a3, 19 ; CHECK-RV32-NEXT: bgez a2, .LBB61_150 -; CHECK-RV32-NEXT: j .LBB61_675 +; CHECK-RV32-NEXT: j .LBB61_679 ; CHECK-RV32-NEXT: .LBB61_150: # %else558 ; CHECK-RV32-NEXT: slli a2, a3, 18 ; CHECK-RV32-NEXT: bgez a2, .LBB61_151 -; CHECK-RV32-NEXT: j .LBB61_676 +; CHECK-RV32-NEXT: j .LBB61_680 ; CHECK-RV32-NEXT: .LBB61_151: # %else562 ; CHECK-RV32-NEXT: slli a2, a3, 17 ; CHECK-RV32-NEXT: bgez a2, .LBB61_152 -; CHECK-RV32-NEXT: j .LBB61_677 +; CHECK-RV32-NEXT: j .LBB61_681 ; CHECK-RV32-NEXT: .LBB61_152: # %else566 ; CHECK-RV32-NEXT: slli a2, a3, 16 ; CHECK-RV32-NEXT: bgez a2, .LBB61_153 -; CHECK-RV32-NEXT: j .LBB61_678 +; CHECK-RV32-NEXT: j .LBB61_682 ; CHECK-RV32-NEXT: .LBB61_153: # %else570 ; CHECK-RV32-NEXT: slli a2, a3, 15 ; CHECK-RV32-NEXT: bgez a2, .LBB61_154 -; CHECK-RV32-NEXT: j .LBB61_679 +; CHECK-RV32-NEXT: j .LBB61_683 ; CHECK-RV32-NEXT: .LBB61_154: # %else574 ; CHECK-RV32-NEXT: slli a2, a3, 14 ; CHECK-RV32-NEXT: bgez a2, .LBB61_155 -; CHECK-RV32-NEXT: j .LBB61_680 +; CHECK-RV32-NEXT: j .LBB61_684 ; CHECK-RV32-NEXT: .LBB61_155: # %else578 ; CHECK-RV32-NEXT: slli a2, a3, 13 ; CHECK-RV32-NEXT: bgez a2, .LBB61_156 -; CHECK-RV32-NEXT: j .LBB61_681 +; CHECK-RV32-NEXT: j .LBB61_685 ; CHECK-RV32-NEXT: .LBB61_156: # %else582 ; CHECK-RV32-NEXT: slli a2, a3, 12 ; CHECK-RV32-NEXT: bgez a2, .LBB61_157 -; CHECK-RV32-NEXT: j .LBB61_682 +; CHECK-RV32-NEXT: j .LBB61_686 ; CHECK-RV32-NEXT: .LBB61_157: # %else586 ; CHECK-RV32-NEXT: slli a2, a3, 11 ; CHECK-RV32-NEXT: bgez a2, .LBB61_158 -; CHECK-RV32-NEXT: j .LBB61_683 +; CHECK-RV32-NEXT: j .LBB61_687 ; CHECK-RV32-NEXT: .LBB61_158: # %else590 ; CHECK-RV32-NEXT: slli a2, a3, 10 ; CHECK-RV32-NEXT: bgez a2, .LBB61_159 -; CHECK-RV32-NEXT: j .LBB61_684 +; CHECK-RV32-NEXT: j .LBB61_688 ; CHECK-RV32-NEXT: .LBB61_159: # %else594 ; CHECK-RV32-NEXT: slli a2, a3, 9 ; CHECK-RV32-NEXT: bgez a2, .LBB61_160 -; CHECK-RV32-NEXT: j .LBB61_685 +; CHECK-RV32-NEXT: j .LBB61_689 ; CHECK-RV32-NEXT: .LBB61_160: # %else598 ; CHECK-RV32-NEXT: slli a2, a3, 8 ; CHECK-RV32-NEXT: bgez a2, .LBB61_161 -; CHECK-RV32-NEXT: j .LBB61_686 +; CHECK-RV32-NEXT: j .LBB61_690 ; CHECK-RV32-NEXT: .LBB61_161: # %else602 ; CHECK-RV32-NEXT: slli a2, a3, 7 ; CHECK-RV32-NEXT: bgez a2, .LBB61_162 -; CHECK-RV32-NEXT: j .LBB61_687 +; CHECK-RV32-NEXT: j .LBB61_691 ; CHECK-RV32-NEXT: .LBB61_162: # %else606 ; CHECK-RV32-NEXT: slli a2, a3, 6 ; CHECK-RV32-NEXT: bgez a2, .LBB61_163 -; CHECK-RV32-NEXT: j .LBB61_688 +; CHECK-RV32-NEXT: j .LBB61_692 ; CHECK-RV32-NEXT: .LBB61_163: # %else610 ; CHECK-RV32-NEXT: slli a2, a3, 5 ; CHECK-RV32-NEXT: bgez a2, .LBB61_164 -; CHECK-RV32-NEXT: j .LBB61_689 +; CHECK-RV32-NEXT: j .LBB61_693 ; CHECK-RV32-NEXT: .LBB61_164: # %else614 ; CHECK-RV32-NEXT: slli a2, a3, 4 ; CHECK-RV32-NEXT: bgez a2, .LBB61_165 -; CHECK-RV32-NEXT: j .LBB61_690 +; CHECK-RV32-NEXT: j .LBB61_694 ; CHECK-RV32-NEXT: .LBB61_165: # %else618 ; CHECK-RV32-NEXT: slli a2, a3, 3 ; CHECK-RV32-NEXT: bgez a2, .LBB61_166 -; CHECK-RV32-NEXT: j .LBB61_691 +; CHECK-RV32-NEXT: j .LBB61_695 ; CHECK-RV32-NEXT: .LBB61_166: # %else622 ; CHECK-RV32-NEXT: slli a2, a3, 2 ; CHECK-RV32-NEXT: bgez a2, .LBB61_168 @@ -2289,123 +2289,123 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-RV32-NEXT: vmv.x.s a2, v24 ; CHECK-RV32-NEXT: bgez a3, .LBB61_171 -; CHECK-RV32-NEXT: j .LBB61_692 +; CHECK-RV32-NEXT: j .LBB61_697 ; CHECK-RV32-NEXT: .LBB61_171: # %else634 ; CHECK-RV32-NEXT: andi a3, a2, 1 ; CHECK-RV32-NEXT: beqz a3, .LBB61_172 -; CHECK-RV32-NEXT: j .LBB61_693 +; CHECK-RV32-NEXT: j .LBB61_698 ; CHECK-RV32-NEXT: .LBB61_172: # %else638 ; CHECK-RV32-NEXT: andi a3, a2, 2 ; CHECK-RV32-NEXT: beqz a3, .LBB61_173 -; CHECK-RV32-NEXT: j .LBB61_694 +; CHECK-RV32-NEXT: j .LBB61_699 ; CHECK-RV32-NEXT: .LBB61_173: # %else642 ; CHECK-RV32-NEXT: andi a3, a2, 4 ; CHECK-RV32-NEXT: beqz a3, .LBB61_174 -; CHECK-RV32-NEXT: j .LBB61_695 +; CHECK-RV32-NEXT: j .LBB61_700 ; CHECK-RV32-NEXT: .LBB61_174: # %else646 ; CHECK-RV32-NEXT: andi a3, a2, 8 ; CHECK-RV32-NEXT: beqz a3, .LBB61_175 -; CHECK-RV32-NEXT: j .LBB61_696 +; CHECK-RV32-NEXT: j .LBB61_701 ; CHECK-RV32-NEXT: .LBB61_175: # %else650 ; CHECK-RV32-NEXT: andi a3, a2, 16 ; CHECK-RV32-NEXT: beqz a3, .LBB61_176 -; CHECK-RV32-NEXT: j .LBB61_697 +; CHECK-RV32-NEXT: j .LBB61_702 ; CHECK-RV32-NEXT: .LBB61_176: # %else654 ; CHECK-RV32-NEXT: andi a3, a2, 32 ; CHECK-RV32-NEXT: beqz a3, .LBB61_177 -; CHECK-RV32-NEXT: j .LBB61_698 +; CHECK-RV32-NEXT: j .LBB61_703 ; CHECK-RV32-NEXT: .LBB61_177: # %else658 ; CHECK-RV32-NEXT: andi a3, a2, 64 ; CHECK-RV32-NEXT: beqz a3, .LBB61_178 -; CHECK-RV32-NEXT: j .LBB61_699 +; CHECK-RV32-NEXT: j .LBB61_704 ; CHECK-RV32-NEXT: .LBB61_178: # %else662 ; CHECK-RV32-NEXT: andi a3, a2, 128 ; CHECK-RV32-NEXT: beqz a3, .LBB61_179 -; CHECK-RV32-NEXT: j .LBB61_700 +; CHECK-RV32-NEXT: j .LBB61_705 ; CHECK-RV32-NEXT: .LBB61_179: # %else666 ; CHECK-RV32-NEXT: andi a3, a2, 256 ; CHECK-RV32-NEXT: beqz a3, .LBB61_180 -; CHECK-RV32-NEXT: j .LBB61_701 +; CHECK-RV32-NEXT: j .LBB61_706 ; CHECK-RV32-NEXT: .LBB61_180: # %else670 ; CHECK-RV32-NEXT: andi a3, a2, 512 ; CHECK-RV32-NEXT: beqz a3, .LBB61_181 -; CHECK-RV32-NEXT: j .LBB61_702 +; CHECK-RV32-NEXT: j .LBB61_707 ; CHECK-RV32-NEXT: .LBB61_181: # %else674 ; CHECK-RV32-NEXT: andi a3, a2, 1024 ; CHECK-RV32-NEXT: beqz a3, .LBB61_182 -; CHECK-RV32-NEXT: j .LBB61_703 +; CHECK-RV32-NEXT: j .LBB61_708 ; CHECK-RV32-NEXT: .LBB61_182: # %else678 ; CHECK-RV32-NEXT: slli a3, a2, 20 ; CHECK-RV32-NEXT: bgez a3, .LBB61_183 -; CHECK-RV32-NEXT: j .LBB61_704 +; CHECK-RV32-NEXT: j .LBB61_709 ; CHECK-RV32-NEXT: .LBB61_183: # %else682 ; CHECK-RV32-NEXT: slli a3, a2, 19 ; CHECK-RV32-NEXT: bgez a3, .LBB61_184 -; CHECK-RV32-NEXT: j .LBB61_705 +; CHECK-RV32-NEXT: j .LBB61_710 ; CHECK-RV32-NEXT: .LBB61_184: # %else686 ; CHECK-RV32-NEXT: slli a3, a2, 18 ; CHECK-RV32-NEXT: bgez a3, .LBB61_185 -; CHECK-RV32-NEXT: j .LBB61_706 +; CHECK-RV32-NEXT: j .LBB61_711 ; CHECK-RV32-NEXT: .LBB61_185: # %else690 ; CHECK-RV32-NEXT: slli a3, a2, 17 ; CHECK-RV32-NEXT: bgez a3, .LBB61_186 -; CHECK-RV32-NEXT: j .LBB61_707 +; CHECK-RV32-NEXT: j .LBB61_712 ; CHECK-RV32-NEXT: .LBB61_186: # %else694 ; CHECK-RV32-NEXT: slli a3, a2, 16 ; CHECK-RV32-NEXT: bgez a3, .LBB61_187 -; CHECK-RV32-NEXT: j .LBB61_708 +; CHECK-RV32-NEXT: j .LBB61_713 ; CHECK-RV32-NEXT: .LBB61_187: # %else698 ; CHECK-RV32-NEXT: slli a3, a2, 15 ; CHECK-RV32-NEXT: bgez a3, .LBB61_188 -; CHECK-RV32-NEXT: j .LBB61_709 +; CHECK-RV32-NEXT: j .LBB61_714 ; CHECK-RV32-NEXT: .LBB61_188: # %else702 ; CHECK-RV32-NEXT: slli a3, a2, 14 ; CHECK-RV32-NEXT: bgez a3, .LBB61_189 -; CHECK-RV32-NEXT: j .LBB61_710 +; CHECK-RV32-NEXT: j .LBB61_715 ; CHECK-RV32-NEXT: .LBB61_189: # %else706 ; CHECK-RV32-NEXT: slli a3, a2, 13 ; CHECK-RV32-NEXT: bgez a3, .LBB61_190 -; CHECK-RV32-NEXT: j .LBB61_711 +; CHECK-RV32-NEXT: j .LBB61_716 ; CHECK-RV32-NEXT: .LBB61_190: # %else710 ; CHECK-RV32-NEXT: slli a3, a2, 12 ; CHECK-RV32-NEXT: bgez a3, .LBB61_191 -; CHECK-RV32-NEXT: j .LBB61_712 +; CHECK-RV32-NEXT: j .LBB61_717 ; CHECK-RV32-NEXT: .LBB61_191: # %else714 ; CHECK-RV32-NEXT: slli a3, a2, 11 ; CHECK-RV32-NEXT: bgez a3, .LBB61_192 -; CHECK-RV32-NEXT: j .LBB61_713 +; CHECK-RV32-NEXT: j .LBB61_718 ; CHECK-RV32-NEXT: .LBB61_192: # %else718 ; CHECK-RV32-NEXT: slli a3, a2, 10 ; CHECK-RV32-NEXT: bgez a3, .LBB61_193 -; CHECK-RV32-NEXT: j .LBB61_714 +; CHECK-RV32-NEXT: j .LBB61_719 ; CHECK-RV32-NEXT: .LBB61_193: # %else722 ; CHECK-RV32-NEXT: slli a3, a2, 9 ; CHECK-RV32-NEXT: bgez a3, .LBB61_194 -; CHECK-RV32-NEXT: j .LBB61_715 +; CHECK-RV32-NEXT: j .LBB61_720 ; CHECK-RV32-NEXT: .LBB61_194: # %else726 ; CHECK-RV32-NEXT: slli a3, a2, 8 ; CHECK-RV32-NEXT: bgez a3, .LBB61_195 -; CHECK-RV32-NEXT: j .LBB61_716 +; CHECK-RV32-NEXT: j .LBB61_721 ; CHECK-RV32-NEXT: .LBB61_195: # %else730 ; CHECK-RV32-NEXT: slli a3, a2, 7 ; CHECK-RV32-NEXT: bgez a3, .LBB61_196 -; CHECK-RV32-NEXT: j .LBB61_717 +; CHECK-RV32-NEXT: j .LBB61_722 ; CHECK-RV32-NEXT: .LBB61_196: # %else734 ; CHECK-RV32-NEXT: slli a3, a2, 6 ; CHECK-RV32-NEXT: bgez a3, .LBB61_197 -; CHECK-RV32-NEXT: j .LBB61_718 +; CHECK-RV32-NEXT: j .LBB61_723 ; CHECK-RV32-NEXT: .LBB61_197: # %else738 ; CHECK-RV32-NEXT: slli a3, a2, 5 ; CHECK-RV32-NEXT: bgez a3, .LBB61_198 -; CHECK-RV32-NEXT: j .LBB61_719 +; CHECK-RV32-NEXT: j .LBB61_724 ; CHECK-RV32-NEXT: .LBB61_198: # %else742 ; CHECK-RV32-NEXT: slli a3, a2, 4 ; CHECK-RV32-NEXT: bgez a3, .LBB61_199 -; CHECK-RV32-NEXT: j .LBB61_720 +; CHECK-RV32-NEXT: j .LBB61_725 ; CHECK-RV32-NEXT: .LBB61_199: # %else746 ; CHECK-RV32-NEXT: slli a3, a2, 3 ; CHECK-RV32-NEXT: bgez a3, .LBB61_200 -; CHECK-RV32-NEXT: j .LBB61_721 +; CHECK-RV32-NEXT: j .LBB61_726 ; CHECK-RV32-NEXT: .LBB61_200: # %else750 ; CHECK-RV32-NEXT: slli a3, a2, 2 ; CHECK-RV32-NEXT: bgez a3, .LBB61_202 @@ -2441,123 +2441,123 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-RV32-NEXT: vmv.x.s a3, v24 ; CHECK-RV32-NEXT: bgez a2, .LBB61_205 -; CHECK-RV32-NEXT: j .LBB61_722 +; CHECK-RV32-NEXT: j .LBB61_728 ; CHECK-RV32-NEXT: .LBB61_205: # %else762 ; CHECK-RV32-NEXT: andi a2, a3, 1 ; CHECK-RV32-NEXT: beqz a2, .LBB61_206 -; CHECK-RV32-NEXT: j .LBB61_723 +; CHECK-RV32-NEXT: j .LBB61_729 ; CHECK-RV32-NEXT: .LBB61_206: # %else766 ; CHECK-RV32-NEXT: andi a2, a3, 2 ; CHECK-RV32-NEXT: beqz a2, .LBB61_207 -; CHECK-RV32-NEXT: j .LBB61_724 +; CHECK-RV32-NEXT: j .LBB61_730 ; CHECK-RV32-NEXT: .LBB61_207: # %else770 ; CHECK-RV32-NEXT: andi a2, a3, 4 ; CHECK-RV32-NEXT: beqz a2, .LBB61_208 -; CHECK-RV32-NEXT: j .LBB61_725 +; CHECK-RV32-NEXT: j .LBB61_731 ; CHECK-RV32-NEXT: .LBB61_208: # %else774 ; CHECK-RV32-NEXT: andi a2, a3, 8 ; CHECK-RV32-NEXT: beqz a2, .LBB61_209 -; CHECK-RV32-NEXT: j .LBB61_726 +; CHECK-RV32-NEXT: j .LBB61_732 ; CHECK-RV32-NEXT: .LBB61_209: # %else778 ; CHECK-RV32-NEXT: andi a2, a3, 16 ; CHECK-RV32-NEXT: beqz a2, .LBB61_210 -; CHECK-RV32-NEXT: j .LBB61_727 +; CHECK-RV32-NEXT: j .LBB61_733 ; CHECK-RV32-NEXT: .LBB61_210: # %else782 ; CHECK-RV32-NEXT: andi a2, a3, 32 ; CHECK-RV32-NEXT: beqz a2, .LBB61_211 -; CHECK-RV32-NEXT: j .LBB61_728 +; CHECK-RV32-NEXT: j .LBB61_734 ; CHECK-RV32-NEXT: .LBB61_211: # %else786 ; CHECK-RV32-NEXT: andi a2, a3, 64 ; CHECK-RV32-NEXT: beqz a2, .LBB61_212 -; CHECK-RV32-NEXT: j .LBB61_729 +; CHECK-RV32-NEXT: j .LBB61_735 ; CHECK-RV32-NEXT: .LBB61_212: # %else790 ; CHECK-RV32-NEXT: andi a2, a3, 128 ; CHECK-RV32-NEXT: beqz a2, .LBB61_213 -; CHECK-RV32-NEXT: j .LBB61_730 +; CHECK-RV32-NEXT: j .LBB61_736 ; CHECK-RV32-NEXT: .LBB61_213: # %else794 ; CHECK-RV32-NEXT: andi a2, a3, 256 ; CHECK-RV32-NEXT: beqz a2, .LBB61_214 -; CHECK-RV32-NEXT: j .LBB61_731 +; CHECK-RV32-NEXT: j .LBB61_737 ; CHECK-RV32-NEXT: .LBB61_214: # %else798 ; CHECK-RV32-NEXT: andi a2, a3, 512 ; CHECK-RV32-NEXT: beqz a2, .LBB61_215 -; CHECK-RV32-NEXT: j .LBB61_732 +; CHECK-RV32-NEXT: j .LBB61_738 ; CHECK-RV32-NEXT: .LBB61_215: # %else802 ; CHECK-RV32-NEXT: andi a2, a3, 1024 ; CHECK-RV32-NEXT: beqz a2, .LBB61_216 -; CHECK-RV32-NEXT: j .LBB61_733 +; CHECK-RV32-NEXT: j .LBB61_739 ; CHECK-RV32-NEXT: .LBB61_216: # %else806 ; CHECK-RV32-NEXT: slli a2, a3, 20 ; CHECK-RV32-NEXT: bgez a2, .LBB61_217 -; CHECK-RV32-NEXT: j .LBB61_734 +; CHECK-RV32-NEXT: j .LBB61_740 ; CHECK-RV32-NEXT: .LBB61_217: # %else810 ; CHECK-RV32-NEXT: slli a2, a3, 19 ; CHECK-RV32-NEXT: bgez a2, .LBB61_218 -; CHECK-RV32-NEXT: j .LBB61_735 +; CHECK-RV32-NEXT: j .LBB61_741 ; CHECK-RV32-NEXT: .LBB61_218: # %else814 ; CHECK-RV32-NEXT: slli a2, a3, 18 ; CHECK-RV32-NEXT: bgez a2, .LBB61_219 -; CHECK-RV32-NEXT: j .LBB61_736 +; CHECK-RV32-NEXT: j .LBB61_742 ; CHECK-RV32-NEXT: .LBB61_219: # %else818 ; CHECK-RV32-NEXT: slli a2, a3, 17 ; CHECK-RV32-NEXT: bgez a2, .LBB61_220 -; CHECK-RV32-NEXT: j .LBB61_737 +; CHECK-RV32-NEXT: j .LBB61_743 ; CHECK-RV32-NEXT: .LBB61_220: # %else822 ; CHECK-RV32-NEXT: slli a2, a3, 16 ; CHECK-RV32-NEXT: bgez a2, .LBB61_221 -; CHECK-RV32-NEXT: j .LBB61_738 +; CHECK-RV32-NEXT: j .LBB61_744 ; CHECK-RV32-NEXT: .LBB61_221: # %else826 ; CHECK-RV32-NEXT: slli a2, a3, 15 ; CHECK-RV32-NEXT: bgez a2, .LBB61_222 -; CHECK-RV32-NEXT: j .LBB61_739 +; CHECK-RV32-NEXT: j .LBB61_745 ; CHECK-RV32-NEXT: .LBB61_222: # %else830 ; CHECK-RV32-NEXT: slli a2, a3, 14 ; CHECK-RV32-NEXT: bgez a2, .LBB61_223 -; CHECK-RV32-NEXT: j .LBB61_740 +; CHECK-RV32-NEXT: j .LBB61_746 ; CHECK-RV32-NEXT: .LBB61_223: # %else834 ; CHECK-RV32-NEXT: slli a2, a3, 13 ; CHECK-RV32-NEXT: bgez a2, .LBB61_224 -; CHECK-RV32-NEXT: j .LBB61_741 +; CHECK-RV32-NEXT: j .LBB61_747 ; CHECK-RV32-NEXT: .LBB61_224: # %else838 ; CHECK-RV32-NEXT: slli a2, a3, 12 ; CHECK-RV32-NEXT: bgez a2, .LBB61_225 -; CHECK-RV32-NEXT: j .LBB61_742 +; CHECK-RV32-NEXT: j .LBB61_748 ; CHECK-RV32-NEXT: .LBB61_225: # %else842 ; CHECK-RV32-NEXT: slli a2, a3, 11 ; CHECK-RV32-NEXT: bgez a2, .LBB61_226 -; CHECK-RV32-NEXT: j .LBB61_743 +; CHECK-RV32-NEXT: j .LBB61_749 ; CHECK-RV32-NEXT: .LBB61_226: # %else846 ; CHECK-RV32-NEXT: slli a2, a3, 10 ; CHECK-RV32-NEXT: bgez a2, .LBB61_227 -; CHECK-RV32-NEXT: j .LBB61_744 +; CHECK-RV32-NEXT: j .LBB61_750 ; CHECK-RV32-NEXT: .LBB61_227: # %else850 ; CHECK-RV32-NEXT: slli a2, a3, 9 ; CHECK-RV32-NEXT: bgez a2, .LBB61_228 -; CHECK-RV32-NEXT: j .LBB61_745 +; CHECK-RV32-NEXT: j .LBB61_751 ; CHECK-RV32-NEXT: .LBB61_228: # %else854 ; CHECK-RV32-NEXT: slli a2, a3, 8 ; CHECK-RV32-NEXT: bgez a2, .LBB61_229 -; CHECK-RV32-NEXT: j .LBB61_746 +; CHECK-RV32-NEXT: j .LBB61_752 ; CHECK-RV32-NEXT: .LBB61_229: # %else858 ; CHECK-RV32-NEXT: slli a2, a3, 7 ; CHECK-RV32-NEXT: bgez a2, .LBB61_230 -; CHECK-RV32-NEXT: j .LBB61_747 +; CHECK-RV32-NEXT: j .LBB61_753 ; CHECK-RV32-NEXT: .LBB61_230: # %else862 ; CHECK-RV32-NEXT: slli a2, a3, 6 ; CHECK-RV32-NEXT: bgez a2, .LBB61_231 -; CHECK-RV32-NEXT: j .LBB61_748 +; CHECK-RV32-NEXT: j .LBB61_754 ; CHECK-RV32-NEXT: .LBB61_231: # %else866 ; CHECK-RV32-NEXT: slli a2, a3, 5 ; CHECK-RV32-NEXT: bgez a2, .LBB61_232 -; CHECK-RV32-NEXT: j .LBB61_749 +; CHECK-RV32-NEXT: j .LBB61_755 ; CHECK-RV32-NEXT: .LBB61_232: # %else870 ; CHECK-RV32-NEXT: slli a2, a3, 4 ; CHECK-RV32-NEXT: bgez a2, .LBB61_233 -; CHECK-RV32-NEXT: j .LBB61_750 +; CHECK-RV32-NEXT: j .LBB61_756 ; CHECK-RV32-NEXT: .LBB61_233: # %else874 ; CHECK-RV32-NEXT: slli a2, a3, 3 ; CHECK-RV32-NEXT: bgez a2, .LBB61_234 -; CHECK-RV32-NEXT: j .LBB61_751 +; CHECK-RV32-NEXT: j .LBB61_757 ; CHECK-RV32-NEXT: .LBB61_234: # %else878 ; CHECK-RV32-NEXT: slli a2, a3, 2 ; CHECK-RV32-NEXT: bgez a2, .LBB61_236 @@ -2593,123 +2593,123 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-RV32-NEXT: vmv.x.s a2, v24 ; CHECK-RV32-NEXT: bgez a3, .LBB61_239 -; CHECK-RV32-NEXT: j .LBB61_752 +; CHECK-RV32-NEXT: j .LBB61_759 ; CHECK-RV32-NEXT: .LBB61_239: # %else890 ; CHECK-RV32-NEXT: andi a3, a2, 1 ; CHECK-RV32-NEXT: beqz a3, .LBB61_240 -; CHECK-RV32-NEXT: j .LBB61_753 +; CHECK-RV32-NEXT: j .LBB61_760 ; CHECK-RV32-NEXT: .LBB61_240: # %else894 ; CHECK-RV32-NEXT: andi a3, a2, 2 ; CHECK-RV32-NEXT: beqz a3, .LBB61_241 -; CHECK-RV32-NEXT: j .LBB61_754 +; CHECK-RV32-NEXT: j .LBB61_761 ; CHECK-RV32-NEXT: .LBB61_241: # %else898 ; CHECK-RV32-NEXT: andi a3, a2, 4 ; CHECK-RV32-NEXT: beqz a3, .LBB61_242 -; CHECK-RV32-NEXT: j .LBB61_755 +; CHECK-RV32-NEXT: j .LBB61_762 ; CHECK-RV32-NEXT: .LBB61_242: # %else902 ; CHECK-RV32-NEXT: andi a3, a2, 8 ; CHECK-RV32-NEXT: beqz a3, .LBB61_243 -; CHECK-RV32-NEXT: j .LBB61_756 +; CHECK-RV32-NEXT: j .LBB61_763 ; CHECK-RV32-NEXT: .LBB61_243: # %else906 ; CHECK-RV32-NEXT: andi a3, a2, 16 ; CHECK-RV32-NEXT: beqz a3, .LBB61_244 -; CHECK-RV32-NEXT: j .LBB61_757 +; CHECK-RV32-NEXT: j .LBB61_764 ; CHECK-RV32-NEXT: .LBB61_244: # %else910 ; CHECK-RV32-NEXT: andi a3, a2, 32 ; CHECK-RV32-NEXT: beqz a3, .LBB61_245 -; CHECK-RV32-NEXT: j .LBB61_758 +; CHECK-RV32-NEXT: j .LBB61_765 ; CHECK-RV32-NEXT: .LBB61_245: # %else914 ; CHECK-RV32-NEXT: andi a3, a2, 64 ; CHECK-RV32-NEXT: beqz a3, .LBB61_246 -; CHECK-RV32-NEXT: j .LBB61_759 +; CHECK-RV32-NEXT: j .LBB61_766 ; CHECK-RV32-NEXT: .LBB61_246: # %else918 ; CHECK-RV32-NEXT: andi a3, a2, 128 ; CHECK-RV32-NEXT: beqz a3, .LBB61_247 -; CHECK-RV32-NEXT: j .LBB61_760 +; CHECK-RV32-NEXT: j .LBB61_767 ; CHECK-RV32-NEXT: .LBB61_247: # %else922 ; CHECK-RV32-NEXT: andi a3, a2, 256 ; CHECK-RV32-NEXT: beqz a3, .LBB61_248 -; CHECK-RV32-NEXT: j .LBB61_761 +; CHECK-RV32-NEXT: j .LBB61_768 ; CHECK-RV32-NEXT: .LBB61_248: # %else926 ; CHECK-RV32-NEXT: andi a3, a2, 512 ; CHECK-RV32-NEXT: beqz a3, .LBB61_249 -; CHECK-RV32-NEXT: j .LBB61_762 +; CHECK-RV32-NEXT: j .LBB61_769 ; CHECK-RV32-NEXT: .LBB61_249: # %else930 ; CHECK-RV32-NEXT: andi a3, a2, 1024 ; CHECK-RV32-NEXT: beqz a3, .LBB61_250 -; CHECK-RV32-NEXT: j .LBB61_763 +; CHECK-RV32-NEXT: j .LBB61_770 ; CHECK-RV32-NEXT: .LBB61_250: # %else934 ; CHECK-RV32-NEXT: slli a3, a2, 20 ; CHECK-RV32-NEXT: bgez a3, .LBB61_251 -; CHECK-RV32-NEXT: j .LBB61_764 +; CHECK-RV32-NEXT: j .LBB61_771 ; CHECK-RV32-NEXT: .LBB61_251: # %else938 ; CHECK-RV32-NEXT: slli a3, a2, 19 ; CHECK-RV32-NEXT: bgez a3, .LBB61_252 -; CHECK-RV32-NEXT: j .LBB61_765 +; CHECK-RV32-NEXT: j .LBB61_772 ; CHECK-RV32-NEXT: .LBB61_252: # %else942 ; CHECK-RV32-NEXT: slli a3, a2, 18 ; CHECK-RV32-NEXT: bgez a3, .LBB61_253 -; CHECK-RV32-NEXT: j .LBB61_766 +; CHECK-RV32-NEXT: j .LBB61_773 ; CHECK-RV32-NEXT: .LBB61_253: # %else946 ; CHECK-RV32-NEXT: slli a3, a2, 17 ; CHECK-RV32-NEXT: bgez a3, .LBB61_254 -; CHECK-RV32-NEXT: j .LBB61_767 +; CHECK-RV32-NEXT: j .LBB61_774 ; CHECK-RV32-NEXT: .LBB61_254: # %else950 ; CHECK-RV32-NEXT: slli a3, a2, 16 ; CHECK-RV32-NEXT: bgez a3, .LBB61_255 -; CHECK-RV32-NEXT: j .LBB61_768 +; CHECK-RV32-NEXT: j .LBB61_775 ; CHECK-RV32-NEXT: .LBB61_255: # %else954 ; CHECK-RV32-NEXT: slli a3, a2, 15 ; CHECK-RV32-NEXT: bgez a3, .LBB61_256 -; CHECK-RV32-NEXT: j .LBB61_769 +; CHECK-RV32-NEXT: j .LBB61_776 ; CHECK-RV32-NEXT: .LBB61_256: # %else958 ; CHECK-RV32-NEXT: slli a3, a2, 14 ; CHECK-RV32-NEXT: bgez a3, .LBB61_257 -; CHECK-RV32-NEXT: j .LBB61_770 +; CHECK-RV32-NEXT: j .LBB61_777 ; CHECK-RV32-NEXT: .LBB61_257: # %else962 ; CHECK-RV32-NEXT: slli a3, a2, 13 ; CHECK-RV32-NEXT: bgez a3, .LBB61_258 -; CHECK-RV32-NEXT: j .LBB61_771 +; CHECK-RV32-NEXT: j .LBB61_778 ; CHECK-RV32-NEXT: .LBB61_258: # %else966 ; CHECK-RV32-NEXT: slli a3, a2, 12 ; CHECK-RV32-NEXT: bgez a3, .LBB61_259 -; CHECK-RV32-NEXT: j .LBB61_772 +; CHECK-RV32-NEXT: j .LBB61_779 ; CHECK-RV32-NEXT: .LBB61_259: # %else970 ; CHECK-RV32-NEXT: slli a3, a2, 11 ; CHECK-RV32-NEXT: bgez a3, .LBB61_260 -; CHECK-RV32-NEXT: j .LBB61_773 +; CHECK-RV32-NEXT: j .LBB61_780 ; CHECK-RV32-NEXT: .LBB61_260: # %else974 ; CHECK-RV32-NEXT: slli a3, a2, 10 ; CHECK-RV32-NEXT: bgez a3, .LBB61_261 -; CHECK-RV32-NEXT: j .LBB61_774 +; CHECK-RV32-NEXT: j .LBB61_781 ; CHECK-RV32-NEXT: .LBB61_261: # %else978 ; CHECK-RV32-NEXT: slli a3, a2, 9 ; CHECK-RV32-NEXT: bgez a3, .LBB61_262 -; CHECK-RV32-NEXT: j .LBB61_775 +; CHECK-RV32-NEXT: j .LBB61_782 ; CHECK-RV32-NEXT: .LBB61_262: # %else982 ; CHECK-RV32-NEXT: slli a3, a2, 8 ; CHECK-RV32-NEXT: bgez a3, .LBB61_263 -; CHECK-RV32-NEXT: j .LBB61_776 +; CHECK-RV32-NEXT: j .LBB61_783 ; CHECK-RV32-NEXT: .LBB61_263: # %else986 ; CHECK-RV32-NEXT: slli a3, a2, 7 ; CHECK-RV32-NEXT: bgez a3, .LBB61_264 -; CHECK-RV32-NEXT: j .LBB61_777 +; CHECK-RV32-NEXT: j .LBB61_784 ; CHECK-RV32-NEXT: .LBB61_264: # %else990 ; CHECK-RV32-NEXT: slli a3, a2, 6 ; CHECK-RV32-NEXT: bgez a3, .LBB61_265 -; CHECK-RV32-NEXT: j .LBB61_778 +; CHECK-RV32-NEXT: j .LBB61_785 ; CHECK-RV32-NEXT: .LBB61_265: # %else994 ; CHECK-RV32-NEXT: slli a3, a2, 5 ; CHECK-RV32-NEXT: bgez a3, .LBB61_266 -; CHECK-RV32-NEXT: j .LBB61_779 +; CHECK-RV32-NEXT: j .LBB61_786 ; CHECK-RV32-NEXT: .LBB61_266: # %else998 ; CHECK-RV32-NEXT: slli a3, a2, 4 ; CHECK-RV32-NEXT: bgez a3, .LBB61_267 -; CHECK-RV32-NEXT: j .LBB61_780 +; CHECK-RV32-NEXT: j .LBB61_787 ; CHECK-RV32-NEXT: .LBB61_267: # %else1002 ; CHECK-RV32-NEXT: slli a3, a2, 3 ; CHECK-RV32-NEXT: bgez a3, .LBB61_268 -; CHECK-RV32-NEXT: j .LBB61_781 +; CHECK-RV32-NEXT: j .LBB61_788 ; CHECK-RV32-NEXT: .LBB61_268: # %else1006 ; CHECK-RV32-NEXT: slli a3, a2, 2 ; CHECK-RV32-NEXT: bgez a3, .LBB61_270 @@ -2745,123 +2745,123 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-RV32-NEXT: vmv.x.s a3, v24 ; CHECK-RV32-NEXT: bgez a2, .LBB61_273 -; CHECK-RV32-NEXT: j .LBB61_782 +; CHECK-RV32-NEXT: j .LBB61_790 ; CHECK-RV32-NEXT: .LBB61_273: # %else1018 ; CHECK-RV32-NEXT: andi a2, a3, 1 ; CHECK-RV32-NEXT: beqz a2, .LBB61_274 -; CHECK-RV32-NEXT: j .LBB61_783 +; CHECK-RV32-NEXT: j .LBB61_791 ; CHECK-RV32-NEXT: .LBB61_274: # %else1022 ; CHECK-RV32-NEXT: andi a2, a3, 2 ; CHECK-RV32-NEXT: beqz a2, .LBB61_275 -; CHECK-RV32-NEXT: j .LBB61_784 +; CHECK-RV32-NEXT: j .LBB61_792 ; CHECK-RV32-NEXT: .LBB61_275: # %else1026 ; CHECK-RV32-NEXT: andi a2, a3, 4 ; CHECK-RV32-NEXT: beqz a2, .LBB61_276 -; CHECK-RV32-NEXT: j .LBB61_785 +; CHECK-RV32-NEXT: j .LBB61_793 ; CHECK-RV32-NEXT: .LBB61_276: # %else1030 ; CHECK-RV32-NEXT: andi a2, a3, 8 ; CHECK-RV32-NEXT: beqz a2, .LBB61_277 -; CHECK-RV32-NEXT: j .LBB61_786 +; CHECK-RV32-NEXT: j .LBB61_794 ; CHECK-RV32-NEXT: .LBB61_277: # %else1034 ; CHECK-RV32-NEXT: andi a2, a3, 16 ; CHECK-RV32-NEXT: beqz a2, .LBB61_278 -; CHECK-RV32-NEXT: j .LBB61_787 +; CHECK-RV32-NEXT: j .LBB61_795 ; CHECK-RV32-NEXT: .LBB61_278: # %else1038 ; CHECK-RV32-NEXT: andi a2, a3, 32 ; CHECK-RV32-NEXT: beqz a2, .LBB61_279 -; CHECK-RV32-NEXT: j .LBB61_788 +; CHECK-RV32-NEXT: j .LBB61_796 ; CHECK-RV32-NEXT: .LBB61_279: # %else1042 ; CHECK-RV32-NEXT: andi a2, a3, 64 ; CHECK-RV32-NEXT: beqz a2, .LBB61_280 -; CHECK-RV32-NEXT: j .LBB61_789 +; CHECK-RV32-NEXT: j .LBB61_797 ; CHECK-RV32-NEXT: .LBB61_280: # %else1046 ; CHECK-RV32-NEXT: andi a2, a3, 128 ; CHECK-RV32-NEXT: beqz a2, .LBB61_281 -; CHECK-RV32-NEXT: j .LBB61_790 +; CHECK-RV32-NEXT: j .LBB61_798 ; CHECK-RV32-NEXT: .LBB61_281: # %else1050 ; CHECK-RV32-NEXT: andi a2, a3, 256 ; CHECK-RV32-NEXT: beqz a2, .LBB61_282 -; CHECK-RV32-NEXT: j .LBB61_791 +; CHECK-RV32-NEXT: j .LBB61_799 ; CHECK-RV32-NEXT: .LBB61_282: # %else1054 ; CHECK-RV32-NEXT: andi a2, a3, 512 ; CHECK-RV32-NEXT: beqz a2, .LBB61_283 -; CHECK-RV32-NEXT: j .LBB61_792 +; CHECK-RV32-NEXT: j .LBB61_800 ; CHECK-RV32-NEXT: .LBB61_283: # %else1058 ; CHECK-RV32-NEXT: andi a2, a3, 1024 ; CHECK-RV32-NEXT: beqz a2, .LBB61_284 -; CHECK-RV32-NEXT: j .LBB61_793 +; CHECK-RV32-NEXT: j .LBB61_801 ; CHECK-RV32-NEXT: .LBB61_284: # %else1062 ; CHECK-RV32-NEXT: slli a2, a3, 20 ; CHECK-RV32-NEXT: bgez a2, .LBB61_285 -; CHECK-RV32-NEXT: j .LBB61_794 +; CHECK-RV32-NEXT: j .LBB61_802 ; CHECK-RV32-NEXT: .LBB61_285: # %else1066 ; CHECK-RV32-NEXT: slli a2, a3, 19 ; CHECK-RV32-NEXT: bgez a2, .LBB61_286 -; CHECK-RV32-NEXT: j .LBB61_795 +; CHECK-RV32-NEXT: j .LBB61_803 ; CHECK-RV32-NEXT: .LBB61_286: # %else1070 ; CHECK-RV32-NEXT: slli a2, a3, 18 ; CHECK-RV32-NEXT: bgez a2, .LBB61_287 -; CHECK-RV32-NEXT: j .LBB61_796 +; CHECK-RV32-NEXT: j .LBB61_804 ; CHECK-RV32-NEXT: .LBB61_287: # %else1074 ; CHECK-RV32-NEXT: slli a2, a3, 17 ; CHECK-RV32-NEXT: bgez a2, .LBB61_288 -; CHECK-RV32-NEXT: j .LBB61_797 +; CHECK-RV32-NEXT: j .LBB61_805 ; CHECK-RV32-NEXT: .LBB61_288: # %else1078 ; CHECK-RV32-NEXT: slli a2, a3, 16 ; CHECK-RV32-NEXT: bgez a2, .LBB61_289 -; CHECK-RV32-NEXT: j .LBB61_798 +; CHECK-RV32-NEXT: j .LBB61_806 ; CHECK-RV32-NEXT: .LBB61_289: # %else1082 ; CHECK-RV32-NEXT: slli a2, a3, 15 ; CHECK-RV32-NEXT: bgez a2, .LBB61_290 -; CHECK-RV32-NEXT: j .LBB61_799 +; CHECK-RV32-NEXT: j .LBB61_807 ; CHECK-RV32-NEXT: .LBB61_290: # %else1086 ; CHECK-RV32-NEXT: slli a2, a3, 14 ; CHECK-RV32-NEXT: bgez a2, .LBB61_291 -; CHECK-RV32-NEXT: j .LBB61_800 +; CHECK-RV32-NEXT: j .LBB61_808 ; CHECK-RV32-NEXT: .LBB61_291: # %else1090 ; CHECK-RV32-NEXT: slli a2, a3, 13 ; CHECK-RV32-NEXT: bgez a2, .LBB61_292 -; CHECK-RV32-NEXT: j .LBB61_801 +; CHECK-RV32-NEXT: j .LBB61_809 ; CHECK-RV32-NEXT: .LBB61_292: # %else1094 ; CHECK-RV32-NEXT: slli a2, a3, 12 ; CHECK-RV32-NEXT: bgez a2, .LBB61_293 -; CHECK-RV32-NEXT: j .LBB61_802 +; CHECK-RV32-NEXT: j .LBB61_810 ; CHECK-RV32-NEXT: .LBB61_293: # %else1098 ; CHECK-RV32-NEXT: slli a2, a3, 11 ; CHECK-RV32-NEXT: bgez a2, .LBB61_294 -; CHECK-RV32-NEXT: j .LBB61_803 +; CHECK-RV32-NEXT: j .LBB61_811 ; CHECK-RV32-NEXT: .LBB61_294: # %else1102 ; CHECK-RV32-NEXT: slli a2, a3, 10 ; CHECK-RV32-NEXT: bgez a2, .LBB61_295 -; CHECK-RV32-NEXT: j .LBB61_804 +; CHECK-RV32-NEXT: j .LBB61_812 ; CHECK-RV32-NEXT: .LBB61_295: # %else1106 ; CHECK-RV32-NEXT: slli a2, a3, 9 ; CHECK-RV32-NEXT: bgez a2, .LBB61_296 -; CHECK-RV32-NEXT: j .LBB61_805 +; CHECK-RV32-NEXT: j .LBB61_813 ; CHECK-RV32-NEXT: .LBB61_296: # %else1110 ; CHECK-RV32-NEXT: slli a2, a3, 8 ; CHECK-RV32-NEXT: bgez a2, .LBB61_297 -; CHECK-RV32-NEXT: j .LBB61_806 +; CHECK-RV32-NEXT: j .LBB61_814 ; CHECK-RV32-NEXT: .LBB61_297: # %else1114 ; CHECK-RV32-NEXT: slli a2, a3, 7 ; CHECK-RV32-NEXT: bgez a2, .LBB61_298 -; CHECK-RV32-NEXT: j .LBB61_807 +; CHECK-RV32-NEXT: j .LBB61_815 ; CHECK-RV32-NEXT: .LBB61_298: # %else1118 ; CHECK-RV32-NEXT: slli a2, a3, 6 ; CHECK-RV32-NEXT: bgez a2, .LBB61_299 -; CHECK-RV32-NEXT: j .LBB61_808 +; CHECK-RV32-NEXT: j .LBB61_816 ; CHECK-RV32-NEXT: .LBB61_299: # %else1122 ; CHECK-RV32-NEXT: slli a2, a3, 5 ; CHECK-RV32-NEXT: bgez a2, .LBB61_300 -; CHECK-RV32-NEXT: j .LBB61_809 +; CHECK-RV32-NEXT: j .LBB61_817 ; CHECK-RV32-NEXT: .LBB61_300: # %else1126 ; CHECK-RV32-NEXT: slli a2, a3, 4 ; CHECK-RV32-NEXT: bgez a2, .LBB61_301 -; CHECK-RV32-NEXT: j .LBB61_810 +; CHECK-RV32-NEXT: j .LBB61_818 ; CHECK-RV32-NEXT: .LBB61_301: # %else1130 ; CHECK-RV32-NEXT: slli a2, a3, 3 ; CHECK-RV32-NEXT: bgez a2, .LBB61_302 -; CHECK-RV32-NEXT: j .LBB61_811 +; CHECK-RV32-NEXT: j .LBB61_819 ; CHECK-RV32-NEXT: .LBB61_302: # %else1134 ; CHECK-RV32-NEXT: slli a2, a3, 2 ; CHECK-RV32-NEXT: bgez a2, .LBB61_304 @@ -2892,123 +2892,123 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-RV32-NEXT: vmv.x.s a2, v24 ; CHECK-RV32-NEXT: bgez a3, .LBB61_307 -; CHECK-RV32-NEXT: j .LBB61_812 +; CHECK-RV32-NEXT: j .LBB61_821 ; CHECK-RV32-NEXT: .LBB61_307: # %else1146 ; CHECK-RV32-NEXT: andi a3, a2, 1 ; CHECK-RV32-NEXT: beqz a3, .LBB61_308 -; CHECK-RV32-NEXT: j .LBB61_813 +; CHECK-RV32-NEXT: j .LBB61_822 ; CHECK-RV32-NEXT: .LBB61_308: # %else1150 ; CHECK-RV32-NEXT: andi a3, a2, 2 ; CHECK-RV32-NEXT: beqz a3, .LBB61_309 -; CHECK-RV32-NEXT: j .LBB61_814 +; CHECK-RV32-NEXT: j .LBB61_823 ; CHECK-RV32-NEXT: .LBB61_309: # %else1154 ; CHECK-RV32-NEXT: andi a3, a2, 4 ; CHECK-RV32-NEXT: beqz a3, .LBB61_310 -; CHECK-RV32-NEXT: j .LBB61_815 +; CHECK-RV32-NEXT: j .LBB61_824 ; CHECK-RV32-NEXT: .LBB61_310: # %else1158 ; CHECK-RV32-NEXT: andi a3, a2, 8 ; CHECK-RV32-NEXT: beqz a3, .LBB61_311 -; CHECK-RV32-NEXT: j .LBB61_816 +; CHECK-RV32-NEXT: j .LBB61_825 ; CHECK-RV32-NEXT: .LBB61_311: # %else1162 ; CHECK-RV32-NEXT: andi a3, a2, 16 ; CHECK-RV32-NEXT: beqz a3, .LBB61_312 -; CHECK-RV32-NEXT: j .LBB61_817 +; CHECK-RV32-NEXT: j .LBB61_826 ; CHECK-RV32-NEXT: .LBB61_312: # %else1166 ; CHECK-RV32-NEXT: andi a3, a2, 32 ; CHECK-RV32-NEXT: beqz a3, .LBB61_313 -; CHECK-RV32-NEXT: j .LBB61_818 +; CHECK-RV32-NEXT: j .LBB61_827 ; CHECK-RV32-NEXT: .LBB61_313: # %else1170 ; CHECK-RV32-NEXT: andi a3, a2, 64 ; CHECK-RV32-NEXT: beqz a3, .LBB61_314 -; CHECK-RV32-NEXT: j .LBB61_819 +; CHECK-RV32-NEXT: j .LBB61_828 ; CHECK-RV32-NEXT: .LBB61_314: # %else1174 ; CHECK-RV32-NEXT: andi a3, a2, 128 ; CHECK-RV32-NEXT: beqz a3, .LBB61_315 -; CHECK-RV32-NEXT: j .LBB61_820 +; CHECK-RV32-NEXT: j .LBB61_829 ; CHECK-RV32-NEXT: .LBB61_315: # %else1178 ; CHECK-RV32-NEXT: andi a3, a2, 256 ; CHECK-RV32-NEXT: beqz a3, .LBB61_316 -; CHECK-RV32-NEXT: j .LBB61_821 +; CHECK-RV32-NEXT: j .LBB61_830 ; CHECK-RV32-NEXT: .LBB61_316: # %else1182 ; CHECK-RV32-NEXT: andi a3, a2, 512 ; CHECK-RV32-NEXT: beqz a3, .LBB61_317 -; CHECK-RV32-NEXT: j .LBB61_822 +; CHECK-RV32-NEXT: j .LBB61_831 ; CHECK-RV32-NEXT: .LBB61_317: # %else1186 ; CHECK-RV32-NEXT: andi a3, a2, 1024 ; CHECK-RV32-NEXT: beqz a3, .LBB61_318 -; CHECK-RV32-NEXT: j .LBB61_823 +; CHECK-RV32-NEXT: j .LBB61_832 ; CHECK-RV32-NEXT: .LBB61_318: # %else1190 ; CHECK-RV32-NEXT: slli a3, a2, 20 ; CHECK-RV32-NEXT: bgez a3, .LBB61_319 -; CHECK-RV32-NEXT: j .LBB61_824 +; CHECK-RV32-NEXT: j .LBB61_833 ; CHECK-RV32-NEXT: .LBB61_319: # %else1194 ; CHECK-RV32-NEXT: slli a3, a2, 19 ; CHECK-RV32-NEXT: bgez a3, .LBB61_320 -; CHECK-RV32-NEXT: j .LBB61_825 +; CHECK-RV32-NEXT: j .LBB61_834 ; CHECK-RV32-NEXT: .LBB61_320: # %else1198 ; CHECK-RV32-NEXT: slli a3, a2, 18 ; CHECK-RV32-NEXT: bgez a3, .LBB61_321 -; CHECK-RV32-NEXT: j .LBB61_826 +; CHECK-RV32-NEXT: j .LBB61_835 ; CHECK-RV32-NEXT: .LBB61_321: # %else1202 ; CHECK-RV32-NEXT: slli a3, a2, 17 ; CHECK-RV32-NEXT: bgez a3, .LBB61_322 -; CHECK-RV32-NEXT: j .LBB61_827 +; CHECK-RV32-NEXT: j .LBB61_836 ; CHECK-RV32-NEXT: .LBB61_322: # %else1206 ; CHECK-RV32-NEXT: slli a3, a2, 16 ; CHECK-RV32-NEXT: bgez a3, .LBB61_323 -; CHECK-RV32-NEXT: j .LBB61_828 +; CHECK-RV32-NEXT: j .LBB61_837 ; CHECK-RV32-NEXT: .LBB61_323: # %else1210 ; CHECK-RV32-NEXT: slli a3, a2, 15 ; CHECK-RV32-NEXT: bgez a3, .LBB61_324 -; CHECK-RV32-NEXT: j .LBB61_829 +; CHECK-RV32-NEXT: j .LBB61_838 ; CHECK-RV32-NEXT: .LBB61_324: # %else1214 ; CHECK-RV32-NEXT: slli a3, a2, 14 ; CHECK-RV32-NEXT: bgez a3, .LBB61_325 -; CHECK-RV32-NEXT: j .LBB61_830 +; CHECK-RV32-NEXT: j .LBB61_839 ; CHECK-RV32-NEXT: .LBB61_325: # %else1218 ; CHECK-RV32-NEXT: slli a3, a2, 13 ; CHECK-RV32-NEXT: bgez a3, .LBB61_326 -; CHECK-RV32-NEXT: j .LBB61_831 +; CHECK-RV32-NEXT: j .LBB61_840 ; CHECK-RV32-NEXT: .LBB61_326: # %else1222 ; CHECK-RV32-NEXT: slli a3, a2, 12 ; CHECK-RV32-NEXT: bgez a3, .LBB61_327 -; CHECK-RV32-NEXT: j .LBB61_832 +; CHECK-RV32-NEXT: j .LBB61_841 ; CHECK-RV32-NEXT: .LBB61_327: # %else1226 ; CHECK-RV32-NEXT: slli a3, a2, 11 ; CHECK-RV32-NEXT: bgez a3, .LBB61_328 -; CHECK-RV32-NEXT: j .LBB61_833 +; CHECK-RV32-NEXT: j .LBB61_842 ; CHECK-RV32-NEXT: .LBB61_328: # %else1230 ; CHECK-RV32-NEXT: slli a3, a2, 10 ; CHECK-RV32-NEXT: bgez a3, .LBB61_329 -; CHECK-RV32-NEXT: j .LBB61_834 +; CHECK-RV32-NEXT: j .LBB61_843 ; CHECK-RV32-NEXT: .LBB61_329: # %else1234 ; CHECK-RV32-NEXT: slli a3, a2, 9 ; CHECK-RV32-NEXT: bgez a3, .LBB61_330 -; CHECK-RV32-NEXT: j .LBB61_835 +; CHECK-RV32-NEXT: j .LBB61_844 ; CHECK-RV32-NEXT: .LBB61_330: # %else1238 ; CHECK-RV32-NEXT: slli a3, a2, 8 ; CHECK-RV32-NEXT: bgez a3, .LBB61_331 -; CHECK-RV32-NEXT: j .LBB61_836 +; CHECK-RV32-NEXT: j .LBB61_845 ; CHECK-RV32-NEXT: .LBB61_331: # %else1242 ; CHECK-RV32-NEXT: slli a3, a2, 7 ; CHECK-RV32-NEXT: bgez a3, .LBB61_332 -; CHECK-RV32-NEXT: j .LBB61_837 +; CHECK-RV32-NEXT: j .LBB61_846 ; CHECK-RV32-NEXT: .LBB61_332: # %else1246 ; CHECK-RV32-NEXT: slli a3, a2, 6 ; CHECK-RV32-NEXT: bgez a3, .LBB61_333 -; CHECK-RV32-NEXT: j .LBB61_838 +; CHECK-RV32-NEXT: j .LBB61_847 ; CHECK-RV32-NEXT: .LBB61_333: # %else1250 ; CHECK-RV32-NEXT: slli a3, a2, 5 ; CHECK-RV32-NEXT: bgez a3, .LBB61_334 -; CHECK-RV32-NEXT: j .LBB61_839 +; CHECK-RV32-NEXT: j .LBB61_848 ; CHECK-RV32-NEXT: .LBB61_334: # %else1254 ; CHECK-RV32-NEXT: slli a3, a2, 4 ; CHECK-RV32-NEXT: bgez a3, .LBB61_335 -; CHECK-RV32-NEXT: j .LBB61_840 +; CHECK-RV32-NEXT: j .LBB61_849 ; CHECK-RV32-NEXT: .LBB61_335: # %else1258 ; CHECK-RV32-NEXT: slli a3, a2, 3 ; CHECK-RV32-NEXT: bgez a3, .LBB61_336 -; CHECK-RV32-NEXT: j .LBB61_841 +; CHECK-RV32-NEXT: j .LBB61_850 ; CHECK-RV32-NEXT: .LBB61_336: # %else1262 ; CHECK-RV32-NEXT: slli a3, a2, 2 ; CHECK-RV32-NEXT: bgez a3, .LBB61_338 @@ -3039,123 +3039,123 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-RV32-NEXT: vmv.x.s a3, v24 ; CHECK-RV32-NEXT: bgez a2, .LBB61_341 -; CHECK-RV32-NEXT: j .LBB61_842 +; CHECK-RV32-NEXT: j .LBB61_852 ; CHECK-RV32-NEXT: .LBB61_341: # %else1274 ; CHECK-RV32-NEXT: andi a2, a3, 1 ; CHECK-RV32-NEXT: beqz a2, .LBB61_342 -; CHECK-RV32-NEXT: j .LBB61_843 +; CHECK-RV32-NEXT: j .LBB61_853 ; CHECK-RV32-NEXT: .LBB61_342: # %else1278 ; CHECK-RV32-NEXT: andi a2, a3, 2 ; CHECK-RV32-NEXT: beqz a2, .LBB61_343 -; CHECK-RV32-NEXT: j .LBB61_844 +; CHECK-RV32-NEXT: j .LBB61_854 ; CHECK-RV32-NEXT: .LBB61_343: # %else1282 ; CHECK-RV32-NEXT: andi a2, a3, 4 ; CHECK-RV32-NEXT: beqz a2, .LBB61_344 -; CHECK-RV32-NEXT: j .LBB61_845 +; CHECK-RV32-NEXT: j .LBB61_855 ; CHECK-RV32-NEXT: .LBB61_344: # %else1286 ; CHECK-RV32-NEXT: andi a2, a3, 8 ; CHECK-RV32-NEXT: beqz a2, .LBB61_345 -; CHECK-RV32-NEXT: j .LBB61_846 +; CHECK-RV32-NEXT: j .LBB61_856 ; CHECK-RV32-NEXT: .LBB61_345: # %else1290 ; CHECK-RV32-NEXT: andi a2, a3, 16 ; CHECK-RV32-NEXT: beqz a2, .LBB61_346 -; CHECK-RV32-NEXT: j .LBB61_847 +; CHECK-RV32-NEXT: j .LBB61_857 ; CHECK-RV32-NEXT: .LBB61_346: # %else1294 ; CHECK-RV32-NEXT: andi a2, a3, 32 ; CHECK-RV32-NEXT: beqz a2, .LBB61_347 -; CHECK-RV32-NEXT: j .LBB61_848 +; CHECK-RV32-NEXT: j .LBB61_858 ; CHECK-RV32-NEXT: .LBB61_347: # %else1298 ; CHECK-RV32-NEXT: andi a2, a3, 64 ; CHECK-RV32-NEXT: beqz a2, .LBB61_348 -; CHECK-RV32-NEXT: j .LBB61_849 +; CHECK-RV32-NEXT: j .LBB61_859 ; CHECK-RV32-NEXT: .LBB61_348: # %else1302 ; CHECK-RV32-NEXT: andi a2, a3, 128 ; CHECK-RV32-NEXT: beqz a2, .LBB61_349 -; CHECK-RV32-NEXT: j .LBB61_850 +; CHECK-RV32-NEXT: j .LBB61_860 ; CHECK-RV32-NEXT: .LBB61_349: # %else1306 ; CHECK-RV32-NEXT: andi a2, a3, 256 ; CHECK-RV32-NEXT: beqz a2, .LBB61_350 -; CHECK-RV32-NEXT: j .LBB61_851 +; CHECK-RV32-NEXT: j .LBB61_861 ; CHECK-RV32-NEXT: .LBB61_350: # %else1310 ; CHECK-RV32-NEXT: andi a2, a3, 512 ; CHECK-RV32-NEXT: beqz a2, .LBB61_351 -; CHECK-RV32-NEXT: j .LBB61_852 +; CHECK-RV32-NEXT: j .LBB61_862 ; CHECK-RV32-NEXT: .LBB61_351: # %else1314 ; CHECK-RV32-NEXT: andi a2, a3, 1024 ; CHECK-RV32-NEXT: beqz a2, .LBB61_352 -; CHECK-RV32-NEXT: j .LBB61_853 +; CHECK-RV32-NEXT: j .LBB61_863 ; CHECK-RV32-NEXT: .LBB61_352: # %else1318 ; CHECK-RV32-NEXT: slli a2, a3, 20 ; CHECK-RV32-NEXT: bgez a2, .LBB61_353 -; CHECK-RV32-NEXT: j .LBB61_854 +; CHECK-RV32-NEXT: j .LBB61_864 ; CHECK-RV32-NEXT: .LBB61_353: # %else1322 ; CHECK-RV32-NEXT: slli a2, a3, 19 ; CHECK-RV32-NEXT: bgez a2, .LBB61_354 -; CHECK-RV32-NEXT: j .LBB61_855 +; CHECK-RV32-NEXT: j .LBB61_865 ; CHECK-RV32-NEXT: .LBB61_354: # %else1326 ; CHECK-RV32-NEXT: slli a2, a3, 18 ; CHECK-RV32-NEXT: bgez a2, .LBB61_355 -; CHECK-RV32-NEXT: j .LBB61_856 +; CHECK-RV32-NEXT: j .LBB61_866 ; CHECK-RV32-NEXT: .LBB61_355: # %else1330 ; CHECK-RV32-NEXT: slli a2, a3, 17 ; CHECK-RV32-NEXT: bgez a2, .LBB61_356 -; CHECK-RV32-NEXT: j .LBB61_857 +; CHECK-RV32-NEXT: j .LBB61_867 ; CHECK-RV32-NEXT: .LBB61_356: # %else1334 ; CHECK-RV32-NEXT: slli a2, a3, 16 ; CHECK-RV32-NEXT: bgez a2, .LBB61_357 -; CHECK-RV32-NEXT: j .LBB61_858 +; CHECK-RV32-NEXT: j .LBB61_868 ; CHECK-RV32-NEXT: .LBB61_357: # %else1338 ; CHECK-RV32-NEXT: slli a2, a3, 15 ; CHECK-RV32-NEXT: bgez a2, .LBB61_358 -; CHECK-RV32-NEXT: j .LBB61_859 +; CHECK-RV32-NEXT: j .LBB61_869 ; CHECK-RV32-NEXT: .LBB61_358: # %else1342 ; CHECK-RV32-NEXT: slli a2, a3, 14 ; CHECK-RV32-NEXT: bgez a2, .LBB61_359 -; CHECK-RV32-NEXT: j .LBB61_860 +; CHECK-RV32-NEXT: j .LBB61_870 ; CHECK-RV32-NEXT: .LBB61_359: # %else1346 ; CHECK-RV32-NEXT: slli a2, a3, 13 ; CHECK-RV32-NEXT: bgez a2, .LBB61_360 -; CHECK-RV32-NEXT: j .LBB61_861 +; CHECK-RV32-NEXT: j .LBB61_871 ; CHECK-RV32-NEXT: .LBB61_360: # %else1350 ; CHECK-RV32-NEXT: slli a2, a3, 12 ; CHECK-RV32-NEXT: bgez a2, .LBB61_361 -; CHECK-RV32-NEXT: j .LBB61_862 +; CHECK-RV32-NEXT: j .LBB61_872 ; CHECK-RV32-NEXT: .LBB61_361: # %else1354 ; CHECK-RV32-NEXT: slli a2, a3, 11 ; CHECK-RV32-NEXT: bgez a2, .LBB61_362 -; CHECK-RV32-NEXT: j .LBB61_863 +; CHECK-RV32-NEXT: j .LBB61_873 ; CHECK-RV32-NEXT: .LBB61_362: # %else1358 ; CHECK-RV32-NEXT: slli a2, a3, 10 ; CHECK-RV32-NEXT: bgez a2, .LBB61_363 -; CHECK-RV32-NEXT: j .LBB61_864 +; CHECK-RV32-NEXT: j .LBB61_874 ; CHECK-RV32-NEXT: .LBB61_363: # %else1362 ; CHECK-RV32-NEXT: slli a2, a3, 9 ; CHECK-RV32-NEXT: bgez a2, .LBB61_364 -; CHECK-RV32-NEXT: j .LBB61_865 +; CHECK-RV32-NEXT: j .LBB61_875 ; CHECK-RV32-NEXT: .LBB61_364: # %else1366 ; CHECK-RV32-NEXT: slli a2, a3, 8 ; CHECK-RV32-NEXT: bgez a2, .LBB61_365 -; CHECK-RV32-NEXT: j .LBB61_866 +; CHECK-RV32-NEXT: j .LBB61_876 ; CHECK-RV32-NEXT: .LBB61_365: # %else1370 ; CHECK-RV32-NEXT: slli a2, a3, 7 ; CHECK-RV32-NEXT: bgez a2, .LBB61_366 -; CHECK-RV32-NEXT: j .LBB61_867 +; CHECK-RV32-NEXT: j .LBB61_877 ; CHECK-RV32-NEXT: .LBB61_366: # %else1374 ; CHECK-RV32-NEXT: slli a2, a3, 6 ; CHECK-RV32-NEXT: bgez a2, .LBB61_367 -; CHECK-RV32-NEXT: j .LBB61_868 +; CHECK-RV32-NEXT: j .LBB61_878 ; CHECK-RV32-NEXT: .LBB61_367: # %else1378 ; CHECK-RV32-NEXT: slli a2, a3, 5 ; CHECK-RV32-NEXT: bgez a2, .LBB61_368 -; CHECK-RV32-NEXT: j .LBB61_869 +; CHECK-RV32-NEXT: j .LBB61_879 ; CHECK-RV32-NEXT: .LBB61_368: # %else1382 ; CHECK-RV32-NEXT: slli a2, a3, 4 ; CHECK-RV32-NEXT: bgez a2, .LBB61_369 -; CHECK-RV32-NEXT: j .LBB61_870 +; CHECK-RV32-NEXT: j .LBB61_880 ; CHECK-RV32-NEXT: .LBB61_369: # %else1386 ; CHECK-RV32-NEXT: slli a2, a3, 3 ; CHECK-RV32-NEXT: bgez a2, .LBB61_370 -; CHECK-RV32-NEXT: j .LBB61_871 +; CHECK-RV32-NEXT: j .LBB61_881 ; CHECK-RV32-NEXT: .LBB61_370: # %else1390 ; CHECK-RV32-NEXT: slli a2, a3, 2 ; CHECK-RV32-NEXT: bgez a2, .LBB61_372 @@ -3186,123 +3186,123 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-RV32-NEXT: vmv.x.s a2, v24 ; CHECK-RV32-NEXT: bgez a3, .LBB61_375 -; CHECK-RV32-NEXT: j .LBB61_872 +; CHECK-RV32-NEXT: j .LBB61_883 ; CHECK-RV32-NEXT: .LBB61_375: # %else1402 ; CHECK-RV32-NEXT: andi a3, a2, 1 ; CHECK-RV32-NEXT: beqz a3, .LBB61_376 -; CHECK-RV32-NEXT: j .LBB61_873 +; CHECK-RV32-NEXT: j .LBB61_884 ; CHECK-RV32-NEXT: .LBB61_376: # %else1406 ; CHECK-RV32-NEXT: andi a3, a2, 2 ; CHECK-RV32-NEXT: beqz a3, .LBB61_377 -; CHECK-RV32-NEXT: j .LBB61_874 +; CHECK-RV32-NEXT: j .LBB61_885 ; CHECK-RV32-NEXT: .LBB61_377: # %else1410 ; CHECK-RV32-NEXT: andi a3, a2, 4 ; CHECK-RV32-NEXT: beqz a3, .LBB61_378 -; CHECK-RV32-NEXT: j .LBB61_875 +; CHECK-RV32-NEXT: j .LBB61_886 ; CHECK-RV32-NEXT: .LBB61_378: # %else1414 ; CHECK-RV32-NEXT: andi a3, a2, 8 ; CHECK-RV32-NEXT: beqz a3, .LBB61_379 -; CHECK-RV32-NEXT: j .LBB61_876 +; CHECK-RV32-NEXT: j .LBB61_887 ; CHECK-RV32-NEXT: .LBB61_379: # %else1418 ; CHECK-RV32-NEXT: andi a3, a2, 16 ; CHECK-RV32-NEXT: beqz a3, .LBB61_380 -; CHECK-RV32-NEXT: j .LBB61_877 +; CHECK-RV32-NEXT: j .LBB61_888 ; CHECK-RV32-NEXT: .LBB61_380: # %else1422 ; CHECK-RV32-NEXT: andi a3, a2, 32 ; CHECK-RV32-NEXT: beqz a3, .LBB61_381 -; CHECK-RV32-NEXT: j .LBB61_878 +; CHECK-RV32-NEXT: j .LBB61_889 ; CHECK-RV32-NEXT: .LBB61_381: # %else1426 ; CHECK-RV32-NEXT: andi a3, a2, 64 ; CHECK-RV32-NEXT: beqz a3, .LBB61_382 -; CHECK-RV32-NEXT: j .LBB61_879 +; CHECK-RV32-NEXT: j .LBB61_890 ; CHECK-RV32-NEXT: .LBB61_382: # %else1430 ; CHECK-RV32-NEXT: andi a3, a2, 128 ; CHECK-RV32-NEXT: beqz a3, .LBB61_383 -; CHECK-RV32-NEXT: j .LBB61_880 +; CHECK-RV32-NEXT: j .LBB61_891 ; CHECK-RV32-NEXT: .LBB61_383: # %else1434 ; CHECK-RV32-NEXT: andi a3, a2, 256 ; CHECK-RV32-NEXT: beqz a3, .LBB61_384 -; CHECK-RV32-NEXT: j .LBB61_881 +; CHECK-RV32-NEXT: j .LBB61_892 ; CHECK-RV32-NEXT: .LBB61_384: # %else1438 ; CHECK-RV32-NEXT: andi a3, a2, 512 ; CHECK-RV32-NEXT: beqz a3, .LBB61_385 -; CHECK-RV32-NEXT: j .LBB61_882 +; CHECK-RV32-NEXT: j .LBB61_893 ; CHECK-RV32-NEXT: .LBB61_385: # %else1442 ; CHECK-RV32-NEXT: andi a3, a2, 1024 ; CHECK-RV32-NEXT: beqz a3, .LBB61_386 -; CHECK-RV32-NEXT: j .LBB61_883 +; CHECK-RV32-NEXT: j .LBB61_894 ; CHECK-RV32-NEXT: .LBB61_386: # %else1446 ; CHECK-RV32-NEXT: slli a3, a2, 20 ; CHECK-RV32-NEXT: bgez a3, .LBB61_387 -; CHECK-RV32-NEXT: j .LBB61_884 +; CHECK-RV32-NEXT: j .LBB61_895 ; CHECK-RV32-NEXT: .LBB61_387: # %else1450 ; CHECK-RV32-NEXT: slli a3, a2, 19 ; CHECK-RV32-NEXT: bgez a3, .LBB61_388 -; CHECK-RV32-NEXT: j .LBB61_885 +; CHECK-RV32-NEXT: j .LBB61_896 ; CHECK-RV32-NEXT: .LBB61_388: # %else1454 ; CHECK-RV32-NEXT: slli a3, a2, 18 ; CHECK-RV32-NEXT: bgez a3, .LBB61_389 -; CHECK-RV32-NEXT: j .LBB61_886 +; CHECK-RV32-NEXT: j .LBB61_897 ; CHECK-RV32-NEXT: .LBB61_389: # %else1458 ; CHECK-RV32-NEXT: slli a3, a2, 17 ; CHECK-RV32-NEXT: bgez a3, .LBB61_390 -; CHECK-RV32-NEXT: j .LBB61_887 +; CHECK-RV32-NEXT: j .LBB61_898 ; CHECK-RV32-NEXT: .LBB61_390: # %else1462 ; CHECK-RV32-NEXT: slli a3, a2, 16 ; CHECK-RV32-NEXT: bgez a3, .LBB61_391 -; CHECK-RV32-NEXT: j .LBB61_888 +; CHECK-RV32-NEXT: j .LBB61_899 ; CHECK-RV32-NEXT: .LBB61_391: # %else1466 ; CHECK-RV32-NEXT: slli a3, a2, 15 ; CHECK-RV32-NEXT: bgez a3, .LBB61_392 -; CHECK-RV32-NEXT: j .LBB61_889 +; CHECK-RV32-NEXT: j .LBB61_900 ; CHECK-RV32-NEXT: .LBB61_392: # %else1470 ; CHECK-RV32-NEXT: slli a3, a2, 14 ; CHECK-RV32-NEXT: bgez a3, .LBB61_393 -; CHECK-RV32-NEXT: j .LBB61_890 +; CHECK-RV32-NEXT: j .LBB61_901 ; CHECK-RV32-NEXT: .LBB61_393: # %else1474 ; CHECK-RV32-NEXT: slli a3, a2, 13 ; CHECK-RV32-NEXT: bgez a3, .LBB61_394 -; CHECK-RV32-NEXT: j .LBB61_891 +; CHECK-RV32-NEXT: j .LBB61_902 ; CHECK-RV32-NEXT: .LBB61_394: # %else1478 ; CHECK-RV32-NEXT: slli a3, a2, 12 ; CHECK-RV32-NEXT: bgez a3, .LBB61_395 -; CHECK-RV32-NEXT: j .LBB61_892 +; CHECK-RV32-NEXT: j .LBB61_903 ; CHECK-RV32-NEXT: .LBB61_395: # %else1482 ; CHECK-RV32-NEXT: slli a3, a2, 11 ; CHECK-RV32-NEXT: bgez a3, .LBB61_396 -; CHECK-RV32-NEXT: j .LBB61_893 +; CHECK-RV32-NEXT: j .LBB61_904 ; CHECK-RV32-NEXT: .LBB61_396: # %else1486 ; CHECK-RV32-NEXT: slli a3, a2, 10 ; CHECK-RV32-NEXT: bgez a3, .LBB61_397 -; CHECK-RV32-NEXT: j .LBB61_894 +; CHECK-RV32-NEXT: j .LBB61_905 ; CHECK-RV32-NEXT: .LBB61_397: # %else1490 ; CHECK-RV32-NEXT: slli a3, a2, 9 ; CHECK-RV32-NEXT: bgez a3, .LBB61_398 -; CHECK-RV32-NEXT: j .LBB61_895 +; CHECK-RV32-NEXT: j .LBB61_906 ; CHECK-RV32-NEXT: .LBB61_398: # %else1494 ; CHECK-RV32-NEXT: slli a3, a2, 8 ; CHECK-RV32-NEXT: bgez a3, .LBB61_399 -; CHECK-RV32-NEXT: j .LBB61_896 +; CHECK-RV32-NEXT: j .LBB61_907 ; CHECK-RV32-NEXT: .LBB61_399: # %else1498 ; CHECK-RV32-NEXT: slli a3, a2, 7 ; CHECK-RV32-NEXT: bgez a3, .LBB61_400 -; CHECK-RV32-NEXT: j .LBB61_897 +; CHECK-RV32-NEXT: j .LBB61_908 ; CHECK-RV32-NEXT: .LBB61_400: # %else1502 ; CHECK-RV32-NEXT: slli a3, a2, 6 ; CHECK-RV32-NEXT: bgez a3, .LBB61_401 -; CHECK-RV32-NEXT: j .LBB61_898 +; CHECK-RV32-NEXT: j .LBB61_909 ; CHECK-RV32-NEXT: .LBB61_401: # %else1506 ; CHECK-RV32-NEXT: slli a3, a2, 5 ; CHECK-RV32-NEXT: bgez a3, .LBB61_402 -; CHECK-RV32-NEXT: j .LBB61_899 +; CHECK-RV32-NEXT: j .LBB61_910 ; CHECK-RV32-NEXT: .LBB61_402: # %else1510 ; CHECK-RV32-NEXT: slli a3, a2, 4 ; CHECK-RV32-NEXT: bgez a3, .LBB61_403 -; CHECK-RV32-NEXT: j .LBB61_900 +; CHECK-RV32-NEXT: j .LBB61_911 ; CHECK-RV32-NEXT: .LBB61_403: # %else1514 ; CHECK-RV32-NEXT: slli a3, a2, 3 ; CHECK-RV32-NEXT: bgez a3, .LBB61_404 -; CHECK-RV32-NEXT: j .LBB61_901 +; CHECK-RV32-NEXT: j .LBB61_912 ; CHECK-RV32-NEXT: .LBB61_404: # %else1518 ; CHECK-RV32-NEXT: slli a3, a2, 2 ; CHECK-RV32-NEXT: bgez a3, .LBB61_406 @@ -3333,123 +3333,123 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-RV32-NEXT: vmv.x.s a3, v24 ; CHECK-RV32-NEXT: bgez a2, .LBB61_409 -; CHECK-RV32-NEXT: j .LBB61_902 +; CHECK-RV32-NEXT: j .LBB61_914 ; CHECK-RV32-NEXT: .LBB61_409: # %else1530 ; CHECK-RV32-NEXT: andi a2, a3, 1 ; CHECK-RV32-NEXT: beqz a2, .LBB61_410 -; CHECK-RV32-NEXT: j .LBB61_903 +; CHECK-RV32-NEXT: j .LBB61_915 ; CHECK-RV32-NEXT: .LBB61_410: # %else1534 ; CHECK-RV32-NEXT: andi a2, a3, 2 ; CHECK-RV32-NEXT: beqz a2, .LBB61_411 -; CHECK-RV32-NEXT: j .LBB61_904 +; CHECK-RV32-NEXT: j .LBB61_916 ; CHECK-RV32-NEXT: .LBB61_411: # %else1538 ; CHECK-RV32-NEXT: andi a2, a3, 4 ; CHECK-RV32-NEXT: beqz a2, .LBB61_412 -; CHECK-RV32-NEXT: j .LBB61_905 +; CHECK-RV32-NEXT: j .LBB61_917 ; CHECK-RV32-NEXT: .LBB61_412: # %else1542 ; CHECK-RV32-NEXT: andi a2, a3, 8 ; CHECK-RV32-NEXT: beqz a2, .LBB61_413 -; CHECK-RV32-NEXT: j .LBB61_906 +; CHECK-RV32-NEXT: j .LBB61_918 ; CHECK-RV32-NEXT: .LBB61_413: # %else1546 ; CHECK-RV32-NEXT: andi a2, a3, 16 ; CHECK-RV32-NEXT: beqz a2, .LBB61_414 -; CHECK-RV32-NEXT: j .LBB61_907 +; CHECK-RV32-NEXT: j .LBB61_919 ; CHECK-RV32-NEXT: .LBB61_414: # %else1550 ; CHECK-RV32-NEXT: andi a2, a3, 32 ; CHECK-RV32-NEXT: beqz a2, .LBB61_415 -; CHECK-RV32-NEXT: j .LBB61_908 +; CHECK-RV32-NEXT: j .LBB61_920 ; CHECK-RV32-NEXT: .LBB61_415: # %else1554 ; CHECK-RV32-NEXT: andi a2, a3, 64 ; CHECK-RV32-NEXT: beqz a2, .LBB61_416 -; CHECK-RV32-NEXT: j .LBB61_909 +; CHECK-RV32-NEXT: j .LBB61_921 ; CHECK-RV32-NEXT: .LBB61_416: # %else1558 ; CHECK-RV32-NEXT: andi a2, a3, 128 ; CHECK-RV32-NEXT: beqz a2, .LBB61_417 -; CHECK-RV32-NEXT: j .LBB61_910 +; CHECK-RV32-NEXT: j .LBB61_922 ; CHECK-RV32-NEXT: .LBB61_417: # %else1562 ; CHECK-RV32-NEXT: andi a2, a3, 256 ; CHECK-RV32-NEXT: beqz a2, .LBB61_418 -; CHECK-RV32-NEXT: j .LBB61_911 +; CHECK-RV32-NEXT: j .LBB61_923 ; CHECK-RV32-NEXT: .LBB61_418: # %else1566 ; CHECK-RV32-NEXT: andi a2, a3, 512 ; CHECK-RV32-NEXT: beqz a2, .LBB61_419 -; CHECK-RV32-NEXT: j .LBB61_912 +; CHECK-RV32-NEXT: j .LBB61_924 ; CHECK-RV32-NEXT: .LBB61_419: # %else1570 ; CHECK-RV32-NEXT: andi a2, a3, 1024 ; CHECK-RV32-NEXT: beqz a2, .LBB61_420 -; CHECK-RV32-NEXT: j .LBB61_913 +; CHECK-RV32-NEXT: j .LBB61_925 ; CHECK-RV32-NEXT: .LBB61_420: # %else1574 ; CHECK-RV32-NEXT: slli a2, a3, 20 ; CHECK-RV32-NEXT: bgez a2, .LBB61_421 -; CHECK-RV32-NEXT: j .LBB61_914 +; CHECK-RV32-NEXT: j .LBB61_926 ; CHECK-RV32-NEXT: .LBB61_421: # %else1578 ; CHECK-RV32-NEXT: slli a2, a3, 19 ; CHECK-RV32-NEXT: bgez a2, .LBB61_422 -; CHECK-RV32-NEXT: j .LBB61_915 +; CHECK-RV32-NEXT: j .LBB61_927 ; CHECK-RV32-NEXT: .LBB61_422: # %else1582 ; CHECK-RV32-NEXT: slli a2, a3, 18 ; CHECK-RV32-NEXT: bgez a2, .LBB61_423 -; CHECK-RV32-NEXT: j .LBB61_916 +; CHECK-RV32-NEXT: j .LBB61_928 ; CHECK-RV32-NEXT: .LBB61_423: # %else1586 ; CHECK-RV32-NEXT: slli a2, a3, 17 ; CHECK-RV32-NEXT: bgez a2, .LBB61_424 -; CHECK-RV32-NEXT: j .LBB61_917 +; CHECK-RV32-NEXT: j .LBB61_929 ; CHECK-RV32-NEXT: .LBB61_424: # %else1590 ; CHECK-RV32-NEXT: slli a2, a3, 16 ; CHECK-RV32-NEXT: bgez a2, .LBB61_425 -; CHECK-RV32-NEXT: j .LBB61_918 +; CHECK-RV32-NEXT: j .LBB61_930 ; CHECK-RV32-NEXT: .LBB61_425: # %else1594 ; CHECK-RV32-NEXT: slli a2, a3, 15 ; CHECK-RV32-NEXT: bgez a2, .LBB61_426 -; CHECK-RV32-NEXT: j .LBB61_919 +; CHECK-RV32-NEXT: j .LBB61_931 ; CHECK-RV32-NEXT: .LBB61_426: # %else1598 ; CHECK-RV32-NEXT: slli a2, a3, 14 ; CHECK-RV32-NEXT: bgez a2, .LBB61_427 -; CHECK-RV32-NEXT: j .LBB61_920 +; CHECK-RV32-NEXT: j .LBB61_932 ; CHECK-RV32-NEXT: .LBB61_427: # %else1602 ; CHECK-RV32-NEXT: slli a2, a3, 13 ; CHECK-RV32-NEXT: bgez a2, .LBB61_428 -; CHECK-RV32-NEXT: j .LBB61_921 +; CHECK-RV32-NEXT: j .LBB61_933 ; CHECK-RV32-NEXT: .LBB61_428: # %else1606 ; CHECK-RV32-NEXT: slli a2, a3, 12 ; CHECK-RV32-NEXT: bgez a2, .LBB61_429 -; CHECK-RV32-NEXT: j .LBB61_922 +; CHECK-RV32-NEXT: j .LBB61_934 ; CHECK-RV32-NEXT: .LBB61_429: # %else1610 ; CHECK-RV32-NEXT: slli a2, a3, 11 ; CHECK-RV32-NEXT: bgez a2, .LBB61_430 -; CHECK-RV32-NEXT: j .LBB61_923 +; CHECK-RV32-NEXT: j .LBB61_935 ; CHECK-RV32-NEXT: .LBB61_430: # %else1614 ; CHECK-RV32-NEXT: slli a2, a3, 10 ; CHECK-RV32-NEXT: bgez a2, .LBB61_431 -; CHECK-RV32-NEXT: j .LBB61_924 +; CHECK-RV32-NEXT: j .LBB61_936 ; CHECK-RV32-NEXT: .LBB61_431: # %else1618 ; CHECK-RV32-NEXT: slli a2, a3, 9 ; CHECK-RV32-NEXT: bgez a2, .LBB61_432 -; CHECK-RV32-NEXT: j .LBB61_925 +; CHECK-RV32-NEXT: j .LBB61_937 ; CHECK-RV32-NEXT: .LBB61_432: # %else1622 ; CHECK-RV32-NEXT: slli a2, a3, 8 ; CHECK-RV32-NEXT: bgez a2, .LBB61_433 -; CHECK-RV32-NEXT: j .LBB61_926 +; CHECK-RV32-NEXT: j .LBB61_938 ; CHECK-RV32-NEXT: .LBB61_433: # %else1626 ; CHECK-RV32-NEXT: slli a2, a3, 7 ; CHECK-RV32-NEXT: bgez a2, .LBB61_434 -; CHECK-RV32-NEXT: j .LBB61_927 +; CHECK-RV32-NEXT: j .LBB61_939 ; CHECK-RV32-NEXT: .LBB61_434: # %else1630 ; CHECK-RV32-NEXT: slli a2, a3, 6 ; CHECK-RV32-NEXT: bgez a2, .LBB61_435 -; CHECK-RV32-NEXT: j .LBB61_928 +; CHECK-RV32-NEXT: j .LBB61_940 ; CHECK-RV32-NEXT: .LBB61_435: # %else1634 ; CHECK-RV32-NEXT: slli a2, a3, 5 ; CHECK-RV32-NEXT: bgez a2, .LBB61_436 -; CHECK-RV32-NEXT: j .LBB61_929 +; CHECK-RV32-NEXT: j .LBB61_941 ; CHECK-RV32-NEXT: .LBB61_436: # %else1638 ; CHECK-RV32-NEXT: slli a2, a3, 4 ; CHECK-RV32-NEXT: bgez a2, .LBB61_437 -; CHECK-RV32-NEXT: j .LBB61_930 +; CHECK-RV32-NEXT: j .LBB61_942 ; CHECK-RV32-NEXT: .LBB61_437: # %else1642 ; CHECK-RV32-NEXT: slli a2, a3, 3 ; CHECK-RV32-NEXT: bgez a2, .LBB61_438 -; CHECK-RV32-NEXT: j .LBB61_931 +; CHECK-RV32-NEXT: j .LBB61_943 ; CHECK-RV32-NEXT: .LBB61_438: # %else1646 ; CHECK-RV32-NEXT: slli a2, a3, 2 ; CHECK-RV32-NEXT: bgez a2, .LBB61_440 @@ -3480,123 +3480,123 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-RV32-NEXT: vmv.x.s a2, v24 ; CHECK-RV32-NEXT: bgez a3, .LBB61_443 -; CHECK-RV32-NEXT: j .LBB61_932 +; CHECK-RV32-NEXT: j .LBB61_945 ; CHECK-RV32-NEXT: .LBB61_443: # %else1658 ; CHECK-RV32-NEXT: andi a3, a2, 1 ; CHECK-RV32-NEXT: beqz a3, .LBB61_444 -; CHECK-RV32-NEXT: j .LBB61_933 +; CHECK-RV32-NEXT: j .LBB61_946 ; CHECK-RV32-NEXT: .LBB61_444: # %else1662 ; CHECK-RV32-NEXT: andi a3, a2, 2 ; CHECK-RV32-NEXT: beqz a3, .LBB61_445 -; CHECK-RV32-NEXT: j .LBB61_934 +; CHECK-RV32-NEXT: j .LBB61_947 ; CHECK-RV32-NEXT: .LBB61_445: # %else1666 ; CHECK-RV32-NEXT: andi a3, a2, 4 ; CHECK-RV32-NEXT: beqz a3, .LBB61_446 -; CHECK-RV32-NEXT: j .LBB61_935 +; CHECK-RV32-NEXT: j .LBB61_948 ; CHECK-RV32-NEXT: .LBB61_446: # %else1670 ; CHECK-RV32-NEXT: andi a3, a2, 8 ; CHECK-RV32-NEXT: beqz a3, .LBB61_447 -; CHECK-RV32-NEXT: j .LBB61_936 +; CHECK-RV32-NEXT: j .LBB61_949 ; CHECK-RV32-NEXT: .LBB61_447: # %else1674 ; CHECK-RV32-NEXT: andi a3, a2, 16 ; CHECK-RV32-NEXT: beqz a3, .LBB61_448 -; CHECK-RV32-NEXT: j .LBB61_937 +; CHECK-RV32-NEXT: j .LBB61_950 ; CHECK-RV32-NEXT: .LBB61_448: # %else1678 ; CHECK-RV32-NEXT: andi a3, a2, 32 ; CHECK-RV32-NEXT: beqz a3, .LBB61_449 -; CHECK-RV32-NEXT: j .LBB61_938 +; CHECK-RV32-NEXT: j .LBB61_951 ; CHECK-RV32-NEXT: .LBB61_449: # %else1682 ; CHECK-RV32-NEXT: andi a3, a2, 64 ; CHECK-RV32-NEXT: beqz a3, .LBB61_450 -; CHECK-RV32-NEXT: j .LBB61_939 +; CHECK-RV32-NEXT: j .LBB61_952 ; CHECK-RV32-NEXT: .LBB61_450: # %else1686 ; CHECK-RV32-NEXT: andi a3, a2, 128 ; CHECK-RV32-NEXT: beqz a3, .LBB61_451 -; CHECK-RV32-NEXT: j .LBB61_940 +; CHECK-RV32-NEXT: j .LBB61_953 ; CHECK-RV32-NEXT: .LBB61_451: # %else1690 ; CHECK-RV32-NEXT: andi a3, a2, 256 ; CHECK-RV32-NEXT: beqz a3, .LBB61_452 -; CHECK-RV32-NEXT: j .LBB61_941 +; CHECK-RV32-NEXT: j .LBB61_954 ; CHECK-RV32-NEXT: .LBB61_452: # %else1694 ; CHECK-RV32-NEXT: andi a3, a2, 512 ; CHECK-RV32-NEXT: beqz a3, .LBB61_453 -; CHECK-RV32-NEXT: j .LBB61_942 +; CHECK-RV32-NEXT: j .LBB61_955 ; CHECK-RV32-NEXT: .LBB61_453: # %else1698 ; CHECK-RV32-NEXT: andi a3, a2, 1024 ; CHECK-RV32-NEXT: beqz a3, .LBB61_454 -; CHECK-RV32-NEXT: j .LBB61_943 +; CHECK-RV32-NEXT: j .LBB61_956 ; CHECK-RV32-NEXT: .LBB61_454: # %else1702 ; CHECK-RV32-NEXT: slli a3, a2, 20 ; CHECK-RV32-NEXT: bgez a3, .LBB61_455 -; CHECK-RV32-NEXT: j .LBB61_944 +; CHECK-RV32-NEXT: j .LBB61_957 ; CHECK-RV32-NEXT: .LBB61_455: # %else1706 ; CHECK-RV32-NEXT: slli a3, a2, 19 ; CHECK-RV32-NEXT: bgez a3, .LBB61_456 -; CHECK-RV32-NEXT: j .LBB61_945 +; CHECK-RV32-NEXT: j .LBB61_958 ; CHECK-RV32-NEXT: .LBB61_456: # %else1710 ; CHECK-RV32-NEXT: slli a3, a2, 18 ; CHECK-RV32-NEXT: bgez a3, .LBB61_457 -; CHECK-RV32-NEXT: j .LBB61_946 +; CHECK-RV32-NEXT: j .LBB61_959 ; CHECK-RV32-NEXT: .LBB61_457: # %else1714 ; CHECK-RV32-NEXT: slli a3, a2, 17 ; CHECK-RV32-NEXT: bgez a3, .LBB61_458 -; CHECK-RV32-NEXT: j .LBB61_947 +; CHECK-RV32-NEXT: j .LBB61_960 ; CHECK-RV32-NEXT: .LBB61_458: # %else1718 ; CHECK-RV32-NEXT: slli a3, a2, 16 ; CHECK-RV32-NEXT: bgez a3, .LBB61_459 -; CHECK-RV32-NEXT: j .LBB61_948 +; CHECK-RV32-NEXT: j .LBB61_961 ; CHECK-RV32-NEXT: .LBB61_459: # %else1722 ; CHECK-RV32-NEXT: slli a3, a2, 15 ; CHECK-RV32-NEXT: bgez a3, .LBB61_460 -; CHECK-RV32-NEXT: j .LBB61_949 +; CHECK-RV32-NEXT: j .LBB61_962 ; CHECK-RV32-NEXT: .LBB61_460: # %else1726 ; CHECK-RV32-NEXT: slli a3, a2, 14 ; CHECK-RV32-NEXT: bgez a3, .LBB61_461 -; CHECK-RV32-NEXT: j .LBB61_950 +; CHECK-RV32-NEXT: j .LBB61_963 ; CHECK-RV32-NEXT: .LBB61_461: # %else1730 ; CHECK-RV32-NEXT: slli a3, a2, 13 ; CHECK-RV32-NEXT: bgez a3, .LBB61_462 -; CHECK-RV32-NEXT: j .LBB61_951 +; CHECK-RV32-NEXT: j .LBB61_964 ; CHECK-RV32-NEXT: .LBB61_462: # %else1734 ; CHECK-RV32-NEXT: slli a3, a2, 12 ; CHECK-RV32-NEXT: bgez a3, .LBB61_463 -; CHECK-RV32-NEXT: j .LBB61_952 +; CHECK-RV32-NEXT: j .LBB61_965 ; CHECK-RV32-NEXT: .LBB61_463: # %else1738 ; CHECK-RV32-NEXT: slli a3, a2, 11 ; CHECK-RV32-NEXT: bgez a3, .LBB61_464 -; CHECK-RV32-NEXT: j .LBB61_953 +; CHECK-RV32-NEXT: j .LBB61_966 ; CHECK-RV32-NEXT: .LBB61_464: # %else1742 ; CHECK-RV32-NEXT: slli a3, a2, 10 ; CHECK-RV32-NEXT: bgez a3, .LBB61_465 -; CHECK-RV32-NEXT: j .LBB61_954 +; CHECK-RV32-NEXT: j .LBB61_967 ; CHECK-RV32-NEXT: .LBB61_465: # %else1746 ; CHECK-RV32-NEXT: slli a3, a2, 9 ; CHECK-RV32-NEXT: bgez a3, .LBB61_466 -; CHECK-RV32-NEXT: j .LBB61_955 +; CHECK-RV32-NEXT: j .LBB61_968 ; CHECK-RV32-NEXT: .LBB61_466: # %else1750 ; CHECK-RV32-NEXT: slli a3, a2, 8 ; CHECK-RV32-NEXT: bgez a3, .LBB61_467 -; CHECK-RV32-NEXT: j .LBB61_956 +; CHECK-RV32-NEXT: j .LBB61_969 ; CHECK-RV32-NEXT: .LBB61_467: # %else1754 ; CHECK-RV32-NEXT: slli a3, a2, 7 ; CHECK-RV32-NEXT: bgez a3, .LBB61_468 -; CHECK-RV32-NEXT: j .LBB61_957 +; CHECK-RV32-NEXT: j .LBB61_970 ; CHECK-RV32-NEXT: .LBB61_468: # %else1758 ; CHECK-RV32-NEXT: slli a3, a2, 6 ; CHECK-RV32-NEXT: bgez a3, .LBB61_469 -; CHECK-RV32-NEXT: j .LBB61_958 +; CHECK-RV32-NEXT: j .LBB61_971 ; CHECK-RV32-NEXT: .LBB61_469: # %else1762 ; CHECK-RV32-NEXT: slli a3, a2, 5 ; CHECK-RV32-NEXT: bgez a3, .LBB61_470 -; CHECK-RV32-NEXT: j .LBB61_959 +; CHECK-RV32-NEXT: j .LBB61_972 ; CHECK-RV32-NEXT: .LBB61_470: # %else1766 ; CHECK-RV32-NEXT: slli a3, a2, 4 ; CHECK-RV32-NEXT: bgez a3, .LBB61_471 -; CHECK-RV32-NEXT: j .LBB61_960 +; CHECK-RV32-NEXT: j .LBB61_973 ; CHECK-RV32-NEXT: .LBB61_471: # %else1770 ; CHECK-RV32-NEXT: slli a3, a2, 3 ; CHECK-RV32-NEXT: bgez a3, .LBB61_472 -; CHECK-RV32-NEXT: j .LBB61_961 +; CHECK-RV32-NEXT: j .LBB61_974 ; CHECK-RV32-NEXT: .LBB61_472: # %else1774 ; CHECK-RV32-NEXT: slli a3, a2, 2 ; CHECK-RV32-NEXT: bgez a3, .LBB61_474 @@ -3627,123 +3627,123 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-RV32-NEXT: vmv.x.s a3, v24 ; CHECK-RV32-NEXT: bgez a2, .LBB61_477 -; CHECK-RV32-NEXT: j .LBB61_962 +; CHECK-RV32-NEXT: j .LBB61_976 ; CHECK-RV32-NEXT: .LBB61_477: # %else1786 ; CHECK-RV32-NEXT: andi a2, a3, 1 ; CHECK-RV32-NEXT: beqz a2, .LBB61_478 -; CHECK-RV32-NEXT: j .LBB61_963 +; CHECK-RV32-NEXT: j .LBB61_977 ; CHECK-RV32-NEXT: .LBB61_478: # %else1790 ; CHECK-RV32-NEXT: andi a2, a3, 2 ; CHECK-RV32-NEXT: beqz a2, .LBB61_479 -; CHECK-RV32-NEXT: j .LBB61_964 +; CHECK-RV32-NEXT: j .LBB61_978 ; CHECK-RV32-NEXT: .LBB61_479: # %else1794 ; CHECK-RV32-NEXT: andi a2, a3, 4 ; CHECK-RV32-NEXT: beqz a2, .LBB61_480 -; CHECK-RV32-NEXT: j .LBB61_965 +; CHECK-RV32-NEXT: j .LBB61_979 ; CHECK-RV32-NEXT: .LBB61_480: # %else1798 ; CHECK-RV32-NEXT: andi a2, a3, 8 ; CHECK-RV32-NEXT: beqz a2, .LBB61_481 -; CHECK-RV32-NEXT: j .LBB61_966 +; CHECK-RV32-NEXT: j .LBB61_980 ; CHECK-RV32-NEXT: .LBB61_481: # %else1802 ; CHECK-RV32-NEXT: andi a2, a3, 16 ; CHECK-RV32-NEXT: beqz a2, .LBB61_482 -; CHECK-RV32-NEXT: j .LBB61_967 +; CHECK-RV32-NEXT: j .LBB61_981 ; CHECK-RV32-NEXT: .LBB61_482: # %else1806 ; CHECK-RV32-NEXT: andi a2, a3, 32 ; CHECK-RV32-NEXT: beqz a2, .LBB61_483 -; CHECK-RV32-NEXT: j .LBB61_968 +; CHECK-RV32-NEXT: j .LBB61_982 ; CHECK-RV32-NEXT: .LBB61_483: # %else1810 ; CHECK-RV32-NEXT: andi a2, a3, 64 ; CHECK-RV32-NEXT: beqz a2, .LBB61_484 -; CHECK-RV32-NEXT: j .LBB61_969 +; CHECK-RV32-NEXT: j .LBB61_983 ; CHECK-RV32-NEXT: .LBB61_484: # %else1814 ; CHECK-RV32-NEXT: andi a2, a3, 128 ; CHECK-RV32-NEXT: beqz a2, .LBB61_485 -; CHECK-RV32-NEXT: j .LBB61_970 +; CHECK-RV32-NEXT: j .LBB61_984 ; CHECK-RV32-NEXT: .LBB61_485: # %else1818 ; CHECK-RV32-NEXT: andi a2, a3, 256 ; CHECK-RV32-NEXT: beqz a2, .LBB61_486 -; CHECK-RV32-NEXT: j .LBB61_971 +; CHECK-RV32-NEXT: j .LBB61_985 ; CHECK-RV32-NEXT: .LBB61_486: # %else1822 ; CHECK-RV32-NEXT: andi a2, a3, 512 ; CHECK-RV32-NEXT: beqz a2, .LBB61_487 -; CHECK-RV32-NEXT: j .LBB61_972 +; CHECK-RV32-NEXT: j .LBB61_986 ; CHECK-RV32-NEXT: .LBB61_487: # %else1826 ; CHECK-RV32-NEXT: andi a2, a3, 1024 ; CHECK-RV32-NEXT: beqz a2, .LBB61_488 -; CHECK-RV32-NEXT: j .LBB61_973 +; CHECK-RV32-NEXT: j .LBB61_987 ; CHECK-RV32-NEXT: .LBB61_488: # %else1830 ; CHECK-RV32-NEXT: slli a2, a3, 20 ; CHECK-RV32-NEXT: bgez a2, .LBB61_489 -; CHECK-RV32-NEXT: j .LBB61_974 +; CHECK-RV32-NEXT: j .LBB61_988 ; CHECK-RV32-NEXT: .LBB61_489: # %else1834 ; CHECK-RV32-NEXT: slli a2, a3, 19 ; CHECK-RV32-NEXT: bgez a2, .LBB61_490 -; CHECK-RV32-NEXT: j .LBB61_975 +; CHECK-RV32-NEXT: j .LBB61_989 ; CHECK-RV32-NEXT: .LBB61_490: # %else1838 ; CHECK-RV32-NEXT: slli a2, a3, 18 ; CHECK-RV32-NEXT: bgez a2, .LBB61_491 -; CHECK-RV32-NEXT: j .LBB61_976 +; CHECK-RV32-NEXT: j .LBB61_990 ; CHECK-RV32-NEXT: .LBB61_491: # %else1842 ; CHECK-RV32-NEXT: slli a2, a3, 17 ; CHECK-RV32-NEXT: bgez a2, .LBB61_492 -; CHECK-RV32-NEXT: j .LBB61_977 +; CHECK-RV32-NEXT: j .LBB61_991 ; CHECK-RV32-NEXT: .LBB61_492: # %else1846 ; CHECK-RV32-NEXT: slli a2, a3, 16 ; CHECK-RV32-NEXT: bgez a2, .LBB61_493 -; CHECK-RV32-NEXT: j .LBB61_978 +; CHECK-RV32-NEXT: j .LBB61_992 ; CHECK-RV32-NEXT: .LBB61_493: # %else1850 ; CHECK-RV32-NEXT: slli a2, a3, 15 ; CHECK-RV32-NEXT: bgez a2, .LBB61_494 -; CHECK-RV32-NEXT: j .LBB61_979 +; CHECK-RV32-NEXT: j .LBB61_993 ; CHECK-RV32-NEXT: .LBB61_494: # %else1854 ; CHECK-RV32-NEXT: slli a2, a3, 14 ; CHECK-RV32-NEXT: bgez a2, .LBB61_495 -; CHECK-RV32-NEXT: j .LBB61_980 +; CHECK-RV32-NEXT: j .LBB61_994 ; CHECK-RV32-NEXT: .LBB61_495: # %else1858 ; CHECK-RV32-NEXT: slli a2, a3, 13 ; CHECK-RV32-NEXT: bgez a2, .LBB61_496 -; CHECK-RV32-NEXT: j .LBB61_981 +; CHECK-RV32-NEXT: j .LBB61_995 ; CHECK-RV32-NEXT: .LBB61_496: # %else1862 ; CHECK-RV32-NEXT: slli a2, a3, 12 ; CHECK-RV32-NEXT: bgez a2, .LBB61_497 -; CHECK-RV32-NEXT: j .LBB61_982 +; CHECK-RV32-NEXT: j .LBB61_996 ; CHECK-RV32-NEXT: .LBB61_497: # %else1866 ; CHECK-RV32-NEXT: slli a2, a3, 11 ; CHECK-RV32-NEXT: bgez a2, .LBB61_498 -; CHECK-RV32-NEXT: j .LBB61_983 +; CHECK-RV32-NEXT: j .LBB61_997 ; CHECK-RV32-NEXT: .LBB61_498: # %else1870 ; CHECK-RV32-NEXT: slli a2, a3, 10 ; CHECK-RV32-NEXT: bgez a2, .LBB61_499 -; CHECK-RV32-NEXT: j .LBB61_984 +; CHECK-RV32-NEXT: j .LBB61_998 ; CHECK-RV32-NEXT: .LBB61_499: # %else1874 ; CHECK-RV32-NEXT: slli a2, a3, 9 ; CHECK-RV32-NEXT: bgez a2, .LBB61_500 -; CHECK-RV32-NEXT: j .LBB61_985 +; CHECK-RV32-NEXT: j .LBB61_999 ; CHECK-RV32-NEXT: .LBB61_500: # %else1878 ; CHECK-RV32-NEXT: slli a2, a3, 8 ; CHECK-RV32-NEXT: bgez a2, .LBB61_501 -; CHECK-RV32-NEXT: j .LBB61_986 +; CHECK-RV32-NEXT: j .LBB61_1000 ; CHECK-RV32-NEXT: .LBB61_501: # %else1882 ; CHECK-RV32-NEXT: slli a2, a3, 7 ; CHECK-RV32-NEXT: bgez a2, .LBB61_502 -; CHECK-RV32-NEXT: j .LBB61_987 +; CHECK-RV32-NEXT: j .LBB61_1001 ; CHECK-RV32-NEXT: .LBB61_502: # %else1886 ; CHECK-RV32-NEXT: slli a2, a3, 6 ; CHECK-RV32-NEXT: bgez a2, .LBB61_503 -; CHECK-RV32-NEXT: j .LBB61_988 +; CHECK-RV32-NEXT: j .LBB61_1002 ; CHECK-RV32-NEXT: .LBB61_503: # %else1890 ; CHECK-RV32-NEXT: slli a2, a3, 5 ; CHECK-RV32-NEXT: bgez a2, .LBB61_504 -; CHECK-RV32-NEXT: j .LBB61_989 +; CHECK-RV32-NEXT: j .LBB61_1003 ; CHECK-RV32-NEXT: .LBB61_504: # %else1894 ; CHECK-RV32-NEXT: slli a2, a3, 4 ; CHECK-RV32-NEXT: bgez a2, .LBB61_505 -; CHECK-RV32-NEXT: j .LBB61_990 +; CHECK-RV32-NEXT: j .LBB61_1004 ; CHECK-RV32-NEXT: .LBB61_505: # %else1898 ; CHECK-RV32-NEXT: slli a2, a3, 3 ; CHECK-RV32-NEXT: bgez a2, .LBB61_506 -; CHECK-RV32-NEXT: j .LBB61_991 +; CHECK-RV32-NEXT: j .LBB61_1005 ; CHECK-RV32-NEXT: .LBB61_506: # %else1902 ; CHECK-RV32-NEXT: slli a2, a3, 2 ; CHECK-RV32-NEXT: bgez a2, .LBB61_508 @@ -3774,134 +3774,134 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-RV32-NEXT: vmv.x.s a1, v24 ; CHECK-RV32-NEXT: bgez a3, .LBB61_511 -; CHECK-RV32-NEXT: j .LBB61_992 +; CHECK-RV32-NEXT: j .LBB61_1007 ; CHECK-RV32-NEXT: .LBB61_511: # %else1914 ; CHECK-RV32-NEXT: andi a2, a1, 1 ; CHECK-RV32-NEXT: beqz a2, .LBB61_512 -; CHECK-RV32-NEXT: j .LBB61_993 +; CHECK-RV32-NEXT: j .LBB61_1008 ; CHECK-RV32-NEXT: .LBB61_512: # %else1918 ; CHECK-RV32-NEXT: andi a2, a1, 2 ; CHECK-RV32-NEXT: beqz a2, .LBB61_513 -; CHECK-RV32-NEXT: j .LBB61_994 +; CHECK-RV32-NEXT: j .LBB61_1009 ; CHECK-RV32-NEXT: .LBB61_513: # %else1922 ; CHECK-RV32-NEXT: andi a2, a1, 4 ; CHECK-RV32-NEXT: beqz a2, .LBB61_514 -; CHECK-RV32-NEXT: j .LBB61_995 +; CHECK-RV32-NEXT: j .LBB61_1010 ; CHECK-RV32-NEXT: .LBB61_514: # %else1926 ; CHECK-RV32-NEXT: andi a2, a1, 8 ; CHECK-RV32-NEXT: beqz a2, .LBB61_515 -; CHECK-RV32-NEXT: j .LBB61_996 +; CHECK-RV32-NEXT: j .LBB61_1011 ; CHECK-RV32-NEXT: .LBB61_515: # %else1930 ; CHECK-RV32-NEXT: andi a2, a1, 16 ; CHECK-RV32-NEXT: beqz a2, .LBB61_516 -; CHECK-RV32-NEXT: j .LBB61_997 +; CHECK-RV32-NEXT: j .LBB61_1012 ; CHECK-RV32-NEXT: .LBB61_516: # %else1934 ; CHECK-RV32-NEXT: andi a2, a1, 32 ; CHECK-RV32-NEXT: beqz a2, .LBB61_517 -; CHECK-RV32-NEXT: j .LBB61_998 +; CHECK-RV32-NEXT: j .LBB61_1013 ; CHECK-RV32-NEXT: .LBB61_517: # %else1938 ; CHECK-RV32-NEXT: andi a2, a1, 64 ; CHECK-RV32-NEXT: beqz a2, .LBB61_518 -; CHECK-RV32-NEXT: j .LBB61_999 +; CHECK-RV32-NEXT: j .LBB61_1014 ; CHECK-RV32-NEXT: .LBB61_518: # %else1942 ; CHECK-RV32-NEXT: andi a2, a1, 128 ; CHECK-RV32-NEXT: beqz a2, .LBB61_519 -; CHECK-RV32-NEXT: j .LBB61_1000 +; CHECK-RV32-NEXT: j .LBB61_1015 ; CHECK-RV32-NEXT: .LBB61_519: # %else1946 ; CHECK-RV32-NEXT: andi a2, a1, 256 ; CHECK-RV32-NEXT: beqz a2, .LBB61_520 -; CHECK-RV32-NEXT: j .LBB61_1001 +; CHECK-RV32-NEXT: j .LBB61_1016 ; CHECK-RV32-NEXT: .LBB61_520: # %else1950 ; CHECK-RV32-NEXT: andi a2, a1, 512 ; CHECK-RV32-NEXT: beqz a2, .LBB61_521 -; CHECK-RV32-NEXT: j .LBB61_1002 +; CHECK-RV32-NEXT: j .LBB61_1017 ; CHECK-RV32-NEXT: .LBB61_521: # %else1954 ; CHECK-RV32-NEXT: andi a2, a1, 1024 ; CHECK-RV32-NEXT: beqz a2, .LBB61_522 -; CHECK-RV32-NEXT: j .LBB61_1003 +; CHECK-RV32-NEXT: j .LBB61_1018 ; CHECK-RV32-NEXT: .LBB61_522: # %else1958 ; CHECK-RV32-NEXT: slli a2, a1, 20 ; CHECK-RV32-NEXT: bgez a2, .LBB61_523 -; CHECK-RV32-NEXT: j .LBB61_1004 +; CHECK-RV32-NEXT: j .LBB61_1019 ; CHECK-RV32-NEXT: .LBB61_523: # %else1962 ; CHECK-RV32-NEXT: slli a2, a1, 19 ; CHECK-RV32-NEXT: bgez a2, .LBB61_524 -; CHECK-RV32-NEXT: j .LBB61_1005 +; CHECK-RV32-NEXT: j .LBB61_1020 ; CHECK-RV32-NEXT: .LBB61_524: # %else1966 ; CHECK-RV32-NEXT: slli a2, a1, 18 ; CHECK-RV32-NEXT: bgez a2, .LBB61_525 -; CHECK-RV32-NEXT: j .LBB61_1006 +; CHECK-RV32-NEXT: j .LBB61_1021 ; CHECK-RV32-NEXT: .LBB61_525: # %else1970 ; CHECK-RV32-NEXT: slli a2, a1, 17 ; CHECK-RV32-NEXT: bgez a2, .LBB61_526 -; CHECK-RV32-NEXT: j .LBB61_1007 +; CHECK-RV32-NEXT: j .LBB61_1022 ; CHECK-RV32-NEXT: .LBB61_526: # %else1974 ; CHECK-RV32-NEXT: slli a2, a1, 16 ; CHECK-RV32-NEXT: bgez a2, .LBB61_527 -; CHECK-RV32-NEXT: j .LBB61_1008 +; CHECK-RV32-NEXT: j .LBB61_1023 ; CHECK-RV32-NEXT: .LBB61_527: # %else1978 ; CHECK-RV32-NEXT: slli a2, a1, 15 ; CHECK-RV32-NEXT: bgez a2, .LBB61_528 -; CHECK-RV32-NEXT: j .LBB61_1009 +; CHECK-RV32-NEXT: j .LBB61_1024 ; CHECK-RV32-NEXT: .LBB61_528: # %else1982 ; CHECK-RV32-NEXT: slli a2, a1, 14 ; CHECK-RV32-NEXT: bgez a2, .LBB61_529 -; CHECK-RV32-NEXT: j .LBB61_1010 +; CHECK-RV32-NEXT: j .LBB61_1025 ; CHECK-RV32-NEXT: .LBB61_529: # %else1986 ; CHECK-RV32-NEXT: slli a2, a1, 13 ; CHECK-RV32-NEXT: bgez a2, .LBB61_530 -; CHECK-RV32-NEXT: j .LBB61_1011 +; CHECK-RV32-NEXT: j .LBB61_1026 ; CHECK-RV32-NEXT: .LBB61_530: # %else1990 ; CHECK-RV32-NEXT: slli a2, a1, 12 ; CHECK-RV32-NEXT: bgez a2, .LBB61_531 -; CHECK-RV32-NEXT: j .LBB61_1012 +; CHECK-RV32-NEXT: j .LBB61_1027 ; CHECK-RV32-NEXT: .LBB61_531: # %else1994 ; CHECK-RV32-NEXT: slli a2, a1, 11 ; CHECK-RV32-NEXT: bgez a2, .LBB61_532 -; CHECK-RV32-NEXT: j .LBB61_1013 +; CHECK-RV32-NEXT: j .LBB61_1028 ; CHECK-RV32-NEXT: .LBB61_532: # %else1998 ; CHECK-RV32-NEXT: slli a2, a1, 10 ; CHECK-RV32-NEXT: bgez a2, .LBB61_533 -; CHECK-RV32-NEXT: j .LBB61_1014 +; CHECK-RV32-NEXT: j .LBB61_1029 ; CHECK-RV32-NEXT: .LBB61_533: # %else2002 ; CHECK-RV32-NEXT: slli a2, a1, 9 ; CHECK-RV32-NEXT: bgez a2, .LBB61_534 -; CHECK-RV32-NEXT: j .LBB61_1015 +; CHECK-RV32-NEXT: j .LBB61_1030 ; CHECK-RV32-NEXT: .LBB61_534: # %else2006 ; CHECK-RV32-NEXT: slli a2, a1, 8 ; CHECK-RV32-NEXT: bgez a2, .LBB61_535 -; CHECK-RV32-NEXT: j .LBB61_1016 +; CHECK-RV32-NEXT: j .LBB61_1031 ; CHECK-RV32-NEXT: .LBB61_535: # %else2010 ; CHECK-RV32-NEXT: slli a2, a1, 7 ; CHECK-RV32-NEXT: bgez a2, .LBB61_536 -; CHECK-RV32-NEXT: j .LBB61_1017 +; CHECK-RV32-NEXT: j .LBB61_1032 ; CHECK-RV32-NEXT: .LBB61_536: # %else2014 ; CHECK-RV32-NEXT: slli a2, a1, 6 ; CHECK-RV32-NEXT: bgez a2, .LBB61_537 -; CHECK-RV32-NEXT: j .LBB61_1018 +; CHECK-RV32-NEXT: j .LBB61_1033 ; CHECK-RV32-NEXT: .LBB61_537: # %else2018 ; CHECK-RV32-NEXT: slli a2, a1, 5 ; CHECK-RV32-NEXT: bgez a2, .LBB61_538 -; CHECK-RV32-NEXT: j .LBB61_1019 +; CHECK-RV32-NEXT: j .LBB61_1034 ; CHECK-RV32-NEXT: .LBB61_538: # %else2022 ; CHECK-RV32-NEXT: slli a2, a1, 4 ; CHECK-RV32-NEXT: bgez a2, .LBB61_539 -; CHECK-RV32-NEXT: j .LBB61_1020 +; CHECK-RV32-NEXT: j .LBB61_1035 ; CHECK-RV32-NEXT: .LBB61_539: # %else2026 ; CHECK-RV32-NEXT: slli a2, a1, 3 ; CHECK-RV32-NEXT: bgez a2, .LBB61_540 -; CHECK-RV32-NEXT: j .LBB61_1021 +; CHECK-RV32-NEXT: j .LBB61_1036 ; CHECK-RV32-NEXT: .LBB61_540: # %else2030 ; CHECK-RV32-NEXT: slli a2, a1, 2 ; CHECK-RV32-NEXT: bgez a2, .LBB61_541 -; CHECK-RV32-NEXT: j .LBB61_1022 +; CHECK-RV32-NEXT: j .LBB61_1037 ; CHECK-RV32-NEXT: .LBB61_541: # %else2034 ; CHECK-RV32-NEXT: slli a2, a1, 1 ; CHECK-RV32-NEXT: bgez a2, .LBB61_542 -; CHECK-RV32-NEXT: j .LBB61_1023 +; CHECK-RV32-NEXT: j .LBB61_1038 ; CHECK-RV32-NEXT: .LBB61_542: # %else2038 ; CHECK-RV32-NEXT: bgez a1, .LBB61_543 -; CHECK-RV32-NEXT: j .LBB61_1024 +; CHECK-RV32-NEXT: j .LBB61_1039 ; CHECK-RV32-NEXT: .LBB61_543: # %else2042 ; CHECK-RV32-NEXT: ret ; CHECK-RV32-NEXT: .LBB61_544: # %cond.load @@ -4237,11 +4237,11 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv1r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a1, a3, 3 -; CHECK-RV32-NEXT: bgez a1, .LBB61_1025 +; CHECK-RV32-NEXT: bgez a1, .LBB61_572 ; CHECK-RV32-NEXT: j .LBB61_29 -; CHECK-RV32-NEXT: .LBB61_1025: # %cond.load105 +; CHECK-RV32-NEXT: .LBB61_572: # %cond.load105 ; CHECK-RV32-NEXT: j .LBB61_30 -; CHECK-RV32-NEXT: .LBB61_572: # %cond.load121 +; CHECK-RV32-NEXT: .LBB61_573: # %cond.load121 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vmv8r.v v16, v8 ; CHECK-RV32-NEXT: vmv.s.x v9, a3 @@ -4252,9 +4252,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv1r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 1 -; CHECK-RV32-NEXT: bnez a3, .LBB61_573 +; CHECK-RV32-NEXT: bnez a3, .LBB61_574 ; CHECK-RV32-NEXT: j .LBB61_36 -; CHECK-RV32-NEXT: .LBB61_573: # %cond.load125 +; CHECK-RV32-NEXT: .LBB61_574: # %cond.load125 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4267,9 +4267,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv1r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 2 -; CHECK-RV32-NEXT: bnez a3, .LBB61_574 +; CHECK-RV32-NEXT: bnez a3, .LBB61_575 ; CHECK-RV32-NEXT: j .LBB61_37 -; CHECK-RV32-NEXT: .LBB61_574: # %cond.load129 +; CHECK-RV32-NEXT: .LBB61_575: # %cond.load129 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4282,9 +4282,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv1r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 4 -; CHECK-RV32-NEXT: bnez a3, .LBB61_575 +; CHECK-RV32-NEXT: bnez a3, .LBB61_576 ; CHECK-RV32-NEXT: j .LBB61_38 -; CHECK-RV32-NEXT: .LBB61_575: # %cond.load133 +; CHECK-RV32-NEXT: .LBB61_576: # %cond.load133 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4297,9 +4297,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv1r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 8 -; CHECK-RV32-NEXT: bnez a3, .LBB61_576 +; CHECK-RV32-NEXT: bnez a3, .LBB61_577 ; CHECK-RV32-NEXT: j .LBB61_39 -; CHECK-RV32-NEXT: .LBB61_576: # %cond.load137 +; CHECK-RV32-NEXT: .LBB61_577: # %cond.load137 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4312,9 +4312,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv1r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 16 -; CHECK-RV32-NEXT: bnez a3, .LBB61_577 +; CHECK-RV32-NEXT: bnez a3, .LBB61_578 ; CHECK-RV32-NEXT: j .LBB61_40 -; CHECK-RV32-NEXT: .LBB61_577: # %cond.load141 +; CHECK-RV32-NEXT: .LBB61_578: # %cond.load141 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4327,9 +4327,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv1r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 32 -; CHECK-RV32-NEXT: bnez a3, .LBB61_578 +; CHECK-RV32-NEXT: bnez a3, .LBB61_579 ; CHECK-RV32-NEXT: j .LBB61_41 -; CHECK-RV32-NEXT: .LBB61_578: # %cond.load145 +; CHECK-RV32-NEXT: .LBB61_579: # %cond.load145 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4342,9 +4342,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv1r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 64 -; CHECK-RV32-NEXT: bnez a3, .LBB61_579 +; CHECK-RV32-NEXT: bnez a3, .LBB61_580 ; CHECK-RV32-NEXT: j .LBB61_42 -; CHECK-RV32-NEXT: .LBB61_579: # %cond.load149 +; CHECK-RV32-NEXT: .LBB61_580: # %cond.load149 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4357,9 +4357,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv1r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 128 -; CHECK-RV32-NEXT: bnez a3, .LBB61_580 +; CHECK-RV32-NEXT: bnez a3, .LBB61_581 ; CHECK-RV32-NEXT: j .LBB61_43 -; CHECK-RV32-NEXT: .LBB61_580: # %cond.load153 +; CHECK-RV32-NEXT: .LBB61_581: # %cond.load153 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4372,9 +4372,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv1r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 256 -; CHECK-RV32-NEXT: bnez a3, .LBB61_581 +; CHECK-RV32-NEXT: bnez a3, .LBB61_582 ; CHECK-RV32-NEXT: j .LBB61_44 -; CHECK-RV32-NEXT: .LBB61_581: # %cond.load157 +; CHECK-RV32-NEXT: .LBB61_582: # %cond.load157 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4387,9 +4387,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv1r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 512 -; CHECK-RV32-NEXT: bnez a3, .LBB61_582 +; CHECK-RV32-NEXT: bnez a3, .LBB61_583 ; CHECK-RV32-NEXT: j .LBB61_45 -; CHECK-RV32-NEXT: .LBB61_582: # %cond.load161 +; CHECK-RV32-NEXT: .LBB61_583: # %cond.load161 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4402,9 +4402,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv1r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 1024 -; CHECK-RV32-NEXT: bnez a3, .LBB61_583 +; CHECK-RV32-NEXT: bnez a3, .LBB61_584 ; CHECK-RV32-NEXT: j .LBB61_46 -; CHECK-RV32-NEXT: .LBB61_583: # %cond.load165 +; CHECK-RV32-NEXT: .LBB61_584: # %cond.load165 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4417,9 +4417,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv1r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 20 -; CHECK-RV32-NEXT: bltz a3, .LBB61_584 +; CHECK-RV32-NEXT: bltz a3, .LBB61_585 ; CHECK-RV32-NEXT: j .LBB61_47 -; CHECK-RV32-NEXT: .LBB61_584: # %cond.load169 +; CHECK-RV32-NEXT: .LBB61_585: # %cond.load169 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4432,9 +4432,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv1r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 19 -; CHECK-RV32-NEXT: bltz a3, .LBB61_585 +; CHECK-RV32-NEXT: bltz a3, .LBB61_586 ; CHECK-RV32-NEXT: j .LBB61_48 -; CHECK-RV32-NEXT: .LBB61_585: # %cond.load173 +; CHECK-RV32-NEXT: .LBB61_586: # %cond.load173 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4447,9 +4447,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv1r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 18 -; CHECK-RV32-NEXT: bltz a3, .LBB61_586 +; CHECK-RV32-NEXT: bltz a3, .LBB61_587 ; CHECK-RV32-NEXT: j .LBB61_49 -; CHECK-RV32-NEXT: .LBB61_586: # %cond.load177 +; CHECK-RV32-NEXT: .LBB61_587: # %cond.load177 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4462,9 +4462,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv1r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 17 -; CHECK-RV32-NEXT: bltz a3, .LBB61_587 +; CHECK-RV32-NEXT: bltz a3, .LBB61_588 ; CHECK-RV32-NEXT: j .LBB61_50 -; CHECK-RV32-NEXT: .LBB61_587: # %cond.load181 +; CHECK-RV32-NEXT: .LBB61_588: # %cond.load181 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4477,9 +4477,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv1r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 16 -; CHECK-RV32-NEXT: bltz a3, .LBB61_588 +; CHECK-RV32-NEXT: bltz a3, .LBB61_589 ; CHECK-RV32-NEXT: j .LBB61_51 -; CHECK-RV32-NEXT: .LBB61_588: # %cond.load185 +; CHECK-RV32-NEXT: .LBB61_589: # %cond.load185 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4492,9 +4492,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv1r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 15 -; CHECK-RV32-NEXT: bltz a3, .LBB61_589 +; CHECK-RV32-NEXT: bltz a3, .LBB61_590 ; CHECK-RV32-NEXT: j .LBB61_52 -; CHECK-RV32-NEXT: .LBB61_589: # %cond.load189 +; CHECK-RV32-NEXT: .LBB61_590: # %cond.load189 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4507,9 +4507,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv1r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 14 -; CHECK-RV32-NEXT: bltz a3, .LBB61_590 +; CHECK-RV32-NEXT: bltz a3, .LBB61_591 ; CHECK-RV32-NEXT: j .LBB61_53 -; CHECK-RV32-NEXT: .LBB61_590: # %cond.load193 +; CHECK-RV32-NEXT: .LBB61_591: # %cond.load193 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4522,9 +4522,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv1r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 13 -; CHECK-RV32-NEXT: bltz a3, .LBB61_591 +; CHECK-RV32-NEXT: bltz a3, .LBB61_592 ; CHECK-RV32-NEXT: j .LBB61_54 -; CHECK-RV32-NEXT: .LBB61_591: # %cond.load197 +; CHECK-RV32-NEXT: .LBB61_592: # %cond.load197 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4537,9 +4537,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv1r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 12 -; CHECK-RV32-NEXT: bltz a3, .LBB61_592 +; CHECK-RV32-NEXT: bltz a3, .LBB61_593 ; CHECK-RV32-NEXT: j .LBB61_55 -; CHECK-RV32-NEXT: .LBB61_592: # %cond.load201 +; CHECK-RV32-NEXT: .LBB61_593: # %cond.load201 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4552,9 +4552,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv1r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 11 -; CHECK-RV32-NEXT: bltz a3, .LBB61_593 +; CHECK-RV32-NEXT: bltz a3, .LBB61_594 ; CHECK-RV32-NEXT: j .LBB61_56 -; CHECK-RV32-NEXT: .LBB61_593: # %cond.load205 +; CHECK-RV32-NEXT: .LBB61_594: # %cond.load205 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4567,9 +4567,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv1r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 10 -; CHECK-RV32-NEXT: bltz a3, .LBB61_594 +; CHECK-RV32-NEXT: bltz a3, .LBB61_595 ; CHECK-RV32-NEXT: j .LBB61_57 -; CHECK-RV32-NEXT: .LBB61_594: # %cond.load209 +; CHECK-RV32-NEXT: .LBB61_595: # %cond.load209 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4582,9 +4582,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv1r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 9 -; CHECK-RV32-NEXT: bltz a3, .LBB61_595 +; CHECK-RV32-NEXT: bltz a3, .LBB61_596 ; CHECK-RV32-NEXT: j .LBB61_58 -; CHECK-RV32-NEXT: .LBB61_595: # %cond.load213 +; CHECK-RV32-NEXT: .LBB61_596: # %cond.load213 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4597,9 +4597,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv1r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 8 -; CHECK-RV32-NEXT: bltz a3, .LBB61_596 +; CHECK-RV32-NEXT: bltz a3, .LBB61_597 ; CHECK-RV32-NEXT: j .LBB61_59 -; CHECK-RV32-NEXT: .LBB61_596: # %cond.load217 +; CHECK-RV32-NEXT: .LBB61_597: # %cond.load217 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4612,9 +4612,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv1r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 7 -; CHECK-RV32-NEXT: bltz a3, .LBB61_597 +; CHECK-RV32-NEXT: bltz a3, .LBB61_598 ; CHECK-RV32-NEXT: j .LBB61_60 -; CHECK-RV32-NEXT: .LBB61_597: # %cond.load221 +; CHECK-RV32-NEXT: .LBB61_598: # %cond.load221 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4627,9 +4627,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv1r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 6 -; CHECK-RV32-NEXT: bltz a3, .LBB61_598 +; CHECK-RV32-NEXT: bltz a3, .LBB61_599 ; CHECK-RV32-NEXT: j .LBB61_61 -; CHECK-RV32-NEXT: .LBB61_598: # %cond.load225 +; CHECK-RV32-NEXT: .LBB61_599: # %cond.load225 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4642,9 +4642,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv1r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 5 -; CHECK-RV32-NEXT: bltz a3, .LBB61_599 +; CHECK-RV32-NEXT: bltz a3, .LBB61_600 ; CHECK-RV32-NEXT: j .LBB61_62 -; CHECK-RV32-NEXT: .LBB61_599: # %cond.load229 +; CHECK-RV32-NEXT: .LBB61_600: # %cond.load229 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4657,9 +4657,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv1r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 4 -; CHECK-RV32-NEXT: bltz a3, .LBB61_600 +; CHECK-RV32-NEXT: bltz a3, .LBB61_601 ; CHECK-RV32-NEXT: j .LBB61_63 -; CHECK-RV32-NEXT: .LBB61_600: # %cond.load233 +; CHECK-RV32-NEXT: .LBB61_601: # %cond.load233 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4672,9 +4672,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv1r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 3 -; CHECK-RV32-NEXT: bltz a3, .LBB61_601 +; CHECK-RV32-NEXT: bltz a3, .LBB61_602 ; CHECK-RV32-NEXT: j .LBB61_64 -; CHECK-RV32-NEXT: .LBB61_601: # %cond.load237 +; CHECK-RV32-NEXT: .LBB61_602: # %cond.load237 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4687,11 +4687,11 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv1r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 2 -; CHECK-RV32-NEXT: bgez a3, .LBB61_1026 +; CHECK-RV32-NEXT: bgez a3, .LBB61_603 ; CHECK-RV32-NEXT: j .LBB61_65 -; CHECK-RV32-NEXT: .LBB61_1026: # %cond.load237 +; CHECK-RV32-NEXT: .LBB61_603: # %cond.load237 ; CHECK-RV32-NEXT: j .LBB61_66 -; CHECK-RV32-NEXT: .LBB61_602: # %cond.load249 +; CHECK-RV32-NEXT: .LBB61_604: # %cond.load249 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vmv8r.v v16, v8 ; CHECK-RV32-NEXT: vmv.s.x v9, a2 @@ -4703,9 +4703,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv1r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a2, a3, 1 -; CHECK-RV32-NEXT: bnez a2, .LBB61_603 +; CHECK-RV32-NEXT: bnez a2, .LBB61_605 ; CHECK-RV32-NEXT: j .LBB61_70 -; CHECK-RV32-NEXT: .LBB61_603: # %cond.load253 +; CHECK-RV32-NEXT: .LBB61_605: # %cond.load253 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4718,9 +4718,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a2, a3, 2 -; CHECK-RV32-NEXT: bnez a2, .LBB61_604 +; CHECK-RV32-NEXT: bnez a2, .LBB61_606 ; CHECK-RV32-NEXT: j .LBB61_71 -; CHECK-RV32-NEXT: .LBB61_604: # %cond.load257 +; CHECK-RV32-NEXT: .LBB61_606: # %cond.load257 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4733,9 +4733,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a2, a3, 4 -; CHECK-RV32-NEXT: bnez a2, .LBB61_605 +; CHECK-RV32-NEXT: bnez a2, .LBB61_607 ; CHECK-RV32-NEXT: j .LBB61_72 -; CHECK-RV32-NEXT: .LBB61_605: # %cond.load261 +; CHECK-RV32-NEXT: .LBB61_607: # %cond.load261 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4748,9 +4748,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a2, a3, 8 -; CHECK-RV32-NEXT: bnez a2, .LBB61_606 +; CHECK-RV32-NEXT: bnez a2, .LBB61_608 ; CHECK-RV32-NEXT: j .LBB61_73 -; CHECK-RV32-NEXT: .LBB61_606: # %cond.load265 +; CHECK-RV32-NEXT: .LBB61_608: # %cond.load265 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4763,9 +4763,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a2, a3, 16 -; CHECK-RV32-NEXT: bnez a2, .LBB61_607 +; CHECK-RV32-NEXT: bnez a2, .LBB61_609 ; CHECK-RV32-NEXT: j .LBB61_74 -; CHECK-RV32-NEXT: .LBB61_607: # %cond.load269 +; CHECK-RV32-NEXT: .LBB61_609: # %cond.load269 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4778,9 +4778,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a2, a3, 32 -; CHECK-RV32-NEXT: bnez a2, .LBB61_608 +; CHECK-RV32-NEXT: bnez a2, .LBB61_610 ; CHECK-RV32-NEXT: j .LBB61_75 -; CHECK-RV32-NEXT: .LBB61_608: # %cond.load273 +; CHECK-RV32-NEXT: .LBB61_610: # %cond.load273 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4793,9 +4793,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a2, a3, 64 -; CHECK-RV32-NEXT: bnez a2, .LBB61_609 +; CHECK-RV32-NEXT: bnez a2, .LBB61_611 ; CHECK-RV32-NEXT: j .LBB61_76 -; CHECK-RV32-NEXT: .LBB61_609: # %cond.load277 +; CHECK-RV32-NEXT: .LBB61_611: # %cond.load277 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4808,9 +4808,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a2, a3, 128 -; CHECK-RV32-NEXT: bnez a2, .LBB61_610 +; CHECK-RV32-NEXT: bnez a2, .LBB61_612 ; CHECK-RV32-NEXT: j .LBB61_77 -; CHECK-RV32-NEXT: .LBB61_610: # %cond.load281 +; CHECK-RV32-NEXT: .LBB61_612: # %cond.load281 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4823,9 +4823,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a2, a3, 256 -; CHECK-RV32-NEXT: bnez a2, .LBB61_611 +; CHECK-RV32-NEXT: bnez a2, .LBB61_613 ; CHECK-RV32-NEXT: j .LBB61_78 -; CHECK-RV32-NEXT: .LBB61_611: # %cond.load285 +; CHECK-RV32-NEXT: .LBB61_613: # %cond.load285 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4838,9 +4838,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a2, a3, 512 -; CHECK-RV32-NEXT: bnez a2, .LBB61_612 +; CHECK-RV32-NEXT: bnez a2, .LBB61_614 ; CHECK-RV32-NEXT: j .LBB61_79 -; CHECK-RV32-NEXT: .LBB61_612: # %cond.load289 +; CHECK-RV32-NEXT: .LBB61_614: # %cond.load289 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4853,9 +4853,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a2, a3, 1024 -; CHECK-RV32-NEXT: bnez a2, .LBB61_613 +; CHECK-RV32-NEXT: bnez a2, .LBB61_615 ; CHECK-RV32-NEXT: j .LBB61_80 -; CHECK-RV32-NEXT: .LBB61_613: # %cond.load293 +; CHECK-RV32-NEXT: .LBB61_615: # %cond.load293 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4868,9 +4868,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 20 -; CHECK-RV32-NEXT: bltz a2, .LBB61_614 +; CHECK-RV32-NEXT: bltz a2, .LBB61_616 ; CHECK-RV32-NEXT: j .LBB61_81 -; CHECK-RV32-NEXT: .LBB61_614: # %cond.load297 +; CHECK-RV32-NEXT: .LBB61_616: # %cond.load297 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4883,9 +4883,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 19 -; CHECK-RV32-NEXT: bltz a2, .LBB61_615 +; CHECK-RV32-NEXT: bltz a2, .LBB61_617 ; CHECK-RV32-NEXT: j .LBB61_82 -; CHECK-RV32-NEXT: .LBB61_615: # %cond.load301 +; CHECK-RV32-NEXT: .LBB61_617: # %cond.load301 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4898,9 +4898,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 18 -; CHECK-RV32-NEXT: bltz a2, .LBB61_616 +; CHECK-RV32-NEXT: bltz a2, .LBB61_618 ; CHECK-RV32-NEXT: j .LBB61_83 -; CHECK-RV32-NEXT: .LBB61_616: # %cond.load305 +; CHECK-RV32-NEXT: .LBB61_618: # %cond.load305 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4913,9 +4913,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 17 -; CHECK-RV32-NEXT: bltz a2, .LBB61_617 +; CHECK-RV32-NEXT: bltz a2, .LBB61_619 ; CHECK-RV32-NEXT: j .LBB61_84 -; CHECK-RV32-NEXT: .LBB61_617: # %cond.load309 +; CHECK-RV32-NEXT: .LBB61_619: # %cond.load309 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4928,9 +4928,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 16 -; CHECK-RV32-NEXT: bltz a2, .LBB61_618 +; CHECK-RV32-NEXT: bltz a2, .LBB61_620 ; CHECK-RV32-NEXT: j .LBB61_85 -; CHECK-RV32-NEXT: .LBB61_618: # %cond.load313 +; CHECK-RV32-NEXT: .LBB61_620: # %cond.load313 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4943,9 +4943,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 15 -; CHECK-RV32-NEXT: bltz a2, .LBB61_619 +; CHECK-RV32-NEXT: bltz a2, .LBB61_621 ; CHECK-RV32-NEXT: j .LBB61_86 -; CHECK-RV32-NEXT: .LBB61_619: # %cond.load317 +; CHECK-RV32-NEXT: .LBB61_621: # %cond.load317 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4958,9 +4958,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 14 -; CHECK-RV32-NEXT: bltz a2, .LBB61_620 +; CHECK-RV32-NEXT: bltz a2, .LBB61_622 ; CHECK-RV32-NEXT: j .LBB61_87 -; CHECK-RV32-NEXT: .LBB61_620: # %cond.load321 +; CHECK-RV32-NEXT: .LBB61_622: # %cond.load321 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4973,9 +4973,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 13 -; CHECK-RV32-NEXT: bltz a2, .LBB61_621 +; CHECK-RV32-NEXT: bltz a2, .LBB61_623 ; CHECK-RV32-NEXT: j .LBB61_88 -; CHECK-RV32-NEXT: .LBB61_621: # %cond.load325 +; CHECK-RV32-NEXT: .LBB61_623: # %cond.load325 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -4988,9 +4988,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 12 -; CHECK-RV32-NEXT: bltz a2, .LBB61_622 +; CHECK-RV32-NEXT: bltz a2, .LBB61_624 ; CHECK-RV32-NEXT: j .LBB61_89 -; CHECK-RV32-NEXT: .LBB61_622: # %cond.load329 +; CHECK-RV32-NEXT: .LBB61_624: # %cond.load329 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5003,9 +5003,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 11 -; CHECK-RV32-NEXT: bltz a2, .LBB61_623 +; CHECK-RV32-NEXT: bltz a2, .LBB61_625 ; CHECK-RV32-NEXT: j .LBB61_90 -; CHECK-RV32-NEXT: .LBB61_623: # %cond.load333 +; CHECK-RV32-NEXT: .LBB61_625: # %cond.load333 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5018,9 +5018,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 10 -; CHECK-RV32-NEXT: bltz a2, .LBB61_624 +; CHECK-RV32-NEXT: bltz a2, .LBB61_626 ; CHECK-RV32-NEXT: j .LBB61_91 -; CHECK-RV32-NEXT: .LBB61_624: # %cond.load337 +; CHECK-RV32-NEXT: .LBB61_626: # %cond.load337 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5033,9 +5033,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 9 -; CHECK-RV32-NEXT: bltz a2, .LBB61_625 +; CHECK-RV32-NEXT: bltz a2, .LBB61_627 ; CHECK-RV32-NEXT: j .LBB61_92 -; CHECK-RV32-NEXT: .LBB61_625: # %cond.load341 +; CHECK-RV32-NEXT: .LBB61_627: # %cond.load341 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5048,9 +5048,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 8 -; CHECK-RV32-NEXT: bltz a2, .LBB61_626 +; CHECK-RV32-NEXT: bltz a2, .LBB61_628 ; CHECK-RV32-NEXT: j .LBB61_93 -; CHECK-RV32-NEXT: .LBB61_626: # %cond.load345 +; CHECK-RV32-NEXT: .LBB61_628: # %cond.load345 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5063,9 +5063,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 7 -; CHECK-RV32-NEXT: bltz a2, .LBB61_627 +; CHECK-RV32-NEXT: bltz a2, .LBB61_629 ; CHECK-RV32-NEXT: j .LBB61_94 -; CHECK-RV32-NEXT: .LBB61_627: # %cond.load349 +; CHECK-RV32-NEXT: .LBB61_629: # %cond.load349 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5078,9 +5078,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 6 -; CHECK-RV32-NEXT: bltz a2, .LBB61_628 +; CHECK-RV32-NEXT: bltz a2, .LBB61_630 ; CHECK-RV32-NEXT: j .LBB61_95 -; CHECK-RV32-NEXT: .LBB61_628: # %cond.load353 +; CHECK-RV32-NEXT: .LBB61_630: # %cond.load353 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5093,9 +5093,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 5 -; CHECK-RV32-NEXT: bltz a2, .LBB61_629 +; CHECK-RV32-NEXT: bltz a2, .LBB61_631 ; CHECK-RV32-NEXT: j .LBB61_96 -; CHECK-RV32-NEXT: .LBB61_629: # %cond.load357 +; CHECK-RV32-NEXT: .LBB61_631: # %cond.load357 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5108,9 +5108,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 4 -; CHECK-RV32-NEXT: bltz a2, .LBB61_630 +; CHECK-RV32-NEXT: bltz a2, .LBB61_632 ; CHECK-RV32-NEXT: j .LBB61_97 -; CHECK-RV32-NEXT: .LBB61_630: # %cond.load361 +; CHECK-RV32-NEXT: .LBB61_632: # %cond.load361 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5123,9 +5123,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 3 -; CHECK-RV32-NEXT: bltz a2, .LBB61_631 +; CHECK-RV32-NEXT: bltz a2, .LBB61_633 ; CHECK-RV32-NEXT: j .LBB61_98 -; CHECK-RV32-NEXT: .LBB61_631: # %cond.load365 +; CHECK-RV32-NEXT: .LBB61_633: # %cond.load365 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5138,11 +5138,11 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 2 -; CHECK-RV32-NEXT: bgez a2, .LBB61_1027 +; CHECK-RV32-NEXT: bgez a2, .LBB61_634 ; CHECK-RV32-NEXT: j .LBB61_99 -; CHECK-RV32-NEXT: .LBB61_1027: # %cond.load365 +; CHECK-RV32-NEXT: .LBB61_634: # %cond.load365 ; CHECK-RV32-NEXT: j .LBB61_100 -; CHECK-RV32-NEXT: .LBB61_632: # %cond.load377 +; CHECK-RV32-NEXT: .LBB61_635: # %cond.load377 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vmv8r.v v16, v8 ; CHECK-RV32-NEXT: vmv.s.x v10, a3 @@ -5154,9 +5154,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 1 -; CHECK-RV32-NEXT: bnez a3, .LBB61_633 +; CHECK-RV32-NEXT: bnez a3, .LBB61_636 ; CHECK-RV32-NEXT: j .LBB61_104 -; CHECK-RV32-NEXT: .LBB61_633: # %cond.load381 +; CHECK-RV32-NEXT: .LBB61_636: # %cond.load381 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5169,9 +5169,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 2 -; CHECK-RV32-NEXT: bnez a3, .LBB61_634 +; CHECK-RV32-NEXT: bnez a3, .LBB61_637 ; CHECK-RV32-NEXT: j .LBB61_105 -; CHECK-RV32-NEXT: .LBB61_634: # %cond.load385 +; CHECK-RV32-NEXT: .LBB61_637: # %cond.load385 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5184,9 +5184,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 4 -; CHECK-RV32-NEXT: bnez a3, .LBB61_635 +; CHECK-RV32-NEXT: bnez a3, .LBB61_638 ; CHECK-RV32-NEXT: j .LBB61_106 -; CHECK-RV32-NEXT: .LBB61_635: # %cond.load389 +; CHECK-RV32-NEXT: .LBB61_638: # %cond.load389 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5199,9 +5199,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 8 -; CHECK-RV32-NEXT: bnez a3, .LBB61_636 +; CHECK-RV32-NEXT: bnez a3, .LBB61_639 ; CHECK-RV32-NEXT: j .LBB61_107 -; CHECK-RV32-NEXT: .LBB61_636: # %cond.load393 +; CHECK-RV32-NEXT: .LBB61_639: # %cond.load393 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5214,9 +5214,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 16 -; CHECK-RV32-NEXT: bnez a3, .LBB61_637 +; CHECK-RV32-NEXT: bnez a3, .LBB61_640 ; CHECK-RV32-NEXT: j .LBB61_108 -; CHECK-RV32-NEXT: .LBB61_637: # %cond.load397 +; CHECK-RV32-NEXT: .LBB61_640: # %cond.load397 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5229,9 +5229,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 32 -; CHECK-RV32-NEXT: bnez a3, .LBB61_638 +; CHECK-RV32-NEXT: bnez a3, .LBB61_641 ; CHECK-RV32-NEXT: j .LBB61_109 -; CHECK-RV32-NEXT: .LBB61_638: # %cond.load401 +; CHECK-RV32-NEXT: .LBB61_641: # %cond.load401 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5244,9 +5244,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 64 -; CHECK-RV32-NEXT: bnez a3, .LBB61_639 +; CHECK-RV32-NEXT: bnez a3, .LBB61_642 ; CHECK-RV32-NEXT: j .LBB61_110 -; CHECK-RV32-NEXT: .LBB61_639: # %cond.load405 +; CHECK-RV32-NEXT: .LBB61_642: # %cond.load405 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5259,9 +5259,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 128 -; CHECK-RV32-NEXT: bnez a3, .LBB61_640 +; CHECK-RV32-NEXT: bnez a3, .LBB61_643 ; CHECK-RV32-NEXT: j .LBB61_111 -; CHECK-RV32-NEXT: .LBB61_640: # %cond.load409 +; CHECK-RV32-NEXT: .LBB61_643: # %cond.load409 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5274,9 +5274,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 256 -; CHECK-RV32-NEXT: bnez a3, .LBB61_641 +; CHECK-RV32-NEXT: bnez a3, .LBB61_644 ; CHECK-RV32-NEXT: j .LBB61_112 -; CHECK-RV32-NEXT: .LBB61_641: # %cond.load413 +; CHECK-RV32-NEXT: .LBB61_644: # %cond.load413 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5289,9 +5289,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 512 -; CHECK-RV32-NEXT: bnez a3, .LBB61_642 +; CHECK-RV32-NEXT: bnez a3, .LBB61_645 ; CHECK-RV32-NEXT: j .LBB61_113 -; CHECK-RV32-NEXT: .LBB61_642: # %cond.load417 +; CHECK-RV32-NEXT: .LBB61_645: # %cond.load417 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5304,9 +5304,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 1024 -; CHECK-RV32-NEXT: bnez a3, .LBB61_643 +; CHECK-RV32-NEXT: bnez a3, .LBB61_646 ; CHECK-RV32-NEXT: j .LBB61_114 -; CHECK-RV32-NEXT: .LBB61_643: # %cond.load421 +; CHECK-RV32-NEXT: .LBB61_646: # %cond.load421 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5319,9 +5319,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 20 -; CHECK-RV32-NEXT: bltz a3, .LBB61_644 +; CHECK-RV32-NEXT: bltz a3, .LBB61_647 ; CHECK-RV32-NEXT: j .LBB61_115 -; CHECK-RV32-NEXT: .LBB61_644: # %cond.load425 +; CHECK-RV32-NEXT: .LBB61_647: # %cond.load425 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5334,9 +5334,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 19 -; CHECK-RV32-NEXT: bltz a3, .LBB61_645 +; CHECK-RV32-NEXT: bltz a3, .LBB61_648 ; CHECK-RV32-NEXT: j .LBB61_116 -; CHECK-RV32-NEXT: .LBB61_645: # %cond.load429 +; CHECK-RV32-NEXT: .LBB61_648: # %cond.load429 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5349,9 +5349,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 18 -; CHECK-RV32-NEXT: bltz a3, .LBB61_646 +; CHECK-RV32-NEXT: bltz a3, .LBB61_649 ; CHECK-RV32-NEXT: j .LBB61_117 -; CHECK-RV32-NEXT: .LBB61_646: # %cond.load433 +; CHECK-RV32-NEXT: .LBB61_649: # %cond.load433 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5364,9 +5364,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 17 -; CHECK-RV32-NEXT: bltz a3, .LBB61_647 +; CHECK-RV32-NEXT: bltz a3, .LBB61_650 ; CHECK-RV32-NEXT: j .LBB61_118 -; CHECK-RV32-NEXT: .LBB61_647: # %cond.load437 +; CHECK-RV32-NEXT: .LBB61_650: # %cond.load437 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5379,9 +5379,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 16 -; CHECK-RV32-NEXT: bltz a3, .LBB61_648 +; CHECK-RV32-NEXT: bltz a3, .LBB61_651 ; CHECK-RV32-NEXT: j .LBB61_119 -; CHECK-RV32-NEXT: .LBB61_648: # %cond.load441 +; CHECK-RV32-NEXT: .LBB61_651: # %cond.load441 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5394,9 +5394,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 15 -; CHECK-RV32-NEXT: bltz a3, .LBB61_649 +; CHECK-RV32-NEXT: bltz a3, .LBB61_652 ; CHECK-RV32-NEXT: j .LBB61_120 -; CHECK-RV32-NEXT: .LBB61_649: # %cond.load445 +; CHECK-RV32-NEXT: .LBB61_652: # %cond.load445 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5409,9 +5409,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 14 -; CHECK-RV32-NEXT: bltz a3, .LBB61_650 +; CHECK-RV32-NEXT: bltz a3, .LBB61_653 ; CHECK-RV32-NEXT: j .LBB61_121 -; CHECK-RV32-NEXT: .LBB61_650: # %cond.load449 +; CHECK-RV32-NEXT: .LBB61_653: # %cond.load449 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5424,9 +5424,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 13 -; CHECK-RV32-NEXT: bltz a3, .LBB61_651 +; CHECK-RV32-NEXT: bltz a3, .LBB61_654 ; CHECK-RV32-NEXT: j .LBB61_122 -; CHECK-RV32-NEXT: .LBB61_651: # %cond.load453 +; CHECK-RV32-NEXT: .LBB61_654: # %cond.load453 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5439,9 +5439,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 12 -; CHECK-RV32-NEXT: bltz a3, .LBB61_652 +; CHECK-RV32-NEXT: bltz a3, .LBB61_655 ; CHECK-RV32-NEXT: j .LBB61_123 -; CHECK-RV32-NEXT: .LBB61_652: # %cond.load457 +; CHECK-RV32-NEXT: .LBB61_655: # %cond.load457 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5454,9 +5454,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 11 -; CHECK-RV32-NEXT: bltz a3, .LBB61_653 +; CHECK-RV32-NEXT: bltz a3, .LBB61_656 ; CHECK-RV32-NEXT: j .LBB61_124 -; CHECK-RV32-NEXT: .LBB61_653: # %cond.load461 +; CHECK-RV32-NEXT: .LBB61_656: # %cond.load461 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5469,9 +5469,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 10 -; CHECK-RV32-NEXT: bltz a3, .LBB61_654 +; CHECK-RV32-NEXT: bltz a3, .LBB61_657 ; CHECK-RV32-NEXT: j .LBB61_125 -; CHECK-RV32-NEXT: .LBB61_654: # %cond.load465 +; CHECK-RV32-NEXT: .LBB61_657: # %cond.load465 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5484,9 +5484,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 9 -; CHECK-RV32-NEXT: bltz a3, .LBB61_655 +; CHECK-RV32-NEXT: bltz a3, .LBB61_658 ; CHECK-RV32-NEXT: j .LBB61_126 -; CHECK-RV32-NEXT: .LBB61_655: # %cond.load469 +; CHECK-RV32-NEXT: .LBB61_658: # %cond.load469 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5499,9 +5499,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 8 -; CHECK-RV32-NEXT: bltz a3, .LBB61_656 +; CHECK-RV32-NEXT: bltz a3, .LBB61_659 ; CHECK-RV32-NEXT: j .LBB61_127 -; CHECK-RV32-NEXT: .LBB61_656: # %cond.load473 +; CHECK-RV32-NEXT: .LBB61_659: # %cond.load473 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5514,9 +5514,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 7 -; CHECK-RV32-NEXT: bltz a3, .LBB61_657 +; CHECK-RV32-NEXT: bltz a3, .LBB61_660 ; CHECK-RV32-NEXT: j .LBB61_128 -; CHECK-RV32-NEXT: .LBB61_657: # %cond.load477 +; CHECK-RV32-NEXT: .LBB61_660: # %cond.load477 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5529,9 +5529,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 6 -; CHECK-RV32-NEXT: bltz a3, .LBB61_658 +; CHECK-RV32-NEXT: bltz a3, .LBB61_661 ; CHECK-RV32-NEXT: j .LBB61_129 -; CHECK-RV32-NEXT: .LBB61_658: # %cond.load481 +; CHECK-RV32-NEXT: .LBB61_661: # %cond.load481 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5544,9 +5544,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 5 -; CHECK-RV32-NEXT: bltz a3, .LBB61_659 +; CHECK-RV32-NEXT: bltz a3, .LBB61_662 ; CHECK-RV32-NEXT: j .LBB61_130 -; CHECK-RV32-NEXT: .LBB61_659: # %cond.load485 +; CHECK-RV32-NEXT: .LBB61_662: # %cond.load485 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5559,9 +5559,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 4 -; CHECK-RV32-NEXT: bltz a3, .LBB61_660 +; CHECK-RV32-NEXT: bltz a3, .LBB61_663 ; CHECK-RV32-NEXT: j .LBB61_131 -; CHECK-RV32-NEXT: .LBB61_660: # %cond.load489 +; CHECK-RV32-NEXT: .LBB61_663: # %cond.load489 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5574,9 +5574,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 3 -; CHECK-RV32-NEXT: bltz a3, .LBB61_661 +; CHECK-RV32-NEXT: bltz a3, .LBB61_664 ; CHECK-RV32-NEXT: j .LBB61_132 -; CHECK-RV32-NEXT: .LBB61_661: # %cond.load493 +; CHECK-RV32-NEXT: .LBB61_664: # %cond.load493 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5589,11 +5589,11 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 2 -; CHECK-RV32-NEXT: bgez a3, .LBB61_1028 +; CHECK-RV32-NEXT: bgez a3, .LBB61_665 ; CHECK-RV32-NEXT: j .LBB61_133 -; CHECK-RV32-NEXT: .LBB61_1028: # %cond.load493 +; CHECK-RV32-NEXT: .LBB61_665: # %cond.load493 ; CHECK-RV32-NEXT: j .LBB61_134 -; CHECK-RV32-NEXT: .LBB61_662: # %cond.load505 +; CHECK-RV32-NEXT: .LBB61_666: # %cond.load505 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vmv8r.v v16, v8 ; CHECK-RV32-NEXT: vmv.s.x v10, a2 @@ -5605,9 +5605,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv2r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a2, a3, 1 -; CHECK-RV32-NEXT: bnez a2, .LBB61_663 +; CHECK-RV32-NEXT: bnez a2, .LBB61_667 ; CHECK-RV32-NEXT: j .LBB61_138 -; CHECK-RV32-NEXT: .LBB61_663: # %cond.load509 +; CHECK-RV32-NEXT: .LBB61_667: # %cond.load509 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5620,9 +5620,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a2, a3, 2 -; CHECK-RV32-NEXT: bnez a2, .LBB61_664 +; CHECK-RV32-NEXT: bnez a2, .LBB61_668 ; CHECK-RV32-NEXT: j .LBB61_139 -; CHECK-RV32-NEXT: .LBB61_664: # %cond.load513 +; CHECK-RV32-NEXT: .LBB61_668: # %cond.load513 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5635,9 +5635,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a2, a3, 4 -; CHECK-RV32-NEXT: bnez a2, .LBB61_665 +; CHECK-RV32-NEXT: bnez a2, .LBB61_669 ; CHECK-RV32-NEXT: j .LBB61_140 -; CHECK-RV32-NEXT: .LBB61_665: # %cond.load517 +; CHECK-RV32-NEXT: .LBB61_669: # %cond.load517 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5650,9 +5650,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a2, a3, 8 -; CHECK-RV32-NEXT: bnez a2, .LBB61_666 +; CHECK-RV32-NEXT: bnez a2, .LBB61_670 ; CHECK-RV32-NEXT: j .LBB61_141 -; CHECK-RV32-NEXT: .LBB61_666: # %cond.load521 +; CHECK-RV32-NEXT: .LBB61_670: # %cond.load521 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5665,9 +5665,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a2, a3, 16 -; CHECK-RV32-NEXT: bnez a2, .LBB61_667 +; CHECK-RV32-NEXT: bnez a2, .LBB61_671 ; CHECK-RV32-NEXT: j .LBB61_142 -; CHECK-RV32-NEXT: .LBB61_667: # %cond.load525 +; CHECK-RV32-NEXT: .LBB61_671: # %cond.load525 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5680,9 +5680,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a2, a3, 32 -; CHECK-RV32-NEXT: bnez a2, .LBB61_668 +; CHECK-RV32-NEXT: bnez a2, .LBB61_672 ; CHECK-RV32-NEXT: j .LBB61_143 -; CHECK-RV32-NEXT: .LBB61_668: # %cond.load529 +; CHECK-RV32-NEXT: .LBB61_672: # %cond.load529 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5695,9 +5695,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a2, a3, 64 -; CHECK-RV32-NEXT: bnez a2, .LBB61_669 +; CHECK-RV32-NEXT: bnez a2, .LBB61_673 ; CHECK-RV32-NEXT: j .LBB61_144 -; CHECK-RV32-NEXT: .LBB61_669: # %cond.load533 +; CHECK-RV32-NEXT: .LBB61_673: # %cond.load533 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5710,9 +5710,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a2, a3, 128 -; CHECK-RV32-NEXT: bnez a2, .LBB61_670 +; CHECK-RV32-NEXT: bnez a2, .LBB61_674 ; CHECK-RV32-NEXT: j .LBB61_145 -; CHECK-RV32-NEXT: .LBB61_670: # %cond.load537 +; CHECK-RV32-NEXT: .LBB61_674: # %cond.load537 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5725,9 +5725,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a2, a3, 256 -; CHECK-RV32-NEXT: bnez a2, .LBB61_671 +; CHECK-RV32-NEXT: bnez a2, .LBB61_675 ; CHECK-RV32-NEXT: j .LBB61_146 -; CHECK-RV32-NEXT: .LBB61_671: # %cond.load541 +; CHECK-RV32-NEXT: .LBB61_675: # %cond.load541 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5740,9 +5740,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a2, a3, 512 -; CHECK-RV32-NEXT: bnez a2, .LBB61_672 +; CHECK-RV32-NEXT: bnez a2, .LBB61_676 ; CHECK-RV32-NEXT: j .LBB61_147 -; CHECK-RV32-NEXT: .LBB61_672: # %cond.load545 +; CHECK-RV32-NEXT: .LBB61_676: # %cond.load545 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5755,9 +5755,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a2, a3, 1024 -; CHECK-RV32-NEXT: bnez a2, .LBB61_673 +; CHECK-RV32-NEXT: bnez a2, .LBB61_677 ; CHECK-RV32-NEXT: j .LBB61_148 -; CHECK-RV32-NEXT: .LBB61_673: # %cond.load549 +; CHECK-RV32-NEXT: .LBB61_677: # %cond.load549 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5770,9 +5770,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 20 -; CHECK-RV32-NEXT: bltz a2, .LBB61_674 +; CHECK-RV32-NEXT: bltz a2, .LBB61_678 ; CHECK-RV32-NEXT: j .LBB61_149 -; CHECK-RV32-NEXT: .LBB61_674: # %cond.load553 +; CHECK-RV32-NEXT: .LBB61_678: # %cond.load553 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5785,9 +5785,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 19 -; CHECK-RV32-NEXT: bltz a2, .LBB61_675 +; CHECK-RV32-NEXT: bltz a2, .LBB61_679 ; CHECK-RV32-NEXT: j .LBB61_150 -; CHECK-RV32-NEXT: .LBB61_675: # %cond.load557 +; CHECK-RV32-NEXT: .LBB61_679: # %cond.load557 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5800,9 +5800,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 18 -; CHECK-RV32-NEXT: bltz a2, .LBB61_676 +; CHECK-RV32-NEXT: bltz a2, .LBB61_680 ; CHECK-RV32-NEXT: j .LBB61_151 -; CHECK-RV32-NEXT: .LBB61_676: # %cond.load561 +; CHECK-RV32-NEXT: .LBB61_680: # %cond.load561 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5815,9 +5815,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 17 -; CHECK-RV32-NEXT: bltz a2, .LBB61_677 +; CHECK-RV32-NEXT: bltz a2, .LBB61_681 ; CHECK-RV32-NEXT: j .LBB61_152 -; CHECK-RV32-NEXT: .LBB61_677: # %cond.load565 +; CHECK-RV32-NEXT: .LBB61_681: # %cond.load565 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5830,9 +5830,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 16 -; CHECK-RV32-NEXT: bltz a2, .LBB61_678 +; CHECK-RV32-NEXT: bltz a2, .LBB61_682 ; CHECK-RV32-NEXT: j .LBB61_153 -; CHECK-RV32-NEXT: .LBB61_678: # %cond.load569 +; CHECK-RV32-NEXT: .LBB61_682: # %cond.load569 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5845,9 +5845,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 15 -; CHECK-RV32-NEXT: bltz a2, .LBB61_679 +; CHECK-RV32-NEXT: bltz a2, .LBB61_683 ; CHECK-RV32-NEXT: j .LBB61_154 -; CHECK-RV32-NEXT: .LBB61_679: # %cond.load573 +; CHECK-RV32-NEXT: .LBB61_683: # %cond.load573 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5860,9 +5860,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 14 -; CHECK-RV32-NEXT: bltz a2, .LBB61_680 +; CHECK-RV32-NEXT: bltz a2, .LBB61_684 ; CHECK-RV32-NEXT: j .LBB61_155 -; CHECK-RV32-NEXT: .LBB61_680: # %cond.load577 +; CHECK-RV32-NEXT: .LBB61_684: # %cond.load577 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5875,9 +5875,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 13 -; CHECK-RV32-NEXT: bltz a2, .LBB61_681 +; CHECK-RV32-NEXT: bltz a2, .LBB61_685 ; CHECK-RV32-NEXT: j .LBB61_156 -; CHECK-RV32-NEXT: .LBB61_681: # %cond.load581 +; CHECK-RV32-NEXT: .LBB61_685: # %cond.load581 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5890,9 +5890,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 12 -; CHECK-RV32-NEXT: bltz a2, .LBB61_682 +; CHECK-RV32-NEXT: bltz a2, .LBB61_686 ; CHECK-RV32-NEXT: j .LBB61_157 -; CHECK-RV32-NEXT: .LBB61_682: # %cond.load585 +; CHECK-RV32-NEXT: .LBB61_686: # %cond.load585 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5905,9 +5905,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 11 -; CHECK-RV32-NEXT: bltz a2, .LBB61_683 +; CHECK-RV32-NEXT: bltz a2, .LBB61_687 ; CHECK-RV32-NEXT: j .LBB61_158 -; CHECK-RV32-NEXT: .LBB61_683: # %cond.load589 +; CHECK-RV32-NEXT: .LBB61_687: # %cond.load589 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5920,9 +5920,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 10 -; CHECK-RV32-NEXT: bltz a2, .LBB61_684 +; CHECK-RV32-NEXT: bltz a2, .LBB61_688 ; CHECK-RV32-NEXT: j .LBB61_159 -; CHECK-RV32-NEXT: .LBB61_684: # %cond.load593 +; CHECK-RV32-NEXT: .LBB61_688: # %cond.load593 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5935,9 +5935,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 9 -; CHECK-RV32-NEXT: bltz a2, .LBB61_685 +; CHECK-RV32-NEXT: bltz a2, .LBB61_689 ; CHECK-RV32-NEXT: j .LBB61_160 -; CHECK-RV32-NEXT: .LBB61_685: # %cond.load597 +; CHECK-RV32-NEXT: .LBB61_689: # %cond.load597 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5950,9 +5950,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 8 -; CHECK-RV32-NEXT: bltz a2, .LBB61_686 +; CHECK-RV32-NEXT: bltz a2, .LBB61_690 ; CHECK-RV32-NEXT: j .LBB61_161 -; CHECK-RV32-NEXT: .LBB61_686: # %cond.load601 +; CHECK-RV32-NEXT: .LBB61_690: # %cond.load601 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5965,9 +5965,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 7 -; CHECK-RV32-NEXT: bltz a2, .LBB61_687 +; CHECK-RV32-NEXT: bltz a2, .LBB61_691 ; CHECK-RV32-NEXT: j .LBB61_162 -; CHECK-RV32-NEXT: .LBB61_687: # %cond.load605 +; CHECK-RV32-NEXT: .LBB61_691: # %cond.load605 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5980,9 +5980,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 6 -; CHECK-RV32-NEXT: bltz a2, .LBB61_688 +; CHECK-RV32-NEXT: bltz a2, .LBB61_692 ; CHECK-RV32-NEXT: j .LBB61_163 -; CHECK-RV32-NEXT: .LBB61_688: # %cond.load609 +; CHECK-RV32-NEXT: .LBB61_692: # %cond.load609 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -5995,9 +5995,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 5 -; CHECK-RV32-NEXT: bltz a2, .LBB61_689 +; CHECK-RV32-NEXT: bltz a2, .LBB61_693 ; CHECK-RV32-NEXT: j .LBB61_164 -; CHECK-RV32-NEXT: .LBB61_689: # %cond.load613 +; CHECK-RV32-NEXT: .LBB61_693: # %cond.load613 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6010,9 +6010,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 4 -; CHECK-RV32-NEXT: bltz a2, .LBB61_690 +; CHECK-RV32-NEXT: bltz a2, .LBB61_694 ; CHECK-RV32-NEXT: j .LBB61_165 -; CHECK-RV32-NEXT: .LBB61_690: # %cond.load617 +; CHECK-RV32-NEXT: .LBB61_694: # %cond.load617 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6025,9 +6025,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 3 -; CHECK-RV32-NEXT: bltz a2, .LBB61_691 +; CHECK-RV32-NEXT: bltz a2, .LBB61_695 ; CHECK-RV32-NEXT: j .LBB61_166 -; CHECK-RV32-NEXT: .LBB61_691: # %cond.load621 +; CHECK-RV32-NEXT: .LBB61_695: # %cond.load621 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6040,11 +6040,11 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 2 -; CHECK-RV32-NEXT: bgez a2, .LBB61_1029 +; CHECK-RV32-NEXT: bgez a2, .LBB61_696 ; CHECK-RV32-NEXT: j .LBB61_167 -; CHECK-RV32-NEXT: .LBB61_1029: # %cond.load621 +; CHECK-RV32-NEXT: .LBB61_696: # %cond.load621 ; CHECK-RV32-NEXT: j .LBB61_168 -; CHECK-RV32-NEXT: .LBB61_692: # %cond.load633 +; CHECK-RV32-NEXT: .LBB61_697: # %cond.load633 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vmv8r.v v16, v8 ; CHECK-RV32-NEXT: vmv.s.x v12, a3 @@ -6056,9 +6056,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 1 -; CHECK-RV32-NEXT: bnez a3, .LBB61_693 +; CHECK-RV32-NEXT: bnez a3, .LBB61_698 ; CHECK-RV32-NEXT: j .LBB61_172 -; CHECK-RV32-NEXT: .LBB61_693: # %cond.load637 +; CHECK-RV32-NEXT: .LBB61_698: # %cond.load637 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6071,9 +6071,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 2 -; CHECK-RV32-NEXT: bnez a3, .LBB61_694 +; CHECK-RV32-NEXT: bnez a3, .LBB61_699 ; CHECK-RV32-NEXT: j .LBB61_173 -; CHECK-RV32-NEXT: .LBB61_694: # %cond.load641 +; CHECK-RV32-NEXT: .LBB61_699: # %cond.load641 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6086,9 +6086,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 4 -; CHECK-RV32-NEXT: bnez a3, .LBB61_695 +; CHECK-RV32-NEXT: bnez a3, .LBB61_700 ; CHECK-RV32-NEXT: j .LBB61_174 -; CHECK-RV32-NEXT: .LBB61_695: # %cond.load645 +; CHECK-RV32-NEXT: .LBB61_700: # %cond.load645 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6101,9 +6101,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 8 -; CHECK-RV32-NEXT: bnez a3, .LBB61_696 +; CHECK-RV32-NEXT: bnez a3, .LBB61_701 ; CHECK-RV32-NEXT: j .LBB61_175 -; CHECK-RV32-NEXT: .LBB61_696: # %cond.load649 +; CHECK-RV32-NEXT: .LBB61_701: # %cond.load649 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6116,9 +6116,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 16 -; CHECK-RV32-NEXT: bnez a3, .LBB61_697 +; CHECK-RV32-NEXT: bnez a3, .LBB61_702 ; CHECK-RV32-NEXT: j .LBB61_176 -; CHECK-RV32-NEXT: .LBB61_697: # %cond.load653 +; CHECK-RV32-NEXT: .LBB61_702: # %cond.load653 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6131,9 +6131,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 32 -; CHECK-RV32-NEXT: bnez a3, .LBB61_698 +; CHECK-RV32-NEXT: bnez a3, .LBB61_703 ; CHECK-RV32-NEXT: j .LBB61_177 -; CHECK-RV32-NEXT: .LBB61_698: # %cond.load657 +; CHECK-RV32-NEXT: .LBB61_703: # %cond.load657 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6146,9 +6146,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 64 -; CHECK-RV32-NEXT: bnez a3, .LBB61_699 +; CHECK-RV32-NEXT: bnez a3, .LBB61_704 ; CHECK-RV32-NEXT: j .LBB61_178 -; CHECK-RV32-NEXT: .LBB61_699: # %cond.load661 +; CHECK-RV32-NEXT: .LBB61_704: # %cond.load661 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6161,9 +6161,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 128 -; CHECK-RV32-NEXT: bnez a3, .LBB61_700 +; CHECK-RV32-NEXT: bnez a3, .LBB61_705 ; CHECK-RV32-NEXT: j .LBB61_179 -; CHECK-RV32-NEXT: .LBB61_700: # %cond.load665 +; CHECK-RV32-NEXT: .LBB61_705: # %cond.load665 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6176,9 +6176,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 256 -; CHECK-RV32-NEXT: bnez a3, .LBB61_701 +; CHECK-RV32-NEXT: bnez a3, .LBB61_706 ; CHECK-RV32-NEXT: j .LBB61_180 -; CHECK-RV32-NEXT: .LBB61_701: # %cond.load669 +; CHECK-RV32-NEXT: .LBB61_706: # %cond.load669 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6191,9 +6191,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 512 -; CHECK-RV32-NEXT: bnez a3, .LBB61_702 +; CHECK-RV32-NEXT: bnez a3, .LBB61_707 ; CHECK-RV32-NEXT: j .LBB61_181 -; CHECK-RV32-NEXT: .LBB61_702: # %cond.load673 +; CHECK-RV32-NEXT: .LBB61_707: # %cond.load673 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6206,9 +6206,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 1024 -; CHECK-RV32-NEXT: bnez a3, .LBB61_703 +; CHECK-RV32-NEXT: bnez a3, .LBB61_708 ; CHECK-RV32-NEXT: j .LBB61_182 -; CHECK-RV32-NEXT: .LBB61_703: # %cond.load677 +; CHECK-RV32-NEXT: .LBB61_708: # %cond.load677 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6221,9 +6221,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 20 -; CHECK-RV32-NEXT: bltz a3, .LBB61_704 +; CHECK-RV32-NEXT: bltz a3, .LBB61_709 ; CHECK-RV32-NEXT: j .LBB61_183 -; CHECK-RV32-NEXT: .LBB61_704: # %cond.load681 +; CHECK-RV32-NEXT: .LBB61_709: # %cond.load681 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6236,9 +6236,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 19 -; CHECK-RV32-NEXT: bltz a3, .LBB61_705 +; CHECK-RV32-NEXT: bltz a3, .LBB61_710 ; CHECK-RV32-NEXT: j .LBB61_184 -; CHECK-RV32-NEXT: .LBB61_705: # %cond.load685 +; CHECK-RV32-NEXT: .LBB61_710: # %cond.load685 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6251,9 +6251,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 18 -; CHECK-RV32-NEXT: bltz a3, .LBB61_706 +; CHECK-RV32-NEXT: bltz a3, .LBB61_711 ; CHECK-RV32-NEXT: j .LBB61_185 -; CHECK-RV32-NEXT: .LBB61_706: # %cond.load689 +; CHECK-RV32-NEXT: .LBB61_711: # %cond.load689 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6266,9 +6266,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 17 -; CHECK-RV32-NEXT: bltz a3, .LBB61_707 +; CHECK-RV32-NEXT: bltz a3, .LBB61_712 ; CHECK-RV32-NEXT: j .LBB61_186 -; CHECK-RV32-NEXT: .LBB61_707: # %cond.load693 +; CHECK-RV32-NEXT: .LBB61_712: # %cond.load693 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6281,9 +6281,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 16 -; CHECK-RV32-NEXT: bltz a3, .LBB61_708 +; CHECK-RV32-NEXT: bltz a3, .LBB61_713 ; CHECK-RV32-NEXT: j .LBB61_187 -; CHECK-RV32-NEXT: .LBB61_708: # %cond.load697 +; CHECK-RV32-NEXT: .LBB61_713: # %cond.load697 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6296,9 +6296,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 15 -; CHECK-RV32-NEXT: bltz a3, .LBB61_709 +; CHECK-RV32-NEXT: bltz a3, .LBB61_714 ; CHECK-RV32-NEXT: j .LBB61_188 -; CHECK-RV32-NEXT: .LBB61_709: # %cond.load701 +; CHECK-RV32-NEXT: .LBB61_714: # %cond.load701 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6311,9 +6311,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 14 -; CHECK-RV32-NEXT: bltz a3, .LBB61_710 +; CHECK-RV32-NEXT: bltz a3, .LBB61_715 ; CHECK-RV32-NEXT: j .LBB61_189 -; CHECK-RV32-NEXT: .LBB61_710: # %cond.load705 +; CHECK-RV32-NEXT: .LBB61_715: # %cond.load705 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6326,9 +6326,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 13 -; CHECK-RV32-NEXT: bltz a3, .LBB61_711 +; CHECK-RV32-NEXT: bltz a3, .LBB61_716 ; CHECK-RV32-NEXT: j .LBB61_190 -; CHECK-RV32-NEXT: .LBB61_711: # %cond.load709 +; CHECK-RV32-NEXT: .LBB61_716: # %cond.load709 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6341,9 +6341,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 12 -; CHECK-RV32-NEXT: bltz a3, .LBB61_712 +; CHECK-RV32-NEXT: bltz a3, .LBB61_717 ; CHECK-RV32-NEXT: j .LBB61_191 -; CHECK-RV32-NEXT: .LBB61_712: # %cond.load713 +; CHECK-RV32-NEXT: .LBB61_717: # %cond.load713 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6356,9 +6356,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 11 -; CHECK-RV32-NEXT: bltz a3, .LBB61_713 +; CHECK-RV32-NEXT: bltz a3, .LBB61_718 ; CHECK-RV32-NEXT: j .LBB61_192 -; CHECK-RV32-NEXT: .LBB61_713: # %cond.load717 +; CHECK-RV32-NEXT: .LBB61_718: # %cond.load717 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6371,9 +6371,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 10 -; CHECK-RV32-NEXT: bltz a3, .LBB61_714 +; CHECK-RV32-NEXT: bltz a3, .LBB61_719 ; CHECK-RV32-NEXT: j .LBB61_193 -; CHECK-RV32-NEXT: .LBB61_714: # %cond.load721 +; CHECK-RV32-NEXT: .LBB61_719: # %cond.load721 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6386,9 +6386,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 9 -; CHECK-RV32-NEXT: bltz a3, .LBB61_715 +; CHECK-RV32-NEXT: bltz a3, .LBB61_720 ; CHECK-RV32-NEXT: j .LBB61_194 -; CHECK-RV32-NEXT: .LBB61_715: # %cond.load725 +; CHECK-RV32-NEXT: .LBB61_720: # %cond.load725 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6401,9 +6401,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 8 -; CHECK-RV32-NEXT: bltz a3, .LBB61_716 +; CHECK-RV32-NEXT: bltz a3, .LBB61_721 ; CHECK-RV32-NEXT: j .LBB61_195 -; CHECK-RV32-NEXT: .LBB61_716: # %cond.load729 +; CHECK-RV32-NEXT: .LBB61_721: # %cond.load729 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6416,9 +6416,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 7 -; CHECK-RV32-NEXT: bltz a3, .LBB61_717 +; CHECK-RV32-NEXT: bltz a3, .LBB61_722 ; CHECK-RV32-NEXT: j .LBB61_196 -; CHECK-RV32-NEXT: .LBB61_717: # %cond.load733 +; CHECK-RV32-NEXT: .LBB61_722: # %cond.load733 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6431,9 +6431,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 6 -; CHECK-RV32-NEXT: bltz a3, .LBB61_718 +; CHECK-RV32-NEXT: bltz a3, .LBB61_723 ; CHECK-RV32-NEXT: j .LBB61_197 -; CHECK-RV32-NEXT: .LBB61_718: # %cond.load737 +; CHECK-RV32-NEXT: .LBB61_723: # %cond.load737 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6446,9 +6446,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 5 -; CHECK-RV32-NEXT: bltz a3, .LBB61_719 +; CHECK-RV32-NEXT: bltz a3, .LBB61_724 ; CHECK-RV32-NEXT: j .LBB61_198 -; CHECK-RV32-NEXT: .LBB61_719: # %cond.load741 +; CHECK-RV32-NEXT: .LBB61_724: # %cond.load741 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6461,9 +6461,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 4 -; CHECK-RV32-NEXT: bltz a3, .LBB61_720 +; CHECK-RV32-NEXT: bltz a3, .LBB61_725 ; CHECK-RV32-NEXT: j .LBB61_199 -; CHECK-RV32-NEXT: .LBB61_720: # %cond.load745 +; CHECK-RV32-NEXT: .LBB61_725: # %cond.load745 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6476,9 +6476,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 3 -; CHECK-RV32-NEXT: bltz a3, .LBB61_721 +; CHECK-RV32-NEXT: bltz a3, .LBB61_726 ; CHECK-RV32-NEXT: j .LBB61_200 -; CHECK-RV32-NEXT: .LBB61_721: # %cond.load749 +; CHECK-RV32-NEXT: .LBB61_726: # %cond.load749 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6491,11 +6491,11 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 2 -; CHECK-RV32-NEXT: bgez a3, .LBB61_1030 +; CHECK-RV32-NEXT: bgez a3, .LBB61_727 ; CHECK-RV32-NEXT: j .LBB61_201 -; CHECK-RV32-NEXT: .LBB61_1030: # %cond.load749 +; CHECK-RV32-NEXT: .LBB61_727: # %cond.load749 ; CHECK-RV32-NEXT: j .LBB61_202 -; CHECK-RV32-NEXT: .LBB61_722: # %cond.load761 +; CHECK-RV32-NEXT: .LBB61_728: # %cond.load761 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vmv8r.v v16, v8 ; CHECK-RV32-NEXT: vmv.s.x v12, a2 @@ -6507,9 +6507,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a2, a3, 1 -; CHECK-RV32-NEXT: bnez a2, .LBB61_723 +; CHECK-RV32-NEXT: bnez a2, .LBB61_729 ; CHECK-RV32-NEXT: j .LBB61_206 -; CHECK-RV32-NEXT: .LBB61_723: # %cond.load765 +; CHECK-RV32-NEXT: .LBB61_729: # %cond.load765 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6522,9 +6522,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a2, a3, 2 -; CHECK-RV32-NEXT: bnez a2, .LBB61_724 +; CHECK-RV32-NEXT: bnez a2, .LBB61_730 ; CHECK-RV32-NEXT: j .LBB61_207 -; CHECK-RV32-NEXT: .LBB61_724: # %cond.load769 +; CHECK-RV32-NEXT: .LBB61_730: # %cond.load769 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6537,9 +6537,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a2, a3, 4 -; CHECK-RV32-NEXT: bnez a2, .LBB61_725 +; CHECK-RV32-NEXT: bnez a2, .LBB61_731 ; CHECK-RV32-NEXT: j .LBB61_208 -; CHECK-RV32-NEXT: .LBB61_725: # %cond.load773 +; CHECK-RV32-NEXT: .LBB61_731: # %cond.load773 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6552,9 +6552,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a2, a3, 8 -; CHECK-RV32-NEXT: bnez a2, .LBB61_726 +; CHECK-RV32-NEXT: bnez a2, .LBB61_732 ; CHECK-RV32-NEXT: j .LBB61_209 -; CHECK-RV32-NEXT: .LBB61_726: # %cond.load777 +; CHECK-RV32-NEXT: .LBB61_732: # %cond.load777 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6567,9 +6567,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a2, a3, 16 -; CHECK-RV32-NEXT: bnez a2, .LBB61_727 +; CHECK-RV32-NEXT: bnez a2, .LBB61_733 ; CHECK-RV32-NEXT: j .LBB61_210 -; CHECK-RV32-NEXT: .LBB61_727: # %cond.load781 +; CHECK-RV32-NEXT: .LBB61_733: # %cond.load781 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6582,9 +6582,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a2, a3, 32 -; CHECK-RV32-NEXT: bnez a2, .LBB61_728 +; CHECK-RV32-NEXT: bnez a2, .LBB61_734 ; CHECK-RV32-NEXT: j .LBB61_211 -; CHECK-RV32-NEXT: .LBB61_728: # %cond.load785 +; CHECK-RV32-NEXT: .LBB61_734: # %cond.load785 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6597,9 +6597,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a2, a3, 64 -; CHECK-RV32-NEXT: bnez a2, .LBB61_729 +; CHECK-RV32-NEXT: bnez a2, .LBB61_735 ; CHECK-RV32-NEXT: j .LBB61_212 -; CHECK-RV32-NEXT: .LBB61_729: # %cond.load789 +; CHECK-RV32-NEXT: .LBB61_735: # %cond.load789 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6612,9 +6612,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a2, a3, 128 -; CHECK-RV32-NEXT: bnez a2, .LBB61_730 +; CHECK-RV32-NEXT: bnez a2, .LBB61_736 ; CHECK-RV32-NEXT: j .LBB61_213 -; CHECK-RV32-NEXT: .LBB61_730: # %cond.load793 +; CHECK-RV32-NEXT: .LBB61_736: # %cond.load793 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6627,9 +6627,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a2, a3, 256 -; CHECK-RV32-NEXT: bnez a2, .LBB61_731 +; CHECK-RV32-NEXT: bnez a2, .LBB61_737 ; CHECK-RV32-NEXT: j .LBB61_214 -; CHECK-RV32-NEXT: .LBB61_731: # %cond.load797 +; CHECK-RV32-NEXT: .LBB61_737: # %cond.load797 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6642,9 +6642,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a2, a3, 512 -; CHECK-RV32-NEXT: bnez a2, .LBB61_732 +; CHECK-RV32-NEXT: bnez a2, .LBB61_738 ; CHECK-RV32-NEXT: j .LBB61_215 -; CHECK-RV32-NEXT: .LBB61_732: # %cond.load801 +; CHECK-RV32-NEXT: .LBB61_738: # %cond.load801 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6657,9 +6657,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a2, a3, 1024 -; CHECK-RV32-NEXT: bnez a2, .LBB61_733 +; CHECK-RV32-NEXT: bnez a2, .LBB61_739 ; CHECK-RV32-NEXT: j .LBB61_216 -; CHECK-RV32-NEXT: .LBB61_733: # %cond.load805 +; CHECK-RV32-NEXT: .LBB61_739: # %cond.load805 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6672,9 +6672,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 20 -; CHECK-RV32-NEXT: bltz a2, .LBB61_734 +; CHECK-RV32-NEXT: bltz a2, .LBB61_740 ; CHECK-RV32-NEXT: j .LBB61_217 -; CHECK-RV32-NEXT: .LBB61_734: # %cond.load809 +; CHECK-RV32-NEXT: .LBB61_740: # %cond.load809 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6687,9 +6687,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 19 -; CHECK-RV32-NEXT: bltz a2, .LBB61_735 +; CHECK-RV32-NEXT: bltz a2, .LBB61_741 ; CHECK-RV32-NEXT: j .LBB61_218 -; CHECK-RV32-NEXT: .LBB61_735: # %cond.load813 +; CHECK-RV32-NEXT: .LBB61_741: # %cond.load813 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6702,9 +6702,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 18 -; CHECK-RV32-NEXT: bltz a2, .LBB61_736 +; CHECK-RV32-NEXT: bltz a2, .LBB61_742 ; CHECK-RV32-NEXT: j .LBB61_219 -; CHECK-RV32-NEXT: .LBB61_736: # %cond.load817 +; CHECK-RV32-NEXT: .LBB61_742: # %cond.load817 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6717,9 +6717,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 17 -; CHECK-RV32-NEXT: bltz a2, .LBB61_737 +; CHECK-RV32-NEXT: bltz a2, .LBB61_743 ; CHECK-RV32-NEXT: j .LBB61_220 -; CHECK-RV32-NEXT: .LBB61_737: # %cond.load821 +; CHECK-RV32-NEXT: .LBB61_743: # %cond.load821 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6732,9 +6732,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 16 -; CHECK-RV32-NEXT: bltz a2, .LBB61_738 +; CHECK-RV32-NEXT: bltz a2, .LBB61_744 ; CHECK-RV32-NEXT: j .LBB61_221 -; CHECK-RV32-NEXT: .LBB61_738: # %cond.load825 +; CHECK-RV32-NEXT: .LBB61_744: # %cond.load825 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6747,9 +6747,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 15 -; CHECK-RV32-NEXT: bltz a2, .LBB61_739 +; CHECK-RV32-NEXT: bltz a2, .LBB61_745 ; CHECK-RV32-NEXT: j .LBB61_222 -; CHECK-RV32-NEXT: .LBB61_739: # %cond.load829 +; CHECK-RV32-NEXT: .LBB61_745: # %cond.load829 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6762,9 +6762,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 14 -; CHECK-RV32-NEXT: bltz a2, .LBB61_740 +; CHECK-RV32-NEXT: bltz a2, .LBB61_746 ; CHECK-RV32-NEXT: j .LBB61_223 -; CHECK-RV32-NEXT: .LBB61_740: # %cond.load833 +; CHECK-RV32-NEXT: .LBB61_746: # %cond.load833 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6777,9 +6777,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 13 -; CHECK-RV32-NEXT: bltz a2, .LBB61_741 +; CHECK-RV32-NEXT: bltz a2, .LBB61_747 ; CHECK-RV32-NEXT: j .LBB61_224 -; CHECK-RV32-NEXT: .LBB61_741: # %cond.load837 +; CHECK-RV32-NEXT: .LBB61_747: # %cond.load837 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6792,9 +6792,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 12 -; CHECK-RV32-NEXT: bltz a2, .LBB61_742 +; CHECK-RV32-NEXT: bltz a2, .LBB61_748 ; CHECK-RV32-NEXT: j .LBB61_225 -; CHECK-RV32-NEXT: .LBB61_742: # %cond.load841 +; CHECK-RV32-NEXT: .LBB61_748: # %cond.load841 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6807,9 +6807,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 11 -; CHECK-RV32-NEXT: bltz a2, .LBB61_743 +; CHECK-RV32-NEXT: bltz a2, .LBB61_749 ; CHECK-RV32-NEXT: j .LBB61_226 -; CHECK-RV32-NEXT: .LBB61_743: # %cond.load845 +; CHECK-RV32-NEXT: .LBB61_749: # %cond.load845 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6822,9 +6822,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 10 -; CHECK-RV32-NEXT: bltz a2, .LBB61_744 +; CHECK-RV32-NEXT: bltz a2, .LBB61_750 ; CHECK-RV32-NEXT: j .LBB61_227 -; CHECK-RV32-NEXT: .LBB61_744: # %cond.load849 +; CHECK-RV32-NEXT: .LBB61_750: # %cond.load849 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6837,9 +6837,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 9 -; CHECK-RV32-NEXT: bltz a2, .LBB61_745 +; CHECK-RV32-NEXT: bltz a2, .LBB61_751 ; CHECK-RV32-NEXT: j .LBB61_228 -; CHECK-RV32-NEXT: .LBB61_745: # %cond.load853 +; CHECK-RV32-NEXT: .LBB61_751: # %cond.load853 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6852,9 +6852,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 8 -; CHECK-RV32-NEXT: bltz a2, .LBB61_746 +; CHECK-RV32-NEXT: bltz a2, .LBB61_752 ; CHECK-RV32-NEXT: j .LBB61_229 -; CHECK-RV32-NEXT: .LBB61_746: # %cond.load857 +; CHECK-RV32-NEXT: .LBB61_752: # %cond.load857 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6867,9 +6867,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 7 -; CHECK-RV32-NEXT: bltz a2, .LBB61_747 +; CHECK-RV32-NEXT: bltz a2, .LBB61_753 ; CHECK-RV32-NEXT: j .LBB61_230 -; CHECK-RV32-NEXT: .LBB61_747: # %cond.load861 +; CHECK-RV32-NEXT: .LBB61_753: # %cond.load861 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6882,9 +6882,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 6 -; CHECK-RV32-NEXT: bltz a2, .LBB61_748 +; CHECK-RV32-NEXT: bltz a2, .LBB61_754 ; CHECK-RV32-NEXT: j .LBB61_231 -; CHECK-RV32-NEXT: .LBB61_748: # %cond.load865 +; CHECK-RV32-NEXT: .LBB61_754: # %cond.load865 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6897,9 +6897,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 5 -; CHECK-RV32-NEXT: bltz a2, .LBB61_749 +; CHECK-RV32-NEXT: bltz a2, .LBB61_755 ; CHECK-RV32-NEXT: j .LBB61_232 -; CHECK-RV32-NEXT: .LBB61_749: # %cond.load869 +; CHECK-RV32-NEXT: .LBB61_755: # %cond.load869 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6912,9 +6912,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 4 -; CHECK-RV32-NEXT: bltz a2, .LBB61_750 +; CHECK-RV32-NEXT: bltz a2, .LBB61_756 ; CHECK-RV32-NEXT: j .LBB61_233 -; CHECK-RV32-NEXT: .LBB61_750: # %cond.load873 +; CHECK-RV32-NEXT: .LBB61_756: # %cond.load873 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6927,9 +6927,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 3 -; CHECK-RV32-NEXT: bltz a2, .LBB61_751 +; CHECK-RV32-NEXT: bltz a2, .LBB61_757 ; CHECK-RV32-NEXT: j .LBB61_234 -; CHECK-RV32-NEXT: .LBB61_751: # %cond.load877 +; CHECK-RV32-NEXT: .LBB61_757: # %cond.load877 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6942,11 +6942,11 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a2, a3, 2 -; CHECK-RV32-NEXT: bgez a2, .LBB61_1031 +; CHECK-RV32-NEXT: bgez a2, .LBB61_758 ; CHECK-RV32-NEXT: j .LBB61_235 -; CHECK-RV32-NEXT: .LBB61_1031: # %cond.load877 +; CHECK-RV32-NEXT: .LBB61_758: # %cond.load877 ; CHECK-RV32-NEXT: j .LBB61_236 -; CHECK-RV32-NEXT: .LBB61_752: # %cond.load889 +; CHECK-RV32-NEXT: .LBB61_759: # %cond.load889 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vmv8r.v v16, v8 ; CHECK-RV32-NEXT: vmv.s.x v12, a3 @@ -6958,9 +6958,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 1 -; CHECK-RV32-NEXT: bnez a3, .LBB61_753 +; CHECK-RV32-NEXT: bnez a3, .LBB61_760 ; CHECK-RV32-NEXT: j .LBB61_240 -; CHECK-RV32-NEXT: .LBB61_753: # %cond.load893 +; CHECK-RV32-NEXT: .LBB61_760: # %cond.load893 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6973,9 +6973,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 2 -; CHECK-RV32-NEXT: bnez a3, .LBB61_754 +; CHECK-RV32-NEXT: bnez a3, .LBB61_761 ; CHECK-RV32-NEXT: j .LBB61_241 -; CHECK-RV32-NEXT: .LBB61_754: # %cond.load897 +; CHECK-RV32-NEXT: .LBB61_761: # %cond.load897 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -6988,9 +6988,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 4 -; CHECK-RV32-NEXT: bnez a3, .LBB61_755 +; CHECK-RV32-NEXT: bnez a3, .LBB61_762 ; CHECK-RV32-NEXT: j .LBB61_242 -; CHECK-RV32-NEXT: .LBB61_755: # %cond.load901 +; CHECK-RV32-NEXT: .LBB61_762: # %cond.load901 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -7003,9 +7003,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 8 -; CHECK-RV32-NEXT: bnez a3, .LBB61_756 +; CHECK-RV32-NEXT: bnez a3, .LBB61_763 ; CHECK-RV32-NEXT: j .LBB61_243 -; CHECK-RV32-NEXT: .LBB61_756: # %cond.load905 +; CHECK-RV32-NEXT: .LBB61_763: # %cond.load905 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -7018,9 +7018,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 16 -; CHECK-RV32-NEXT: bnez a3, .LBB61_757 +; CHECK-RV32-NEXT: bnez a3, .LBB61_764 ; CHECK-RV32-NEXT: j .LBB61_244 -; CHECK-RV32-NEXT: .LBB61_757: # %cond.load909 +; CHECK-RV32-NEXT: .LBB61_764: # %cond.load909 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -7033,9 +7033,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 32 -; CHECK-RV32-NEXT: bnez a3, .LBB61_758 +; CHECK-RV32-NEXT: bnez a3, .LBB61_765 ; CHECK-RV32-NEXT: j .LBB61_245 -; CHECK-RV32-NEXT: .LBB61_758: # %cond.load913 +; CHECK-RV32-NEXT: .LBB61_765: # %cond.load913 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -7048,9 +7048,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 64 -; CHECK-RV32-NEXT: bnez a3, .LBB61_759 +; CHECK-RV32-NEXT: bnez a3, .LBB61_766 ; CHECK-RV32-NEXT: j .LBB61_246 -; CHECK-RV32-NEXT: .LBB61_759: # %cond.load917 +; CHECK-RV32-NEXT: .LBB61_766: # %cond.load917 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -7063,9 +7063,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 128 -; CHECK-RV32-NEXT: bnez a3, .LBB61_760 +; CHECK-RV32-NEXT: bnez a3, .LBB61_767 ; CHECK-RV32-NEXT: j .LBB61_247 -; CHECK-RV32-NEXT: .LBB61_760: # %cond.load921 +; CHECK-RV32-NEXT: .LBB61_767: # %cond.load921 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -7078,9 +7078,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 256 -; CHECK-RV32-NEXT: bnez a3, .LBB61_761 +; CHECK-RV32-NEXT: bnez a3, .LBB61_768 ; CHECK-RV32-NEXT: j .LBB61_248 -; CHECK-RV32-NEXT: .LBB61_761: # %cond.load925 +; CHECK-RV32-NEXT: .LBB61_768: # %cond.load925 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -7093,9 +7093,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 512 -; CHECK-RV32-NEXT: bnez a3, .LBB61_762 +; CHECK-RV32-NEXT: bnez a3, .LBB61_769 ; CHECK-RV32-NEXT: j .LBB61_249 -; CHECK-RV32-NEXT: .LBB61_762: # %cond.load929 +; CHECK-RV32-NEXT: .LBB61_769: # %cond.load929 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -7108,9 +7108,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a3, a2, 1024 -; CHECK-RV32-NEXT: bnez a3, .LBB61_763 +; CHECK-RV32-NEXT: bnez a3, .LBB61_770 ; CHECK-RV32-NEXT: j .LBB61_250 -; CHECK-RV32-NEXT: .LBB61_763: # %cond.load933 +; CHECK-RV32-NEXT: .LBB61_770: # %cond.load933 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -7123,9 +7123,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 20 -; CHECK-RV32-NEXT: bltz a3, .LBB61_764 +; CHECK-RV32-NEXT: bltz a3, .LBB61_771 ; CHECK-RV32-NEXT: j .LBB61_251 -; CHECK-RV32-NEXT: .LBB61_764: # %cond.load937 +; CHECK-RV32-NEXT: .LBB61_771: # %cond.load937 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -7138,9 +7138,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 19 -; CHECK-RV32-NEXT: bltz a3, .LBB61_765 +; CHECK-RV32-NEXT: bltz a3, .LBB61_772 ; CHECK-RV32-NEXT: j .LBB61_252 -; CHECK-RV32-NEXT: .LBB61_765: # %cond.load941 +; CHECK-RV32-NEXT: .LBB61_772: # %cond.load941 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -7153,9 +7153,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 18 -; CHECK-RV32-NEXT: bltz a3, .LBB61_766 +; CHECK-RV32-NEXT: bltz a3, .LBB61_773 ; CHECK-RV32-NEXT: j .LBB61_253 -; CHECK-RV32-NEXT: .LBB61_766: # %cond.load945 +; CHECK-RV32-NEXT: .LBB61_773: # %cond.load945 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -7168,9 +7168,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 17 -; CHECK-RV32-NEXT: bltz a3, .LBB61_767 +; CHECK-RV32-NEXT: bltz a3, .LBB61_774 ; CHECK-RV32-NEXT: j .LBB61_254 -; CHECK-RV32-NEXT: .LBB61_767: # %cond.load949 +; CHECK-RV32-NEXT: .LBB61_774: # %cond.load949 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -7183,9 +7183,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 16 -; CHECK-RV32-NEXT: bltz a3, .LBB61_768 +; CHECK-RV32-NEXT: bltz a3, .LBB61_775 ; CHECK-RV32-NEXT: j .LBB61_255 -; CHECK-RV32-NEXT: .LBB61_768: # %cond.load953 +; CHECK-RV32-NEXT: .LBB61_775: # %cond.load953 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -7198,9 +7198,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 15 -; CHECK-RV32-NEXT: bltz a3, .LBB61_769 +; CHECK-RV32-NEXT: bltz a3, .LBB61_776 ; CHECK-RV32-NEXT: j .LBB61_256 -; CHECK-RV32-NEXT: .LBB61_769: # %cond.load957 +; CHECK-RV32-NEXT: .LBB61_776: # %cond.load957 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -7213,9 +7213,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 14 -; CHECK-RV32-NEXT: bltz a3, .LBB61_770 +; CHECK-RV32-NEXT: bltz a3, .LBB61_777 ; CHECK-RV32-NEXT: j .LBB61_257 -; CHECK-RV32-NEXT: .LBB61_770: # %cond.load961 +; CHECK-RV32-NEXT: .LBB61_777: # %cond.load961 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -7228,9 +7228,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 13 -; CHECK-RV32-NEXT: bltz a3, .LBB61_771 +; CHECK-RV32-NEXT: bltz a3, .LBB61_778 ; CHECK-RV32-NEXT: j .LBB61_258 -; CHECK-RV32-NEXT: .LBB61_771: # %cond.load965 +; CHECK-RV32-NEXT: .LBB61_778: # %cond.load965 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -7243,9 +7243,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 12 -; CHECK-RV32-NEXT: bltz a3, .LBB61_772 +; CHECK-RV32-NEXT: bltz a3, .LBB61_779 ; CHECK-RV32-NEXT: j .LBB61_259 -; CHECK-RV32-NEXT: .LBB61_772: # %cond.load969 +; CHECK-RV32-NEXT: .LBB61_779: # %cond.load969 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -7258,9 +7258,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 11 -; CHECK-RV32-NEXT: bltz a3, .LBB61_773 +; CHECK-RV32-NEXT: bltz a3, .LBB61_780 ; CHECK-RV32-NEXT: j .LBB61_260 -; CHECK-RV32-NEXT: .LBB61_773: # %cond.load973 +; CHECK-RV32-NEXT: .LBB61_780: # %cond.load973 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -7273,9 +7273,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 10 -; CHECK-RV32-NEXT: bltz a3, .LBB61_774 +; CHECK-RV32-NEXT: bltz a3, .LBB61_781 ; CHECK-RV32-NEXT: j .LBB61_261 -; CHECK-RV32-NEXT: .LBB61_774: # %cond.load977 +; CHECK-RV32-NEXT: .LBB61_781: # %cond.load977 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -7288,9 +7288,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 9 -; CHECK-RV32-NEXT: bltz a3, .LBB61_775 +; CHECK-RV32-NEXT: bltz a3, .LBB61_782 ; CHECK-RV32-NEXT: j .LBB61_262 -; CHECK-RV32-NEXT: .LBB61_775: # %cond.load981 +; CHECK-RV32-NEXT: .LBB61_782: # %cond.load981 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -7303,9 +7303,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 8 -; CHECK-RV32-NEXT: bltz a3, .LBB61_776 +; CHECK-RV32-NEXT: bltz a3, .LBB61_783 ; CHECK-RV32-NEXT: j .LBB61_263 -; CHECK-RV32-NEXT: .LBB61_776: # %cond.load985 +; CHECK-RV32-NEXT: .LBB61_783: # %cond.load985 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -7318,9 +7318,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 7 -; CHECK-RV32-NEXT: bltz a3, .LBB61_777 +; CHECK-RV32-NEXT: bltz a3, .LBB61_784 ; CHECK-RV32-NEXT: j .LBB61_264 -; CHECK-RV32-NEXT: .LBB61_777: # %cond.load989 +; CHECK-RV32-NEXT: .LBB61_784: # %cond.load989 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -7333,9 +7333,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 6 -; CHECK-RV32-NEXT: bltz a3, .LBB61_778 +; CHECK-RV32-NEXT: bltz a3, .LBB61_785 ; CHECK-RV32-NEXT: j .LBB61_265 -; CHECK-RV32-NEXT: .LBB61_778: # %cond.load993 +; CHECK-RV32-NEXT: .LBB61_785: # %cond.load993 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -7348,9 +7348,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 5 -; CHECK-RV32-NEXT: bltz a3, .LBB61_779 +; CHECK-RV32-NEXT: bltz a3, .LBB61_786 ; CHECK-RV32-NEXT: j .LBB61_266 -; CHECK-RV32-NEXT: .LBB61_779: # %cond.load997 +; CHECK-RV32-NEXT: .LBB61_786: # %cond.load997 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -7363,9 +7363,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 4 -; CHECK-RV32-NEXT: bltz a3, .LBB61_780 +; CHECK-RV32-NEXT: bltz a3, .LBB61_787 ; CHECK-RV32-NEXT: j .LBB61_267 -; CHECK-RV32-NEXT: .LBB61_780: # %cond.load1001 +; CHECK-RV32-NEXT: .LBB61_787: # %cond.load1001 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -7378,9 +7378,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 3 -; CHECK-RV32-NEXT: bltz a3, .LBB61_781 +; CHECK-RV32-NEXT: bltz a3, .LBB61_788 ; CHECK-RV32-NEXT: j .LBB61_268 -; CHECK-RV32-NEXT: .LBB61_781: # %cond.load1005 +; CHECK-RV32-NEXT: .LBB61_788: # %cond.load1005 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV32-NEXT: vmv8r.v v16, v8 @@ -7393,11 +7393,11 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: slli a3, a2, 2 -; CHECK-RV32-NEXT: bgez a3, .LBB61_1032 +; CHECK-RV32-NEXT: bgez a3, .LBB61_789 ; CHECK-RV32-NEXT: j .LBB61_269 -; CHECK-RV32-NEXT: .LBB61_1032: # %cond.load1005 +; CHECK-RV32-NEXT: .LBB61_789: # %cond.load1005 ; CHECK-RV32-NEXT: j .LBB61_270 -; CHECK-RV32-NEXT: .LBB61_782: # %cond.load1017 +; CHECK-RV32-NEXT: .LBB61_790: # %cond.load1017 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vmv8r.v v16, v8 ; CHECK-RV32-NEXT: vmv.s.x v12, a2 @@ -7409,9 +7409,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vmv4r.v v16, v8 ; CHECK-RV32-NEXT: vmv8r.v v8, v16 ; CHECK-RV32-NEXT: andi a2, a3, 1 -; CHECK-RV32-NEXT: bnez a2, .LBB61_783 +; CHECK-RV32-NEXT: bnez a2, .LBB61_791 ; CHECK-RV32-NEXT: j .LBB61_274 -; CHECK-RV32-NEXT: .LBB61_783: # %cond.load1021 +; CHECK-RV32-NEXT: .LBB61_791: # %cond.load1021 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7422,9 +7422,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 2 -; CHECK-RV32-NEXT: bnez a2, .LBB61_784 +; CHECK-RV32-NEXT: bnez a2, .LBB61_792 ; CHECK-RV32-NEXT: j .LBB61_275 -; CHECK-RV32-NEXT: .LBB61_784: # %cond.load1025 +; CHECK-RV32-NEXT: .LBB61_792: # %cond.load1025 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7435,9 +7435,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 4 -; CHECK-RV32-NEXT: bnez a2, .LBB61_785 +; CHECK-RV32-NEXT: bnez a2, .LBB61_793 ; CHECK-RV32-NEXT: j .LBB61_276 -; CHECK-RV32-NEXT: .LBB61_785: # %cond.load1029 +; CHECK-RV32-NEXT: .LBB61_793: # %cond.load1029 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7448,9 +7448,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 8 -; CHECK-RV32-NEXT: bnez a2, .LBB61_786 +; CHECK-RV32-NEXT: bnez a2, .LBB61_794 ; CHECK-RV32-NEXT: j .LBB61_277 -; CHECK-RV32-NEXT: .LBB61_786: # %cond.load1033 +; CHECK-RV32-NEXT: .LBB61_794: # %cond.load1033 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7461,9 +7461,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 16 -; CHECK-RV32-NEXT: bnez a2, .LBB61_787 +; CHECK-RV32-NEXT: bnez a2, .LBB61_795 ; CHECK-RV32-NEXT: j .LBB61_278 -; CHECK-RV32-NEXT: .LBB61_787: # %cond.load1037 +; CHECK-RV32-NEXT: .LBB61_795: # %cond.load1037 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7474,9 +7474,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 32 -; CHECK-RV32-NEXT: bnez a2, .LBB61_788 +; CHECK-RV32-NEXT: bnez a2, .LBB61_796 ; CHECK-RV32-NEXT: j .LBB61_279 -; CHECK-RV32-NEXT: .LBB61_788: # %cond.load1041 +; CHECK-RV32-NEXT: .LBB61_796: # %cond.load1041 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7487,9 +7487,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 64 -; CHECK-RV32-NEXT: bnez a2, .LBB61_789 +; CHECK-RV32-NEXT: bnez a2, .LBB61_797 ; CHECK-RV32-NEXT: j .LBB61_280 -; CHECK-RV32-NEXT: .LBB61_789: # %cond.load1045 +; CHECK-RV32-NEXT: .LBB61_797: # %cond.load1045 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7500,9 +7500,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 128 -; CHECK-RV32-NEXT: bnez a2, .LBB61_790 +; CHECK-RV32-NEXT: bnez a2, .LBB61_798 ; CHECK-RV32-NEXT: j .LBB61_281 -; CHECK-RV32-NEXT: .LBB61_790: # %cond.load1049 +; CHECK-RV32-NEXT: .LBB61_798: # %cond.load1049 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7513,9 +7513,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 256 -; CHECK-RV32-NEXT: bnez a2, .LBB61_791 +; CHECK-RV32-NEXT: bnez a2, .LBB61_799 ; CHECK-RV32-NEXT: j .LBB61_282 -; CHECK-RV32-NEXT: .LBB61_791: # %cond.load1053 +; CHECK-RV32-NEXT: .LBB61_799: # %cond.load1053 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7526,9 +7526,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 512 -; CHECK-RV32-NEXT: bnez a2, .LBB61_792 +; CHECK-RV32-NEXT: bnez a2, .LBB61_800 ; CHECK-RV32-NEXT: j .LBB61_283 -; CHECK-RV32-NEXT: .LBB61_792: # %cond.load1057 +; CHECK-RV32-NEXT: .LBB61_800: # %cond.load1057 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7539,9 +7539,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 1024 -; CHECK-RV32-NEXT: bnez a2, .LBB61_793 +; CHECK-RV32-NEXT: bnez a2, .LBB61_801 ; CHECK-RV32-NEXT: j .LBB61_284 -; CHECK-RV32-NEXT: .LBB61_793: # %cond.load1061 +; CHECK-RV32-NEXT: .LBB61_801: # %cond.load1061 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7552,9 +7552,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 20 -; CHECK-RV32-NEXT: bltz a2, .LBB61_794 +; CHECK-RV32-NEXT: bltz a2, .LBB61_802 ; CHECK-RV32-NEXT: j .LBB61_285 -; CHECK-RV32-NEXT: .LBB61_794: # %cond.load1065 +; CHECK-RV32-NEXT: .LBB61_802: # %cond.load1065 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7565,9 +7565,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 19 -; CHECK-RV32-NEXT: bltz a2, .LBB61_795 +; CHECK-RV32-NEXT: bltz a2, .LBB61_803 ; CHECK-RV32-NEXT: j .LBB61_286 -; CHECK-RV32-NEXT: .LBB61_795: # %cond.load1069 +; CHECK-RV32-NEXT: .LBB61_803: # %cond.load1069 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7578,9 +7578,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 18 -; CHECK-RV32-NEXT: bltz a2, .LBB61_796 +; CHECK-RV32-NEXT: bltz a2, .LBB61_804 ; CHECK-RV32-NEXT: j .LBB61_287 -; CHECK-RV32-NEXT: .LBB61_796: # %cond.load1073 +; CHECK-RV32-NEXT: .LBB61_804: # %cond.load1073 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7591,9 +7591,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 17 -; CHECK-RV32-NEXT: bltz a2, .LBB61_797 +; CHECK-RV32-NEXT: bltz a2, .LBB61_805 ; CHECK-RV32-NEXT: j .LBB61_288 -; CHECK-RV32-NEXT: .LBB61_797: # %cond.load1077 +; CHECK-RV32-NEXT: .LBB61_805: # %cond.load1077 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7604,9 +7604,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 16 -; CHECK-RV32-NEXT: bltz a2, .LBB61_798 +; CHECK-RV32-NEXT: bltz a2, .LBB61_806 ; CHECK-RV32-NEXT: j .LBB61_289 -; CHECK-RV32-NEXT: .LBB61_798: # %cond.load1081 +; CHECK-RV32-NEXT: .LBB61_806: # %cond.load1081 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7617,9 +7617,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 15 -; CHECK-RV32-NEXT: bltz a2, .LBB61_799 +; CHECK-RV32-NEXT: bltz a2, .LBB61_807 ; CHECK-RV32-NEXT: j .LBB61_290 -; CHECK-RV32-NEXT: .LBB61_799: # %cond.load1085 +; CHECK-RV32-NEXT: .LBB61_807: # %cond.load1085 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7630,9 +7630,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 14 -; CHECK-RV32-NEXT: bltz a2, .LBB61_800 +; CHECK-RV32-NEXT: bltz a2, .LBB61_808 ; CHECK-RV32-NEXT: j .LBB61_291 -; CHECK-RV32-NEXT: .LBB61_800: # %cond.load1089 +; CHECK-RV32-NEXT: .LBB61_808: # %cond.load1089 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7643,9 +7643,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 13 -; CHECK-RV32-NEXT: bltz a2, .LBB61_801 +; CHECK-RV32-NEXT: bltz a2, .LBB61_809 ; CHECK-RV32-NEXT: j .LBB61_292 -; CHECK-RV32-NEXT: .LBB61_801: # %cond.load1093 +; CHECK-RV32-NEXT: .LBB61_809: # %cond.load1093 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7656,9 +7656,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 12 -; CHECK-RV32-NEXT: bltz a2, .LBB61_802 +; CHECK-RV32-NEXT: bltz a2, .LBB61_810 ; CHECK-RV32-NEXT: j .LBB61_293 -; CHECK-RV32-NEXT: .LBB61_802: # %cond.load1097 +; CHECK-RV32-NEXT: .LBB61_810: # %cond.load1097 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7669,9 +7669,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 11 -; CHECK-RV32-NEXT: bltz a2, .LBB61_803 +; CHECK-RV32-NEXT: bltz a2, .LBB61_811 ; CHECK-RV32-NEXT: j .LBB61_294 -; CHECK-RV32-NEXT: .LBB61_803: # %cond.load1101 +; CHECK-RV32-NEXT: .LBB61_811: # %cond.load1101 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7682,9 +7682,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 10 -; CHECK-RV32-NEXT: bltz a2, .LBB61_804 +; CHECK-RV32-NEXT: bltz a2, .LBB61_812 ; CHECK-RV32-NEXT: j .LBB61_295 -; CHECK-RV32-NEXT: .LBB61_804: # %cond.load1105 +; CHECK-RV32-NEXT: .LBB61_812: # %cond.load1105 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7695,9 +7695,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 9 -; CHECK-RV32-NEXT: bltz a2, .LBB61_805 +; CHECK-RV32-NEXT: bltz a2, .LBB61_813 ; CHECK-RV32-NEXT: j .LBB61_296 -; CHECK-RV32-NEXT: .LBB61_805: # %cond.load1109 +; CHECK-RV32-NEXT: .LBB61_813: # %cond.load1109 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7708,9 +7708,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 8 -; CHECK-RV32-NEXT: bltz a2, .LBB61_806 +; CHECK-RV32-NEXT: bltz a2, .LBB61_814 ; CHECK-RV32-NEXT: j .LBB61_297 -; CHECK-RV32-NEXT: .LBB61_806: # %cond.load1113 +; CHECK-RV32-NEXT: .LBB61_814: # %cond.load1113 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7721,9 +7721,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 7 -; CHECK-RV32-NEXT: bltz a2, .LBB61_807 +; CHECK-RV32-NEXT: bltz a2, .LBB61_815 ; CHECK-RV32-NEXT: j .LBB61_298 -; CHECK-RV32-NEXT: .LBB61_807: # %cond.load1117 +; CHECK-RV32-NEXT: .LBB61_815: # %cond.load1117 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7734,9 +7734,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 6 -; CHECK-RV32-NEXT: bltz a2, .LBB61_808 +; CHECK-RV32-NEXT: bltz a2, .LBB61_816 ; CHECK-RV32-NEXT: j .LBB61_299 -; CHECK-RV32-NEXT: .LBB61_808: # %cond.load1121 +; CHECK-RV32-NEXT: .LBB61_816: # %cond.load1121 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7747,9 +7747,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 5 -; CHECK-RV32-NEXT: bltz a2, .LBB61_809 +; CHECK-RV32-NEXT: bltz a2, .LBB61_817 ; CHECK-RV32-NEXT: j .LBB61_300 -; CHECK-RV32-NEXT: .LBB61_809: # %cond.load1125 +; CHECK-RV32-NEXT: .LBB61_817: # %cond.load1125 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7760,9 +7760,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 4 -; CHECK-RV32-NEXT: bltz a2, .LBB61_810 +; CHECK-RV32-NEXT: bltz a2, .LBB61_818 ; CHECK-RV32-NEXT: j .LBB61_301 -; CHECK-RV32-NEXT: .LBB61_810: # %cond.load1129 +; CHECK-RV32-NEXT: .LBB61_818: # %cond.load1129 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7773,9 +7773,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 3 -; CHECK-RV32-NEXT: bltz a2, .LBB61_811 +; CHECK-RV32-NEXT: bltz a2, .LBB61_819 ; CHECK-RV32-NEXT: j .LBB61_302 -; CHECK-RV32-NEXT: .LBB61_811: # %cond.load1133 +; CHECK-RV32-NEXT: .LBB61_819: # %cond.load1133 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7786,11 +7786,11 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 2 -; CHECK-RV32-NEXT: bgez a2, .LBB61_1033 +; CHECK-RV32-NEXT: bgez a2, .LBB61_820 ; CHECK-RV32-NEXT: j .LBB61_303 -; CHECK-RV32-NEXT: .LBB61_1033: # %cond.load1133 +; CHECK-RV32-NEXT: .LBB61_820: # %cond.load1133 ; CHECK-RV32-NEXT: j .LBB61_304 -; CHECK-RV32-NEXT: .LBB61_812: # %cond.load1145 +; CHECK-RV32-NEXT: .LBB61_821: # %cond.load1145 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vmv.s.x v16, a3 ; CHECK-RV32-NEXT: li a3, 288 @@ -7799,9 +7799,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a3, a2, 1 -; CHECK-RV32-NEXT: bnez a3, .LBB61_813 +; CHECK-RV32-NEXT: bnez a3, .LBB61_822 ; CHECK-RV32-NEXT: j .LBB61_308 -; CHECK-RV32-NEXT: .LBB61_813: # %cond.load1149 +; CHECK-RV32-NEXT: .LBB61_822: # %cond.load1149 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7812,9 +7812,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a3, a2, 2 -; CHECK-RV32-NEXT: bnez a3, .LBB61_814 +; CHECK-RV32-NEXT: bnez a3, .LBB61_823 ; CHECK-RV32-NEXT: j .LBB61_309 -; CHECK-RV32-NEXT: .LBB61_814: # %cond.load1153 +; CHECK-RV32-NEXT: .LBB61_823: # %cond.load1153 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7825,9 +7825,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a3, a2, 4 -; CHECK-RV32-NEXT: bnez a3, .LBB61_815 +; CHECK-RV32-NEXT: bnez a3, .LBB61_824 ; CHECK-RV32-NEXT: j .LBB61_310 -; CHECK-RV32-NEXT: .LBB61_815: # %cond.load1157 +; CHECK-RV32-NEXT: .LBB61_824: # %cond.load1157 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7838,9 +7838,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a3, a2, 8 -; CHECK-RV32-NEXT: bnez a3, .LBB61_816 +; CHECK-RV32-NEXT: bnez a3, .LBB61_825 ; CHECK-RV32-NEXT: j .LBB61_311 -; CHECK-RV32-NEXT: .LBB61_816: # %cond.load1161 +; CHECK-RV32-NEXT: .LBB61_825: # %cond.load1161 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7851,9 +7851,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a3, a2, 16 -; CHECK-RV32-NEXT: bnez a3, .LBB61_817 +; CHECK-RV32-NEXT: bnez a3, .LBB61_826 ; CHECK-RV32-NEXT: j .LBB61_312 -; CHECK-RV32-NEXT: .LBB61_817: # %cond.load1165 +; CHECK-RV32-NEXT: .LBB61_826: # %cond.load1165 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7864,9 +7864,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a3, a2, 32 -; CHECK-RV32-NEXT: bnez a3, .LBB61_818 +; CHECK-RV32-NEXT: bnez a3, .LBB61_827 ; CHECK-RV32-NEXT: j .LBB61_313 -; CHECK-RV32-NEXT: .LBB61_818: # %cond.load1169 +; CHECK-RV32-NEXT: .LBB61_827: # %cond.load1169 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7877,9 +7877,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a3, a2, 64 -; CHECK-RV32-NEXT: bnez a3, .LBB61_819 +; CHECK-RV32-NEXT: bnez a3, .LBB61_828 ; CHECK-RV32-NEXT: j .LBB61_314 -; CHECK-RV32-NEXT: .LBB61_819: # %cond.load1173 +; CHECK-RV32-NEXT: .LBB61_828: # %cond.load1173 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7890,9 +7890,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a3, a2, 128 -; CHECK-RV32-NEXT: bnez a3, .LBB61_820 +; CHECK-RV32-NEXT: bnez a3, .LBB61_829 ; CHECK-RV32-NEXT: j .LBB61_315 -; CHECK-RV32-NEXT: .LBB61_820: # %cond.load1177 +; CHECK-RV32-NEXT: .LBB61_829: # %cond.load1177 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7903,9 +7903,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a3, a2, 256 -; CHECK-RV32-NEXT: bnez a3, .LBB61_821 +; CHECK-RV32-NEXT: bnez a3, .LBB61_830 ; CHECK-RV32-NEXT: j .LBB61_316 -; CHECK-RV32-NEXT: .LBB61_821: # %cond.load1181 +; CHECK-RV32-NEXT: .LBB61_830: # %cond.load1181 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7916,9 +7916,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a3, a2, 512 -; CHECK-RV32-NEXT: bnez a3, .LBB61_822 +; CHECK-RV32-NEXT: bnez a3, .LBB61_831 ; CHECK-RV32-NEXT: j .LBB61_317 -; CHECK-RV32-NEXT: .LBB61_822: # %cond.load1185 +; CHECK-RV32-NEXT: .LBB61_831: # %cond.load1185 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7929,9 +7929,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a3, a2, 1024 -; CHECK-RV32-NEXT: bnez a3, .LBB61_823 +; CHECK-RV32-NEXT: bnez a3, .LBB61_832 ; CHECK-RV32-NEXT: j .LBB61_318 -; CHECK-RV32-NEXT: .LBB61_823: # %cond.load1189 +; CHECK-RV32-NEXT: .LBB61_832: # %cond.load1189 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7942,9 +7942,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 20 -; CHECK-RV32-NEXT: bltz a3, .LBB61_824 +; CHECK-RV32-NEXT: bltz a3, .LBB61_833 ; CHECK-RV32-NEXT: j .LBB61_319 -; CHECK-RV32-NEXT: .LBB61_824: # %cond.load1193 +; CHECK-RV32-NEXT: .LBB61_833: # %cond.load1193 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7955,9 +7955,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 19 -; CHECK-RV32-NEXT: bltz a3, .LBB61_825 +; CHECK-RV32-NEXT: bltz a3, .LBB61_834 ; CHECK-RV32-NEXT: j .LBB61_320 -; CHECK-RV32-NEXT: .LBB61_825: # %cond.load1197 +; CHECK-RV32-NEXT: .LBB61_834: # %cond.load1197 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7968,9 +7968,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 18 -; CHECK-RV32-NEXT: bltz a3, .LBB61_826 +; CHECK-RV32-NEXT: bltz a3, .LBB61_835 ; CHECK-RV32-NEXT: j .LBB61_321 -; CHECK-RV32-NEXT: .LBB61_826: # %cond.load1201 +; CHECK-RV32-NEXT: .LBB61_835: # %cond.load1201 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7981,9 +7981,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 17 -; CHECK-RV32-NEXT: bltz a3, .LBB61_827 +; CHECK-RV32-NEXT: bltz a3, .LBB61_836 ; CHECK-RV32-NEXT: j .LBB61_322 -; CHECK-RV32-NEXT: .LBB61_827: # %cond.load1205 +; CHECK-RV32-NEXT: .LBB61_836: # %cond.load1205 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -7994,9 +7994,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 16 -; CHECK-RV32-NEXT: bltz a3, .LBB61_828 +; CHECK-RV32-NEXT: bltz a3, .LBB61_837 ; CHECK-RV32-NEXT: j .LBB61_323 -; CHECK-RV32-NEXT: .LBB61_828: # %cond.load1209 +; CHECK-RV32-NEXT: .LBB61_837: # %cond.load1209 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8007,9 +8007,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 15 -; CHECK-RV32-NEXT: bltz a3, .LBB61_829 +; CHECK-RV32-NEXT: bltz a3, .LBB61_838 ; CHECK-RV32-NEXT: j .LBB61_324 -; CHECK-RV32-NEXT: .LBB61_829: # %cond.load1213 +; CHECK-RV32-NEXT: .LBB61_838: # %cond.load1213 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8020,9 +8020,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 14 -; CHECK-RV32-NEXT: bltz a3, .LBB61_830 +; CHECK-RV32-NEXT: bltz a3, .LBB61_839 ; CHECK-RV32-NEXT: j .LBB61_325 -; CHECK-RV32-NEXT: .LBB61_830: # %cond.load1217 +; CHECK-RV32-NEXT: .LBB61_839: # %cond.load1217 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8033,9 +8033,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 13 -; CHECK-RV32-NEXT: bltz a3, .LBB61_831 +; CHECK-RV32-NEXT: bltz a3, .LBB61_840 ; CHECK-RV32-NEXT: j .LBB61_326 -; CHECK-RV32-NEXT: .LBB61_831: # %cond.load1221 +; CHECK-RV32-NEXT: .LBB61_840: # %cond.load1221 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8046,9 +8046,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 12 -; CHECK-RV32-NEXT: bltz a3, .LBB61_832 +; CHECK-RV32-NEXT: bltz a3, .LBB61_841 ; CHECK-RV32-NEXT: j .LBB61_327 -; CHECK-RV32-NEXT: .LBB61_832: # %cond.load1225 +; CHECK-RV32-NEXT: .LBB61_841: # %cond.load1225 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8059,9 +8059,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 11 -; CHECK-RV32-NEXT: bltz a3, .LBB61_833 +; CHECK-RV32-NEXT: bltz a3, .LBB61_842 ; CHECK-RV32-NEXT: j .LBB61_328 -; CHECK-RV32-NEXT: .LBB61_833: # %cond.load1229 +; CHECK-RV32-NEXT: .LBB61_842: # %cond.load1229 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8072,9 +8072,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 10 -; CHECK-RV32-NEXT: bltz a3, .LBB61_834 +; CHECK-RV32-NEXT: bltz a3, .LBB61_843 ; CHECK-RV32-NEXT: j .LBB61_329 -; CHECK-RV32-NEXT: .LBB61_834: # %cond.load1233 +; CHECK-RV32-NEXT: .LBB61_843: # %cond.load1233 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8085,9 +8085,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 9 -; CHECK-RV32-NEXT: bltz a3, .LBB61_835 +; CHECK-RV32-NEXT: bltz a3, .LBB61_844 ; CHECK-RV32-NEXT: j .LBB61_330 -; CHECK-RV32-NEXT: .LBB61_835: # %cond.load1237 +; CHECK-RV32-NEXT: .LBB61_844: # %cond.load1237 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8098,9 +8098,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 8 -; CHECK-RV32-NEXT: bltz a3, .LBB61_836 +; CHECK-RV32-NEXT: bltz a3, .LBB61_845 ; CHECK-RV32-NEXT: j .LBB61_331 -; CHECK-RV32-NEXT: .LBB61_836: # %cond.load1241 +; CHECK-RV32-NEXT: .LBB61_845: # %cond.load1241 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8111,9 +8111,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 7 -; CHECK-RV32-NEXT: bltz a3, .LBB61_837 +; CHECK-RV32-NEXT: bltz a3, .LBB61_846 ; CHECK-RV32-NEXT: j .LBB61_332 -; CHECK-RV32-NEXT: .LBB61_837: # %cond.load1245 +; CHECK-RV32-NEXT: .LBB61_846: # %cond.load1245 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8124,9 +8124,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 6 -; CHECK-RV32-NEXT: bltz a3, .LBB61_838 +; CHECK-RV32-NEXT: bltz a3, .LBB61_847 ; CHECK-RV32-NEXT: j .LBB61_333 -; CHECK-RV32-NEXT: .LBB61_838: # %cond.load1249 +; CHECK-RV32-NEXT: .LBB61_847: # %cond.load1249 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8137,9 +8137,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 5 -; CHECK-RV32-NEXT: bltz a3, .LBB61_839 +; CHECK-RV32-NEXT: bltz a3, .LBB61_848 ; CHECK-RV32-NEXT: j .LBB61_334 -; CHECK-RV32-NEXT: .LBB61_839: # %cond.load1253 +; CHECK-RV32-NEXT: .LBB61_848: # %cond.load1253 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8150,9 +8150,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 4 -; CHECK-RV32-NEXT: bltz a3, .LBB61_840 +; CHECK-RV32-NEXT: bltz a3, .LBB61_849 ; CHECK-RV32-NEXT: j .LBB61_335 -; CHECK-RV32-NEXT: .LBB61_840: # %cond.load1257 +; CHECK-RV32-NEXT: .LBB61_849: # %cond.load1257 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8163,9 +8163,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 3 -; CHECK-RV32-NEXT: bltz a3, .LBB61_841 +; CHECK-RV32-NEXT: bltz a3, .LBB61_850 ; CHECK-RV32-NEXT: j .LBB61_336 -; CHECK-RV32-NEXT: .LBB61_841: # %cond.load1261 +; CHECK-RV32-NEXT: .LBB61_850: # %cond.load1261 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8176,11 +8176,11 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 2 -; CHECK-RV32-NEXT: bgez a3, .LBB61_1034 +; CHECK-RV32-NEXT: bgez a3, .LBB61_851 ; CHECK-RV32-NEXT: j .LBB61_337 -; CHECK-RV32-NEXT: .LBB61_1034: # %cond.load1261 +; CHECK-RV32-NEXT: .LBB61_851: # %cond.load1261 ; CHECK-RV32-NEXT: j .LBB61_338 -; CHECK-RV32-NEXT: .LBB61_842: # %cond.load1273 +; CHECK-RV32-NEXT: .LBB61_852: # %cond.load1273 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vmv.s.x v16, a2 ; CHECK-RV32-NEXT: li a2, 320 @@ -8189,9 +8189,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 1 -; CHECK-RV32-NEXT: bnez a2, .LBB61_843 +; CHECK-RV32-NEXT: bnez a2, .LBB61_853 ; CHECK-RV32-NEXT: j .LBB61_342 -; CHECK-RV32-NEXT: .LBB61_843: # %cond.load1277 +; CHECK-RV32-NEXT: .LBB61_853: # %cond.load1277 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8202,9 +8202,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 2 -; CHECK-RV32-NEXT: bnez a2, .LBB61_844 +; CHECK-RV32-NEXT: bnez a2, .LBB61_854 ; CHECK-RV32-NEXT: j .LBB61_343 -; CHECK-RV32-NEXT: .LBB61_844: # %cond.load1281 +; CHECK-RV32-NEXT: .LBB61_854: # %cond.load1281 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8215,9 +8215,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 4 -; CHECK-RV32-NEXT: bnez a2, .LBB61_845 +; CHECK-RV32-NEXT: bnez a2, .LBB61_855 ; CHECK-RV32-NEXT: j .LBB61_344 -; CHECK-RV32-NEXT: .LBB61_845: # %cond.load1285 +; CHECK-RV32-NEXT: .LBB61_855: # %cond.load1285 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8228,9 +8228,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 8 -; CHECK-RV32-NEXT: bnez a2, .LBB61_846 +; CHECK-RV32-NEXT: bnez a2, .LBB61_856 ; CHECK-RV32-NEXT: j .LBB61_345 -; CHECK-RV32-NEXT: .LBB61_846: # %cond.load1289 +; CHECK-RV32-NEXT: .LBB61_856: # %cond.load1289 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8241,9 +8241,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 16 -; CHECK-RV32-NEXT: bnez a2, .LBB61_847 +; CHECK-RV32-NEXT: bnez a2, .LBB61_857 ; CHECK-RV32-NEXT: j .LBB61_346 -; CHECK-RV32-NEXT: .LBB61_847: # %cond.load1293 +; CHECK-RV32-NEXT: .LBB61_857: # %cond.load1293 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8254,9 +8254,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 32 -; CHECK-RV32-NEXT: bnez a2, .LBB61_848 +; CHECK-RV32-NEXT: bnez a2, .LBB61_858 ; CHECK-RV32-NEXT: j .LBB61_347 -; CHECK-RV32-NEXT: .LBB61_848: # %cond.load1297 +; CHECK-RV32-NEXT: .LBB61_858: # %cond.load1297 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8267,9 +8267,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 64 -; CHECK-RV32-NEXT: bnez a2, .LBB61_849 +; CHECK-RV32-NEXT: bnez a2, .LBB61_859 ; CHECK-RV32-NEXT: j .LBB61_348 -; CHECK-RV32-NEXT: .LBB61_849: # %cond.load1301 +; CHECK-RV32-NEXT: .LBB61_859: # %cond.load1301 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8280,9 +8280,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 128 -; CHECK-RV32-NEXT: bnez a2, .LBB61_850 +; CHECK-RV32-NEXT: bnez a2, .LBB61_860 ; CHECK-RV32-NEXT: j .LBB61_349 -; CHECK-RV32-NEXT: .LBB61_850: # %cond.load1305 +; CHECK-RV32-NEXT: .LBB61_860: # %cond.load1305 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8293,9 +8293,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 256 -; CHECK-RV32-NEXT: bnez a2, .LBB61_851 +; CHECK-RV32-NEXT: bnez a2, .LBB61_861 ; CHECK-RV32-NEXT: j .LBB61_350 -; CHECK-RV32-NEXT: .LBB61_851: # %cond.load1309 +; CHECK-RV32-NEXT: .LBB61_861: # %cond.load1309 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8306,9 +8306,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 512 -; CHECK-RV32-NEXT: bnez a2, .LBB61_852 +; CHECK-RV32-NEXT: bnez a2, .LBB61_862 ; CHECK-RV32-NEXT: j .LBB61_351 -; CHECK-RV32-NEXT: .LBB61_852: # %cond.load1313 +; CHECK-RV32-NEXT: .LBB61_862: # %cond.load1313 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8319,9 +8319,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 1024 -; CHECK-RV32-NEXT: bnez a2, .LBB61_853 +; CHECK-RV32-NEXT: bnez a2, .LBB61_863 ; CHECK-RV32-NEXT: j .LBB61_352 -; CHECK-RV32-NEXT: .LBB61_853: # %cond.load1317 +; CHECK-RV32-NEXT: .LBB61_863: # %cond.load1317 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8332,9 +8332,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 20 -; CHECK-RV32-NEXT: bltz a2, .LBB61_854 +; CHECK-RV32-NEXT: bltz a2, .LBB61_864 ; CHECK-RV32-NEXT: j .LBB61_353 -; CHECK-RV32-NEXT: .LBB61_854: # %cond.load1321 +; CHECK-RV32-NEXT: .LBB61_864: # %cond.load1321 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8345,9 +8345,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 19 -; CHECK-RV32-NEXT: bltz a2, .LBB61_855 +; CHECK-RV32-NEXT: bltz a2, .LBB61_865 ; CHECK-RV32-NEXT: j .LBB61_354 -; CHECK-RV32-NEXT: .LBB61_855: # %cond.load1325 +; CHECK-RV32-NEXT: .LBB61_865: # %cond.load1325 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8358,9 +8358,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 18 -; CHECK-RV32-NEXT: bltz a2, .LBB61_856 +; CHECK-RV32-NEXT: bltz a2, .LBB61_866 ; CHECK-RV32-NEXT: j .LBB61_355 -; CHECK-RV32-NEXT: .LBB61_856: # %cond.load1329 +; CHECK-RV32-NEXT: .LBB61_866: # %cond.load1329 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8371,9 +8371,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 17 -; CHECK-RV32-NEXT: bltz a2, .LBB61_857 +; CHECK-RV32-NEXT: bltz a2, .LBB61_867 ; CHECK-RV32-NEXT: j .LBB61_356 -; CHECK-RV32-NEXT: .LBB61_857: # %cond.load1333 +; CHECK-RV32-NEXT: .LBB61_867: # %cond.load1333 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8384,9 +8384,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 16 -; CHECK-RV32-NEXT: bltz a2, .LBB61_858 +; CHECK-RV32-NEXT: bltz a2, .LBB61_868 ; CHECK-RV32-NEXT: j .LBB61_357 -; CHECK-RV32-NEXT: .LBB61_858: # %cond.load1337 +; CHECK-RV32-NEXT: .LBB61_868: # %cond.load1337 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8397,9 +8397,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 15 -; CHECK-RV32-NEXT: bltz a2, .LBB61_859 +; CHECK-RV32-NEXT: bltz a2, .LBB61_869 ; CHECK-RV32-NEXT: j .LBB61_358 -; CHECK-RV32-NEXT: .LBB61_859: # %cond.load1341 +; CHECK-RV32-NEXT: .LBB61_869: # %cond.load1341 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8410,9 +8410,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 14 -; CHECK-RV32-NEXT: bltz a2, .LBB61_860 +; CHECK-RV32-NEXT: bltz a2, .LBB61_870 ; CHECK-RV32-NEXT: j .LBB61_359 -; CHECK-RV32-NEXT: .LBB61_860: # %cond.load1345 +; CHECK-RV32-NEXT: .LBB61_870: # %cond.load1345 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8423,9 +8423,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 13 -; CHECK-RV32-NEXT: bltz a2, .LBB61_861 +; CHECK-RV32-NEXT: bltz a2, .LBB61_871 ; CHECK-RV32-NEXT: j .LBB61_360 -; CHECK-RV32-NEXT: .LBB61_861: # %cond.load1349 +; CHECK-RV32-NEXT: .LBB61_871: # %cond.load1349 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8436,9 +8436,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 12 -; CHECK-RV32-NEXT: bltz a2, .LBB61_862 +; CHECK-RV32-NEXT: bltz a2, .LBB61_872 ; CHECK-RV32-NEXT: j .LBB61_361 -; CHECK-RV32-NEXT: .LBB61_862: # %cond.load1353 +; CHECK-RV32-NEXT: .LBB61_872: # %cond.load1353 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8449,9 +8449,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 11 -; CHECK-RV32-NEXT: bltz a2, .LBB61_863 +; CHECK-RV32-NEXT: bltz a2, .LBB61_873 ; CHECK-RV32-NEXT: j .LBB61_362 -; CHECK-RV32-NEXT: .LBB61_863: # %cond.load1357 +; CHECK-RV32-NEXT: .LBB61_873: # %cond.load1357 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8462,9 +8462,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 10 -; CHECK-RV32-NEXT: bltz a2, .LBB61_864 +; CHECK-RV32-NEXT: bltz a2, .LBB61_874 ; CHECK-RV32-NEXT: j .LBB61_363 -; CHECK-RV32-NEXT: .LBB61_864: # %cond.load1361 +; CHECK-RV32-NEXT: .LBB61_874: # %cond.load1361 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8475,9 +8475,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 9 -; CHECK-RV32-NEXT: bltz a2, .LBB61_865 +; CHECK-RV32-NEXT: bltz a2, .LBB61_875 ; CHECK-RV32-NEXT: j .LBB61_364 -; CHECK-RV32-NEXT: .LBB61_865: # %cond.load1365 +; CHECK-RV32-NEXT: .LBB61_875: # %cond.load1365 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8488,9 +8488,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 8 -; CHECK-RV32-NEXT: bltz a2, .LBB61_866 +; CHECK-RV32-NEXT: bltz a2, .LBB61_876 ; CHECK-RV32-NEXT: j .LBB61_365 -; CHECK-RV32-NEXT: .LBB61_866: # %cond.load1369 +; CHECK-RV32-NEXT: .LBB61_876: # %cond.load1369 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8501,9 +8501,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 7 -; CHECK-RV32-NEXT: bltz a2, .LBB61_867 +; CHECK-RV32-NEXT: bltz a2, .LBB61_877 ; CHECK-RV32-NEXT: j .LBB61_366 -; CHECK-RV32-NEXT: .LBB61_867: # %cond.load1373 +; CHECK-RV32-NEXT: .LBB61_877: # %cond.load1373 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8514,9 +8514,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 6 -; CHECK-RV32-NEXT: bltz a2, .LBB61_868 +; CHECK-RV32-NEXT: bltz a2, .LBB61_878 ; CHECK-RV32-NEXT: j .LBB61_367 -; CHECK-RV32-NEXT: .LBB61_868: # %cond.load1377 +; CHECK-RV32-NEXT: .LBB61_878: # %cond.load1377 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8527,9 +8527,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 5 -; CHECK-RV32-NEXT: bltz a2, .LBB61_869 +; CHECK-RV32-NEXT: bltz a2, .LBB61_879 ; CHECK-RV32-NEXT: j .LBB61_368 -; CHECK-RV32-NEXT: .LBB61_869: # %cond.load1381 +; CHECK-RV32-NEXT: .LBB61_879: # %cond.load1381 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8540,9 +8540,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 4 -; CHECK-RV32-NEXT: bltz a2, .LBB61_870 +; CHECK-RV32-NEXT: bltz a2, .LBB61_880 ; CHECK-RV32-NEXT: j .LBB61_369 -; CHECK-RV32-NEXT: .LBB61_870: # %cond.load1385 +; CHECK-RV32-NEXT: .LBB61_880: # %cond.load1385 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8553,9 +8553,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 3 -; CHECK-RV32-NEXT: bltz a2, .LBB61_871 +; CHECK-RV32-NEXT: bltz a2, .LBB61_881 ; CHECK-RV32-NEXT: j .LBB61_370 -; CHECK-RV32-NEXT: .LBB61_871: # %cond.load1389 +; CHECK-RV32-NEXT: .LBB61_881: # %cond.load1389 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8566,11 +8566,11 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 2 -; CHECK-RV32-NEXT: bgez a2, .LBB61_1035 +; CHECK-RV32-NEXT: bgez a2, .LBB61_882 ; CHECK-RV32-NEXT: j .LBB61_371 -; CHECK-RV32-NEXT: .LBB61_1035: # %cond.load1389 +; CHECK-RV32-NEXT: .LBB61_882: # %cond.load1389 ; CHECK-RV32-NEXT: j .LBB61_372 -; CHECK-RV32-NEXT: .LBB61_872: # %cond.load1401 +; CHECK-RV32-NEXT: .LBB61_883: # %cond.load1401 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vmv.s.x v16, a3 ; CHECK-RV32-NEXT: li a3, 352 @@ -8579,9 +8579,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a3, a2, 1 -; CHECK-RV32-NEXT: bnez a3, .LBB61_873 +; CHECK-RV32-NEXT: bnez a3, .LBB61_884 ; CHECK-RV32-NEXT: j .LBB61_376 -; CHECK-RV32-NEXT: .LBB61_873: # %cond.load1405 +; CHECK-RV32-NEXT: .LBB61_884: # %cond.load1405 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8592,9 +8592,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a3, a2, 2 -; CHECK-RV32-NEXT: bnez a3, .LBB61_874 +; CHECK-RV32-NEXT: bnez a3, .LBB61_885 ; CHECK-RV32-NEXT: j .LBB61_377 -; CHECK-RV32-NEXT: .LBB61_874: # %cond.load1409 +; CHECK-RV32-NEXT: .LBB61_885: # %cond.load1409 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8605,9 +8605,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a3, a2, 4 -; CHECK-RV32-NEXT: bnez a3, .LBB61_875 +; CHECK-RV32-NEXT: bnez a3, .LBB61_886 ; CHECK-RV32-NEXT: j .LBB61_378 -; CHECK-RV32-NEXT: .LBB61_875: # %cond.load1413 +; CHECK-RV32-NEXT: .LBB61_886: # %cond.load1413 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8618,9 +8618,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a3, a2, 8 -; CHECK-RV32-NEXT: bnez a3, .LBB61_876 +; CHECK-RV32-NEXT: bnez a3, .LBB61_887 ; CHECK-RV32-NEXT: j .LBB61_379 -; CHECK-RV32-NEXT: .LBB61_876: # %cond.load1417 +; CHECK-RV32-NEXT: .LBB61_887: # %cond.load1417 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8631,9 +8631,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a3, a2, 16 -; CHECK-RV32-NEXT: bnez a3, .LBB61_877 +; CHECK-RV32-NEXT: bnez a3, .LBB61_888 ; CHECK-RV32-NEXT: j .LBB61_380 -; CHECK-RV32-NEXT: .LBB61_877: # %cond.load1421 +; CHECK-RV32-NEXT: .LBB61_888: # %cond.load1421 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8644,9 +8644,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a3, a2, 32 -; CHECK-RV32-NEXT: bnez a3, .LBB61_878 +; CHECK-RV32-NEXT: bnez a3, .LBB61_889 ; CHECK-RV32-NEXT: j .LBB61_381 -; CHECK-RV32-NEXT: .LBB61_878: # %cond.load1425 +; CHECK-RV32-NEXT: .LBB61_889: # %cond.load1425 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8657,9 +8657,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a3, a2, 64 -; CHECK-RV32-NEXT: bnez a3, .LBB61_879 +; CHECK-RV32-NEXT: bnez a3, .LBB61_890 ; CHECK-RV32-NEXT: j .LBB61_382 -; CHECK-RV32-NEXT: .LBB61_879: # %cond.load1429 +; CHECK-RV32-NEXT: .LBB61_890: # %cond.load1429 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8670,9 +8670,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a3, a2, 128 -; CHECK-RV32-NEXT: bnez a3, .LBB61_880 +; CHECK-RV32-NEXT: bnez a3, .LBB61_891 ; CHECK-RV32-NEXT: j .LBB61_383 -; CHECK-RV32-NEXT: .LBB61_880: # %cond.load1433 +; CHECK-RV32-NEXT: .LBB61_891: # %cond.load1433 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8683,9 +8683,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a3, a2, 256 -; CHECK-RV32-NEXT: bnez a3, .LBB61_881 +; CHECK-RV32-NEXT: bnez a3, .LBB61_892 ; CHECK-RV32-NEXT: j .LBB61_384 -; CHECK-RV32-NEXT: .LBB61_881: # %cond.load1437 +; CHECK-RV32-NEXT: .LBB61_892: # %cond.load1437 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8696,9 +8696,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a3, a2, 512 -; CHECK-RV32-NEXT: bnez a3, .LBB61_882 +; CHECK-RV32-NEXT: bnez a3, .LBB61_893 ; CHECK-RV32-NEXT: j .LBB61_385 -; CHECK-RV32-NEXT: .LBB61_882: # %cond.load1441 +; CHECK-RV32-NEXT: .LBB61_893: # %cond.load1441 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8709,9 +8709,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a3, a2, 1024 -; CHECK-RV32-NEXT: bnez a3, .LBB61_883 +; CHECK-RV32-NEXT: bnez a3, .LBB61_894 ; CHECK-RV32-NEXT: j .LBB61_386 -; CHECK-RV32-NEXT: .LBB61_883: # %cond.load1445 +; CHECK-RV32-NEXT: .LBB61_894: # %cond.load1445 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8722,9 +8722,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 20 -; CHECK-RV32-NEXT: bltz a3, .LBB61_884 +; CHECK-RV32-NEXT: bltz a3, .LBB61_895 ; CHECK-RV32-NEXT: j .LBB61_387 -; CHECK-RV32-NEXT: .LBB61_884: # %cond.load1449 +; CHECK-RV32-NEXT: .LBB61_895: # %cond.load1449 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8735,9 +8735,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 19 -; CHECK-RV32-NEXT: bltz a3, .LBB61_885 +; CHECK-RV32-NEXT: bltz a3, .LBB61_896 ; CHECK-RV32-NEXT: j .LBB61_388 -; CHECK-RV32-NEXT: .LBB61_885: # %cond.load1453 +; CHECK-RV32-NEXT: .LBB61_896: # %cond.load1453 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8748,9 +8748,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 18 -; CHECK-RV32-NEXT: bltz a3, .LBB61_886 +; CHECK-RV32-NEXT: bltz a3, .LBB61_897 ; CHECK-RV32-NEXT: j .LBB61_389 -; CHECK-RV32-NEXT: .LBB61_886: # %cond.load1457 +; CHECK-RV32-NEXT: .LBB61_897: # %cond.load1457 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8761,9 +8761,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 17 -; CHECK-RV32-NEXT: bltz a3, .LBB61_887 +; CHECK-RV32-NEXT: bltz a3, .LBB61_898 ; CHECK-RV32-NEXT: j .LBB61_390 -; CHECK-RV32-NEXT: .LBB61_887: # %cond.load1461 +; CHECK-RV32-NEXT: .LBB61_898: # %cond.load1461 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8774,9 +8774,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 16 -; CHECK-RV32-NEXT: bltz a3, .LBB61_888 +; CHECK-RV32-NEXT: bltz a3, .LBB61_899 ; CHECK-RV32-NEXT: j .LBB61_391 -; CHECK-RV32-NEXT: .LBB61_888: # %cond.load1465 +; CHECK-RV32-NEXT: .LBB61_899: # %cond.load1465 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8787,9 +8787,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 15 -; CHECK-RV32-NEXT: bltz a3, .LBB61_889 +; CHECK-RV32-NEXT: bltz a3, .LBB61_900 ; CHECK-RV32-NEXT: j .LBB61_392 -; CHECK-RV32-NEXT: .LBB61_889: # %cond.load1469 +; CHECK-RV32-NEXT: .LBB61_900: # %cond.load1469 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8800,9 +8800,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 14 -; CHECK-RV32-NEXT: bltz a3, .LBB61_890 +; CHECK-RV32-NEXT: bltz a3, .LBB61_901 ; CHECK-RV32-NEXT: j .LBB61_393 -; CHECK-RV32-NEXT: .LBB61_890: # %cond.load1473 +; CHECK-RV32-NEXT: .LBB61_901: # %cond.load1473 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8813,9 +8813,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 13 -; CHECK-RV32-NEXT: bltz a3, .LBB61_891 +; CHECK-RV32-NEXT: bltz a3, .LBB61_902 ; CHECK-RV32-NEXT: j .LBB61_394 -; CHECK-RV32-NEXT: .LBB61_891: # %cond.load1477 +; CHECK-RV32-NEXT: .LBB61_902: # %cond.load1477 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8826,9 +8826,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 12 -; CHECK-RV32-NEXT: bltz a3, .LBB61_892 +; CHECK-RV32-NEXT: bltz a3, .LBB61_903 ; CHECK-RV32-NEXT: j .LBB61_395 -; CHECK-RV32-NEXT: .LBB61_892: # %cond.load1481 +; CHECK-RV32-NEXT: .LBB61_903: # %cond.load1481 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8839,9 +8839,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 11 -; CHECK-RV32-NEXT: bltz a3, .LBB61_893 +; CHECK-RV32-NEXT: bltz a3, .LBB61_904 ; CHECK-RV32-NEXT: j .LBB61_396 -; CHECK-RV32-NEXT: .LBB61_893: # %cond.load1485 +; CHECK-RV32-NEXT: .LBB61_904: # %cond.load1485 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8852,9 +8852,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 10 -; CHECK-RV32-NEXT: bltz a3, .LBB61_894 +; CHECK-RV32-NEXT: bltz a3, .LBB61_905 ; CHECK-RV32-NEXT: j .LBB61_397 -; CHECK-RV32-NEXT: .LBB61_894: # %cond.load1489 +; CHECK-RV32-NEXT: .LBB61_905: # %cond.load1489 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8865,9 +8865,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 9 -; CHECK-RV32-NEXT: bltz a3, .LBB61_895 +; CHECK-RV32-NEXT: bltz a3, .LBB61_906 ; CHECK-RV32-NEXT: j .LBB61_398 -; CHECK-RV32-NEXT: .LBB61_895: # %cond.load1493 +; CHECK-RV32-NEXT: .LBB61_906: # %cond.load1493 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8878,9 +8878,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 8 -; CHECK-RV32-NEXT: bltz a3, .LBB61_896 +; CHECK-RV32-NEXT: bltz a3, .LBB61_907 ; CHECK-RV32-NEXT: j .LBB61_399 -; CHECK-RV32-NEXT: .LBB61_896: # %cond.load1497 +; CHECK-RV32-NEXT: .LBB61_907: # %cond.load1497 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8891,9 +8891,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 7 -; CHECK-RV32-NEXT: bltz a3, .LBB61_897 +; CHECK-RV32-NEXT: bltz a3, .LBB61_908 ; CHECK-RV32-NEXT: j .LBB61_400 -; CHECK-RV32-NEXT: .LBB61_897: # %cond.load1501 +; CHECK-RV32-NEXT: .LBB61_908: # %cond.load1501 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8904,9 +8904,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 6 -; CHECK-RV32-NEXT: bltz a3, .LBB61_898 +; CHECK-RV32-NEXT: bltz a3, .LBB61_909 ; CHECK-RV32-NEXT: j .LBB61_401 -; CHECK-RV32-NEXT: .LBB61_898: # %cond.load1505 +; CHECK-RV32-NEXT: .LBB61_909: # %cond.load1505 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8917,9 +8917,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 5 -; CHECK-RV32-NEXT: bltz a3, .LBB61_899 +; CHECK-RV32-NEXT: bltz a3, .LBB61_910 ; CHECK-RV32-NEXT: j .LBB61_402 -; CHECK-RV32-NEXT: .LBB61_899: # %cond.load1509 +; CHECK-RV32-NEXT: .LBB61_910: # %cond.load1509 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8930,9 +8930,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 4 -; CHECK-RV32-NEXT: bltz a3, .LBB61_900 +; CHECK-RV32-NEXT: bltz a3, .LBB61_911 ; CHECK-RV32-NEXT: j .LBB61_403 -; CHECK-RV32-NEXT: .LBB61_900: # %cond.load1513 +; CHECK-RV32-NEXT: .LBB61_911: # %cond.load1513 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8943,9 +8943,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 3 -; CHECK-RV32-NEXT: bltz a3, .LBB61_901 +; CHECK-RV32-NEXT: bltz a3, .LBB61_912 ; CHECK-RV32-NEXT: j .LBB61_404 -; CHECK-RV32-NEXT: .LBB61_901: # %cond.load1517 +; CHECK-RV32-NEXT: .LBB61_912: # %cond.load1517 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8956,11 +8956,11 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 2 -; CHECK-RV32-NEXT: bgez a3, .LBB61_1036 +; CHECK-RV32-NEXT: bgez a3, .LBB61_913 ; CHECK-RV32-NEXT: j .LBB61_405 -; CHECK-RV32-NEXT: .LBB61_1036: # %cond.load1517 +; CHECK-RV32-NEXT: .LBB61_913: # %cond.load1517 ; CHECK-RV32-NEXT: j .LBB61_406 -; CHECK-RV32-NEXT: .LBB61_902: # %cond.load1529 +; CHECK-RV32-NEXT: .LBB61_914: # %cond.load1529 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vmv.s.x v16, a2 ; CHECK-RV32-NEXT: li a2, 384 @@ -8969,9 +8969,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 1 -; CHECK-RV32-NEXT: bnez a2, .LBB61_903 +; CHECK-RV32-NEXT: bnez a2, .LBB61_915 ; CHECK-RV32-NEXT: j .LBB61_410 -; CHECK-RV32-NEXT: .LBB61_903: # %cond.load1533 +; CHECK-RV32-NEXT: .LBB61_915: # %cond.load1533 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8982,9 +8982,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 2 -; CHECK-RV32-NEXT: bnez a2, .LBB61_904 +; CHECK-RV32-NEXT: bnez a2, .LBB61_916 ; CHECK-RV32-NEXT: j .LBB61_411 -; CHECK-RV32-NEXT: .LBB61_904: # %cond.load1537 +; CHECK-RV32-NEXT: .LBB61_916: # %cond.load1537 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -8995,9 +8995,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 4 -; CHECK-RV32-NEXT: bnez a2, .LBB61_905 +; CHECK-RV32-NEXT: bnez a2, .LBB61_917 ; CHECK-RV32-NEXT: j .LBB61_412 -; CHECK-RV32-NEXT: .LBB61_905: # %cond.load1541 +; CHECK-RV32-NEXT: .LBB61_917: # %cond.load1541 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9008,9 +9008,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 8 -; CHECK-RV32-NEXT: bnez a2, .LBB61_906 +; CHECK-RV32-NEXT: bnez a2, .LBB61_918 ; CHECK-RV32-NEXT: j .LBB61_413 -; CHECK-RV32-NEXT: .LBB61_906: # %cond.load1545 +; CHECK-RV32-NEXT: .LBB61_918: # %cond.load1545 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9021,9 +9021,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 16 -; CHECK-RV32-NEXT: bnez a2, .LBB61_907 +; CHECK-RV32-NEXT: bnez a2, .LBB61_919 ; CHECK-RV32-NEXT: j .LBB61_414 -; CHECK-RV32-NEXT: .LBB61_907: # %cond.load1549 +; CHECK-RV32-NEXT: .LBB61_919: # %cond.load1549 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9034,9 +9034,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 32 -; CHECK-RV32-NEXT: bnez a2, .LBB61_908 +; CHECK-RV32-NEXT: bnez a2, .LBB61_920 ; CHECK-RV32-NEXT: j .LBB61_415 -; CHECK-RV32-NEXT: .LBB61_908: # %cond.load1553 +; CHECK-RV32-NEXT: .LBB61_920: # %cond.load1553 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9047,9 +9047,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 64 -; CHECK-RV32-NEXT: bnez a2, .LBB61_909 +; CHECK-RV32-NEXT: bnez a2, .LBB61_921 ; CHECK-RV32-NEXT: j .LBB61_416 -; CHECK-RV32-NEXT: .LBB61_909: # %cond.load1557 +; CHECK-RV32-NEXT: .LBB61_921: # %cond.load1557 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9060,9 +9060,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 128 -; CHECK-RV32-NEXT: bnez a2, .LBB61_910 +; CHECK-RV32-NEXT: bnez a2, .LBB61_922 ; CHECK-RV32-NEXT: j .LBB61_417 -; CHECK-RV32-NEXT: .LBB61_910: # %cond.load1561 +; CHECK-RV32-NEXT: .LBB61_922: # %cond.load1561 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9073,9 +9073,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 256 -; CHECK-RV32-NEXT: bnez a2, .LBB61_911 +; CHECK-RV32-NEXT: bnez a2, .LBB61_923 ; CHECK-RV32-NEXT: j .LBB61_418 -; CHECK-RV32-NEXT: .LBB61_911: # %cond.load1565 +; CHECK-RV32-NEXT: .LBB61_923: # %cond.load1565 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9086,9 +9086,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 512 -; CHECK-RV32-NEXT: bnez a2, .LBB61_912 +; CHECK-RV32-NEXT: bnez a2, .LBB61_924 ; CHECK-RV32-NEXT: j .LBB61_419 -; CHECK-RV32-NEXT: .LBB61_912: # %cond.load1569 +; CHECK-RV32-NEXT: .LBB61_924: # %cond.load1569 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9099,9 +9099,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 1024 -; CHECK-RV32-NEXT: bnez a2, .LBB61_913 +; CHECK-RV32-NEXT: bnez a2, .LBB61_925 ; CHECK-RV32-NEXT: j .LBB61_420 -; CHECK-RV32-NEXT: .LBB61_913: # %cond.load1573 +; CHECK-RV32-NEXT: .LBB61_925: # %cond.load1573 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9112,9 +9112,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 20 -; CHECK-RV32-NEXT: bltz a2, .LBB61_914 +; CHECK-RV32-NEXT: bltz a2, .LBB61_926 ; CHECK-RV32-NEXT: j .LBB61_421 -; CHECK-RV32-NEXT: .LBB61_914: # %cond.load1577 +; CHECK-RV32-NEXT: .LBB61_926: # %cond.load1577 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9125,9 +9125,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 19 -; CHECK-RV32-NEXT: bltz a2, .LBB61_915 +; CHECK-RV32-NEXT: bltz a2, .LBB61_927 ; CHECK-RV32-NEXT: j .LBB61_422 -; CHECK-RV32-NEXT: .LBB61_915: # %cond.load1581 +; CHECK-RV32-NEXT: .LBB61_927: # %cond.load1581 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9138,9 +9138,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 18 -; CHECK-RV32-NEXT: bltz a2, .LBB61_916 +; CHECK-RV32-NEXT: bltz a2, .LBB61_928 ; CHECK-RV32-NEXT: j .LBB61_423 -; CHECK-RV32-NEXT: .LBB61_916: # %cond.load1585 +; CHECK-RV32-NEXT: .LBB61_928: # %cond.load1585 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9151,9 +9151,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 17 -; CHECK-RV32-NEXT: bltz a2, .LBB61_917 +; CHECK-RV32-NEXT: bltz a2, .LBB61_929 ; CHECK-RV32-NEXT: j .LBB61_424 -; CHECK-RV32-NEXT: .LBB61_917: # %cond.load1589 +; CHECK-RV32-NEXT: .LBB61_929: # %cond.load1589 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9164,9 +9164,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 16 -; CHECK-RV32-NEXT: bltz a2, .LBB61_918 +; CHECK-RV32-NEXT: bltz a2, .LBB61_930 ; CHECK-RV32-NEXT: j .LBB61_425 -; CHECK-RV32-NEXT: .LBB61_918: # %cond.load1593 +; CHECK-RV32-NEXT: .LBB61_930: # %cond.load1593 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9177,9 +9177,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 15 -; CHECK-RV32-NEXT: bltz a2, .LBB61_919 +; CHECK-RV32-NEXT: bltz a2, .LBB61_931 ; CHECK-RV32-NEXT: j .LBB61_426 -; CHECK-RV32-NEXT: .LBB61_919: # %cond.load1597 +; CHECK-RV32-NEXT: .LBB61_931: # %cond.load1597 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9190,9 +9190,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 14 -; CHECK-RV32-NEXT: bltz a2, .LBB61_920 +; CHECK-RV32-NEXT: bltz a2, .LBB61_932 ; CHECK-RV32-NEXT: j .LBB61_427 -; CHECK-RV32-NEXT: .LBB61_920: # %cond.load1601 +; CHECK-RV32-NEXT: .LBB61_932: # %cond.load1601 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9203,9 +9203,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 13 -; CHECK-RV32-NEXT: bltz a2, .LBB61_921 +; CHECK-RV32-NEXT: bltz a2, .LBB61_933 ; CHECK-RV32-NEXT: j .LBB61_428 -; CHECK-RV32-NEXT: .LBB61_921: # %cond.load1605 +; CHECK-RV32-NEXT: .LBB61_933: # %cond.load1605 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9216,9 +9216,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 12 -; CHECK-RV32-NEXT: bltz a2, .LBB61_922 +; CHECK-RV32-NEXT: bltz a2, .LBB61_934 ; CHECK-RV32-NEXT: j .LBB61_429 -; CHECK-RV32-NEXT: .LBB61_922: # %cond.load1609 +; CHECK-RV32-NEXT: .LBB61_934: # %cond.load1609 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9229,9 +9229,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 11 -; CHECK-RV32-NEXT: bltz a2, .LBB61_923 +; CHECK-RV32-NEXT: bltz a2, .LBB61_935 ; CHECK-RV32-NEXT: j .LBB61_430 -; CHECK-RV32-NEXT: .LBB61_923: # %cond.load1613 +; CHECK-RV32-NEXT: .LBB61_935: # %cond.load1613 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9242,9 +9242,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 10 -; CHECK-RV32-NEXT: bltz a2, .LBB61_924 +; CHECK-RV32-NEXT: bltz a2, .LBB61_936 ; CHECK-RV32-NEXT: j .LBB61_431 -; CHECK-RV32-NEXT: .LBB61_924: # %cond.load1617 +; CHECK-RV32-NEXT: .LBB61_936: # %cond.load1617 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9255,9 +9255,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 9 -; CHECK-RV32-NEXT: bltz a2, .LBB61_925 +; CHECK-RV32-NEXT: bltz a2, .LBB61_937 ; CHECK-RV32-NEXT: j .LBB61_432 -; CHECK-RV32-NEXT: .LBB61_925: # %cond.load1621 +; CHECK-RV32-NEXT: .LBB61_937: # %cond.load1621 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9268,9 +9268,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 8 -; CHECK-RV32-NEXT: bltz a2, .LBB61_926 +; CHECK-RV32-NEXT: bltz a2, .LBB61_938 ; CHECK-RV32-NEXT: j .LBB61_433 -; CHECK-RV32-NEXT: .LBB61_926: # %cond.load1625 +; CHECK-RV32-NEXT: .LBB61_938: # %cond.load1625 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9281,9 +9281,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 7 -; CHECK-RV32-NEXT: bltz a2, .LBB61_927 +; CHECK-RV32-NEXT: bltz a2, .LBB61_939 ; CHECK-RV32-NEXT: j .LBB61_434 -; CHECK-RV32-NEXT: .LBB61_927: # %cond.load1629 +; CHECK-RV32-NEXT: .LBB61_939: # %cond.load1629 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9294,9 +9294,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 6 -; CHECK-RV32-NEXT: bltz a2, .LBB61_928 +; CHECK-RV32-NEXT: bltz a2, .LBB61_940 ; CHECK-RV32-NEXT: j .LBB61_435 -; CHECK-RV32-NEXT: .LBB61_928: # %cond.load1633 +; CHECK-RV32-NEXT: .LBB61_940: # %cond.load1633 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9307,9 +9307,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 5 -; CHECK-RV32-NEXT: bltz a2, .LBB61_929 +; CHECK-RV32-NEXT: bltz a2, .LBB61_941 ; CHECK-RV32-NEXT: j .LBB61_436 -; CHECK-RV32-NEXT: .LBB61_929: # %cond.load1637 +; CHECK-RV32-NEXT: .LBB61_941: # %cond.load1637 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9320,9 +9320,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 4 -; CHECK-RV32-NEXT: bltz a2, .LBB61_930 +; CHECK-RV32-NEXT: bltz a2, .LBB61_942 ; CHECK-RV32-NEXT: j .LBB61_437 -; CHECK-RV32-NEXT: .LBB61_930: # %cond.load1641 +; CHECK-RV32-NEXT: .LBB61_942: # %cond.load1641 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9333,9 +9333,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 3 -; CHECK-RV32-NEXT: bltz a2, .LBB61_931 +; CHECK-RV32-NEXT: bltz a2, .LBB61_943 ; CHECK-RV32-NEXT: j .LBB61_438 -; CHECK-RV32-NEXT: .LBB61_931: # %cond.load1645 +; CHECK-RV32-NEXT: .LBB61_943: # %cond.load1645 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9346,11 +9346,11 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 2 -; CHECK-RV32-NEXT: bgez a2, .LBB61_1037 +; CHECK-RV32-NEXT: bgez a2, .LBB61_944 ; CHECK-RV32-NEXT: j .LBB61_439 -; CHECK-RV32-NEXT: .LBB61_1037: # %cond.load1645 +; CHECK-RV32-NEXT: .LBB61_944: # %cond.load1645 ; CHECK-RV32-NEXT: j .LBB61_440 -; CHECK-RV32-NEXT: .LBB61_932: # %cond.load1657 +; CHECK-RV32-NEXT: .LBB61_945: # %cond.load1657 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: vmv.s.x v16, a3 ; CHECK-RV32-NEXT: li a3, 416 @@ -9359,9 +9359,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a3, a2, 1 -; CHECK-RV32-NEXT: bnez a3, .LBB61_933 +; CHECK-RV32-NEXT: bnez a3, .LBB61_946 ; CHECK-RV32-NEXT: j .LBB61_444 -; CHECK-RV32-NEXT: .LBB61_933: # %cond.load1661 +; CHECK-RV32-NEXT: .LBB61_946: # %cond.load1661 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9372,9 +9372,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a3, a2, 2 -; CHECK-RV32-NEXT: bnez a3, .LBB61_934 +; CHECK-RV32-NEXT: bnez a3, .LBB61_947 ; CHECK-RV32-NEXT: j .LBB61_445 -; CHECK-RV32-NEXT: .LBB61_934: # %cond.load1665 +; CHECK-RV32-NEXT: .LBB61_947: # %cond.load1665 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9385,9 +9385,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a3, a2, 4 -; CHECK-RV32-NEXT: bnez a3, .LBB61_935 +; CHECK-RV32-NEXT: bnez a3, .LBB61_948 ; CHECK-RV32-NEXT: j .LBB61_446 -; CHECK-RV32-NEXT: .LBB61_935: # %cond.load1669 +; CHECK-RV32-NEXT: .LBB61_948: # %cond.load1669 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9398,9 +9398,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a3, a2, 8 -; CHECK-RV32-NEXT: bnez a3, .LBB61_936 +; CHECK-RV32-NEXT: bnez a3, .LBB61_949 ; CHECK-RV32-NEXT: j .LBB61_447 -; CHECK-RV32-NEXT: .LBB61_936: # %cond.load1673 +; CHECK-RV32-NEXT: .LBB61_949: # %cond.load1673 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9411,9 +9411,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a3, a2, 16 -; CHECK-RV32-NEXT: bnez a3, .LBB61_937 +; CHECK-RV32-NEXT: bnez a3, .LBB61_950 ; CHECK-RV32-NEXT: j .LBB61_448 -; CHECK-RV32-NEXT: .LBB61_937: # %cond.load1677 +; CHECK-RV32-NEXT: .LBB61_950: # %cond.load1677 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9424,9 +9424,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a3, a2, 32 -; CHECK-RV32-NEXT: bnez a3, .LBB61_938 +; CHECK-RV32-NEXT: bnez a3, .LBB61_951 ; CHECK-RV32-NEXT: j .LBB61_449 -; CHECK-RV32-NEXT: .LBB61_938: # %cond.load1681 +; CHECK-RV32-NEXT: .LBB61_951: # %cond.load1681 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9437,9 +9437,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a3, a2, 64 -; CHECK-RV32-NEXT: bnez a3, .LBB61_939 +; CHECK-RV32-NEXT: bnez a3, .LBB61_952 ; CHECK-RV32-NEXT: j .LBB61_450 -; CHECK-RV32-NEXT: .LBB61_939: # %cond.load1685 +; CHECK-RV32-NEXT: .LBB61_952: # %cond.load1685 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9450,9 +9450,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a3, a2, 128 -; CHECK-RV32-NEXT: bnez a3, .LBB61_940 +; CHECK-RV32-NEXT: bnez a3, .LBB61_953 ; CHECK-RV32-NEXT: j .LBB61_451 -; CHECK-RV32-NEXT: .LBB61_940: # %cond.load1689 +; CHECK-RV32-NEXT: .LBB61_953: # %cond.load1689 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9463,9 +9463,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a3, a2, 256 -; CHECK-RV32-NEXT: bnez a3, .LBB61_941 +; CHECK-RV32-NEXT: bnez a3, .LBB61_954 ; CHECK-RV32-NEXT: j .LBB61_452 -; CHECK-RV32-NEXT: .LBB61_941: # %cond.load1693 +; CHECK-RV32-NEXT: .LBB61_954: # %cond.load1693 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9476,9 +9476,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a3, a2, 512 -; CHECK-RV32-NEXT: bnez a3, .LBB61_942 +; CHECK-RV32-NEXT: bnez a3, .LBB61_955 ; CHECK-RV32-NEXT: j .LBB61_453 -; CHECK-RV32-NEXT: .LBB61_942: # %cond.load1697 +; CHECK-RV32-NEXT: .LBB61_955: # %cond.load1697 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9489,9 +9489,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a3, a2, 1024 -; CHECK-RV32-NEXT: bnez a3, .LBB61_943 +; CHECK-RV32-NEXT: bnez a3, .LBB61_956 ; CHECK-RV32-NEXT: j .LBB61_454 -; CHECK-RV32-NEXT: .LBB61_943: # %cond.load1701 +; CHECK-RV32-NEXT: .LBB61_956: # %cond.load1701 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9502,9 +9502,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 20 -; CHECK-RV32-NEXT: bltz a3, .LBB61_944 +; CHECK-RV32-NEXT: bltz a3, .LBB61_957 ; CHECK-RV32-NEXT: j .LBB61_455 -; CHECK-RV32-NEXT: .LBB61_944: # %cond.load1705 +; CHECK-RV32-NEXT: .LBB61_957: # %cond.load1705 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9515,9 +9515,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 19 -; CHECK-RV32-NEXT: bltz a3, .LBB61_945 +; CHECK-RV32-NEXT: bltz a3, .LBB61_958 ; CHECK-RV32-NEXT: j .LBB61_456 -; CHECK-RV32-NEXT: .LBB61_945: # %cond.load1709 +; CHECK-RV32-NEXT: .LBB61_958: # %cond.load1709 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9528,9 +9528,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 18 -; CHECK-RV32-NEXT: bltz a3, .LBB61_946 +; CHECK-RV32-NEXT: bltz a3, .LBB61_959 ; CHECK-RV32-NEXT: j .LBB61_457 -; CHECK-RV32-NEXT: .LBB61_946: # %cond.load1713 +; CHECK-RV32-NEXT: .LBB61_959: # %cond.load1713 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9541,9 +9541,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 17 -; CHECK-RV32-NEXT: bltz a3, .LBB61_947 +; CHECK-RV32-NEXT: bltz a3, .LBB61_960 ; CHECK-RV32-NEXT: j .LBB61_458 -; CHECK-RV32-NEXT: .LBB61_947: # %cond.load1717 +; CHECK-RV32-NEXT: .LBB61_960: # %cond.load1717 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9554,9 +9554,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 16 -; CHECK-RV32-NEXT: bltz a3, .LBB61_948 +; CHECK-RV32-NEXT: bltz a3, .LBB61_961 ; CHECK-RV32-NEXT: j .LBB61_459 -; CHECK-RV32-NEXT: .LBB61_948: # %cond.load1721 +; CHECK-RV32-NEXT: .LBB61_961: # %cond.load1721 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9567,9 +9567,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 15 -; CHECK-RV32-NEXT: bltz a3, .LBB61_949 +; CHECK-RV32-NEXT: bltz a3, .LBB61_962 ; CHECK-RV32-NEXT: j .LBB61_460 -; CHECK-RV32-NEXT: .LBB61_949: # %cond.load1725 +; CHECK-RV32-NEXT: .LBB61_962: # %cond.load1725 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9580,9 +9580,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 14 -; CHECK-RV32-NEXT: bltz a3, .LBB61_950 +; CHECK-RV32-NEXT: bltz a3, .LBB61_963 ; CHECK-RV32-NEXT: j .LBB61_461 -; CHECK-RV32-NEXT: .LBB61_950: # %cond.load1729 +; CHECK-RV32-NEXT: .LBB61_963: # %cond.load1729 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9593,9 +9593,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 13 -; CHECK-RV32-NEXT: bltz a3, .LBB61_951 +; CHECK-RV32-NEXT: bltz a3, .LBB61_964 ; CHECK-RV32-NEXT: j .LBB61_462 -; CHECK-RV32-NEXT: .LBB61_951: # %cond.load1733 +; CHECK-RV32-NEXT: .LBB61_964: # %cond.load1733 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9606,9 +9606,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 12 -; CHECK-RV32-NEXT: bltz a3, .LBB61_952 +; CHECK-RV32-NEXT: bltz a3, .LBB61_965 ; CHECK-RV32-NEXT: j .LBB61_463 -; CHECK-RV32-NEXT: .LBB61_952: # %cond.load1737 +; CHECK-RV32-NEXT: .LBB61_965: # %cond.load1737 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9619,9 +9619,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 11 -; CHECK-RV32-NEXT: bltz a3, .LBB61_953 +; CHECK-RV32-NEXT: bltz a3, .LBB61_966 ; CHECK-RV32-NEXT: j .LBB61_464 -; CHECK-RV32-NEXT: .LBB61_953: # %cond.load1741 +; CHECK-RV32-NEXT: .LBB61_966: # %cond.load1741 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9632,9 +9632,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 10 -; CHECK-RV32-NEXT: bltz a3, .LBB61_954 +; CHECK-RV32-NEXT: bltz a3, .LBB61_967 ; CHECK-RV32-NEXT: j .LBB61_465 -; CHECK-RV32-NEXT: .LBB61_954: # %cond.load1745 +; CHECK-RV32-NEXT: .LBB61_967: # %cond.load1745 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9645,9 +9645,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 9 -; CHECK-RV32-NEXT: bltz a3, .LBB61_955 +; CHECK-RV32-NEXT: bltz a3, .LBB61_968 ; CHECK-RV32-NEXT: j .LBB61_466 -; CHECK-RV32-NEXT: .LBB61_955: # %cond.load1749 +; CHECK-RV32-NEXT: .LBB61_968: # %cond.load1749 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9658,9 +9658,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 8 -; CHECK-RV32-NEXT: bltz a3, .LBB61_956 +; CHECK-RV32-NEXT: bltz a3, .LBB61_969 ; CHECK-RV32-NEXT: j .LBB61_467 -; CHECK-RV32-NEXT: .LBB61_956: # %cond.load1753 +; CHECK-RV32-NEXT: .LBB61_969: # %cond.load1753 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9671,9 +9671,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 7 -; CHECK-RV32-NEXT: bltz a3, .LBB61_957 +; CHECK-RV32-NEXT: bltz a3, .LBB61_970 ; CHECK-RV32-NEXT: j .LBB61_468 -; CHECK-RV32-NEXT: .LBB61_957: # %cond.load1757 +; CHECK-RV32-NEXT: .LBB61_970: # %cond.load1757 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9684,9 +9684,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 6 -; CHECK-RV32-NEXT: bltz a3, .LBB61_958 +; CHECK-RV32-NEXT: bltz a3, .LBB61_971 ; CHECK-RV32-NEXT: j .LBB61_469 -; CHECK-RV32-NEXT: .LBB61_958: # %cond.load1761 +; CHECK-RV32-NEXT: .LBB61_971: # %cond.load1761 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9697,9 +9697,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 5 -; CHECK-RV32-NEXT: bltz a3, .LBB61_959 +; CHECK-RV32-NEXT: bltz a3, .LBB61_972 ; CHECK-RV32-NEXT: j .LBB61_470 -; CHECK-RV32-NEXT: .LBB61_959: # %cond.load1765 +; CHECK-RV32-NEXT: .LBB61_972: # %cond.load1765 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9710,9 +9710,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 4 -; CHECK-RV32-NEXT: bltz a3, .LBB61_960 +; CHECK-RV32-NEXT: bltz a3, .LBB61_973 ; CHECK-RV32-NEXT: j .LBB61_471 -; CHECK-RV32-NEXT: .LBB61_960: # %cond.load1769 +; CHECK-RV32-NEXT: .LBB61_973: # %cond.load1769 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9723,9 +9723,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 3 -; CHECK-RV32-NEXT: bltz a3, .LBB61_961 +; CHECK-RV32-NEXT: bltz a3, .LBB61_974 ; CHECK-RV32-NEXT: j .LBB61_472 -; CHECK-RV32-NEXT: .LBB61_961: # %cond.load1773 +; CHECK-RV32-NEXT: .LBB61_974: # %cond.load1773 ; CHECK-RV32-NEXT: lbu a3, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9736,11 +9736,11 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a3, a2, 2 -; CHECK-RV32-NEXT: bgez a3, .LBB61_1038 +; CHECK-RV32-NEXT: bgez a3, .LBB61_975 ; CHECK-RV32-NEXT: j .LBB61_473 -; CHECK-RV32-NEXT: .LBB61_1038: # %cond.load1773 +; CHECK-RV32-NEXT: .LBB61_975: # %cond.load1773 ; CHECK-RV32-NEXT: j .LBB61_474 -; CHECK-RV32-NEXT: .LBB61_962: # %cond.load1785 +; CHECK-RV32-NEXT: .LBB61_976: # %cond.load1785 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vmv.s.x v16, a2 ; CHECK-RV32-NEXT: li a2, 448 @@ -9749,9 +9749,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 1 -; CHECK-RV32-NEXT: bnez a2, .LBB61_963 +; CHECK-RV32-NEXT: bnez a2, .LBB61_977 ; CHECK-RV32-NEXT: j .LBB61_478 -; CHECK-RV32-NEXT: .LBB61_963: # %cond.load1789 +; CHECK-RV32-NEXT: .LBB61_977: # %cond.load1789 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9762,9 +9762,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 2 -; CHECK-RV32-NEXT: bnez a2, .LBB61_964 +; CHECK-RV32-NEXT: bnez a2, .LBB61_978 ; CHECK-RV32-NEXT: j .LBB61_479 -; CHECK-RV32-NEXT: .LBB61_964: # %cond.load1793 +; CHECK-RV32-NEXT: .LBB61_978: # %cond.load1793 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9775,9 +9775,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 4 -; CHECK-RV32-NEXT: bnez a2, .LBB61_965 +; CHECK-RV32-NEXT: bnez a2, .LBB61_979 ; CHECK-RV32-NEXT: j .LBB61_480 -; CHECK-RV32-NEXT: .LBB61_965: # %cond.load1797 +; CHECK-RV32-NEXT: .LBB61_979: # %cond.load1797 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9788,9 +9788,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 8 -; CHECK-RV32-NEXT: bnez a2, .LBB61_966 +; CHECK-RV32-NEXT: bnez a2, .LBB61_980 ; CHECK-RV32-NEXT: j .LBB61_481 -; CHECK-RV32-NEXT: .LBB61_966: # %cond.load1801 +; CHECK-RV32-NEXT: .LBB61_980: # %cond.load1801 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9801,9 +9801,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 16 -; CHECK-RV32-NEXT: bnez a2, .LBB61_967 +; CHECK-RV32-NEXT: bnez a2, .LBB61_981 ; CHECK-RV32-NEXT: j .LBB61_482 -; CHECK-RV32-NEXT: .LBB61_967: # %cond.load1805 +; CHECK-RV32-NEXT: .LBB61_981: # %cond.load1805 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9814,9 +9814,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 32 -; CHECK-RV32-NEXT: bnez a2, .LBB61_968 +; CHECK-RV32-NEXT: bnez a2, .LBB61_982 ; CHECK-RV32-NEXT: j .LBB61_483 -; CHECK-RV32-NEXT: .LBB61_968: # %cond.load1809 +; CHECK-RV32-NEXT: .LBB61_982: # %cond.load1809 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9827,9 +9827,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 64 -; CHECK-RV32-NEXT: bnez a2, .LBB61_969 +; CHECK-RV32-NEXT: bnez a2, .LBB61_983 ; CHECK-RV32-NEXT: j .LBB61_484 -; CHECK-RV32-NEXT: .LBB61_969: # %cond.load1813 +; CHECK-RV32-NEXT: .LBB61_983: # %cond.load1813 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9840,9 +9840,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 128 -; CHECK-RV32-NEXT: bnez a2, .LBB61_970 +; CHECK-RV32-NEXT: bnez a2, .LBB61_984 ; CHECK-RV32-NEXT: j .LBB61_485 -; CHECK-RV32-NEXT: .LBB61_970: # %cond.load1817 +; CHECK-RV32-NEXT: .LBB61_984: # %cond.load1817 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9853,9 +9853,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 256 -; CHECK-RV32-NEXT: bnez a2, .LBB61_971 +; CHECK-RV32-NEXT: bnez a2, .LBB61_985 ; CHECK-RV32-NEXT: j .LBB61_486 -; CHECK-RV32-NEXT: .LBB61_971: # %cond.load1821 +; CHECK-RV32-NEXT: .LBB61_985: # %cond.load1821 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9866,9 +9866,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 512 -; CHECK-RV32-NEXT: bnez a2, .LBB61_972 +; CHECK-RV32-NEXT: bnez a2, .LBB61_986 ; CHECK-RV32-NEXT: j .LBB61_487 -; CHECK-RV32-NEXT: .LBB61_972: # %cond.load1825 +; CHECK-RV32-NEXT: .LBB61_986: # %cond.load1825 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9879,9 +9879,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a3, 1024 -; CHECK-RV32-NEXT: bnez a2, .LBB61_973 +; CHECK-RV32-NEXT: bnez a2, .LBB61_987 ; CHECK-RV32-NEXT: j .LBB61_488 -; CHECK-RV32-NEXT: .LBB61_973: # %cond.load1829 +; CHECK-RV32-NEXT: .LBB61_987: # %cond.load1829 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9892,9 +9892,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 20 -; CHECK-RV32-NEXT: bltz a2, .LBB61_974 +; CHECK-RV32-NEXT: bltz a2, .LBB61_988 ; CHECK-RV32-NEXT: j .LBB61_489 -; CHECK-RV32-NEXT: .LBB61_974: # %cond.load1833 +; CHECK-RV32-NEXT: .LBB61_988: # %cond.load1833 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9905,9 +9905,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 19 -; CHECK-RV32-NEXT: bltz a2, .LBB61_975 +; CHECK-RV32-NEXT: bltz a2, .LBB61_989 ; CHECK-RV32-NEXT: j .LBB61_490 -; CHECK-RV32-NEXT: .LBB61_975: # %cond.load1837 +; CHECK-RV32-NEXT: .LBB61_989: # %cond.load1837 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9918,9 +9918,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 18 -; CHECK-RV32-NEXT: bltz a2, .LBB61_976 +; CHECK-RV32-NEXT: bltz a2, .LBB61_990 ; CHECK-RV32-NEXT: j .LBB61_491 -; CHECK-RV32-NEXT: .LBB61_976: # %cond.load1841 +; CHECK-RV32-NEXT: .LBB61_990: # %cond.load1841 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9931,9 +9931,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 17 -; CHECK-RV32-NEXT: bltz a2, .LBB61_977 +; CHECK-RV32-NEXT: bltz a2, .LBB61_991 ; CHECK-RV32-NEXT: j .LBB61_492 -; CHECK-RV32-NEXT: .LBB61_977: # %cond.load1845 +; CHECK-RV32-NEXT: .LBB61_991: # %cond.load1845 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9944,9 +9944,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 16 -; CHECK-RV32-NEXT: bltz a2, .LBB61_978 +; CHECK-RV32-NEXT: bltz a2, .LBB61_992 ; CHECK-RV32-NEXT: j .LBB61_493 -; CHECK-RV32-NEXT: .LBB61_978: # %cond.load1849 +; CHECK-RV32-NEXT: .LBB61_992: # %cond.load1849 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9957,9 +9957,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 15 -; CHECK-RV32-NEXT: bltz a2, .LBB61_979 +; CHECK-RV32-NEXT: bltz a2, .LBB61_993 ; CHECK-RV32-NEXT: j .LBB61_494 -; CHECK-RV32-NEXT: .LBB61_979: # %cond.load1853 +; CHECK-RV32-NEXT: .LBB61_993: # %cond.load1853 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9970,9 +9970,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 14 -; CHECK-RV32-NEXT: bltz a2, .LBB61_980 +; CHECK-RV32-NEXT: bltz a2, .LBB61_994 ; CHECK-RV32-NEXT: j .LBB61_495 -; CHECK-RV32-NEXT: .LBB61_980: # %cond.load1857 +; CHECK-RV32-NEXT: .LBB61_994: # %cond.load1857 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9983,9 +9983,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 13 -; CHECK-RV32-NEXT: bltz a2, .LBB61_981 +; CHECK-RV32-NEXT: bltz a2, .LBB61_995 ; CHECK-RV32-NEXT: j .LBB61_496 -; CHECK-RV32-NEXT: .LBB61_981: # %cond.load1861 +; CHECK-RV32-NEXT: .LBB61_995: # %cond.load1861 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -9996,9 +9996,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 12 -; CHECK-RV32-NEXT: bltz a2, .LBB61_982 +; CHECK-RV32-NEXT: bltz a2, .LBB61_996 ; CHECK-RV32-NEXT: j .LBB61_497 -; CHECK-RV32-NEXT: .LBB61_982: # %cond.load1865 +; CHECK-RV32-NEXT: .LBB61_996: # %cond.load1865 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -10009,9 +10009,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 11 -; CHECK-RV32-NEXT: bltz a2, .LBB61_983 +; CHECK-RV32-NEXT: bltz a2, .LBB61_997 ; CHECK-RV32-NEXT: j .LBB61_498 -; CHECK-RV32-NEXT: .LBB61_983: # %cond.load1869 +; CHECK-RV32-NEXT: .LBB61_997: # %cond.load1869 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -10022,9 +10022,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 10 -; CHECK-RV32-NEXT: bltz a2, .LBB61_984 +; CHECK-RV32-NEXT: bltz a2, .LBB61_998 ; CHECK-RV32-NEXT: j .LBB61_499 -; CHECK-RV32-NEXT: .LBB61_984: # %cond.load1873 +; CHECK-RV32-NEXT: .LBB61_998: # %cond.load1873 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -10035,9 +10035,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 9 -; CHECK-RV32-NEXT: bltz a2, .LBB61_985 +; CHECK-RV32-NEXT: bltz a2, .LBB61_999 ; CHECK-RV32-NEXT: j .LBB61_500 -; CHECK-RV32-NEXT: .LBB61_985: # %cond.load1877 +; CHECK-RV32-NEXT: .LBB61_999: # %cond.load1877 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -10048,9 +10048,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 8 -; CHECK-RV32-NEXT: bltz a2, .LBB61_986 +; CHECK-RV32-NEXT: bltz a2, .LBB61_1000 ; CHECK-RV32-NEXT: j .LBB61_501 -; CHECK-RV32-NEXT: .LBB61_986: # %cond.load1881 +; CHECK-RV32-NEXT: .LBB61_1000: # %cond.load1881 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -10061,9 +10061,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 7 -; CHECK-RV32-NEXT: bltz a2, .LBB61_987 +; CHECK-RV32-NEXT: bltz a2, .LBB61_1001 ; CHECK-RV32-NEXT: j .LBB61_502 -; CHECK-RV32-NEXT: .LBB61_987: # %cond.load1885 +; CHECK-RV32-NEXT: .LBB61_1001: # %cond.load1885 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -10074,9 +10074,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 6 -; CHECK-RV32-NEXT: bltz a2, .LBB61_988 +; CHECK-RV32-NEXT: bltz a2, .LBB61_1002 ; CHECK-RV32-NEXT: j .LBB61_503 -; CHECK-RV32-NEXT: .LBB61_988: # %cond.load1889 +; CHECK-RV32-NEXT: .LBB61_1002: # %cond.load1889 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -10087,9 +10087,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 5 -; CHECK-RV32-NEXT: bltz a2, .LBB61_989 +; CHECK-RV32-NEXT: bltz a2, .LBB61_1003 ; CHECK-RV32-NEXT: j .LBB61_504 -; CHECK-RV32-NEXT: .LBB61_989: # %cond.load1893 +; CHECK-RV32-NEXT: .LBB61_1003: # %cond.load1893 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -10100,9 +10100,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 4 -; CHECK-RV32-NEXT: bltz a2, .LBB61_990 +; CHECK-RV32-NEXT: bltz a2, .LBB61_1004 ; CHECK-RV32-NEXT: j .LBB61_505 -; CHECK-RV32-NEXT: .LBB61_990: # %cond.load1897 +; CHECK-RV32-NEXT: .LBB61_1004: # %cond.load1897 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -10113,9 +10113,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 3 -; CHECK-RV32-NEXT: bltz a2, .LBB61_991 +; CHECK-RV32-NEXT: bltz a2, .LBB61_1005 ; CHECK-RV32-NEXT: j .LBB61_506 -; CHECK-RV32-NEXT: .LBB61_991: # %cond.load1901 +; CHECK-RV32-NEXT: .LBB61_1005: # %cond.load1901 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a4, 512 ; CHECK-RV32-NEXT: vsetvli zero, a4, e8, m1, ta, ma @@ -10126,11 +10126,11 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a4 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a3, 2 -; CHECK-RV32-NEXT: bgez a2, .LBB61_1039 +; CHECK-RV32-NEXT: bgez a2, .LBB61_1006 ; CHECK-RV32-NEXT: j .LBB61_507 -; CHECK-RV32-NEXT: .LBB61_1039: # %cond.load1901 +; CHECK-RV32-NEXT: .LBB61_1006: # %cond.load1901 ; CHECK-RV32-NEXT: j .LBB61_508 -; CHECK-RV32-NEXT: .LBB61_992: # %cond.load1913 +; CHECK-RV32-NEXT: .LBB61_1007: # %cond.load1913 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: vmv.s.x v16, a2 ; CHECK-RV32-NEXT: li a2, 480 @@ -10139,9 +10139,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a1, 1 -; CHECK-RV32-NEXT: bnez a2, .LBB61_993 +; CHECK-RV32-NEXT: bnez a2, .LBB61_1008 ; CHECK-RV32-NEXT: j .LBB61_512 -; CHECK-RV32-NEXT: .LBB61_993: # %cond.load1917 +; CHECK-RV32-NEXT: .LBB61_1008: # %cond.load1917 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a3, 512 ; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -10152,9 +10152,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a1, 2 -; CHECK-RV32-NEXT: bnez a2, .LBB61_994 +; CHECK-RV32-NEXT: bnez a2, .LBB61_1009 ; CHECK-RV32-NEXT: j .LBB61_513 -; CHECK-RV32-NEXT: .LBB61_994: # %cond.load1921 +; CHECK-RV32-NEXT: .LBB61_1009: # %cond.load1921 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a3, 512 ; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -10165,9 +10165,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a1, 4 -; CHECK-RV32-NEXT: bnez a2, .LBB61_995 +; CHECK-RV32-NEXT: bnez a2, .LBB61_1010 ; CHECK-RV32-NEXT: j .LBB61_514 -; CHECK-RV32-NEXT: .LBB61_995: # %cond.load1925 +; CHECK-RV32-NEXT: .LBB61_1010: # %cond.load1925 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a3, 512 ; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -10178,9 +10178,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a1, 8 -; CHECK-RV32-NEXT: bnez a2, .LBB61_996 +; CHECK-RV32-NEXT: bnez a2, .LBB61_1011 ; CHECK-RV32-NEXT: j .LBB61_515 -; CHECK-RV32-NEXT: .LBB61_996: # %cond.load1929 +; CHECK-RV32-NEXT: .LBB61_1011: # %cond.load1929 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a3, 512 ; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -10191,9 +10191,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a1, 16 -; CHECK-RV32-NEXT: bnez a2, .LBB61_997 +; CHECK-RV32-NEXT: bnez a2, .LBB61_1012 ; CHECK-RV32-NEXT: j .LBB61_516 -; CHECK-RV32-NEXT: .LBB61_997: # %cond.load1933 +; CHECK-RV32-NEXT: .LBB61_1012: # %cond.load1933 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a3, 512 ; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -10204,9 +10204,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a1, 32 -; CHECK-RV32-NEXT: bnez a2, .LBB61_998 +; CHECK-RV32-NEXT: bnez a2, .LBB61_1013 ; CHECK-RV32-NEXT: j .LBB61_517 -; CHECK-RV32-NEXT: .LBB61_998: # %cond.load1937 +; CHECK-RV32-NEXT: .LBB61_1013: # %cond.load1937 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a3, 512 ; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -10217,9 +10217,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a1, 64 -; CHECK-RV32-NEXT: bnez a2, .LBB61_999 +; CHECK-RV32-NEXT: bnez a2, .LBB61_1014 ; CHECK-RV32-NEXT: j .LBB61_518 -; CHECK-RV32-NEXT: .LBB61_999: # %cond.load1941 +; CHECK-RV32-NEXT: .LBB61_1014: # %cond.load1941 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a3, 512 ; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -10230,9 +10230,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a1, 128 -; CHECK-RV32-NEXT: bnez a2, .LBB61_1000 +; CHECK-RV32-NEXT: bnez a2, .LBB61_1015 ; CHECK-RV32-NEXT: j .LBB61_519 -; CHECK-RV32-NEXT: .LBB61_1000: # %cond.load1945 +; CHECK-RV32-NEXT: .LBB61_1015: # %cond.load1945 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a3, 512 ; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -10243,9 +10243,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a1, 256 -; CHECK-RV32-NEXT: bnez a2, .LBB61_1001 +; CHECK-RV32-NEXT: bnez a2, .LBB61_1016 ; CHECK-RV32-NEXT: j .LBB61_520 -; CHECK-RV32-NEXT: .LBB61_1001: # %cond.load1949 +; CHECK-RV32-NEXT: .LBB61_1016: # %cond.load1949 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a3, 512 ; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -10256,9 +10256,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a1, 512 -; CHECK-RV32-NEXT: bnez a2, .LBB61_1002 +; CHECK-RV32-NEXT: bnez a2, .LBB61_1017 ; CHECK-RV32-NEXT: j .LBB61_521 -; CHECK-RV32-NEXT: .LBB61_1002: # %cond.load1953 +; CHECK-RV32-NEXT: .LBB61_1017: # %cond.load1953 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a3, 512 ; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -10269,9 +10269,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: andi a2, a1, 1024 -; CHECK-RV32-NEXT: bnez a2, .LBB61_1003 +; CHECK-RV32-NEXT: bnez a2, .LBB61_1018 ; CHECK-RV32-NEXT: j .LBB61_522 -; CHECK-RV32-NEXT: .LBB61_1003: # %cond.load1957 +; CHECK-RV32-NEXT: .LBB61_1018: # %cond.load1957 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a3, 512 ; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -10282,9 +10282,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a1, 20 -; CHECK-RV32-NEXT: bltz a2, .LBB61_1004 +; CHECK-RV32-NEXT: bltz a2, .LBB61_1019 ; CHECK-RV32-NEXT: j .LBB61_523 -; CHECK-RV32-NEXT: .LBB61_1004: # %cond.load1961 +; CHECK-RV32-NEXT: .LBB61_1019: # %cond.load1961 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a3, 512 ; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -10295,9 +10295,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a1, 19 -; CHECK-RV32-NEXT: bltz a2, .LBB61_1005 +; CHECK-RV32-NEXT: bltz a2, .LBB61_1020 ; CHECK-RV32-NEXT: j .LBB61_524 -; CHECK-RV32-NEXT: .LBB61_1005: # %cond.load1965 +; CHECK-RV32-NEXT: .LBB61_1020: # %cond.load1965 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a3, 512 ; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -10308,9 +10308,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a1, 18 -; CHECK-RV32-NEXT: bltz a2, .LBB61_1006 +; CHECK-RV32-NEXT: bltz a2, .LBB61_1021 ; CHECK-RV32-NEXT: j .LBB61_525 -; CHECK-RV32-NEXT: .LBB61_1006: # %cond.load1969 +; CHECK-RV32-NEXT: .LBB61_1021: # %cond.load1969 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a3, 512 ; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -10321,9 +10321,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a1, 17 -; CHECK-RV32-NEXT: bltz a2, .LBB61_1007 +; CHECK-RV32-NEXT: bltz a2, .LBB61_1022 ; CHECK-RV32-NEXT: j .LBB61_526 -; CHECK-RV32-NEXT: .LBB61_1007: # %cond.load1973 +; CHECK-RV32-NEXT: .LBB61_1022: # %cond.load1973 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a3, 512 ; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -10334,9 +10334,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a1, 16 -; CHECK-RV32-NEXT: bltz a2, .LBB61_1008 +; CHECK-RV32-NEXT: bltz a2, .LBB61_1023 ; CHECK-RV32-NEXT: j .LBB61_527 -; CHECK-RV32-NEXT: .LBB61_1008: # %cond.load1977 +; CHECK-RV32-NEXT: .LBB61_1023: # %cond.load1977 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a3, 512 ; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -10347,9 +10347,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a1, 15 -; CHECK-RV32-NEXT: bltz a2, .LBB61_1009 +; CHECK-RV32-NEXT: bltz a2, .LBB61_1024 ; CHECK-RV32-NEXT: j .LBB61_528 -; CHECK-RV32-NEXT: .LBB61_1009: # %cond.load1981 +; CHECK-RV32-NEXT: .LBB61_1024: # %cond.load1981 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a3, 512 ; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -10360,9 +10360,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a1, 14 -; CHECK-RV32-NEXT: bltz a2, .LBB61_1010 +; CHECK-RV32-NEXT: bltz a2, .LBB61_1025 ; CHECK-RV32-NEXT: j .LBB61_529 -; CHECK-RV32-NEXT: .LBB61_1010: # %cond.load1985 +; CHECK-RV32-NEXT: .LBB61_1025: # %cond.load1985 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a3, 512 ; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -10373,9 +10373,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a1, 13 -; CHECK-RV32-NEXT: bltz a2, .LBB61_1011 +; CHECK-RV32-NEXT: bltz a2, .LBB61_1026 ; CHECK-RV32-NEXT: j .LBB61_530 -; CHECK-RV32-NEXT: .LBB61_1011: # %cond.load1989 +; CHECK-RV32-NEXT: .LBB61_1026: # %cond.load1989 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a3, 512 ; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -10386,9 +10386,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a1, 12 -; CHECK-RV32-NEXT: bltz a2, .LBB61_1012 +; CHECK-RV32-NEXT: bltz a2, .LBB61_1027 ; CHECK-RV32-NEXT: j .LBB61_531 -; CHECK-RV32-NEXT: .LBB61_1012: # %cond.load1993 +; CHECK-RV32-NEXT: .LBB61_1027: # %cond.load1993 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a3, 512 ; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -10399,9 +10399,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a1, 11 -; CHECK-RV32-NEXT: bltz a2, .LBB61_1013 +; CHECK-RV32-NEXT: bltz a2, .LBB61_1028 ; CHECK-RV32-NEXT: j .LBB61_532 -; CHECK-RV32-NEXT: .LBB61_1013: # %cond.load1997 +; CHECK-RV32-NEXT: .LBB61_1028: # %cond.load1997 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a3, 512 ; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -10412,9 +10412,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a1, 10 -; CHECK-RV32-NEXT: bltz a2, .LBB61_1014 +; CHECK-RV32-NEXT: bltz a2, .LBB61_1029 ; CHECK-RV32-NEXT: j .LBB61_533 -; CHECK-RV32-NEXT: .LBB61_1014: # %cond.load2001 +; CHECK-RV32-NEXT: .LBB61_1029: # %cond.load2001 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a3, 512 ; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -10425,9 +10425,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a1, 9 -; CHECK-RV32-NEXT: bltz a2, .LBB61_1015 +; CHECK-RV32-NEXT: bltz a2, .LBB61_1030 ; CHECK-RV32-NEXT: j .LBB61_534 -; CHECK-RV32-NEXT: .LBB61_1015: # %cond.load2005 +; CHECK-RV32-NEXT: .LBB61_1030: # %cond.load2005 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a3, 512 ; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -10438,9 +10438,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a1, 8 -; CHECK-RV32-NEXT: bltz a2, .LBB61_1016 +; CHECK-RV32-NEXT: bltz a2, .LBB61_1031 ; CHECK-RV32-NEXT: j .LBB61_535 -; CHECK-RV32-NEXT: .LBB61_1016: # %cond.load2009 +; CHECK-RV32-NEXT: .LBB61_1031: # %cond.load2009 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a3, 512 ; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -10451,9 +10451,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a1, 7 -; CHECK-RV32-NEXT: bltz a2, .LBB61_1017 +; CHECK-RV32-NEXT: bltz a2, .LBB61_1032 ; CHECK-RV32-NEXT: j .LBB61_536 -; CHECK-RV32-NEXT: .LBB61_1017: # %cond.load2013 +; CHECK-RV32-NEXT: .LBB61_1032: # %cond.load2013 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a3, 512 ; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -10464,9 +10464,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a1, 6 -; CHECK-RV32-NEXT: bltz a2, .LBB61_1018 +; CHECK-RV32-NEXT: bltz a2, .LBB61_1033 ; CHECK-RV32-NEXT: j .LBB61_537 -; CHECK-RV32-NEXT: .LBB61_1018: # %cond.load2017 +; CHECK-RV32-NEXT: .LBB61_1033: # %cond.load2017 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a3, 512 ; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -10477,9 +10477,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a1, 5 -; CHECK-RV32-NEXT: bltz a2, .LBB61_1019 +; CHECK-RV32-NEXT: bltz a2, .LBB61_1034 ; CHECK-RV32-NEXT: j .LBB61_538 -; CHECK-RV32-NEXT: .LBB61_1019: # %cond.load2021 +; CHECK-RV32-NEXT: .LBB61_1034: # %cond.load2021 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a3, 512 ; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -10490,9 +10490,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a1, 4 -; CHECK-RV32-NEXT: bltz a2, .LBB61_1020 +; CHECK-RV32-NEXT: bltz a2, .LBB61_1035 ; CHECK-RV32-NEXT: j .LBB61_539 -; CHECK-RV32-NEXT: .LBB61_1020: # %cond.load2025 +; CHECK-RV32-NEXT: .LBB61_1035: # %cond.load2025 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a3, 512 ; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -10503,9 +10503,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a1, 3 -; CHECK-RV32-NEXT: bltz a2, .LBB61_1021 +; CHECK-RV32-NEXT: bltz a2, .LBB61_1036 ; CHECK-RV32-NEXT: j .LBB61_540 -; CHECK-RV32-NEXT: .LBB61_1021: # %cond.load2029 +; CHECK-RV32-NEXT: .LBB61_1036: # %cond.load2029 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a3, 512 ; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -10516,9 +10516,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a1, 2 -; CHECK-RV32-NEXT: bltz a2, .LBB61_1022 +; CHECK-RV32-NEXT: bltz a2, .LBB61_1037 ; CHECK-RV32-NEXT: j .LBB61_541 -; CHECK-RV32-NEXT: .LBB61_1022: # %cond.load2033 +; CHECK-RV32-NEXT: .LBB61_1037: # %cond.load2033 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a3, 512 ; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -10529,9 +10529,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV32-NEXT: addi a0, a0, 1 ; CHECK-RV32-NEXT: slli a2, a1, 1 -; CHECK-RV32-NEXT: bltz a2, .LBB61_1023 +; CHECK-RV32-NEXT: bltz a2, .LBB61_1038 ; CHECK-RV32-NEXT: j .LBB61_542 -; CHECK-RV32-NEXT: .LBB61_1023: # %cond.load2037 +; CHECK-RV32-NEXT: .LBB61_1038: # %cond.load2037 ; CHECK-RV32-NEXT: lbu a2, 0(a0) ; CHECK-RV32-NEXT: li a3, 512 ; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -10541,9 +10541,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, tu, ma ; CHECK-RV32-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV32-NEXT: addi a0, a0, 1 -; CHECK-RV32-NEXT: bltz a1, .LBB61_1024 +; CHECK-RV32-NEXT: bltz a1, .LBB61_1039 ; CHECK-RV32-NEXT: j .LBB61_543 -; CHECK-RV32-NEXT: .LBB61_1024: # %cond.load2041 +; CHECK-RV32-NEXT: .LBB61_1039: # %cond.load2041 ; CHECK-RV32-NEXT: lbu a0, 0(a0) ; CHECK-RV32-NEXT: li a1, 512 ; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m8, ta, ma @@ -10834,251 +10834,251 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-RV64-NEXT: vmv.x.s a1, v24 ; CHECK-RV64-NEXT: bgez a2, .LBB61_66 -; CHECK-RV64-NEXT: j .LBB61_588 +; CHECK-RV64-NEXT: j .LBB61_589 ; CHECK-RV64-NEXT: .LBB61_66: # %else250 ; CHECK-RV64-NEXT: andi a2, a1, 1 ; CHECK-RV64-NEXT: beqz a2, .LBB61_67 -; CHECK-RV64-NEXT: j .LBB61_589 +; CHECK-RV64-NEXT: j .LBB61_590 ; CHECK-RV64-NEXT: .LBB61_67: # %else254 ; CHECK-RV64-NEXT: andi a2, a1, 2 ; CHECK-RV64-NEXT: beqz a2, .LBB61_68 -; CHECK-RV64-NEXT: j .LBB61_590 +; CHECK-RV64-NEXT: j .LBB61_591 ; CHECK-RV64-NEXT: .LBB61_68: # %else258 ; CHECK-RV64-NEXT: andi a2, a1, 4 ; CHECK-RV64-NEXT: beqz a2, .LBB61_69 -; CHECK-RV64-NEXT: j .LBB61_591 +; CHECK-RV64-NEXT: j .LBB61_592 ; CHECK-RV64-NEXT: .LBB61_69: # %else262 ; CHECK-RV64-NEXT: andi a2, a1, 8 ; CHECK-RV64-NEXT: beqz a2, .LBB61_70 -; CHECK-RV64-NEXT: j .LBB61_592 +; CHECK-RV64-NEXT: j .LBB61_593 ; CHECK-RV64-NEXT: .LBB61_70: # %else266 ; CHECK-RV64-NEXT: andi a2, a1, 16 ; CHECK-RV64-NEXT: beqz a2, .LBB61_71 -; CHECK-RV64-NEXT: j .LBB61_593 +; CHECK-RV64-NEXT: j .LBB61_594 ; CHECK-RV64-NEXT: .LBB61_71: # %else270 ; CHECK-RV64-NEXT: andi a2, a1, 32 ; CHECK-RV64-NEXT: beqz a2, .LBB61_72 -; CHECK-RV64-NEXT: j .LBB61_594 +; CHECK-RV64-NEXT: j .LBB61_595 ; CHECK-RV64-NEXT: .LBB61_72: # %else274 ; CHECK-RV64-NEXT: andi a2, a1, 64 ; CHECK-RV64-NEXT: beqz a2, .LBB61_73 -; CHECK-RV64-NEXT: j .LBB61_595 +; CHECK-RV64-NEXT: j .LBB61_596 ; CHECK-RV64-NEXT: .LBB61_73: # %else278 ; CHECK-RV64-NEXT: andi a2, a1, 128 ; CHECK-RV64-NEXT: beqz a2, .LBB61_74 -; CHECK-RV64-NEXT: j .LBB61_596 +; CHECK-RV64-NEXT: j .LBB61_597 ; CHECK-RV64-NEXT: .LBB61_74: # %else282 ; CHECK-RV64-NEXT: andi a2, a1, 256 ; CHECK-RV64-NEXT: beqz a2, .LBB61_75 -; CHECK-RV64-NEXT: j .LBB61_597 +; CHECK-RV64-NEXT: j .LBB61_598 ; CHECK-RV64-NEXT: .LBB61_75: # %else286 ; CHECK-RV64-NEXT: andi a2, a1, 512 ; CHECK-RV64-NEXT: beqz a2, .LBB61_76 -; CHECK-RV64-NEXT: j .LBB61_598 +; CHECK-RV64-NEXT: j .LBB61_599 ; CHECK-RV64-NEXT: .LBB61_76: # %else290 ; CHECK-RV64-NEXT: andi a2, a1, 1024 ; CHECK-RV64-NEXT: beqz a2, .LBB61_77 -; CHECK-RV64-NEXT: j .LBB61_599 +; CHECK-RV64-NEXT: j .LBB61_600 ; CHECK-RV64-NEXT: .LBB61_77: # %else294 ; CHECK-RV64-NEXT: slli a2, a1, 52 ; CHECK-RV64-NEXT: bgez a2, .LBB61_78 -; CHECK-RV64-NEXT: j .LBB61_600 +; CHECK-RV64-NEXT: j .LBB61_601 ; CHECK-RV64-NEXT: .LBB61_78: # %else298 ; CHECK-RV64-NEXT: slli a2, a1, 51 ; CHECK-RV64-NEXT: bgez a2, .LBB61_79 -; CHECK-RV64-NEXT: j .LBB61_601 +; CHECK-RV64-NEXT: j .LBB61_602 ; CHECK-RV64-NEXT: .LBB61_79: # %else302 ; CHECK-RV64-NEXT: slli a2, a1, 50 ; CHECK-RV64-NEXT: bgez a2, .LBB61_80 -; CHECK-RV64-NEXT: j .LBB61_602 +; CHECK-RV64-NEXT: j .LBB61_603 ; CHECK-RV64-NEXT: .LBB61_80: # %else306 ; CHECK-RV64-NEXT: slli a2, a1, 49 ; CHECK-RV64-NEXT: bgez a2, .LBB61_81 -; CHECK-RV64-NEXT: j .LBB61_603 +; CHECK-RV64-NEXT: j .LBB61_604 ; CHECK-RV64-NEXT: .LBB61_81: # %else310 ; CHECK-RV64-NEXT: slli a2, a1, 48 ; CHECK-RV64-NEXT: bgez a2, .LBB61_82 -; CHECK-RV64-NEXT: j .LBB61_604 +; CHECK-RV64-NEXT: j .LBB61_605 ; CHECK-RV64-NEXT: .LBB61_82: # %else314 ; CHECK-RV64-NEXT: slli a2, a1, 47 ; CHECK-RV64-NEXT: bgez a2, .LBB61_83 -; CHECK-RV64-NEXT: j .LBB61_605 +; CHECK-RV64-NEXT: j .LBB61_606 ; CHECK-RV64-NEXT: .LBB61_83: # %else318 ; CHECK-RV64-NEXT: slli a2, a1, 46 ; CHECK-RV64-NEXT: bgez a2, .LBB61_84 -; CHECK-RV64-NEXT: j .LBB61_606 +; CHECK-RV64-NEXT: j .LBB61_607 ; CHECK-RV64-NEXT: .LBB61_84: # %else322 ; CHECK-RV64-NEXT: slli a2, a1, 45 ; CHECK-RV64-NEXT: bgez a2, .LBB61_85 -; CHECK-RV64-NEXT: j .LBB61_607 +; CHECK-RV64-NEXT: j .LBB61_608 ; CHECK-RV64-NEXT: .LBB61_85: # %else326 ; CHECK-RV64-NEXT: slli a2, a1, 44 ; CHECK-RV64-NEXT: bgez a2, .LBB61_86 -; CHECK-RV64-NEXT: j .LBB61_608 +; CHECK-RV64-NEXT: j .LBB61_609 ; CHECK-RV64-NEXT: .LBB61_86: # %else330 ; CHECK-RV64-NEXT: slli a2, a1, 43 ; CHECK-RV64-NEXT: bgez a2, .LBB61_87 -; CHECK-RV64-NEXT: j .LBB61_609 +; CHECK-RV64-NEXT: j .LBB61_610 ; CHECK-RV64-NEXT: .LBB61_87: # %else334 ; CHECK-RV64-NEXT: slli a2, a1, 42 ; CHECK-RV64-NEXT: bgez a2, .LBB61_88 -; CHECK-RV64-NEXT: j .LBB61_610 +; CHECK-RV64-NEXT: j .LBB61_611 ; CHECK-RV64-NEXT: .LBB61_88: # %else338 ; CHECK-RV64-NEXT: slli a2, a1, 41 ; CHECK-RV64-NEXT: bgez a2, .LBB61_89 -; CHECK-RV64-NEXT: j .LBB61_611 +; CHECK-RV64-NEXT: j .LBB61_612 ; CHECK-RV64-NEXT: .LBB61_89: # %else342 ; CHECK-RV64-NEXT: slli a2, a1, 40 ; CHECK-RV64-NEXT: bgez a2, .LBB61_90 -; CHECK-RV64-NEXT: j .LBB61_612 +; CHECK-RV64-NEXT: j .LBB61_613 ; CHECK-RV64-NEXT: .LBB61_90: # %else346 ; CHECK-RV64-NEXT: slli a2, a1, 39 ; CHECK-RV64-NEXT: bgez a2, .LBB61_91 -; CHECK-RV64-NEXT: j .LBB61_613 +; CHECK-RV64-NEXT: j .LBB61_614 ; CHECK-RV64-NEXT: .LBB61_91: # %else350 ; CHECK-RV64-NEXT: slli a2, a1, 38 ; CHECK-RV64-NEXT: bgez a2, .LBB61_92 -; CHECK-RV64-NEXT: j .LBB61_614 +; CHECK-RV64-NEXT: j .LBB61_615 ; CHECK-RV64-NEXT: .LBB61_92: # %else354 ; CHECK-RV64-NEXT: slli a2, a1, 37 ; CHECK-RV64-NEXT: bgez a2, .LBB61_93 -; CHECK-RV64-NEXT: j .LBB61_615 +; CHECK-RV64-NEXT: j .LBB61_616 ; CHECK-RV64-NEXT: .LBB61_93: # %else358 ; CHECK-RV64-NEXT: slli a2, a1, 36 ; CHECK-RV64-NEXT: bgez a2, .LBB61_94 -; CHECK-RV64-NEXT: j .LBB61_616 +; CHECK-RV64-NEXT: j .LBB61_617 ; CHECK-RV64-NEXT: .LBB61_94: # %else362 ; CHECK-RV64-NEXT: slli a2, a1, 35 ; CHECK-RV64-NEXT: bgez a2, .LBB61_95 -; CHECK-RV64-NEXT: j .LBB61_617 +; CHECK-RV64-NEXT: j .LBB61_618 ; CHECK-RV64-NEXT: .LBB61_95: # %else366 ; CHECK-RV64-NEXT: slli a2, a1, 34 ; CHECK-RV64-NEXT: bgez a2, .LBB61_96 -; CHECK-RV64-NEXT: j .LBB61_618 +; CHECK-RV64-NEXT: j .LBB61_619 ; CHECK-RV64-NEXT: .LBB61_96: # %else370 ; CHECK-RV64-NEXT: slli a2, a1, 33 ; CHECK-RV64-NEXT: bgez a2, .LBB61_97 -; CHECK-RV64-NEXT: j .LBB61_619 +; CHECK-RV64-NEXT: j .LBB61_620 ; CHECK-RV64-NEXT: .LBB61_97: # %else374 ; CHECK-RV64-NEXT: slli a2, a1, 32 ; CHECK-RV64-NEXT: bgez a2, .LBB61_98 -; CHECK-RV64-NEXT: j .LBB61_620 +; CHECK-RV64-NEXT: j .LBB61_621 ; CHECK-RV64-NEXT: .LBB61_98: # %else378 ; CHECK-RV64-NEXT: slli a2, a1, 31 ; CHECK-RV64-NEXT: bgez a2, .LBB61_99 -; CHECK-RV64-NEXT: j .LBB61_621 +; CHECK-RV64-NEXT: j .LBB61_622 ; CHECK-RV64-NEXT: .LBB61_99: # %else382 ; CHECK-RV64-NEXT: slli a2, a1, 30 ; CHECK-RV64-NEXT: bgez a2, .LBB61_100 -; CHECK-RV64-NEXT: j .LBB61_622 +; CHECK-RV64-NEXT: j .LBB61_623 ; CHECK-RV64-NEXT: .LBB61_100: # %else386 ; CHECK-RV64-NEXT: slli a2, a1, 29 ; CHECK-RV64-NEXT: bgez a2, .LBB61_101 -; CHECK-RV64-NEXT: j .LBB61_623 +; CHECK-RV64-NEXT: j .LBB61_624 ; CHECK-RV64-NEXT: .LBB61_101: # %else390 ; CHECK-RV64-NEXT: slli a2, a1, 28 ; CHECK-RV64-NEXT: bgez a2, .LBB61_102 -; CHECK-RV64-NEXT: j .LBB61_624 +; CHECK-RV64-NEXT: j .LBB61_625 ; CHECK-RV64-NEXT: .LBB61_102: # %else394 ; CHECK-RV64-NEXT: slli a2, a1, 27 ; CHECK-RV64-NEXT: bgez a2, .LBB61_103 -; CHECK-RV64-NEXT: j .LBB61_625 +; CHECK-RV64-NEXT: j .LBB61_626 ; CHECK-RV64-NEXT: .LBB61_103: # %else398 ; CHECK-RV64-NEXT: slli a2, a1, 26 ; CHECK-RV64-NEXT: bgez a2, .LBB61_104 -; CHECK-RV64-NEXT: j .LBB61_626 +; CHECK-RV64-NEXT: j .LBB61_627 ; CHECK-RV64-NEXT: .LBB61_104: # %else402 ; CHECK-RV64-NEXT: slli a2, a1, 25 ; CHECK-RV64-NEXT: bgez a2, .LBB61_105 -; CHECK-RV64-NEXT: j .LBB61_627 +; CHECK-RV64-NEXT: j .LBB61_628 ; CHECK-RV64-NEXT: .LBB61_105: # %else406 ; CHECK-RV64-NEXT: slli a2, a1, 24 ; CHECK-RV64-NEXT: bgez a2, .LBB61_106 -; CHECK-RV64-NEXT: j .LBB61_628 +; CHECK-RV64-NEXT: j .LBB61_629 ; CHECK-RV64-NEXT: .LBB61_106: # %else410 ; CHECK-RV64-NEXT: slli a2, a1, 23 ; CHECK-RV64-NEXT: bgez a2, .LBB61_107 -; CHECK-RV64-NEXT: j .LBB61_629 +; CHECK-RV64-NEXT: j .LBB61_630 ; CHECK-RV64-NEXT: .LBB61_107: # %else414 ; CHECK-RV64-NEXT: slli a2, a1, 22 ; CHECK-RV64-NEXT: bgez a2, .LBB61_108 -; CHECK-RV64-NEXT: j .LBB61_630 +; CHECK-RV64-NEXT: j .LBB61_631 ; CHECK-RV64-NEXT: .LBB61_108: # %else418 ; CHECK-RV64-NEXT: slli a2, a1, 21 ; CHECK-RV64-NEXT: bgez a2, .LBB61_109 -; CHECK-RV64-NEXT: j .LBB61_631 +; CHECK-RV64-NEXT: j .LBB61_632 ; CHECK-RV64-NEXT: .LBB61_109: # %else422 ; CHECK-RV64-NEXT: slli a2, a1, 20 ; CHECK-RV64-NEXT: bgez a2, .LBB61_110 -; CHECK-RV64-NEXT: j .LBB61_632 +; CHECK-RV64-NEXT: j .LBB61_633 ; CHECK-RV64-NEXT: .LBB61_110: # %else426 ; CHECK-RV64-NEXT: slli a2, a1, 19 ; CHECK-RV64-NEXT: bgez a2, .LBB61_111 -; CHECK-RV64-NEXT: j .LBB61_633 +; CHECK-RV64-NEXT: j .LBB61_634 ; CHECK-RV64-NEXT: .LBB61_111: # %else430 ; CHECK-RV64-NEXT: slli a2, a1, 18 ; CHECK-RV64-NEXT: bgez a2, .LBB61_112 -; CHECK-RV64-NEXT: j .LBB61_634 +; CHECK-RV64-NEXT: j .LBB61_635 ; CHECK-RV64-NEXT: .LBB61_112: # %else434 ; CHECK-RV64-NEXT: slli a2, a1, 17 ; CHECK-RV64-NEXT: bgez a2, .LBB61_113 -; CHECK-RV64-NEXT: j .LBB61_635 +; CHECK-RV64-NEXT: j .LBB61_636 ; CHECK-RV64-NEXT: .LBB61_113: # %else438 ; CHECK-RV64-NEXT: slli a2, a1, 16 ; CHECK-RV64-NEXT: bgez a2, .LBB61_114 -; CHECK-RV64-NEXT: j .LBB61_636 +; CHECK-RV64-NEXT: j .LBB61_637 ; CHECK-RV64-NEXT: .LBB61_114: # %else442 ; CHECK-RV64-NEXT: slli a2, a1, 15 ; CHECK-RV64-NEXT: bgez a2, .LBB61_115 -; CHECK-RV64-NEXT: j .LBB61_637 +; CHECK-RV64-NEXT: j .LBB61_638 ; CHECK-RV64-NEXT: .LBB61_115: # %else446 ; CHECK-RV64-NEXT: slli a2, a1, 14 ; CHECK-RV64-NEXT: bgez a2, .LBB61_116 -; CHECK-RV64-NEXT: j .LBB61_638 +; CHECK-RV64-NEXT: j .LBB61_639 ; CHECK-RV64-NEXT: .LBB61_116: # %else450 ; CHECK-RV64-NEXT: slli a2, a1, 13 ; CHECK-RV64-NEXT: bgez a2, .LBB61_117 -; CHECK-RV64-NEXT: j .LBB61_639 +; CHECK-RV64-NEXT: j .LBB61_640 ; CHECK-RV64-NEXT: .LBB61_117: # %else454 ; CHECK-RV64-NEXT: slli a2, a1, 12 ; CHECK-RV64-NEXT: bgez a2, .LBB61_118 -; CHECK-RV64-NEXT: j .LBB61_640 +; CHECK-RV64-NEXT: j .LBB61_641 ; CHECK-RV64-NEXT: .LBB61_118: # %else458 ; CHECK-RV64-NEXT: slli a2, a1, 11 ; CHECK-RV64-NEXT: bgez a2, .LBB61_119 -; CHECK-RV64-NEXT: j .LBB61_641 +; CHECK-RV64-NEXT: j .LBB61_642 ; CHECK-RV64-NEXT: .LBB61_119: # %else462 ; CHECK-RV64-NEXT: slli a2, a1, 10 ; CHECK-RV64-NEXT: bgez a2, .LBB61_120 -; CHECK-RV64-NEXT: j .LBB61_642 +; CHECK-RV64-NEXT: j .LBB61_643 ; CHECK-RV64-NEXT: .LBB61_120: # %else466 ; CHECK-RV64-NEXT: slli a2, a1, 9 ; CHECK-RV64-NEXT: bgez a2, .LBB61_121 -; CHECK-RV64-NEXT: j .LBB61_643 +; CHECK-RV64-NEXT: j .LBB61_644 ; CHECK-RV64-NEXT: .LBB61_121: # %else470 ; CHECK-RV64-NEXT: slli a2, a1, 8 ; CHECK-RV64-NEXT: bgez a2, .LBB61_122 -; CHECK-RV64-NEXT: j .LBB61_644 +; CHECK-RV64-NEXT: j .LBB61_645 ; CHECK-RV64-NEXT: .LBB61_122: # %else474 ; CHECK-RV64-NEXT: slli a2, a1, 7 ; CHECK-RV64-NEXT: bgez a2, .LBB61_123 -; CHECK-RV64-NEXT: j .LBB61_645 +; CHECK-RV64-NEXT: j .LBB61_646 ; CHECK-RV64-NEXT: .LBB61_123: # %else478 ; CHECK-RV64-NEXT: slli a2, a1, 6 ; CHECK-RV64-NEXT: bgez a2, .LBB61_124 -; CHECK-RV64-NEXT: j .LBB61_646 +; CHECK-RV64-NEXT: j .LBB61_647 ; CHECK-RV64-NEXT: .LBB61_124: # %else482 ; CHECK-RV64-NEXT: slli a2, a1, 5 ; CHECK-RV64-NEXT: bgez a2, .LBB61_125 -; CHECK-RV64-NEXT: j .LBB61_647 +; CHECK-RV64-NEXT: j .LBB61_648 ; CHECK-RV64-NEXT: .LBB61_125: # %else486 ; CHECK-RV64-NEXT: slli a2, a1, 4 ; CHECK-RV64-NEXT: bgez a2, .LBB61_126 -; CHECK-RV64-NEXT: j .LBB61_648 +; CHECK-RV64-NEXT: j .LBB61_649 ; CHECK-RV64-NEXT: .LBB61_126: # %else490 ; CHECK-RV64-NEXT: slli a2, a1, 3 ; CHECK-RV64-NEXT: bgez a2, .LBB61_127 -; CHECK-RV64-NEXT: j .LBB61_649 +; CHECK-RV64-NEXT: j .LBB61_650 ; CHECK-RV64-NEXT: .LBB61_127: # %else494 ; CHECK-RV64-NEXT: slli a2, a1, 2 ; CHECK-RV64-NEXT: bgez a2, .LBB61_129 @@ -11114,251 +11114,251 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-RV64-NEXT: vmv.x.s a2, v24 ; CHECK-RV64-NEXT: bgez a1, .LBB61_132 -; CHECK-RV64-NEXT: j .LBB61_650 +; CHECK-RV64-NEXT: j .LBB61_652 ; CHECK-RV64-NEXT: .LBB61_132: # %else506 ; CHECK-RV64-NEXT: andi a1, a2, 1 ; CHECK-RV64-NEXT: beqz a1, .LBB61_133 -; CHECK-RV64-NEXT: j .LBB61_651 +; CHECK-RV64-NEXT: j .LBB61_653 ; CHECK-RV64-NEXT: .LBB61_133: # %else510 ; CHECK-RV64-NEXT: andi a1, a2, 2 ; CHECK-RV64-NEXT: beqz a1, .LBB61_134 -; CHECK-RV64-NEXT: j .LBB61_652 +; CHECK-RV64-NEXT: j .LBB61_654 ; CHECK-RV64-NEXT: .LBB61_134: # %else514 ; CHECK-RV64-NEXT: andi a1, a2, 4 ; CHECK-RV64-NEXT: beqz a1, .LBB61_135 -; CHECK-RV64-NEXT: j .LBB61_653 +; CHECK-RV64-NEXT: j .LBB61_655 ; CHECK-RV64-NEXT: .LBB61_135: # %else518 ; CHECK-RV64-NEXT: andi a1, a2, 8 ; CHECK-RV64-NEXT: beqz a1, .LBB61_136 -; CHECK-RV64-NEXT: j .LBB61_654 +; CHECK-RV64-NEXT: j .LBB61_656 ; CHECK-RV64-NEXT: .LBB61_136: # %else522 ; CHECK-RV64-NEXT: andi a1, a2, 16 ; CHECK-RV64-NEXT: beqz a1, .LBB61_137 -; CHECK-RV64-NEXT: j .LBB61_655 +; CHECK-RV64-NEXT: j .LBB61_657 ; CHECK-RV64-NEXT: .LBB61_137: # %else526 ; CHECK-RV64-NEXT: andi a1, a2, 32 ; CHECK-RV64-NEXT: beqz a1, .LBB61_138 -; CHECK-RV64-NEXT: j .LBB61_656 +; CHECK-RV64-NEXT: j .LBB61_658 ; CHECK-RV64-NEXT: .LBB61_138: # %else530 ; CHECK-RV64-NEXT: andi a1, a2, 64 ; CHECK-RV64-NEXT: beqz a1, .LBB61_139 -; CHECK-RV64-NEXT: j .LBB61_657 +; CHECK-RV64-NEXT: j .LBB61_659 ; CHECK-RV64-NEXT: .LBB61_139: # %else534 ; CHECK-RV64-NEXT: andi a1, a2, 128 ; CHECK-RV64-NEXT: beqz a1, .LBB61_140 -; CHECK-RV64-NEXT: j .LBB61_658 +; CHECK-RV64-NEXT: j .LBB61_660 ; CHECK-RV64-NEXT: .LBB61_140: # %else538 ; CHECK-RV64-NEXT: andi a1, a2, 256 ; CHECK-RV64-NEXT: beqz a1, .LBB61_141 -; CHECK-RV64-NEXT: j .LBB61_659 +; CHECK-RV64-NEXT: j .LBB61_661 ; CHECK-RV64-NEXT: .LBB61_141: # %else542 ; CHECK-RV64-NEXT: andi a1, a2, 512 ; CHECK-RV64-NEXT: beqz a1, .LBB61_142 -; CHECK-RV64-NEXT: j .LBB61_660 +; CHECK-RV64-NEXT: j .LBB61_662 ; CHECK-RV64-NEXT: .LBB61_142: # %else546 ; CHECK-RV64-NEXT: andi a1, a2, 1024 ; CHECK-RV64-NEXT: beqz a1, .LBB61_143 -; CHECK-RV64-NEXT: j .LBB61_661 +; CHECK-RV64-NEXT: j .LBB61_663 ; CHECK-RV64-NEXT: .LBB61_143: # %else550 ; CHECK-RV64-NEXT: slli a1, a2, 52 ; CHECK-RV64-NEXT: bgez a1, .LBB61_144 -; CHECK-RV64-NEXT: j .LBB61_662 +; CHECK-RV64-NEXT: j .LBB61_664 ; CHECK-RV64-NEXT: .LBB61_144: # %else554 ; CHECK-RV64-NEXT: slli a1, a2, 51 ; CHECK-RV64-NEXT: bgez a1, .LBB61_145 -; CHECK-RV64-NEXT: j .LBB61_663 +; CHECK-RV64-NEXT: j .LBB61_665 ; CHECK-RV64-NEXT: .LBB61_145: # %else558 ; CHECK-RV64-NEXT: slli a1, a2, 50 ; CHECK-RV64-NEXT: bgez a1, .LBB61_146 -; CHECK-RV64-NEXT: j .LBB61_664 +; CHECK-RV64-NEXT: j .LBB61_666 ; CHECK-RV64-NEXT: .LBB61_146: # %else562 ; CHECK-RV64-NEXT: slli a1, a2, 49 ; CHECK-RV64-NEXT: bgez a1, .LBB61_147 -; CHECK-RV64-NEXT: j .LBB61_665 +; CHECK-RV64-NEXT: j .LBB61_667 ; CHECK-RV64-NEXT: .LBB61_147: # %else566 ; CHECK-RV64-NEXT: slli a1, a2, 48 ; CHECK-RV64-NEXT: bgez a1, .LBB61_148 -; CHECK-RV64-NEXT: j .LBB61_666 +; CHECK-RV64-NEXT: j .LBB61_668 ; CHECK-RV64-NEXT: .LBB61_148: # %else570 ; CHECK-RV64-NEXT: slli a1, a2, 47 ; CHECK-RV64-NEXT: bgez a1, .LBB61_149 -; CHECK-RV64-NEXT: j .LBB61_667 +; CHECK-RV64-NEXT: j .LBB61_669 ; CHECK-RV64-NEXT: .LBB61_149: # %else574 ; CHECK-RV64-NEXT: slli a1, a2, 46 ; CHECK-RV64-NEXT: bgez a1, .LBB61_150 -; CHECK-RV64-NEXT: j .LBB61_668 +; CHECK-RV64-NEXT: j .LBB61_670 ; CHECK-RV64-NEXT: .LBB61_150: # %else578 ; CHECK-RV64-NEXT: slli a1, a2, 45 ; CHECK-RV64-NEXT: bgez a1, .LBB61_151 -; CHECK-RV64-NEXT: j .LBB61_669 +; CHECK-RV64-NEXT: j .LBB61_671 ; CHECK-RV64-NEXT: .LBB61_151: # %else582 ; CHECK-RV64-NEXT: slli a1, a2, 44 ; CHECK-RV64-NEXT: bgez a1, .LBB61_152 -; CHECK-RV64-NEXT: j .LBB61_670 +; CHECK-RV64-NEXT: j .LBB61_672 ; CHECK-RV64-NEXT: .LBB61_152: # %else586 ; CHECK-RV64-NEXT: slli a1, a2, 43 ; CHECK-RV64-NEXT: bgez a1, .LBB61_153 -; CHECK-RV64-NEXT: j .LBB61_671 +; CHECK-RV64-NEXT: j .LBB61_673 ; CHECK-RV64-NEXT: .LBB61_153: # %else590 ; CHECK-RV64-NEXT: slli a1, a2, 42 ; CHECK-RV64-NEXT: bgez a1, .LBB61_154 -; CHECK-RV64-NEXT: j .LBB61_672 +; CHECK-RV64-NEXT: j .LBB61_674 ; CHECK-RV64-NEXT: .LBB61_154: # %else594 ; CHECK-RV64-NEXT: slli a1, a2, 41 ; CHECK-RV64-NEXT: bgez a1, .LBB61_155 -; CHECK-RV64-NEXT: j .LBB61_673 +; CHECK-RV64-NEXT: j .LBB61_675 ; CHECK-RV64-NEXT: .LBB61_155: # %else598 ; CHECK-RV64-NEXT: slli a1, a2, 40 ; CHECK-RV64-NEXT: bgez a1, .LBB61_156 -; CHECK-RV64-NEXT: j .LBB61_674 +; CHECK-RV64-NEXT: j .LBB61_676 ; CHECK-RV64-NEXT: .LBB61_156: # %else602 ; CHECK-RV64-NEXT: slli a1, a2, 39 ; CHECK-RV64-NEXT: bgez a1, .LBB61_157 -; CHECK-RV64-NEXT: j .LBB61_675 +; CHECK-RV64-NEXT: j .LBB61_677 ; CHECK-RV64-NEXT: .LBB61_157: # %else606 ; CHECK-RV64-NEXT: slli a1, a2, 38 ; CHECK-RV64-NEXT: bgez a1, .LBB61_158 -; CHECK-RV64-NEXT: j .LBB61_676 +; CHECK-RV64-NEXT: j .LBB61_678 ; CHECK-RV64-NEXT: .LBB61_158: # %else610 ; CHECK-RV64-NEXT: slli a1, a2, 37 ; CHECK-RV64-NEXT: bgez a1, .LBB61_159 -; CHECK-RV64-NEXT: j .LBB61_677 +; CHECK-RV64-NEXT: j .LBB61_679 ; CHECK-RV64-NEXT: .LBB61_159: # %else614 ; CHECK-RV64-NEXT: slli a1, a2, 36 ; CHECK-RV64-NEXT: bgez a1, .LBB61_160 -; CHECK-RV64-NEXT: j .LBB61_678 +; CHECK-RV64-NEXT: j .LBB61_680 ; CHECK-RV64-NEXT: .LBB61_160: # %else618 ; CHECK-RV64-NEXT: slli a1, a2, 35 ; CHECK-RV64-NEXT: bgez a1, .LBB61_161 -; CHECK-RV64-NEXT: j .LBB61_679 +; CHECK-RV64-NEXT: j .LBB61_681 ; CHECK-RV64-NEXT: .LBB61_161: # %else622 ; CHECK-RV64-NEXT: slli a1, a2, 34 ; CHECK-RV64-NEXT: bgez a1, .LBB61_162 -; CHECK-RV64-NEXT: j .LBB61_680 +; CHECK-RV64-NEXT: j .LBB61_682 ; CHECK-RV64-NEXT: .LBB61_162: # %else626 ; CHECK-RV64-NEXT: slli a1, a2, 33 ; CHECK-RV64-NEXT: bgez a1, .LBB61_163 -; CHECK-RV64-NEXT: j .LBB61_681 +; CHECK-RV64-NEXT: j .LBB61_683 ; CHECK-RV64-NEXT: .LBB61_163: # %else630 ; CHECK-RV64-NEXT: slli a1, a2, 32 ; CHECK-RV64-NEXT: bgez a1, .LBB61_164 -; CHECK-RV64-NEXT: j .LBB61_682 +; CHECK-RV64-NEXT: j .LBB61_684 ; CHECK-RV64-NEXT: .LBB61_164: # %else634 ; CHECK-RV64-NEXT: slli a1, a2, 31 ; CHECK-RV64-NEXT: bgez a1, .LBB61_165 -; CHECK-RV64-NEXT: j .LBB61_683 +; CHECK-RV64-NEXT: j .LBB61_685 ; CHECK-RV64-NEXT: .LBB61_165: # %else638 ; CHECK-RV64-NEXT: slli a1, a2, 30 ; CHECK-RV64-NEXT: bgez a1, .LBB61_166 -; CHECK-RV64-NEXT: j .LBB61_684 +; CHECK-RV64-NEXT: j .LBB61_686 ; CHECK-RV64-NEXT: .LBB61_166: # %else642 ; CHECK-RV64-NEXT: slli a1, a2, 29 ; CHECK-RV64-NEXT: bgez a1, .LBB61_167 -; CHECK-RV64-NEXT: j .LBB61_685 +; CHECK-RV64-NEXT: j .LBB61_687 ; CHECK-RV64-NEXT: .LBB61_167: # %else646 ; CHECK-RV64-NEXT: slli a1, a2, 28 ; CHECK-RV64-NEXT: bgez a1, .LBB61_168 -; CHECK-RV64-NEXT: j .LBB61_686 +; CHECK-RV64-NEXT: j .LBB61_688 ; CHECK-RV64-NEXT: .LBB61_168: # %else650 ; CHECK-RV64-NEXT: slli a1, a2, 27 ; CHECK-RV64-NEXT: bgez a1, .LBB61_169 -; CHECK-RV64-NEXT: j .LBB61_687 +; CHECK-RV64-NEXT: j .LBB61_689 ; CHECK-RV64-NEXT: .LBB61_169: # %else654 ; CHECK-RV64-NEXT: slli a1, a2, 26 ; CHECK-RV64-NEXT: bgez a1, .LBB61_170 -; CHECK-RV64-NEXT: j .LBB61_688 +; CHECK-RV64-NEXT: j .LBB61_690 ; CHECK-RV64-NEXT: .LBB61_170: # %else658 ; CHECK-RV64-NEXT: slli a1, a2, 25 ; CHECK-RV64-NEXT: bgez a1, .LBB61_171 -; CHECK-RV64-NEXT: j .LBB61_689 +; CHECK-RV64-NEXT: j .LBB61_691 ; CHECK-RV64-NEXT: .LBB61_171: # %else662 ; CHECK-RV64-NEXT: slli a1, a2, 24 ; CHECK-RV64-NEXT: bgez a1, .LBB61_172 -; CHECK-RV64-NEXT: j .LBB61_690 +; CHECK-RV64-NEXT: j .LBB61_692 ; CHECK-RV64-NEXT: .LBB61_172: # %else666 ; CHECK-RV64-NEXT: slli a1, a2, 23 ; CHECK-RV64-NEXT: bgez a1, .LBB61_173 -; CHECK-RV64-NEXT: j .LBB61_691 +; CHECK-RV64-NEXT: j .LBB61_693 ; CHECK-RV64-NEXT: .LBB61_173: # %else670 ; CHECK-RV64-NEXT: slli a1, a2, 22 ; CHECK-RV64-NEXT: bgez a1, .LBB61_174 -; CHECK-RV64-NEXT: j .LBB61_692 +; CHECK-RV64-NEXT: j .LBB61_694 ; CHECK-RV64-NEXT: .LBB61_174: # %else674 ; CHECK-RV64-NEXT: slli a1, a2, 21 ; CHECK-RV64-NEXT: bgez a1, .LBB61_175 -; CHECK-RV64-NEXT: j .LBB61_693 +; CHECK-RV64-NEXT: j .LBB61_695 ; CHECK-RV64-NEXT: .LBB61_175: # %else678 ; CHECK-RV64-NEXT: slli a1, a2, 20 ; CHECK-RV64-NEXT: bgez a1, .LBB61_176 -; CHECK-RV64-NEXT: j .LBB61_694 +; CHECK-RV64-NEXT: j .LBB61_696 ; CHECK-RV64-NEXT: .LBB61_176: # %else682 ; CHECK-RV64-NEXT: slli a1, a2, 19 ; CHECK-RV64-NEXT: bgez a1, .LBB61_177 -; CHECK-RV64-NEXT: j .LBB61_695 +; CHECK-RV64-NEXT: j .LBB61_697 ; CHECK-RV64-NEXT: .LBB61_177: # %else686 ; CHECK-RV64-NEXT: slli a1, a2, 18 ; CHECK-RV64-NEXT: bgez a1, .LBB61_178 -; CHECK-RV64-NEXT: j .LBB61_696 +; CHECK-RV64-NEXT: j .LBB61_698 ; CHECK-RV64-NEXT: .LBB61_178: # %else690 ; CHECK-RV64-NEXT: slli a1, a2, 17 ; CHECK-RV64-NEXT: bgez a1, .LBB61_179 -; CHECK-RV64-NEXT: j .LBB61_697 +; CHECK-RV64-NEXT: j .LBB61_699 ; CHECK-RV64-NEXT: .LBB61_179: # %else694 ; CHECK-RV64-NEXT: slli a1, a2, 16 ; CHECK-RV64-NEXT: bgez a1, .LBB61_180 -; CHECK-RV64-NEXT: j .LBB61_698 +; CHECK-RV64-NEXT: j .LBB61_700 ; CHECK-RV64-NEXT: .LBB61_180: # %else698 ; CHECK-RV64-NEXT: slli a1, a2, 15 ; CHECK-RV64-NEXT: bgez a1, .LBB61_181 -; CHECK-RV64-NEXT: j .LBB61_699 +; CHECK-RV64-NEXT: j .LBB61_701 ; CHECK-RV64-NEXT: .LBB61_181: # %else702 ; CHECK-RV64-NEXT: slli a1, a2, 14 ; CHECK-RV64-NEXT: bgez a1, .LBB61_182 -; CHECK-RV64-NEXT: j .LBB61_700 +; CHECK-RV64-NEXT: j .LBB61_702 ; CHECK-RV64-NEXT: .LBB61_182: # %else706 ; CHECK-RV64-NEXT: slli a1, a2, 13 ; CHECK-RV64-NEXT: bgez a1, .LBB61_183 -; CHECK-RV64-NEXT: j .LBB61_701 +; CHECK-RV64-NEXT: j .LBB61_703 ; CHECK-RV64-NEXT: .LBB61_183: # %else710 ; CHECK-RV64-NEXT: slli a1, a2, 12 ; CHECK-RV64-NEXT: bgez a1, .LBB61_184 -; CHECK-RV64-NEXT: j .LBB61_702 +; CHECK-RV64-NEXT: j .LBB61_704 ; CHECK-RV64-NEXT: .LBB61_184: # %else714 ; CHECK-RV64-NEXT: slli a1, a2, 11 ; CHECK-RV64-NEXT: bgez a1, .LBB61_185 -; CHECK-RV64-NEXT: j .LBB61_703 +; CHECK-RV64-NEXT: j .LBB61_705 ; CHECK-RV64-NEXT: .LBB61_185: # %else718 ; CHECK-RV64-NEXT: slli a1, a2, 10 ; CHECK-RV64-NEXT: bgez a1, .LBB61_186 -; CHECK-RV64-NEXT: j .LBB61_704 +; CHECK-RV64-NEXT: j .LBB61_706 ; CHECK-RV64-NEXT: .LBB61_186: # %else722 ; CHECK-RV64-NEXT: slli a1, a2, 9 ; CHECK-RV64-NEXT: bgez a1, .LBB61_187 -; CHECK-RV64-NEXT: j .LBB61_705 +; CHECK-RV64-NEXT: j .LBB61_707 ; CHECK-RV64-NEXT: .LBB61_187: # %else726 ; CHECK-RV64-NEXT: slli a1, a2, 8 ; CHECK-RV64-NEXT: bgez a1, .LBB61_188 -; CHECK-RV64-NEXT: j .LBB61_706 +; CHECK-RV64-NEXT: j .LBB61_708 ; CHECK-RV64-NEXT: .LBB61_188: # %else730 ; CHECK-RV64-NEXT: slli a1, a2, 7 ; CHECK-RV64-NEXT: bgez a1, .LBB61_189 -; CHECK-RV64-NEXT: j .LBB61_707 +; CHECK-RV64-NEXT: j .LBB61_709 ; CHECK-RV64-NEXT: .LBB61_189: # %else734 ; CHECK-RV64-NEXT: slli a1, a2, 6 ; CHECK-RV64-NEXT: bgez a1, .LBB61_190 -; CHECK-RV64-NEXT: j .LBB61_708 +; CHECK-RV64-NEXT: j .LBB61_710 ; CHECK-RV64-NEXT: .LBB61_190: # %else738 ; CHECK-RV64-NEXT: slli a1, a2, 5 ; CHECK-RV64-NEXT: bgez a1, .LBB61_191 -; CHECK-RV64-NEXT: j .LBB61_709 +; CHECK-RV64-NEXT: j .LBB61_711 ; CHECK-RV64-NEXT: .LBB61_191: # %else742 ; CHECK-RV64-NEXT: slli a1, a2, 4 ; CHECK-RV64-NEXT: bgez a1, .LBB61_192 -; CHECK-RV64-NEXT: j .LBB61_710 +; CHECK-RV64-NEXT: j .LBB61_712 ; CHECK-RV64-NEXT: .LBB61_192: # %else746 ; CHECK-RV64-NEXT: slli a1, a2, 3 ; CHECK-RV64-NEXT: bgez a1, .LBB61_193 -; CHECK-RV64-NEXT: j .LBB61_711 +; CHECK-RV64-NEXT: j .LBB61_713 ; CHECK-RV64-NEXT: .LBB61_193: # %else750 ; CHECK-RV64-NEXT: slli a1, a2, 2 ; CHECK-RV64-NEXT: bgez a1, .LBB61_195 @@ -11394,251 +11394,251 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-RV64-NEXT: vmv.x.s a1, v24 ; CHECK-RV64-NEXT: bgez a2, .LBB61_198 -; CHECK-RV64-NEXT: j .LBB61_712 +; CHECK-RV64-NEXT: j .LBB61_715 ; CHECK-RV64-NEXT: .LBB61_198: # %else762 ; CHECK-RV64-NEXT: andi a2, a1, 1 ; CHECK-RV64-NEXT: beqz a2, .LBB61_199 -; CHECK-RV64-NEXT: j .LBB61_713 +; CHECK-RV64-NEXT: j .LBB61_716 ; CHECK-RV64-NEXT: .LBB61_199: # %else766 ; CHECK-RV64-NEXT: andi a2, a1, 2 ; CHECK-RV64-NEXT: beqz a2, .LBB61_200 -; CHECK-RV64-NEXT: j .LBB61_714 +; CHECK-RV64-NEXT: j .LBB61_717 ; CHECK-RV64-NEXT: .LBB61_200: # %else770 ; CHECK-RV64-NEXT: andi a2, a1, 4 ; CHECK-RV64-NEXT: beqz a2, .LBB61_201 -; CHECK-RV64-NEXT: j .LBB61_715 +; CHECK-RV64-NEXT: j .LBB61_718 ; CHECK-RV64-NEXT: .LBB61_201: # %else774 ; CHECK-RV64-NEXT: andi a2, a1, 8 ; CHECK-RV64-NEXT: beqz a2, .LBB61_202 -; CHECK-RV64-NEXT: j .LBB61_716 +; CHECK-RV64-NEXT: j .LBB61_719 ; CHECK-RV64-NEXT: .LBB61_202: # %else778 ; CHECK-RV64-NEXT: andi a2, a1, 16 ; CHECK-RV64-NEXT: beqz a2, .LBB61_203 -; CHECK-RV64-NEXT: j .LBB61_717 +; CHECK-RV64-NEXT: j .LBB61_720 ; CHECK-RV64-NEXT: .LBB61_203: # %else782 ; CHECK-RV64-NEXT: andi a2, a1, 32 ; CHECK-RV64-NEXT: beqz a2, .LBB61_204 -; CHECK-RV64-NEXT: j .LBB61_718 +; CHECK-RV64-NEXT: j .LBB61_721 ; CHECK-RV64-NEXT: .LBB61_204: # %else786 ; CHECK-RV64-NEXT: andi a2, a1, 64 ; CHECK-RV64-NEXT: beqz a2, .LBB61_205 -; CHECK-RV64-NEXT: j .LBB61_719 +; CHECK-RV64-NEXT: j .LBB61_722 ; CHECK-RV64-NEXT: .LBB61_205: # %else790 ; CHECK-RV64-NEXT: andi a2, a1, 128 ; CHECK-RV64-NEXT: beqz a2, .LBB61_206 -; CHECK-RV64-NEXT: j .LBB61_720 +; CHECK-RV64-NEXT: j .LBB61_723 ; CHECK-RV64-NEXT: .LBB61_206: # %else794 ; CHECK-RV64-NEXT: andi a2, a1, 256 ; CHECK-RV64-NEXT: beqz a2, .LBB61_207 -; CHECK-RV64-NEXT: j .LBB61_721 +; CHECK-RV64-NEXT: j .LBB61_724 ; CHECK-RV64-NEXT: .LBB61_207: # %else798 ; CHECK-RV64-NEXT: andi a2, a1, 512 ; CHECK-RV64-NEXT: beqz a2, .LBB61_208 -; CHECK-RV64-NEXT: j .LBB61_722 +; CHECK-RV64-NEXT: j .LBB61_725 ; CHECK-RV64-NEXT: .LBB61_208: # %else802 ; CHECK-RV64-NEXT: andi a2, a1, 1024 ; CHECK-RV64-NEXT: beqz a2, .LBB61_209 -; CHECK-RV64-NEXT: j .LBB61_723 +; CHECK-RV64-NEXT: j .LBB61_726 ; CHECK-RV64-NEXT: .LBB61_209: # %else806 ; CHECK-RV64-NEXT: slli a2, a1, 52 ; CHECK-RV64-NEXT: bgez a2, .LBB61_210 -; CHECK-RV64-NEXT: j .LBB61_724 +; CHECK-RV64-NEXT: j .LBB61_727 ; CHECK-RV64-NEXT: .LBB61_210: # %else810 ; CHECK-RV64-NEXT: slli a2, a1, 51 ; CHECK-RV64-NEXT: bgez a2, .LBB61_211 -; CHECK-RV64-NEXT: j .LBB61_725 +; CHECK-RV64-NEXT: j .LBB61_728 ; CHECK-RV64-NEXT: .LBB61_211: # %else814 ; CHECK-RV64-NEXT: slli a2, a1, 50 ; CHECK-RV64-NEXT: bgez a2, .LBB61_212 -; CHECK-RV64-NEXT: j .LBB61_726 +; CHECK-RV64-NEXT: j .LBB61_729 ; CHECK-RV64-NEXT: .LBB61_212: # %else818 ; CHECK-RV64-NEXT: slli a2, a1, 49 ; CHECK-RV64-NEXT: bgez a2, .LBB61_213 -; CHECK-RV64-NEXT: j .LBB61_727 +; CHECK-RV64-NEXT: j .LBB61_730 ; CHECK-RV64-NEXT: .LBB61_213: # %else822 ; CHECK-RV64-NEXT: slli a2, a1, 48 ; CHECK-RV64-NEXT: bgez a2, .LBB61_214 -; CHECK-RV64-NEXT: j .LBB61_728 +; CHECK-RV64-NEXT: j .LBB61_731 ; CHECK-RV64-NEXT: .LBB61_214: # %else826 ; CHECK-RV64-NEXT: slli a2, a1, 47 ; CHECK-RV64-NEXT: bgez a2, .LBB61_215 -; CHECK-RV64-NEXT: j .LBB61_729 +; CHECK-RV64-NEXT: j .LBB61_732 ; CHECK-RV64-NEXT: .LBB61_215: # %else830 ; CHECK-RV64-NEXT: slli a2, a1, 46 ; CHECK-RV64-NEXT: bgez a2, .LBB61_216 -; CHECK-RV64-NEXT: j .LBB61_730 +; CHECK-RV64-NEXT: j .LBB61_733 ; CHECK-RV64-NEXT: .LBB61_216: # %else834 ; CHECK-RV64-NEXT: slli a2, a1, 45 ; CHECK-RV64-NEXT: bgez a2, .LBB61_217 -; CHECK-RV64-NEXT: j .LBB61_731 +; CHECK-RV64-NEXT: j .LBB61_734 ; CHECK-RV64-NEXT: .LBB61_217: # %else838 ; CHECK-RV64-NEXT: slli a2, a1, 44 ; CHECK-RV64-NEXT: bgez a2, .LBB61_218 -; CHECK-RV64-NEXT: j .LBB61_732 +; CHECK-RV64-NEXT: j .LBB61_735 ; CHECK-RV64-NEXT: .LBB61_218: # %else842 ; CHECK-RV64-NEXT: slli a2, a1, 43 ; CHECK-RV64-NEXT: bgez a2, .LBB61_219 -; CHECK-RV64-NEXT: j .LBB61_733 +; CHECK-RV64-NEXT: j .LBB61_736 ; CHECK-RV64-NEXT: .LBB61_219: # %else846 ; CHECK-RV64-NEXT: slli a2, a1, 42 ; CHECK-RV64-NEXT: bgez a2, .LBB61_220 -; CHECK-RV64-NEXT: j .LBB61_734 +; CHECK-RV64-NEXT: j .LBB61_737 ; CHECK-RV64-NEXT: .LBB61_220: # %else850 ; CHECK-RV64-NEXT: slli a2, a1, 41 ; CHECK-RV64-NEXT: bgez a2, .LBB61_221 -; CHECK-RV64-NEXT: j .LBB61_735 +; CHECK-RV64-NEXT: j .LBB61_738 ; CHECK-RV64-NEXT: .LBB61_221: # %else854 ; CHECK-RV64-NEXT: slli a2, a1, 40 ; CHECK-RV64-NEXT: bgez a2, .LBB61_222 -; CHECK-RV64-NEXT: j .LBB61_736 +; CHECK-RV64-NEXT: j .LBB61_739 ; CHECK-RV64-NEXT: .LBB61_222: # %else858 ; CHECK-RV64-NEXT: slli a2, a1, 39 ; CHECK-RV64-NEXT: bgez a2, .LBB61_223 -; CHECK-RV64-NEXT: j .LBB61_737 +; CHECK-RV64-NEXT: j .LBB61_740 ; CHECK-RV64-NEXT: .LBB61_223: # %else862 ; CHECK-RV64-NEXT: slli a2, a1, 38 ; CHECK-RV64-NEXT: bgez a2, .LBB61_224 -; CHECK-RV64-NEXT: j .LBB61_738 +; CHECK-RV64-NEXT: j .LBB61_741 ; CHECK-RV64-NEXT: .LBB61_224: # %else866 ; CHECK-RV64-NEXT: slli a2, a1, 37 ; CHECK-RV64-NEXT: bgez a2, .LBB61_225 -; CHECK-RV64-NEXT: j .LBB61_739 +; CHECK-RV64-NEXT: j .LBB61_742 ; CHECK-RV64-NEXT: .LBB61_225: # %else870 ; CHECK-RV64-NEXT: slli a2, a1, 36 ; CHECK-RV64-NEXT: bgez a2, .LBB61_226 -; CHECK-RV64-NEXT: j .LBB61_740 +; CHECK-RV64-NEXT: j .LBB61_743 ; CHECK-RV64-NEXT: .LBB61_226: # %else874 ; CHECK-RV64-NEXT: slli a2, a1, 35 ; CHECK-RV64-NEXT: bgez a2, .LBB61_227 -; CHECK-RV64-NEXT: j .LBB61_741 +; CHECK-RV64-NEXT: j .LBB61_744 ; CHECK-RV64-NEXT: .LBB61_227: # %else878 ; CHECK-RV64-NEXT: slli a2, a1, 34 ; CHECK-RV64-NEXT: bgez a2, .LBB61_228 -; CHECK-RV64-NEXT: j .LBB61_742 +; CHECK-RV64-NEXT: j .LBB61_745 ; CHECK-RV64-NEXT: .LBB61_228: # %else882 ; CHECK-RV64-NEXT: slli a2, a1, 33 ; CHECK-RV64-NEXT: bgez a2, .LBB61_229 -; CHECK-RV64-NEXT: j .LBB61_743 +; CHECK-RV64-NEXT: j .LBB61_746 ; CHECK-RV64-NEXT: .LBB61_229: # %else886 ; CHECK-RV64-NEXT: slli a2, a1, 32 ; CHECK-RV64-NEXT: bgez a2, .LBB61_230 -; CHECK-RV64-NEXT: j .LBB61_744 +; CHECK-RV64-NEXT: j .LBB61_747 ; CHECK-RV64-NEXT: .LBB61_230: # %else890 ; CHECK-RV64-NEXT: slli a2, a1, 31 ; CHECK-RV64-NEXT: bgez a2, .LBB61_231 -; CHECK-RV64-NEXT: j .LBB61_745 +; CHECK-RV64-NEXT: j .LBB61_748 ; CHECK-RV64-NEXT: .LBB61_231: # %else894 ; CHECK-RV64-NEXT: slli a2, a1, 30 ; CHECK-RV64-NEXT: bgez a2, .LBB61_232 -; CHECK-RV64-NEXT: j .LBB61_746 +; CHECK-RV64-NEXT: j .LBB61_749 ; CHECK-RV64-NEXT: .LBB61_232: # %else898 ; CHECK-RV64-NEXT: slli a2, a1, 29 ; CHECK-RV64-NEXT: bgez a2, .LBB61_233 -; CHECK-RV64-NEXT: j .LBB61_747 +; CHECK-RV64-NEXT: j .LBB61_750 ; CHECK-RV64-NEXT: .LBB61_233: # %else902 ; CHECK-RV64-NEXT: slli a2, a1, 28 ; CHECK-RV64-NEXT: bgez a2, .LBB61_234 -; CHECK-RV64-NEXT: j .LBB61_748 +; CHECK-RV64-NEXT: j .LBB61_751 ; CHECK-RV64-NEXT: .LBB61_234: # %else906 ; CHECK-RV64-NEXT: slli a2, a1, 27 ; CHECK-RV64-NEXT: bgez a2, .LBB61_235 -; CHECK-RV64-NEXT: j .LBB61_749 +; CHECK-RV64-NEXT: j .LBB61_752 ; CHECK-RV64-NEXT: .LBB61_235: # %else910 ; CHECK-RV64-NEXT: slli a2, a1, 26 ; CHECK-RV64-NEXT: bgez a2, .LBB61_236 -; CHECK-RV64-NEXT: j .LBB61_750 +; CHECK-RV64-NEXT: j .LBB61_753 ; CHECK-RV64-NEXT: .LBB61_236: # %else914 ; CHECK-RV64-NEXT: slli a2, a1, 25 ; CHECK-RV64-NEXT: bgez a2, .LBB61_237 -; CHECK-RV64-NEXT: j .LBB61_751 +; CHECK-RV64-NEXT: j .LBB61_754 ; CHECK-RV64-NEXT: .LBB61_237: # %else918 ; CHECK-RV64-NEXT: slli a2, a1, 24 ; CHECK-RV64-NEXT: bgez a2, .LBB61_238 -; CHECK-RV64-NEXT: j .LBB61_752 +; CHECK-RV64-NEXT: j .LBB61_755 ; CHECK-RV64-NEXT: .LBB61_238: # %else922 ; CHECK-RV64-NEXT: slli a2, a1, 23 ; CHECK-RV64-NEXT: bgez a2, .LBB61_239 -; CHECK-RV64-NEXT: j .LBB61_753 +; CHECK-RV64-NEXT: j .LBB61_756 ; CHECK-RV64-NEXT: .LBB61_239: # %else926 ; CHECK-RV64-NEXT: slli a2, a1, 22 ; CHECK-RV64-NEXT: bgez a2, .LBB61_240 -; CHECK-RV64-NEXT: j .LBB61_754 +; CHECK-RV64-NEXT: j .LBB61_757 ; CHECK-RV64-NEXT: .LBB61_240: # %else930 ; CHECK-RV64-NEXT: slli a2, a1, 21 ; CHECK-RV64-NEXT: bgez a2, .LBB61_241 -; CHECK-RV64-NEXT: j .LBB61_755 +; CHECK-RV64-NEXT: j .LBB61_758 ; CHECK-RV64-NEXT: .LBB61_241: # %else934 ; CHECK-RV64-NEXT: slli a2, a1, 20 ; CHECK-RV64-NEXT: bgez a2, .LBB61_242 -; CHECK-RV64-NEXT: j .LBB61_756 +; CHECK-RV64-NEXT: j .LBB61_759 ; CHECK-RV64-NEXT: .LBB61_242: # %else938 ; CHECK-RV64-NEXT: slli a2, a1, 19 ; CHECK-RV64-NEXT: bgez a2, .LBB61_243 -; CHECK-RV64-NEXT: j .LBB61_757 +; CHECK-RV64-NEXT: j .LBB61_760 ; CHECK-RV64-NEXT: .LBB61_243: # %else942 ; CHECK-RV64-NEXT: slli a2, a1, 18 ; CHECK-RV64-NEXT: bgez a2, .LBB61_244 -; CHECK-RV64-NEXT: j .LBB61_758 +; CHECK-RV64-NEXT: j .LBB61_761 ; CHECK-RV64-NEXT: .LBB61_244: # %else946 ; CHECK-RV64-NEXT: slli a2, a1, 17 ; CHECK-RV64-NEXT: bgez a2, .LBB61_245 -; CHECK-RV64-NEXT: j .LBB61_759 +; CHECK-RV64-NEXT: j .LBB61_762 ; CHECK-RV64-NEXT: .LBB61_245: # %else950 ; CHECK-RV64-NEXT: slli a2, a1, 16 ; CHECK-RV64-NEXT: bgez a2, .LBB61_246 -; CHECK-RV64-NEXT: j .LBB61_760 +; CHECK-RV64-NEXT: j .LBB61_763 ; CHECK-RV64-NEXT: .LBB61_246: # %else954 ; CHECK-RV64-NEXT: slli a2, a1, 15 ; CHECK-RV64-NEXT: bgez a2, .LBB61_247 -; CHECK-RV64-NEXT: j .LBB61_761 +; CHECK-RV64-NEXT: j .LBB61_764 ; CHECK-RV64-NEXT: .LBB61_247: # %else958 ; CHECK-RV64-NEXT: slli a2, a1, 14 ; CHECK-RV64-NEXT: bgez a2, .LBB61_248 -; CHECK-RV64-NEXT: j .LBB61_762 +; CHECK-RV64-NEXT: j .LBB61_765 ; CHECK-RV64-NEXT: .LBB61_248: # %else962 ; CHECK-RV64-NEXT: slli a2, a1, 13 ; CHECK-RV64-NEXT: bgez a2, .LBB61_249 -; CHECK-RV64-NEXT: j .LBB61_763 +; CHECK-RV64-NEXT: j .LBB61_766 ; CHECK-RV64-NEXT: .LBB61_249: # %else966 ; CHECK-RV64-NEXT: slli a2, a1, 12 ; CHECK-RV64-NEXT: bgez a2, .LBB61_250 -; CHECK-RV64-NEXT: j .LBB61_764 +; CHECK-RV64-NEXT: j .LBB61_767 ; CHECK-RV64-NEXT: .LBB61_250: # %else970 ; CHECK-RV64-NEXT: slli a2, a1, 11 ; CHECK-RV64-NEXT: bgez a2, .LBB61_251 -; CHECK-RV64-NEXT: j .LBB61_765 +; CHECK-RV64-NEXT: j .LBB61_768 ; CHECK-RV64-NEXT: .LBB61_251: # %else974 ; CHECK-RV64-NEXT: slli a2, a1, 10 ; CHECK-RV64-NEXT: bgez a2, .LBB61_252 -; CHECK-RV64-NEXT: j .LBB61_766 +; CHECK-RV64-NEXT: j .LBB61_769 ; CHECK-RV64-NEXT: .LBB61_252: # %else978 ; CHECK-RV64-NEXT: slli a2, a1, 9 ; CHECK-RV64-NEXT: bgez a2, .LBB61_253 -; CHECK-RV64-NEXT: j .LBB61_767 +; CHECK-RV64-NEXT: j .LBB61_770 ; CHECK-RV64-NEXT: .LBB61_253: # %else982 ; CHECK-RV64-NEXT: slli a2, a1, 8 ; CHECK-RV64-NEXT: bgez a2, .LBB61_254 -; CHECK-RV64-NEXT: j .LBB61_768 +; CHECK-RV64-NEXT: j .LBB61_771 ; CHECK-RV64-NEXT: .LBB61_254: # %else986 ; CHECK-RV64-NEXT: slli a2, a1, 7 ; CHECK-RV64-NEXT: bgez a2, .LBB61_255 -; CHECK-RV64-NEXT: j .LBB61_769 +; CHECK-RV64-NEXT: j .LBB61_772 ; CHECK-RV64-NEXT: .LBB61_255: # %else990 ; CHECK-RV64-NEXT: slli a2, a1, 6 ; CHECK-RV64-NEXT: bgez a2, .LBB61_256 -; CHECK-RV64-NEXT: j .LBB61_770 +; CHECK-RV64-NEXT: j .LBB61_773 ; CHECK-RV64-NEXT: .LBB61_256: # %else994 ; CHECK-RV64-NEXT: slli a2, a1, 5 ; CHECK-RV64-NEXT: bgez a2, .LBB61_257 -; CHECK-RV64-NEXT: j .LBB61_771 +; CHECK-RV64-NEXT: j .LBB61_774 ; CHECK-RV64-NEXT: .LBB61_257: # %else998 ; CHECK-RV64-NEXT: slli a2, a1, 4 ; CHECK-RV64-NEXT: bgez a2, .LBB61_258 -; CHECK-RV64-NEXT: j .LBB61_772 +; CHECK-RV64-NEXT: j .LBB61_775 ; CHECK-RV64-NEXT: .LBB61_258: # %else1002 ; CHECK-RV64-NEXT: slli a2, a1, 3 ; CHECK-RV64-NEXT: bgez a2, .LBB61_259 -; CHECK-RV64-NEXT: j .LBB61_773 +; CHECK-RV64-NEXT: j .LBB61_776 ; CHECK-RV64-NEXT: .LBB61_259: # %else1006 ; CHECK-RV64-NEXT: slli a2, a1, 2 ; CHECK-RV64-NEXT: bgez a2, .LBB61_261 @@ -11674,251 +11674,251 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-RV64-NEXT: vmv.x.s a2, v24 ; CHECK-RV64-NEXT: bgez a1, .LBB61_264 -; CHECK-RV64-NEXT: j .LBB61_774 +; CHECK-RV64-NEXT: j .LBB61_778 ; CHECK-RV64-NEXT: .LBB61_264: # %else1018 ; CHECK-RV64-NEXT: andi a1, a2, 1 ; CHECK-RV64-NEXT: beqz a1, .LBB61_265 -; CHECK-RV64-NEXT: j .LBB61_775 +; CHECK-RV64-NEXT: j .LBB61_779 ; CHECK-RV64-NEXT: .LBB61_265: # %else1022 ; CHECK-RV64-NEXT: andi a1, a2, 2 ; CHECK-RV64-NEXT: beqz a1, .LBB61_266 -; CHECK-RV64-NEXT: j .LBB61_776 +; CHECK-RV64-NEXT: j .LBB61_780 ; CHECK-RV64-NEXT: .LBB61_266: # %else1026 ; CHECK-RV64-NEXT: andi a1, a2, 4 ; CHECK-RV64-NEXT: beqz a1, .LBB61_267 -; CHECK-RV64-NEXT: j .LBB61_777 +; CHECK-RV64-NEXT: j .LBB61_781 ; CHECK-RV64-NEXT: .LBB61_267: # %else1030 ; CHECK-RV64-NEXT: andi a1, a2, 8 ; CHECK-RV64-NEXT: beqz a1, .LBB61_268 -; CHECK-RV64-NEXT: j .LBB61_778 +; CHECK-RV64-NEXT: j .LBB61_782 ; CHECK-RV64-NEXT: .LBB61_268: # %else1034 ; CHECK-RV64-NEXT: andi a1, a2, 16 ; CHECK-RV64-NEXT: beqz a1, .LBB61_269 -; CHECK-RV64-NEXT: j .LBB61_779 +; CHECK-RV64-NEXT: j .LBB61_783 ; CHECK-RV64-NEXT: .LBB61_269: # %else1038 ; CHECK-RV64-NEXT: andi a1, a2, 32 ; CHECK-RV64-NEXT: beqz a1, .LBB61_270 -; CHECK-RV64-NEXT: j .LBB61_780 +; CHECK-RV64-NEXT: j .LBB61_784 ; CHECK-RV64-NEXT: .LBB61_270: # %else1042 ; CHECK-RV64-NEXT: andi a1, a2, 64 ; CHECK-RV64-NEXT: beqz a1, .LBB61_271 -; CHECK-RV64-NEXT: j .LBB61_781 +; CHECK-RV64-NEXT: j .LBB61_785 ; CHECK-RV64-NEXT: .LBB61_271: # %else1046 ; CHECK-RV64-NEXT: andi a1, a2, 128 ; CHECK-RV64-NEXT: beqz a1, .LBB61_272 -; CHECK-RV64-NEXT: j .LBB61_782 +; CHECK-RV64-NEXT: j .LBB61_786 ; CHECK-RV64-NEXT: .LBB61_272: # %else1050 ; CHECK-RV64-NEXT: andi a1, a2, 256 ; CHECK-RV64-NEXT: beqz a1, .LBB61_273 -; CHECK-RV64-NEXT: j .LBB61_783 +; CHECK-RV64-NEXT: j .LBB61_787 ; CHECK-RV64-NEXT: .LBB61_273: # %else1054 ; CHECK-RV64-NEXT: andi a1, a2, 512 ; CHECK-RV64-NEXT: beqz a1, .LBB61_274 -; CHECK-RV64-NEXT: j .LBB61_784 +; CHECK-RV64-NEXT: j .LBB61_788 ; CHECK-RV64-NEXT: .LBB61_274: # %else1058 ; CHECK-RV64-NEXT: andi a1, a2, 1024 ; CHECK-RV64-NEXT: beqz a1, .LBB61_275 -; CHECK-RV64-NEXT: j .LBB61_785 +; CHECK-RV64-NEXT: j .LBB61_789 ; CHECK-RV64-NEXT: .LBB61_275: # %else1062 ; CHECK-RV64-NEXT: slli a1, a2, 52 ; CHECK-RV64-NEXT: bgez a1, .LBB61_276 -; CHECK-RV64-NEXT: j .LBB61_786 +; CHECK-RV64-NEXT: j .LBB61_790 ; CHECK-RV64-NEXT: .LBB61_276: # %else1066 ; CHECK-RV64-NEXT: slli a1, a2, 51 ; CHECK-RV64-NEXT: bgez a1, .LBB61_277 -; CHECK-RV64-NEXT: j .LBB61_787 +; CHECK-RV64-NEXT: j .LBB61_791 ; CHECK-RV64-NEXT: .LBB61_277: # %else1070 ; CHECK-RV64-NEXT: slli a1, a2, 50 ; CHECK-RV64-NEXT: bgez a1, .LBB61_278 -; CHECK-RV64-NEXT: j .LBB61_788 +; CHECK-RV64-NEXT: j .LBB61_792 ; CHECK-RV64-NEXT: .LBB61_278: # %else1074 ; CHECK-RV64-NEXT: slli a1, a2, 49 ; CHECK-RV64-NEXT: bgez a1, .LBB61_279 -; CHECK-RV64-NEXT: j .LBB61_789 +; CHECK-RV64-NEXT: j .LBB61_793 ; CHECK-RV64-NEXT: .LBB61_279: # %else1078 ; CHECK-RV64-NEXT: slli a1, a2, 48 ; CHECK-RV64-NEXT: bgez a1, .LBB61_280 -; CHECK-RV64-NEXT: j .LBB61_790 +; CHECK-RV64-NEXT: j .LBB61_794 ; CHECK-RV64-NEXT: .LBB61_280: # %else1082 ; CHECK-RV64-NEXT: slli a1, a2, 47 ; CHECK-RV64-NEXT: bgez a1, .LBB61_281 -; CHECK-RV64-NEXT: j .LBB61_791 +; CHECK-RV64-NEXT: j .LBB61_795 ; CHECK-RV64-NEXT: .LBB61_281: # %else1086 ; CHECK-RV64-NEXT: slli a1, a2, 46 ; CHECK-RV64-NEXT: bgez a1, .LBB61_282 -; CHECK-RV64-NEXT: j .LBB61_792 +; CHECK-RV64-NEXT: j .LBB61_796 ; CHECK-RV64-NEXT: .LBB61_282: # %else1090 ; CHECK-RV64-NEXT: slli a1, a2, 45 ; CHECK-RV64-NEXT: bgez a1, .LBB61_283 -; CHECK-RV64-NEXT: j .LBB61_793 +; CHECK-RV64-NEXT: j .LBB61_797 ; CHECK-RV64-NEXT: .LBB61_283: # %else1094 ; CHECK-RV64-NEXT: slli a1, a2, 44 ; CHECK-RV64-NEXT: bgez a1, .LBB61_284 -; CHECK-RV64-NEXT: j .LBB61_794 +; CHECK-RV64-NEXT: j .LBB61_798 ; CHECK-RV64-NEXT: .LBB61_284: # %else1098 ; CHECK-RV64-NEXT: slli a1, a2, 43 ; CHECK-RV64-NEXT: bgez a1, .LBB61_285 -; CHECK-RV64-NEXT: j .LBB61_795 +; CHECK-RV64-NEXT: j .LBB61_799 ; CHECK-RV64-NEXT: .LBB61_285: # %else1102 ; CHECK-RV64-NEXT: slli a1, a2, 42 ; CHECK-RV64-NEXT: bgez a1, .LBB61_286 -; CHECK-RV64-NEXT: j .LBB61_796 +; CHECK-RV64-NEXT: j .LBB61_800 ; CHECK-RV64-NEXT: .LBB61_286: # %else1106 ; CHECK-RV64-NEXT: slli a1, a2, 41 ; CHECK-RV64-NEXT: bgez a1, .LBB61_287 -; CHECK-RV64-NEXT: j .LBB61_797 +; CHECK-RV64-NEXT: j .LBB61_801 ; CHECK-RV64-NEXT: .LBB61_287: # %else1110 ; CHECK-RV64-NEXT: slli a1, a2, 40 ; CHECK-RV64-NEXT: bgez a1, .LBB61_288 -; CHECK-RV64-NEXT: j .LBB61_798 +; CHECK-RV64-NEXT: j .LBB61_802 ; CHECK-RV64-NEXT: .LBB61_288: # %else1114 ; CHECK-RV64-NEXT: slli a1, a2, 39 ; CHECK-RV64-NEXT: bgez a1, .LBB61_289 -; CHECK-RV64-NEXT: j .LBB61_799 +; CHECK-RV64-NEXT: j .LBB61_803 ; CHECK-RV64-NEXT: .LBB61_289: # %else1118 ; CHECK-RV64-NEXT: slli a1, a2, 38 ; CHECK-RV64-NEXT: bgez a1, .LBB61_290 -; CHECK-RV64-NEXT: j .LBB61_800 +; CHECK-RV64-NEXT: j .LBB61_804 ; CHECK-RV64-NEXT: .LBB61_290: # %else1122 ; CHECK-RV64-NEXT: slli a1, a2, 37 ; CHECK-RV64-NEXT: bgez a1, .LBB61_291 -; CHECK-RV64-NEXT: j .LBB61_801 +; CHECK-RV64-NEXT: j .LBB61_805 ; CHECK-RV64-NEXT: .LBB61_291: # %else1126 ; CHECK-RV64-NEXT: slli a1, a2, 36 ; CHECK-RV64-NEXT: bgez a1, .LBB61_292 -; CHECK-RV64-NEXT: j .LBB61_802 +; CHECK-RV64-NEXT: j .LBB61_806 ; CHECK-RV64-NEXT: .LBB61_292: # %else1130 ; CHECK-RV64-NEXT: slli a1, a2, 35 ; CHECK-RV64-NEXT: bgez a1, .LBB61_293 -; CHECK-RV64-NEXT: j .LBB61_803 +; CHECK-RV64-NEXT: j .LBB61_807 ; CHECK-RV64-NEXT: .LBB61_293: # %else1134 ; CHECK-RV64-NEXT: slli a1, a2, 34 ; CHECK-RV64-NEXT: bgez a1, .LBB61_294 -; CHECK-RV64-NEXT: j .LBB61_804 +; CHECK-RV64-NEXT: j .LBB61_808 ; CHECK-RV64-NEXT: .LBB61_294: # %else1138 ; CHECK-RV64-NEXT: slli a1, a2, 33 ; CHECK-RV64-NEXT: bgez a1, .LBB61_295 -; CHECK-RV64-NEXT: j .LBB61_805 +; CHECK-RV64-NEXT: j .LBB61_809 ; CHECK-RV64-NEXT: .LBB61_295: # %else1142 ; CHECK-RV64-NEXT: slli a1, a2, 32 ; CHECK-RV64-NEXT: bgez a1, .LBB61_296 -; CHECK-RV64-NEXT: j .LBB61_806 +; CHECK-RV64-NEXT: j .LBB61_810 ; CHECK-RV64-NEXT: .LBB61_296: # %else1146 ; CHECK-RV64-NEXT: slli a1, a2, 31 ; CHECK-RV64-NEXT: bgez a1, .LBB61_297 -; CHECK-RV64-NEXT: j .LBB61_807 +; CHECK-RV64-NEXT: j .LBB61_811 ; CHECK-RV64-NEXT: .LBB61_297: # %else1150 ; CHECK-RV64-NEXT: slli a1, a2, 30 ; CHECK-RV64-NEXT: bgez a1, .LBB61_298 -; CHECK-RV64-NEXT: j .LBB61_808 +; CHECK-RV64-NEXT: j .LBB61_812 ; CHECK-RV64-NEXT: .LBB61_298: # %else1154 ; CHECK-RV64-NEXT: slli a1, a2, 29 ; CHECK-RV64-NEXT: bgez a1, .LBB61_299 -; CHECK-RV64-NEXT: j .LBB61_809 +; CHECK-RV64-NEXT: j .LBB61_813 ; CHECK-RV64-NEXT: .LBB61_299: # %else1158 ; CHECK-RV64-NEXT: slli a1, a2, 28 ; CHECK-RV64-NEXT: bgez a1, .LBB61_300 -; CHECK-RV64-NEXT: j .LBB61_810 +; CHECK-RV64-NEXT: j .LBB61_814 ; CHECK-RV64-NEXT: .LBB61_300: # %else1162 ; CHECK-RV64-NEXT: slli a1, a2, 27 ; CHECK-RV64-NEXT: bgez a1, .LBB61_301 -; CHECK-RV64-NEXT: j .LBB61_811 +; CHECK-RV64-NEXT: j .LBB61_815 ; CHECK-RV64-NEXT: .LBB61_301: # %else1166 ; CHECK-RV64-NEXT: slli a1, a2, 26 ; CHECK-RV64-NEXT: bgez a1, .LBB61_302 -; CHECK-RV64-NEXT: j .LBB61_812 +; CHECK-RV64-NEXT: j .LBB61_816 ; CHECK-RV64-NEXT: .LBB61_302: # %else1170 ; CHECK-RV64-NEXT: slli a1, a2, 25 ; CHECK-RV64-NEXT: bgez a1, .LBB61_303 -; CHECK-RV64-NEXT: j .LBB61_813 +; CHECK-RV64-NEXT: j .LBB61_817 ; CHECK-RV64-NEXT: .LBB61_303: # %else1174 ; CHECK-RV64-NEXT: slli a1, a2, 24 ; CHECK-RV64-NEXT: bgez a1, .LBB61_304 -; CHECK-RV64-NEXT: j .LBB61_814 +; CHECK-RV64-NEXT: j .LBB61_818 ; CHECK-RV64-NEXT: .LBB61_304: # %else1178 ; CHECK-RV64-NEXT: slli a1, a2, 23 ; CHECK-RV64-NEXT: bgez a1, .LBB61_305 -; CHECK-RV64-NEXT: j .LBB61_815 +; CHECK-RV64-NEXT: j .LBB61_819 ; CHECK-RV64-NEXT: .LBB61_305: # %else1182 ; CHECK-RV64-NEXT: slli a1, a2, 22 ; CHECK-RV64-NEXT: bgez a1, .LBB61_306 -; CHECK-RV64-NEXT: j .LBB61_816 +; CHECK-RV64-NEXT: j .LBB61_820 ; CHECK-RV64-NEXT: .LBB61_306: # %else1186 ; CHECK-RV64-NEXT: slli a1, a2, 21 ; CHECK-RV64-NEXT: bgez a1, .LBB61_307 -; CHECK-RV64-NEXT: j .LBB61_817 +; CHECK-RV64-NEXT: j .LBB61_821 ; CHECK-RV64-NEXT: .LBB61_307: # %else1190 ; CHECK-RV64-NEXT: slli a1, a2, 20 ; CHECK-RV64-NEXT: bgez a1, .LBB61_308 -; CHECK-RV64-NEXT: j .LBB61_818 +; CHECK-RV64-NEXT: j .LBB61_822 ; CHECK-RV64-NEXT: .LBB61_308: # %else1194 ; CHECK-RV64-NEXT: slli a1, a2, 19 ; CHECK-RV64-NEXT: bgez a1, .LBB61_309 -; CHECK-RV64-NEXT: j .LBB61_819 +; CHECK-RV64-NEXT: j .LBB61_823 ; CHECK-RV64-NEXT: .LBB61_309: # %else1198 ; CHECK-RV64-NEXT: slli a1, a2, 18 ; CHECK-RV64-NEXT: bgez a1, .LBB61_310 -; CHECK-RV64-NEXT: j .LBB61_820 +; CHECK-RV64-NEXT: j .LBB61_824 ; CHECK-RV64-NEXT: .LBB61_310: # %else1202 ; CHECK-RV64-NEXT: slli a1, a2, 17 ; CHECK-RV64-NEXT: bgez a1, .LBB61_311 -; CHECK-RV64-NEXT: j .LBB61_821 +; CHECK-RV64-NEXT: j .LBB61_825 ; CHECK-RV64-NEXT: .LBB61_311: # %else1206 ; CHECK-RV64-NEXT: slli a1, a2, 16 ; CHECK-RV64-NEXT: bgez a1, .LBB61_312 -; CHECK-RV64-NEXT: j .LBB61_822 +; CHECK-RV64-NEXT: j .LBB61_826 ; CHECK-RV64-NEXT: .LBB61_312: # %else1210 ; CHECK-RV64-NEXT: slli a1, a2, 15 ; CHECK-RV64-NEXT: bgez a1, .LBB61_313 -; CHECK-RV64-NEXT: j .LBB61_823 +; CHECK-RV64-NEXT: j .LBB61_827 ; CHECK-RV64-NEXT: .LBB61_313: # %else1214 ; CHECK-RV64-NEXT: slli a1, a2, 14 ; CHECK-RV64-NEXT: bgez a1, .LBB61_314 -; CHECK-RV64-NEXT: j .LBB61_824 +; CHECK-RV64-NEXT: j .LBB61_828 ; CHECK-RV64-NEXT: .LBB61_314: # %else1218 ; CHECK-RV64-NEXT: slli a1, a2, 13 ; CHECK-RV64-NEXT: bgez a1, .LBB61_315 -; CHECK-RV64-NEXT: j .LBB61_825 +; CHECK-RV64-NEXT: j .LBB61_829 ; CHECK-RV64-NEXT: .LBB61_315: # %else1222 ; CHECK-RV64-NEXT: slli a1, a2, 12 ; CHECK-RV64-NEXT: bgez a1, .LBB61_316 -; CHECK-RV64-NEXT: j .LBB61_826 +; CHECK-RV64-NEXT: j .LBB61_830 ; CHECK-RV64-NEXT: .LBB61_316: # %else1226 ; CHECK-RV64-NEXT: slli a1, a2, 11 ; CHECK-RV64-NEXT: bgez a1, .LBB61_317 -; CHECK-RV64-NEXT: j .LBB61_827 +; CHECK-RV64-NEXT: j .LBB61_831 ; CHECK-RV64-NEXT: .LBB61_317: # %else1230 ; CHECK-RV64-NEXT: slli a1, a2, 10 ; CHECK-RV64-NEXT: bgez a1, .LBB61_318 -; CHECK-RV64-NEXT: j .LBB61_828 +; CHECK-RV64-NEXT: j .LBB61_832 ; CHECK-RV64-NEXT: .LBB61_318: # %else1234 ; CHECK-RV64-NEXT: slli a1, a2, 9 ; CHECK-RV64-NEXT: bgez a1, .LBB61_319 -; CHECK-RV64-NEXT: j .LBB61_829 +; CHECK-RV64-NEXT: j .LBB61_833 ; CHECK-RV64-NEXT: .LBB61_319: # %else1238 ; CHECK-RV64-NEXT: slli a1, a2, 8 ; CHECK-RV64-NEXT: bgez a1, .LBB61_320 -; CHECK-RV64-NEXT: j .LBB61_830 +; CHECK-RV64-NEXT: j .LBB61_834 ; CHECK-RV64-NEXT: .LBB61_320: # %else1242 ; CHECK-RV64-NEXT: slli a1, a2, 7 ; CHECK-RV64-NEXT: bgez a1, .LBB61_321 -; CHECK-RV64-NEXT: j .LBB61_831 +; CHECK-RV64-NEXT: j .LBB61_835 ; CHECK-RV64-NEXT: .LBB61_321: # %else1246 ; CHECK-RV64-NEXT: slli a1, a2, 6 ; CHECK-RV64-NEXT: bgez a1, .LBB61_322 -; CHECK-RV64-NEXT: j .LBB61_832 +; CHECK-RV64-NEXT: j .LBB61_836 ; CHECK-RV64-NEXT: .LBB61_322: # %else1250 ; CHECK-RV64-NEXT: slli a1, a2, 5 ; CHECK-RV64-NEXT: bgez a1, .LBB61_323 -; CHECK-RV64-NEXT: j .LBB61_833 +; CHECK-RV64-NEXT: j .LBB61_837 ; CHECK-RV64-NEXT: .LBB61_323: # %else1254 ; CHECK-RV64-NEXT: slli a1, a2, 4 ; CHECK-RV64-NEXT: bgez a1, .LBB61_324 -; CHECK-RV64-NEXT: j .LBB61_834 +; CHECK-RV64-NEXT: j .LBB61_838 ; CHECK-RV64-NEXT: .LBB61_324: # %else1258 ; CHECK-RV64-NEXT: slli a1, a2, 3 ; CHECK-RV64-NEXT: bgez a1, .LBB61_325 -; CHECK-RV64-NEXT: j .LBB61_835 +; CHECK-RV64-NEXT: j .LBB61_839 ; CHECK-RV64-NEXT: .LBB61_325: # %else1262 ; CHECK-RV64-NEXT: slli a1, a2, 2 ; CHECK-RV64-NEXT: bgez a1, .LBB61_327 @@ -11949,251 +11949,251 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-RV64-NEXT: vmv.x.s a1, v24 ; CHECK-RV64-NEXT: bgez a2, .LBB61_330 -; CHECK-RV64-NEXT: j .LBB61_836 +; CHECK-RV64-NEXT: j .LBB61_841 ; CHECK-RV64-NEXT: .LBB61_330: # %else1274 ; CHECK-RV64-NEXT: andi a2, a1, 1 ; CHECK-RV64-NEXT: beqz a2, .LBB61_331 -; CHECK-RV64-NEXT: j .LBB61_837 +; CHECK-RV64-NEXT: j .LBB61_842 ; CHECK-RV64-NEXT: .LBB61_331: # %else1278 ; CHECK-RV64-NEXT: andi a2, a1, 2 ; CHECK-RV64-NEXT: beqz a2, .LBB61_332 -; CHECK-RV64-NEXT: j .LBB61_838 +; CHECK-RV64-NEXT: j .LBB61_843 ; CHECK-RV64-NEXT: .LBB61_332: # %else1282 ; CHECK-RV64-NEXT: andi a2, a1, 4 ; CHECK-RV64-NEXT: beqz a2, .LBB61_333 -; CHECK-RV64-NEXT: j .LBB61_839 +; CHECK-RV64-NEXT: j .LBB61_844 ; CHECK-RV64-NEXT: .LBB61_333: # %else1286 ; CHECK-RV64-NEXT: andi a2, a1, 8 ; CHECK-RV64-NEXT: beqz a2, .LBB61_334 -; CHECK-RV64-NEXT: j .LBB61_840 +; CHECK-RV64-NEXT: j .LBB61_845 ; CHECK-RV64-NEXT: .LBB61_334: # %else1290 ; CHECK-RV64-NEXT: andi a2, a1, 16 ; CHECK-RV64-NEXT: beqz a2, .LBB61_335 -; CHECK-RV64-NEXT: j .LBB61_841 +; CHECK-RV64-NEXT: j .LBB61_846 ; CHECK-RV64-NEXT: .LBB61_335: # %else1294 ; CHECK-RV64-NEXT: andi a2, a1, 32 ; CHECK-RV64-NEXT: beqz a2, .LBB61_336 -; CHECK-RV64-NEXT: j .LBB61_842 +; CHECK-RV64-NEXT: j .LBB61_847 ; CHECK-RV64-NEXT: .LBB61_336: # %else1298 ; CHECK-RV64-NEXT: andi a2, a1, 64 ; CHECK-RV64-NEXT: beqz a2, .LBB61_337 -; CHECK-RV64-NEXT: j .LBB61_843 +; CHECK-RV64-NEXT: j .LBB61_848 ; CHECK-RV64-NEXT: .LBB61_337: # %else1302 ; CHECK-RV64-NEXT: andi a2, a1, 128 ; CHECK-RV64-NEXT: beqz a2, .LBB61_338 -; CHECK-RV64-NEXT: j .LBB61_844 +; CHECK-RV64-NEXT: j .LBB61_849 ; CHECK-RV64-NEXT: .LBB61_338: # %else1306 ; CHECK-RV64-NEXT: andi a2, a1, 256 ; CHECK-RV64-NEXT: beqz a2, .LBB61_339 -; CHECK-RV64-NEXT: j .LBB61_845 +; CHECK-RV64-NEXT: j .LBB61_850 ; CHECK-RV64-NEXT: .LBB61_339: # %else1310 ; CHECK-RV64-NEXT: andi a2, a1, 512 ; CHECK-RV64-NEXT: beqz a2, .LBB61_340 -; CHECK-RV64-NEXT: j .LBB61_846 +; CHECK-RV64-NEXT: j .LBB61_851 ; CHECK-RV64-NEXT: .LBB61_340: # %else1314 ; CHECK-RV64-NEXT: andi a2, a1, 1024 ; CHECK-RV64-NEXT: beqz a2, .LBB61_341 -; CHECK-RV64-NEXT: j .LBB61_847 +; CHECK-RV64-NEXT: j .LBB61_852 ; CHECK-RV64-NEXT: .LBB61_341: # %else1318 ; CHECK-RV64-NEXT: slli a2, a1, 52 ; CHECK-RV64-NEXT: bgez a2, .LBB61_342 -; CHECK-RV64-NEXT: j .LBB61_848 +; CHECK-RV64-NEXT: j .LBB61_853 ; CHECK-RV64-NEXT: .LBB61_342: # %else1322 ; CHECK-RV64-NEXT: slli a2, a1, 51 ; CHECK-RV64-NEXT: bgez a2, .LBB61_343 -; CHECK-RV64-NEXT: j .LBB61_849 +; CHECK-RV64-NEXT: j .LBB61_854 ; CHECK-RV64-NEXT: .LBB61_343: # %else1326 ; CHECK-RV64-NEXT: slli a2, a1, 50 ; CHECK-RV64-NEXT: bgez a2, .LBB61_344 -; CHECK-RV64-NEXT: j .LBB61_850 +; CHECK-RV64-NEXT: j .LBB61_855 ; CHECK-RV64-NEXT: .LBB61_344: # %else1330 ; CHECK-RV64-NEXT: slli a2, a1, 49 ; CHECK-RV64-NEXT: bgez a2, .LBB61_345 -; CHECK-RV64-NEXT: j .LBB61_851 +; CHECK-RV64-NEXT: j .LBB61_856 ; CHECK-RV64-NEXT: .LBB61_345: # %else1334 ; CHECK-RV64-NEXT: slli a2, a1, 48 ; CHECK-RV64-NEXT: bgez a2, .LBB61_346 -; CHECK-RV64-NEXT: j .LBB61_852 +; CHECK-RV64-NEXT: j .LBB61_857 ; CHECK-RV64-NEXT: .LBB61_346: # %else1338 ; CHECK-RV64-NEXT: slli a2, a1, 47 ; CHECK-RV64-NEXT: bgez a2, .LBB61_347 -; CHECK-RV64-NEXT: j .LBB61_853 +; CHECK-RV64-NEXT: j .LBB61_858 ; CHECK-RV64-NEXT: .LBB61_347: # %else1342 ; CHECK-RV64-NEXT: slli a2, a1, 46 ; CHECK-RV64-NEXT: bgez a2, .LBB61_348 -; CHECK-RV64-NEXT: j .LBB61_854 +; CHECK-RV64-NEXT: j .LBB61_859 ; CHECK-RV64-NEXT: .LBB61_348: # %else1346 ; CHECK-RV64-NEXT: slli a2, a1, 45 ; CHECK-RV64-NEXT: bgez a2, .LBB61_349 -; CHECK-RV64-NEXT: j .LBB61_855 +; CHECK-RV64-NEXT: j .LBB61_860 ; CHECK-RV64-NEXT: .LBB61_349: # %else1350 ; CHECK-RV64-NEXT: slli a2, a1, 44 ; CHECK-RV64-NEXT: bgez a2, .LBB61_350 -; CHECK-RV64-NEXT: j .LBB61_856 +; CHECK-RV64-NEXT: j .LBB61_861 ; CHECK-RV64-NEXT: .LBB61_350: # %else1354 ; CHECK-RV64-NEXT: slli a2, a1, 43 ; CHECK-RV64-NEXT: bgez a2, .LBB61_351 -; CHECK-RV64-NEXT: j .LBB61_857 +; CHECK-RV64-NEXT: j .LBB61_862 ; CHECK-RV64-NEXT: .LBB61_351: # %else1358 ; CHECK-RV64-NEXT: slli a2, a1, 42 ; CHECK-RV64-NEXT: bgez a2, .LBB61_352 -; CHECK-RV64-NEXT: j .LBB61_858 +; CHECK-RV64-NEXT: j .LBB61_863 ; CHECK-RV64-NEXT: .LBB61_352: # %else1362 ; CHECK-RV64-NEXT: slli a2, a1, 41 ; CHECK-RV64-NEXT: bgez a2, .LBB61_353 -; CHECK-RV64-NEXT: j .LBB61_859 +; CHECK-RV64-NEXT: j .LBB61_864 ; CHECK-RV64-NEXT: .LBB61_353: # %else1366 ; CHECK-RV64-NEXT: slli a2, a1, 40 ; CHECK-RV64-NEXT: bgez a2, .LBB61_354 -; CHECK-RV64-NEXT: j .LBB61_860 +; CHECK-RV64-NEXT: j .LBB61_865 ; CHECK-RV64-NEXT: .LBB61_354: # %else1370 ; CHECK-RV64-NEXT: slli a2, a1, 39 ; CHECK-RV64-NEXT: bgez a2, .LBB61_355 -; CHECK-RV64-NEXT: j .LBB61_861 +; CHECK-RV64-NEXT: j .LBB61_866 ; CHECK-RV64-NEXT: .LBB61_355: # %else1374 ; CHECK-RV64-NEXT: slli a2, a1, 38 ; CHECK-RV64-NEXT: bgez a2, .LBB61_356 -; CHECK-RV64-NEXT: j .LBB61_862 +; CHECK-RV64-NEXT: j .LBB61_867 ; CHECK-RV64-NEXT: .LBB61_356: # %else1378 ; CHECK-RV64-NEXT: slli a2, a1, 37 ; CHECK-RV64-NEXT: bgez a2, .LBB61_357 -; CHECK-RV64-NEXT: j .LBB61_863 +; CHECK-RV64-NEXT: j .LBB61_868 ; CHECK-RV64-NEXT: .LBB61_357: # %else1382 ; CHECK-RV64-NEXT: slli a2, a1, 36 ; CHECK-RV64-NEXT: bgez a2, .LBB61_358 -; CHECK-RV64-NEXT: j .LBB61_864 +; CHECK-RV64-NEXT: j .LBB61_869 ; CHECK-RV64-NEXT: .LBB61_358: # %else1386 ; CHECK-RV64-NEXT: slli a2, a1, 35 ; CHECK-RV64-NEXT: bgez a2, .LBB61_359 -; CHECK-RV64-NEXT: j .LBB61_865 +; CHECK-RV64-NEXT: j .LBB61_870 ; CHECK-RV64-NEXT: .LBB61_359: # %else1390 ; CHECK-RV64-NEXT: slli a2, a1, 34 ; CHECK-RV64-NEXT: bgez a2, .LBB61_360 -; CHECK-RV64-NEXT: j .LBB61_866 +; CHECK-RV64-NEXT: j .LBB61_871 ; CHECK-RV64-NEXT: .LBB61_360: # %else1394 ; CHECK-RV64-NEXT: slli a2, a1, 33 ; CHECK-RV64-NEXT: bgez a2, .LBB61_361 -; CHECK-RV64-NEXT: j .LBB61_867 +; CHECK-RV64-NEXT: j .LBB61_872 ; CHECK-RV64-NEXT: .LBB61_361: # %else1398 ; CHECK-RV64-NEXT: slli a2, a1, 32 ; CHECK-RV64-NEXT: bgez a2, .LBB61_362 -; CHECK-RV64-NEXT: j .LBB61_868 +; CHECK-RV64-NEXT: j .LBB61_873 ; CHECK-RV64-NEXT: .LBB61_362: # %else1402 ; CHECK-RV64-NEXT: slli a2, a1, 31 ; CHECK-RV64-NEXT: bgez a2, .LBB61_363 -; CHECK-RV64-NEXT: j .LBB61_869 +; CHECK-RV64-NEXT: j .LBB61_874 ; CHECK-RV64-NEXT: .LBB61_363: # %else1406 ; CHECK-RV64-NEXT: slli a2, a1, 30 ; CHECK-RV64-NEXT: bgez a2, .LBB61_364 -; CHECK-RV64-NEXT: j .LBB61_870 +; CHECK-RV64-NEXT: j .LBB61_875 ; CHECK-RV64-NEXT: .LBB61_364: # %else1410 ; CHECK-RV64-NEXT: slli a2, a1, 29 ; CHECK-RV64-NEXT: bgez a2, .LBB61_365 -; CHECK-RV64-NEXT: j .LBB61_871 +; CHECK-RV64-NEXT: j .LBB61_876 ; CHECK-RV64-NEXT: .LBB61_365: # %else1414 ; CHECK-RV64-NEXT: slli a2, a1, 28 ; CHECK-RV64-NEXT: bgez a2, .LBB61_366 -; CHECK-RV64-NEXT: j .LBB61_872 +; CHECK-RV64-NEXT: j .LBB61_877 ; CHECK-RV64-NEXT: .LBB61_366: # %else1418 ; CHECK-RV64-NEXT: slli a2, a1, 27 ; CHECK-RV64-NEXT: bgez a2, .LBB61_367 -; CHECK-RV64-NEXT: j .LBB61_873 +; CHECK-RV64-NEXT: j .LBB61_878 ; CHECK-RV64-NEXT: .LBB61_367: # %else1422 ; CHECK-RV64-NEXT: slli a2, a1, 26 ; CHECK-RV64-NEXT: bgez a2, .LBB61_368 -; CHECK-RV64-NEXT: j .LBB61_874 +; CHECK-RV64-NEXT: j .LBB61_879 ; CHECK-RV64-NEXT: .LBB61_368: # %else1426 ; CHECK-RV64-NEXT: slli a2, a1, 25 ; CHECK-RV64-NEXT: bgez a2, .LBB61_369 -; CHECK-RV64-NEXT: j .LBB61_875 +; CHECK-RV64-NEXT: j .LBB61_880 ; CHECK-RV64-NEXT: .LBB61_369: # %else1430 ; CHECK-RV64-NEXT: slli a2, a1, 24 ; CHECK-RV64-NEXT: bgez a2, .LBB61_370 -; CHECK-RV64-NEXT: j .LBB61_876 +; CHECK-RV64-NEXT: j .LBB61_881 ; CHECK-RV64-NEXT: .LBB61_370: # %else1434 ; CHECK-RV64-NEXT: slli a2, a1, 23 ; CHECK-RV64-NEXT: bgez a2, .LBB61_371 -; CHECK-RV64-NEXT: j .LBB61_877 +; CHECK-RV64-NEXT: j .LBB61_882 ; CHECK-RV64-NEXT: .LBB61_371: # %else1438 ; CHECK-RV64-NEXT: slli a2, a1, 22 ; CHECK-RV64-NEXT: bgez a2, .LBB61_372 -; CHECK-RV64-NEXT: j .LBB61_878 +; CHECK-RV64-NEXT: j .LBB61_883 ; CHECK-RV64-NEXT: .LBB61_372: # %else1442 ; CHECK-RV64-NEXT: slli a2, a1, 21 ; CHECK-RV64-NEXT: bgez a2, .LBB61_373 -; CHECK-RV64-NEXT: j .LBB61_879 +; CHECK-RV64-NEXT: j .LBB61_884 ; CHECK-RV64-NEXT: .LBB61_373: # %else1446 ; CHECK-RV64-NEXT: slli a2, a1, 20 ; CHECK-RV64-NEXT: bgez a2, .LBB61_374 -; CHECK-RV64-NEXT: j .LBB61_880 +; CHECK-RV64-NEXT: j .LBB61_885 ; CHECK-RV64-NEXT: .LBB61_374: # %else1450 ; CHECK-RV64-NEXT: slli a2, a1, 19 ; CHECK-RV64-NEXT: bgez a2, .LBB61_375 -; CHECK-RV64-NEXT: j .LBB61_881 +; CHECK-RV64-NEXT: j .LBB61_886 ; CHECK-RV64-NEXT: .LBB61_375: # %else1454 ; CHECK-RV64-NEXT: slli a2, a1, 18 ; CHECK-RV64-NEXT: bgez a2, .LBB61_376 -; CHECK-RV64-NEXT: j .LBB61_882 +; CHECK-RV64-NEXT: j .LBB61_887 ; CHECK-RV64-NEXT: .LBB61_376: # %else1458 ; CHECK-RV64-NEXT: slli a2, a1, 17 ; CHECK-RV64-NEXT: bgez a2, .LBB61_377 -; CHECK-RV64-NEXT: j .LBB61_883 +; CHECK-RV64-NEXT: j .LBB61_888 ; CHECK-RV64-NEXT: .LBB61_377: # %else1462 ; CHECK-RV64-NEXT: slli a2, a1, 16 ; CHECK-RV64-NEXT: bgez a2, .LBB61_378 -; CHECK-RV64-NEXT: j .LBB61_884 +; CHECK-RV64-NEXT: j .LBB61_889 ; CHECK-RV64-NEXT: .LBB61_378: # %else1466 ; CHECK-RV64-NEXT: slli a2, a1, 15 ; CHECK-RV64-NEXT: bgez a2, .LBB61_379 -; CHECK-RV64-NEXT: j .LBB61_885 +; CHECK-RV64-NEXT: j .LBB61_890 ; CHECK-RV64-NEXT: .LBB61_379: # %else1470 ; CHECK-RV64-NEXT: slli a2, a1, 14 ; CHECK-RV64-NEXT: bgez a2, .LBB61_380 -; CHECK-RV64-NEXT: j .LBB61_886 +; CHECK-RV64-NEXT: j .LBB61_891 ; CHECK-RV64-NEXT: .LBB61_380: # %else1474 ; CHECK-RV64-NEXT: slli a2, a1, 13 ; CHECK-RV64-NEXT: bgez a2, .LBB61_381 -; CHECK-RV64-NEXT: j .LBB61_887 +; CHECK-RV64-NEXT: j .LBB61_892 ; CHECK-RV64-NEXT: .LBB61_381: # %else1478 ; CHECK-RV64-NEXT: slli a2, a1, 12 ; CHECK-RV64-NEXT: bgez a2, .LBB61_382 -; CHECK-RV64-NEXT: j .LBB61_888 +; CHECK-RV64-NEXT: j .LBB61_893 ; CHECK-RV64-NEXT: .LBB61_382: # %else1482 ; CHECK-RV64-NEXT: slli a2, a1, 11 ; CHECK-RV64-NEXT: bgez a2, .LBB61_383 -; CHECK-RV64-NEXT: j .LBB61_889 +; CHECK-RV64-NEXT: j .LBB61_894 ; CHECK-RV64-NEXT: .LBB61_383: # %else1486 ; CHECK-RV64-NEXT: slli a2, a1, 10 ; CHECK-RV64-NEXT: bgez a2, .LBB61_384 -; CHECK-RV64-NEXT: j .LBB61_890 +; CHECK-RV64-NEXT: j .LBB61_895 ; CHECK-RV64-NEXT: .LBB61_384: # %else1490 ; CHECK-RV64-NEXT: slli a2, a1, 9 ; CHECK-RV64-NEXT: bgez a2, .LBB61_385 -; CHECK-RV64-NEXT: j .LBB61_891 +; CHECK-RV64-NEXT: j .LBB61_896 ; CHECK-RV64-NEXT: .LBB61_385: # %else1494 ; CHECK-RV64-NEXT: slli a2, a1, 8 ; CHECK-RV64-NEXT: bgez a2, .LBB61_386 -; CHECK-RV64-NEXT: j .LBB61_892 +; CHECK-RV64-NEXT: j .LBB61_897 ; CHECK-RV64-NEXT: .LBB61_386: # %else1498 ; CHECK-RV64-NEXT: slli a2, a1, 7 ; CHECK-RV64-NEXT: bgez a2, .LBB61_387 -; CHECK-RV64-NEXT: j .LBB61_893 +; CHECK-RV64-NEXT: j .LBB61_898 ; CHECK-RV64-NEXT: .LBB61_387: # %else1502 ; CHECK-RV64-NEXT: slli a2, a1, 6 ; CHECK-RV64-NEXT: bgez a2, .LBB61_388 -; CHECK-RV64-NEXT: j .LBB61_894 +; CHECK-RV64-NEXT: j .LBB61_899 ; CHECK-RV64-NEXT: .LBB61_388: # %else1506 ; CHECK-RV64-NEXT: slli a2, a1, 5 ; CHECK-RV64-NEXT: bgez a2, .LBB61_389 -; CHECK-RV64-NEXT: j .LBB61_895 +; CHECK-RV64-NEXT: j .LBB61_900 ; CHECK-RV64-NEXT: .LBB61_389: # %else1510 ; CHECK-RV64-NEXT: slli a2, a1, 4 ; CHECK-RV64-NEXT: bgez a2, .LBB61_390 -; CHECK-RV64-NEXT: j .LBB61_896 +; CHECK-RV64-NEXT: j .LBB61_901 ; CHECK-RV64-NEXT: .LBB61_390: # %else1514 ; CHECK-RV64-NEXT: slli a2, a1, 3 ; CHECK-RV64-NEXT: bgez a2, .LBB61_391 -; CHECK-RV64-NEXT: j .LBB61_897 +; CHECK-RV64-NEXT: j .LBB61_902 ; CHECK-RV64-NEXT: .LBB61_391: # %else1518 ; CHECK-RV64-NEXT: slli a2, a1, 2 ; CHECK-RV64-NEXT: bgez a2, .LBB61_393 @@ -12224,251 +12224,251 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-RV64-NEXT: vmv.x.s a2, v24 ; CHECK-RV64-NEXT: bgez a1, .LBB61_396 -; CHECK-RV64-NEXT: j .LBB61_898 +; CHECK-RV64-NEXT: j .LBB61_904 ; CHECK-RV64-NEXT: .LBB61_396: # %else1530 ; CHECK-RV64-NEXT: andi a1, a2, 1 ; CHECK-RV64-NEXT: beqz a1, .LBB61_397 -; CHECK-RV64-NEXT: j .LBB61_899 +; CHECK-RV64-NEXT: j .LBB61_905 ; CHECK-RV64-NEXT: .LBB61_397: # %else1534 ; CHECK-RV64-NEXT: andi a1, a2, 2 ; CHECK-RV64-NEXT: beqz a1, .LBB61_398 -; CHECK-RV64-NEXT: j .LBB61_900 +; CHECK-RV64-NEXT: j .LBB61_906 ; CHECK-RV64-NEXT: .LBB61_398: # %else1538 ; CHECK-RV64-NEXT: andi a1, a2, 4 ; CHECK-RV64-NEXT: beqz a1, .LBB61_399 -; CHECK-RV64-NEXT: j .LBB61_901 +; CHECK-RV64-NEXT: j .LBB61_907 ; CHECK-RV64-NEXT: .LBB61_399: # %else1542 ; CHECK-RV64-NEXT: andi a1, a2, 8 ; CHECK-RV64-NEXT: beqz a1, .LBB61_400 -; CHECK-RV64-NEXT: j .LBB61_902 +; CHECK-RV64-NEXT: j .LBB61_908 ; CHECK-RV64-NEXT: .LBB61_400: # %else1546 ; CHECK-RV64-NEXT: andi a1, a2, 16 ; CHECK-RV64-NEXT: beqz a1, .LBB61_401 -; CHECK-RV64-NEXT: j .LBB61_903 +; CHECK-RV64-NEXT: j .LBB61_909 ; CHECK-RV64-NEXT: .LBB61_401: # %else1550 ; CHECK-RV64-NEXT: andi a1, a2, 32 ; CHECK-RV64-NEXT: beqz a1, .LBB61_402 -; CHECK-RV64-NEXT: j .LBB61_904 +; CHECK-RV64-NEXT: j .LBB61_910 ; CHECK-RV64-NEXT: .LBB61_402: # %else1554 ; CHECK-RV64-NEXT: andi a1, a2, 64 ; CHECK-RV64-NEXT: beqz a1, .LBB61_403 -; CHECK-RV64-NEXT: j .LBB61_905 +; CHECK-RV64-NEXT: j .LBB61_911 ; CHECK-RV64-NEXT: .LBB61_403: # %else1558 ; CHECK-RV64-NEXT: andi a1, a2, 128 ; CHECK-RV64-NEXT: beqz a1, .LBB61_404 -; CHECK-RV64-NEXT: j .LBB61_906 +; CHECK-RV64-NEXT: j .LBB61_912 ; CHECK-RV64-NEXT: .LBB61_404: # %else1562 ; CHECK-RV64-NEXT: andi a1, a2, 256 ; CHECK-RV64-NEXT: beqz a1, .LBB61_405 -; CHECK-RV64-NEXT: j .LBB61_907 +; CHECK-RV64-NEXT: j .LBB61_913 ; CHECK-RV64-NEXT: .LBB61_405: # %else1566 ; CHECK-RV64-NEXT: andi a1, a2, 512 ; CHECK-RV64-NEXT: beqz a1, .LBB61_406 -; CHECK-RV64-NEXT: j .LBB61_908 +; CHECK-RV64-NEXT: j .LBB61_914 ; CHECK-RV64-NEXT: .LBB61_406: # %else1570 ; CHECK-RV64-NEXT: andi a1, a2, 1024 ; CHECK-RV64-NEXT: beqz a1, .LBB61_407 -; CHECK-RV64-NEXT: j .LBB61_909 +; CHECK-RV64-NEXT: j .LBB61_915 ; CHECK-RV64-NEXT: .LBB61_407: # %else1574 ; CHECK-RV64-NEXT: slli a1, a2, 52 ; CHECK-RV64-NEXT: bgez a1, .LBB61_408 -; CHECK-RV64-NEXT: j .LBB61_910 +; CHECK-RV64-NEXT: j .LBB61_916 ; CHECK-RV64-NEXT: .LBB61_408: # %else1578 ; CHECK-RV64-NEXT: slli a1, a2, 51 ; CHECK-RV64-NEXT: bgez a1, .LBB61_409 -; CHECK-RV64-NEXT: j .LBB61_911 +; CHECK-RV64-NEXT: j .LBB61_917 ; CHECK-RV64-NEXT: .LBB61_409: # %else1582 ; CHECK-RV64-NEXT: slli a1, a2, 50 ; CHECK-RV64-NEXT: bgez a1, .LBB61_410 -; CHECK-RV64-NEXT: j .LBB61_912 +; CHECK-RV64-NEXT: j .LBB61_918 ; CHECK-RV64-NEXT: .LBB61_410: # %else1586 ; CHECK-RV64-NEXT: slli a1, a2, 49 ; CHECK-RV64-NEXT: bgez a1, .LBB61_411 -; CHECK-RV64-NEXT: j .LBB61_913 +; CHECK-RV64-NEXT: j .LBB61_919 ; CHECK-RV64-NEXT: .LBB61_411: # %else1590 ; CHECK-RV64-NEXT: slli a1, a2, 48 ; CHECK-RV64-NEXT: bgez a1, .LBB61_412 -; CHECK-RV64-NEXT: j .LBB61_914 +; CHECK-RV64-NEXT: j .LBB61_920 ; CHECK-RV64-NEXT: .LBB61_412: # %else1594 ; CHECK-RV64-NEXT: slli a1, a2, 47 ; CHECK-RV64-NEXT: bgez a1, .LBB61_413 -; CHECK-RV64-NEXT: j .LBB61_915 +; CHECK-RV64-NEXT: j .LBB61_921 ; CHECK-RV64-NEXT: .LBB61_413: # %else1598 ; CHECK-RV64-NEXT: slli a1, a2, 46 ; CHECK-RV64-NEXT: bgez a1, .LBB61_414 -; CHECK-RV64-NEXT: j .LBB61_916 +; CHECK-RV64-NEXT: j .LBB61_922 ; CHECK-RV64-NEXT: .LBB61_414: # %else1602 ; CHECK-RV64-NEXT: slli a1, a2, 45 ; CHECK-RV64-NEXT: bgez a1, .LBB61_415 -; CHECK-RV64-NEXT: j .LBB61_917 +; CHECK-RV64-NEXT: j .LBB61_923 ; CHECK-RV64-NEXT: .LBB61_415: # %else1606 ; CHECK-RV64-NEXT: slli a1, a2, 44 ; CHECK-RV64-NEXT: bgez a1, .LBB61_416 -; CHECK-RV64-NEXT: j .LBB61_918 +; CHECK-RV64-NEXT: j .LBB61_924 ; CHECK-RV64-NEXT: .LBB61_416: # %else1610 ; CHECK-RV64-NEXT: slli a1, a2, 43 ; CHECK-RV64-NEXT: bgez a1, .LBB61_417 -; CHECK-RV64-NEXT: j .LBB61_919 +; CHECK-RV64-NEXT: j .LBB61_925 ; CHECK-RV64-NEXT: .LBB61_417: # %else1614 ; CHECK-RV64-NEXT: slli a1, a2, 42 ; CHECK-RV64-NEXT: bgez a1, .LBB61_418 -; CHECK-RV64-NEXT: j .LBB61_920 +; CHECK-RV64-NEXT: j .LBB61_926 ; CHECK-RV64-NEXT: .LBB61_418: # %else1618 ; CHECK-RV64-NEXT: slli a1, a2, 41 ; CHECK-RV64-NEXT: bgez a1, .LBB61_419 -; CHECK-RV64-NEXT: j .LBB61_921 +; CHECK-RV64-NEXT: j .LBB61_927 ; CHECK-RV64-NEXT: .LBB61_419: # %else1622 ; CHECK-RV64-NEXT: slli a1, a2, 40 ; CHECK-RV64-NEXT: bgez a1, .LBB61_420 -; CHECK-RV64-NEXT: j .LBB61_922 +; CHECK-RV64-NEXT: j .LBB61_928 ; CHECK-RV64-NEXT: .LBB61_420: # %else1626 ; CHECK-RV64-NEXT: slli a1, a2, 39 ; CHECK-RV64-NEXT: bgez a1, .LBB61_421 -; CHECK-RV64-NEXT: j .LBB61_923 +; CHECK-RV64-NEXT: j .LBB61_929 ; CHECK-RV64-NEXT: .LBB61_421: # %else1630 ; CHECK-RV64-NEXT: slli a1, a2, 38 ; CHECK-RV64-NEXT: bgez a1, .LBB61_422 -; CHECK-RV64-NEXT: j .LBB61_924 +; CHECK-RV64-NEXT: j .LBB61_930 ; CHECK-RV64-NEXT: .LBB61_422: # %else1634 ; CHECK-RV64-NEXT: slli a1, a2, 37 ; CHECK-RV64-NEXT: bgez a1, .LBB61_423 -; CHECK-RV64-NEXT: j .LBB61_925 +; CHECK-RV64-NEXT: j .LBB61_931 ; CHECK-RV64-NEXT: .LBB61_423: # %else1638 ; CHECK-RV64-NEXT: slli a1, a2, 36 ; CHECK-RV64-NEXT: bgez a1, .LBB61_424 -; CHECK-RV64-NEXT: j .LBB61_926 +; CHECK-RV64-NEXT: j .LBB61_932 ; CHECK-RV64-NEXT: .LBB61_424: # %else1642 ; CHECK-RV64-NEXT: slli a1, a2, 35 ; CHECK-RV64-NEXT: bgez a1, .LBB61_425 -; CHECK-RV64-NEXT: j .LBB61_927 +; CHECK-RV64-NEXT: j .LBB61_933 ; CHECK-RV64-NEXT: .LBB61_425: # %else1646 ; CHECK-RV64-NEXT: slli a1, a2, 34 ; CHECK-RV64-NEXT: bgez a1, .LBB61_426 -; CHECK-RV64-NEXT: j .LBB61_928 +; CHECK-RV64-NEXT: j .LBB61_934 ; CHECK-RV64-NEXT: .LBB61_426: # %else1650 ; CHECK-RV64-NEXT: slli a1, a2, 33 ; CHECK-RV64-NEXT: bgez a1, .LBB61_427 -; CHECK-RV64-NEXT: j .LBB61_929 +; CHECK-RV64-NEXT: j .LBB61_935 ; CHECK-RV64-NEXT: .LBB61_427: # %else1654 ; CHECK-RV64-NEXT: slli a1, a2, 32 ; CHECK-RV64-NEXT: bgez a1, .LBB61_428 -; CHECK-RV64-NEXT: j .LBB61_930 +; CHECK-RV64-NEXT: j .LBB61_936 ; CHECK-RV64-NEXT: .LBB61_428: # %else1658 ; CHECK-RV64-NEXT: slli a1, a2, 31 ; CHECK-RV64-NEXT: bgez a1, .LBB61_429 -; CHECK-RV64-NEXT: j .LBB61_931 +; CHECK-RV64-NEXT: j .LBB61_937 ; CHECK-RV64-NEXT: .LBB61_429: # %else1662 ; CHECK-RV64-NEXT: slli a1, a2, 30 ; CHECK-RV64-NEXT: bgez a1, .LBB61_430 -; CHECK-RV64-NEXT: j .LBB61_932 +; CHECK-RV64-NEXT: j .LBB61_938 ; CHECK-RV64-NEXT: .LBB61_430: # %else1666 ; CHECK-RV64-NEXT: slli a1, a2, 29 ; CHECK-RV64-NEXT: bgez a1, .LBB61_431 -; CHECK-RV64-NEXT: j .LBB61_933 +; CHECK-RV64-NEXT: j .LBB61_939 ; CHECK-RV64-NEXT: .LBB61_431: # %else1670 ; CHECK-RV64-NEXT: slli a1, a2, 28 ; CHECK-RV64-NEXT: bgez a1, .LBB61_432 -; CHECK-RV64-NEXT: j .LBB61_934 +; CHECK-RV64-NEXT: j .LBB61_940 ; CHECK-RV64-NEXT: .LBB61_432: # %else1674 ; CHECK-RV64-NEXT: slli a1, a2, 27 ; CHECK-RV64-NEXT: bgez a1, .LBB61_433 -; CHECK-RV64-NEXT: j .LBB61_935 +; CHECK-RV64-NEXT: j .LBB61_941 ; CHECK-RV64-NEXT: .LBB61_433: # %else1678 ; CHECK-RV64-NEXT: slli a1, a2, 26 ; CHECK-RV64-NEXT: bgez a1, .LBB61_434 -; CHECK-RV64-NEXT: j .LBB61_936 +; CHECK-RV64-NEXT: j .LBB61_942 ; CHECK-RV64-NEXT: .LBB61_434: # %else1682 ; CHECK-RV64-NEXT: slli a1, a2, 25 ; CHECK-RV64-NEXT: bgez a1, .LBB61_435 -; CHECK-RV64-NEXT: j .LBB61_937 +; CHECK-RV64-NEXT: j .LBB61_943 ; CHECK-RV64-NEXT: .LBB61_435: # %else1686 ; CHECK-RV64-NEXT: slli a1, a2, 24 ; CHECK-RV64-NEXT: bgez a1, .LBB61_436 -; CHECK-RV64-NEXT: j .LBB61_938 +; CHECK-RV64-NEXT: j .LBB61_944 ; CHECK-RV64-NEXT: .LBB61_436: # %else1690 ; CHECK-RV64-NEXT: slli a1, a2, 23 ; CHECK-RV64-NEXT: bgez a1, .LBB61_437 -; CHECK-RV64-NEXT: j .LBB61_939 +; CHECK-RV64-NEXT: j .LBB61_945 ; CHECK-RV64-NEXT: .LBB61_437: # %else1694 ; CHECK-RV64-NEXT: slli a1, a2, 22 ; CHECK-RV64-NEXT: bgez a1, .LBB61_438 -; CHECK-RV64-NEXT: j .LBB61_940 +; CHECK-RV64-NEXT: j .LBB61_946 ; CHECK-RV64-NEXT: .LBB61_438: # %else1698 ; CHECK-RV64-NEXT: slli a1, a2, 21 ; CHECK-RV64-NEXT: bgez a1, .LBB61_439 -; CHECK-RV64-NEXT: j .LBB61_941 +; CHECK-RV64-NEXT: j .LBB61_947 ; CHECK-RV64-NEXT: .LBB61_439: # %else1702 ; CHECK-RV64-NEXT: slli a1, a2, 20 ; CHECK-RV64-NEXT: bgez a1, .LBB61_440 -; CHECK-RV64-NEXT: j .LBB61_942 +; CHECK-RV64-NEXT: j .LBB61_948 ; CHECK-RV64-NEXT: .LBB61_440: # %else1706 ; CHECK-RV64-NEXT: slli a1, a2, 19 ; CHECK-RV64-NEXT: bgez a1, .LBB61_441 -; CHECK-RV64-NEXT: j .LBB61_943 +; CHECK-RV64-NEXT: j .LBB61_949 ; CHECK-RV64-NEXT: .LBB61_441: # %else1710 ; CHECK-RV64-NEXT: slli a1, a2, 18 ; CHECK-RV64-NEXT: bgez a1, .LBB61_442 -; CHECK-RV64-NEXT: j .LBB61_944 +; CHECK-RV64-NEXT: j .LBB61_950 ; CHECK-RV64-NEXT: .LBB61_442: # %else1714 ; CHECK-RV64-NEXT: slli a1, a2, 17 ; CHECK-RV64-NEXT: bgez a1, .LBB61_443 -; CHECK-RV64-NEXT: j .LBB61_945 +; CHECK-RV64-NEXT: j .LBB61_951 ; CHECK-RV64-NEXT: .LBB61_443: # %else1718 ; CHECK-RV64-NEXT: slli a1, a2, 16 ; CHECK-RV64-NEXT: bgez a1, .LBB61_444 -; CHECK-RV64-NEXT: j .LBB61_946 +; CHECK-RV64-NEXT: j .LBB61_952 ; CHECK-RV64-NEXT: .LBB61_444: # %else1722 ; CHECK-RV64-NEXT: slli a1, a2, 15 ; CHECK-RV64-NEXT: bgez a1, .LBB61_445 -; CHECK-RV64-NEXT: j .LBB61_947 +; CHECK-RV64-NEXT: j .LBB61_953 ; CHECK-RV64-NEXT: .LBB61_445: # %else1726 ; CHECK-RV64-NEXT: slli a1, a2, 14 ; CHECK-RV64-NEXT: bgez a1, .LBB61_446 -; CHECK-RV64-NEXT: j .LBB61_948 +; CHECK-RV64-NEXT: j .LBB61_954 ; CHECK-RV64-NEXT: .LBB61_446: # %else1730 ; CHECK-RV64-NEXT: slli a1, a2, 13 ; CHECK-RV64-NEXT: bgez a1, .LBB61_447 -; CHECK-RV64-NEXT: j .LBB61_949 +; CHECK-RV64-NEXT: j .LBB61_955 ; CHECK-RV64-NEXT: .LBB61_447: # %else1734 ; CHECK-RV64-NEXT: slli a1, a2, 12 ; CHECK-RV64-NEXT: bgez a1, .LBB61_448 -; CHECK-RV64-NEXT: j .LBB61_950 +; CHECK-RV64-NEXT: j .LBB61_956 ; CHECK-RV64-NEXT: .LBB61_448: # %else1738 ; CHECK-RV64-NEXT: slli a1, a2, 11 ; CHECK-RV64-NEXT: bgez a1, .LBB61_449 -; CHECK-RV64-NEXT: j .LBB61_951 +; CHECK-RV64-NEXT: j .LBB61_957 ; CHECK-RV64-NEXT: .LBB61_449: # %else1742 ; CHECK-RV64-NEXT: slli a1, a2, 10 ; CHECK-RV64-NEXT: bgez a1, .LBB61_450 -; CHECK-RV64-NEXT: j .LBB61_952 +; CHECK-RV64-NEXT: j .LBB61_958 ; CHECK-RV64-NEXT: .LBB61_450: # %else1746 ; CHECK-RV64-NEXT: slli a1, a2, 9 ; CHECK-RV64-NEXT: bgez a1, .LBB61_451 -; CHECK-RV64-NEXT: j .LBB61_953 +; CHECK-RV64-NEXT: j .LBB61_959 ; CHECK-RV64-NEXT: .LBB61_451: # %else1750 ; CHECK-RV64-NEXT: slli a1, a2, 8 ; CHECK-RV64-NEXT: bgez a1, .LBB61_452 -; CHECK-RV64-NEXT: j .LBB61_954 +; CHECK-RV64-NEXT: j .LBB61_960 ; CHECK-RV64-NEXT: .LBB61_452: # %else1754 ; CHECK-RV64-NEXT: slli a1, a2, 7 ; CHECK-RV64-NEXT: bgez a1, .LBB61_453 -; CHECK-RV64-NEXT: j .LBB61_955 +; CHECK-RV64-NEXT: j .LBB61_961 ; CHECK-RV64-NEXT: .LBB61_453: # %else1758 ; CHECK-RV64-NEXT: slli a1, a2, 6 ; CHECK-RV64-NEXT: bgez a1, .LBB61_454 -; CHECK-RV64-NEXT: j .LBB61_956 +; CHECK-RV64-NEXT: j .LBB61_962 ; CHECK-RV64-NEXT: .LBB61_454: # %else1762 ; CHECK-RV64-NEXT: slli a1, a2, 5 ; CHECK-RV64-NEXT: bgez a1, .LBB61_455 -; CHECK-RV64-NEXT: j .LBB61_957 +; CHECK-RV64-NEXT: j .LBB61_963 ; CHECK-RV64-NEXT: .LBB61_455: # %else1766 ; CHECK-RV64-NEXT: slli a1, a2, 4 ; CHECK-RV64-NEXT: bgez a1, .LBB61_456 -; CHECK-RV64-NEXT: j .LBB61_958 +; CHECK-RV64-NEXT: j .LBB61_964 ; CHECK-RV64-NEXT: .LBB61_456: # %else1770 ; CHECK-RV64-NEXT: slli a1, a2, 3 ; CHECK-RV64-NEXT: bgez a1, .LBB61_457 -; CHECK-RV64-NEXT: j .LBB61_959 +; CHECK-RV64-NEXT: j .LBB61_965 ; CHECK-RV64-NEXT: .LBB61_457: # %else1774 ; CHECK-RV64-NEXT: slli a1, a2, 2 ; CHECK-RV64-NEXT: bgez a1, .LBB61_459 @@ -12499,262 +12499,262 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-RV64-NEXT: vmv.x.s a1, v24 ; CHECK-RV64-NEXT: bgez a2, .LBB61_462 -; CHECK-RV64-NEXT: j .LBB61_960 +; CHECK-RV64-NEXT: j .LBB61_967 ; CHECK-RV64-NEXT: .LBB61_462: # %else1786 ; CHECK-RV64-NEXT: andi a2, a1, 1 ; CHECK-RV64-NEXT: beqz a2, .LBB61_463 -; CHECK-RV64-NEXT: j .LBB61_961 +; CHECK-RV64-NEXT: j .LBB61_968 ; CHECK-RV64-NEXT: .LBB61_463: # %else1790 ; CHECK-RV64-NEXT: andi a2, a1, 2 ; CHECK-RV64-NEXT: beqz a2, .LBB61_464 -; CHECK-RV64-NEXT: j .LBB61_962 +; CHECK-RV64-NEXT: j .LBB61_969 ; CHECK-RV64-NEXT: .LBB61_464: # %else1794 ; CHECK-RV64-NEXT: andi a2, a1, 4 ; CHECK-RV64-NEXT: beqz a2, .LBB61_465 -; CHECK-RV64-NEXT: j .LBB61_963 +; CHECK-RV64-NEXT: j .LBB61_970 ; CHECK-RV64-NEXT: .LBB61_465: # %else1798 ; CHECK-RV64-NEXT: andi a2, a1, 8 ; CHECK-RV64-NEXT: beqz a2, .LBB61_466 -; CHECK-RV64-NEXT: j .LBB61_964 +; CHECK-RV64-NEXT: j .LBB61_971 ; CHECK-RV64-NEXT: .LBB61_466: # %else1802 ; CHECK-RV64-NEXT: andi a2, a1, 16 ; CHECK-RV64-NEXT: beqz a2, .LBB61_467 -; CHECK-RV64-NEXT: j .LBB61_965 +; CHECK-RV64-NEXT: j .LBB61_972 ; CHECK-RV64-NEXT: .LBB61_467: # %else1806 ; CHECK-RV64-NEXT: andi a2, a1, 32 ; CHECK-RV64-NEXT: beqz a2, .LBB61_468 -; CHECK-RV64-NEXT: j .LBB61_966 +; CHECK-RV64-NEXT: j .LBB61_973 ; CHECK-RV64-NEXT: .LBB61_468: # %else1810 ; CHECK-RV64-NEXT: andi a2, a1, 64 ; CHECK-RV64-NEXT: beqz a2, .LBB61_469 -; CHECK-RV64-NEXT: j .LBB61_967 +; CHECK-RV64-NEXT: j .LBB61_974 ; CHECK-RV64-NEXT: .LBB61_469: # %else1814 ; CHECK-RV64-NEXT: andi a2, a1, 128 ; CHECK-RV64-NEXT: beqz a2, .LBB61_470 -; CHECK-RV64-NEXT: j .LBB61_968 +; CHECK-RV64-NEXT: j .LBB61_975 ; CHECK-RV64-NEXT: .LBB61_470: # %else1818 ; CHECK-RV64-NEXT: andi a2, a1, 256 ; CHECK-RV64-NEXT: beqz a2, .LBB61_471 -; CHECK-RV64-NEXT: j .LBB61_969 +; CHECK-RV64-NEXT: j .LBB61_976 ; CHECK-RV64-NEXT: .LBB61_471: # %else1822 ; CHECK-RV64-NEXT: andi a2, a1, 512 ; CHECK-RV64-NEXT: beqz a2, .LBB61_472 -; CHECK-RV64-NEXT: j .LBB61_970 +; CHECK-RV64-NEXT: j .LBB61_977 ; CHECK-RV64-NEXT: .LBB61_472: # %else1826 ; CHECK-RV64-NEXT: andi a2, a1, 1024 ; CHECK-RV64-NEXT: beqz a2, .LBB61_473 -; CHECK-RV64-NEXT: j .LBB61_971 +; CHECK-RV64-NEXT: j .LBB61_978 ; CHECK-RV64-NEXT: .LBB61_473: # %else1830 ; CHECK-RV64-NEXT: slli a2, a1, 52 ; CHECK-RV64-NEXT: bgez a2, .LBB61_474 -; CHECK-RV64-NEXT: j .LBB61_972 +; CHECK-RV64-NEXT: j .LBB61_979 ; CHECK-RV64-NEXT: .LBB61_474: # %else1834 ; CHECK-RV64-NEXT: slli a2, a1, 51 ; CHECK-RV64-NEXT: bgez a2, .LBB61_475 -; CHECK-RV64-NEXT: j .LBB61_973 +; CHECK-RV64-NEXT: j .LBB61_980 ; CHECK-RV64-NEXT: .LBB61_475: # %else1838 ; CHECK-RV64-NEXT: slli a2, a1, 50 ; CHECK-RV64-NEXT: bgez a2, .LBB61_476 -; CHECK-RV64-NEXT: j .LBB61_974 +; CHECK-RV64-NEXT: j .LBB61_981 ; CHECK-RV64-NEXT: .LBB61_476: # %else1842 ; CHECK-RV64-NEXT: slli a2, a1, 49 ; CHECK-RV64-NEXT: bgez a2, .LBB61_477 -; CHECK-RV64-NEXT: j .LBB61_975 +; CHECK-RV64-NEXT: j .LBB61_982 ; CHECK-RV64-NEXT: .LBB61_477: # %else1846 ; CHECK-RV64-NEXT: slli a2, a1, 48 ; CHECK-RV64-NEXT: bgez a2, .LBB61_478 -; CHECK-RV64-NEXT: j .LBB61_976 +; CHECK-RV64-NEXT: j .LBB61_983 ; CHECK-RV64-NEXT: .LBB61_478: # %else1850 ; CHECK-RV64-NEXT: slli a2, a1, 47 ; CHECK-RV64-NEXT: bgez a2, .LBB61_479 -; CHECK-RV64-NEXT: j .LBB61_977 +; CHECK-RV64-NEXT: j .LBB61_984 ; CHECK-RV64-NEXT: .LBB61_479: # %else1854 ; CHECK-RV64-NEXT: slli a2, a1, 46 ; CHECK-RV64-NEXT: bgez a2, .LBB61_480 -; CHECK-RV64-NEXT: j .LBB61_978 +; CHECK-RV64-NEXT: j .LBB61_985 ; CHECK-RV64-NEXT: .LBB61_480: # %else1858 ; CHECK-RV64-NEXT: slli a2, a1, 45 ; CHECK-RV64-NEXT: bgez a2, .LBB61_481 -; CHECK-RV64-NEXT: j .LBB61_979 +; CHECK-RV64-NEXT: j .LBB61_986 ; CHECK-RV64-NEXT: .LBB61_481: # %else1862 ; CHECK-RV64-NEXT: slli a2, a1, 44 ; CHECK-RV64-NEXT: bgez a2, .LBB61_482 -; CHECK-RV64-NEXT: j .LBB61_980 +; CHECK-RV64-NEXT: j .LBB61_987 ; CHECK-RV64-NEXT: .LBB61_482: # %else1866 ; CHECK-RV64-NEXT: slli a2, a1, 43 ; CHECK-RV64-NEXT: bgez a2, .LBB61_483 -; CHECK-RV64-NEXT: j .LBB61_981 +; CHECK-RV64-NEXT: j .LBB61_988 ; CHECK-RV64-NEXT: .LBB61_483: # %else1870 ; CHECK-RV64-NEXT: slli a2, a1, 42 ; CHECK-RV64-NEXT: bgez a2, .LBB61_484 -; CHECK-RV64-NEXT: j .LBB61_982 +; CHECK-RV64-NEXT: j .LBB61_989 ; CHECK-RV64-NEXT: .LBB61_484: # %else1874 ; CHECK-RV64-NEXT: slli a2, a1, 41 ; CHECK-RV64-NEXT: bgez a2, .LBB61_485 -; CHECK-RV64-NEXT: j .LBB61_983 +; CHECK-RV64-NEXT: j .LBB61_990 ; CHECK-RV64-NEXT: .LBB61_485: # %else1878 ; CHECK-RV64-NEXT: slli a2, a1, 40 ; CHECK-RV64-NEXT: bgez a2, .LBB61_486 -; CHECK-RV64-NEXT: j .LBB61_984 +; CHECK-RV64-NEXT: j .LBB61_991 ; CHECK-RV64-NEXT: .LBB61_486: # %else1882 ; CHECK-RV64-NEXT: slli a2, a1, 39 ; CHECK-RV64-NEXT: bgez a2, .LBB61_487 -; CHECK-RV64-NEXT: j .LBB61_985 +; CHECK-RV64-NEXT: j .LBB61_992 ; CHECK-RV64-NEXT: .LBB61_487: # %else1886 ; CHECK-RV64-NEXT: slli a2, a1, 38 ; CHECK-RV64-NEXT: bgez a2, .LBB61_488 -; CHECK-RV64-NEXT: j .LBB61_986 +; CHECK-RV64-NEXT: j .LBB61_993 ; CHECK-RV64-NEXT: .LBB61_488: # %else1890 ; CHECK-RV64-NEXT: slli a2, a1, 37 ; CHECK-RV64-NEXT: bgez a2, .LBB61_489 -; CHECK-RV64-NEXT: j .LBB61_987 +; CHECK-RV64-NEXT: j .LBB61_994 ; CHECK-RV64-NEXT: .LBB61_489: # %else1894 ; CHECK-RV64-NEXT: slli a2, a1, 36 ; CHECK-RV64-NEXT: bgez a2, .LBB61_490 -; CHECK-RV64-NEXT: j .LBB61_988 +; CHECK-RV64-NEXT: j .LBB61_995 ; CHECK-RV64-NEXT: .LBB61_490: # %else1898 ; CHECK-RV64-NEXT: slli a2, a1, 35 ; CHECK-RV64-NEXT: bgez a2, .LBB61_491 -; CHECK-RV64-NEXT: j .LBB61_989 +; CHECK-RV64-NEXT: j .LBB61_996 ; CHECK-RV64-NEXT: .LBB61_491: # %else1902 ; CHECK-RV64-NEXT: slli a2, a1, 34 ; CHECK-RV64-NEXT: bgez a2, .LBB61_492 -; CHECK-RV64-NEXT: j .LBB61_990 +; CHECK-RV64-NEXT: j .LBB61_997 ; CHECK-RV64-NEXT: .LBB61_492: # %else1906 ; CHECK-RV64-NEXT: slli a2, a1, 33 ; CHECK-RV64-NEXT: bgez a2, .LBB61_493 -; CHECK-RV64-NEXT: j .LBB61_991 +; CHECK-RV64-NEXT: j .LBB61_998 ; CHECK-RV64-NEXT: .LBB61_493: # %else1910 ; CHECK-RV64-NEXT: slli a2, a1, 32 ; CHECK-RV64-NEXT: bgez a2, .LBB61_494 -; CHECK-RV64-NEXT: j .LBB61_992 +; CHECK-RV64-NEXT: j .LBB61_999 ; CHECK-RV64-NEXT: .LBB61_494: # %else1914 ; CHECK-RV64-NEXT: slli a2, a1, 31 ; CHECK-RV64-NEXT: bgez a2, .LBB61_495 -; CHECK-RV64-NEXT: j .LBB61_993 +; CHECK-RV64-NEXT: j .LBB61_1000 ; CHECK-RV64-NEXT: .LBB61_495: # %else1918 ; CHECK-RV64-NEXT: slli a2, a1, 30 ; CHECK-RV64-NEXT: bgez a2, .LBB61_496 -; CHECK-RV64-NEXT: j .LBB61_994 +; CHECK-RV64-NEXT: j .LBB61_1001 ; CHECK-RV64-NEXT: .LBB61_496: # %else1922 ; CHECK-RV64-NEXT: slli a2, a1, 29 ; CHECK-RV64-NEXT: bgez a2, .LBB61_497 -; CHECK-RV64-NEXT: j .LBB61_995 +; CHECK-RV64-NEXT: j .LBB61_1002 ; CHECK-RV64-NEXT: .LBB61_497: # %else1926 ; CHECK-RV64-NEXT: slli a2, a1, 28 ; CHECK-RV64-NEXT: bgez a2, .LBB61_498 -; CHECK-RV64-NEXT: j .LBB61_996 +; CHECK-RV64-NEXT: j .LBB61_1003 ; CHECK-RV64-NEXT: .LBB61_498: # %else1930 ; CHECK-RV64-NEXT: slli a2, a1, 27 ; CHECK-RV64-NEXT: bgez a2, .LBB61_499 -; CHECK-RV64-NEXT: j .LBB61_997 +; CHECK-RV64-NEXT: j .LBB61_1004 ; CHECK-RV64-NEXT: .LBB61_499: # %else1934 ; CHECK-RV64-NEXT: slli a2, a1, 26 ; CHECK-RV64-NEXT: bgez a2, .LBB61_500 -; CHECK-RV64-NEXT: j .LBB61_998 +; CHECK-RV64-NEXT: j .LBB61_1005 ; CHECK-RV64-NEXT: .LBB61_500: # %else1938 ; CHECK-RV64-NEXT: slli a2, a1, 25 ; CHECK-RV64-NEXT: bgez a2, .LBB61_501 -; CHECK-RV64-NEXT: j .LBB61_999 +; CHECK-RV64-NEXT: j .LBB61_1006 ; CHECK-RV64-NEXT: .LBB61_501: # %else1942 ; CHECK-RV64-NEXT: slli a2, a1, 24 ; CHECK-RV64-NEXT: bgez a2, .LBB61_502 -; CHECK-RV64-NEXT: j .LBB61_1000 +; CHECK-RV64-NEXT: j .LBB61_1007 ; CHECK-RV64-NEXT: .LBB61_502: # %else1946 ; CHECK-RV64-NEXT: slli a2, a1, 23 ; CHECK-RV64-NEXT: bgez a2, .LBB61_503 -; CHECK-RV64-NEXT: j .LBB61_1001 +; CHECK-RV64-NEXT: j .LBB61_1008 ; CHECK-RV64-NEXT: .LBB61_503: # %else1950 ; CHECK-RV64-NEXT: slli a2, a1, 22 ; CHECK-RV64-NEXT: bgez a2, .LBB61_504 -; CHECK-RV64-NEXT: j .LBB61_1002 +; CHECK-RV64-NEXT: j .LBB61_1009 ; CHECK-RV64-NEXT: .LBB61_504: # %else1954 ; CHECK-RV64-NEXT: slli a2, a1, 21 ; CHECK-RV64-NEXT: bgez a2, .LBB61_505 -; CHECK-RV64-NEXT: j .LBB61_1003 +; CHECK-RV64-NEXT: j .LBB61_1010 ; CHECK-RV64-NEXT: .LBB61_505: # %else1958 ; CHECK-RV64-NEXT: slli a2, a1, 20 ; CHECK-RV64-NEXT: bgez a2, .LBB61_506 -; CHECK-RV64-NEXT: j .LBB61_1004 +; CHECK-RV64-NEXT: j .LBB61_1011 ; CHECK-RV64-NEXT: .LBB61_506: # %else1962 ; CHECK-RV64-NEXT: slli a2, a1, 19 ; CHECK-RV64-NEXT: bgez a2, .LBB61_507 -; CHECK-RV64-NEXT: j .LBB61_1005 +; CHECK-RV64-NEXT: j .LBB61_1012 ; CHECK-RV64-NEXT: .LBB61_507: # %else1966 ; CHECK-RV64-NEXT: slli a2, a1, 18 ; CHECK-RV64-NEXT: bgez a2, .LBB61_508 -; CHECK-RV64-NEXT: j .LBB61_1006 +; CHECK-RV64-NEXT: j .LBB61_1013 ; CHECK-RV64-NEXT: .LBB61_508: # %else1970 ; CHECK-RV64-NEXT: slli a2, a1, 17 ; CHECK-RV64-NEXT: bgez a2, .LBB61_509 -; CHECK-RV64-NEXT: j .LBB61_1007 +; CHECK-RV64-NEXT: j .LBB61_1014 ; CHECK-RV64-NEXT: .LBB61_509: # %else1974 ; CHECK-RV64-NEXT: slli a2, a1, 16 ; CHECK-RV64-NEXT: bgez a2, .LBB61_510 -; CHECK-RV64-NEXT: j .LBB61_1008 +; CHECK-RV64-NEXT: j .LBB61_1015 ; CHECK-RV64-NEXT: .LBB61_510: # %else1978 ; CHECK-RV64-NEXT: slli a2, a1, 15 ; CHECK-RV64-NEXT: bgez a2, .LBB61_511 -; CHECK-RV64-NEXT: j .LBB61_1009 +; CHECK-RV64-NEXT: j .LBB61_1016 ; CHECK-RV64-NEXT: .LBB61_511: # %else1982 ; CHECK-RV64-NEXT: slli a2, a1, 14 ; CHECK-RV64-NEXT: bgez a2, .LBB61_512 -; CHECK-RV64-NEXT: j .LBB61_1010 +; CHECK-RV64-NEXT: j .LBB61_1017 ; CHECK-RV64-NEXT: .LBB61_512: # %else1986 ; CHECK-RV64-NEXT: slli a2, a1, 13 ; CHECK-RV64-NEXT: bgez a2, .LBB61_513 -; CHECK-RV64-NEXT: j .LBB61_1011 +; CHECK-RV64-NEXT: j .LBB61_1018 ; CHECK-RV64-NEXT: .LBB61_513: # %else1990 ; CHECK-RV64-NEXT: slli a2, a1, 12 ; CHECK-RV64-NEXT: bgez a2, .LBB61_514 -; CHECK-RV64-NEXT: j .LBB61_1012 +; CHECK-RV64-NEXT: j .LBB61_1019 ; CHECK-RV64-NEXT: .LBB61_514: # %else1994 ; CHECK-RV64-NEXT: slli a2, a1, 11 ; CHECK-RV64-NEXT: bgez a2, .LBB61_515 -; CHECK-RV64-NEXT: j .LBB61_1013 +; CHECK-RV64-NEXT: j .LBB61_1020 ; CHECK-RV64-NEXT: .LBB61_515: # %else1998 ; CHECK-RV64-NEXT: slli a2, a1, 10 ; CHECK-RV64-NEXT: bgez a2, .LBB61_516 -; CHECK-RV64-NEXT: j .LBB61_1014 +; CHECK-RV64-NEXT: j .LBB61_1021 ; CHECK-RV64-NEXT: .LBB61_516: # %else2002 ; CHECK-RV64-NEXT: slli a2, a1, 9 ; CHECK-RV64-NEXT: bgez a2, .LBB61_517 -; CHECK-RV64-NEXT: j .LBB61_1015 +; CHECK-RV64-NEXT: j .LBB61_1022 ; CHECK-RV64-NEXT: .LBB61_517: # %else2006 ; CHECK-RV64-NEXT: slli a2, a1, 8 ; CHECK-RV64-NEXT: bgez a2, .LBB61_518 -; CHECK-RV64-NEXT: j .LBB61_1016 +; CHECK-RV64-NEXT: j .LBB61_1023 ; CHECK-RV64-NEXT: .LBB61_518: # %else2010 ; CHECK-RV64-NEXT: slli a2, a1, 7 ; CHECK-RV64-NEXT: bgez a2, .LBB61_519 -; CHECK-RV64-NEXT: j .LBB61_1017 +; CHECK-RV64-NEXT: j .LBB61_1024 ; CHECK-RV64-NEXT: .LBB61_519: # %else2014 ; CHECK-RV64-NEXT: slli a2, a1, 6 ; CHECK-RV64-NEXT: bgez a2, .LBB61_520 -; CHECK-RV64-NEXT: j .LBB61_1018 +; CHECK-RV64-NEXT: j .LBB61_1025 ; CHECK-RV64-NEXT: .LBB61_520: # %else2018 ; CHECK-RV64-NEXT: slli a2, a1, 5 ; CHECK-RV64-NEXT: bgez a2, .LBB61_521 -; CHECK-RV64-NEXT: j .LBB61_1019 +; CHECK-RV64-NEXT: j .LBB61_1026 ; CHECK-RV64-NEXT: .LBB61_521: # %else2022 ; CHECK-RV64-NEXT: slli a2, a1, 4 ; CHECK-RV64-NEXT: bgez a2, .LBB61_522 -; CHECK-RV64-NEXT: j .LBB61_1020 +; CHECK-RV64-NEXT: j .LBB61_1027 ; CHECK-RV64-NEXT: .LBB61_522: # %else2026 ; CHECK-RV64-NEXT: slli a2, a1, 3 ; CHECK-RV64-NEXT: bgez a2, .LBB61_523 -; CHECK-RV64-NEXT: j .LBB61_1021 +; CHECK-RV64-NEXT: j .LBB61_1028 ; CHECK-RV64-NEXT: .LBB61_523: # %else2030 ; CHECK-RV64-NEXT: slli a2, a1, 2 ; CHECK-RV64-NEXT: bgez a2, .LBB61_524 -; CHECK-RV64-NEXT: j .LBB61_1022 +; CHECK-RV64-NEXT: j .LBB61_1029 ; CHECK-RV64-NEXT: .LBB61_524: # %else2034 ; CHECK-RV64-NEXT: slli a2, a1, 1 ; CHECK-RV64-NEXT: bgez a2, .LBB61_525 -; CHECK-RV64-NEXT: j .LBB61_1023 +; CHECK-RV64-NEXT: j .LBB61_1030 ; CHECK-RV64-NEXT: .LBB61_525: # %else2038 ; CHECK-RV64-NEXT: bgez a1, .LBB61_526 -; CHECK-RV64-NEXT: j .LBB61_1024 +; CHECK-RV64-NEXT: j .LBB61_1031 ; CHECK-RV64-NEXT: .LBB61_526: # %else2042 ; CHECK-RV64-NEXT: ret ; CHECK-RV64-NEXT: .LBB61_527: # %cond.load @@ -13575,11 +13575,11 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv1r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 2 -; CHECK-RV64-NEXT: bgez a1, .LBB61_1025 +; CHECK-RV64-NEXT: bgez a1, .LBB61_588 ; CHECK-RV64-NEXT: j .LBB61_62 -; CHECK-RV64-NEXT: .LBB61_1025: # %cond.load237 +; CHECK-RV64-NEXT: .LBB61_588: # %cond.load237 ; CHECK-RV64-NEXT: j .LBB61_63 -; CHECK-RV64-NEXT: .LBB61_588: # %cond.load249 +; CHECK-RV64-NEXT: .LBB61_589: # %cond.load249 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vmv8r.v v16, v8 ; CHECK-RV64-NEXT: vmv.s.x v9, a2 @@ -13591,9 +13591,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv1r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: andi a2, a1, 1 -; CHECK-RV64-NEXT: bnez a2, .LBB61_589 +; CHECK-RV64-NEXT: bnez a2, .LBB61_590 ; CHECK-RV64-NEXT: j .LBB61_67 -; CHECK-RV64-NEXT: .LBB61_589: # %cond.load253 +; CHECK-RV64-NEXT: .LBB61_590: # %cond.load253 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -13606,9 +13606,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: andi a2, a1, 2 -; CHECK-RV64-NEXT: bnez a2, .LBB61_590 +; CHECK-RV64-NEXT: bnez a2, .LBB61_591 ; CHECK-RV64-NEXT: j .LBB61_68 -; CHECK-RV64-NEXT: .LBB61_590: # %cond.load257 +; CHECK-RV64-NEXT: .LBB61_591: # %cond.load257 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -13621,9 +13621,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: andi a2, a1, 4 -; CHECK-RV64-NEXT: bnez a2, .LBB61_591 +; CHECK-RV64-NEXT: bnez a2, .LBB61_592 ; CHECK-RV64-NEXT: j .LBB61_69 -; CHECK-RV64-NEXT: .LBB61_591: # %cond.load261 +; CHECK-RV64-NEXT: .LBB61_592: # %cond.load261 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -13636,9 +13636,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: andi a2, a1, 8 -; CHECK-RV64-NEXT: bnez a2, .LBB61_592 +; CHECK-RV64-NEXT: bnez a2, .LBB61_593 ; CHECK-RV64-NEXT: j .LBB61_70 -; CHECK-RV64-NEXT: .LBB61_592: # %cond.load265 +; CHECK-RV64-NEXT: .LBB61_593: # %cond.load265 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -13651,9 +13651,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: andi a2, a1, 16 -; CHECK-RV64-NEXT: bnez a2, .LBB61_593 +; CHECK-RV64-NEXT: bnez a2, .LBB61_594 ; CHECK-RV64-NEXT: j .LBB61_71 -; CHECK-RV64-NEXT: .LBB61_593: # %cond.load269 +; CHECK-RV64-NEXT: .LBB61_594: # %cond.load269 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -13666,9 +13666,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: andi a2, a1, 32 -; CHECK-RV64-NEXT: bnez a2, .LBB61_594 +; CHECK-RV64-NEXT: bnez a2, .LBB61_595 ; CHECK-RV64-NEXT: j .LBB61_72 -; CHECK-RV64-NEXT: .LBB61_594: # %cond.load273 +; CHECK-RV64-NEXT: .LBB61_595: # %cond.load273 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -13681,9 +13681,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: andi a2, a1, 64 -; CHECK-RV64-NEXT: bnez a2, .LBB61_595 +; CHECK-RV64-NEXT: bnez a2, .LBB61_596 ; CHECK-RV64-NEXT: j .LBB61_73 -; CHECK-RV64-NEXT: .LBB61_595: # %cond.load277 +; CHECK-RV64-NEXT: .LBB61_596: # %cond.load277 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -13696,9 +13696,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: andi a2, a1, 128 -; CHECK-RV64-NEXT: bnez a2, .LBB61_596 +; CHECK-RV64-NEXT: bnez a2, .LBB61_597 ; CHECK-RV64-NEXT: j .LBB61_74 -; CHECK-RV64-NEXT: .LBB61_596: # %cond.load281 +; CHECK-RV64-NEXT: .LBB61_597: # %cond.load281 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -13711,9 +13711,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: andi a2, a1, 256 -; CHECK-RV64-NEXT: bnez a2, .LBB61_597 +; CHECK-RV64-NEXT: bnez a2, .LBB61_598 ; CHECK-RV64-NEXT: j .LBB61_75 -; CHECK-RV64-NEXT: .LBB61_597: # %cond.load285 +; CHECK-RV64-NEXT: .LBB61_598: # %cond.load285 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -13726,9 +13726,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: andi a2, a1, 512 -; CHECK-RV64-NEXT: bnez a2, .LBB61_598 +; CHECK-RV64-NEXT: bnez a2, .LBB61_599 ; CHECK-RV64-NEXT: j .LBB61_76 -; CHECK-RV64-NEXT: .LBB61_598: # %cond.load289 +; CHECK-RV64-NEXT: .LBB61_599: # %cond.load289 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -13741,9 +13741,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: andi a2, a1, 1024 -; CHECK-RV64-NEXT: bnez a2, .LBB61_599 +; CHECK-RV64-NEXT: bnez a2, .LBB61_600 ; CHECK-RV64-NEXT: j .LBB61_77 -; CHECK-RV64-NEXT: .LBB61_599: # %cond.load293 +; CHECK-RV64-NEXT: .LBB61_600: # %cond.load293 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -13756,9 +13756,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 52 -; CHECK-RV64-NEXT: bltz a2, .LBB61_600 +; CHECK-RV64-NEXT: bltz a2, .LBB61_601 ; CHECK-RV64-NEXT: j .LBB61_78 -; CHECK-RV64-NEXT: .LBB61_600: # %cond.load297 +; CHECK-RV64-NEXT: .LBB61_601: # %cond.load297 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -13771,9 +13771,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 51 -; CHECK-RV64-NEXT: bltz a2, .LBB61_601 +; CHECK-RV64-NEXT: bltz a2, .LBB61_602 ; CHECK-RV64-NEXT: j .LBB61_79 -; CHECK-RV64-NEXT: .LBB61_601: # %cond.load301 +; CHECK-RV64-NEXT: .LBB61_602: # %cond.load301 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -13786,9 +13786,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 50 -; CHECK-RV64-NEXT: bltz a2, .LBB61_602 +; CHECK-RV64-NEXT: bltz a2, .LBB61_603 ; CHECK-RV64-NEXT: j .LBB61_80 -; CHECK-RV64-NEXT: .LBB61_602: # %cond.load305 +; CHECK-RV64-NEXT: .LBB61_603: # %cond.load305 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -13801,9 +13801,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 49 -; CHECK-RV64-NEXT: bltz a2, .LBB61_603 +; CHECK-RV64-NEXT: bltz a2, .LBB61_604 ; CHECK-RV64-NEXT: j .LBB61_81 -; CHECK-RV64-NEXT: .LBB61_603: # %cond.load309 +; CHECK-RV64-NEXT: .LBB61_604: # %cond.load309 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -13816,9 +13816,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 48 -; CHECK-RV64-NEXT: bltz a2, .LBB61_604 +; CHECK-RV64-NEXT: bltz a2, .LBB61_605 ; CHECK-RV64-NEXT: j .LBB61_82 -; CHECK-RV64-NEXT: .LBB61_604: # %cond.load313 +; CHECK-RV64-NEXT: .LBB61_605: # %cond.load313 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -13831,9 +13831,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 47 -; CHECK-RV64-NEXT: bltz a2, .LBB61_605 +; CHECK-RV64-NEXT: bltz a2, .LBB61_606 ; CHECK-RV64-NEXT: j .LBB61_83 -; CHECK-RV64-NEXT: .LBB61_605: # %cond.load317 +; CHECK-RV64-NEXT: .LBB61_606: # %cond.load317 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -13846,9 +13846,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 46 -; CHECK-RV64-NEXT: bltz a2, .LBB61_606 +; CHECK-RV64-NEXT: bltz a2, .LBB61_607 ; CHECK-RV64-NEXT: j .LBB61_84 -; CHECK-RV64-NEXT: .LBB61_606: # %cond.load321 +; CHECK-RV64-NEXT: .LBB61_607: # %cond.load321 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -13861,9 +13861,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 45 -; CHECK-RV64-NEXT: bltz a2, .LBB61_607 +; CHECK-RV64-NEXT: bltz a2, .LBB61_608 ; CHECK-RV64-NEXT: j .LBB61_85 -; CHECK-RV64-NEXT: .LBB61_607: # %cond.load325 +; CHECK-RV64-NEXT: .LBB61_608: # %cond.load325 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -13876,9 +13876,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 44 -; CHECK-RV64-NEXT: bltz a2, .LBB61_608 +; CHECK-RV64-NEXT: bltz a2, .LBB61_609 ; CHECK-RV64-NEXT: j .LBB61_86 -; CHECK-RV64-NEXT: .LBB61_608: # %cond.load329 +; CHECK-RV64-NEXT: .LBB61_609: # %cond.load329 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -13891,9 +13891,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 43 -; CHECK-RV64-NEXT: bltz a2, .LBB61_609 +; CHECK-RV64-NEXT: bltz a2, .LBB61_610 ; CHECK-RV64-NEXT: j .LBB61_87 -; CHECK-RV64-NEXT: .LBB61_609: # %cond.load333 +; CHECK-RV64-NEXT: .LBB61_610: # %cond.load333 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -13906,9 +13906,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 42 -; CHECK-RV64-NEXT: bltz a2, .LBB61_610 +; CHECK-RV64-NEXT: bltz a2, .LBB61_611 ; CHECK-RV64-NEXT: j .LBB61_88 -; CHECK-RV64-NEXT: .LBB61_610: # %cond.load337 +; CHECK-RV64-NEXT: .LBB61_611: # %cond.load337 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -13921,9 +13921,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 41 -; CHECK-RV64-NEXT: bltz a2, .LBB61_611 +; CHECK-RV64-NEXT: bltz a2, .LBB61_612 ; CHECK-RV64-NEXT: j .LBB61_89 -; CHECK-RV64-NEXT: .LBB61_611: # %cond.load341 +; CHECK-RV64-NEXT: .LBB61_612: # %cond.load341 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -13936,9 +13936,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 40 -; CHECK-RV64-NEXT: bltz a2, .LBB61_612 +; CHECK-RV64-NEXT: bltz a2, .LBB61_613 ; CHECK-RV64-NEXT: j .LBB61_90 -; CHECK-RV64-NEXT: .LBB61_612: # %cond.load345 +; CHECK-RV64-NEXT: .LBB61_613: # %cond.load345 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -13951,9 +13951,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 39 -; CHECK-RV64-NEXT: bltz a2, .LBB61_613 +; CHECK-RV64-NEXT: bltz a2, .LBB61_614 ; CHECK-RV64-NEXT: j .LBB61_91 -; CHECK-RV64-NEXT: .LBB61_613: # %cond.load349 +; CHECK-RV64-NEXT: .LBB61_614: # %cond.load349 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -13966,9 +13966,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 38 -; CHECK-RV64-NEXT: bltz a2, .LBB61_614 +; CHECK-RV64-NEXT: bltz a2, .LBB61_615 ; CHECK-RV64-NEXT: j .LBB61_92 -; CHECK-RV64-NEXT: .LBB61_614: # %cond.load353 +; CHECK-RV64-NEXT: .LBB61_615: # %cond.load353 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -13981,9 +13981,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 37 -; CHECK-RV64-NEXT: bltz a2, .LBB61_615 +; CHECK-RV64-NEXT: bltz a2, .LBB61_616 ; CHECK-RV64-NEXT: j .LBB61_93 -; CHECK-RV64-NEXT: .LBB61_615: # %cond.load357 +; CHECK-RV64-NEXT: .LBB61_616: # %cond.load357 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -13996,9 +13996,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 36 -; CHECK-RV64-NEXT: bltz a2, .LBB61_616 +; CHECK-RV64-NEXT: bltz a2, .LBB61_617 ; CHECK-RV64-NEXT: j .LBB61_94 -; CHECK-RV64-NEXT: .LBB61_616: # %cond.load361 +; CHECK-RV64-NEXT: .LBB61_617: # %cond.load361 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14011,9 +14011,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 35 -; CHECK-RV64-NEXT: bltz a2, .LBB61_617 +; CHECK-RV64-NEXT: bltz a2, .LBB61_618 ; CHECK-RV64-NEXT: j .LBB61_95 -; CHECK-RV64-NEXT: .LBB61_617: # %cond.load365 +; CHECK-RV64-NEXT: .LBB61_618: # %cond.load365 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14026,9 +14026,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 34 -; CHECK-RV64-NEXT: bltz a2, .LBB61_618 +; CHECK-RV64-NEXT: bltz a2, .LBB61_619 ; CHECK-RV64-NEXT: j .LBB61_96 -; CHECK-RV64-NEXT: .LBB61_618: # %cond.load369 +; CHECK-RV64-NEXT: .LBB61_619: # %cond.load369 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14041,9 +14041,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 33 -; CHECK-RV64-NEXT: bltz a2, .LBB61_619 +; CHECK-RV64-NEXT: bltz a2, .LBB61_620 ; CHECK-RV64-NEXT: j .LBB61_97 -; CHECK-RV64-NEXT: .LBB61_619: # %cond.load373 +; CHECK-RV64-NEXT: .LBB61_620: # %cond.load373 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14056,9 +14056,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 32 -; CHECK-RV64-NEXT: bltz a2, .LBB61_620 +; CHECK-RV64-NEXT: bltz a2, .LBB61_621 ; CHECK-RV64-NEXT: j .LBB61_98 -; CHECK-RV64-NEXT: .LBB61_620: # %cond.load377 +; CHECK-RV64-NEXT: .LBB61_621: # %cond.load377 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14071,9 +14071,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 31 -; CHECK-RV64-NEXT: bltz a2, .LBB61_621 +; CHECK-RV64-NEXT: bltz a2, .LBB61_622 ; CHECK-RV64-NEXT: j .LBB61_99 -; CHECK-RV64-NEXT: .LBB61_621: # %cond.load381 +; CHECK-RV64-NEXT: .LBB61_622: # %cond.load381 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14086,9 +14086,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 30 -; CHECK-RV64-NEXT: bltz a2, .LBB61_622 +; CHECK-RV64-NEXT: bltz a2, .LBB61_623 ; CHECK-RV64-NEXT: j .LBB61_100 -; CHECK-RV64-NEXT: .LBB61_622: # %cond.load385 +; CHECK-RV64-NEXT: .LBB61_623: # %cond.load385 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14101,9 +14101,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 29 -; CHECK-RV64-NEXT: bltz a2, .LBB61_623 +; CHECK-RV64-NEXT: bltz a2, .LBB61_624 ; CHECK-RV64-NEXT: j .LBB61_101 -; CHECK-RV64-NEXT: .LBB61_623: # %cond.load389 +; CHECK-RV64-NEXT: .LBB61_624: # %cond.load389 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14116,9 +14116,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 28 -; CHECK-RV64-NEXT: bltz a2, .LBB61_624 +; CHECK-RV64-NEXT: bltz a2, .LBB61_625 ; CHECK-RV64-NEXT: j .LBB61_102 -; CHECK-RV64-NEXT: .LBB61_624: # %cond.load393 +; CHECK-RV64-NEXT: .LBB61_625: # %cond.load393 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14131,9 +14131,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 27 -; CHECK-RV64-NEXT: bltz a2, .LBB61_625 +; CHECK-RV64-NEXT: bltz a2, .LBB61_626 ; CHECK-RV64-NEXT: j .LBB61_103 -; CHECK-RV64-NEXT: .LBB61_625: # %cond.load397 +; CHECK-RV64-NEXT: .LBB61_626: # %cond.load397 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14146,9 +14146,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 26 -; CHECK-RV64-NEXT: bltz a2, .LBB61_626 +; CHECK-RV64-NEXT: bltz a2, .LBB61_627 ; CHECK-RV64-NEXT: j .LBB61_104 -; CHECK-RV64-NEXT: .LBB61_626: # %cond.load401 +; CHECK-RV64-NEXT: .LBB61_627: # %cond.load401 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14161,9 +14161,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 25 -; CHECK-RV64-NEXT: bltz a2, .LBB61_627 +; CHECK-RV64-NEXT: bltz a2, .LBB61_628 ; CHECK-RV64-NEXT: j .LBB61_105 -; CHECK-RV64-NEXT: .LBB61_627: # %cond.load405 +; CHECK-RV64-NEXT: .LBB61_628: # %cond.load405 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14176,9 +14176,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 24 -; CHECK-RV64-NEXT: bltz a2, .LBB61_628 +; CHECK-RV64-NEXT: bltz a2, .LBB61_629 ; CHECK-RV64-NEXT: j .LBB61_106 -; CHECK-RV64-NEXT: .LBB61_628: # %cond.load409 +; CHECK-RV64-NEXT: .LBB61_629: # %cond.load409 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14191,9 +14191,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 23 -; CHECK-RV64-NEXT: bltz a2, .LBB61_629 +; CHECK-RV64-NEXT: bltz a2, .LBB61_630 ; CHECK-RV64-NEXT: j .LBB61_107 -; CHECK-RV64-NEXT: .LBB61_629: # %cond.load413 +; CHECK-RV64-NEXT: .LBB61_630: # %cond.load413 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14206,9 +14206,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 22 -; CHECK-RV64-NEXT: bltz a2, .LBB61_630 +; CHECK-RV64-NEXT: bltz a2, .LBB61_631 ; CHECK-RV64-NEXT: j .LBB61_108 -; CHECK-RV64-NEXT: .LBB61_630: # %cond.load417 +; CHECK-RV64-NEXT: .LBB61_631: # %cond.load417 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14221,9 +14221,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 21 -; CHECK-RV64-NEXT: bltz a2, .LBB61_631 +; CHECK-RV64-NEXT: bltz a2, .LBB61_632 ; CHECK-RV64-NEXT: j .LBB61_109 -; CHECK-RV64-NEXT: .LBB61_631: # %cond.load421 +; CHECK-RV64-NEXT: .LBB61_632: # %cond.load421 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14236,9 +14236,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 20 -; CHECK-RV64-NEXT: bltz a2, .LBB61_632 +; CHECK-RV64-NEXT: bltz a2, .LBB61_633 ; CHECK-RV64-NEXT: j .LBB61_110 -; CHECK-RV64-NEXT: .LBB61_632: # %cond.load425 +; CHECK-RV64-NEXT: .LBB61_633: # %cond.load425 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14251,9 +14251,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 19 -; CHECK-RV64-NEXT: bltz a2, .LBB61_633 +; CHECK-RV64-NEXT: bltz a2, .LBB61_634 ; CHECK-RV64-NEXT: j .LBB61_111 -; CHECK-RV64-NEXT: .LBB61_633: # %cond.load429 +; CHECK-RV64-NEXT: .LBB61_634: # %cond.load429 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14266,9 +14266,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 18 -; CHECK-RV64-NEXT: bltz a2, .LBB61_634 +; CHECK-RV64-NEXT: bltz a2, .LBB61_635 ; CHECK-RV64-NEXT: j .LBB61_112 -; CHECK-RV64-NEXT: .LBB61_634: # %cond.load433 +; CHECK-RV64-NEXT: .LBB61_635: # %cond.load433 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14281,9 +14281,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 17 -; CHECK-RV64-NEXT: bltz a2, .LBB61_635 +; CHECK-RV64-NEXT: bltz a2, .LBB61_636 ; CHECK-RV64-NEXT: j .LBB61_113 -; CHECK-RV64-NEXT: .LBB61_635: # %cond.load437 +; CHECK-RV64-NEXT: .LBB61_636: # %cond.load437 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14296,9 +14296,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 16 -; CHECK-RV64-NEXT: bltz a2, .LBB61_636 +; CHECK-RV64-NEXT: bltz a2, .LBB61_637 ; CHECK-RV64-NEXT: j .LBB61_114 -; CHECK-RV64-NEXT: .LBB61_636: # %cond.load441 +; CHECK-RV64-NEXT: .LBB61_637: # %cond.load441 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14311,9 +14311,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 15 -; CHECK-RV64-NEXT: bltz a2, .LBB61_637 +; CHECK-RV64-NEXT: bltz a2, .LBB61_638 ; CHECK-RV64-NEXT: j .LBB61_115 -; CHECK-RV64-NEXT: .LBB61_637: # %cond.load445 +; CHECK-RV64-NEXT: .LBB61_638: # %cond.load445 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14326,9 +14326,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 14 -; CHECK-RV64-NEXT: bltz a2, .LBB61_638 +; CHECK-RV64-NEXT: bltz a2, .LBB61_639 ; CHECK-RV64-NEXT: j .LBB61_116 -; CHECK-RV64-NEXT: .LBB61_638: # %cond.load449 +; CHECK-RV64-NEXT: .LBB61_639: # %cond.load449 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14341,9 +14341,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 13 -; CHECK-RV64-NEXT: bltz a2, .LBB61_639 +; CHECK-RV64-NEXT: bltz a2, .LBB61_640 ; CHECK-RV64-NEXT: j .LBB61_117 -; CHECK-RV64-NEXT: .LBB61_639: # %cond.load453 +; CHECK-RV64-NEXT: .LBB61_640: # %cond.load453 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14356,9 +14356,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 12 -; CHECK-RV64-NEXT: bltz a2, .LBB61_640 +; CHECK-RV64-NEXT: bltz a2, .LBB61_641 ; CHECK-RV64-NEXT: j .LBB61_118 -; CHECK-RV64-NEXT: .LBB61_640: # %cond.load457 +; CHECK-RV64-NEXT: .LBB61_641: # %cond.load457 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14371,9 +14371,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 11 -; CHECK-RV64-NEXT: bltz a2, .LBB61_641 +; CHECK-RV64-NEXT: bltz a2, .LBB61_642 ; CHECK-RV64-NEXT: j .LBB61_119 -; CHECK-RV64-NEXT: .LBB61_641: # %cond.load461 +; CHECK-RV64-NEXT: .LBB61_642: # %cond.load461 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14386,9 +14386,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 10 -; CHECK-RV64-NEXT: bltz a2, .LBB61_642 +; CHECK-RV64-NEXT: bltz a2, .LBB61_643 ; CHECK-RV64-NEXT: j .LBB61_120 -; CHECK-RV64-NEXT: .LBB61_642: # %cond.load465 +; CHECK-RV64-NEXT: .LBB61_643: # %cond.load465 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14401,9 +14401,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 9 -; CHECK-RV64-NEXT: bltz a2, .LBB61_643 +; CHECK-RV64-NEXT: bltz a2, .LBB61_644 ; CHECK-RV64-NEXT: j .LBB61_121 -; CHECK-RV64-NEXT: .LBB61_643: # %cond.load469 +; CHECK-RV64-NEXT: .LBB61_644: # %cond.load469 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14416,9 +14416,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 8 -; CHECK-RV64-NEXT: bltz a2, .LBB61_644 +; CHECK-RV64-NEXT: bltz a2, .LBB61_645 ; CHECK-RV64-NEXT: j .LBB61_122 -; CHECK-RV64-NEXT: .LBB61_644: # %cond.load473 +; CHECK-RV64-NEXT: .LBB61_645: # %cond.load473 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14431,9 +14431,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 7 -; CHECK-RV64-NEXT: bltz a2, .LBB61_645 +; CHECK-RV64-NEXT: bltz a2, .LBB61_646 ; CHECK-RV64-NEXT: j .LBB61_123 -; CHECK-RV64-NEXT: .LBB61_645: # %cond.load477 +; CHECK-RV64-NEXT: .LBB61_646: # %cond.load477 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14446,9 +14446,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 6 -; CHECK-RV64-NEXT: bltz a2, .LBB61_646 +; CHECK-RV64-NEXT: bltz a2, .LBB61_647 ; CHECK-RV64-NEXT: j .LBB61_124 -; CHECK-RV64-NEXT: .LBB61_646: # %cond.load481 +; CHECK-RV64-NEXT: .LBB61_647: # %cond.load481 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14461,9 +14461,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 5 -; CHECK-RV64-NEXT: bltz a2, .LBB61_647 +; CHECK-RV64-NEXT: bltz a2, .LBB61_648 ; CHECK-RV64-NEXT: j .LBB61_125 -; CHECK-RV64-NEXT: .LBB61_647: # %cond.load485 +; CHECK-RV64-NEXT: .LBB61_648: # %cond.load485 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14476,9 +14476,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 4 -; CHECK-RV64-NEXT: bltz a2, .LBB61_648 +; CHECK-RV64-NEXT: bltz a2, .LBB61_649 ; CHECK-RV64-NEXT: j .LBB61_126 -; CHECK-RV64-NEXT: .LBB61_648: # %cond.load489 +; CHECK-RV64-NEXT: .LBB61_649: # %cond.load489 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14491,9 +14491,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 3 -; CHECK-RV64-NEXT: bltz a2, .LBB61_649 +; CHECK-RV64-NEXT: bltz a2, .LBB61_650 ; CHECK-RV64-NEXT: j .LBB61_127 -; CHECK-RV64-NEXT: .LBB61_649: # %cond.load493 +; CHECK-RV64-NEXT: .LBB61_650: # %cond.load493 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14506,11 +14506,11 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 2 -; CHECK-RV64-NEXT: bgez a2, .LBB61_1026 +; CHECK-RV64-NEXT: bgez a2, .LBB61_651 ; CHECK-RV64-NEXT: j .LBB61_128 -; CHECK-RV64-NEXT: .LBB61_1026: # %cond.load493 +; CHECK-RV64-NEXT: .LBB61_651: # %cond.load493 ; CHECK-RV64-NEXT: j .LBB61_129 -; CHECK-RV64-NEXT: .LBB61_650: # %cond.load505 +; CHECK-RV64-NEXT: .LBB61_652: # %cond.load505 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vmv8r.v v16, v8 ; CHECK-RV64-NEXT: vmv.s.x v10, a1 @@ -14522,9 +14522,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv2r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: andi a1, a2, 1 -; CHECK-RV64-NEXT: bnez a1, .LBB61_651 +; CHECK-RV64-NEXT: bnez a1, .LBB61_653 ; CHECK-RV64-NEXT: j .LBB61_133 -; CHECK-RV64-NEXT: .LBB61_651: # %cond.load509 +; CHECK-RV64-NEXT: .LBB61_653: # %cond.load509 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14537,9 +14537,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: andi a1, a2, 2 -; CHECK-RV64-NEXT: bnez a1, .LBB61_652 +; CHECK-RV64-NEXT: bnez a1, .LBB61_654 ; CHECK-RV64-NEXT: j .LBB61_134 -; CHECK-RV64-NEXT: .LBB61_652: # %cond.load513 +; CHECK-RV64-NEXT: .LBB61_654: # %cond.load513 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14552,9 +14552,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: andi a1, a2, 4 -; CHECK-RV64-NEXT: bnez a1, .LBB61_653 +; CHECK-RV64-NEXT: bnez a1, .LBB61_655 ; CHECK-RV64-NEXT: j .LBB61_135 -; CHECK-RV64-NEXT: .LBB61_653: # %cond.load517 +; CHECK-RV64-NEXT: .LBB61_655: # %cond.load517 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14567,9 +14567,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: andi a1, a2, 8 -; CHECK-RV64-NEXT: bnez a1, .LBB61_654 +; CHECK-RV64-NEXT: bnez a1, .LBB61_656 ; CHECK-RV64-NEXT: j .LBB61_136 -; CHECK-RV64-NEXT: .LBB61_654: # %cond.load521 +; CHECK-RV64-NEXT: .LBB61_656: # %cond.load521 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14582,9 +14582,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: andi a1, a2, 16 -; CHECK-RV64-NEXT: bnez a1, .LBB61_655 +; CHECK-RV64-NEXT: bnez a1, .LBB61_657 ; CHECK-RV64-NEXT: j .LBB61_137 -; CHECK-RV64-NEXT: .LBB61_655: # %cond.load525 +; CHECK-RV64-NEXT: .LBB61_657: # %cond.load525 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14597,9 +14597,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: andi a1, a2, 32 -; CHECK-RV64-NEXT: bnez a1, .LBB61_656 +; CHECK-RV64-NEXT: bnez a1, .LBB61_658 ; CHECK-RV64-NEXT: j .LBB61_138 -; CHECK-RV64-NEXT: .LBB61_656: # %cond.load529 +; CHECK-RV64-NEXT: .LBB61_658: # %cond.load529 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14612,9 +14612,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: andi a1, a2, 64 -; CHECK-RV64-NEXT: bnez a1, .LBB61_657 +; CHECK-RV64-NEXT: bnez a1, .LBB61_659 ; CHECK-RV64-NEXT: j .LBB61_139 -; CHECK-RV64-NEXT: .LBB61_657: # %cond.load533 +; CHECK-RV64-NEXT: .LBB61_659: # %cond.load533 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14627,9 +14627,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: andi a1, a2, 128 -; CHECK-RV64-NEXT: bnez a1, .LBB61_658 +; CHECK-RV64-NEXT: bnez a1, .LBB61_660 ; CHECK-RV64-NEXT: j .LBB61_140 -; CHECK-RV64-NEXT: .LBB61_658: # %cond.load537 +; CHECK-RV64-NEXT: .LBB61_660: # %cond.load537 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14642,9 +14642,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: andi a1, a2, 256 -; CHECK-RV64-NEXT: bnez a1, .LBB61_659 +; CHECK-RV64-NEXT: bnez a1, .LBB61_661 ; CHECK-RV64-NEXT: j .LBB61_141 -; CHECK-RV64-NEXT: .LBB61_659: # %cond.load541 +; CHECK-RV64-NEXT: .LBB61_661: # %cond.load541 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14657,9 +14657,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: andi a1, a2, 512 -; CHECK-RV64-NEXT: bnez a1, .LBB61_660 +; CHECK-RV64-NEXT: bnez a1, .LBB61_662 ; CHECK-RV64-NEXT: j .LBB61_142 -; CHECK-RV64-NEXT: .LBB61_660: # %cond.load545 +; CHECK-RV64-NEXT: .LBB61_662: # %cond.load545 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14672,9 +14672,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: andi a1, a2, 1024 -; CHECK-RV64-NEXT: bnez a1, .LBB61_661 +; CHECK-RV64-NEXT: bnez a1, .LBB61_663 ; CHECK-RV64-NEXT: j .LBB61_143 -; CHECK-RV64-NEXT: .LBB61_661: # %cond.load549 +; CHECK-RV64-NEXT: .LBB61_663: # %cond.load549 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14687,9 +14687,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 52 -; CHECK-RV64-NEXT: bltz a1, .LBB61_662 +; CHECK-RV64-NEXT: bltz a1, .LBB61_664 ; CHECK-RV64-NEXT: j .LBB61_144 -; CHECK-RV64-NEXT: .LBB61_662: # %cond.load553 +; CHECK-RV64-NEXT: .LBB61_664: # %cond.load553 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14702,9 +14702,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 51 -; CHECK-RV64-NEXT: bltz a1, .LBB61_663 +; CHECK-RV64-NEXT: bltz a1, .LBB61_665 ; CHECK-RV64-NEXT: j .LBB61_145 -; CHECK-RV64-NEXT: .LBB61_663: # %cond.load557 +; CHECK-RV64-NEXT: .LBB61_665: # %cond.load557 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14717,9 +14717,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 50 -; CHECK-RV64-NEXT: bltz a1, .LBB61_664 +; CHECK-RV64-NEXT: bltz a1, .LBB61_666 ; CHECK-RV64-NEXT: j .LBB61_146 -; CHECK-RV64-NEXT: .LBB61_664: # %cond.load561 +; CHECK-RV64-NEXT: .LBB61_666: # %cond.load561 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14732,9 +14732,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 49 -; CHECK-RV64-NEXT: bltz a1, .LBB61_665 +; CHECK-RV64-NEXT: bltz a1, .LBB61_667 ; CHECK-RV64-NEXT: j .LBB61_147 -; CHECK-RV64-NEXT: .LBB61_665: # %cond.load565 +; CHECK-RV64-NEXT: .LBB61_667: # %cond.load565 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14747,9 +14747,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 48 -; CHECK-RV64-NEXT: bltz a1, .LBB61_666 +; CHECK-RV64-NEXT: bltz a1, .LBB61_668 ; CHECK-RV64-NEXT: j .LBB61_148 -; CHECK-RV64-NEXT: .LBB61_666: # %cond.load569 +; CHECK-RV64-NEXT: .LBB61_668: # %cond.load569 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14762,9 +14762,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 47 -; CHECK-RV64-NEXT: bltz a1, .LBB61_667 +; CHECK-RV64-NEXT: bltz a1, .LBB61_669 ; CHECK-RV64-NEXT: j .LBB61_149 -; CHECK-RV64-NEXT: .LBB61_667: # %cond.load573 +; CHECK-RV64-NEXT: .LBB61_669: # %cond.load573 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14777,9 +14777,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 46 -; CHECK-RV64-NEXT: bltz a1, .LBB61_668 +; CHECK-RV64-NEXT: bltz a1, .LBB61_670 ; CHECK-RV64-NEXT: j .LBB61_150 -; CHECK-RV64-NEXT: .LBB61_668: # %cond.load577 +; CHECK-RV64-NEXT: .LBB61_670: # %cond.load577 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14792,9 +14792,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 45 -; CHECK-RV64-NEXT: bltz a1, .LBB61_669 +; CHECK-RV64-NEXT: bltz a1, .LBB61_671 ; CHECK-RV64-NEXT: j .LBB61_151 -; CHECK-RV64-NEXT: .LBB61_669: # %cond.load581 +; CHECK-RV64-NEXT: .LBB61_671: # %cond.load581 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14807,9 +14807,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 44 -; CHECK-RV64-NEXT: bltz a1, .LBB61_670 +; CHECK-RV64-NEXT: bltz a1, .LBB61_672 ; CHECK-RV64-NEXT: j .LBB61_152 -; CHECK-RV64-NEXT: .LBB61_670: # %cond.load585 +; CHECK-RV64-NEXT: .LBB61_672: # %cond.load585 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14822,9 +14822,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 43 -; CHECK-RV64-NEXT: bltz a1, .LBB61_671 +; CHECK-RV64-NEXT: bltz a1, .LBB61_673 ; CHECK-RV64-NEXT: j .LBB61_153 -; CHECK-RV64-NEXT: .LBB61_671: # %cond.load589 +; CHECK-RV64-NEXT: .LBB61_673: # %cond.load589 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14837,9 +14837,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 42 -; CHECK-RV64-NEXT: bltz a1, .LBB61_672 +; CHECK-RV64-NEXT: bltz a1, .LBB61_674 ; CHECK-RV64-NEXT: j .LBB61_154 -; CHECK-RV64-NEXT: .LBB61_672: # %cond.load593 +; CHECK-RV64-NEXT: .LBB61_674: # %cond.load593 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14852,9 +14852,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 41 -; CHECK-RV64-NEXT: bltz a1, .LBB61_673 +; CHECK-RV64-NEXT: bltz a1, .LBB61_675 ; CHECK-RV64-NEXT: j .LBB61_155 -; CHECK-RV64-NEXT: .LBB61_673: # %cond.load597 +; CHECK-RV64-NEXT: .LBB61_675: # %cond.load597 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14867,9 +14867,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 40 -; CHECK-RV64-NEXT: bltz a1, .LBB61_674 +; CHECK-RV64-NEXT: bltz a1, .LBB61_676 ; CHECK-RV64-NEXT: j .LBB61_156 -; CHECK-RV64-NEXT: .LBB61_674: # %cond.load601 +; CHECK-RV64-NEXT: .LBB61_676: # %cond.load601 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14882,9 +14882,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 39 -; CHECK-RV64-NEXT: bltz a1, .LBB61_675 +; CHECK-RV64-NEXT: bltz a1, .LBB61_677 ; CHECK-RV64-NEXT: j .LBB61_157 -; CHECK-RV64-NEXT: .LBB61_675: # %cond.load605 +; CHECK-RV64-NEXT: .LBB61_677: # %cond.load605 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14897,9 +14897,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 38 -; CHECK-RV64-NEXT: bltz a1, .LBB61_676 +; CHECK-RV64-NEXT: bltz a1, .LBB61_678 ; CHECK-RV64-NEXT: j .LBB61_158 -; CHECK-RV64-NEXT: .LBB61_676: # %cond.load609 +; CHECK-RV64-NEXT: .LBB61_678: # %cond.load609 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14912,9 +14912,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 37 -; CHECK-RV64-NEXT: bltz a1, .LBB61_677 +; CHECK-RV64-NEXT: bltz a1, .LBB61_679 ; CHECK-RV64-NEXT: j .LBB61_159 -; CHECK-RV64-NEXT: .LBB61_677: # %cond.load613 +; CHECK-RV64-NEXT: .LBB61_679: # %cond.load613 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14927,9 +14927,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 36 -; CHECK-RV64-NEXT: bltz a1, .LBB61_678 +; CHECK-RV64-NEXT: bltz a1, .LBB61_680 ; CHECK-RV64-NEXT: j .LBB61_160 -; CHECK-RV64-NEXT: .LBB61_678: # %cond.load617 +; CHECK-RV64-NEXT: .LBB61_680: # %cond.load617 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14942,9 +14942,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 35 -; CHECK-RV64-NEXT: bltz a1, .LBB61_679 +; CHECK-RV64-NEXT: bltz a1, .LBB61_681 ; CHECK-RV64-NEXT: j .LBB61_161 -; CHECK-RV64-NEXT: .LBB61_679: # %cond.load621 +; CHECK-RV64-NEXT: .LBB61_681: # %cond.load621 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14957,9 +14957,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 34 -; CHECK-RV64-NEXT: bltz a1, .LBB61_680 +; CHECK-RV64-NEXT: bltz a1, .LBB61_682 ; CHECK-RV64-NEXT: j .LBB61_162 -; CHECK-RV64-NEXT: .LBB61_680: # %cond.load625 +; CHECK-RV64-NEXT: .LBB61_682: # %cond.load625 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14972,9 +14972,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 33 -; CHECK-RV64-NEXT: bltz a1, .LBB61_681 +; CHECK-RV64-NEXT: bltz a1, .LBB61_683 ; CHECK-RV64-NEXT: j .LBB61_163 -; CHECK-RV64-NEXT: .LBB61_681: # %cond.load629 +; CHECK-RV64-NEXT: .LBB61_683: # %cond.load629 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -14987,9 +14987,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 32 -; CHECK-RV64-NEXT: bltz a1, .LBB61_682 +; CHECK-RV64-NEXT: bltz a1, .LBB61_684 ; CHECK-RV64-NEXT: j .LBB61_164 -; CHECK-RV64-NEXT: .LBB61_682: # %cond.load633 +; CHECK-RV64-NEXT: .LBB61_684: # %cond.load633 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15002,9 +15002,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 31 -; CHECK-RV64-NEXT: bltz a1, .LBB61_683 +; CHECK-RV64-NEXT: bltz a1, .LBB61_685 ; CHECK-RV64-NEXT: j .LBB61_165 -; CHECK-RV64-NEXT: .LBB61_683: # %cond.load637 +; CHECK-RV64-NEXT: .LBB61_685: # %cond.load637 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15017,9 +15017,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 30 -; CHECK-RV64-NEXT: bltz a1, .LBB61_684 +; CHECK-RV64-NEXT: bltz a1, .LBB61_686 ; CHECK-RV64-NEXT: j .LBB61_166 -; CHECK-RV64-NEXT: .LBB61_684: # %cond.load641 +; CHECK-RV64-NEXT: .LBB61_686: # %cond.load641 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15032,9 +15032,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 29 -; CHECK-RV64-NEXT: bltz a1, .LBB61_685 +; CHECK-RV64-NEXT: bltz a1, .LBB61_687 ; CHECK-RV64-NEXT: j .LBB61_167 -; CHECK-RV64-NEXT: .LBB61_685: # %cond.load645 +; CHECK-RV64-NEXT: .LBB61_687: # %cond.load645 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15047,9 +15047,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 28 -; CHECK-RV64-NEXT: bltz a1, .LBB61_686 +; CHECK-RV64-NEXT: bltz a1, .LBB61_688 ; CHECK-RV64-NEXT: j .LBB61_168 -; CHECK-RV64-NEXT: .LBB61_686: # %cond.load649 +; CHECK-RV64-NEXT: .LBB61_688: # %cond.load649 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15062,9 +15062,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 27 -; CHECK-RV64-NEXT: bltz a1, .LBB61_687 +; CHECK-RV64-NEXT: bltz a1, .LBB61_689 ; CHECK-RV64-NEXT: j .LBB61_169 -; CHECK-RV64-NEXT: .LBB61_687: # %cond.load653 +; CHECK-RV64-NEXT: .LBB61_689: # %cond.load653 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15077,9 +15077,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 26 -; CHECK-RV64-NEXT: bltz a1, .LBB61_688 +; CHECK-RV64-NEXT: bltz a1, .LBB61_690 ; CHECK-RV64-NEXT: j .LBB61_170 -; CHECK-RV64-NEXT: .LBB61_688: # %cond.load657 +; CHECK-RV64-NEXT: .LBB61_690: # %cond.load657 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15092,9 +15092,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 25 -; CHECK-RV64-NEXT: bltz a1, .LBB61_689 +; CHECK-RV64-NEXT: bltz a1, .LBB61_691 ; CHECK-RV64-NEXT: j .LBB61_171 -; CHECK-RV64-NEXT: .LBB61_689: # %cond.load661 +; CHECK-RV64-NEXT: .LBB61_691: # %cond.load661 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15107,9 +15107,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 24 -; CHECK-RV64-NEXT: bltz a1, .LBB61_690 +; CHECK-RV64-NEXT: bltz a1, .LBB61_692 ; CHECK-RV64-NEXT: j .LBB61_172 -; CHECK-RV64-NEXT: .LBB61_690: # %cond.load665 +; CHECK-RV64-NEXT: .LBB61_692: # %cond.load665 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15122,9 +15122,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 23 -; CHECK-RV64-NEXT: bltz a1, .LBB61_691 +; CHECK-RV64-NEXT: bltz a1, .LBB61_693 ; CHECK-RV64-NEXT: j .LBB61_173 -; CHECK-RV64-NEXT: .LBB61_691: # %cond.load669 +; CHECK-RV64-NEXT: .LBB61_693: # %cond.load669 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15137,9 +15137,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 22 -; CHECK-RV64-NEXT: bltz a1, .LBB61_692 +; CHECK-RV64-NEXT: bltz a1, .LBB61_694 ; CHECK-RV64-NEXT: j .LBB61_174 -; CHECK-RV64-NEXT: .LBB61_692: # %cond.load673 +; CHECK-RV64-NEXT: .LBB61_694: # %cond.load673 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15152,9 +15152,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 21 -; CHECK-RV64-NEXT: bltz a1, .LBB61_693 +; CHECK-RV64-NEXT: bltz a1, .LBB61_695 ; CHECK-RV64-NEXT: j .LBB61_175 -; CHECK-RV64-NEXT: .LBB61_693: # %cond.load677 +; CHECK-RV64-NEXT: .LBB61_695: # %cond.load677 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15167,9 +15167,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 20 -; CHECK-RV64-NEXT: bltz a1, .LBB61_694 +; CHECK-RV64-NEXT: bltz a1, .LBB61_696 ; CHECK-RV64-NEXT: j .LBB61_176 -; CHECK-RV64-NEXT: .LBB61_694: # %cond.load681 +; CHECK-RV64-NEXT: .LBB61_696: # %cond.load681 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15182,9 +15182,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 19 -; CHECK-RV64-NEXT: bltz a1, .LBB61_695 +; CHECK-RV64-NEXT: bltz a1, .LBB61_697 ; CHECK-RV64-NEXT: j .LBB61_177 -; CHECK-RV64-NEXT: .LBB61_695: # %cond.load685 +; CHECK-RV64-NEXT: .LBB61_697: # %cond.load685 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15197,9 +15197,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 18 -; CHECK-RV64-NEXT: bltz a1, .LBB61_696 +; CHECK-RV64-NEXT: bltz a1, .LBB61_698 ; CHECK-RV64-NEXT: j .LBB61_178 -; CHECK-RV64-NEXT: .LBB61_696: # %cond.load689 +; CHECK-RV64-NEXT: .LBB61_698: # %cond.load689 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15212,9 +15212,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 17 -; CHECK-RV64-NEXT: bltz a1, .LBB61_697 +; CHECK-RV64-NEXT: bltz a1, .LBB61_699 ; CHECK-RV64-NEXT: j .LBB61_179 -; CHECK-RV64-NEXT: .LBB61_697: # %cond.load693 +; CHECK-RV64-NEXT: .LBB61_699: # %cond.load693 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15227,9 +15227,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 16 -; CHECK-RV64-NEXT: bltz a1, .LBB61_698 +; CHECK-RV64-NEXT: bltz a1, .LBB61_700 ; CHECK-RV64-NEXT: j .LBB61_180 -; CHECK-RV64-NEXT: .LBB61_698: # %cond.load697 +; CHECK-RV64-NEXT: .LBB61_700: # %cond.load697 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15242,9 +15242,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 15 -; CHECK-RV64-NEXT: bltz a1, .LBB61_699 +; CHECK-RV64-NEXT: bltz a1, .LBB61_701 ; CHECK-RV64-NEXT: j .LBB61_181 -; CHECK-RV64-NEXT: .LBB61_699: # %cond.load701 +; CHECK-RV64-NEXT: .LBB61_701: # %cond.load701 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15257,9 +15257,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 14 -; CHECK-RV64-NEXT: bltz a1, .LBB61_700 +; CHECK-RV64-NEXT: bltz a1, .LBB61_702 ; CHECK-RV64-NEXT: j .LBB61_182 -; CHECK-RV64-NEXT: .LBB61_700: # %cond.load705 +; CHECK-RV64-NEXT: .LBB61_702: # %cond.load705 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15272,9 +15272,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 13 -; CHECK-RV64-NEXT: bltz a1, .LBB61_701 +; CHECK-RV64-NEXT: bltz a1, .LBB61_703 ; CHECK-RV64-NEXT: j .LBB61_183 -; CHECK-RV64-NEXT: .LBB61_701: # %cond.load709 +; CHECK-RV64-NEXT: .LBB61_703: # %cond.load709 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15287,9 +15287,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 12 -; CHECK-RV64-NEXT: bltz a1, .LBB61_702 +; CHECK-RV64-NEXT: bltz a1, .LBB61_704 ; CHECK-RV64-NEXT: j .LBB61_184 -; CHECK-RV64-NEXT: .LBB61_702: # %cond.load713 +; CHECK-RV64-NEXT: .LBB61_704: # %cond.load713 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15302,9 +15302,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 11 -; CHECK-RV64-NEXT: bltz a1, .LBB61_703 +; CHECK-RV64-NEXT: bltz a1, .LBB61_705 ; CHECK-RV64-NEXT: j .LBB61_185 -; CHECK-RV64-NEXT: .LBB61_703: # %cond.load717 +; CHECK-RV64-NEXT: .LBB61_705: # %cond.load717 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15317,9 +15317,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 10 -; CHECK-RV64-NEXT: bltz a1, .LBB61_704 +; CHECK-RV64-NEXT: bltz a1, .LBB61_706 ; CHECK-RV64-NEXT: j .LBB61_186 -; CHECK-RV64-NEXT: .LBB61_704: # %cond.load721 +; CHECK-RV64-NEXT: .LBB61_706: # %cond.load721 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15332,9 +15332,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 9 -; CHECK-RV64-NEXT: bltz a1, .LBB61_705 +; CHECK-RV64-NEXT: bltz a1, .LBB61_707 ; CHECK-RV64-NEXT: j .LBB61_187 -; CHECK-RV64-NEXT: .LBB61_705: # %cond.load725 +; CHECK-RV64-NEXT: .LBB61_707: # %cond.load725 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15347,9 +15347,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 8 -; CHECK-RV64-NEXT: bltz a1, .LBB61_706 +; CHECK-RV64-NEXT: bltz a1, .LBB61_708 ; CHECK-RV64-NEXT: j .LBB61_188 -; CHECK-RV64-NEXT: .LBB61_706: # %cond.load729 +; CHECK-RV64-NEXT: .LBB61_708: # %cond.load729 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15362,9 +15362,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 7 -; CHECK-RV64-NEXT: bltz a1, .LBB61_707 +; CHECK-RV64-NEXT: bltz a1, .LBB61_709 ; CHECK-RV64-NEXT: j .LBB61_189 -; CHECK-RV64-NEXT: .LBB61_707: # %cond.load733 +; CHECK-RV64-NEXT: .LBB61_709: # %cond.load733 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15377,9 +15377,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 6 -; CHECK-RV64-NEXT: bltz a1, .LBB61_708 +; CHECK-RV64-NEXT: bltz a1, .LBB61_710 ; CHECK-RV64-NEXT: j .LBB61_190 -; CHECK-RV64-NEXT: .LBB61_708: # %cond.load737 +; CHECK-RV64-NEXT: .LBB61_710: # %cond.load737 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15392,9 +15392,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 5 -; CHECK-RV64-NEXT: bltz a1, .LBB61_709 +; CHECK-RV64-NEXT: bltz a1, .LBB61_711 ; CHECK-RV64-NEXT: j .LBB61_191 -; CHECK-RV64-NEXT: .LBB61_709: # %cond.load741 +; CHECK-RV64-NEXT: .LBB61_711: # %cond.load741 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15407,9 +15407,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 4 -; CHECK-RV64-NEXT: bltz a1, .LBB61_710 +; CHECK-RV64-NEXT: bltz a1, .LBB61_712 ; CHECK-RV64-NEXT: j .LBB61_192 -; CHECK-RV64-NEXT: .LBB61_710: # %cond.load745 +; CHECK-RV64-NEXT: .LBB61_712: # %cond.load745 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15422,9 +15422,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 3 -; CHECK-RV64-NEXT: bltz a1, .LBB61_711 +; CHECK-RV64-NEXT: bltz a1, .LBB61_713 ; CHECK-RV64-NEXT: j .LBB61_193 -; CHECK-RV64-NEXT: .LBB61_711: # %cond.load749 +; CHECK-RV64-NEXT: .LBB61_713: # %cond.load749 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15437,11 +15437,11 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a1, a2, 2 -; CHECK-RV64-NEXT: bgez a1, .LBB61_1027 +; CHECK-RV64-NEXT: bgez a1, .LBB61_714 ; CHECK-RV64-NEXT: j .LBB61_194 -; CHECK-RV64-NEXT: .LBB61_1027: # %cond.load749 +; CHECK-RV64-NEXT: .LBB61_714: # %cond.load749 ; CHECK-RV64-NEXT: j .LBB61_195 -; CHECK-RV64-NEXT: .LBB61_712: # %cond.load761 +; CHECK-RV64-NEXT: .LBB61_715: # %cond.load761 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vmv8r.v v16, v8 ; CHECK-RV64-NEXT: vmv.s.x v12, a2 @@ -15453,9 +15453,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: andi a2, a1, 1 -; CHECK-RV64-NEXT: bnez a2, .LBB61_713 +; CHECK-RV64-NEXT: bnez a2, .LBB61_716 ; CHECK-RV64-NEXT: j .LBB61_199 -; CHECK-RV64-NEXT: .LBB61_713: # %cond.load765 +; CHECK-RV64-NEXT: .LBB61_716: # %cond.load765 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15468,9 +15468,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: andi a2, a1, 2 -; CHECK-RV64-NEXT: bnez a2, .LBB61_714 +; CHECK-RV64-NEXT: bnez a2, .LBB61_717 ; CHECK-RV64-NEXT: j .LBB61_200 -; CHECK-RV64-NEXT: .LBB61_714: # %cond.load769 +; CHECK-RV64-NEXT: .LBB61_717: # %cond.load769 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15483,9 +15483,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: andi a2, a1, 4 -; CHECK-RV64-NEXT: bnez a2, .LBB61_715 +; CHECK-RV64-NEXT: bnez a2, .LBB61_718 ; CHECK-RV64-NEXT: j .LBB61_201 -; CHECK-RV64-NEXT: .LBB61_715: # %cond.load773 +; CHECK-RV64-NEXT: .LBB61_718: # %cond.load773 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15498,9 +15498,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: andi a2, a1, 8 -; CHECK-RV64-NEXT: bnez a2, .LBB61_716 +; CHECK-RV64-NEXT: bnez a2, .LBB61_719 ; CHECK-RV64-NEXT: j .LBB61_202 -; CHECK-RV64-NEXT: .LBB61_716: # %cond.load777 +; CHECK-RV64-NEXT: .LBB61_719: # %cond.load777 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15513,9 +15513,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: andi a2, a1, 16 -; CHECK-RV64-NEXT: bnez a2, .LBB61_717 +; CHECK-RV64-NEXT: bnez a2, .LBB61_720 ; CHECK-RV64-NEXT: j .LBB61_203 -; CHECK-RV64-NEXT: .LBB61_717: # %cond.load781 +; CHECK-RV64-NEXT: .LBB61_720: # %cond.load781 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15528,9 +15528,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: andi a2, a1, 32 -; CHECK-RV64-NEXT: bnez a2, .LBB61_718 +; CHECK-RV64-NEXT: bnez a2, .LBB61_721 ; CHECK-RV64-NEXT: j .LBB61_204 -; CHECK-RV64-NEXT: .LBB61_718: # %cond.load785 +; CHECK-RV64-NEXT: .LBB61_721: # %cond.load785 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15543,9 +15543,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: andi a2, a1, 64 -; CHECK-RV64-NEXT: bnez a2, .LBB61_719 +; CHECK-RV64-NEXT: bnez a2, .LBB61_722 ; CHECK-RV64-NEXT: j .LBB61_205 -; CHECK-RV64-NEXT: .LBB61_719: # %cond.load789 +; CHECK-RV64-NEXT: .LBB61_722: # %cond.load789 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15558,9 +15558,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: andi a2, a1, 128 -; CHECK-RV64-NEXT: bnez a2, .LBB61_720 +; CHECK-RV64-NEXT: bnez a2, .LBB61_723 ; CHECK-RV64-NEXT: j .LBB61_206 -; CHECK-RV64-NEXT: .LBB61_720: # %cond.load793 +; CHECK-RV64-NEXT: .LBB61_723: # %cond.load793 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15573,9 +15573,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: andi a2, a1, 256 -; CHECK-RV64-NEXT: bnez a2, .LBB61_721 +; CHECK-RV64-NEXT: bnez a2, .LBB61_724 ; CHECK-RV64-NEXT: j .LBB61_207 -; CHECK-RV64-NEXT: .LBB61_721: # %cond.load797 +; CHECK-RV64-NEXT: .LBB61_724: # %cond.load797 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15588,9 +15588,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: andi a2, a1, 512 -; CHECK-RV64-NEXT: bnez a2, .LBB61_722 +; CHECK-RV64-NEXT: bnez a2, .LBB61_725 ; CHECK-RV64-NEXT: j .LBB61_208 -; CHECK-RV64-NEXT: .LBB61_722: # %cond.load801 +; CHECK-RV64-NEXT: .LBB61_725: # %cond.load801 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15603,9 +15603,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: andi a2, a1, 1024 -; CHECK-RV64-NEXT: bnez a2, .LBB61_723 +; CHECK-RV64-NEXT: bnez a2, .LBB61_726 ; CHECK-RV64-NEXT: j .LBB61_209 -; CHECK-RV64-NEXT: .LBB61_723: # %cond.load805 +; CHECK-RV64-NEXT: .LBB61_726: # %cond.load805 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15618,9 +15618,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 52 -; CHECK-RV64-NEXT: bltz a2, .LBB61_724 +; CHECK-RV64-NEXT: bltz a2, .LBB61_727 ; CHECK-RV64-NEXT: j .LBB61_210 -; CHECK-RV64-NEXT: .LBB61_724: # %cond.load809 +; CHECK-RV64-NEXT: .LBB61_727: # %cond.load809 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15633,9 +15633,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 51 -; CHECK-RV64-NEXT: bltz a2, .LBB61_725 +; CHECK-RV64-NEXT: bltz a2, .LBB61_728 ; CHECK-RV64-NEXT: j .LBB61_211 -; CHECK-RV64-NEXT: .LBB61_725: # %cond.load813 +; CHECK-RV64-NEXT: .LBB61_728: # %cond.load813 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15648,9 +15648,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 50 -; CHECK-RV64-NEXT: bltz a2, .LBB61_726 +; CHECK-RV64-NEXT: bltz a2, .LBB61_729 ; CHECK-RV64-NEXT: j .LBB61_212 -; CHECK-RV64-NEXT: .LBB61_726: # %cond.load817 +; CHECK-RV64-NEXT: .LBB61_729: # %cond.load817 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15663,9 +15663,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 49 -; CHECK-RV64-NEXT: bltz a2, .LBB61_727 +; CHECK-RV64-NEXT: bltz a2, .LBB61_730 ; CHECK-RV64-NEXT: j .LBB61_213 -; CHECK-RV64-NEXT: .LBB61_727: # %cond.load821 +; CHECK-RV64-NEXT: .LBB61_730: # %cond.load821 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15678,9 +15678,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 48 -; CHECK-RV64-NEXT: bltz a2, .LBB61_728 +; CHECK-RV64-NEXT: bltz a2, .LBB61_731 ; CHECK-RV64-NEXT: j .LBB61_214 -; CHECK-RV64-NEXT: .LBB61_728: # %cond.load825 +; CHECK-RV64-NEXT: .LBB61_731: # %cond.load825 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15693,9 +15693,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 47 -; CHECK-RV64-NEXT: bltz a2, .LBB61_729 +; CHECK-RV64-NEXT: bltz a2, .LBB61_732 ; CHECK-RV64-NEXT: j .LBB61_215 -; CHECK-RV64-NEXT: .LBB61_729: # %cond.load829 +; CHECK-RV64-NEXT: .LBB61_732: # %cond.load829 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15708,9 +15708,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 46 -; CHECK-RV64-NEXT: bltz a2, .LBB61_730 +; CHECK-RV64-NEXT: bltz a2, .LBB61_733 ; CHECK-RV64-NEXT: j .LBB61_216 -; CHECK-RV64-NEXT: .LBB61_730: # %cond.load833 +; CHECK-RV64-NEXT: .LBB61_733: # %cond.load833 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15723,9 +15723,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 45 -; CHECK-RV64-NEXT: bltz a2, .LBB61_731 +; CHECK-RV64-NEXT: bltz a2, .LBB61_734 ; CHECK-RV64-NEXT: j .LBB61_217 -; CHECK-RV64-NEXT: .LBB61_731: # %cond.load837 +; CHECK-RV64-NEXT: .LBB61_734: # %cond.load837 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15738,9 +15738,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 44 -; CHECK-RV64-NEXT: bltz a2, .LBB61_732 +; CHECK-RV64-NEXT: bltz a2, .LBB61_735 ; CHECK-RV64-NEXT: j .LBB61_218 -; CHECK-RV64-NEXT: .LBB61_732: # %cond.load841 +; CHECK-RV64-NEXT: .LBB61_735: # %cond.load841 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15753,9 +15753,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 43 -; CHECK-RV64-NEXT: bltz a2, .LBB61_733 +; CHECK-RV64-NEXT: bltz a2, .LBB61_736 ; CHECK-RV64-NEXT: j .LBB61_219 -; CHECK-RV64-NEXT: .LBB61_733: # %cond.load845 +; CHECK-RV64-NEXT: .LBB61_736: # %cond.load845 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15768,9 +15768,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 42 -; CHECK-RV64-NEXT: bltz a2, .LBB61_734 +; CHECK-RV64-NEXT: bltz a2, .LBB61_737 ; CHECK-RV64-NEXT: j .LBB61_220 -; CHECK-RV64-NEXT: .LBB61_734: # %cond.load849 +; CHECK-RV64-NEXT: .LBB61_737: # %cond.load849 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15783,9 +15783,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 41 -; CHECK-RV64-NEXT: bltz a2, .LBB61_735 +; CHECK-RV64-NEXT: bltz a2, .LBB61_738 ; CHECK-RV64-NEXT: j .LBB61_221 -; CHECK-RV64-NEXT: .LBB61_735: # %cond.load853 +; CHECK-RV64-NEXT: .LBB61_738: # %cond.load853 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15798,9 +15798,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 40 -; CHECK-RV64-NEXT: bltz a2, .LBB61_736 +; CHECK-RV64-NEXT: bltz a2, .LBB61_739 ; CHECK-RV64-NEXT: j .LBB61_222 -; CHECK-RV64-NEXT: .LBB61_736: # %cond.load857 +; CHECK-RV64-NEXT: .LBB61_739: # %cond.load857 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15813,9 +15813,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 39 -; CHECK-RV64-NEXT: bltz a2, .LBB61_737 +; CHECK-RV64-NEXT: bltz a2, .LBB61_740 ; CHECK-RV64-NEXT: j .LBB61_223 -; CHECK-RV64-NEXT: .LBB61_737: # %cond.load861 +; CHECK-RV64-NEXT: .LBB61_740: # %cond.load861 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15828,9 +15828,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 38 -; CHECK-RV64-NEXT: bltz a2, .LBB61_738 +; CHECK-RV64-NEXT: bltz a2, .LBB61_741 ; CHECK-RV64-NEXT: j .LBB61_224 -; CHECK-RV64-NEXT: .LBB61_738: # %cond.load865 +; CHECK-RV64-NEXT: .LBB61_741: # %cond.load865 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15843,9 +15843,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 37 -; CHECK-RV64-NEXT: bltz a2, .LBB61_739 +; CHECK-RV64-NEXT: bltz a2, .LBB61_742 ; CHECK-RV64-NEXT: j .LBB61_225 -; CHECK-RV64-NEXT: .LBB61_739: # %cond.load869 +; CHECK-RV64-NEXT: .LBB61_742: # %cond.load869 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15858,9 +15858,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 36 -; CHECK-RV64-NEXT: bltz a2, .LBB61_740 +; CHECK-RV64-NEXT: bltz a2, .LBB61_743 ; CHECK-RV64-NEXT: j .LBB61_226 -; CHECK-RV64-NEXT: .LBB61_740: # %cond.load873 +; CHECK-RV64-NEXT: .LBB61_743: # %cond.load873 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15873,9 +15873,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 35 -; CHECK-RV64-NEXT: bltz a2, .LBB61_741 +; CHECK-RV64-NEXT: bltz a2, .LBB61_744 ; CHECK-RV64-NEXT: j .LBB61_227 -; CHECK-RV64-NEXT: .LBB61_741: # %cond.load877 +; CHECK-RV64-NEXT: .LBB61_744: # %cond.load877 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15888,9 +15888,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 34 -; CHECK-RV64-NEXT: bltz a2, .LBB61_742 +; CHECK-RV64-NEXT: bltz a2, .LBB61_745 ; CHECK-RV64-NEXT: j .LBB61_228 -; CHECK-RV64-NEXT: .LBB61_742: # %cond.load881 +; CHECK-RV64-NEXT: .LBB61_745: # %cond.load881 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15903,9 +15903,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 33 -; CHECK-RV64-NEXT: bltz a2, .LBB61_743 +; CHECK-RV64-NEXT: bltz a2, .LBB61_746 ; CHECK-RV64-NEXT: j .LBB61_229 -; CHECK-RV64-NEXT: .LBB61_743: # %cond.load885 +; CHECK-RV64-NEXT: .LBB61_746: # %cond.load885 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15918,9 +15918,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 32 -; CHECK-RV64-NEXT: bltz a2, .LBB61_744 +; CHECK-RV64-NEXT: bltz a2, .LBB61_747 ; CHECK-RV64-NEXT: j .LBB61_230 -; CHECK-RV64-NEXT: .LBB61_744: # %cond.load889 +; CHECK-RV64-NEXT: .LBB61_747: # %cond.load889 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15933,9 +15933,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 31 -; CHECK-RV64-NEXT: bltz a2, .LBB61_745 +; CHECK-RV64-NEXT: bltz a2, .LBB61_748 ; CHECK-RV64-NEXT: j .LBB61_231 -; CHECK-RV64-NEXT: .LBB61_745: # %cond.load893 +; CHECK-RV64-NEXT: .LBB61_748: # %cond.load893 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15948,9 +15948,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 30 -; CHECK-RV64-NEXT: bltz a2, .LBB61_746 +; CHECK-RV64-NEXT: bltz a2, .LBB61_749 ; CHECK-RV64-NEXT: j .LBB61_232 -; CHECK-RV64-NEXT: .LBB61_746: # %cond.load897 +; CHECK-RV64-NEXT: .LBB61_749: # %cond.load897 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15963,9 +15963,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 29 -; CHECK-RV64-NEXT: bltz a2, .LBB61_747 +; CHECK-RV64-NEXT: bltz a2, .LBB61_750 ; CHECK-RV64-NEXT: j .LBB61_233 -; CHECK-RV64-NEXT: .LBB61_747: # %cond.load901 +; CHECK-RV64-NEXT: .LBB61_750: # %cond.load901 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15978,9 +15978,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 28 -; CHECK-RV64-NEXT: bltz a2, .LBB61_748 +; CHECK-RV64-NEXT: bltz a2, .LBB61_751 ; CHECK-RV64-NEXT: j .LBB61_234 -; CHECK-RV64-NEXT: .LBB61_748: # %cond.load905 +; CHECK-RV64-NEXT: .LBB61_751: # %cond.load905 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -15993,9 +15993,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 27 -; CHECK-RV64-NEXT: bltz a2, .LBB61_749 +; CHECK-RV64-NEXT: bltz a2, .LBB61_752 ; CHECK-RV64-NEXT: j .LBB61_235 -; CHECK-RV64-NEXT: .LBB61_749: # %cond.load909 +; CHECK-RV64-NEXT: .LBB61_752: # %cond.load909 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -16008,9 +16008,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 26 -; CHECK-RV64-NEXT: bltz a2, .LBB61_750 +; CHECK-RV64-NEXT: bltz a2, .LBB61_753 ; CHECK-RV64-NEXT: j .LBB61_236 -; CHECK-RV64-NEXT: .LBB61_750: # %cond.load913 +; CHECK-RV64-NEXT: .LBB61_753: # %cond.load913 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -16023,9 +16023,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 25 -; CHECK-RV64-NEXT: bltz a2, .LBB61_751 +; CHECK-RV64-NEXT: bltz a2, .LBB61_754 ; CHECK-RV64-NEXT: j .LBB61_237 -; CHECK-RV64-NEXT: .LBB61_751: # %cond.load917 +; CHECK-RV64-NEXT: .LBB61_754: # %cond.load917 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -16038,9 +16038,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 24 -; CHECK-RV64-NEXT: bltz a2, .LBB61_752 +; CHECK-RV64-NEXT: bltz a2, .LBB61_755 ; CHECK-RV64-NEXT: j .LBB61_238 -; CHECK-RV64-NEXT: .LBB61_752: # %cond.load921 +; CHECK-RV64-NEXT: .LBB61_755: # %cond.load921 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -16053,9 +16053,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 23 -; CHECK-RV64-NEXT: bltz a2, .LBB61_753 +; CHECK-RV64-NEXT: bltz a2, .LBB61_756 ; CHECK-RV64-NEXT: j .LBB61_239 -; CHECK-RV64-NEXT: .LBB61_753: # %cond.load925 +; CHECK-RV64-NEXT: .LBB61_756: # %cond.load925 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -16068,9 +16068,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 22 -; CHECK-RV64-NEXT: bltz a2, .LBB61_754 +; CHECK-RV64-NEXT: bltz a2, .LBB61_757 ; CHECK-RV64-NEXT: j .LBB61_240 -; CHECK-RV64-NEXT: .LBB61_754: # %cond.load929 +; CHECK-RV64-NEXT: .LBB61_757: # %cond.load929 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -16083,9 +16083,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 21 -; CHECK-RV64-NEXT: bltz a2, .LBB61_755 +; CHECK-RV64-NEXT: bltz a2, .LBB61_758 ; CHECK-RV64-NEXT: j .LBB61_241 -; CHECK-RV64-NEXT: .LBB61_755: # %cond.load933 +; CHECK-RV64-NEXT: .LBB61_758: # %cond.load933 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -16098,9 +16098,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 20 -; CHECK-RV64-NEXT: bltz a2, .LBB61_756 +; CHECK-RV64-NEXT: bltz a2, .LBB61_759 ; CHECK-RV64-NEXT: j .LBB61_242 -; CHECK-RV64-NEXT: .LBB61_756: # %cond.load937 +; CHECK-RV64-NEXT: .LBB61_759: # %cond.load937 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -16113,9 +16113,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 19 -; CHECK-RV64-NEXT: bltz a2, .LBB61_757 +; CHECK-RV64-NEXT: bltz a2, .LBB61_760 ; CHECK-RV64-NEXT: j .LBB61_243 -; CHECK-RV64-NEXT: .LBB61_757: # %cond.load941 +; CHECK-RV64-NEXT: .LBB61_760: # %cond.load941 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -16128,9 +16128,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 18 -; CHECK-RV64-NEXT: bltz a2, .LBB61_758 +; CHECK-RV64-NEXT: bltz a2, .LBB61_761 ; CHECK-RV64-NEXT: j .LBB61_244 -; CHECK-RV64-NEXT: .LBB61_758: # %cond.load945 +; CHECK-RV64-NEXT: .LBB61_761: # %cond.load945 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -16143,9 +16143,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 17 -; CHECK-RV64-NEXT: bltz a2, .LBB61_759 +; CHECK-RV64-NEXT: bltz a2, .LBB61_762 ; CHECK-RV64-NEXT: j .LBB61_245 -; CHECK-RV64-NEXT: .LBB61_759: # %cond.load949 +; CHECK-RV64-NEXT: .LBB61_762: # %cond.load949 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -16158,9 +16158,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 16 -; CHECK-RV64-NEXT: bltz a2, .LBB61_760 +; CHECK-RV64-NEXT: bltz a2, .LBB61_763 ; CHECK-RV64-NEXT: j .LBB61_246 -; CHECK-RV64-NEXT: .LBB61_760: # %cond.load953 +; CHECK-RV64-NEXT: .LBB61_763: # %cond.load953 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -16173,9 +16173,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 15 -; CHECK-RV64-NEXT: bltz a2, .LBB61_761 +; CHECK-RV64-NEXT: bltz a2, .LBB61_764 ; CHECK-RV64-NEXT: j .LBB61_247 -; CHECK-RV64-NEXT: .LBB61_761: # %cond.load957 +; CHECK-RV64-NEXT: .LBB61_764: # %cond.load957 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -16188,9 +16188,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 14 -; CHECK-RV64-NEXT: bltz a2, .LBB61_762 +; CHECK-RV64-NEXT: bltz a2, .LBB61_765 ; CHECK-RV64-NEXT: j .LBB61_248 -; CHECK-RV64-NEXT: .LBB61_762: # %cond.load961 +; CHECK-RV64-NEXT: .LBB61_765: # %cond.load961 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -16203,9 +16203,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 13 -; CHECK-RV64-NEXT: bltz a2, .LBB61_763 +; CHECK-RV64-NEXT: bltz a2, .LBB61_766 ; CHECK-RV64-NEXT: j .LBB61_249 -; CHECK-RV64-NEXT: .LBB61_763: # %cond.load965 +; CHECK-RV64-NEXT: .LBB61_766: # %cond.load965 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -16218,9 +16218,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 12 -; CHECK-RV64-NEXT: bltz a2, .LBB61_764 +; CHECK-RV64-NEXT: bltz a2, .LBB61_767 ; CHECK-RV64-NEXT: j .LBB61_250 -; CHECK-RV64-NEXT: .LBB61_764: # %cond.load969 +; CHECK-RV64-NEXT: .LBB61_767: # %cond.load969 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -16233,9 +16233,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 11 -; CHECK-RV64-NEXT: bltz a2, .LBB61_765 +; CHECK-RV64-NEXT: bltz a2, .LBB61_768 ; CHECK-RV64-NEXT: j .LBB61_251 -; CHECK-RV64-NEXT: .LBB61_765: # %cond.load973 +; CHECK-RV64-NEXT: .LBB61_768: # %cond.load973 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -16248,9 +16248,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 10 -; CHECK-RV64-NEXT: bltz a2, .LBB61_766 +; CHECK-RV64-NEXT: bltz a2, .LBB61_769 ; CHECK-RV64-NEXT: j .LBB61_252 -; CHECK-RV64-NEXT: .LBB61_766: # %cond.load977 +; CHECK-RV64-NEXT: .LBB61_769: # %cond.load977 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -16263,9 +16263,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 9 -; CHECK-RV64-NEXT: bltz a2, .LBB61_767 +; CHECK-RV64-NEXT: bltz a2, .LBB61_770 ; CHECK-RV64-NEXT: j .LBB61_253 -; CHECK-RV64-NEXT: .LBB61_767: # %cond.load981 +; CHECK-RV64-NEXT: .LBB61_770: # %cond.load981 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -16278,9 +16278,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 8 -; CHECK-RV64-NEXT: bltz a2, .LBB61_768 +; CHECK-RV64-NEXT: bltz a2, .LBB61_771 ; CHECK-RV64-NEXT: j .LBB61_254 -; CHECK-RV64-NEXT: .LBB61_768: # %cond.load985 +; CHECK-RV64-NEXT: .LBB61_771: # %cond.load985 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -16293,9 +16293,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 7 -; CHECK-RV64-NEXT: bltz a2, .LBB61_769 +; CHECK-RV64-NEXT: bltz a2, .LBB61_772 ; CHECK-RV64-NEXT: j .LBB61_255 -; CHECK-RV64-NEXT: .LBB61_769: # %cond.load989 +; CHECK-RV64-NEXT: .LBB61_772: # %cond.load989 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -16308,9 +16308,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 6 -; CHECK-RV64-NEXT: bltz a2, .LBB61_770 +; CHECK-RV64-NEXT: bltz a2, .LBB61_773 ; CHECK-RV64-NEXT: j .LBB61_256 -; CHECK-RV64-NEXT: .LBB61_770: # %cond.load993 +; CHECK-RV64-NEXT: .LBB61_773: # %cond.load993 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -16323,9 +16323,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 5 -; CHECK-RV64-NEXT: bltz a2, .LBB61_771 +; CHECK-RV64-NEXT: bltz a2, .LBB61_774 ; CHECK-RV64-NEXT: j .LBB61_257 -; CHECK-RV64-NEXT: .LBB61_771: # %cond.load997 +; CHECK-RV64-NEXT: .LBB61_774: # %cond.load997 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -16338,9 +16338,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 4 -; CHECK-RV64-NEXT: bltz a2, .LBB61_772 +; CHECK-RV64-NEXT: bltz a2, .LBB61_775 ; CHECK-RV64-NEXT: j .LBB61_258 -; CHECK-RV64-NEXT: .LBB61_772: # %cond.load1001 +; CHECK-RV64-NEXT: .LBB61_775: # %cond.load1001 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -16353,9 +16353,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 3 -; CHECK-RV64-NEXT: bltz a2, .LBB61_773 +; CHECK-RV64-NEXT: bltz a2, .LBB61_776 ; CHECK-RV64-NEXT: j .LBB61_259 -; CHECK-RV64-NEXT: .LBB61_773: # %cond.load1005 +; CHECK-RV64-NEXT: .LBB61_776: # %cond.load1005 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-RV64-NEXT: vmv8r.v v16, v8 @@ -16368,11 +16368,11 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: slli a2, a1, 2 -; CHECK-RV64-NEXT: bgez a2, .LBB61_1028 +; CHECK-RV64-NEXT: bgez a2, .LBB61_777 ; CHECK-RV64-NEXT: j .LBB61_260 -; CHECK-RV64-NEXT: .LBB61_1028: # %cond.load1005 +; CHECK-RV64-NEXT: .LBB61_777: # %cond.load1005 ; CHECK-RV64-NEXT: j .LBB61_261 -; CHECK-RV64-NEXT: .LBB61_774: # %cond.load1017 +; CHECK-RV64-NEXT: .LBB61_778: # %cond.load1017 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vmv8r.v v16, v8 ; CHECK-RV64-NEXT: vmv.s.x v12, a1 @@ -16384,9 +16384,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vmv4r.v v16, v8 ; CHECK-RV64-NEXT: vmv8r.v v8, v16 ; CHECK-RV64-NEXT: andi a1, a2, 1 -; CHECK-RV64-NEXT: bnez a1, .LBB61_775 +; CHECK-RV64-NEXT: bnez a1, .LBB61_779 ; CHECK-RV64-NEXT: j .LBB61_265 -; CHECK-RV64-NEXT: .LBB61_775: # %cond.load1021 +; CHECK-RV64-NEXT: .LBB61_779: # %cond.load1021 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16397,9 +16397,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a1, a2, 2 -; CHECK-RV64-NEXT: bnez a1, .LBB61_776 +; CHECK-RV64-NEXT: bnez a1, .LBB61_780 ; CHECK-RV64-NEXT: j .LBB61_266 -; CHECK-RV64-NEXT: .LBB61_776: # %cond.load1025 +; CHECK-RV64-NEXT: .LBB61_780: # %cond.load1025 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16410,9 +16410,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a1, a2, 4 -; CHECK-RV64-NEXT: bnez a1, .LBB61_777 +; CHECK-RV64-NEXT: bnez a1, .LBB61_781 ; CHECK-RV64-NEXT: j .LBB61_267 -; CHECK-RV64-NEXT: .LBB61_777: # %cond.load1029 +; CHECK-RV64-NEXT: .LBB61_781: # %cond.load1029 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16423,9 +16423,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a1, a2, 8 -; CHECK-RV64-NEXT: bnez a1, .LBB61_778 +; CHECK-RV64-NEXT: bnez a1, .LBB61_782 ; CHECK-RV64-NEXT: j .LBB61_268 -; CHECK-RV64-NEXT: .LBB61_778: # %cond.load1033 +; CHECK-RV64-NEXT: .LBB61_782: # %cond.load1033 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16436,9 +16436,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a1, a2, 16 -; CHECK-RV64-NEXT: bnez a1, .LBB61_779 +; CHECK-RV64-NEXT: bnez a1, .LBB61_783 ; CHECK-RV64-NEXT: j .LBB61_269 -; CHECK-RV64-NEXT: .LBB61_779: # %cond.load1037 +; CHECK-RV64-NEXT: .LBB61_783: # %cond.load1037 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16449,9 +16449,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a1, a2, 32 -; CHECK-RV64-NEXT: bnez a1, .LBB61_780 +; CHECK-RV64-NEXT: bnez a1, .LBB61_784 ; CHECK-RV64-NEXT: j .LBB61_270 -; CHECK-RV64-NEXT: .LBB61_780: # %cond.load1041 +; CHECK-RV64-NEXT: .LBB61_784: # %cond.load1041 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16462,9 +16462,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a1, a2, 64 -; CHECK-RV64-NEXT: bnez a1, .LBB61_781 +; CHECK-RV64-NEXT: bnez a1, .LBB61_785 ; CHECK-RV64-NEXT: j .LBB61_271 -; CHECK-RV64-NEXT: .LBB61_781: # %cond.load1045 +; CHECK-RV64-NEXT: .LBB61_785: # %cond.load1045 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16475,9 +16475,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a1, a2, 128 -; CHECK-RV64-NEXT: bnez a1, .LBB61_782 +; CHECK-RV64-NEXT: bnez a1, .LBB61_786 ; CHECK-RV64-NEXT: j .LBB61_272 -; CHECK-RV64-NEXT: .LBB61_782: # %cond.load1049 +; CHECK-RV64-NEXT: .LBB61_786: # %cond.load1049 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16488,9 +16488,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a1, a2, 256 -; CHECK-RV64-NEXT: bnez a1, .LBB61_783 +; CHECK-RV64-NEXT: bnez a1, .LBB61_787 ; CHECK-RV64-NEXT: j .LBB61_273 -; CHECK-RV64-NEXT: .LBB61_783: # %cond.load1053 +; CHECK-RV64-NEXT: .LBB61_787: # %cond.load1053 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16501,9 +16501,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a1, a2, 512 -; CHECK-RV64-NEXT: bnez a1, .LBB61_784 +; CHECK-RV64-NEXT: bnez a1, .LBB61_788 ; CHECK-RV64-NEXT: j .LBB61_274 -; CHECK-RV64-NEXT: .LBB61_784: # %cond.load1057 +; CHECK-RV64-NEXT: .LBB61_788: # %cond.load1057 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16514,9 +16514,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a1, a2, 1024 -; CHECK-RV64-NEXT: bnez a1, .LBB61_785 +; CHECK-RV64-NEXT: bnez a1, .LBB61_789 ; CHECK-RV64-NEXT: j .LBB61_275 -; CHECK-RV64-NEXT: .LBB61_785: # %cond.load1061 +; CHECK-RV64-NEXT: .LBB61_789: # %cond.load1061 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16527,9 +16527,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 52 -; CHECK-RV64-NEXT: bltz a1, .LBB61_786 +; CHECK-RV64-NEXT: bltz a1, .LBB61_790 ; CHECK-RV64-NEXT: j .LBB61_276 -; CHECK-RV64-NEXT: .LBB61_786: # %cond.load1065 +; CHECK-RV64-NEXT: .LBB61_790: # %cond.load1065 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16540,9 +16540,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 51 -; CHECK-RV64-NEXT: bltz a1, .LBB61_787 +; CHECK-RV64-NEXT: bltz a1, .LBB61_791 ; CHECK-RV64-NEXT: j .LBB61_277 -; CHECK-RV64-NEXT: .LBB61_787: # %cond.load1069 +; CHECK-RV64-NEXT: .LBB61_791: # %cond.load1069 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16553,9 +16553,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 50 -; CHECK-RV64-NEXT: bltz a1, .LBB61_788 +; CHECK-RV64-NEXT: bltz a1, .LBB61_792 ; CHECK-RV64-NEXT: j .LBB61_278 -; CHECK-RV64-NEXT: .LBB61_788: # %cond.load1073 +; CHECK-RV64-NEXT: .LBB61_792: # %cond.load1073 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16566,9 +16566,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 49 -; CHECK-RV64-NEXT: bltz a1, .LBB61_789 +; CHECK-RV64-NEXT: bltz a1, .LBB61_793 ; CHECK-RV64-NEXT: j .LBB61_279 -; CHECK-RV64-NEXT: .LBB61_789: # %cond.load1077 +; CHECK-RV64-NEXT: .LBB61_793: # %cond.load1077 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16579,9 +16579,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 48 -; CHECK-RV64-NEXT: bltz a1, .LBB61_790 +; CHECK-RV64-NEXT: bltz a1, .LBB61_794 ; CHECK-RV64-NEXT: j .LBB61_280 -; CHECK-RV64-NEXT: .LBB61_790: # %cond.load1081 +; CHECK-RV64-NEXT: .LBB61_794: # %cond.load1081 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16592,9 +16592,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 47 -; CHECK-RV64-NEXT: bltz a1, .LBB61_791 +; CHECK-RV64-NEXT: bltz a1, .LBB61_795 ; CHECK-RV64-NEXT: j .LBB61_281 -; CHECK-RV64-NEXT: .LBB61_791: # %cond.load1085 +; CHECK-RV64-NEXT: .LBB61_795: # %cond.load1085 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16605,9 +16605,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 46 -; CHECK-RV64-NEXT: bltz a1, .LBB61_792 +; CHECK-RV64-NEXT: bltz a1, .LBB61_796 ; CHECK-RV64-NEXT: j .LBB61_282 -; CHECK-RV64-NEXT: .LBB61_792: # %cond.load1089 +; CHECK-RV64-NEXT: .LBB61_796: # %cond.load1089 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16618,9 +16618,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 45 -; CHECK-RV64-NEXT: bltz a1, .LBB61_793 +; CHECK-RV64-NEXT: bltz a1, .LBB61_797 ; CHECK-RV64-NEXT: j .LBB61_283 -; CHECK-RV64-NEXT: .LBB61_793: # %cond.load1093 +; CHECK-RV64-NEXT: .LBB61_797: # %cond.load1093 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16631,9 +16631,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 44 -; CHECK-RV64-NEXT: bltz a1, .LBB61_794 +; CHECK-RV64-NEXT: bltz a1, .LBB61_798 ; CHECK-RV64-NEXT: j .LBB61_284 -; CHECK-RV64-NEXT: .LBB61_794: # %cond.load1097 +; CHECK-RV64-NEXT: .LBB61_798: # %cond.load1097 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16644,9 +16644,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 43 -; CHECK-RV64-NEXT: bltz a1, .LBB61_795 +; CHECK-RV64-NEXT: bltz a1, .LBB61_799 ; CHECK-RV64-NEXT: j .LBB61_285 -; CHECK-RV64-NEXT: .LBB61_795: # %cond.load1101 +; CHECK-RV64-NEXT: .LBB61_799: # %cond.load1101 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16657,9 +16657,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 42 -; CHECK-RV64-NEXT: bltz a1, .LBB61_796 +; CHECK-RV64-NEXT: bltz a1, .LBB61_800 ; CHECK-RV64-NEXT: j .LBB61_286 -; CHECK-RV64-NEXT: .LBB61_796: # %cond.load1105 +; CHECK-RV64-NEXT: .LBB61_800: # %cond.load1105 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16670,9 +16670,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 41 -; CHECK-RV64-NEXT: bltz a1, .LBB61_797 +; CHECK-RV64-NEXT: bltz a1, .LBB61_801 ; CHECK-RV64-NEXT: j .LBB61_287 -; CHECK-RV64-NEXT: .LBB61_797: # %cond.load1109 +; CHECK-RV64-NEXT: .LBB61_801: # %cond.load1109 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16683,9 +16683,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 40 -; CHECK-RV64-NEXT: bltz a1, .LBB61_798 +; CHECK-RV64-NEXT: bltz a1, .LBB61_802 ; CHECK-RV64-NEXT: j .LBB61_288 -; CHECK-RV64-NEXT: .LBB61_798: # %cond.load1113 +; CHECK-RV64-NEXT: .LBB61_802: # %cond.load1113 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16696,9 +16696,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 39 -; CHECK-RV64-NEXT: bltz a1, .LBB61_799 +; CHECK-RV64-NEXT: bltz a1, .LBB61_803 ; CHECK-RV64-NEXT: j .LBB61_289 -; CHECK-RV64-NEXT: .LBB61_799: # %cond.load1117 +; CHECK-RV64-NEXT: .LBB61_803: # %cond.load1117 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16709,9 +16709,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 38 -; CHECK-RV64-NEXT: bltz a1, .LBB61_800 +; CHECK-RV64-NEXT: bltz a1, .LBB61_804 ; CHECK-RV64-NEXT: j .LBB61_290 -; CHECK-RV64-NEXT: .LBB61_800: # %cond.load1121 +; CHECK-RV64-NEXT: .LBB61_804: # %cond.load1121 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16722,9 +16722,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 37 -; CHECK-RV64-NEXT: bltz a1, .LBB61_801 +; CHECK-RV64-NEXT: bltz a1, .LBB61_805 ; CHECK-RV64-NEXT: j .LBB61_291 -; CHECK-RV64-NEXT: .LBB61_801: # %cond.load1125 +; CHECK-RV64-NEXT: .LBB61_805: # %cond.load1125 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16735,9 +16735,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 36 -; CHECK-RV64-NEXT: bltz a1, .LBB61_802 +; CHECK-RV64-NEXT: bltz a1, .LBB61_806 ; CHECK-RV64-NEXT: j .LBB61_292 -; CHECK-RV64-NEXT: .LBB61_802: # %cond.load1129 +; CHECK-RV64-NEXT: .LBB61_806: # %cond.load1129 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16748,9 +16748,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 35 -; CHECK-RV64-NEXT: bltz a1, .LBB61_803 +; CHECK-RV64-NEXT: bltz a1, .LBB61_807 ; CHECK-RV64-NEXT: j .LBB61_293 -; CHECK-RV64-NEXT: .LBB61_803: # %cond.load1133 +; CHECK-RV64-NEXT: .LBB61_807: # %cond.load1133 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16761,9 +16761,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 34 -; CHECK-RV64-NEXT: bltz a1, .LBB61_804 +; CHECK-RV64-NEXT: bltz a1, .LBB61_808 ; CHECK-RV64-NEXT: j .LBB61_294 -; CHECK-RV64-NEXT: .LBB61_804: # %cond.load1137 +; CHECK-RV64-NEXT: .LBB61_808: # %cond.load1137 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16774,9 +16774,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 33 -; CHECK-RV64-NEXT: bltz a1, .LBB61_805 +; CHECK-RV64-NEXT: bltz a1, .LBB61_809 ; CHECK-RV64-NEXT: j .LBB61_295 -; CHECK-RV64-NEXT: .LBB61_805: # %cond.load1141 +; CHECK-RV64-NEXT: .LBB61_809: # %cond.load1141 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16787,9 +16787,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 32 -; CHECK-RV64-NEXT: bltz a1, .LBB61_806 +; CHECK-RV64-NEXT: bltz a1, .LBB61_810 ; CHECK-RV64-NEXT: j .LBB61_296 -; CHECK-RV64-NEXT: .LBB61_806: # %cond.load1145 +; CHECK-RV64-NEXT: .LBB61_810: # %cond.load1145 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16800,9 +16800,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 31 -; CHECK-RV64-NEXT: bltz a1, .LBB61_807 +; CHECK-RV64-NEXT: bltz a1, .LBB61_811 ; CHECK-RV64-NEXT: j .LBB61_297 -; CHECK-RV64-NEXT: .LBB61_807: # %cond.load1149 +; CHECK-RV64-NEXT: .LBB61_811: # %cond.load1149 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16813,9 +16813,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 30 -; CHECK-RV64-NEXT: bltz a1, .LBB61_808 +; CHECK-RV64-NEXT: bltz a1, .LBB61_812 ; CHECK-RV64-NEXT: j .LBB61_298 -; CHECK-RV64-NEXT: .LBB61_808: # %cond.load1153 +; CHECK-RV64-NEXT: .LBB61_812: # %cond.load1153 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16826,9 +16826,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 29 -; CHECK-RV64-NEXT: bltz a1, .LBB61_809 +; CHECK-RV64-NEXT: bltz a1, .LBB61_813 ; CHECK-RV64-NEXT: j .LBB61_299 -; CHECK-RV64-NEXT: .LBB61_809: # %cond.load1157 +; CHECK-RV64-NEXT: .LBB61_813: # %cond.load1157 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16839,9 +16839,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 28 -; CHECK-RV64-NEXT: bltz a1, .LBB61_810 +; CHECK-RV64-NEXT: bltz a1, .LBB61_814 ; CHECK-RV64-NEXT: j .LBB61_300 -; CHECK-RV64-NEXT: .LBB61_810: # %cond.load1161 +; CHECK-RV64-NEXT: .LBB61_814: # %cond.load1161 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16852,9 +16852,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 27 -; CHECK-RV64-NEXT: bltz a1, .LBB61_811 +; CHECK-RV64-NEXT: bltz a1, .LBB61_815 ; CHECK-RV64-NEXT: j .LBB61_301 -; CHECK-RV64-NEXT: .LBB61_811: # %cond.load1165 +; CHECK-RV64-NEXT: .LBB61_815: # %cond.load1165 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16865,9 +16865,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 26 -; CHECK-RV64-NEXT: bltz a1, .LBB61_812 +; CHECK-RV64-NEXT: bltz a1, .LBB61_816 ; CHECK-RV64-NEXT: j .LBB61_302 -; CHECK-RV64-NEXT: .LBB61_812: # %cond.load1169 +; CHECK-RV64-NEXT: .LBB61_816: # %cond.load1169 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16878,9 +16878,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 25 -; CHECK-RV64-NEXT: bltz a1, .LBB61_813 +; CHECK-RV64-NEXT: bltz a1, .LBB61_817 ; CHECK-RV64-NEXT: j .LBB61_303 -; CHECK-RV64-NEXT: .LBB61_813: # %cond.load1173 +; CHECK-RV64-NEXT: .LBB61_817: # %cond.load1173 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16891,9 +16891,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 24 -; CHECK-RV64-NEXT: bltz a1, .LBB61_814 +; CHECK-RV64-NEXT: bltz a1, .LBB61_818 ; CHECK-RV64-NEXT: j .LBB61_304 -; CHECK-RV64-NEXT: .LBB61_814: # %cond.load1177 +; CHECK-RV64-NEXT: .LBB61_818: # %cond.load1177 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16904,9 +16904,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 23 -; CHECK-RV64-NEXT: bltz a1, .LBB61_815 +; CHECK-RV64-NEXT: bltz a1, .LBB61_819 ; CHECK-RV64-NEXT: j .LBB61_305 -; CHECK-RV64-NEXT: .LBB61_815: # %cond.load1181 +; CHECK-RV64-NEXT: .LBB61_819: # %cond.load1181 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16917,9 +16917,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 22 -; CHECK-RV64-NEXT: bltz a1, .LBB61_816 +; CHECK-RV64-NEXT: bltz a1, .LBB61_820 ; CHECK-RV64-NEXT: j .LBB61_306 -; CHECK-RV64-NEXT: .LBB61_816: # %cond.load1185 +; CHECK-RV64-NEXT: .LBB61_820: # %cond.load1185 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16930,9 +16930,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 21 -; CHECK-RV64-NEXT: bltz a1, .LBB61_817 +; CHECK-RV64-NEXT: bltz a1, .LBB61_821 ; CHECK-RV64-NEXT: j .LBB61_307 -; CHECK-RV64-NEXT: .LBB61_817: # %cond.load1189 +; CHECK-RV64-NEXT: .LBB61_821: # %cond.load1189 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16943,9 +16943,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 20 -; CHECK-RV64-NEXT: bltz a1, .LBB61_818 +; CHECK-RV64-NEXT: bltz a1, .LBB61_822 ; CHECK-RV64-NEXT: j .LBB61_308 -; CHECK-RV64-NEXT: .LBB61_818: # %cond.load1193 +; CHECK-RV64-NEXT: .LBB61_822: # %cond.load1193 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16956,9 +16956,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 19 -; CHECK-RV64-NEXT: bltz a1, .LBB61_819 +; CHECK-RV64-NEXT: bltz a1, .LBB61_823 ; CHECK-RV64-NEXT: j .LBB61_309 -; CHECK-RV64-NEXT: .LBB61_819: # %cond.load1197 +; CHECK-RV64-NEXT: .LBB61_823: # %cond.load1197 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16969,9 +16969,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 18 -; CHECK-RV64-NEXT: bltz a1, .LBB61_820 +; CHECK-RV64-NEXT: bltz a1, .LBB61_824 ; CHECK-RV64-NEXT: j .LBB61_310 -; CHECK-RV64-NEXT: .LBB61_820: # %cond.load1201 +; CHECK-RV64-NEXT: .LBB61_824: # %cond.load1201 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16982,9 +16982,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 17 -; CHECK-RV64-NEXT: bltz a1, .LBB61_821 +; CHECK-RV64-NEXT: bltz a1, .LBB61_825 ; CHECK-RV64-NEXT: j .LBB61_311 -; CHECK-RV64-NEXT: .LBB61_821: # %cond.load1205 +; CHECK-RV64-NEXT: .LBB61_825: # %cond.load1205 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -16995,9 +16995,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 16 -; CHECK-RV64-NEXT: bltz a1, .LBB61_822 +; CHECK-RV64-NEXT: bltz a1, .LBB61_826 ; CHECK-RV64-NEXT: j .LBB61_312 -; CHECK-RV64-NEXT: .LBB61_822: # %cond.load1209 +; CHECK-RV64-NEXT: .LBB61_826: # %cond.load1209 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17008,9 +17008,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 15 -; CHECK-RV64-NEXT: bltz a1, .LBB61_823 +; CHECK-RV64-NEXT: bltz a1, .LBB61_827 ; CHECK-RV64-NEXT: j .LBB61_313 -; CHECK-RV64-NEXT: .LBB61_823: # %cond.load1213 +; CHECK-RV64-NEXT: .LBB61_827: # %cond.load1213 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17021,9 +17021,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 14 -; CHECK-RV64-NEXT: bltz a1, .LBB61_824 +; CHECK-RV64-NEXT: bltz a1, .LBB61_828 ; CHECK-RV64-NEXT: j .LBB61_314 -; CHECK-RV64-NEXT: .LBB61_824: # %cond.load1217 +; CHECK-RV64-NEXT: .LBB61_828: # %cond.load1217 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17034,9 +17034,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 13 -; CHECK-RV64-NEXT: bltz a1, .LBB61_825 +; CHECK-RV64-NEXT: bltz a1, .LBB61_829 ; CHECK-RV64-NEXT: j .LBB61_315 -; CHECK-RV64-NEXT: .LBB61_825: # %cond.load1221 +; CHECK-RV64-NEXT: .LBB61_829: # %cond.load1221 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17047,9 +17047,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 12 -; CHECK-RV64-NEXT: bltz a1, .LBB61_826 +; CHECK-RV64-NEXT: bltz a1, .LBB61_830 ; CHECK-RV64-NEXT: j .LBB61_316 -; CHECK-RV64-NEXT: .LBB61_826: # %cond.load1225 +; CHECK-RV64-NEXT: .LBB61_830: # %cond.load1225 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17060,9 +17060,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 11 -; CHECK-RV64-NEXT: bltz a1, .LBB61_827 +; CHECK-RV64-NEXT: bltz a1, .LBB61_831 ; CHECK-RV64-NEXT: j .LBB61_317 -; CHECK-RV64-NEXT: .LBB61_827: # %cond.load1229 +; CHECK-RV64-NEXT: .LBB61_831: # %cond.load1229 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17073,9 +17073,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 10 -; CHECK-RV64-NEXT: bltz a1, .LBB61_828 +; CHECK-RV64-NEXT: bltz a1, .LBB61_832 ; CHECK-RV64-NEXT: j .LBB61_318 -; CHECK-RV64-NEXT: .LBB61_828: # %cond.load1233 +; CHECK-RV64-NEXT: .LBB61_832: # %cond.load1233 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17086,9 +17086,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 9 -; CHECK-RV64-NEXT: bltz a1, .LBB61_829 +; CHECK-RV64-NEXT: bltz a1, .LBB61_833 ; CHECK-RV64-NEXT: j .LBB61_319 -; CHECK-RV64-NEXT: .LBB61_829: # %cond.load1237 +; CHECK-RV64-NEXT: .LBB61_833: # %cond.load1237 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17099,9 +17099,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 8 -; CHECK-RV64-NEXT: bltz a1, .LBB61_830 +; CHECK-RV64-NEXT: bltz a1, .LBB61_834 ; CHECK-RV64-NEXT: j .LBB61_320 -; CHECK-RV64-NEXT: .LBB61_830: # %cond.load1241 +; CHECK-RV64-NEXT: .LBB61_834: # %cond.load1241 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17112,9 +17112,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 7 -; CHECK-RV64-NEXT: bltz a1, .LBB61_831 +; CHECK-RV64-NEXT: bltz a1, .LBB61_835 ; CHECK-RV64-NEXT: j .LBB61_321 -; CHECK-RV64-NEXT: .LBB61_831: # %cond.load1245 +; CHECK-RV64-NEXT: .LBB61_835: # %cond.load1245 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17125,9 +17125,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 6 -; CHECK-RV64-NEXT: bltz a1, .LBB61_832 +; CHECK-RV64-NEXT: bltz a1, .LBB61_836 ; CHECK-RV64-NEXT: j .LBB61_322 -; CHECK-RV64-NEXT: .LBB61_832: # %cond.load1249 +; CHECK-RV64-NEXT: .LBB61_836: # %cond.load1249 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17138,9 +17138,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 5 -; CHECK-RV64-NEXT: bltz a1, .LBB61_833 +; CHECK-RV64-NEXT: bltz a1, .LBB61_837 ; CHECK-RV64-NEXT: j .LBB61_323 -; CHECK-RV64-NEXT: .LBB61_833: # %cond.load1253 +; CHECK-RV64-NEXT: .LBB61_837: # %cond.load1253 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17151,9 +17151,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 4 -; CHECK-RV64-NEXT: bltz a1, .LBB61_834 +; CHECK-RV64-NEXT: bltz a1, .LBB61_838 ; CHECK-RV64-NEXT: j .LBB61_324 -; CHECK-RV64-NEXT: .LBB61_834: # %cond.load1257 +; CHECK-RV64-NEXT: .LBB61_838: # %cond.load1257 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17164,9 +17164,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 3 -; CHECK-RV64-NEXT: bltz a1, .LBB61_835 +; CHECK-RV64-NEXT: bltz a1, .LBB61_839 ; CHECK-RV64-NEXT: j .LBB61_325 -; CHECK-RV64-NEXT: .LBB61_835: # %cond.load1261 +; CHECK-RV64-NEXT: .LBB61_839: # %cond.load1261 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17177,11 +17177,11 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 2 -; CHECK-RV64-NEXT: bgez a1, .LBB61_1029 +; CHECK-RV64-NEXT: bgez a1, .LBB61_840 ; CHECK-RV64-NEXT: j .LBB61_326 -; CHECK-RV64-NEXT: .LBB61_1029: # %cond.load1261 +; CHECK-RV64-NEXT: .LBB61_840: # %cond.load1261 ; CHECK-RV64-NEXT: j .LBB61_327 -; CHECK-RV64-NEXT: .LBB61_836: # %cond.load1273 +; CHECK-RV64-NEXT: .LBB61_841: # %cond.load1273 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vmv.s.x v16, a2 ; CHECK-RV64-NEXT: li a2, 320 @@ -17190,9 +17190,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a2, a1, 1 -; CHECK-RV64-NEXT: bnez a2, .LBB61_837 +; CHECK-RV64-NEXT: bnez a2, .LBB61_842 ; CHECK-RV64-NEXT: j .LBB61_331 -; CHECK-RV64-NEXT: .LBB61_837: # %cond.load1277 +; CHECK-RV64-NEXT: .LBB61_842: # %cond.load1277 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17203,9 +17203,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a2, a1, 2 -; CHECK-RV64-NEXT: bnez a2, .LBB61_838 +; CHECK-RV64-NEXT: bnez a2, .LBB61_843 ; CHECK-RV64-NEXT: j .LBB61_332 -; CHECK-RV64-NEXT: .LBB61_838: # %cond.load1281 +; CHECK-RV64-NEXT: .LBB61_843: # %cond.load1281 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17216,9 +17216,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a2, a1, 4 -; CHECK-RV64-NEXT: bnez a2, .LBB61_839 +; CHECK-RV64-NEXT: bnez a2, .LBB61_844 ; CHECK-RV64-NEXT: j .LBB61_333 -; CHECK-RV64-NEXT: .LBB61_839: # %cond.load1285 +; CHECK-RV64-NEXT: .LBB61_844: # %cond.load1285 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17229,9 +17229,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a2, a1, 8 -; CHECK-RV64-NEXT: bnez a2, .LBB61_840 +; CHECK-RV64-NEXT: bnez a2, .LBB61_845 ; CHECK-RV64-NEXT: j .LBB61_334 -; CHECK-RV64-NEXT: .LBB61_840: # %cond.load1289 +; CHECK-RV64-NEXT: .LBB61_845: # %cond.load1289 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17242,9 +17242,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a2, a1, 16 -; CHECK-RV64-NEXT: bnez a2, .LBB61_841 +; CHECK-RV64-NEXT: bnez a2, .LBB61_846 ; CHECK-RV64-NEXT: j .LBB61_335 -; CHECK-RV64-NEXT: .LBB61_841: # %cond.load1293 +; CHECK-RV64-NEXT: .LBB61_846: # %cond.load1293 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17255,9 +17255,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a2, a1, 32 -; CHECK-RV64-NEXT: bnez a2, .LBB61_842 +; CHECK-RV64-NEXT: bnez a2, .LBB61_847 ; CHECK-RV64-NEXT: j .LBB61_336 -; CHECK-RV64-NEXT: .LBB61_842: # %cond.load1297 +; CHECK-RV64-NEXT: .LBB61_847: # %cond.load1297 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17268,9 +17268,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a2, a1, 64 -; CHECK-RV64-NEXT: bnez a2, .LBB61_843 +; CHECK-RV64-NEXT: bnez a2, .LBB61_848 ; CHECK-RV64-NEXT: j .LBB61_337 -; CHECK-RV64-NEXT: .LBB61_843: # %cond.load1301 +; CHECK-RV64-NEXT: .LBB61_848: # %cond.load1301 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17281,9 +17281,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a2, a1, 128 -; CHECK-RV64-NEXT: bnez a2, .LBB61_844 +; CHECK-RV64-NEXT: bnez a2, .LBB61_849 ; CHECK-RV64-NEXT: j .LBB61_338 -; CHECK-RV64-NEXT: .LBB61_844: # %cond.load1305 +; CHECK-RV64-NEXT: .LBB61_849: # %cond.load1305 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17294,9 +17294,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a2, a1, 256 -; CHECK-RV64-NEXT: bnez a2, .LBB61_845 +; CHECK-RV64-NEXT: bnez a2, .LBB61_850 ; CHECK-RV64-NEXT: j .LBB61_339 -; CHECK-RV64-NEXT: .LBB61_845: # %cond.load1309 +; CHECK-RV64-NEXT: .LBB61_850: # %cond.load1309 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17307,9 +17307,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a2, a1, 512 -; CHECK-RV64-NEXT: bnez a2, .LBB61_846 +; CHECK-RV64-NEXT: bnez a2, .LBB61_851 ; CHECK-RV64-NEXT: j .LBB61_340 -; CHECK-RV64-NEXT: .LBB61_846: # %cond.load1313 +; CHECK-RV64-NEXT: .LBB61_851: # %cond.load1313 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17320,9 +17320,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a2, a1, 1024 -; CHECK-RV64-NEXT: bnez a2, .LBB61_847 +; CHECK-RV64-NEXT: bnez a2, .LBB61_852 ; CHECK-RV64-NEXT: j .LBB61_341 -; CHECK-RV64-NEXT: .LBB61_847: # %cond.load1317 +; CHECK-RV64-NEXT: .LBB61_852: # %cond.load1317 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17333,9 +17333,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 52 -; CHECK-RV64-NEXT: bltz a2, .LBB61_848 +; CHECK-RV64-NEXT: bltz a2, .LBB61_853 ; CHECK-RV64-NEXT: j .LBB61_342 -; CHECK-RV64-NEXT: .LBB61_848: # %cond.load1321 +; CHECK-RV64-NEXT: .LBB61_853: # %cond.load1321 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17346,9 +17346,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 51 -; CHECK-RV64-NEXT: bltz a2, .LBB61_849 +; CHECK-RV64-NEXT: bltz a2, .LBB61_854 ; CHECK-RV64-NEXT: j .LBB61_343 -; CHECK-RV64-NEXT: .LBB61_849: # %cond.load1325 +; CHECK-RV64-NEXT: .LBB61_854: # %cond.load1325 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17359,9 +17359,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 50 -; CHECK-RV64-NEXT: bltz a2, .LBB61_850 +; CHECK-RV64-NEXT: bltz a2, .LBB61_855 ; CHECK-RV64-NEXT: j .LBB61_344 -; CHECK-RV64-NEXT: .LBB61_850: # %cond.load1329 +; CHECK-RV64-NEXT: .LBB61_855: # %cond.load1329 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17372,9 +17372,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 49 -; CHECK-RV64-NEXT: bltz a2, .LBB61_851 +; CHECK-RV64-NEXT: bltz a2, .LBB61_856 ; CHECK-RV64-NEXT: j .LBB61_345 -; CHECK-RV64-NEXT: .LBB61_851: # %cond.load1333 +; CHECK-RV64-NEXT: .LBB61_856: # %cond.load1333 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17385,9 +17385,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 48 -; CHECK-RV64-NEXT: bltz a2, .LBB61_852 +; CHECK-RV64-NEXT: bltz a2, .LBB61_857 ; CHECK-RV64-NEXT: j .LBB61_346 -; CHECK-RV64-NEXT: .LBB61_852: # %cond.load1337 +; CHECK-RV64-NEXT: .LBB61_857: # %cond.load1337 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17398,9 +17398,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 47 -; CHECK-RV64-NEXT: bltz a2, .LBB61_853 +; CHECK-RV64-NEXT: bltz a2, .LBB61_858 ; CHECK-RV64-NEXT: j .LBB61_347 -; CHECK-RV64-NEXT: .LBB61_853: # %cond.load1341 +; CHECK-RV64-NEXT: .LBB61_858: # %cond.load1341 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17411,9 +17411,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 46 -; CHECK-RV64-NEXT: bltz a2, .LBB61_854 +; CHECK-RV64-NEXT: bltz a2, .LBB61_859 ; CHECK-RV64-NEXT: j .LBB61_348 -; CHECK-RV64-NEXT: .LBB61_854: # %cond.load1345 +; CHECK-RV64-NEXT: .LBB61_859: # %cond.load1345 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17424,9 +17424,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 45 -; CHECK-RV64-NEXT: bltz a2, .LBB61_855 +; CHECK-RV64-NEXT: bltz a2, .LBB61_860 ; CHECK-RV64-NEXT: j .LBB61_349 -; CHECK-RV64-NEXT: .LBB61_855: # %cond.load1349 +; CHECK-RV64-NEXT: .LBB61_860: # %cond.load1349 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17437,9 +17437,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 44 -; CHECK-RV64-NEXT: bltz a2, .LBB61_856 +; CHECK-RV64-NEXT: bltz a2, .LBB61_861 ; CHECK-RV64-NEXT: j .LBB61_350 -; CHECK-RV64-NEXT: .LBB61_856: # %cond.load1353 +; CHECK-RV64-NEXT: .LBB61_861: # %cond.load1353 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17450,9 +17450,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 43 -; CHECK-RV64-NEXT: bltz a2, .LBB61_857 +; CHECK-RV64-NEXT: bltz a2, .LBB61_862 ; CHECK-RV64-NEXT: j .LBB61_351 -; CHECK-RV64-NEXT: .LBB61_857: # %cond.load1357 +; CHECK-RV64-NEXT: .LBB61_862: # %cond.load1357 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17463,9 +17463,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 42 -; CHECK-RV64-NEXT: bltz a2, .LBB61_858 +; CHECK-RV64-NEXT: bltz a2, .LBB61_863 ; CHECK-RV64-NEXT: j .LBB61_352 -; CHECK-RV64-NEXT: .LBB61_858: # %cond.load1361 +; CHECK-RV64-NEXT: .LBB61_863: # %cond.load1361 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17476,9 +17476,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 41 -; CHECK-RV64-NEXT: bltz a2, .LBB61_859 +; CHECK-RV64-NEXT: bltz a2, .LBB61_864 ; CHECK-RV64-NEXT: j .LBB61_353 -; CHECK-RV64-NEXT: .LBB61_859: # %cond.load1365 +; CHECK-RV64-NEXT: .LBB61_864: # %cond.load1365 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17489,9 +17489,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 40 -; CHECK-RV64-NEXT: bltz a2, .LBB61_860 +; CHECK-RV64-NEXT: bltz a2, .LBB61_865 ; CHECK-RV64-NEXT: j .LBB61_354 -; CHECK-RV64-NEXT: .LBB61_860: # %cond.load1369 +; CHECK-RV64-NEXT: .LBB61_865: # %cond.load1369 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17502,9 +17502,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 39 -; CHECK-RV64-NEXT: bltz a2, .LBB61_861 +; CHECK-RV64-NEXT: bltz a2, .LBB61_866 ; CHECK-RV64-NEXT: j .LBB61_355 -; CHECK-RV64-NEXT: .LBB61_861: # %cond.load1373 +; CHECK-RV64-NEXT: .LBB61_866: # %cond.load1373 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17515,9 +17515,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 38 -; CHECK-RV64-NEXT: bltz a2, .LBB61_862 +; CHECK-RV64-NEXT: bltz a2, .LBB61_867 ; CHECK-RV64-NEXT: j .LBB61_356 -; CHECK-RV64-NEXT: .LBB61_862: # %cond.load1377 +; CHECK-RV64-NEXT: .LBB61_867: # %cond.load1377 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17528,9 +17528,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 37 -; CHECK-RV64-NEXT: bltz a2, .LBB61_863 +; CHECK-RV64-NEXT: bltz a2, .LBB61_868 ; CHECK-RV64-NEXT: j .LBB61_357 -; CHECK-RV64-NEXT: .LBB61_863: # %cond.load1381 +; CHECK-RV64-NEXT: .LBB61_868: # %cond.load1381 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17541,9 +17541,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 36 -; CHECK-RV64-NEXT: bltz a2, .LBB61_864 +; CHECK-RV64-NEXT: bltz a2, .LBB61_869 ; CHECK-RV64-NEXT: j .LBB61_358 -; CHECK-RV64-NEXT: .LBB61_864: # %cond.load1385 +; CHECK-RV64-NEXT: .LBB61_869: # %cond.load1385 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17554,9 +17554,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 35 -; CHECK-RV64-NEXT: bltz a2, .LBB61_865 +; CHECK-RV64-NEXT: bltz a2, .LBB61_870 ; CHECK-RV64-NEXT: j .LBB61_359 -; CHECK-RV64-NEXT: .LBB61_865: # %cond.load1389 +; CHECK-RV64-NEXT: .LBB61_870: # %cond.load1389 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17567,9 +17567,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 34 -; CHECK-RV64-NEXT: bltz a2, .LBB61_866 +; CHECK-RV64-NEXT: bltz a2, .LBB61_871 ; CHECK-RV64-NEXT: j .LBB61_360 -; CHECK-RV64-NEXT: .LBB61_866: # %cond.load1393 +; CHECK-RV64-NEXT: .LBB61_871: # %cond.load1393 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17580,9 +17580,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 33 -; CHECK-RV64-NEXT: bltz a2, .LBB61_867 +; CHECK-RV64-NEXT: bltz a2, .LBB61_872 ; CHECK-RV64-NEXT: j .LBB61_361 -; CHECK-RV64-NEXT: .LBB61_867: # %cond.load1397 +; CHECK-RV64-NEXT: .LBB61_872: # %cond.load1397 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17593,9 +17593,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 32 -; CHECK-RV64-NEXT: bltz a2, .LBB61_868 +; CHECK-RV64-NEXT: bltz a2, .LBB61_873 ; CHECK-RV64-NEXT: j .LBB61_362 -; CHECK-RV64-NEXT: .LBB61_868: # %cond.load1401 +; CHECK-RV64-NEXT: .LBB61_873: # %cond.load1401 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17606,9 +17606,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 31 -; CHECK-RV64-NEXT: bltz a2, .LBB61_869 +; CHECK-RV64-NEXT: bltz a2, .LBB61_874 ; CHECK-RV64-NEXT: j .LBB61_363 -; CHECK-RV64-NEXT: .LBB61_869: # %cond.load1405 +; CHECK-RV64-NEXT: .LBB61_874: # %cond.load1405 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17619,9 +17619,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 30 -; CHECK-RV64-NEXT: bltz a2, .LBB61_870 +; CHECK-RV64-NEXT: bltz a2, .LBB61_875 ; CHECK-RV64-NEXT: j .LBB61_364 -; CHECK-RV64-NEXT: .LBB61_870: # %cond.load1409 +; CHECK-RV64-NEXT: .LBB61_875: # %cond.load1409 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17632,9 +17632,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 29 -; CHECK-RV64-NEXT: bltz a2, .LBB61_871 +; CHECK-RV64-NEXT: bltz a2, .LBB61_876 ; CHECK-RV64-NEXT: j .LBB61_365 -; CHECK-RV64-NEXT: .LBB61_871: # %cond.load1413 +; CHECK-RV64-NEXT: .LBB61_876: # %cond.load1413 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17645,9 +17645,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 28 -; CHECK-RV64-NEXT: bltz a2, .LBB61_872 +; CHECK-RV64-NEXT: bltz a2, .LBB61_877 ; CHECK-RV64-NEXT: j .LBB61_366 -; CHECK-RV64-NEXT: .LBB61_872: # %cond.load1417 +; CHECK-RV64-NEXT: .LBB61_877: # %cond.load1417 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17658,9 +17658,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 27 -; CHECK-RV64-NEXT: bltz a2, .LBB61_873 +; CHECK-RV64-NEXT: bltz a2, .LBB61_878 ; CHECK-RV64-NEXT: j .LBB61_367 -; CHECK-RV64-NEXT: .LBB61_873: # %cond.load1421 +; CHECK-RV64-NEXT: .LBB61_878: # %cond.load1421 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17671,9 +17671,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 26 -; CHECK-RV64-NEXT: bltz a2, .LBB61_874 +; CHECK-RV64-NEXT: bltz a2, .LBB61_879 ; CHECK-RV64-NEXT: j .LBB61_368 -; CHECK-RV64-NEXT: .LBB61_874: # %cond.load1425 +; CHECK-RV64-NEXT: .LBB61_879: # %cond.load1425 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17684,9 +17684,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 25 -; CHECK-RV64-NEXT: bltz a2, .LBB61_875 +; CHECK-RV64-NEXT: bltz a2, .LBB61_880 ; CHECK-RV64-NEXT: j .LBB61_369 -; CHECK-RV64-NEXT: .LBB61_875: # %cond.load1429 +; CHECK-RV64-NEXT: .LBB61_880: # %cond.load1429 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17697,9 +17697,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 24 -; CHECK-RV64-NEXT: bltz a2, .LBB61_876 +; CHECK-RV64-NEXT: bltz a2, .LBB61_881 ; CHECK-RV64-NEXT: j .LBB61_370 -; CHECK-RV64-NEXT: .LBB61_876: # %cond.load1433 +; CHECK-RV64-NEXT: .LBB61_881: # %cond.load1433 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17710,9 +17710,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 23 -; CHECK-RV64-NEXT: bltz a2, .LBB61_877 +; CHECK-RV64-NEXT: bltz a2, .LBB61_882 ; CHECK-RV64-NEXT: j .LBB61_371 -; CHECK-RV64-NEXT: .LBB61_877: # %cond.load1437 +; CHECK-RV64-NEXT: .LBB61_882: # %cond.load1437 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17723,9 +17723,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 22 -; CHECK-RV64-NEXT: bltz a2, .LBB61_878 +; CHECK-RV64-NEXT: bltz a2, .LBB61_883 ; CHECK-RV64-NEXT: j .LBB61_372 -; CHECK-RV64-NEXT: .LBB61_878: # %cond.load1441 +; CHECK-RV64-NEXT: .LBB61_883: # %cond.load1441 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17736,9 +17736,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 21 -; CHECK-RV64-NEXT: bltz a2, .LBB61_879 +; CHECK-RV64-NEXT: bltz a2, .LBB61_884 ; CHECK-RV64-NEXT: j .LBB61_373 -; CHECK-RV64-NEXT: .LBB61_879: # %cond.load1445 +; CHECK-RV64-NEXT: .LBB61_884: # %cond.load1445 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17749,9 +17749,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 20 -; CHECK-RV64-NEXT: bltz a2, .LBB61_880 +; CHECK-RV64-NEXT: bltz a2, .LBB61_885 ; CHECK-RV64-NEXT: j .LBB61_374 -; CHECK-RV64-NEXT: .LBB61_880: # %cond.load1449 +; CHECK-RV64-NEXT: .LBB61_885: # %cond.load1449 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17762,9 +17762,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 19 -; CHECK-RV64-NEXT: bltz a2, .LBB61_881 +; CHECK-RV64-NEXT: bltz a2, .LBB61_886 ; CHECK-RV64-NEXT: j .LBB61_375 -; CHECK-RV64-NEXT: .LBB61_881: # %cond.load1453 +; CHECK-RV64-NEXT: .LBB61_886: # %cond.load1453 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17775,9 +17775,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 18 -; CHECK-RV64-NEXT: bltz a2, .LBB61_882 +; CHECK-RV64-NEXT: bltz a2, .LBB61_887 ; CHECK-RV64-NEXT: j .LBB61_376 -; CHECK-RV64-NEXT: .LBB61_882: # %cond.load1457 +; CHECK-RV64-NEXT: .LBB61_887: # %cond.load1457 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17788,9 +17788,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 17 -; CHECK-RV64-NEXT: bltz a2, .LBB61_883 +; CHECK-RV64-NEXT: bltz a2, .LBB61_888 ; CHECK-RV64-NEXT: j .LBB61_377 -; CHECK-RV64-NEXT: .LBB61_883: # %cond.load1461 +; CHECK-RV64-NEXT: .LBB61_888: # %cond.load1461 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17801,9 +17801,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 16 -; CHECK-RV64-NEXT: bltz a2, .LBB61_884 +; CHECK-RV64-NEXT: bltz a2, .LBB61_889 ; CHECK-RV64-NEXT: j .LBB61_378 -; CHECK-RV64-NEXT: .LBB61_884: # %cond.load1465 +; CHECK-RV64-NEXT: .LBB61_889: # %cond.load1465 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17814,9 +17814,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 15 -; CHECK-RV64-NEXT: bltz a2, .LBB61_885 +; CHECK-RV64-NEXT: bltz a2, .LBB61_890 ; CHECK-RV64-NEXT: j .LBB61_379 -; CHECK-RV64-NEXT: .LBB61_885: # %cond.load1469 +; CHECK-RV64-NEXT: .LBB61_890: # %cond.load1469 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17827,9 +17827,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 14 -; CHECK-RV64-NEXT: bltz a2, .LBB61_886 +; CHECK-RV64-NEXT: bltz a2, .LBB61_891 ; CHECK-RV64-NEXT: j .LBB61_380 -; CHECK-RV64-NEXT: .LBB61_886: # %cond.load1473 +; CHECK-RV64-NEXT: .LBB61_891: # %cond.load1473 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17840,9 +17840,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 13 -; CHECK-RV64-NEXT: bltz a2, .LBB61_887 +; CHECK-RV64-NEXT: bltz a2, .LBB61_892 ; CHECK-RV64-NEXT: j .LBB61_381 -; CHECK-RV64-NEXT: .LBB61_887: # %cond.load1477 +; CHECK-RV64-NEXT: .LBB61_892: # %cond.load1477 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17853,9 +17853,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 12 -; CHECK-RV64-NEXT: bltz a2, .LBB61_888 +; CHECK-RV64-NEXT: bltz a2, .LBB61_893 ; CHECK-RV64-NEXT: j .LBB61_382 -; CHECK-RV64-NEXT: .LBB61_888: # %cond.load1481 +; CHECK-RV64-NEXT: .LBB61_893: # %cond.load1481 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17866,9 +17866,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 11 -; CHECK-RV64-NEXT: bltz a2, .LBB61_889 +; CHECK-RV64-NEXT: bltz a2, .LBB61_894 ; CHECK-RV64-NEXT: j .LBB61_383 -; CHECK-RV64-NEXT: .LBB61_889: # %cond.load1485 +; CHECK-RV64-NEXT: .LBB61_894: # %cond.load1485 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17879,9 +17879,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 10 -; CHECK-RV64-NEXT: bltz a2, .LBB61_890 +; CHECK-RV64-NEXT: bltz a2, .LBB61_895 ; CHECK-RV64-NEXT: j .LBB61_384 -; CHECK-RV64-NEXT: .LBB61_890: # %cond.load1489 +; CHECK-RV64-NEXT: .LBB61_895: # %cond.load1489 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17892,9 +17892,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 9 -; CHECK-RV64-NEXT: bltz a2, .LBB61_891 +; CHECK-RV64-NEXT: bltz a2, .LBB61_896 ; CHECK-RV64-NEXT: j .LBB61_385 -; CHECK-RV64-NEXT: .LBB61_891: # %cond.load1493 +; CHECK-RV64-NEXT: .LBB61_896: # %cond.load1493 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17905,9 +17905,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 8 -; CHECK-RV64-NEXT: bltz a2, .LBB61_892 +; CHECK-RV64-NEXT: bltz a2, .LBB61_897 ; CHECK-RV64-NEXT: j .LBB61_386 -; CHECK-RV64-NEXT: .LBB61_892: # %cond.load1497 +; CHECK-RV64-NEXT: .LBB61_897: # %cond.load1497 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17918,9 +17918,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 7 -; CHECK-RV64-NEXT: bltz a2, .LBB61_893 +; CHECK-RV64-NEXT: bltz a2, .LBB61_898 ; CHECK-RV64-NEXT: j .LBB61_387 -; CHECK-RV64-NEXT: .LBB61_893: # %cond.load1501 +; CHECK-RV64-NEXT: .LBB61_898: # %cond.load1501 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17931,9 +17931,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 6 -; CHECK-RV64-NEXT: bltz a2, .LBB61_894 +; CHECK-RV64-NEXT: bltz a2, .LBB61_899 ; CHECK-RV64-NEXT: j .LBB61_388 -; CHECK-RV64-NEXT: .LBB61_894: # %cond.load1505 +; CHECK-RV64-NEXT: .LBB61_899: # %cond.load1505 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17944,9 +17944,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 5 -; CHECK-RV64-NEXT: bltz a2, .LBB61_895 +; CHECK-RV64-NEXT: bltz a2, .LBB61_900 ; CHECK-RV64-NEXT: j .LBB61_389 -; CHECK-RV64-NEXT: .LBB61_895: # %cond.load1509 +; CHECK-RV64-NEXT: .LBB61_900: # %cond.load1509 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17957,9 +17957,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 4 -; CHECK-RV64-NEXT: bltz a2, .LBB61_896 +; CHECK-RV64-NEXT: bltz a2, .LBB61_901 ; CHECK-RV64-NEXT: j .LBB61_390 -; CHECK-RV64-NEXT: .LBB61_896: # %cond.load1513 +; CHECK-RV64-NEXT: .LBB61_901: # %cond.load1513 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17970,9 +17970,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 3 -; CHECK-RV64-NEXT: bltz a2, .LBB61_897 +; CHECK-RV64-NEXT: bltz a2, .LBB61_902 ; CHECK-RV64-NEXT: j .LBB61_391 -; CHECK-RV64-NEXT: .LBB61_897: # %cond.load1517 +; CHECK-RV64-NEXT: .LBB61_902: # %cond.load1517 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -17983,11 +17983,11 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 2 -; CHECK-RV64-NEXT: bgez a2, .LBB61_1030 +; CHECK-RV64-NEXT: bgez a2, .LBB61_903 ; CHECK-RV64-NEXT: j .LBB61_392 -; CHECK-RV64-NEXT: .LBB61_1030: # %cond.load1517 +; CHECK-RV64-NEXT: .LBB61_903: # %cond.load1517 ; CHECK-RV64-NEXT: j .LBB61_393 -; CHECK-RV64-NEXT: .LBB61_898: # %cond.load1529 +; CHECK-RV64-NEXT: .LBB61_904: # %cond.load1529 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: vmv.s.x v16, a1 ; CHECK-RV64-NEXT: li a1, 384 @@ -17996,9 +17996,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a1, a2, 1 -; CHECK-RV64-NEXT: bnez a1, .LBB61_899 +; CHECK-RV64-NEXT: bnez a1, .LBB61_905 ; CHECK-RV64-NEXT: j .LBB61_397 -; CHECK-RV64-NEXT: .LBB61_899: # %cond.load1533 +; CHECK-RV64-NEXT: .LBB61_905: # %cond.load1533 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18009,9 +18009,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a1, a2, 2 -; CHECK-RV64-NEXT: bnez a1, .LBB61_900 +; CHECK-RV64-NEXT: bnez a1, .LBB61_906 ; CHECK-RV64-NEXT: j .LBB61_398 -; CHECK-RV64-NEXT: .LBB61_900: # %cond.load1537 +; CHECK-RV64-NEXT: .LBB61_906: # %cond.load1537 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18022,9 +18022,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a1, a2, 4 -; CHECK-RV64-NEXT: bnez a1, .LBB61_901 +; CHECK-RV64-NEXT: bnez a1, .LBB61_907 ; CHECK-RV64-NEXT: j .LBB61_399 -; CHECK-RV64-NEXT: .LBB61_901: # %cond.load1541 +; CHECK-RV64-NEXT: .LBB61_907: # %cond.load1541 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18035,9 +18035,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a1, a2, 8 -; CHECK-RV64-NEXT: bnez a1, .LBB61_902 +; CHECK-RV64-NEXT: bnez a1, .LBB61_908 ; CHECK-RV64-NEXT: j .LBB61_400 -; CHECK-RV64-NEXT: .LBB61_902: # %cond.load1545 +; CHECK-RV64-NEXT: .LBB61_908: # %cond.load1545 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18048,9 +18048,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a1, a2, 16 -; CHECK-RV64-NEXT: bnez a1, .LBB61_903 +; CHECK-RV64-NEXT: bnez a1, .LBB61_909 ; CHECK-RV64-NEXT: j .LBB61_401 -; CHECK-RV64-NEXT: .LBB61_903: # %cond.load1549 +; CHECK-RV64-NEXT: .LBB61_909: # %cond.load1549 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18061,9 +18061,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a1, a2, 32 -; CHECK-RV64-NEXT: bnez a1, .LBB61_904 +; CHECK-RV64-NEXT: bnez a1, .LBB61_910 ; CHECK-RV64-NEXT: j .LBB61_402 -; CHECK-RV64-NEXT: .LBB61_904: # %cond.load1553 +; CHECK-RV64-NEXT: .LBB61_910: # %cond.load1553 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18074,9 +18074,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a1, a2, 64 -; CHECK-RV64-NEXT: bnez a1, .LBB61_905 +; CHECK-RV64-NEXT: bnez a1, .LBB61_911 ; CHECK-RV64-NEXT: j .LBB61_403 -; CHECK-RV64-NEXT: .LBB61_905: # %cond.load1557 +; CHECK-RV64-NEXT: .LBB61_911: # %cond.load1557 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18087,9 +18087,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a1, a2, 128 -; CHECK-RV64-NEXT: bnez a1, .LBB61_906 +; CHECK-RV64-NEXT: bnez a1, .LBB61_912 ; CHECK-RV64-NEXT: j .LBB61_404 -; CHECK-RV64-NEXT: .LBB61_906: # %cond.load1561 +; CHECK-RV64-NEXT: .LBB61_912: # %cond.load1561 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18100,9 +18100,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a1, a2, 256 -; CHECK-RV64-NEXT: bnez a1, .LBB61_907 +; CHECK-RV64-NEXT: bnez a1, .LBB61_913 ; CHECK-RV64-NEXT: j .LBB61_405 -; CHECK-RV64-NEXT: .LBB61_907: # %cond.load1565 +; CHECK-RV64-NEXT: .LBB61_913: # %cond.load1565 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18113,9 +18113,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a1, a2, 512 -; CHECK-RV64-NEXT: bnez a1, .LBB61_908 +; CHECK-RV64-NEXT: bnez a1, .LBB61_914 ; CHECK-RV64-NEXT: j .LBB61_406 -; CHECK-RV64-NEXT: .LBB61_908: # %cond.load1569 +; CHECK-RV64-NEXT: .LBB61_914: # %cond.load1569 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18126,9 +18126,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a1, a2, 1024 -; CHECK-RV64-NEXT: bnez a1, .LBB61_909 +; CHECK-RV64-NEXT: bnez a1, .LBB61_915 ; CHECK-RV64-NEXT: j .LBB61_407 -; CHECK-RV64-NEXT: .LBB61_909: # %cond.load1573 +; CHECK-RV64-NEXT: .LBB61_915: # %cond.load1573 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18139,9 +18139,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 52 -; CHECK-RV64-NEXT: bltz a1, .LBB61_910 +; CHECK-RV64-NEXT: bltz a1, .LBB61_916 ; CHECK-RV64-NEXT: j .LBB61_408 -; CHECK-RV64-NEXT: .LBB61_910: # %cond.load1577 +; CHECK-RV64-NEXT: .LBB61_916: # %cond.load1577 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18152,9 +18152,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 51 -; CHECK-RV64-NEXT: bltz a1, .LBB61_911 +; CHECK-RV64-NEXT: bltz a1, .LBB61_917 ; CHECK-RV64-NEXT: j .LBB61_409 -; CHECK-RV64-NEXT: .LBB61_911: # %cond.load1581 +; CHECK-RV64-NEXT: .LBB61_917: # %cond.load1581 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18165,9 +18165,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 50 -; CHECK-RV64-NEXT: bltz a1, .LBB61_912 +; CHECK-RV64-NEXT: bltz a1, .LBB61_918 ; CHECK-RV64-NEXT: j .LBB61_410 -; CHECK-RV64-NEXT: .LBB61_912: # %cond.load1585 +; CHECK-RV64-NEXT: .LBB61_918: # %cond.load1585 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18178,9 +18178,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 49 -; CHECK-RV64-NEXT: bltz a1, .LBB61_913 +; CHECK-RV64-NEXT: bltz a1, .LBB61_919 ; CHECK-RV64-NEXT: j .LBB61_411 -; CHECK-RV64-NEXT: .LBB61_913: # %cond.load1589 +; CHECK-RV64-NEXT: .LBB61_919: # %cond.load1589 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18191,9 +18191,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 48 -; CHECK-RV64-NEXT: bltz a1, .LBB61_914 +; CHECK-RV64-NEXT: bltz a1, .LBB61_920 ; CHECK-RV64-NEXT: j .LBB61_412 -; CHECK-RV64-NEXT: .LBB61_914: # %cond.load1593 +; CHECK-RV64-NEXT: .LBB61_920: # %cond.load1593 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18204,9 +18204,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 47 -; CHECK-RV64-NEXT: bltz a1, .LBB61_915 +; CHECK-RV64-NEXT: bltz a1, .LBB61_921 ; CHECK-RV64-NEXT: j .LBB61_413 -; CHECK-RV64-NEXT: .LBB61_915: # %cond.load1597 +; CHECK-RV64-NEXT: .LBB61_921: # %cond.load1597 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18217,9 +18217,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 46 -; CHECK-RV64-NEXT: bltz a1, .LBB61_916 +; CHECK-RV64-NEXT: bltz a1, .LBB61_922 ; CHECK-RV64-NEXT: j .LBB61_414 -; CHECK-RV64-NEXT: .LBB61_916: # %cond.load1601 +; CHECK-RV64-NEXT: .LBB61_922: # %cond.load1601 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18230,9 +18230,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 45 -; CHECK-RV64-NEXT: bltz a1, .LBB61_917 +; CHECK-RV64-NEXT: bltz a1, .LBB61_923 ; CHECK-RV64-NEXT: j .LBB61_415 -; CHECK-RV64-NEXT: .LBB61_917: # %cond.load1605 +; CHECK-RV64-NEXT: .LBB61_923: # %cond.load1605 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18243,9 +18243,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 44 -; CHECK-RV64-NEXT: bltz a1, .LBB61_918 +; CHECK-RV64-NEXT: bltz a1, .LBB61_924 ; CHECK-RV64-NEXT: j .LBB61_416 -; CHECK-RV64-NEXT: .LBB61_918: # %cond.load1609 +; CHECK-RV64-NEXT: .LBB61_924: # %cond.load1609 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18256,9 +18256,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 43 -; CHECK-RV64-NEXT: bltz a1, .LBB61_919 +; CHECK-RV64-NEXT: bltz a1, .LBB61_925 ; CHECK-RV64-NEXT: j .LBB61_417 -; CHECK-RV64-NEXT: .LBB61_919: # %cond.load1613 +; CHECK-RV64-NEXT: .LBB61_925: # %cond.load1613 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18269,9 +18269,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 42 -; CHECK-RV64-NEXT: bltz a1, .LBB61_920 +; CHECK-RV64-NEXT: bltz a1, .LBB61_926 ; CHECK-RV64-NEXT: j .LBB61_418 -; CHECK-RV64-NEXT: .LBB61_920: # %cond.load1617 +; CHECK-RV64-NEXT: .LBB61_926: # %cond.load1617 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18282,9 +18282,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 41 -; CHECK-RV64-NEXT: bltz a1, .LBB61_921 +; CHECK-RV64-NEXT: bltz a1, .LBB61_927 ; CHECK-RV64-NEXT: j .LBB61_419 -; CHECK-RV64-NEXT: .LBB61_921: # %cond.load1621 +; CHECK-RV64-NEXT: .LBB61_927: # %cond.load1621 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18295,9 +18295,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 40 -; CHECK-RV64-NEXT: bltz a1, .LBB61_922 +; CHECK-RV64-NEXT: bltz a1, .LBB61_928 ; CHECK-RV64-NEXT: j .LBB61_420 -; CHECK-RV64-NEXT: .LBB61_922: # %cond.load1625 +; CHECK-RV64-NEXT: .LBB61_928: # %cond.load1625 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18308,9 +18308,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 39 -; CHECK-RV64-NEXT: bltz a1, .LBB61_923 +; CHECK-RV64-NEXT: bltz a1, .LBB61_929 ; CHECK-RV64-NEXT: j .LBB61_421 -; CHECK-RV64-NEXT: .LBB61_923: # %cond.load1629 +; CHECK-RV64-NEXT: .LBB61_929: # %cond.load1629 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18321,9 +18321,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 38 -; CHECK-RV64-NEXT: bltz a1, .LBB61_924 +; CHECK-RV64-NEXT: bltz a1, .LBB61_930 ; CHECK-RV64-NEXT: j .LBB61_422 -; CHECK-RV64-NEXT: .LBB61_924: # %cond.load1633 +; CHECK-RV64-NEXT: .LBB61_930: # %cond.load1633 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18334,9 +18334,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 37 -; CHECK-RV64-NEXT: bltz a1, .LBB61_925 +; CHECK-RV64-NEXT: bltz a1, .LBB61_931 ; CHECK-RV64-NEXT: j .LBB61_423 -; CHECK-RV64-NEXT: .LBB61_925: # %cond.load1637 +; CHECK-RV64-NEXT: .LBB61_931: # %cond.load1637 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18347,9 +18347,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 36 -; CHECK-RV64-NEXT: bltz a1, .LBB61_926 +; CHECK-RV64-NEXT: bltz a1, .LBB61_932 ; CHECK-RV64-NEXT: j .LBB61_424 -; CHECK-RV64-NEXT: .LBB61_926: # %cond.load1641 +; CHECK-RV64-NEXT: .LBB61_932: # %cond.load1641 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18360,9 +18360,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 35 -; CHECK-RV64-NEXT: bltz a1, .LBB61_927 +; CHECK-RV64-NEXT: bltz a1, .LBB61_933 ; CHECK-RV64-NEXT: j .LBB61_425 -; CHECK-RV64-NEXT: .LBB61_927: # %cond.load1645 +; CHECK-RV64-NEXT: .LBB61_933: # %cond.load1645 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18373,9 +18373,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 34 -; CHECK-RV64-NEXT: bltz a1, .LBB61_928 +; CHECK-RV64-NEXT: bltz a1, .LBB61_934 ; CHECK-RV64-NEXT: j .LBB61_426 -; CHECK-RV64-NEXT: .LBB61_928: # %cond.load1649 +; CHECK-RV64-NEXT: .LBB61_934: # %cond.load1649 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18386,9 +18386,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 33 -; CHECK-RV64-NEXT: bltz a1, .LBB61_929 +; CHECK-RV64-NEXT: bltz a1, .LBB61_935 ; CHECK-RV64-NEXT: j .LBB61_427 -; CHECK-RV64-NEXT: .LBB61_929: # %cond.load1653 +; CHECK-RV64-NEXT: .LBB61_935: # %cond.load1653 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18399,9 +18399,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 32 -; CHECK-RV64-NEXT: bltz a1, .LBB61_930 +; CHECK-RV64-NEXT: bltz a1, .LBB61_936 ; CHECK-RV64-NEXT: j .LBB61_428 -; CHECK-RV64-NEXT: .LBB61_930: # %cond.load1657 +; CHECK-RV64-NEXT: .LBB61_936: # %cond.load1657 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18412,9 +18412,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 31 -; CHECK-RV64-NEXT: bltz a1, .LBB61_931 +; CHECK-RV64-NEXT: bltz a1, .LBB61_937 ; CHECK-RV64-NEXT: j .LBB61_429 -; CHECK-RV64-NEXT: .LBB61_931: # %cond.load1661 +; CHECK-RV64-NEXT: .LBB61_937: # %cond.load1661 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18425,9 +18425,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 30 -; CHECK-RV64-NEXT: bltz a1, .LBB61_932 +; CHECK-RV64-NEXT: bltz a1, .LBB61_938 ; CHECK-RV64-NEXT: j .LBB61_430 -; CHECK-RV64-NEXT: .LBB61_932: # %cond.load1665 +; CHECK-RV64-NEXT: .LBB61_938: # %cond.load1665 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18438,9 +18438,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 29 -; CHECK-RV64-NEXT: bltz a1, .LBB61_933 +; CHECK-RV64-NEXT: bltz a1, .LBB61_939 ; CHECK-RV64-NEXT: j .LBB61_431 -; CHECK-RV64-NEXT: .LBB61_933: # %cond.load1669 +; CHECK-RV64-NEXT: .LBB61_939: # %cond.load1669 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18451,9 +18451,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 28 -; CHECK-RV64-NEXT: bltz a1, .LBB61_934 +; CHECK-RV64-NEXT: bltz a1, .LBB61_940 ; CHECK-RV64-NEXT: j .LBB61_432 -; CHECK-RV64-NEXT: .LBB61_934: # %cond.load1673 +; CHECK-RV64-NEXT: .LBB61_940: # %cond.load1673 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18464,9 +18464,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 27 -; CHECK-RV64-NEXT: bltz a1, .LBB61_935 +; CHECK-RV64-NEXT: bltz a1, .LBB61_941 ; CHECK-RV64-NEXT: j .LBB61_433 -; CHECK-RV64-NEXT: .LBB61_935: # %cond.load1677 +; CHECK-RV64-NEXT: .LBB61_941: # %cond.load1677 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18477,9 +18477,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 26 -; CHECK-RV64-NEXT: bltz a1, .LBB61_936 +; CHECK-RV64-NEXT: bltz a1, .LBB61_942 ; CHECK-RV64-NEXT: j .LBB61_434 -; CHECK-RV64-NEXT: .LBB61_936: # %cond.load1681 +; CHECK-RV64-NEXT: .LBB61_942: # %cond.load1681 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18490,9 +18490,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 25 -; CHECK-RV64-NEXT: bltz a1, .LBB61_937 +; CHECK-RV64-NEXT: bltz a1, .LBB61_943 ; CHECK-RV64-NEXT: j .LBB61_435 -; CHECK-RV64-NEXT: .LBB61_937: # %cond.load1685 +; CHECK-RV64-NEXT: .LBB61_943: # %cond.load1685 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18503,9 +18503,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 24 -; CHECK-RV64-NEXT: bltz a1, .LBB61_938 +; CHECK-RV64-NEXT: bltz a1, .LBB61_944 ; CHECK-RV64-NEXT: j .LBB61_436 -; CHECK-RV64-NEXT: .LBB61_938: # %cond.load1689 +; CHECK-RV64-NEXT: .LBB61_944: # %cond.load1689 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18516,9 +18516,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 23 -; CHECK-RV64-NEXT: bltz a1, .LBB61_939 +; CHECK-RV64-NEXT: bltz a1, .LBB61_945 ; CHECK-RV64-NEXT: j .LBB61_437 -; CHECK-RV64-NEXT: .LBB61_939: # %cond.load1693 +; CHECK-RV64-NEXT: .LBB61_945: # %cond.load1693 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18529,9 +18529,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 22 -; CHECK-RV64-NEXT: bltz a1, .LBB61_940 +; CHECK-RV64-NEXT: bltz a1, .LBB61_946 ; CHECK-RV64-NEXT: j .LBB61_438 -; CHECK-RV64-NEXT: .LBB61_940: # %cond.load1697 +; CHECK-RV64-NEXT: .LBB61_946: # %cond.load1697 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18542,9 +18542,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 21 -; CHECK-RV64-NEXT: bltz a1, .LBB61_941 +; CHECK-RV64-NEXT: bltz a1, .LBB61_947 ; CHECK-RV64-NEXT: j .LBB61_439 -; CHECK-RV64-NEXT: .LBB61_941: # %cond.load1701 +; CHECK-RV64-NEXT: .LBB61_947: # %cond.load1701 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18555,9 +18555,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 20 -; CHECK-RV64-NEXT: bltz a1, .LBB61_942 +; CHECK-RV64-NEXT: bltz a1, .LBB61_948 ; CHECK-RV64-NEXT: j .LBB61_440 -; CHECK-RV64-NEXT: .LBB61_942: # %cond.load1705 +; CHECK-RV64-NEXT: .LBB61_948: # %cond.load1705 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18568,9 +18568,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 19 -; CHECK-RV64-NEXT: bltz a1, .LBB61_943 +; CHECK-RV64-NEXT: bltz a1, .LBB61_949 ; CHECK-RV64-NEXT: j .LBB61_441 -; CHECK-RV64-NEXT: .LBB61_943: # %cond.load1709 +; CHECK-RV64-NEXT: .LBB61_949: # %cond.load1709 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18581,9 +18581,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 18 -; CHECK-RV64-NEXT: bltz a1, .LBB61_944 +; CHECK-RV64-NEXT: bltz a1, .LBB61_950 ; CHECK-RV64-NEXT: j .LBB61_442 -; CHECK-RV64-NEXT: .LBB61_944: # %cond.load1713 +; CHECK-RV64-NEXT: .LBB61_950: # %cond.load1713 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18594,9 +18594,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 17 -; CHECK-RV64-NEXT: bltz a1, .LBB61_945 +; CHECK-RV64-NEXT: bltz a1, .LBB61_951 ; CHECK-RV64-NEXT: j .LBB61_443 -; CHECK-RV64-NEXT: .LBB61_945: # %cond.load1717 +; CHECK-RV64-NEXT: .LBB61_951: # %cond.load1717 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18607,9 +18607,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 16 -; CHECK-RV64-NEXT: bltz a1, .LBB61_946 +; CHECK-RV64-NEXT: bltz a1, .LBB61_952 ; CHECK-RV64-NEXT: j .LBB61_444 -; CHECK-RV64-NEXT: .LBB61_946: # %cond.load1721 +; CHECK-RV64-NEXT: .LBB61_952: # %cond.load1721 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18620,9 +18620,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 15 -; CHECK-RV64-NEXT: bltz a1, .LBB61_947 +; CHECK-RV64-NEXT: bltz a1, .LBB61_953 ; CHECK-RV64-NEXT: j .LBB61_445 -; CHECK-RV64-NEXT: .LBB61_947: # %cond.load1725 +; CHECK-RV64-NEXT: .LBB61_953: # %cond.load1725 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18633,9 +18633,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 14 -; CHECK-RV64-NEXT: bltz a1, .LBB61_948 +; CHECK-RV64-NEXT: bltz a1, .LBB61_954 ; CHECK-RV64-NEXT: j .LBB61_446 -; CHECK-RV64-NEXT: .LBB61_948: # %cond.load1729 +; CHECK-RV64-NEXT: .LBB61_954: # %cond.load1729 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18646,9 +18646,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 13 -; CHECK-RV64-NEXT: bltz a1, .LBB61_949 +; CHECK-RV64-NEXT: bltz a1, .LBB61_955 ; CHECK-RV64-NEXT: j .LBB61_447 -; CHECK-RV64-NEXT: .LBB61_949: # %cond.load1733 +; CHECK-RV64-NEXT: .LBB61_955: # %cond.load1733 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18659,9 +18659,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 12 -; CHECK-RV64-NEXT: bltz a1, .LBB61_950 +; CHECK-RV64-NEXT: bltz a1, .LBB61_956 ; CHECK-RV64-NEXT: j .LBB61_448 -; CHECK-RV64-NEXT: .LBB61_950: # %cond.load1737 +; CHECK-RV64-NEXT: .LBB61_956: # %cond.load1737 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18672,9 +18672,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 11 -; CHECK-RV64-NEXT: bltz a1, .LBB61_951 +; CHECK-RV64-NEXT: bltz a1, .LBB61_957 ; CHECK-RV64-NEXT: j .LBB61_449 -; CHECK-RV64-NEXT: .LBB61_951: # %cond.load1741 +; CHECK-RV64-NEXT: .LBB61_957: # %cond.load1741 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18685,9 +18685,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 10 -; CHECK-RV64-NEXT: bltz a1, .LBB61_952 +; CHECK-RV64-NEXT: bltz a1, .LBB61_958 ; CHECK-RV64-NEXT: j .LBB61_450 -; CHECK-RV64-NEXT: .LBB61_952: # %cond.load1745 +; CHECK-RV64-NEXT: .LBB61_958: # %cond.load1745 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18698,9 +18698,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 9 -; CHECK-RV64-NEXT: bltz a1, .LBB61_953 +; CHECK-RV64-NEXT: bltz a1, .LBB61_959 ; CHECK-RV64-NEXT: j .LBB61_451 -; CHECK-RV64-NEXT: .LBB61_953: # %cond.load1749 +; CHECK-RV64-NEXT: .LBB61_959: # %cond.load1749 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18711,9 +18711,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 8 -; CHECK-RV64-NEXT: bltz a1, .LBB61_954 +; CHECK-RV64-NEXT: bltz a1, .LBB61_960 ; CHECK-RV64-NEXT: j .LBB61_452 -; CHECK-RV64-NEXT: .LBB61_954: # %cond.load1753 +; CHECK-RV64-NEXT: .LBB61_960: # %cond.load1753 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18724,9 +18724,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 7 -; CHECK-RV64-NEXT: bltz a1, .LBB61_955 +; CHECK-RV64-NEXT: bltz a1, .LBB61_961 ; CHECK-RV64-NEXT: j .LBB61_453 -; CHECK-RV64-NEXT: .LBB61_955: # %cond.load1757 +; CHECK-RV64-NEXT: .LBB61_961: # %cond.load1757 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18737,9 +18737,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 6 -; CHECK-RV64-NEXT: bltz a1, .LBB61_956 +; CHECK-RV64-NEXT: bltz a1, .LBB61_962 ; CHECK-RV64-NEXT: j .LBB61_454 -; CHECK-RV64-NEXT: .LBB61_956: # %cond.load1761 +; CHECK-RV64-NEXT: .LBB61_962: # %cond.load1761 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18750,9 +18750,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 5 -; CHECK-RV64-NEXT: bltz a1, .LBB61_957 +; CHECK-RV64-NEXT: bltz a1, .LBB61_963 ; CHECK-RV64-NEXT: j .LBB61_455 -; CHECK-RV64-NEXT: .LBB61_957: # %cond.load1765 +; CHECK-RV64-NEXT: .LBB61_963: # %cond.load1765 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18763,9 +18763,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 4 -; CHECK-RV64-NEXT: bltz a1, .LBB61_958 +; CHECK-RV64-NEXT: bltz a1, .LBB61_964 ; CHECK-RV64-NEXT: j .LBB61_456 -; CHECK-RV64-NEXT: .LBB61_958: # %cond.load1769 +; CHECK-RV64-NEXT: .LBB61_964: # %cond.load1769 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18776,9 +18776,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 3 -; CHECK-RV64-NEXT: bltz a1, .LBB61_959 +; CHECK-RV64-NEXT: bltz a1, .LBB61_965 ; CHECK-RV64-NEXT: j .LBB61_457 -; CHECK-RV64-NEXT: .LBB61_959: # %cond.load1773 +; CHECK-RV64-NEXT: .LBB61_965: # %cond.load1773 ; CHECK-RV64-NEXT: lbu a1, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18789,11 +18789,11 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a1, a2, 2 -; CHECK-RV64-NEXT: bgez a1, .LBB61_1031 +; CHECK-RV64-NEXT: bgez a1, .LBB61_966 ; CHECK-RV64-NEXT: j .LBB61_458 -; CHECK-RV64-NEXT: .LBB61_1031: # %cond.load1773 +; CHECK-RV64-NEXT: .LBB61_966: # %cond.load1773 ; CHECK-RV64-NEXT: j .LBB61_459 -; CHECK-RV64-NEXT: .LBB61_960: # %cond.load1785 +; CHECK-RV64-NEXT: .LBB61_967: # %cond.load1785 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: vmv.s.x v16, a2 ; CHECK-RV64-NEXT: li a2, 448 @@ -18802,9 +18802,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a2, a1, 1 -; CHECK-RV64-NEXT: bnez a2, .LBB61_961 +; CHECK-RV64-NEXT: bnez a2, .LBB61_968 ; CHECK-RV64-NEXT: j .LBB61_463 -; CHECK-RV64-NEXT: .LBB61_961: # %cond.load1789 +; CHECK-RV64-NEXT: .LBB61_968: # %cond.load1789 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18815,9 +18815,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a2, a1, 2 -; CHECK-RV64-NEXT: bnez a2, .LBB61_962 +; CHECK-RV64-NEXT: bnez a2, .LBB61_969 ; CHECK-RV64-NEXT: j .LBB61_464 -; CHECK-RV64-NEXT: .LBB61_962: # %cond.load1793 +; CHECK-RV64-NEXT: .LBB61_969: # %cond.load1793 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18828,9 +18828,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a2, a1, 4 -; CHECK-RV64-NEXT: bnez a2, .LBB61_963 +; CHECK-RV64-NEXT: bnez a2, .LBB61_970 ; CHECK-RV64-NEXT: j .LBB61_465 -; CHECK-RV64-NEXT: .LBB61_963: # %cond.load1797 +; CHECK-RV64-NEXT: .LBB61_970: # %cond.load1797 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18841,9 +18841,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a2, a1, 8 -; CHECK-RV64-NEXT: bnez a2, .LBB61_964 +; CHECK-RV64-NEXT: bnez a2, .LBB61_971 ; CHECK-RV64-NEXT: j .LBB61_466 -; CHECK-RV64-NEXT: .LBB61_964: # %cond.load1801 +; CHECK-RV64-NEXT: .LBB61_971: # %cond.load1801 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18854,9 +18854,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a2, a1, 16 -; CHECK-RV64-NEXT: bnez a2, .LBB61_965 +; CHECK-RV64-NEXT: bnez a2, .LBB61_972 ; CHECK-RV64-NEXT: j .LBB61_467 -; CHECK-RV64-NEXT: .LBB61_965: # %cond.load1805 +; CHECK-RV64-NEXT: .LBB61_972: # %cond.load1805 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18867,9 +18867,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a2, a1, 32 -; CHECK-RV64-NEXT: bnez a2, .LBB61_966 +; CHECK-RV64-NEXT: bnez a2, .LBB61_973 ; CHECK-RV64-NEXT: j .LBB61_468 -; CHECK-RV64-NEXT: .LBB61_966: # %cond.load1809 +; CHECK-RV64-NEXT: .LBB61_973: # %cond.load1809 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18880,9 +18880,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a2, a1, 64 -; CHECK-RV64-NEXT: bnez a2, .LBB61_967 +; CHECK-RV64-NEXT: bnez a2, .LBB61_974 ; CHECK-RV64-NEXT: j .LBB61_469 -; CHECK-RV64-NEXT: .LBB61_967: # %cond.load1813 +; CHECK-RV64-NEXT: .LBB61_974: # %cond.load1813 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18893,9 +18893,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a2, a1, 128 -; CHECK-RV64-NEXT: bnez a2, .LBB61_968 +; CHECK-RV64-NEXT: bnez a2, .LBB61_975 ; CHECK-RV64-NEXT: j .LBB61_470 -; CHECK-RV64-NEXT: .LBB61_968: # %cond.load1817 +; CHECK-RV64-NEXT: .LBB61_975: # %cond.load1817 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18906,9 +18906,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a2, a1, 256 -; CHECK-RV64-NEXT: bnez a2, .LBB61_969 +; CHECK-RV64-NEXT: bnez a2, .LBB61_976 ; CHECK-RV64-NEXT: j .LBB61_471 -; CHECK-RV64-NEXT: .LBB61_969: # %cond.load1821 +; CHECK-RV64-NEXT: .LBB61_976: # %cond.load1821 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18919,9 +18919,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a2, a1, 512 -; CHECK-RV64-NEXT: bnez a2, .LBB61_970 +; CHECK-RV64-NEXT: bnez a2, .LBB61_977 ; CHECK-RV64-NEXT: j .LBB61_472 -; CHECK-RV64-NEXT: .LBB61_970: # %cond.load1825 +; CHECK-RV64-NEXT: .LBB61_977: # %cond.load1825 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18932,9 +18932,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: andi a2, a1, 1024 -; CHECK-RV64-NEXT: bnez a2, .LBB61_971 +; CHECK-RV64-NEXT: bnez a2, .LBB61_978 ; CHECK-RV64-NEXT: j .LBB61_473 -; CHECK-RV64-NEXT: .LBB61_971: # %cond.load1829 +; CHECK-RV64-NEXT: .LBB61_978: # %cond.load1829 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18945,9 +18945,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 52 -; CHECK-RV64-NEXT: bltz a2, .LBB61_972 +; CHECK-RV64-NEXT: bltz a2, .LBB61_979 ; CHECK-RV64-NEXT: j .LBB61_474 -; CHECK-RV64-NEXT: .LBB61_972: # %cond.load1833 +; CHECK-RV64-NEXT: .LBB61_979: # %cond.load1833 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18958,9 +18958,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 51 -; CHECK-RV64-NEXT: bltz a2, .LBB61_973 +; CHECK-RV64-NEXT: bltz a2, .LBB61_980 ; CHECK-RV64-NEXT: j .LBB61_475 -; CHECK-RV64-NEXT: .LBB61_973: # %cond.load1837 +; CHECK-RV64-NEXT: .LBB61_980: # %cond.load1837 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18971,9 +18971,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 50 -; CHECK-RV64-NEXT: bltz a2, .LBB61_974 +; CHECK-RV64-NEXT: bltz a2, .LBB61_981 ; CHECK-RV64-NEXT: j .LBB61_476 -; CHECK-RV64-NEXT: .LBB61_974: # %cond.load1841 +; CHECK-RV64-NEXT: .LBB61_981: # %cond.load1841 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18984,9 +18984,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 49 -; CHECK-RV64-NEXT: bltz a2, .LBB61_975 +; CHECK-RV64-NEXT: bltz a2, .LBB61_982 ; CHECK-RV64-NEXT: j .LBB61_477 -; CHECK-RV64-NEXT: .LBB61_975: # %cond.load1845 +; CHECK-RV64-NEXT: .LBB61_982: # %cond.load1845 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -18997,9 +18997,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 48 -; CHECK-RV64-NEXT: bltz a2, .LBB61_976 +; CHECK-RV64-NEXT: bltz a2, .LBB61_983 ; CHECK-RV64-NEXT: j .LBB61_478 -; CHECK-RV64-NEXT: .LBB61_976: # %cond.load1849 +; CHECK-RV64-NEXT: .LBB61_983: # %cond.load1849 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19010,9 +19010,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 47 -; CHECK-RV64-NEXT: bltz a2, .LBB61_977 +; CHECK-RV64-NEXT: bltz a2, .LBB61_984 ; CHECK-RV64-NEXT: j .LBB61_479 -; CHECK-RV64-NEXT: .LBB61_977: # %cond.load1853 +; CHECK-RV64-NEXT: .LBB61_984: # %cond.load1853 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19023,9 +19023,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 46 -; CHECK-RV64-NEXT: bltz a2, .LBB61_978 +; CHECK-RV64-NEXT: bltz a2, .LBB61_985 ; CHECK-RV64-NEXT: j .LBB61_480 -; CHECK-RV64-NEXT: .LBB61_978: # %cond.load1857 +; CHECK-RV64-NEXT: .LBB61_985: # %cond.load1857 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19036,9 +19036,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 45 -; CHECK-RV64-NEXT: bltz a2, .LBB61_979 +; CHECK-RV64-NEXT: bltz a2, .LBB61_986 ; CHECK-RV64-NEXT: j .LBB61_481 -; CHECK-RV64-NEXT: .LBB61_979: # %cond.load1861 +; CHECK-RV64-NEXT: .LBB61_986: # %cond.load1861 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19049,9 +19049,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 44 -; CHECK-RV64-NEXT: bltz a2, .LBB61_980 +; CHECK-RV64-NEXT: bltz a2, .LBB61_987 ; CHECK-RV64-NEXT: j .LBB61_482 -; CHECK-RV64-NEXT: .LBB61_980: # %cond.load1865 +; CHECK-RV64-NEXT: .LBB61_987: # %cond.load1865 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19062,9 +19062,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 43 -; CHECK-RV64-NEXT: bltz a2, .LBB61_981 +; CHECK-RV64-NEXT: bltz a2, .LBB61_988 ; CHECK-RV64-NEXT: j .LBB61_483 -; CHECK-RV64-NEXT: .LBB61_981: # %cond.load1869 +; CHECK-RV64-NEXT: .LBB61_988: # %cond.load1869 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19075,9 +19075,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 42 -; CHECK-RV64-NEXT: bltz a2, .LBB61_982 +; CHECK-RV64-NEXT: bltz a2, .LBB61_989 ; CHECK-RV64-NEXT: j .LBB61_484 -; CHECK-RV64-NEXT: .LBB61_982: # %cond.load1873 +; CHECK-RV64-NEXT: .LBB61_989: # %cond.load1873 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19088,9 +19088,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 41 -; CHECK-RV64-NEXT: bltz a2, .LBB61_983 +; CHECK-RV64-NEXT: bltz a2, .LBB61_990 ; CHECK-RV64-NEXT: j .LBB61_485 -; CHECK-RV64-NEXT: .LBB61_983: # %cond.load1877 +; CHECK-RV64-NEXT: .LBB61_990: # %cond.load1877 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19101,9 +19101,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 40 -; CHECK-RV64-NEXT: bltz a2, .LBB61_984 +; CHECK-RV64-NEXT: bltz a2, .LBB61_991 ; CHECK-RV64-NEXT: j .LBB61_486 -; CHECK-RV64-NEXT: .LBB61_984: # %cond.load1881 +; CHECK-RV64-NEXT: .LBB61_991: # %cond.load1881 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19114,9 +19114,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 39 -; CHECK-RV64-NEXT: bltz a2, .LBB61_985 +; CHECK-RV64-NEXT: bltz a2, .LBB61_992 ; CHECK-RV64-NEXT: j .LBB61_487 -; CHECK-RV64-NEXT: .LBB61_985: # %cond.load1885 +; CHECK-RV64-NEXT: .LBB61_992: # %cond.load1885 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19127,9 +19127,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 38 -; CHECK-RV64-NEXT: bltz a2, .LBB61_986 +; CHECK-RV64-NEXT: bltz a2, .LBB61_993 ; CHECK-RV64-NEXT: j .LBB61_488 -; CHECK-RV64-NEXT: .LBB61_986: # %cond.load1889 +; CHECK-RV64-NEXT: .LBB61_993: # %cond.load1889 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19140,9 +19140,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 37 -; CHECK-RV64-NEXT: bltz a2, .LBB61_987 +; CHECK-RV64-NEXT: bltz a2, .LBB61_994 ; CHECK-RV64-NEXT: j .LBB61_489 -; CHECK-RV64-NEXT: .LBB61_987: # %cond.load1893 +; CHECK-RV64-NEXT: .LBB61_994: # %cond.load1893 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19153,9 +19153,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 36 -; CHECK-RV64-NEXT: bltz a2, .LBB61_988 +; CHECK-RV64-NEXT: bltz a2, .LBB61_995 ; CHECK-RV64-NEXT: j .LBB61_490 -; CHECK-RV64-NEXT: .LBB61_988: # %cond.load1897 +; CHECK-RV64-NEXT: .LBB61_995: # %cond.load1897 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19166,9 +19166,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 35 -; CHECK-RV64-NEXT: bltz a2, .LBB61_989 +; CHECK-RV64-NEXT: bltz a2, .LBB61_996 ; CHECK-RV64-NEXT: j .LBB61_491 -; CHECK-RV64-NEXT: .LBB61_989: # %cond.load1901 +; CHECK-RV64-NEXT: .LBB61_996: # %cond.load1901 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19179,9 +19179,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 34 -; CHECK-RV64-NEXT: bltz a2, .LBB61_990 +; CHECK-RV64-NEXT: bltz a2, .LBB61_997 ; CHECK-RV64-NEXT: j .LBB61_492 -; CHECK-RV64-NEXT: .LBB61_990: # %cond.load1905 +; CHECK-RV64-NEXT: .LBB61_997: # %cond.load1905 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19192,9 +19192,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 33 -; CHECK-RV64-NEXT: bltz a2, .LBB61_991 +; CHECK-RV64-NEXT: bltz a2, .LBB61_998 ; CHECK-RV64-NEXT: j .LBB61_493 -; CHECK-RV64-NEXT: .LBB61_991: # %cond.load1909 +; CHECK-RV64-NEXT: .LBB61_998: # %cond.load1909 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19205,9 +19205,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 32 -; CHECK-RV64-NEXT: bltz a2, .LBB61_992 +; CHECK-RV64-NEXT: bltz a2, .LBB61_999 ; CHECK-RV64-NEXT: j .LBB61_494 -; CHECK-RV64-NEXT: .LBB61_992: # %cond.load1913 +; CHECK-RV64-NEXT: .LBB61_999: # %cond.load1913 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19218,9 +19218,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 31 -; CHECK-RV64-NEXT: bltz a2, .LBB61_993 +; CHECK-RV64-NEXT: bltz a2, .LBB61_1000 ; CHECK-RV64-NEXT: j .LBB61_495 -; CHECK-RV64-NEXT: .LBB61_993: # %cond.load1917 +; CHECK-RV64-NEXT: .LBB61_1000: # %cond.load1917 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19231,9 +19231,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 30 -; CHECK-RV64-NEXT: bltz a2, .LBB61_994 +; CHECK-RV64-NEXT: bltz a2, .LBB61_1001 ; CHECK-RV64-NEXT: j .LBB61_496 -; CHECK-RV64-NEXT: .LBB61_994: # %cond.load1921 +; CHECK-RV64-NEXT: .LBB61_1001: # %cond.load1921 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19244,9 +19244,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 29 -; CHECK-RV64-NEXT: bltz a2, .LBB61_995 +; CHECK-RV64-NEXT: bltz a2, .LBB61_1002 ; CHECK-RV64-NEXT: j .LBB61_497 -; CHECK-RV64-NEXT: .LBB61_995: # %cond.load1925 +; CHECK-RV64-NEXT: .LBB61_1002: # %cond.load1925 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19257,9 +19257,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 28 -; CHECK-RV64-NEXT: bltz a2, .LBB61_996 +; CHECK-RV64-NEXT: bltz a2, .LBB61_1003 ; CHECK-RV64-NEXT: j .LBB61_498 -; CHECK-RV64-NEXT: .LBB61_996: # %cond.load1929 +; CHECK-RV64-NEXT: .LBB61_1003: # %cond.load1929 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19270,9 +19270,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 27 -; CHECK-RV64-NEXT: bltz a2, .LBB61_997 +; CHECK-RV64-NEXT: bltz a2, .LBB61_1004 ; CHECK-RV64-NEXT: j .LBB61_499 -; CHECK-RV64-NEXT: .LBB61_997: # %cond.load1933 +; CHECK-RV64-NEXT: .LBB61_1004: # %cond.load1933 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19283,9 +19283,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 26 -; CHECK-RV64-NEXT: bltz a2, .LBB61_998 +; CHECK-RV64-NEXT: bltz a2, .LBB61_1005 ; CHECK-RV64-NEXT: j .LBB61_500 -; CHECK-RV64-NEXT: .LBB61_998: # %cond.load1937 +; CHECK-RV64-NEXT: .LBB61_1005: # %cond.load1937 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19296,9 +19296,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 25 -; CHECK-RV64-NEXT: bltz a2, .LBB61_999 +; CHECK-RV64-NEXT: bltz a2, .LBB61_1006 ; CHECK-RV64-NEXT: j .LBB61_501 -; CHECK-RV64-NEXT: .LBB61_999: # %cond.load1941 +; CHECK-RV64-NEXT: .LBB61_1006: # %cond.load1941 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19309,9 +19309,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 24 -; CHECK-RV64-NEXT: bltz a2, .LBB61_1000 +; CHECK-RV64-NEXT: bltz a2, .LBB61_1007 ; CHECK-RV64-NEXT: j .LBB61_502 -; CHECK-RV64-NEXT: .LBB61_1000: # %cond.load1945 +; CHECK-RV64-NEXT: .LBB61_1007: # %cond.load1945 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19322,9 +19322,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 23 -; CHECK-RV64-NEXT: bltz a2, .LBB61_1001 +; CHECK-RV64-NEXT: bltz a2, .LBB61_1008 ; CHECK-RV64-NEXT: j .LBB61_503 -; CHECK-RV64-NEXT: .LBB61_1001: # %cond.load1949 +; CHECK-RV64-NEXT: .LBB61_1008: # %cond.load1949 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19335,9 +19335,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 22 -; CHECK-RV64-NEXT: bltz a2, .LBB61_1002 +; CHECK-RV64-NEXT: bltz a2, .LBB61_1009 ; CHECK-RV64-NEXT: j .LBB61_504 -; CHECK-RV64-NEXT: .LBB61_1002: # %cond.load1953 +; CHECK-RV64-NEXT: .LBB61_1009: # %cond.load1953 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19348,9 +19348,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 21 -; CHECK-RV64-NEXT: bltz a2, .LBB61_1003 +; CHECK-RV64-NEXT: bltz a2, .LBB61_1010 ; CHECK-RV64-NEXT: j .LBB61_505 -; CHECK-RV64-NEXT: .LBB61_1003: # %cond.load1957 +; CHECK-RV64-NEXT: .LBB61_1010: # %cond.load1957 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19361,9 +19361,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 20 -; CHECK-RV64-NEXT: bltz a2, .LBB61_1004 +; CHECK-RV64-NEXT: bltz a2, .LBB61_1011 ; CHECK-RV64-NEXT: j .LBB61_506 -; CHECK-RV64-NEXT: .LBB61_1004: # %cond.load1961 +; CHECK-RV64-NEXT: .LBB61_1011: # %cond.load1961 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19374,9 +19374,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 19 -; CHECK-RV64-NEXT: bltz a2, .LBB61_1005 +; CHECK-RV64-NEXT: bltz a2, .LBB61_1012 ; CHECK-RV64-NEXT: j .LBB61_507 -; CHECK-RV64-NEXT: .LBB61_1005: # %cond.load1965 +; CHECK-RV64-NEXT: .LBB61_1012: # %cond.load1965 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19387,9 +19387,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 18 -; CHECK-RV64-NEXT: bltz a2, .LBB61_1006 +; CHECK-RV64-NEXT: bltz a2, .LBB61_1013 ; CHECK-RV64-NEXT: j .LBB61_508 -; CHECK-RV64-NEXT: .LBB61_1006: # %cond.load1969 +; CHECK-RV64-NEXT: .LBB61_1013: # %cond.load1969 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19400,9 +19400,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 17 -; CHECK-RV64-NEXT: bltz a2, .LBB61_1007 +; CHECK-RV64-NEXT: bltz a2, .LBB61_1014 ; CHECK-RV64-NEXT: j .LBB61_509 -; CHECK-RV64-NEXT: .LBB61_1007: # %cond.load1973 +; CHECK-RV64-NEXT: .LBB61_1014: # %cond.load1973 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19413,9 +19413,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 16 -; CHECK-RV64-NEXT: bltz a2, .LBB61_1008 +; CHECK-RV64-NEXT: bltz a2, .LBB61_1015 ; CHECK-RV64-NEXT: j .LBB61_510 -; CHECK-RV64-NEXT: .LBB61_1008: # %cond.load1977 +; CHECK-RV64-NEXT: .LBB61_1015: # %cond.load1977 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19426,9 +19426,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 15 -; CHECK-RV64-NEXT: bltz a2, .LBB61_1009 +; CHECK-RV64-NEXT: bltz a2, .LBB61_1016 ; CHECK-RV64-NEXT: j .LBB61_511 -; CHECK-RV64-NEXT: .LBB61_1009: # %cond.load1981 +; CHECK-RV64-NEXT: .LBB61_1016: # %cond.load1981 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19439,9 +19439,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 14 -; CHECK-RV64-NEXT: bltz a2, .LBB61_1010 +; CHECK-RV64-NEXT: bltz a2, .LBB61_1017 ; CHECK-RV64-NEXT: j .LBB61_512 -; CHECK-RV64-NEXT: .LBB61_1010: # %cond.load1985 +; CHECK-RV64-NEXT: .LBB61_1017: # %cond.load1985 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19452,9 +19452,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 13 -; CHECK-RV64-NEXT: bltz a2, .LBB61_1011 +; CHECK-RV64-NEXT: bltz a2, .LBB61_1018 ; CHECK-RV64-NEXT: j .LBB61_513 -; CHECK-RV64-NEXT: .LBB61_1011: # %cond.load1989 +; CHECK-RV64-NEXT: .LBB61_1018: # %cond.load1989 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19465,9 +19465,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 12 -; CHECK-RV64-NEXT: bltz a2, .LBB61_1012 +; CHECK-RV64-NEXT: bltz a2, .LBB61_1019 ; CHECK-RV64-NEXT: j .LBB61_514 -; CHECK-RV64-NEXT: .LBB61_1012: # %cond.load1993 +; CHECK-RV64-NEXT: .LBB61_1019: # %cond.load1993 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19478,9 +19478,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 11 -; CHECK-RV64-NEXT: bltz a2, .LBB61_1013 +; CHECK-RV64-NEXT: bltz a2, .LBB61_1020 ; CHECK-RV64-NEXT: j .LBB61_515 -; CHECK-RV64-NEXT: .LBB61_1013: # %cond.load1997 +; CHECK-RV64-NEXT: .LBB61_1020: # %cond.load1997 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19491,9 +19491,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 10 -; CHECK-RV64-NEXT: bltz a2, .LBB61_1014 +; CHECK-RV64-NEXT: bltz a2, .LBB61_1021 ; CHECK-RV64-NEXT: j .LBB61_516 -; CHECK-RV64-NEXT: .LBB61_1014: # %cond.load2001 +; CHECK-RV64-NEXT: .LBB61_1021: # %cond.load2001 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19504,9 +19504,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 9 -; CHECK-RV64-NEXT: bltz a2, .LBB61_1015 +; CHECK-RV64-NEXT: bltz a2, .LBB61_1022 ; CHECK-RV64-NEXT: j .LBB61_517 -; CHECK-RV64-NEXT: .LBB61_1015: # %cond.load2005 +; CHECK-RV64-NEXT: .LBB61_1022: # %cond.load2005 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19517,9 +19517,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 8 -; CHECK-RV64-NEXT: bltz a2, .LBB61_1016 +; CHECK-RV64-NEXT: bltz a2, .LBB61_1023 ; CHECK-RV64-NEXT: j .LBB61_518 -; CHECK-RV64-NEXT: .LBB61_1016: # %cond.load2009 +; CHECK-RV64-NEXT: .LBB61_1023: # %cond.load2009 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19530,9 +19530,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 7 -; CHECK-RV64-NEXT: bltz a2, .LBB61_1017 +; CHECK-RV64-NEXT: bltz a2, .LBB61_1024 ; CHECK-RV64-NEXT: j .LBB61_519 -; CHECK-RV64-NEXT: .LBB61_1017: # %cond.load2013 +; CHECK-RV64-NEXT: .LBB61_1024: # %cond.load2013 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19543,9 +19543,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 6 -; CHECK-RV64-NEXT: bltz a2, .LBB61_1018 +; CHECK-RV64-NEXT: bltz a2, .LBB61_1025 ; CHECK-RV64-NEXT: j .LBB61_520 -; CHECK-RV64-NEXT: .LBB61_1018: # %cond.load2017 +; CHECK-RV64-NEXT: .LBB61_1025: # %cond.load2017 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19556,9 +19556,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 5 -; CHECK-RV64-NEXT: bltz a2, .LBB61_1019 +; CHECK-RV64-NEXT: bltz a2, .LBB61_1026 ; CHECK-RV64-NEXT: j .LBB61_521 -; CHECK-RV64-NEXT: .LBB61_1019: # %cond.load2021 +; CHECK-RV64-NEXT: .LBB61_1026: # %cond.load2021 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19569,9 +19569,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 4 -; CHECK-RV64-NEXT: bltz a2, .LBB61_1020 +; CHECK-RV64-NEXT: bltz a2, .LBB61_1027 ; CHECK-RV64-NEXT: j .LBB61_522 -; CHECK-RV64-NEXT: .LBB61_1020: # %cond.load2025 +; CHECK-RV64-NEXT: .LBB61_1027: # %cond.load2025 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19582,9 +19582,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 3 -; CHECK-RV64-NEXT: bltz a2, .LBB61_1021 +; CHECK-RV64-NEXT: bltz a2, .LBB61_1028 ; CHECK-RV64-NEXT: j .LBB61_523 -; CHECK-RV64-NEXT: .LBB61_1021: # %cond.load2029 +; CHECK-RV64-NEXT: .LBB61_1028: # %cond.load2029 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19595,9 +19595,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 2 -; CHECK-RV64-NEXT: bltz a2, .LBB61_1022 +; CHECK-RV64-NEXT: bltz a2, .LBB61_1029 ; CHECK-RV64-NEXT: j .LBB61_524 -; CHECK-RV64-NEXT: .LBB61_1022: # %cond.load2033 +; CHECK-RV64-NEXT: .LBB61_1029: # %cond.load2033 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19608,9 +19608,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 ; CHECK-RV64-NEXT: slli a2, a1, 1 -; CHECK-RV64-NEXT: bltz a2, .LBB61_1023 +; CHECK-RV64-NEXT: bltz a2, .LBB61_1030 ; CHECK-RV64-NEXT: j .LBB61_525 -; CHECK-RV64-NEXT: .LBB61_1023: # %cond.load2037 +; CHECK-RV64-NEXT: .LBB61_1030: # %cond.load2037 ; CHECK-RV64-NEXT: lbu a2, 0(a0) ; CHECK-RV64-NEXT: li a3, 512 ; CHECK-RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -19620,9 +19620,9 @@ define <512 x i8> @test_expandload_v512i8_vlen512(ptr %base, <512 x i1> %mask, < ; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, tu, ma ; CHECK-RV64-NEXT: vslideup.vx v8, v16, a3 ; CHECK-RV64-NEXT: addi a0, a0, 1 -; CHECK-RV64-NEXT: bltz a1, .LBB61_1024 +; CHECK-RV64-NEXT: bltz a1, .LBB61_1031 ; CHECK-RV64-NEXT: j .LBB61_526 -; CHECK-RV64-NEXT: .LBB61_1024: # %cond.load2041 +; CHECK-RV64-NEXT: .LBB61_1031: # %cond.load2041 ; CHECK-RV64-NEXT: lbu a0, 0(a0) ; CHECK-RV64-NEXT: li a1, 512 ; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m8, ta, ma diff --git a/llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll b/llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll index dc625e25bd6f4..f845bd687fd51 100644 --- a/llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll +++ b/llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll @@ -804,17 +804,17 @@ define void @sextw_removal_ccor(i1 %c, i32 signext %arg, i32 signext %arg1, i32 ; RV64SFBSIFIVEU74-NEXT: andi a0, a0, 1 ; RV64SFBSIFIVEU74-NEXT: mv s1, a2 ; RV64SFBSIFIVEU74-NEXT: sd ra, 24(sp) # 8-byte Folded Spill -; RV64SFBSIFIVEU74-NEXT: beqz a0, .LBB15_4 -; RV64SFBSIFIVEU74-NEXT: # %bb.3: # %bb +; RV64SFBSIFIVEU74-NEXT: beqz a0, .LBB15_2 +; RV64SFBSIFIVEU74-NEXT: # %bb.1: # %bb ; RV64SFBSIFIVEU74-NEXT: or s0, a3, a1 -; RV64SFBSIFIVEU74-NEXT: .LBB15_4: # %bb -; RV64SFBSIFIVEU74-NEXT: .LBB15_1: # %bb2 +; RV64SFBSIFIVEU74-NEXT: .LBB15_2: # %bb +; RV64SFBSIFIVEU74-NEXT: .LBB15_3: # %bb2 ; RV64SFBSIFIVEU74-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64SFBSIFIVEU74-NEXT: mv a0, s0 ; RV64SFBSIFIVEU74-NEXT: call bar ; RV64SFBSIFIVEU74-NEXT: sllw s0, s0, s1 -; RV64SFBSIFIVEU74-NEXT: bnez a0, .LBB15_1 -; RV64SFBSIFIVEU74-NEXT: # %bb.2: # %bb7 +; RV64SFBSIFIVEU74-NEXT: bnez a0, .LBB15_3 +; RV64SFBSIFIVEU74-NEXT: # %bb.4: # %bb7 ; RV64SFBSIFIVEU74-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64SFBSIFIVEU74-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64SFBSIFIVEU74-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -854,17 +854,17 @@ define void @sextw_removal_ccor(i1 %c, i32 signext %arg, i32 signext %arg1, i32 ; ZICOND-NEXT: andi a0, a0, 1 ; ZICOND-NEXT: mv s1, a2 ; ZICOND-NEXT: sd ra, 24(sp) # 8-byte Folded Spill -; ZICOND-NEXT: beqz a0, .LBB15_4 -; ZICOND-NEXT: # %bb.3: # %bb +; ZICOND-NEXT: beqz a0, .LBB15_2 +; ZICOND-NEXT: # %bb.1: # %bb ; ZICOND-NEXT: or s0, a3, a1 -; ZICOND-NEXT: .LBB15_4: # %bb -; ZICOND-NEXT: .LBB15_1: # %bb2 +; ZICOND-NEXT: .LBB15_2: # %bb +; ZICOND-NEXT: .LBB15_3: # %bb2 ; ZICOND-NEXT: # =>This Inner Loop Header: Depth=1 ; ZICOND-NEXT: mv a0, s0 ; ZICOND-NEXT: call bar ; ZICOND-NEXT: sllw s0, s0, s1 -; ZICOND-NEXT: bnez a0, .LBB15_1 -; ZICOND-NEXT: # %bb.2: # %bb7 +; ZICOND-NEXT: bnez a0, .LBB15_3 +; ZICOND-NEXT: # %bb.4: # %bb7 ; ZICOND-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; ZICOND-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; ZICOND-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -880,17 +880,17 @@ define void @sextw_removal_ccor(i1 %c, i32 signext %arg, i32 signext %arg1, i32 ; RV32SFB-NEXT: andi a0, a0, 1 ; RV32SFB-NEXT: mv s1, a2 ; RV32SFB-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32SFB-NEXT: beqz a0, .LBB15_4 -; RV32SFB-NEXT: # %bb.3: # %bb +; RV32SFB-NEXT: beqz a0, .LBB15_2 +; RV32SFB-NEXT: # %bb.1: # %bb ; RV32SFB-NEXT: or s0, a3, a1 -; RV32SFB-NEXT: .LBB15_4: # %bb -; RV32SFB-NEXT: .LBB15_1: # %bb2 +; RV32SFB-NEXT: .LBB15_2: # %bb +; RV32SFB-NEXT: .LBB15_3: # %bb2 ; RV32SFB-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32SFB-NEXT: mv a0, s0 ; RV32SFB-NEXT: call bar ; RV32SFB-NEXT: sll s0, s0, s1 -; RV32SFB-NEXT: bnez a0, .LBB15_1 -; RV32SFB-NEXT: # %bb.2: # %bb7 +; RV32SFB-NEXT: bnez a0, .LBB15_3 +; RV32SFB-NEXT: # %bb.4: # %bb7 ; RV32SFB-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32SFB-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32SFB-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -947,17 +947,17 @@ define void @sextw_removal_ccaddw(i1 %c, i32 signext %arg, i32 signext %arg1, i3 ; RV64SFBSIFIVEU74-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64SFBSIFIVEU74-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64SFBSIFIVEU74-NEXT: mv s0, a2 -; RV64SFBSIFIVEU74-NEXT: beqz a0, .LBB16_4 -; RV64SFBSIFIVEU74-NEXT: # %bb.3: # %bb +; RV64SFBSIFIVEU74-NEXT: beqz a0, .LBB16_2 +; RV64SFBSIFIVEU74-NEXT: # %bb.1: # %bb ; RV64SFBSIFIVEU74-NEXT: addw s1, a1, a3 -; RV64SFBSIFIVEU74-NEXT: .LBB16_4: # %bb -; RV64SFBSIFIVEU74-NEXT: .LBB16_1: # %bb2 +; RV64SFBSIFIVEU74-NEXT: .LBB16_2: # %bb +; RV64SFBSIFIVEU74-NEXT: .LBB16_3: # %bb2 ; RV64SFBSIFIVEU74-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64SFBSIFIVEU74-NEXT: mv a0, s1 ; RV64SFBSIFIVEU74-NEXT: call bar ; RV64SFBSIFIVEU74-NEXT: sllw s1, s1, s0 -; RV64SFBSIFIVEU74-NEXT: bnez a0, .LBB16_1 -; RV64SFBSIFIVEU74-NEXT: # %bb.2: # %bb7 +; RV64SFBSIFIVEU74-NEXT: bnez a0, .LBB16_3 +; RV64SFBSIFIVEU74-NEXT: # %bb.4: # %bb7 ; RV64SFBSIFIVEU74-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64SFBSIFIVEU74-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64SFBSIFIVEU74-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -997,17 +997,17 @@ define void @sextw_removal_ccaddw(i1 %c, i32 signext %arg, i32 signext %arg1, i3 ; ZICOND-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; ZICOND-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; ZICOND-NEXT: mv s0, a2 -; ZICOND-NEXT: beqz a0, .LBB16_4 -; ZICOND-NEXT: # %bb.3: # %bb +; ZICOND-NEXT: beqz a0, .LBB16_2 +; ZICOND-NEXT: # %bb.1: # %bb ; ZICOND-NEXT: addw s1, a1, a3 -; ZICOND-NEXT: .LBB16_4: # %bb -; ZICOND-NEXT: .LBB16_1: # %bb2 +; ZICOND-NEXT: .LBB16_2: # %bb +; ZICOND-NEXT: .LBB16_3: # %bb2 ; ZICOND-NEXT: # =>This Inner Loop Header: Depth=1 ; ZICOND-NEXT: mv a0, s1 ; ZICOND-NEXT: call bar ; ZICOND-NEXT: sllw s1, s1, s0 -; ZICOND-NEXT: bnez a0, .LBB16_1 -; ZICOND-NEXT: # %bb.2: # %bb7 +; ZICOND-NEXT: bnez a0, .LBB16_3 +; ZICOND-NEXT: # %bb.4: # %bb7 ; ZICOND-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; ZICOND-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; ZICOND-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -1023,17 +1023,17 @@ define void @sextw_removal_ccaddw(i1 %c, i32 signext %arg, i32 signext %arg1, i3 ; RV32SFB-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32SFB-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32SFB-NEXT: mv s0, a2 -; RV32SFB-NEXT: beqz a0, .LBB16_4 -; RV32SFB-NEXT: # %bb.3: # %bb +; RV32SFB-NEXT: beqz a0, .LBB16_2 +; RV32SFB-NEXT: # %bb.1: # %bb ; RV32SFB-NEXT: add s1, a1, a3 -; RV32SFB-NEXT: .LBB16_4: # %bb -; RV32SFB-NEXT: .LBB16_1: # %bb2 +; RV32SFB-NEXT: .LBB16_2: # %bb +; RV32SFB-NEXT: .LBB16_3: # %bb2 ; RV32SFB-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32SFB-NEXT: mv a0, s1 ; RV32SFB-NEXT: call bar ; RV32SFB-NEXT: sll s1, s1, s0 -; RV32SFB-NEXT: bnez a0, .LBB16_1 -; RV32SFB-NEXT: # %bb.2: # %bb7 +; RV32SFB-NEXT: bnez a0, .LBB16_3 +; RV32SFB-NEXT: # %bb.4: # %bb7 ; RV32SFB-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32SFB-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32SFB-NEXT: lw s1, 4(sp) # 4-byte Folded Reload diff --git a/llvm/test/CodeGen/VE/Scalar/atomic_cmp_swap.ll b/llvm/test/CodeGen/VE/Scalar/atomic_cmp_swap.ll index b70f0ea602d0b..9ae1aa93d4c56 100644 --- a/llvm/test/CodeGen/VE/Scalar/atomic_cmp_swap.ll +++ b/llvm/test/CodeGen/VE/Scalar/atomic_cmp_swap.ll @@ -1429,8 +1429,8 @@ define zeroext i1 @_Z30atomic_cmp_swap_relaxed_stk_i1Rbb(ptr nocapture nonnull a ; CHECK-LABEL: _Z30atomic_cmp_swap_relaxed_stk_i1Rbb: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: adds.l %s11, -16, %s11 -; CHECK-NEXT: brge.l %s11, %s8, .LBB33_4 -; CHECK-NEXT: # %bb.3: # %bb +; CHECK-NEXT: brge.l %s11, %s8, .LBB33_2 +; CHECK-NEXT: # %bb.1: # %bb ; CHECK-NEXT: ld %s61, 24(, %s14) ; CHECK-NEXT: or %s62, 0, %s0 ; CHECK-NEXT: lea %s63, 315 @@ -1439,7 +1439,7 @@ define zeroext i1 @_Z30atomic_cmp_swap_relaxed_stk_i1Rbb(ptr nocapture nonnull a ; CHECK-NEXT: shm.l %s11, 16(%s61) ; CHECK-NEXT: monc ; CHECK-NEXT: or %s0, 0, %s62 -; CHECK-NEXT: .LBB33_4: # %bb +; CHECK-NEXT: .LBB33_2: # %bb ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: ld1b.zx %s3, (, %s0) ; CHECK-NEXT: ldl.zx %s4, 8(, %s11) @@ -1454,10 +1454,10 @@ define zeroext i1 @_Z30atomic_cmp_swap_relaxed_stk_i1Rbb(ptr nocapture nonnull a ; CHECK-NEXT: cmps.w.sx %s3, %s1, %s3 ; CHECK-NEXT: or %s2, 0, (0)1 ; CHECK-NEXT: cmov.w.eq %s2, (63)0, %s3 -; CHECK-NEXT: brne.w 0, %s2, .LBB33_2 -; CHECK-NEXT: # %bb.1: # %bb7 +; CHECK-NEXT: brne.w 0, %s2, .LBB33_4 +; CHECK-NEXT: # %bb.3: # %bb7 ; CHECK-NEXT: st1b %s1, (, %s0) -; CHECK-NEXT: .LBB33_2: # %bb9 +; CHECK-NEXT: .LBB33_4: # %bb9 ; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1 ; CHECK-NEXT: adds.l %s11, 16, %s11 ; CHECK-NEXT: b.l.t (, %s10) @@ -1491,8 +1491,8 @@ define signext i8 @_Z30atomic_cmp_swap_relaxed_stk_i8Rcc(ptr nocapture nonnull a ; CHECK-LABEL: _Z30atomic_cmp_swap_relaxed_stk_i8Rcc: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: adds.l %s11, -16, %s11 -; CHECK-NEXT: brge.l %s11, %s8, .LBB34_4 -; CHECK-NEXT: # %bb.3: # %bb +; CHECK-NEXT: brge.l %s11, %s8, .LBB34_2 +; CHECK-NEXT: # %bb.1: # %bb ; CHECK-NEXT: ld %s61, 24(, %s14) ; CHECK-NEXT: or %s62, 0, %s0 ; CHECK-NEXT: lea %s63, 315 @@ -1501,7 +1501,7 @@ define signext i8 @_Z30atomic_cmp_swap_relaxed_stk_i8Rcc(ptr nocapture nonnull a ; CHECK-NEXT: shm.l %s11, 16(%s61) ; CHECK-NEXT: monc ; CHECK-NEXT: or %s0, 0, %s62 -; CHECK-NEXT: .LBB34_4: # %bb +; CHECK-NEXT: .LBB34_2: # %bb ; CHECK-NEXT: ld1b.zx %s3, (, %s0) ; CHECK-NEXT: lea %s2, 8(, %s11) ; CHECK-NEXT: and %s1, %s1, (56)0 @@ -1517,10 +1517,10 @@ define signext i8 @_Z30atomic_cmp_swap_relaxed_stk_i8Rcc(ptr nocapture nonnull a ; CHECK-NEXT: cmps.w.sx %s3, %s1, %s3 ; CHECK-NEXT: or %s2, 0, (0)1 ; CHECK-NEXT: cmov.w.eq %s2, (63)0, %s3 -; CHECK-NEXT: brne.w 0, %s2, .LBB34_2 -; CHECK-NEXT: # %bb.1: # %bb6 +; CHECK-NEXT: brne.w 0, %s2, .LBB34_4 +; CHECK-NEXT: # %bb.3: # %bb6 ; CHECK-NEXT: st1b %s1, (, %s0) -; CHECK-NEXT: .LBB34_2: # %bb8 +; CHECK-NEXT: .LBB34_4: # %bb8 ; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1 ; CHECK-NEXT: adds.l %s11, 16, %s11 ; CHECK-NEXT: b.l.t (, %s10) @@ -1548,8 +1548,8 @@ define zeroext i8 @_Z30atomic_cmp_swap_relaxed_stk_u8Rhh(ptr nocapture nonnull a ; CHECK-LABEL: _Z30atomic_cmp_swap_relaxed_stk_u8Rhh: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: adds.l %s11, -16, %s11 -; CHECK-NEXT: brge.l %s11, %s8, .LBB35_4 -; CHECK-NEXT: # %bb.3: # %bb +; CHECK-NEXT: brge.l %s11, %s8, .LBB35_2 +; CHECK-NEXT: # %bb.1: # %bb ; CHECK-NEXT: ld %s61, 24(, %s14) ; CHECK-NEXT: or %s62, 0, %s0 ; CHECK-NEXT: lea %s63, 315 @@ -1558,7 +1558,7 @@ define zeroext i8 @_Z30atomic_cmp_swap_relaxed_stk_u8Rhh(ptr nocapture nonnull a ; CHECK-NEXT: shm.l %s11, 16(%s61) ; CHECK-NEXT: monc ; CHECK-NEXT: or %s0, 0, %s62 -; CHECK-NEXT: .LBB35_4: # %bb +; CHECK-NEXT: .LBB35_2: # %bb ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: ld1b.zx %s3, (, %s0) ; CHECK-NEXT: ldl.zx %s4, 8(, %s11) @@ -1573,10 +1573,10 @@ define zeroext i8 @_Z30atomic_cmp_swap_relaxed_stk_u8Rhh(ptr nocapture nonnull a ; CHECK-NEXT: cmps.w.sx %s3, %s1, %s3 ; CHECK-NEXT: or %s2, 0, (0)1 ; CHECK-NEXT: cmov.w.eq %s2, (63)0, %s3 -; CHECK-NEXT: brne.w 0, %s2, .LBB35_2 -; CHECK-NEXT: # %bb.1: # %bb6 +; CHECK-NEXT: brne.w 0, %s2, .LBB35_4 +; CHECK-NEXT: # %bb.3: # %bb6 ; CHECK-NEXT: st1b %s1, (, %s0) -; CHECK-NEXT: .LBB35_2: # %bb8 +; CHECK-NEXT: .LBB35_4: # %bb8 ; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1 ; CHECK-NEXT: adds.l %s11, 16, %s11 ; CHECK-NEXT: b.l.t (, %s10) @@ -1604,8 +1604,8 @@ define signext i16 @_Z31atomic_cmp_swap_relaxed_stk_i16Rss(ptr nocapture nonnull ; CHECK-LABEL: _Z31atomic_cmp_swap_relaxed_stk_i16Rss: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: adds.l %s11, -16, %s11 -; CHECK-NEXT: brge.l %s11, %s8, .LBB36_4 -; CHECK-NEXT: # %bb.3: # %bb +; CHECK-NEXT: brge.l %s11, %s8, .LBB36_2 +; CHECK-NEXT: # %bb.1: # %bb ; CHECK-NEXT: ld %s61, 24(, %s14) ; CHECK-NEXT: or %s62, 0, %s0 ; CHECK-NEXT: lea %s63, 315 @@ -1614,7 +1614,7 @@ define signext i16 @_Z31atomic_cmp_swap_relaxed_stk_i16Rss(ptr nocapture nonnull ; CHECK-NEXT: shm.l %s11, 16(%s61) ; CHECK-NEXT: monc ; CHECK-NEXT: or %s0, 0, %s62 -; CHECK-NEXT: .LBB36_4: # %bb +; CHECK-NEXT: .LBB36_2: # %bb ; CHECK-NEXT: ld2b.zx %s3, (, %s0) ; CHECK-NEXT: lea %s2, 8(, %s11) ; CHECK-NEXT: and %s1, %s1, (48)0 @@ -1630,10 +1630,10 @@ define signext i16 @_Z31atomic_cmp_swap_relaxed_stk_i16Rss(ptr nocapture nonnull ; CHECK-NEXT: cmps.w.sx %s3, %s1, %s3 ; CHECK-NEXT: or %s2, 0, (0)1 ; CHECK-NEXT: cmov.w.eq %s2, (63)0, %s3 -; CHECK-NEXT: brne.w 0, %s2, .LBB36_2 -; CHECK-NEXT: # %bb.1: # %bb7 +; CHECK-NEXT: brne.w 0, %s2, .LBB36_4 +; CHECK-NEXT: # %bb.3: # %bb7 ; CHECK-NEXT: st2b %s1, (, %s0) -; CHECK-NEXT: .LBB36_2: # %bb9 +; CHECK-NEXT: .LBB36_4: # %bb9 ; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1 ; CHECK-NEXT: adds.l %s11, 16, %s11 ; CHECK-NEXT: b.l.t (, %s10) @@ -1661,8 +1661,8 @@ define zeroext i16 @_Z31atomic_cmp_swap_relaxed_stk_u16Rtt(ptr nocapture nonnull ; CHECK-LABEL: _Z31atomic_cmp_swap_relaxed_stk_u16Rtt: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: adds.l %s11, -16, %s11 -; CHECK-NEXT: brge.l %s11, %s8, .LBB37_4 -; CHECK-NEXT: # %bb.3: # %bb +; CHECK-NEXT: brge.l %s11, %s8, .LBB37_2 +; CHECK-NEXT: # %bb.1: # %bb ; CHECK-NEXT: ld %s61, 24(, %s14) ; CHECK-NEXT: or %s62, 0, %s0 ; CHECK-NEXT: lea %s63, 315 @@ -1671,7 +1671,7 @@ define zeroext i16 @_Z31atomic_cmp_swap_relaxed_stk_u16Rtt(ptr nocapture nonnull ; CHECK-NEXT: shm.l %s11, 16(%s61) ; CHECK-NEXT: monc ; CHECK-NEXT: or %s0, 0, %s62 -; CHECK-NEXT: .LBB37_4: # %bb +; CHECK-NEXT: .LBB37_2: # %bb ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: ld2b.zx %s3, (, %s0) ; CHECK-NEXT: ldl.zx %s4, 8(, %s11) @@ -1686,10 +1686,10 @@ define zeroext i16 @_Z31atomic_cmp_swap_relaxed_stk_u16Rtt(ptr nocapture nonnull ; CHECK-NEXT: cmps.w.sx %s3, %s1, %s3 ; CHECK-NEXT: or %s2, 0, (0)1 ; CHECK-NEXT: cmov.w.eq %s2, (63)0, %s3 -; CHECK-NEXT: brne.w 0, %s2, .LBB37_2 -; CHECK-NEXT: # %bb.1: # %bb7 +; CHECK-NEXT: brne.w 0, %s2, .LBB37_4 +; CHECK-NEXT: # %bb.3: # %bb7 ; CHECK-NEXT: st2b %s1, (, %s0) -; CHECK-NEXT: .LBB37_2: # %bb9 +; CHECK-NEXT: .LBB37_4: # %bb9 ; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1 ; CHECK-NEXT: adds.l %s11, 16, %s11 ; CHECK-NEXT: b.l.t (, %s10) @@ -1717,8 +1717,8 @@ define signext i32 @_Z31atomic_cmp_swap_relaxed_stk_i32Rii(ptr nocapture nonnull ; CHECK-LABEL: _Z31atomic_cmp_swap_relaxed_stk_i32Rii: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: adds.l %s11, -16, %s11 -; CHECK-NEXT: brge.l %s11, %s8, .LBB38_4 -; CHECK-NEXT: # %bb.3: # %bb +; CHECK-NEXT: brge.l %s11, %s8, .LBB38_2 +; CHECK-NEXT: # %bb.1: # %bb ; CHECK-NEXT: ld %s61, 24(, %s14) ; CHECK-NEXT: or %s62, 0, %s0 ; CHECK-NEXT: lea %s63, 315 @@ -1727,16 +1727,16 @@ define signext i32 @_Z31atomic_cmp_swap_relaxed_stk_i32Rii(ptr nocapture nonnull ; CHECK-NEXT: shm.l %s11, 16(%s61) ; CHECK-NEXT: monc ; CHECK-NEXT: or %s0, 0, %s62 -; CHECK-NEXT: .LBB38_4: # %bb +; CHECK-NEXT: .LBB38_2: # %bb ; CHECK-NEXT: ldl.sx %s3, (, %s0) ; CHECK-NEXT: cas.w %s1, 8(%s11), %s3 ; CHECK-NEXT: cmps.w.sx %s4, %s1, %s3 ; CHECK-NEXT: or %s2, 0, (0)1 ; CHECK-NEXT: cmov.w.eq %s2, (63)0, %s4 -; CHECK-NEXT: breq.w %s1, %s3, .LBB38_2 -; CHECK-NEXT: # %bb.1: # %bb7 +; CHECK-NEXT: breq.w %s1, %s3, .LBB38_4 +; CHECK-NEXT: # %bb.3: # %bb7 ; CHECK-NEXT: stl %s1, (, %s0) -; CHECK-NEXT: .LBB38_2: # %bb9 +; CHECK-NEXT: .LBB38_4: # %bb9 ; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1 ; CHECK-NEXT: adds.l %s11, 16, %s11 ; CHECK-NEXT: b.l.t (, %s10) @@ -1764,8 +1764,8 @@ define zeroext i32 @_Z31atomic_cmp_swap_relaxed_stk_u32Rjj(ptr nocapture nonnull ; CHECK-LABEL: _Z31atomic_cmp_swap_relaxed_stk_u32Rjj: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: adds.l %s11, -16, %s11 -; CHECK-NEXT: brge.l %s11, %s8, .LBB39_4 -; CHECK-NEXT: # %bb.3: # %bb +; CHECK-NEXT: brge.l %s11, %s8, .LBB39_2 +; CHECK-NEXT: # %bb.1: # %bb ; CHECK-NEXT: ld %s61, 24(, %s14) ; CHECK-NEXT: or %s62, 0, %s0 ; CHECK-NEXT: lea %s63, 315 @@ -1774,16 +1774,16 @@ define zeroext i32 @_Z31atomic_cmp_swap_relaxed_stk_u32Rjj(ptr nocapture nonnull ; CHECK-NEXT: shm.l %s11, 16(%s61) ; CHECK-NEXT: monc ; CHECK-NEXT: or %s0, 0, %s62 -; CHECK-NEXT: .LBB39_4: # %bb +; CHECK-NEXT: .LBB39_2: # %bb ; CHECK-NEXT: ldl.sx %s3, (, %s0) ; CHECK-NEXT: cas.w %s1, 8(%s11), %s3 ; CHECK-NEXT: cmps.w.sx %s4, %s1, %s3 ; CHECK-NEXT: or %s2, 0, (0)1 ; CHECK-NEXT: cmov.w.eq %s2, (63)0, %s4 -; CHECK-NEXT: breq.w %s1, %s3, .LBB39_2 -; CHECK-NEXT: # %bb.1: # %bb7 +; CHECK-NEXT: breq.w %s1, %s3, .LBB39_4 +; CHECK-NEXT: # %bb.3: # %bb7 ; CHECK-NEXT: stl %s1, (, %s0) -; CHECK-NEXT: .LBB39_2: # %bb9 +; CHECK-NEXT: .LBB39_4: # %bb9 ; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1 ; CHECK-NEXT: adds.l %s11, 16, %s11 ; CHECK-NEXT: b.l.t (, %s10) @@ -1811,8 +1811,8 @@ define i64 @_Z31atomic_cmp_swap_relaxed_stk_i64Rll(ptr nocapture nonnull align 8 ; CHECK-LABEL: _Z31atomic_cmp_swap_relaxed_stk_i64Rll: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: adds.l %s11, -16, %s11 -; CHECK-NEXT: brge.l %s11, %s8, .LBB40_4 -; CHECK-NEXT: # %bb.3: # %bb +; CHECK-NEXT: brge.l %s11, %s8, .LBB40_2 +; CHECK-NEXT: # %bb.1: # %bb ; CHECK-NEXT: ld %s61, 24(, %s14) ; CHECK-NEXT: or %s62, 0, %s0 ; CHECK-NEXT: lea %s63, 315 @@ -1821,16 +1821,16 @@ define i64 @_Z31atomic_cmp_swap_relaxed_stk_i64Rll(ptr nocapture nonnull align 8 ; CHECK-NEXT: shm.l %s11, 16(%s61) ; CHECK-NEXT: monc ; CHECK-NEXT: or %s0, 0, %s62 -; CHECK-NEXT: .LBB40_4: # %bb +; CHECK-NEXT: .LBB40_2: # %bb ; CHECK-NEXT: ld %s3, (, %s0) ; CHECK-NEXT: cas.l %s1, 8(%s11), %s3 ; CHECK-NEXT: cmps.l %s4, %s1, %s3 ; CHECK-NEXT: or %s2, 0, (0)1 ; CHECK-NEXT: cmov.l.eq %s2, (63)0, %s4 -; CHECK-NEXT: breq.l %s1, %s3, .LBB40_2 -; CHECK-NEXT: # %bb.1: # %bb7 +; CHECK-NEXT: breq.l %s1, %s3, .LBB40_4 +; CHECK-NEXT: # %bb.3: # %bb7 ; CHECK-NEXT: st %s1, (, %s0) -; CHECK-NEXT: .LBB40_2: # %bb9 +; CHECK-NEXT: .LBB40_4: # %bb9 ; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1 ; CHECK-NEXT: adds.l %s11, 16, %s11 ; CHECK-NEXT: b.l.t (, %s10) @@ -1858,8 +1858,8 @@ define i64 @_Z31atomic_cmp_swap_relaxed_stk_u64Rmm(ptr nocapture nonnull align 8 ; CHECK-LABEL: _Z31atomic_cmp_swap_relaxed_stk_u64Rmm: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: adds.l %s11, -16, %s11 -; CHECK-NEXT: brge.l %s11, %s8, .LBB41_4 -; CHECK-NEXT: # %bb.3: # %bb +; CHECK-NEXT: brge.l %s11, %s8, .LBB41_2 +; CHECK-NEXT: # %bb.1: # %bb ; CHECK-NEXT: ld %s61, 24(, %s14) ; CHECK-NEXT: or %s62, 0, %s0 ; CHECK-NEXT: lea %s63, 315 @@ -1868,16 +1868,16 @@ define i64 @_Z31atomic_cmp_swap_relaxed_stk_u64Rmm(ptr nocapture nonnull align 8 ; CHECK-NEXT: shm.l %s11, 16(%s61) ; CHECK-NEXT: monc ; CHECK-NEXT: or %s0, 0, %s62 -; CHECK-NEXT: .LBB41_4: # %bb +; CHECK-NEXT: .LBB41_2: # %bb ; CHECK-NEXT: ld %s3, (, %s0) ; CHECK-NEXT: cas.l %s1, 8(%s11), %s3 ; CHECK-NEXT: cmps.l %s4, %s1, %s3 ; CHECK-NEXT: or %s2, 0, (0)1 ; CHECK-NEXT: cmov.l.eq %s2, (63)0, %s4 -; CHECK-NEXT: breq.l %s1, %s3, .LBB41_2 -; CHECK-NEXT: # %bb.1: # %bb7 +; CHECK-NEXT: breq.l %s1, %s3, .LBB41_4 +; CHECK-NEXT: # %bb.3: # %bb7 ; CHECK-NEXT: st %s1, (, %s0) -; CHECK-NEXT: .LBB41_2: # %bb9 +; CHECK-NEXT: .LBB41_4: # %bb9 ; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1 ; CHECK-NEXT: adds.l %s11, 16, %s11 ; CHECK-NEXT: b.l.t (, %s10) diff --git a/llvm/test/CodeGen/VE/Scalar/br_analyze.ll b/llvm/test/CodeGen/VE/Scalar/br_analyze.ll index 78b9708ab8223..09507241b902b 100644 --- a/llvm/test/CodeGen/VE/Scalar/br_analyze.ll +++ b/llvm/test/CodeGen/VE/Scalar/br_analyze.ll @@ -13,8 +13,8 @@ define i32 @f1(i32 %a, ptr %bptr) { ; CHECK-NEXT: st %s10, 8(, %s11) ; CHECK-NEXT: or %s9, 0, %s11 ; CHECK-NEXT: lea %s11, -240(, %s11) -; CHECK-NEXT: brge.l %s11, %s8, .LBB0_4 -; CHECK-NEXT: # %bb.3: # %entry +; CHECK-NEXT: brge.l %s11, %s8, .LBB0_2 +; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: ld %s61, 24(, %s14) ; CHECK-NEXT: or %s62, 0, %s0 ; CHECK-NEXT: lea %s63, 315 @@ -23,17 +23,17 @@ define i32 @f1(i32 %a, ptr %bptr) { ; CHECK-NEXT: shm.l %s11, 16(%s61) ; CHECK-NEXT: monc ; CHECK-NEXT: or %s0, 0, %s62 -; CHECK-NEXT: .LBB0_4: # %entry +; CHECK-NEXT: .LBB0_2: # %entry ; CHECK-NEXT: ldl.sx %s1, (, %s1) ; CHECK-NEXT: cmpu.w %s0, %s1, %s0 -; CHECK-NEXT: brlt.w 0, %s0, .LBB0_2 -; CHECK-NEXT: # %bb.1: # %return +; CHECK-NEXT: brlt.w 0, %s0, .LBB0_4 +; CHECK-NEXT: # %bb.3: # %return ; CHECK-NEXT: or %s0, 1, (0)1 ; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: ld %s10, 8(, %s11) ; CHECK-NEXT: ld %s9, (, %s11) ; CHECK-NEXT: b.l.t (, %s10) -; CHECK-NEXT: .LBB0_2: # %callit +; CHECK-NEXT: .LBB0_4: # %callit ; CHECK-NEXT: lea %s0, foo@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, foo@hi(, %s0) @@ -60,8 +60,8 @@ define i32 @f2(i32 %a) { ; CHECK-NEXT: st %s10, 8(, %s11) ; CHECK-NEXT: or %s9, 0, %s11 ; CHECK-NEXT: lea %s11, -240(, %s11) -; CHECK-NEXT: brge.l %s11, %s8, .LBB1_4 -; CHECK-NEXT: # %bb.3: # %entry +; CHECK-NEXT: brge.l %s11, %s8, .LBB1_2 +; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: ld %s61, 24(, %s14) ; CHECK-NEXT: or %s62, 0, %s0 ; CHECK-NEXT: lea %s63, 315 @@ -70,15 +70,15 @@ define i32 @f2(i32 %a) { ; CHECK-NEXT: shm.l %s11, 16(%s61) ; CHECK-NEXT: monc ; CHECK-NEXT: or %s0, 0, %s62 -; CHECK-NEXT: .LBB1_4: # %entry -; CHECK-NEXT: breq.w 0, %s0, .LBB1_2 -; CHECK-NEXT: # %bb.1: # %return +; CHECK-NEXT: .LBB1_2: # %entry +; CHECK-NEXT: breq.w 0, %s0, .LBB1_4 +; CHECK-NEXT: # %bb.3: # %return ; CHECK-NEXT: or %s0, 1, (0)1 ; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: ld %s10, 8(, %s11) ; CHECK-NEXT: ld %s9, (, %s11) ; CHECK-NEXT: b.l.t (, %s10) -; CHECK-NEXT: .LBB1_2: # %callit +; CHECK-NEXT: .LBB1_4: # %callit ; CHECK-NEXT: lea %s0, foo@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, foo@hi(, %s0) diff --git a/llvm/test/CodeGen/VE/Scalar/br_jt.ll b/llvm/test/CodeGen/VE/Scalar/br_jt.ll index fd880a7f42912..664ad3093af32 100644 --- a/llvm/test/CodeGen/VE/Scalar/br_jt.ll +++ b/llvm/test/CodeGen/VE/Scalar/br_jt.ll @@ -12,21 +12,21 @@ define signext i32 @br_jt3(i32 signext %0) { ; CHECK-LABEL: br_jt3: ; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (32)0 -; CHECK-NEXT: breq.w 1, %s0, .LBB0_1 +; CHECK-NEXT: breq.w 1, %s0, .LBB0_6 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: breq.w 4, %s0, .LBB0_4 ; CHECK-NEXT: # %bb.2: -; CHECK-NEXT: breq.w 4, %s0, .LBB0_5 +; CHECK-NEXT: brne.w 2, %s0, .LBB0_5 ; CHECK-NEXT: # %bb.3: -; CHECK-NEXT: brne.w 2, %s0, .LBB0_6 -; CHECK-NEXT: # %bb.4: ; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: b.l.t (, %s10) -; CHECK-NEXT: .LBB0_5: +; CHECK-NEXT: .LBB0_4: ; CHECK-NEXT: or %s0, 7, (0)1 -; CHECK-NEXT: .LBB0_6: +; CHECK-NEXT: .LBB0_5: ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: b.l.t (, %s10) -; CHECK-NEXT: .LBB0_1: +; CHECK-NEXT: .LBB0_6: ; CHECK-NEXT: or %s0, 3, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -34,21 +34,21 @@ define signext i32 @br_jt3(i32 signext %0) { ; PIC-LABEL: br_jt3: ; PIC: # %bb.0: ; PIC-NEXT: and %s0, %s0, (32)0 -; PIC-NEXT: breq.w 1, %s0, .LBB0_1 +; PIC-NEXT: breq.w 1, %s0, .LBB0_6 +; PIC-NEXT: # %bb.1: +; PIC-NEXT: breq.w 4, %s0, .LBB0_4 ; PIC-NEXT: # %bb.2: -; PIC-NEXT: breq.w 4, %s0, .LBB0_5 +; PIC-NEXT: brne.w 2, %s0, .LBB0_5 ; PIC-NEXT: # %bb.3: -; PIC-NEXT: brne.w 2, %s0, .LBB0_6 -; PIC-NEXT: # %bb.4: ; PIC-NEXT: or %s0, 0, (0)1 ; PIC-NEXT: adds.w.sx %s0, %s0, (0)1 ; PIC-NEXT: b.l.t (, %s10) -; PIC-NEXT: .LBB0_5: +; PIC-NEXT: .LBB0_4: ; PIC-NEXT: or %s0, 7, (0)1 -; PIC-NEXT: .LBB0_6: +; PIC-NEXT: .LBB0_5: ; PIC-NEXT: adds.w.sx %s0, %s0, (0)1 ; PIC-NEXT: b.l.t (, %s10) -; PIC-NEXT: .LBB0_1: +; PIC-NEXT: .LBB0_6: ; PIC-NEXT: or %s0, 3, (0)1 ; PIC-NEXT: adds.w.sx %s0, %s0, (0)1 ; PIC-NEXT: b.l.t (, %s10) @@ -139,18 +139,18 @@ define signext i32 @br_jt7(i32 signext %0) { ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: adds.w.sx %s1, -1, %s0 ; CHECK-NEXT: cmpu.w %s2, 8, %s1 -; CHECK-NEXT: brgt.w 0, %s2, .LBB2_3 +; CHECK-NEXT: brgt.w 0, %s2, .LBB2_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: and %s2, %s1, (48)0 ; CHECK-NEXT: lea %s3, 463 ; CHECK-NEXT: and %s3, %s3, (32)0 ; CHECK-NEXT: srl %s2, %s3, %s2 ; CHECK-NEXT: and %s2, 1, %s2 -; CHECK-NEXT: brne.w 0, %s2, .LBB2_2 -; CHECK-NEXT: .LBB2_3: +; CHECK-NEXT: brne.w 0, %s2, .LBB2_3 +; CHECK-NEXT: .LBB2_2: ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: b.l.t (, %s10) -; CHECK-NEXT: .LBB2_2: +; CHECK-NEXT: .LBB2_3: ; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1 ; CHECK-NEXT: sll %s0, %s0, 2 ; CHECK-NEXT: lea %s1, .Lswitch.table.br_jt7@lo @@ -170,18 +170,18 @@ define signext i32 @br_jt7(i32 signext %0) { ; PIC-NEXT: and %s15, %s15, (32)0 ; PIC-NEXT: sic %s16 ; PIC-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15) -; PIC-NEXT: brgt.w 0, %s2, .LBB2_3 +; PIC-NEXT: brgt.w 0, %s2, .LBB2_2 ; PIC-NEXT: # %bb.1: ; PIC-NEXT: and %s2, %s1, (48)0 ; PIC-NEXT: lea %s3, 463 ; PIC-NEXT: and %s3, %s3, (32)0 ; PIC-NEXT: srl %s2, %s3, %s2 ; PIC-NEXT: and %s2, 1, %s2 -; PIC-NEXT: brne.w 0, %s2, .LBB2_2 -; PIC-NEXT: .LBB2_3: +; PIC-NEXT: brne.w 0, %s2, .LBB2_3 +; PIC-NEXT: .LBB2_2: ; PIC-NEXT: adds.w.sx %s0, %s0, (0)1 ; PIC-NEXT: br.l.t .LBB2_4 -; PIC-NEXT: .LBB2_2: +; PIC-NEXT: .LBB2_3: ; PIC-NEXT: adds.w.sx %s0, %s1, (0)1 ; PIC-NEXT: sll %s0, %s0, 2 ; PIC-NEXT: lea %s1, .Lswitch.table.br_jt7@gotoff_lo @@ -220,18 +220,18 @@ define signext i32 @br_jt8(i32 signext %0) { ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: adds.w.sx %s1, -1, %s0 ; CHECK-NEXT: cmpu.w %s2, 8, %s1 -; CHECK-NEXT: brgt.w 0, %s2, .LBB3_3 +; CHECK-NEXT: brgt.w 0, %s2, .LBB3_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: and %s2, %s1, (48)0 ; CHECK-NEXT: lea %s3, 495 ; CHECK-NEXT: and %s3, %s3, (32)0 ; CHECK-NEXT: srl %s2, %s3, %s2 ; CHECK-NEXT: and %s2, 1, %s2 -; CHECK-NEXT: brne.w 0, %s2, .LBB3_2 -; CHECK-NEXT: .LBB3_3: +; CHECK-NEXT: brne.w 0, %s2, .LBB3_3 +; CHECK-NEXT: .LBB3_2: ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: b.l.t (, %s10) -; CHECK-NEXT: .LBB3_2: +; CHECK-NEXT: .LBB3_3: ; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1 ; CHECK-NEXT: sll %s0, %s0, 2 ; CHECK-NEXT: lea %s1, .Lswitch.table.br_jt8@lo @@ -251,18 +251,18 @@ define signext i32 @br_jt8(i32 signext %0) { ; PIC-NEXT: and %s15, %s15, (32)0 ; PIC-NEXT: sic %s16 ; PIC-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15) -; PIC-NEXT: brgt.w 0, %s2, .LBB3_3 +; PIC-NEXT: brgt.w 0, %s2, .LBB3_2 ; PIC-NEXT: # %bb.1: ; PIC-NEXT: and %s2, %s1, (48)0 ; PIC-NEXT: lea %s3, 495 ; PIC-NEXT: and %s3, %s3, (32)0 ; PIC-NEXT: srl %s2, %s3, %s2 ; PIC-NEXT: and %s2, 1, %s2 -; PIC-NEXT: brne.w 0, %s2, .LBB3_2 -; PIC-NEXT: .LBB3_3: +; PIC-NEXT: brne.w 0, %s2, .LBB3_3 +; PIC-NEXT: .LBB3_2: ; PIC-NEXT: adds.w.sx %s0, %s0, (0)1 ; PIC-NEXT: br.l.t .LBB3_4 -; PIC-NEXT: .LBB3_2: +; PIC-NEXT: .LBB3_3: ; PIC-NEXT: adds.w.sx %s0, %s1, (0)1 ; PIC-NEXT: sll %s0, %s0, 2 ; PIC-NEXT: lea %s1, .Lswitch.table.br_jt8@gotoff_lo @@ -299,22 +299,22 @@ define signext i32 @br_jt3_m(i32 signext %0, i32 signext %1) { ; CHECK-LABEL: br_jt3_m: ; CHECK: # %bb.0: ; CHECK-NEXT: and %s0, %s0, (32)0 -; CHECK-NEXT: breq.w 1, %s0, .LBB4_1 +; CHECK-NEXT: breq.w 1, %s0, .LBB4_6 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: breq.w 4, %s0, .LBB4_4 ; CHECK-NEXT: # %bb.2: -; CHECK-NEXT: breq.w 4, %s0, .LBB4_5 +; CHECK-NEXT: brne.w 2, %s0, .LBB4_5 ; CHECK-NEXT: # %bb.3: -; CHECK-NEXT: brne.w 2, %s0, .LBB4_6 -; CHECK-NEXT: # %bb.4: ; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: b.l.t (, %s10) -; CHECK-NEXT: .LBB4_5: +; CHECK-NEXT: .LBB4_4: ; CHECK-NEXT: and %s0, %s1, (32)0 ; CHECK-NEXT: adds.w.sx %s0, 3, %s0 -; CHECK-NEXT: .LBB4_6: +; CHECK-NEXT: .LBB4_5: ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: b.l.t (, %s10) -; CHECK-NEXT: .LBB4_1: +; CHECK-NEXT: .LBB4_6: ; CHECK-NEXT: or %s0, 3, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -322,22 +322,22 @@ define signext i32 @br_jt3_m(i32 signext %0, i32 signext %1) { ; PIC-LABEL: br_jt3_m: ; PIC: # %bb.0: ; PIC-NEXT: and %s0, %s0, (32)0 -; PIC-NEXT: breq.w 1, %s0, .LBB4_1 +; PIC-NEXT: breq.w 1, %s0, .LBB4_6 +; PIC-NEXT: # %bb.1: +; PIC-NEXT: breq.w 4, %s0, .LBB4_4 ; PIC-NEXT: # %bb.2: -; PIC-NEXT: breq.w 4, %s0, .LBB4_5 +; PIC-NEXT: brne.w 2, %s0, .LBB4_5 ; PIC-NEXT: # %bb.3: -; PIC-NEXT: brne.w 2, %s0, .LBB4_6 -; PIC-NEXT: # %bb.4: ; PIC-NEXT: or %s0, 0, (0)1 ; PIC-NEXT: adds.w.sx %s0, %s0, (0)1 ; PIC-NEXT: b.l.t (, %s10) -; PIC-NEXT: .LBB4_5: +; PIC-NEXT: .LBB4_4: ; PIC-NEXT: and %s0, %s1, (32)0 ; PIC-NEXT: adds.w.sx %s0, 3, %s0 -; PIC-NEXT: .LBB4_6: +; PIC-NEXT: .LBB4_5: ; PIC-NEXT: adds.w.sx %s0, %s0, (0)1 ; PIC-NEXT: b.l.t (, %s10) -; PIC-NEXT: .LBB4_1: +; PIC-NEXT: .LBB4_6: ; PIC-NEXT: or %s0, 3, (0)1 ; PIC-NEXT: adds.w.sx %s0, %s0, (0)1 ; PIC-NEXT: b.l.t (, %s10) @@ -456,7 +456,7 @@ define signext i32 @br_jt7_m(i32 signext %0, i32 signext %1) { ; CHECK-NEXT: and %s2, %s0, (32)0 ; CHECK-NEXT: adds.w.sx %s0, -1, %s2 ; CHECK-NEXT: cmpu.w %s3, 8, %s0 -; CHECK-NEXT: brgt.w 0, %s3, .LBB6_8 +; CHECK-NEXT: brgt.w 0, %s3, .LBB6_3 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: sll %s0, %s0, 3 @@ -471,12 +471,12 @@ define signext i32 @br_jt7_m(i32 signext %0, i32 signext %1) { ; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: b.l.t (, %s10) -; CHECK-NEXT: .LBB6_8: +; CHECK-NEXT: .LBB6_3: ; CHECK-NEXT: or %s0, 0, %s2 -; CHECK-NEXT: .LBB6_9: +; CHECK-NEXT: .LBB6_4: ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: b.l.t (, %s10) -; CHECK-NEXT: .LBB6_7: +; CHECK-NEXT: .LBB6_5: ; CHECK-NEXT: or %s0, 11, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -484,15 +484,15 @@ define signext i32 @br_jt7_m(i32 signext %0, i32 signext %1) { ; CHECK-NEXT: or %s0, 10, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: b.l.t (, %s10) -; CHECK-NEXT: .LBB6_3: +; CHECK-NEXT: .LBB6_7: ; CHECK-NEXT: or %s0, 4, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: b.l.t (, %s10) -; CHECK-NEXT: .LBB6_4: +; CHECK-NEXT: .LBB6_8: ; CHECK-NEXT: adds.w.sx %s0, 3, %s1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: b.l.t (, %s10) -; CHECK-NEXT: .LBB6_5: +; CHECK-NEXT: .LBB6_9: ; CHECK-NEXT: adds.w.sx %s0, -2, %s1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -500,50 +500,50 @@ define signext i32 @br_jt7_m(i32 signext %0, i32 signext %1) { ; PIC-LABEL: br_jt7_m: ; PIC: # %bb.0: ; PIC-NEXT: and %s0, %s0, (32)0 -; PIC-NEXT: brge.w 3, %s0, .LBB6_1 -; PIC-NEXT: # %bb.6: -; PIC-NEXT: brlt.w 7, %s0, .LBB6_10 -; PIC-NEXT: # %bb.7: +; PIC-NEXT: brge.w 3, %s0, .LBB6_5 +; PIC-NEXT: # %bb.1: +; PIC-NEXT: brlt.w 7, %s0, .LBB6_9 +; PIC-NEXT: # %bb.2: ; PIC-NEXT: and %s1, %s1, (32)0 -; PIC-NEXT: breq.w 4, %s0, .LBB6_14 -; PIC-NEXT: # %bb.8: -; PIC-NEXT: brne.w 7, %s0, .LBB6_16 -; PIC-NEXT: # %bb.9: +; PIC-NEXT: breq.w 4, %s0, .LBB6_13 +; PIC-NEXT: # %bb.3: +; PIC-NEXT: brne.w 7, %s0, .LBB6_15 +; PIC-NEXT: # %bb.4: ; PIC-NEXT: adds.w.sx %s0, -2, %s1 ; PIC-NEXT: adds.w.sx %s0, %s0, (0)1 ; PIC-NEXT: b.l.t (, %s10) -; PIC-NEXT: .LBB6_1: -; PIC-NEXT: breq.w 1, %s0, .LBB6_2 -; PIC-NEXT: # %bb.3: -; PIC-NEXT: breq.w 2, %s0, .LBB6_13 -; PIC-NEXT: # %bb.4: -; PIC-NEXT: brne.w 3, %s0, .LBB6_16 -; PIC-NEXT: # %bb.5: +; PIC-NEXT: .LBB6_5: +; PIC-NEXT: breq.w 1, %s0, .LBB6_12 +; PIC-NEXT: # %bb.6: +; PIC-NEXT: breq.w 2, %s0, .LBB6_16 +; PIC-NEXT: # %bb.7: +; PIC-NEXT: brne.w 3, %s0, .LBB6_15 +; PIC-NEXT: # %bb.8: ; PIC-NEXT: or %s0, 4, (0)1 ; PIC-NEXT: adds.w.sx %s0, %s0, (0)1 ; PIC-NEXT: b.l.t (, %s10) -; PIC-NEXT: .LBB6_10: -; PIC-NEXT: breq.w 8, %s0, .LBB6_15 +; PIC-NEXT: .LBB6_9: +; PIC-NEXT: breq.w 8, %s0, .LBB6_14 +; PIC-NEXT: # %bb.10: +; PIC-NEXT: brne.w 9, %s0, .LBB6_15 ; PIC-NEXT: # %bb.11: -; PIC-NEXT: brne.w 9, %s0, .LBB6_16 -; PIC-NEXT: # %bb.12: ; PIC-NEXT: or %s0, 10, (0)1 ; PIC-NEXT: adds.w.sx %s0, %s0, (0)1 ; PIC-NEXT: b.l.t (, %s10) -; PIC-NEXT: .LBB6_2: +; PIC-NEXT: .LBB6_12: ; PIC-NEXT: or %s0, 3, (0)1 ; PIC-NEXT: adds.w.sx %s0, %s0, (0)1 ; PIC-NEXT: b.l.t (, %s10) -; PIC-NEXT: .LBB6_14: +; PIC-NEXT: .LBB6_13: ; PIC-NEXT: adds.w.sx %s0, 3, %s1 ; PIC-NEXT: adds.w.sx %s0, %s0, (0)1 ; PIC-NEXT: b.l.t (, %s10) -; PIC-NEXT: .LBB6_15: +; PIC-NEXT: .LBB6_14: ; PIC-NEXT: or %s0, 11, (0)1 -; PIC-NEXT: .LBB6_16: +; PIC-NEXT: .LBB6_15: ; PIC-NEXT: adds.w.sx %s0, %s0, (0)1 ; PIC-NEXT: b.l.t (, %s10) -; PIC-NEXT: .LBB6_13: +; PIC-NEXT: .LBB6_16: ; PIC-NEXT: or %s0, 0, (0)1 ; PIC-NEXT: adds.w.sx %s0, %s0, (0)1 ; PIC-NEXT: b.l.t (, %s10) @@ -592,7 +592,7 @@ define signext i32 @br_jt8_m(i32 signext %0, i32 signext %1) { ; CHECK-NEXT: and %s2, %s0, (32)0 ; CHECK-NEXT: adds.w.sx %s0, -1, %s2 ; CHECK-NEXT: cmpu.w %s3, 8, %s0 -; CHECK-NEXT: brgt.w 0, %s3, .LBB7_9 +; CHECK-NEXT: brgt.w 0, %s3, .LBB7_3 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1 ; CHECK-NEXT: sll %s0, %s0, 3 @@ -607,16 +607,16 @@ define signext i32 @br_jt8_m(i32 signext %0, i32 signext %1) { ; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: b.l.t (, %s10) -; CHECK-NEXT: .LBB7_9: +; CHECK-NEXT: .LBB7_3: ; CHECK-NEXT: or %s0, 0, %s2 -; CHECK-NEXT: .LBB7_10: +; CHECK-NEXT: .LBB7_4: ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: b.l.t (, %s10) -; CHECK-NEXT: .LBB7_6: +; CHECK-NEXT: .LBB7_5: ; CHECK-NEXT: adds.w.sx %s0, -2, %s1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: b.l.t (, %s10) -; CHECK-NEXT: .LBB7_8: +; CHECK-NEXT: .LBB7_6: ; CHECK-NEXT: or %s0, 11, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -624,15 +624,15 @@ define signext i32 @br_jt8_m(i32 signext %0, i32 signext %1) { ; CHECK-NEXT: or %s0, 10, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: b.l.t (, %s10) -; CHECK-NEXT: .LBB7_3: +; CHECK-NEXT: .LBB7_8: ; CHECK-NEXT: or %s0, 4, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: b.l.t (, %s10) -; CHECK-NEXT: .LBB7_4: +; CHECK-NEXT: .LBB7_9: ; CHECK-NEXT: adds.w.sx %s0, 3, %s1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: b.l.t (, %s10) -; CHECK-NEXT: .LBB7_5: +; CHECK-NEXT: .LBB7_10: ; CHECK-NEXT: adds.w.sx %s0, -5, %s1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -648,7 +648,7 @@ define signext i32 @br_jt8_m(i32 signext %0, i32 signext %1) { ; PIC-NEXT: and %s15, %s15, (32)0 ; PIC-NEXT: sic %s16 ; PIC-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15) -; PIC-NEXT: brgt.w 0, %s3, .LBB7_9 +; PIC-NEXT: brgt.w 0, %s3, .LBB7_3 ; PIC-NEXT: # %bb.1: ; PIC-NEXT: and %s1, %s1, (32)0 ; PIC-NEXT: adds.w.zx %s0, %s0, (0)1 @@ -666,25 +666,25 @@ define signext i32 @br_jt8_m(i32 signext %0, i32 signext %1) { ; PIC-NEXT: .LBB7_2: ; PIC-NEXT: or %s0, 0, (0)1 ; PIC-NEXT: br.l.t .LBB7_10 -; PIC-NEXT: .LBB7_9: +; PIC-NEXT: .LBB7_3: ; PIC-NEXT: or %s0, 0, %s2 ; PIC-NEXT: br.l.t .LBB7_10 -; PIC-NEXT: .LBB7_6: +; PIC-NEXT: .LBB7_4: ; PIC-NEXT: adds.w.sx %s0, -2, %s1 ; PIC-NEXT: br.l.t .LBB7_10 -; PIC-NEXT: .LBB7_8: +; PIC-NEXT: .LBB7_5: ; PIC-NEXT: or %s0, 11, (0)1 ; PIC-NEXT: br.l.t .LBB7_10 -; PIC-NEXT: .LBB7_7: +; PIC-NEXT: .LBB7_6: ; PIC-NEXT: or %s0, 10, (0)1 ; PIC-NEXT: br.l.t .LBB7_10 -; PIC-NEXT: .LBB7_3: +; PIC-NEXT: .LBB7_7: ; PIC-NEXT: or %s0, 4, (0)1 ; PIC-NEXT: br.l.t .LBB7_10 -; PIC-NEXT: .LBB7_4: +; PIC-NEXT: .LBB7_8: ; PIC-NEXT: adds.w.sx %s0, 3, %s1 ; PIC-NEXT: br.l.t .LBB7_10 -; PIC-NEXT: .LBB7_5: +; PIC-NEXT: .LBB7_9: ; PIC-NEXT: adds.w.sx %s0, -5, %s1 ; PIC-NEXT: .LBB7_10: ; PIC-NEXT: adds.w.sx %s0, %s0, (0)1 diff --git a/llvm/test/CodeGen/VE/Scalar/brind.ll b/llvm/test/CodeGen/VE/Scalar/brind.ll index b92a4366981ab..a22606f274da3 100644 --- a/llvm/test/CodeGen/VE/Scalar/brind.ll +++ b/llvm/test/CodeGen/VE/Scalar/brind.ll @@ -19,7 +19,7 @@ define signext i32 @brind(i32 signext %0) { ; CHECK-NEXT: cmov.w.eq %s1, %s2, %s0 ; CHECK-NEXT: b.l.t (, %s1) ; CHECK-NEXT: .Ltmp0: # Block address taken -; CHECK-NEXT: .LBB0_3: +; CHECK-NEXT: .LBB0_1: ; CHECK-NEXT: or %s0, -1, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: b.l.t (, %s10) @@ -29,7 +29,7 @@ define signext i32 @brind(i32 signext %0) { ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: b.l.t (, %s10) ; CHECK-NEXT: .Ltmp1: # Block address taken -; CHECK-NEXT: .LBB0_1: +; CHECK-NEXT: .LBB0_3: ; CHECK-NEXT: or %s0, 1, (0)1 ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: b.l.t (, %s10) diff --git a/llvm/test/CodeGen/VE/Scalar/builtin_sjlj.ll b/llvm/test/CodeGen/VE/Scalar/builtin_sjlj.ll index 2713d61d16c2f..e079eacb80da4 100644 --- a/llvm/test/CodeGen/VE/Scalar/builtin_sjlj.ll +++ b/llvm/test/CodeGen/VE/Scalar/builtin_sjlj.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 ; RUN: llc < %s -mtriple=ve | FileCheck %s ; RUN: llc < %s -mtriple=ve -relocation-model=pic | \ ; RUN: FileCheck %s -check-prefix=PIC @@ -9,7 +10,22 @@ ; Function Attrs: noinline nounwind optnone define signext i32 @t_setjmp() { ; CHECK-LABEL: t_setjmp: -; CHECK: .LBB{{[0-9]+}}_5: +; CHECK: # %bb.0: +; CHECK-NEXT: st %s9, (, %s11) +; CHECK-NEXT: st %s10, 8(, %s11) +; CHECK-NEXT: or %s9, 0, %s11 +; CHECK-NEXT: lea %s11, -176(, %s11) +; CHECK-NEXT: brge.l %s11, %s8, .LBB0_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: ld %s61, 24(, %s14) +; CHECK-NEXT: or %s62, 0, %s0 +; CHECK-NEXT: lea %s63, 315 +; CHECK-NEXT: shm.l %s63, (%s61) +; CHECK-NEXT: shm.l %s8, 8(%s61) +; CHECK-NEXT: shm.l %s11, 16(%s61) +; CHECK-NEXT: monc +; CHECK-NEXT: or %s0, 0, %s62 +; CHECK-NEXT: .LBB0_2: ; CHECK-NEXT: st %s18, 48(, %s9) # 8-byte Folded Spill ; CHECK-NEXT: st %s19, 56(, %s9) # 8-byte Folded Spill ; CHECK-NEXT: st %s20, 64(, %s9) # 8-byte Folded Spill @@ -31,17 +47,17 @@ define signext i32 @t_setjmp() { ; CHECK-NEXT: lea.sl %s0, buf@hi(, %s0) ; CHECK-NEXT: st %s9, (, %s0) ; CHECK-NEXT: st %s11, 16(, %s0) -; CHECK-NEXT: lea %s1, .LBB{{[0-9]+}}_3@lo +; CHECK-NEXT: lea %s1, .LBB0_4@lo ; CHECK-NEXT: and %s1, %s1, (32)0 -; CHECK-NEXT: lea.sl %s1, .LBB{{[0-9]+}}_3@hi(, %s1) +; CHECK-NEXT: lea.sl %s1, .LBB0_4@hi(, %s1) ; CHECK-NEXT: st %s1, 8(, %s0) -; CHECK-NEXT: # EH_SJlJ_SETUP .LBB{{[0-9]+}}_3 -; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: # EH_SJlJ_SETUP .LBB0_4 +; CHECK-NEXT: # %bb.3: ; CHECK-NEXT: lea %s0, 0 -; CHECK-NEXT: br.l.t .LBB{{[0-9]+}}_2 -; CHECK-NEXT: .LBB{{[0-9]+}}_3: # Block address taken +; CHECK-NEXT: br.l.t .LBB0_5 +; CHECK-NEXT: .LBB0_4: # Block address taken ; CHECK-NEXT: lea %s0, 1 -; CHECK-NEXT: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: .LBB0_5: ; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 ; CHECK-NEXT: ld %s33, 168(, %s9) # 8-byte Folded Reload ; CHECK-NEXT: ld %s32, 160(, %s9) # 8-byte Folded Reload @@ -60,6 +76,9 @@ define signext i32 @t_setjmp() { ; CHECK-NEXT: ld %s19, 56(, %s9) # 8-byte Folded Reload ; CHECK-NEXT: ld %s18, 48(, %s9) # 8-byte Folded Reload ; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: ld %s10, 8(, %s11) +; CHECK-NEXT: ld %s9, (, %s11) +; CHECK-NEXT: b.l.t (, %s10) ; ; PIC-LABEL: t_setjmp: ; PIC: # %bb.0: @@ -69,8 +88,8 @@ define signext i32 @t_setjmp() { ; PIC-NEXT: st %s16, 32(, %s11) ; PIC-NEXT: or %s9, 0, %s11 ; PIC-NEXT: lea %s11, -176(, %s11) -; PIC-NEXT: brge.l %s11, %s8, .LBB0_5 -; PIC-NEXT: # %bb.4: +; PIC-NEXT: brge.l %s11, %s8, .LBB0_2 +; PIC-NEXT: # %bb.1: ; PIC-NEXT: ld %s61, 24(, %s14) ; PIC-NEXT: or %s62, 0, %s0 ; PIC-NEXT: lea %s63, 315 @@ -79,7 +98,7 @@ define signext i32 @t_setjmp() { ; PIC-NEXT: shm.l %s11, 16(%s61) ; PIC-NEXT: monc ; PIC-NEXT: or %s0, 0, %s62 -; PIC-NEXT: .LBB0_5: +; PIC-NEXT: .LBB0_2: ; PIC-NEXT: st %s18, 48(, %s9) # 8-byte Folded Spill ; PIC-NEXT: st %s19, 56(, %s9) # 8-byte Folded Spill ; PIC-NEXT: st %s20, 64(, %s9) # 8-byte Folded Spill @@ -106,17 +125,17 @@ define signext i32 @t_setjmp() { ; PIC-NEXT: ld %s0, (%s0, %s15) ; PIC-NEXT: st %s9, (, %s0) ; PIC-NEXT: st %s11, 16(, %s0) -; PIC-NEXT: lea %s1, .LBB0_3@gotoff_lo +; PIC-NEXT: lea %s1, .LBB0_4@gotoff_lo ; PIC-NEXT: and %s1, %s1, (32)0 -; PIC-NEXT: lea.sl %s1, .LBB0_3@gotoff_hi(%s1, %s15) +; PIC-NEXT: lea.sl %s1, .LBB0_4@gotoff_hi(%s1, %s15) ; PIC-NEXT: st %s1, 8(, %s0) -; PIC-NEXT: # EH_SJlJ_SETUP .LBB0_3 -; PIC-NEXT: # %bb.1: +; PIC-NEXT: # EH_SJlJ_SETUP .LBB0_4 +; PIC-NEXT: # %bb.3: ; PIC-NEXT: lea %s0, 0 -; PIC-NEXT: br.l.t .LBB0_2 -; PIC-NEXT: .LBB0_3: # Block address taken +; PIC-NEXT: br.l.t .LBB0_5 +; PIC-NEXT: .LBB0_4: # Block address taken ; PIC-NEXT: lea %s0, 1 -; PIC-NEXT: .LBB0_2: +; PIC-NEXT: .LBB0_5: ; PIC-NEXT: adds.w.sx %s0, %s0, (0)1 ; PIC-NEXT: ld %s33, 168(, %s9) # 8-byte Folded Reload ; PIC-NEXT: ld %s32, 160(, %s9) # 8-byte Folded Reload @@ -160,7 +179,22 @@ declare i32 @llvm.eh.sjlj.setjmp(ptr) ; Function Attrs: noinline nounwind optnone define void @t_longjmp() { ; CHECK-LABEL: t_longjmp: -; CHECK: .LBB{{[0-9]+}}_2: +; CHECK: # %bb.0: +; CHECK-NEXT: st %s9, (, %s11) +; CHECK-NEXT: st %s10, 8(, %s11) +; CHECK-NEXT: or %s9, 0, %s11 +; CHECK-NEXT: lea %s11, -176(, %s11) +; CHECK-NEXT: brge.l.t %s11, %s8, .LBB1_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: ld %s61, 24(, %s14) +; CHECK-NEXT: or %s62, 0, %s0 +; CHECK-NEXT: lea %s63, 315 +; CHECK-NEXT: shm.l %s63, (%s61) +; CHECK-NEXT: shm.l %s8, 8(%s61) +; CHECK-NEXT: shm.l %s11, 16(%s61) +; CHECK-NEXT: monc +; CHECK-NEXT: or %s0, 0, %s62 +; CHECK-NEXT: .LBB1_2: ; CHECK-NEXT: lea %s0, buf@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, buf@hi(, %s0) diff --git a/llvm/test/CodeGen/VE/Scalar/builtin_sjlj_bp.ll b/llvm/test/CodeGen/VE/Scalar/builtin_sjlj_bp.ll index 6fdf71da75c4a..a231fe0019a8a 100644 --- a/llvm/test/CodeGen/VE/Scalar/builtin_sjlj_bp.ll +++ b/llvm/test/CodeGen/VE/Scalar/builtin_sjlj_bp.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 ; RUN: llc < %s -mtriple=ve | FileCheck %s %Foo = type { [125 x i8] } @@ -7,7 +8,25 @@ declare i32 @llvm.eh.sjlj.setjmp(ptr) nounwind ; Function Attrs: noinline nounwind optnone define i32 @t_setjmp(i64 %n, ptr byval(%Foo) nocapture readnone align 8 %f) { ; CHECK-LABEL: t_setjmp: -; CHECK: .LBB{{[0-9]+}}_5: +; CHECK: # %bb.0: +; CHECK-NEXT: st %s9, (, %s11) +; CHECK-NEXT: st %s10, 8(, %s11) +; CHECK-NEXT: st %s17, 40(, %s11) +; CHECK-NEXT: or %s9, 0, %s11 +; CHECK-NEXT: lea %s11, -384(, %s11) +; CHECK-NEXT: and %s11, %s11, (58)1 +; CHECK-NEXT: or %s17, 0, %s11 +; CHECK-NEXT: brge.l %s11, %s8, .LBB0_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: ld %s61, 24(, %s14) +; CHECK-NEXT: or %s62, 0, %s0 +; CHECK-NEXT: lea %s63, 315 +; CHECK-NEXT: shm.l %s63, (%s61) +; CHECK-NEXT: shm.l %s8, 8(%s61) +; CHECK-NEXT: shm.l %s11, 16(%s61) +; CHECK-NEXT: monc +; CHECK-NEXT: or %s0, 0, %s62 +; CHECK-NEXT: .LBB0_2: ; CHECK-NEXT: st %s18, 48(, %s9) # 8-byte Folded Spill ; CHECK-NEXT: st %s19, 56(, %s9) # 8-byte Folded Spill ; CHECK-NEXT: st %s20, 64(, %s9) # 8-byte Folded Spill @@ -34,20 +53,20 @@ define i32 @t_setjmp(i64 %n, ptr byval(%Foo) nocapture readnone align 8 %f) { ; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: lea %s1, 240(, %s11) ; CHECK-NEXT: st %s1, 328(, %s17) -; CHECK-NEXT: lea %s0, .LBB{{[0-9]+}}_3@lo +; CHECK-NEXT: lea %s0, .LBB0_4@lo ; CHECK-NEXT: and %s0, %s0, (32)0 -; CHECK-NEXT: lea.sl %s0, .LBB{{[0-9]+}}_3@hi(, %s0) +; CHECK-NEXT: lea.sl %s0, .LBB0_4@hi(, %s0) ; CHECK-NEXT: st %s17, 24(, %s1) ; CHECK-NEXT: st %s1, 296(, %s17) # 8-byte Folded Spill ; CHECK-NEXT: st %s0, 8(, %s1) -; CHECK-NEXT: # EH_SJlJ_SETUP .LBB{{[0-9]+}}_3 -; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: # EH_SJlJ_SETUP .LBB0_4 +; CHECK-NEXT: # %bb.3: ; CHECK-NEXT: lea %s5, 0 -; CHECK-NEXT: br.l.t .LBB{{[0-9]+}}_2 -; CHECK-NEXT: .LBB{{[0-9]+}}_3: # Block address taken +; CHECK-NEXT: br.l.t .LBB0_5 +; CHECK-NEXT: .LBB0_4: # Block address taken ; CHECK-NEXT: ld %s17, 24(, %s10) ; CHECK-NEXT: lea %s5, 1 -; CHECK-NEXT: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: .LBB0_5: ; CHECK-NEXT: lea %s0, whatever@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, whatever@hi(, %s0) @@ -75,6 +94,10 @@ define i32 @t_setjmp(i64 %n, ptr byval(%Foo) nocapture readnone align 8 %f) { ; CHECK-NEXT: ld %s19, 56(, %s9) # 8-byte Folded Reload ; CHECK-NEXT: ld %s18, 48(, %s9) # 8-byte Folded Reload ; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: ld %s17, 40(, %s11) +; CHECK-NEXT: ld %s10, 8(, %s11) +; CHECK-NEXT: ld %s9, (, %s11) +; CHECK-NEXT: b.l.t (, %s10) %buf = alloca [5 x ptr], align 16 %p = alloca ptr, align 8 %q = alloca i8, align 64 diff --git a/llvm/test/CodeGen/VE/Scalar/builtin_sjlj_callsite.ll b/llvm/test/CodeGen/VE/Scalar/builtin_sjlj_callsite.ll index 190d9af3fe0db..73c17007228db 100644 --- a/llvm/test/CodeGen/VE/Scalar/builtin_sjlj_callsite.ll +++ b/llvm/test/CodeGen/VE/Scalar/builtin_sjlj_callsite.ll @@ -11,8 +11,8 @@ define void @test_callsite() personality ptr @__gxx_personality_sj0 { ; CHECK-NEXT: st %s10, 8(, %s11) ; CHECK-NEXT: or %s9, 0, %s11 ; CHECK-NEXT: lea %s11, -432(, %s11) -; CHECK-NEXT: brge.l %s11, %s8, .LBB0_7 -; CHECK-NEXT: # %bb.6: +; CHECK-NEXT: brge.l %s11, %s8, .LBB0_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: ld %s61, 24(, %s14) ; CHECK-NEXT: or %s62, 0, %s0 ; CHECK-NEXT: lea %s63, 315 @@ -21,7 +21,7 @@ define void @test_callsite() personality ptr @__gxx_personality_sj0 { ; CHECK-NEXT: shm.l %s11, 16(%s61) ; CHECK-NEXT: monc ; CHECK-NEXT: or %s0, 0, %s62 -; CHECK-NEXT: .LBB0_7: +; CHECK-NEXT: .LBB0_2: ; CHECK-NEXT: st %s18, 48(, %s9) # 8-byte Folded Spill ; CHECK-NEXT: st %s19, 56(, %s9) # 8-byte Folded Spill ; CHECK-NEXT: st %s20, 64(, %s9) # 8-byte Folded Spill @@ -48,9 +48,9 @@ define void @test_callsite() personality ptr @__gxx_personality_sj0 { ; CHECK-NEXT: st %s0, -48(, %s9) ; CHECK-NEXT: st %s9, -40(, %s9) ; CHECK-NEXT: st %s11, -24(, %s9) -; CHECK-NEXT: lea %s0, .LBB0_3@lo +; CHECK-NEXT: lea %s0, .LBB0_4@lo ; CHECK-NEXT: and %s0, %s0, (32)0 -; CHECK-NEXT: lea.sl %s0, .LBB0_3@hi(, %s0) +; CHECK-NEXT: lea.sl %s0, .LBB0_4@hi(, %s0) ; CHECK-NEXT: st %s0, -32(, %s9) ; CHECK-NEXT: lea %s0, _Unwind_SjLj_Register@lo ; CHECK-NEXT: and %s0, %s0, (32)0 @@ -59,13 +59,13 @@ define void @test_callsite() personality ptr @__gxx_personality_sj0 { ; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: or %s0, 1, (0)1 ; CHECK-NEXT: st %s0, -96(, %s9) -; CHECK-NEXT: .Ltmp0: +; CHECK-NEXT: .Ltmp0: # EH_LABEL ; CHECK-NEXT: lea %s0, f@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, f@hi(, %s0) ; CHECK-NEXT: bsic %s10, (, %s12) -; CHECK-NEXT: .Ltmp1: -; CHECK-NEXT: .LBB0_2: # %try.cont +; CHECK-NEXT: .Ltmp1: # EH_LABEL +; CHECK-NEXT: .LBB0_3: # %try.cont ; CHECK-NEXT: or %s0, -1, (0)1 ; CHECK-NEXT: st %s0, -96(, %s9) ; CHECK-NEXT: lea %s0, _Unwind_SjLj_Unregister@lo @@ -97,26 +97,26 @@ define void @test_callsite() personality ptr @__gxx_personality_sj0 { ; CHECK-NEXT: ld %s10, 8(, %s11) ; CHECK-NEXT: ld %s9, (, %s11) ; CHECK-NEXT: b.l.t (, %s10) -; CHECK-NEXT: .LBB0_3: +; CHECK-NEXT: .LBB0_4: ; CHECK-NEXT: ldl.zx %s0, -96(, %s9) -; CHECK-NEXT: brgt.l 1, %s0, .LBB0_4 +; CHECK-NEXT: brgt.l 1, %s0, .LBB0_6 ; CHECK-NEXT: # %bb.5: ; CHECK-NEXT: lea %s0, abort@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, abort@hi(, %s0) ; CHECK-NEXT: bsic %s10, (, %s0) -; CHECK-NEXT: .LBB0_4: +; CHECK-NEXT: .LBB0_6: ; CHECK-NEXT: lea %s1, .LJTI0_0@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, .LJTI0_0@hi(, %s1) ; CHECK-NEXT: sll %s0, %s0, 3 ; CHECK-NEXT: ld %s0, (%s0, %s1) ; CHECK-NEXT: b.l.t (, %s0) -; CHECK-NEXT: .LBB0_1: # %lpad -; CHECK-NEXT: .Ltmp2: +; CHECK-NEXT: .LBB0_7: # %lpad +; CHECK-NEXT: .Ltmp2: # EH_LABEL ; CHECK-NEXT: ld %s0, -88(, %s9) ; CHECK-NEXT: ld %s0, -80(, %s9) -; CHECK-NEXT: br.l.t .LBB0_2 +; CHECK-NEXT: br.l.t .LBB0_3 ; ; PIC-LABEL: test_callsite: ; PIC: # %bb.0: @@ -126,8 +126,8 @@ define void @test_callsite() personality ptr @__gxx_personality_sj0 { ; PIC-NEXT: st %s16, 32(, %s11) ; PIC-NEXT: or %s9, 0, %s11 ; PIC-NEXT: lea %s11, -432(, %s11) -; PIC-NEXT: brge.l %s11, %s8, .LBB0_7 -; PIC-NEXT: # %bb.6: +; PIC-NEXT: brge.l %s11, %s8, .LBB0_2 +; PIC-NEXT: # %bb.1: ; PIC-NEXT: ld %s61, 24(, %s14) ; PIC-NEXT: or %s62, 0, %s0 ; PIC-NEXT: lea %s63, 315 @@ -136,7 +136,7 @@ define void @test_callsite() personality ptr @__gxx_personality_sj0 { ; PIC-NEXT: shm.l %s11, 16(%s61) ; PIC-NEXT: monc ; PIC-NEXT: or %s0, 0, %s62 -; PIC-NEXT: .LBB0_7: +; PIC-NEXT: .LBB0_2: ; PIC-NEXT: st %s18, 48(, %s9) # 8-byte Folded Spill ; PIC-NEXT: st %s19, 56(, %s9) # 8-byte Folded Spill ; PIC-NEXT: st %s20, 64(, %s9) # 8-byte Folded Spill @@ -168,9 +168,9 @@ define void @test_callsite() personality ptr @__gxx_personality_sj0 { ; PIC-NEXT: st %s0, -48(, %s9) ; PIC-NEXT: st %s9, -40(, %s9) ; PIC-NEXT: st %s11, -24(, %s9) -; PIC-NEXT: lea %s0, .LBB0_3@gotoff_lo +; PIC-NEXT: lea %s0, .LBB0_4@gotoff_lo ; PIC-NEXT: and %s0, %s0, (32)0 -; PIC-NEXT: lea.sl %s0, .LBB0_3@gotoff_hi(%s0, %s15) +; PIC-NEXT: lea.sl %s0, .LBB0_4@gotoff_hi(%s0, %s15) ; PIC-NEXT: st %s0, -32(, %s9) ; PIC-NEXT: lea %s12, _Unwind_SjLj_Register@plt_lo(-24) ; PIC-NEXT: and %s12, %s12, (32)0 @@ -180,14 +180,14 @@ define void @test_callsite() personality ptr @__gxx_personality_sj0 { ; PIC-NEXT: bsic %s10, (, %s12) ; PIC-NEXT: or %s0, 1, (0)1 ; PIC-NEXT: st %s0, -96(, %s9) -; PIC-NEXT: .Ltmp0: +; PIC-NEXT: .Ltmp0: # EH_LABEL ; PIC-NEXT: lea %s12, f@plt_lo(-24) ; PIC-NEXT: and %s12, %s12, (32)0 ; PIC-NEXT: sic %s16 ; PIC-NEXT: lea.sl %s12, f@plt_hi(%s16, %s12) ; PIC-NEXT: bsic %s10, (, %s12) -; PIC-NEXT: .Ltmp1: -; PIC-NEXT: .LBB0_2: # %try.cont +; PIC-NEXT: .Ltmp1: # EH_LABEL +; PIC-NEXT: .LBB0_3: # %try.cont ; PIC-NEXT: or %s0, -1, (0)1 ; PIC-NEXT: st %s0, -96(, %s9) ; PIC-NEXT: lea %s18, _Unwind_SjLj_Unregister@plt_lo(-24) @@ -222,20 +222,20 @@ define void @test_callsite() personality ptr @__gxx_personality_sj0 { ; PIC-NEXT: ld %s10, 8(, %s11) ; PIC-NEXT: ld %s9, (, %s11) ; PIC-NEXT: b.l.t (, %s10) -; PIC-NEXT: .LBB0_3: +; PIC-NEXT: .LBB0_4: ; PIC-NEXT: ldl.zx %s0, -96(, %s9) ; PIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24) ; PIC-NEXT: and %s15, %s15, (32)0 ; PIC-NEXT: sic %s16 ; PIC-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15) -; PIC-NEXT: brgt.l 1, %s0, .LBB0_4 +; PIC-NEXT: brgt.l 1, %s0, .LBB0_6 ; PIC-NEXT: # %bb.5: ; PIC-NEXT: lea %s0, abort@plt_lo(-24) ; PIC-NEXT: and %s0, %s0, (32)0 ; PIC-NEXT: sic %s16 ; PIC-NEXT: lea.sl %s0, abort@plt_hi(%s16, %s0) ; PIC-NEXT: bsic %s10, (, %s0) -; PIC-NEXT: .LBB0_4: +; PIC-NEXT: .LBB0_6: ; PIC-NEXT: lea %s1, .LJTI0_0@gotoff_lo ; PIC-NEXT: and %s1, %s1, (32)0 ; PIC-NEXT: lea.sl %s1, .LJTI0_0@gotoff_hi(%s1, %s15) @@ -246,11 +246,11 @@ define void @test_callsite() personality ptr @__gxx_personality_sj0 { ; PIC-NEXT: lea.sl %s1, test_callsite@gotoff_hi(%s1, %s15) ; PIC-NEXT: adds.l %s0, %s0, %s1 ; PIC-NEXT: b.l.t (, %s0) -; PIC-NEXT: .LBB0_1: # %lpad -; PIC-NEXT: .Ltmp2: +; PIC-NEXT: .LBB0_7: # %lpad +; PIC-NEXT: .Ltmp2: # EH_LABEL ; PIC-NEXT: ld %s0, -88(, %s9) ; PIC-NEXT: ld %s0, -80(, %s9) -; PIC-NEXT: br.l.t .LBB0_2 +; PIC-NEXT: br.l.t .LBB0_3 %fn_context = alloca { ptr, i32, [4 x i32], ptr, ptr, [5 x ptr] }, align 4 call void @llvm.eh.sjlj.callsite(i32 0) invoke void @f() diff --git a/llvm/test/CodeGen/VE/Scalar/builtin_sjlj_landingpad.ll b/llvm/test/CodeGen/VE/Scalar/builtin_sjlj_landingpad.ll index f255be5eecb99..bf6cc35cb9568 100644 --- a/llvm/test/CodeGen/VE/Scalar/builtin_sjlj_landingpad.ll +++ b/llvm/test/CodeGen/VE/Scalar/builtin_sjlj_landingpad.ll @@ -12,8 +12,8 @@ define dso_local i32 @foo(i32 %arg) local_unnamed_addr personality ptr @__gxx_pe ; CHECK-NEXT: st %s10, 8(, %s11) ; CHECK-NEXT: or %s9, 0, %s11 ; CHECK-NEXT: lea %s11, -352(, %s11) -; CHECK-NEXT: brge.l %s11, %s8, .LBB0_8 -; CHECK-NEXT: # %bb.7: # %entry +; CHECK-NEXT: brge.l %s11, %s8, .LBB0_2 +; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: ld %s61, 24(, %s14) ; CHECK-NEXT: or %s62, 0, %s0 ; CHECK-NEXT: lea %s63, 315 @@ -22,7 +22,7 @@ define dso_local i32 @foo(i32 %arg) local_unnamed_addr personality ptr @__gxx_pe ; CHECK-NEXT: shm.l %s11, 16(%s61) ; CHECK-NEXT: monc ; CHECK-NEXT: or %s0, 0, %s62 -; CHECK-NEXT: .LBB0_8: # %entry +; CHECK-NEXT: .LBB0_2: # %entry ; CHECK-NEXT: st %s18, 48(, %s9) # 8-byte Folded Spill ; CHECK-NEXT: st %s19, 56(, %s9) # 8-byte Folded Spill ; CHECK-NEXT: st %s20, 64(, %s9) # 8-byte Folded Spill @@ -49,9 +49,9 @@ define dso_local i32 @foo(i32 %arg) local_unnamed_addr personality ptr @__gxx_pe ; CHECK-NEXT: st %s0, -48(, %s9) ; CHECK-NEXT: st %s9, -40(, %s9) ; CHECK-NEXT: st %s11, -24(, %s9) -; CHECK-NEXT: lea %s0, .LBB0_3@lo +; CHECK-NEXT: lea %s0, .LBB0_5@lo ; CHECK-NEXT: and %s0, %s0, (32)0 -; CHECK-NEXT: lea.sl %s0, .LBB0_3@hi(, %s0) +; CHECK-NEXT: lea.sl %s0, .LBB0_5@hi(, %s0) ; CHECK-NEXT: st %s0, -32(, %s9) ; CHECK-NEXT: lea %s0, _Unwind_SjLj_Register@lo ; CHECK-NEXT: and %s0, %s0, (32)0 @@ -60,20 +60,20 @@ define dso_local i32 @foo(i32 %arg) local_unnamed_addr personality ptr @__gxx_pe ; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: or %s0, 1, (0)1 ; CHECK-NEXT: st %s0, -96(, %s9) -; CHECK-NEXT: .Ltmp0: +; CHECK-NEXT: .Ltmp0: # EH_LABEL ; CHECK-NEXT: lea %s0, errorbar@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, errorbar@hi(, %s0) ; CHECK-NEXT: bsic %s10, (, %s12) -; CHECK-NEXT: .Ltmp1: -; CHECK-NEXT: # %bb.1: # %exit +; CHECK-NEXT: .Ltmp1: # EH_LABEL +; CHECK-NEXT: # %bb.3: # %exit ; CHECK-NEXT: lea %s0, _Unwind_SjLj_Unregister@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s12, _Unwind_SjLj_Unregister@hi(, %s0) ; CHECK-NEXT: lea %s0, -104(, %s9) ; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: or %s0, 0, (0)1 -; CHECK-NEXT: .LBB0_2: # %exit +; CHECK-NEXT: .LBB0_4: # %exit ; CHECK-NEXT: ld %s33, 168(, %s9) # 8-byte Folded Reload ; CHECK-NEXT: ld %s32, 160(, %s9) # 8-byte Folded Reload ; CHECK-NEXT: ld %s31, 152(, %s9) # 8-byte Folded Reload @@ -94,23 +94,23 @@ define dso_local i32 @foo(i32 %arg) local_unnamed_addr personality ptr @__gxx_pe ; CHECK-NEXT: ld %s10, 8(, %s11) ; CHECK-NEXT: ld %s9, (, %s11) ; CHECK-NEXT: b.l.t (, %s10) -; CHECK-NEXT: .LBB0_3: +; CHECK-NEXT: .LBB0_5: ; CHECK-NEXT: ldl.zx %s0, -96(, %s9) -; CHECK-NEXT: brgt.l 1, %s0, .LBB0_4 -; CHECK-NEXT: # %bb.5: +; CHECK-NEXT: brgt.l 1, %s0, .LBB0_7 +; CHECK-NEXT: # %bb.6: ; CHECK-NEXT: lea %s0, abort@lo ; CHECK-NEXT: and %s0, %s0, (32)0 ; CHECK-NEXT: lea.sl %s0, abort@hi(, %s0) ; CHECK-NEXT: bsic %s10, (, %s0) -; CHECK-NEXT: .LBB0_4: +; CHECK-NEXT: .LBB0_7: ; CHECK-NEXT: lea %s1, .LJTI0_0@lo ; CHECK-NEXT: and %s1, %s1, (32)0 ; CHECK-NEXT: lea.sl %s1, .LJTI0_0@hi(, %s1) ; CHECK-NEXT: sll %s0, %s0, 3 ; CHECK-NEXT: ld %s0, (%s0, %s1) ; CHECK-NEXT: b.l.t (, %s0) -; CHECK-NEXT: .LBB0_6: # %handle -; CHECK-NEXT: .Ltmp2: +; CHECK-NEXT: .LBB0_8: # %handle +; CHECK-NEXT: .Ltmp2: # EH_LABEL ; CHECK-NEXT: ld %s0, -88(, %s9) ; CHECK-NEXT: ld %s0, -80(, %s9) ; CHECK-NEXT: lea %s0, _Unwind_SjLj_Unregister@lo @@ -119,7 +119,7 @@ define dso_local i32 @foo(i32 %arg) local_unnamed_addr personality ptr @__gxx_pe ; CHECK-NEXT: lea %s0, -104(, %s9) ; CHECK-NEXT: bsic %s10, (, %s12) ; CHECK-NEXT: or %s0, 1, (0)1 -; CHECK-NEXT: br.l.t .LBB0_2 +; CHECK-NEXT: br.l.t .LBB0_4 ; ; PIC-LABEL: foo: ; PIC: # %bb.0: # %entry @@ -129,8 +129,8 @@ define dso_local i32 @foo(i32 %arg) local_unnamed_addr personality ptr @__gxx_pe ; PIC-NEXT: st %s16, 32(, %s11) ; PIC-NEXT: or %s9, 0, %s11 ; PIC-NEXT: lea %s11, -352(, %s11) -; PIC-NEXT: brge.l %s11, %s8, .LBB0_8 -; PIC-NEXT: # %bb.7: # %entry +; PIC-NEXT: brge.l %s11, %s8, .LBB0_2 +; PIC-NEXT: # %bb.1: # %entry ; PIC-NEXT: ld %s61, 24(, %s14) ; PIC-NEXT: or %s62, 0, %s0 ; PIC-NEXT: lea %s63, 315 @@ -139,7 +139,7 @@ define dso_local i32 @foo(i32 %arg) local_unnamed_addr personality ptr @__gxx_pe ; PIC-NEXT: shm.l %s11, 16(%s61) ; PIC-NEXT: monc ; PIC-NEXT: or %s0, 0, %s62 -; PIC-NEXT: .LBB0_8: # %entry +; PIC-NEXT: .LBB0_2: # %entry ; PIC-NEXT: st %s18, 48(, %s9) # 8-byte Folded Spill ; PIC-NEXT: st %s19, 56(, %s9) # 8-byte Folded Spill ; PIC-NEXT: st %s20, 64(, %s9) # 8-byte Folded Spill @@ -171,9 +171,9 @@ define dso_local i32 @foo(i32 %arg) local_unnamed_addr personality ptr @__gxx_pe ; PIC-NEXT: st %s0, -48(, %s9) ; PIC-NEXT: st %s9, -40(, %s9) ; PIC-NEXT: st %s11, -24(, %s9) -; PIC-NEXT: lea %s0, .LBB0_3@gotoff_lo +; PIC-NEXT: lea %s0, .LBB0_5@gotoff_lo ; PIC-NEXT: and %s0, %s0, (32)0 -; PIC-NEXT: lea.sl %s0, .LBB0_3@gotoff_hi(%s0, %s15) +; PIC-NEXT: lea.sl %s0, .LBB0_5@gotoff_hi(%s0, %s15) ; PIC-NEXT: st %s0, -32(, %s9) ; PIC-NEXT: lea %s12, _Unwind_SjLj_Register@plt_lo(-24) ; PIC-NEXT: and %s12, %s12, (32)0 @@ -183,14 +183,14 @@ define dso_local i32 @foo(i32 %arg) local_unnamed_addr personality ptr @__gxx_pe ; PIC-NEXT: bsic %s10, (, %s12) ; PIC-NEXT: or %s0, 1, (0)1 ; PIC-NEXT: st %s0, -96(, %s9) -; PIC-NEXT: .Ltmp0: +; PIC-NEXT: .Ltmp0: # EH_LABEL ; PIC-NEXT: lea %s12, errorbar@plt_lo(-24) ; PIC-NEXT: and %s12, %s12, (32)0 ; PIC-NEXT: sic %s16 ; PIC-NEXT: lea.sl %s12, errorbar@plt_hi(%s16, %s12) ; PIC-NEXT: bsic %s10, (, %s12) -; PIC-NEXT: .Ltmp1: -; PIC-NEXT: # %bb.1: # %exit +; PIC-NEXT: .Ltmp1: # EH_LABEL +; PIC-NEXT: # %bb.3: # %exit ; PIC-NEXT: lea %s12, _Unwind_SjLj_Unregister@plt_lo(-24) ; PIC-NEXT: and %s12, %s12, (32)0 ; PIC-NEXT: sic %s16 @@ -198,7 +198,7 @@ define dso_local i32 @foo(i32 %arg) local_unnamed_addr personality ptr @__gxx_pe ; PIC-NEXT: lea %s0, -104(, %s9) ; PIC-NEXT: bsic %s10, (, %s12) ; PIC-NEXT: or %s0, 0, (0)1 -; PIC-NEXT: .LBB0_2: # %exit +; PIC-NEXT: .LBB0_4: # %exit ; PIC-NEXT: ld %s33, 168(, %s9) # 8-byte Folded Reload ; PIC-NEXT: ld %s32, 160(, %s9) # 8-byte Folded Reload ; PIC-NEXT: ld %s31, 152(, %s9) # 8-byte Folded Reload @@ -221,20 +221,20 @@ define dso_local i32 @foo(i32 %arg) local_unnamed_addr personality ptr @__gxx_pe ; PIC-NEXT: ld %s10, 8(, %s11) ; PIC-NEXT: ld %s9, (, %s11) ; PIC-NEXT: b.l.t (, %s10) -; PIC-NEXT: .LBB0_3: +; PIC-NEXT: .LBB0_5: ; PIC-NEXT: ldl.zx %s0, -96(, %s9) ; PIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24) ; PIC-NEXT: and %s15, %s15, (32)0 ; PIC-NEXT: sic %s16 ; PIC-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15) -; PIC-NEXT: brgt.l 1, %s0, .LBB0_4 -; PIC-NEXT: # %bb.5: +; PIC-NEXT: brgt.l 1, %s0, .LBB0_7 +; PIC-NEXT: # %bb.6: ; PIC-NEXT: lea %s0, abort@plt_lo(-24) ; PIC-NEXT: and %s0, %s0, (32)0 ; PIC-NEXT: sic %s16 ; PIC-NEXT: lea.sl %s0, abort@plt_hi(%s16, %s0) ; PIC-NEXT: bsic %s10, (, %s0) -; PIC-NEXT: .LBB0_4: +; PIC-NEXT: .LBB0_7: ; PIC-NEXT: lea %s1, .LJTI0_0@gotoff_lo ; PIC-NEXT: and %s1, %s1, (32)0 ; PIC-NEXT: lea.sl %s1, .LJTI0_0@gotoff_hi(%s1, %s15) @@ -245,8 +245,8 @@ define dso_local i32 @foo(i32 %arg) local_unnamed_addr personality ptr @__gxx_pe ; PIC-NEXT: lea.sl %s1, foo@gotoff_hi(%s1, %s15) ; PIC-NEXT: adds.l %s0, %s0, %s1 ; PIC-NEXT: b.l.t (, %s0) -; PIC-NEXT: .LBB0_6: # %handle -; PIC-NEXT: .Ltmp2: +; PIC-NEXT: .LBB0_8: # %handle +; PIC-NEXT: .Ltmp2: # EH_LABEL ; PIC-NEXT: ld %s0, -88(, %s9) ; PIC-NEXT: ld %s0, -80(, %s9) ; PIC-NEXT: lea %s12, _Unwind_SjLj_Unregister@plt_lo(-24) @@ -256,7 +256,7 @@ define dso_local i32 @foo(i32 %arg) local_unnamed_addr personality ptr @__gxx_pe ; PIC-NEXT: lea %s0, -104(, %s9) ; PIC-NEXT: bsic %s10, (, %s12) ; PIC-NEXT: or %s0, 1, (0)1 -; PIC-NEXT: br.l.t .LBB0_2 +; PIC-NEXT: br.l.t .LBB0_4 entry: invoke void @errorbar() to label %exit unwind label %handle diff --git a/llvm/test/CodeGen/VE/Scalar/load_stk.ll b/llvm/test/CodeGen/VE/Scalar/load_stk.ll index 9ffab1464a992..d80f16b4a38b1 100644 --- a/llvm/test/CodeGen/VE/Scalar/load_stk.ll +++ b/llvm/test/CodeGen/VE/Scalar/load_stk.ll @@ -129,8 +129,8 @@ define x86_fastcallcc i64 @loadi64_stk_big() { ; CHECK-LABEL: loadi64_stk_big: ; CHECK: # %bb.0: ; CHECK-NEXT: lea %s11, -2147483648(, %s11) -; CHECK-NEXT: brge.l %s11, %s8, .LBB1_4 -; CHECK-NEXT: # %bb.3: +; CHECK-NEXT: brge.l %s11, %s8, .LBB1_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: ld %s61, 24(, %s14) ; CHECK-NEXT: or %s62, 0, %s0 ; CHECK-NEXT: lea %s63, 315 @@ -139,15 +139,15 @@ define x86_fastcallcc i64 @loadi64_stk_big() { ; CHECK-NEXT: shm.l %s11, 16(%s61) ; CHECK-NEXT: monc ; CHECK-NEXT: or %s0, 0, %s62 -; CHECK-NEXT: .LBB1_4: +; CHECK-NEXT: .LBB1_2: ; CHECK-NEXT: ld %s0, 2147483640(, %s11) ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: lea %s2, 2147483640 -; CHECK-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: .LBB1_3: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ld %s3, (%s1, %s11) ; CHECK-NEXT: lea %s1, 8(, %s1) -; CHECK-NEXT: brne.l %s1, %s2, .LBB1_1 -; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: brne.l %s1, %s2, .LBB1_3 +; CHECK-NEXT: # %bb.4: ; CHECK-NEXT: lea %s13, -2147483648 ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s11, (%s13, %s11) @@ -180,8 +180,8 @@ define x86_fastcallcc i64 @loadi64_stk_big2() { ; CHECK-NEXT: lea %s13, 2147483632 ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) -; CHECK-NEXT: brge.l %s11, %s8, .LBB2_4 -; CHECK-NEXT: # %bb.3: +; CHECK-NEXT: brge.l %s11, %s8, .LBB2_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: ld %s61, 24(, %s14) ; CHECK-NEXT: or %s62, 0, %s0 ; CHECK-NEXT: lea %s63, 315 @@ -190,7 +190,7 @@ define x86_fastcallcc i64 @loadi64_stk_big2() { ; CHECK-NEXT: shm.l %s11, 16(%s61) ; CHECK-NEXT: monc ; CHECK-NEXT: or %s0, 0, %s62 -; CHECK-NEXT: .LBB2_4: +; CHECK-NEXT: .LBB2_2: ; CHECK-NEXT: lea %s13, -2147483640 ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s13, (%s11, %s13) @@ -198,11 +198,11 @@ define x86_fastcallcc i64 @loadi64_stk_big2() { ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: lea %s2, -2147483648 ; CHECK-NEXT: and %s2, %s2, (32)0 -; CHECK-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: .LBB2_3: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ld %s3, 8(%s1, %s11) ; CHECK-NEXT: lea %s1, 8(, %s1) -; CHECK-NEXT: brne.l %s1, %s2, .LBB2_1 -; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: brne.l %s1, %s2, .LBB2_3 +; CHECK-NEXT: # %bb.4: ; CHECK-NEXT: lea %s13, -2147483632 ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s11, (%s13, %s11) @@ -464,8 +464,8 @@ define x86_fastcallcc fp128 @loadquad_stk_big() { ; CHECK-NEXT: lea %s13, 2147483632 ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) -; CHECK-NEXT: brge.l %s11, %s8, .LBB8_4 -; CHECK-NEXT: # %bb.3: +; CHECK-NEXT: brge.l %s11, %s8, .LBB8_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: ld %s61, 24(, %s14) ; CHECK-NEXT: or %s62, 0, %s0 ; CHECK-NEXT: lea %s63, 315 @@ -474,7 +474,7 @@ define x86_fastcallcc fp128 @loadquad_stk_big() { ; CHECK-NEXT: shm.l %s11, 16(%s61) ; CHECK-NEXT: monc ; CHECK-NEXT: or %s0, 0, %s62 -; CHECK-NEXT: .LBB8_4: +; CHECK-NEXT: .LBB8_2: ; CHECK-NEXT: lea %s13, -2147483648 ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s13, (%s11, %s13) @@ -482,11 +482,11 @@ define x86_fastcallcc fp128 @loadquad_stk_big() { ; CHECK-NEXT: ld %s0, 8(, %s13) ; CHECK-NEXT: or %s2, 0, (0)1 ; CHECK-NEXT: lea %s3, 2147483640 -; CHECK-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: .LBB8_3: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ld %s4, 8(%s2, %s11) ; CHECK-NEXT: lea %s2, 8(, %s2) -; CHECK-NEXT: brne.l %s2, %s3, .LBB8_1 -; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: brne.l %s2, %s3, .LBB8_3 +; CHECK-NEXT: # %bb.4: ; CHECK-NEXT: lea %s13, -2147483632 ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s11, (%s13, %s11) @@ -519,8 +519,8 @@ define x86_fastcallcc fp128 @loadquad_stk_big2() { ; CHECK-NEXT: lea %s13, 2147483632 ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) -; CHECK-NEXT: brge.l %s11, %s8, .LBB9_4 -; CHECK-NEXT: # %bb.3: +; CHECK-NEXT: brge.l %s11, %s8, .LBB9_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: ld %s61, 24(, %s14) ; CHECK-NEXT: or %s62, 0, %s0 ; CHECK-NEXT: lea %s63, 315 @@ -529,7 +529,7 @@ define x86_fastcallcc fp128 @loadquad_stk_big2() { ; CHECK-NEXT: shm.l %s11, 16(%s61) ; CHECK-NEXT: monc ; CHECK-NEXT: or %s0, 0, %s62 -; CHECK-NEXT: .LBB9_4: +; CHECK-NEXT: .LBB9_2: ; CHECK-NEXT: lea %s13, -2147483648 ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s13, (%s11, %s13) @@ -538,11 +538,11 @@ define x86_fastcallcc fp128 @loadquad_stk_big2() { ; CHECK-NEXT: or %s2, 0, (0)1 ; CHECK-NEXT: lea %s3, -2147483648 ; CHECK-NEXT: and %s3, %s3, (32)0 -; CHECK-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: .LBB9_3: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ld %s4, (%s2, %s11) ; CHECK-NEXT: lea %s2, 8(, %s2) -; CHECK-NEXT: brne.l %s2, %s3, .LBB9_1 -; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: brne.l %s2, %s3, .LBB9_3 +; CHECK-NEXT: # %bb.4: ; CHECK-NEXT: lea %s13, -2147483632 ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s11, (%s13, %s11) diff --git a/llvm/test/CodeGen/VE/Scalar/store_stk.ll b/llvm/test/CodeGen/VE/Scalar/store_stk.ll index 76a3fda813620..8d8fa477123eb 100644 --- a/llvm/test/CodeGen/VE/Scalar/store_stk.ll +++ b/llvm/test/CodeGen/VE/Scalar/store_stk.ll @@ -129,8 +129,8 @@ define x86_fastcallcc void @storei64_stk_big(i64 noundef %0, i64 noundef %1) { ; CHECK-LABEL: storei64_stk_big: ; CHECK: # %bb.0: ; CHECK-NEXT: lea %s11, -2147483648(, %s11) -; CHECK-NEXT: brge.l %s11, %s8, .LBB1_4 -; CHECK-NEXT: # %bb.3: +; CHECK-NEXT: brge.l %s11, %s8, .LBB1_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: ld %s61, 24(, %s14) ; CHECK-NEXT: or %s62, 0, %s0 ; CHECK-NEXT: lea %s63, 315 @@ -139,15 +139,15 @@ define x86_fastcallcc void @storei64_stk_big(i64 noundef %0, i64 noundef %1) { ; CHECK-NEXT: shm.l %s11, 16(%s61) ; CHECK-NEXT: monc ; CHECK-NEXT: or %s0, 0, %s62 -; CHECK-NEXT: .LBB1_4: +; CHECK-NEXT: .LBB1_2: ; CHECK-NEXT: st %s0, 2147483640(, %s11) ; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: lea %s2, 2147483640 -; CHECK-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: .LBB1_3: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: st %s1, (%s0, %s11) ; CHECK-NEXT: lea %s0, 8(, %s0) -; CHECK-NEXT: brne.l %s0, %s2, .LBB1_1 -; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: brne.l %s0, %s2, .LBB1_3 +; CHECK-NEXT: # %bb.4: ; CHECK-NEXT: lea %s13, -2147483648 ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s11, (%s13, %s11) @@ -180,8 +180,8 @@ define x86_fastcallcc void @storei64_stk_big2(i64 noundef %0, i64 noundef %1) { ; CHECK-NEXT: lea %s13, 2147483632 ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) -; CHECK-NEXT: brge.l %s11, %s8, .LBB2_4 -; CHECK-NEXT: # %bb.3: +; CHECK-NEXT: brge.l %s11, %s8, .LBB2_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: ld %s61, 24(, %s14) ; CHECK-NEXT: or %s62, 0, %s0 ; CHECK-NEXT: lea %s63, 315 @@ -190,7 +190,7 @@ define x86_fastcallcc void @storei64_stk_big2(i64 noundef %0, i64 noundef %1) { ; CHECK-NEXT: shm.l %s11, 16(%s61) ; CHECK-NEXT: monc ; CHECK-NEXT: or %s0, 0, %s62 -; CHECK-NEXT: .LBB2_4: +; CHECK-NEXT: .LBB2_2: ; CHECK-NEXT: lea %s13, -2147483640 ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s13, (%s11, %s13) @@ -198,11 +198,11 @@ define x86_fastcallcc void @storei64_stk_big2(i64 noundef %0, i64 noundef %1) { ; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: lea %s2, -2147483648 ; CHECK-NEXT: and %s2, %s2, (32)0 -; CHECK-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: .LBB2_3: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: st %s1, 8(%s0, %s11) ; CHECK-NEXT: lea %s0, 8(, %s0) -; CHECK-NEXT: brne.l %s0, %s2, .LBB2_1 -; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: brne.l %s0, %s2, .LBB2_3 +; CHECK-NEXT: # %bb.4: ; CHECK-NEXT: lea %s13, -2147483632 ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s11, (%s13, %s11) @@ -469,8 +469,8 @@ define x86_fastcallcc void @storequad_stk_big(fp128 noundef %0, i64 noundef %1) ; CHECK-NEXT: lea %s13, 2147483632 ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) -; CHECK-NEXT: brge.l %s11, %s8, .LBB8_4 -; CHECK-NEXT: # %bb.3: +; CHECK-NEXT: brge.l %s11, %s8, .LBB8_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: ld %s61, 24(, %s14) ; CHECK-NEXT: or %s62, 0, %s0 ; CHECK-NEXT: lea %s63, 315 @@ -479,7 +479,7 @@ define x86_fastcallcc void @storequad_stk_big(fp128 noundef %0, i64 noundef %1) ; CHECK-NEXT: shm.l %s11, 16(%s61) ; CHECK-NEXT: monc ; CHECK-NEXT: or %s0, 0, %s62 -; CHECK-NEXT: .LBB8_4: +; CHECK-NEXT: .LBB8_2: ; CHECK-NEXT: lea %s13, -2147483648 ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s13, (%s11, %s13) @@ -487,11 +487,11 @@ define x86_fastcallcc void @storequad_stk_big(fp128 noundef %0, i64 noundef %1) ; CHECK-NEXT: st %s0, 8(, %s13) ; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: lea %s1, 2147483640 -; CHECK-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: .LBB8_3: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: st %s2, 8(%s0, %s11) ; CHECK-NEXT: lea %s0, 8(, %s0) -; CHECK-NEXT: brne.l %s0, %s1, .LBB8_1 -; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: brne.l %s0, %s1, .LBB8_3 +; CHECK-NEXT: # %bb.4: ; CHECK-NEXT: lea %s13, -2147483632 ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s11, (%s13, %s11) @@ -524,8 +524,8 @@ define x86_fastcallcc void @storequad_stk_big2(fp128 noundef %0, i64 noundef %1) ; CHECK-NEXT: lea %s13, 2147483632 ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) -; CHECK-NEXT: brge.l %s11, %s8, .LBB9_4 -; CHECK-NEXT: # %bb.3: +; CHECK-NEXT: brge.l %s11, %s8, .LBB9_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: ld %s61, 24(, %s14) ; CHECK-NEXT: or %s62, 0, %s0 ; CHECK-NEXT: lea %s63, 315 @@ -534,7 +534,7 @@ define x86_fastcallcc void @storequad_stk_big2(fp128 noundef %0, i64 noundef %1) ; CHECK-NEXT: shm.l %s11, 16(%s61) ; CHECK-NEXT: monc ; CHECK-NEXT: or %s0, 0, %s62 -; CHECK-NEXT: .LBB9_4: +; CHECK-NEXT: .LBB9_2: ; CHECK-NEXT: lea %s13, -2147483648 ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s13, (%s11, %s13) @@ -543,11 +543,11 @@ define x86_fastcallcc void @storequad_stk_big2(fp128 noundef %0, i64 noundef %1) ; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: lea %s1, -2147483648 ; CHECK-NEXT: and %s1, %s1, (32)0 -; CHECK-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: .LBB9_3: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: st %s2, (%s0, %s11) ; CHECK-NEXT: lea %s0, 8(, %s0) -; CHECK-NEXT: brne.l %s0, %s1, .LBB9_1 -; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: brne.l %s0, %s1, .LBB9_3 +; CHECK-NEXT: # %bb.4: ; CHECK-NEXT: lea %s13, -2147483632 ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s11, (%s13, %s11) diff --git a/llvm/test/CodeGen/VE/Vector/load_stk_ldvm.ll b/llvm/test/CodeGen/VE/Vector/load_stk_ldvm.ll index 18464d9e24341..6edd4832bb6ef 100644 --- a/llvm/test/CodeGen/VE/Vector/load_stk_ldvm.ll +++ b/llvm/test/CodeGen/VE/Vector/load_stk_ldvm.ll @@ -146,8 +146,8 @@ define fastcc <256 x i1> @load__vm256_stk_big_fit() { ; CHECK-NEXT: or %s9, 0, %s11 ; CHECK-NEXT: lea %s11, -2147483648(, %s11) ; CHECK-NEXT: and %s11, %s11, (59)1 -; CHECK-NEXT: brge.l %s11, %s8, .LBB1_4 -; CHECK-NEXT: # %bb.3: +; CHECK-NEXT: brge.l %s11, %s8, .LBB1_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: ld %s61, 24(, %s14) ; CHECK-NEXT: or %s62, 0, %s0 ; CHECK-NEXT: lea %s63, 315 @@ -156,7 +156,7 @@ define fastcc <256 x i1> @load__vm256_stk_big_fit() { ; CHECK-NEXT: shm.l %s11, 16(%s61) ; CHECK-NEXT: monc ; CHECK-NEXT: or %s0, 0, %s62 -; CHECK-NEXT: .LBB1_4: +; CHECK-NEXT: .LBB1_2: ; CHECK-NEXT: ld %s16, 2147483616(, %s11) ; CHECK-NEXT: lvm %vm1, 0, %s16 ; CHECK-NEXT: ld %s16, 2147483624(, %s11) @@ -167,11 +167,11 @@ define fastcc <256 x i1> @load__vm256_stk_big_fit() { ; CHECK-NEXT: lvm %vm1, 3, %s16 ; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: lea %s1, 2147483424 -; CHECK-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: .LBB1_3: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ld %s2, 192(%s0, %s11) ; CHECK-NEXT: lea %s0, 8(, %s0) -; CHECK-NEXT: brne.l %s0, %s1, .LBB1_1 -; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: brne.l %s0, %s1, .LBB1_3 +; CHECK-NEXT: # %bb.4: ; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: ld %s10, 8(, %s11) ; CHECK-NEXT: ld %s9, (, %s11) @@ -208,8 +208,8 @@ define fastcc <256 x i1> @load__vm256_stk_big() { ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) ; CHECK-NEXT: and %s11, %s11, (59)1 -; CHECK-NEXT: brge.l %s11, %s8, .LBB2_4 -; CHECK-NEXT: # %bb.3: +; CHECK-NEXT: brge.l %s11, %s8, .LBB2_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: ld %s61, 24(, %s14) ; CHECK-NEXT: or %s62, 0, %s0 ; CHECK-NEXT: lea %s63, 315 @@ -218,7 +218,7 @@ define fastcc <256 x i1> @load__vm256_stk_big() { ; CHECK-NEXT: shm.l %s11, 16(%s61) ; CHECK-NEXT: monc ; CHECK-NEXT: or %s0, 0, %s62 -; CHECK-NEXT: .LBB2_4: +; CHECK-NEXT: .LBB2_2: ; CHECK-NEXT: lea %s13, -2147483648 ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s13, (%s11, %s13) @@ -232,11 +232,11 @@ define fastcc <256 x i1> @load__vm256_stk_big() { ; CHECK-NEXT: lvm %vm1, 3, %s16 ; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: lea %s1, 2147483432 -; CHECK-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: .LBB2_3: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ld %s2, 216(%s0, %s11) ; CHECK-NEXT: lea %s0, 8(, %s0) -; CHECK-NEXT: brne.l %s0, %s1, .LBB2_1 -; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: brne.l %s0, %s1, .LBB2_3 +; CHECK-NEXT: # %bb.4: ; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: ld %s10, 8(, %s11) ; CHECK-NEXT: ld %s9, (, %s11) @@ -273,8 +273,8 @@ define fastcc <256 x i1> @load__vm256_stk_big2() { ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) ; CHECK-NEXT: and %s11, %s11, (59)1 -; CHECK-NEXT: brge.l %s11, %s8, .LBB3_4 -; CHECK-NEXT: # %bb.3: +; CHECK-NEXT: brge.l %s11, %s8, .LBB3_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: ld %s61, 24(, %s14) ; CHECK-NEXT: or %s62, 0, %s0 ; CHECK-NEXT: lea %s63, 315 @@ -283,7 +283,7 @@ define fastcc <256 x i1> @load__vm256_stk_big2() { ; CHECK-NEXT: shm.l %s11, 16(%s61) ; CHECK-NEXT: monc ; CHECK-NEXT: or %s0, 0, %s62 -; CHECK-NEXT: .LBB3_4: +; CHECK-NEXT: .LBB3_2: ; CHECK-NEXT: lea %s13, -2147483456 ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s13, (%s11, %s13) @@ -298,11 +298,11 @@ define fastcc <256 x i1> @load__vm256_stk_big2() { ; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: lea %s1, -2147483648 ; CHECK-NEXT: and %s1, %s1, (32)0 -; CHECK-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: .LBB3_3: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ld %s2, 192(%s0, %s11) ; CHECK-NEXT: lea %s0, 8(, %s0) -; CHECK-NEXT: brne.l %s0, %s1, .LBB3_1 -; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: brne.l %s0, %s1, .LBB3_3 +; CHECK-NEXT: # %bb.4: ; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: ld %s10, 8(, %s11) ; CHECK-NEXT: ld %s9, (, %s11) @@ -644,8 +644,8 @@ define fastcc <512 x i1> @load__vm512_stk_big_fit() { ; CHECK-NEXT: or %s9, 0, %s11 ; CHECK-NEXT: lea %s11, -2147483648(, %s11) ; CHECK-NEXT: and %s11, %s11, (58)1 -; CHECK-NEXT: brge.l %s11, %s8, .LBB9_4 -; CHECK-NEXT: # %bb.3: +; CHECK-NEXT: brge.l %s11, %s8, .LBB9_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: ld %s61, 24(, %s14) ; CHECK-NEXT: or %s62, 0, %s0 ; CHECK-NEXT: lea %s63, 315 @@ -654,7 +654,7 @@ define fastcc <512 x i1> @load__vm512_stk_big_fit() { ; CHECK-NEXT: shm.l %s11, 16(%s61) ; CHECK-NEXT: monc ; CHECK-NEXT: or %s0, 0, %s62 -; CHECK-NEXT: .LBB9_4: +; CHECK-NEXT: .LBB9_2: ; CHECK-NEXT: # implicit-def: $vmp1 ; CHECK-NEXT: ld %s16, 2147483584(, %s11) ; CHECK-NEXT: lvm %vm3, 0, %s16 @@ -674,11 +674,11 @@ define fastcc <512 x i1> @load__vm512_stk_big_fit() { ; CHECK-NEXT: lvm %vm2, 3, %s16 ; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: lea %s1, 2147483392 -; CHECK-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: .LBB9_3: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ld %s2, 192(%s0, %s11) ; CHECK-NEXT: lea %s0, 8(, %s0) -; CHECK-NEXT: brne.l %s0, %s1, .LBB9_1 -; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: brne.l %s0, %s1, .LBB9_3 +; CHECK-NEXT: # %bb.4: ; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: ld %s10, 8(, %s11) ; CHECK-NEXT: ld %s9, (, %s11) @@ -715,8 +715,8 @@ define fastcc <512 x i1> @load__vm512_stk_big() { ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) ; CHECK-NEXT: and %s11, %s11, (58)1 -; CHECK-NEXT: brge.l %s11, %s8, .LBB10_4 -; CHECK-NEXT: # %bb.3: +; CHECK-NEXT: brge.l %s11, %s8, .LBB10_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: ld %s61, 24(, %s14) ; CHECK-NEXT: or %s62, 0, %s0 ; CHECK-NEXT: lea %s63, 315 @@ -725,7 +725,7 @@ define fastcc <512 x i1> @load__vm512_stk_big() { ; CHECK-NEXT: shm.l %s11, 16(%s61) ; CHECK-NEXT: monc ; CHECK-NEXT: or %s0, 0, %s62 -; CHECK-NEXT: .LBB10_4: +; CHECK-NEXT: .LBB10_2: ; CHECK-NEXT: lea %s13, -2147483648 ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s13, (%s11, %s13) @@ -748,11 +748,11 @@ define fastcc <512 x i1> @load__vm512_stk_big() { ; CHECK-NEXT: lvm %vm2, 3, %s16 ; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: lea %s1, 2147483400 -; CHECK-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: .LBB10_3: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ld %s2, 248(%s0, %s11) ; CHECK-NEXT: lea %s0, 8(, %s0) -; CHECK-NEXT: brne.l %s0, %s1, .LBB10_1 -; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: brne.l %s0, %s1, .LBB10_3 +; CHECK-NEXT: # %bb.4: ; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: ld %s10, 8(, %s11) ; CHECK-NEXT: ld %s9, (, %s11) @@ -789,8 +789,8 @@ define fastcc <512 x i1> @load__vm512_stk_big2() { ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) ; CHECK-NEXT: and %s11, %s11, (58)1 -; CHECK-NEXT: brge.l %s11, %s8, .LBB11_4 -; CHECK-NEXT: # %bb.3: +; CHECK-NEXT: brge.l %s11, %s8, .LBB11_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: ld %s61, 24(, %s14) ; CHECK-NEXT: or %s62, 0, %s0 ; CHECK-NEXT: lea %s63, 315 @@ -799,7 +799,7 @@ define fastcc <512 x i1> @load__vm512_stk_big2() { ; CHECK-NEXT: shm.l %s11, 16(%s61) ; CHECK-NEXT: monc ; CHECK-NEXT: or %s0, 0, %s62 -; CHECK-NEXT: .LBB11_4: +; CHECK-NEXT: .LBB11_2: ; CHECK-NEXT: lea %s13, -2147483456 ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s13, (%s11, %s13) @@ -823,11 +823,11 @@ define fastcc <512 x i1> @load__vm512_stk_big2() { ; CHECK-NEXT: or %s0, 0, (0)1 ; CHECK-NEXT: lea %s1, -2147483648 ; CHECK-NEXT: and %s1, %s1, (32)0 -; CHECK-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: .LBB11_3: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ld %s2, 192(%s0, %s11) ; CHECK-NEXT: lea %s0, 8(, %s0) -; CHECK-NEXT: brne.l %s0, %s1, .LBB11_1 -; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: brne.l %s0, %s1, .LBB11_3 +; CHECK-NEXT: # %bb.4: ; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: ld %s10, 8(, %s11) ; CHECK-NEXT: ld %s9, (, %s11) diff --git a/llvm/test/CodeGen/VE/Vector/store_stk_stvm.ll b/llvm/test/CodeGen/VE/Vector/store_stk_stvm.ll index 5a443bb3ee9e1..521a3de80718d 100644 --- a/llvm/test/CodeGen/VE/Vector/store_stk_stvm.ll +++ b/llvm/test/CodeGen/VE/Vector/store_stk_stvm.ll @@ -146,8 +146,8 @@ define fastcc void @store__vm256_stk_big_fit(<256 x i1> noundef %0, i64 noundef ; CHECK-NEXT: or %s9, 0, %s11 ; CHECK-NEXT: lea %s11, -2147483648(, %s11) ; CHECK-NEXT: and %s11, %s11, (59)1 -; CHECK-NEXT: brge.l %s11, %s8, .LBB1_4 -; CHECK-NEXT: # %bb.3: +; CHECK-NEXT: brge.l %s11, %s8, .LBB1_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: ld %s61, 24(, %s14) ; CHECK-NEXT: or %s62, 0, %s0 ; CHECK-NEXT: lea %s63, 315 @@ -156,7 +156,7 @@ define fastcc void @store__vm256_stk_big_fit(<256 x i1> noundef %0, i64 noundef ; CHECK-NEXT: shm.l %s11, 16(%s61) ; CHECK-NEXT: monc ; CHECK-NEXT: or %s0, 0, %s62 -; CHECK-NEXT: .LBB1_4: +; CHECK-NEXT: .LBB1_2: ; CHECK-NEXT: svm %s16, %vm1, 0 ; CHECK-NEXT: st %s16, 2147483616(, %s11) ; CHECK-NEXT: svm %s16, %vm1, 1 @@ -167,11 +167,11 @@ define fastcc void @store__vm256_stk_big_fit(<256 x i1> noundef %0, i64 noundef ; CHECK-NEXT: st %s16, 2147483640(, %s11) ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: lea %s2, 2147483424 -; CHECK-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: .LBB1_3: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: st %s0, 192(%s1, %s11) ; CHECK-NEXT: lea %s1, 8(, %s1) -; CHECK-NEXT: brne.l %s1, %s2, .LBB1_1 -; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: brne.l %s1, %s2, .LBB1_3 +; CHECK-NEXT: # %bb.4: ; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: ld %s10, 8(, %s11) ; CHECK-NEXT: ld %s9, (, %s11) @@ -208,8 +208,8 @@ define fastcc void @store__vm256_stk_big(<256 x i1> noundef %0, i64 noundef %1) ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) ; CHECK-NEXT: and %s11, %s11, (59)1 -; CHECK-NEXT: brge.l %s11, %s8, .LBB2_4 -; CHECK-NEXT: # %bb.3: +; CHECK-NEXT: brge.l %s11, %s8, .LBB2_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: ld %s61, 24(, %s14) ; CHECK-NEXT: or %s62, 0, %s0 ; CHECK-NEXT: lea %s63, 315 @@ -218,7 +218,7 @@ define fastcc void @store__vm256_stk_big(<256 x i1> noundef %0, i64 noundef %1) ; CHECK-NEXT: shm.l %s11, 16(%s61) ; CHECK-NEXT: monc ; CHECK-NEXT: or %s0, 0, %s62 -; CHECK-NEXT: .LBB2_4: +; CHECK-NEXT: .LBB2_2: ; CHECK-NEXT: lea %s13, -2147483648 ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s13, (%s11, %s13) @@ -232,11 +232,11 @@ define fastcc void @store__vm256_stk_big(<256 x i1> noundef %0, i64 noundef %1) ; CHECK-NEXT: st %s16, 24(, %s13) ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: lea %s2, 2147483432 -; CHECK-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: .LBB2_3: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: st %s0, 216(%s1, %s11) ; CHECK-NEXT: lea %s1, 8(, %s1) -; CHECK-NEXT: brne.l %s1, %s2, .LBB2_1 -; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: brne.l %s1, %s2, .LBB2_3 +; CHECK-NEXT: # %bb.4: ; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: ld %s10, 8(, %s11) ; CHECK-NEXT: ld %s9, (, %s11) @@ -273,8 +273,8 @@ define fastcc void @store__vm256_stk_big2(<256 x i1> noundef %0, i64 noundef %1) ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) ; CHECK-NEXT: and %s11, %s11, (59)1 -; CHECK-NEXT: brge.l %s11, %s8, .LBB3_4 -; CHECK-NEXT: # %bb.3: +; CHECK-NEXT: brge.l %s11, %s8, .LBB3_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: ld %s61, 24(, %s14) ; CHECK-NEXT: or %s62, 0, %s0 ; CHECK-NEXT: lea %s63, 315 @@ -283,7 +283,7 @@ define fastcc void @store__vm256_stk_big2(<256 x i1> noundef %0, i64 noundef %1) ; CHECK-NEXT: shm.l %s11, 16(%s61) ; CHECK-NEXT: monc ; CHECK-NEXT: or %s0, 0, %s62 -; CHECK-NEXT: .LBB3_4: +; CHECK-NEXT: .LBB3_2: ; CHECK-NEXT: lea %s13, -2147483456 ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s13, (%s11, %s13) @@ -298,11 +298,11 @@ define fastcc void @store__vm256_stk_big2(<256 x i1> noundef %0, i64 noundef %1) ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: lea %s2, -2147483648 ; CHECK-NEXT: and %s2, %s2, (32)0 -; CHECK-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: .LBB3_3: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: st %s0, 192(%s1, %s11) ; CHECK-NEXT: lea %s1, 8(, %s1) -; CHECK-NEXT: brne.l %s1, %s2, .LBB3_1 -; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: brne.l %s1, %s2, .LBB3_3 +; CHECK-NEXT: # %bb.4: ; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: ld %s10, 8(, %s11) ; CHECK-NEXT: ld %s9, (, %s11) @@ -726,8 +726,8 @@ define fastcc void @store__vm512_stk_big(<512 x i1> noundef %0, i64 noundef %1) ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) ; CHECK-NEXT: and %s11, %s11, (58)1 -; CHECK-NEXT: brge.l %s11, %s8, .LBB10_4 -; CHECK-NEXT: # %bb.3: +; CHECK-NEXT: brge.l %s11, %s8, .LBB10_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: ld %s61, 24(, %s14) ; CHECK-NEXT: or %s62, 0, %s0 ; CHECK-NEXT: lea %s63, 315 @@ -736,7 +736,7 @@ define fastcc void @store__vm512_stk_big(<512 x i1> noundef %0, i64 noundef %1) ; CHECK-NEXT: shm.l %s11, 16(%s61) ; CHECK-NEXT: monc ; CHECK-NEXT: or %s0, 0, %s62 -; CHECK-NEXT: .LBB10_4: +; CHECK-NEXT: .LBB10_2: ; CHECK-NEXT: lea %s13, -2147483456 ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s13, (%s11, %s13) @@ -758,11 +758,11 @@ define fastcc void @store__vm512_stk_big(<512 x i1> noundef %0, i64 noundef %1) ; CHECK-NEXT: st %s16, 56(, %s13) ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: lea %s2, 2147483640 -; CHECK-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: .LBB10_3: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: st %s0, 200(%s1, %s11) ; CHECK-NEXT: lea %s1, 8(, %s1) -; CHECK-NEXT: brne.l %s1, %s2, .LBB10_1 -; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: brne.l %s1, %s2, .LBB10_3 +; CHECK-NEXT: # %bb.4: ; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: ld %s10, 8(, %s11) ; CHECK-NEXT: ld %s9, (, %s11) @@ -799,8 +799,8 @@ define fastcc void @store__vm512_stk_big2(<512 x i1> noundef %0, i64 noundef %1) ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) ; CHECK-NEXT: and %s11, %s11, (58)1 -; CHECK-NEXT: brge.l %s11, %s8, .LBB11_4 -; CHECK-NEXT: # %bb.3: +; CHECK-NEXT: brge.l %s11, %s8, .LBB11_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: ld %s61, 24(, %s14) ; CHECK-NEXT: or %s62, 0, %s0 ; CHECK-NEXT: lea %s63, 315 @@ -809,7 +809,7 @@ define fastcc void @store__vm512_stk_big2(<512 x i1> noundef %0, i64 noundef %1) ; CHECK-NEXT: shm.l %s11, 16(%s61) ; CHECK-NEXT: monc ; CHECK-NEXT: or %s0, 0, %s62 -; CHECK-NEXT: .LBB11_4: +; CHECK-NEXT: .LBB11_2: ; CHECK-NEXT: lea %s13, -2147483456 ; CHECK-NEXT: and %s13, %s13, (32)0 ; CHECK-NEXT: lea.sl %s13, (%s11, %s13) @@ -832,11 +832,11 @@ define fastcc void @store__vm512_stk_big2(<512 x i1> noundef %0, i64 noundef %1) ; CHECK-NEXT: or %s1, 0, (0)1 ; CHECK-NEXT: lea %s2, -2147483648 ; CHECK-NEXT: and %s2, %s2, (32)0 -; CHECK-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: .LBB11_3: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: st %s0, 192(%s1, %s11) ; CHECK-NEXT: lea %s1, 8(, %s1) -; CHECK-NEXT: brne.l %s1, %s2, .LBB11_1 -; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: brne.l %s1, %s2, .LBB11_3 +; CHECK-NEXT: # %bb.4: ; CHECK-NEXT: or %s11, 0, %s9 ; CHECK-NEXT: ld %s10, 8(, %s11) ; CHECK-NEXT: ld %s9, (, %s11) diff --git a/llvm/test/CodeGen/WinEH/wineh-dynamic-alloca.ll b/llvm/test/CodeGen/WinEH/wineh-dynamic-alloca.ll index aee1838445c56..35e5668c049ef 100644 --- a/llvm/test/CodeGen/WinEH/wineh-dynamic-alloca.ll +++ b/llvm/test/CodeGen/WinEH/wineh-dynamic-alloca.ll @@ -24,9 +24,9 @@ define dso_local noundef i32 @foo() local_unnamed_addr #0 personality ptr @__Cxx ; CHECK-NEXT: movl %ecx, -24(%ebp) ; CHECK-NEXT: movl %eax, %fs:0 ; CHECK-NEXT: cmpb $1, _bar -; CHECK-NEXT: je LBB0_1 -; CHECK-NEXT: LBB0_5: # %exit -; CHECK-NEXT: $ehgcr_0_5: +; CHECK-NEXT: je LBB0_2 +; CHECK-NEXT: LBB0_1: # %exit +; CHECK-NEXT: $ehgcr_0_1: ; CHECK-NEXT: movl -24(%ebp), %eax ; CHECK-NEXT: movl %eax, %fs:0 ; CHECK-NEXT: xorl %eax, %eax @@ -36,7 +36,7 @@ define dso_local noundef i32 @foo() local_unnamed_addr #0 personality ptr @__Cxx ; CHECK-NEXT: popl %ebx ; CHECK-NEXT: popl %ebp ; CHECK-NEXT: retl -; CHECK-NEXT: LBB0_1: # %if.then +; CHECK-NEXT: LBB0_2: # %if.then ; CHECK-NEXT: pushl %eax ; CHECK-NEXT: pushl %eax ; CHECK-NEXT: movl %esp, %eax @@ -44,22 +44,22 @@ define dso_local noundef i32 @foo() local_unnamed_addr #0 personality ptr @__Cxx ; CHECK-NEXT: movl $123, (%eax) ; CHECK-NEXT: movl $0, -16(%ebp) ; CHECK-NEXT: calll _alwaysthrows -; CHECK-NEXT: # %bb.4: # %unreachable.i -; CHECK-NEXT: LBB0_3: # Block address taken +; CHECK-NEXT: # %bb.3: # %unreachable.i +; CHECK-NEXT: LBB0_4: # Block address taken ; CHECK-NEXT: # %catch.i ; CHECK-NEXT: addl $12, %ebp -; CHECK-NEXT: jmp LBB0_5 -; CHECK-NEXT: .def "?catch$2@?0?foo@4HA"; +; CHECK-NEXT: jmp LBB0_1 +; CHECK-NEXT: .def "?catch$5@?0?foo@4HA"; ; CHECK-NEXT: .scl 3; ; CHECK-NEXT: .type 32; ; CHECK-NEXT: .endef ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: "?catch$2@?0?foo@4HA": -; CHECK-NEXT: LBB0_2: # %catch.i +; CHECK-NEXT: "?catch$5@?0?foo@4HA": +; CHECK-NEXT: LBB0_5: # %catch.i ; CHECK-NEXT: pushl %ebp ; CHECK-NEXT: addl $12, %ebp ; CHECK-NEXT: movl %esp, -28(%ebp) -; CHECK-NEXT: movl $LBB0_3, %eax +; CHECK-NEXT: movl $LBB0_4, %eax ; CHECK-NEXT: popl %ebp ; CHECK-NEXT: retl # CATCHRET ; CHECK-NEXT: Lfunc_end0: diff --git a/llvm/test/CodeGen/WinEH/wineh-inlined-inalloca.ll b/llvm/test/CodeGen/WinEH/wineh-inlined-inalloca.ll index 87f6d000e4b58..55a47cfed4880 100644 --- a/llvm/test/CodeGen/WinEH/wineh-inlined-inalloca.ll +++ b/llvm/test/CodeGen/WinEH/wineh-inlined-inalloca.ll @@ -29,13 +29,13 @@ define dso_local noundef i32 @foo() local_unnamed_addr #0 personality ptr @__Cxx ; CHECK-NEXT: calll _bar ; CHECK-NEXT: movl $0, -16(%ebp) ; CHECK-NEXT: calll _alwaysthrows -; CHECK-NEXT: # %bb.3: # %unreachable.i +; CHECK-NEXT: # %bb.1: # %unreachable.i ; CHECK-NEXT: LBB0_2: # Block address taken ; CHECK-NEXT: # %catch.i ; CHECK-NEXT: addl $12, %ebp -; CHECK-NEXT: jmp LBB0_4 -; CHECK-NEXT: LBB0_4: # %exit -; CHECK-NEXT: $ehgcr_0_4: +; CHECK-NEXT: jmp LBB0_3 +; CHECK-NEXT: LBB0_3: # %exit +; CHECK-NEXT: $ehgcr_0_3: ; CHECK-NEXT: movl -24(%ebp), %eax ; CHECK-NEXT: movl %eax, %fs:0 ; CHECK-NEXT: xorl %eax, %eax @@ -45,13 +45,13 @@ define dso_local noundef i32 @foo() local_unnamed_addr #0 personality ptr @__Cxx ; CHECK-NEXT: popl %ebx ; CHECK-NEXT: popl %ebp ; CHECK-NEXT: retl -; CHECK-NEXT: .def "?catch$1@?0?foo@4HA"; +; CHECK-NEXT: .def "?catch$4@?0?foo@4HA"; ; CHECK-NEXT: .scl 3; ; CHECK-NEXT: .type 32; ; CHECK-NEXT: .endef ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: "?catch$1@?0?foo@4HA": -; CHECK-NEXT: LBB0_1: # %catch.i +; CHECK-NEXT: "?catch$4@?0?foo@4HA": +; CHECK-NEXT: LBB0_4: # %catch.i ; CHECK-NEXT: pushl %ebp ; CHECK-NEXT: addl $12, %ebp ; CHECK-NEXT: movl %esp, -28(%ebp) diff --git a/llvm/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll b/llvm/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll index 1e5ee2f71d9b4..5f4728da464ba 100644 --- a/llvm/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll +++ b/llvm/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll @@ -21,32 +21,32 @@ define dso_local void @foo(ptr %a0, ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5) ; CHECK-NEXT: movq %rsp, %rcx ; CHECK-NEXT: subl %r8d, %eax ; CHECK-NEXT: movslq %eax, %rdx -; CHECK-NEXT: js .LBB0_1 -; CHECK-NEXT: # %bb.11: # %b63 +; CHECK-NEXT: js .LBB0_7 +; CHECK-NEXT: # %bb.1: # %b63 ; CHECK-NEXT: testq %rdx, %rdx -; CHECK-NEXT: js .LBB0_14 -; CHECK-NEXT: # %bb.12: +; CHECK-NEXT: js .LBB0_4 +; CHECK-NEXT: # %bb.2: ; CHECK-NEXT: xorl %r8d, %r8d ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_13: # %a25b +; CHECK-NEXT: .LBB0_3: # %a25b ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: testb %r8b, %r8b -; CHECK-NEXT: je .LBB0_13 -; CHECK-NEXT: .LBB0_14: # %b85 +; CHECK-NEXT: je .LBB0_3 +; CHECK-NEXT: .LBB0_4: # %b85 ; CHECK-NEXT: movb $1, %r8b ; CHECK-NEXT: testb %r8b, %r8b -; CHECK-NEXT: jne .LBB0_1 -; CHECK-NEXT: # %bb.15: +; CHECK-NEXT: jne .LBB0_7 +; CHECK-NEXT: # %bb.5: ; CHECK-NEXT: xorl %r8d, %r8d ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_16: # %a25b140 +; CHECK-NEXT: .LBB0_6: # %a25b140 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: testb %r8b, %r8b -; CHECK-NEXT: je .LBB0_16 -; CHECK-NEXT: .LBB0_1: # %a29b +; CHECK-NEXT: je .LBB0_6 +; CHECK-NEXT: .LBB0_7: # %a29b ; CHECK-NEXT: cmpl %esi, %edi -; CHECK-NEXT: js .LBB0_10 -; CHECK-NEXT: # %bb.2: # %b158 +; CHECK-NEXT: js .LBB0_39 +; CHECK-NEXT: # %bb.8: # %b158 ; CHECK-NEXT: movslq (%r9), %rsi ; CHECK-NEXT: movl %esi, %edi ; CHECK-NEXT: orl %eax, %edi @@ -55,82 +55,82 @@ define dso_local void @foo(ptr %a0, ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5) ; CHECK-NEXT: xorl %r9d, %r9d ; CHECK-NEXT: xorps %xmm0, %xmm0 ; CHECK-NEXT: movb $1, %r10b -; CHECK-NEXT: jmp .LBB0_3 +; CHECK-NEXT: jmp .LBB0_10 ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .LBB0_9: # %b1606 -; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1 +; CHECK-NEXT: # in Loop: Header=BB0_10 Depth=1 ; CHECK-NEXT: testb %r9b, %r9b -; CHECK-NEXT: je .LBB0_10 -; CHECK-NEXT: .LBB0_3: # %a29b173 +; CHECK-NEXT: je .LBB0_39 +; CHECK-NEXT: .LBB0_10: # %a29b173 ; CHECK-NEXT: # =>This Loop Header: Depth=1 -; CHECK-NEXT: # Child Loop BB0_36 Depth 2 -; CHECK-NEXT: # Child Loop BB0_19 Depth 2 -; CHECK-NEXT: # Child Loop BB0_20 Depth 2 -; CHECK-NEXT: # Child Loop BB0_37 Depth 3 -; CHECK-NEXT: # Child Loop BB0_22 Depth 2 -; CHECK-NEXT: # Child Loop BB0_23 Depth 3 -; CHECK-NEXT: # Child Loop BB0_25 Depth 2 +; CHECK-NEXT: # Child Loop BB0_12 Depth 2 +; CHECK-NEXT: # Child Loop BB0_14 Depth 2 +; CHECK-NEXT: # Child Loop BB0_24 Depth 2 +; CHECK-NEXT: # Child Loop BB0_25 Depth 3 +; CHECK-NEXT: # Child Loop BB0_37 Depth 2 ; CHECK-NEXT: # Child Loop BB0_38 Depth 3 +; CHECK-NEXT: # Child Loop BB0_27 Depth 2 ; CHECK-NEXT: # Child Loop BB0_28 Depth 3 -; CHECK-NEXT: # Child Loop BB0_29 Depth 2 -; CHECK-NEXT: # Child Loop BB0_39 Depth 3 -; CHECK-NEXT: # Child Loop BB0_32 Depth 3 -; CHECK-NEXT: # Child Loop BB0_33 Depth 2 -; CHECK-NEXT: # Child Loop BB0_35 Depth 2 +; CHECK-NEXT: # Child Loop BB0_30 Depth 3 +; CHECK-NEXT: # Child Loop BB0_32 Depth 2 +; CHECK-NEXT: # Child Loop BB0_33 Depth 3 +; CHECK-NEXT: # Child Loop BB0_35 Depth 3 +; CHECK-NEXT: # Child Loop BB0_19 Depth 2 +; CHECK-NEXT: # Child Loop BB0_22 Depth 2 ; CHECK-NEXT: testl %eax, %eax -; CHECK-NEXT: js .LBB0_4 -; CHECK-NEXT: # %bb.17: # %b179 -; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1 +; CHECK-NEXT: js .LBB0_15 +; CHECK-NEXT: # %bb.11: # %b179 +; CHECK-NEXT: # in Loop: Header=BB0_10 Depth=1 ; CHECK-NEXT: testq %rdx, %rdx -; CHECK-NEXT: js .LBB0_18 +; CHECK-NEXT: js .LBB0_13 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_36: # %a30b -; CHECK-NEXT: # Parent Loop BB0_3 Depth=1 +; CHECK-NEXT: .LBB0_12: # %a30b +; CHECK-NEXT: # Parent Loop BB0_10 Depth=1 ; CHECK-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-NEXT: testb %r9b, %r9b -; CHECK-NEXT: je .LBB0_36 -; CHECK-NEXT: .LBB0_18: # %b188 -; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1 +; CHECK-NEXT: je .LBB0_12 +; CHECK-NEXT: .LBB0_13: # %b188 +; CHECK-NEXT: # in Loop: Header=BB0_10 Depth=1 ; CHECK-NEXT: testb %r10b, %r10b -; CHECK-NEXT: jne .LBB0_4 +; CHECK-NEXT: jne .LBB0_15 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_19: # %a30b294 -; CHECK-NEXT: # Parent Loop BB0_3 Depth=1 +; CHECK-NEXT: .LBB0_14: # %a30b294 +; CHECK-NEXT: # Parent Loop BB0_10 Depth=1 ; CHECK-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-NEXT: testb %r9b, %r9b -; CHECK-NEXT: je .LBB0_19 -; CHECK-NEXT: .LBB0_4: # %a33b -; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1 +; CHECK-NEXT: je .LBB0_14 +; CHECK-NEXT: .LBB0_15: # %a33b +; CHECK-NEXT: # in Loop: Header=BB0_10 Depth=1 ; CHECK-NEXT: testl %edi, %edi -; CHECK-NEXT: jns .LBB0_20 -; CHECK-NEXT: .LBB0_5: # %a50b -; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1 +; CHECK-NEXT: jns .LBB0_24 +; CHECK-NEXT: .LBB0_16: # %a50b +; CHECK-NEXT: # in Loop: Header=BB0_10 Depth=1 ; CHECK-NEXT: testl %edi, %edi -; CHECK-NEXT: jns .LBB0_25 -; CHECK-NEXT: .LBB0_6: # %a57b -; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1 +; CHECK-NEXT: jns .LBB0_27 +; CHECK-NEXT: .LBB0_17: # %a57b +; CHECK-NEXT: # in Loop: Header=BB0_10 Depth=1 ; CHECK-NEXT: testb %r8b, %r8b -; CHECK-NEXT: je .LBB0_29 -; CHECK-NEXT: .LBB0_7: # %a66b -; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1 +; CHECK-NEXT: je .LBB0_32 +; CHECK-NEXT: .LBB0_18: # %a66b +; CHECK-NEXT: # in Loop: Header=BB0_10 Depth=1 ; CHECK-NEXT: testb %r8b, %r8b -; CHECK-NEXT: jne .LBB0_8 +; CHECK-NEXT: jne .LBB0_21 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_33: # %a74b -; CHECK-NEXT: # Parent Loop BB0_3 Depth=1 +; CHECK-NEXT: .LBB0_19: # %a74b +; CHECK-NEXT: # Parent Loop BB0_10 Depth=1 ; CHECK-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-NEXT: testb %r9b, %r9b -; CHECK-NEXT: jne .LBB0_33 -; CHECK-NEXT: # %bb.34: # %b1582 -; CHECK-NEXT: # in Loop: Header=BB0_33 Depth=2 -; CHECK-NEXT: jne .LBB0_33 -; CHECK-NEXT: .LBB0_8: # %a93b -; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1 +; CHECK-NEXT: jne .LBB0_19 +; CHECK-NEXT: # %bb.20: # %b1582 +; CHECK-NEXT: # in Loop: Header=BB0_19 Depth=2 +; CHECK-NEXT: jne .LBB0_19 +; CHECK-NEXT: .LBB0_21: # %a93b +; CHECK-NEXT: # in Loop: Header=BB0_10 Depth=1 ; CHECK-NEXT: testl %eax, %eax ; CHECK-NEXT: js .LBB0_9 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_35: # %a97b -; CHECK-NEXT: # Parent Loop BB0_3 Depth=1 +; CHECK-NEXT: .LBB0_22: # %a97b +; CHECK-NEXT: # Parent Loop BB0_10 Depth=1 ; CHECK-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; CHECK-NEXT: addss %xmm0, %xmm1 @@ -140,109 +140,109 @@ define dso_local void @foo(ptr %a0, ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5) ; CHECK-NEXT: addss %xmm1, %xmm2 ; CHECK-NEXT: movss %xmm2, i6000(%rip) ; CHECK-NEXT: testb %r9b, %r9b -; CHECK-NEXT: jne .LBB0_35 +; CHECK-NEXT: jne .LBB0_22 ; CHECK-NEXT: jmp .LBB0_9 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_21: # %b377 -; CHECK-NEXT: # in Loop: Header=BB0_20 Depth=2 +; CHECK-NEXT: .LBB0_23: # %b377 +; CHECK-NEXT: # in Loop: Header=BB0_24 Depth=2 ; CHECK-NEXT: testb %r9b, %r9b -; CHECK-NEXT: je .LBB0_22 -; CHECK-NEXT: .LBB0_20: # %b341 -; CHECK-NEXT: # Parent Loop BB0_3 Depth=1 +; CHECK-NEXT: je .LBB0_37 +; CHECK-NEXT: .LBB0_24: # %b341 +; CHECK-NEXT: # Parent Loop BB0_10 Depth=1 ; CHECK-NEXT: # => This Loop Header: Depth=2 -; CHECK-NEXT: # Child Loop BB0_37 Depth 3 +; CHECK-NEXT: # Child Loop BB0_25 Depth 3 ; CHECK-NEXT: testq %rsi, %rsi -; CHECK-NEXT: js .LBB0_21 +; CHECK-NEXT: js .LBB0_23 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_37: # %a35b -; CHECK-NEXT: # Parent Loop BB0_3 Depth=1 -; CHECK-NEXT: # Parent Loop BB0_20 Depth=2 +; CHECK-NEXT: .LBB0_25: # %a35b +; CHECK-NEXT: # Parent Loop BB0_10 Depth=1 +; CHECK-NEXT: # Parent Loop BB0_24 Depth=2 ; CHECK-NEXT: # => This Inner Loop Header: Depth=3 ; CHECK-NEXT: testb %r9b, %r9b -; CHECK-NEXT: je .LBB0_37 -; CHECK-NEXT: jmp .LBB0_21 +; CHECK-NEXT: je .LBB0_25 +; CHECK-NEXT: jmp .LBB0_23 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_27: # %b1016 -; CHECK-NEXT: # in Loop: Header=BB0_25 Depth=2 +; CHECK-NEXT: .LBB0_26: # %b1016 +; CHECK-NEXT: # in Loop: Header=BB0_27 Depth=2 ; CHECK-NEXT: testq %rsi, %rsi -; CHECK-NEXT: jle .LBB0_6 -; CHECK-NEXT: .LBB0_25: # %b858 -; CHECK-NEXT: # Parent Loop BB0_3 Depth=1 +; CHECK-NEXT: jle .LBB0_17 +; CHECK-NEXT: .LBB0_27: # %b858 +; CHECK-NEXT: # Parent Loop BB0_10 Depth=1 ; CHECK-NEXT: # => This Loop Header: Depth=2 -; CHECK-NEXT: # Child Loop BB0_38 Depth 3 ; CHECK-NEXT: # Child Loop BB0_28 Depth 3 +; CHECK-NEXT: # Child Loop BB0_30 Depth 3 ; CHECK-NEXT: testq %rdx, %rdx -; CHECK-NEXT: js .LBB0_26 +; CHECK-NEXT: js .LBB0_29 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_38: # %a53b -; CHECK-NEXT: # Parent Loop BB0_3 Depth=1 -; CHECK-NEXT: # Parent Loop BB0_25 Depth=2 +; CHECK-NEXT: .LBB0_28: # %a53b +; CHECK-NEXT: # Parent Loop BB0_10 Depth=1 +; CHECK-NEXT: # Parent Loop BB0_27 Depth=2 ; CHECK-NEXT: # => This Inner Loop Header: Depth=3 ; CHECK-NEXT: testb %r9b, %r9b -; CHECK-NEXT: je .LBB0_38 -; CHECK-NEXT: .LBB0_26: # %b879 -; CHECK-NEXT: # in Loop: Header=BB0_25 Depth=2 +; CHECK-NEXT: je .LBB0_28 +; CHECK-NEXT: .LBB0_29: # %b879 +; CHECK-NEXT: # in Loop: Header=BB0_27 Depth=2 ; CHECK-NEXT: testb %r10b, %r10b -; CHECK-NEXT: jne .LBB0_27 +; CHECK-NEXT: jne .LBB0_26 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_28: # %a53b1019 -; CHECK-NEXT: # Parent Loop BB0_3 Depth=1 -; CHECK-NEXT: # Parent Loop BB0_25 Depth=2 +; CHECK-NEXT: .LBB0_30: # %a53b1019 +; CHECK-NEXT: # Parent Loop BB0_10 Depth=1 +; CHECK-NEXT: # Parent Loop BB0_27 Depth=2 ; CHECK-NEXT: # => This Inner Loop Header: Depth=3 ; CHECK-NEXT: testq %rdx, %rdx -; CHECK-NEXT: jle .LBB0_28 -; CHECK-NEXT: jmp .LBB0_27 +; CHECK-NEXT: jle .LBB0_30 +; CHECK-NEXT: jmp .LBB0_26 ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .LBB0_31: # %b1263 -; CHECK-NEXT: # in Loop: Header=BB0_29 Depth=2 +; CHECK-NEXT: # in Loop: Header=BB0_32 Depth=2 ; CHECK-NEXT: testq %rdx, %rdx -; CHECK-NEXT: jle .LBB0_7 -; CHECK-NEXT: .LBB0_29: # %b1117 -; CHECK-NEXT: # Parent Loop BB0_3 Depth=1 +; CHECK-NEXT: jle .LBB0_18 +; CHECK-NEXT: .LBB0_32: # %b1117 +; CHECK-NEXT: # Parent Loop BB0_10 Depth=1 ; CHECK-NEXT: # => This Loop Header: Depth=2 -; CHECK-NEXT: # Child Loop BB0_39 Depth 3 -; CHECK-NEXT: # Child Loop BB0_32 Depth 3 +; CHECK-NEXT: # Child Loop BB0_33 Depth 3 +; CHECK-NEXT: # Child Loop BB0_35 Depth 3 ; CHECK-NEXT: testq %rsi, %rsi -; CHECK-NEXT: js .LBB0_30 +; CHECK-NEXT: js .LBB0_34 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_39: # %a63b -; CHECK-NEXT: # Parent Loop BB0_3 Depth=1 -; CHECK-NEXT: # Parent Loop BB0_29 Depth=2 +; CHECK-NEXT: .LBB0_33: # %a63b +; CHECK-NEXT: # Parent Loop BB0_10 Depth=1 +; CHECK-NEXT: # Parent Loop BB0_32 Depth=2 ; CHECK-NEXT: # => This Inner Loop Header: Depth=3 ; CHECK-NEXT: testq %rsi, %rsi -; CHECK-NEXT: jle .LBB0_39 -; CHECK-NEXT: .LBB0_30: # %b1139 -; CHECK-NEXT: # in Loop: Header=BB0_29 Depth=2 +; CHECK-NEXT: jle .LBB0_33 +; CHECK-NEXT: .LBB0_34: # %b1139 +; CHECK-NEXT: # in Loop: Header=BB0_32 Depth=2 ; CHECK-NEXT: testq %rsi, %rsi ; CHECK-NEXT: jle .LBB0_31 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_32: # %a63b1266 -; CHECK-NEXT: # Parent Loop BB0_3 Depth=1 -; CHECK-NEXT: # Parent Loop BB0_29 Depth=2 +; CHECK-NEXT: .LBB0_35: # %a63b1266 +; CHECK-NEXT: # Parent Loop BB0_10 Depth=1 +; CHECK-NEXT: # Parent Loop BB0_32 Depth=2 ; CHECK-NEXT: # => This Inner Loop Header: Depth=3 ; CHECK-NEXT: testq %rsi, %rsi -; CHECK-NEXT: jle .LBB0_32 +; CHECK-NEXT: jle .LBB0_35 ; CHECK-NEXT: jmp .LBB0_31 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_24: # %b712 -; CHECK-NEXT: # in Loop: Header=BB0_22 Depth=2 +; CHECK-NEXT: .LBB0_36: # %b712 +; CHECK-NEXT: # in Loop: Header=BB0_37 Depth=2 ; CHECK-NEXT: testb %r9b, %r9b -; CHECK-NEXT: je .LBB0_5 -; CHECK-NEXT: .LBB0_22: # %b535 -; CHECK-NEXT: # Parent Loop BB0_3 Depth=1 +; CHECK-NEXT: je .LBB0_16 +; CHECK-NEXT: .LBB0_37: # %b535 +; CHECK-NEXT: # Parent Loop BB0_10 Depth=1 ; CHECK-NEXT: # => This Loop Header: Depth=2 -; CHECK-NEXT: # Child Loop BB0_23 Depth 3 +; CHECK-NEXT: # Child Loop BB0_38 Depth 3 ; CHECK-NEXT: testq %rdx, %rdx -; CHECK-NEXT: js .LBB0_24 +; CHECK-NEXT: js .LBB0_36 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_23: # %a45b -; CHECK-NEXT: # Parent Loop BB0_3 Depth=1 -; CHECK-NEXT: # Parent Loop BB0_22 Depth=2 +; CHECK-NEXT: .LBB0_38: # %a45b +; CHECK-NEXT: # Parent Loop BB0_10 Depth=1 +; CHECK-NEXT: # Parent Loop BB0_37 Depth=2 ; CHECK-NEXT: # => This Inner Loop Header: Depth=3 ; CHECK-NEXT: testb %r9b, %r9b -; CHECK-NEXT: je .LBB0_23 -; CHECK-NEXT: jmp .LBB0_24 -; CHECK-NEXT: .LBB0_10: # %a109b +; CHECK-NEXT: je .LBB0_38 +; CHECK-NEXT: jmp .LBB0_36 +; CHECK-NEXT: .LBB0_39: # %a109b ; CHECK-NEXT: movq %rbp, %rsp ; CHECK-NEXT: popq %rbp ; CHECK-NEXT: .cfi_def_cfa %rsp, 8 diff --git a/llvm/test/CodeGen/X86/2007-02-16-BranchFold.ll b/llvm/test/CodeGen/X86/2007-02-16-BranchFold.ll index 206574eeae2ae..eacbf462b52c0 100644 --- a/llvm/test/CodeGen/X86/2007-02-16-BranchFold.ll +++ b/llvm/test/CodeGen/X86/2007-02-16-BranchFold.ll @@ -50,34 +50,34 @@ define i16 @main_bb_2E_i9_2E_i_2E_i932_2E_ce(ptr %l_addr.01.0.i2.i.i929, ptr %tm ; CHECK-NEXT: calll _fprintf ; CHECK-NEXT: movl 20(%edi), %eax ; CHECK-NEXT: testl %eax, %eax -; CHECK-NEXT: jle LBB0_6 +; CHECK-NEXT: jle LBB0_4 ; CHECK-NEXT: ## %bb.1: ## %NodeBlock4 ; CHECK-NEXT: cmpl $2, %eax -; CHECK-NEXT: jge LBB0_2 -; CHECK-NEXT: ## %bb.4: ## %LeafBlock2 +; CHECK-NEXT: jge LBB0_7 +; CHECK-NEXT: ## %bb.2: ## %LeafBlock2 ; CHECK-NEXT: cmpl $1, %eax -; CHECK-NEXT: jne LBB0_3 -; CHECK-NEXT: ## %bb.5: ## %bb20.i.i937.exitStub +; CHECK-NEXT: jne LBB0_10 +; CHECK-NEXT: ## %bb.3: ## %bb20.i.i937.exitStub ; CHECK-NEXT: movl %edi, (%esi) ; CHECK-NEXT: movw $3, %ax ; CHECK-NEXT: addl $20, %esp ; CHECK-NEXT: popl %esi ; CHECK-NEXT: popl %edi ; CHECK-NEXT: retl -; CHECK-NEXT: LBB0_6: ## %NodeBlock +; CHECK-NEXT: LBB0_4: ## %NodeBlock ; CHECK-NEXT: js LBB0_9 -; CHECK-NEXT: ## %bb.7: ## %LeafBlock1 -; CHECK-NEXT: jne LBB0_3 -; CHECK-NEXT: ## %bb.8: ## %bb12.i.i935.exitStub +; CHECK-NEXT: ## %bb.5: ## %LeafBlock1 +; CHECK-NEXT: jne LBB0_10 +; CHECK-NEXT: ## %bb.6: ## %bb12.i.i935.exitStub ; CHECK-NEXT: movl %edi, (%esi) ; CHECK-NEXT: movw $2, %ax ; CHECK-NEXT: addl $20, %esp ; CHECK-NEXT: popl %esi ; CHECK-NEXT: popl %edi ; CHECK-NEXT: retl -; CHECK-NEXT: LBB0_2: ## %LeafBlock3 -; CHECK-NEXT: jne LBB0_3 -; CHECK-NEXT: ## %bb.11: ## %bb28.i.i938.exitStub +; CHECK-NEXT: LBB0_7: ## %LeafBlock3 +; CHECK-NEXT: jne LBB0_10 +; CHECK-NEXT: ## %bb.8: ## %bb28.i.i938.exitStub ; CHECK-NEXT: movl %edi, (%esi) ; CHECK-NEXT: movw $4, %ax ; CHECK-NEXT: addl $20, %esp @@ -86,15 +86,15 @@ define i16 @main_bb_2E_i9_2E_i_2E_i932_2E_ce(ptr %l_addr.01.0.i2.i.i929, ptr %tm ; CHECK-NEXT: retl ; CHECK-NEXT: LBB0_9: ## %LeafBlock ; CHECK-NEXT: cmpl $-1, %eax -; CHECK-NEXT: je LBB0_10 -; CHECK-NEXT: LBB0_3: ## %NewDefault +; CHECK-NEXT: je LBB0_11 +; CHECK-NEXT: LBB0_10: ## %NewDefault ; CHECK-NEXT: movl %edi, (%esi) ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: addl $20, %esp ; CHECK-NEXT: popl %esi ; CHECK-NEXT: popl %edi ; CHECK-NEXT: retl -; CHECK-NEXT: LBB0_10: ## %bb.i14.i.exitStub +; CHECK-NEXT: LBB0_11: ## %bb.i14.i.exitStub ; CHECK-NEXT: movl %edi, (%esi) ; CHECK-NEXT: movw $1, %ax ; CHECK-NEXT: addl $20, %esp diff --git a/llvm/test/CodeGen/X86/2007-08-09-IllegalX86-64Asm.ll b/llvm/test/CodeGen/X86/2007-08-09-IllegalX86-64Asm.ll index 7bdc4e19a1cf6..d03f85ec09dca 100644 --- a/llvm/test/CodeGen/X86/2007-08-09-IllegalX86-64Asm.ll +++ b/llvm/test/CodeGen/X86/2007-08-09-IllegalX86-64Asm.ll @@ -87,7 +87,7 @@ define ptr @ubyte_divmod(ptr %a, ptr %b) { ; CHECK-NEXT: LBB0_8: ## %bb17 ; CHECK-NEXT: callq _PyErr_Occurred ; CHECK-NEXT: testq %rax, %rax -; CHECK-NEXT: jne LBB0_27 +; CHECK-NEXT: jne LBB0_26 ; CHECK-NEXT: ## %bb.9: ## %cond_next ; CHECK-NEXT: movq _PyArray_API@GOTPCREL(%rip), %rax ; CHECK-NEXT: movq (%rax), %rax @@ -97,7 +97,7 @@ define ptr @ubyte_divmod(ptr %a, ptr %b) { ; CHECK-NEXT: movq %r14, %rdi ; CHECK-NEXT: movq %rbx, %rsi ; CHECK-NEXT: callq *40(%rax) -; CHECK-NEXT: jmp LBB0_28 +; CHECK-NEXT: jmp LBB0_27 ; CHECK-NEXT: LBB0_11: ## %cond_true.i ; CHECK-NEXT: movl $4, %edi ; CHECK-NEXT: callq _feraiseexcept @@ -113,21 +113,21 @@ define ptr @ubyte_divmod(ptr %a, ptr %b) { ; CHECK-NEXT: movzbl %sil, %eax ; CHECK-NEXT: divb %dl ; CHECK-NEXT: movzbl %ah, %ebx -; CHECK-NEXT: jmp LBB0_18 +; CHECK-NEXT: jmp LBB0_17 ; CHECK-NEXT: LBB0_14: ## %cond_true.i200 ; CHECK-NEXT: testb %dl, %dl -; CHECK-NEXT: jne LBB0_17 -; CHECK-NEXT: ## %bb.16: ## %cond_true14.i +; CHECK-NEXT: jne LBB0_16 +; CHECK-NEXT: ## %bb.15: ## %cond_true14.i ; CHECK-NEXT: movl $4, %edi ; CHECK-NEXT: callq _feraiseexcept -; CHECK-NEXT: LBB0_17: ## %ubyte_ctype_remainder.exit +; CHECK-NEXT: LBB0_16: ## %ubyte_ctype_remainder.exit ; CHECK-NEXT: xorl %ebx, %ebx -; CHECK-NEXT: LBB0_18: ## %ubyte_ctype_remainder.exit +; CHECK-NEXT: LBB0_17: ## %ubyte_ctype_remainder.exit ; CHECK-NEXT: movq (%r14), %rax ; CHECK-NEXT: callq *224(%rax) ; CHECK-NEXT: testl %eax, %eax -; CHECK-NEXT: je LBB0_21 -; CHECK-NEXT: ## %bb.19: ## %cond_true61 +; CHECK-NEXT: je LBB0_20 +; CHECK-NEXT: ## %bb.18: ## %cond_true61 ; CHECK-NEXT: movl %eax, %ebp ; CHECK-NEXT: movq (%r14), %rax ; CHECK-NEXT: movq _.str5@GOTPCREL(%rip), %rdi @@ -136,8 +136,8 @@ define ptr @ubyte_divmod(ptr %a, ptr %b) { ; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rcx ; CHECK-NEXT: callq *200(%rax) ; CHECK-NEXT: testl %eax, %eax -; CHECK-NEXT: js LBB0_27 -; CHECK-NEXT: ## %bb.20: ## %cond_next73 +; CHECK-NEXT: js LBB0_26 +; CHECK-NEXT: ## %bb.19: ## %cond_next73 ; CHECK-NEXT: movl $1, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movq (%r14), %rax ; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rsi @@ -146,13 +146,13 @@ define ptr @ubyte_divmod(ptr %a, ptr %b) { ; CHECK-NEXT: movl %ebp, %edx ; CHECK-NEXT: callq *232(%rax) ; CHECK-NEXT: testl %eax, %eax -; CHECK-NEXT: jne LBB0_27 -; CHECK-NEXT: LBB0_21: ## %cond_next89 +; CHECK-NEXT: jne LBB0_26 +; CHECK-NEXT: LBB0_20: ## %cond_next89 ; CHECK-NEXT: movl $2, %edi ; CHECK-NEXT: callq _PyTuple_New ; CHECK-NEXT: testq %rax, %rax -; CHECK-NEXT: je LBB0_27 -; CHECK-NEXT: ## %bb.22: ## %cond_next97 +; CHECK-NEXT: je LBB0_26 +; CHECK-NEXT: ## %bb.21: ## %cond_next97 ; CHECK-NEXT: movq %rax, %r14 ; CHECK-NEXT: movq _PyArray_API@GOTPCREL(%rip), %r12 ; CHECK-NEXT: movq (%r12), %rax @@ -160,8 +160,8 @@ define ptr @ubyte_divmod(ptr %a, ptr %b) { ; CHECK-NEXT: xorl %esi, %esi ; CHECK-NEXT: callq *304(%rdi) ; CHECK-NEXT: testq %rax, %rax -; CHECK-NEXT: je LBB0_25 -; CHECK-NEXT: ## %bb.23: ## %cond_next135 +; CHECK-NEXT: je LBB0_24 +; CHECK-NEXT: ## %bb.22: ## %cond_next135 ; CHECK-NEXT: movb %r15b, 16(%rax) ; CHECK-NEXT: movq %rax, 24(%r14) ; CHECK-NEXT: movq (%r12), %rax @@ -169,22 +169,22 @@ define ptr @ubyte_divmod(ptr %a, ptr %b) { ; CHECK-NEXT: xorl %esi, %esi ; CHECK-NEXT: callq *304(%rdi) ; CHECK-NEXT: testq %rax, %rax -; CHECK-NEXT: je LBB0_25 -; CHECK-NEXT: ## %bb.24: ## %cond_next182 +; CHECK-NEXT: je LBB0_24 +; CHECK-NEXT: ## %bb.23: ## %cond_next182 ; CHECK-NEXT: movb %bl, 16(%rax) ; CHECK-NEXT: movq %rax, 32(%r14) ; CHECK-NEXT: movq %r14, %rax -; CHECK-NEXT: jmp LBB0_28 -; CHECK-NEXT: LBB0_25: ## %cond_true113 +; CHECK-NEXT: jmp LBB0_27 +; CHECK-NEXT: LBB0_24: ## %cond_true113 ; CHECK-NEXT: decq (%r14) -; CHECK-NEXT: jne LBB0_27 -; CHECK-NEXT: ## %bb.26: ## %cond_true126 +; CHECK-NEXT: jne LBB0_26 +; CHECK-NEXT: ## %bb.25: ## %cond_true126 ; CHECK-NEXT: movq 8(%r14), %rax ; CHECK-NEXT: movq %r14, %rdi ; CHECK-NEXT: callq *48(%rax) -; CHECK-NEXT: LBB0_27: ## %UnifiedReturnBlock +; CHECK-NEXT: LBB0_26: ## %UnifiedReturnBlock ; CHECK-NEXT: xorl %eax, %eax -; CHECK-NEXT: LBB0_28: ## %UnifiedReturnBlock +; CHECK-NEXT: LBB0_27: ## %UnifiedReturnBlock ; CHECK-NEXT: addq $32, %rsp ; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %r12 diff --git a/llvm/test/CodeGen/X86/2007-10-29-ExtendSetCC.ll b/llvm/test/CodeGen/X86/2007-10-29-ExtendSetCC.ll index 212dc0bfb12e9..83502de51cfeb 100644 --- a/llvm/test/CodeGen/X86/2007-10-29-ExtendSetCC.ll +++ b/llvm/test/CodeGen/X86/2007-10-29-ExtendSetCC.ll @@ -29,13 +29,13 @@ define signext i16 @t_freeze(ptr %p) { ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: movswl (%ecx), %eax ; CHECK-NEXT: testl %eax, %eax -; CHECK-NEXT: js .LBB1_1 -; CHECK-NEXT: # %bb.2: # %cond_next +; CHECK-NEXT: js .LBB1_2 +; CHECK-NEXT: # %bb.1: # %cond_next ; CHECK-NEXT: andl $15, %eax ; CHECK-NEXT: movl %eax, (%ecx) ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: retl -; CHECK-NEXT: .LBB1_1: # %cond_true +; CHECK-NEXT: .LBB1_2: # %cond_true ; CHECK-NEXT: # kill: def $ax killed $ax killed $eax ; CHECK-NEXT: retl entry: diff --git a/llvm/test/CodeGen/X86/2007-11-06-InstrSched.ll b/llvm/test/CodeGen/X86/2007-11-06-InstrSched.ll index bbce246a5d394..1e861defed45b 100644 --- a/llvm/test/CodeGen/X86/2007-11-06-InstrSched.ll +++ b/llvm/test/CodeGen/X86/2007-11-06-InstrSched.ll @@ -8,14 +8,14 @@ define float @foo(ptr %x, ptr %y, i32 %c) nounwind { ; CHECK-NEXT: pushl %eax ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: testl %eax, %eax -; CHECK-NEXT: je .LBB0_1 -; CHECK-NEXT: # %bb.2: # %bb18.preheader +; CHECK-NEXT: je .LBB0_3 +; CHECK-NEXT: # %bb.1: # %bb18.preheader ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx ; CHECK-NEXT: xorps %xmm0, %xmm0 ; CHECK-NEXT: xorl %esi, %esi ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_3: # %bb18 +; CHECK-NEXT: .LBB0_2: # %bb18 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: xorps %xmm1, %xmm1 ; CHECK-NEXT: cvtsi2ssl (%edx,%esi,4), %xmm1 @@ -23,9 +23,9 @@ define float @foo(ptr %x, ptr %y, i32 %c) nounwind { ; CHECK-NEXT: addss %xmm1, %xmm0 ; CHECK-NEXT: incl %esi ; CHECK-NEXT: cmpl %eax, %esi -; CHECK-NEXT: jb .LBB0_3 +; CHECK-NEXT: jb .LBB0_2 ; CHECK-NEXT: jmp .LBB0_4 -; CHECK-NEXT: .LBB0_1: +; CHECK-NEXT: .LBB0_3: ; CHECK-NEXT: xorps %xmm0, %xmm0 ; CHECK-NEXT: .LBB0_4: # %bb23 ; CHECK-NEXT: movss %xmm0, (%esp) diff --git a/llvm/test/CodeGen/X86/2007-11-30-LoadFolding-Bug.ll b/llvm/test/CodeGen/X86/2007-11-30-LoadFolding-Bug.ll index 6541693776099..43957adac1ca1 100644 --- a/llvm/test/CodeGen/X86/2007-11-30-LoadFolding-Bug.ll +++ b/llvm/test/CodeGen/X86/2007-11-30-LoadFolding-Bug.ll @@ -25,10 +25,10 @@ define fastcc void @mp_sqrt(i32 %n, i32 %radix, ptr %in, ptr %out, ptr %tmp1, pt ; CHECK-NEXT: testb $1, %cl ; CHECK-NEXT: jne .LBB0_1 ; CHECK-NEXT: # %bb.2: # %mp_unexp_mp2d.exit.i -; CHECK-NEXT: je .LBB0_3 -; CHECK-NEXT: # %bb.5: # %cond_next.i -; CHECK-NEXT: jne .LBB0_3 -; CHECK-NEXT: # %bb.6: # %cond_next36.i +; CHECK-NEXT: je .LBB0_8 +; CHECK-NEXT: # %bb.3: # %cond_next.i +; CHECK-NEXT: jne .LBB0_8 +; CHECK-NEXT: # %bb.4: # %cond_next36.i ; CHECK-NEXT: movl $0, 0 ; CHECK-NEXT: movzbl %cl, %ebp ; CHECK-NEXT: andl $1, %ebp @@ -37,7 +37,7 @@ define fastcc void @mp_sqrt(i32 %n, i32 %radix, ptr %in, ptr %out, ptr %tmp1, pt ; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: xorpd %xmm1, %xmm1 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_7: # %bb.i28.i +; CHECK-NEXT: .LBB0_5: # %bb.i28.i ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: cvttsd2si %xmm1, %edi ; CHECK-NEXT: cmpl %edx, %edi @@ -49,11 +49,11 @@ define fastcc void @mp_sqrt(i32 %n, i32 %radix, ptr %in, ptr %out, ptr %tmp1, pt ; CHECK-NEXT: subsd %xmm2, %xmm1 ; CHECK-NEXT: mulsd %xmm0, %xmm1 ; CHECK-NEXT: addl $-2, %ebp -; CHECK-NEXT: jne .LBB0_7 -; CHECK-NEXT: # %bb.8: # %mp_unexp_d2mp.exit29.i +; CHECK-NEXT: jne .LBB0_5 +; CHECK-NEXT: # %bb.6: # %mp_unexp_d2mp.exit29.i ; CHECK-NEXT: movl $0, 0 -; CHECK-NEXT: je .LBB0_9 -; CHECK-NEXT: # %bb.10: # %mp_sqrt_init.exit +; CHECK-NEXT: je .LBB0_10 +; CHECK-NEXT: # %bb.7: # %mp_sqrt_init.exit ; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: movl %edx, %edi ; CHECK-NEXT: movl %esi, %edx @@ -76,18 +76,18 @@ define fastcc void @mp_sqrt(i32 %n, i32 %radix, ptr %in, ptr %out, ptr %tmp1, pt ; CHECK-NEXT: addl $12, %esp ; CHECK-NEXT: testl %ebp, %ebp ; CHECK-NEXT: je .LBB0_11 -; CHECK-NEXT: .LBB0_3: # %cond_true.i +; CHECK-NEXT: .LBB0_8: # %cond_true.i ; CHECK-NEXT: addl $4, %esp -; CHECK-NEXT: .LBB0_4: # %cond_true.i +; CHECK-NEXT: .LBB0_9: # %cond_true.i ; CHECK-NEXT: popl %esi ; CHECK-NEXT: popl %edi ; CHECK-NEXT: popl %ebx ; CHECK-NEXT: popl %ebp ; CHECK-NEXT: retl ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_9: # %bb.i.i +; CHECK-NEXT: .LBB0_10: # %bb.i.i ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: jmp .LBB0_9 +; CHECK-NEXT: jmp .LBB0_10 ; CHECK-NEXT: .LBB0_11: # %cond_false.i ; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: movl (%esp), %esi # 4-byte Reload @@ -124,7 +124,7 @@ define fastcc void @mp_sqrt(i32 %n, i32 %radix, ptr %in, ptr %out, ptr %tmp1, pt ; CHECK-NEXT: pushl %ebx ; CHECK-NEXT: calll mp_mul_d2i@PLT ; CHECK-NEXT: addl $16, %esp -; CHECK-NEXT: jmp .LBB0_4 +; CHECK-NEXT: jmp .LBB0_9 entry: br label %bb.i5 diff --git a/llvm/test/CodeGen/X86/2008-04-09-BranchFolding.ll b/llvm/test/CodeGen/X86/2008-04-09-BranchFolding.ll index 45b5ce562d805..643c2a746491c 100644 --- a/llvm/test/CodeGen/X86/2008-04-09-BranchFolding.ll +++ b/llvm/test/CodeGen/X86/2008-04-09-BranchFolding.ll @@ -13,11 +13,11 @@ define fastcc ptr @pushdecl(ptr %x) nounwind { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB0_1 -; CHECK-NEXT: # %bb.2: # %bb17.i +; CHECK-NEXT: jne .LBB0_2 +; CHECK-NEXT: # %bb.1: # %bb17.i ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: retl -; CHECK-NEXT: .LBB0_1: # %bb160 +; CHECK-NEXT: .LBB0_2: # %bb160 ; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: retl diff --git a/llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll b/llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll index b32afdc2214e0..0a8393a46b82c 100644 --- a/llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll +++ b/llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll @@ -17,15 +17,15 @@ define i16 @SQLDriversW(ptr %henv, i16 zeroext %fDir, ptr %szDrvDesc, i16 signe ; CHECK-NEXT: subl $12, %esp ; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: je LBB0_1 -; CHECK-NEXT: ## %bb.3: ## %bb28 +; CHECK-NEXT: je LBB0_7 +; CHECK-NEXT: ## %bb.1: ## %bb28 ; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %ebx ; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %ebp ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edi ; CHECK-NEXT: movw $-2, %si -; CHECK-NEXT: jne LBB0_6 -; CHECK-NEXT: ## %bb.4: ## %bb37 +; CHECK-NEXT: jne LBB0_4 +; CHECK-NEXT: ## %bb.2: ## %bb37 ; CHECK-NEXT: movw $0, 40(%edi) ; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: leal (,%ecx,4), %ecx @@ -48,22 +48,22 @@ define i16 @SQLDriversW(ptr %henv, i16 zeroext %fDir, ptr %szDrvDesc, i16 signe ; CHECK-NEXT: movl %eax, %esi ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: je LBB0_1 -; CHECK-NEXT: ## %bb.5: +; CHECK-NEXT: je LBB0_7 +; CHECK-NEXT: ## %bb.3: ; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %ecx -; CHECK-NEXT: LBB0_6: ## %done +; CHECK-NEXT: LBB0_4: ## %done ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: je LBB0_7 -; CHECK-NEXT: ## %bb.8: ## %bb167 +; CHECK-NEXT: je LBB0_6 +; CHECK-NEXT: ## %bb.5: ## %bb167 ; CHECK-NEXT: subl $12, %esp ; CHECK-NEXT: movl L_iodbcdm_global_lock$non_lazy_ptr, %eax ; CHECK-NEXT: pushl %eax ; CHECK-NEXT: calll _pthread_mutex_unlock ; CHECK-NEXT: addl $16, %esp ; CHECK-NEXT: movl %esi, %eax -; CHECK-NEXT: jmp LBB0_2 -; CHECK-NEXT: LBB0_7: ## %bb150 +; CHECK-NEXT: jmp LBB0_8 +; CHECK-NEXT: LBB0_6: ## %bb150 ; CHECK-NEXT: movswl %si, %eax ; CHECK-NEXT: subl $8, %esp ; CHECK-NEXT: movswl %cx, %ecx @@ -81,9 +81,9 @@ define i16 @SQLDriversW(ptr %henv, i16 zeroext %fDir, ptr %szDrvDesc, i16 signe ; CHECK-NEXT: pushl $1 ; CHECK-NEXT: calll _trace_SQLDriversW ; CHECK-NEXT: addl $48, %esp -; CHECK-NEXT: LBB0_1: ## %bb +; CHECK-NEXT: LBB0_7: ## %bb ; CHECK-NEXT: xorl %eax, %eax -; CHECK-NEXT: LBB0_2: ## %bb +; CHECK-NEXT: LBB0_8: ## %bb ; CHECK-NEXT: addl $12, %esp ; CHECK-NEXT: popl %esi ; CHECK-NEXT: popl %edi diff --git a/llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll b/llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll index 3913e93b83a66..d774415ddc502 100644 --- a/llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll +++ b/llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll @@ -34,74 +34,74 @@ define void @_ZNK10wxDateTime6FormatEPKwRKNS_8TimeZoneE(ptr noalias sret(%struct ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi ; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %ebx ; CHECK-NEXT: testb $1, %bl -; CHECK-NEXT: je LBB0_25 +; CHECK-NEXT: je LBB0_22 ; CHECK-NEXT: ## %bb.1: ## %bb116.i -; CHECK-NEXT: je LBB0_25 +; CHECK-NEXT: je LBB0_22 ; CHECK-NEXT: ## %bb.2: ## %bb52.i.i -; CHECK-NEXT: je LBB0_25 +; CHECK-NEXT: je LBB0_22 ; CHECK-NEXT: ## %bb.3: ## %bb142.i -; CHECK-NEXT: je LBB0_25 +; CHECK-NEXT: je LBB0_22 ; CHECK-NEXT: ## %bb.4: ; CHECK-NEXT: movl L_.str89$non_lazy_ptr, %edi ; CHECK-NEXT: movb $1, %bh ; CHECK-NEXT: movl L_.str$non_lazy_ptr, %ebp -; CHECK-NEXT: jmp LBB0_5 -; CHECK-NEXT: LBB0_21: ## %bb7806 -; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1 +; CHECK-NEXT: jmp LBB0_6 +; CHECK-NEXT: LBB0_5: ## %bb7806 +; CHECK-NEXT: ## in Loop: Header=BB0_6 Depth=1 ; CHECK-NEXT: Ltmp16: ## EH_LABEL ; CHECK-NEXT: movl $0, {{[0-9]+}}(%esp) ; CHECK-NEXT: movl $1, {{[0-9]+}}(%esp) ; CHECK-NEXT: movl $0, (%esp) ; CHECK-NEXT: calll __ZN12wxStringBase6appendEmw ; CHECK-NEXT: Ltmp17: ## EH_LABEL -; CHECK-NEXT: LBB0_5: ## %bb3261 +; CHECK-NEXT: LBB0_6: ## %bb3261 ; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: cmpl $37, 0 -; CHECK-NEXT: jne LBB0_25 -; CHECK-NEXT: ## %bb.6: ## %bb3306 -; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1 +; CHECK-NEXT: jne LBB0_22 +; CHECK-NEXT: ## %bb.7: ## %bb3306 +; CHECK-NEXT: ## in Loop: Header=BB0_6 Depth=1 ; CHECK-NEXT: Ltmp0: ## EH_LABEL ; CHECK-NEXT: movl %edi, {{[0-9]+}}(%esp) ; CHECK-NEXT: movl $0, (%esp) ; CHECK-NEXT: calll __ZN12wxStringBaseaSEPKw ; CHECK-NEXT: Ltmp1: ## EH_LABEL -; CHECK-NEXT: ## %bb.7: ## %bb3314 -; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1 +; CHECK-NEXT: ## %bb.8: ## %bb3314 +; CHECK-NEXT: ## in Loop: Header=BB0_6 Depth=1 ; CHECK-NEXT: movl 0, %eax ; CHECK-NEXT: cmpl $121, %eax -; CHECK-NEXT: ja LBB0_25 -; CHECK-NEXT: ## %bb.8: ## %bb3314 -; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1 +; CHECK-NEXT: ja LBB0_22 +; CHECK-NEXT: ## %bb.9: ## %bb3314 +; CHECK-NEXT: ## in Loop: Header=BB0_6 Depth=1 ; CHECK-NEXT: jmpl *LJTI0_0(,%eax,4) ; CHECK-NEXT: LBB0_10: ## %bb5809 -; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1 +; CHECK-NEXT: ## in Loop: Header=BB0_6 Depth=1 ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne LBB0_25 +; CHECK-NEXT: jne LBB0_22 ; CHECK-NEXT: ## %bb.11: ## %bb5809 -; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1 +; CHECK-NEXT: ## in Loop: Header=BB0_6 Depth=1 ; CHECK-NEXT: testb %bh, %bh -; CHECK-NEXT: je LBB0_25 +; CHECK-NEXT: je LBB0_22 ; CHECK-NEXT: ## %bb.12: ## %bb91.i8504 -; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1 +; CHECK-NEXT: ## in Loop: Header=BB0_6 Depth=1 ; CHECK-NEXT: testb $1, %bl ; CHECK-NEXT: je LBB0_14 ; CHECK-NEXT: ## %bb.13: ## %bb155.i8541 -; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1 +; CHECK-NEXT: ## in Loop: Header=BB0_6 Depth=1 ; CHECK-NEXT: Ltmp4: ## EH_LABEL ; CHECK-NEXT: movl $0, {{[0-9]+}}(%esp) ; CHECK-NEXT: movl $0, (%esp) ; CHECK-NEXT: calll _gmtime_r ; CHECK-NEXT: Ltmp5: ## EH_LABEL ; CHECK-NEXT: LBB0_14: ## %bb182.i8560 -; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1 +; CHECK-NEXT: ## in Loop: Header=BB0_6 Depth=1 ; CHECK-NEXT: testb $1, %bl -; CHECK-NEXT: je LBB0_15 -; CHECK-NEXT: ## %bb.16: ## %bb278.i8617 -; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1 +; CHECK-NEXT: je LBB0_17 +; CHECK-NEXT: ## %bb.15: ## %bb278.i8617 +; CHECK-NEXT: ## in Loop: Header=BB0_6 Depth=1 ; CHECK-NEXT: je LBB0_18 -; CHECK-NEXT: ## %bb.17: ## %bb440.i8663 -; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1 +; CHECK-NEXT: ## %bb.16: ## %bb440.i8663 +; CHECK-NEXT: ## in Loop: Header=BB0_6 Depth=1 ; CHECK-NEXT: Ltmp6: ## EH_LABEL ; CHECK-NEXT: movl L_.str4$non_lazy_ptr, %eax ; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp) @@ -114,11 +114,11 @@ define void @_ZNK10wxDateTime6FormatEPKwRKNS_8TimeZoneE(ptr noalias sret(%struct ; CHECK-NEXT: calll __Z10wxOnAssertPKwiPKcS0_S0_ ; CHECK-NEXT: Ltmp7: ## EH_LABEL ; CHECK-NEXT: jmp LBB0_18 -; CHECK-NEXT: LBB0_15: ## %bb187.i8591 -; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1 -; CHECK-NEXT: jne LBB0_25 +; CHECK-NEXT: LBB0_17: ## %bb187.i8591 +; CHECK-NEXT: ## in Loop: Header=BB0_6 Depth=1 +; CHECK-NEXT: jne LBB0_22 ; CHECK-NEXT: LBB0_18: ## %invcont5814 -; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1 +; CHECK-NEXT: ## in Loop: Header=BB0_6 Depth=1 ; CHECK-NEXT: Ltmp8: ## EH_LABEL ; CHECK-NEXT: movl $0, {{[0-9]+}}(%esp) ; CHECK-NEXT: movl $0, {{[0-9]+}}(%esp) @@ -127,7 +127,7 @@ define void @_ZNK10wxDateTime6FormatEPKwRKNS_8TimeZoneE(ptr noalias sret(%struct ; CHECK-NEXT: subl $4, %esp ; CHECK-NEXT: Ltmp9: ## EH_LABEL ; CHECK-NEXT: ## %bb.19: ## %invcont5831 -; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1 +; CHECK-NEXT: ## in Loop: Header=BB0_6 Depth=1 ; CHECK-NEXT: Ltmp10: ## EH_LABEL ; CHECK-NEXT: movl $0, {{[0-9]+}}(%esp) ; CHECK-NEXT: movl $0, {{[0-9]+}}(%esp) @@ -135,8 +135,8 @@ define void @_ZNK10wxDateTime6FormatEPKwRKNS_8TimeZoneE(ptr noalias sret(%struct ; CHECK-NEXT: movl $0, (%esp) ; CHECK-NEXT: calll __ZN12wxStringBase10ConcatSelfEmPKwm ; CHECK-NEXT: Ltmp11: ## EH_LABEL -; CHECK-NEXT: jmp LBB0_5 -; CHECK-NEXT: LBB0_9: ## %bb5657 +; CHECK-NEXT: jmp LBB0_6 +; CHECK-NEXT: LBB0_20: ## %bb5657 ; CHECK-NEXT: Ltmp13: ## EH_LABEL ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp) @@ -144,8 +144,8 @@ define void @_ZNK10wxDateTime6FormatEPKwRKNS_8TimeZoneE(ptr noalias sret(%struct ; CHECK-NEXT: movl %eax, (%esp) ; CHECK-NEXT: calll __ZNK10wxDateTime12GetDayOfYearERKNS_8TimeZoneE ; CHECK-NEXT: Ltmp14: ## EH_LABEL -; CHECK-NEXT: jmp LBB0_25 -; CHECK-NEXT: LBB0_20: ## %bb5968 +; CHECK-NEXT: jmp LBB0_22 +; CHECK-NEXT: LBB0_21: ## %bb5968 ; CHECK-NEXT: Ltmp2: ## EH_LABEL ; CHECK-NEXT: movl $0, {{[0-9]+}}(%esp) ; CHECK-NEXT: movl $0, {{[0-9]+}}(%esp) @@ -153,7 +153,7 @@ define void @_ZNK10wxDateTime6FormatEPKwRKNS_8TimeZoneE(ptr noalias sret(%struct ; CHECK-NEXT: calll __ZN8wxString6FormatEPKwz ; CHECK-NEXT: subl $4, %esp ; CHECK-NEXT: Ltmp3: ## EH_LABEL -; CHECK-NEXT: LBB0_25: ## %bb115.critedge.i +; CHECK-NEXT: LBB0_22: ## %bb115.critedge.i ; CHECK-NEXT: movl %esi, %eax ; CHECK-NEXT: addl $28, %esp ; CHECK-NEXT: popl %esi @@ -163,13 +163,13 @@ define void @_ZNK10wxDateTime6FormatEPKwRKNS_8TimeZoneE(ptr noalias sret(%struct ; CHECK-NEXT: retl $4 ; CHECK-NEXT: LBB0_23: ## %lpad.loopexit.split-lp ; CHECK-NEXT: Ltmp15: ## EH_LABEL -; CHECK-NEXT: jmp LBB0_25 +; CHECK-NEXT: jmp LBB0_22 ; CHECK-NEXT: LBB0_24: ## %lpad8185 ; CHECK-NEXT: Ltmp12: ## EH_LABEL -; CHECK-NEXT: jmp LBB0_25 -; CHECK-NEXT: LBB0_22: ## %lpad.loopexit +; CHECK-NEXT: jmp LBB0_22 +; CHECK-NEXT: LBB0_25: ## %lpad.loopexit ; CHECK-NEXT: Ltmp18: ## EH_LABEL -; CHECK-NEXT: jmp LBB0_25 +; CHECK-NEXT: jmp LBB0_22 ; CHECK-NEXT: Lfunc_end0: entry: br i1 %foo, label %bb116.i, label %bb115.critedge.i diff --git a/llvm/test/CodeGen/X86/2008-04-28-CoalescerBug.ll b/llvm/test/CodeGen/X86/2008-04-28-CoalescerBug.ll index c95fc00b3ee6d..5181cf504f105 100644 --- a/llvm/test/CodeGen/X86/2008-04-28-CoalescerBug.ll +++ b/llvm/test/CodeGen/X86/2008-04-28-CoalescerBug.ll @@ -26,13 +26,13 @@ define void @t(ptr %depth, ptr %bop, i32 %mode) nounwind { ; CHECK-NEXT: LBB0_4: ## %bb13088 ; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne LBB0_5 -; CHECK-NEXT: ## %bb.6: ## %bb13101 +; CHECK-NEXT: jne LBB0_6 +; CHECK-NEXT: ## %bb.5: ## %bb13101 ; CHECK-NEXT: ## in Loop: Header=BB0_4 Depth=1 ; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: jmp LBB0_7 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: LBB0_5: ## in Loop: Header=BB0_4 Depth=1 +; CHECK-NEXT: LBB0_6: ## in Loop: Header=BB0_4 Depth=1 ; CHECK-NEXT: movl $65535, %ecx ## imm = 0xFFFF ; CHECK-NEXT: LBB0_7: ## %bb13107 ; CHECK-NEXT: ## in Loop: Header=BB0_4 Depth=1 diff --git a/llvm/test/CodeGen/X86/2008-05-01-InvalidOrdCompare.ll b/llvm/test/CodeGen/X86/2008-05-01-InvalidOrdCompare.ll index ff7a99ada7e50..5c137c07eaacd 100644 --- a/llvm/test/CodeGen/X86/2008-05-01-InvalidOrdCompare.ll +++ b/llvm/test/CodeGen/X86/2008-05-01-InvalidOrdCompare.ll @@ -12,11 +12,11 @@ define i32 @test(double %p) nounwind { ; CHECK-NEXT: fnstsw %ax ; CHECK-NEXT: # kill: def $ah killed $ah killed $ax ; CHECK-NEXT: sahf -; CHECK-NEXT: jp .LBB0_1 -; CHECK-NEXT: # %bb.2: # %UnifiedReturnBlock +; CHECK-NEXT: jp .LBB0_2 +; CHECK-NEXT: # %bb.1: # %UnifiedReturnBlock ; CHECK-NEXT: movl $42, %eax ; CHECK-NEXT: retl -; CHECK-NEXT: .LBB0_1: # %bb +; CHECK-NEXT: .LBB0_2: # %bb ; CHECK-NEXT: calll test2@PLT ; CHECK-NEXT: movl $17, %eax ; CHECK-NEXT: retl diff --git a/llvm/test/CodeGen/X86/2009-08-12-badswitch.ll b/llvm/test/CodeGen/X86/2009-08-12-badswitch.ll index 527684f5a27db..2c033701e222e 100644 --- a/llvm/test/CodeGen/X86/2009-08-12-badswitch.ll +++ b/llvm/test/CodeGen/X86/2009-08-12-badswitch.ll @@ -36,88 +36,88 @@ define internal fastcc i32 @foo(i64 %bar) nounwind ssp { ; CHECK-NEXT: pushq %rax ; CHECK-NEXT: addq $-2, %rdi ; CHECK-NEXT: cmpq $25, %rdi -; CHECK-NEXT: ja LBB0_2 +; CHECK-NEXT: ja LBB0_27 ; CHECK-NEXT: ## %bb.1: ## %bb49 ; CHECK-NEXT: leaq LJTI0_0(%rip), %rax ; CHECK-NEXT: movslq (%rax,%rdi,4), %rcx ; CHECK-NEXT: addq %rax, %rcx ; CHECK-NEXT: jmpq *%rcx -; CHECK-NEXT: LBB0_3: ## %RRETURN_6 +; CHECK-NEXT: LBB0_2: ## %RRETURN_6 ; CHECK-NEXT: callq _f2 ; CHECK-NEXT: jmp LBB0_28 -; CHECK-NEXT: LBB0_18: ## %RRETURN_29 +; CHECK-NEXT: LBB0_3: ## %RRETURN_29 ; CHECK-NEXT: callq _f17 ; CHECK-NEXT: jmp LBB0_28 -; CHECK-NEXT: LBB0_16: ## %RRETURN_27 +; CHECK-NEXT: LBB0_4: ## %RRETURN_27 ; CHECK-NEXT: callq _f15 ; CHECK-NEXT: jmp LBB0_28 -; CHECK-NEXT: LBB0_13: ## %RRETURN_22 +; CHECK-NEXT: LBB0_5: ## %RRETURN_22 ; CHECK-NEXT: callq _f12 ; CHECK-NEXT: jmp LBB0_28 ; CHECK-NEXT: LBB0_6: ## %RRETURN_15 ; CHECK-NEXT: callq _f5 ; CHECK-NEXT: jmp LBB0_28 -; CHECK-NEXT: LBB0_14: ## %RRETURN_24 +; CHECK-NEXT: LBB0_7: ## %RRETURN_24 ; CHECK-NEXT: callq _f13 ; CHECK-NEXT: jmp LBB0_28 -; CHECK-NEXT: LBB0_11: ## %RRETURN_20 +; CHECK-NEXT: LBB0_8: ## %RRETURN_20 ; CHECK-NEXT: callq _f10 ; CHECK-NEXT: jmp LBB0_28 -; CHECK-NEXT: LBB0_27: ## %RRETURN_1 +; CHECK-NEXT: LBB0_9: ## %RRETURN_1 ; CHECK-NEXT: callq _f26 ; CHECK-NEXT: jmp LBB0_28 -; CHECK-NEXT: LBB0_26: ## %RRETURN_52 +; CHECK-NEXT: LBB0_10: ## %RRETURN_52 ; CHECK-NEXT: callq _f25 ; CHECK-NEXT: jmp LBB0_28 -; CHECK-NEXT: LBB0_4: ## %RRETURN_7 +; CHECK-NEXT: LBB0_11: ## %RRETURN_7 ; CHECK-NEXT: callq _f3 ; CHECK-NEXT: jmp LBB0_28 -; CHECK-NEXT: LBB0_17: ## %RRETURN_28 +; CHECK-NEXT: LBB0_12: ## %RRETURN_28 ; CHECK-NEXT: callq _f16 ; CHECK-NEXT: jmp LBB0_28 -; CHECK-NEXT: LBB0_5: ## %RRETURN_14 +; CHECK-NEXT: LBB0_13: ## %RRETURN_14 ; CHECK-NEXT: callq _f4 ; CHECK-NEXT: jmp LBB0_28 -; CHECK-NEXT: LBB0_9: ## %RRETURN_18 +; CHECK-NEXT: LBB0_14: ## %RRETURN_18 ; CHECK-NEXT: callq _f8 ; CHECK-NEXT: jmp LBB0_28 -; CHECK-NEXT: LBB0_19: ## %RRETURN_30 +; CHECK-NEXT: LBB0_15: ## %RRETURN_30 ; CHECK-NEXT: callq _f18 ; CHECK-NEXT: jmp LBB0_28 -; CHECK-NEXT: LBB0_22: ## %RRETURN_40 +; CHECK-NEXT: LBB0_16: ## %RRETURN_40 ; CHECK-NEXT: callq _f21 ; CHECK-NEXT: jmp LBB0_28 -; CHECK-NEXT: LBB0_7: ## %RRETURN_16 +; CHECK-NEXT: LBB0_17: ## %RRETURN_16 ; CHECK-NEXT: callq _f6 ; CHECK-NEXT: jmp LBB0_28 -; CHECK-NEXT: LBB0_23: ## %RRETURN_42 +; CHECK-NEXT: LBB0_18: ## %RRETURN_42 ; CHECK-NEXT: callq _f22 ; CHECK-NEXT: jmp LBB0_28 -; CHECK-NEXT: LBB0_15: ## %RRETURN_26 +; CHECK-NEXT: LBB0_19: ## %RRETURN_26 ; CHECK-NEXT: callq _f14 ; CHECK-NEXT: jmp LBB0_28 -; CHECK-NEXT: LBB0_8: ## %RRETURN_17 +; CHECK-NEXT: LBB0_20: ## %RRETURN_17 ; CHECK-NEXT: callq _f7 ; CHECK-NEXT: jmp LBB0_28 -; CHECK-NEXT: LBB0_20: ## %RRETURN_31 +; CHECK-NEXT: LBB0_21: ## %RRETURN_31 ; CHECK-NEXT: callq _f19 ; CHECK-NEXT: jmp LBB0_28 -; CHECK-NEXT: LBB0_12: ## %RRETURN_21 +; CHECK-NEXT: LBB0_22: ## %RRETURN_21 ; CHECK-NEXT: callq _f11 ; CHECK-NEXT: jmp LBB0_28 -; CHECK-NEXT: LBB0_10: ## %RRETURN_19 +; CHECK-NEXT: LBB0_23: ## %RRETURN_19 ; CHECK-NEXT: callq _f9 ; CHECK-NEXT: jmp LBB0_28 ; CHECK-NEXT: LBB0_24: ## %RRETURN_44 ; CHECK-NEXT: callq _f23 ; CHECK-NEXT: jmp LBB0_28 -; CHECK-NEXT: LBB0_21: ## %RRETURN_38 +; CHECK-NEXT: LBB0_25: ## %RRETURN_38 ; CHECK-NEXT: callq _f20 ; CHECK-NEXT: jmp LBB0_28 -; CHECK-NEXT: LBB0_25: ## %RRETURN_48 +; CHECK-NEXT: LBB0_26: ## %RRETURN_48 ; CHECK-NEXT: callq _f24 ; CHECK-NEXT: jmp LBB0_28 -; CHECK-NEXT: LBB0_2: ## %RETURN +; CHECK-NEXT: LBB0_27: ## %RETURN ; CHECK-NEXT: callq _f1 ; CHECK-NEXT: LBB0_28: ## %EXIT ; CHECK-NEXT: xorl %eax, %eax @@ -125,58 +125,58 @@ define internal fastcc i32 @foo(i64 %bar) nounwind ssp { ; CHECK-NEXT: retq ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: .data_region jt32 -; CHECK-NEXT: L0_0_set_3 = LBB0_3-LJTI0_0 -; CHECK-NEXT: L0_0_set_4 = LBB0_4-LJTI0_0 -; CHECK-NEXT: L0_0_set_5 = LBB0_5-LJTI0_0 -; CHECK-NEXT: L0_0_set_6 = LBB0_6-LJTI0_0 -; CHECK-NEXT: L0_0_set_7 = LBB0_7-LJTI0_0 -; CHECK-NEXT: L0_0_set_8 = LBB0_8-LJTI0_0 -; CHECK-NEXT: L0_0_set_9 = LBB0_9-LJTI0_0 -; CHECK-NEXT: L0_0_set_10 = LBB0_10-LJTI0_0 +; CHECK-NEXT: L0_0_set_2 = LBB0_2-LJTI0_0 ; CHECK-NEXT: L0_0_set_11 = LBB0_11-LJTI0_0 -; CHECK-NEXT: L0_0_set_12 = LBB0_12-LJTI0_0 ; CHECK-NEXT: L0_0_set_13 = LBB0_13-LJTI0_0 +; CHECK-NEXT: L0_0_set_6 = LBB0_6-LJTI0_0 +; CHECK-NEXT: L0_0_set_17 = LBB0_17-LJTI0_0 +; CHECK-NEXT: L0_0_set_20 = LBB0_20-LJTI0_0 ; CHECK-NEXT: L0_0_set_14 = LBB0_14-LJTI0_0 +; CHECK-NEXT: L0_0_set_23 = LBB0_23-LJTI0_0 +; CHECK-NEXT: L0_0_set_8 = LBB0_8-LJTI0_0 +; CHECK-NEXT: L0_0_set_22 = LBB0_22-LJTI0_0 +; CHECK-NEXT: L0_0_set_5 = LBB0_5-LJTI0_0 +; CHECK-NEXT: L0_0_set_7 = LBB0_7-LJTI0_0 +; CHECK-NEXT: L0_0_set_19 = LBB0_19-LJTI0_0 +; CHECK-NEXT: L0_0_set_4 = LBB0_4-LJTI0_0 +; CHECK-NEXT: L0_0_set_12 = LBB0_12-LJTI0_0 +; CHECK-NEXT: L0_0_set_3 = LBB0_3-LJTI0_0 ; CHECK-NEXT: L0_0_set_15 = LBB0_15-LJTI0_0 +; CHECK-NEXT: L0_0_set_21 = LBB0_21-LJTI0_0 +; CHECK-NEXT: L0_0_set_25 = LBB0_25-LJTI0_0 ; CHECK-NEXT: L0_0_set_16 = LBB0_16-LJTI0_0 -; CHECK-NEXT: L0_0_set_17 = LBB0_17-LJTI0_0 ; CHECK-NEXT: L0_0_set_18 = LBB0_18-LJTI0_0 -; CHECK-NEXT: L0_0_set_19 = LBB0_19-LJTI0_0 -; CHECK-NEXT: L0_0_set_20 = LBB0_20-LJTI0_0 -; CHECK-NEXT: L0_0_set_21 = LBB0_21-LJTI0_0 -; CHECK-NEXT: L0_0_set_22 = LBB0_22-LJTI0_0 -; CHECK-NEXT: L0_0_set_23 = LBB0_23-LJTI0_0 ; CHECK-NEXT: L0_0_set_24 = LBB0_24-LJTI0_0 -; CHECK-NEXT: L0_0_set_25 = LBB0_25-LJTI0_0 ; CHECK-NEXT: L0_0_set_26 = LBB0_26-LJTI0_0 -; CHECK-NEXT: L0_0_set_27 = LBB0_27-LJTI0_0 +; CHECK-NEXT: L0_0_set_10 = LBB0_10-LJTI0_0 +; CHECK-NEXT: L0_0_set_9 = LBB0_9-LJTI0_0 ; CHECK-NEXT: LJTI0_0: -; CHECK-NEXT: .long L0_0_set_3 -; CHECK-NEXT: .long L0_0_set_3 -; CHECK-NEXT: .long L0_0_set_4 -; CHECK-NEXT: .long L0_0_set_5 -; CHECK-NEXT: .long L0_0_set_6 -; CHECK-NEXT: .long L0_0_set_7 -; CHECK-NEXT: .long L0_0_set_8 -; CHECK-NEXT: .long L0_0_set_9 -; CHECK-NEXT: .long L0_0_set_10 +; CHECK-NEXT: .long L0_0_set_2 +; CHECK-NEXT: .long L0_0_set_2 ; CHECK-NEXT: .long L0_0_set_11 -; CHECK-NEXT: .long L0_0_set_12 ; CHECK-NEXT: .long L0_0_set_13 +; CHECK-NEXT: .long L0_0_set_6 +; CHECK-NEXT: .long L0_0_set_17 +; CHECK-NEXT: .long L0_0_set_20 ; CHECK-NEXT: .long L0_0_set_14 +; CHECK-NEXT: .long L0_0_set_23 +; CHECK-NEXT: .long L0_0_set_8 +; CHECK-NEXT: .long L0_0_set_22 +; CHECK-NEXT: .long L0_0_set_5 +; CHECK-NEXT: .long L0_0_set_7 +; CHECK-NEXT: .long L0_0_set_19 +; CHECK-NEXT: .long L0_0_set_4 +; CHECK-NEXT: .long L0_0_set_12 +; CHECK-NEXT: .long L0_0_set_3 ; CHECK-NEXT: .long L0_0_set_15 +; CHECK-NEXT: .long L0_0_set_21 +; CHECK-NEXT: .long L0_0_set_25 ; CHECK-NEXT: .long L0_0_set_16 -; CHECK-NEXT: .long L0_0_set_17 ; CHECK-NEXT: .long L0_0_set_18 -; CHECK-NEXT: .long L0_0_set_19 -; CHECK-NEXT: .long L0_0_set_20 -; CHECK-NEXT: .long L0_0_set_21 -; CHECK-NEXT: .long L0_0_set_22 -; CHECK-NEXT: .long L0_0_set_23 ; CHECK-NEXT: .long L0_0_set_24 -; CHECK-NEXT: .long L0_0_set_25 ; CHECK-NEXT: .long L0_0_set_26 -; CHECK-NEXT: .long L0_0_set_27 +; CHECK-NEXT: .long L0_0_set_10 +; CHECK-NEXT: .long L0_0_set_9 ; CHECK-NEXT: .end_data_region entry: br label %bb49 diff --git a/llvm/test/CodeGen/X86/2010-08-04-MaskedSignedCompare.ll b/llvm/test/CodeGen/X86/2010-08-04-MaskedSignedCompare.ll index 0e57e9d135a4d..f2da950f1ffcc 100644 --- a/llvm/test/CodeGen/X86/2010-08-04-MaskedSignedCompare.ll +++ b/llvm/test/CodeGen/X86/2010-08-04-MaskedSignedCompare.ll @@ -13,12 +13,12 @@ define dso_local i32 @main() nounwind { ; CHECK-NEXT: cmpq g_16(%rip), %rax ; CHECK-NEXT: sbbl %eax, %eax ; CHECK-NEXT: testb $-106, %al -; CHECK-NEXT: jle .LBB0_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jle .LBB0_2 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: movl $1, g_38(%rip) ; CHECK-NEXT: movl $1, %esi ; CHECK-NEXT: jmp .LBB0_3 -; CHECK-NEXT: .LBB0_1: # %entry.if.end_crit_edge +; CHECK-NEXT: .LBB0_2: # %entry.if.end_crit_edge ; CHECK-NEXT: movl g_38(%rip), %esi ; CHECK-NEXT: .LBB0_3: # %if.end ; CHECK-NEXT: pushq %rax diff --git a/llvm/test/CodeGen/X86/2011-12-26-extractelement-duplicate-load.ll b/llvm/test/CodeGen/X86/2011-12-26-extractelement-duplicate-load.ll index 075b9631f5272..7929d0dff7d1d 100644 --- a/llvm/test/CodeGen/X86/2011-12-26-extractelement-duplicate-load.ll +++ b/llvm/test/CodeGen/X86/2011-12-26-extractelement-duplicate-load.ll @@ -11,11 +11,11 @@ define <4 x i32> @test(ptr %p) { ; CHECK-LABEL: test: ; CHECK: # %bb.0: ; CHECK-NEXT: cmpl $3, 8(%rdi) -; CHECK-NEXT: je .LBB0_1 -; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: je .LBB0_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: xorps %xmm0, %xmm0 ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB0_1: +; CHECK-NEXT: .LBB0_2: ; CHECK-NEXT: movaps (%rdi), %xmm0 ; CHECK-NEXT: retq %v = load <4 x i32>, ptr %p diff --git a/llvm/test/CodeGen/X86/2012-01-10-UndefExceptionEdge.ll b/llvm/test/CodeGen/X86/2012-01-10-UndefExceptionEdge.ll index f2b4c49b1dbcd..d2053dc462c5d 100644 --- a/llvm/test/CodeGen/X86/2012-01-10-UndefExceptionEdge.ll +++ b/llvm/test/CodeGen/X86/2012-01-10-UndefExceptionEdge.ll @@ -44,20 +44,20 @@ define void @f(ptr nocapture %arg, ptr nocapture %arg1, ptr nocapture %arg2, ptr ; CHECK-NEXT: movl %eax, %esi ; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne LBB0_2 -; CHECK-NEXT: ## %bb.7: ## %bb31 +; CHECK-NEXT: jne LBB0_17 +; CHECK-NEXT: ## %bb.2: ## %bb31 ; CHECK-NEXT: ## implicit-def: $eax ; CHECK-NEXT: ## kill: killed $eax -; CHECK-NEXT: LBB0_8: ## %bb38 +; CHECK-NEXT: LBB0_3: ## %bb38 ; CHECK-NEXT: ## =>This Loop Header: Depth=1 -; CHECK-NEXT: ## Child Loop BB0_13 Depth 2 -; CHECK-NEXT: ## Child Loop BB0_16 Depth 3 -; CHECK-NEXT: ## Child Loop BB0_21 Depth 2 +; CHECK-NEXT: ## Child Loop BB0_7 Depth 2 +; CHECK-NEXT: ## Child Loop BB0_10 Depth 3 +; CHECK-NEXT: ## Child Loop BB0_14 Depth 2 ; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne LBB0_9 -; CHECK-NEXT: ## %bb.10: ## %bb41 -; CHECK-NEXT: ## in Loop: Header=BB0_8 Depth=1 +; CHECK-NEXT: jne LBB0_20 +; CHECK-NEXT: ## %bb.4: ## %bb41 +; CHECK-NEXT: ## in Loop: Header=BB0_3 Depth=1 ; CHECK-NEXT: Ltmp2: ## EH_LABEL ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp) @@ -65,84 +65,84 @@ define void @f(ptr nocapture %arg, ptr nocapture %arg1, ptr nocapture %arg2, ptr ; CHECK-NEXT: movl %esi, (%esp) ; CHECK-NEXT: calll _Pjii ; CHECK-NEXT: Ltmp3: ## EH_LABEL -; CHECK-NEXT: ## %bb.11: ## %bb42 -; CHECK-NEXT: ## in Loop: Header=BB0_8 Depth=1 +; CHECK-NEXT: ## %bb.5: ## %bb42 +; CHECK-NEXT: ## in Loop: Header=BB0_3 Depth=1 ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: decl %eax ; CHECK-NEXT: testl %eax, %eax -; CHECK-NEXT: jne LBB0_18 -; CHECK-NEXT: ## %bb.12: ## %bb45.preheader -; CHECK-NEXT: ## in Loop: Header=BB0_8 Depth=1 +; CHECK-NEXT: jne LBB0_16 +; CHECK-NEXT: ## %bb.6: ## %bb45.preheader +; CHECK-NEXT: ## in Loop: Header=BB0_3 Depth=1 ; CHECK-NEXT: movl $255, %eax -; CHECK-NEXT: LBB0_13: ## %bb45 -; CHECK-NEXT: ## Parent Loop BB0_8 Depth=1 +; CHECK-NEXT: LBB0_7: ## %bb45 +; CHECK-NEXT: ## Parent Loop BB0_3 Depth=1 ; CHECK-NEXT: ## => This Loop Header: Depth=2 -; CHECK-NEXT: ## Child Loop BB0_16 Depth 3 +; CHECK-NEXT: ## Child Loop BB0_10 Depth 3 ; CHECK-NEXT: movb $1, %cl ; CHECK-NEXT: testb %cl, %cl -; CHECK-NEXT: jne LBB0_19 -; CHECK-NEXT: ## %bb.14: ## %bb48 -; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=2 -; CHECK-NEXT: jne LBB0_17 -; CHECK-NEXT: ## %bb.15: ## %bb49.preheader -; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=2 +; CHECK-NEXT: jne LBB0_12 +; CHECK-NEXT: ## %bb.8: ## %bb48 +; CHECK-NEXT: ## in Loop: Header=BB0_7 Depth=2 +; CHECK-NEXT: jne LBB0_11 +; CHECK-NEXT: ## %bb.9: ## %bb49.preheader +; CHECK-NEXT: ## in Loop: Header=BB0_7 Depth=2 ; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: movl %esi, %edx ; CHECK-NEXT: movl %edi, %ebx -; CHECK-NEXT: LBB0_16: ## %bb49 -; CHECK-NEXT: ## Parent Loop BB0_8 Depth=1 -; CHECK-NEXT: ## Parent Loop BB0_13 Depth=2 +; CHECK-NEXT: LBB0_10: ## %bb49 +; CHECK-NEXT: ## Parent Loop BB0_3 Depth=1 +; CHECK-NEXT: ## Parent Loop BB0_7 Depth=2 ; CHECK-NEXT: ## => This Inner Loop Header: Depth=3 ; CHECK-NEXT: incl %ecx ; CHECK-NEXT: addl $4, %edx ; CHECK-NEXT: decl %ebx -; CHECK-NEXT: jne LBB0_16 -; CHECK-NEXT: LBB0_17: ## %bb57 -; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=2 +; CHECK-NEXT: jne LBB0_10 +; CHECK-NEXT: LBB0_11: ## %bb57 +; CHECK-NEXT: ## in Loop: Header=BB0_7 Depth=2 ; CHECK-NEXT: decl %eax -; CHECK-NEXT: jmp LBB0_13 -; CHECK-NEXT: LBB0_19: ## %bb59 -; CHECK-NEXT: ## in Loop: Header=BB0_8 Depth=1 +; CHECK-NEXT: jmp LBB0_7 +; CHECK-NEXT: LBB0_12: ## %bb59 +; CHECK-NEXT: ## in Loop: Header=BB0_3 Depth=1 ; CHECK-NEXT: movl $-4, %eax ; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp) ; CHECK-NEXT: movl $0, (%esp) ; CHECK-NEXT: calll ___bzero ; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne LBB0_22 -; CHECK-NEXT: ## %bb.20: ## %bb61.preheader -; CHECK-NEXT: ## in Loop: Header=BB0_8 Depth=1 +; CHECK-NEXT: jne LBB0_15 +; CHECK-NEXT: ## %bb.13: ## %bb61.preheader +; CHECK-NEXT: ## in Loop: Header=BB0_3 Depth=1 ; CHECK-NEXT: movl %esi, %eax ; CHECK-NEXT: movl %edi, %ecx -; CHECK-NEXT: LBB0_21: ## %bb61 -; CHECK-NEXT: ## Parent Loop BB0_8 Depth=1 +; CHECK-NEXT: LBB0_14: ## %bb61 +; CHECK-NEXT: ## Parent Loop BB0_3 Depth=1 ; CHECK-NEXT: ## => This Inner Loop Header: Depth=2 ; CHECK-NEXT: movl $0, (%eax) ; CHECK-NEXT: addl $4, %eax ; CHECK-NEXT: decl %ecx -; CHECK-NEXT: jne LBB0_21 -; CHECK-NEXT: LBB0_22: ## %bb67 -; CHECK-NEXT: ## in Loop: Header=BB0_8 Depth=1 +; CHECK-NEXT: jne LBB0_14 +; CHECK-NEXT: LBB0_15: ## %bb67 +; CHECK-NEXT: ## in Loop: Header=BB0_3 Depth=1 ; CHECK-NEXT: decl {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Folded Spill -; CHECK-NEXT: jmp LBB0_8 -; CHECK-NEXT: LBB0_18: ## %bb43 +; CHECK-NEXT: jmp LBB0_3 +; CHECK-NEXT: LBB0_16: ## %bb43 ; CHECK-NEXT: Ltmp5: ## EH_LABEL ; CHECK-NEXT: movl %esi, %ebx ; CHECK-NEXT: calll _OnOverFlow ; CHECK-NEXT: Ltmp6: ## EH_LABEL -; CHECK-NEXT: jmp LBB0_3 -; CHECK-NEXT: LBB0_2: ## %bb29 +; CHECK-NEXT: jmp LBB0_18 +; CHECK-NEXT: LBB0_17: ## %bb29 ; CHECK-NEXT: Ltmp7: ## EH_LABEL ; CHECK-NEXT: movl %esi, %ebx ; CHECK-NEXT: calll _OnOverFlow ; CHECK-NEXT: Ltmp8: ## EH_LABEL -; CHECK-NEXT: LBB0_3: ## %bb30 +; CHECK-NEXT: LBB0_18: ## %bb30 ; CHECK-NEXT: ud2 -; CHECK-NEXT: LBB0_4: ## %bb20.loopexit +; CHECK-NEXT: LBB0_19: ## %bb20.loopexit ; CHECK-NEXT: Ltmp4: ## EH_LABEL -; CHECK-NEXT: LBB0_9: +; CHECK-NEXT: LBB0_20: ; CHECK-NEXT: movl %esi, %ebx -; CHECK-NEXT: LBB0_6: ## %bb23 +; CHECK-NEXT: LBB0_21: ## %bb23 ; CHECK-NEXT: testl %ebx, %ebx ; CHECK-NEXT: addl $28, %esp ; CHECK-NEXT: popl %esi @@ -150,9 +150,9 @@ define void @f(ptr nocapture %arg, ptr nocapture %arg1, ptr nocapture %arg2, ptr ; CHECK-NEXT: popl %ebx ; CHECK-NEXT: popl %ebp ; CHECK-NEXT: retl -; CHECK-NEXT: LBB0_5: ## %bb20.loopexit.split-lp +; CHECK-NEXT: LBB0_22: ## %bb20.loopexit.split-lp ; CHECK-NEXT: Ltmp9: ## EH_LABEL -; CHECK-NEXT: jmp LBB0_6 +; CHECK-NEXT: jmp LBB0_21 ; CHECK-NEXT: Lfunc_end0: bb: br i1 undef, label %bb6, label %bb7 diff --git a/llvm/test/CodeGen/X86/AMX/amx-across-func.ll b/llvm/test/CodeGen/X86/AMX/amx-across-func.ll index 2bda8db040296..692b1c0129028 100644 --- a/llvm/test/CodeGen/X86/AMX/amx-across-func.ll +++ b/llvm/test/CodeGen/X86/AMX/amx-across-func.ll @@ -228,7 +228,7 @@ define dso_local i32 @test_loop(i32 %0) nounwind { ; CHECK-NEXT: callq foo ; CHECK-NEXT: ldtilecfg (%rsp) ; CHECK-NEXT: testl %ebx, %ebx -; CHECK-NEXT: jg .LBB2_4 +; CHECK-NEXT: jg .LBB2_6 ; CHECK-NEXT: # %bb.1: # %.preheader ; CHECK-NEXT: movl $7, %ebp ; CHECK-NEXT: movl $buf, %r14d @@ -252,14 +252,14 @@ define dso_local i32 @test_loop(i32 %0) nounwind { ; CHECK-NEXT: jne .LBB2_2 ; CHECK-NEXT: # %bb.3: ; CHECK-NEXT: cmpl $3, %ebx -; CHECK-NEXT: jne .LBB2_4 -; CHECK-NEXT: # %bb.6: +; CHECK-NEXT: jne .LBB2_6 +; CHECK-NEXT: # %bb.4: ; CHECK-NEXT: testl %ebp, %ebp -; CHECK-NEXT: jne .LBB2_5 -; CHECK-NEXT: # %bb.7: +; CHECK-NEXT: jne .LBB2_7 +; CHECK-NEXT: # %bb.5: ; CHECK-NEXT: incl %ebx ; CHECK-NEXT: jmp .LBB2_8 -; CHECK-NEXT: .LBB2_4: +; CHECK-NEXT: .LBB2_6: ; CHECK-NEXT: callq foo ; CHECK-NEXT: ldtilecfg (%rsp) ; CHECK-NEXT: movl $32, %eax @@ -267,7 +267,7 @@ define dso_local i32 @test_loop(i32 %0) nounwind { ; CHECK-NEXT: movw $8, %dx ; CHECK-NEXT: tileloadd (%rcx,%rax), %tmm0 ; CHECK-NEXT: tilestored %tmm0, (%rcx,%rax) -; CHECK-NEXT: .LBB2_5: +; CHECK-NEXT: .LBB2_7: ; CHECK-NEXT: decl %ebx ; CHECK-NEXT: .LBB2_8: ; CHECK-NEXT: movl %ebx, %eax @@ -293,7 +293,7 @@ define dso_local i32 @test_loop(i32 %0) nounwind { ; IPRA-NEXT: ldtilecfg {{[0-9]+}}(%rsp) ; IPRA-NEXT: callq foo ; IPRA-NEXT: testl %edi, %edi -; IPRA-NEXT: jg .LBB2_4 +; IPRA-NEXT: jg .LBB2_6 ; IPRA-NEXT: # %bb.1: # %.preheader ; IPRA-NEXT: movl $7, %ecx ; IPRA-NEXT: movl $buf, %edx @@ -311,21 +311,21 @@ define dso_local i32 @test_loop(i32 %0) nounwind { ; IPRA-NEXT: jne .LBB2_2 ; IPRA-NEXT: # %bb.3: ; IPRA-NEXT: cmpl $3, %eax -; IPRA-NEXT: jne .LBB2_4 -; IPRA-NEXT: # %bb.6: +; IPRA-NEXT: jne .LBB2_6 +; IPRA-NEXT: # %bb.4: ; IPRA-NEXT: testl %ecx, %ecx -; IPRA-NEXT: jne .LBB2_5 -; IPRA-NEXT: # %bb.7: +; IPRA-NEXT: jne .LBB2_7 +; IPRA-NEXT: # %bb.5: ; IPRA-NEXT: incl %eax ; IPRA-NEXT: jmp .LBB2_8 -; IPRA-NEXT: .LBB2_4: +; IPRA-NEXT: .LBB2_6: ; IPRA-NEXT: callq foo ; IPRA-NEXT: movl $32, %ecx ; IPRA-NEXT: movl $buf+1024, %edx ; IPRA-NEXT: movw $8, %si ; IPRA-NEXT: tileloadd (%rdx,%rcx), %tmm0 ; IPRA-NEXT: tilestored %tmm0, (%rdx,%rcx) -; IPRA-NEXT: .LBB2_5: +; IPRA-NEXT: .LBB2_7: ; IPRA-NEXT: decl %eax ; IPRA-NEXT: .LBB2_8: ; IPRA-NEXT: addq $72, %rsp diff --git a/llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll b/llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll index 8a8e7a3b4df2c..85bc2596c84ef 100644 --- a/llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll +++ b/llvm/test/CodeGen/X86/AMX/amx-ldtilecfg-insert.ll @@ -64,7 +64,7 @@ define dso_local void @test2(i16 signext %0, i16 signext %1) nounwind { ; CHECK-NEXT: ldtilecfg {{[0-9]+}}(%rsp) ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB1_3 +; CHECK-NEXT: jne .LBB1_2 ; CHECK-NEXT: # %bb.1: # %if.true ; CHECK-NEXT: movw $8, %ax ; CHECK-NEXT: tilezero %tmm0 @@ -75,8 +75,8 @@ define dso_local void @test2(i16 signext %0, i16 signext %1) nounwind { ; CHECK-NEXT: tileloadd (%rdx,%rcx), %tmm2 ; CHECK-NEXT: tdpbssd %tmm2, %tmm1, %tmm0 ; CHECK-NEXT: tilestored %tmm0, (%rdx,%rcx) -; CHECK-NEXT: jmp .LBB1_2 -; CHECK-NEXT: .LBB1_3: # %if.false +; CHECK-NEXT: jmp .LBB1_3 +; CHECK-NEXT: .LBB1_2: # %if.false ; CHECK-NEXT: movl $buf, %eax ; CHECK-NEXT: movl $32, %ecx ; CHECK-NEXT: movw $8, %dx @@ -87,7 +87,7 @@ define dso_local void @test2(i16 signext %0, i16 signext %1) nounwind { ; CHECK-NEXT: tileloadd (%rax,%rcx), %tmm2 ; CHECK-NEXT: tdpbssd %tmm2, %tmm4, %tmm3 ; CHECK-NEXT: tilestored %tmm3, (%rax,%rcx) -; CHECK-NEXT: .LBB1_2: # %if.true +; CHECK-NEXT: .LBB1_3: # %if.true ; CHECK-NEXT: addq $72, %rsp ; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %rbp @@ -240,26 +240,26 @@ define dso_local void @test5(i16 signext %0, i16 signext %1) nounwind { ; CHECK-NEXT: movl $32, %edx ; CHECK-NEXT: movl %esi, %r8d ; CHECK-NEXT: decl %r8d -; CHECK-NEXT: jmp .LBB4_1 +; CHECK-NEXT: jmp .LBB4_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB4_3: # %if.false -; CHECK-NEXT: # in Loop: Header=BB4_1 Depth=1 +; CHECK-NEXT: .LBB4_1: # %if.false +; CHECK-NEXT: # in Loop: Header=BB4_2 Depth=1 ; CHECK-NEXT: movl %r8d, %esi ; CHECK-NEXT: movw %r8w, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: cmpw $7, %si -; CHECK-NEXT: jne .LBB4_5 -; CHECK-NEXT: .LBB4_1: # %loop.bb1 +; CHECK-NEXT: jne .LBB4_4 +; CHECK-NEXT: .LBB4_2: # %loop.bb1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ldtilecfg -{{[0-9]+}}(%rsp) ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB4_3 -; CHECK-NEXT: # %bb.2: # %if.true -; CHECK-NEXT: # in Loop: Header=BB4_1 Depth=1 +; CHECK-NEXT: jne .LBB4_1 +; CHECK-NEXT: # %bb.3: # %if.true +; CHECK-NEXT: # in Loop: Header=BB4_2 Depth=1 ; CHECK-NEXT: tilezero %tmm0 ; CHECK-NEXT: tilestored %tmm0, (%rcx,%rdx) ; CHECK-NEXT: cmpw $7, %si -; CHECK-NEXT: je .LBB4_1 -; CHECK-NEXT: .LBB4_5: # %exit +; CHECK-NEXT: je .LBB4_2 +; CHECK-NEXT: .LBB4_4: # %exit ; CHECK-NEXT: tilerelease ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq @@ -300,13 +300,13 @@ define dso_local void @test6(i16 signext %0) nounwind { ; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: movl $buf, %edx ; CHECK-NEXT: movl $32, %esi -; CHECK-NEXT: jmp .LBB5_1 +; CHECK-NEXT: jmp .LBB5_3 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB5_3: # %if.false -; CHECK-NEXT: # in Loop: Header=BB5_1 Depth=1 +; CHECK-NEXT: .LBB5_1: # %if.false +; CHECK-NEXT: # in Loop: Header=BB5_3 Depth=1 ; CHECK-NEXT: decl %eax -; CHECK-NEXT: .LBB5_4: # %loop.bb2 -; CHECK-NEXT: # in Loop: Header=BB5_1 Depth=1 +; CHECK-NEXT: .LBB5_2: # %loop.bb2 +; CHECK-NEXT: # in Loop: Header=BB5_3 Depth=1 ; CHECK-NEXT: leal (%rdi,%rax), %r8d ; CHECK-NEXT: movw %r8w, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: cmpw $7, %ax @@ -314,14 +314,14 @@ define dso_local void @test6(i16 signext %0) nounwind { ; CHECK-NEXT: tilezero %tmm0 ; CHECK-NEXT: tilestored %tmm0, (%rdx,%rsi) ; CHECK-NEXT: jne .LBB5_5 -; CHECK-NEXT: .LBB5_1: # %loop.bb1 +; CHECK-NEXT: .LBB5_3: # %loop.bb1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: testb %cl, %cl -; CHECK-NEXT: jne .LBB5_3 -; CHECK-NEXT: # %bb.2: # %if.true -; CHECK-NEXT: # in Loop: Header=BB5_1 Depth=1 +; CHECK-NEXT: jne .LBB5_1 +; CHECK-NEXT: # %bb.4: # %if.true +; CHECK-NEXT: # in Loop: Header=BB5_3 Depth=1 ; CHECK-NEXT: incl %eax -; CHECK-NEXT: jmp .LBB5_4 +; CHECK-NEXT: jmp .LBB5_2 ; CHECK-NEXT: .LBB5_5: # %exit ; CHECK-NEXT: tilerelease ; CHECK-NEXT: vzeroupper diff --git a/llvm/test/CodeGen/X86/AMX/amx-tile-basic.ll b/llvm/test/CodeGen/X86/AMX/amx-tile-basic.ll index 9cf7aab0b3655..0c9b9b9e10d9d 100644 --- a/llvm/test/CodeGen/X86/AMX/amx-tile-basic.ll +++ b/llvm/test/CodeGen/X86/AMX/amx-tile-basic.ll @@ -76,39 +76,39 @@ define void @PR90954(ptr %0, ptr %1, i32 %2) nounwind { ; CHECK-NEXT: movb $1, %r8b ; CHECK-NEXT: xorl %r9d, %r9d ; CHECK-NEXT: xorl %r10d, %r10d -; CHECK-NEXT: jmp .LBB1_1 +; CHECK-NEXT: jmp .LBB1_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB1_5: # in Loop: Header=BB1_1 Depth=1 +; CHECK-NEXT: .LBB1_1: # in Loop: Header=BB1_2 Depth=1 ; CHECK-NEXT: incq %r10 ; CHECK-NEXT: addl %edx, %r9d -; CHECK-NEXT: .LBB1_1: # =>This Loop Header: Depth=1 -; CHECK-NEXT: # Child Loop BB1_2 Depth 2 +; CHECK-NEXT: .LBB1_2: # =>This Loop Header: Depth=1 +; CHECK-NEXT: # Child Loop BB1_4 Depth 2 ; CHECK-NEXT: movslq %r9d, %r11 ; CHECK-NEXT: leaq (%rsi,%r11,4), %r11 ; CHECK-NEXT: xorl %ebx, %ebx ; CHECK-NEXT: xorl %r14d, %r14d -; CHECK-NEXT: jmp .LBB1_2 +; CHECK-NEXT: jmp .LBB1_4 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB1_4: # in Loop: Header=BB1_2 Depth=2 +; CHECK-NEXT: .LBB1_3: # in Loop: Header=BB1_4 Depth=2 ; CHECK-NEXT: tilestored %tmm1, (%r11,%rax) ; CHECK-NEXT: incq %r14 ; CHECK-NEXT: addq $64, %r11 ; CHECK-NEXT: decq %rbx -; CHECK-NEXT: je .LBB1_5 -; CHECK-NEXT: .LBB1_2: # Parent Loop BB1_1 Depth=1 +; CHECK-NEXT: je .LBB1_1 +; CHECK-NEXT: .LBB1_4: # Parent Loop BB1_2 Depth=1 ; CHECK-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-NEXT: tilezero %tmm0 ; CHECK-NEXT: tilezero %tmm1 ; CHECK-NEXT: testb %r8b, %r8b -; CHECK-NEXT: jne .LBB1_4 -; CHECK-NEXT: # %bb.3: # in Loop: Header=BB1_2 Depth=2 +; CHECK-NEXT: jne .LBB1_3 +; CHECK-NEXT: # %bb.5: # in Loop: Header=BB1_4 Depth=2 ; CHECK-NEXT: tilezero %tmm1 ; CHECK-NEXT: tilezero %tmm2 ; CHECK-NEXT: tdpbf16ps %tmm2, %tmm1, %tmm0 ; CHECK-NEXT: movabsq $64, %rbp ; CHECK-NEXT: tilestored %tmm0, 896(%rsp,%rbp) # 1024-byte Folded Spill ; CHECK-NEXT: tileloadd 896(%rsp,%rbp), %tmm1 # 1024-byte Folded Reload -; CHECK-NEXT: jmp .LBB1_4 +; CHECK-NEXT: jmp .LBB1_3 %4 = shl i32 %2, 4 %5 = icmp eq i64 0, 0 br label %6 diff --git a/llvm/test/CodeGen/X86/MachineSink-Issue98477.ll b/llvm/test/CodeGen/X86/MachineSink-Issue98477.ll index 4abb1f8e1ca42..4871d1c472548 100644 --- a/llvm/test/CodeGen/X86/MachineSink-Issue98477.ll +++ b/llvm/test/CodeGen/X86/MachineSink-Issue98477.ll @@ -9,39 +9,39 @@ define i32 @main(i1 %tobool.not, i32 %0) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movl $1, %r8d ; CHECK-NEXT: testb $1, %dil -; CHECK-NEXT: jne .LBB0_8 +; CHECK-NEXT: jne .LBB0_7 ; CHECK-NEXT: .LBB0_1: # %j.preheader ; CHECK-NEXT: xorl %r9d, %r9d -; CHECK-NEXT: jmp .LBB0_2 +; CHECK-NEXT: jmp .LBB0_3 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_5: # %if.then4 -; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 +; CHECK-NEXT: .LBB0_2: # %if.then4 +; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1 ; CHECK-NEXT: movl $1, %eax ; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: divl %r8d ; CHECK-NEXT: testb $1, %dil ; CHECK-NEXT: jne .LBB0_6 -; CHECK-NEXT: .LBB0_2: # %j +; CHECK-NEXT: .LBB0_3: # %j ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: movl $1, %eax ; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: idivl %esi ; CHECK-NEXT: movl %edx, %ecx ; CHECK-NEXT: testb %r9b, %r9b -; CHECK-NEXT: jne .LBB0_5 -; CHECK-NEXT: # %bb.3: # %j -; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 +; CHECK-NEXT: jne .LBB0_2 +; CHECK-NEXT: # %bb.4: # %j +; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1 ; CHECK-NEXT: testl %r9d, %r9d -; CHECK-NEXT: js .LBB0_5 -; CHECK-NEXT: # %bb.4: +; CHECK-NEXT: js .LBB0_2 +; CHECK-NEXT: # %bb.5: ; CHECK-NEXT: movl %r9d, %edx ; CHECK-NEXT: .LBB0_6: # %if.end9 ; CHECK-NEXT: testl %edx, %edx -; CHECK-NEXT: jne .LBB0_7 -; CHECK-NEXT: .LBB0_8: # %if.end13 +; CHECK-NEXT: jne .LBB0_8 +; CHECK-NEXT: .LBB0_7: # %if.end13 ; CHECK-NEXT: xorl %r8d, %r8d ; CHECK-NEXT: jmp .LBB0_1 -; CHECK-NEXT: .LBB0_7: # %while.body.lr.ph +; CHECK-NEXT: .LBB0_8: # %while.body.lr.ph ; CHECK-NEXT: movl %ecx, %eax ; CHECK-NEXT: retq entry: diff --git a/llvm/test/CodeGen/X86/MachineSink-eflags.ll b/llvm/test/CodeGen/X86/MachineSink-eflags.ll index a6f38fbdc4b67..01d0ea72d2200 100644 --- a/llvm/test/CodeGen/X86/MachineSink-eflags.ll +++ b/llvm/test/CodeGen/X86/MachineSink-eflags.ll @@ -25,11 +25,11 @@ define void @foo(ptr nocapture %_stubArgs) nounwind { ; CHECK-NEXT: addq %rsi, %rcx ; CHECK-NEXT: shlq $4, %rcx ; CHECK-NEXT: cmpl $0, (%rdi) -; CHECK-NEXT: jne .LBB0_1 -; CHECK-NEXT: # %bb.2: # %entry +; CHECK-NEXT: jne .LBB0_2 +; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: xorps %xmm0, %xmm0 ; CHECK-NEXT: jmp .LBB0_3 -; CHECK-NEXT: .LBB0_1: +; CHECK-NEXT: .LBB0_2: ; CHECK-NEXT: movaps (%rax,%rdx), %xmm0 ; CHECK-NEXT: .LBB0_3: # %entry ; CHECK-NEXT: leaq -{{[0-9]+}}(%rsp), %rsp diff --git a/llvm/test/CodeGen/X86/PR40322.ll b/llvm/test/CodeGen/X86/PR40322.ll index 49709cb9b88f8..4c8a80d512483 100644 --- a/llvm/test/CodeGen/X86/PR40322.ll +++ b/llvm/test/CodeGen/X86/PR40322.ll @@ -72,16 +72,16 @@ define void @_Z2ami(i32) #0 personality ptr @__gxx_personality_v0 { ; CHECK-MINGW-X86-NEXT: addl $12, %esp ; CHECK-MINGW-X86-NEXT: .cfi_adjust_cfa_offset -12 ; CHECK-MINGW-X86-NEXT: Ltmp4: -; CHECK-MINGW-X86-NEXT: # %bb.8: # %unreachable -; CHECK-MINGW-X86-NEXT: LBB0_5: # %lpad +; CHECK-MINGW-X86-NEXT: # %bb.5: # %unreachable +; CHECK-MINGW-X86-NEXT: LBB0_6: # %lpad ; CHECK-MINGW-X86-NEXT: Ltmp2: ; CHECK-MINGW-X86-NEXT: movl %eax, %edi ; CHECK-MINGW-X86-NEXT: .cfi_escape 0x2e, 0x04 ; CHECK-MINGW-X86-NEXT: pushl $__ZGVZ2amiE2au ; CHECK-MINGW-X86-NEXT: .cfi_adjust_cfa_offset 4 ; CHECK-MINGW-X86-NEXT: calll ___cxa_guard_abort -; CHECK-MINGW-X86-NEXT: jmp LBB0_7 -; CHECK-MINGW-X86-NEXT: LBB0_6: # %lpad1 +; CHECK-MINGW-X86-NEXT: jmp LBB0_8 +; CHECK-MINGW-X86-NEXT: LBB0_7: # %lpad1 ; CHECK-MINGW-X86-NEXT: .cfi_def_cfa_offset 12 ; CHECK-MINGW-X86-NEXT: Ltmp5: ; CHECK-MINGW-X86-NEXT: movl %eax, %edi @@ -89,7 +89,7 @@ define void @_Z2ami(i32) #0 personality ptr @__gxx_personality_v0 { ; CHECK-MINGW-X86-NEXT: pushl %esi ; CHECK-MINGW-X86-NEXT: .cfi_adjust_cfa_offset 4 ; CHECK-MINGW-X86-NEXT: calll __ZdlPv -; CHECK-MINGW-X86-NEXT: LBB0_7: # %eh.resume +; CHECK-MINGW-X86-NEXT: LBB0_8: # %eh.resume ; CHECK-MINGW-X86-NEXT: addl $4, %esp ; CHECK-MINGW-X86-NEXT: .cfi_adjust_cfa_offset -4 ; CHECK-MINGW-X86-NEXT: .cfi_escape 0x2e, 0x04 diff --git a/llvm/test/CodeGen/X86/PR71178-register-coalescer-crash.ll b/llvm/test/CodeGen/X86/PR71178-register-coalescer-crash.ll index 12d66f64cb73d..38a9f03b41078 100644 --- a/llvm/test/CodeGen/X86/PR71178-register-coalescer-crash.ll +++ b/llvm/test/CodeGen/X86/PR71178-register-coalescer-crash.ll @@ -7,45 +7,45 @@ define i32 @h(i1 %arg, i32 %arg1) { ; CHECK-NEXT: movl $1, %eax ; CHECK-NEXT: movabsq $9166129423, %rcx # imm = 0x22258090F ; CHECK-NEXT: xorl %edx, %edx -; CHECK-NEXT: jmp .LBB0_1 +; CHECK-NEXT: jmp .LBB0_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_9: # %bb18 -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: .LBB0_1: # %bb18 +; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb $1, %dil -; CHECK-NEXT: jne .LBB0_10 -; CHECK-NEXT: .LBB0_1: # %bb4 +; CHECK-NEXT: jne .LBB0_9 +; CHECK-NEXT: .LBB0_2: # %bb4 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: testq %rdx, %rdx -; CHECK-NEXT: jne .LBB0_2 -; CHECK-NEXT: # %bb.7: # %bb16 -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: jne .LBB0_5 +; CHECK-NEXT: # %bb.3: # %bb16 +; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: testb $1, %dil -; CHECK-NEXT: jne .LBB0_9 -; CHECK-NEXT: # %bb.8: # %bb17 -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: jne .LBB0_1 +; CHECK-NEXT: # %bb.4: # %bb17 +; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: movq %rcx, %rdx -; CHECK-NEXT: jmp .LBB0_9 -; CHECK-NEXT: .LBB0_2: # %bb9 -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: jmp .LBB0_1 +; CHECK-NEXT: .LBB0_5: # %bb9 +; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: testb $1, %dil ; CHECK-NEXT: testb $1, %dil -; CHECK-NEXT: je .LBB0_4 -; CHECK-NEXT: # %bb.3: # %bb13 -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: je .LBB0_7 +; CHECK-NEXT: # %bb.6: # %bb13 +; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: xorl %eax, %eax -; CHECK-NEXT: .LBB0_4: # %bb14 -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: .LBB0_7: # %bb14 +; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: cmpl $1, %esi -; CHECK-NEXT: je .LBB0_1 -; CHECK-NEXT: # %bb.5: # %bb14 +; CHECK-NEXT: je .LBB0_2 +; CHECK-NEXT: # %bb.8: # %bb14 ; CHECK-NEXT: movl %eax, %r8d ; CHECK-NEXT: testl %esi, %esi ; CHECK-NEXT: movl %esi, %eax -; CHECK-NEXT: jne .LBB0_6 -; CHECK-NEXT: .LBB0_10: # %bb22 +; CHECK-NEXT: jne .LBB0_10 +; CHECK-NEXT: .LBB0_9: # %bb22 ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB0_6: # %bb22.loopexit1 +; CHECK-NEXT: .LBB0_10: # %bb22.loopexit1 ; CHECK-NEXT: movl %r8d, %eax ; CHECK-NEXT: retq bb: diff --git a/llvm/test/CodeGen/X86/SwitchLowering.ll b/llvm/test/CodeGen/X86/SwitchLowering.ll index 921b4e3d24d11..628966c95e14d 100644 --- a/llvm/test/CodeGen/X86/SwitchLowering.ll +++ b/llvm/test/CodeGen/X86/SwitchLowering.ll @@ -72,10 +72,10 @@ define i32 @baz(i32 %0) { ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: movl $13056, %edx # imm = 0x3300 ; CHECK-NEXT: btl %ecx, %edx -; CHECK-NEXT: jae .LBB1_1 -; CHECK-NEXT: # %bb.2: # %return +; CHECK-NEXT: jae .LBB1_2 +; CHECK-NEXT: # %bb.1: # %return ; CHECK-NEXT: retl -; CHECK-NEXT: .LBB1_1: # %sw.epilog8 +; CHECK-NEXT: .LBB1_2: # %sw.epilog8 ; CHECK-NEXT: movl $1, %eax ; CHECK-NEXT: retl switch i32 %0, label %if.then.unreachabledefault [ diff --git a/llvm/test/CodeGen/X86/abs.ll b/llvm/test/CodeGen/X86/abs.ll index e252d5953e60e..91950c261580f 100644 --- a/llvm/test/CodeGen/X86/abs.ll +++ b/llvm/test/CodeGen/X86/abs.ll @@ -737,12 +737,12 @@ define i8 @test_minsigned_i8(i8 %a0, i8 %a1) nounwind { ; X86: # %bb.0: ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X86-NEXT: cmpb $-128, %al -; X86-NEXT: jne .LBB17_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: jne .LBB17_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: retl -; X86-NEXT: .LBB17_1: +; X86-NEXT: .LBB17_2: ; X86-NEXT: movl %eax, %ecx ; X86-NEXT: sarb $7, %cl ; X86-NEXT: xorb %cl, %al @@ -824,12 +824,12 @@ define i64 @test_minsigned_i64(i64 %a0, i64 %a1) nounwind { ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: leal -2147483648(%edx), %ecx ; X86-NEXT: orl %eax, %ecx -; X86-NEXT: jne .LBB20_1 -; X86-NEXT: # %bb.2: # %select.end +; X86-NEXT: jne .LBB20_2 +; X86-NEXT: # %bb.1: # %select.end ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB20_1: # %select.false.sink +; X86-NEXT: .LBB20_2: # %select.false.sink ; X86-NEXT: movl %edx, %ecx ; X86-NEXT: sarl $31, %ecx ; X86-NEXT: xorl %ecx, %edx diff --git a/llvm/test/CodeGen/X86/absolute-bt.ll b/llvm/test/CodeGen/X86/absolute-bt.ll index 7c42e4f190b8f..f64bfacfc608b 100644 --- a/llvm/test/CodeGen/X86/absolute-bt.ll +++ b/llvm/test/CodeGen/X86/absolute-bt.ll @@ -17,10 +17,10 @@ define void @foo32(ptr %ptr) nounwind { ; CHECK-NEXT: movl $bit_mask32, %eax ; CHECK-NEXT: movl (%rdi), %ecx ; CHECK-NEXT: btl %ecx, %eax -; CHECK-NEXT: jae .LBB0_1 -; CHECK-NEXT: # %bb.2: # %f +; CHECK-NEXT: jae .LBB0_2 +; CHECK-NEXT: # %bb.1: # %f ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB0_1: # %t +; CHECK-NEXT: .LBB0_2: # %t ; CHECK-NEXT: pushq %rax ; CHECK-NEXT: callq f@PLT ; CHECK-NEXT: popq %rax @@ -46,10 +46,10 @@ define void @foo64(ptr %ptr) nounwind { ; CHECK-NEXT: movabsq $bit_mask64, %rax ; CHECK-NEXT: movl (%rdi), %ecx ; CHECK-NEXT: btq %rcx, %rax -; CHECK-NEXT: jae .LBB1_1 -; CHECK-NEXT: # %bb.2: # %f +; CHECK-NEXT: jae .LBB1_2 +; CHECK-NEXT: # %bb.1: # %f ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB1_1: # %t +; CHECK-NEXT: .LBB1_2: # %t ; CHECK-NEXT: pushq %rax ; CHECK-NEXT: callq f@PLT ; CHECK-NEXT: popq %rax diff --git a/llvm/test/CodeGen/X86/absolute-constant.ll b/llvm/test/CodeGen/X86/absolute-constant.ll index 5cd9bd8f56e66..4d0dbe013d2e7 100644 --- a/llvm/test/CodeGen/X86/absolute-constant.ll +++ b/llvm/test/CodeGen/X86/absolute-constant.ll @@ -11,21 +11,21 @@ define void @bar(ptr %x) { ; CHECK-LABEL: bar: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: testb $foo, (%rdi) -; CHECK-NEXT: je .LBB0_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: je .LBB0_2 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: jmp xf@PLT # TAILCALL -; CHECK-NEXT: .LBB0_1: # %if.end +; CHECK-NEXT: .LBB0_2: # %if.end ; CHECK-NEXT: retq ; ; PIC-LABEL: bar: ; PIC: # %bb.0: # %entry ; PIC-NEXT: testb $foo, (%rdi) -; PIC-NEXT: je .LBB0_1 -; PIC-NEXT: # %bb.2: # %if.then +; PIC-NEXT: je .LBB0_2 +; PIC-NEXT: # %bb.1: # %if.then ; PIC-NEXT: xorl %eax, %eax ; PIC-NEXT: jmp xf@PLT # TAILCALL -; PIC-NEXT: .LBB0_1: # %if.end +; PIC-NEXT: .LBB0_2: # %if.end ; PIC-NEXT: retq entry: %0 = load i8, ptr %x, align 1 diff --git a/llvm/test/CodeGen/X86/addr-mode-matcher-2.ll b/llvm/test/CodeGen/X86/addr-mode-matcher-2.ll index c810fe137024c..f0488db6d49a1 100644 --- a/llvm/test/CodeGen/X86/addr-mode-matcher-2.ll +++ b/llvm/test/CodeGen/X86/addr-mode-matcher-2.ll @@ -25,37 +25,37 @@ define void @foo_sext_nsw(i1 zeroext, i32) nounwind { ; X86-LABEL: foo_sext_nsw: ; X86: # %bb.0: ; X86-NEXT: cmpb $0, {{[0-9]+}}(%esp) -; X86-NEXT: je .LBB0_1 -; X86-NEXT: # %bb.3: +; X86-NEXT: je .LBB0_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: retl -; X86-NEXT: .LBB0_1: # %.preheader +; X86-NEXT: .LBB0_2: # %.preheader ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: .p2align 4 -; X86-NEXT: .LBB0_2: # =>This Inner Loop Header: Depth=1 +; X86-NEXT: .LBB0_3: # =>This Inner Loop Header: Depth=1 ; X86-NEXT: leal (%eax,%eax,4), %eax ; X86-NEXT: leal 20(,%eax,4), %eax ; X86-NEXT: pushl %eax ; X86-NEXT: calll bar@PLT ; X86-NEXT: addl $4, %esp -; X86-NEXT: jmp .LBB0_2 +; X86-NEXT: jmp .LBB0_3 ; ; X64-LABEL: foo_sext_nsw: ; X64: # %bb.0: ; X64-NEXT: pushq %rax ; X64-NEXT: testl %edi, %edi -; X64-NEXT: je .LBB0_1 -; X64-NEXT: # %bb.3: +; X64-NEXT: je .LBB0_2 +; X64-NEXT: # %bb.1: ; X64-NEXT: popq %rax ; X64-NEXT: retq -; X64-NEXT: .LBB0_1: # %.preheader +; X64-NEXT: .LBB0_2: # %.preheader ; X64-NEXT: movl %esi, %eax ; X64-NEXT: .p2align 4 -; X64-NEXT: .LBB0_2: # =>This Inner Loop Header: Depth=1 +; X64-NEXT: .LBB0_3: # =>This Inner Loop Header: Depth=1 ; X64-NEXT: cltq ; X64-NEXT: shlq $2, %rax ; X64-NEXT: leaq 20(%rax,%rax,4), %rdi ; X64-NEXT: callq bar@PLT -; X64-NEXT: jmp .LBB0_2 +; X64-NEXT: jmp .LBB0_3 br i1 %0, label %9, label %3 %4 = phi i32 [ %8, %3 ], [ %1, %2 ] @@ -72,38 +72,38 @@ define void @foo_sext_nuw(i1 zeroext, i32) nounwind { ; X86-LABEL: foo_sext_nuw: ; X86: # %bb.0: ; X86-NEXT: cmpb $0, {{[0-9]+}}(%esp) -; X86-NEXT: je .LBB1_1 -; X86-NEXT: # %bb.3: +; X86-NEXT: je .LBB1_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: retl -; X86-NEXT: .LBB1_1: # %.preheader +; X86-NEXT: .LBB1_2: # %.preheader ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: .p2align 4 -; X86-NEXT: .LBB1_2: # =>This Inner Loop Header: Depth=1 +; X86-NEXT: .LBB1_3: # =>This Inner Loop Header: Depth=1 ; X86-NEXT: leal (%eax,%eax,4), %eax ; X86-NEXT: leal 20(,%eax,4), %eax ; X86-NEXT: pushl %eax ; X86-NEXT: calll bar@PLT ; X86-NEXT: addl $4, %esp -; X86-NEXT: jmp .LBB1_2 +; X86-NEXT: jmp .LBB1_3 ; ; X64-LABEL: foo_sext_nuw: ; X64: # %bb.0: ; X64-NEXT: pushq %rax ; X64-NEXT: testl %edi, %edi -; X64-NEXT: je .LBB1_1 -; X64-NEXT: # %bb.3: +; X64-NEXT: je .LBB1_2 +; X64-NEXT: # %bb.1: ; X64-NEXT: popq %rax ; X64-NEXT: retq -; X64-NEXT: .LBB1_1: # %.preheader +; X64-NEXT: .LBB1_2: # %.preheader ; X64-NEXT: movl %esi, %eax ; X64-NEXT: .p2align 4 -; X64-NEXT: .LBB1_2: # =>This Inner Loop Header: Depth=1 +; X64-NEXT: .LBB1_3: # =>This Inner Loop Header: Depth=1 ; X64-NEXT: incl %eax ; X64-NEXT: cltq ; X64-NEXT: shlq $2, %rax ; X64-NEXT: leaq (%rax,%rax,4), %rdi ; X64-NEXT: callq bar@PLT -; X64-NEXT: jmp .LBB1_2 +; X64-NEXT: jmp .LBB1_3 br i1 %0, label %9, label %3 %4 = phi i32 [ %8, %3 ], [ %1, %2 ] @@ -120,38 +120,38 @@ define void @foo_zext_nsw(i1 zeroext, i32) nounwind { ; X86-LABEL: foo_zext_nsw: ; X86: # %bb.0: ; X86-NEXT: cmpb $0, {{[0-9]+}}(%esp) -; X86-NEXT: je .LBB2_1 -; X86-NEXT: # %bb.3: +; X86-NEXT: je .LBB2_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: retl -; X86-NEXT: .LBB2_1: # %.preheader +; X86-NEXT: .LBB2_2: # %.preheader ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: .p2align 4 -; X86-NEXT: .LBB2_2: # =>This Inner Loop Header: Depth=1 +; X86-NEXT: .LBB2_3: # =>This Inner Loop Header: Depth=1 ; X86-NEXT: leal (%eax,%eax,4), %eax ; X86-NEXT: leal 20(,%eax,4), %eax ; X86-NEXT: pushl %eax ; X86-NEXT: calll bar@PLT ; X86-NEXT: addl $4, %esp -; X86-NEXT: jmp .LBB2_2 +; X86-NEXT: jmp .LBB2_3 ; ; X64-LABEL: foo_zext_nsw: ; X64: # %bb.0: ; X64-NEXT: pushq %rax ; X64-NEXT: testl %edi, %edi -; X64-NEXT: je .LBB2_1 -; X64-NEXT: # %bb.3: +; X64-NEXT: je .LBB2_2 +; X64-NEXT: # %bb.1: ; X64-NEXT: popq %rax ; X64-NEXT: retq -; X64-NEXT: .LBB2_1: # %.preheader +; X64-NEXT: .LBB2_2: # %.preheader ; X64-NEXT: movl %esi, %eax ; X64-NEXT: .p2align 4 -; X64-NEXT: .LBB2_2: # =>This Inner Loop Header: Depth=1 +; X64-NEXT: .LBB2_3: # =>This Inner Loop Header: Depth=1 ; X64-NEXT: incl %eax ; X64-NEXT: shlq $2, %rax ; X64-NEXT: leaq (%rax,%rax,4), %rdi ; X64-NEXT: callq bar@PLT ; X64-NEXT: # kill: def $eax killed $eax def $rax -; X64-NEXT: jmp .LBB2_2 +; X64-NEXT: jmp .LBB2_3 br i1 %0, label %9, label %3 %4 = phi i32 [ %8, %3 ], [ %1, %2 ] @@ -168,37 +168,37 @@ define void @foo_zext_nuw(i1 zeroext, i32) nounwind { ; X86-LABEL: foo_zext_nuw: ; X86: # %bb.0: ; X86-NEXT: cmpb $0, {{[0-9]+}}(%esp) -; X86-NEXT: je .LBB3_1 -; X86-NEXT: # %bb.3: +; X86-NEXT: je .LBB3_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: retl -; X86-NEXT: .LBB3_1: # %.preheader +; X86-NEXT: .LBB3_2: # %.preheader ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: .p2align 4 -; X86-NEXT: .LBB3_2: # =>This Inner Loop Header: Depth=1 +; X86-NEXT: .LBB3_3: # =>This Inner Loop Header: Depth=1 ; X86-NEXT: leal (%eax,%eax,4), %eax ; X86-NEXT: leal 20(,%eax,4), %eax ; X86-NEXT: pushl %eax ; X86-NEXT: calll bar@PLT ; X86-NEXT: addl $4, %esp -; X86-NEXT: jmp .LBB3_2 +; X86-NEXT: jmp .LBB3_3 ; ; X64-LABEL: foo_zext_nuw: ; X64: # %bb.0: ; X64-NEXT: pushq %rax ; X64-NEXT: testl %edi, %edi -; X64-NEXT: je .LBB3_1 -; X64-NEXT: # %bb.3: +; X64-NEXT: je .LBB3_2 +; X64-NEXT: # %bb.1: ; X64-NEXT: popq %rax ; X64-NEXT: retq -; X64-NEXT: .LBB3_1: # %.preheader +; X64-NEXT: .LBB3_2: # %.preheader ; X64-NEXT: movl %esi, %eax ; X64-NEXT: .p2align 4 -; X64-NEXT: .LBB3_2: # =>This Inner Loop Header: Depth=1 +; X64-NEXT: .LBB3_3: # =>This Inner Loop Header: Depth=1 ; X64-NEXT: movl %eax, %eax ; X64-NEXT: shlq $2, %rax ; X64-NEXT: leaq 20(%rax,%rax,4), %rdi ; X64-NEXT: callq bar@PLT -; X64-NEXT: jmp .LBB3_2 +; X64-NEXT: jmp .LBB3_3 br i1 %0, label %9, label %3 %4 = phi i32 [ %8, %3 ], [ %1, %2 ] @@ -215,38 +215,38 @@ define void @foo_sext(i1 zeroext, i32) nounwind { ; X86-LABEL: foo_sext: ; X86: # %bb.0: ; X86-NEXT: cmpb $0, {{[0-9]+}}(%esp) -; X86-NEXT: je .LBB4_1 -; X86-NEXT: # %bb.3: +; X86-NEXT: je .LBB4_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: retl -; X86-NEXT: .LBB4_1: # %.preheader +; X86-NEXT: .LBB4_2: # %.preheader ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: .p2align 4 -; X86-NEXT: .LBB4_2: # =>This Inner Loop Header: Depth=1 +; X86-NEXT: .LBB4_3: # =>This Inner Loop Header: Depth=1 ; X86-NEXT: leal (%eax,%eax,4), %eax ; X86-NEXT: leal 20(,%eax,4), %eax ; X86-NEXT: pushl %eax ; X86-NEXT: calll bar@PLT ; X86-NEXT: addl $4, %esp -; X86-NEXT: jmp .LBB4_2 +; X86-NEXT: jmp .LBB4_3 ; ; X64-LABEL: foo_sext: ; X64: # %bb.0: ; X64-NEXT: pushq %rax ; X64-NEXT: testl %edi, %edi -; X64-NEXT: je .LBB4_1 -; X64-NEXT: # %bb.3: +; X64-NEXT: je .LBB4_2 +; X64-NEXT: # %bb.1: ; X64-NEXT: popq %rax ; X64-NEXT: retq -; X64-NEXT: .LBB4_1: # %.preheader +; X64-NEXT: .LBB4_2: # %.preheader ; X64-NEXT: movl %esi, %eax ; X64-NEXT: .p2align 4 -; X64-NEXT: .LBB4_2: # =>This Inner Loop Header: Depth=1 +; X64-NEXT: .LBB4_3: # =>This Inner Loop Header: Depth=1 ; X64-NEXT: incl %eax ; X64-NEXT: cltq ; X64-NEXT: shlq $2, %rax ; X64-NEXT: leaq (%rax,%rax,4), %rdi ; X64-NEXT: callq bar@PLT -; X64-NEXT: jmp .LBB4_2 +; X64-NEXT: jmp .LBB4_3 br i1 %0, label %9, label %3 %4 = phi i32 [ %8, %3 ], [ %1, %2 ] @@ -263,38 +263,38 @@ define void @foo_zext(i1 zeroext, i32) nounwind { ; X86-LABEL: foo_zext: ; X86: # %bb.0: ; X86-NEXT: cmpb $0, {{[0-9]+}}(%esp) -; X86-NEXT: je .LBB5_1 -; X86-NEXT: # %bb.3: +; X86-NEXT: je .LBB5_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: retl -; X86-NEXT: .LBB5_1: # %.preheader +; X86-NEXT: .LBB5_2: # %.preheader ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: .p2align 4 -; X86-NEXT: .LBB5_2: # =>This Inner Loop Header: Depth=1 +; X86-NEXT: .LBB5_3: # =>This Inner Loop Header: Depth=1 ; X86-NEXT: leal (%eax,%eax,4), %eax ; X86-NEXT: leal 20(,%eax,4), %eax ; X86-NEXT: pushl %eax ; X86-NEXT: calll bar@PLT ; X86-NEXT: addl $4, %esp -; X86-NEXT: jmp .LBB5_2 +; X86-NEXT: jmp .LBB5_3 ; ; X64-LABEL: foo_zext: ; X64: # %bb.0: ; X64-NEXT: pushq %rax ; X64-NEXT: testl %edi, %edi -; X64-NEXT: je .LBB5_1 -; X64-NEXT: # %bb.3: +; X64-NEXT: je .LBB5_2 +; X64-NEXT: # %bb.1: ; X64-NEXT: popq %rax ; X64-NEXT: retq -; X64-NEXT: .LBB5_1: # %.preheader +; X64-NEXT: .LBB5_2: # %.preheader ; X64-NEXT: movl %esi, %eax ; X64-NEXT: .p2align 4 -; X64-NEXT: .LBB5_2: # =>This Inner Loop Header: Depth=1 +; X64-NEXT: .LBB5_3: # =>This Inner Loop Header: Depth=1 ; X64-NEXT: incl %eax ; X64-NEXT: shlq $2, %rax ; X64-NEXT: leaq (%rax,%rax,4), %rdi ; X64-NEXT: callq bar@PLT ; X64-NEXT: # kill: def $eax killed $eax def $rax -; X64-NEXT: jmp .LBB5_2 +; X64-NEXT: jmp .LBB5_3 br i1 %0, label %9, label %3 %4 = phi i32 [ %8, %3 ], [ %1, %2 ] diff --git a/llvm/test/CodeGen/X86/align-branch-boundary-suppressions.ll b/llvm/test/CodeGen/X86/align-branch-boundary-suppressions.ll index 97e2b5ff63e51..8abacc9b3f9f7 100644 --- a/llvm/test/CodeGen/X86/align-branch-boundary-suppressions.ll +++ b/llvm/test/CodeGen/X86/align-branch-boundary-suppressions.ll @@ -16,11 +16,11 @@ define i32 @implicit_null_check(ptr %x) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: #noautopadding ; CHECK-NEXT: .Ltmp0: -; CHECK-NEXT: movl (%rdi), %eax # on-fault: .LBB0_1 +; CHECK-NEXT: movl (%rdi), %eax # on-fault: .LBB0_2 ; CHECK-NEXT: #autopadding -; CHECK-NEXT: # %bb.2: # %not_null +; CHECK-NEXT: # %bb.1: # %not_null ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB0_1: # %is_null +; CHECK-NEXT: .LBB0_2: # %is_null ; CHECK-NEXT: movl $42, %eax ; CHECK-NEXT: retq diff --git a/llvm/test/CodeGen/X86/and-sink.ll b/llvm/test/CodeGen/X86/and-sink.ll index d9a34d743ac65..95095edbba0f9 100644 --- a/llvm/test/CodeGen/X86/and-sink.ll +++ b/llvm/test/CodeGen/X86/and-sink.ll @@ -103,17 +103,17 @@ define i32 @and_sink3(i1 %c, ptr %p) { ; CHECK-LABEL: and_sink3: ; CHECK: # %bb.0: ; CHECK-NEXT: testb $1, {{[0-9]+}}(%esp) -; CHECK-NEXT: je .LBB2_3 +; CHECK-NEXT: je .LBB2_2 ; CHECK-NEXT: # %bb.1: # %bb0 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: movzbl (%eax), %eax ; CHECK-NEXT: testl %eax, %eax ; CHECK-NEXT: movl $0, A -; CHECK-NEXT: je .LBB2_2 -; CHECK-NEXT: .LBB2_3: # %bb2 +; CHECK-NEXT: je .LBB2_3 +; CHECK-NEXT: .LBB2_2: # %bb2 ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: retl -; CHECK-NEXT: .LBB2_2: # %bb1 +; CHECK-NEXT: .LBB2_3: # %bb1 ; CHECK-NEXT: movl $1, %eax ; CHECK-NEXT: retl @@ -141,22 +141,22 @@ define i32 @and_sink4(i32 %a, i32 %b, i1 %c) { ; CHECK-LABEL: and_sink4: ; CHECK: # %bb.0: ; CHECK-NEXT: testb $1, {{[0-9]+}}(%esp) -; CHECK-NEXT: je .LBB3_4 +; CHECK-NEXT: je .LBB3_3 ; CHECK-NEXT: # %bb.1: # %bb0 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: testl %eax, %ecx ; CHECK-NEXT: movl $0, A -; CHECK-NEXT: jne .LBB3_4 +; CHECK-NEXT: jne .LBB3_3 ; CHECK-NEXT: # %bb.2: # %bb1 ; CHECK-NEXT: leal (%ecx,%eax), %edx ; CHECK-NEXT: testl %eax, %ecx ; CHECK-NEXT: movl %edx, B -; CHECK-NEXT: je .LBB3_3 -; CHECK-NEXT: .LBB3_4: # %bb3 +; CHECK-NEXT: je .LBB3_4 +; CHECK-NEXT: .LBB3_3: # %bb3 ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: retl -; CHECK-NEXT: .LBB3_3: # %bb2 +; CHECK-NEXT: .LBB3_4: # %bb2 ; CHECK-NEXT: movl $1, %eax ; CHECK-NEXT: retl @@ -192,22 +192,22 @@ define i32 @and_sink5(i32 %a, i32 %b, i32 %a2, i32 %b2, i1 %c) { ; CHECK-LABEL: and_sink5: ; CHECK: # %bb.0: ; CHECK-NEXT: testb $1, {{[0-9]+}}(%esp) -; CHECK-NEXT: je .LBB4_4 +; CHECK-NEXT: je .LBB4_3 ; CHECK-NEXT: # %bb.1: # %bb0 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: andl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: movl $0, A -; CHECK-NEXT: jne .LBB4_4 +; CHECK-NEXT: jne .LBB4_3 ; CHECK-NEXT: # %bb.2: # %bb1 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: addl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: testl %eax, %eax ; CHECK-NEXT: movl %ecx, B -; CHECK-NEXT: je .LBB4_3 -; CHECK-NEXT: .LBB4_4: # %bb3 +; CHECK-NEXT: je .LBB4_4 +; CHECK-NEXT: .LBB4_3: # %bb3 ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: retl -; CHECK-NEXT: .LBB4_3: # %bb2 +; CHECK-NEXT: .LBB4_4: # %bb2 ; CHECK-NEXT: movl $1, %eax ; CHECK-NEXT: retl diff --git a/llvm/test/CodeGen/X86/andnot-patterns.ll b/llvm/test/CodeGen/X86/andnot-patterns.ll index fc573fbd4fc99..8c960a1e4ef09 100644 --- a/llvm/test/CodeGen/X86/andnot-patterns.ll +++ b/llvm/test/CodeGen/X86/andnot-patterns.ll @@ -21,11 +21,11 @@ define i64 @andnot_rotl_i64(i64 %a0, i64 %a1, i64 %a2) nounwind { ; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NOBMI-NEXT: testb $32, %cl -; X86-NOBMI-NEXT: jne .LBB0_1 -; X86-NOBMI-NEXT: # %bb.2: +; X86-NOBMI-NEXT: jne .LBB0_2 +; X86-NOBMI-NEXT: # %bb.1: ; X86-NOBMI-NEXT: movl %eax, %edx ; X86-NOBMI-NEXT: jmp .LBB0_3 -; X86-NOBMI-NEXT: .LBB0_1: +; X86-NOBMI-NEXT: .LBB0_2: ; X86-NOBMI-NEXT: movl %esi, %edx ; X86-NOBMI-NEXT: movl %eax, %esi ; X86-NOBMI-NEXT: .LBB0_3: @@ -47,11 +47,11 @@ define i64 @andnot_rotl_i64(i64 %a0, i64 %a1, i64 %a2) nounwind { ; X86-BMI-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-BMI-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-BMI-NEXT: testb $32, %cl -; X86-BMI-NEXT: jne .LBB0_1 -; X86-BMI-NEXT: # %bb.2: +; X86-BMI-NEXT: jne .LBB0_2 +; X86-BMI-NEXT: # %bb.1: ; X86-BMI-NEXT: movl %eax, %esi ; X86-BMI-NEXT: jmp .LBB0_3 -; X86-BMI-NEXT: .LBB0_1: +; X86-BMI-NEXT: .LBB0_2: ; X86-BMI-NEXT: movl %edx, %esi ; X86-BMI-NEXT: movl %eax, %edx ; X86-BMI-NEXT: .LBB0_3: @@ -202,11 +202,11 @@ define i64 @andnot_rotl_i64_multiuse_rot(i64 %a0, i64 %a1, i64 %a2) nounwind { ; X86-NEXT: notl %edx ; X86-NEXT: notl %esi ; X86-NEXT: testb $32, %cl -; X86-NEXT: jne .LBB4_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: jne .LBB4_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: movl %esi, %eax ; X86-NEXT: jmp .LBB4_3 -; X86-NEXT: .LBB4_1: +; X86-NEXT: .LBB4_2: ; X86-NEXT: movl %edx, %eax ; X86-NEXT: movl %esi, %edx ; X86-NEXT: .LBB4_3: @@ -262,11 +262,11 @@ define i64 @andnot_rotr_i64(i64 %a0, i64 %a1, i64 %a2) nounwind { ; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NOBMI-NEXT: testb $32, %cl -; X86-NOBMI-NEXT: je .LBB5_1 -; X86-NOBMI-NEXT: # %bb.2: +; X86-NOBMI-NEXT: je .LBB5_2 +; X86-NOBMI-NEXT: # %bb.1: ; X86-NOBMI-NEXT: movl %eax, %edx ; X86-NOBMI-NEXT: jmp .LBB5_3 -; X86-NOBMI-NEXT: .LBB5_1: +; X86-NOBMI-NEXT: .LBB5_2: ; X86-NOBMI-NEXT: movl %esi, %edx ; X86-NOBMI-NEXT: movl %eax, %esi ; X86-NOBMI-NEXT: .LBB5_3: @@ -288,11 +288,11 @@ define i64 @andnot_rotr_i64(i64 %a0, i64 %a1, i64 %a2) nounwind { ; X86-BMI-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-BMI-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-BMI-NEXT: testb $32, %cl -; X86-BMI-NEXT: je .LBB5_1 -; X86-BMI-NEXT: # %bb.2: +; X86-BMI-NEXT: je .LBB5_2 +; X86-BMI-NEXT: # %bb.1: ; X86-BMI-NEXT: movl %eax, %esi ; X86-BMI-NEXT: jmp .LBB5_3 -; X86-BMI-NEXT: .LBB5_1: +; X86-BMI-NEXT: .LBB5_2: ; X86-BMI-NEXT: movl %edx, %esi ; X86-BMI-NEXT: movl %eax, %edx ; X86-BMI-NEXT: .LBB5_3: diff --git a/llvm/test/CodeGen/X86/apx/ccmp.ll b/llvm/test/CodeGen/X86/apx/ccmp.ll index a9cf0c060e729..f92279f8e0173 100644 --- a/llvm/test/CodeGen/X86/apx/ccmp.ll +++ b/llvm/test/CodeGen/X86/apx/ccmp.ll @@ -8,28 +8,28 @@ define void @ccmp8rr_zf(i8 noundef %a, i8 noundef %b, i8 noundef %c) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cmpb %dl, %dil # encoding: [0x40,0x38,0xd7] ; CHECK-NEXT: ccmpneb {dfv=zf} %dl, %sil # encoding: [0x62,0xf4,0x14,0x05,0x38,0xd6] -; CHECK-NEXT: jne .LBB0_1 # encoding: [0x75,A] -; CHECK-NEXT: # fixup A - offset: 1, value: .LBB0_1, kind: FK_PCRel_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jne .LBB0_2 # encoding: [0x75,A] +; CHECK-NEXT: # fixup A - offset: 1, value: .LBB0_2, kind: FK_PCRel_1 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; CHECK-NEXT: jmp foo # TAILCALL ; CHECK-NEXT: # encoding: [0xeb,A] ; CHECK-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; CHECK-NEXT: .LBB0_1: # %if.end +; CHECK-NEXT: .LBB0_2: # %if.end ; CHECK-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: ccmp8rr_zf: ; NDD: # %bb.0: # %entry ; NDD-NEXT: cmpb %dl, %dil # encoding: [0x40,0x38,0xd7] ; NDD-NEXT: ccmpneb {dfv=zf} %dl, %sil # encoding: [0x62,0xf4,0x14,0x05,0x38,0xd6] -; NDD-NEXT: jne .LBB0_1 # encoding: [0x75,A] -; NDD-NEXT: # fixup A - offset: 1, value: .LBB0_1, kind: FK_PCRel_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: jne .LBB0_2 # encoding: [0x75,A] +; NDD-NEXT: # fixup A - offset: 1, value: .LBB0_2, kind: FK_PCRel_1 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; NDD-NEXT: jmp foo # TAILCALL ; NDD-NEXT: # encoding: [0xeb,A] ; NDD-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; NDD-NEXT: .LBB0_1: # %if.end +; NDD-NEXT: .LBB0_2: # %if.end ; NDD-NEXT: retq # encoding: [0xc3] ; ; SETZUCC-LABEL: ccmp8rr_zf: @@ -67,28 +67,28 @@ define void @ccmp8rr_cf(i8 noundef %a, i8 noundef %b) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cmpb $2, %dil # encoding: [0x40,0x80,0xff,0x02] ; CHECK-NEXT: ccmpgeb {dfv=cf} $2, %sil # encoding: [0x62,0xf4,0x0c,0x0d,0x80,0xfe,0x02] -; CHECK-NEXT: jb .LBB1_1 # encoding: [0x72,A] -; CHECK-NEXT: # fixup A - offset: 1, value: .LBB1_1, kind: FK_PCRel_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jb .LBB1_2 # encoding: [0x72,A] +; CHECK-NEXT: # fixup A - offset: 1, value: .LBB1_2, kind: FK_PCRel_1 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; CHECK-NEXT: jmp foo # TAILCALL ; CHECK-NEXT: # encoding: [0xeb,A] ; CHECK-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; CHECK-NEXT: .LBB1_1: # %if.end +; CHECK-NEXT: .LBB1_2: # %if.end ; CHECK-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: ccmp8rr_cf: ; NDD: # %bb.0: # %entry ; NDD-NEXT: cmpb $2, %dil # encoding: [0x40,0x80,0xff,0x02] ; NDD-NEXT: ccmpgeb {dfv=cf} $2, %sil # encoding: [0x62,0xf4,0x0c,0x0d,0x80,0xfe,0x02] -; NDD-NEXT: jb .LBB1_1 # encoding: [0x72,A] -; NDD-NEXT: # fixup A - offset: 1, value: .LBB1_1, kind: FK_PCRel_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: jb .LBB1_2 # encoding: [0x72,A] +; NDD-NEXT: # fixup A - offset: 1, value: .LBB1_2, kind: FK_PCRel_1 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; NDD-NEXT: jmp foo # TAILCALL ; NDD-NEXT: # encoding: [0xeb,A] ; NDD-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; NDD-NEXT: .LBB1_1: # %if.end +; NDD-NEXT: .LBB1_2: # %if.end ; NDD-NEXT: retq # encoding: [0xc3] ; ; SETZUCC-LABEL: ccmp8rr_cf: @@ -98,14 +98,14 @@ define void @ccmp8rr_cf(i8 noundef %a, i8 noundef %b) { ; SETZUCC-NEXT: cmpb $2, %sil # encoding: [0x40,0x80,0xfe,0x02] ; SETZUCC-NEXT: setzub %cl # encoding: [0x62,0xf4,0x7f,0x18,0x42,0xc1] ; SETZUCC-NEXT: orb %al, %cl # encoding: [0x08,0xc1] -; SETZUCC-NEXT: jne .LBB1_1 # encoding: [0x75,A] -; SETZUCC-NEXT: # fixup A - offset: 1, value: .LBB1_1, kind: FK_PCRel_1 -; SETZUCC-NEXT: # %bb.2: # %if.then +; SETZUCC-NEXT: jne .LBB1_2 # encoding: [0x75,A] +; SETZUCC-NEXT: # fixup A - offset: 1, value: .LBB1_2, kind: FK_PCRel_1 +; SETZUCC-NEXT: # %bb.1: # %if.then ; SETZUCC-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; SETZUCC-NEXT: jmp foo # TAILCALL ; SETZUCC-NEXT: # encoding: [0xeb,A] ; SETZUCC-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; SETZUCC-NEXT: .LBB1_1: # %if.end +; SETZUCC-NEXT: .LBB1_2: # %if.end ; SETZUCC-NEXT: retq # encoding: [0xc3] entry: %cmp = icmp sgt i8 %a, 1 @@ -234,28 +234,28 @@ define void @ccmp16rr_sf(i16 noundef %a, i16 noundef %b, i16 noundef %c) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cmpw %dx, %di # encoding: [0x66,0x39,0xd7] ; CHECK-NEXT: ccmplew {dfv=sf} %dx, %si # encoding: [0x62,0xf4,0x25,0x0e,0x39,0xd6] -; CHECK-NEXT: jge .LBB4_1 # encoding: [0x7d,A] -; CHECK-NEXT: # fixup A - offset: 1, value: .LBB4_1, kind: FK_PCRel_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jge .LBB4_2 # encoding: [0x7d,A] +; CHECK-NEXT: # fixup A - offset: 1, value: .LBB4_2, kind: FK_PCRel_1 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; CHECK-NEXT: jmp foo # TAILCALL ; CHECK-NEXT: # encoding: [0xeb,A] ; CHECK-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; CHECK-NEXT: .LBB4_1: # %if.end +; CHECK-NEXT: .LBB4_2: # %if.end ; CHECK-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: ccmp16rr_sf: ; NDD: # %bb.0: # %entry ; NDD-NEXT: cmpw %dx, %di # encoding: [0x66,0x39,0xd7] ; NDD-NEXT: ccmplew {dfv=sf} %dx, %si # encoding: [0x62,0xf4,0x25,0x0e,0x39,0xd6] -; NDD-NEXT: jge .LBB4_1 # encoding: [0x7d,A] -; NDD-NEXT: # fixup A - offset: 1, value: .LBB4_1, kind: FK_PCRel_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: jge .LBB4_2 # encoding: [0x7d,A] +; NDD-NEXT: # fixup A - offset: 1, value: .LBB4_2, kind: FK_PCRel_1 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; NDD-NEXT: jmp foo # TAILCALL ; NDD-NEXT: # encoding: [0xeb,A] ; NDD-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; NDD-NEXT: .LBB4_1: # %if.end +; NDD-NEXT: .LBB4_2: # %if.end ; NDD-NEXT: retq # encoding: [0xc3] ; ; SETZUCC-LABEL: ccmp16rr_sf: @@ -265,14 +265,14 @@ define void @ccmp16rr_sf(i16 noundef %a, i16 noundef %b, i16 noundef %c) { ; SETZUCC-NEXT: cmpw %dx, %si # encoding: [0x66,0x39,0xd6] ; SETZUCC-NEXT: setzuge %cl # encoding: [0x62,0xf4,0x7f,0x18,0x4d,0xc1] ; SETZUCC-NEXT: testb %cl, %al # encoding: [0x84,0xc8] -; SETZUCC-NEXT: jne .LBB4_1 # encoding: [0x75,A] -; SETZUCC-NEXT: # fixup A - offset: 1, value: .LBB4_1, kind: FK_PCRel_1 -; SETZUCC-NEXT: # %bb.2: # %if.then +; SETZUCC-NEXT: jne .LBB4_2 # encoding: [0x75,A] +; SETZUCC-NEXT: # fixup A - offset: 1, value: .LBB4_2, kind: FK_PCRel_1 +; SETZUCC-NEXT: # %bb.1: # %if.then ; SETZUCC-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; SETZUCC-NEXT: jmp foo # TAILCALL ; SETZUCC-NEXT: # encoding: [0xeb,A] ; SETZUCC-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; SETZUCC-NEXT: .LBB4_1: # %if.end +; SETZUCC-NEXT: .LBB4_2: # %if.end ; SETZUCC-NEXT: retq # encoding: [0xc3] entry: %cmp = icmp sgt i16 %a, %c @@ -293,28 +293,28 @@ define void @ccmp32rr_cf(i32 noundef %a, i32 noundef %b, i32 noundef %c) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cmpl %edx, %edi # encoding: [0x39,0xd7] ; CHECK-NEXT: ccmpbl {dfv=cf} %edx, %esi # encoding: [0x62,0xf4,0x0c,0x02,0x39,0xd6] -; CHECK-NEXT: ja .LBB5_1 # encoding: [0x77,A] -; CHECK-NEXT: # fixup A - offset: 1, value: .LBB5_1, kind: FK_PCRel_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: ja .LBB5_2 # encoding: [0x77,A] +; CHECK-NEXT: # fixup A - offset: 1, value: .LBB5_2, kind: FK_PCRel_1 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; CHECK-NEXT: jmp foo # TAILCALL ; CHECK-NEXT: # encoding: [0xeb,A] ; CHECK-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; CHECK-NEXT: .LBB5_1: # %if.end +; CHECK-NEXT: .LBB5_2: # %if.end ; CHECK-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: ccmp32rr_cf: ; NDD: # %bb.0: # %entry ; NDD-NEXT: cmpl %edx, %edi # encoding: [0x39,0xd7] ; NDD-NEXT: ccmpbl {dfv=cf} %edx, %esi # encoding: [0x62,0xf4,0x0c,0x02,0x39,0xd6] -; NDD-NEXT: ja .LBB5_1 # encoding: [0x77,A] -; NDD-NEXT: # fixup A - offset: 1, value: .LBB5_1, kind: FK_PCRel_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: ja .LBB5_2 # encoding: [0x77,A] +; NDD-NEXT: # fixup A - offset: 1, value: .LBB5_2, kind: FK_PCRel_1 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; NDD-NEXT: jmp foo # TAILCALL ; NDD-NEXT: # encoding: [0xeb,A] ; NDD-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; NDD-NEXT: .LBB5_1: # %if.end +; NDD-NEXT: .LBB5_2: # %if.end ; NDD-NEXT: retq # encoding: [0xc3] ; ; SETZUCC-LABEL: ccmp32rr_cf: @@ -324,14 +324,14 @@ define void @ccmp32rr_cf(i32 noundef %a, i32 noundef %b, i32 noundef %c) { ; SETZUCC-NEXT: cmpl %edx, %esi # encoding: [0x39,0xd6] ; SETZUCC-NEXT: setzua %cl # encoding: [0x62,0xf4,0x7f,0x18,0x47,0xc1] ; SETZUCC-NEXT: testb %cl, %al # encoding: [0x84,0xc8] -; SETZUCC-NEXT: jne .LBB5_1 # encoding: [0x75,A] -; SETZUCC-NEXT: # fixup A - offset: 1, value: .LBB5_1, kind: FK_PCRel_1 -; SETZUCC-NEXT: # %bb.2: # %if.then +; SETZUCC-NEXT: jne .LBB5_2 # encoding: [0x75,A] +; SETZUCC-NEXT: # fixup A - offset: 1, value: .LBB5_2, kind: FK_PCRel_1 +; SETZUCC-NEXT: # %bb.1: # %if.then ; SETZUCC-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; SETZUCC-NEXT: jmp foo # TAILCALL ; SETZUCC-NEXT: # encoding: [0xeb,A] ; SETZUCC-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; SETZUCC-NEXT: .LBB5_1: # %if.end +; SETZUCC-NEXT: .LBB5_2: # %if.end ; SETZUCC-NEXT: retq # encoding: [0xc3] entry: %cmp = icmp uge i32 %a, %c @@ -352,28 +352,28 @@ define void @ccmp64rr_of(i64 %a, i64 %b, i64 %c) { ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: cmpq %rdx, %rdi # encoding: [0x48,0x39,0xd7] ; CHECK-NEXT: ccmpbq {dfv=of} %rsi, %rdi # encoding: [0x62,0xf4,0xc4,0x02,0x39,0xf7] -; CHECK-NEXT: jno .LBB6_1 # encoding: [0x71,A] -; CHECK-NEXT: # fixup A - offset: 1, value: .LBB6_1, kind: FK_PCRel_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jno .LBB6_2 # encoding: [0x71,A] +; CHECK-NEXT: # fixup A - offset: 1, value: .LBB6_2, kind: FK_PCRel_1 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; CHECK-NEXT: jmp foo # TAILCALL ; CHECK-NEXT: # encoding: [0xeb,A] ; CHECK-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; CHECK-NEXT: .LBB6_1: # %if.end +; CHECK-NEXT: .LBB6_2: # %if.end ; CHECK-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: ccmp64rr_of: ; NDD: # %bb.0: # %bb ; NDD-NEXT: cmpq %rdx, %rdi # encoding: [0x48,0x39,0xd7] ; NDD-NEXT: ccmpbq {dfv=of} %rsi, %rdi # encoding: [0x62,0xf4,0xc4,0x02,0x39,0xf7] -; NDD-NEXT: jno .LBB6_1 # encoding: [0x71,A] -; NDD-NEXT: # fixup A - offset: 1, value: .LBB6_1, kind: FK_PCRel_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: jno .LBB6_2 # encoding: [0x71,A] +; NDD-NEXT: # fixup A - offset: 1, value: .LBB6_2, kind: FK_PCRel_1 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; NDD-NEXT: jmp foo # TAILCALL ; NDD-NEXT: # encoding: [0xeb,A] ; NDD-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; NDD-NEXT: .LBB6_1: # %if.end +; NDD-NEXT: .LBB6_2: # %if.end ; NDD-NEXT: retq # encoding: [0xc3] ; ; SETZUCC-LABEL: ccmp64rr_of: @@ -383,14 +383,14 @@ define void @ccmp64rr_of(i64 %a, i64 %b, i64 %c) { ; SETZUCC-NEXT: cmpq %rsi, %rdi # encoding: [0x48,0x39,0xf7] ; SETZUCC-NEXT: setzuno %cl # encoding: [0x62,0xf4,0x7f,0x18,0x41,0xc1] ; SETZUCC-NEXT: testb %cl, %al # encoding: [0x84,0xc8] -; SETZUCC-NEXT: jne .LBB6_1 # encoding: [0x75,A] -; SETZUCC-NEXT: # fixup A - offset: 1, value: .LBB6_1, kind: FK_PCRel_1 -; SETZUCC-NEXT: # %bb.2: # %if.then +; SETZUCC-NEXT: jne .LBB6_2 # encoding: [0x75,A] +; SETZUCC-NEXT: # fixup A - offset: 1, value: .LBB6_2, kind: FK_PCRel_1 +; SETZUCC-NEXT: # %bb.1: # %if.then ; SETZUCC-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; SETZUCC-NEXT: jmp foo # TAILCALL ; SETZUCC-NEXT: # encoding: [0xeb,A] ; SETZUCC-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; SETZUCC-NEXT: .LBB6_1: # %if.end +; SETZUCC-NEXT: .LBB6_2: # %if.end ; SETZUCC-NEXT: retq # encoding: [0xc3] bb: %cmp = icmp uge i64 %a, %c @@ -459,28 +459,28 @@ define void @ccmp8ri_zf(i8 noundef %a, i8 noundef %b, i8 noundef %c) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cmpb %dl, %dil # encoding: [0x40,0x38,0xd7] ; CHECK-NEXT: ccmpleb {dfv=zf} $123, %sil # encoding: [0x62,0xf4,0x14,0x0e,0x80,0xfe,0x7b] -; CHECK-NEXT: jne .LBB8_1 # encoding: [0x75,A] -; CHECK-NEXT: # fixup A - offset: 1, value: .LBB8_1, kind: FK_PCRel_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jne .LBB8_2 # encoding: [0x75,A] +; CHECK-NEXT: # fixup A - offset: 1, value: .LBB8_2, kind: FK_PCRel_1 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; CHECK-NEXT: jmp foo # TAILCALL ; CHECK-NEXT: # encoding: [0xeb,A] ; CHECK-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; CHECK-NEXT: .LBB8_1: # %if.end +; CHECK-NEXT: .LBB8_2: # %if.end ; CHECK-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: ccmp8ri_zf: ; NDD: # %bb.0: # %entry ; NDD-NEXT: cmpb %dl, %dil # encoding: [0x40,0x38,0xd7] ; NDD-NEXT: ccmpleb {dfv=zf} $123, %sil # encoding: [0x62,0xf4,0x14,0x0e,0x80,0xfe,0x7b] -; NDD-NEXT: jne .LBB8_1 # encoding: [0x75,A] -; NDD-NEXT: # fixup A - offset: 1, value: .LBB8_1, kind: FK_PCRel_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: jne .LBB8_2 # encoding: [0x75,A] +; NDD-NEXT: # fixup A - offset: 1, value: .LBB8_2, kind: FK_PCRel_1 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; NDD-NEXT: jmp foo # TAILCALL ; NDD-NEXT: # encoding: [0xeb,A] ; NDD-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; NDD-NEXT: .LBB8_1: # %if.end +; NDD-NEXT: .LBB8_2: # %if.end ; NDD-NEXT: retq # encoding: [0xc3] ; ; SETZUCC-LABEL: ccmp8ri_zf: @@ -490,14 +490,14 @@ define void @ccmp8ri_zf(i8 noundef %a, i8 noundef %b, i8 noundef %c) { ; SETZUCC-NEXT: cmpb $123, %sil # encoding: [0x40,0x80,0xfe,0x7b] ; SETZUCC-NEXT: setzune %cl # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc1] ; SETZUCC-NEXT: testb %cl, %al # encoding: [0x84,0xc8] -; SETZUCC-NEXT: jne .LBB8_1 # encoding: [0x75,A] -; SETZUCC-NEXT: # fixup A - offset: 1, value: .LBB8_1, kind: FK_PCRel_1 -; SETZUCC-NEXT: # %bb.2: # %if.then +; SETZUCC-NEXT: jne .LBB8_2 # encoding: [0x75,A] +; SETZUCC-NEXT: # fixup A - offset: 1, value: .LBB8_2, kind: FK_PCRel_1 +; SETZUCC-NEXT: # %bb.1: # %if.then ; SETZUCC-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; SETZUCC-NEXT: jmp foo # TAILCALL ; SETZUCC-NEXT: # encoding: [0xeb,A] ; SETZUCC-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; SETZUCC-NEXT: .LBB8_1: # %if.end +; SETZUCC-NEXT: .LBB8_2: # %if.end ; SETZUCC-NEXT: retq # encoding: [0xc3] entry: %cmp = icmp sgt i8 %a, %c @@ -698,14 +698,14 @@ define void @ccmp16ri_zf(i16 noundef %a, i16 noundef %b, i16 noundef %c) { ; CHECK-NEXT: movswl %si, %eax # encoding: [0x0f,0xbf,0xc6] ; CHECK-NEXT: ccmpael {dfv=sf} $1234, %eax # encoding: [0x62,0xf4,0x24,0x03,0x81,0xf8,0xd2,0x04,0x00,0x00] ; CHECK-NEXT: # imm = 0x4D2 -; CHECK-NEXT: jge .LBB12_1 # encoding: [0x7d,A] -; CHECK-NEXT: # fixup A - offset: 1, value: .LBB12_1, kind: FK_PCRel_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jge .LBB12_2 # encoding: [0x7d,A] +; CHECK-NEXT: # fixup A - offset: 1, value: .LBB12_2, kind: FK_PCRel_1 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; CHECK-NEXT: jmp foo # TAILCALL ; CHECK-NEXT: # encoding: [0xeb,A] ; CHECK-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; CHECK-NEXT: .LBB12_1: # %if.end +; CHECK-NEXT: .LBB12_2: # %if.end ; CHECK-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: ccmp16ri_zf: @@ -714,14 +714,14 @@ define void @ccmp16ri_zf(i16 noundef %a, i16 noundef %b, i16 noundef %c) { ; NDD-NEXT: movswl %si, %eax # encoding: [0x0f,0xbf,0xc6] ; NDD-NEXT: ccmpael {dfv=sf} $1234, %eax # encoding: [0x62,0xf4,0x24,0x03,0x81,0xf8,0xd2,0x04,0x00,0x00] ; NDD-NEXT: # imm = 0x4D2 -; NDD-NEXT: jge .LBB12_1 # encoding: [0x7d,A] -; NDD-NEXT: # fixup A - offset: 1, value: .LBB12_1, kind: FK_PCRel_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: jge .LBB12_2 # encoding: [0x7d,A] +; NDD-NEXT: # fixup A - offset: 1, value: .LBB12_2, kind: FK_PCRel_1 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; NDD-NEXT: jmp foo # TAILCALL ; NDD-NEXT: # encoding: [0xeb,A] ; NDD-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; NDD-NEXT: .LBB12_1: # %if.end +; NDD-NEXT: .LBB12_2: # %if.end ; NDD-NEXT: retq # encoding: [0xc3] ; ; SETZUCC-LABEL: ccmp16ri_zf: @@ -733,14 +733,14 @@ define void @ccmp16ri_zf(i16 noundef %a, i16 noundef %b, i16 noundef %c) { ; SETZUCC-NEXT: # imm = 0x4D2 ; SETZUCC-NEXT: setzuge %cl # encoding: [0x62,0xf4,0x7f,0x18,0x4d,0xc1] ; SETZUCC-NEXT: testb %cl, %al # encoding: [0x84,0xc8] -; SETZUCC-NEXT: jne .LBB12_1 # encoding: [0x75,A] -; SETZUCC-NEXT: # fixup A - offset: 1, value: .LBB12_1, kind: FK_PCRel_1 -; SETZUCC-NEXT: # %bb.2: # %if.then +; SETZUCC-NEXT: jne .LBB12_2 # encoding: [0x75,A] +; SETZUCC-NEXT: # fixup A - offset: 1, value: .LBB12_2, kind: FK_PCRel_1 +; SETZUCC-NEXT: # %bb.1: # %if.then ; SETZUCC-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; SETZUCC-NEXT: jmp foo # TAILCALL ; SETZUCC-NEXT: # encoding: [0xeb,A] ; SETZUCC-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; SETZUCC-NEXT: .LBB12_1: # %if.end +; SETZUCC-NEXT: .LBB12_2: # %if.end ; SETZUCC-NEXT: retq # encoding: [0xc3] entry: %cmp = icmp ult i16 %a, %c @@ -762,14 +762,14 @@ define void @ccmp32ri_cf(i32 noundef %a, i32 noundef %b, i32 noundef %c) { ; CHECK-NEXT: cmpl %edx, %edi # encoding: [0x39,0xd7] ; CHECK-NEXT: ccmpbl {dfv=cf} $1048577, %esi # encoding: [0x62,0xf4,0x0c,0x02,0x81,0xfe,0x01,0x00,0x10,0x00] ; CHECK-NEXT: # imm = 0x100001 -; CHECK-NEXT: jae .LBB13_1 # encoding: [0x73,A] -; CHECK-NEXT: # fixup A - offset: 1, value: .LBB13_1, kind: FK_PCRel_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jae .LBB13_2 # encoding: [0x73,A] +; CHECK-NEXT: # fixup A - offset: 1, value: .LBB13_2, kind: FK_PCRel_1 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; CHECK-NEXT: jmp foo # TAILCALL ; CHECK-NEXT: # encoding: [0xeb,A] ; CHECK-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; CHECK-NEXT: .LBB13_1: # %if.end +; CHECK-NEXT: .LBB13_2: # %if.end ; CHECK-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: ccmp32ri_cf: @@ -777,14 +777,14 @@ define void @ccmp32ri_cf(i32 noundef %a, i32 noundef %b, i32 noundef %c) { ; NDD-NEXT: cmpl %edx, %edi # encoding: [0x39,0xd7] ; NDD-NEXT: ccmpbl {dfv=cf} $1048577, %esi # encoding: [0x62,0xf4,0x0c,0x02,0x81,0xfe,0x01,0x00,0x10,0x00] ; NDD-NEXT: # imm = 0x100001 -; NDD-NEXT: jae .LBB13_1 # encoding: [0x73,A] -; NDD-NEXT: # fixup A - offset: 1, value: .LBB13_1, kind: FK_PCRel_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: jae .LBB13_2 # encoding: [0x73,A] +; NDD-NEXT: # fixup A - offset: 1, value: .LBB13_2, kind: FK_PCRel_1 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; NDD-NEXT: jmp foo # TAILCALL ; NDD-NEXT: # encoding: [0xeb,A] ; NDD-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; NDD-NEXT: .LBB13_1: # %if.end +; NDD-NEXT: .LBB13_2: # %if.end ; NDD-NEXT: retq # encoding: [0xc3] ; ; SETZUCC-LABEL: ccmp32ri_cf: @@ -795,14 +795,14 @@ define void @ccmp32ri_cf(i32 noundef %a, i32 noundef %b, i32 noundef %c) { ; SETZUCC-NEXT: # imm = 0x100001 ; SETZUCC-NEXT: setzuae %cl # encoding: [0x62,0xf4,0x7f,0x18,0x43,0xc1] ; SETZUCC-NEXT: testb %cl, %al # encoding: [0x84,0xc8] -; SETZUCC-NEXT: jne .LBB13_1 # encoding: [0x75,A] -; SETZUCC-NEXT: # fixup A - offset: 1, value: .LBB13_1, kind: FK_PCRel_1 -; SETZUCC-NEXT: # %bb.2: # %if.then +; SETZUCC-NEXT: jne .LBB13_2 # encoding: [0x75,A] +; SETZUCC-NEXT: # fixup A - offset: 1, value: .LBB13_2, kind: FK_PCRel_1 +; SETZUCC-NEXT: # %bb.1: # %if.then ; SETZUCC-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; SETZUCC-NEXT: jmp foo # TAILCALL ; SETZUCC-NEXT: # encoding: [0xeb,A] ; SETZUCC-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; SETZUCC-NEXT: .LBB13_1: # %if.end +; SETZUCC-NEXT: .LBB13_2: # %if.end ; SETZUCC-NEXT: retq # encoding: [0xc3] entry: %cmp = icmp uge i32 %a, %c @@ -824,14 +824,14 @@ define void @ccmp64ri32_zf(i64 noundef %a, i64 noundef %b, i64 noundef %c) { ; CHECK-NEXT: cmpq %rdx, %rdi # encoding: [0x48,0x39,0xd7] ; CHECK-NEXT: ccmpbeq {dfv=sf} $123456, %rsi # encoding: [0x62,0xf4,0xa4,0x06,0x81,0xfe,0x40,0xe2,0x01,0x00] ; CHECK-NEXT: # imm = 0x1E240 -; CHECK-NEXT: jge .LBB14_1 # encoding: [0x7d,A] -; CHECK-NEXT: # fixup A - offset: 1, value: .LBB14_1, kind: FK_PCRel_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jge .LBB14_2 # encoding: [0x7d,A] +; CHECK-NEXT: # fixup A - offset: 1, value: .LBB14_2, kind: FK_PCRel_1 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; CHECK-NEXT: jmp foo # TAILCALL ; CHECK-NEXT: # encoding: [0xeb,A] ; CHECK-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; CHECK-NEXT: .LBB14_1: # %if.end +; CHECK-NEXT: .LBB14_2: # %if.end ; CHECK-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: ccmp64ri32_zf: @@ -839,14 +839,14 @@ define void @ccmp64ri32_zf(i64 noundef %a, i64 noundef %b, i64 noundef %c) { ; NDD-NEXT: cmpq %rdx, %rdi # encoding: [0x48,0x39,0xd7] ; NDD-NEXT: ccmpbeq {dfv=sf} $123456, %rsi # encoding: [0x62,0xf4,0xa4,0x06,0x81,0xfe,0x40,0xe2,0x01,0x00] ; NDD-NEXT: # imm = 0x1E240 -; NDD-NEXT: jge .LBB14_1 # encoding: [0x7d,A] -; NDD-NEXT: # fixup A - offset: 1, value: .LBB14_1, kind: FK_PCRel_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: jge .LBB14_2 # encoding: [0x7d,A] +; NDD-NEXT: # fixup A - offset: 1, value: .LBB14_2, kind: FK_PCRel_1 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; NDD-NEXT: jmp foo # TAILCALL ; NDD-NEXT: # encoding: [0xeb,A] ; NDD-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; NDD-NEXT: .LBB14_1: # %if.end +; NDD-NEXT: .LBB14_2: # %if.end ; NDD-NEXT: retq # encoding: [0xc3] ; ; SETZUCC-LABEL: ccmp64ri32_zf: @@ -857,14 +857,14 @@ define void @ccmp64ri32_zf(i64 noundef %a, i64 noundef %b, i64 noundef %c) { ; SETZUCC-NEXT: # imm = 0x1E240 ; SETZUCC-NEXT: setzuge %cl # encoding: [0x62,0xf4,0x7f,0x18,0x4d,0xc1] ; SETZUCC-NEXT: testb %cl, %al # encoding: [0x84,0xc8] -; SETZUCC-NEXT: jne .LBB14_1 # encoding: [0x75,A] -; SETZUCC-NEXT: # fixup A - offset: 1, value: .LBB14_1, kind: FK_PCRel_1 -; SETZUCC-NEXT: # %bb.2: # %if.then +; SETZUCC-NEXT: jne .LBB14_2 # encoding: [0x75,A] +; SETZUCC-NEXT: # fixup A - offset: 1, value: .LBB14_2, kind: FK_PCRel_1 +; SETZUCC-NEXT: # %bb.1: # %if.then ; SETZUCC-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; SETZUCC-NEXT: jmp foo # TAILCALL ; SETZUCC-NEXT: # encoding: [0xeb,A] ; SETZUCC-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; SETZUCC-NEXT: .LBB14_1: # %if.end +; SETZUCC-NEXT: .LBB14_2: # %if.end ; SETZUCC-NEXT: retq # encoding: [0xc3] entry: %cmp = icmp ugt i64 %a, %c @@ -885,28 +885,28 @@ define void @ccmp8rm_zf(i8 noundef %a, i8 noundef %b, i8 noundef %c, ptr %ptr) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cmpb %dl, %dil # encoding: [0x40,0x38,0xd7] ; CHECK-NEXT: ccmpneb {dfv=zf} (%rcx), %sil # encoding: [0x62,0xf4,0x14,0x05,0x3a,0x31] -; CHECK-NEXT: jne .LBB15_1 # encoding: [0x75,A] -; CHECK-NEXT: # fixup A - offset: 1, value: .LBB15_1, kind: FK_PCRel_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jne .LBB15_2 # encoding: [0x75,A] +; CHECK-NEXT: # fixup A - offset: 1, value: .LBB15_2, kind: FK_PCRel_1 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; CHECK-NEXT: jmp foo # TAILCALL ; CHECK-NEXT: # encoding: [0xeb,A] ; CHECK-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; CHECK-NEXT: .LBB15_1: # %if.end +; CHECK-NEXT: .LBB15_2: # %if.end ; CHECK-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: ccmp8rm_zf: ; NDD: # %bb.0: # %entry ; NDD-NEXT: cmpb %dl, %dil # encoding: [0x40,0x38,0xd7] ; NDD-NEXT: ccmpneb {dfv=zf} (%rcx), %sil # encoding: [0x62,0xf4,0x14,0x05,0x3a,0x31] -; NDD-NEXT: jne .LBB15_1 # encoding: [0x75,A] -; NDD-NEXT: # fixup A - offset: 1, value: .LBB15_1, kind: FK_PCRel_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: jne .LBB15_2 # encoding: [0x75,A] +; NDD-NEXT: # fixup A - offset: 1, value: .LBB15_2, kind: FK_PCRel_1 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; NDD-NEXT: jmp foo # TAILCALL ; NDD-NEXT: # encoding: [0xeb,A] ; NDD-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; NDD-NEXT: .LBB15_1: # %if.end +; NDD-NEXT: .LBB15_2: # %if.end ; NDD-NEXT: retq # encoding: [0xc3] ; ; SETZUCC-LABEL: ccmp8rm_zf: @@ -945,28 +945,28 @@ define void @ccmp16rm_sf(i16 noundef %a, i16 noundef %b, i16 noundef %c, ptr %pt ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cmpw %dx, %di # encoding: [0x66,0x39,0xd7] ; CHECK-NEXT: ccmplew {dfv=sf} (%rcx), %si # encoding: [0x62,0xf4,0x25,0x0e,0x3b,0x31] -; CHECK-NEXT: jge .LBB16_1 # encoding: [0x7d,A] -; CHECK-NEXT: # fixup A - offset: 1, value: .LBB16_1, kind: FK_PCRel_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jge .LBB16_2 # encoding: [0x7d,A] +; CHECK-NEXT: # fixup A - offset: 1, value: .LBB16_2, kind: FK_PCRel_1 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; CHECK-NEXT: jmp foo # TAILCALL ; CHECK-NEXT: # encoding: [0xeb,A] ; CHECK-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; CHECK-NEXT: .LBB16_1: # %if.end +; CHECK-NEXT: .LBB16_2: # %if.end ; CHECK-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: ccmp16rm_sf: ; NDD: # %bb.0: # %entry ; NDD-NEXT: cmpw %dx, %di # encoding: [0x66,0x39,0xd7] ; NDD-NEXT: ccmplew {dfv=sf} (%rcx), %si # encoding: [0x62,0xf4,0x25,0x0e,0x3b,0x31] -; NDD-NEXT: jge .LBB16_1 # encoding: [0x7d,A] -; NDD-NEXT: # fixup A - offset: 1, value: .LBB16_1, kind: FK_PCRel_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: jge .LBB16_2 # encoding: [0x7d,A] +; NDD-NEXT: # fixup A - offset: 1, value: .LBB16_2, kind: FK_PCRel_1 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; NDD-NEXT: jmp foo # TAILCALL ; NDD-NEXT: # encoding: [0xeb,A] ; NDD-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; NDD-NEXT: .LBB16_1: # %if.end +; NDD-NEXT: .LBB16_2: # %if.end ; NDD-NEXT: retq # encoding: [0xc3] ; ; SETZUCC-LABEL: ccmp16rm_sf: @@ -1005,28 +1005,28 @@ define void @ccmp32rm_cf(i32 noundef %a, i32 noundef %b, i32 noundef %c, ptr %pt ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cmpl %edx, %edi # encoding: [0x39,0xd7] ; CHECK-NEXT: ccmpgl {dfv=cf} (%rcx), %esi # encoding: [0x62,0xf4,0x0c,0x0f,0x3b,0x31] -; CHECK-NEXT: ja .LBB17_1 # encoding: [0x77,A] -; CHECK-NEXT: # fixup A - offset: 1, value: .LBB17_1, kind: FK_PCRel_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: ja .LBB17_2 # encoding: [0x77,A] +; CHECK-NEXT: # fixup A - offset: 1, value: .LBB17_2, kind: FK_PCRel_1 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; CHECK-NEXT: jmp foo # TAILCALL ; CHECK-NEXT: # encoding: [0xeb,A] ; CHECK-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; CHECK-NEXT: .LBB17_1: # %if.end +; CHECK-NEXT: .LBB17_2: # %if.end ; CHECK-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: ccmp32rm_cf: ; NDD: # %bb.0: # %entry ; NDD-NEXT: cmpl %edx, %edi # encoding: [0x39,0xd7] ; NDD-NEXT: ccmpgl {dfv=cf} (%rcx), %esi # encoding: [0x62,0xf4,0x0c,0x0f,0x3b,0x31] -; NDD-NEXT: ja .LBB17_1 # encoding: [0x77,A] -; NDD-NEXT: # fixup A - offset: 1, value: .LBB17_1, kind: FK_PCRel_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: ja .LBB17_2 # encoding: [0x77,A] +; NDD-NEXT: # fixup A - offset: 1, value: .LBB17_2, kind: FK_PCRel_1 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; NDD-NEXT: jmp foo # TAILCALL ; NDD-NEXT: # encoding: [0xeb,A] ; NDD-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; NDD-NEXT: .LBB17_1: # %if.end +; NDD-NEXT: .LBB17_2: # %if.end ; NDD-NEXT: retq # encoding: [0xc3] ; ; SETZUCC-LABEL: ccmp32rm_cf: @@ -1065,28 +1065,28 @@ define void @ccmp64rm_sf(i64 noundef %a, i64 noundef %b, i64 noundef %c, ptr %pt ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cmpq %rdx, %rdi # encoding: [0x48,0x39,0xd7] ; CHECK-NEXT: ccmpleq {dfv=sf} (%rcx), %rsi # encoding: [0x62,0xf4,0xa4,0x0e,0x3b,0x31] -; CHECK-NEXT: jge .LBB18_1 # encoding: [0x7d,A] -; CHECK-NEXT: # fixup A - offset: 1, value: .LBB18_1, kind: FK_PCRel_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jge .LBB18_2 # encoding: [0x7d,A] +; CHECK-NEXT: # fixup A - offset: 1, value: .LBB18_2, kind: FK_PCRel_1 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; CHECK-NEXT: jmp foo # TAILCALL ; CHECK-NEXT: # encoding: [0xeb,A] ; CHECK-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; CHECK-NEXT: .LBB18_1: # %if.end +; CHECK-NEXT: .LBB18_2: # %if.end ; CHECK-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: ccmp64rm_sf: ; NDD: # %bb.0: # %entry ; NDD-NEXT: cmpq %rdx, %rdi # encoding: [0x48,0x39,0xd7] ; NDD-NEXT: ccmpleq {dfv=sf} (%rcx), %rsi # encoding: [0x62,0xf4,0xa4,0x0e,0x3b,0x31] -; NDD-NEXT: jge .LBB18_1 # encoding: [0x7d,A] -; NDD-NEXT: # fixup A - offset: 1, value: .LBB18_1, kind: FK_PCRel_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: jge .LBB18_2 # encoding: [0x7d,A] +; NDD-NEXT: # fixup A - offset: 1, value: .LBB18_2, kind: FK_PCRel_1 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; NDD-NEXT: jmp foo # TAILCALL ; NDD-NEXT: # encoding: [0xeb,A] ; NDD-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; NDD-NEXT: .LBB18_1: # %if.end +; NDD-NEXT: .LBB18_2: # %if.end ; NDD-NEXT: retq # encoding: [0xc3] ; ; SETZUCC-LABEL: ccmp64rm_sf: @@ -1125,28 +1125,28 @@ define void @ccmp8mr_zf(i8 noundef %a, i8 noundef %c, ptr %ptr) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cmpb %sil, %dil # encoding: [0x40,0x38,0xf7] ; CHECK-NEXT: ccmpgeb {dfv=zf} %sil, (%rdx) # encoding: [0x62,0xf4,0x14,0x0d,0x38,0x32] -; CHECK-NEXT: jne .LBB19_1 # encoding: [0x75,A] -; CHECK-NEXT: # fixup A - offset: 1, value: .LBB19_1, kind: FK_PCRel_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jne .LBB19_2 # encoding: [0x75,A] +; CHECK-NEXT: # fixup A - offset: 1, value: .LBB19_2, kind: FK_PCRel_1 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; CHECK-NEXT: jmp foo # TAILCALL ; CHECK-NEXT: # encoding: [0xeb,A] ; CHECK-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; CHECK-NEXT: .LBB19_1: # %if.end +; CHECK-NEXT: .LBB19_2: # %if.end ; CHECK-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: ccmp8mr_zf: ; NDD: # %bb.0: # %entry ; NDD-NEXT: cmpb %sil, %dil # encoding: [0x40,0x38,0xf7] ; NDD-NEXT: ccmpgeb {dfv=zf} %sil, (%rdx) # encoding: [0x62,0xf4,0x14,0x0d,0x38,0x32] -; NDD-NEXT: jne .LBB19_1 # encoding: [0x75,A] -; NDD-NEXT: # fixup A - offset: 1, value: .LBB19_1, kind: FK_PCRel_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: jne .LBB19_2 # encoding: [0x75,A] +; NDD-NEXT: # fixup A - offset: 1, value: .LBB19_2, kind: FK_PCRel_1 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; NDD-NEXT: jmp foo # TAILCALL ; NDD-NEXT: # encoding: [0xeb,A] ; NDD-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; NDD-NEXT: .LBB19_1: # %if.end +; NDD-NEXT: .LBB19_2: # %if.end ; NDD-NEXT: retq # encoding: [0xc3] ; ; SETZUCC-LABEL: ccmp8mr_zf: @@ -1185,28 +1185,28 @@ define void @ccmp16mr_sf(i16 noundef %a, i16 noundef %c, ptr %ptr) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cmpw %si, %di # encoding: [0x66,0x39,0xf7] ; CHECK-NEXT: ccmplew {dfv=sf} %si, (%rdx) # encoding: [0x62,0xf4,0x25,0x0e,0x39,0x32] -; CHECK-NEXT: jge .LBB20_1 # encoding: [0x7d,A] -; CHECK-NEXT: # fixup A - offset: 1, value: .LBB20_1, kind: FK_PCRel_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jge .LBB20_2 # encoding: [0x7d,A] +; CHECK-NEXT: # fixup A - offset: 1, value: .LBB20_2, kind: FK_PCRel_1 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; CHECK-NEXT: jmp foo # TAILCALL ; CHECK-NEXT: # encoding: [0xeb,A] ; CHECK-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; CHECK-NEXT: .LBB20_1: # %if.end +; CHECK-NEXT: .LBB20_2: # %if.end ; CHECK-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: ccmp16mr_sf: ; NDD: # %bb.0: # %entry ; NDD-NEXT: cmpw %si, %di # encoding: [0x66,0x39,0xf7] ; NDD-NEXT: ccmplew {dfv=sf} %si, (%rdx) # encoding: [0x62,0xf4,0x25,0x0e,0x39,0x32] -; NDD-NEXT: jge .LBB20_1 # encoding: [0x7d,A] -; NDD-NEXT: # fixup A - offset: 1, value: .LBB20_1, kind: FK_PCRel_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: jge .LBB20_2 # encoding: [0x7d,A] +; NDD-NEXT: # fixup A - offset: 1, value: .LBB20_2, kind: FK_PCRel_1 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; NDD-NEXT: jmp foo # TAILCALL ; NDD-NEXT: # encoding: [0xeb,A] ; NDD-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; NDD-NEXT: .LBB20_1: # %if.end +; NDD-NEXT: .LBB20_2: # %if.end ; NDD-NEXT: retq # encoding: [0xc3] ; ; SETZUCC-LABEL: ccmp16mr_sf: @@ -1245,28 +1245,28 @@ define void @ccmp32mr_cf(i32 noundef %a, i32 noundef %c, ptr %ptr) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cmpl %esi, %edi # encoding: [0x39,0xf7] ; CHECK-NEXT: ccmpll {dfv=cf} %esi, (%rdx) # encoding: [0x62,0xf4,0x0c,0x0c,0x39,0x32] -; CHECK-NEXT: ja .LBB21_1 # encoding: [0x77,A] -; CHECK-NEXT: # fixup A - offset: 1, value: .LBB21_1, kind: FK_PCRel_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: ja .LBB21_2 # encoding: [0x77,A] +; CHECK-NEXT: # fixup A - offset: 1, value: .LBB21_2, kind: FK_PCRel_1 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; CHECK-NEXT: jmp foo # TAILCALL ; CHECK-NEXT: # encoding: [0xeb,A] ; CHECK-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; CHECK-NEXT: .LBB21_1: # %if.end +; CHECK-NEXT: .LBB21_2: # %if.end ; CHECK-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: ccmp32mr_cf: ; NDD: # %bb.0: # %entry ; NDD-NEXT: cmpl %esi, %edi # encoding: [0x39,0xf7] ; NDD-NEXT: ccmpll {dfv=cf} %esi, (%rdx) # encoding: [0x62,0xf4,0x0c,0x0c,0x39,0x32] -; NDD-NEXT: ja .LBB21_1 # encoding: [0x77,A] -; NDD-NEXT: # fixup A - offset: 1, value: .LBB21_1, kind: FK_PCRel_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: ja .LBB21_2 # encoding: [0x77,A] +; NDD-NEXT: # fixup A - offset: 1, value: .LBB21_2, kind: FK_PCRel_1 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; NDD-NEXT: jmp foo # TAILCALL ; NDD-NEXT: # encoding: [0xeb,A] ; NDD-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; NDD-NEXT: .LBB21_1: # %if.end +; NDD-NEXT: .LBB21_2: # %if.end ; NDD-NEXT: retq # encoding: [0xc3] ; ; SETZUCC-LABEL: ccmp32mr_cf: @@ -1305,28 +1305,28 @@ define void @ccmp64mr_sf(i64 noundef %a, i64 noundef %c, ptr %ptr) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cmpq %rsi, %rdi # encoding: [0x48,0x39,0xf7] ; CHECK-NEXT: ccmpleq {dfv=sf} %rsi, (%rdx) # encoding: [0x62,0xf4,0xa4,0x0e,0x39,0x32] -; CHECK-NEXT: jge .LBB22_1 # encoding: [0x7d,A] -; CHECK-NEXT: # fixup A - offset: 1, value: .LBB22_1, kind: FK_PCRel_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jge .LBB22_2 # encoding: [0x7d,A] +; CHECK-NEXT: # fixup A - offset: 1, value: .LBB22_2, kind: FK_PCRel_1 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; CHECK-NEXT: jmp foo # TAILCALL ; CHECK-NEXT: # encoding: [0xeb,A] ; CHECK-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; CHECK-NEXT: .LBB22_1: # %if.end +; CHECK-NEXT: .LBB22_2: # %if.end ; CHECK-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: ccmp64mr_sf: ; NDD: # %bb.0: # %entry ; NDD-NEXT: cmpq %rsi, %rdi # encoding: [0x48,0x39,0xf7] ; NDD-NEXT: ccmpleq {dfv=sf} %rsi, (%rdx) # encoding: [0x62,0xf4,0xa4,0x0e,0x39,0x32] -; NDD-NEXT: jge .LBB22_1 # encoding: [0x7d,A] -; NDD-NEXT: # fixup A - offset: 1, value: .LBB22_1, kind: FK_PCRel_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: jge .LBB22_2 # encoding: [0x7d,A] +; NDD-NEXT: # fixup A - offset: 1, value: .LBB22_2, kind: FK_PCRel_1 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; NDD-NEXT: jmp foo # TAILCALL ; NDD-NEXT: # encoding: [0xeb,A] ; NDD-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; NDD-NEXT: .LBB22_1: # %if.end +; NDD-NEXT: .LBB22_2: # %if.end ; NDD-NEXT: retq # encoding: [0xc3] ; ; SETZUCC-LABEL: ccmp64mr_sf: @@ -1365,28 +1365,28 @@ define void @ccmp8mi_zf(i8 noundef %a, i8 noundef %c, ptr %ptr) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cmpb %sil, %dil # encoding: [0x40,0x38,0xf7] ; CHECK-NEXT: ccmpneb {dfv=zf} $123, (%rdx) # encoding: [0x62,0xf4,0x14,0x05,0x80,0x3a,0x7b] -; CHECK-NEXT: jne .LBB23_1 # encoding: [0x75,A] -; CHECK-NEXT: # fixup A - offset: 1, value: .LBB23_1, kind: FK_PCRel_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jne .LBB23_2 # encoding: [0x75,A] +; CHECK-NEXT: # fixup A - offset: 1, value: .LBB23_2, kind: FK_PCRel_1 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; CHECK-NEXT: jmp foo # TAILCALL ; CHECK-NEXT: # encoding: [0xeb,A] ; CHECK-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; CHECK-NEXT: .LBB23_1: # %if.end +; CHECK-NEXT: .LBB23_2: # %if.end ; CHECK-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: ccmp8mi_zf: ; NDD: # %bb.0: # %entry ; NDD-NEXT: cmpb %sil, %dil # encoding: [0x40,0x38,0xf7] ; NDD-NEXT: ccmpneb {dfv=zf} $123, (%rdx) # encoding: [0x62,0xf4,0x14,0x05,0x80,0x3a,0x7b] -; NDD-NEXT: jne .LBB23_1 # encoding: [0x75,A] -; NDD-NEXT: # fixup A - offset: 1, value: .LBB23_1, kind: FK_PCRel_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: jne .LBB23_2 # encoding: [0x75,A] +; NDD-NEXT: # fixup A - offset: 1, value: .LBB23_2, kind: FK_PCRel_1 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; NDD-NEXT: jmp foo # TAILCALL ; NDD-NEXT: # encoding: [0xeb,A] ; NDD-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; NDD-NEXT: .LBB23_1: # %if.end +; NDD-NEXT: .LBB23_2: # %if.end ; NDD-NEXT: retq # encoding: [0xc3] ; ; SETZUCC-LABEL: ccmp8mi_zf: @@ -1426,14 +1426,14 @@ define void @ccmp16mi_zf(i16 noundef %a, i16 noundef %c, ptr %ptr) { ; CHECK-NEXT: cmpw %si, %di # encoding: [0x66,0x39,0xf7] ; CHECK-NEXT: ccmplew {dfv=sf} $1234, (%rdx) # encoding: [0x62,0xf4,0x25,0x0e,0x81,0x3a,0xd2,0x04] ; CHECK-NEXT: # imm = 0x4D2 -; CHECK-NEXT: jge .LBB24_1 # encoding: [0x7d,A] -; CHECK-NEXT: # fixup A - offset: 1, value: .LBB24_1, kind: FK_PCRel_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jge .LBB24_2 # encoding: [0x7d,A] +; CHECK-NEXT: # fixup A - offset: 1, value: .LBB24_2, kind: FK_PCRel_1 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; CHECK-NEXT: jmp foo # TAILCALL ; CHECK-NEXT: # encoding: [0xeb,A] ; CHECK-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; CHECK-NEXT: .LBB24_1: # %if.end +; CHECK-NEXT: .LBB24_2: # %if.end ; CHECK-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: ccmp16mi_zf: @@ -1441,14 +1441,14 @@ define void @ccmp16mi_zf(i16 noundef %a, i16 noundef %c, ptr %ptr) { ; NDD-NEXT: cmpw %si, %di # encoding: [0x66,0x39,0xf7] ; NDD-NEXT: ccmplew {dfv=sf} $1234, (%rdx) # encoding: [0x62,0xf4,0x25,0x0e,0x81,0x3a,0xd2,0x04] ; NDD-NEXT: # imm = 0x4D2 -; NDD-NEXT: jge .LBB24_1 # encoding: [0x7d,A] -; NDD-NEXT: # fixup A - offset: 1, value: .LBB24_1, kind: FK_PCRel_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: jge .LBB24_2 # encoding: [0x7d,A] +; NDD-NEXT: # fixup A - offset: 1, value: .LBB24_2, kind: FK_PCRel_1 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; NDD-NEXT: jmp foo # TAILCALL ; NDD-NEXT: # encoding: [0xeb,A] ; NDD-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; NDD-NEXT: .LBB24_1: # %if.end +; NDD-NEXT: .LBB24_2: # %if.end ; NDD-NEXT: retq # encoding: [0xc3] ; ; SETZUCC-LABEL: ccmp16mi_zf: @@ -1490,14 +1490,14 @@ define void @ccmp32mi_cf(i32 noundef %a, i32 noundef %c, ptr %ptr) { ; CHECK-NEXT: cmpl %esi, %edi # encoding: [0x39,0xf7] ; CHECK-NEXT: ccmpnel {dfv=cf} $123457, (%rdx) # encoding: [0x62,0xf4,0x0c,0x05,0x81,0x3a,0x41,0xe2,0x01,0x00] ; CHECK-NEXT: # imm = 0x1E241 -; CHECK-NEXT: jae .LBB25_1 # encoding: [0x73,A] -; CHECK-NEXT: # fixup A - offset: 1, value: .LBB25_1, kind: FK_PCRel_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jae .LBB25_2 # encoding: [0x73,A] +; CHECK-NEXT: # fixup A - offset: 1, value: .LBB25_2, kind: FK_PCRel_1 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; CHECK-NEXT: jmp foo # TAILCALL ; CHECK-NEXT: # encoding: [0xeb,A] ; CHECK-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; CHECK-NEXT: .LBB25_1: # %if.end +; CHECK-NEXT: .LBB25_2: # %if.end ; CHECK-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: ccmp32mi_cf: @@ -1505,14 +1505,14 @@ define void @ccmp32mi_cf(i32 noundef %a, i32 noundef %c, ptr %ptr) { ; NDD-NEXT: cmpl %esi, %edi # encoding: [0x39,0xf7] ; NDD-NEXT: ccmpnel {dfv=cf} $123457, (%rdx) # encoding: [0x62,0xf4,0x0c,0x05,0x81,0x3a,0x41,0xe2,0x01,0x00] ; NDD-NEXT: # imm = 0x1E241 -; NDD-NEXT: jae .LBB25_1 # encoding: [0x73,A] -; NDD-NEXT: # fixup A - offset: 1, value: .LBB25_1, kind: FK_PCRel_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: jae .LBB25_2 # encoding: [0x73,A] +; NDD-NEXT: # fixup A - offset: 1, value: .LBB25_2, kind: FK_PCRel_1 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; NDD-NEXT: jmp foo # TAILCALL ; NDD-NEXT: # encoding: [0xeb,A] ; NDD-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; NDD-NEXT: .LBB25_1: # %if.end +; NDD-NEXT: .LBB25_2: # %if.end ; NDD-NEXT: retq # encoding: [0xc3] ; ; SETZUCC-LABEL: ccmp32mi_cf: @@ -1553,14 +1553,14 @@ define void @ccmp64mi32_zf(i64 noundef %a, i64 noundef %c, ptr %ptr) { ; CHECK-NEXT: cmpq %rsi, %rdi # encoding: [0x48,0x39,0xf7] ; CHECK-NEXT: ccmpleq {dfv=sf} $123456, (%rdx) # encoding: [0x62,0xf4,0xa4,0x0e,0x81,0x3a,0x40,0xe2,0x01,0x00] ; CHECK-NEXT: # imm = 0x1E240 -; CHECK-NEXT: jge .LBB26_1 # encoding: [0x7d,A] -; CHECK-NEXT: # fixup A - offset: 1, value: .LBB26_1, kind: FK_PCRel_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jge .LBB26_2 # encoding: [0x7d,A] +; CHECK-NEXT: # fixup A - offset: 1, value: .LBB26_2, kind: FK_PCRel_1 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; CHECK-NEXT: jmp foo # TAILCALL ; CHECK-NEXT: # encoding: [0xeb,A] ; CHECK-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; CHECK-NEXT: .LBB26_1: # %if.end +; CHECK-NEXT: .LBB26_2: # %if.end ; CHECK-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: ccmp64mi32_zf: @@ -1568,14 +1568,14 @@ define void @ccmp64mi32_zf(i64 noundef %a, i64 noundef %c, ptr %ptr) { ; NDD-NEXT: cmpq %rsi, %rdi # encoding: [0x48,0x39,0xf7] ; NDD-NEXT: ccmpleq {dfv=sf} $123456, (%rdx) # encoding: [0x62,0xf4,0xa4,0x0e,0x81,0x3a,0x40,0xe2,0x01,0x00] ; NDD-NEXT: # imm = 0x1E240 -; NDD-NEXT: jge .LBB26_1 # encoding: [0x7d,A] -; NDD-NEXT: # fixup A - offset: 1, value: .LBB26_1, kind: FK_PCRel_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: jge .LBB26_2 # encoding: [0x7d,A] +; NDD-NEXT: # fixup A - offset: 1, value: .LBB26_2, kind: FK_PCRel_1 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; NDD-NEXT: jmp foo # TAILCALL ; NDD-NEXT: # encoding: [0xeb,A] ; NDD-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; NDD-NEXT: .LBB26_1: # %if.end +; NDD-NEXT: .LBB26_2: # %if.end ; NDD-NEXT: retq # encoding: [0xc3] ; ; SETZUCC-LABEL: ccmp64mi32_zf: @@ -1616,14 +1616,14 @@ define void @ccmp_continous(i32 noundef %a, i32 noundef %b, i32 noundef %c) { ; CHECK-NEXT: testl %edi, %edi # encoding: [0x85,0xff] ; CHECK-NEXT: ccmplel {dfv=} $2, %esi # encoding: [0x62,0xf4,0x04,0x0e,0x83,0xfe,0x02] ; CHECK-NEXT: ccmpll {dfv=} $3, %edx # encoding: [0x62,0xf4,0x04,0x0c,0x83,0xfa,0x03] -; CHECK-NEXT: jge .LBB27_1 # encoding: [0x7d,A] -; CHECK-NEXT: # fixup A - offset: 1, value: .LBB27_1, kind: FK_PCRel_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jge .LBB27_2 # encoding: [0x7d,A] +; CHECK-NEXT: # fixup A - offset: 1, value: .LBB27_2, kind: FK_PCRel_1 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; CHECK-NEXT: jmp foo # TAILCALL ; CHECK-NEXT: # encoding: [0xeb,A] ; CHECK-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; CHECK-NEXT: .LBB27_1: # %if.end +; CHECK-NEXT: .LBB27_2: # %if.end ; CHECK-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: ccmp_continous: @@ -1631,14 +1631,14 @@ define void @ccmp_continous(i32 noundef %a, i32 noundef %b, i32 noundef %c) { ; NDD-NEXT: testl %edi, %edi # encoding: [0x85,0xff] ; NDD-NEXT: ccmplel {dfv=} $2, %esi # encoding: [0x62,0xf4,0x04,0x0e,0x83,0xfe,0x02] ; NDD-NEXT: ccmpll {dfv=} $3, %edx # encoding: [0x62,0xf4,0x04,0x0c,0x83,0xfa,0x03] -; NDD-NEXT: jge .LBB27_1 # encoding: [0x7d,A] -; NDD-NEXT: # fixup A - offset: 1, value: .LBB27_1, kind: FK_PCRel_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: jge .LBB27_2 # encoding: [0x7d,A] +; NDD-NEXT: # fixup A - offset: 1, value: .LBB27_2, kind: FK_PCRel_1 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; NDD-NEXT: jmp foo # TAILCALL ; NDD-NEXT: # encoding: [0xeb,A] ; NDD-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; NDD-NEXT: .LBB27_1: # %if.end +; NDD-NEXT: .LBB27_2: # %if.end ; NDD-NEXT: retq # encoding: [0xc3] ; ; SETZUCC-LABEL: ccmp_continous: @@ -1651,14 +1651,14 @@ define void @ccmp_continous(i32 noundef %a, i32 noundef %b, i32 noundef %c) { ; SETZUCC-NEXT: cmpl $3, %edx # encoding: [0x83,0xfa,0x03] ; SETZUCC-NEXT: setzuge %al # encoding: [0x62,0xf4,0x7f,0x18,0x4d,0xc0] ; SETZUCC-NEXT: orb %cl, %al # encoding: [0x08,0xc8] -; SETZUCC-NEXT: jne .LBB27_1 # encoding: [0x75,A] -; SETZUCC-NEXT: # fixup A - offset: 1, value: .LBB27_1, kind: FK_PCRel_1 -; SETZUCC-NEXT: # %bb.2: # %if.then +; SETZUCC-NEXT: jne .LBB27_2 # encoding: [0x75,A] +; SETZUCC-NEXT: # fixup A - offset: 1, value: .LBB27_2, kind: FK_PCRel_1 +; SETZUCC-NEXT: # %bb.1: # %if.then ; SETZUCC-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; SETZUCC-NEXT: jmp foo # TAILCALL ; SETZUCC-NEXT: # encoding: [0xeb,A] ; SETZUCC-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; SETZUCC-NEXT: .LBB27_1: # %if.end +; SETZUCC-NEXT: .LBB27_2: # %if.end ; SETZUCC-NEXT: retq # encoding: [0xc3] entry: %cmp = icmp slt i32 %a, 1 @@ -1758,14 +1758,14 @@ define void @ccmp64ri64(i64 noundef %a, i64 noundef %b, i64 noundef %c) { ; CHECK-NEXT: movabsq $9992147483646, %rax # encoding: [0x48,0xb8,0xfe,0xbb,0x66,0x7a,0x16,0x09,0x00,0x00] ; CHECK-NEXT: # imm = 0x9167A66BBFE ; CHECK-NEXT: ccmpbeq {dfv=zf} %rax, %rsi # encoding: [0x62,0xf4,0x94,0x06,0x39,0xc6] -; CHECK-NEXT: jg .LBB30_1 # encoding: [0x7f,A] -; CHECK-NEXT: # fixup A - offset: 1, value: .LBB30_1, kind: FK_PCRel_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jg .LBB30_2 # encoding: [0x7f,A] +; CHECK-NEXT: # fixup A - offset: 1, value: .LBB30_2, kind: FK_PCRel_1 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; CHECK-NEXT: jmp foo # TAILCALL ; CHECK-NEXT: # encoding: [0xeb,A] ; CHECK-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; CHECK-NEXT: .LBB30_1: # %if.end +; CHECK-NEXT: .LBB30_2: # %if.end ; CHECK-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: ccmp64ri64: @@ -1774,14 +1774,14 @@ define void @ccmp64ri64(i64 noundef %a, i64 noundef %b, i64 noundef %c) { ; NDD-NEXT: movabsq $9992147483646, %rax # encoding: [0x48,0xb8,0xfe,0xbb,0x66,0x7a,0x16,0x09,0x00,0x00] ; NDD-NEXT: # imm = 0x9167A66BBFE ; NDD-NEXT: ccmpbeq {dfv=zf} %rax, %rsi # encoding: [0x62,0xf4,0x94,0x06,0x39,0xc6] -; NDD-NEXT: jg .LBB30_1 # encoding: [0x7f,A] -; NDD-NEXT: # fixup A - offset: 1, value: .LBB30_1, kind: FK_PCRel_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: jg .LBB30_2 # encoding: [0x7f,A] +; NDD-NEXT: # fixup A - offset: 1, value: .LBB30_2, kind: FK_PCRel_1 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; NDD-NEXT: jmp foo # TAILCALL ; NDD-NEXT: # encoding: [0xeb,A] ; NDD-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; NDD-NEXT: .LBB30_1: # %if.end +; NDD-NEXT: .LBB30_2: # %if.end ; NDD-NEXT: retq # encoding: [0xc3] ; ; SETZUCC-LABEL: ccmp64ri64: @@ -1793,14 +1793,14 @@ define void @ccmp64ri64(i64 noundef %a, i64 noundef %b, i64 noundef %c) { ; SETZUCC-NEXT: cmpq %rcx, %rsi # encoding: [0x48,0x39,0xce] ; SETZUCC-NEXT: setzug %cl # encoding: [0x62,0xf4,0x7f,0x18,0x4f,0xc1] ; SETZUCC-NEXT: testb %cl, %al # encoding: [0x84,0xc8] -; SETZUCC-NEXT: jne .LBB30_1 # encoding: [0x75,A] -; SETZUCC-NEXT: # fixup A - offset: 1, value: .LBB30_1, kind: FK_PCRel_1 -; SETZUCC-NEXT: # %bb.2: # %if.then +; SETZUCC-NEXT: jne .LBB30_2 # encoding: [0x75,A] +; SETZUCC-NEXT: # fixup A - offset: 1, value: .LBB30_2, kind: FK_PCRel_1 +; SETZUCC-NEXT: # %bb.1: # %if.then ; SETZUCC-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; SETZUCC-NEXT: jmp foo # TAILCALL ; SETZUCC-NEXT: # encoding: [0xeb,A] ; SETZUCC-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; SETZUCC-NEXT: .LBB30_1: # %if.end +; SETZUCC-NEXT: .LBB30_2: # %if.end ; SETZUCC-NEXT: retq # encoding: [0xc3] entry: %cmp = icmp ugt i64 %a, %c diff --git a/llvm/test/CodeGen/X86/apx/check-nf-in-suppress-reloc-pass.ll b/llvm/test/CodeGen/X86/apx/check-nf-in-suppress-reloc-pass.ll index 3a2c954e37077..23f17d83fe96f 100644 --- a/llvm/test/CodeGen/X86/apx/check-nf-in-suppress-reloc-pass.ll +++ b/llvm/test/CodeGen/X86/apx/check-nf-in-suppress-reloc-pass.ll @@ -21,10 +21,10 @@ define fastcc void @foo(i32 %0, i1 %or.cond) nounwind { ; CHECK-NEXT: movl %r15d, %r12d ; CHECK-NEXT: xorl %r13d, %r13d ; CHECK-NEXT: xorl %ebp, %ebp -; CHECK-NEXT: jmp .LBB0_1 +; CHECK-NEXT: jmp .LBB0_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_3: # %if.end41 -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: .LBB0_1: # %if.end41 +; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: leaq (%r12,%rbp), %rdi ; CHECK-NEXT: # kill: def $edi killed $edi killed $rdi ; CHECK-NEXT: xorl %esi, %esi @@ -32,18 +32,18 @@ define fastcc void @foo(i32 %0, i1 %or.cond) nounwind { ; CHECK-NEXT: callq *%r13 ; CHECK-NEXT: incq %rbp ; CHECK-NEXT: addq $20, %r14 -; CHECK-NEXT: .LBB0_1: # %for.body30 +; CHECK-NEXT: .LBB0_2: # %for.body30 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: testb $1, %bl -; CHECK-NEXT: je .LBB0_3 -; CHECK-NEXT: # %bb.2: # %if.then37 -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: je .LBB0_1 +; CHECK-NEXT: # %bb.3: # %if.then37 +; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: movq %r15, %rax ; CHECK-NEXT: addq %rbp, %rax ; CHECK-NEXT: movq 0, %rax ; CHECK-NEXT: {nf} addq %r15, %rax ; CHECK-NEXT: movb $0, (%rbp,%rax) -; CHECK-NEXT: jmp .LBB0_3 +; CHECK-NEXT: jmp .LBB0_1 entry: %1 = sext i32 %0 to i64 br label %for.body30 diff --git a/llvm/test/CodeGen/X86/apx/ctest.ll b/llvm/test/CodeGen/X86/apx/ctest.ll index 0bd4ac1862ca1..9481cc69c85d3 100644 --- a/llvm/test/CodeGen/X86/apx/ctest.ll +++ b/llvm/test/CodeGen/X86/apx/ctest.ll @@ -8,22 +8,22 @@ define void @ctest8rr_zf(i8 noundef %a, i8 noundef %b) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: testb %dil, %dil ; CHECK-NEXT: ctestneb {dfv=zf} %sil, %sil -; CHECK-NEXT: jne .LBB0_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jne .LBB0_2 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: jmp foo # TAILCALL -; CHECK-NEXT: .LBB0_1: # %if.end +; CHECK-NEXT: .LBB0_2: # %if.end ; CHECK-NEXT: retq ; ; NDD-LABEL: ctest8rr_zf: ; NDD: # %bb.0: # %entry ; NDD-NEXT: testb %dil, %dil ; NDD-NEXT: ctestneb {dfv=zf} %sil, %sil -; NDD-NEXT: jne .LBB0_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: jne .LBB0_2 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax ; NDD-NEXT: jmp foo # TAILCALL -; NDD-NEXT: .LBB0_1: # %if.end +; NDD-NEXT: .LBB0_2: # %if.end ; NDD-NEXT: retq ; ; SETZUCC-LABEL: ctest8rr_zf: @@ -233,22 +233,22 @@ define void @ctest8rr_sf(i8 noundef %a, i8 noundef %b) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: testb %dil, %dil ; CHECK-NEXT: ctesteb {dfv=sf} %sil, %sil -; CHECK-NEXT: js .LBB4_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: js .LBB4_2 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: jmp foo # TAILCALL -; CHECK-NEXT: .LBB4_1: # %if.end +; CHECK-NEXT: .LBB4_2: # %if.end ; CHECK-NEXT: retq ; ; NDD-LABEL: ctest8rr_sf: ; NDD: # %bb.0: # %entry ; NDD-NEXT: testb %dil, %dil ; NDD-NEXT: ctesteb {dfv=sf} %sil, %sil -; NDD-NEXT: js .LBB4_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: js .LBB4_2 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax ; NDD-NEXT: jmp foo # TAILCALL -; NDD-NEXT: .LBB4_1: # %if.end +; NDD-NEXT: .LBB4_2: # %if.end ; NDD-NEXT: retq ; ; SETZUCC-LABEL: ctest8rr_sf: @@ -258,14 +258,14 @@ define void @ctest8rr_sf(i8 noundef %a, i8 noundef %b) { ; SETZUCC-NEXT: testb %sil, %sil # encoding: [0x40,0x84,0xf6] ; SETZUCC-NEXT: setzus %cl # encoding: [0x62,0xf4,0x7f,0x18,0x48,0xc1] ; SETZUCC-NEXT: orb %al, %cl # encoding: [0x08,0xc1] -; SETZUCC-NEXT: jne .LBB4_1 # encoding: [0x75,A] -; SETZUCC-NEXT: # fixup A - offset: 1, value: .LBB4_1, kind: FK_PCRel_1 -; SETZUCC-NEXT: # %bb.2: # %if.then +; SETZUCC-NEXT: jne .LBB4_2 # encoding: [0x75,A] +; SETZUCC-NEXT: # fixup A - offset: 1, value: .LBB4_2, kind: FK_PCRel_1 +; SETZUCC-NEXT: # %bb.1: # %if.then ; SETZUCC-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; SETZUCC-NEXT: jmp foo # TAILCALL ; SETZUCC-NEXT: # encoding: [0xeb,A] ; SETZUCC-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; SETZUCC-NEXT: .LBB4_1: # %if.end +; SETZUCC-NEXT: .LBB4_2: # %if.end ; SETZUCC-NEXT: retq # encoding: [0xc3] entry: %cmp = icmp ule i8 %a, 0 @@ -390,22 +390,22 @@ define void @ctest16rr_sf(i16 noundef %a, i16 noundef %b) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: testw %di, %di ; CHECK-NEXT: ctestlew {dfv=sf} %si, %si -; CHECK-NEXT: jns .LBB7_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jns .LBB7_2 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: jmp foo # TAILCALL -; CHECK-NEXT: .LBB7_1: # %if.end +; CHECK-NEXT: .LBB7_2: # %if.end ; CHECK-NEXT: retq ; ; NDD-LABEL: ctest16rr_sf: ; NDD: # %bb.0: # %entry ; NDD-NEXT: testw %di, %di ; NDD-NEXT: ctestlew {dfv=sf} %si, %si -; NDD-NEXT: jns .LBB7_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: jns .LBB7_2 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax ; NDD-NEXT: jmp foo # TAILCALL -; NDD-NEXT: .LBB7_1: # %if.end +; NDD-NEXT: .LBB7_2: # %if.end ; NDD-NEXT: retq ; ; SETZUCC-LABEL: ctest16rr_sf: @@ -415,14 +415,14 @@ define void @ctest16rr_sf(i16 noundef %a, i16 noundef %b) { ; SETZUCC-NEXT: testw %si, %si # encoding: [0x66,0x85,0xf6] ; SETZUCC-NEXT: setzuns %cl # encoding: [0x62,0xf4,0x7f,0x18,0x49,0xc1] ; SETZUCC-NEXT: testb %cl, %al # encoding: [0x84,0xc8] -; SETZUCC-NEXT: jne .LBB7_1 # encoding: [0x75,A] -; SETZUCC-NEXT: # fixup A - offset: 1, value: .LBB7_1, kind: FK_PCRel_1 -; SETZUCC-NEXT: # %bb.2: # %if.then +; SETZUCC-NEXT: jne .LBB7_2 # encoding: [0x75,A] +; SETZUCC-NEXT: # fixup A - offset: 1, value: .LBB7_2, kind: FK_PCRel_1 +; SETZUCC-NEXT: # %bb.1: # %if.then ; SETZUCC-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; SETZUCC-NEXT: jmp foo # TAILCALL ; SETZUCC-NEXT: # encoding: [0xeb,A] ; SETZUCC-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; SETZUCC-NEXT: .LBB7_1: # %if.end +; SETZUCC-NEXT: .LBB7_2: # %if.end ; SETZUCC-NEXT: retq # encoding: [0xc3] entry: %cmp = icmp sgt i16 %a, 0 @@ -443,22 +443,22 @@ define void @ctest32rr_zf(i32 noundef %a, i32 noundef %b) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: testl %edi, %edi ; CHECK-NEXT: ctestsl {dfv=zf} %esi, %esi -; CHECK-NEXT: jne .LBB8_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jne .LBB8_2 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: jmp foo # TAILCALL -; CHECK-NEXT: .LBB8_1: # %if.end +; CHECK-NEXT: .LBB8_2: # %if.end ; CHECK-NEXT: retq ; ; NDD-LABEL: ctest32rr_zf: ; NDD: # %bb.0: # %entry ; NDD-NEXT: testl %edi, %edi ; NDD-NEXT: ctestsl {dfv=zf} %esi, %esi -; NDD-NEXT: jne .LBB8_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: jne .LBB8_2 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax ; NDD-NEXT: jmp foo # TAILCALL -; NDD-NEXT: .LBB8_1: # %if.end +; NDD-NEXT: .LBB8_2: # %if.end ; NDD-NEXT: retq ; ; SETZUCC-LABEL: ctest32rr_zf: @@ -468,14 +468,14 @@ define void @ctest32rr_zf(i32 noundef %a, i32 noundef %b) { ; SETZUCC-NEXT: testl %esi, %esi # encoding: [0x85,0xf6] ; SETZUCC-NEXT: setzune %cl # encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc1] ; SETZUCC-NEXT: testb %cl, %al # encoding: [0x84,0xc8] -; SETZUCC-NEXT: jne .LBB8_1 # encoding: [0x75,A] -; SETZUCC-NEXT: # fixup A - offset: 1, value: .LBB8_1, kind: FK_PCRel_1 -; SETZUCC-NEXT: # %bb.2: # %if.then +; SETZUCC-NEXT: jne .LBB8_2 # encoding: [0x75,A] +; SETZUCC-NEXT: # fixup A - offset: 1, value: .LBB8_2, kind: FK_PCRel_1 +; SETZUCC-NEXT: # %bb.1: # %if.then ; SETZUCC-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; SETZUCC-NEXT: jmp foo # TAILCALL ; SETZUCC-NEXT: # encoding: [0xeb,A] ; SETZUCC-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; SETZUCC-NEXT: .LBB8_1: # %if.end +; SETZUCC-NEXT: .LBB8_2: # %if.end ; SETZUCC-NEXT: retq # encoding: [0xc3] entry: %cmp = icmp sge i32 %a, 0 @@ -496,22 +496,22 @@ define void @ctest8ri_zf(i8 noundef %a, i8 noundef %b) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: testb %dil, %dil ; CHECK-NEXT: ctestneb {dfv=zf} $123, %sil -; CHECK-NEXT: jne .LBB9_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jne .LBB9_2 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: jmp foo # TAILCALL -; CHECK-NEXT: .LBB9_1: # %if.end +; CHECK-NEXT: .LBB9_2: # %if.end ; CHECK-NEXT: retq ; ; NDD-LABEL: ctest8ri_zf: ; NDD: # %bb.0: # %entry ; NDD-NEXT: testb %dil, %dil ; NDD-NEXT: ctestneb {dfv=zf} $123, %sil -; NDD-NEXT: jne .LBB9_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: jne .LBB9_2 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax ; NDD-NEXT: jmp foo # TAILCALL -; NDD-NEXT: .LBB9_1: # %if.end +; NDD-NEXT: .LBB9_2: # %if.end ; NDD-NEXT: retq ; ; SETZUCC-LABEL: ctest8ri_zf: @@ -551,22 +551,22 @@ define void @ctest16ri_zf(i16 noundef %a, i16 noundef %b) { ; CHECK-NEXT: andl $1234, %esi # imm = 0x4D2 ; CHECK-NEXT: testw %di, %di ; CHECK-NEXT: ctestnew {dfv=zf} %si, %si -; CHECK-NEXT: jne .LBB10_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jne .LBB10_2 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: jmp foo # TAILCALL -; CHECK-NEXT: .LBB10_1: # %if.end +; CHECK-NEXT: .LBB10_2: # %if.end ; CHECK-NEXT: retq ; ; NDD-LABEL: ctest16ri_zf: ; NDD: # %bb.0: # %entry ; NDD-NEXT: testw %di, %di ; NDD-NEXT: ctestnew {dfv=zf} $1234, %si # imm = 0x4D2 -; NDD-NEXT: jne .LBB10_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: jne .LBB10_2 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax ; NDD-NEXT: jmp foo # TAILCALL -; NDD-NEXT: .LBB10_1: # %if.end +; NDD-NEXT: .LBB10_2: # %if.end ; NDD-NEXT: retq ; ; SETZUCC-LABEL: ctest16ri_zf: @@ -606,22 +606,22 @@ define void @ctest32ri_zf(i32 noundef %a, i32 noundef %b) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: testl %edi, %edi ; CHECK-NEXT: ctestnel {dfv=zf} $12345, %esi # imm = 0x3039 -; CHECK-NEXT: jne .LBB11_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jne .LBB11_2 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: jmp foo # TAILCALL -; CHECK-NEXT: .LBB11_1: # %if.end +; CHECK-NEXT: .LBB11_2: # %if.end ; CHECK-NEXT: retq ; ; NDD-LABEL: ctest32ri_zf: ; NDD: # %bb.0: # %entry ; NDD-NEXT: testl %edi, %edi ; NDD-NEXT: ctestnel {dfv=zf} $12345, %esi # imm = 0x3039 -; NDD-NEXT: jne .LBB11_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: jne .LBB11_2 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax ; NDD-NEXT: jmp foo # TAILCALL -; NDD-NEXT: .LBB11_1: # %if.end +; NDD-NEXT: .LBB11_2: # %if.end ; NDD-NEXT: retq ; ; SETZUCC-LABEL: ctest32ri_zf: @@ -661,22 +661,22 @@ define void @ctest64ri32_zf(i64 noundef %a, i64 noundef %b) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: testq %rdi, %rdi ; CHECK-NEXT: ctestneq {dfv=zf} $123456, %rsi # imm = 0x1E240 -; CHECK-NEXT: jne .LBB12_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jne .LBB12_2 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: jmp foo # TAILCALL -; CHECK-NEXT: .LBB12_1: # %if.end +; CHECK-NEXT: .LBB12_2: # %if.end ; CHECK-NEXT: retq ; ; NDD-LABEL: ctest64ri32_zf: ; NDD: # %bb.0: # %entry ; NDD-NEXT: testq %rdi, %rdi ; NDD-NEXT: ctestneq {dfv=zf} $123456, %rsi # imm = 0x1E240 -; NDD-NEXT: jne .LBB12_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: jne .LBB12_2 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax ; NDD-NEXT: jmp foo # TAILCALL -; NDD-NEXT: .LBB12_1: # %if.end +; NDD-NEXT: .LBB12_2: # %if.end ; NDD-NEXT: retq ; ; SETZUCC-LABEL: ctest64ri32_zf: @@ -717,11 +717,11 @@ define void @ctest8mr_zf(i8 noundef %a, ptr %ptr) { ; CHECK-NEXT: movzbl (%rsi), %eax ; CHECK-NEXT: testb %dil, %dil ; CHECK-NEXT: ctestneb {dfv=zf} %al, %al -; CHECK-NEXT: jne .LBB13_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jne .LBB13_2 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: jmp foo # TAILCALL -; CHECK-NEXT: .LBB13_1: # %if.end +; CHECK-NEXT: .LBB13_2: # %if.end ; CHECK-NEXT: retq ; ; NDD-LABEL: ctest8mr_zf: @@ -729,11 +729,11 @@ define void @ctest8mr_zf(i8 noundef %a, ptr %ptr) { ; NDD-NEXT: movzbl (%rsi), %eax ; NDD-NEXT: testb %dil, %dil ; NDD-NEXT: ctestneb {dfv=zf} %al, %al -; NDD-NEXT: jne .LBB13_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: jne .LBB13_2 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax ; NDD-NEXT: jmp foo # TAILCALL -; NDD-NEXT: .LBB13_1: # %if.end +; NDD-NEXT: .LBB13_2: # %if.end ; NDD-NEXT: retq ; ; SETZUCC-LABEL: ctest8mr_zf: @@ -773,11 +773,11 @@ define void @ctest16mr_zf(i16 noundef %a, ptr %ptr) { ; CHECK-NEXT: movzwl (%rsi), %eax ; CHECK-NEXT: testw %di, %di ; CHECK-NEXT: ctestnew {dfv=zf} %ax, %ax -; CHECK-NEXT: jne .LBB14_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jne .LBB14_2 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: jmp foo # TAILCALL -; CHECK-NEXT: .LBB14_1: # %if.end +; CHECK-NEXT: .LBB14_2: # %if.end ; CHECK-NEXT: retq ; ; NDD-LABEL: ctest16mr_zf: @@ -785,11 +785,11 @@ define void @ctest16mr_zf(i16 noundef %a, ptr %ptr) { ; NDD-NEXT: movzwl (%rsi), %eax ; NDD-NEXT: testw %di, %di ; NDD-NEXT: ctestnew {dfv=zf} %ax, %ax -; NDD-NEXT: jne .LBB14_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: jne .LBB14_2 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax ; NDD-NEXT: jmp foo # TAILCALL -; NDD-NEXT: .LBB14_1: # %if.end +; NDD-NEXT: .LBB14_2: # %if.end ; NDD-NEXT: retq ; ; SETZUCC-LABEL: ctest16mr_zf: @@ -829,11 +829,11 @@ define void @ctest32mr_cf(i32 noundef %a, ptr %ptr) { ; CHECK-NEXT: movl (%rsi), %eax ; CHECK-NEXT: testl %edi, %edi ; CHECK-NEXT: ctestnel {dfv=zf} %eax, %eax -; CHECK-NEXT: jne .LBB15_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jne .LBB15_2 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: jmp foo # TAILCALL -; CHECK-NEXT: .LBB15_1: # %if.end +; CHECK-NEXT: .LBB15_2: # %if.end ; CHECK-NEXT: retq ; ; NDD-LABEL: ctest32mr_cf: @@ -841,11 +841,11 @@ define void @ctest32mr_cf(i32 noundef %a, ptr %ptr) { ; NDD-NEXT: movl (%rsi), %eax ; NDD-NEXT: testl %edi, %edi ; NDD-NEXT: ctestnel {dfv=zf} %eax, %eax -; NDD-NEXT: jne .LBB15_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: jne .LBB15_2 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax ; NDD-NEXT: jmp foo # TAILCALL -; NDD-NEXT: .LBB15_1: # %if.end +; NDD-NEXT: .LBB15_2: # %if.end ; NDD-NEXT: retq ; ; SETZUCC-LABEL: ctest32mr_cf: @@ -885,11 +885,11 @@ define void @ctest64mr_zf(i64 noundef %a, ptr %ptr) { ; CHECK-NEXT: movq (%rsi), %rax ; CHECK-NEXT: testq %rdi, %rdi ; CHECK-NEXT: ctestneq {dfv=zf} %rax, %rax -; CHECK-NEXT: jne .LBB16_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jne .LBB16_2 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: jmp foo # TAILCALL -; CHECK-NEXT: .LBB16_1: # %if.end +; CHECK-NEXT: .LBB16_2: # %if.end ; CHECK-NEXT: retq ; ; NDD-LABEL: ctest64mr_zf: @@ -897,11 +897,11 @@ define void @ctest64mr_zf(i64 noundef %a, ptr %ptr) { ; NDD-NEXT: movq (%rsi), %rax ; NDD-NEXT: testq %rdi, %rdi ; NDD-NEXT: ctestneq {dfv=zf} %rax, %rax -; NDD-NEXT: jne .LBB16_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: jne .LBB16_2 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax ; NDD-NEXT: jmp foo # TAILCALL -; NDD-NEXT: .LBB16_1: # %if.end +; NDD-NEXT: .LBB16_2: # %if.end ; NDD-NEXT: retq ; ; SETZUCC-LABEL: ctest64mr_zf: @@ -940,22 +940,22 @@ define void @ctest8mi_zf(i8 noundef %a, ptr %ptr) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: testb %dil, %dil ; CHECK-NEXT: ctestneb {dfv=zf} $123, (%rsi) -; CHECK-NEXT: jne .LBB17_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jne .LBB17_2 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: jmp foo # TAILCALL -; CHECK-NEXT: .LBB17_1: # %if.end +; CHECK-NEXT: .LBB17_2: # %if.end ; CHECK-NEXT: retq ; ; NDD-LABEL: ctest8mi_zf: ; NDD: # %bb.0: # %entry ; NDD-NEXT: testb %dil, %dil ; NDD-NEXT: ctestneb {dfv=zf} $123, (%rsi) -; NDD-NEXT: jne .LBB17_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: jne .LBB17_2 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax ; NDD-NEXT: jmp foo # TAILCALL -; NDD-NEXT: .LBB17_1: # %if.end +; NDD-NEXT: .LBB17_2: # %if.end ; NDD-NEXT: retq ; ; SETZUCC-LABEL: ctest8mi_zf: @@ -998,22 +998,22 @@ define void @ctest16mi_zf(i16 noundef %a, ptr %ptr) { ; CHECK-NEXT: andl $1234, %eax # imm = 0x4D2 ; CHECK-NEXT: testw %di, %di ; CHECK-NEXT: ctestnew {dfv=zf} %ax, %ax -; CHECK-NEXT: jne .LBB18_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jne .LBB18_2 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: jmp foo # TAILCALL -; CHECK-NEXT: .LBB18_1: # %if.end +; CHECK-NEXT: .LBB18_2: # %if.end ; CHECK-NEXT: retq ; ; NDD-LABEL: ctest16mi_zf: ; NDD: # %bb.0: # %entry ; NDD-NEXT: testw %di, %di ; NDD-NEXT: ctestnew {dfv=zf} $1234, (%rsi) # imm = 0x4D2 -; NDD-NEXT: jne .LBB18_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: jne .LBB18_2 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax ; NDD-NEXT: jmp foo # TAILCALL -; NDD-NEXT: .LBB18_1: # %if.end +; NDD-NEXT: .LBB18_2: # %if.end ; NDD-NEXT: retq ; ; SETZUCC-LABEL: ctest16mi_zf: @@ -1057,22 +1057,22 @@ define void @ctest32mi_zf(i32 noundef %a, ptr %ptr) { ; CHECK-NEXT: andl $12345, %eax # imm = 0x3039 ; CHECK-NEXT: testl %edi, %edi ; CHECK-NEXT: ctestnew {dfv=zf} %ax, %ax -; CHECK-NEXT: jne .LBB19_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jne .LBB19_2 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: jmp foo # TAILCALL -; CHECK-NEXT: .LBB19_1: # %if.end +; CHECK-NEXT: .LBB19_2: # %if.end ; CHECK-NEXT: retq ; ; NDD-LABEL: ctest32mi_zf: ; NDD: # %bb.0: # %entry ; NDD-NEXT: testl %edi, %edi ; NDD-NEXT: ctestnew {dfv=zf} $12345, (%rsi) # imm = 0x3039 -; NDD-NEXT: jne .LBB19_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: jne .LBB19_2 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax ; NDD-NEXT: jmp foo # TAILCALL -; NDD-NEXT: .LBB19_1: # %if.end +; NDD-NEXT: .LBB19_2: # %if.end ; NDD-NEXT: retq ; ; SETZUCC-LABEL: ctest32mi_zf: @@ -1114,22 +1114,22 @@ define void @ctest64mi32_zf(i64 noundef %a, ptr %ptr) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: testq %rdi, %rdi ; CHECK-NEXT: ctestnel {dfv=zf} $123456, (%rsi) # imm = 0x1E240 -; CHECK-NEXT: jne .LBB20_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jne .LBB20_2 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: jmp foo # TAILCALL -; CHECK-NEXT: .LBB20_1: # %if.end +; CHECK-NEXT: .LBB20_2: # %if.end ; CHECK-NEXT: retq ; ; NDD-LABEL: ctest64mi32_zf: ; NDD: # %bb.0: # %entry ; NDD-NEXT: testq %rdi, %rdi ; NDD-NEXT: ctestnel {dfv=zf} $123456, (%rsi) # imm = 0x1E240 -; NDD-NEXT: jne .LBB20_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: jne .LBB20_2 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax ; NDD-NEXT: jmp foo # TAILCALL -; NDD-NEXT: .LBB20_1: # %if.end +; NDD-NEXT: .LBB20_2: # %if.end ; NDD-NEXT: retq ; ; SETZUCC-LABEL: ctest64mi32_zf: @@ -1172,11 +1172,11 @@ define void @ctest_continous(i32 noundef %a, i32 noundef %b, i32 noundef %c) { ; CHECK-NEXT: cmpl %esi, %edi ; CHECK-NEXT: ctestll {dfv=} %esi, %esi ; CHECK-NEXT: ctestnsl {dfv=sf} %edx, %edx -; CHECK-NEXT: jns .LBB21_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jns .LBB21_2 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: jmp foo # TAILCALL -; CHECK-NEXT: .LBB21_1: # %if.end +; CHECK-NEXT: .LBB21_2: # %if.end ; CHECK-NEXT: retq ; ; NDD-LABEL: ctest_continous: @@ -1184,11 +1184,11 @@ define void @ctest_continous(i32 noundef %a, i32 noundef %b, i32 noundef %c) { ; NDD-NEXT: cmpl %esi, %edi ; NDD-NEXT: ctestll {dfv=} %esi, %esi ; NDD-NEXT: ctestnsl {dfv=sf} %edx, %edx -; NDD-NEXT: jns .LBB21_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: jns .LBB21_2 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax ; NDD-NEXT: jmp foo # TAILCALL -; NDD-NEXT: .LBB21_1: # %if.end +; NDD-NEXT: .LBB21_2: # %if.end ; NDD-NEXT: retq ; ; SETZUCC-LABEL: ctest_continous: @@ -1201,14 +1201,14 @@ define void @ctest_continous(i32 noundef %a, i32 noundef %b, i32 noundef %c) { ; SETZUCC-NEXT: testl %edx, %edx # encoding: [0x85,0xd2] ; SETZUCC-NEXT: setzuns %al # encoding: [0x62,0xf4,0x7f,0x18,0x49,0xc0] ; SETZUCC-NEXT: testb %al, %cl # encoding: [0x84,0xc1] -; SETZUCC-NEXT: jne .LBB21_1 # encoding: [0x75,A] -; SETZUCC-NEXT: # fixup A - offset: 1, value: .LBB21_1, kind: FK_PCRel_1 -; SETZUCC-NEXT: # %bb.2: # %if.then +; SETZUCC-NEXT: jne .LBB21_2 # encoding: [0x75,A] +; SETZUCC-NEXT: # fixup A - offset: 1, value: .LBB21_2, kind: FK_PCRel_1 +; SETZUCC-NEXT: # %bb.1: # %if.then ; SETZUCC-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; SETZUCC-NEXT: jmp foo # TAILCALL ; SETZUCC-NEXT: # encoding: [0xeb,A] ; SETZUCC-NEXT: # fixup A - offset: 1, value: foo, kind: FK_PCRel_1 -; SETZUCC-NEXT: .LBB21_1: # %if.end +; SETZUCC-NEXT: .LBB21_2: # %if.end ; SETZUCC-NEXT: retq # encoding: [0xc3] entry: %cmp = icmp slt i32 %a, %b @@ -1307,11 +1307,11 @@ define void @ctest64ri64(i64 noundef %a, i64 noundef %b) { ; CHECK-NEXT: testq %rdi, %rdi ; CHECK-NEXT: movabsq $9992147483647, %rax # imm = 0x9167A66BBFF ; CHECK-NEXT: ctestneq {dfv=zf} %rax, %rsi -; CHECK-NEXT: jne .LBB24_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jne .LBB24_2 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: jmp foo # TAILCALL -; CHECK-NEXT: .LBB24_1: # %if.end +; CHECK-NEXT: .LBB24_2: # %if.end ; CHECK-NEXT: retq ; ; NDD-LABEL: ctest64ri64: @@ -1319,11 +1319,11 @@ define void @ctest64ri64(i64 noundef %a, i64 noundef %b) { ; NDD-NEXT: testq %rdi, %rdi ; NDD-NEXT: movabsq $9992147483647, %rax # imm = 0x9167A66BBFF ; NDD-NEXT: ctestneq {dfv=zf} %rax, %rsi -; NDD-NEXT: jne .LBB24_1 -; NDD-NEXT: # %bb.2: # %if.then +; NDD-NEXT: jne .LBB24_2 +; NDD-NEXT: # %bb.1: # %if.then ; NDD-NEXT: xorl %eax, %eax ; NDD-NEXT: jmp foo # TAILCALL -; NDD-NEXT: .LBB24_1: # %if.end +; NDD-NEXT: .LBB24_2: # %if.end ; NDD-NEXT: retq ; ; SETZUCC-LABEL: ctest64ri64: diff --git a/llvm/test/CodeGen/X86/apx/kmov-postrapseudos.ll b/llvm/test/CodeGen/X86/apx/kmov-postrapseudos.ll index fd811b0bbfc4e..923587792d191 100644 --- a/llvm/test/CodeGen/X86/apx/kmov-postrapseudos.ll +++ b/llvm/test/CodeGen/X86/apx/kmov-postrapseudos.ll @@ -53,24 +53,24 @@ define i32 @kmovrk_1(<4 x ptr> %arg) { ; AVX512-LABEL: kmovrk_1: ; AVX512: # %bb.0: # %bb ; AVX512-NEXT: vptest %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x17,0xc0] -; AVX512-NEXT: jne .LBB2_1 # encoding: [0x75,A] -; AVX512-NEXT: # fixup A - offset: 1, value: .LBB2_1, kind: FK_PCRel_1 -; AVX512-NEXT: # %bb.2: # %bb3 +; AVX512-NEXT: jne .LBB2_2 # encoding: [0x75,A] +; AVX512-NEXT: # fixup A - offset: 1, value: .LBB2_2, kind: FK_PCRel_1 +; AVX512-NEXT: # %bb.1: # %bb3 ; AVX512-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; AVX512-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77] ; AVX512-NEXT: retq # encoding: [0xc3] -; AVX512-NEXT: .LBB2_1: # %bb2 +; AVX512-NEXT: .LBB2_2: # %bb2 ; ; AVX512BW-LABEL: kmovrk_1: ; AVX512BW: # %bb.0: # %bb ; AVX512BW-NEXT: vptest %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x17,0xc0] -; AVX512BW-NEXT: jne .LBB2_1 # encoding: [0x75,A] -; AVX512BW-NEXT: # fixup A - offset: 1, value: .LBB2_1, kind: FK_PCRel_1 -; AVX512BW-NEXT: # %bb.2: # %bb3 +; AVX512BW-NEXT: jne .LBB2_2 # encoding: [0x75,A] +; AVX512BW-NEXT: # fixup A - offset: 1, value: .LBB2_2, kind: FK_PCRel_1 +; AVX512BW-NEXT: # %bb.1: # %bb3 ; AVX512BW-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; AVX512BW-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77] ; AVX512BW-NEXT: retq # encoding: [0xc3] -; AVX512BW-NEXT: .LBB2_1: # %bb2 +; AVX512BW-NEXT: .LBB2_2: # %bb2 bb: %icmp = icmp ne <4 x ptr> %arg, zeroinitializer %freeze = freeze <4 x i1> %icmp diff --git a/llvm/test/CodeGen/X86/apx/nf-regressions.ll b/llvm/test/CodeGen/X86/apx/nf-regressions.ll index 68bd05a0737b6..15df93eb6cb39 100644 --- a/llvm/test/CodeGen/X86/apx/nf-regressions.ll +++ b/llvm/test/CodeGen/X86/apx/nf-regressions.ll @@ -8,36 +8,36 @@ define void @convertToThreeAddress(ptr %arg, ptr %arg1) { ; CHECK-NEXT: movslq (%rsi), %rcx ; CHECK-NEXT: subq %rax, %rcx ; CHECK-NEXT: leaq 1(%rcx), %rax -; CHECK-NEXT: js .LBB0_1 +; CHECK-NEXT: js .LBB0_3 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_6: # %bb +; CHECK-NEXT: .LBB0_1: # %bb ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: cmpq $1, %rax -; CHECK-NEXT: jg .LBB0_6 -; CHECK-NEXT: .LBB0_5: # %bb16 +; CHECK-NEXT: jg .LBB0_1 +; CHECK-NEXT: .LBB0_2: # %bb16 ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB0_1: +; CHECK-NEXT: .LBB0_3: ; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_2: # %bb10 +; CHECK-NEXT: .LBB0_4: # %bb10 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: testb %dl, %dl -; CHECK-NEXT: je .LBB0_3 -; CHECK-NEXT: # %bb.7: # %bb11 -; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 +; CHECK-NEXT: je .LBB0_6 +; CHECK-NEXT: # %bb.5: # %bb11 +; CHECK-NEXT: # in Loop: Header=BB0_4 Depth=1 ; CHECK-NEXT: testq %rcx, %rcx -; CHECK-NEXT: jns .LBB0_2 -; CHECK-NEXT: jmp .LBB0_5 -; CHECK-NEXT: .LBB0_3: # %bb10 +; CHECK-NEXT: jns .LBB0_4 +; CHECK-NEXT: jmp .LBB0_2 +; CHECK-NEXT: .LBB0_6: # %bb10 ; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: testb %cl, %cl -; CHECK-NEXT: jne .LBB0_5 +; CHECK-NEXT: jne .LBB0_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_4: # %bb12 +; CHECK-NEXT: .LBB0_7: # %bb12 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: cmpq $1, %rax -; CHECK-NEXT: jg .LBB0_4 -; CHECK-NEXT: jmp .LBB0_5 +; CHECK-NEXT: jg .LBB0_7 +; CHECK-NEXT: jmp .LBB0_2 entry: %i = load i32, ptr %arg, align 4 %i2 = sext i32 %i to i64 diff --git a/llvm/test/CodeGen/X86/asm-label.ll b/llvm/test/CodeGen/X86/asm-label.ll index 2d3e7b624d354..c7602edc33fdd 100644 --- a/llvm/test/CodeGen/X86/asm-label.ll +++ b/llvm/test/CodeGen/X86/asm-label.ll @@ -4,8 +4,8 @@ ; we would print the jump, but not the label because it was considered ; a fall through. -; CHECK: jmp LBB0_9 -; CHECK: LBB0_9: ## %cleanup +; CHECK: jmp LBB0_5 +; CHECK: LBB0_5: ## %cleanup ; RUN: llc -filetype=obj -mtriple=x86_64 -O0 -save-temp-labels < %s | llvm-objdump -d - | FileCheck %s --check-prefix=SAVETEMP diff --git a/llvm/test/CodeGen/X86/atomic-bit-test.ll b/llvm/test/CodeGen/X86/atomic-bit-test.ll index b06bef44a5e9e..fd07f33ebc5ec 100644 --- a/llvm/test/CodeGen/X86/atomic-bit-test.ll +++ b/llvm/test/CodeGen/X86/atomic-bit-test.ll @@ -541,20 +541,20 @@ define void @no_and_cmp0_fold() nounwind { ; X86-NEXT: lock btsl $3, v32 ; X86-NEXT: xorl %eax, %eax ; X86-NEXT: testb %al, %al -; X86-NEXT: je .LBB18_1 -; X86-NEXT: # %bb.2: # %if.end +; X86-NEXT: je .LBB18_2 +; X86-NEXT: # %bb.1: # %if.end ; X86-NEXT: retl -; X86-NEXT: .LBB18_1: # %if.then +; X86-NEXT: .LBB18_2: # %if.then ; ; X64-LABEL: no_and_cmp0_fold: ; X64: # %bb.0: # %entry ; X64-NEXT: lock btsl $3, v32(%rip) ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: testb %al, %al -; X64-NEXT: je .LBB18_1 -; X64-NEXT: # %bb.2: # %if.end +; X64-NEXT: je .LBB18_2 +; X64-NEXT: # %bb.1: # %if.end ; X64-NEXT: retq -; X64-NEXT: .LBB18_1: # %if.then +; X64-NEXT: .LBB18_2: # %if.then entry: %0 = atomicrmw or ptr @v32, i32 8 monotonic, align 4 %and = and i32 %0, 8 diff --git a/llvm/test/CodeGen/X86/atomic-flags.ll b/llvm/test/CodeGen/X86/atomic-flags.ll index 317af67deb163..f6b4c52847a33 100644 --- a/llvm/test/CodeGen/X86/atomic-flags.ll +++ b/llvm/test/CodeGen/X86/atomic-flags.ll @@ -12,14 +12,14 @@ define i32 @atomic_and_flags_1(ptr %p, i32 %a, i32 %b) { ; X64-NEXT: # %bb.1: # %L1 ; X64-NEXT: incb (%rdi) ; X64-NEXT: cmpl %edx, %esi -; X64-NEXT: jne .LBB0_2 -; X64-NEXT: # %bb.4: # %L3 +; X64-NEXT: jne .LBB0_4 +; X64-NEXT: # %bb.2: # %L3 ; X64-NEXT: movl $3, %eax ; X64-NEXT: retq ; X64-NEXT: .LBB0_3: # %L2 ; X64-NEXT: movl $2, %eax ; X64-NEXT: retq -; X64-NEXT: .LBB0_2: # %L4 +; X64-NEXT: .LBB0_4: # %L4 ; X64-NEXT: movl $4, %eax ; X64-NEXT: retq ; @@ -33,14 +33,14 @@ define i32 @atomic_and_flags_1(ptr %p, i32 %a, i32 %b) { ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: incb (%edx) ; X86-NEXT: cmpl %eax, %ecx -; X86-NEXT: jne .LBB0_2 -; X86-NEXT: # %bb.4: # %L3 +; X86-NEXT: jne .LBB0_4 +; X86-NEXT: # %bb.2: # %L3 ; X86-NEXT: movl $3, %eax ; X86-NEXT: retl ; X86-NEXT: .LBB0_3: # %L2 ; X86-NEXT: movl $2, %eax ; X86-NEXT: retl -; X86-NEXT: .LBB0_2: # %L4 +; X86-NEXT: .LBB0_4: # %L4 ; X86-NEXT: movl $4, %eax ; X86-NEXT: retl ; Generate flags value, and use it. @@ -78,14 +78,14 @@ define i32 @atomic_and_flags_2(ptr %p, i32 %a, i32 %b) { ; X64-NEXT: # %bb.1: # %L1 ; X64-NEXT: addb $2, (%rdi) ; X64-NEXT: cmpl %edx, %esi -; X64-NEXT: jne .LBB1_2 -; X64-NEXT: # %bb.4: # %L3 +; X64-NEXT: jne .LBB1_4 +; X64-NEXT: # %bb.2: # %L3 ; X64-NEXT: movl $3, %eax ; X64-NEXT: retq ; X64-NEXT: .LBB1_3: # %L2 ; X64-NEXT: movl $2, %eax ; X64-NEXT: retq -; X64-NEXT: .LBB1_2: # %L4 +; X64-NEXT: .LBB1_4: # %L4 ; X64-NEXT: movl $4, %eax ; X64-NEXT: retq ; @@ -99,14 +99,14 @@ define i32 @atomic_and_flags_2(ptr %p, i32 %a, i32 %b) { ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: addb $2, (%edx) ; X86-NEXT: cmpl %eax, %ecx -; X86-NEXT: jne .LBB1_2 -; X86-NEXT: # %bb.4: # %L3 +; X86-NEXT: jne .LBB1_4 +; X86-NEXT: # %bb.2: # %L3 ; X86-NEXT: movl $3, %eax ; X86-NEXT: retl ; X86-NEXT: .LBB1_3: # %L2 ; X86-NEXT: movl $2, %eax ; X86-NEXT: retl -; X86-NEXT: .LBB1_2: # %L4 +; X86-NEXT: .LBB1_4: # %L4 ; X86-NEXT: movl $4, %eax ; X86-NEXT: retl %cmp = icmp eq i32 %a, %b diff --git a/llvm/test/CodeGen/X86/atomic-rm-bit-test-64.ll b/llvm/test/CodeGen/X86/atomic-rm-bit-test-64.ll index 3fe5b70edc718..cf70050111d3e 100644 --- a/llvm/test/CodeGen/X86/atomic-rm-bit-test-64.ll +++ b/llvm/test/CodeGen/X86/atomic-rm-bit-test-64.ll @@ -1103,11 +1103,11 @@ define i64 @atomic_shl1_and_64_gpr_brnz(ptr %v, i64 %c) nounwind { ; CHECK-NEXT: movl %esi, %eax ; CHECK-NEXT: andl $63, %eax ; CHECK-NEXT: lock btrq %rax, (%rdi) -; CHECK-NEXT: jae .LBB40_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jae .LBB40_2 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: movq (%rdi,%rsi,8), %rax ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB40_1: +; CHECK-NEXT: .LBB40_2: ; CHECK-NEXT: movl $123, %eax ; CHECK-NEXT: retq entry: @@ -1146,11 +1146,11 @@ define i64 @atomic_shl2_and_64_gpr_brnz(ptr %v, i64 %c) nounwind { ; CHECK-NEXT: jne .LBB41_1 ; CHECK-NEXT: # %bb.2: # %atomicrmw.end ; CHECK-NEXT: testq %rdx, %rax -; CHECK-NEXT: je .LBB41_3 -; CHECK-NEXT: # %bb.4: # %if.then +; CHECK-NEXT: je .LBB41_4 +; CHECK-NEXT: # %bb.3: # %if.then ; CHECK-NEXT: movq (%rdi,%rcx,8), %rax ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB41_3: +; CHECK-NEXT: .LBB41_4: ; CHECK-NEXT: movl $123, %eax ; CHECK-NEXT: retq entry: @@ -1189,11 +1189,11 @@ define i64 @atomic_shl1_neq_and_64_gpr_brnz(ptr %v, i64 %c) nounwind { ; CHECK-NEXT: leal 1(%rcx), %edx ; CHECK-NEXT: movzbl %dl, %edx ; CHECK-NEXT: btq %rdx, %rax -; CHECK-NEXT: jae .LBB42_3 -; CHECK-NEXT: # %bb.4: # %if.then +; CHECK-NEXT: jae .LBB42_4 +; CHECK-NEXT: # %bb.3: # %if.then ; CHECK-NEXT: movq (%rdi,%rcx,8), %rax ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB42_3: +; CHECK-NEXT: .LBB42_4: ; CHECK-NEXT: movl $123, %eax ; CHECK-NEXT: retq entry: @@ -1221,11 +1221,11 @@ define i64 @atomic_shl1_small_mask_and_64_gpr_brnz(ptr %v, i64 %c) nounwind { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: andl $31, %esi ; CHECK-NEXT: lock btrq %rsi, (%rdi) -; CHECK-NEXT: jae .LBB43_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jae .LBB43_2 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: movq (%rdi,%rsi,8), %rax ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB43_1: +; CHECK-NEXT: .LBB43_2: ; CHECK-NEXT: movl $123, %eax ; CHECK-NEXT: retq entry: @@ -1253,11 +1253,11 @@ define i64 @atomic_shl1_mask0_and_64_gpr_brnz(ptr %v, i64 %c) nounwind { ; CHECK-NEXT: movl %esi, %eax ; CHECK-NEXT: andl $63, %eax ; CHECK-NEXT: lock btrq %rax, (%rdi) -; CHECK-NEXT: jae .LBB44_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jae .LBB44_2 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: movq (%rdi,%rsi,8), %rax ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB44_1: +; CHECK-NEXT: .LBB44_2: ; CHECK-NEXT: movl $123, %eax ; CHECK-NEXT: retq entry: @@ -1286,11 +1286,11 @@ define i64 @atomic_shl1_mask1_and_64_gpr_brnz(ptr %v, i64 %c) nounwind { ; CHECK-NEXT: movl %esi, %eax ; CHECK-NEXT: andl $63, %eax ; CHECK-NEXT: lock btrq %rax, (%rdi) -; CHECK-NEXT: jae .LBB45_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jae .LBB45_2 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: movq (%rdi,%rsi,8), %rax ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB45_1: +; CHECK-NEXT: .LBB45_2: ; CHECK-NEXT: movl $123, %eax ; CHECK-NEXT: retq entry: @@ -1319,11 +1319,11 @@ define i64 @atomic_shl1_mask01_and_64_gpr_brnz(ptr %v, i64 %c) nounwind { ; CHECK-NEXT: movl %esi, %eax ; CHECK-NEXT: andl $63, %eax ; CHECK-NEXT: lock btrq %rax, (%rdi) -; CHECK-NEXT: jae .LBB46_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jae .LBB46_2 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: movq (%rdi,%rsi,8), %rax ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB46_1: +; CHECK-NEXT: .LBB46_2: ; CHECK-NEXT: movl $123, %eax ; CHECK-NEXT: retq entry: @@ -1363,11 +1363,11 @@ define i64 @atomic_blsi_and_64_gpr_brnz(ptr %v, i64 %c) nounwind { ; CHECK-NEXT: jne .LBB47_1 ; CHECK-NEXT: # %bb.2: # %atomicrmw.end ; CHECK-NEXT: testq %rcx, %rax -; CHECK-NEXT: je .LBB47_3 -; CHECK-NEXT: # %bb.4: # %if.then +; CHECK-NEXT: je .LBB47_4 +; CHECK-NEXT: # %bb.3: # %if.then ; CHECK-NEXT: movq (%rdi,%rsi,8), %rax ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB47_3: +; CHECK-NEXT: .LBB47_4: ; CHECK-NEXT: movl $123, %eax ; CHECK-NEXT: retq entry: @@ -1393,11 +1393,11 @@ define i64 @atomic_shl1_xor_64_const_br(ptr %v) nounwind { ; CHECK-LABEL: atomic_shl1_xor_64_const_br: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lock btcq $4, (%rdi) -; CHECK-NEXT: jae .LBB48_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jae .LBB48_2 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: movq 32(%rdi), %rax ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB48_1: +; CHECK-NEXT: .LBB48_2: ; CHECK-NEXT: movl $123, %eax ; CHECK-NEXT: retq entry: @@ -1457,10 +1457,10 @@ define i64 @atomic_shl1_xor_64_const_brz(ptr %v) nounwind { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lock btcq $4, (%rdi) ; CHECK-NEXT: movl $123, %eax -; CHECK-NEXT: jae .LBB50_1 -; CHECK-NEXT: # %bb.2: # %return +; CHECK-NEXT: jae .LBB50_2 +; CHECK-NEXT: # %bb.1: # %return ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB50_1: # %if.then +; CHECK-NEXT: .LBB50_2: # %if.then ; CHECK-NEXT: movq 32(%rdi), %rax ; CHECK-NEXT: retq entry: @@ -1519,11 +1519,11 @@ define i64 @atomic_shl1_xor_64_const_brnz(ptr %v) nounwind { ; CHECK-LABEL: atomic_shl1_xor_64_const_brnz: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lock btcq $4, (%rdi) -; CHECK-NEXT: jae .LBB52_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: jae .LBB52_2 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: movq 32(%rdi), %rax ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB52_1: +; CHECK-NEXT: .LBB52_2: ; CHECK-NEXT: movl $123, %eax ; CHECK-NEXT: retq entry: diff --git a/llvm/test/CodeGen/X86/atomic-rm-bit-test.ll b/llvm/test/CodeGen/X86/atomic-rm-bit-test.ll index 71887e369bd18..92fe8cc9f3564 100644 --- a/llvm/test/CodeGen/X86/atomic-rm-bit-test.ll +++ b/llvm/test/CodeGen/X86/atomic-rm-bit-test.ll @@ -351,13 +351,13 @@ define zeroext i8 @atomic_shl1_and_8_gpr_brnz(ptr %v, i8 zeroext %c) nounwind { ; X86-NEXT: # %bb.2: # %atomicrmw.end ; X86-NEXT: movzbl %al, %eax ; X86-NEXT: testl %eax, %ebx -; X86-NEXT: je .LBB6_3 -; X86-NEXT: # %bb.4: # %if.then +; X86-NEXT: je .LBB6_4 +; X86-NEXT: # %bb.3: # %if.then ; X86-NEXT: movzbl %cl, %eax ; X86-NEXT: movzbl (%edx,%eax), %eax ; X86-NEXT: popl %ebx ; X86-NEXT: retl -; X86-NEXT: .LBB6_3: +; X86-NEXT: .LBB6_4: ; X86-NEXT: movb $123, %al ; X86-NEXT: popl %ebx ; X86-NEXT: retl @@ -380,12 +380,12 @@ define zeroext i8 @atomic_shl1_and_8_gpr_brnz(ptr %v, i8 zeroext %c) nounwind { ; X64-NEXT: # %bb.2: # %atomicrmw.end ; X64-NEXT: movzbl %al, %eax ; X64-NEXT: testl %eax, %edx -; X64-NEXT: je .LBB6_3 -; X64-NEXT: # %bb.4: # %if.then +; X64-NEXT: je .LBB6_4 +; X64-NEXT: # %bb.3: # %if.then ; X64-NEXT: movzbl %cl, %eax ; X64-NEXT: movzbl (%rdi,%rax), %eax ; X64-NEXT: retq -; X64-NEXT: .LBB6_3: +; X64-NEXT: .LBB6_4: ; X64-NEXT: movb $123, %al ; X64-NEXT: retq entry: @@ -430,12 +430,12 @@ define zeroext i8 @atomic_shl1_mask0_and_8_gpr_brnz(ptr %v, i8 zeroext %c) nounw ; X86-NEXT: movzbl %al, %esi ; X86-NEXT: movzbl %cl, %eax ; X86-NEXT: btl %eax, %esi -; X86-NEXT: jae .LBB7_3 -; X86-NEXT: # %bb.4: # %if.then +; X86-NEXT: jae .LBB7_4 +; X86-NEXT: # %bb.3: # %if.then ; X86-NEXT: movzbl (%edx,%eax), %eax ; X86-NEXT: popl %esi ; X86-NEXT: retl -; X86-NEXT: .LBB7_3: +; X86-NEXT: .LBB7_4: ; X86-NEXT: movb $123, %al ; X86-NEXT: popl %esi ; X86-NEXT: retl @@ -457,11 +457,11 @@ define zeroext i8 @atomic_shl1_mask0_and_8_gpr_brnz(ptr %v, i8 zeroext %c) nounw ; X64-NEXT: movzbl %al, %edx ; X64-NEXT: movzbl %cl, %eax ; X64-NEXT: btl %eax, %edx -; X64-NEXT: jae .LBB7_3 -; X64-NEXT: # %bb.4: # %if.then +; X64-NEXT: jae .LBB7_4 +; X64-NEXT: # %bb.3: # %if.then ; X64-NEXT: movzbl (%rdi,%rax), %eax ; X64-NEXT: retq -; X64-NEXT: .LBB7_3: +; X64-NEXT: .LBB7_4: ; X64-NEXT: movb $123, %al ; X64-NEXT: retq entry: @@ -510,13 +510,13 @@ define zeroext i8 @atomic_shl1_mask01_and_8_gpr_brnz(ptr %v, i8 zeroext %c) noun ; X86-NEXT: # %bb.2: # %atomicrmw.end ; X86-NEXT: movzbl %al, %ecx ; X86-NEXT: testl %ecx, %ebx -; X86-NEXT: je .LBB8_3 -; X86-NEXT: # %bb.4: # %if.then +; X86-NEXT: je .LBB8_4 +; X86-NEXT: # %bb.3: # %if.then ; X86-NEXT: movzbl %ah, %eax ; X86-NEXT: movzbl (%edx,%eax), %eax ; X86-NEXT: popl %ebx ; X86-NEXT: retl -; X86-NEXT: .LBB8_3: +; X86-NEXT: .LBB8_4: ; X86-NEXT: movb $123, %al ; X86-NEXT: popl %ebx ; X86-NEXT: retl @@ -540,12 +540,12 @@ define zeroext i8 @atomic_shl1_mask01_and_8_gpr_brnz(ptr %v, i8 zeroext %c) noun ; X64-NEXT: # %bb.2: # %atomicrmw.end ; X64-NEXT: movzbl %al, %eax ; X64-NEXT: testl %eax, %edx -; X64-NEXT: je .LBB8_3 -; X64-NEXT: # %bb.4: # %if.then +; X64-NEXT: je .LBB8_4 +; X64-NEXT: # %bb.3: # %if.then ; X64-NEXT: movzbl %sil, %eax ; X64-NEXT: movzbl (%rdi,%rax), %eax ; X64-NEXT: retq -; X64-NEXT: .LBB8_3: +; X64-NEXT: .LBB8_4: ; X64-NEXT: movb $123, %al ; X64-NEXT: retq entry: @@ -1838,10 +1838,10 @@ define zeroext i16 @atomic_shl1_xor_16_gpr_brz(ptr %v, i16 zeroext %c) nounwind ; X64-NEXT: movzwl %ax, %esi ; X64-NEXT: movw $123, %ax ; X64-NEXT: testl %esi, %edx -; X64-NEXT: je .LBB30_3 -; X64-NEXT: # %bb.4: # %return +; X64-NEXT: je .LBB30_4 +; X64-NEXT: # %bb.3: # %return ; X64-NEXT: retq -; X64-NEXT: .LBB30_3: # %if.then +; X64-NEXT: .LBB30_4: # %if.then ; X64-NEXT: movzwl %cx, %eax ; X64-NEXT: movzwl (%rdi,%rax,2), %eax ; X64-NEXT: retq @@ -1921,10 +1921,10 @@ define zeroext i16 @atomic_shl1_small_mask_xor_16_gpr_brz(ptr %v, i16 zeroext %c ; X64-NEXT: movzwl %ax, %edx ; X64-NEXT: movw $123, %ax ; X64-NEXT: btl %ecx, %edx -; X64-NEXT: jae .LBB31_3 -; X64-NEXT: # %bb.4: # %return +; X64-NEXT: jae .LBB31_4 +; X64-NEXT: # %bb.3: # %return ; X64-NEXT: retq -; X64-NEXT: .LBB31_3: # %if.then +; X64-NEXT: .LBB31_4: # %if.then ; X64-NEXT: movzwl %cx, %eax ; X64-NEXT: movzwl (%rdi,%rax,2), %eax ; X64-NEXT: retq @@ -2004,10 +2004,10 @@ define zeroext i16 @atomic_shl1_mask0_xor_16_gpr_brz(ptr %v, i16 zeroext %c) nou ; X64-NEXT: movzwl %ax, %ecx ; X64-NEXT: movw $123, %ax ; X64-NEXT: btl %esi, %ecx -; X64-NEXT: jae .LBB32_3 -; X64-NEXT: # %bb.4: # %return +; X64-NEXT: jae .LBB32_4 +; X64-NEXT: # %bb.3: # %return ; X64-NEXT: retq -; X64-NEXT: .LBB32_3: # %if.then +; X64-NEXT: .LBB32_4: # %if.then ; X64-NEXT: movzwl %si, %eax ; X64-NEXT: movzwl (%rdi,%rax,2), %eax ; X64-NEXT: retq @@ -2088,10 +2088,10 @@ define zeroext i16 @atomic_shl1_mask1_xor_16_gpr_brz(ptr %v, i16 zeroext %c) nou ; X64-NEXT: andl $15, %esi ; X64-NEXT: movw $123, %ax ; X64-NEXT: btl %esi, %edx -; X64-NEXT: jae .LBB33_3 -; X64-NEXT: # %bb.4: # %return +; X64-NEXT: jae .LBB33_4 +; X64-NEXT: # %bb.3: # %return ; X64-NEXT: retq -; X64-NEXT: .LBB33_3: # %if.then +; X64-NEXT: .LBB33_4: # %if.then ; X64-NEXT: movzwl %cx, %eax ; X64-NEXT: movzwl (%rdi,%rax,2), %eax ; X64-NEXT: retq @@ -2175,10 +2175,10 @@ define zeroext i16 @atomic_shl1_mask01_xor_16_gpr_brz(ptr %v, i16 zeroext %c) no ; X64-NEXT: movzwl %ax, %ecx ; X64-NEXT: movw $123, %ax ; X64-NEXT: testl %ecx, %esi -; X64-NEXT: je .LBB34_3 -; X64-NEXT: # %bb.4: # %return +; X64-NEXT: je .LBB34_4 +; X64-NEXT: # %bb.3: # %return ; X64-NEXT: retq -; X64-NEXT: .LBB34_3: # %if.then +; X64-NEXT: .LBB34_4: # %if.then ; X64-NEXT: movzwl %dx, %eax ; X64-NEXT: movzwl (%rdi,%rax,2), %eax ; X64-NEXT: retq @@ -2256,10 +2256,10 @@ define zeroext i16 @atomic_blsi_xor_16_gpr_brz(ptr %v, i16 zeroext %c) nounwind ; X64-NEXT: movzwl %ax, %edx ; X64-NEXT: movw $123, %ax ; X64-NEXT: testl %edx, %ecx -; X64-NEXT: je .LBB35_3 -; X64-NEXT: # %bb.4: # %return +; X64-NEXT: je .LBB35_4 +; X64-NEXT: # %bb.3: # %return ; X64-NEXT: retq -; X64-NEXT: .LBB35_3: # %if.then +; X64-NEXT: .LBB35_4: # %if.then ; X64-NEXT: movzwl %si, %eax ; X64-NEXT: movzwl (%rdi,%rax,2), %eax ; X64-NEXT: retq @@ -3037,12 +3037,12 @@ define zeroext i16 @atomic_shl1_and_16_gpr_brnz(ptr %v, i16 zeroext %c) nounwind ; X86-NEXT: # %bb.2: # %atomicrmw.end ; X86-NEXT: movzwl %ax, %eax ; X86-NEXT: testl %eax, %esi -; X86-NEXT: je .LBB48_3 -; X86-NEXT: # %bb.4: # %if.then +; X86-NEXT: je .LBB48_4 +; X86-NEXT: # %bb.3: # %if.then ; X86-NEXT: movzwl %cx, %eax ; X86-NEXT: movzwl (%edx,%eax,2), %eax ; X86-NEXT: jmp .LBB48_5 -; X86-NEXT: .LBB48_3: +; X86-NEXT: .LBB48_4: ; X86-NEXT: movw $123, %ax ; X86-NEXT: .LBB48_5: # %return ; X86-NEXT: popl %esi @@ -3070,12 +3070,12 @@ define zeroext i16 @atomic_shl1_and_16_gpr_brnz(ptr %v, i16 zeroext %c) nounwind ; X64-NEXT: # %bb.2: # %atomicrmw.end ; X64-NEXT: movzwl %ax, %eax ; X64-NEXT: testl %eax, %edx -; X64-NEXT: je .LBB48_3 -; X64-NEXT: # %bb.4: # %if.then +; X64-NEXT: je .LBB48_4 +; X64-NEXT: # %bb.3: # %if.then ; X64-NEXT: movzwl %cx, %eax ; X64-NEXT: movzwl (%rdi,%rax,2), %eax ; X64-NEXT: retq -; X64-NEXT: .LBB48_3: +; X64-NEXT: .LBB48_4: ; X64-NEXT: movw $123, %ax ; X64-NEXT: retq entry: @@ -3123,12 +3123,12 @@ define zeroext i16 @atomic_shl1_small_mask_and_16_gpr_brnz(ptr %v, i16 zeroext % ; X86-NEXT: # %bb.2: # %atomicrmw.end ; X86-NEXT: movzwl %ax, %eax ; X86-NEXT: btl %ecx, %eax -; X86-NEXT: jae .LBB49_3 -; X86-NEXT: # %bb.4: # %if.then +; X86-NEXT: jae .LBB49_4 +; X86-NEXT: # %bb.3: # %if.then ; X86-NEXT: movzwl %cx, %eax ; X86-NEXT: movzwl (%edx,%eax,2), %eax ; X86-NEXT: jmp .LBB49_5 -; X86-NEXT: .LBB49_3: +; X86-NEXT: .LBB49_4: ; X86-NEXT: movw $123, %ax ; X86-NEXT: .LBB49_5: # %return ; X86-NEXT: popl %esi @@ -3154,12 +3154,12 @@ define zeroext i16 @atomic_shl1_small_mask_and_16_gpr_brnz(ptr %v, i16 zeroext % ; X64-NEXT: # %bb.2: # %atomicrmw.end ; X64-NEXT: movzwl %ax, %eax ; X64-NEXT: btl %ecx, %eax -; X64-NEXT: jae .LBB49_3 -; X64-NEXT: # %bb.4: # %if.then +; X64-NEXT: jae .LBB49_4 +; X64-NEXT: # %bb.3: # %if.then ; X64-NEXT: movzwl %cx, %eax ; X64-NEXT: movzwl (%rdi,%rax,2), %eax ; X64-NEXT: retq -; X64-NEXT: .LBB49_3: +; X64-NEXT: .LBB49_4: ; X64-NEXT: movw $123, %ax ; X64-NEXT: retq entry: @@ -3207,12 +3207,12 @@ define zeroext i16 @atomic_shl1_mask0_and_16_gpr_brnz(ptr %v, i16 zeroext %c) no ; X86-NEXT: # %bb.2: # %atomicrmw.end ; X86-NEXT: movzwl %ax, %eax ; X86-NEXT: btl %ecx, %eax -; X86-NEXT: jae .LBB50_3 -; X86-NEXT: # %bb.4: # %if.then +; X86-NEXT: jae .LBB50_4 +; X86-NEXT: # %bb.3: # %if.then ; X86-NEXT: movzwl %cx, %eax ; X86-NEXT: movzwl (%edx,%eax,2), %eax ; X86-NEXT: jmp .LBB50_5 -; X86-NEXT: .LBB50_3: +; X86-NEXT: .LBB50_4: ; X86-NEXT: movw $123, %ax ; X86-NEXT: .LBB50_5: # %return ; X86-NEXT: popl %esi @@ -3237,12 +3237,12 @@ define zeroext i16 @atomic_shl1_mask0_and_16_gpr_brnz(ptr %v, i16 zeroext %c) no ; X64-NEXT: # %bb.2: # %atomicrmw.end ; X64-NEXT: movzwl %ax, %eax ; X64-NEXT: btl %ecx, %eax -; X64-NEXT: jae .LBB50_3 -; X64-NEXT: # %bb.4: # %if.then +; X64-NEXT: jae .LBB50_4 +; X64-NEXT: # %bb.3: # %if.then ; X64-NEXT: movzwl %cx, %eax ; X64-NEXT: movzwl (%rdi,%rax,2), %eax ; X64-NEXT: retq -; X64-NEXT: .LBB50_3: +; X64-NEXT: .LBB50_4: ; X64-NEXT: movw $123, %ax ; X64-NEXT: retq entry: @@ -3292,12 +3292,12 @@ define zeroext i16 @atomic_shl1_mask1_and_16_gpr_brnz(ptr %v, i16 zeroext %c) no ; X86-NEXT: movl %ecx, %esi ; X86-NEXT: andl $15, %esi ; X86-NEXT: btl %esi, %eax -; X86-NEXT: jae .LBB51_3 -; X86-NEXT: # %bb.4: # %if.then +; X86-NEXT: jae .LBB51_4 +; X86-NEXT: # %bb.3: # %if.then ; X86-NEXT: movzwl %cx, %eax ; X86-NEXT: movzwl (%edx,%eax,2), %eax ; X86-NEXT: jmp .LBB51_5 -; X86-NEXT: .LBB51_3: +; X86-NEXT: .LBB51_4: ; X86-NEXT: movw $123, %ax ; X86-NEXT: .LBB51_5: # %return ; X86-NEXT: popl %esi @@ -3324,12 +3324,12 @@ define zeroext i16 @atomic_shl1_mask1_and_16_gpr_brnz(ptr %v, i16 zeroext %c) no ; X64-NEXT: movl %ecx, %edx ; X64-NEXT: andl $15, %edx ; X64-NEXT: btl %edx, %eax -; X64-NEXT: jae .LBB51_3 -; X64-NEXT: # %bb.4: # %if.then +; X64-NEXT: jae .LBB51_4 +; X64-NEXT: # %bb.3: # %if.then ; X64-NEXT: movzwl %cx, %eax ; X64-NEXT: movzwl (%rdi,%rax,2), %eax ; X64-NEXT: retq -; X64-NEXT: .LBB51_3: +; X64-NEXT: .LBB51_4: ; X64-NEXT: movw $123, %ax ; X64-NEXT: retq entry: @@ -3384,12 +3384,12 @@ define zeroext i16 @atomic_shl1_mask01_and_16_gpr_brnz(ptr %v, i16 zeroext %c) n ; X86-NEXT: # %bb.2: # %atomicrmw.end ; X86-NEXT: movzwl %ax, %eax ; X86-NEXT: testl %eax, %esi -; X86-NEXT: je .LBB52_3 -; X86-NEXT: # %bb.4: # %if.then +; X86-NEXT: je .LBB52_4 +; X86-NEXT: # %bb.3: # %if.then ; X86-NEXT: movzwl %bx, %eax ; X86-NEXT: movzwl (%edx,%eax,2), %eax ; X86-NEXT: jmp .LBB52_5 -; X86-NEXT: .LBB52_3: +; X86-NEXT: .LBB52_4: ; X86-NEXT: movw $123, %ax ; X86-NEXT: .LBB52_5: # %return ; X86-NEXT: popl %esi @@ -3420,12 +3420,12 @@ define zeroext i16 @atomic_shl1_mask01_and_16_gpr_brnz(ptr %v, i16 zeroext %c) n ; X64-NEXT: # %bb.2: # %atomicrmw.end ; X64-NEXT: movzwl %ax, %eax ; X64-NEXT: testl %eax, %esi -; X64-NEXT: je .LBB52_3 -; X64-NEXT: # %bb.4: # %if.then +; X64-NEXT: je .LBB52_4 +; X64-NEXT: # %bb.3: # %if.then ; X64-NEXT: movzwl %dx, %eax ; X64-NEXT: movzwl (%rdi,%rax,2), %eax ; X64-NEXT: retq -; X64-NEXT: .LBB52_3: +; X64-NEXT: .LBB52_4: ; X64-NEXT: movw $123, %ax ; X64-NEXT: retq entry: @@ -3477,12 +3477,12 @@ define zeroext i16 @atomic_blsi_and_16_gpr_brnz(ptr %v, i16 zeroext %c) nounwind ; X86-NEXT: # %bb.2: # %atomicrmw.end ; X86-NEXT: movzwl %ax, %eax ; X86-NEXT: testl %eax, %esi -; X86-NEXT: je .LBB53_3 -; X86-NEXT: # %bb.4: # %if.then +; X86-NEXT: je .LBB53_4 +; X86-NEXT: # %bb.3: # %if.then ; X86-NEXT: movzwl %cx, %eax ; X86-NEXT: movzwl (%edx,%eax,2), %eax ; X86-NEXT: jmp .LBB53_5 -; X86-NEXT: .LBB53_3: +; X86-NEXT: .LBB53_4: ; X86-NEXT: movw $123, %ax ; X86-NEXT: .LBB53_5: # %return ; X86-NEXT: popl %esi @@ -3510,12 +3510,12 @@ define zeroext i16 @atomic_blsi_and_16_gpr_brnz(ptr %v, i16 zeroext %c) nounwind ; X64-NEXT: # %bb.2: # %atomicrmw.end ; X64-NEXT: movzwl %ax, %eax ; X64-NEXT: testl %eax, %ecx -; X64-NEXT: je .LBB53_3 -; X64-NEXT: # %bb.4: # %if.then +; X64-NEXT: je .LBB53_4 +; X64-NEXT: # %bb.3: # %if.then ; X64-NEXT: movzwl %si, %eax ; X64-NEXT: movzwl (%rdi,%rax,2), %eax ; X64-NEXT: retq -; X64-NEXT: .LBB53_3: +; X64-NEXT: .LBB53_4: ; X64-NEXT: movw $123, %ax ; X64-NEXT: retq entry: @@ -3615,22 +3615,22 @@ define zeroext i16 @atomic_shl1_or_16_const_brnz(ptr %v) nounwind { ; X86: # %bb.0: # %entry ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: lock btsw $4, (%eax) -; X86-NEXT: jae .LBB56_1 -; X86-NEXT: # %bb.2: # %if.then +; X86-NEXT: jae .LBB56_2 +; X86-NEXT: # %bb.1: # %if.then ; X86-NEXT: movzwl 8(%eax), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB56_1: +; X86-NEXT: .LBB56_2: ; X86-NEXT: movw $123, %ax ; X86-NEXT: retl ; ; X64-LABEL: atomic_shl1_or_16_const_brnz: ; X64: # %bb.0: # %entry ; X64-NEXT: lock btsw $4, (%rdi) -; X64-NEXT: jae .LBB56_1 -; X64-NEXT: # %bb.2: # %if.then +; X64-NEXT: jae .LBB56_2 +; X64-NEXT: # %bb.1: # %if.then ; X64-NEXT: movzwl 8(%rdi), %eax ; X64-NEXT: retq -; X64-NEXT: .LBB56_1: +; X64-NEXT: .LBB56_2: ; X64-NEXT: movw $123, %ax ; X64-NEXT: retq entry: @@ -3727,10 +3727,10 @@ define zeroext i16 @atomic_shl1_and_16_const_brz(ptr %v) nounwind { ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: lock btrw $4, (%ecx) ; X86-NEXT: movw $123, %ax -; X86-NEXT: jae .LBB59_1 -; X86-NEXT: # %bb.2: # %return +; X86-NEXT: jae .LBB59_2 +; X86-NEXT: # %bb.1: # %return ; X86-NEXT: retl -; X86-NEXT: .LBB59_1: # %if.then +; X86-NEXT: .LBB59_2: # %if.then ; X86-NEXT: movzwl 8(%ecx), %eax ; X86-NEXT: retl ; @@ -3738,10 +3738,10 @@ define zeroext i16 @atomic_shl1_and_16_const_brz(ptr %v) nounwind { ; X64: # %bb.0: # %entry ; X64-NEXT: lock btrw $4, (%rdi) ; X64-NEXT: movw $123, %ax -; X64-NEXT: jae .LBB59_1 -; X64-NEXT: # %bb.2: # %return +; X64-NEXT: jae .LBB59_2 +; X64-NEXT: # %bb.1: # %return ; X64-NEXT: retq -; X64-NEXT: .LBB59_1: # %if.then +; X64-NEXT: .LBB59_2: # %if.then ; X64-NEXT: movzwl 8(%rdi), %eax ; X64-NEXT: retq entry: @@ -4629,11 +4629,11 @@ define i32 @atomic_shl1_or_32_gpr_br(ptr %v, i32 %c) nounwind { ; X86-NEXT: movl %eax, %edx ; X86-NEXT: andl $31, %edx ; X86-NEXT: lock btsl %edx, (%ecx) -; X86-NEXT: jae .LBB78_1 -; X86-NEXT: # %bb.2: # %if.then +; X86-NEXT: jae .LBB78_2 +; X86-NEXT: # %bb.1: # %if.then ; X86-NEXT: movl (%ecx,%eax,4), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB78_1: +; X86-NEXT: .LBB78_2: ; X86-NEXT: movl $123, %eax ; X86-NEXT: retl ; @@ -4642,12 +4642,12 @@ define i32 @atomic_shl1_or_32_gpr_br(ptr %v, i32 %c) nounwind { ; X64-NEXT: movl %esi, %eax ; X64-NEXT: andl $31, %eax ; X64-NEXT: lock btsl %eax, (%rdi) -; X64-NEXT: jae .LBB78_1 -; X64-NEXT: # %bb.2: # %if.then +; X64-NEXT: jae .LBB78_2 +; X64-NEXT: # %bb.1: # %if.then ; X64-NEXT: movl %esi, %eax ; X64-NEXT: movl (%rdi,%rax,4), %eax ; X64-NEXT: retq -; X64-NEXT: .LBB78_1: +; X64-NEXT: .LBB78_2: ; X64-NEXT: movl $123, %eax ; X64-NEXT: retq entry: @@ -4675,11 +4675,11 @@ define i32 @atomic_shl1_small_mask_or_32_gpr_br(ptr %v, i32 %c) nounwind { ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: andl $15, %ecx ; X86-NEXT: lock btsl %ecx, (%eax) -; X86-NEXT: jae .LBB79_1 -; X86-NEXT: # %bb.2: # %if.then +; X86-NEXT: jae .LBB79_2 +; X86-NEXT: # %bb.1: # %if.then ; X86-NEXT: movl (%eax,%ecx,4), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB79_1: +; X86-NEXT: .LBB79_2: ; X86-NEXT: movl $123, %eax ; X86-NEXT: retl ; @@ -4687,12 +4687,12 @@ define i32 @atomic_shl1_small_mask_or_32_gpr_br(ptr %v, i32 %c) nounwind { ; X64: # %bb.0: # %entry ; X64-NEXT: andl $15, %esi ; X64-NEXT: lock btsl %esi, (%rdi) -; X64-NEXT: jae .LBB79_1 -; X64-NEXT: # %bb.2: # %if.then +; X64-NEXT: jae .LBB79_2 +; X64-NEXT: # %bb.1: # %if.then ; X64-NEXT: movl %esi, %eax ; X64-NEXT: movl (%rdi,%rax,4), %eax ; X64-NEXT: retq -; X64-NEXT: .LBB79_1: +; X64-NEXT: .LBB79_2: ; X64-NEXT: movl $123, %eax ; X64-NEXT: retq entry: @@ -4722,11 +4722,11 @@ define i32 @atomic_shl1_mask0_or_32_gpr_br(ptr %v, i32 %c) nounwind { ; X86-NEXT: movl %eax, %edx ; X86-NEXT: andl $31, %edx ; X86-NEXT: lock btsl %edx, (%ecx) -; X86-NEXT: jae .LBB80_1 -; X86-NEXT: # %bb.2: # %if.then +; X86-NEXT: jae .LBB80_2 +; X86-NEXT: # %bb.1: # %if.then ; X86-NEXT: movl (%ecx,%eax,4), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB80_1: +; X86-NEXT: .LBB80_2: ; X86-NEXT: movl $123, %eax ; X86-NEXT: retl ; @@ -4735,12 +4735,12 @@ define i32 @atomic_shl1_mask0_or_32_gpr_br(ptr %v, i32 %c) nounwind { ; X64-NEXT: movl %esi, %eax ; X64-NEXT: andl $31, %eax ; X64-NEXT: lock btsl %eax, (%rdi) -; X64-NEXT: jae .LBB80_1 -; X64-NEXT: # %bb.2: # %if.then +; X64-NEXT: jae .LBB80_2 +; X64-NEXT: # %bb.1: # %if.then ; X64-NEXT: movl %esi, %eax ; X64-NEXT: movl (%rdi,%rax,4), %eax ; X64-NEXT: retq -; X64-NEXT: .LBB80_1: +; X64-NEXT: .LBB80_2: ; X64-NEXT: movl $123, %eax ; X64-NEXT: retq entry: @@ -4771,11 +4771,11 @@ define i32 @atomic_shl1_mask1_or_32_gpr_br(ptr %v, i32 %c) nounwind { ; X86-NEXT: movl %eax, %edx ; X86-NEXT: andl $31, %edx ; X86-NEXT: lock btsl %edx, (%ecx) -; X86-NEXT: jae .LBB81_1 -; X86-NEXT: # %bb.2: # %if.then +; X86-NEXT: jae .LBB81_2 +; X86-NEXT: # %bb.1: # %if.then ; X86-NEXT: movl (%ecx,%eax,4), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB81_1: +; X86-NEXT: .LBB81_2: ; X86-NEXT: movl $123, %eax ; X86-NEXT: retl ; @@ -4784,12 +4784,12 @@ define i32 @atomic_shl1_mask1_or_32_gpr_br(ptr %v, i32 %c) nounwind { ; X64-NEXT: movl %esi, %eax ; X64-NEXT: andl $31, %eax ; X64-NEXT: lock btsl %eax, (%rdi) -; X64-NEXT: jae .LBB81_1 -; X64-NEXT: # %bb.2: # %if.then +; X64-NEXT: jae .LBB81_2 +; X64-NEXT: # %bb.1: # %if.then ; X64-NEXT: movl %esi, %eax ; X64-NEXT: movl (%rdi,%rax,4), %eax ; X64-NEXT: retq -; X64-NEXT: .LBB81_1: +; X64-NEXT: .LBB81_2: ; X64-NEXT: movl $123, %eax ; X64-NEXT: retq entry: @@ -4820,11 +4820,11 @@ define i32 @atomic_shl1_mask01_or_32_gpr_br(ptr %v, i32 %c) nounwind { ; X86-NEXT: movl %eax, %edx ; X86-NEXT: andl $31, %edx ; X86-NEXT: lock btsl %edx, (%ecx) -; X86-NEXT: jae .LBB82_1 -; X86-NEXT: # %bb.2: # %if.then +; X86-NEXT: jae .LBB82_2 +; X86-NEXT: # %bb.1: # %if.then ; X86-NEXT: movl (%ecx,%eax,4), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB82_1: +; X86-NEXT: .LBB82_2: ; X86-NEXT: movl $123, %eax ; X86-NEXT: retl ; @@ -4833,12 +4833,12 @@ define i32 @atomic_shl1_mask01_or_32_gpr_br(ptr %v, i32 %c) nounwind { ; X64-NEXT: movl %esi, %eax ; X64-NEXT: andl $31, %eax ; X64-NEXT: lock btsl %eax, (%rdi) -; X64-NEXT: jae .LBB82_1 -; X64-NEXT: # %bb.2: # %if.then +; X64-NEXT: jae .LBB82_2 +; X64-NEXT: # %bb.1: # %if.then ; X64-NEXT: movl %esi, %eax ; X64-NEXT: movl (%rdi,%rax,4), %eax ; X64-NEXT: retq -; X64-NEXT: .LBB82_1: +; X64-NEXT: .LBB82_2: ; X64-NEXT: movl $123, %eax ; X64-NEXT: retq entry: @@ -4880,11 +4880,11 @@ define i32 @atomic_blsi_or_32_gpr_br(ptr %v, i32 %c) nounwind { ; X86-NEXT: jne .LBB83_1 ; X86-NEXT: # %bb.2: # %atomicrmw.end ; X86-NEXT: testl %esi, %eax -; X86-NEXT: je .LBB83_3 -; X86-NEXT: # %bb.4: # %if.then +; X86-NEXT: je .LBB83_4 +; X86-NEXT: # %bb.3: # %if.then ; X86-NEXT: movl (%edx,%ecx,4), %eax ; X86-NEXT: jmp .LBB83_5 -; X86-NEXT: .LBB83_3: +; X86-NEXT: .LBB83_4: ; X86-NEXT: movl $123, %eax ; X86-NEXT: .LBB83_5: # %return ; X86-NEXT: popl %esi @@ -4906,12 +4906,12 @@ define i32 @atomic_blsi_or_32_gpr_br(ptr %v, i32 %c) nounwind { ; X64-NEXT: jne .LBB83_1 ; X64-NEXT: # %bb.2: # %atomicrmw.end ; X64-NEXT: testl %ecx, %eax -; X64-NEXT: je .LBB83_3 -; X64-NEXT: # %bb.4: # %if.then +; X64-NEXT: je .LBB83_4 +; X64-NEXT: # %bb.3: # %if.then ; X64-NEXT: movl %esi, %eax ; X64-NEXT: movl (%rdi,%rax,4), %eax ; X64-NEXT: retq -; X64-NEXT: .LBB83_3: +; X64-NEXT: .LBB83_4: ; X64-NEXT: movl $123, %eax ; X64-NEXT: retq entry: @@ -4942,10 +4942,10 @@ define i32 @atomic_shl1_or_32_gpr_brz(ptr %v, i32 %c) nounwind { ; X86-NEXT: andl $31, %eax ; X86-NEXT: lock btsl %eax, (%edx) ; X86-NEXT: movl $123, %eax -; X86-NEXT: jae .LBB84_1 -; X86-NEXT: # %bb.2: # %return +; X86-NEXT: jae .LBB84_2 +; X86-NEXT: # %bb.1: # %return ; X86-NEXT: retl -; X86-NEXT: .LBB84_1: # %if.then +; X86-NEXT: .LBB84_2: # %if.then ; X86-NEXT: movl (%edx,%ecx,4), %eax ; X86-NEXT: retl ; @@ -4955,10 +4955,10 @@ define i32 @atomic_shl1_or_32_gpr_brz(ptr %v, i32 %c) nounwind { ; X64-NEXT: andl $31, %eax ; X64-NEXT: lock btsl %eax, (%rdi) ; X64-NEXT: movl $123, %eax -; X64-NEXT: jae .LBB84_1 -; X64-NEXT: # %bb.2: # %return +; X64-NEXT: jae .LBB84_2 +; X64-NEXT: # %bb.1: # %return ; X64-NEXT: retq -; X64-NEXT: .LBB84_1: # %if.then +; X64-NEXT: .LBB84_2: # %if.then ; X64-NEXT: movl %esi, %eax ; X64-NEXT: movl (%rdi,%rax,4), %eax ; X64-NEXT: retq @@ -4988,10 +4988,10 @@ define i32 @atomic_shl1_small_mask_or_32_gpr_brz(ptr %v, i32 %c) nounwind { ; X86-NEXT: andl $15, %edx ; X86-NEXT: lock btsl %edx, (%ecx) ; X86-NEXT: movl $123, %eax -; X86-NEXT: jae .LBB85_1 -; X86-NEXT: # %bb.2: # %return +; X86-NEXT: jae .LBB85_2 +; X86-NEXT: # %bb.1: # %return ; X86-NEXT: retl -; X86-NEXT: .LBB85_1: # %if.then +; X86-NEXT: .LBB85_2: # %if.then ; X86-NEXT: movl (%ecx,%edx,4), %eax ; X86-NEXT: retl ; @@ -5000,10 +5000,10 @@ define i32 @atomic_shl1_small_mask_or_32_gpr_brz(ptr %v, i32 %c) nounwind { ; X64-NEXT: andl $15, %esi ; X64-NEXT: lock btsl %esi, (%rdi) ; X64-NEXT: movl $123, %eax -; X64-NEXT: jae .LBB85_1 -; X64-NEXT: # %bb.2: # %return +; X64-NEXT: jae .LBB85_2 +; X64-NEXT: # %bb.1: # %return ; X64-NEXT: retq -; X64-NEXT: .LBB85_1: # %if.then +; X64-NEXT: .LBB85_2: # %if.then ; X64-NEXT: movl %esi, %eax ; X64-NEXT: movl (%rdi,%rax,4), %eax ; X64-NEXT: retq @@ -5035,10 +5035,10 @@ define i32 @atomic_shl1_mask0_or_32_gpr_brz(ptr %v, i32 %c) nounwind { ; X86-NEXT: andl $31, %eax ; X86-NEXT: lock btsl %eax, (%edx) ; X86-NEXT: movl $123, %eax -; X86-NEXT: jae .LBB86_1 -; X86-NEXT: # %bb.2: # %return +; X86-NEXT: jae .LBB86_2 +; X86-NEXT: # %bb.1: # %return ; X86-NEXT: retl -; X86-NEXT: .LBB86_1: # %if.then +; X86-NEXT: .LBB86_2: # %if.then ; X86-NEXT: movl (%edx,%ecx,4), %eax ; X86-NEXT: retl ; @@ -5048,10 +5048,10 @@ define i32 @atomic_shl1_mask0_or_32_gpr_brz(ptr %v, i32 %c) nounwind { ; X64-NEXT: andl $31, %eax ; X64-NEXT: lock btsl %eax, (%rdi) ; X64-NEXT: movl $123, %eax -; X64-NEXT: jae .LBB86_1 -; X64-NEXT: # %bb.2: # %return +; X64-NEXT: jae .LBB86_2 +; X64-NEXT: # %bb.1: # %return ; X64-NEXT: retq -; X64-NEXT: .LBB86_1: # %if.then +; X64-NEXT: .LBB86_2: # %if.then ; X64-NEXT: movl %esi, %eax ; X64-NEXT: movl (%rdi,%rax,4), %eax ; X64-NEXT: retq @@ -5084,10 +5084,10 @@ define i32 @atomic_shl1_mask1_or_32_gpr_brz(ptr %v, i32 %c) nounwind { ; X86-NEXT: andl $31, %eax ; X86-NEXT: lock btsl %eax, (%edx) ; X86-NEXT: movl $123, %eax -; X86-NEXT: jae .LBB87_1 -; X86-NEXT: # %bb.2: # %return +; X86-NEXT: jae .LBB87_2 +; X86-NEXT: # %bb.1: # %return ; X86-NEXT: retl -; X86-NEXT: .LBB87_1: # %if.then +; X86-NEXT: .LBB87_2: # %if.then ; X86-NEXT: movl (%edx,%ecx,4), %eax ; X86-NEXT: retl ; @@ -5097,10 +5097,10 @@ define i32 @atomic_shl1_mask1_or_32_gpr_brz(ptr %v, i32 %c) nounwind { ; X64-NEXT: andl $31, %eax ; X64-NEXT: lock btsl %eax, (%rdi) ; X64-NEXT: movl $123, %eax -; X64-NEXT: jae .LBB87_1 -; X64-NEXT: # %bb.2: # %return +; X64-NEXT: jae .LBB87_2 +; X64-NEXT: # %bb.1: # %return ; X64-NEXT: retq -; X64-NEXT: .LBB87_1: # %if.then +; X64-NEXT: .LBB87_2: # %if.then ; X64-NEXT: movl %esi, %eax ; X64-NEXT: movl (%rdi,%rax,4), %eax ; X64-NEXT: retq @@ -5133,10 +5133,10 @@ define i32 @atomic_shl1_mask01_or_32_gpr_brz(ptr %v, i32 %c) nounwind { ; X86-NEXT: andl $31, %eax ; X86-NEXT: lock btsl %eax, (%edx) ; X86-NEXT: movl $123, %eax -; X86-NEXT: jae .LBB88_1 -; X86-NEXT: # %bb.2: # %return +; X86-NEXT: jae .LBB88_2 +; X86-NEXT: # %bb.1: # %return ; X86-NEXT: retl -; X86-NEXT: .LBB88_1: # %if.then +; X86-NEXT: .LBB88_2: # %if.then ; X86-NEXT: movl (%edx,%ecx,4), %eax ; X86-NEXT: retl ; @@ -5146,10 +5146,10 @@ define i32 @atomic_shl1_mask01_or_32_gpr_brz(ptr %v, i32 %c) nounwind { ; X64-NEXT: andl $31, %eax ; X64-NEXT: lock btsl %eax, (%rdi) ; X64-NEXT: movl $123, %eax -; X64-NEXT: jae .LBB88_1 -; X64-NEXT: # %bb.2: # %return +; X64-NEXT: jae .LBB88_2 +; X64-NEXT: # %bb.1: # %return ; X64-NEXT: retq -; X64-NEXT: .LBB88_1: # %if.then +; X64-NEXT: .LBB88_2: # %if.then ; X64-NEXT: movl %esi, %eax ; X64-NEXT: movl (%rdi,%rax,4), %eax ; X64-NEXT: retq @@ -5218,11 +5218,11 @@ define i32 @atomic_blsi_or_32_gpr_brz(ptr %v, i32 %c) nounwind { ; X64-NEXT: # %bb.2: # %atomicrmw.end ; X64-NEXT: movl $123, %ecx ; X64-NEXT: testl %edx, %eax -; X64-NEXT: je .LBB89_3 -; X64-NEXT: # %bb.4: # %return +; X64-NEXT: je .LBB89_4 +; X64-NEXT: # %bb.3: # %return ; X64-NEXT: movl %ecx, %eax ; X64-NEXT: retq -; X64-NEXT: .LBB89_3: # %if.then +; X64-NEXT: .LBB89_4: # %if.then ; X64-NEXT: movl %esi, %eax ; X64-NEXT: movl (%rdi,%rax,4), %ecx ; X64-NEXT: movl %ecx, %eax @@ -5254,11 +5254,11 @@ define i32 @atomic_shl1_or_32_gpr_brnz(ptr %v, i32 %c) nounwind { ; X86-NEXT: movl %eax, %edx ; X86-NEXT: andl $31, %edx ; X86-NEXT: lock btsl %edx, (%ecx) -; X86-NEXT: jae .LBB90_1 -; X86-NEXT: # %bb.2: # %if.then +; X86-NEXT: jae .LBB90_2 +; X86-NEXT: # %bb.1: # %if.then ; X86-NEXT: movl (%ecx,%eax,4), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB90_1: +; X86-NEXT: .LBB90_2: ; X86-NEXT: movl $123, %eax ; X86-NEXT: retl ; @@ -5267,12 +5267,12 @@ define i32 @atomic_shl1_or_32_gpr_brnz(ptr %v, i32 %c) nounwind { ; X64-NEXT: movl %esi, %eax ; X64-NEXT: andl $31, %eax ; X64-NEXT: lock btsl %eax, (%rdi) -; X64-NEXT: jae .LBB90_1 -; X64-NEXT: # %bb.2: # %if.then +; X64-NEXT: jae .LBB90_2 +; X64-NEXT: # %bb.1: # %if.then ; X64-NEXT: movl %esi, %eax ; X64-NEXT: movl (%rdi,%rax,4), %eax ; X64-NEXT: retq -; X64-NEXT: .LBB90_1: +; X64-NEXT: .LBB90_2: ; X64-NEXT: movl $123, %eax ; X64-NEXT: retq entry: @@ -5300,11 +5300,11 @@ define i32 @atomic_shl1_small_mask_or_32_gpr_brnz(ptr %v, i32 %c) nounwind { ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: andl $15, %ecx ; X86-NEXT: lock btsl %ecx, (%eax) -; X86-NEXT: jae .LBB91_1 -; X86-NEXT: # %bb.2: # %if.then +; X86-NEXT: jae .LBB91_2 +; X86-NEXT: # %bb.1: # %if.then ; X86-NEXT: movl (%eax,%ecx,4), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB91_1: +; X86-NEXT: .LBB91_2: ; X86-NEXT: movl $123, %eax ; X86-NEXT: retl ; @@ -5312,12 +5312,12 @@ define i32 @atomic_shl1_small_mask_or_32_gpr_brnz(ptr %v, i32 %c) nounwind { ; X64: # %bb.0: # %entry ; X64-NEXT: andl $15, %esi ; X64-NEXT: lock btsl %esi, (%rdi) -; X64-NEXT: jae .LBB91_1 -; X64-NEXT: # %bb.2: # %if.then +; X64-NEXT: jae .LBB91_2 +; X64-NEXT: # %bb.1: # %if.then ; X64-NEXT: movl %esi, %eax ; X64-NEXT: movl (%rdi,%rax,4), %eax ; X64-NEXT: retq -; X64-NEXT: .LBB91_1: +; X64-NEXT: .LBB91_2: ; X64-NEXT: movl $123, %eax ; X64-NEXT: retq entry: @@ -5347,11 +5347,11 @@ define i32 @atomic_shl1_mask0_or_32_gpr_brnz(ptr %v, i32 %c) nounwind { ; X86-NEXT: movl %eax, %edx ; X86-NEXT: andl $31, %edx ; X86-NEXT: lock btsl %edx, (%ecx) -; X86-NEXT: jae .LBB92_1 -; X86-NEXT: # %bb.2: # %if.then +; X86-NEXT: jae .LBB92_2 +; X86-NEXT: # %bb.1: # %if.then ; X86-NEXT: movl (%ecx,%eax,4), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB92_1: +; X86-NEXT: .LBB92_2: ; X86-NEXT: movl $123, %eax ; X86-NEXT: retl ; @@ -5360,12 +5360,12 @@ define i32 @atomic_shl1_mask0_or_32_gpr_brnz(ptr %v, i32 %c) nounwind { ; X64-NEXT: movl %esi, %eax ; X64-NEXT: andl $31, %eax ; X64-NEXT: lock btsl %eax, (%rdi) -; X64-NEXT: jae .LBB92_1 -; X64-NEXT: # %bb.2: # %if.then +; X64-NEXT: jae .LBB92_2 +; X64-NEXT: # %bb.1: # %if.then ; X64-NEXT: movl %esi, %eax ; X64-NEXT: movl (%rdi,%rax,4), %eax ; X64-NEXT: retq -; X64-NEXT: .LBB92_1: +; X64-NEXT: .LBB92_2: ; X64-NEXT: movl $123, %eax ; X64-NEXT: retq entry: @@ -5396,11 +5396,11 @@ define i32 @atomic_shl1_mask1_or_32_gpr_brnz(ptr %v, i32 %c) nounwind { ; X86-NEXT: movl %eax, %edx ; X86-NEXT: andl $31, %edx ; X86-NEXT: lock btsl %edx, (%ecx) -; X86-NEXT: jae .LBB93_1 -; X86-NEXT: # %bb.2: # %if.then +; X86-NEXT: jae .LBB93_2 +; X86-NEXT: # %bb.1: # %if.then ; X86-NEXT: movl (%ecx,%eax,4), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB93_1: +; X86-NEXT: .LBB93_2: ; X86-NEXT: movl $123, %eax ; X86-NEXT: retl ; @@ -5409,12 +5409,12 @@ define i32 @atomic_shl1_mask1_or_32_gpr_brnz(ptr %v, i32 %c) nounwind { ; X64-NEXT: movl %esi, %eax ; X64-NEXT: andl $31, %eax ; X64-NEXT: lock btsl %eax, (%rdi) -; X64-NEXT: jae .LBB93_1 -; X64-NEXT: # %bb.2: # %if.then +; X64-NEXT: jae .LBB93_2 +; X64-NEXT: # %bb.1: # %if.then ; X64-NEXT: movl %esi, %eax ; X64-NEXT: movl (%rdi,%rax,4), %eax ; X64-NEXT: retq -; X64-NEXT: .LBB93_1: +; X64-NEXT: .LBB93_2: ; X64-NEXT: movl $123, %eax ; X64-NEXT: retq entry: @@ -5445,11 +5445,11 @@ define i32 @atomic_shl1_mask01_or_32_gpr_brnz(ptr %v, i32 %c) nounwind { ; X86-NEXT: movl %eax, %edx ; X86-NEXT: andl $31, %edx ; X86-NEXT: lock btsl %edx, (%ecx) -; X86-NEXT: jae .LBB94_1 -; X86-NEXT: # %bb.2: # %if.then +; X86-NEXT: jae .LBB94_2 +; X86-NEXT: # %bb.1: # %if.then ; X86-NEXT: movl (%ecx,%eax,4), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB94_1: +; X86-NEXT: .LBB94_2: ; X86-NEXT: movl $123, %eax ; X86-NEXT: retl ; @@ -5458,12 +5458,12 @@ define i32 @atomic_shl1_mask01_or_32_gpr_brnz(ptr %v, i32 %c) nounwind { ; X64-NEXT: movl %esi, %eax ; X64-NEXT: andl $31, %eax ; X64-NEXT: lock btsl %eax, (%rdi) -; X64-NEXT: jae .LBB94_1 -; X64-NEXT: # %bb.2: # %if.then +; X64-NEXT: jae .LBB94_2 +; X64-NEXT: # %bb.1: # %if.then ; X64-NEXT: movl %esi, %eax ; X64-NEXT: movl (%rdi,%rax,4), %eax ; X64-NEXT: retq -; X64-NEXT: .LBB94_1: +; X64-NEXT: .LBB94_2: ; X64-NEXT: movl $123, %eax ; X64-NEXT: retq entry: @@ -5505,11 +5505,11 @@ define i32 @atomic_blsi_or_32_gpr_brnz(ptr %v, i32 %c) nounwind { ; X86-NEXT: jne .LBB95_1 ; X86-NEXT: # %bb.2: # %atomicrmw.end ; X86-NEXT: testl %esi, %eax -; X86-NEXT: je .LBB95_3 -; X86-NEXT: # %bb.4: # %if.then +; X86-NEXT: je .LBB95_4 +; X86-NEXT: # %bb.3: # %if.then ; X86-NEXT: movl (%edx,%ecx,4), %eax ; X86-NEXT: jmp .LBB95_5 -; X86-NEXT: .LBB95_3: +; X86-NEXT: .LBB95_4: ; X86-NEXT: movl $123, %eax ; X86-NEXT: .LBB95_5: # %return ; X86-NEXT: popl %esi @@ -5531,12 +5531,12 @@ define i32 @atomic_blsi_or_32_gpr_brnz(ptr %v, i32 %c) nounwind { ; X64-NEXT: jne .LBB95_1 ; X64-NEXT: # %bb.2: # %atomicrmw.end ; X64-NEXT: testl %ecx, %eax -; X64-NEXT: je .LBB95_3 -; X64-NEXT: # %bb.4: # %if.then +; X64-NEXT: je .LBB95_4 +; X64-NEXT: # %bb.3: # %if.then ; X64-NEXT: movl %esi, %eax ; X64-NEXT: movl (%rdi,%rax,4), %eax ; X64-NEXT: retq -; X64-NEXT: .LBB95_3: +; X64-NEXT: .LBB95_4: ; X64-NEXT: movl $123, %eax ; X64-NEXT: retq entry: @@ -5982,11 +5982,11 @@ define i32 @atomic_shl1_mask0_and_32_gpr_br(ptr %v, i32 %c) nounwind { ; X86-NEXT: jne .LBB104_1 ; X86-NEXT: # %bb.2: # %atomicrmw.end ; X86-NEXT: btl %ecx, %eax -; X86-NEXT: jae .LBB104_3 -; X86-NEXT: # %bb.4: # %if.then +; X86-NEXT: jae .LBB104_4 +; X86-NEXT: # %bb.3: # %if.then ; X86-NEXT: movl (%edx,%ecx,4), %eax ; X86-NEXT: jmp .LBB104_5 -; X86-NEXT: .LBB104_3: +; X86-NEXT: .LBB104_4: ; X86-NEXT: movl $123, %eax ; X86-NEXT: .LBB104_5: # %return ; X86-NEXT: popl %esi @@ -6008,12 +6008,12 @@ define i32 @atomic_shl1_mask0_and_32_gpr_br(ptr %v, i32 %c) nounwind { ; X64-NEXT: jne .LBB104_1 ; X64-NEXT: # %bb.2: # %atomicrmw.end ; X64-NEXT: btl %ecx, %eax -; X64-NEXT: jae .LBB104_3 -; X64-NEXT: # %bb.4: # %if.then +; X64-NEXT: jae .LBB104_4 +; X64-NEXT: # %bb.3: # %if.then ; X64-NEXT: movl %ecx, %eax ; X64-NEXT: movl (%rdi,%rax,4), %eax ; X64-NEXT: retq -; X64-NEXT: .LBB104_3: +; X64-NEXT: .LBB104_4: ; X64-NEXT: movl $123, %eax ; X64-NEXT: retq entry: @@ -6055,11 +6055,11 @@ define i32 @atomic_shl1_mask1_and_32_gpr_br(ptr %v, i32 %c) nounwind { ; X86-NEXT: jne .LBB105_1 ; X86-NEXT: # %bb.2: # %atomicrmw.end ; X86-NEXT: btl %ecx, %eax -; X86-NEXT: jae .LBB105_3 -; X86-NEXT: # %bb.4: # %if.then +; X86-NEXT: jae .LBB105_4 +; X86-NEXT: # %bb.3: # %if.then ; X86-NEXT: movl (%edx,%ecx,4), %eax ; X86-NEXT: jmp .LBB105_5 -; X86-NEXT: .LBB105_3: +; X86-NEXT: .LBB105_4: ; X86-NEXT: movl $123, %eax ; X86-NEXT: .LBB105_5: # %return ; X86-NEXT: popl %esi @@ -6081,12 +6081,12 @@ define i32 @atomic_shl1_mask1_and_32_gpr_br(ptr %v, i32 %c) nounwind { ; X64-NEXT: jne .LBB105_1 ; X64-NEXT: # %bb.2: # %atomicrmw.end ; X64-NEXT: btl %ecx, %eax -; X64-NEXT: jae .LBB105_3 -; X64-NEXT: # %bb.4: # %if.then +; X64-NEXT: jae .LBB105_4 +; X64-NEXT: # %bb.3: # %if.then ; X64-NEXT: movl %ecx, %eax ; X64-NEXT: movl (%rdi,%rax,4), %eax ; X64-NEXT: retq -; X64-NEXT: .LBB105_3: +; X64-NEXT: .LBB105_4: ; X64-NEXT: movl $123, %eax ; X64-NEXT: retq entry: @@ -6344,11 +6344,11 @@ define i32 @atomic_shl1_mask0_and_32_gpr_brz(ptr %v, i32 %c) nounwind { ; X64-NEXT: # %bb.2: # %atomicrmw.end ; X64-NEXT: movl $123, %edx ; X64-NEXT: btl %ecx, %eax -; X64-NEXT: jae .LBB110_3 -; X64-NEXT: # %bb.4: # %return +; X64-NEXT: jae .LBB110_4 +; X64-NEXT: # %bb.3: # %return ; X64-NEXT: movl %edx, %eax ; X64-NEXT: retq -; X64-NEXT: .LBB110_3: # %if.then +; X64-NEXT: .LBB110_4: # %if.then ; X64-NEXT: movl %ecx, %eax ; X64-NEXT: movl (%rdi,%rax,4), %edx ; X64-NEXT: movl %edx, %eax @@ -6418,11 +6418,11 @@ define i32 @atomic_shl1_mask1_and_32_gpr_brz(ptr %v, i32 %c) nounwind { ; X64-NEXT: # %bb.2: # %atomicrmw.end ; X64-NEXT: movl $123, %edx ; X64-NEXT: btl %ecx, %eax -; X64-NEXT: jae .LBB111_3 -; X64-NEXT: # %bb.4: # %return +; X64-NEXT: jae .LBB111_4 +; X64-NEXT: # %bb.3: # %return ; X64-NEXT: movl %edx, %eax ; X64-NEXT: retq -; X64-NEXT: .LBB111_3: # %if.then +; X64-NEXT: .LBB111_4: # %if.then ; X64-NEXT: movl %ecx, %eax ; X64-NEXT: movl (%rdi,%rax,4), %edx ; X64-NEXT: movl %edx, %eax @@ -6755,22 +6755,22 @@ define i32 @atomic_shl1_and_32_const_br(ptr %v) nounwind { ; X86: # %bb.0: # %entry ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: lock btrl $4, (%eax) -; X86-NEXT: jae .LBB120_1 -; X86-NEXT: # %bb.2: # %if.then +; X86-NEXT: jae .LBB120_2 +; X86-NEXT: # %bb.1: # %if.then ; X86-NEXT: movl 16(%eax), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB120_1: +; X86-NEXT: .LBB120_2: ; X86-NEXT: movl $123, %eax ; X86-NEXT: retl ; ; X64-LABEL: atomic_shl1_and_32_const_br: ; X64: # %bb.0: # %entry ; X64-NEXT: lock btrl $4, (%rdi) -; X64-NEXT: jae .LBB120_1 -; X64-NEXT: # %bb.2: # %if.then +; X64-NEXT: jae .LBB120_2 +; X64-NEXT: # %bb.1: # %if.then ; X64-NEXT: movl 16(%rdi), %eax ; X64-NEXT: retq -; X64-NEXT: .LBB120_1: +; X64-NEXT: .LBB120_2: ; X64-NEXT: movl $123, %eax ; X64-NEXT: retq entry: @@ -6795,10 +6795,10 @@ define i32 @atomic_shl1_and_32_const_brz(ptr %v) nounwind { ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: lock btrl $4, (%ecx) ; X86-NEXT: movl $123, %eax -; X86-NEXT: jae .LBB121_1 -; X86-NEXT: # %bb.2: # %return +; X86-NEXT: jae .LBB121_2 +; X86-NEXT: # %bb.1: # %return ; X86-NEXT: retl -; X86-NEXT: .LBB121_1: # %if.then +; X86-NEXT: .LBB121_2: # %if.then ; X86-NEXT: movl 16(%ecx), %eax ; X86-NEXT: retl ; @@ -6806,10 +6806,10 @@ define i32 @atomic_shl1_and_32_const_brz(ptr %v) nounwind { ; X64: # %bb.0: # %entry ; X64-NEXT: lock btrl $4, (%rdi) ; X64-NEXT: movl $123, %eax -; X64-NEXT: jae .LBB121_1 -; X64-NEXT: # %bb.2: # %return +; X64-NEXT: jae .LBB121_2 +; X64-NEXT: # %bb.1: # %return ; X64-NEXT: retq -; X64-NEXT: .LBB121_1: # %if.then +; X64-NEXT: .LBB121_2: # %if.then ; X64-NEXT: movl 16(%rdi), %eax ; X64-NEXT: retq entry: diff --git a/llvm/test/CodeGen/X86/atomic-unordered.ll b/llvm/test/CodeGen/X86/atomic-unordered.ll index 7946204865ab6..247e2eccaa03d 100644 --- a/llvm/test/CodeGen/X86/atomic-unordered.ll +++ b/llvm/test/CodeGen/X86/atomic-unordered.ll @@ -628,12 +628,12 @@ define i64 @load_fold_sdiv2(ptr %p, i64 %v2) { ; CHECK-O3-NEXT: movq %rax, %rcx ; CHECK-O3-NEXT: orq %rsi, %rcx ; CHECK-O3-NEXT: shrq $32, %rcx -; CHECK-O3-NEXT: je .LBB35_1 -; CHECK-O3-NEXT: # %bb.2: +; CHECK-O3-NEXT: je .LBB35_2 +; CHECK-O3-NEXT: # %bb.1: ; CHECK-O3-NEXT: cqto ; CHECK-O3-NEXT: idivq %rsi ; CHECK-O3-NEXT: retq -; CHECK-O3-NEXT: .LBB35_1: +; CHECK-O3-NEXT: .LBB35_2: ; CHECK-O3-NEXT: # kill: def $eax killed $eax killed $rax ; CHECK-O3-NEXT: xorl %edx, %edx ; CHECK-O3-NEXT: divl %esi @@ -659,12 +659,12 @@ define i64 @load_fold_sdiv3(ptr %p1, ptr %p2) { ; CHECK-O3-NEXT: movq %rax, %rdx ; CHECK-O3-NEXT: orq %rcx, %rdx ; CHECK-O3-NEXT: shrq $32, %rdx -; CHECK-O3-NEXT: je .LBB36_1 -; CHECK-O3-NEXT: # %bb.2: +; CHECK-O3-NEXT: je .LBB36_2 +; CHECK-O3-NEXT: # %bb.1: ; CHECK-O3-NEXT: cqto ; CHECK-O3-NEXT: idivq %rcx ; CHECK-O3-NEXT: retq -; CHECK-O3-NEXT: .LBB36_1: +; CHECK-O3-NEXT: .LBB36_2: ; CHECK-O3-NEXT: # kill: def $eax killed $eax killed $rax ; CHECK-O3-NEXT: xorl %edx, %edx ; CHECK-O3-NEXT: divl %ecx @@ -714,12 +714,12 @@ define i64 @load_fold_udiv2(ptr %p, i64 %v2) { ; CHECK-O3-NEXT: movq %rax, %rcx ; CHECK-O3-NEXT: orq %rsi, %rcx ; CHECK-O3-NEXT: shrq $32, %rcx -; CHECK-O3-NEXT: je .LBB38_1 -; CHECK-O3-NEXT: # %bb.2: +; CHECK-O3-NEXT: je .LBB38_2 +; CHECK-O3-NEXT: # %bb.1: ; CHECK-O3-NEXT: xorl %edx, %edx ; CHECK-O3-NEXT: divq %rsi ; CHECK-O3-NEXT: retq -; CHECK-O3-NEXT: .LBB38_1: +; CHECK-O3-NEXT: .LBB38_2: ; CHECK-O3-NEXT: # kill: def $eax killed $eax killed $rax ; CHECK-O3-NEXT: xorl %edx, %edx ; CHECK-O3-NEXT: divl %esi @@ -746,12 +746,12 @@ define i64 @load_fold_udiv3(ptr %p1, ptr %p2) { ; CHECK-O3-NEXT: movq %rax, %rdx ; CHECK-O3-NEXT: orq %rcx, %rdx ; CHECK-O3-NEXT: shrq $32, %rdx -; CHECK-O3-NEXT: je .LBB39_1 -; CHECK-O3-NEXT: # %bb.2: +; CHECK-O3-NEXT: je .LBB39_2 +; CHECK-O3-NEXT: # %bb.1: ; CHECK-O3-NEXT: xorl %edx, %edx ; CHECK-O3-NEXT: divq %rcx ; CHECK-O3-NEXT: retq -; CHECK-O3-NEXT: .LBB39_1: +; CHECK-O3-NEXT: .LBB39_2: ; CHECK-O3-NEXT: # kill: def $eax killed $eax killed $rax ; CHECK-O3-NEXT: xorl %edx, %edx ; CHECK-O3-NEXT: divl %ecx @@ -811,13 +811,13 @@ define i64 @load_fold_srem2(ptr %p, i64 %v2) { ; CHECK-O3-NEXT: movq %rax, %rcx ; CHECK-O3-NEXT: orq %rsi, %rcx ; CHECK-O3-NEXT: shrq $32, %rcx -; CHECK-O3-NEXT: je .LBB41_1 -; CHECK-O3-NEXT: # %bb.2: +; CHECK-O3-NEXT: je .LBB41_2 +; CHECK-O3-NEXT: # %bb.1: ; CHECK-O3-NEXT: cqto ; CHECK-O3-NEXT: idivq %rsi ; CHECK-O3-NEXT: movq %rdx, %rax ; CHECK-O3-NEXT: retq -; CHECK-O3-NEXT: .LBB41_1: +; CHECK-O3-NEXT: .LBB41_2: ; CHECK-O3-NEXT: # kill: def $eax killed $eax killed $rax ; CHECK-O3-NEXT: xorl %edx, %edx ; CHECK-O3-NEXT: divl %esi @@ -844,13 +844,13 @@ define i64 @load_fold_srem3(ptr %p1, ptr %p2) { ; CHECK-O3-NEXT: movq %rax, %rdx ; CHECK-O3-NEXT: orq %rcx, %rdx ; CHECK-O3-NEXT: shrq $32, %rdx -; CHECK-O3-NEXT: je .LBB42_1 -; CHECK-O3-NEXT: # %bb.2: +; CHECK-O3-NEXT: je .LBB42_2 +; CHECK-O3-NEXT: # %bb.1: ; CHECK-O3-NEXT: cqto ; CHECK-O3-NEXT: idivq %rcx ; CHECK-O3-NEXT: movq %rdx, %rax ; CHECK-O3-NEXT: retq -; CHECK-O3-NEXT: .LBB42_1: +; CHECK-O3-NEXT: .LBB42_2: ; CHECK-O3-NEXT: # kill: def $eax killed $eax killed $rax ; CHECK-O3-NEXT: xorl %edx, %edx ; CHECK-O3-NEXT: divl %ecx @@ -907,13 +907,13 @@ define i64 @load_fold_urem2(ptr %p, i64 %v2) { ; CHECK-O3-NEXT: movq %rax, %rcx ; CHECK-O3-NEXT: orq %rsi, %rcx ; CHECK-O3-NEXT: shrq $32, %rcx -; CHECK-O3-NEXT: je .LBB44_1 -; CHECK-O3-NEXT: # %bb.2: +; CHECK-O3-NEXT: je .LBB44_2 +; CHECK-O3-NEXT: # %bb.1: ; CHECK-O3-NEXT: xorl %edx, %edx ; CHECK-O3-NEXT: divq %rsi ; CHECK-O3-NEXT: movq %rdx, %rax ; CHECK-O3-NEXT: retq -; CHECK-O3-NEXT: .LBB44_1: +; CHECK-O3-NEXT: .LBB44_2: ; CHECK-O3-NEXT: # kill: def $eax killed $eax killed $rax ; CHECK-O3-NEXT: xorl %edx, %edx ; CHECK-O3-NEXT: divl %esi @@ -941,13 +941,13 @@ define i64 @load_fold_urem3(ptr %p1, ptr %p2) { ; CHECK-O3-NEXT: movq %rax, %rdx ; CHECK-O3-NEXT: orq %rcx, %rdx ; CHECK-O3-NEXT: shrq $32, %rdx -; CHECK-O3-NEXT: je .LBB45_1 -; CHECK-O3-NEXT: # %bb.2: +; CHECK-O3-NEXT: je .LBB45_2 +; CHECK-O3-NEXT: # %bb.1: ; CHECK-O3-NEXT: xorl %edx, %edx ; CHECK-O3-NEXT: divq %rcx ; CHECK-O3-NEXT: movq %rdx, %rax ; CHECK-O3-NEXT: retq -; CHECK-O3-NEXT: .LBB45_1: +; CHECK-O3-NEXT: .LBB45_2: ; CHECK-O3-NEXT: # kill: def $eax killed $eax killed $rax ; CHECK-O3-NEXT: xorl %edx, %edx ; CHECK-O3-NEXT: divl %ecx @@ -1464,13 +1464,13 @@ define void @rmw_fold_sdiv2(ptr %p, i64 %v) { ; CHECK-O3-NEXT: movq %rax, %rcx ; CHECK-O3-NEXT: orq %rsi, %rcx ; CHECK-O3-NEXT: shrq $32, %rcx -; CHECK-O3-NEXT: je .LBB74_1 -; CHECK-O3-NEXT: # %bb.2: +; CHECK-O3-NEXT: je .LBB74_2 +; CHECK-O3-NEXT: # %bb.1: ; CHECK-O3-NEXT: cqto ; CHECK-O3-NEXT: idivq %rsi ; CHECK-O3-NEXT: movq %rax, (%rdi) ; CHECK-O3-NEXT: retq -; CHECK-O3-NEXT: .LBB74_1: +; CHECK-O3-NEXT: .LBB74_2: ; CHECK-O3-NEXT: # kill: def $eax killed $eax killed $rax ; CHECK-O3-NEXT: xorl %edx, %edx ; CHECK-O3-NEXT: divl %esi @@ -1516,13 +1516,13 @@ define void @rmw_fold_udiv2(ptr %p, i64 %v) { ; CHECK-O3-NEXT: movq %rax, %rcx ; CHECK-O3-NEXT: orq %rsi, %rcx ; CHECK-O3-NEXT: shrq $32, %rcx -; CHECK-O3-NEXT: je .LBB76_1 -; CHECK-O3-NEXT: # %bb.2: +; CHECK-O3-NEXT: je .LBB76_2 +; CHECK-O3-NEXT: # %bb.1: ; CHECK-O3-NEXT: xorl %edx, %edx ; CHECK-O3-NEXT: divq %rsi ; CHECK-O3-NEXT: movq %rax, (%rdi) ; CHECK-O3-NEXT: retq -; CHECK-O3-NEXT: .LBB76_1: +; CHECK-O3-NEXT: .LBB76_2: ; CHECK-O3-NEXT: # kill: def $eax killed $eax killed $rax ; CHECK-O3-NEXT: xorl %edx, %edx ; CHECK-O3-NEXT: divl %esi @@ -1594,13 +1594,13 @@ define void @rmw_fold_srem2(ptr %p, i64 %v) { ; CHECK-O3-NEXT: movq %rax, %rcx ; CHECK-O3-NEXT: orq %rsi, %rcx ; CHECK-O3-NEXT: shrq $32, %rcx -; CHECK-O3-NEXT: je .LBB78_1 -; CHECK-O3-NEXT: # %bb.2: +; CHECK-O3-NEXT: je .LBB78_2 +; CHECK-O3-NEXT: # %bb.1: ; CHECK-O3-NEXT: cqto ; CHECK-O3-NEXT: idivq %rsi ; CHECK-O3-NEXT: movq %rdx, (%rdi) ; CHECK-O3-NEXT: retq -; CHECK-O3-NEXT: .LBB78_1: +; CHECK-O3-NEXT: .LBB78_2: ; CHECK-O3-NEXT: # kill: def $eax killed $eax killed $rax ; CHECK-O3-NEXT: xorl %edx, %edx ; CHECK-O3-NEXT: divl %esi @@ -1662,13 +1662,13 @@ define void @rmw_fold_urem2(ptr %p, i64 %v) { ; CHECK-O3-NEXT: movq %rax, %rcx ; CHECK-O3-NEXT: orq %rsi, %rcx ; CHECK-O3-NEXT: shrq $32, %rcx -; CHECK-O3-NEXT: je .LBB80_1 -; CHECK-O3-NEXT: # %bb.2: +; CHECK-O3-NEXT: je .LBB80_2 +; CHECK-O3-NEXT: # %bb.1: ; CHECK-O3-NEXT: xorl %edx, %edx ; CHECK-O3-NEXT: divq %rsi ; CHECK-O3-NEXT: movq %rdx, (%rdi) ; CHECK-O3-NEXT: retq -; CHECK-O3-NEXT: .LBB80_1: +; CHECK-O3-NEXT: .LBB80_2: ; CHECK-O3-NEXT: # kill: def $eax killed $eax killed $rax ; CHECK-O3-NEXT: xorl %edx, %edx ; CHECK-O3-NEXT: divl %esi diff --git a/llvm/test/CodeGen/X86/atomic32.ll b/llvm/test/CodeGen/X86/atomic32.ll index f4666738db7d2..29f32b542d31d 100644 --- a/llvm/test/CodeGen/X86/atomic32.ll +++ b/llvm/test/CodeGen/X86/atomic32.ll @@ -324,12 +324,12 @@ define void @atomic_fetch_max32(i32 %x) nounwind { ; X86-NOCMOV-NEXT: movl %eax, %ecx ; X86-NOCMOV-NEXT: subl %edx, %ecx ; X86-NOCMOV-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NOCMOV-NEXT: jg .LBB6_4 -; X86-NOCMOV-NEXT: # %bb.3: # %atomicrmw.start +; X86-NOCMOV-NEXT: jg .LBB6_3 +; X86-NOCMOV-NEXT: # %bb.2: # %atomicrmw.start ; X86-NOCMOV-NEXT: # in Loop: Header=BB6_1 Depth=1 ; X86-NOCMOV-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NOCMOV-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NOCMOV-NEXT: .LBB6_4: # %atomicrmw.start +; X86-NOCMOV-NEXT: .LBB6_3: # %atomicrmw.start ; X86-NOCMOV-NEXT: # in Loop: Header=BB6_1 Depth=1 ; X86-NOCMOV-NEXT: movl (%esp), %eax # 4-byte Reload ; X86-NOCMOV-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload @@ -337,9 +337,9 @@ define void @atomic_fetch_max32(i32 %x) nounwind { ; X86-NOCMOV-NEXT: sete %cl ; X86-NOCMOV-NEXT: testb $1, %cl ; X86-NOCMOV-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NOCMOV-NEXT: jne .LBB6_2 +; X86-NOCMOV-NEXT: jne .LBB6_4 ; X86-NOCMOV-NEXT: jmp .LBB6_1 -; X86-NOCMOV-NEXT: .LBB6_2: # %atomicrmw.end +; X86-NOCMOV-NEXT: .LBB6_4: # %atomicrmw.end ; X86-NOCMOV-NEXT: addl $16, %esp ; X86-NOCMOV-NEXT: retl ; @@ -358,12 +358,12 @@ define void @atomic_fetch_max32(i32 %x) nounwind { ; X86-NOX87-NEXT: movl %eax, %ecx ; X86-NOX87-NEXT: subl %edx, %ecx ; X86-NOX87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NOX87-NEXT: jg .LBB6_4 -; X86-NOX87-NEXT: # %bb.3: # %atomicrmw.start +; X86-NOX87-NEXT: jg .LBB6_3 +; X86-NOX87-NEXT: # %bb.2: # %atomicrmw.start ; X86-NOX87-NEXT: # in Loop: Header=BB6_1 Depth=1 ; X86-NOX87-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NOX87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NOX87-NEXT: .LBB6_4: # %atomicrmw.start +; X86-NOX87-NEXT: .LBB6_3: # %atomicrmw.start ; X86-NOX87-NEXT: # in Loop: Header=BB6_1 Depth=1 ; X86-NOX87-NEXT: movl (%esp), %eax # 4-byte Reload ; X86-NOX87-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload @@ -371,9 +371,9 @@ define void @atomic_fetch_max32(i32 %x) nounwind { ; X86-NOX87-NEXT: sete %cl ; X86-NOX87-NEXT: testb $1, %cl ; X86-NOX87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NOX87-NEXT: jne .LBB6_2 +; X86-NOX87-NEXT: jne .LBB6_4 ; X86-NOX87-NEXT: jmp .LBB6_1 -; X86-NOX87-NEXT: .LBB6_2: # %atomicrmw.end +; X86-NOX87-NEXT: .LBB6_4: # %atomicrmw.end ; X86-NOX87-NEXT: addl $16, %esp ; X86-NOX87-NEXT: retl %t1 = atomicrmw max ptr @sc32, i32 %x acquire @@ -441,12 +441,12 @@ define void @atomic_fetch_min32(i32 %x) nounwind { ; X86-NOCMOV-NEXT: movl %eax, %ecx ; X86-NOCMOV-NEXT: subl %edx, %ecx ; X86-NOCMOV-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NOCMOV-NEXT: jle .LBB7_4 -; X86-NOCMOV-NEXT: # %bb.3: # %atomicrmw.start +; X86-NOCMOV-NEXT: jle .LBB7_3 +; X86-NOCMOV-NEXT: # %bb.2: # %atomicrmw.start ; X86-NOCMOV-NEXT: # in Loop: Header=BB7_1 Depth=1 ; X86-NOCMOV-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NOCMOV-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NOCMOV-NEXT: .LBB7_4: # %atomicrmw.start +; X86-NOCMOV-NEXT: .LBB7_3: # %atomicrmw.start ; X86-NOCMOV-NEXT: # in Loop: Header=BB7_1 Depth=1 ; X86-NOCMOV-NEXT: movl (%esp), %eax # 4-byte Reload ; X86-NOCMOV-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload @@ -454,9 +454,9 @@ define void @atomic_fetch_min32(i32 %x) nounwind { ; X86-NOCMOV-NEXT: sete %cl ; X86-NOCMOV-NEXT: testb $1, %cl ; X86-NOCMOV-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NOCMOV-NEXT: jne .LBB7_2 +; X86-NOCMOV-NEXT: jne .LBB7_4 ; X86-NOCMOV-NEXT: jmp .LBB7_1 -; X86-NOCMOV-NEXT: .LBB7_2: # %atomicrmw.end +; X86-NOCMOV-NEXT: .LBB7_4: # %atomicrmw.end ; X86-NOCMOV-NEXT: addl $16, %esp ; X86-NOCMOV-NEXT: retl ; @@ -475,12 +475,12 @@ define void @atomic_fetch_min32(i32 %x) nounwind { ; X86-NOX87-NEXT: movl %eax, %ecx ; X86-NOX87-NEXT: subl %edx, %ecx ; X86-NOX87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NOX87-NEXT: jle .LBB7_4 -; X86-NOX87-NEXT: # %bb.3: # %atomicrmw.start +; X86-NOX87-NEXT: jle .LBB7_3 +; X86-NOX87-NEXT: # %bb.2: # %atomicrmw.start ; X86-NOX87-NEXT: # in Loop: Header=BB7_1 Depth=1 ; X86-NOX87-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NOX87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NOX87-NEXT: .LBB7_4: # %atomicrmw.start +; X86-NOX87-NEXT: .LBB7_3: # %atomicrmw.start ; X86-NOX87-NEXT: # in Loop: Header=BB7_1 Depth=1 ; X86-NOX87-NEXT: movl (%esp), %eax # 4-byte Reload ; X86-NOX87-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload @@ -488,9 +488,9 @@ define void @atomic_fetch_min32(i32 %x) nounwind { ; X86-NOX87-NEXT: sete %cl ; X86-NOX87-NEXT: testb $1, %cl ; X86-NOX87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NOX87-NEXT: jne .LBB7_2 +; X86-NOX87-NEXT: jne .LBB7_4 ; X86-NOX87-NEXT: jmp .LBB7_1 -; X86-NOX87-NEXT: .LBB7_2: # %atomicrmw.end +; X86-NOX87-NEXT: .LBB7_4: # %atomicrmw.end ; X86-NOX87-NEXT: addl $16, %esp ; X86-NOX87-NEXT: retl %t1 = atomicrmw min ptr @sc32, i32 %x acquire @@ -558,12 +558,12 @@ define void @atomic_fetch_umax32(i32 %x) nounwind { ; X86-NOCMOV-NEXT: movl %eax, %ecx ; X86-NOCMOV-NEXT: subl %edx, %ecx ; X86-NOCMOV-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NOCMOV-NEXT: ja .LBB8_4 -; X86-NOCMOV-NEXT: # %bb.3: # %atomicrmw.start +; X86-NOCMOV-NEXT: ja .LBB8_3 +; X86-NOCMOV-NEXT: # %bb.2: # %atomicrmw.start ; X86-NOCMOV-NEXT: # in Loop: Header=BB8_1 Depth=1 ; X86-NOCMOV-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NOCMOV-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NOCMOV-NEXT: .LBB8_4: # %atomicrmw.start +; X86-NOCMOV-NEXT: .LBB8_3: # %atomicrmw.start ; X86-NOCMOV-NEXT: # in Loop: Header=BB8_1 Depth=1 ; X86-NOCMOV-NEXT: movl (%esp), %eax # 4-byte Reload ; X86-NOCMOV-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload @@ -571,9 +571,9 @@ define void @atomic_fetch_umax32(i32 %x) nounwind { ; X86-NOCMOV-NEXT: sete %cl ; X86-NOCMOV-NEXT: testb $1, %cl ; X86-NOCMOV-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NOCMOV-NEXT: jne .LBB8_2 +; X86-NOCMOV-NEXT: jne .LBB8_4 ; X86-NOCMOV-NEXT: jmp .LBB8_1 -; X86-NOCMOV-NEXT: .LBB8_2: # %atomicrmw.end +; X86-NOCMOV-NEXT: .LBB8_4: # %atomicrmw.end ; X86-NOCMOV-NEXT: addl $16, %esp ; X86-NOCMOV-NEXT: retl ; @@ -592,12 +592,12 @@ define void @atomic_fetch_umax32(i32 %x) nounwind { ; X86-NOX87-NEXT: movl %eax, %ecx ; X86-NOX87-NEXT: subl %edx, %ecx ; X86-NOX87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NOX87-NEXT: ja .LBB8_4 -; X86-NOX87-NEXT: # %bb.3: # %atomicrmw.start +; X86-NOX87-NEXT: ja .LBB8_3 +; X86-NOX87-NEXT: # %bb.2: # %atomicrmw.start ; X86-NOX87-NEXT: # in Loop: Header=BB8_1 Depth=1 ; X86-NOX87-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NOX87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NOX87-NEXT: .LBB8_4: # %atomicrmw.start +; X86-NOX87-NEXT: .LBB8_3: # %atomicrmw.start ; X86-NOX87-NEXT: # in Loop: Header=BB8_1 Depth=1 ; X86-NOX87-NEXT: movl (%esp), %eax # 4-byte Reload ; X86-NOX87-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload @@ -605,9 +605,9 @@ define void @atomic_fetch_umax32(i32 %x) nounwind { ; X86-NOX87-NEXT: sete %cl ; X86-NOX87-NEXT: testb $1, %cl ; X86-NOX87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NOX87-NEXT: jne .LBB8_2 +; X86-NOX87-NEXT: jne .LBB8_4 ; X86-NOX87-NEXT: jmp .LBB8_1 -; X86-NOX87-NEXT: .LBB8_2: # %atomicrmw.end +; X86-NOX87-NEXT: .LBB8_4: # %atomicrmw.end ; X86-NOX87-NEXT: addl $16, %esp ; X86-NOX87-NEXT: retl %t1 = atomicrmw umax ptr @sc32, i32 %x acquire @@ -675,12 +675,12 @@ define void @atomic_fetch_umin32(i32 %x) nounwind { ; X86-NOCMOV-NEXT: movl %eax, %ecx ; X86-NOCMOV-NEXT: subl %edx, %ecx ; X86-NOCMOV-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NOCMOV-NEXT: jbe .LBB9_4 -; X86-NOCMOV-NEXT: # %bb.3: # %atomicrmw.start +; X86-NOCMOV-NEXT: jbe .LBB9_3 +; X86-NOCMOV-NEXT: # %bb.2: # %atomicrmw.start ; X86-NOCMOV-NEXT: # in Loop: Header=BB9_1 Depth=1 ; X86-NOCMOV-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NOCMOV-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NOCMOV-NEXT: .LBB9_4: # %atomicrmw.start +; X86-NOCMOV-NEXT: .LBB9_3: # %atomicrmw.start ; X86-NOCMOV-NEXT: # in Loop: Header=BB9_1 Depth=1 ; X86-NOCMOV-NEXT: movl (%esp), %eax # 4-byte Reload ; X86-NOCMOV-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload @@ -688,9 +688,9 @@ define void @atomic_fetch_umin32(i32 %x) nounwind { ; X86-NOCMOV-NEXT: sete %cl ; X86-NOCMOV-NEXT: testb $1, %cl ; X86-NOCMOV-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NOCMOV-NEXT: jne .LBB9_2 +; X86-NOCMOV-NEXT: jne .LBB9_4 ; X86-NOCMOV-NEXT: jmp .LBB9_1 -; X86-NOCMOV-NEXT: .LBB9_2: # %atomicrmw.end +; X86-NOCMOV-NEXT: .LBB9_4: # %atomicrmw.end ; X86-NOCMOV-NEXT: addl $16, %esp ; X86-NOCMOV-NEXT: retl ; @@ -709,12 +709,12 @@ define void @atomic_fetch_umin32(i32 %x) nounwind { ; X86-NOX87-NEXT: movl %eax, %ecx ; X86-NOX87-NEXT: subl %edx, %ecx ; X86-NOX87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NOX87-NEXT: jbe .LBB9_4 -; X86-NOX87-NEXT: # %bb.3: # %atomicrmw.start +; X86-NOX87-NEXT: jbe .LBB9_3 +; X86-NOX87-NEXT: # %bb.2: # %atomicrmw.start ; X86-NOX87-NEXT: # in Loop: Header=BB9_1 Depth=1 ; X86-NOX87-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NOX87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NOX87-NEXT: .LBB9_4: # %atomicrmw.start +; X86-NOX87-NEXT: .LBB9_3: # %atomicrmw.start ; X86-NOX87-NEXT: # in Loop: Header=BB9_1 Depth=1 ; X86-NOX87-NEXT: movl (%esp), %eax # 4-byte Reload ; X86-NOX87-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload @@ -722,9 +722,9 @@ define void @atomic_fetch_umin32(i32 %x) nounwind { ; X86-NOX87-NEXT: sete %cl ; X86-NOX87-NEXT: testb $1, %cl ; X86-NOX87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NOX87-NEXT: jne .LBB9_2 +; X86-NOX87-NEXT: jne .LBB9_4 ; X86-NOX87-NEXT: jmp .LBB9_1 -; X86-NOX87-NEXT: .LBB9_2: # %atomicrmw.end +; X86-NOX87-NEXT: .LBB9_4: # %atomicrmw.end ; X86-NOX87-NEXT: addl $16, %esp ; X86-NOX87-NEXT: retl %t1 = atomicrmw umin ptr @sc32, i32 %x acquire diff --git a/llvm/test/CodeGen/X86/atomic64.ll b/llvm/test/CodeGen/X86/atomic64.ll index 8f4da356e06cb..508fdd0be5139 100644 --- a/llvm/test/CodeGen/X86/atomic64.ll +++ b/llvm/test/CodeGen/X86/atomic64.ll @@ -350,14 +350,14 @@ define void @atomic_fetch_max64(i64 %x) nounwind { ; I486-NEXT: sbbl %eax, %edx ; I486-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; I486-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; I486-NEXT: jl .LBB6_4 -; I486-NEXT: # %bb.3: # %atomicrmw.start +; I486-NEXT: jl .LBB6_3 +; I486-NEXT: # %bb.2: # %atomicrmw.start ; I486-NEXT: # in Loop: Header=BB6_1 Depth=1 ; I486-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; I486-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; I486-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; I486-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; I486-NEXT: .LBB6_4: # %atomicrmw.start +; I486-NEXT: .LBB6_3: # %atomicrmw.start ; I486-NEXT: # in Loop: Header=BB6_1 Depth=1 ; I486-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; I486-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload @@ -381,8 +381,8 @@ define void @atomic_fetch_max64(i64 %x) nounwind { ; I486-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; I486-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; I486-NEXT: je .LBB6_1 -; I486-NEXT: jmp .LBB6_2 -; I486-NEXT: .LBB6_2: # %atomicrmw.end +; I486-NEXT: jmp .LBB6_4 +; I486-NEXT: .LBB6_4: # %atomicrmw.end ; I486-NEXT: leal -4(%ebp), %esp ; I486-NEXT: popl %esi ; I486-NEXT: popl %ebp @@ -442,14 +442,14 @@ define void @atomic_fetch_min64(i64 %x) nounwind { ; I486-NEXT: sbbl %eax, %edx ; I486-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; I486-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; I486-NEXT: jge .LBB7_4 -; I486-NEXT: # %bb.3: # %atomicrmw.start +; I486-NEXT: jge .LBB7_3 +; I486-NEXT: # %bb.2: # %atomicrmw.start ; I486-NEXT: # in Loop: Header=BB7_1 Depth=1 ; I486-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; I486-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; I486-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; I486-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; I486-NEXT: .LBB7_4: # %atomicrmw.start +; I486-NEXT: .LBB7_3: # %atomicrmw.start ; I486-NEXT: # in Loop: Header=BB7_1 Depth=1 ; I486-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; I486-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload @@ -473,8 +473,8 @@ define void @atomic_fetch_min64(i64 %x) nounwind { ; I486-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; I486-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; I486-NEXT: je .LBB7_1 -; I486-NEXT: jmp .LBB7_2 -; I486-NEXT: .LBB7_2: # %atomicrmw.end +; I486-NEXT: jmp .LBB7_4 +; I486-NEXT: .LBB7_4: # %atomicrmw.end ; I486-NEXT: leal -4(%ebp), %esp ; I486-NEXT: popl %esi ; I486-NEXT: popl %ebp @@ -534,14 +534,14 @@ define void @atomic_fetch_umax64(i64 %x) nounwind { ; I486-NEXT: sbbl %eax, %edx ; I486-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; I486-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; I486-NEXT: jb .LBB8_4 -; I486-NEXT: # %bb.3: # %atomicrmw.start +; I486-NEXT: jb .LBB8_3 +; I486-NEXT: # %bb.2: # %atomicrmw.start ; I486-NEXT: # in Loop: Header=BB8_1 Depth=1 ; I486-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; I486-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; I486-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; I486-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; I486-NEXT: .LBB8_4: # %atomicrmw.start +; I486-NEXT: .LBB8_3: # %atomicrmw.start ; I486-NEXT: # in Loop: Header=BB8_1 Depth=1 ; I486-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; I486-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload @@ -565,8 +565,8 @@ define void @atomic_fetch_umax64(i64 %x) nounwind { ; I486-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; I486-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; I486-NEXT: je .LBB8_1 -; I486-NEXT: jmp .LBB8_2 -; I486-NEXT: .LBB8_2: # %atomicrmw.end +; I486-NEXT: jmp .LBB8_4 +; I486-NEXT: .LBB8_4: # %atomicrmw.end ; I486-NEXT: leal -4(%ebp), %esp ; I486-NEXT: popl %esi ; I486-NEXT: popl %ebp @@ -626,14 +626,14 @@ define void @atomic_fetch_umin64(i64 %x) nounwind { ; I486-NEXT: sbbl %eax, %edx ; I486-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; I486-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; I486-NEXT: jae .LBB9_4 -; I486-NEXT: # %bb.3: # %atomicrmw.start +; I486-NEXT: jae .LBB9_3 +; I486-NEXT: # %bb.2: # %atomicrmw.start ; I486-NEXT: # in Loop: Header=BB9_1 Depth=1 ; I486-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; I486-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; I486-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; I486-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; I486-NEXT: .LBB9_4: # %atomicrmw.start +; I486-NEXT: .LBB9_3: # %atomicrmw.start ; I486-NEXT: # in Loop: Header=BB9_1 Depth=1 ; I486-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; I486-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload @@ -657,8 +657,8 @@ define void @atomic_fetch_umin64(i64 %x) nounwind { ; I486-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; I486-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; I486-NEXT: je .LBB9_1 -; I486-NEXT: jmp .LBB9_2 -; I486-NEXT: .LBB9_2: # %atomicrmw.end +; I486-NEXT: jmp .LBB9_4 +; I486-NEXT: .LBB9_4: # %atomicrmw.end ; I486-NEXT: leal -4(%ebp), %esp ; I486-NEXT: popl %esi ; I486-NEXT: popl %ebp diff --git a/llvm/test/CodeGen/X86/atomicrmw-cond-sub-clamp.ll b/llvm/test/CodeGen/X86/atomicrmw-cond-sub-clamp.ll index 3e1a631e39b06..ef1da56d7eafd 100644 --- a/llvm/test/CodeGen/X86/atomicrmw-cond-sub-clamp.ll +++ b/llvm/test/CodeGen/X86/atomicrmw-cond-sub-clamp.ll @@ -8,21 +8,21 @@ define i8 @atomicrmw_usub_cond_i8(ptr %ptr, i8 %val) { ; CHECK-32-NEXT: movzbl {{[0-9]+}}(%esp), %ecx ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %edx ; CHECK-32-NEXT: movzbl (%edx), %eax -; CHECK-32-NEXT: jmp .LBB0_1 +; CHECK-32-NEXT: jmp .LBB0_2 ; CHECK-32-NEXT: .p2align 4 -; CHECK-32-NEXT: .LBB0_3: # %atomicrmw.start -; CHECK-32-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-32-NEXT: .LBB0_1: # %atomicrmw.start +; CHECK-32-NEXT: # in Loop: Header=BB0_2 Depth=1 ; CHECK-32-NEXT: lock cmpxchgb %ah, (%edx) ; CHECK-32-NEXT: je .LBB0_4 -; CHECK-32-NEXT: .LBB0_1: # %atomicrmw.start +; CHECK-32-NEXT: .LBB0_2: # %atomicrmw.start ; CHECK-32-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-32-NEXT: movb %al, %ah ; CHECK-32-NEXT: subb %cl, %ah -; CHECK-32-NEXT: jae .LBB0_3 -; CHECK-32-NEXT: # %bb.2: # %atomicrmw.start -; CHECK-32-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-32-NEXT: jae .LBB0_1 +; CHECK-32-NEXT: # %bb.3: # %atomicrmw.start +; CHECK-32-NEXT: # in Loop: Header=BB0_2 Depth=1 ; CHECK-32-NEXT: movb %al, %ah -; CHECK-32-NEXT: jmp .LBB0_3 +; CHECK-32-NEXT: jmp .LBB0_1 ; CHECK-32-NEXT: .LBB0_4: # %atomicrmw.end ; CHECK-32-NEXT: retl ; @@ -54,23 +54,23 @@ define i16 @atomicrmw_usub_cond_i16(ptr %ptr, i16 %val) { ; CHECK-32-NEXT: movzwl {{[0-9]+}}(%esp), %ecx ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %edx ; CHECK-32-NEXT: movzwl (%edx), %eax -; CHECK-32-NEXT: jmp .LBB1_1 +; CHECK-32-NEXT: jmp .LBB1_2 ; CHECK-32-NEXT: .p2align 4 -; CHECK-32-NEXT: .LBB1_3: # %atomicrmw.start -; CHECK-32-NEXT: # in Loop: Header=BB1_1 Depth=1 +; CHECK-32-NEXT: .LBB1_1: # %atomicrmw.start +; CHECK-32-NEXT: # in Loop: Header=BB1_2 Depth=1 ; CHECK-32-NEXT: # kill: def $ax killed $ax killed $eax ; CHECK-32-NEXT: lock cmpxchgw %si, (%edx) ; CHECK-32-NEXT: # kill: def $ax killed $ax def $eax ; CHECK-32-NEXT: je .LBB1_4 -; CHECK-32-NEXT: .LBB1_1: # %atomicrmw.start +; CHECK-32-NEXT: .LBB1_2: # %atomicrmw.start ; CHECK-32-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-32-NEXT: movl %eax, %esi ; CHECK-32-NEXT: subw %cx, %si -; CHECK-32-NEXT: jae .LBB1_3 -; CHECK-32-NEXT: # %bb.2: # %atomicrmw.start -; CHECK-32-NEXT: # in Loop: Header=BB1_1 Depth=1 +; CHECK-32-NEXT: jae .LBB1_1 +; CHECK-32-NEXT: # %bb.3: # %atomicrmw.start +; CHECK-32-NEXT: # in Loop: Header=BB1_2 Depth=1 ; CHECK-32-NEXT: movl %eax, %esi -; CHECK-32-NEXT: jmp .LBB1_3 +; CHECK-32-NEXT: jmp .LBB1_1 ; CHECK-32-NEXT: .LBB1_4: # %atomicrmw.end ; CHECK-32-NEXT: # kill: def $ax killed $ax killed $eax ; CHECK-32-NEXT: popl %esi @@ -106,21 +106,21 @@ define i32 @atomicrmw_usub_cond_i32(ptr %ptr, i32 %val) { ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %edx ; CHECK-32-NEXT: movl (%edx), %eax -; CHECK-32-NEXT: jmp .LBB2_1 +; CHECK-32-NEXT: jmp .LBB2_2 ; CHECK-32-NEXT: .p2align 4 -; CHECK-32-NEXT: .LBB2_3: # %atomicrmw.start -; CHECK-32-NEXT: # in Loop: Header=BB2_1 Depth=1 +; CHECK-32-NEXT: .LBB2_1: # %atomicrmw.start +; CHECK-32-NEXT: # in Loop: Header=BB2_2 Depth=1 ; CHECK-32-NEXT: lock cmpxchgl %esi, (%edx) ; CHECK-32-NEXT: je .LBB2_4 -; CHECK-32-NEXT: .LBB2_1: # %atomicrmw.start +; CHECK-32-NEXT: .LBB2_2: # %atomicrmw.start ; CHECK-32-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-32-NEXT: movl %eax, %esi ; CHECK-32-NEXT: subl %ecx, %esi -; CHECK-32-NEXT: jae .LBB2_3 -; CHECK-32-NEXT: # %bb.2: # %atomicrmw.start -; CHECK-32-NEXT: # in Loop: Header=BB2_1 Depth=1 +; CHECK-32-NEXT: jae .LBB2_1 +; CHECK-32-NEXT: # %bb.3: # %atomicrmw.start +; CHECK-32-NEXT: # in Loop: Header=BB2_2 Depth=1 ; CHECK-32-NEXT: movl %eax, %esi -; CHECK-32-NEXT: jmp .LBB2_3 +; CHECK-32-NEXT: jmp .LBB2_1 ; CHECK-32-NEXT: .LBB2_4: # %atomicrmw.end ; CHECK-32-NEXT: popl %esi ; CHECK-32-NEXT: .cfi_def_cfa_offset 4 @@ -163,24 +163,24 @@ define i64 @atomicrmw_usub_cond_i64(ptr %ptr, i64 %val) { ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %ebp ; CHECK-32-NEXT: movl (%ebp), %eax ; CHECK-32-NEXT: movl 4(%ebp), %edx -; CHECK-32-NEXT: jmp .LBB3_1 +; CHECK-32-NEXT: jmp .LBB3_2 ; CHECK-32-NEXT: .p2align 4 -; CHECK-32-NEXT: .LBB3_3: # %atomicrmw.start -; CHECK-32-NEXT: # in Loop: Header=BB3_1 Depth=1 +; CHECK-32-NEXT: .LBB3_1: # %atomicrmw.start +; CHECK-32-NEXT: # in Loop: Header=BB3_2 Depth=1 ; CHECK-32-NEXT: lock cmpxchg8b (%ebp) ; CHECK-32-NEXT: je .LBB3_4 -; CHECK-32-NEXT: .LBB3_1: # %atomicrmw.start +; CHECK-32-NEXT: .LBB3_2: # %atomicrmw.start ; CHECK-32-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-32-NEXT: movl %eax, %ebx ; CHECK-32-NEXT: subl %edi, %ebx ; CHECK-32-NEXT: movl %edx, %ecx ; CHECK-32-NEXT: sbbl %esi, %ecx -; CHECK-32-NEXT: jae .LBB3_3 -; CHECK-32-NEXT: # %bb.2: # %atomicrmw.start -; CHECK-32-NEXT: # in Loop: Header=BB3_1 Depth=1 +; CHECK-32-NEXT: jae .LBB3_1 +; CHECK-32-NEXT: # %bb.3: # %atomicrmw.start +; CHECK-32-NEXT: # in Loop: Header=BB3_2 Depth=1 ; CHECK-32-NEXT: movl %edx, %ecx ; CHECK-32-NEXT: movl %eax, %ebx -; CHECK-32-NEXT: jmp .LBB3_3 +; CHECK-32-NEXT: jmp .LBB3_1 ; CHECK-32-NEXT: .LBB3_4: # %atomicrmw.end ; CHECK-32-NEXT: popl %esi ; CHECK-32-NEXT: .cfi_def_cfa_offset 16 @@ -218,20 +218,20 @@ define i8 @atomicrmw_usub_sat_i8(ptr %ptr, i8 %val) { ; CHECK-32-NEXT: movzbl {{[0-9]+}}(%esp), %ecx ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %edx ; CHECK-32-NEXT: movzbl (%edx), %eax -; CHECK-32-NEXT: jmp .LBB4_1 +; CHECK-32-NEXT: jmp .LBB4_2 ; CHECK-32-NEXT: .p2align 4 -; CHECK-32-NEXT: .LBB4_3: # %atomicrmw.start -; CHECK-32-NEXT: # in Loop: Header=BB4_1 Depth=1 +; CHECK-32-NEXT: .LBB4_1: # %atomicrmw.start +; CHECK-32-NEXT: # in Loop: Header=BB4_2 Depth=1 ; CHECK-32-NEXT: lock cmpxchgb %bl, (%edx) ; CHECK-32-NEXT: je .LBB4_4 -; CHECK-32-NEXT: .LBB4_1: # %atomicrmw.start +; CHECK-32-NEXT: .LBB4_2: # %atomicrmw.start ; CHECK-32-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-32-NEXT: movl %eax, %ebx ; CHECK-32-NEXT: subb %cl, %bl -; CHECK-32-NEXT: jae .LBB4_3 -; CHECK-32-NEXT: # %bb.2: # in Loop: Header=BB4_1 Depth=1 +; CHECK-32-NEXT: jae .LBB4_1 +; CHECK-32-NEXT: # %bb.3: # in Loop: Header=BB4_2 Depth=1 ; CHECK-32-NEXT: xorl %ebx, %ebx -; CHECK-32-NEXT: jmp .LBB4_3 +; CHECK-32-NEXT: jmp .LBB4_1 ; CHECK-32-NEXT: .LBB4_4: # %atomicrmw.end ; CHECK-32-NEXT: popl %ebx ; CHECK-32-NEXT: .cfi_def_cfa_offset 4 @@ -268,22 +268,22 @@ define i16 @atomicrmw_usub_sat_i16(ptr %ptr, i16 %val) { ; CHECK-32-NEXT: movzwl {{[0-9]+}}(%esp), %ecx ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %edx ; CHECK-32-NEXT: movzwl (%edx), %eax -; CHECK-32-NEXT: jmp .LBB5_1 +; CHECK-32-NEXT: jmp .LBB5_2 ; CHECK-32-NEXT: .p2align 4 -; CHECK-32-NEXT: .LBB5_3: # %atomicrmw.start -; CHECK-32-NEXT: # in Loop: Header=BB5_1 Depth=1 +; CHECK-32-NEXT: .LBB5_1: # %atomicrmw.start +; CHECK-32-NEXT: # in Loop: Header=BB5_2 Depth=1 ; CHECK-32-NEXT: lock cmpxchgw %si, (%edx) ; CHECK-32-NEXT: je .LBB5_4 -; CHECK-32-NEXT: .LBB5_1: # %atomicrmw.start +; CHECK-32-NEXT: .LBB5_2: # %atomicrmw.start ; CHECK-32-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-32-NEXT: xorl %esi, %esi ; CHECK-32-NEXT: movl %eax, %edi ; CHECK-32-NEXT: subw %cx, %di -; CHECK-32-NEXT: jb .LBB5_3 -; CHECK-32-NEXT: # %bb.2: # %atomicrmw.start -; CHECK-32-NEXT: # in Loop: Header=BB5_1 Depth=1 +; CHECK-32-NEXT: jb .LBB5_1 +; CHECK-32-NEXT: # %bb.3: # %atomicrmw.start +; CHECK-32-NEXT: # in Loop: Header=BB5_2 Depth=1 ; CHECK-32-NEXT: movl %edi, %esi -; CHECK-32-NEXT: jmp .LBB5_3 +; CHECK-32-NEXT: jmp .LBB5_1 ; CHECK-32-NEXT: .LBB5_4: # %atomicrmw.end ; CHECK-32-NEXT: popl %esi ; CHECK-32-NEXT: .cfi_def_cfa_offset 8 @@ -321,22 +321,22 @@ define i32 @atomicrmw_usub_sat_i32(ptr %ptr, i32 %val) { ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %edx ; CHECK-32-NEXT: movl (%edx), %eax -; CHECK-32-NEXT: jmp .LBB6_1 +; CHECK-32-NEXT: jmp .LBB6_2 ; CHECK-32-NEXT: .p2align 4 -; CHECK-32-NEXT: .LBB6_3: # %atomicrmw.start -; CHECK-32-NEXT: # in Loop: Header=BB6_1 Depth=1 +; CHECK-32-NEXT: .LBB6_1: # %atomicrmw.start +; CHECK-32-NEXT: # in Loop: Header=BB6_2 Depth=1 ; CHECK-32-NEXT: lock cmpxchgl %esi, (%edx) ; CHECK-32-NEXT: je .LBB6_4 -; CHECK-32-NEXT: .LBB6_1: # %atomicrmw.start +; CHECK-32-NEXT: .LBB6_2: # %atomicrmw.start ; CHECK-32-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-32-NEXT: xorl %esi, %esi ; CHECK-32-NEXT: movl %eax, %edi ; CHECK-32-NEXT: subl %ecx, %edi -; CHECK-32-NEXT: jb .LBB6_3 -; CHECK-32-NEXT: # %bb.2: # %atomicrmw.start -; CHECK-32-NEXT: # in Loop: Header=BB6_1 Depth=1 +; CHECK-32-NEXT: jb .LBB6_1 +; CHECK-32-NEXT: # %bb.3: # %atomicrmw.start +; CHECK-32-NEXT: # in Loop: Header=BB6_2 Depth=1 ; CHECK-32-NEXT: movl %edi, %esi -; CHECK-32-NEXT: jmp .LBB6_3 +; CHECK-32-NEXT: jmp .LBB6_1 ; CHECK-32-NEXT: .LBB6_4: # %atomicrmw.end ; CHECK-32-NEXT: popl %esi ; CHECK-32-NEXT: .cfi_def_cfa_offset 8 @@ -380,17 +380,17 @@ define i64 @atomicrmw_usub_sat_i64(ptr %ptr, i64 %val) { ; CHECK-32-NEXT: movl {{[0-9]+}}(%esp), %ebp ; CHECK-32-NEXT: movl (%ebp), %esi ; CHECK-32-NEXT: movl 4(%ebp), %edi -; CHECK-32-NEXT: jmp .LBB7_1 +; CHECK-32-NEXT: jmp .LBB7_2 ; CHECK-32-NEXT: .p2align 4 -; CHECK-32-NEXT: .LBB7_3: # %atomicrmw.start -; CHECK-32-NEXT: # in Loop: Header=BB7_1 Depth=1 +; CHECK-32-NEXT: .LBB7_1: # %atomicrmw.start +; CHECK-32-NEXT: # in Loop: Header=BB7_2 Depth=1 ; CHECK-32-NEXT: movl %esi, %eax ; CHECK-32-NEXT: movl %edi, %edx ; CHECK-32-NEXT: lock cmpxchg8b (%ebp) ; CHECK-32-NEXT: movl %eax, %esi ; CHECK-32-NEXT: movl %edx, %edi ; CHECK-32-NEXT: je .LBB7_4 -; CHECK-32-NEXT: .LBB7_1: # %atomicrmw.start +; CHECK-32-NEXT: .LBB7_2: # %atomicrmw.start ; CHECK-32-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-32-NEXT: xorl %ecx, %ecx ; CHECK-32-NEXT: movl %esi, %eax @@ -398,12 +398,12 @@ define i64 @atomicrmw_usub_sat_i64(ptr %ptr, i64 %val) { ; CHECK-32-NEXT: movl %edi, %edx ; CHECK-32-NEXT: sbbl {{[0-9]+}}(%esp), %edx ; CHECK-32-NEXT: movl $0, %ebx -; CHECK-32-NEXT: jb .LBB7_3 -; CHECK-32-NEXT: # %bb.2: # %atomicrmw.start -; CHECK-32-NEXT: # in Loop: Header=BB7_1 Depth=1 +; CHECK-32-NEXT: jb .LBB7_1 +; CHECK-32-NEXT: # %bb.3: # %atomicrmw.start +; CHECK-32-NEXT: # in Loop: Header=BB7_2 Depth=1 ; CHECK-32-NEXT: movl %edx, %ecx ; CHECK-32-NEXT: movl %eax, %ebx -; CHECK-32-NEXT: jmp .LBB7_3 +; CHECK-32-NEXT: jmp .LBB7_1 ; CHECK-32-NEXT: .LBB7_4: # %atomicrmw.end ; CHECK-32-NEXT: movl %esi, %eax ; CHECK-32-NEXT: movl %edi, %edx diff --git a/llvm/test/CodeGen/X86/avx2-masked-gather.ll b/llvm/test/CodeGen/X86/avx2-masked-gather.ll index 2429536bdb15f..25c85926e39ba 100644 --- a/llvm/test/CodeGen/X86/avx2-masked-gather.ll +++ b/llvm/test/CodeGen/X86/avx2-masked-gather.ll @@ -32,19 +32,19 @@ define <2 x i32> @masked_gather_v2i32(ptr %ptr, <2 x i1> %masks, <2 x i32> %pass ; NOGATHER-NEXT: vpsllq $63, %xmm0, %xmm0 ; NOGATHER-NEXT: vmovmskpd %xmm0, %eax ; NOGATHER-NEXT: testb $1, %al -; NOGATHER-NEXT: jne .LBB0_1 -; NOGATHER-NEXT: # %bb.2: # %else -; NOGATHER-NEXT: testb $2, %al ; NOGATHER-NEXT: jne .LBB0_3 -; NOGATHER-NEXT: .LBB0_4: # %else2 +; NOGATHER-NEXT: # %bb.1: # %else +; NOGATHER-NEXT: testb $2, %al +; NOGATHER-NEXT: jne .LBB0_4 +; NOGATHER-NEXT: .LBB0_2: # %else2 ; NOGATHER-NEXT: vmovdqa %xmm1, %xmm0 ; NOGATHER-NEXT: retq -; NOGATHER-NEXT: .LBB0_1: # %cond.load +; NOGATHER-NEXT: .LBB0_3: # %cond.load ; NOGATHER-NEXT: vmovq %xmm2, %rcx ; NOGATHER-NEXT: vpinsrd $0, (%rcx), %xmm1, %xmm1 ; NOGATHER-NEXT: testb $2, %al -; NOGATHER-NEXT: je .LBB0_4 -; NOGATHER-NEXT: .LBB0_3: # %cond.load1 +; NOGATHER-NEXT: je .LBB0_2 +; NOGATHER-NEXT: .LBB0_4: # %cond.load1 ; NOGATHER-NEXT: vpextrq $1, %xmm2, %rax ; NOGATHER-NEXT: vpinsrd $1, (%rax), %xmm1, %xmm1 ; NOGATHER-NEXT: vmovdqa %xmm1, %xmm0 @@ -81,19 +81,19 @@ define <4 x i32> @masked_gather_v2i32_concat(ptr %ptr, <2 x i1> %masks, <2 x i32 ; NOGATHER-NEXT: vpsllq $63, %xmm0, %xmm0 ; NOGATHER-NEXT: vmovmskpd %xmm0, %eax ; NOGATHER-NEXT: testb $1, %al -; NOGATHER-NEXT: jne .LBB1_1 -; NOGATHER-NEXT: # %bb.2: # %else -; NOGATHER-NEXT: testb $2, %al ; NOGATHER-NEXT: jne .LBB1_3 -; NOGATHER-NEXT: .LBB1_4: # %else2 +; NOGATHER-NEXT: # %bb.1: # %else +; NOGATHER-NEXT: testb $2, %al +; NOGATHER-NEXT: jne .LBB1_4 +; NOGATHER-NEXT: .LBB1_2: # %else2 ; NOGATHER-NEXT: vmovdqa %xmm1, %xmm0 ; NOGATHER-NEXT: retq -; NOGATHER-NEXT: .LBB1_1: # %cond.load +; NOGATHER-NEXT: .LBB1_3: # %cond.load ; NOGATHER-NEXT: vmovq %xmm2, %rcx ; NOGATHER-NEXT: vpinsrd $0, (%rcx), %xmm1, %xmm1 ; NOGATHER-NEXT: testb $2, %al -; NOGATHER-NEXT: je .LBB1_4 -; NOGATHER-NEXT: .LBB1_3: # %cond.load1 +; NOGATHER-NEXT: je .LBB1_2 +; NOGATHER-NEXT: .LBB1_4: # %cond.load1 ; NOGATHER-NEXT: vpextrq $1, %xmm2, %rax ; NOGATHER-NEXT: vpinsrd $1, (%rax), %xmm1, %xmm1 ; NOGATHER-NEXT: vmovdqa %xmm1, %xmm0 @@ -133,20 +133,20 @@ define <2 x float> @masked_gather_v2float(ptr %ptr, <2 x i1> %masks, <2 x float> ; NOGATHER-NEXT: vpsllq $63, %xmm0, %xmm0 ; NOGATHER-NEXT: vmovmskpd %xmm0, %eax ; NOGATHER-NEXT: testb $1, %al -; NOGATHER-NEXT: jne .LBB2_1 -; NOGATHER-NEXT: # %bb.2: # %else -; NOGATHER-NEXT: testb $2, %al ; NOGATHER-NEXT: jne .LBB2_3 -; NOGATHER-NEXT: .LBB2_4: # %else2 +; NOGATHER-NEXT: # %bb.1: # %else +; NOGATHER-NEXT: testb $2, %al +; NOGATHER-NEXT: jne .LBB2_4 +; NOGATHER-NEXT: .LBB2_2: # %else2 ; NOGATHER-NEXT: vmovaps %xmm1, %xmm0 ; NOGATHER-NEXT: retq -; NOGATHER-NEXT: .LBB2_1: # %cond.load +; NOGATHER-NEXT: .LBB2_3: # %cond.load ; NOGATHER-NEXT: vmovq %xmm2, %rcx ; NOGATHER-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; NOGATHER-NEXT: vblendps {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3] ; NOGATHER-NEXT: testb $2, %al -; NOGATHER-NEXT: je .LBB2_4 -; NOGATHER-NEXT: .LBB2_3: # %cond.load1 +; NOGATHER-NEXT: je .LBB2_2 +; NOGATHER-NEXT: .LBB2_4: # %cond.load1 ; NOGATHER-NEXT: vpextrq $1, %xmm2, %rax ; NOGATHER-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[2,3] ; NOGATHER-NEXT: vmovaps %xmm1, %xmm0 @@ -183,20 +183,20 @@ define <4 x float> @masked_gather_v2float_concat(ptr %ptr, <2 x i1> %masks, <2 x ; NOGATHER-NEXT: vpsllq $63, %xmm0, %xmm0 ; NOGATHER-NEXT: vmovmskpd %xmm0, %eax ; NOGATHER-NEXT: testb $1, %al -; NOGATHER-NEXT: jne .LBB3_1 -; NOGATHER-NEXT: # %bb.2: # %else -; NOGATHER-NEXT: testb $2, %al ; NOGATHER-NEXT: jne .LBB3_3 -; NOGATHER-NEXT: .LBB3_4: # %else2 +; NOGATHER-NEXT: # %bb.1: # %else +; NOGATHER-NEXT: testb $2, %al +; NOGATHER-NEXT: jne .LBB3_4 +; NOGATHER-NEXT: .LBB3_2: # %else2 ; NOGATHER-NEXT: vmovaps %xmm1, %xmm0 ; NOGATHER-NEXT: retq -; NOGATHER-NEXT: .LBB3_1: # %cond.load +; NOGATHER-NEXT: .LBB3_3: # %cond.load ; NOGATHER-NEXT: vmovq %xmm2, %rcx ; NOGATHER-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; NOGATHER-NEXT: vblendps {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3] ; NOGATHER-NEXT: testb $2, %al -; NOGATHER-NEXT: je .LBB3_4 -; NOGATHER-NEXT: .LBB3_3: # %cond.load1 +; NOGATHER-NEXT: je .LBB3_2 +; NOGATHER-NEXT: .LBB3_4: # %cond.load1 ; NOGATHER-NEXT: vpextrq $1, %xmm2, %rax ; NOGATHER-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[2,3] ; NOGATHER-NEXT: vmovaps %xmm1, %xmm0 @@ -245,20 +245,20 @@ define <4 x i32> @masked_gather_v4i32(<4 x ptr> %ptrs, <4 x i1> %masks, <4 x i32 ; NOGATHER-NEXT: .LBB4_4: # %else2 ; NOGATHER-NEXT: vextractf128 $1, %ymm0, %xmm0 ; NOGATHER-NEXT: testb $4, %al -; NOGATHER-NEXT: jne .LBB4_5 -; NOGATHER-NEXT: # %bb.6: # %else5 -; NOGATHER-NEXT: testb $8, %al ; NOGATHER-NEXT: jne .LBB4_7 -; NOGATHER-NEXT: .LBB4_8: # %else8 +; NOGATHER-NEXT: # %bb.5: # %else5 +; NOGATHER-NEXT: testb $8, %al +; NOGATHER-NEXT: jne .LBB4_8 +; NOGATHER-NEXT: .LBB4_6: # %else8 ; NOGATHER-NEXT: vmovdqa %xmm2, %xmm0 ; NOGATHER-NEXT: vzeroupper ; NOGATHER-NEXT: retq -; NOGATHER-NEXT: .LBB4_5: # %cond.load4 +; NOGATHER-NEXT: .LBB4_7: # %cond.load4 ; NOGATHER-NEXT: vmovq %xmm0, %rcx ; NOGATHER-NEXT: vpinsrd $2, (%rcx), %xmm2, %xmm2 ; NOGATHER-NEXT: testb $8, %al -; NOGATHER-NEXT: je .LBB4_8 -; NOGATHER-NEXT: .LBB4_7: # %cond.load7 +; NOGATHER-NEXT: je .LBB4_6 +; NOGATHER-NEXT: .LBB4_8: # %cond.load7 ; NOGATHER-NEXT: vpextrq $1, %xmm0, %rax ; NOGATHER-NEXT: vpinsrd $3, (%rax), %xmm2, %xmm2 ; NOGATHER-NEXT: vmovdqa %xmm2, %xmm0 @@ -306,20 +306,20 @@ define <4 x float> @masked_gather_v4float(<4 x ptr> %ptrs, <4 x i1> %masks, <4 x ; NOGATHER-NEXT: .LBB5_4: # %else2 ; NOGATHER-NEXT: vextractf128 $1, %ymm0, %xmm0 ; NOGATHER-NEXT: testb $4, %al -; NOGATHER-NEXT: jne .LBB5_5 -; NOGATHER-NEXT: # %bb.6: # %else5 -; NOGATHER-NEXT: testb $8, %al ; NOGATHER-NEXT: jne .LBB5_7 -; NOGATHER-NEXT: .LBB5_8: # %else8 +; NOGATHER-NEXT: # %bb.5: # %else5 +; NOGATHER-NEXT: testb $8, %al +; NOGATHER-NEXT: jne .LBB5_8 +; NOGATHER-NEXT: .LBB5_6: # %else8 ; NOGATHER-NEXT: vmovaps %xmm2, %xmm0 ; NOGATHER-NEXT: vzeroupper ; NOGATHER-NEXT: retq -; NOGATHER-NEXT: .LBB5_5: # %cond.load4 +; NOGATHER-NEXT: .LBB5_7: # %cond.load4 ; NOGATHER-NEXT: vmovq %xmm0, %rcx ; NOGATHER-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3] ; NOGATHER-NEXT: testb $8, %al -; NOGATHER-NEXT: je .LBB5_8 -; NOGATHER-NEXT: .LBB5_7: # %cond.load7 +; NOGATHER-NEXT: je .LBB5_6 +; NOGATHER-NEXT: .LBB5_8: # %cond.load7 ; NOGATHER-NEXT: vpextrq $1, %xmm0, %rax ; NOGATHER-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],mem[0] ; NOGATHER-NEXT: vmovaps %xmm2, %xmm0 @@ -408,20 +408,20 @@ define <8 x i32> @masked_gather_v8i32(ptr %ptr, <8 x i1> %masks, <8 x i32> %pass ; NOGATHER-NEXT: .LBB6_12: # %else14 ; NOGATHER-NEXT: vextractf128 $1, %ymm0, %xmm0 ; NOGATHER-NEXT: testb $64, %al -; NOGATHER-NEXT: jne .LBB6_13 -; NOGATHER-NEXT: # %bb.14: # %else17 -; NOGATHER-NEXT: testb $-128, %al ; NOGATHER-NEXT: jne .LBB6_15 -; NOGATHER-NEXT: .LBB6_16: # %else20 +; NOGATHER-NEXT: # %bb.13: # %else17 +; NOGATHER-NEXT: testb $-128, %al +; NOGATHER-NEXT: jne .LBB6_16 +; NOGATHER-NEXT: .LBB6_14: # %else20 ; NOGATHER-NEXT: vmovaps %ymm1, %ymm0 ; NOGATHER-NEXT: retq -; NOGATHER-NEXT: .LBB6_13: # %cond.load16 +; NOGATHER-NEXT: .LBB6_15: # %cond.load16 ; NOGATHER-NEXT: vmovq %xmm0, %rcx ; NOGATHER-NEXT: vbroadcastss (%rcx), %ymm2 ; NOGATHER-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1,2,3,4,5],ymm2[6],ymm1[7] ; NOGATHER-NEXT: testb $-128, %al -; NOGATHER-NEXT: je .LBB6_16 -; NOGATHER-NEXT: .LBB6_15: # %cond.load19 +; NOGATHER-NEXT: je .LBB6_14 +; NOGATHER-NEXT: .LBB6_16: # %cond.load19 ; NOGATHER-NEXT: vpextrq $1, %xmm0, %rax ; NOGATHER-NEXT: vbroadcastss (%rax), %ymm0 ; NOGATHER-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1,2,3,4,5,6],ymm0[7] @@ -511,20 +511,20 @@ define <8 x float> @masked_gather_v8float(ptr %ptr, <8 x i1> %masks, <8 x float> ; NOGATHER-NEXT: .LBB7_12: # %else14 ; NOGATHER-NEXT: vextractf128 $1, %ymm0, %xmm0 ; NOGATHER-NEXT: testb $64, %al -; NOGATHER-NEXT: jne .LBB7_13 -; NOGATHER-NEXT: # %bb.14: # %else17 -; NOGATHER-NEXT: testb $-128, %al ; NOGATHER-NEXT: jne .LBB7_15 -; NOGATHER-NEXT: .LBB7_16: # %else20 +; NOGATHER-NEXT: # %bb.13: # %else17 +; NOGATHER-NEXT: testb $-128, %al +; NOGATHER-NEXT: jne .LBB7_16 +; NOGATHER-NEXT: .LBB7_14: # %else20 ; NOGATHER-NEXT: vmovaps %ymm1, %ymm0 ; NOGATHER-NEXT: retq -; NOGATHER-NEXT: .LBB7_13: # %cond.load16 +; NOGATHER-NEXT: .LBB7_15: # %cond.load16 ; NOGATHER-NEXT: vmovq %xmm0, %rcx ; NOGATHER-NEXT: vbroadcastss (%rcx), %ymm2 ; NOGATHER-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1,2,3,4,5],ymm2[6],ymm1[7] ; NOGATHER-NEXT: testb $-128, %al -; NOGATHER-NEXT: je .LBB7_16 -; NOGATHER-NEXT: .LBB7_15: # %cond.load19 +; NOGATHER-NEXT: je .LBB7_14 +; NOGATHER-NEXT: .LBB7_16: # %cond.load19 ; NOGATHER-NEXT: vpextrq $1, %xmm0, %rax ; NOGATHER-NEXT: vbroadcastss (%rax), %ymm0 ; NOGATHER-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1,2,3,4,5,6],ymm0[7] @@ -579,20 +579,20 @@ define <4 x i64> @masked_gather_v4i64(ptr %ptr, <4 x i1> %masks, <4 x i64> %pass ; NOGATHER-NEXT: .LBB8_4: # %else2 ; NOGATHER-NEXT: vextractf128 $1, %ymm2, %xmm0 ; NOGATHER-NEXT: testb $4, %al -; NOGATHER-NEXT: jne .LBB8_5 -; NOGATHER-NEXT: # %bb.6: # %else5 -; NOGATHER-NEXT: testb $8, %al ; NOGATHER-NEXT: jne .LBB8_7 -; NOGATHER-NEXT: .LBB8_8: # %else8 +; NOGATHER-NEXT: # %bb.5: # %else5 +; NOGATHER-NEXT: testb $8, %al +; NOGATHER-NEXT: jne .LBB8_8 +; NOGATHER-NEXT: .LBB8_6: # %else8 ; NOGATHER-NEXT: vmovaps %ymm1, %ymm0 ; NOGATHER-NEXT: retq -; NOGATHER-NEXT: .LBB8_5: # %cond.load4 +; NOGATHER-NEXT: .LBB8_7: # %cond.load4 ; NOGATHER-NEXT: vmovq %xmm0, %rcx ; NOGATHER-NEXT: vbroadcastsd (%rcx), %ymm2 ; NOGATHER-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm2[4,5],ymm1[6,7] ; NOGATHER-NEXT: testb $8, %al -; NOGATHER-NEXT: je .LBB8_8 -; NOGATHER-NEXT: .LBB8_7: # %cond.load7 +; NOGATHER-NEXT: je .LBB8_6 +; NOGATHER-NEXT: .LBB8_8: # %cond.load7 ; NOGATHER-NEXT: vpextrq $1, %xmm0, %rax ; NOGATHER-NEXT: vbroadcastsd (%rax), %ymm0 ; NOGATHER-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1,2,3,4,5],ymm0[6,7] @@ -647,20 +647,20 @@ define <4 x double> @masked_gather_v4double(ptr %ptr, <4 x i1> %masks, <4 x doub ; NOGATHER-NEXT: .LBB9_4: # %else2 ; NOGATHER-NEXT: vextractf128 $1, %ymm2, %xmm0 ; NOGATHER-NEXT: testb $4, %al -; NOGATHER-NEXT: jne .LBB9_5 -; NOGATHER-NEXT: # %bb.6: # %else5 -; NOGATHER-NEXT: testb $8, %al ; NOGATHER-NEXT: jne .LBB9_7 -; NOGATHER-NEXT: .LBB9_8: # %else8 +; NOGATHER-NEXT: # %bb.5: # %else5 +; NOGATHER-NEXT: testb $8, %al +; NOGATHER-NEXT: jne .LBB9_8 +; NOGATHER-NEXT: .LBB9_6: # %else8 ; NOGATHER-NEXT: vmovaps %ymm1, %ymm0 ; NOGATHER-NEXT: retq -; NOGATHER-NEXT: .LBB9_5: # %cond.load4 +; NOGATHER-NEXT: .LBB9_7: # %cond.load4 ; NOGATHER-NEXT: vmovq %xmm0, %rcx ; NOGATHER-NEXT: vbroadcastsd (%rcx), %ymm2 ; NOGATHER-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm2[4,5],ymm1[6,7] ; NOGATHER-NEXT: testb $8, %al -; NOGATHER-NEXT: je .LBB9_8 -; NOGATHER-NEXT: .LBB9_7: # %cond.load7 +; NOGATHER-NEXT: je .LBB9_6 +; NOGATHER-NEXT: .LBB9_8: # %cond.load7 ; NOGATHER-NEXT: vpextrq $1, %xmm0, %rax ; NOGATHER-NEXT: vbroadcastsd (%rax), %ymm0 ; NOGATHER-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1,2,3,4,5],ymm0[6,7] @@ -698,19 +698,19 @@ define <2 x i64> @masked_gather_v2i64(ptr %ptr, <2 x i1> %masks, <2 x i64> %pass ; NOGATHER-NEXT: vpsllq $63, %xmm0, %xmm0 ; NOGATHER-NEXT: vmovmskpd %xmm0, %eax ; NOGATHER-NEXT: testb $1, %al -; NOGATHER-NEXT: jne .LBB10_1 -; NOGATHER-NEXT: # %bb.2: # %else -; NOGATHER-NEXT: testb $2, %al ; NOGATHER-NEXT: jne .LBB10_3 -; NOGATHER-NEXT: .LBB10_4: # %else2 +; NOGATHER-NEXT: # %bb.1: # %else +; NOGATHER-NEXT: testb $2, %al +; NOGATHER-NEXT: jne .LBB10_4 +; NOGATHER-NEXT: .LBB10_2: # %else2 ; NOGATHER-NEXT: vmovdqa %xmm1, %xmm0 ; NOGATHER-NEXT: retq -; NOGATHER-NEXT: .LBB10_1: # %cond.load +; NOGATHER-NEXT: .LBB10_3: # %cond.load ; NOGATHER-NEXT: vmovq %xmm2, %rcx ; NOGATHER-NEXT: vpinsrq $0, (%rcx), %xmm1, %xmm1 ; NOGATHER-NEXT: testb $2, %al -; NOGATHER-NEXT: je .LBB10_4 -; NOGATHER-NEXT: .LBB10_3: # %cond.load1 +; NOGATHER-NEXT: je .LBB10_2 +; NOGATHER-NEXT: .LBB10_4: # %cond.load1 ; NOGATHER-NEXT: vpextrq $1, %xmm2, %rax ; NOGATHER-NEXT: vpinsrq $1, (%rax), %xmm1, %xmm1 ; NOGATHER-NEXT: vmovdqa %xmm1, %xmm0 @@ -747,19 +747,19 @@ define <2 x double> @masked_gather_v2double(ptr %ptr, <2 x i1> %masks, <2 x doub ; NOGATHER-NEXT: vpsllq $63, %xmm0, %xmm0 ; NOGATHER-NEXT: vmovmskpd %xmm0, %eax ; NOGATHER-NEXT: testb $1, %al -; NOGATHER-NEXT: jne .LBB11_1 -; NOGATHER-NEXT: # %bb.2: # %else -; NOGATHER-NEXT: testb $2, %al ; NOGATHER-NEXT: jne .LBB11_3 -; NOGATHER-NEXT: .LBB11_4: # %else2 +; NOGATHER-NEXT: # %bb.1: # %else +; NOGATHER-NEXT: testb $2, %al +; NOGATHER-NEXT: jne .LBB11_4 +; NOGATHER-NEXT: .LBB11_2: # %else2 ; NOGATHER-NEXT: vmovaps %xmm1, %xmm0 ; NOGATHER-NEXT: retq -; NOGATHER-NEXT: .LBB11_1: # %cond.load +; NOGATHER-NEXT: .LBB11_3: # %cond.load ; NOGATHER-NEXT: vmovq %xmm2, %rcx ; NOGATHER-NEXT: vmovlps {{.*#+}} xmm1 = mem[0,1],xmm1[2,3] ; NOGATHER-NEXT: testb $2, %al -; NOGATHER-NEXT: je .LBB11_4 -; NOGATHER-NEXT: .LBB11_3: # %cond.load1 +; NOGATHER-NEXT: je .LBB11_2 +; NOGATHER-NEXT: .LBB11_4: # %cond.load1 ; NOGATHER-NEXT: vpextrq $1, %xmm2, %rax ; NOGATHER-NEXT: vmovhps {{.*#+}} xmm1 = xmm1[0,1],mem[0,1] ; NOGATHER-NEXT: vmovaps %xmm1, %xmm0 diff --git a/llvm/test/CodeGen/X86/avx2-vbroadcast.ll b/llvm/test/CodeGen/X86/avx2-vbroadcast.ll index c50af6968f5bb..fea75176a54f8 100644 --- a/llvm/test/CodeGen/X86/avx2-vbroadcast.ll +++ b/llvm/test/CodeGen/X86/avx2-vbroadcast.ll @@ -680,25 +680,25 @@ define void @crash() nounwind alwaysinline { ; X86: ## %bb.0: ## %WGLoopsEntry ; X86-NEXT: xorl %eax, %eax ; X86-NEXT: testb %al, %al -; X86-NEXT: je LBB33_1 -; X86-NEXT: ## %bb.2: ## %ret +; X86-NEXT: je LBB33_2 +; X86-NEXT: ## %bb.1: ## %ret ; X86-NEXT: retl ; X86-NEXT: .p2align 4 -; X86-NEXT: LBB33_1: ## %footer329VF +; X86-NEXT: LBB33_2: ## %footer329VF ; X86-NEXT: ## =>This Inner Loop Header: Depth=1 -; X86-NEXT: jmp LBB33_1 +; X86-NEXT: jmp LBB33_2 ; ; X64-LABEL: crash: ; X64: ## %bb.0: ## %WGLoopsEntry ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: testb %al, %al -; X64-NEXT: je LBB33_1 -; X64-NEXT: ## %bb.2: ## %ret +; X64-NEXT: je LBB33_2 +; X64-NEXT: ## %bb.1: ## %ret ; X64-NEXT: retq ; X64-NEXT: .p2align 4 -; X64-NEXT: LBB33_1: ## %footer329VF +; X64-NEXT: LBB33_2: ## %footer329VF ; X64-NEXT: ## =>This Inner Loop Header: Depth=1 -; X64-NEXT: jmp LBB33_1 +; X64-NEXT: jmp LBB33_2 WGLoopsEntry: br i1 undef, label %ret, label %footer329VF diff --git a/llvm/test/CodeGen/X86/avx512-cmp.ll b/llvm/test/CodeGen/X86/avx512-cmp.ll index ac099b5c6718e..9f0252c38c062 100644 --- a/llvm/test/CodeGen/X86/avx512-cmp.ll +++ b/llvm/test/CodeGen/X86/avx512-cmp.ll @@ -64,11 +64,11 @@ define float @test5(float %p) #0 { ; ALL: ## %bb.0: ## %entry ; ALL-NEXT: vxorps %xmm1, %xmm1, %xmm1 ; ALL-NEXT: vucomiss %xmm1, %xmm0 -; ALL-NEXT: jne LBB3_1 -; ALL-NEXT: jp LBB3_1 -; ALL-NEXT: ## %bb.2: ## %return +; ALL-NEXT: jne LBB3_2 +; ALL-NEXT: jp LBB3_2 +; ALL-NEXT: ## %bb.1: ## %return ; ALL-NEXT: retq -; ALL-NEXT: LBB3_1: ## %if.end +; ALL-NEXT: LBB3_2: ## %if.end ; ALL-NEXT: vcmpltss %xmm0, %xmm1, %k1 ; ALL-NEXT: vmovss {{.*#+}} xmm0 = [-1.0E+0,0.0E+0,0.0E+0,0.0E+0] ; ALL-NEXT: vmovss {{.*#+}} xmm0 {%k1} = [1.0E+0,0.0E+0,0.0E+0,0.0E+0] @@ -159,11 +159,11 @@ define i32 @test10(i64 %b, i64 %c, i1 %d) { ; ALL-NEXT: cmpq %rsi, %rdi ; ALL-NEXT: sete %al ; ALL-NEXT: testb %dl, %al -; ALL-NEXT: je LBB8_1 -; ALL-NEXT: ## %bb.2: ## %if.end.i +; ALL-NEXT: je LBB8_2 +; ALL-NEXT: ## %bb.1: ## %if.end.i ; ALL-NEXT: movl $6, %eax ; ALL-NEXT: retq -; ALL-NEXT: LBB8_1: ## %if.then.i +; ALL-NEXT: LBB8_2: ## %if.then.i ; ALL-NEXT: movl $5, %eax ; ALL-NEXT: retq diff --git a/llvm/test/CodeGen/X86/avx512-i1test.ll b/llvm/test/CodeGen/X86/avx512-i1test.ll index c5d4c87d66da2..5fdf9ced62692 100644 --- a/llvm/test/CodeGen/X86/avx512-i1test.ll +++ b/llvm/test/CodeGen/X86/avx512-i1test.ll @@ -9,18 +9,18 @@ define void @func() { ; CHECK-LABEL: func: ; CHECK: # %bb.0: # %bb1 ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: je .LBB0_1 -; CHECK-NEXT: # %bb.3: # %L_30 +; CHECK-NEXT: je .LBB0_2 +; CHECK-NEXT: # %bb.1: # %L_30 ; CHECK-NEXT: retq ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_1: # %bb33 +; CHECK-NEXT: .LBB0_2: # %bb33 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB0_1 -; CHECK-NEXT: # %bb.2: # %bb35 -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: jne .LBB0_2 +; CHECK-NEXT: # %bb.3: # %bb35 +; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jmp .LBB0_1 +; CHECK-NEXT: jmp .LBB0_2 bb1: br i1 poison, label %L_10, label %L_10 diff --git a/llvm/test/CodeGen/X86/avx512-mask-op.ll b/llvm/test/CodeGen/X86/avx512-mask-op.ll index da0cef0e4e99b..baa20eb8c73ee 100644 --- a/llvm/test/CodeGen/X86/avx512-mask-op.ll +++ b/llvm/test/CodeGen/X86/avx512-mask-op.ll @@ -669,11 +669,11 @@ define <16 x i8> @test8(<16 x i32>%a, <16 x i32>%b, i32 %a1, i32 %b1) { ; KNL-LABEL: test8: ; KNL: ## %bb.0: ; KNL-NEXT: cmpl %esi, %edi -; KNL-NEXT: jg LBB17_1 -; KNL-NEXT: ## %bb.2: +; KNL-NEXT: jg LBB17_2 +; KNL-NEXT: ## %bb.1: ; KNL-NEXT: kxorw %k0, %k0, %k1 ; KNL-NEXT: jmp LBB17_3 -; KNL-NEXT: LBB17_1: +; KNL-NEXT: LBB17_2: ; KNL-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; KNL-NEXT: vpcmpgtd %zmm1, %zmm0, %k1 ; KNL-NEXT: LBB17_3: @@ -685,13 +685,13 @@ define <16 x i8> @test8(<16 x i32>%a, <16 x i32>%b, i32 %a1, i32 %b1) { ; SKX-LABEL: test8: ; SKX: ## %bb.0: ; SKX-NEXT: cmpl %esi, %edi -; SKX-NEXT: jg LBB17_1 -; SKX-NEXT: ## %bb.2: +; SKX-NEXT: jg LBB17_2 +; SKX-NEXT: ## %bb.1: ; SKX-NEXT: kxorw %k0, %k0, %k0 ; SKX-NEXT: vpmovm2b %k0, %xmm0 ; SKX-NEXT: vzeroupper ; SKX-NEXT: retq -; SKX-NEXT: LBB17_1: +; SKX-NEXT: LBB17_2: ; SKX-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; SKX-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 ; SKX-NEXT: vpmovm2b %k0, %xmm0 @@ -701,14 +701,14 @@ define <16 x i8> @test8(<16 x i32>%a, <16 x i32>%b, i32 %a1, i32 %b1) { ; AVX512BW-LABEL: test8: ; AVX512BW: ## %bb.0: ; AVX512BW-NEXT: cmpl %esi, %edi -; AVX512BW-NEXT: jg LBB17_1 -; AVX512BW-NEXT: ## %bb.2: +; AVX512BW-NEXT: jg LBB17_2 +; AVX512BW-NEXT: ## %bb.1: ; AVX512BW-NEXT: kxorw %k0, %k0, %k0 ; AVX512BW-NEXT: vpmovm2b %k0, %zmm0 ; AVX512BW-NEXT: ## kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq -; AVX512BW-NEXT: LBB17_1: +; AVX512BW-NEXT: LBB17_2: ; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; AVX512BW-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 ; AVX512BW-NEXT: vpmovm2b %k0, %zmm0 @@ -719,11 +719,11 @@ define <16 x i8> @test8(<16 x i32>%a, <16 x i32>%b, i32 %a1, i32 %b1) { ; AVX512DQ-LABEL: test8: ; AVX512DQ: ## %bb.0: ; AVX512DQ-NEXT: cmpl %esi, %edi -; AVX512DQ-NEXT: jg LBB17_1 -; AVX512DQ-NEXT: ## %bb.2: +; AVX512DQ-NEXT: jg LBB17_2 +; AVX512DQ-NEXT: ## %bb.1: ; AVX512DQ-NEXT: kxorw %k0, %k0, %k0 ; AVX512DQ-NEXT: jmp LBB17_3 -; AVX512DQ-NEXT: LBB17_1: +; AVX512DQ-NEXT: LBB17_2: ; AVX512DQ-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; AVX512DQ-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 ; AVX512DQ-NEXT: LBB17_3: @@ -736,13 +736,13 @@ define <16 x i8> @test8(<16 x i32>%a, <16 x i32>%b, i32 %a1, i32 %b1) { ; X86: ## %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: cmpl {{[0-9]+}}(%esp), %eax -; X86-NEXT: jg LBB17_1 -; X86-NEXT: ## %bb.2: +; X86-NEXT: jg LBB17_2 +; X86-NEXT: ## %bb.1: ; X86-NEXT: kxorw %k0, %k0, %k0 ; X86-NEXT: vpmovm2b %k0, %xmm0 ; X86-NEXT: vzeroupper ; X86-NEXT: retl -; X86-NEXT: LBB17_1: +; X86-NEXT: LBB17_2: ; X86-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; X86-NEXT: vpcmpgtd %zmm1, %zmm0, %k0 ; X86-NEXT: vpmovm2b %k0, %xmm0 @@ -760,11 +760,11 @@ define <16 x i1> @test9(<16 x i1>%a, <16 x i1>%b, i32 %a1, i32 %b1) { ; KNL-LABEL: test9: ; KNL: ## %bb.0: ; KNL-NEXT: cmpl %esi, %edi -; KNL-NEXT: jg LBB18_1 -; KNL-NEXT: ## %bb.2: +; KNL-NEXT: jg LBB18_2 +; KNL-NEXT: ## %bb.1: ; KNL-NEXT: vpmovsxbd %xmm1, %zmm0 ; KNL-NEXT: jmp LBB18_3 -; KNL-NEXT: LBB18_1: +; KNL-NEXT: LBB18_2: ; KNL-NEXT: vpmovsxbd %xmm0, %zmm0 ; KNL-NEXT: LBB18_3: ; KNL-NEXT: vpslld $31, %zmm0, %zmm0 @@ -777,11 +777,11 @@ define <16 x i1> @test9(<16 x i1>%a, <16 x i1>%b, i32 %a1, i32 %b1) { ; SKX-LABEL: test9: ; SKX: ## %bb.0: ; SKX-NEXT: cmpl %esi, %edi -; SKX-NEXT: jg LBB18_1 -; SKX-NEXT: ## %bb.2: +; SKX-NEXT: jg LBB18_2 +; SKX-NEXT: ## %bb.1: ; SKX-NEXT: vpsllw $7, %xmm1, %xmm0 ; SKX-NEXT: jmp LBB18_3 -; SKX-NEXT: LBB18_1: +; SKX-NEXT: LBB18_2: ; SKX-NEXT: vpsllw $7, %xmm0, %xmm0 ; SKX-NEXT: LBB18_3: ; SKX-NEXT: vpmovb2m %xmm0, %k0 @@ -791,11 +791,11 @@ define <16 x i1> @test9(<16 x i1>%a, <16 x i1>%b, i32 %a1, i32 %b1) { ; AVX512BW-LABEL: test9: ; AVX512BW: ## %bb.0: ; AVX512BW-NEXT: cmpl %esi, %edi -; AVX512BW-NEXT: jg LBB18_1 -; AVX512BW-NEXT: ## %bb.2: +; AVX512BW-NEXT: jg LBB18_2 +; AVX512BW-NEXT: ## %bb.1: ; AVX512BW-NEXT: vpsllw $7, %xmm1, %xmm0 ; AVX512BW-NEXT: jmp LBB18_3 -; AVX512BW-NEXT: LBB18_1: +; AVX512BW-NEXT: LBB18_2: ; AVX512BW-NEXT: vpsllw $7, %xmm0, %xmm0 ; AVX512BW-NEXT: LBB18_3: ; AVX512BW-NEXT: vpmovb2m %zmm0, %k0 @@ -807,11 +807,11 @@ define <16 x i1> @test9(<16 x i1>%a, <16 x i1>%b, i32 %a1, i32 %b1) { ; AVX512DQ-LABEL: test9: ; AVX512DQ: ## %bb.0: ; AVX512DQ-NEXT: cmpl %esi, %edi -; AVX512DQ-NEXT: jg LBB18_1 -; AVX512DQ-NEXT: ## %bb.2: +; AVX512DQ-NEXT: jg LBB18_2 +; AVX512DQ-NEXT: ## %bb.1: ; AVX512DQ-NEXT: vpmovsxbd %xmm1, %zmm0 ; AVX512DQ-NEXT: jmp LBB18_3 -; AVX512DQ-NEXT: LBB18_1: +; AVX512DQ-NEXT: LBB18_2: ; AVX512DQ-NEXT: vpmovsxbd %xmm0, %zmm0 ; AVX512DQ-NEXT: LBB18_3: ; AVX512DQ-NEXT: vpslld $31, %zmm0, %zmm0 @@ -825,11 +825,11 @@ define <16 x i1> @test9(<16 x i1>%a, <16 x i1>%b, i32 %a1, i32 %b1) { ; X86: ## %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: cmpl {{[0-9]+}}(%esp), %eax -; X86-NEXT: jg LBB18_1 -; X86-NEXT: ## %bb.2: +; X86-NEXT: jg LBB18_2 +; X86-NEXT: ## %bb.1: ; X86-NEXT: vpsllw $7, %xmm1, %xmm0 ; X86-NEXT: jmp LBB18_3 -; X86-NEXT: LBB18_1: +; X86-NEXT: LBB18_2: ; X86-NEXT: vpsllw $7, %xmm0, %xmm0 ; X86-NEXT: LBB18_3: ; X86-NEXT: vpmovb2m %xmm0, %k0 @@ -844,11 +844,11 @@ define <8 x i1> @test10(<8 x i1>%a, <8 x i1>%b, i32 %a1, i32 %b1) { ; KNL-LABEL: test10: ; KNL: ## %bb.0: ; KNL-NEXT: cmpl %esi, %edi -; KNL-NEXT: jg LBB19_1 -; KNL-NEXT: ## %bb.2: +; KNL-NEXT: jg LBB19_2 +; KNL-NEXT: ## %bb.1: ; KNL-NEXT: vpmovsxwq %xmm1, %zmm0 ; KNL-NEXT: jmp LBB19_3 -; KNL-NEXT: LBB19_1: +; KNL-NEXT: LBB19_2: ; KNL-NEXT: vpmovsxwq %xmm0, %zmm0 ; KNL-NEXT: LBB19_3: ; KNL-NEXT: vpsllq $63, %zmm0, %zmm0 @@ -862,11 +862,11 @@ define <8 x i1> @test10(<8 x i1>%a, <8 x i1>%b, i32 %a1, i32 %b1) { ; SKX-LABEL: test10: ; SKX: ## %bb.0: ; SKX-NEXT: cmpl %esi, %edi -; SKX-NEXT: jg LBB19_1 -; SKX-NEXT: ## %bb.2: +; SKX-NEXT: jg LBB19_2 +; SKX-NEXT: ## %bb.1: ; SKX-NEXT: vpsllw $15, %xmm1, %xmm0 ; SKX-NEXT: jmp LBB19_3 -; SKX-NEXT: LBB19_1: +; SKX-NEXT: LBB19_2: ; SKX-NEXT: vpsllw $15, %xmm0, %xmm0 ; SKX-NEXT: LBB19_3: ; SKX-NEXT: vpmovw2m %xmm0, %k0 @@ -876,11 +876,11 @@ define <8 x i1> @test10(<8 x i1>%a, <8 x i1>%b, i32 %a1, i32 %b1) { ; AVX512BW-LABEL: test10: ; AVX512BW: ## %bb.0: ; AVX512BW-NEXT: cmpl %esi, %edi -; AVX512BW-NEXT: jg LBB19_1 -; AVX512BW-NEXT: ## %bb.2: +; AVX512BW-NEXT: jg LBB19_2 +; AVX512BW-NEXT: ## %bb.1: ; AVX512BW-NEXT: vpsllw $15, %xmm1, %xmm0 ; AVX512BW-NEXT: jmp LBB19_3 -; AVX512BW-NEXT: LBB19_1: +; AVX512BW-NEXT: LBB19_2: ; AVX512BW-NEXT: vpsllw $15, %xmm0, %xmm0 ; AVX512BW-NEXT: LBB19_3: ; AVX512BW-NEXT: vpmovw2m %zmm0, %k0 @@ -892,11 +892,11 @@ define <8 x i1> @test10(<8 x i1>%a, <8 x i1>%b, i32 %a1, i32 %b1) { ; AVX512DQ-LABEL: test10: ; AVX512DQ: ## %bb.0: ; AVX512DQ-NEXT: cmpl %esi, %edi -; AVX512DQ-NEXT: jg LBB19_1 -; AVX512DQ-NEXT: ## %bb.2: +; AVX512DQ-NEXT: jg LBB19_2 +; AVX512DQ-NEXT: ## %bb.1: ; AVX512DQ-NEXT: vpmovsxwq %xmm1, %zmm0 ; AVX512DQ-NEXT: jmp LBB19_3 -; AVX512DQ-NEXT: LBB19_1: +; AVX512DQ-NEXT: LBB19_2: ; AVX512DQ-NEXT: vpmovsxwq %xmm0, %zmm0 ; AVX512DQ-NEXT: LBB19_3: ; AVX512DQ-NEXT: vpsllq $63, %zmm0, %zmm0 @@ -911,11 +911,11 @@ define <8 x i1> @test10(<8 x i1>%a, <8 x i1>%b, i32 %a1, i32 %b1) { ; X86: ## %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: cmpl {{[0-9]+}}(%esp), %eax -; X86-NEXT: jg LBB19_1 -; X86-NEXT: ## %bb.2: +; X86-NEXT: jg LBB19_2 +; X86-NEXT: ## %bb.1: ; X86-NEXT: vpsllw $15, %xmm1, %xmm0 ; X86-NEXT: jmp LBB19_3 -; X86-NEXT: LBB19_1: +; X86-NEXT: LBB19_2: ; X86-NEXT: vpsllw $15, %xmm0, %xmm0 ; X86-NEXT: LBB19_3: ; X86-NEXT: vpmovw2m %xmm0, %k0 @@ -930,11 +930,11 @@ define <4 x i1> @test11(<4 x i1>%a, <4 x i1>%b, i32 %a1, i32 %b1) { ; KNL-LABEL: test11: ; KNL: ## %bb.0: ; KNL-NEXT: cmpl %esi, %edi -; KNL-NEXT: jg LBB20_1 -; KNL-NEXT: ## %bb.2: +; KNL-NEXT: jg LBB20_2 +; KNL-NEXT: ## %bb.1: ; KNL-NEXT: vpslld $31, %xmm1, %xmm0 ; KNL-NEXT: jmp LBB20_3 -; KNL-NEXT: LBB20_1: +; KNL-NEXT: LBB20_2: ; KNL-NEXT: vpslld $31, %xmm0, %xmm0 ; KNL-NEXT: LBB20_3: ; KNL-NEXT: vptestmd %zmm0, %zmm0, %k1 @@ -946,11 +946,11 @@ define <4 x i1> @test11(<4 x i1>%a, <4 x i1>%b, i32 %a1, i32 %b1) { ; SKX-LABEL: test11: ; SKX: ## %bb.0: ; SKX-NEXT: cmpl %esi, %edi -; SKX-NEXT: jg LBB20_1 -; SKX-NEXT: ## %bb.2: +; SKX-NEXT: jg LBB20_2 +; SKX-NEXT: ## %bb.1: ; SKX-NEXT: vpslld $31, %xmm1, %xmm0 ; SKX-NEXT: jmp LBB20_3 -; SKX-NEXT: LBB20_1: +; SKX-NEXT: LBB20_2: ; SKX-NEXT: vpslld $31, %xmm0, %xmm0 ; SKX-NEXT: LBB20_3: ; SKX-NEXT: vpmovd2m %xmm0, %k0 @@ -960,11 +960,11 @@ define <4 x i1> @test11(<4 x i1>%a, <4 x i1>%b, i32 %a1, i32 %b1) { ; AVX512BW-LABEL: test11: ; AVX512BW: ## %bb.0: ; AVX512BW-NEXT: cmpl %esi, %edi -; AVX512BW-NEXT: jg LBB20_1 -; AVX512BW-NEXT: ## %bb.2: +; AVX512BW-NEXT: jg LBB20_2 +; AVX512BW-NEXT: ## %bb.1: ; AVX512BW-NEXT: vpslld $31, %xmm1, %xmm0 ; AVX512BW-NEXT: jmp LBB20_3 -; AVX512BW-NEXT: LBB20_1: +; AVX512BW-NEXT: LBB20_2: ; AVX512BW-NEXT: vpslld $31, %xmm0, %xmm0 ; AVX512BW-NEXT: LBB20_3: ; AVX512BW-NEXT: vptestmd %zmm0, %zmm0, %k1 @@ -976,11 +976,11 @@ define <4 x i1> @test11(<4 x i1>%a, <4 x i1>%b, i32 %a1, i32 %b1) { ; AVX512DQ-LABEL: test11: ; AVX512DQ: ## %bb.0: ; AVX512DQ-NEXT: cmpl %esi, %edi -; AVX512DQ-NEXT: jg LBB20_1 -; AVX512DQ-NEXT: ## %bb.2: +; AVX512DQ-NEXT: jg LBB20_2 +; AVX512DQ-NEXT: ## %bb.1: ; AVX512DQ-NEXT: vpslld $31, %xmm1, %xmm0 ; AVX512DQ-NEXT: jmp LBB20_3 -; AVX512DQ-NEXT: LBB20_1: +; AVX512DQ-NEXT: LBB20_2: ; AVX512DQ-NEXT: vpslld $31, %xmm0, %xmm0 ; AVX512DQ-NEXT: LBB20_3: ; AVX512DQ-NEXT: vpmovd2m %zmm0, %k0 @@ -993,11 +993,11 @@ define <4 x i1> @test11(<4 x i1>%a, <4 x i1>%b, i32 %a1, i32 %b1) { ; X86: ## %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: cmpl {{[0-9]+}}(%esp), %eax -; X86-NEXT: jg LBB20_1 -; X86-NEXT: ## %bb.2: +; X86-NEXT: jg LBB20_2 +; X86-NEXT: ## %bb.1: ; X86-NEXT: vpslld $31, %xmm1, %xmm0 ; X86-NEXT: jmp LBB20_3 -; X86-NEXT: LBB20_1: +; X86-NEXT: LBB20_2: ; X86-NEXT: vpslld $31, %xmm0, %xmm0 ; X86-NEXT: LBB20_3: ; X86-NEXT: vpmovd2m %xmm0, %k0 @@ -3998,11 +3998,11 @@ define void @ktest_signed(<16 x i32> %x, <16 x i32> %y) { ; KNL-NEXT: vptestnmd %zmm0, %zmm0, %k0 ; KNL-NEXT: kmovw %k0, %eax ; KNL-NEXT: testw %ax, %ax -; KNL-NEXT: jle LBB66_1 -; KNL-NEXT: ## %bb.2: ## %bb.2 +; KNL-NEXT: jle LBB66_2 +; KNL-NEXT: ## %bb.1: ## %bb.2 ; KNL-NEXT: vzeroupper ; KNL-NEXT: retq -; KNL-NEXT: LBB66_1: ## %bb.1 +; KNL-NEXT: LBB66_2: ## %bb.1 ; KNL-NEXT: pushq %rax ; KNL-NEXT: .cfi_def_cfa_offset 16 ; KNL-NEXT: vzeroupper @@ -4016,11 +4016,11 @@ define void @ktest_signed(<16 x i32> %x, <16 x i32> %y) { ; SKX-NEXT: vptestnmd %zmm0, %zmm0, %k0 ; SKX-NEXT: kmovd %k0, %eax ; SKX-NEXT: testw %ax, %ax -; SKX-NEXT: jle LBB66_1 -; SKX-NEXT: ## %bb.2: ## %bb.2 +; SKX-NEXT: jle LBB66_2 +; SKX-NEXT: ## %bb.1: ## %bb.2 ; SKX-NEXT: vzeroupper ; SKX-NEXT: retq -; SKX-NEXT: LBB66_1: ## %bb.1 +; SKX-NEXT: LBB66_2: ## %bb.1 ; SKX-NEXT: pushq %rax ; SKX-NEXT: .cfi_def_cfa_offset 16 ; SKX-NEXT: vzeroupper @@ -4034,11 +4034,11 @@ define void @ktest_signed(<16 x i32> %x, <16 x i32> %y) { ; AVX512BW-NEXT: vptestnmd %zmm0, %zmm0, %k0 ; AVX512BW-NEXT: kmovd %k0, %eax ; AVX512BW-NEXT: testw %ax, %ax -; AVX512BW-NEXT: jle LBB66_1 -; AVX512BW-NEXT: ## %bb.2: ## %bb.2 +; AVX512BW-NEXT: jle LBB66_2 +; AVX512BW-NEXT: ## %bb.1: ## %bb.2 ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq -; AVX512BW-NEXT: LBB66_1: ## %bb.1 +; AVX512BW-NEXT: LBB66_2: ## %bb.1 ; AVX512BW-NEXT: pushq %rax ; AVX512BW-NEXT: .cfi_def_cfa_offset 16 ; AVX512BW-NEXT: vzeroupper @@ -4052,11 +4052,11 @@ define void @ktest_signed(<16 x i32> %x, <16 x i32> %y) { ; AVX512DQ-NEXT: vptestnmd %zmm0, %zmm0, %k0 ; AVX512DQ-NEXT: kmovw %k0, %eax ; AVX512DQ-NEXT: testw %ax, %ax -; AVX512DQ-NEXT: jle LBB66_1 -; AVX512DQ-NEXT: ## %bb.2: ## %bb.2 +; AVX512DQ-NEXT: jle LBB66_2 +; AVX512DQ-NEXT: ## %bb.1: ## %bb.2 ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq -; AVX512DQ-NEXT: LBB66_1: ## %bb.1 +; AVX512DQ-NEXT: LBB66_2: ## %bb.1 ; AVX512DQ-NEXT: pushq %rax ; AVX512DQ-NEXT: .cfi_def_cfa_offset 16 ; AVX512DQ-NEXT: vzeroupper @@ -4070,11 +4070,11 @@ define void @ktest_signed(<16 x i32> %x, <16 x i32> %y) { ; X86-NEXT: vptestnmd %zmm0, %zmm0, %k0 ; X86-NEXT: kmovd %k0, %eax ; X86-NEXT: testw %ax, %ax -; X86-NEXT: jle LBB66_1 -; X86-NEXT: ## %bb.2: ## %bb.2 +; X86-NEXT: jle LBB66_2 +; X86-NEXT: ## %bb.1: ## %bb.2 ; X86-NEXT: vzeroupper ; X86-NEXT: retl -; X86-NEXT: LBB66_1: ## %bb.1 +; X86-NEXT: LBB66_2: ## %bb.1 ; X86-NEXT: subl $12, %esp ; X86-NEXT: .cfi_def_cfa_offset 16 ; X86-NEXT: vzeroupper @@ -4349,11 +4349,11 @@ define void @ktest_3(<8 x i32> %w, <8 x i32> %x, <8 x i32> %y, <8 x i32> %z) { ; KNL-NEXT: kandw %k1, %k0, %k0 ; KNL-NEXT: kmovw %k0, %eax ; KNL-NEXT: testb %al, %al -; KNL-NEXT: je LBB74_1 -; KNL-NEXT: ## %bb.2: ## %exit +; KNL-NEXT: je LBB74_2 +; KNL-NEXT: ## %bb.1: ## %exit ; KNL-NEXT: vzeroupper ; KNL-NEXT: retq -; KNL-NEXT: LBB74_1: ## %bar +; KNL-NEXT: LBB74_2: ## %bar ; KNL-NEXT: pushq %rax ; KNL-NEXT: .cfi_def_cfa_offset 16 ; KNL-NEXT: vzeroupper @@ -4370,11 +4370,11 @@ define void @ktest_3(<8 x i32> %w, <8 x i32> %x, <8 x i32> %y, <8 x i32> %z) { ; SKX-NEXT: vptestnmd %ymm3, %ymm3, %k2 ; SKX-NEXT: korb %k2, %k1, %k1 ; SKX-NEXT: ktestb %k1, %k0 -; SKX-NEXT: je LBB74_1 -; SKX-NEXT: ## %bb.2: ## %exit +; SKX-NEXT: je LBB74_2 +; SKX-NEXT: ## %bb.1: ## %exit ; SKX-NEXT: vzeroupper ; SKX-NEXT: retq -; SKX-NEXT: LBB74_1: ## %bar +; SKX-NEXT: LBB74_2: ## %bar ; SKX-NEXT: pushq %rax ; SKX-NEXT: .cfi_def_cfa_offset 16 ; SKX-NEXT: vzeroupper @@ -4397,11 +4397,11 @@ define void @ktest_3(<8 x i32> %w, <8 x i32> %x, <8 x i32> %y, <8 x i32> %z) { ; AVX512BW-NEXT: kandw %k1, %k0, %k0 ; AVX512BW-NEXT: kmovd %k0, %eax ; AVX512BW-NEXT: testb %al, %al -; AVX512BW-NEXT: je LBB74_1 -; AVX512BW-NEXT: ## %bb.2: ## %exit +; AVX512BW-NEXT: je LBB74_2 +; AVX512BW-NEXT: ## %bb.1: ## %exit ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq -; AVX512BW-NEXT: LBB74_1: ## %bar +; AVX512BW-NEXT: LBB74_2: ## %bar ; AVX512BW-NEXT: pushq %rax ; AVX512BW-NEXT: .cfi_def_cfa_offset 16 ; AVX512BW-NEXT: vzeroupper @@ -4422,11 +4422,11 @@ define void @ktest_3(<8 x i32> %w, <8 x i32> %x, <8 x i32> %y, <8 x i32> %z) { ; AVX512DQ-NEXT: korb %k1, %k0, %k0 ; AVX512DQ-NEXT: korb %k3, %k2, %k1 ; AVX512DQ-NEXT: ktestb %k1, %k0 -; AVX512DQ-NEXT: je LBB74_1 -; AVX512DQ-NEXT: ## %bb.2: ## %exit +; AVX512DQ-NEXT: je LBB74_2 +; AVX512DQ-NEXT: ## %bb.1: ## %exit ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq -; AVX512DQ-NEXT: LBB74_1: ## %bar +; AVX512DQ-NEXT: LBB74_2: ## %bar ; AVX512DQ-NEXT: pushq %rax ; AVX512DQ-NEXT: .cfi_def_cfa_offset 16 ; AVX512DQ-NEXT: vzeroupper @@ -4443,11 +4443,11 @@ define void @ktest_3(<8 x i32> %w, <8 x i32> %x, <8 x i32> %y, <8 x i32> %z) { ; X86-NEXT: vptestnmd %ymm3, %ymm3, %k2 ; X86-NEXT: korb %k2, %k1, %k1 ; X86-NEXT: ktestb %k1, %k0 -; X86-NEXT: je LBB74_1 -; X86-NEXT: ## %bb.2: ## %exit +; X86-NEXT: je LBB74_2 +; X86-NEXT: ## %bb.1: ## %exit ; X86-NEXT: vzeroupper ; X86-NEXT: retl -; X86-NEXT: LBB74_1: ## %bar +; X86-NEXT: LBB74_2: ## %bar ; X86-NEXT: subl $12, %esp ; X86-NEXT: .cfi_def_cfa_offset 16 ; X86-NEXT: vzeroupper @@ -4485,11 +4485,11 @@ define void @ktest_4(<8 x i64> %w, <8 x i64> %x, <8 x i64> %y, <8 x i64> %z) { ; KNL-NEXT: kandw %k1, %k0, %k0 ; KNL-NEXT: kmovw %k0, %eax ; KNL-NEXT: testb %al, %al -; KNL-NEXT: je LBB75_1 -; KNL-NEXT: ## %bb.2: ## %exit +; KNL-NEXT: je LBB75_2 +; KNL-NEXT: ## %bb.1: ## %exit ; KNL-NEXT: vzeroupper ; KNL-NEXT: retq -; KNL-NEXT: LBB75_1: ## %bar +; KNL-NEXT: LBB75_2: ## %bar ; KNL-NEXT: pushq %rax ; KNL-NEXT: .cfi_def_cfa_offset 16 ; KNL-NEXT: vzeroupper @@ -4506,11 +4506,11 @@ define void @ktest_4(<8 x i64> %w, <8 x i64> %x, <8 x i64> %y, <8 x i64> %z) { ; SKX-NEXT: vptestnmq %zmm3, %zmm3, %k2 ; SKX-NEXT: korb %k2, %k1, %k1 ; SKX-NEXT: ktestb %k1, %k0 -; SKX-NEXT: je LBB75_1 -; SKX-NEXT: ## %bb.2: ## %exit +; SKX-NEXT: je LBB75_2 +; SKX-NEXT: ## %bb.1: ## %exit ; SKX-NEXT: vzeroupper ; SKX-NEXT: retq -; SKX-NEXT: LBB75_1: ## %bar +; SKX-NEXT: LBB75_2: ## %bar ; SKX-NEXT: pushq %rax ; SKX-NEXT: .cfi_def_cfa_offset 16 ; SKX-NEXT: vzeroupper @@ -4529,11 +4529,11 @@ define void @ktest_4(<8 x i64> %w, <8 x i64> %x, <8 x i64> %y, <8 x i64> %z) { ; AVX512BW-NEXT: kandw %k1, %k0, %k0 ; AVX512BW-NEXT: kmovd %k0, %eax ; AVX512BW-NEXT: testb %al, %al -; AVX512BW-NEXT: je LBB75_1 -; AVX512BW-NEXT: ## %bb.2: ## %exit +; AVX512BW-NEXT: je LBB75_2 +; AVX512BW-NEXT: ## %bb.1: ## %exit ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq -; AVX512BW-NEXT: LBB75_1: ## %bar +; AVX512BW-NEXT: LBB75_2: ## %bar ; AVX512BW-NEXT: pushq %rax ; AVX512BW-NEXT: .cfi_def_cfa_offset 16 ; AVX512BW-NEXT: vzeroupper @@ -4550,11 +4550,11 @@ define void @ktest_4(<8 x i64> %w, <8 x i64> %x, <8 x i64> %y, <8 x i64> %z) { ; AVX512DQ-NEXT: vptestnmq %zmm3, %zmm3, %k2 ; AVX512DQ-NEXT: korb %k2, %k1, %k1 ; AVX512DQ-NEXT: ktestb %k1, %k0 -; AVX512DQ-NEXT: je LBB75_1 -; AVX512DQ-NEXT: ## %bb.2: ## %exit +; AVX512DQ-NEXT: je LBB75_2 +; AVX512DQ-NEXT: ## %bb.1: ## %exit ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq -; AVX512DQ-NEXT: LBB75_1: ## %bar +; AVX512DQ-NEXT: LBB75_2: ## %bar ; AVX512DQ-NEXT: pushq %rax ; AVX512DQ-NEXT: .cfi_def_cfa_offset 16 ; AVX512DQ-NEXT: vzeroupper @@ -4571,11 +4571,11 @@ define void @ktest_4(<8 x i64> %w, <8 x i64> %x, <8 x i64> %y, <8 x i64> %z) { ; X86-NEXT: vptestnmq %zmm3, %zmm3, %k2 ; X86-NEXT: korb %k2, %k1, %k1 ; X86-NEXT: ktestb %k1, %k0 -; X86-NEXT: je LBB75_1 -; X86-NEXT: ## %bb.2: ## %exit +; X86-NEXT: je LBB75_2 +; X86-NEXT: ## %bb.1: ## %exit ; X86-NEXT: vzeroupper ; X86-NEXT: retl -; X86-NEXT: LBB75_1: ## %bar +; X86-NEXT: LBB75_2: ## %bar ; X86-NEXT: subl $12, %esp ; X86-NEXT: .cfi_def_cfa_offset 16 ; X86-NEXT: vzeroupper @@ -4612,11 +4612,11 @@ define void @ktest_5(<16 x i32> %w, <16 x i32> %x, <16 x i32> %y, <16 x i32> %z) ; KNL-NEXT: korw %k2, %k1, %k1 ; KNL-NEXT: kandw %k1, %k0, %k0 ; KNL-NEXT: kortestw %k0, %k0 -; KNL-NEXT: je LBB76_1 -; KNL-NEXT: ## %bb.2: ## %exit +; KNL-NEXT: je LBB76_2 +; KNL-NEXT: ## %bb.1: ## %exit ; KNL-NEXT: vzeroupper ; KNL-NEXT: retq -; KNL-NEXT: LBB76_1: ## %bar +; KNL-NEXT: LBB76_2: ## %bar ; KNL-NEXT: pushq %rax ; KNL-NEXT: .cfi_def_cfa_offset 16 ; KNL-NEXT: vzeroupper @@ -4633,11 +4633,11 @@ define void @ktest_5(<16 x i32> %w, <16 x i32> %x, <16 x i32> %y, <16 x i32> %z) ; SKX-NEXT: vptestnmd %zmm3, %zmm3, %k2 ; SKX-NEXT: korw %k2, %k1, %k1 ; SKX-NEXT: ktestw %k1, %k0 -; SKX-NEXT: je LBB76_1 -; SKX-NEXT: ## %bb.2: ## %exit +; SKX-NEXT: je LBB76_2 +; SKX-NEXT: ## %bb.1: ## %exit ; SKX-NEXT: vzeroupper ; SKX-NEXT: retq -; SKX-NEXT: LBB76_1: ## %bar +; SKX-NEXT: LBB76_2: ## %bar ; SKX-NEXT: pushq %rax ; SKX-NEXT: .cfi_def_cfa_offset 16 ; SKX-NEXT: vzeroupper @@ -4655,11 +4655,11 @@ define void @ktest_5(<16 x i32> %w, <16 x i32> %x, <16 x i32> %y, <16 x i32> %z) ; AVX512BW-NEXT: korw %k2, %k1, %k1 ; AVX512BW-NEXT: kandw %k1, %k0, %k0 ; AVX512BW-NEXT: kortestw %k0, %k0 -; AVX512BW-NEXT: je LBB76_1 -; AVX512BW-NEXT: ## %bb.2: ## %exit +; AVX512BW-NEXT: je LBB76_2 +; AVX512BW-NEXT: ## %bb.1: ## %exit ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq -; AVX512BW-NEXT: LBB76_1: ## %bar +; AVX512BW-NEXT: LBB76_2: ## %bar ; AVX512BW-NEXT: pushq %rax ; AVX512BW-NEXT: .cfi_def_cfa_offset 16 ; AVX512BW-NEXT: vzeroupper @@ -4676,11 +4676,11 @@ define void @ktest_5(<16 x i32> %w, <16 x i32> %x, <16 x i32> %y, <16 x i32> %z) ; AVX512DQ-NEXT: vptestnmd %zmm3, %zmm3, %k2 ; AVX512DQ-NEXT: korw %k2, %k1, %k1 ; AVX512DQ-NEXT: ktestw %k1, %k0 -; AVX512DQ-NEXT: je LBB76_1 -; AVX512DQ-NEXT: ## %bb.2: ## %exit +; AVX512DQ-NEXT: je LBB76_2 +; AVX512DQ-NEXT: ## %bb.1: ## %exit ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq -; AVX512DQ-NEXT: LBB76_1: ## %bar +; AVX512DQ-NEXT: LBB76_2: ## %bar ; AVX512DQ-NEXT: pushq %rax ; AVX512DQ-NEXT: .cfi_def_cfa_offset 16 ; AVX512DQ-NEXT: vzeroupper @@ -4697,11 +4697,11 @@ define void @ktest_5(<16 x i32> %w, <16 x i32> %x, <16 x i32> %y, <16 x i32> %z) ; X86-NEXT: vptestnmd %zmm3, %zmm3, %k2 ; X86-NEXT: korw %k2, %k1, %k1 ; X86-NEXT: ktestw %k1, %k0 -; X86-NEXT: je LBB76_1 -; X86-NEXT: ## %bb.2: ## %exit +; X86-NEXT: je LBB76_2 +; X86-NEXT: ## %bb.1: ## %exit ; X86-NEXT: vzeroupper ; X86-NEXT: retl -; X86-NEXT: LBB76_1: ## %bar +; X86-NEXT: LBB76_2: ## %bar ; X86-NEXT: subl $12, %esp ; X86-NEXT: .cfi_def_cfa_offset 16 ; X86-NEXT: vzeroupper @@ -4755,11 +4755,11 @@ define void @ktest_6(<32 x i16> %w, <32 x i16> %x, <32 x i16> %y, <32 x i16> %z) ; KNL-NEXT: vpslld $31, %zmm0, %zmm0 ; KNL-NEXT: vptestmd %zmm0, %zmm0, %k0 ; KNL-NEXT: kortestw %k0, %k0 -; KNL-NEXT: je LBB77_1 -; KNL-NEXT: ## %bb.2: ## %exit +; KNL-NEXT: je LBB77_2 +; KNL-NEXT: ## %bb.1: ## %exit ; KNL-NEXT: vzeroupper ; KNL-NEXT: retq -; KNL-NEXT: LBB77_1: ## %bar +; KNL-NEXT: LBB77_2: ## %bar ; KNL-NEXT: pushq %rax ; KNL-NEXT: .cfi_def_cfa_offset 16 ; KNL-NEXT: vzeroupper @@ -4776,11 +4776,11 @@ define void @ktest_6(<32 x i16> %w, <32 x i16> %x, <32 x i16> %y, <32 x i16> %z) ; SKX-NEXT: vptestnmw %zmm3, %zmm3, %k2 ; SKX-NEXT: kord %k2, %k1, %k1 ; SKX-NEXT: ktestd %k1, %k0 -; SKX-NEXT: je LBB77_1 -; SKX-NEXT: ## %bb.2: ## %exit +; SKX-NEXT: je LBB77_2 +; SKX-NEXT: ## %bb.1: ## %exit ; SKX-NEXT: vzeroupper ; SKX-NEXT: retq -; SKX-NEXT: LBB77_1: ## %bar +; SKX-NEXT: LBB77_2: ## %bar ; SKX-NEXT: pushq %rax ; SKX-NEXT: .cfi_def_cfa_offset 16 ; SKX-NEXT: vzeroupper @@ -4797,11 +4797,11 @@ define void @ktest_6(<32 x i16> %w, <32 x i16> %x, <32 x i16> %y, <32 x i16> %z) ; AVX512BW-NEXT: vptestnmw %zmm3, %zmm3, %k2 ; AVX512BW-NEXT: kord %k2, %k1, %k1 ; AVX512BW-NEXT: ktestd %k1, %k0 -; AVX512BW-NEXT: je LBB77_1 -; AVX512BW-NEXT: ## %bb.2: ## %exit +; AVX512BW-NEXT: je LBB77_2 +; AVX512BW-NEXT: ## %bb.1: ## %exit ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq -; AVX512BW-NEXT: LBB77_1: ## %bar +; AVX512BW-NEXT: LBB77_2: ## %bar ; AVX512BW-NEXT: pushq %rax ; AVX512BW-NEXT: .cfi_def_cfa_offset 16 ; AVX512BW-NEXT: vzeroupper @@ -4836,11 +4836,11 @@ define void @ktest_6(<32 x i16> %w, <32 x i16> %x, <32 x i16> %y, <32 x i16> %z) ; AVX512DQ-NEXT: vpslld $31, %zmm0, %zmm0 ; AVX512DQ-NEXT: vpmovd2m %zmm0, %k0 ; AVX512DQ-NEXT: kortestw %k0, %k0 -; AVX512DQ-NEXT: je LBB77_1 -; AVX512DQ-NEXT: ## %bb.2: ## %exit +; AVX512DQ-NEXT: je LBB77_2 +; AVX512DQ-NEXT: ## %bb.1: ## %exit ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq -; AVX512DQ-NEXT: LBB77_1: ## %bar +; AVX512DQ-NEXT: LBB77_2: ## %bar ; AVX512DQ-NEXT: pushq %rax ; AVX512DQ-NEXT: .cfi_def_cfa_offset 16 ; AVX512DQ-NEXT: vzeroupper @@ -4857,11 +4857,11 @@ define void @ktest_6(<32 x i16> %w, <32 x i16> %x, <32 x i16> %y, <32 x i16> %z) ; X86-NEXT: vptestnmw %zmm3, %zmm3, %k2 ; X86-NEXT: kord %k2, %k1, %k1 ; X86-NEXT: ktestd %k1, %k0 -; X86-NEXT: je LBB77_1 -; X86-NEXT: ## %bb.2: ## %exit +; X86-NEXT: je LBB77_2 +; X86-NEXT: ## %bb.1: ## %exit ; X86-NEXT: vzeroupper ; X86-NEXT: retl -; X86-NEXT: LBB77_1: ## %bar +; X86-NEXT: LBB77_2: ## %bar ; X86-NEXT: subl $12, %esp ; X86-NEXT: .cfi_def_cfa_offset 16 ; X86-NEXT: vzeroupper @@ -4913,11 +4913,11 @@ define void @ktest_7(<64 x i8> %w, <64 x i8> %x, <64 x i8> %y, <64 x i8> %z) { ; KNL-NEXT: vpor %ymm0, %ymm2, %ymm0 ; KNL-NEXT: vpmovmskb %ymm0, %eax ; KNL-NEXT: testl %eax, %eax -; KNL-NEXT: je LBB78_1 -; KNL-NEXT: ## %bb.2: ## %exit +; KNL-NEXT: je LBB78_2 +; KNL-NEXT: ## %bb.1: ## %exit ; KNL-NEXT: vzeroupper ; KNL-NEXT: retq -; KNL-NEXT: LBB78_1: ## %bar +; KNL-NEXT: LBB78_2: ## %bar ; KNL-NEXT: pushq %rax ; KNL-NEXT: .cfi_def_cfa_offset 16 ; KNL-NEXT: vzeroupper @@ -4934,11 +4934,11 @@ define void @ktest_7(<64 x i8> %w, <64 x i8> %x, <64 x i8> %y, <64 x i8> %z) { ; SKX-NEXT: vptestnmb %zmm3, %zmm3, %k2 ; SKX-NEXT: korq %k2, %k1, %k1 ; SKX-NEXT: ktestq %k1, %k0 -; SKX-NEXT: je LBB78_1 -; SKX-NEXT: ## %bb.2: ## %exit +; SKX-NEXT: je LBB78_2 +; SKX-NEXT: ## %bb.1: ## %exit ; SKX-NEXT: vzeroupper ; SKX-NEXT: retq -; SKX-NEXT: LBB78_1: ## %bar +; SKX-NEXT: LBB78_2: ## %bar ; SKX-NEXT: pushq %rax ; SKX-NEXT: .cfi_def_cfa_offset 16 ; SKX-NEXT: vzeroupper @@ -4955,11 +4955,11 @@ define void @ktest_7(<64 x i8> %w, <64 x i8> %x, <64 x i8> %y, <64 x i8> %z) { ; AVX512BW-NEXT: vptestnmb %zmm3, %zmm3, %k2 ; AVX512BW-NEXT: korq %k2, %k1, %k1 ; AVX512BW-NEXT: ktestq %k1, %k0 -; AVX512BW-NEXT: je LBB78_1 -; AVX512BW-NEXT: ## %bb.2: ## %exit +; AVX512BW-NEXT: je LBB78_2 +; AVX512BW-NEXT: ## %bb.1: ## %exit ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq -; AVX512BW-NEXT: LBB78_1: ## %bar +; AVX512BW-NEXT: LBB78_2: ## %bar ; AVX512BW-NEXT: pushq %rax ; AVX512BW-NEXT: .cfi_def_cfa_offset 16 ; AVX512BW-NEXT: vzeroupper @@ -4992,11 +4992,11 @@ define void @ktest_7(<64 x i8> %w, <64 x i8> %x, <64 x i8> %y, <64 x i8> %z) { ; AVX512DQ-NEXT: vpor %ymm0, %ymm2, %ymm0 ; AVX512DQ-NEXT: vpmovmskb %ymm0, %eax ; AVX512DQ-NEXT: testl %eax, %eax -; AVX512DQ-NEXT: je LBB78_1 -; AVX512DQ-NEXT: ## %bb.2: ## %exit +; AVX512DQ-NEXT: je LBB78_2 +; AVX512DQ-NEXT: ## %bb.1: ## %exit ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq -; AVX512DQ-NEXT: LBB78_1: ## %bar +; AVX512DQ-NEXT: LBB78_2: ## %bar ; AVX512DQ-NEXT: pushq %rax ; AVX512DQ-NEXT: .cfi_def_cfa_offset 16 ; AVX512DQ-NEXT: vzeroupper @@ -5015,11 +5015,11 @@ define void @ktest_7(<64 x i8> %w, <64 x i8> %x, <64 x i8> %y, <64 x i8> %z) { ; X86-NEXT: kandq %k1, %k0, %k0 ; X86-NEXT: kshiftrq $32, %k0, %k1 ; X86-NEXT: kortestd %k1, %k0 -; X86-NEXT: je LBB78_1 -; X86-NEXT: ## %bb.2: ## %exit +; X86-NEXT: je LBB78_2 +; X86-NEXT: ## %bb.1: ## %exit ; X86-NEXT: vzeroupper ; X86-NEXT: retl -; X86-NEXT: LBB78_1: ## %bar +; X86-NEXT: LBB78_2: ## %bar ; X86-NEXT: subl $12, %esp ; X86-NEXT: .cfi_def_cfa_offset 16 ; X86-NEXT: vzeroupper diff --git a/llvm/test/CodeGen/X86/avx512-select.ll b/llvm/test/CodeGen/X86/avx512-select.ll index 721ffbe1ceb79..e11a3739c9e03 100644 --- a/llvm/test/CodeGen/X86/avx512-select.ll +++ b/llvm/test/CodeGen/X86/avx512-select.ll @@ -644,8 +644,8 @@ define void @select_v1i1(ptr %w, ptr %x, ptr %y, i1 %z) nounwind { ; X86-AVX512F: # %bb.0: ; X86-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-AVX512F-NEXT: testb $1, {{[0-9]+}}(%esp) -; X86-AVX512F-NEXT: jne .LBB18_1 -; X86-AVX512F-NEXT: # %bb.2: +; X86-AVX512F-NEXT: jne .LBB18_2 +; X86-AVX512F-NEXT: # %bb.1: ; X86-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-AVX512F-NEXT: movzbl (%edx), %edx @@ -654,7 +654,7 @@ define void @select_v1i1(ptr %w, ptr %x, ptr %y, i1 %z) nounwind { ; X86-AVX512F-NEXT: kmovw %ecx, %k1 ; X86-AVX512F-NEXT: kxorw %k1, %k0, %k0 ; X86-AVX512F-NEXT: jmp .LBB18_3 -; X86-AVX512F-NEXT: .LBB18_1: +; X86-AVX512F-NEXT: .LBB18_2: ; X86-AVX512F-NEXT: movzbl (%eax), %ecx ; X86-AVX512F-NEXT: kmovw %ecx, %k0 ; X86-AVX512F-NEXT: .LBB18_3: @@ -667,15 +667,15 @@ define void @select_v1i1(ptr %w, ptr %x, ptr %y, i1 %z) nounwind { ; X64-AVX512F-LABEL: select_v1i1: ; X64-AVX512F: # %bb.0: ; X64-AVX512F-NEXT: testb $1, %cl -; X64-AVX512F-NEXT: jne .LBB18_1 -; X64-AVX512F-NEXT: # %bb.2: +; X64-AVX512F-NEXT: jne .LBB18_2 +; X64-AVX512F-NEXT: # %bb.1: ; X64-AVX512F-NEXT: movzbl (%rdx), %eax ; X64-AVX512F-NEXT: kmovw %eax, %k0 ; X64-AVX512F-NEXT: movzbl (%rdi), %eax ; X64-AVX512F-NEXT: kmovw %eax, %k1 ; X64-AVX512F-NEXT: kxorw %k1, %k0, %k0 ; X64-AVX512F-NEXT: jmp .LBB18_3 -; X64-AVX512F-NEXT: .LBB18_1: +; X64-AVX512F-NEXT: .LBB18_2: ; X64-AVX512F-NEXT: movzbl (%rsi), %eax ; X64-AVX512F-NEXT: kmovw %eax, %k0 ; X64-AVX512F-NEXT: .LBB18_3: @@ -689,8 +689,8 @@ define void @select_v1i1(ptr %w, ptr %x, ptr %y, i1 %z) nounwind { ; X86-AVX512BW: # %bb.0: ; X86-AVX512BW-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-AVX512BW-NEXT: testb $1, {{[0-9]+}}(%esp) -; X86-AVX512BW-NEXT: jne .LBB18_1 -; X86-AVX512BW-NEXT: # %bb.2: +; X86-AVX512BW-NEXT: jne .LBB18_2 +; X86-AVX512BW-NEXT: # %bb.1: ; X86-AVX512BW-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-AVX512BW-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-AVX512BW-NEXT: movzbl (%edx), %edx @@ -699,7 +699,7 @@ define void @select_v1i1(ptr %w, ptr %x, ptr %y, i1 %z) nounwind { ; X86-AVX512BW-NEXT: kmovd %ecx, %k1 ; X86-AVX512BW-NEXT: kxorw %k1, %k0, %k0 ; X86-AVX512BW-NEXT: jmp .LBB18_3 -; X86-AVX512BW-NEXT: .LBB18_1: +; X86-AVX512BW-NEXT: .LBB18_2: ; X86-AVX512BW-NEXT: movzbl (%eax), %ecx ; X86-AVX512BW-NEXT: kmovd %ecx, %k0 ; X86-AVX512BW-NEXT: .LBB18_3: @@ -712,15 +712,15 @@ define void @select_v1i1(ptr %w, ptr %x, ptr %y, i1 %z) nounwind { ; X64-AVX512BW-LABEL: select_v1i1: ; X64-AVX512BW: # %bb.0: ; X64-AVX512BW-NEXT: testb $1, %cl -; X64-AVX512BW-NEXT: jne .LBB18_1 -; X64-AVX512BW-NEXT: # %bb.2: +; X64-AVX512BW-NEXT: jne .LBB18_2 +; X64-AVX512BW-NEXT: # %bb.1: ; X64-AVX512BW-NEXT: movzbl (%rdx), %eax ; X64-AVX512BW-NEXT: kmovd %eax, %k0 ; X64-AVX512BW-NEXT: movzbl (%rdi), %eax ; X64-AVX512BW-NEXT: kmovd %eax, %k1 ; X64-AVX512BW-NEXT: kxorw %k1, %k0, %k0 ; X64-AVX512BW-NEXT: jmp .LBB18_3 -; X64-AVX512BW-NEXT: .LBB18_1: +; X64-AVX512BW-NEXT: .LBB18_2: ; X64-AVX512BW-NEXT: movzbl (%rsi), %eax ; X64-AVX512BW-NEXT: kmovd %eax, %k0 ; X64-AVX512BW-NEXT: .LBB18_3: diff --git a/llvm/test/CodeGen/X86/avx512vnni-combine.ll b/llvm/test/CodeGen/X86/avx512vnni-combine.ll index b7d950e994241..e4dd8a903acaf 100644 --- a/llvm/test/CodeGen/X86/avx512vnni-combine.ll +++ b/llvm/test/CodeGen/X86/avx512vnni-combine.ll @@ -40,22 +40,22 @@ define <8 x i64> @foo_512(i32 %0, <8 x i64> %1, <8 x i64> %2, ptr %3) { ; CHECK-LABEL: foo_512: ; CHECK: # %bb.0: ; CHECK-NEXT: testl %edi, %edi -; CHECK-NEXT: jle .LBB1_6 +; CHECK-NEXT: jle .LBB1_8 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: movl %edi, %edx ; CHECK-NEXT: movl %edx, %eax ; CHECK-NEXT: andl $3, %eax ; CHECK-NEXT: cmpl $4, %edi -; CHECK-NEXT: jae .LBB1_7 +; CHECK-NEXT: jae .LBB1_3 ; CHECK-NEXT: # %bb.2: ; CHECK-NEXT: xorl %ecx, %ecx -; CHECK-NEXT: jmp .LBB1_3 -; CHECK-NEXT: .LBB1_7: +; CHECK-NEXT: jmp .LBB1_5 +; CHECK-NEXT: .LBB1_3: ; CHECK-NEXT: andl $-4, %edx ; CHECK-NEXT: leaq 192(%rsi), %rdi ; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB1_8: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: .LBB1_4: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vpdpwssd -192(%rdi), %zmm1, %zmm0 ; CHECK-NEXT: vpmaddwd -128(%rdi), %zmm1, %zmm2 ; CHECK-NEXT: vpaddd %zmm2, %zmm0, %zmm0 @@ -66,22 +66,22 @@ define <8 x i64> @foo_512(i32 %0, <8 x i64> %1, <8 x i64> %2, ptr %3) { ; CHECK-NEXT: addq $4, %rcx ; CHECK-NEXT: addq $256, %rdi # imm = 0x100 ; CHECK-NEXT: cmpq %rcx, %rdx -; CHECK-NEXT: jne .LBB1_8 -; CHECK-NEXT: .LBB1_3: +; CHECK-NEXT: jne .LBB1_4 +; CHECK-NEXT: .LBB1_5: ; CHECK-NEXT: testq %rax, %rax -; CHECK-NEXT: je .LBB1_6 -; CHECK-NEXT: # %bb.4: # %.preheader +; CHECK-NEXT: je .LBB1_8 +; CHECK-NEXT: # %bb.6: # %.preheader ; CHECK-NEXT: shlq $6, %rcx ; CHECK-NEXT: addq %rcx, %rsi ; CHECK-NEXT: shll $6, %eax ; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB1_5: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: .LBB1_7: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vpdpwssd (%rsi,%rcx), %zmm1, %zmm0 ; CHECK-NEXT: addq $64, %rcx ; CHECK-NEXT: cmpq %rcx, %rax -; CHECK-NEXT: jne .LBB1_5 -; CHECK-NEXT: .LBB1_6: +; CHECK-NEXT: jne .LBB1_7 +; CHECK-NEXT: .LBB1_8: ; CHECK-NEXT: retq %5 = icmp sgt i32 %0, 0 br i1 %5, label %6, label %33 @@ -166,21 +166,21 @@ define void @bar_512(i32 %0, ptr %1, <8 x i64> %2, ptr %3) { ; CHECK-LABEL: bar_512: ; CHECK: # %bb.0: ; CHECK-NEXT: testl %edi, %edi -; CHECK-NEXT: jle .LBB2_5 +; CHECK-NEXT: jle .LBB2_7 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: cmpl $1, %edi -; CHECK-NEXT: jne .LBB2_6 +; CHECK-NEXT: jne .LBB2_3 ; CHECK-NEXT: # %bb.2: ; CHECK-NEXT: xorl %ecx, %ecx -; CHECK-NEXT: jmp .LBB2_3 -; CHECK-NEXT: .LBB2_6: +; CHECK-NEXT: jmp .LBB2_5 +; CHECK-NEXT: .LBB2_3: ; CHECK-NEXT: movl %eax, %edi ; CHECK-NEXT: andl $-2, %edi ; CHECK-NEXT: movl $64, %r8d ; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB2_7: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: .LBB2_4: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vmovdqa64 (%rsi,%r8), %zmm1 ; CHECK-NEXT: vpmaddwd -64(%rdx,%r8), %zmm0, %zmm2 ; CHECK-NEXT: vpaddd -64(%rsi,%r8), %zmm2, %zmm2 @@ -191,16 +191,16 @@ define void @bar_512(i32 %0, ptr %1, <8 x i64> %2, ptr %3) { ; CHECK-NEXT: addq $2, %rcx ; CHECK-NEXT: subq $-128, %r8 ; CHECK-NEXT: cmpq %rcx, %rdi -; CHECK-NEXT: jne .LBB2_7 -; CHECK-NEXT: .LBB2_3: +; CHECK-NEXT: jne .LBB2_4 +; CHECK-NEXT: .LBB2_5: ; CHECK-NEXT: testb $1, %al -; CHECK-NEXT: je .LBB2_5 -; CHECK-NEXT: # %bb.4: +; CHECK-NEXT: je .LBB2_7 +; CHECK-NEXT: # %bb.6: ; CHECK-NEXT: shlq $6, %rcx ; CHECK-NEXT: vpmaddwd (%rdx,%rcx), %zmm0, %zmm0 ; CHECK-NEXT: vpaddd (%rsi,%rcx), %zmm0, %zmm0 ; CHECK-NEXT: vmovdqa64 %zmm0, (%rsi,%rcx) -; CHECK-NEXT: .LBB2_5: +; CHECK-NEXT: .LBB2_7: ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq %5 = icmp sgt i32 %0, 0 diff --git a/llvm/test/CodeGen/X86/avxvnni-combine.ll b/llvm/test/CodeGen/X86/avxvnni-combine.ll index 45f9a6475244e..938bd766baa5b 100644 --- a/llvm/test/CodeGen/X86/avxvnni-combine.ll +++ b/llvm/test/CodeGen/X86/avxvnni-combine.ll @@ -45,22 +45,22 @@ define <2 x i64> @foo_128(i32 %0, <2 x i64> %1, <2 x i64> %2, ptr %3) { ; AVX-LABEL: foo_128: ; AVX: # %bb.0: ; AVX-NEXT: testl %edi, %edi -; AVX-NEXT: jle .LBB1_6 +; AVX-NEXT: jle .LBB1_8 ; AVX-NEXT: # %bb.1: ; AVX-NEXT: movl %edi, %edx ; AVX-NEXT: movl %edx, %eax ; AVX-NEXT: andl $3, %eax ; AVX-NEXT: cmpl $4, %edi -; AVX-NEXT: jae .LBB1_7 +; AVX-NEXT: jae .LBB1_3 ; AVX-NEXT: # %bb.2: ; AVX-NEXT: xorl %ecx, %ecx -; AVX-NEXT: jmp .LBB1_3 -; AVX-NEXT: .LBB1_7: +; AVX-NEXT: jmp .LBB1_5 +; AVX-NEXT: .LBB1_3: ; AVX-NEXT: andl $-4, %edx ; AVX-NEXT: leaq 48(%rsi), %rdi ; AVX-NEXT: xorl %ecx, %ecx ; AVX-NEXT: .p2align 4 -; AVX-NEXT: .LBB1_8: # =>This Inner Loop Header: Depth=1 +; AVX-NEXT: .LBB1_4: # =>This Inner Loop Header: Depth=1 ; AVX-NEXT: {vex} vpdpwssd -48(%rdi), %xmm1, %xmm0 ; AVX-NEXT: vpmaddwd -32(%rdi), %xmm1, %xmm2 ; AVX-NEXT: vpaddd %xmm2, %xmm0, %xmm0 @@ -71,43 +71,43 @@ define <2 x i64> @foo_128(i32 %0, <2 x i64> %1, <2 x i64> %2, ptr %3) { ; AVX-NEXT: addq $4, %rcx ; AVX-NEXT: addq $64, %rdi ; AVX-NEXT: cmpq %rcx, %rdx -; AVX-NEXT: jne .LBB1_8 -; AVX-NEXT: .LBB1_3: +; AVX-NEXT: jne .LBB1_4 +; AVX-NEXT: .LBB1_5: ; AVX-NEXT: testq %rax, %rax -; AVX-NEXT: je .LBB1_6 -; AVX-NEXT: # %bb.4: # %.preheader +; AVX-NEXT: je .LBB1_8 +; AVX-NEXT: # %bb.6: # %.preheader ; AVX-NEXT: shlq $4, %rcx ; AVX-NEXT: addq %rcx, %rsi ; AVX-NEXT: shll $4, %eax ; AVX-NEXT: xorl %ecx, %ecx ; AVX-NEXT: .p2align 4 -; AVX-NEXT: .LBB1_5: # =>This Inner Loop Header: Depth=1 +; AVX-NEXT: .LBB1_7: # =>This Inner Loop Header: Depth=1 ; AVX-NEXT: {vex} vpdpwssd (%rsi,%rcx), %xmm1, %xmm0 ; AVX-NEXT: addq $16, %rcx ; AVX-NEXT: cmpq %rcx, %rax -; AVX-NEXT: jne .LBB1_5 -; AVX-NEXT: .LBB1_6: +; AVX-NEXT: jne .LBB1_7 +; AVX-NEXT: .LBB1_8: ; AVX-NEXT: retq ; ; AVX512-LABEL: foo_128: ; AVX512: # %bb.0: ; AVX512-NEXT: testl %edi, %edi -; AVX512-NEXT: jle .LBB1_6 +; AVX512-NEXT: jle .LBB1_8 ; AVX512-NEXT: # %bb.1: ; AVX512-NEXT: movl %edi, %edx ; AVX512-NEXT: movl %edx, %eax ; AVX512-NEXT: andl $3, %eax ; AVX512-NEXT: cmpl $4, %edi -; AVX512-NEXT: jae .LBB1_7 +; AVX512-NEXT: jae .LBB1_3 ; AVX512-NEXT: # %bb.2: ; AVX512-NEXT: xorl %ecx, %ecx -; AVX512-NEXT: jmp .LBB1_3 -; AVX512-NEXT: .LBB1_7: +; AVX512-NEXT: jmp .LBB1_5 +; AVX512-NEXT: .LBB1_3: ; AVX512-NEXT: andl $-4, %edx ; AVX512-NEXT: leaq 48(%rsi), %rdi ; AVX512-NEXT: xorl %ecx, %ecx ; AVX512-NEXT: .p2align 4 -; AVX512-NEXT: .LBB1_8: # =>This Inner Loop Header: Depth=1 +; AVX512-NEXT: .LBB1_4: # =>This Inner Loop Header: Depth=1 ; AVX512-NEXT: vpdpwssd -48(%rdi), %xmm1, %xmm0 ; AVX512-NEXT: vpmaddwd -32(%rdi), %xmm1, %xmm2 ; AVX512-NEXT: vpaddd %xmm2, %xmm0, %xmm0 @@ -118,22 +118,22 @@ define <2 x i64> @foo_128(i32 %0, <2 x i64> %1, <2 x i64> %2, ptr %3) { ; AVX512-NEXT: addq $4, %rcx ; AVX512-NEXT: addq $64, %rdi ; AVX512-NEXT: cmpq %rcx, %rdx -; AVX512-NEXT: jne .LBB1_8 -; AVX512-NEXT: .LBB1_3: +; AVX512-NEXT: jne .LBB1_4 +; AVX512-NEXT: .LBB1_5: ; AVX512-NEXT: testq %rax, %rax -; AVX512-NEXT: je .LBB1_6 -; AVX512-NEXT: # %bb.4: # %.preheader +; AVX512-NEXT: je .LBB1_8 +; AVX512-NEXT: # %bb.6: # %.preheader ; AVX512-NEXT: shlq $4, %rcx ; AVX512-NEXT: addq %rcx, %rsi ; AVX512-NEXT: shll $4, %eax ; AVX512-NEXT: xorl %ecx, %ecx ; AVX512-NEXT: .p2align 4 -; AVX512-NEXT: .LBB1_5: # =>This Inner Loop Header: Depth=1 +; AVX512-NEXT: .LBB1_7: # =>This Inner Loop Header: Depth=1 ; AVX512-NEXT: vpdpwssd (%rsi,%rcx), %xmm1, %xmm0 ; AVX512-NEXT: addq $16, %rcx ; AVX512-NEXT: cmpq %rcx, %rax -; AVX512-NEXT: jne .LBB1_5 -; AVX512-NEXT: .LBB1_6: +; AVX512-NEXT: jne .LBB1_7 +; AVX512-NEXT: .LBB1_8: ; AVX512-NEXT: retq %5 = icmp sgt i32 %0, 0 br i1 %5, label %6, label %33 @@ -212,21 +212,21 @@ define void @bar_128(i32 %0, ptr %1, <2 x i64> %2, ptr %3) { ; AVX-LABEL: bar_128: ; AVX: # %bb.0: ; AVX-NEXT: testl %edi, %edi -; AVX-NEXT: jle .LBB2_5 +; AVX-NEXT: jle .LBB2_7 ; AVX-NEXT: # %bb.1: ; AVX-NEXT: movl %edi, %eax ; AVX-NEXT: cmpl $1, %edi -; AVX-NEXT: jne .LBB2_6 +; AVX-NEXT: jne .LBB2_3 ; AVX-NEXT: # %bb.2: ; AVX-NEXT: xorl %ecx, %ecx -; AVX-NEXT: jmp .LBB2_3 -; AVX-NEXT: .LBB2_6: +; AVX-NEXT: jmp .LBB2_5 +; AVX-NEXT: .LBB2_3: ; AVX-NEXT: movl %eax, %edi ; AVX-NEXT: andl $-2, %edi ; AVX-NEXT: movl $16, %r8d ; AVX-NEXT: xorl %ecx, %ecx ; AVX-NEXT: .p2align 4 -; AVX-NEXT: .LBB2_7: # =>This Inner Loop Header: Depth=1 +; AVX-NEXT: .LBB2_4: # =>This Inner Loop Header: Depth=1 ; AVX-NEXT: vmovdqa (%rsi,%r8), %xmm1 ; AVX-NEXT: vpmaddwd -16(%rdx,%r8), %xmm0, %xmm2 ; AVX-NEXT: vpaddd -16(%rsi,%r8), %xmm2, %xmm2 @@ -237,36 +237,36 @@ define void @bar_128(i32 %0, ptr %1, <2 x i64> %2, ptr %3) { ; AVX-NEXT: addq $2, %rcx ; AVX-NEXT: addq $32, %r8 ; AVX-NEXT: cmpq %rcx, %rdi -; AVX-NEXT: jne .LBB2_7 -; AVX-NEXT: .LBB2_3: +; AVX-NEXT: jne .LBB2_4 +; AVX-NEXT: .LBB2_5: ; AVX-NEXT: testb $1, %al -; AVX-NEXT: je .LBB2_5 -; AVX-NEXT: # %bb.4: +; AVX-NEXT: je .LBB2_7 +; AVX-NEXT: # %bb.6: ; AVX-NEXT: shlq $4, %rcx ; AVX-NEXT: vmovdqa (%rsi,%rcx), %xmm1 ; AVX-NEXT: {vex} vpdpwssd (%rdx,%rcx), %xmm0, %xmm1 ; AVX-NEXT: vmovdqa %xmm1, (%rsi,%rcx) -; AVX-NEXT: .LBB2_5: +; AVX-NEXT: .LBB2_7: ; AVX-NEXT: retq ; ; AVX512-LABEL: bar_128: ; AVX512: # %bb.0: ; AVX512-NEXT: testl %edi, %edi -; AVX512-NEXT: jle .LBB2_5 +; AVX512-NEXT: jle .LBB2_7 ; AVX512-NEXT: # %bb.1: ; AVX512-NEXT: movl %edi, %eax ; AVX512-NEXT: cmpl $1, %edi -; AVX512-NEXT: jne .LBB2_6 +; AVX512-NEXT: jne .LBB2_3 ; AVX512-NEXT: # %bb.2: ; AVX512-NEXT: xorl %ecx, %ecx -; AVX512-NEXT: jmp .LBB2_3 -; AVX512-NEXT: .LBB2_6: +; AVX512-NEXT: jmp .LBB2_5 +; AVX512-NEXT: .LBB2_3: ; AVX512-NEXT: movl %eax, %edi ; AVX512-NEXT: andl $-2, %edi ; AVX512-NEXT: movl $16, %r8d ; AVX512-NEXT: xorl %ecx, %ecx ; AVX512-NEXT: .p2align 4 -; AVX512-NEXT: .LBB2_7: # =>This Inner Loop Header: Depth=1 +; AVX512-NEXT: .LBB2_4: # =>This Inner Loop Header: Depth=1 ; AVX512-NEXT: vmovdqa (%rsi,%r8), %xmm1 ; AVX512-NEXT: vpmaddwd -16(%rdx,%r8), %xmm0, %xmm2 ; AVX512-NEXT: vpaddd -16(%rsi,%r8), %xmm2, %xmm2 @@ -277,16 +277,16 @@ define void @bar_128(i32 %0, ptr %1, <2 x i64> %2, ptr %3) { ; AVX512-NEXT: addq $2, %rcx ; AVX512-NEXT: addq $32, %r8 ; AVX512-NEXT: cmpq %rcx, %rdi -; AVX512-NEXT: jne .LBB2_7 -; AVX512-NEXT: .LBB2_3: +; AVX512-NEXT: jne .LBB2_4 +; AVX512-NEXT: .LBB2_5: ; AVX512-NEXT: testb $1, %al -; AVX512-NEXT: je .LBB2_5 -; AVX512-NEXT: # %bb.4: +; AVX512-NEXT: je .LBB2_7 +; AVX512-NEXT: # %bb.6: ; AVX512-NEXT: shlq $4, %rcx ; AVX512-NEXT: vpmaddwd (%rdx,%rcx), %xmm0, %xmm0 ; AVX512-NEXT: vpaddd (%rsi,%rcx), %xmm0, %xmm0 ; AVX512-NEXT: vmovdqa %xmm0, (%rsi,%rcx) -; AVX512-NEXT: .LBB2_5: +; AVX512-NEXT: .LBB2_7: ; AVX512-NEXT: retq %5 = icmp sgt i32 %0, 0 br i1 %5, label %6, label %22 @@ -392,22 +392,22 @@ define <4 x i64> @foo_256(i32 %0, <4 x i64> %1, <4 x i64> %2, ptr %3) { ; AVX-LABEL: foo_256: ; AVX: # %bb.0: ; AVX-NEXT: testl %edi, %edi -; AVX-NEXT: jle .LBB4_6 +; AVX-NEXT: jle .LBB4_8 ; AVX-NEXT: # %bb.1: ; AVX-NEXT: movl %edi, %edx ; AVX-NEXT: movl %edx, %eax ; AVX-NEXT: andl $3, %eax ; AVX-NEXT: cmpl $4, %edi -; AVX-NEXT: jae .LBB4_7 +; AVX-NEXT: jae .LBB4_3 ; AVX-NEXT: # %bb.2: ; AVX-NEXT: xorl %ecx, %ecx -; AVX-NEXT: jmp .LBB4_3 -; AVX-NEXT: .LBB4_7: +; AVX-NEXT: jmp .LBB4_5 +; AVX-NEXT: .LBB4_3: ; AVX-NEXT: andl $-4, %edx ; AVX-NEXT: leaq 96(%rsi), %rdi ; AVX-NEXT: xorl %ecx, %ecx ; AVX-NEXT: .p2align 4 -; AVX-NEXT: .LBB4_8: # =>This Inner Loop Header: Depth=1 +; AVX-NEXT: .LBB4_4: # =>This Inner Loop Header: Depth=1 ; AVX-NEXT: {vex} vpdpwssd -96(%rdi), %ymm1, %ymm0 ; AVX-NEXT: vpmaddwd -64(%rdi), %ymm1, %ymm2 ; AVX-NEXT: vpaddd %ymm2, %ymm0, %ymm0 @@ -418,43 +418,43 @@ define <4 x i64> @foo_256(i32 %0, <4 x i64> %1, <4 x i64> %2, ptr %3) { ; AVX-NEXT: addq $4, %rcx ; AVX-NEXT: subq $-128, %rdi ; AVX-NEXT: cmpq %rcx, %rdx -; AVX-NEXT: jne .LBB4_8 -; AVX-NEXT: .LBB4_3: +; AVX-NEXT: jne .LBB4_4 +; AVX-NEXT: .LBB4_5: ; AVX-NEXT: testq %rax, %rax -; AVX-NEXT: je .LBB4_6 -; AVX-NEXT: # %bb.4: # %.preheader +; AVX-NEXT: je .LBB4_8 +; AVX-NEXT: # %bb.6: # %.preheader ; AVX-NEXT: shlq $5, %rcx ; AVX-NEXT: addq %rcx, %rsi ; AVX-NEXT: shll $5, %eax ; AVX-NEXT: xorl %ecx, %ecx ; AVX-NEXT: .p2align 4 -; AVX-NEXT: .LBB4_5: # =>This Inner Loop Header: Depth=1 +; AVX-NEXT: .LBB4_7: # =>This Inner Loop Header: Depth=1 ; AVX-NEXT: {vex} vpdpwssd (%rsi,%rcx), %ymm1, %ymm0 ; AVX-NEXT: addq $32, %rcx ; AVX-NEXT: cmpq %rcx, %rax -; AVX-NEXT: jne .LBB4_5 -; AVX-NEXT: .LBB4_6: +; AVX-NEXT: jne .LBB4_7 +; AVX-NEXT: .LBB4_8: ; AVX-NEXT: retq ; ; AVX512-LABEL: foo_256: ; AVX512: # %bb.0: ; AVX512-NEXT: testl %edi, %edi -; AVX512-NEXT: jle .LBB4_6 +; AVX512-NEXT: jle .LBB4_8 ; AVX512-NEXT: # %bb.1: ; AVX512-NEXT: movl %edi, %edx ; AVX512-NEXT: movl %edx, %eax ; AVX512-NEXT: andl $3, %eax ; AVX512-NEXT: cmpl $4, %edi -; AVX512-NEXT: jae .LBB4_7 +; AVX512-NEXT: jae .LBB4_3 ; AVX512-NEXT: # %bb.2: ; AVX512-NEXT: xorl %ecx, %ecx -; AVX512-NEXT: jmp .LBB4_3 -; AVX512-NEXT: .LBB4_7: +; AVX512-NEXT: jmp .LBB4_5 +; AVX512-NEXT: .LBB4_3: ; AVX512-NEXT: andl $-4, %edx ; AVX512-NEXT: leaq 96(%rsi), %rdi ; AVX512-NEXT: xorl %ecx, %ecx ; AVX512-NEXT: .p2align 4 -; AVX512-NEXT: .LBB4_8: # =>This Inner Loop Header: Depth=1 +; AVX512-NEXT: .LBB4_4: # =>This Inner Loop Header: Depth=1 ; AVX512-NEXT: vpdpwssd -96(%rdi), %ymm1, %ymm0 ; AVX512-NEXT: vpmaddwd -64(%rdi), %ymm1, %ymm2 ; AVX512-NEXT: vpaddd %ymm2, %ymm0, %ymm0 @@ -465,22 +465,22 @@ define <4 x i64> @foo_256(i32 %0, <4 x i64> %1, <4 x i64> %2, ptr %3) { ; AVX512-NEXT: addq $4, %rcx ; AVX512-NEXT: subq $-128, %rdi ; AVX512-NEXT: cmpq %rcx, %rdx -; AVX512-NEXT: jne .LBB4_8 -; AVX512-NEXT: .LBB4_3: +; AVX512-NEXT: jne .LBB4_4 +; AVX512-NEXT: .LBB4_5: ; AVX512-NEXT: testq %rax, %rax -; AVX512-NEXT: je .LBB4_6 -; AVX512-NEXT: # %bb.4: # %.preheader +; AVX512-NEXT: je .LBB4_8 +; AVX512-NEXT: # %bb.6: # %.preheader ; AVX512-NEXT: shlq $5, %rcx ; AVX512-NEXT: addq %rcx, %rsi ; AVX512-NEXT: shll $5, %eax ; AVX512-NEXT: xorl %ecx, %ecx ; AVX512-NEXT: .p2align 4 -; AVX512-NEXT: .LBB4_5: # =>This Inner Loop Header: Depth=1 +; AVX512-NEXT: .LBB4_7: # =>This Inner Loop Header: Depth=1 ; AVX512-NEXT: vpdpwssd (%rsi,%rcx), %ymm1, %ymm0 ; AVX512-NEXT: addq $32, %rcx ; AVX512-NEXT: cmpq %rcx, %rax -; AVX512-NEXT: jne .LBB4_5 -; AVX512-NEXT: .LBB4_6: +; AVX512-NEXT: jne .LBB4_7 +; AVX512-NEXT: .LBB4_8: ; AVX512-NEXT: retq %5 = icmp sgt i32 %0, 0 br i1 %5, label %6, label %33 @@ -566,21 +566,21 @@ define void @bar_256(i32 %0, ptr %1, <4 x i64> %2, ptr %3) { ; AVX-LABEL: bar_256: ; AVX: # %bb.0: ; AVX-NEXT: testl %edi, %edi -; AVX-NEXT: jle .LBB5_5 +; AVX-NEXT: jle .LBB5_7 ; AVX-NEXT: # %bb.1: ; AVX-NEXT: movl %edi, %eax ; AVX-NEXT: cmpl $1, %edi -; AVX-NEXT: jne .LBB5_6 +; AVX-NEXT: jne .LBB5_3 ; AVX-NEXT: # %bb.2: ; AVX-NEXT: xorl %ecx, %ecx -; AVX-NEXT: jmp .LBB5_3 -; AVX-NEXT: .LBB5_6: +; AVX-NEXT: jmp .LBB5_5 +; AVX-NEXT: .LBB5_3: ; AVX-NEXT: movl %eax, %edi ; AVX-NEXT: andl $-2, %edi ; AVX-NEXT: movl $32, %r8d ; AVX-NEXT: xorl %ecx, %ecx ; AVX-NEXT: .p2align 4 -; AVX-NEXT: .LBB5_7: # =>This Inner Loop Header: Depth=1 +; AVX-NEXT: .LBB5_4: # =>This Inner Loop Header: Depth=1 ; AVX-NEXT: vmovdqa (%rsi,%r8), %ymm1 ; AVX-NEXT: vpmaddwd -32(%rdx,%r8), %ymm0, %ymm2 ; AVX-NEXT: vpaddd -32(%rsi,%r8), %ymm2, %ymm2 @@ -591,37 +591,37 @@ define void @bar_256(i32 %0, ptr %1, <4 x i64> %2, ptr %3) { ; AVX-NEXT: addq $2, %rcx ; AVX-NEXT: addq $64, %r8 ; AVX-NEXT: cmpq %rcx, %rdi -; AVX-NEXT: jne .LBB5_7 -; AVX-NEXT: .LBB5_3: +; AVX-NEXT: jne .LBB5_4 +; AVX-NEXT: .LBB5_5: ; AVX-NEXT: testb $1, %al -; AVX-NEXT: je .LBB5_5 -; AVX-NEXT: # %bb.4: +; AVX-NEXT: je .LBB5_7 +; AVX-NEXT: # %bb.6: ; AVX-NEXT: shlq $5, %rcx ; AVX-NEXT: vmovdqa (%rsi,%rcx), %ymm1 ; AVX-NEXT: {vex} vpdpwssd (%rdx,%rcx), %ymm0, %ymm1 ; AVX-NEXT: vmovdqa %ymm1, (%rsi,%rcx) -; AVX-NEXT: .LBB5_5: +; AVX-NEXT: .LBB5_7: ; AVX-NEXT: vzeroupper ; AVX-NEXT: retq ; ; AVX512-LABEL: bar_256: ; AVX512: # %bb.0: ; AVX512-NEXT: testl %edi, %edi -; AVX512-NEXT: jle .LBB5_5 +; AVX512-NEXT: jle .LBB5_7 ; AVX512-NEXT: # %bb.1: ; AVX512-NEXT: movl %edi, %eax ; AVX512-NEXT: cmpl $1, %edi -; AVX512-NEXT: jne .LBB5_6 +; AVX512-NEXT: jne .LBB5_3 ; AVX512-NEXT: # %bb.2: ; AVX512-NEXT: xorl %ecx, %ecx -; AVX512-NEXT: jmp .LBB5_3 -; AVX512-NEXT: .LBB5_6: +; AVX512-NEXT: jmp .LBB5_5 +; AVX512-NEXT: .LBB5_3: ; AVX512-NEXT: movl %eax, %edi ; AVX512-NEXT: andl $-2, %edi ; AVX512-NEXT: movl $32, %r8d ; AVX512-NEXT: xorl %ecx, %ecx ; AVX512-NEXT: .p2align 4 -; AVX512-NEXT: .LBB5_7: # =>This Inner Loop Header: Depth=1 +; AVX512-NEXT: .LBB5_4: # =>This Inner Loop Header: Depth=1 ; AVX512-NEXT: vmovdqa (%rsi,%r8), %ymm1 ; AVX512-NEXT: vpmaddwd -32(%rdx,%r8), %ymm0, %ymm2 ; AVX512-NEXT: vpaddd -32(%rsi,%r8), %ymm2, %ymm2 @@ -632,16 +632,16 @@ define void @bar_256(i32 %0, ptr %1, <4 x i64> %2, ptr %3) { ; AVX512-NEXT: addq $2, %rcx ; AVX512-NEXT: addq $64, %r8 ; AVX512-NEXT: cmpq %rcx, %rdi -; AVX512-NEXT: jne .LBB5_7 -; AVX512-NEXT: .LBB5_3: +; AVX512-NEXT: jne .LBB5_4 +; AVX512-NEXT: .LBB5_5: ; AVX512-NEXT: testb $1, %al -; AVX512-NEXT: je .LBB5_5 -; AVX512-NEXT: # %bb.4: +; AVX512-NEXT: je .LBB5_7 +; AVX512-NEXT: # %bb.6: ; AVX512-NEXT: shlq $5, %rcx ; AVX512-NEXT: vpmaddwd (%rdx,%rcx), %ymm0, %ymm0 ; AVX512-NEXT: vpaddd (%rsi,%rcx), %ymm0, %ymm0 ; AVX512-NEXT: vmovdqa %ymm0, (%rsi,%rcx) -; AVX512-NEXT: .LBB5_5: +; AVX512-NEXT: .LBB5_7: ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %5 = icmp sgt i32 %0, 0 diff --git a/llvm/test/CodeGen/X86/basic-block-sections-cloning-1.ll b/llvm/test/CodeGen/X86/basic-block-sections-cloning-1.ll index 0f84b891a7c52..3f31c8b3bbfeb 100644 --- a/llvm/test/CodeGen/X86/basic-block-sections-cloning-1.ll +++ b/llvm/test/CodeGen/X86/basic-block-sections-cloning-1.ll @@ -50,20 +50,20 @@ cold: ; CHECK: .section .text.foo,"ax",@progbits ; CHECK: foo: ; CHECK: # %bb.0: # %b0 -; CHECK: jne .LBB0_1 -; CHECK-NEXT: # %bb.7: # %b3 -; CHECK: jne .LBB0_4 -; CHECK-NEXT: # %bb.8: # %b5 +; CHECK: jne .LBB0_3 +; CHECK-NEXT: # %bb.1: # %b3 +; CHECK: jne .LBB0_6 +; CHECK-NEXT: # %bb.2: # %b5 ; CHECK: retq -; CHECK-NEXT: .LBB0_1: # %b1 -; CHECK: je .LBB0_3 -; CHECK-NEXT: # %bb.2: # %b2 -; CHECK: callq effect@PLT -; CHECK-NEXT: .LBB0_3: # %b3 +; CHECK-NEXT: .LBB0_3: # %b1 ; CHECK: je .LBB0_5 -; CHECK-NEXT: .LBB0_4: # %b4 +; CHECK-NEXT: # %bb.4: # %b2 +; CHECK: callq effect@PLT +; CHECK-NEXT: .LBB0_5: # %b3 +; CHECK: je .LBB0_7 +; CHECK-NEXT: .LBB0_6: # %b4 ; CHECK: je foo.cold -; CHECK-NEXT: .LBB0_5: # %b5 +; CHECK-NEXT: .LBB0_7: # %b5 ; CHECK: retq ;; split section diff --git a/llvm/test/CodeGen/X86/basic-block-sections-cloning-2.ll b/llvm/test/CodeGen/X86/basic-block-sections-cloning-2.ll index c433491a49430..aec7a9d78b206 100644 --- a/llvm/test/CodeGen/X86/basic-block-sections-cloning-2.ll +++ b/llvm/test/CodeGen/X86/basic-block-sections-cloning-2.ll @@ -55,28 +55,28 @@ cold: ; CHECK: foo: ; CHECK: # %bb.0: # %b0 ; CHECK: jne foo.__part.1 -; CHECK-NEXT: # %bb.7: # %b3 -; CHECK: jne .LBB0_4 -; CHECK-NEXT: # %bb.8: # %b5 +; CHECK-NEXT: # %bb.1: # %b3 +; CHECK: jne .LBB0_9 +; CHECK-NEXT: # %bb.2: # %b5 ; CHECK: retq ;; second cluster: ; CHECK: .section .text.foo,"ax",@progbits,unique,1 ; CHECK-NEXT: foo.__part.1: # %b1 -; CHECK: jne .LBB0_2 -; CHECK-NEXT: # %bb.9: # %b3 -; CHECK: je .LBB0_5 -; CHECK-NEXT: # %bb.10: # %b4 +; CHECK: jne .LBB0_7 +; CHECK-NEXT: # %bb.4: # %b3 +; CHECK: je .LBB0_10 +; CHECK-NEXT: # %bb.5: # %b4 ; CHECK: je foo.cold -; CHECK-NEXT: # %bb.11: # %b5 +; CHECK-NEXT: # %bb.6: # %b5 ; CHECK: retq -; CHECK-NEXT: .LBB0_2: # %b2 +; CHECK-NEXT: .LBB0_7: # %b2 ; CHECK: callq effect@PLT -; CHECK-NEXT: # %bb.3: # %b3 -; CHECK: je .LBB0_5 -; CHECK-NEXT: .LBB0_4: # %b4 +; CHECK-NEXT: # %bb.8: # %b3 +; CHECK: je .LBB0_10 +; CHECK-NEXT: .LBB0_9: # %b4 ; CHECK: je foo.cold -; CHECK-NEXT: .LBB0_5: # %b5 +; CHECK-NEXT: .LBB0_10: # %b5 ; CHECK: retq ;; split section diff --git a/llvm/test/CodeGen/X86/basic-block-sections-cloning-indirect.ll b/llvm/test/CodeGen/X86/basic-block-sections-cloning-indirect.ll index 3d9a8d36ca105..b873d114f6aed 100644 --- a/llvm/test/CodeGen/X86/basic-block-sections-cloning-indirect.ll +++ b/llvm/test/CodeGen/X86/basic-block-sections-cloning-indirect.ll @@ -31,12 +31,12 @@ b3: ; CHECK: bar: ; CHECK: # %bb.0: # %b0 ; CHECK: je .LBB0_2 -; CHECK-NEXT: # %bb.4: # %b1 +; CHECK-NEXT: # %bb.1: # %b1 ; CHECK: jmpq *%rax ; CHECK-NEXT: .Ltmp0: # Block address taken ; CHECK-NEXT: .LBB0_2: # %b2 ; CHECK: retq -; CHECK-NEXT: # %bb.1: # %b1 +; CHECK-NEXT: # %bb.3: # %b1 ; CHECK: jmpq *%rax ; CHECK: .section .text.split.bar,"ax",@progbits ; CHECK: bar.cold: # %b3 diff --git a/llvm/test/CodeGen/X86/basic-block-sections-cloning-invalid.ll b/llvm/test/CodeGen/X86/basic-block-sections-cloning-invalid.ll index 3c3c4b55e89b3..cfbdc53e42bec 100644 --- a/llvm/test/CodeGen/X86/basic-block-sections-cloning-invalid.ll +++ b/llvm/test/CodeGen/X86/basic-block-sections-cloning-invalid.ll @@ -72,9 +72,9 @@ cold: ; CHECK: # %bb.0: # %b0 ; CHECK: je .LBB0_3 -; PATH: # %bb.7: # %b1 -; PATH: # %bb.8: # %b2 -; PATH: jne .LBB0_4 +; PATH: # %bb.1: # %b1 +; PATH: # %bb.2: # %b2 +; PATH: jne .LBB0_7 ; CHECK: # %bb.1: # %b1 ; CHECK: jne foo.cold diff --git a/llvm/test/CodeGen/X86/basic-block-sections-clusters-bb-hash.ll b/llvm/test/CodeGen/X86/basic-block-sections-clusters-bb-hash.ll index 6fe7bf5c25cd4..ed3342880e903 100644 --- a/llvm/test/CodeGen/X86/basic-block-sections-clusters-bb-hash.ll +++ b/llvm/test/CodeGen/X86/basic-block-sections-clusters-bb-hash.ll @@ -78,16 +78,16 @@ declare i32 @baz() #1 ; CHECK-NOT: .section ; CHECK-NOT: .LBB_END0_{{0-9}}+ ; LINUX-SECTIONS1-LABEL: # %bb.1: -; LINUX-SECTIONS2-LABEL: # %bb.2: +; LINUX-SECTIONS2-LABEL: # %bb.1: ; CHECK-NOT: .section ; CHECK-NOT: .LBB_END0_{{0-9}}+ -; CHECK-LABEL: .LBB0_3: -; CHECK-LABEL: .LBB_END0_3: +; CHECK-LABEL: .LBB0_2: +; CHECK-LABEL: .LBB_END0_2: ; CHECK-NEXT: .section .text.split.foo,"ax",@progbits ; CHECK-LABEL: foo.cold: -; LINUX-SECTIONS1-LABEL: .LBB_END0_2: -; LINUX-SECTIONS2-LABEL: .LBB_END0_1: -; LINUX-SECTIONS1-LABEL: .size foo.cold, .LBB_END0_2-foo.cold -; LINUX-SECTIONS2-LABEL: .size foo.cold, .LBB_END0_1-foo.cold +; LINUX-SECTIONS1-LABEL: .LBB_END0_3: +; LINUX-SECTIONS2-LABEL: .LBB_END0_3: +; LINUX-SECTIONS1-LABEL: .size foo.cold, .LBB_END0_3-foo.cold +; LINUX-SECTIONS2-LABEL: .size foo.cold, .LBB_END0_3-foo.cold ; CHECK-LABEL: .Lfunc_end0: ; CHECK-NEXT: .size foo, .Lfunc_end0-foo diff --git a/llvm/test/CodeGen/X86/basic-block-sections-clusters-branches.ll b/llvm/test/CodeGen/X86/basic-block-sections-clusters-branches.ll index b463454e07c6b..97190ccd4ba0d 100644 --- a/llvm/test/CodeGen/X86/basic-block-sections-clusters-branches.ll +++ b/llvm/test/CodeGen/X86/basic-block-sections-clusters-branches.ll @@ -45,7 +45,7 @@ declare i32 @baz() #1 ; LINUX-SECTIONS1-LABEL: foo: ; LINUX-SECTIONS1: jne foo.__part.1 ; LINUX-SECTIONS1-NOT: {{jne|je|jmp}} -; LINUX-SECTIONS1-LABEL: # %bb.2: +; LINUX-SECTIONS1-LABEL: # %bb.1: ; LINUX-SECTIONS1: jmp foo.cold ; LINUX-SECTIONS1: .section .text.foo,"ax",@progbits,unique,1 ; LINUX-SECTIONS1-LABEL: foo.__part.1: @@ -57,7 +57,7 @@ declare i32 @baz() #1 ; LINUX-SECTIONS2-LABEL: foo: ; LINUX-SECTIONS2: jne foo.__part.0 ; LINUX-SECTIONS2-NOT: {{jne|je|jmp}} -; LINUX-SECTIONS2-LABEL: # %bb.2: +; LINUX-SECTIONS2-LABEL: # %bb.1: ; LINUX-SECTIONS2: jmp .LBB0_3 ; LINUX-SECTIONS2: .section .text.foo,"ax",@progbits,unique,1 ; LINUX-SECTIONS2: foo.__part.0: diff --git a/llvm/test/CodeGen/X86/basic-block-sections-clusters-eh.ll b/llvm/test/CodeGen/X86/basic-block-sections-clusters-eh.ll index 77b4b27ac046d..3bb37e945f47e 100644 --- a/llvm/test/CodeGen/X86/basic-block-sections-clusters-eh.ll +++ b/llvm/test/CodeGen/X86/basic-block-sections-clusters-eh.ll @@ -54,17 +54,17 @@ declare i32 @__gxx_personality_v0(...) ; LINUX-SECTIONS1: .section .text.main,"ax",@progbits ; LINUX-SECTIONS1-LABEL: main: ; LINUX-SECTIONS1-NOT: .section -; LINUX-SECTIONS1-LABEL: .LBB0_4: +; LINUX-SECTIONS1-LABEL: .LBB0_1: ; LINUX-SECTIONS1-NOT: .section -; LINUX-SECTIONS1-LABEL: .LBB0_5: +; LINUX-SECTIONS1-LABEL: .LBB0_2: ; LINUX-SECTIONS1-NOT: .section -; LINUX-SECTIONS1-LABEL: .LBB0_6: +; LINUX-SECTIONS1-LABEL: .LBB0_3: ; LINUX-SECTIONS1: .section .text.main,"ax",@progbits,unique,1 ; LINUX-SECTIONS1-LABEL: main.__part.0: ; LINUX-SECTIONS1: .section .text.eh.main,"ax",@progbits ; LINUX-SECTIONS1-LABEL: main.eh: ; LINUX-SECTIONS1-NOT: .section -; LINUX-SECTIONS1-LABEL: .LBB0_3: +; LINUX-SECTIONS1-LABEL: .LBB0_6: ; LINUX-SECTIONS1-NOT: .section ; LINUX-SECTIONS1: .section .text.main,"ax",@progbits ; LINUX-SECTIONS1-LABEL: .Lfunc_end0 @@ -73,16 +73,16 @@ declare i32 @__gxx_personality_v0(...) ; LINUX-SECTIONS2: .section .text.main,"ax",@progbits ; LINUX-SECTIONS2-LABEL: main: ; LINUX-SECTIONS2-NOT: .section -; LINUX-SECTIONS2-LABEL: .LBB0_4: +; LINUX-SECTIONS2-LABEL: .LBB0_1: ; LINUX-SECTIONS2-NOT: .section -; LINUX-SECTIONS2-LABEL: .LBB0_5: +; LINUX-SECTIONS2-LABEL: .LBB0_2: ; LINUX-SECTIONS2-NOT: .section -; LINUX-SECTIONS2-LABEL: .LBB0_6: +; LINUX-SECTIONS2-LABEL: .LBB0_3: ; LINUX-SECTIONS2: .section .text.main,"ax",@progbits,unique,1 ; LINUX-SECTIONS2-LABEL: main.__part.0: ; LINUX-SECTIONS2-NOT: .section -; LINUX-SECTIONS2-LABEL: .LBB0_2: +; LINUX-SECTIONS2-LABEL: .LBB0_5: ; LINUX-SECTIONS2-NOT: .section -; LINUX-SECTIONS2-LABEL: .LBB0_3: +; LINUX-SECTIONS2-LABEL: .LBB0_6: ; LINUX-SECTIONS2: .section .text.main,"ax",@progbits ; LINUX-SECTIONS2-LABEL: .Lfunc_end0 diff --git a/llvm/test/CodeGen/X86/basic-block-sections-clusters.ll b/llvm/test/CodeGen/X86/basic-block-sections-clusters.ll index a2ea84ff88592..09c4b293ab81f 100644 --- a/llvm/test/CodeGen/X86/basic-block-sections-clusters.ll +++ b/llvm/test/CodeGen/X86/basic-block-sections-clusters.ll @@ -57,12 +57,12 @@ declare i32 @baz() #1 ; LINUX-SECTIONS1-LABEL: foo: ; LINUX-SECTIONS1-NOT: .section ; LINUX-SECTIONS1-NOT: .LBB_END0_{{0-9}}+ -; LINUX-SECTIONS1-LABEL: # %bb.2: +; LINUX-SECTIONS1-LABEL: # %bb.1: ; LINUX-SECTIONS1-NOT: .LBB_END0_{{0-9}}+ ; LINUX-SECTIONS1: .section .text.foo,"ax",@progbits,unique,1 ; LINUX-SECTIONS1-LABEL: foo.__part.1: -; LINUX-SECTIONS1-LABEL: .LBB_END0_1: -; LINUX-SECTIONS1-NEXT: .size foo.__part.1, .LBB_END0_1-foo.__part.1 +; LINUX-SECTIONS1-LABEL: .LBB_END0_2: +; LINUX-SECTIONS1-NEXT: .size foo.__part.1, .LBB_END0_2-foo.__part.1 ; LINUX-SECTIONS1-NOT: .section ; LINUX-SECTIONS1: .section .text.split.foo,"ax",@progbits ; LINUX-SECTIONS1-LABEL: foo.cold: @@ -77,7 +77,7 @@ declare i32 @baz() #1 ; LINUX-SECTIONS2-LABEL: foo: ; LINUX-SECTIONS2-NOT: .LBB_END0_{{0-9}}+ ; LINUX-SECTIONS2-NOT: .section -; LINUX-SECTIONS2-LABEL: # %bb.2: +; LINUX-SECTIONS2-LABEL: # %bb.1: ; LINUX-SECTIONS2-NOT: .LBB_END0_{{0-9}}+ ; LINUX-SECTIONS2: .section .text.foo,"ax",@progbits,unique,1 ; LINUX-SECTIONS2-NEXT: foo.__part.0: diff --git a/llvm/test/CodeGen/X86/basic-block-sections-entryblock.ll b/llvm/test/CodeGen/X86/basic-block-sections-entryblock.ll index 349015e1403df..b23722f0b6559 100644 --- a/llvm/test/CodeGen/X86/basic-block-sections-entryblock.ll +++ b/llvm/test/CodeGen/X86/basic-block-sections-entryblock.ll @@ -26,7 +26,7 @@ b2: ; preds = %b0 ; LINUX-SECTIONS1: foo: ; LINUX-SECTIONS1: # %bb.0: # %b0 ; LINUX-SECTIONS1: jne foo.cold -; LINUX-SECTIONS1: # %bb.2: # %b2 +; LINUX-SECTIONS1: # %bb.1: # %b2 ; LINUX-SECTIONS1: retq ; LINUX-SECTIONS1: .section .text.split.foo,"ax",@progbits ; LINUX-SECTIONS1: foo.cold: # %b1 diff --git a/llvm/test/CodeGen/X86/bfloat.ll b/llvm/test/CodeGen/X86/bfloat.ll index 7bccd6ba088ac..0fb7e4a569f61 100644 --- a/llvm/test/CodeGen/X86/bfloat.ll +++ b/llvm/test/CodeGen/X86/bfloat.ll @@ -938,13 +938,13 @@ define <32 x bfloat> @pr63017_2() nounwind { ; SSE2-LABEL: pr63017_2: ; SSE2: # %bb.0: ; SSE2-NEXT: testb %al, %al -; SSE2-NEXT: jne .LBB16_1 -; SSE2-NEXT: # %bb.2: # %cond.load +; SSE2-NEXT: jne .LBB16_2 +; SSE2-NEXT: # %bb.1: # %cond.load ; SSE2-NEXT: movzwl (%rax), %eax ; SSE2-NEXT: shll $16, %eax ; SSE2-NEXT: movd %eax, %xmm0 ; SSE2-NEXT: jmp .LBB16_3 -; SSE2-NEXT: .LBB16_1: +; SSE2-NEXT: .LBB16_2: ; SSE2-NEXT: movd {{.*#+}} xmm0 = [-1.0E+0,0.0E+0,0.0E+0,0.0E+0] ; SSE2-NEXT: .LBB16_3: ; SSE2-NEXT: pushq %r14 diff --git a/llvm/test/CodeGen/X86/bitcast-and-setcc-256.ll b/llvm/test/CodeGen/X86/bitcast-and-setcc-256.ll index 234c7a0a500d3..a6cae81863029 100644 --- a/llvm/test/CodeGen/X86/bitcast-and-setcc-256.ll +++ b/llvm/test/CodeGen/X86/bitcast-and-setcc-256.ll @@ -517,11 +517,11 @@ define i8 @v8i32_or_select(<8 x i32> %a0, <8 x i32> %a1, <8 x i32> %a2, <8 x i32 ; SSE2-SSSE3-NEXT: pcmpeqd %xmm0, %xmm2 ; SSE2-SSSE3-NEXT: pcmpeqd %xmm1, %xmm3 ; SSE2-SSSE3-NEXT: testb $1, %dil -; SSE2-SSSE3-NEXT: jne .LBB7_1 -; SSE2-SSSE3-NEXT: # %bb.2: +; SSE2-SSSE3-NEXT: jne .LBB7_2 +; SSE2-SSSE3-NEXT: # %bb.1: ; SSE2-SSSE3-NEXT: pxor %xmm0, %xmm0 ; SSE2-SSSE3-NEXT: jmp .LBB7_3 -; SSE2-SSSE3-NEXT: .LBB7_1: +; SSE2-SSSE3-NEXT: .LBB7_2: ; SSE2-SSSE3-NEXT: pcmpeqd %xmm5, %xmm1 ; SSE2-SSSE3-NEXT: pcmpeqd %xmm4, %xmm0 ; SSE2-SSSE3-NEXT: packssdw %xmm1, %xmm0 @@ -539,11 +539,11 @@ define i8 @v8i32_or_select(<8 x i32> %a0, <8 x i32> %a1, <8 x i32> %a2, <8 x i32 ; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4 ; AVX1-NEXT: testb $1, %dil -; AVX1-NEXT: jne .LBB7_1 -; AVX1-NEXT: # %bb.2: +; AVX1-NEXT: jne .LBB7_2 +; AVX1-NEXT: # %bb.1: ; AVX1-NEXT: vxorps %xmm2, %xmm2, %xmm2 ; AVX1-NEXT: jmp .LBB7_3 -; AVX1-NEXT: .LBB7_1: +; AVX1-NEXT: .LBB7_2: ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm5 ; AVX1-NEXT: vpcmpeqd %xmm5, %xmm4, %xmm5 ; AVX1-NEXT: vpcmpeqd %xmm2, %xmm0, %xmm2 @@ -563,11 +563,11 @@ define i8 @v8i32_or_select(<8 x i32> %a0, <8 x i32> %a1, <8 x i32> %a2, <8 x i32 ; AVX2-LABEL: v8i32_or_select: ; AVX2: # %bb.0: ; AVX2-NEXT: testb $1, %dil -; AVX2-NEXT: jne .LBB7_1 -; AVX2-NEXT: # %bb.2: +; AVX2-NEXT: jne .LBB7_2 +; AVX2-NEXT: # %bb.1: ; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX2-NEXT: jmp .LBB7_3 -; AVX2-NEXT: .LBB7_1: +; AVX2-NEXT: .LBB7_2: ; AVX2-NEXT: vpcmpeqd %ymm2, %ymm0, %ymm2 ; AVX2-NEXT: .LBB7_3: ; AVX2-NEXT: vpcmpeqd %ymm1, %ymm0, %ymm0 @@ -584,11 +584,11 @@ define i8 @v8i32_or_select(<8 x i32> %a0, <8 x i32> %a1, <8 x i32> %a2, <8 x i32 ; AVX512F-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; AVX512F-NEXT: vpcmpgtd %ymm3, %ymm1, %k1 ; AVX512F-NEXT: testb $1, %dil -; AVX512F-NEXT: jne .LBB7_1 -; AVX512F-NEXT: # %bb.2: +; AVX512F-NEXT: jne .LBB7_2 +; AVX512F-NEXT: # %bb.1: ; AVX512F-NEXT: kxorw %k0, %k0, %k2 ; AVX512F-NEXT: jmp .LBB7_3 -; AVX512F-NEXT: .LBB7_1: +; AVX512F-NEXT: .LBB7_2: ; AVX512F-NEXT: vpcmpeqd %ymm2, %ymm0, %k2 ; AVX512F-NEXT: .LBB7_3: ; AVX512F-NEXT: korw %k0, %k1, %k0 @@ -604,11 +604,11 @@ define i8 @v8i32_or_select(<8 x i32> %a0, <8 x i32> %a1, <8 x i32> %a2, <8 x i32 ; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; AVX512BW-NEXT: vpcmpgtd %ymm3, %ymm1, %k1 ; AVX512BW-NEXT: testb $1, %dil -; AVX512BW-NEXT: jne .LBB7_1 -; AVX512BW-NEXT: # %bb.2: +; AVX512BW-NEXT: jne .LBB7_2 +; AVX512BW-NEXT: # %bb.1: ; AVX512BW-NEXT: kxorw %k0, %k0, %k2 ; AVX512BW-NEXT: jmp .LBB7_3 -; AVX512BW-NEXT: .LBB7_1: +; AVX512BW-NEXT: .LBB7_2: ; AVX512BW-NEXT: vpcmpeqd %ymm2, %ymm0, %k2 ; AVX512BW-NEXT: .LBB7_3: ; AVX512BW-NEXT: korw %k0, %k1, %k0 diff --git a/llvm/test/CodeGen/X86/bittest-big-integer.ll b/llvm/test/CodeGen/X86/bittest-big-integer.ll index 96ccc7b0f7527..18d84753a5ab1 100644 --- a/llvm/test/CodeGen/X86/bittest-big-integer.ll +++ b/llvm/test/CodeGen/X86/bittest-big-integer.ll @@ -1567,30 +1567,30 @@ define i32 @blsr_u512(ptr %word) nounwind { ; X86-NEXT: orl %ecx, %esi ; X86-NEXT: orl %eax, %esi ; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: je .LBB26_1 -; X86-NEXT: # %bb.2: # %cond.false +; X86-NEXT: je .LBB26_3 +; X86-NEXT: # %bb.1: # %cond.false ; X86-NEXT: testl %ebx, %ebx ; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: jne .LBB26_3 -; X86-NEXT: # %bb.4: # %cond.false +; X86-NEXT: jne .LBB26_4 +; X86-NEXT: # %bb.2: # %cond.false ; X86-NEXT: rep bsfl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload ; X86-NEXT: addl $32, %eax ; X86-NEXT: jmp .LBB26_5 -; X86-NEXT: .LBB26_1: -; X86-NEXT: movl $512, %ecx # imm = 0x200 -; X86-NEXT: jmp .LBB26_41 ; X86-NEXT: .LBB26_3: +; X86-NEXT: movl $512, %ecx # imm = 0x200 +; X86-NEXT: jmp .LBB26_36 +; X86-NEXT: .LBB26_4: ; X86-NEXT: rep bsfl %ebx, %eax ; X86-NEXT: .LBB26_5: # %cond.false ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; X86-NEXT: testl %ecx, %ecx -; X86-NEXT: jne .LBB26_6 -; X86-NEXT: # %bb.7: # %cond.false +; X86-NEXT: jne .LBB26_7 +; X86-NEXT: # %bb.6: # %cond.false ; X86-NEXT: rep bsfl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload ; X86-NEXT: addl $32, %ecx ; X86-NEXT: jmp .LBB26_8 -; X86-NEXT: .LBB26_6: +; X86-NEXT: .LBB26_7: ; X86-NEXT: rep bsfl %ecx, %ecx ; X86-NEXT: .LBB26_8: # %cond.false ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload @@ -1602,105 +1602,105 @@ define i32 @blsr_u512(ptr %word) nounwind { ; X86-NEXT: .LBB26_10: # %cond.false ; X86-NEXT: testl %esi, %esi ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload -; X86-NEXT: jne .LBB26_11 -; X86-NEXT: # %bb.12: # %cond.false +; X86-NEXT: jne .LBB26_13 +; X86-NEXT: # %bb.11: # %cond.false ; X86-NEXT: rep bsfl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload ; X86-NEXT: addl $32, %ecx ; X86-NEXT: testl %edx, %edx -; X86-NEXT: je .LBB26_15 -; X86-NEXT: .LBB26_14: +; X86-NEXT: je .LBB26_14 +; X86-NEXT: .LBB26_12: ; X86-NEXT: rep bsfl %edx, %edx ; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Folded Reload -; X86-NEXT: je .LBB26_17 -; X86-NEXT: jmp .LBB26_18 -; X86-NEXT: .LBB26_11: +; X86-NEXT: je .LBB26_15 +; X86-NEXT: jmp .LBB26_16 +; X86-NEXT: .LBB26_13: ; X86-NEXT: rep bsfl %esi, %ecx ; X86-NEXT: testl %edx, %edx -; X86-NEXT: jne .LBB26_14 -; X86-NEXT: .LBB26_15: # %cond.false +; X86-NEXT: jne .LBB26_12 +; X86-NEXT: .LBB26_14: # %cond.false ; X86-NEXT: rep bsfl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload ; X86-NEXT: addl $32, %edx ; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Folded Reload -; X86-NEXT: jne .LBB26_18 -; X86-NEXT: .LBB26_17: # %cond.false +; X86-NEXT: jne .LBB26_16 +; X86-NEXT: .LBB26_15: # %cond.false ; X86-NEXT: addl $64, %edx ; X86-NEXT: movl %edx, %ecx -; X86-NEXT: .LBB26_18: # %cond.false +; X86-NEXT: .LBB26_16: # %cond.false ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload ; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload ; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Folded Reload ; X86-NEXT: orl %edx, %esi -; X86-NEXT: jne .LBB26_20 -; X86-NEXT: # %bb.19: # %cond.false +; X86-NEXT: jne .LBB26_18 +; X86-NEXT: # %bb.17: # %cond.false ; X86-NEXT: subl $-128, %ecx ; X86-NEXT: movl %ecx, %eax -; X86-NEXT: .LBB26_20: # %cond.false +; X86-NEXT: .LBB26_18: # %cond.false ; X86-NEXT: addl $256, %eax # imm = 0x100 ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload ; X86-NEXT: testl %edx, %edx ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload -; X86-NEXT: jne .LBB26_21 -; X86-NEXT: # %bb.22: # %cond.false +; X86-NEXT: jne .LBB26_20 +; X86-NEXT: # %bb.19: # %cond.false ; X86-NEXT: rep bsfl %edi, %ebx ; X86-NEXT: addl $32, %ebx -; X86-NEXT: jmp .LBB26_23 -; X86-NEXT: .LBB26_21: +; X86-NEXT: jmp .LBB26_21 +; X86-NEXT: .LBB26_20: ; X86-NEXT: rep bsfl %edx, %ebx -; X86-NEXT: .LBB26_23: # %cond.false +; X86-NEXT: .LBB26_21: # %cond.false ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; X86-NEXT: testl %ecx, %ecx -; X86-NEXT: jne .LBB26_24 -; X86-NEXT: # %bb.25: # %cond.false +; X86-NEXT: jne .LBB26_23 +; X86-NEXT: # %bb.22: # %cond.false ; X86-NEXT: rep bsfl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload ; X86-NEXT: addl $32, %ecx ; X86-NEXT: orl %edi, %edx -; X86-NEXT: je .LBB26_27 -; X86-NEXT: jmp .LBB26_28 -; X86-NEXT: .LBB26_24: +; X86-NEXT: je .LBB26_24 +; X86-NEXT: jmp .LBB26_25 +; X86-NEXT: .LBB26_23: ; X86-NEXT: rep bsfl %ecx, %ecx ; X86-NEXT: orl %edi, %edx -; X86-NEXT: jne .LBB26_28 -; X86-NEXT: .LBB26_27: # %cond.false +; X86-NEXT: jne .LBB26_25 +; X86-NEXT: .LBB26_24: # %cond.false ; X86-NEXT: addl $64, %ecx ; X86-NEXT: movl %ecx, %ebx -; X86-NEXT: .LBB26_28: # %cond.false +; X86-NEXT: .LBB26_25: # %cond.false ; X86-NEXT: testl %esi, %esi ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload -; X86-NEXT: jne .LBB26_29 -; X86-NEXT: # %bb.30: # %cond.false +; X86-NEXT: jne .LBB26_28 +; X86-NEXT: # %bb.26: # %cond.false ; X86-NEXT: rep bsfl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload ; X86-NEXT: addl $32, %ecx ; X86-NEXT: testl %edx, %edx -; X86-NEXT: je .LBB26_33 -; X86-NEXT: .LBB26_32: +; X86-NEXT: je .LBB26_29 +; X86-NEXT: .LBB26_27: ; X86-NEXT: rep bsfl %edx, %edx ; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Folded Reload -; X86-NEXT: je .LBB26_35 -; X86-NEXT: jmp .LBB26_36 -; X86-NEXT: .LBB26_29: +; X86-NEXT: je .LBB26_30 +; X86-NEXT: jmp .LBB26_31 +; X86-NEXT: .LBB26_28: ; X86-NEXT: rep bsfl %esi, %ecx ; X86-NEXT: testl %edx, %edx -; X86-NEXT: jne .LBB26_32 -; X86-NEXT: .LBB26_33: # %cond.false +; X86-NEXT: jne .LBB26_27 +; X86-NEXT: .LBB26_29: # %cond.false ; X86-NEXT: rep bsfl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload ; X86-NEXT: addl $32, %edx ; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Folded Reload -; X86-NEXT: jne .LBB26_36 -; X86-NEXT: .LBB26_35: # %cond.false +; X86-NEXT: jne .LBB26_31 +; X86-NEXT: .LBB26_30: # %cond.false ; X86-NEXT: addl $64, %edx ; X86-NEXT: movl %edx, %ecx -; X86-NEXT: .LBB26_36: # %cond.false +; X86-NEXT: .LBB26_31: # %cond.false ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload ; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload ; X86-NEXT: movl %edi, %esi ; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Folded Reload ; X86-NEXT: orl %edx, %esi -; X86-NEXT: jne .LBB26_38 -; X86-NEXT: # %bb.37: # %cond.false +; X86-NEXT: jne .LBB26_33 +; X86-NEXT: # %bb.32: # %cond.false ; X86-NEXT: subl $-128, %ecx ; X86-NEXT: movl %ecx, %ebx -; X86-NEXT: .LBB26_38: # %cond.false +; X86-NEXT: .LBB26_33: # %cond.false ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload @@ -1713,12 +1713,12 @@ define i32 @blsr_u512(ptr %word) nounwind { ; X86-NEXT: orl %ecx, %esi ; X86-NEXT: orl %edx, %esi ; X86-NEXT: movl %ebx, %ecx -; X86-NEXT: jne .LBB26_40 -; X86-NEXT: # %bb.39: # %cond.false +; X86-NEXT: jne .LBB26_35 +; X86-NEXT: # %bb.34: # %cond.false ; X86-NEXT: movl %eax, %ecx -; X86-NEXT: .LBB26_40: # %cond.false +; X86-NEXT: .LBB26_35: # %cond.false ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload -; X86-NEXT: .LBB26_41: # %cond.end +; X86-NEXT: .LBB26_36: # %cond.end ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NEXT: movl %ecx, %esi ; X86-NEXT: shrl $3, %esi diff --git a/llvm/test/CodeGen/X86/block-placement.ll b/llvm/test/CodeGen/X86/block-placement.ll index 1369131413053..04b0bb649450d 100644 --- a/llvm/test/CodeGen/X86/block-placement.ll +++ b/llvm/test/CodeGen/X86/block-placement.ll @@ -475,12 +475,12 @@ define void @fpcmp_unanalyzable_branch(i1 %cond, double %a0, i1 %arg) { ; CHECK-LABEL: fpcmp_unanalyzable_branch: ; CHECK: # %bb.0: # %entry ; CHECK: # %bb.1: # %entry.if.then_crit_edge -; CHECK: .LBB10_5: # %if.then -; CHECK: .LBB10_6: # %if.end -; CHECK: # %bb.3: # %exit -; CHECK: jne .LBB10_4 -; CHECK-NEXT: jnp .LBB10_6 -; CHECK: jmp .LBB10_5 +; CHECK: .LBB10_2: # %if.then +; CHECK: .LBB10_3: # %if.end +; CHECK: # %bb.5: # %exit +; CHECK: jne .LBB10_6 +; CHECK-NEXT: jnp .LBB10_3 +; CHECK: jmp .LBB10_2 entry: ; Note that this branch must be strongly biased toward diff --git a/llvm/test/CodeGen/X86/bmi-select-distrib.ll b/llvm/test/CodeGen/X86/bmi-select-distrib.ll index e5696ded4fbf1..1542a7eedc570 100644 --- a/llvm/test/CodeGen/X86/bmi-select-distrib.ll +++ b/llvm/test/CodeGen/X86/bmi-select-distrib.ll @@ -166,12 +166,12 @@ define <4 x i32> @and_select_neg_v4xi32(i1 %a0, <4 x i32> %a1) nounwind { ; X86-LABEL: and_select_neg_v4xi32: ; X86: # %bb.0: ; X86-NEXT: testb $1, {{[0-9]+}}(%esp) -; X86-NEXT: jne .LBB6_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: jne .LBB6_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: pcmpeqd %xmm1, %xmm1 ; X86-NEXT: pand %xmm1, %xmm0 ; X86-NEXT: retl -; X86-NEXT: .LBB6_1: +; X86-NEXT: .LBB6_2: ; X86-NEXT: pxor %xmm1, %xmm1 ; X86-NEXT: psubd %xmm0, %xmm1 ; X86-NEXT: pand %xmm1, %xmm0 @@ -180,12 +180,12 @@ define <4 x i32> @and_select_neg_v4xi32(i1 %a0, <4 x i32> %a1) nounwind { ; X64-LABEL: and_select_neg_v4xi32: ; X64: # %bb.0: ; X64-NEXT: testb $1, %dil -; X64-NEXT: jne .LBB6_1 -; X64-NEXT: # %bb.2: +; X64-NEXT: jne .LBB6_2 +; X64-NEXT: # %bb.1: ; X64-NEXT: pcmpeqd %xmm1, %xmm1 ; X64-NEXT: pand %xmm1, %xmm0 ; X64-NEXT: retq -; X64-NEXT: .LBB6_1: +; X64-NEXT: .LBB6_2: ; X64-NEXT: pxor %xmm1, %xmm1 ; X64-NEXT: psubd %xmm0, %xmm1 ; X64-NEXT: pand %xmm1, %xmm0 @@ -749,12 +749,12 @@ define <4 x i32> @xor_select_sub_1_v4xi32(i1 %a0, <4 x i32> %a1) nounwind { ; X86-LABEL: xor_select_sub_1_v4xi32: ; X86: # %bb.0: ; X86-NEXT: testb $1, {{[0-9]+}}(%esp) -; X86-NEXT: jne .LBB28_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: jne .LBB28_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: xorps %xmm1, %xmm1 ; X86-NEXT: xorps %xmm1, %xmm0 ; X86-NEXT: retl -; X86-NEXT: .LBB28_1: +; X86-NEXT: .LBB28_2: ; X86-NEXT: pcmpeqd %xmm1, %xmm1 ; X86-NEXT: paddd %xmm0, %xmm1 ; X86-NEXT: pxor %xmm1, %xmm0 @@ -763,12 +763,12 @@ define <4 x i32> @xor_select_sub_1_v4xi32(i1 %a0, <4 x i32> %a1) nounwind { ; X64-LABEL: xor_select_sub_1_v4xi32: ; X64: # %bb.0: ; X64-NEXT: testb $1, %dil -; X64-NEXT: jne .LBB28_1 -; X64-NEXT: # %bb.2: +; X64-NEXT: jne .LBB28_2 +; X64-NEXT: # %bb.1: ; X64-NEXT: xorps %xmm1, %xmm1 ; X64-NEXT: xorps %xmm1, %xmm0 ; X64-NEXT: retq -; X64-NEXT: .LBB28_1: +; X64-NEXT: .LBB28_2: ; X64-NEXT: pcmpeqd %xmm1, %xmm1 ; X64-NEXT: paddd %xmm0, %xmm1 ; X64-NEXT: pxor %xmm1, %xmm0 diff --git a/llvm/test/CodeGen/X86/bmi.ll b/llvm/test/CodeGen/X86/bmi.ll index 4041934d404e2..262c62106950d 100644 --- a/llvm/test/CodeGen/X86/bmi.ll +++ b/llvm/test/CodeGen/X86/bmi.ll @@ -1907,12 +1907,12 @@ define void @pr42118_i64(i64 %x) { ; X86-NEXT: andl %eax, %edx ; X86-NEXT: andl %ecx, %esi ; X86-NEXT: orl %edx, %esi -; X86-NEXT: jne .LBB58_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: jne .LBB58_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: popl %esi ; X86-NEXT: .cfi_def_cfa_offset 4 ; X86-NEXT: jmp bar # TAILCALL -; X86-NEXT: .LBB58_1: +; X86-NEXT: .LBB58_2: ; X86-NEXT: .cfi_def_cfa_offset 8 ; X86-NEXT: popl %esi ; X86-NEXT: .cfi_def_cfa_offset 4 @@ -1950,11 +1950,11 @@ define i32 @blsi_cflag_32(i32 %x, i32 %y) nounwind { ; X86: # %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: testl %eax, %eax -; X86-NEXT: jne .LBB59_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: jne .LBB59_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB59_1: +; X86-NEXT: .LBB59_2: ; X86-NEXT: blsil %eax, %eax ; X86-NEXT: retl ; @@ -1990,12 +1990,12 @@ define i64 @blsi_cflag_64(i64 %x, i64 %y) nounwind { ; X86-NEXT: sbbl %esi, %edx ; X86-NEXT: movl %ecx, %edi ; X86-NEXT: orl %esi, %edi -; X86-NEXT: jne .LBB60_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: jne .LBB60_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: jmp .LBB60_3 -; X86-NEXT: .LBB60_1: +; X86-NEXT: .LBB60_2: ; X86-NEXT: andl %esi, %edx ; X86-NEXT: andl %ecx, %eax ; X86-NEXT: .LBB60_3: diff --git a/llvm/test/CodeGen/X86/branch-hint.ll b/llvm/test/CodeGen/X86/branch-hint.ll index 591fb324e1b7b..61c62942d52bf 100644 --- a/llvm/test/CodeGen/X86/branch-hint.ll +++ b/llvm/test/CodeGen/X86/branch-hint.ll @@ -43,10 +43,10 @@ define void @p61(i32 %x, ptr %p) { ; CHECK-LABEL: p61: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: testl %edi, %edi -; CHECK-NEXT: jne .LBB1_1 -; CHECK-NEXT: # %bb.2: # %if.end +; CHECK-NEXT: jne .LBB1_2 +; CHECK-NEXT: # %bb.1: # %if.end ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB1_1: # %if.then +; CHECK-NEXT: .LBB1_2: # %if.then ; CHECK-NEXT: movl %edi, (%rsi) ; CHECK-NEXT: retq ; @@ -72,4 +72,4 @@ if.end: } !0 = !{!"branch_weights", i32 51, i32 49} -!1 = !{!"branch_weights", i32 61, i32 39} \ No newline at end of file +!1 = !{!"branch_weights", i32 61, i32 39} diff --git a/llvm/test/CodeGen/X86/break-false-dep.ll b/llvm/test/CodeGen/X86/break-false-dep.ll index 6943622fac7f2..8547c2dceb498 100644 --- a/llvm/test/CodeGen/X86/break-false-dep.ll +++ b/llvm/test/CodeGen/X86/break-false-dep.ll @@ -133,13 +133,13 @@ define dso_local float @loopdep1(i32 %m) nounwind uwtable readnone ssp { ; SSE-LINUX-LABEL: loopdep1: ; SSE-LINUX: # %bb.0: # %entry ; SSE-LINUX-NEXT: testl %edi, %edi -; SSE-LINUX-NEXT: je .LBB6_1 -; SSE-LINUX-NEXT: # %bb.2: # %for.body.preheader +; SSE-LINUX-NEXT: je .LBB6_4 +; SSE-LINUX-NEXT: # %bb.1: # %for.body.preheader ; SSE-LINUX-NEXT: movl $1, %eax ; SSE-LINUX-NEXT: xorps %xmm0, %xmm0 ; SSE-LINUX-NEXT: xorps %xmm1, %xmm1 ; SSE-LINUX-NEXT: .p2align 4 -; SSE-LINUX-NEXT: .LBB6_3: # %for.body +; SSE-LINUX-NEXT: .LBB6_2: # %for.body ; SSE-LINUX-NEXT: # =>This Inner Loop Header: Depth=1 ; SSE-LINUX-NEXT: xorps %xmm2, %xmm2 ; SSE-LINUX-NEXT: cvtsi2ss %eax, %xmm2 @@ -149,11 +149,11 @@ define dso_local float @loopdep1(i32 %m) nounwind uwtable readnone ssp { ; SSE-LINUX-NEXT: addss %xmm3, %xmm1 ; SSE-LINUX-NEXT: incl %eax ; SSE-LINUX-NEXT: decl %edi -; SSE-LINUX-NEXT: jne .LBB6_3 -; SSE-LINUX-NEXT: # %bb.4: # %for.end +; SSE-LINUX-NEXT: jne .LBB6_2 +; SSE-LINUX-NEXT: # %bb.3: # %for.end ; SSE-LINUX-NEXT: subss %xmm1, %xmm0 ; SSE-LINUX-NEXT: retq -; SSE-LINUX-NEXT: .LBB6_1: +; SSE-LINUX-NEXT: .LBB6_4: ; SSE-LINUX-NEXT: xorps %xmm0, %xmm0 ; SSE-LINUX-NEXT: xorps %xmm1, %xmm1 ; SSE-LINUX-NEXT: subss %xmm1, %xmm0 @@ -162,13 +162,13 @@ define dso_local float @loopdep1(i32 %m) nounwind uwtable readnone ssp { ; SSE-WIN-LABEL: loopdep1: ; SSE-WIN: # %bb.0: # %entry ; SSE-WIN-NEXT: testl %ecx, %ecx -; SSE-WIN-NEXT: je .LBB6_1 -; SSE-WIN-NEXT: # %bb.2: # %for.body.preheader +; SSE-WIN-NEXT: je .LBB6_4 +; SSE-WIN-NEXT: # %bb.1: # %for.body.preheader ; SSE-WIN-NEXT: movl $1, %eax ; SSE-WIN-NEXT: xorps %xmm0, %xmm0 ; SSE-WIN-NEXT: xorps %xmm1, %xmm1 ; SSE-WIN-NEXT: .p2align 4 -; SSE-WIN-NEXT: .LBB6_3: # %for.body +; SSE-WIN-NEXT: .LBB6_2: # %for.body ; SSE-WIN-NEXT: # =>This Inner Loop Header: Depth=1 ; SSE-WIN-NEXT: xorps %xmm2, %xmm2 ; SSE-WIN-NEXT: cvtsi2ss %eax, %xmm2 @@ -178,11 +178,11 @@ define dso_local float @loopdep1(i32 %m) nounwind uwtable readnone ssp { ; SSE-WIN-NEXT: addss %xmm3, %xmm1 ; SSE-WIN-NEXT: incl %eax ; SSE-WIN-NEXT: decl %ecx -; SSE-WIN-NEXT: jne .LBB6_3 -; SSE-WIN-NEXT: # %bb.4: # %for.end +; SSE-WIN-NEXT: jne .LBB6_2 +; SSE-WIN-NEXT: # %bb.3: # %for.end ; SSE-WIN-NEXT: subss %xmm1, %xmm0 ; SSE-WIN-NEXT: retq -; SSE-WIN-NEXT: .LBB6_1: +; SSE-WIN-NEXT: .LBB6_4: ; SSE-WIN-NEXT: xorps %xmm0, %xmm0 ; SSE-WIN-NEXT: xorps %xmm1, %xmm1 ; SSE-WIN-NEXT: subss %xmm1, %xmm0 @@ -191,13 +191,13 @@ define dso_local float @loopdep1(i32 %m) nounwind uwtable readnone ssp { ; AVX1-LABEL: loopdep1: ; AVX1: # %bb.0: # %entry ; AVX1-NEXT: testl %ecx, %ecx -; AVX1-NEXT: je .LBB6_1 -; AVX1-NEXT: # %bb.2: # %for.body.preheader +; AVX1-NEXT: je .LBB6_4 +; AVX1-NEXT: # %bb.1: # %for.body.preheader ; AVX1-NEXT: movl $1, %eax ; AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1 ; AVX1-NEXT: .p2align 4 -; AVX1-NEXT: .LBB6_3: # %for.body +; AVX1-NEXT: .LBB6_2: # %for.body ; AVX1-NEXT: # =>This Inner Loop Header: Depth=1 ; AVX1-NEXT: vcvtsi2ss %eax, %xmm5, %xmm2 ; AVX1-NEXT: vcvtsi2ss %ecx, %xmm5, %xmm3 @@ -205,11 +205,11 @@ define dso_local float @loopdep1(i32 %m) nounwind uwtable readnone ssp { ; AVX1-NEXT: vaddss %xmm3, %xmm1, %xmm1 ; AVX1-NEXT: incl %eax ; AVX1-NEXT: decl %ecx -; AVX1-NEXT: jne .LBB6_3 -; AVX1-NEXT: # %bb.4: # %for.end +; AVX1-NEXT: jne .LBB6_2 +; AVX1-NEXT: # %bb.3: # %for.end ; AVX1-NEXT: vsubss %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB6_1: +; AVX1-NEXT: .LBB6_4: ; AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1 ; AVX1-NEXT: vsubss %xmm1, %xmm0, %xmm0 @@ -218,13 +218,13 @@ define dso_local float @loopdep1(i32 %m) nounwind uwtable readnone ssp { ; AVX512VL-LABEL: loopdep1: ; AVX512VL: # %bb.0: # %entry ; AVX512VL-NEXT: testl %ecx, %ecx -; AVX512VL-NEXT: je .LBB6_1 -; AVX512VL-NEXT: # %bb.2: # %for.body.preheader +; AVX512VL-NEXT: je .LBB6_4 +; AVX512VL-NEXT: # %bb.1: # %for.body.preheader ; AVX512VL-NEXT: movl $1, %eax ; AVX512VL-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX512VL-NEXT: vxorps %xmm1, %xmm1, %xmm1 ; AVX512VL-NEXT: .p2align 4 -; AVX512VL-NEXT: .LBB6_3: # %for.body +; AVX512VL-NEXT: .LBB6_2: # %for.body ; AVX512VL-NEXT: # =>This Inner Loop Header: Depth=1 ; AVX512VL-NEXT: vcvtsi2ss %eax, %xmm5, %xmm2 ; AVX512VL-NEXT: vaddss %xmm2, %xmm0, %xmm0 @@ -232,11 +232,11 @@ define dso_local float @loopdep1(i32 %m) nounwind uwtable readnone ssp { ; AVX512VL-NEXT: vaddss %xmm2, %xmm1, %xmm1 ; AVX512VL-NEXT: incl %eax ; AVX512VL-NEXT: decl %ecx -; AVX512VL-NEXT: jne .LBB6_3 -; AVX512VL-NEXT: # %bb.4: # %for.end +; AVX512VL-NEXT: jne .LBB6_2 +; AVX512VL-NEXT: # %bb.3: # %for.end ; AVX512VL-NEXT: vsubss %xmm1, %xmm0, %xmm0 ; AVX512VL-NEXT: retq -; AVX512VL-NEXT: .LBB6_1: +; AVX512VL-NEXT: .LBB6_4: ; AVX512VL-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX512VL-NEXT: vxorps %xmm1, %xmm1, %xmm1 ; AVX512VL-NEXT: vsubss %xmm1, %xmm0, %xmm0 diff --git a/llvm/test/CodeGen/X86/bsf.ll b/llvm/test/CodeGen/X86/bsf.ll index f780f0172647f..1c5bd0108c25d 100644 --- a/llvm/test/CodeGen/X86/bsf.ll +++ b/llvm/test/CodeGen/X86/bsf.ll @@ -7,13 +7,13 @@ define i8 @cmov_bsf8(i8 %x, i8 %y) nounwind { ; X86: # %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: testb %al, %al -; X86-NEXT: je .LBB0_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: je .LBB0_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: orl $256, %eax # imm = 0x100 ; X86-NEXT: rep bsfl %eax, %eax ; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: retl -; X86-NEXT: .LBB0_1: +; X86-NEXT: .LBB0_2: ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: retl @@ -38,12 +38,12 @@ define i8 @cmov_bsf8_undef(i8 %x, i8 %y) nounwind { ; X86: # %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: testb %al, %al -; X86-NEXT: jne .LBB1_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: jne .LBB1_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: retl -; X86-NEXT: .LBB1_1: +; X86-NEXT: .LBB1_2: ; X86-NEXT: rep bsfl %eax, %eax ; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: retl @@ -66,12 +66,12 @@ define i16 @cmov_bsf16(i16 %x, i16 %y) nounwind { ; X86: # %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: testw %ax, %ax -; X86-NEXT: jne .LBB2_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: jne .LBB2_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-NEXT: # kill: def $ax killed $ax killed $eax ; X86-NEXT: retl -; X86-NEXT: .LBB2_1: +; X86-NEXT: .LBB2_2: ; X86-NEXT: orl $65536, %eax # imm = 0x10000 ; X86-NEXT: rep bsfl %eax, %eax ; X86-NEXT: # kill: def $ax killed $ax killed $eax @@ -97,12 +97,12 @@ define i16 @cmov_bsf16_undef(i16 %x, i16 %y) nounwind { ; X86: # %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: testw %ax, %ax -; X86-NEXT: je .LBB3_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: je .LBB3_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: rep bsfl %eax, %eax ; X86-NEXT: # kill: def $ax killed $ax killed $eax ; X86-NEXT: retl -; X86-NEXT: .LBB3_1: +; X86-NEXT: .LBB3_2: ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-NEXT: # kill: def $ax killed $ax killed $eax ; X86-NEXT: retl @@ -125,20 +125,20 @@ define i32 @cmov_bsf32(i32 %x, i32 %y) nounwind { ; X86: # %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: testl %ecx, %ecx -; X86-NEXT: je .LBB4_1 -; X86-NEXT: # %bb.2: # %cond.false +; X86-NEXT: je .LBB4_4 +; X86-NEXT: # %bb.1: # %cond.false ; X86-NEXT: rep bsfl %ecx, %eax ; X86-NEXT: testl %ecx, %ecx -; X86-NEXT: jne .LBB4_5 -; X86-NEXT: .LBB4_4: +; X86-NEXT: jne .LBB4_3 +; X86-NEXT: .LBB4_2: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax -; X86-NEXT: .LBB4_5: # %cond.end +; X86-NEXT: .LBB4_3: # %cond.end ; X86-NEXT: retl -; X86-NEXT: .LBB4_1: +; X86-NEXT: .LBB4_4: ; X86-NEXT: movl $32, %eax ; X86-NEXT: testl %ecx, %ecx -; X86-NEXT: je .LBB4_4 -; X86-NEXT: jmp .LBB4_5 +; X86-NEXT: je .LBB4_2 +; X86-NEXT: jmp .LBB4_3 ; ; X64-LABEL: cmov_bsf32: ; X64: # %bb.0: @@ -157,11 +157,11 @@ define i32 @cmov_bsf32_undef(i32 %x, i32 %y) nounwind { ; X86: # %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: testl %eax, %eax -; X86-NEXT: jne .LBB5_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: jne .LBB5_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB5_1: +; X86-NEXT: .LBB5_2: ; X86-NEXT: rep bsfl %eax, %eax ; X86-NEXT: retl ; @@ -184,18 +184,18 @@ define i64 @cmov_bsf64(i64 %x, i64 %y) nounwind { ; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-NEXT: movl %esi, %eax ; X86-NEXT: orl %ecx, %eax -; X86-NEXT: je .LBB6_1 -; X86-NEXT: # %bb.2: # %cond.false +; X86-NEXT: je .LBB6_3 +; X86-NEXT: # %bb.1: # %cond.false ; X86-NEXT: testl %esi, %esi -; X86-NEXT: jne .LBB6_3 -; X86-NEXT: # %bb.4: # %cond.false +; X86-NEXT: jne .LBB6_4 +; X86-NEXT: # %bb.2: # %cond.false ; X86-NEXT: rep bsfl %ecx, %eax ; X86-NEXT: addl $32, %eax ; X86-NEXT: jmp .LBB6_5 -; X86-NEXT: .LBB6_1: +; X86-NEXT: .LBB6_3: ; X86-NEXT: movl $64, %eax ; X86-NEXT: jmp .LBB6_5 -; X86-NEXT: .LBB6_3: +; X86-NEXT: .LBB6_4: ; X86-NEXT: rep bsfl %esi, %eax ; X86-NEXT: .LBB6_5: # %cond.end ; X86-NEXT: xorl %edx, %edx @@ -227,20 +227,20 @@ define i64 @cmov_bsf64_undef(i64 %x, i64 %y) nounwind { ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl %ecx, %edx ; X86-NEXT: orl %eax, %edx -; X86-NEXT: je .LBB7_5 +; X86-NEXT: je .LBB7_3 ; X86-NEXT: # %bb.1: # %select.false.sink ; X86-NEXT: testl %ecx, %ecx -; X86-NEXT: jne .LBB7_2 -; X86-NEXT: # %bb.3: # %select.false.sink +; X86-NEXT: jne .LBB7_4 +; X86-NEXT: # %bb.2: # %select.false.sink ; X86-NEXT: rep bsfl %eax, %eax ; X86-NEXT: addl $32, %eax ; X86-NEXT: xorl %edx, %edx ; X86-NEXT: retl -; X86-NEXT: .LBB7_5: # %select.end +; X86-NEXT: .LBB7_3: # %select.end ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB7_2: +; X86-NEXT: .LBB7_4: ; X86-NEXT: rep bsfl %ecx, %eax ; X86-NEXT: xorl %edx, %edx ; X86-NEXT: retl @@ -275,53 +275,53 @@ define i128 @cmov_bsf128(i128 %x, i128 %y) nounwind { ; X86-NEXT: orl %ecx, %esi ; X86-NEXT: orl %eax, %esi ; X86-NEXT: movl 8(%ebp), %eax -; X86-NEXT: je .LBB8_1 -; X86-NEXT: # %bb.2: # %cond.false +; X86-NEXT: je .LBB8_4 +; X86-NEXT: # %bb.1: # %cond.false ; X86-NEXT: testl %edx, %edx -; X86-NEXT: jne .LBB8_3 -; X86-NEXT: # %bb.4: # %cond.false +; X86-NEXT: jne .LBB8_5 +; X86-NEXT: # %bb.2: # %cond.false ; X86-NEXT: rep bsfl %edi, %ebx ; X86-NEXT: addl $32, %ebx ; X86-NEXT: testl %ecx, %ecx -; X86-NEXT: je .LBB8_7 -; X86-NEXT: .LBB8_6: +; X86-NEXT: je .LBB8_6 +; X86-NEXT: .LBB8_3: ; X86-NEXT: rep bsfl %ecx, %esi -; X86-NEXT: jmp .LBB8_8 -; X86-NEXT: .LBB8_1: +; X86-NEXT: jmp .LBB8_7 +; X86-NEXT: .LBB8_4: ; X86-NEXT: movl $128, %ebx -; X86-NEXT: jmp .LBB8_11 -; X86-NEXT: .LBB8_3: +; X86-NEXT: jmp .LBB8_10 +; X86-NEXT: .LBB8_5: ; X86-NEXT: rep bsfl %edx, %ebx ; X86-NEXT: testl %ecx, %ecx -; X86-NEXT: jne .LBB8_6 -; X86-NEXT: .LBB8_7: # %cond.false +; X86-NEXT: jne .LBB8_3 +; X86-NEXT: .LBB8_6: # %cond.false ; X86-NEXT: rep bsfl 36(%ebp), %esi ; X86-NEXT: addl $32, %esi -; X86-NEXT: .LBB8_8: # %cond.false +; X86-NEXT: .LBB8_7: # %cond.false ; X86-NEXT: movl %edx, %ecx ; X86-NEXT: orl %edi, %ecx -; X86-NEXT: jne .LBB8_10 -; X86-NEXT: # %bb.9: # %cond.false +; X86-NEXT: jne .LBB8_9 +; X86-NEXT: # %bb.8: # %cond.false ; X86-NEXT: addl $64, %esi ; X86-NEXT: movl %esi, %ebx -; X86-NEXT: .LBB8_10: # %cond.false +; X86-NEXT: .LBB8_9: # %cond.false ; X86-NEXT: movl 32(%ebp), %ecx -; X86-NEXT: .LBB8_11: # %cond.end +; X86-NEXT: .LBB8_10: # %cond.end ; X86-NEXT: orl %ecx, %edx ; X86-NEXT: orl 36(%ebp), %edi ; X86-NEXT: orl %edx, %edi ; X86-NEXT: je .LBB8_12 -; X86-NEXT: # %bb.13: # %cond.end +; X86-NEXT: # %bb.11: # %cond.end ; X86-NEXT: xorl %ecx, %ecx ; X86-NEXT: xorl %edx, %edx ; X86-NEXT: xorl %esi, %esi -; X86-NEXT: jmp .LBB8_14 +; X86-NEXT: jmp .LBB8_13 ; X86-NEXT: .LBB8_12: ; X86-NEXT: movl 52(%ebp), %esi ; X86-NEXT: movl 48(%ebp), %edx ; X86-NEXT: movl 44(%ebp), %ecx ; X86-NEXT: movl 40(%ebp), %ebx -; X86-NEXT: .LBB8_14: # %cond.end +; X86-NEXT: .LBB8_13: # %cond.end ; X86-NEXT: movl %esi, 12(%eax) ; X86-NEXT: movl %edx, 8(%eax) ; X86-NEXT: movl %ecx, 4(%eax) @@ -377,21 +377,21 @@ define i128 @cmov_bsf128_undef(i128 %x, i128 %y) nounwind { ; X86-NEXT: orl %edi, %ebx ; X86-NEXT: orl %eax, %ebx ; X86-NEXT: movl 8(%ebp), %eax -; X86-NEXT: je .LBB9_11 +; X86-NEXT: je .LBB9_4 ; X86-NEXT: # %bb.1: # %select.true.sink ; X86-NEXT: testl %edx, %edx -; X86-NEXT: jne .LBB9_2 -; X86-NEXT: # %bb.3: # %select.true.sink +; X86-NEXT: jne .LBB9_5 +; X86-NEXT: # %bb.2: # %select.true.sink ; X86-NEXT: rep bsfl %ecx, %ebx ; X86-NEXT: addl $32, %ebx ; X86-NEXT: testl %edi, %edi ; X86-NEXT: je .LBB9_6 -; X86-NEXT: .LBB9_5: +; X86-NEXT: .LBB9_3: ; X86-NEXT: rep bsfl %edi, %esi ; X86-NEXT: orl %ecx, %edx -; X86-NEXT: je .LBB9_8 -; X86-NEXT: jmp .LBB9_9 -; X86-NEXT: .LBB9_11: # %select.end +; X86-NEXT: je .LBB9_7 +; X86-NEXT: jmp .LBB9_8 +; X86-NEXT: .LBB9_4: # %select.end ; X86-NEXT: movl 52(%ebp), %ecx ; X86-NEXT: movl 48(%ebp), %edx ; X86-NEXT: movl 44(%ebp), %esi @@ -400,25 +400,25 @@ define i128 @cmov_bsf128_undef(i128 %x, i128 %y) nounwind { ; X86-NEXT: movl %esi, 4(%eax) ; X86-NEXT: movl %edx, 8(%eax) ; X86-NEXT: movl %ecx, 12(%eax) -; X86-NEXT: jmp .LBB9_10 -; X86-NEXT: .LBB9_2: +; X86-NEXT: jmp .LBB9_9 +; X86-NEXT: .LBB9_5: ; X86-NEXT: rep bsfl %edx, %ebx ; X86-NEXT: testl %edi, %edi -; X86-NEXT: jne .LBB9_5 +; X86-NEXT: jne .LBB9_3 ; X86-NEXT: .LBB9_6: # %select.true.sink ; X86-NEXT: rep bsfl %esi, %esi ; X86-NEXT: addl $32, %esi ; X86-NEXT: orl %ecx, %edx -; X86-NEXT: jne .LBB9_9 -; X86-NEXT: .LBB9_8: # %select.true.sink +; X86-NEXT: jne .LBB9_8 +; X86-NEXT: .LBB9_7: # %select.true.sink ; X86-NEXT: addl $64, %esi ; X86-NEXT: movl %esi, %ebx -; X86-NEXT: .LBB9_9: # %select.true.sink +; X86-NEXT: .LBB9_8: # %select.true.sink ; X86-NEXT: movl %ebx, (%eax) ; X86-NEXT: movl $0, 12(%eax) ; X86-NEXT: movl $0, 8(%eax) ; X86-NEXT: movl $0, 4(%eax) -; X86-NEXT: .LBB9_10: # %select.true.sink +; X86-NEXT: .LBB9_9: # %select.true.sink ; X86-NEXT: leal -12(%ebp), %esp ; X86-NEXT: popl %esi ; X86-NEXT: popl %edi diff --git a/llvm/test/CodeGen/X86/bsr.ll b/llvm/test/CodeGen/X86/bsr.ll index affacc5ee6487..2a78b9f59b08c 100644 --- a/llvm/test/CodeGen/X86/bsr.ll +++ b/llvm/test/CodeGen/X86/bsr.ll @@ -7,21 +7,21 @@ define i8 @cmov_bsr8(i8 %x, i8 %y) nounwind { ; X86: # %bb.0: ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: testb %cl, %cl -; X86-NEXT: je .LBB0_1 -; X86-NEXT: # %bb.2: # %cond.false +; X86-NEXT: je .LBB0_3 +; X86-NEXT: # %bb.1: # %cond.false ; X86-NEXT: movzbl %cl, %eax ; X86-NEXT: bsrl %eax, %eax ; X86-NEXT: xorl $7, %eax ; X86-NEXT: testb %cl, %cl ; X86-NEXT: je .LBB0_4 -; X86-NEXT: .LBB0_5: # %cond.end +; X86-NEXT: .LBB0_2: # %cond.end ; X86-NEXT: xorb $7, %al ; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: retl -; X86-NEXT: .LBB0_1: +; X86-NEXT: .LBB0_3: ; X86-NEXT: movb $8, %al ; X86-NEXT: testb %cl, %cl -; X86-NEXT: jne .LBB0_5 +; X86-NEXT: jne .LBB0_2 ; X86-NEXT: .LBB0_4: ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X86-NEXT: # kill: def $al killed $al killed $eax @@ -48,12 +48,12 @@ define i8 @cmov_bsr8_undef(i8 %x, i8 %y) nounwind { ; X86: # %bb.0: ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X86-NEXT: testl %eax, %eax -; X86-NEXT: jne .LBB1_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: jne .LBB1_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: retl -; X86-NEXT: .LBB1_1: +; X86-NEXT: .LBB1_2: ; X86-NEXT: bsrl %eax, %eax ; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: retl @@ -78,20 +78,20 @@ define i16 @cmov_bsr16(i16 %x, i16 %y) nounwind { ; X86: # %bb.0: ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-NEXT: testw %ax, %ax -; X86-NEXT: je .LBB2_1 -; X86-NEXT: # %bb.2: # %cond.false +; X86-NEXT: je .LBB2_3 +; X86-NEXT: # %bb.1: # %cond.false ; X86-NEXT: bsrw %ax, %cx ; X86-NEXT: xorl $15, %ecx ; X86-NEXT: testw %ax, %ax ; X86-NEXT: jne .LBB2_4 -; X86-NEXT: .LBB2_5: # %cond.end +; X86-NEXT: .LBB2_2: # %cond.end ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-NEXT: # kill: def $ax killed $ax killed $eax ; X86-NEXT: retl -; X86-NEXT: .LBB2_1: +; X86-NEXT: .LBB2_3: ; X86-NEXT: movw $16, %cx ; X86-NEXT: testw %ax, %ax -; X86-NEXT: je .LBB2_5 +; X86-NEXT: je .LBB2_2 ; X86-NEXT: .LBB2_4: ; X86-NEXT: movzwl %cx, %eax ; X86-NEXT: xorl $15, %eax @@ -117,11 +117,11 @@ define i16 @cmov_bsr16_undef(i16 %x, i16 %y) nounwind { ; X86: # %bb.0: ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-NEXT: testw %ax, %ax -; X86-NEXT: je .LBB3_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: je .LBB3_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: bsrw %ax, %ax ; X86-NEXT: retl -; X86-NEXT: .LBB3_1: +; X86-NEXT: .LBB3_2: ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-NEXT: retl ; @@ -143,19 +143,19 @@ define i32 @cmov_bsr32(i32 %x, i32 %y) nounwind { ; X86: # %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: testl %ecx, %ecx -; X86-NEXT: je .LBB4_1 -; X86-NEXT: # %bb.2: # %cond.false +; X86-NEXT: je .LBB4_3 +; X86-NEXT: # %bb.1: # %cond.false ; X86-NEXT: bsrl %ecx, %eax ; X86-NEXT: xorl $31, %eax ; X86-NEXT: testl %ecx, %ecx ; X86-NEXT: je .LBB4_4 -; X86-NEXT: .LBB4_5: # %cond.end +; X86-NEXT: .LBB4_2: # %cond.end ; X86-NEXT: xorl $31, %eax ; X86-NEXT: retl -; X86-NEXT: .LBB4_1: +; X86-NEXT: .LBB4_3: ; X86-NEXT: movl $32, %eax ; X86-NEXT: testl %ecx, %ecx -; X86-NEXT: jne .LBB4_5 +; X86-NEXT: jne .LBB4_2 ; X86-NEXT: .LBB4_4: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: retl @@ -177,11 +177,11 @@ define i32 @cmov_bsr32_undef(i32 %x, i32 %y) nounwind { ; X86: # %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: testl %eax, %eax -; X86-NEXT: jne .LBB5_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: jne .LBB5_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB5_1: +; X86-NEXT: .LBB5_2: ; X86-NEXT: bsrl %eax, %eax ; X86-NEXT: retl ; @@ -204,30 +204,30 @@ define i64 @cmov_bsr64(i64 %x, i64 %y) nounwind { ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl %edx, %eax ; X86-NEXT: orl %ecx, %eax -; X86-NEXT: je .LBB6_1 -; X86-NEXT: # %bb.2: # %cond.false +; X86-NEXT: je .LBB6_3 +; X86-NEXT: # %bb.1: # %cond.false ; X86-NEXT: testl %ecx, %ecx -; X86-NEXT: jne .LBB6_3 -; X86-NEXT: # %bb.4: # %cond.false +; X86-NEXT: jne .LBB6_5 +; X86-NEXT: # %bb.2: # %cond.false ; X86-NEXT: bsrl %edx, %eax ; X86-NEXT: xorl $31, %eax ; X86-NEXT: orl $32, %eax ; X86-NEXT: orl %ecx, %edx -; X86-NEXT: je .LBB6_7 +; X86-NEXT: je .LBB6_4 ; X86-NEXT: jmp .LBB6_6 -; X86-NEXT: .LBB6_1: +; X86-NEXT: .LBB6_3: ; X86-NEXT: movl $64, %eax ; X86-NEXT: orl %ecx, %edx ; X86-NEXT: jne .LBB6_6 -; X86-NEXT: .LBB6_7: # %cond.end +; X86-NEXT: .LBB6_4: # %cond.end ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB6_3: +; X86-NEXT: .LBB6_5: ; X86-NEXT: bsrl %ecx, %eax ; X86-NEXT: xorl $31, %eax ; X86-NEXT: orl %ecx, %edx -; X86-NEXT: je .LBB6_7 +; X86-NEXT: je .LBB6_4 ; X86-NEXT: .LBB6_6: ; X86-NEXT: xorl $63, %eax ; X86-NEXT: xorl %edx, %edx @@ -251,23 +251,23 @@ define i64 @cmov_bsr64_undef(i64 %x, i64 %y) nounwind { ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: testl %edx, %edx -; X86-NEXT: jne .LBB7_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: jne .LBB7_3 +; X86-NEXT: # %bb.1: ; X86-NEXT: bsrl %ecx, %eax ; X86-NEXT: xorl $31, %eax ; X86-NEXT: orl $32, %eax ; X86-NEXT: orl %edx, %ecx -; X86-NEXT: jne .LBB7_5 -; X86-NEXT: .LBB7_4: +; X86-NEXT: jne .LBB7_4 +; X86-NEXT: .LBB7_2: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: retl -; X86-NEXT: .LBB7_1: +; X86-NEXT: .LBB7_3: ; X86-NEXT: bsrl %edx, %eax ; X86-NEXT: xorl $31, %eax ; X86-NEXT: orl %edx, %ecx -; X86-NEXT: je .LBB7_4 -; X86-NEXT: .LBB7_5: +; X86-NEXT: je .LBB7_2 +; X86-NEXT: .LBB7_4: ; X86-NEXT: xorl $63, %eax ; X86-NEXT: xorl %edx, %edx ; X86-NEXT: retl @@ -303,61 +303,61 @@ define i128 @cmov_bsr128(i128 %x, i128 %y) nounwind { ; X86-NEXT: movl %ecx, %edx ; X86-NEXT: orl %ebx, %edx ; X86-NEXT: orl %eax, %edx -; X86-NEXT: je .LBB8_1 -; X86-NEXT: # %bb.2: # %cond.false +; X86-NEXT: je .LBB8_4 +; X86-NEXT: # %bb.1: # %cond.false ; X86-NEXT: testl %esi, %esi -; X86-NEXT: jne .LBB8_3 -; X86-NEXT: # %bb.4: # %cond.false +; X86-NEXT: jne .LBB8_5 +; X86-NEXT: # %bb.2: # %cond.false ; X86-NEXT: movl %esi, %eax ; X86-NEXT: bsrl %ebx, %esi ; X86-NEXT: xorl $31, %esi ; X86-NEXT: orl $32, %esi ; X86-NEXT: testl %edi, %edi -; X86-NEXT: je .LBB8_7 -; X86-NEXT: .LBB8_6: +; X86-NEXT: je .LBB8_6 +; X86-NEXT: .LBB8_3: ; X86-NEXT: bsrl %edi, %edx ; X86-NEXT: xorl $31, %edx ; X86-NEXT: orl %eax, %ebx -; X86-NEXT: je .LBB8_9 -; X86-NEXT: jmp .LBB8_10 -; X86-NEXT: .LBB8_1: +; X86-NEXT: je .LBB8_7 +; X86-NEXT: jmp .LBB8_8 +; X86-NEXT: .LBB8_4: ; X86-NEXT: movl %esi, %eax ; X86-NEXT: movl $128, %esi -; X86-NEXT: jmp .LBB8_11 -; X86-NEXT: .LBB8_3: +; X86-NEXT: jmp .LBB8_9 +; X86-NEXT: .LBB8_5: ; X86-NEXT: movl %esi, %eax ; X86-NEXT: bsrl %esi, %esi ; X86-NEXT: xorl $31, %esi ; X86-NEXT: testl %edi, %edi -; X86-NEXT: jne .LBB8_6 -; X86-NEXT: .LBB8_7: # %cond.false +; X86-NEXT: jne .LBB8_3 +; X86-NEXT: .LBB8_6: # %cond.false ; X86-NEXT: bsrl %ecx, %edx ; X86-NEXT: xorl $31, %edx ; X86-NEXT: orl $32, %edx ; X86-NEXT: orl %eax, %ebx -; X86-NEXT: jne .LBB8_10 -; X86-NEXT: .LBB8_9: # %cond.false +; X86-NEXT: jne .LBB8_8 +; X86-NEXT: .LBB8_7: # %cond.false ; X86-NEXT: orl $64, %edx ; X86-NEXT: movl %edx, %esi -; X86-NEXT: .LBB8_10: # %cond.false +; X86-NEXT: .LBB8_8: # %cond.false ; X86-NEXT: movl 32(%ebp), %ebx -; X86-NEXT: .LBB8_11: # %cond.end +; X86-NEXT: .LBB8_9: # %cond.end ; X86-NEXT: orl %ebx, %ecx ; X86-NEXT: orl %eax, %edi ; X86-NEXT: orl %ecx, %edi -; X86-NEXT: je .LBB8_12 -; X86-NEXT: # %bb.13: # %cond.end +; X86-NEXT: je .LBB8_11 +; X86-NEXT: # %bb.10: # %cond.end ; X86-NEXT: xorl $127, %esi ; X86-NEXT: xorl %ecx, %ecx ; X86-NEXT: xorl %edx, %edx ; X86-NEXT: xorl %edi, %edi -; X86-NEXT: jmp .LBB8_14 -; X86-NEXT: .LBB8_12: +; X86-NEXT: jmp .LBB8_12 +; X86-NEXT: .LBB8_11: ; X86-NEXT: movl 52(%ebp), %edi ; X86-NEXT: movl 48(%ebp), %edx ; X86-NEXT: movl 44(%ebp), %ecx ; X86-NEXT: movl 40(%ebp), %esi -; X86-NEXT: .LBB8_14: # %cond.end +; X86-NEXT: .LBB8_12: # %cond.end ; X86-NEXT: movl 8(%ebp), %eax ; X86-NEXT: movl %edi, 12(%eax) ; X86-NEXT: movl %edx, 8(%eax) @@ -408,51 +408,51 @@ define i128 @cmov_bsr128_undef(i128 %x, i128 %y) nounwind { ; X86-NEXT: movl 32(%ebp), %edi ; X86-NEXT: movl 36(%ebp), %eax ; X86-NEXT: testl %eax, %eax -; X86-NEXT: jne .LBB9_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: jne .LBB9_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: bsrl %edi, %esi ; X86-NEXT: xorl $31, %esi ; X86-NEXT: orl $32, %esi ; X86-NEXT: jmp .LBB9_3 -; X86-NEXT: .LBB9_1: +; X86-NEXT: .LBB9_2: ; X86-NEXT: bsrl %eax, %esi ; X86-NEXT: xorl $31, %esi ; X86-NEXT: .LBB9_3: ; X86-NEXT: movl 24(%ebp), %ebx ; X86-NEXT: testl %edx, %edx -; X86-NEXT: jne .LBB9_4 -; X86-NEXT: # %bb.5: +; X86-NEXT: jne .LBB9_5 +; X86-NEXT: # %bb.4: ; X86-NEXT: bsrl %ebx, %ecx ; X86-NEXT: xorl $31, %ecx ; X86-NEXT: orl $32, %ecx ; X86-NEXT: orl %eax, %edi -; X86-NEXT: je .LBB9_7 -; X86-NEXT: jmp .LBB9_8 -; X86-NEXT: .LBB9_4: +; X86-NEXT: je .LBB9_6 +; X86-NEXT: jmp .LBB9_7 +; X86-NEXT: .LBB9_5: ; X86-NEXT: bsrl %edx, %ecx ; X86-NEXT: xorl $31, %ecx ; X86-NEXT: orl %eax, %edi -; X86-NEXT: jne .LBB9_8 -; X86-NEXT: .LBB9_7: +; X86-NEXT: jne .LBB9_7 +; X86-NEXT: .LBB9_6: ; X86-NEXT: orl $64, %ecx ; X86-NEXT: movl %ecx, %esi -; X86-NEXT: .LBB9_8: +; X86-NEXT: .LBB9_7: ; X86-NEXT: orl %eax, %edx ; X86-NEXT: orl 32(%ebp), %ebx ; X86-NEXT: orl %edx, %ebx ; X86-NEXT: jne .LBB9_9 -; X86-NEXT: # %bb.10: +; X86-NEXT: # %bb.8: ; X86-NEXT: movl 48(%ebp), %edx ; X86-NEXT: movl 52(%ebp), %edi ; X86-NEXT: movl 40(%ebp), %esi ; X86-NEXT: movl 44(%ebp), %ecx -; X86-NEXT: jmp .LBB9_11 +; X86-NEXT: jmp .LBB9_10 ; X86-NEXT: .LBB9_9: ; X86-NEXT: xorl $127, %esi ; X86-NEXT: xorl %ecx, %ecx ; X86-NEXT: xorl %edx, %edx ; X86-NEXT: xorl %edi, %edi -; X86-NEXT: .LBB9_11: +; X86-NEXT: .LBB9_10: ; X86-NEXT: movl 8(%ebp), %eax ; X86-NEXT: movl %edi, 12(%eax) ; X86-NEXT: movl %edx, 8(%eax) diff --git a/llvm/test/CodeGen/X86/bt.ll b/llvm/test/CodeGen/X86/bt.ll index 3a792abda1230..d1490599de607 100644 --- a/llvm/test/CodeGen/X86/bt.ll +++ b/llvm/test/CodeGen/X86/bt.ll @@ -63,20 +63,20 @@ define void @test2b(i32 %x, i32 %n) nounwind { ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: btl %ecx, %eax -; X86-NEXT: jae .LBB1_1 -; X86-NEXT: # %bb.2: # %UnifiedReturnBlock +; X86-NEXT: jae .LBB1_2 +; X86-NEXT: # %bb.1: # %UnifiedReturnBlock ; X86-NEXT: retl -; X86-NEXT: .LBB1_1: # %bb +; X86-NEXT: .LBB1_2: # %bb ; X86-NEXT: calll foo@PLT ; X86-NEXT: retl ; ; X64-LABEL: test2b: ; X64: # %bb.0: # %entry ; X64-NEXT: btl %esi, %edi -; X64-NEXT: jae .LBB1_1 -; X64-NEXT: # %bb.2: # %UnifiedReturnBlock +; X64-NEXT: jae .LBB1_2 +; X64-NEXT: # %bb.1: # %UnifiedReturnBlock ; X64-NEXT: retq -; X64-NEXT: .LBB1_1: # %bb +; X64-NEXT: .LBB1_2: # %bb ; X64-NEXT: pushq %rax ; X64-NEXT: callq foo@PLT ; X64-NEXT: popq %rax @@ -137,20 +137,20 @@ define void @atest2b(i32 %x, i32 %n) nounwind { ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: btl %ecx, %eax -; X86-NEXT: jae .LBB3_1 -; X86-NEXT: # %bb.2: # %UnifiedReturnBlock +; X86-NEXT: jae .LBB3_2 +; X86-NEXT: # %bb.1: # %UnifiedReturnBlock ; X86-NEXT: retl -; X86-NEXT: .LBB3_1: # %bb +; X86-NEXT: .LBB3_2: # %bb ; X86-NEXT: calll foo@PLT ; X86-NEXT: retl ; ; X64-LABEL: atest2b: ; X64: # %bb.0: # %entry ; X64-NEXT: btl %esi, %edi -; X64-NEXT: jae .LBB3_1 -; X64-NEXT: # %bb.2: # %UnifiedReturnBlock +; X64-NEXT: jae .LBB3_2 +; X64-NEXT: # %bb.1: # %UnifiedReturnBlock ; X64-NEXT: retq -; X64-NEXT: .LBB3_1: # %bb +; X64-NEXT: .LBB3_2: # %bb ; X64-NEXT: pushq %rax ; X64-NEXT: callq foo@PLT ; X64-NEXT: popq %rax @@ -175,20 +175,20 @@ define void @test3(i32 %x, i32 %n) nounwind { ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: btl %ecx, %eax -; X86-NEXT: jae .LBB4_1 -; X86-NEXT: # %bb.2: # %UnifiedReturnBlock +; X86-NEXT: jae .LBB4_2 +; X86-NEXT: # %bb.1: # %UnifiedReturnBlock ; X86-NEXT: retl -; X86-NEXT: .LBB4_1: # %bb +; X86-NEXT: .LBB4_2: # %bb ; X86-NEXT: calll foo@PLT ; X86-NEXT: retl ; ; X64-LABEL: test3: ; X64: # %bb.0: # %entry ; X64-NEXT: btl %esi, %edi -; X64-NEXT: jae .LBB4_1 -; X64-NEXT: # %bb.2: # %UnifiedReturnBlock +; X64-NEXT: jae .LBB4_2 +; X64-NEXT: # %bb.1: # %UnifiedReturnBlock ; X64-NEXT: retq -; X64-NEXT: .LBB4_1: # %bb +; X64-NEXT: .LBB4_2: # %bb ; X64-NEXT: pushq %rax ; X64-NEXT: callq foo@PLT ; X64-NEXT: popq %rax @@ -213,20 +213,20 @@ define void @test3b(i32 %x, i32 %n) nounwind { ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: btl %ecx, %eax -; X86-NEXT: jae .LBB5_1 -; X86-NEXT: # %bb.2: # %UnifiedReturnBlock +; X86-NEXT: jae .LBB5_2 +; X86-NEXT: # %bb.1: # %UnifiedReturnBlock ; X86-NEXT: retl -; X86-NEXT: .LBB5_1: # %bb +; X86-NEXT: .LBB5_2: # %bb ; X86-NEXT: calll foo@PLT ; X86-NEXT: retl ; ; X64-LABEL: test3b: ; X64: # %bb.0: # %entry ; X64-NEXT: btl %esi, %edi -; X64-NEXT: jae .LBB5_1 -; X64-NEXT: # %bb.2: # %UnifiedReturnBlock +; X64-NEXT: jae .LBB5_2 +; X64-NEXT: # %bb.1: # %UnifiedReturnBlock ; X64-NEXT: retq -; X64-NEXT: .LBB5_1: # %bb +; X64-NEXT: .LBB5_2: # %bb ; X64-NEXT: pushq %rax ; X64-NEXT: callq foo@PLT ; X64-NEXT: popq %rax diff --git a/llvm/test/CodeGen/X86/bypass-slow-division-32.ll b/llvm/test/CodeGen/X86/bypass-slow-division-32.ll index fe4201d9a2f73..e7fa729a293e7 100644 --- a/llvm/test/CodeGen/X86/bypass-slow-division-32.ll +++ b/llvm/test/CodeGen/X86/bypass-slow-division-32.ll @@ -10,12 +10,12 @@ define i32 @Test_get_quotient(i32 %a, i32 %b) nounwind { ; CHECK-NEXT: movl %eax, %edx ; CHECK-NEXT: orl %ecx, %edx ; CHECK-NEXT: testl $-256, %edx -; CHECK-NEXT: je .LBB0_1 -; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: je .LBB0_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: cltd ; CHECK-NEXT: idivl %ecx ; CHECK-NEXT: retl -; CHECK-NEXT: .LBB0_1: +; CHECK-NEXT: .LBB0_2: ; CHECK-NEXT: movzbl %al, %eax ; CHECK-NEXT: divb %cl ; CHECK-NEXT: movzbl %al, %eax @@ -32,13 +32,13 @@ define i32 @Test_get_remainder(i32 %a, i32 %b) nounwind { ; CHECK-NEXT: movl %eax, %edx ; CHECK-NEXT: orl %ecx, %edx ; CHECK-NEXT: testl $-256, %edx -; CHECK-NEXT: je .LBB1_1 -; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: je .LBB1_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: cltd ; CHECK-NEXT: idivl %ecx ; CHECK-NEXT: movl %edx, %eax ; CHECK-NEXT: retl -; CHECK-NEXT: .LBB1_1: +; CHECK-NEXT: .LBB1_2: ; CHECK-NEXT: movzbl %al, %eax ; CHECK-NEXT: divb %cl ; CHECK-NEXT: movzbl %ah, %eax @@ -55,13 +55,13 @@ define i32 @Test_get_quotient_and_remainder(i32 %a, i32 %b) nounwind { ; CHECK-NEXT: movl %eax, %edx ; CHECK-NEXT: orl %ecx, %edx ; CHECK-NEXT: testl $-256, %edx -; CHECK-NEXT: je .LBB2_1 -; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: je .LBB2_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: cltd ; CHECK-NEXT: idivl %ecx ; CHECK-NEXT: addl %edx, %eax ; CHECK-NEXT: retl -; CHECK-NEXT: .LBB2_1: +; CHECK-NEXT: .LBB2_2: ; CHECK-NEXT: movzbl %al, %eax ; CHECK-NEXT: divb %cl ; CHECK-NEXT: movzbl %ah, %edx @@ -85,30 +85,30 @@ define i32 @Test_use_div_and_idiv(i32 %a, i32 %b) nounwind { ; CHECK-NEXT: movl %ecx, %edi ; CHECK-NEXT: orl %ebx, %edi ; CHECK-NEXT: testl $-256, %edi -; CHECK-NEXT: je .LBB3_1 -; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: je .LBB3_3 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: movl %ecx, %eax ; CHECK-NEXT: cltd ; CHECK-NEXT: idivl %ebx ; CHECK-NEXT: movl %eax, %esi ; CHECK-NEXT: testl $-256, %edi ; CHECK-NEXT: je .LBB3_4 -; CHECK-NEXT: .LBB3_5: +; CHECK-NEXT: .LBB3_2: ; CHECK-NEXT: movl %ecx, %eax ; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: divl %ebx -; CHECK-NEXT: jmp .LBB3_6 -; CHECK-NEXT: .LBB3_1: +; CHECK-NEXT: jmp .LBB3_5 +; CHECK-NEXT: .LBB3_3: ; CHECK-NEXT: movzbl %cl, %eax ; CHECK-NEXT: divb %bl ; CHECK-NEXT: movzbl %al, %esi ; CHECK-NEXT: testl $-256, %edi -; CHECK-NEXT: jne .LBB3_5 +; CHECK-NEXT: jne .LBB3_2 ; CHECK-NEXT: .LBB3_4: ; CHECK-NEXT: movzbl %cl, %eax ; CHECK-NEXT: divb %bl ; CHECK-NEXT: movzbl %al, %eax -; CHECK-NEXT: .LBB3_6: +; CHECK-NEXT: .LBB3_5: ; CHECK-NEXT: addl %eax, %esi ; CHECK-NEXT: movl %esi, %eax ; CHECK-NEXT: popl %esi @@ -194,13 +194,13 @@ define i32 @Test_use_div_imm_reg(i32 %a) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: testl $-256, %ecx -; CHECK-NEXT: je .LBB8_1 -; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: je .LBB8_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: movl $4, %eax ; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: idivl %ecx ; CHECK-NEXT: retl -; CHECK-NEXT: .LBB8_1: +; CHECK-NEXT: .LBB8_2: ; CHECK-NEXT: movb $4, %al ; CHECK-NEXT: movzbl %al, %eax ; CHECK-NEXT: divb %cl @@ -215,13 +215,13 @@ define i32 @Test_use_rem_imm_reg(i32 %a) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: testl $-256, %ecx -; CHECK-NEXT: je .LBB9_1 -; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: je .LBB9_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: movl $4, %eax ; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: idivl %ecx ; CHECK-NEXT: retl -; CHECK-NEXT: .LBB9_1: +; CHECK-NEXT: .LBB9_2: ; CHECK-NEXT: movb $4, %al ; CHECK-NEXT: movzbl %al, %eax ; CHECK-NEXT: divb %cl diff --git a/llvm/test/CodeGen/X86/bypass-slow-division-64.ll b/llvm/test/CodeGen/X86/bypass-slow-division-64.ll index 821b7b8e4144f..0456efdd25140 100644 --- a/llvm/test/CodeGen/X86/bypass-slow-division-64.ll +++ b/llvm/test/CodeGen/X86/bypass-slow-division-64.ll @@ -46,12 +46,12 @@ define i64 @sdiv_quotient(i64 %a, i64 %b) nounwind { ; SLOW-DIVQ-DAG: movq %rdi, %rcx ; SLOW-DIVQ-DAG: orq %rsi, %rcx ; SLOW-DIVQ-DAG: shrq $32, %rcx -; SLOW-DIVQ-NEXT: je .LBB0_1 -; SLOW-DIVQ-NEXT: # %bb.2: +; SLOW-DIVQ-NEXT: je .LBB0_2 +; SLOW-DIVQ-NEXT: # %bb.1: ; SLOW-DIVQ-NEXT: cqto ; SLOW-DIVQ-NEXT: idivq %rsi ; SLOW-DIVQ-NEXT: retq -; SLOW-DIVQ-NEXT: .LBB0_1: +; SLOW-DIVQ-NEXT: .LBB0_2: ; SLOW-DIVQ-DAG: # kill: def $eax killed $eax killed $rax ; SLOW-DIVQ-DAG: xorl %edx, %edx ; SLOW-DIVQ-NEXT: divl %esi @@ -98,13 +98,13 @@ define i64 @sdiv_remainder(i64 %a, i64 %b) nounwind { ; SLOW-DIVQ-DAG: movq %rdi, %rcx ; SLOW-DIVQ-DAG: orq %rsi, %rcx ; SLOW-DIVQ-DAG: shrq $32, %rcx -; SLOW-DIVQ-NEXT: je .LBB3_1 -; SLOW-DIVQ-NEXT: # %bb.2: +; SLOW-DIVQ-NEXT: je .LBB3_2 +; SLOW-DIVQ-NEXT: # %bb.1: ; SLOW-DIVQ-NEXT: cqto ; SLOW-DIVQ-NEXT: idivq %rsi ; SLOW-DIVQ-NEXT: movq %rdx, %rax ; SLOW-DIVQ-NEXT: retq -; SLOW-DIVQ-NEXT: .LBB3_1: +; SLOW-DIVQ-NEXT: .LBB3_2: ; SLOW-DIVQ-DAG: # kill: def $eax killed $eax killed $rax ; SLOW-DIVQ-DAG: xorl %edx, %edx ; SLOW-DIVQ-NEXT: divl %esi @@ -153,13 +153,13 @@ define i64 @sdiv_quotient_and_remainder(i64 %a, i64 %b) nounwind { ; SLOW-DIVQ-DAG: movq %rdi, %rcx ; SLOW-DIVQ-DAG: orq %rsi, %rcx ; SLOW-DIVQ-DAG: shrq $32, %rcx -; SLOW-DIVQ-NEXT: je .LBB6_1 -; SLOW-DIVQ-NEXT: # %bb.2: +; SLOW-DIVQ-NEXT: je .LBB6_2 +; SLOW-DIVQ-NEXT: # %bb.1: ; SLOW-DIVQ-NEXT: cqto ; SLOW-DIVQ-NEXT: idivq %rsi ; SLOW-DIVQ-NEXT: addq %rdx, %rax ; SLOW-DIVQ-NEXT: retq -; SLOW-DIVQ-NEXT: .LBB6_1: +; SLOW-DIVQ-NEXT: .LBB6_2: ; SLOW-DIVQ-DAG: # kill: def $eax killed $eax killed $rax ; SLOW-DIVQ-DAG: xorl %edx, %edx ; SLOW-DIVQ-NEXT: divl %esi @@ -219,12 +219,12 @@ define i64 @udiv_quotient(i64 %a, i64 %b) nounwind { ; SLOW-DIVQ-DAG: movq %rdi, %rcx ; SLOW-DIVQ-DAG: orq %rsi, %rcx ; SLOW-DIVQ-DAG: shrq $32, %rcx -; SLOW-DIVQ-NEXT: je .LBB9_1 -; SLOW-DIVQ-NEXT: # %bb.2: +; SLOW-DIVQ-NEXT: je .LBB9_2 +; SLOW-DIVQ-NEXT: # %bb.1: ; SLOW-DIVQ-NEXT: xorl %edx, %edx ; SLOW-DIVQ-NEXT: divq %rsi ; SLOW-DIVQ-NEXT: retq -; SLOW-DIVQ-NEXT: .LBB9_1: +; SLOW-DIVQ-NEXT: .LBB9_2: ; SLOW-DIVQ-DAG: # kill: def $eax killed $eax killed $rax ; SLOW-DIVQ-DAG: xorl %edx, %edx ; SLOW-DIVQ-NEXT: divl %esi @@ -271,13 +271,13 @@ define i64 @udiv_remainder(i64 %a, i64 %b) nounwind { ; SLOW-DIVQ-DAG: movq %rdi, %rcx ; SLOW-DIVQ-DAG: orq %rsi, %rcx ; SLOW-DIVQ-DAG: shrq $32, %rcx -; SLOW-DIVQ-NEXT: je .LBB12_1 -; SLOW-DIVQ-NEXT: # %bb.2: +; SLOW-DIVQ-NEXT: je .LBB12_2 +; SLOW-DIVQ-NEXT: # %bb.1: ; SLOW-DIVQ-NEXT: xorl %edx, %edx ; SLOW-DIVQ-NEXT: divq %rsi ; SLOW-DIVQ-NEXT: movq %rdx, %rax ; SLOW-DIVQ-NEXT: retq -; SLOW-DIVQ-NEXT: .LBB12_1: +; SLOW-DIVQ-NEXT: .LBB12_2: ; SLOW-DIVQ-DAG: # kill: def $eax killed $eax killed $rax ; SLOW-DIVQ-DAG: xorl %edx, %edx ; SLOW-DIVQ-NEXT: divl %esi @@ -326,13 +326,13 @@ define i64 @udiv_quotient_and_remainder(i64 %a, i64 %b) nounwind { ; SLOW-DIVQ-DAG: movq %rdi, %rcx ; SLOW-DIVQ-DAG: orq %rsi, %rcx ; SLOW-DIVQ-DAG: shrq $32, %rcx -; SLOW-DIVQ-NEXT: je .LBB15_1 -; SLOW-DIVQ-NEXT: # %bb.2: +; SLOW-DIVQ-NEXT: je .LBB15_2 +; SLOW-DIVQ-NEXT: # %bb.1: ; SLOW-DIVQ-NEXT: xorl %edx, %edx ; SLOW-DIVQ-NEXT: divq %rsi ; SLOW-DIVQ-NEXT: addq %rdx, %rax ; SLOW-DIVQ-NEXT: retq -; SLOW-DIVQ-NEXT: .LBB15_1: +; SLOW-DIVQ-NEXT: .LBB15_2: ; SLOW-DIVQ-DAG: # kill: def $eax killed $eax killed $rax ; SLOW-DIVQ-DAG: xorl %edx, %edx ; SLOW-DIVQ-NEXT: divl %esi diff --git a/llvm/test/CodeGen/X86/bypass-slow-division-tune.ll b/llvm/test/CodeGen/X86/bypass-slow-division-tune.ll index afecf00113a0a..33fe7f58c4c74 100644 --- a/llvm/test/CodeGen/X86/bypass-slow-division-tune.ll +++ b/llvm/test/CodeGen/X86/bypass-slow-division-tune.ll @@ -15,13 +15,13 @@ define i32 @div32(i32 %a, i32 %b) { ; ATOM-NEXT: movl %edi, %eax ; ATOM-NEXT: orl %esi, %eax ; ATOM-NEXT: testl $-256, %eax -; ATOM-NEXT: je .LBB0_1 -; ATOM-NEXT: # %bb.2: +; ATOM-NEXT: je .LBB0_2 +; ATOM-NEXT: # %bb.1: ; ATOM-NEXT: movl %edi, %eax ; ATOM-NEXT: cltd ; ATOM-NEXT: idivl %esi ; ATOM-NEXT: retq -; ATOM-NEXT: .LBB0_1: +; ATOM-NEXT: .LBB0_2: ; ATOM-NEXT: movzbl %dil, %eax ; ATOM-NEXT: divb %sil ; ATOM-NEXT: movzbl %al, %eax @@ -53,12 +53,12 @@ define i64 @div64(i64 %a, i64 %b) { ; ATOM-NEXT: movq %rdi, %rax ; ATOM-NEXT: orq %rsi, %rcx ; ATOM-NEXT: shrq $32, %rcx -; ATOM-NEXT: je .LBB1_1 -; ATOM-NEXT: # %bb.2: +; ATOM-NEXT: je .LBB1_2 +; ATOM-NEXT: # %bb.1: ; ATOM-NEXT: cqto ; ATOM-NEXT: idivq %rsi ; ATOM-NEXT: retq -; ATOM-NEXT: .LBB1_1: +; ATOM-NEXT: .LBB1_2: ; ATOM-NEXT: # kill: def $eax killed $eax killed $rax ; ATOM-NEXT: xorl %edx, %edx ; ATOM-NEXT: divl %esi @@ -71,12 +71,12 @@ define i64 @div64(i64 %a, i64 %b) { ; X64-NEXT: movq %rdi, %rcx ; X64-NEXT: orq %rsi, %rcx ; X64-NEXT: shrq $32, %rcx -; X64-NEXT: je .LBB1_1 -; X64-NEXT: # %bb.2: +; X64-NEXT: je .LBB1_2 +; X64-NEXT: # %bb.1: ; X64-NEXT: cqto ; X64-NEXT: idivq %rsi ; X64-NEXT: retq -; X64-NEXT: .LBB1_1: +; X64-NEXT: .LBB1_2: ; X64-NEXT: # kill: def $eax killed $eax killed $rax ; X64-NEXT: xorl %edx, %edx ; X64-NEXT: divl %esi @@ -89,12 +89,12 @@ define i64 @div64(i64 %a, i64 %b) { ; SLM-NEXT: movq %rdi, %rax ; SLM-NEXT: orq %rsi, %rcx ; SLM-NEXT: shrq $32, %rcx -; SLM-NEXT: je .LBB1_1 -; SLM-NEXT: # %bb.2: +; SLM-NEXT: je .LBB1_2 +; SLM-NEXT: # %bb.1: ; SLM-NEXT: cqto ; SLM-NEXT: idivq %rsi ; SLM-NEXT: retq -; SLM-NEXT: .LBB1_1: +; SLM-NEXT: .LBB1_2: ; SLM-NEXT: xorl %edx, %edx ; SLM-NEXT: # kill: def $eax killed $eax killed $rax ; SLM-NEXT: divl %esi @@ -107,12 +107,12 @@ define i64 @div64(i64 %a, i64 %b) { ; SKL-NEXT: movq %rdi, %rcx ; SKL-NEXT: orq %rsi, %rcx ; SKL-NEXT: shrq $32, %rcx -; SKL-NEXT: je .LBB1_1 -; SKL-NEXT: # %bb.2: +; SKL-NEXT: je .LBB1_2 +; SKL-NEXT: # %bb.1: ; SKL-NEXT: cqto ; SKL-NEXT: idivq %rsi ; SKL-NEXT: retq -; SKL-NEXT: .LBB1_1: +; SKL-NEXT: .LBB1_2: ; SKL-NEXT: # kill: def $eax killed $eax killed $rax ; SKL-NEXT: xorl %edx, %edx ; SKL-NEXT: divl %esi @@ -183,12 +183,12 @@ define i64 @div64_hugews(i64 %a, i64 %b) { ; ATOM-NEXT: movq %rdi, %rax ; ATOM-NEXT: orq %rsi, %rcx ; ATOM-NEXT: shrq $32, %rcx -; ATOM-NEXT: je .LBB4_1 -; ATOM-NEXT: # %bb.2: +; ATOM-NEXT: je .LBB4_2 +; ATOM-NEXT: # %bb.1: ; ATOM-NEXT: cqto ; ATOM-NEXT: idivq %rsi ; ATOM-NEXT: retq -; ATOM-NEXT: .LBB4_1: +; ATOM-NEXT: .LBB4_2: ; ATOM-NEXT: # kill: def $eax killed $eax killed $rax ; ATOM-NEXT: xorl %edx, %edx ; ATOM-NEXT: divl %esi @@ -201,12 +201,12 @@ define i64 @div64_hugews(i64 %a, i64 %b) { ; X64-NEXT: movq %rdi, %rcx ; X64-NEXT: orq %rsi, %rcx ; X64-NEXT: shrq $32, %rcx -; X64-NEXT: je .LBB4_1 -; X64-NEXT: # %bb.2: +; X64-NEXT: je .LBB4_2 +; X64-NEXT: # %bb.1: ; X64-NEXT: cqto ; X64-NEXT: idivq %rsi ; X64-NEXT: retq -; X64-NEXT: .LBB4_1: +; X64-NEXT: .LBB4_2: ; X64-NEXT: # kill: def $eax killed $eax killed $rax ; X64-NEXT: xorl %edx, %edx ; X64-NEXT: divl %esi @@ -219,12 +219,12 @@ define i64 @div64_hugews(i64 %a, i64 %b) { ; SLM-NEXT: movq %rdi, %rax ; SLM-NEXT: orq %rsi, %rcx ; SLM-NEXT: shrq $32, %rcx -; SLM-NEXT: je .LBB4_1 -; SLM-NEXT: # %bb.2: +; SLM-NEXT: je .LBB4_2 +; SLM-NEXT: # %bb.1: ; SLM-NEXT: cqto ; SLM-NEXT: idivq %rsi ; SLM-NEXT: retq -; SLM-NEXT: .LBB4_1: +; SLM-NEXT: .LBB4_2: ; SLM-NEXT: xorl %edx, %edx ; SLM-NEXT: # kill: def $eax killed $eax killed $rax ; SLM-NEXT: divl %esi @@ -237,12 +237,12 @@ define i64 @div64_hugews(i64 %a, i64 %b) { ; SKL-NEXT: movq %rdi, %rcx ; SKL-NEXT: orq %rsi, %rcx ; SKL-NEXT: shrq $32, %rcx -; SKL-NEXT: je .LBB4_1 -; SKL-NEXT: # %bb.2: +; SKL-NEXT: je .LBB4_2 +; SKL-NEXT: # %bb.1: ; SKL-NEXT: cqto ; SKL-NEXT: idivq %rsi ; SKL-NEXT: retq -; SKL-NEXT: .LBB4_1: +; SKL-NEXT: .LBB4_2: ; SKL-NEXT: # kill: def $eax killed $eax killed $rax ; SKL-NEXT: xorl %edx, %edx ; SKL-NEXT: divl %esi diff --git a/llvm/test/CodeGen/X86/callbr-asm-sink.ll b/llvm/test/CodeGen/X86/callbr-asm-sink.ll index c0a501fba0919..e664ebe2b81f7 100644 --- a/llvm/test/CodeGen/X86/callbr-asm-sink.ll +++ b/llvm/test/CodeGen/X86/callbr-asm-sink.ll @@ -12,11 +12,11 @@ define void @klist_dec_and_del(ptr) { ; CHECK: # %bb.0: ; CHECK-NEXT: leaq 8(%rdi), %rax ; CHECK-NEXT: #APP -; CHECK-NEXT: # 8(%rdi) .LBB0_1 +; CHECK-NEXT: # 8(%rdi) .LBB0_2 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB0_1: # Inline asm indirect target +; CHECK-NEXT: .LBB0_2: # Inline asm indirect target ; CHECK-NEXT: # Label of block must be emitted ; CHECK-NEXT: movq $0, -8(%rax) ; CHECK-NEXT: retq diff --git a/llvm/test/CodeGen/X86/callbr-asm.ll b/llvm/test/CodeGen/X86/callbr-asm.ll index 16b23fa81e341..af67aa0ade16e 100644 --- a/llvm/test/CodeGen/X86/callbr-asm.ll +++ b/llvm/test/CodeGen/X86/callbr-asm.ll @@ -171,13 +171,13 @@ define void @test4() { ; CHECK-LABEL: test4: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: #APP -; CHECK-NEXT: ja .LBB4_3 +; CHECK-NEXT: ja .LBB4_2 ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: # %bb.1: # %asm.fallthrough ; CHECK-NEXT: #APP -; CHECK-NEXT: ja .LBB4_3 +; CHECK-NEXT: ja .LBB4_2 ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: .LBB4_3: # Inline asm indirect target +; CHECK-NEXT: .LBB4_2: # Inline asm indirect target ; CHECK-NEXT: # %quux ; CHECK-NEXT: # Label of block must be emitted ; CHECK-NEXT: retl diff --git a/llvm/test/CodeGen/X86/cgp-usubo.ll b/llvm/test/CodeGen/X86/cgp-usubo.ll index 57e2a2b22bc9b..cde1c18347ccb 100644 --- a/llvm/test/CodeGen/X86/cgp-usubo.ll +++ b/llvm/test/CodeGen/X86/cgp-usubo.ll @@ -129,18 +129,18 @@ define i1 @usubo_ult_sub_dominates_i64(i64 %x, i64 %y, ptr %p, i1 %cond) nounwin ; CHECK-LABEL: usubo_ult_sub_dominates_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: testb $1, %cl -; CHECK-NEXT: je .LBB8_2 +; CHECK-NEXT: je .LBB8_3 ; CHECK-NEXT: # %bb.1: # %t ; CHECK-NEXT: movq %rdi, %rax ; CHECK-NEXT: subq %rsi, %rax ; CHECK-NEXT: movq %rax, (%rdx) ; CHECK-NEXT: testb $1, %cl -; CHECK-NEXT: je .LBB8_2 -; CHECK-NEXT: # %bb.3: # %end +; CHECK-NEXT: je .LBB8_3 +; CHECK-NEXT: # %bb.2: # %end ; CHECK-NEXT: cmpq %rsi, %rdi ; CHECK-NEXT: setb %al ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB8_2: # %f +; CHECK-NEXT: .LBB8_3: # %f ; CHECK-NEXT: movl %ecx, %eax ; CHECK-NEXT: retq entry: @@ -169,7 +169,7 @@ define i1 @usubo_ult_cmp_dominates_i64(i64 %x, i64 %y, ptr %p, i1 %cond) nounwin ; CHECK-NEXT: pushq %rax ; CHECK-NEXT: movl %ecx, %ebp ; CHECK-NEXT: testb $1, %bpl -; CHECK-NEXT: je .LBB9_2 +; CHECK-NEXT: je .LBB9_3 ; CHECK-NEXT: # %bb.1: # %t ; CHECK-NEXT: movq %rdx, %rbx ; CHECK-NEXT: movq %rdi, %r14 @@ -179,14 +179,14 @@ define i1 @usubo_ult_cmp_dominates_i64(i64 %x, i64 %y, ptr %p, i1 %cond) nounwin ; CHECK-NEXT: movq %rsi, %r15 ; CHECK-NEXT: callq call@PLT ; CHECK-NEXT: subq %r15, %r14 -; CHECK-NEXT: jae .LBB9_2 -; CHECK-NEXT: # %bb.4: # %end +; CHECK-NEXT: jae .LBB9_3 +; CHECK-NEXT: # %bb.2: # %end ; CHECK-NEXT: setb %al ; CHECK-NEXT: movq %r14, (%rbx) -; CHECK-NEXT: jmp .LBB9_3 -; CHECK-NEXT: .LBB9_2: # %f -; CHECK-NEXT: movl %ebp, %eax +; CHECK-NEXT: jmp .LBB9_4 ; CHECK-NEXT: .LBB9_3: # %f +; CHECK-NEXT: movl %ebp, %eax +; CHECK-NEXT: .LBB9_4: # %f ; CHECK-NEXT: addq $8, %rsp ; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %r14 diff --git a/llvm/test/CodeGen/X86/clear-highbits.ll b/llvm/test/CodeGen/X86/clear-highbits.ll index 755b1094234fd..e46a6e0c33f49 100644 --- a/llvm/test/CodeGen/X86/clear-highbits.ll +++ b/llvm/test/CodeGen/X86/clear-highbits.ll @@ -530,11 +530,11 @@ define i64 @clear_highbits64_c0(i64 %val, i64 %numhighbits) nounwind { ; X86-BASELINE-NEXT: shrl %cl, %esi ; X86-BASELINE-NEXT: xorl %edx, %edx ; X86-BASELINE-NEXT: testb $32, %cl -; X86-BASELINE-NEXT: jne .LBB13_1 -; X86-BASELINE-NEXT: # %bb.2: +; X86-BASELINE-NEXT: jne .LBB13_2 +; X86-BASELINE-NEXT: # %bb.1: ; X86-BASELINE-NEXT: movl %esi, %edx ; X86-BASELINE-NEXT: jmp .LBB13_3 -; X86-BASELINE-NEXT: .LBB13_1: +; X86-BASELINE-NEXT: .LBB13_2: ; X86-BASELINE-NEXT: movl %esi, %eax ; X86-BASELINE-NEXT: .LBB13_3: ; X86-BASELINE-NEXT: andl {{[0-9]+}}(%esp), %eax @@ -603,11 +603,11 @@ define i64 @clear_highbits64_c1_indexzext(i64 %val, i8 %numhighbits) nounwind { ; X86-BASELINE-NEXT: shrl %cl, %esi ; X86-BASELINE-NEXT: xorl %edx, %edx ; X86-BASELINE-NEXT: testb $32, %cl -; X86-BASELINE-NEXT: jne .LBB14_1 -; X86-BASELINE-NEXT: # %bb.2: +; X86-BASELINE-NEXT: jne .LBB14_2 +; X86-BASELINE-NEXT: # %bb.1: ; X86-BASELINE-NEXT: movl %esi, %edx ; X86-BASELINE-NEXT: jmp .LBB14_3 -; X86-BASELINE-NEXT: .LBB14_1: +; X86-BASELINE-NEXT: .LBB14_2: ; X86-BASELINE-NEXT: movl %esi, %eax ; X86-BASELINE-NEXT: .LBB14_3: ; X86-BASELINE-NEXT: andl {{[0-9]+}}(%esp), %eax @@ -679,11 +679,11 @@ define i64 @clear_highbits64_c2_load(ptr %w, i64 %numhighbits) nounwind { ; X86-BASELINE-NEXT: shrl %cl, %edi ; X86-BASELINE-NEXT: xorl %edx, %edx ; X86-BASELINE-NEXT: testb $32, %cl -; X86-BASELINE-NEXT: jne .LBB15_1 -; X86-BASELINE-NEXT: # %bb.2: +; X86-BASELINE-NEXT: jne .LBB15_2 +; X86-BASELINE-NEXT: # %bb.1: ; X86-BASELINE-NEXT: movl %edi, %edx ; X86-BASELINE-NEXT: jmp .LBB15_3 -; X86-BASELINE-NEXT: .LBB15_1: +; X86-BASELINE-NEXT: .LBB15_2: ; X86-BASELINE-NEXT: movl %edi, %eax ; X86-BASELINE-NEXT: .LBB15_3: ; X86-BASELINE-NEXT: andl (%esi), %eax @@ -762,11 +762,11 @@ define i64 @clear_highbits64_c3_load_indexzext(ptr %w, i8 %numhighbits) nounwind ; X86-BASELINE-NEXT: shrl %cl, %edi ; X86-BASELINE-NEXT: xorl %edx, %edx ; X86-BASELINE-NEXT: testb $32, %cl -; X86-BASELINE-NEXT: jne .LBB16_1 -; X86-BASELINE-NEXT: # %bb.2: +; X86-BASELINE-NEXT: jne .LBB16_2 +; X86-BASELINE-NEXT: # %bb.1: ; X86-BASELINE-NEXT: movl %edi, %edx ; X86-BASELINE-NEXT: jmp .LBB16_3 -; X86-BASELINE-NEXT: .LBB16_1: +; X86-BASELINE-NEXT: .LBB16_2: ; X86-BASELINE-NEXT: movl %edi, %eax ; X86-BASELINE-NEXT: .LBB16_3: ; X86-BASELINE-NEXT: andl (%esi), %eax @@ -844,11 +844,11 @@ define i64 @clear_highbits64_c4_commutative(i64 %val, i64 %numhighbits) nounwind ; X86-BASELINE-NEXT: shrl %cl, %esi ; X86-BASELINE-NEXT: xorl %edx, %edx ; X86-BASELINE-NEXT: testb $32, %cl -; X86-BASELINE-NEXT: jne .LBB17_1 -; X86-BASELINE-NEXT: # %bb.2: +; X86-BASELINE-NEXT: jne .LBB17_2 +; X86-BASELINE-NEXT: # %bb.1: ; X86-BASELINE-NEXT: movl %esi, %edx ; X86-BASELINE-NEXT: jmp .LBB17_3 -; X86-BASELINE-NEXT: .LBB17_1: +; X86-BASELINE-NEXT: .LBB17_2: ; X86-BASELINE-NEXT: movl %esi, %eax ; X86-BASELINE-NEXT: .LBB17_3: ; X86-BASELINE-NEXT: andl {{[0-9]+}}(%esp), %eax diff --git a/llvm/test/CodeGen/X86/clear-lowbits.ll b/llvm/test/CodeGen/X86/clear-lowbits.ll index 49ea2d0f1ed7a..7f9b33377a47e 100644 --- a/llvm/test/CodeGen/X86/clear-lowbits.ll +++ b/llvm/test/CodeGen/X86/clear-lowbits.ll @@ -1665,11 +1665,11 @@ define i64 @oneuse64(i64 %val, i64 %numlowbits, ptr %escape) nounwind { ; X86-NOBMI2-NEXT: shll %cl, %edi ; X86-NOBMI2-NEXT: xorl %eax, %eax ; X86-NOBMI2-NEXT: testb $32, %cl -; X86-NOBMI2-NEXT: jne .LBB37_1 -; X86-NOBMI2-NEXT: # %bb.2: +; X86-NOBMI2-NEXT: jne .LBB37_2 +; X86-NOBMI2-NEXT: # %bb.1: ; X86-NOBMI2-NEXT: movl %edi, %eax ; X86-NOBMI2-NEXT: jmp .LBB37_3 -; X86-NOBMI2-NEXT: .LBB37_1: +; X86-NOBMI2-NEXT: .LBB37_2: ; X86-NOBMI2-NEXT: movl %edi, %edx ; X86-NOBMI2-NEXT: .LBB37_3: ; X86-NOBMI2-NEXT: movl %edx, 4(%esi) @@ -1690,11 +1690,11 @@ define i64 @oneuse64(i64 %val, i64 %numlowbits, ptr %escape) nounwind { ; X86-BMI2-NEXT: shlxl %ebx, %edx, %esi ; X86-BMI2-NEXT: xorl %eax, %eax ; X86-BMI2-NEXT: testb $32, %bl -; X86-BMI2-NEXT: jne .LBB37_1 -; X86-BMI2-NEXT: # %bb.2: +; X86-BMI2-NEXT: jne .LBB37_2 +; X86-BMI2-NEXT: # %bb.1: ; X86-BMI2-NEXT: movl %esi, %eax ; X86-BMI2-NEXT: jmp .LBB37_3 -; X86-BMI2-NEXT: .LBB37_1: +; X86-BMI2-NEXT: .LBB37_2: ; X86-BMI2-NEXT: movl %esi, %edx ; X86-BMI2-NEXT: .LBB37_3: ; X86-BMI2-NEXT: movl %edx, 4(%ecx) diff --git a/llvm/test/CodeGen/X86/cmov-fp.ll b/llvm/test/CodeGen/X86/cmov-fp.ll index 77665d083b7e3..9b526940e0c65 100644 --- a/llvm/test/CodeGen/X86/cmov-fp.ll +++ b/llvm/test/CodeGen/X86/cmov-fp.ll @@ -14,11 +14,11 @@ define double @test1(i32 %a, i32 %b, double %x) nounwind { ; SSE-NEXT: subl $8, %esp ; SSE-NEXT: movl 8(%ebp), %eax ; SSE-NEXT: cmpl 12(%ebp), %eax -; SSE-NEXT: ja .LBB0_1 -; SSE-NEXT: # %bb.2: +; SSE-NEXT: ja .LBB0_2 +; SSE-NEXT: # %bb.1: ; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; SSE-NEXT: jmp .LBB0_3 -; SSE-NEXT: .LBB0_1: +; SSE-NEXT: .LBB0_2: ; SSE-NEXT: movsd {{.*#+}} xmm0 = [9.9E+1,0.0E+0] ; SSE-NEXT: .LBB0_3: ; SSE-NEXT: movsd %xmm0, (%esp) @@ -66,11 +66,11 @@ define double @test2(i32 %a, i32 %b, double %x) nounwind { ; SSE-NEXT: subl $8, %esp ; SSE-NEXT: movl 8(%ebp), %eax ; SSE-NEXT: cmpl 12(%ebp), %eax -; SSE-NEXT: jae .LBB1_1 -; SSE-NEXT: # %bb.2: +; SSE-NEXT: jae .LBB1_2 +; SSE-NEXT: # %bb.1: ; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; SSE-NEXT: jmp .LBB1_3 -; SSE-NEXT: .LBB1_1: +; SSE-NEXT: .LBB1_2: ; SSE-NEXT: movsd {{.*#+}} xmm0 = [9.9E+1,0.0E+0] ; SSE-NEXT: .LBB1_3: ; SSE-NEXT: movsd %xmm0, (%esp) @@ -118,11 +118,11 @@ define double @test3(i32 %a, i32 %b, double %x) nounwind { ; SSE-NEXT: subl $8, %esp ; SSE-NEXT: movl 8(%ebp), %eax ; SSE-NEXT: cmpl 12(%ebp), %eax -; SSE-NEXT: jb .LBB2_1 -; SSE-NEXT: # %bb.2: +; SSE-NEXT: jb .LBB2_2 +; SSE-NEXT: # %bb.1: ; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; SSE-NEXT: jmp .LBB2_3 -; SSE-NEXT: .LBB2_1: +; SSE-NEXT: .LBB2_2: ; SSE-NEXT: movsd {{.*#+}} xmm0 = [9.9E+1,0.0E+0] ; SSE-NEXT: .LBB2_3: ; SSE-NEXT: movsd %xmm0, (%esp) @@ -170,11 +170,11 @@ define double @test4(i32 %a, i32 %b, double %x) nounwind { ; SSE-NEXT: subl $8, %esp ; SSE-NEXT: movl 8(%ebp), %eax ; SSE-NEXT: cmpl 12(%ebp), %eax -; SSE-NEXT: jbe .LBB3_1 -; SSE-NEXT: # %bb.2: +; SSE-NEXT: jbe .LBB3_2 +; SSE-NEXT: # %bb.1: ; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; SSE-NEXT: jmp .LBB3_3 -; SSE-NEXT: .LBB3_1: +; SSE-NEXT: .LBB3_2: ; SSE-NEXT: movsd {{.*#+}} xmm0 = [9.9E+1,0.0E+0] ; SSE-NEXT: .LBB3_3: ; SSE-NEXT: movsd %xmm0, (%esp) @@ -222,11 +222,11 @@ define double @test5(i32 %a, i32 %b, double %x) nounwind { ; SSE-NEXT: subl $8, %esp ; SSE-NEXT: movl 8(%ebp), %eax ; SSE-NEXT: cmpl 12(%ebp), %eax -; SSE-NEXT: jg .LBB4_1 -; SSE-NEXT: # %bb.2: +; SSE-NEXT: jg .LBB4_2 +; SSE-NEXT: # %bb.1: ; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; SSE-NEXT: jmp .LBB4_3 -; SSE-NEXT: .LBB4_1: +; SSE-NEXT: .LBB4_2: ; SSE-NEXT: movsd {{.*#+}} xmm0 = [9.9E+1,0.0E+0] ; SSE-NEXT: .LBB4_3: ; SSE-NEXT: movsd %xmm0, (%esp) @@ -276,11 +276,11 @@ define double @test6(i32 %a, i32 %b, double %x) nounwind { ; SSE-NEXT: subl $8, %esp ; SSE-NEXT: movl 8(%ebp), %eax ; SSE-NEXT: cmpl 12(%ebp), %eax -; SSE-NEXT: jge .LBB5_1 -; SSE-NEXT: # %bb.2: +; SSE-NEXT: jge .LBB5_2 +; SSE-NEXT: # %bb.1: ; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; SSE-NEXT: jmp .LBB5_3 -; SSE-NEXT: .LBB5_1: +; SSE-NEXT: .LBB5_2: ; SSE-NEXT: movsd {{.*#+}} xmm0 = [9.9E+1,0.0E+0] ; SSE-NEXT: .LBB5_3: ; SSE-NEXT: movsd %xmm0, (%esp) @@ -330,11 +330,11 @@ define double @test7(i32 %a, i32 %b, double %x) nounwind { ; SSE-NEXT: subl $8, %esp ; SSE-NEXT: movl 8(%ebp), %eax ; SSE-NEXT: cmpl 12(%ebp), %eax -; SSE-NEXT: jl .LBB6_1 -; SSE-NEXT: # %bb.2: +; SSE-NEXT: jl .LBB6_2 +; SSE-NEXT: # %bb.1: ; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; SSE-NEXT: jmp .LBB6_3 -; SSE-NEXT: .LBB6_1: +; SSE-NEXT: .LBB6_2: ; SSE-NEXT: movsd {{.*#+}} xmm0 = [9.9E+1,0.0E+0] ; SSE-NEXT: .LBB6_3: ; SSE-NEXT: movsd %xmm0, (%esp) @@ -384,11 +384,11 @@ define double @test8(i32 %a, i32 %b, double %x) nounwind { ; SSE-NEXT: subl $8, %esp ; SSE-NEXT: movl 8(%ebp), %eax ; SSE-NEXT: cmpl 12(%ebp), %eax -; SSE-NEXT: jle .LBB7_1 -; SSE-NEXT: # %bb.2: +; SSE-NEXT: jle .LBB7_2 +; SSE-NEXT: # %bb.1: ; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; SSE-NEXT: jmp .LBB7_3 -; SSE-NEXT: .LBB7_1: +; SSE-NEXT: .LBB7_2: ; SSE-NEXT: movsd {{.*#+}} xmm0 = [9.9E+1,0.0E+0] ; SSE-NEXT: .LBB7_3: ; SSE-NEXT: movsd %xmm0, (%esp) @@ -435,11 +435,11 @@ define float @test9(i32 %a, i32 %b, float %x) nounwind { ; SSE-NEXT: pushl %eax ; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax -; SSE-NEXT: ja .LBB8_1 -; SSE-NEXT: # %bb.2: +; SSE-NEXT: ja .LBB8_2 +; SSE-NEXT: # %bb.1: ; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE-NEXT: jmp .LBB8_3 -; SSE-NEXT: .LBB8_1: +; SSE-NEXT: .LBB8_2: ; SSE-NEXT: movss {{.*#+}} xmm0 = [9.9E+1,0.0E+0,0.0E+0,0.0E+0] ; SSE-NEXT: .LBB8_3: ; SSE-NEXT: movss %xmm0, (%esp) @@ -452,11 +452,11 @@ define float @test9(i32 %a, i32 %b, float %x) nounwind { ; NOSSE2-NEXT: pushl %eax ; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax -; NOSSE2-NEXT: ja .LBB8_1 -; NOSSE2-NEXT: # %bb.2: +; NOSSE2-NEXT: ja .LBB8_2 +; NOSSE2-NEXT: # %bb.1: ; NOSSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; NOSSE2-NEXT: jmp .LBB8_3 -; NOSSE2-NEXT: .LBB8_1: +; NOSSE2-NEXT: .LBB8_2: ; NOSSE2-NEXT: movss {{.*#+}} xmm0 = [9.9E+1,0.0E+0,0.0E+0,0.0E+0] ; NOSSE2-NEXT: .LBB8_3: ; NOSSE2-NEXT: movss %xmm0, (%esp) @@ -500,11 +500,11 @@ define float @test10(i32 %a, i32 %b, float %x) nounwind { ; SSE-NEXT: pushl %eax ; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax -; SSE-NEXT: jae .LBB9_1 -; SSE-NEXT: # %bb.2: +; SSE-NEXT: jae .LBB9_2 +; SSE-NEXT: # %bb.1: ; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE-NEXT: jmp .LBB9_3 -; SSE-NEXT: .LBB9_1: +; SSE-NEXT: .LBB9_2: ; SSE-NEXT: movss {{.*#+}} xmm0 = [9.9E+1,0.0E+0,0.0E+0,0.0E+0] ; SSE-NEXT: .LBB9_3: ; SSE-NEXT: movss %xmm0, (%esp) @@ -517,11 +517,11 @@ define float @test10(i32 %a, i32 %b, float %x) nounwind { ; NOSSE2-NEXT: pushl %eax ; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax -; NOSSE2-NEXT: jae .LBB9_1 -; NOSSE2-NEXT: # %bb.2: +; NOSSE2-NEXT: jae .LBB9_2 +; NOSSE2-NEXT: # %bb.1: ; NOSSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; NOSSE2-NEXT: jmp .LBB9_3 -; NOSSE2-NEXT: .LBB9_1: +; NOSSE2-NEXT: .LBB9_2: ; NOSSE2-NEXT: movss {{.*#+}} xmm0 = [9.9E+1,0.0E+0,0.0E+0,0.0E+0] ; NOSSE2-NEXT: .LBB9_3: ; NOSSE2-NEXT: movss %xmm0, (%esp) @@ -565,11 +565,11 @@ define float @test11(i32 %a, i32 %b, float %x) nounwind { ; SSE-NEXT: pushl %eax ; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax -; SSE-NEXT: jb .LBB10_1 -; SSE-NEXT: # %bb.2: +; SSE-NEXT: jb .LBB10_2 +; SSE-NEXT: # %bb.1: ; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE-NEXT: jmp .LBB10_3 -; SSE-NEXT: .LBB10_1: +; SSE-NEXT: .LBB10_2: ; SSE-NEXT: movss {{.*#+}} xmm0 = [9.9E+1,0.0E+0,0.0E+0,0.0E+0] ; SSE-NEXT: .LBB10_3: ; SSE-NEXT: movss %xmm0, (%esp) @@ -582,11 +582,11 @@ define float @test11(i32 %a, i32 %b, float %x) nounwind { ; NOSSE2-NEXT: pushl %eax ; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax -; NOSSE2-NEXT: jb .LBB10_1 -; NOSSE2-NEXT: # %bb.2: +; NOSSE2-NEXT: jb .LBB10_2 +; NOSSE2-NEXT: # %bb.1: ; NOSSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; NOSSE2-NEXT: jmp .LBB10_3 -; NOSSE2-NEXT: .LBB10_1: +; NOSSE2-NEXT: .LBB10_2: ; NOSSE2-NEXT: movss {{.*#+}} xmm0 = [9.9E+1,0.0E+0,0.0E+0,0.0E+0] ; NOSSE2-NEXT: .LBB10_3: ; NOSSE2-NEXT: movss %xmm0, (%esp) @@ -630,11 +630,11 @@ define float @test12(i32 %a, i32 %b, float %x) nounwind { ; SSE-NEXT: pushl %eax ; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax -; SSE-NEXT: jbe .LBB11_1 -; SSE-NEXT: # %bb.2: +; SSE-NEXT: jbe .LBB11_2 +; SSE-NEXT: # %bb.1: ; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE-NEXT: jmp .LBB11_3 -; SSE-NEXT: .LBB11_1: +; SSE-NEXT: .LBB11_2: ; SSE-NEXT: movss {{.*#+}} xmm0 = [9.9E+1,0.0E+0,0.0E+0,0.0E+0] ; SSE-NEXT: .LBB11_3: ; SSE-NEXT: movss %xmm0, (%esp) @@ -647,11 +647,11 @@ define float @test12(i32 %a, i32 %b, float %x) nounwind { ; NOSSE2-NEXT: pushl %eax ; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax -; NOSSE2-NEXT: jbe .LBB11_1 -; NOSSE2-NEXT: # %bb.2: +; NOSSE2-NEXT: jbe .LBB11_2 +; NOSSE2-NEXT: # %bb.1: ; NOSSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; NOSSE2-NEXT: jmp .LBB11_3 -; NOSSE2-NEXT: .LBB11_1: +; NOSSE2-NEXT: .LBB11_2: ; NOSSE2-NEXT: movss {{.*#+}} xmm0 = [9.9E+1,0.0E+0,0.0E+0,0.0E+0] ; NOSSE2-NEXT: .LBB11_3: ; NOSSE2-NEXT: movss %xmm0, (%esp) @@ -695,11 +695,11 @@ define float @test13(i32 %a, i32 %b, float %x) nounwind { ; SSE-NEXT: pushl %eax ; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax -; SSE-NEXT: jg .LBB12_1 -; SSE-NEXT: # %bb.2: +; SSE-NEXT: jg .LBB12_2 +; SSE-NEXT: # %bb.1: ; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE-NEXT: jmp .LBB12_3 -; SSE-NEXT: .LBB12_1: +; SSE-NEXT: .LBB12_2: ; SSE-NEXT: movss {{.*#+}} xmm0 = [9.9E+1,0.0E+0,0.0E+0,0.0E+0] ; SSE-NEXT: .LBB12_3: ; SSE-NEXT: movss %xmm0, (%esp) @@ -712,11 +712,11 @@ define float @test13(i32 %a, i32 %b, float %x) nounwind { ; NOSSE2-NEXT: pushl %eax ; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax -; NOSSE2-NEXT: jg .LBB12_1 -; NOSSE2-NEXT: # %bb.2: +; NOSSE2-NEXT: jg .LBB12_2 +; NOSSE2-NEXT: # %bb.1: ; NOSSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; NOSSE2-NEXT: jmp .LBB12_3 -; NOSSE2-NEXT: .LBB12_1: +; NOSSE2-NEXT: .LBB12_2: ; NOSSE2-NEXT: movss {{.*#+}} xmm0 = [9.9E+1,0.0E+0,0.0E+0,0.0E+0] ; NOSSE2-NEXT: .LBB12_3: ; NOSSE2-NEXT: movss %xmm0, (%esp) @@ -762,11 +762,11 @@ define float @test14(i32 %a, i32 %b, float %x) nounwind { ; SSE-NEXT: pushl %eax ; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax -; SSE-NEXT: jge .LBB13_1 -; SSE-NEXT: # %bb.2: +; SSE-NEXT: jge .LBB13_2 +; SSE-NEXT: # %bb.1: ; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE-NEXT: jmp .LBB13_3 -; SSE-NEXT: .LBB13_1: +; SSE-NEXT: .LBB13_2: ; SSE-NEXT: movss {{.*#+}} xmm0 = [9.9E+1,0.0E+0,0.0E+0,0.0E+0] ; SSE-NEXT: .LBB13_3: ; SSE-NEXT: movss %xmm0, (%esp) @@ -779,11 +779,11 @@ define float @test14(i32 %a, i32 %b, float %x) nounwind { ; NOSSE2-NEXT: pushl %eax ; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax -; NOSSE2-NEXT: jge .LBB13_1 -; NOSSE2-NEXT: # %bb.2: +; NOSSE2-NEXT: jge .LBB13_2 +; NOSSE2-NEXT: # %bb.1: ; NOSSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; NOSSE2-NEXT: jmp .LBB13_3 -; NOSSE2-NEXT: .LBB13_1: +; NOSSE2-NEXT: .LBB13_2: ; NOSSE2-NEXT: movss {{.*#+}} xmm0 = [9.9E+1,0.0E+0,0.0E+0,0.0E+0] ; NOSSE2-NEXT: .LBB13_3: ; NOSSE2-NEXT: movss %xmm0, (%esp) @@ -829,11 +829,11 @@ define float @test15(i32 %a, i32 %b, float %x) nounwind { ; SSE-NEXT: pushl %eax ; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax -; SSE-NEXT: jl .LBB14_1 -; SSE-NEXT: # %bb.2: +; SSE-NEXT: jl .LBB14_2 +; SSE-NEXT: # %bb.1: ; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE-NEXT: jmp .LBB14_3 -; SSE-NEXT: .LBB14_1: +; SSE-NEXT: .LBB14_2: ; SSE-NEXT: movss {{.*#+}} xmm0 = [9.9E+1,0.0E+0,0.0E+0,0.0E+0] ; SSE-NEXT: .LBB14_3: ; SSE-NEXT: movss %xmm0, (%esp) @@ -846,11 +846,11 @@ define float @test15(i32 %a, i32 %b, float %x) nounwind { ; NOSSE2-NEXT: pushl %eax ; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax -; NOSSE2-NEXT: jl .LBB14_1 -; NOSSE2-NEXT: # %bb.2: +; NOSSE2-NEXT: jl .LBB14_2 +; NOSSE2-NEXT: # %bb.1: ; NOSSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; NOSSE2-NEXT: jmp .LBB14_3 -; NOSSE2-NEXT: .LBB14_1: +; NOSSE2-NEXT: .LBB14_2: ; NOSSE2-NEXT: movss {{.*#+}} xmm0 = [9.9E+1,0.0E+0,0.0E+0,0.0E+0] ; NOSSE2-NEXT: .LBB14_3: ; NOSSE2-NEXT: movss %xmm0, (%esp) @@ -896,11 +896,11 @@ define float @test16(i32 %a, i32 %b, float %x) nounwind { ; SSE-NEXT: pushl %eax ; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax -; SSE-NEXT: jle .LBB15_1 -; SSE-NEXT: # %bb.2: +; SSE-NEXT: jle .LBB15_2 +; SSE-NEXT: # %bb.1: ; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE-NEXT: jmp .LBB15_3 -; SSE-NEXT: .LBB15_1: +; SSE-NEXT: .LBB15_2: ; SSE-NEXT: movss {{.*#+}} xmm0 = [9.9E+1,0.0E+0,0.0E+0,0.0E+0] ; SSE-NEXT: .LBB15_3: ; SSE-NEXT: movss %xmm0, (%esp) @@ -913,11 +913,11 @@ define float @test16(i32 %a, i32 %b, float %x) nounwind { ; NOSSE2-NEXT: pushl %eax ; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax -; NOSSE2-NEXT: jle .LBB15_1 -; NOSSE2-NEXT: # %bb.2: +; NOSSE2-NEXT: jle .LBB15_2 +; NOSSE2-NEXT: # %bb.1: ; NOSSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; NOSSE2-NEXT: jmp .LBB15_3 -; NOSSE2-NEXT: .LBB15_1: +; NOSSE2-NEXT: .LBB15_2: ; NOSSE2-NEXT: movss {{.*#+}} xmm0 = [9.9E+1,0.0E+0,0.0E+0,0.0E+0] ; NOSSE2-NEXT: .LBB15_3: ; NOSSE2-NEXT: movss %xmm0, (%esp) diff --git a/llvm/test/CodeGen/X86/cmov-into-branch.ll b/llvm/test/CodeGen/X86/cmov-into-branch.ll index b18283dd8e8d2..87a14aab03171 100644 --- a/llvm/test/CodeGen/X86/cmov-into-branch.ll +++ b/llvm/test/CodeGen/X86/cmov-into-branch.ll @@ -117,10 +117,10 @@ define i32 @weighted_select3(i32 %a, i32 %b) { ; CHECK: # %bb.0: ; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: testl %edi, %edi -; CHECK-NEXT: je .LBB7_1 -; CHECK-NEXT: # %bb.2: # %select.end +; CHECK-NEXT: je .LBB7_2 +; CHECK-NEXT: # %bb.1: # %select.end ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB7_1: # %select.false +; CHECK-NEXT: .LBB7_2: # %select.false ; CHECK-NEXT: movl %esi, %eax ; CHECK-NEXT: retq %cmp = icmp ne i32 %a, 0 diff --git a/llvm/test/CodeGen/X86/cmovcmov.ll b/llvm/test/CodeGen/X86/cmovcmov.ll index d2d1c4db4608d..d4476c6acf395 100644 --- a/llvm/test/CodeGen/X86/cmovcmov.ll +++ b/llvm/test/CodeGen/X86/cmovcmov.ll @@ -231,13 +231,13 @@ define dso_local float @test_zext_fcmp_une(float %a, float %b) nounwind { ; NOCMOV-NEXT: sahf ; NOCMOV-NEXT: fld1 ; NOCMOV-NEXT: fldz -; NOCMOV-NEXT: jne .LBB5_1 -; NOCMOV-NEXT: # %bb.2: # %entry +; NOCMOV-NEXT: jne .LBB5_3 +; NOCMOV-NEXT: # %bb.1: # %entry ; NOCMOV-NEXT: jp .LBB5_5 -; NOCMOV-NEXT: # %bb.3: # %entry +; NOCMOV-NEXT: # %bb.2: # %entry ; NOCMOV-NEXT: fstp %st(1) ; NOCMOV-NEXT: jmp .LBB5_4 -; NOCMOV-NEXT: .LBB5_1: +; NOCMOV-NEXT: .LBB5_3: ; NOCMOV-NEXT: fstp %st(0) ; NOCMOV-NEXT: .LBB5_4: # %entry ; NOCMOV-NEXT: fldz @@ -269,13 +269,13 @@ define dso_local float @test_zext_fcmp_oeq(float %a, float %b) nounwind { ; NOCMOV-NEXT: sahf ; NOCMOV-NEXT: fldz ; NOCMOV-NEXT: fld1 -; NOCMOV-NEXT: jne .LBB6_1 -; NOCMOV-NEXT: # %bb.2: # %entry +; NOCMOV-NEXT: jne .LBB6_3 +; NOCMOV-NEXT: # %bb.1: # %entry ; NOCMOV-NEXT: jp .LBB6_5 -; NOCMOV-NEXT: # %bb.3: # %entry +; NOCMOV-NEXT: # %bb.2: # %entry ; NOCMOV-NEXT: fstp %st(1) ; NOCMOV-NEXT: jmp .LBB6_4 -; NOCMOV-NEXT: .LBB6_1: +; NOCMOV-NEXT: .LBB6_3: ; NOCMOV-NEXT: fstp %st(0) ; NOCMOV-NEXT: .LBB6_4: # %entry ; NOCMOV-NEXT: fldz @@ -329,23 +329,23 @@ define dso_local void @no_cascade_opt(i32 %v0, i32 %v1, i32 %v2, i32 %v3) nounwi ; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: movb $20, %al ; NOCMOV-NEXT: movb $20, %cl -; NOCMOV-NEXT: jge .LBB7_1 -; NOCMOV-NEXT: # %bb.2: # %entry -; NOCMOV-NEXT: jle .LBB7_3 -; NOCMOV-NEXT: .LBB7_4: # %entry +; NOCMOV-NEXT: jge .LBB7_4 +; NOCMOV-NEXT: # %bb.1: # %entry +; NOCMOV-NEXT: jle .LBB7_5 +; NOCMOV-NEXT: .LBB7_2: # %entry ; NOCMOV-NEXT: cmpl $0, {{[0-9]+}}(%esp) -; NOCMOV-NEXT: jne .LBB7_5 -; NOCMOV-NEXT: .LBB7_6: # %entry +; NOCMOV-NEXT: jne .LBB7_6 +; NOCMOV-NEXT: .LBB7_3: # %entry ; NOCMOV-NEXT: movb %al, g8 ; NOCMOV-NEXT: retl -; NOCMOV-NEXT: .LBB7_1: # %entry +; NOCMOV-NEXT: .LBB7_4: # %entry ; NOCMOV-NEXT: movzbl {{[0-9]+}}(%esp), %ecx -; NOCMOV-NEXT: jg .LBB7_4 -; NOCMOV-NEXT: .LBB7_3: # %entry +; NOCMOV-NEXT: jg .LBB7_2 +; NOCMOV-NEXT: .LBB7_5: # %entry ; NOCMOV-NEXT: movl %ecx, %eax ; NOCMOV-NEXT: cmpl $0, {{[0-9]+}}(%esp) -; NOCMOV-NEXT: je .LBB7_6 -; NOCMOV-NEXT: .LBB7_5: # %entry +; NOCMOV-NEXT: je .LBB7_3 +; NOCMOV-NEXT: .LBB7_6: # %entry ; NOCMOV-NEXT: movl %ecx, %eax ; NOCMOV-NEXT: movb %al, g8 ; NOCMOV-NEXT: retl diff --git a/llvm/test/CodeGen/X86/cmp-bool.ll b/llvm/test/CodeGen/X86/cmp-bool.ll index 617b485e0de0f..81d1d6a98363c 100644 --- a/llvm/test/CodeGen/X86/cmp-bool.ll +++ b/llvm/test/CodeGen/X86/cmp-bool.ll @@ -26,10 +26,10 @@ define void @bool_ne(i1 zeroext %a, i1 zeroext %b, ptr nocapture %c) nounwind { ; CHECK-LABEL: bool_ne: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cmpb %sil, %dil -; CHECK-NEXT: je .LBB1_1 -; CHECK-NEXT: # %bb.2: # %if.then +; CHECK-NEXT: je .LBB1_2 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: jmpq *%rdx # TAILCALL -; CHECK-NEXT: .LBB1_1: # %if.end +; CHECK-NEXT: .LBB1_2: # %if.end ; CHECK-NEXT: retq entry: %cmp = xor i1 %a, %b diff --git a/llvm/test/CodeGen/X86/cmp.ll b/llvm/test/CodeGen/X86/cmp.ll index ed3f0e0f0aa71..aefbefdfe03eb 100644 --- a/llvm/test/CodeGen/X86/cmp.ll +++ b/llvm/test/CodeGen/X86/cmp.ll @@ -145,12 +145,12 @@ define i32 @test6() nounwind align 2 { ; CHECK-LABEL: test6: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cmpq $0, -{{[0-9]+}}(%rsp) # encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00] -; CHECK-NEXT: je .LBB6_1 # encoding: [0x74,A] -; CHECK-NEXT: # fixup A - offset: 1, value: .LBB6_1, kind: FK_PCRel_1 -; CHECK-NEXT: # %bb.2: # %F +; CHECK-NEXT: je .LBB6_2 # encoding: [0x74,A] +; CHECK-NEXT: # fixup A - offset: 1, value: .LBB6_2, kind: FK_PCRel_1 +; CHECK-NEXT: # %bb.1: # %F ; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; CHECK-NEXT: retq # encoding: [0xc3] -; CHECK-NEXT: .LBB6_1: # %T +; CHECK-NEXT: .LBB6_2: # %T ; CHECK-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00] ; CHECK-NEXT: retq # encoding: [0xc3] entry: diff --git a/llvm/test/CodeGen/X86/cmpxchg-clobber-flags.ll b/llvm/test/CodeGen/X86/cmpxchg-clobber-flags.ll index 4877d15e44a4f..84efd4a531be0 100644 --- a/llvm/test/CodeGen/X86/cmpxchg-clobber-flags.ll +++ b/llvm/test/CodeGen/X86/cmpxchg-clobber-flags.ll @@ -42,13 +42,13 @@ define i64 @test_intervening_call(ptr %foo, i64 %bar, i64 %baz) nounwind { ; X86-GOOD-RA-NEXT: calll bar@PLT ; X86-GOOD-RA-NEXT: addl $16, %esp ; X86-GOOD-RA-NEXT: testb %bl, %bl -; X86-GOOD-RA-NEXT: jne .LBB0_3 +; X86-GOOD-RA-NEXT: jne .LBB0_2 ; X86-GOOD-RA-NEXT: # %bb.1: # %t ; X86-GOOD-RA-NEXT: movl $42, %eax -; X86-GOOD-RA-NEXT: jmp .LBB0_2 -; X86-GOOD-RA-NEXT: .LBB0_3: # %f +; X86-GOOD-RA-NEXT: jmp .LBB0_3 +; X86-GOOD-RA-NEXT: .LBB0_2: # %f ; X86-GOOD-RA-NEXT: xorl %eax, %eax -; X86-GOOD-RA-NEXT: .LBB0_2: # %t +; X86-GOOD-RA-NEXT: .LBB0_3: # %t ; X86-GOOD-RA-NEXT: xorl %edx, %edx ; X86-GOOD-RA-NEXT: addl $4, %esp ; X86-GOOD-RA-NEXT: popl %esi @@ -73,13 +73,13 @@ define i64 @test_intervening_call(ptr %foo, i64 %bar, i64 %baz) nounwind { ; X86-FAST-RA-NEXT: calll bar@PLT ; X86-FAST-RA-NEXT: addl $16, %esp ; X86-FAST-RA-NEXT: testb %bl, %bl -; X86-FAST-RA-NEXT: jne .LBB0_3 +; X86-FAST-RA-NEXT: jne .LBB0_2 ; X86-FAST-RA-NEXT: # %bb.1: # %t ; X86-FAST-RA-NEXT: movl $42, %eax -; X86-FAST-RA-NEXT: jmp .LBB0_2 -; X86-FAST-RA-NEXT: .LBB0_3: # %f +; X86-FAST-RA-NEXT: jmp .LBB0_3 +; X86-FAST-RA-NEXT: .LBB0_2: # %f ; X86-FAST-RA-NEXT: xorl %eax, %eax -; X86-FAST-RA-NEXT: .LBB0_2: # %t +; X86-FAST-RA-NEXT: .LBB0_3: # %t ; X86-FAST-RA-NEXT: xorl %edx, %edx ; X86-FAST-RA-NEXT: addl $4, %esp ; X86-FAST-RA-NEXT: popl %esi diff --git a/llvm/test/CodeGen/X86/coalesce-esp.ll b/llvm/test/CodeGen/X86/coalesce-esp.ll index 0c495c9cf2b00..f6cc52c7aa650 100644 --- a/llvm/test/CodeGen/X86/coalesce-esp.ll +++ b/llvm/test/CodeGen/X86/coalesce-esp.ll @@ -19,26 +19,26 @@ define void @_ZSt17__gslice_to_indexjRKSt8valarrayIjES2_RS0_(i32 %__o, ptr nocap ; CHECK-NEXT: movl %esp, %eax ; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: testb %cl, %cl -; CHECK-NEXT: je .LBB0_1 -; CHECK-NEXT: # %bb.5: # %return +; CHECK-NEXT: je .LBB0_2 +; CHECK-NEXT: # %bb.1: # %return ; CHECK-NEXT: movl %ebp, %esp ; CHECK-NEXT: popl %ebp ; CHECK-NEXT: retl -; CHECK-NEXT: .LBB0_1: # %bb4.preheader +; CHECK-NEXT: .LBB0_2: # %bb4.preheader ; CHECK-NEXT: xorl %edx, %edx -; CHECK-NEXT: jmp .LBB0_2 +; CHECK-NEXT: jmp .LBB0_4 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_4: # %bb7.backedge -; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 +; CHECK-NEXT: .LBB0_3: # %bb7.backedge +; CHECK-NEXT: # in Loop: Header=BB0_4 Depth=1 ; CHECK-NEXT: addl $-4, %edx -; CHECK-NEXT: .LBB0_2: # %bb4 +; CHECK-NEXT: .LBB0_4: # %bb4 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: testb %cl, %cl -; CHECK-NEXT: jne .LBB0_4 -; CHECK-NEXT: # %bb.3: # %bb5 -; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 +; CHECK-NEXT: jne .LBB0_3 +; CHECK-NEXT: # %bb.5: # %bb5 +; CHECK-NEXT: # in Loop: Header=BB0_4 Depth=1 ; CHECK-NEXT: movl $0, (%eax,%edx) -; CHECK-NEXT: jmp .LBB0_4 +; CHECK-NEXT: jmp .LBB0_3 entry: %0 = alloca i32, i32 undef, align 4 ; [#uses=1] br i1 undef, label %return, label %bb4 diff --git a/llvm/test/CodeGen/X86/coalescer-commute4.ll b/llvm/test/CodeGen/X86/coalescer-commute4.ll index 0ec99dcba88ae..3710bdc406983 100644 --- a/llvm/test/CodeGen/X86/coalescer-commute4.ll +++ b/llvm/test/CodeGen/X86/coalescer-commute4.ll @@ -9,14 +9,14 @@ define float @foo(ptr %x, ptr %y, i32 %c) nounwind { ; CHECK-NEXT: pushl %eax ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: testl %eax, %eax -; CHECK-NEXT: je LBB0_1 -; CHECK-NEXT: ## %bb.2: ## %bb.preheader +; CHECK-NEXT: je LBB0_3 +; CHECK-NEXT: ## %bb.1: ## %bb.preheader ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx ; CHECK-NEXT: xorps %xmm0, %xmm0 ; CHECK-NEXT: xorl %esi, %esi ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: LBB0_3: ## %bb +; CHECK-NEXT: LBB0_2: ## %bb ; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: xorps %xmm1, %xmm1 ; CHECK-NEXT: cvtsi2ssl (%edx,%esi,4), %xmm1 @@ -24,9 +24,9 @@ define float @foo(ptr %x, ptr %y, i32 %c) nounwind { ; CHECK-NEXT: addss %xmm1, %xmm0 ; CHECK-NEXT: incl %esi ; CHECK-NEXT: cmpl %eax, %esi -; CHECK-NEXT: jb LBB0_3 +; CHECK-NEXT: jb LBB0_2 ; CHECK-NEXT: jmp LBB0_4 -; CHECK-NEXT: LBB0_1: +; CHECK-NEXT: LBB0_3: ; CHECK-NEXT: xorps %xmm0, %xmm0 ; CHECK-NEXT: LBB0_4: ## %bb23 ; CHECK-NEXT: movss %xmm0, (%esp) diff --git a/llvm/test/CodeGen/X86/coalescer-dead-flag-verifier-error.ll b/llvm/test/CodeGen/X86/coalescer-dead-flag-verifier-error.ll index a42a715bdc6ab..7b3e45512a213 100644 --- a/llvm/test/CodeGen/X86/coalescer-dead-flag-verifier-error.ll +++ b/llvm/test/CodeGen/X86/coalescer-dead-flag-verifier-error.ll @@ -10,31 +10,31 @@ define void @_ZNK4llvm5APInt21multiplicativeInverseERKS0_(ptr %r) { ; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %ecx, %ecx -; CHECK-NEXT: jmp .LBB0_1 +; CHECK-NEXT: jmp .LBB0_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_4: # %_ZNK4llvm5APInt13getActiveBitsEv.exit.i.i -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: .LBB0_1: # %_ZNK4llvm5APInt13getActiveBitsEv.exit.i.i +; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: movl %edx, %edx ; CHECK-NEXT: shlq $4, %rdx ; CHECK-NEXT: movl $0, (%rdi,%rdx) ; CHECK-NEXT: movl %ecx, %edx -; CHECK-NEXT: .LBB0_1: # %bb +; CHECK-NEXT: .LBB0_2: # %bb ; CHECK-NEXT: # =>This Loop Header: Depth=1 ; CHECK-NEXT: # Child Loop BB0_3 Depth 2 ; CHECK-NEXT: xorl $1, %ecx ; CHECK-NEXT: xorl %esi, %esi ; CHECK-NEXT: movq %rcx, %r8 ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB0_4 +; CHECK-NEXT: jne .LBB0_1 ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .LBB0_3: # %for.body.i.i.i.i.i.3 -; CHECK-NEXT: # Parent Loop BB0_1 Depth=1 +; CHECK-NEXT: # Parent Loop BB0_2 Depth=1 ; CHECK-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-NEXT: orq $1, %r8 ; CHECK-NEXT: orq $1, %rsi ; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: je .LBB0_3 -; CHECK-NEXT: jmp .LBB0_4 +; CHECK-NEXT: jmp .LBB0_1 entry: br label %bb @@ -71,15 +71,15 @@ define void @_ZNK4llvm5APInt21multiplicativeInverseERKS0__assert(ptr %r) { ; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %ecx, %ecx -; CHECK-NEXT: jmp .LBB1_1 +; CHECK-NEXT: jmp .LBB1_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB1_4: # %_ZNK4llvm5APInt13getActiveBitsEv.exit.i.i -; CHECK-NEXT: # in Loop: Header=BB1_1 Depth=1 +; CHECK-NEXT: .LBB1_1: # %_ZNK4llvm5APInt13getActiveBitsEv.exit.i.i +; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1 ; CHECK-NEXT: movl %edx, %edx ; CHECK-NEXT: shlq $4, %rdx ; CHECK-NEXT: movl $0, (%rdi,%rdx) ; CHECK-NEXT: movl %ecx, %edx -; CHECK-NEXT: .LBB1_1: # %bb +; CHECK-NEXT: .LBB1_2: # %bb ; CHECK-NEXT: # =>This Loop Header: Depth=1 ; CHECK-NEXT: # Child Loop BB1_3 Depth 2 ; CHECK-NEXT: xorl $1, %ecx @@ -88,16 +88,16 @@ define void @_ZNK4llvm5APInt21multiplicativeInverseERKS0__assert(ptr %r) { ; CHECK-NEXT: movq (%rsi), %rsi ; CHECK-NEXT: xorl %r8d, %r8d ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB1_4 +; CHECK-NEXT: jne .LBB1_1 ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .LBB1_3: # %for.body.i.i.i.i.i.3 -; CHECK-NEXT: # Parent Loop BB1_1 Depth=1 +; CHECK-NEXT: # Parent Loop BB1_2 Depth=1 ; CHECK-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-NEXT: orq $1, %rsi ; CHECK-NEXT: orq $1, %r8 ; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: je .LBB1_3 -; CHECK-NEXT: jmp .LBB1_4 +; CHECK-NEXT: jmp .LBB1_1 entry: br label %bb diff --git a/llvm/test/CodeGen/X86/coalescer-implicit-def-regression.ll b/llvm/test/CodeGen/X86/coalescer-implicit-def-regression.ll index 66ba54f3e318e..1de247318bfa3 100644 --- a/llvm/test/CodeGen/X86/coalescer-implicit-def-regression.ll +++ b/llvm/test/CodeGen/X86/coalescer-implicit-def-regression.ll @@ -11,26 +11,26 @@ define i1 @_ZN4llvm8LLParser17parseDIEnumeratorERPNS_6MDNodeEb(i32 %arg) { ; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: cmpl $1, %edi -; CHECK-NEXT: je .LBB0_1 -; CHECK-NEXT: # %bb.2: # %entry +; CHECK-NEXT: je .LBB0_5 +; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: testl %edi, %edi -; CHECK-NEXT: jne .LBB0_4 -; CHECK-NEXT: # %bb.3: # %if.end.i.i.preheader +; CHECK-NEXT: jne .LBB0_3 +; CHECK-NEXT: # %bb.2: # %if.end.i.i.preheader ; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: movl $1, %ecx -; CHECK-NEXT: .LBB0_4: # %if.then.i.i +; CHECK-NEXT: .LBB0_3: # %if.then.i.i ; CHECK-NEXT: movb $1, %dl ; CHECK-NEXT: testb %dl, %dl ; CHECK-NEXT: je .LBB0_6 -; CHECK-NEXT: .LBB0_7: # %do.end +; CHECK-NEXT: .LBB0_4: # %do.end ; CHECK-NEXT: movq %rcx, 0 ; CHECK-NEXT: movb %al, 0 ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB0_1: +; CHECK-NEXT: .LBB0_5: ; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: testb %dl, %dl -; CHECK-NEXT: jne .LBB0_7 +; CHECK-NEXT: jne .LBB0_4 ; CHECK-NEXT: .LBB0_6: # %if.then8 ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: retq diff --git a/llvm/test/CodeGen/X86/code-align-loops.ll b/llvm/test/CodeGen/X86/code-align-loops.ll index cd2bac54fee14..49b73809f434c 100644 --- a/llvm/test/CodeGen/X86/code-align-loops.ll +++ b/llvm/test/CodeGen/X86/code-align-loops.ll @@ -1,4 +1,3 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-pc-linux-gnu | FileCheck %s -check-prefixes=CHECK,ALIGN ; RUN: llc < %s -mtriple=x86_64-pc-linux-gnu -align-loops=32 | FileCheck %s -check-prefixes=CHECK,ALIGN32 ; RUN: llc < %s -mtriple=x86_64-pc-linux-gnu -align-loops=256 | FileCheck %s -check-prefixes=CHECK,ALIGN256 @@ -148,7 +147,7 @@ while.end: ; preds = %while.cond ; CHECK-LABEL: test4_multilatch: ; ALIGN: .p2align 6 -; ALIGN-NEXT: .LBB3_4: # %bb4 +; ALIGN-NEXT: .LBB3_1: # %bb4 define void @test4_multilatch(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { entry: br label %bb1 diff --git a/llvm/test/CodeGen/X86/combine-sbb.ll b/llvm/test/CodeGen/X86/combine-sbb.ll index 62744d4f3050a..8d4ab71192408 100644 --- a/llvm/test/CodeGen/X86/combine-sbb.ll +++ b/llvm/test/CodeGen/X86/combine-sbb.ll @@ -199,12 +199,12 @@ define i32 @PR40483_sub3(ptr, i32) nounwind { ; X86-NEXT: subl %esi, %ecx ; X86-NEXT: subl %esi, %edx ; X86-NEXT: movl %edx, (%eax) -; X86-NEXT: jae .LBB5_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: jae .LBB5_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: xorl %eax, %eax ; X86-NEXT: popl %esi ; X86-NEXT: retl -; X86-NEXT: .LBB5_1: +; X86-NEXT: .LBB5_2: ; X86-NEXT: movl %ecx, %eax ; X86-NEXT: negl %eax ; X86-NEXT: orl %ecx, %eax diff --git a/llvm/test/CodeGen/X86/combine-storetomstore.ll b/llvm/test/CodeGen/X86/combine-storetomstore.ll index 45a1172b2323e..979298b5d1937 100644 --- a/llvm/test/CodeGen/X86/combine-storetomstore.ll +++ b/llvm/test/CodeGen/X86/combine-storetomstore.ll @@ -142,11 +142,11 @@ define void @test_masked_store_success_v4f16(<4 x half> %x, ptr %ptr, <4 x i1> % ; AVX-NEXT: cmovnel %ecx, %eax ; AVX-NEXT: vpextrb $8, %xmm1, %ecx ; AVX-NEXT: testb $1, %cl -; AVX-NEXT: jne .LBB4_1 -; AVX-NEXT: # %bb.2: +; AVX-NEXT: jne .LBB4_2 +; AVX-NEXT: # %bb.1: ; AVX-NEXT: movl 4(%rdi), %ecx ; AVX-NEXT: jmp .LBB4_3 -; AVX-NEXT: .LBB4_1: +; AVX-NEXT: .LBB4_2: ; AVX-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3] ; AVX-NEXT: vpextrw $0, %xmm2, %ecx ; AVX-NEXT: .LBB4_3: @@ -156,11 +156,11 @@ define void @test_masked_store_success_v4f16(<4 x half> %x, ptr %ptr, <4 x i1> % ; AVX-NEXT: cmovnel %edx, %esi ; AVX-NEXT: vmovd %xmm1, %edx ; AVX-NEXT: testb $1, %dl -; AVX-NEXT: jne .LBB4_4 -; AVX-NEXT: # %bb.5: +; AVX-NEXT: jne .LBB4_5 +; AVX-NEXT: # %bb.4: ; AVX-NEXT: movl (%rdi), %edx ; AVX-NEXT: jmp .LBB4_6 -; AVX-NEXT: .LBB4_4: +; AVX-NEXT: .LBB4_5: ; AVX-NEXT: vpextrw $0, %xmm0, %edx ; AVX-NEXT: .LBB4_6: ; AVX-NEXT: movw %dx, (%rdi) @@ -181,11 +181,11 @@ define void @test_masked_store_success_v4f16(<4 x half> %x, ptr %ptr, <4 x i1> % ; AVX2-NEXT: cmovnel %ecx, %eax ; AVX2-NEXT: vpextrb $8, %xmm1, %ecx ; AVX2-NEXT: testb $1, %cl -; AVX2-NEXT: jne .LBB4_1 -; AVX2-NEXT: # %bb.2: +; AVX2-NEXT: jne .LBB4_2 +; AVX2-NEXT: # %bb.1: ; AVX2-NEXT: movl 4(%rdi), %ecx ; AVX2-NEXT: jmp .LBB4_3 -; AVX2-NEXT: .LBB4_1: +; AVX2-NEXT: .LBB4_2: ; AVX2-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3] ; AVX2-NEXT: vpextrw $0, %xmm2, %ecx ; AVX2-NEXT: .LBB4_3: @@ -195,11 +195,11 @@ define void @test_masked_store_success_v4f16(<4 x half> %x, ptr %ptr, <4 x i1> % ; AVX2-NEXT: cmovnel %edx, %esi ; AVX2-NEXT: vmovd %xmm1, %edx ; AVX2-NEXT: testb $1, %dl -; AVX2-NEXT: jne .LBB4_4 -; AVX2-NEXT: # %bb.5: +; AVX2-NEXT: jne .LBB4_5 +; AVX2-NEXT: # %bb.4: ; AVX2-NEXT: movl (%rdi), %edx ; AVX2-NEXT: jmp .LBB4_6 -; AVX2-NEXT: .LBB4_4: +; AVX2-NEXT: .LBB4_5: ; AVX2-NEXT: vpextrw $0, %xmm0, %edx ; AVX2-NEXT: .LBB4_6: ; AVX2-NEXT: movw %dx, (%rdi) diff --git a/llvm/test/CodeGen/X86/concat-fpext-v2bf16.ll b/llvm/test/CodeGen/X86/concat-fpext-v2bf16.ll index b3891a61f4574..5c7a8042a3063 100644 --- a/llvm/test/CodeGen/X86/concat-fpext-v2bf16.ll +++ b/llvm/test/CodeGen/X86/concat-fpext-v2bf16.ll @@ -5,10 +5,10 @@ define void @test(<2 x ptr> %ptr) { ; CHECK-LABEL: test: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: je .LBB0_1 -; CHECK-NEXT: # %bb.2: # %loop.127.preheader +; CHECK-NEXT: je .LBB0_2 +; CHECK-NEXT: # %bb.1: # %loop.127.preheader ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB0_1: # %ifmerge.89 +; CHECK-NEXT: .LBB0_2: # %ifmerge.89 ; CHECK-NEXT: vbroadcastss %xmm0, %xmm0 ; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; CHECK-NEXT: vpbroadcastw (%rax), %xmm2 diff --git a/llvm/test/CodeGen/X86/conditional-tailcall.ll b/llvm/test/CodeGen/X86/conditional-tailcall.ll index 2859a87db3d56..b77012dd555f0 100644 --- a/llvm/test/CodeGen/X86/conditional-tailcall.ll +++ b/llvm/test/CodeGen/X86/conditional-tailcall.ll @@ -262,18 +262,18 @@ define zeroext i1 @pr31257(ptr nocapture readonly dereferenceable(8) %s) minsize ; CHECK32-NEXT: .LBB3_1: # %for.cond ; CHECK32-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK32-NEXT: testl %edx, %edx # encoding: [0x85,0xd2] -; CHECK32-NEXT: je .LBB3_14 # encoding: [0x74,A] -; CHECK32-NEXT: # fixup A - offset: 1, value: .LBB3_14, kind: FK_PCRel_1 +; CHECK32-NEXT: je .LBB3_12 # encoding: [0x74,A] +; CHECK32-NEXT: # fixup A - offset: 1, value: .LBB3_12, kind: FK_PCRel_1 ; CHECK32-NEXT: # %bb.2: # %for.body ; CHECK32-NEXT: # in Loop: Header=BB3_1 Depth=1 ; CHECK32-NEXT: cmpl $2, %ebx # encoding: [0x83,0xfb,0x02] -; CHECK32-NEXT: je .LBB3_12 # encoding: [0x74,A] -; CHECK32-NEXT: # fixup A - offset: 1, value: .LBB3_12, kind: FK_PCRel_1 +; CHECK32-NEXT: je .LBB3_10 # encoding: [0x74,A] +; CHECK32-NEXT: # fixup A - offset: 1, value: .LBB3_10, kind: FK_PCRel_1 ; CHECK32-NEXT: # %bb.3: # %for.body ; CHECK32-NEXT: # in Loop: Header=BB3_1 Depth=1 ; CHECK32-NEXT: cmpl $1, %ebx # encoding: [0x83,0xfb,0x01] -; CHECK32-NEXT: je .LBB3_10 # encoding: [0x74,A] -; CHECK32-NEXT: # fixup A - offset: 1, value: .LBB3_10, kind: FK_PCRel_1 +; CHECK32-NEXT: je .LBB3_8 # encoding: [0x74,A] +; CHECK32-NEXT: # fixup A - offset: 1, value: .LBB3_8, kind: FK_PCRel_1 ; CHECK32-NEXT: # %bb.4: # %for.body ; CHECK32-NEXT: # in Loop: Header=BB3_1 Depth=1 ; CHECK32-NEXT: testl %ebx, %ebx # encoding: [0x85,0xdb] @@ -296,46 +296,46 @@ define zeroext i1 @pr31257(ptr nocapture readonly dereferenceable(8) %s) minsize ; CHECK32-NEXT: # in Loop: Header=BB3_1 Depth=1 ; CHECK32-NEXT: addl $-48, %ebp # encoding: [0x83,0xc5,0xd0] ; CHECK32-NEXT: cmpl $10, %ebp # encoding: [0x83,0xfd,0x0a] -; CHECK32-NEXT: jmp .LBB3_8 # encoding: [0xeb,A] -; CHECK32-NEXT: # fixup A - offset: 1, value: .LBB3_8, kind: FK_PCRel_1 -; CHECK32-NEXT: .LBB3_10: # %sw.bb14 +; CHECK32-NEXT: jmp .LBB3_9 # encoding: [0xeb,A] +; CHECK32-NEXT: # fixup A - offset: 1, value: .LBB3_9, kind: FK_PCRel_1 +; CHECK32-NEXT: .LBB3_8: # %sw.bb14 ; CHECK32-NEXT: # in Loop: Header=BB3_1 Depth=1 ; CHECK32-NEXT: movzbl (%eax), %ebx # encoding: [0x0f,0xb6,0x18] ; CHECK32-NEXT: addl $-48, %ebx # encoding: [0x83,0xc3,0xd0] ; CHECK32-NEXT: cmpl $10, %ebx # encoding: [0x83,0xfb,0x0a] -; CHECK32-NEXT: .LBB3_8: # %if.else +; CHECK32-NEXT: .LBB3_9: # %if.else ; CHECK32-NEXT: # in Loop: Header=BB3_1 Depth=1 ; CHECK32-NEXT: movl %esi, %ebx # encoding: [0x89,0xf3] -; CHECK32-NEXT: jae .LBB3_9 # encoding: [0x73,A] -; CHECK32-NEXT: # fixup A - offset: 1, value: .LBB3_9, kind: FK_PCRel_1 +; CHECK32-NEXT: jae .LBB3_13 # encoding: [0x73,A] +; CHECK32-NEXT: # fixup A - offset: 1, value: .LBB3_13, kind: FK_PCRel_1 ; CHECK32-NEXT: jmp .LBB3_11 # encoding: [0xeb,A] ; CHECK32-NEXT: # fixup A - offset: 1, value: .LBB3_11, kind: FK_PCRel_1 -; CHECK32-NEXT: .LBB3_12: # %sw.bb22 +; CHECK32-NEXT: .LBB3_10: # %sw.bb22 ; CHECK32-NEXT: # in Loop: Header=BB3_1 Depth=1 ; CHECK32-NEXT: movzbl (%eax), %ebx # encoding: [0x0f,0xb6,0x18] ; CHECK32-NEXT: addl $-48, %ebx # encoding: [0x83,0xc3,0xd0] ; CHECK32-NEXT: cmpl $10, %ebx # encoding: [0x83,0xfb,0x0a] ; CHECK32-NEXT: movl %esi, %ebx # encoding: [0x89,0xf3] -; CHECK32-NEXT: jae .LBB3_13 # encoding: [0x73,A] -; CHECK32-NEXT: # fixup A - offset: 1, value: .LBB3_13, kind: FK_PCRel_1 +; CHECK32-NEXT: jae .LBB3_16 # encoding: [0x73,A] +; CHECK32-NEXT: # fixup A - offset: 1, value: .LBB3_16, kind: FK_PCRel_1 ; CHECK32-NEXT: .LBB3_11: # %for.inc ; CHECK32-NEXT: # in Loop: Header=BB3_1 Depth=1 ; CHECK32-NEXT: incl %eax # encoding: [0x40] ; CHECK32-NEXT: decl %edx # encoding: [0x4a] ; CHECK32-NEXT: jmp .LBB3_1 # encoding: [0xeb,A] ; CHECK32-NEXT: # fixup A - offset: 1, value: .LBB3_1, kind: FK_PCRel_1 -; CHECK32-NEXT: .LBB3_14: +; CHECK32-NEXT: .LBB3_12: ; CHECK32-NEXT: cmpl $2, %ebx # encoding: [0x83,0xfb,0x02] ; CHECK32-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] -; CHECK32-NEXT: jmp .LBB3_15 # encoding: [0xeb,A] -; CHECK32-NEXT: # fixup A - offset: 1, value: .LBB3_15, kind: FK_PCRel_1 -; CHECK32-NEXT: .LBB3_9: +; CHECK32-NEXT: jmp .LBB3_14 # encoding: [0xeb,A] +; CHECK32-NEXT: # fixup A - offset: 1, value: .LBB3_14, kind: FK_PCRel_1 +; CHECK32-NEXT: .LBB3_13: ; CHECK32-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] -; CHECK32-NEXT: .LBB3_15: # %cleanup.thread +; CHECK32-NEXT: .LBB3_14: # %cleanup.thread ; CHECK32-NEXT: # kill: def $al killed $al killed $eax ; CHECK32-NEXT: addl $12, %esp # encoding: [0x83,0xc4,0x0c] ; CHECK32-NEXT: .cfi_def_cfa_offset 20 -; CHECK32-NEXT: .LBB3_16: # %cleanup.thread +; CHECK32-NEXT: .LBB3_15: # %cleanup.thread ; CHECK32-NEXT: popl %esi # encoding: [0x5e] ; CHECK32-NEXT: .cfi_def_cfa_offset 16 ; CHECK32-NEXT: popl %edi # encoding: [0x5f] @@ -345,7 +345,7 @@ define zeroext i1 @pr31257(ptr nocapture readonly dereferenceable(8) %s) minsize ; CHECK32-NEXT: popl %ebp # encoding: [0x5d] ; CHECK32-NEXT: .cfi_def_cfa_offset 4 ; CHECK32-NEXT: retl # encoding: [0xc3] -; CHECK32-NEXT: .LBB3_13: # %if.else28 +; CHECK32-NEXT: .LBB3_16: # %if.else28 ; CHECK32-NEXT: .cfi_def_cfa_offset 32 ; CHECK32-NEXT: subl $8, %esp # encoding: [0x83,0xec,0x08] ; CHECK32-NEXT: .cfi_adjust_cfa_offset 8 @@ -357,8 +357,8 @@ define zeroext i1 @pr31257(ptr nocapture readonly dereferenceable(8) %s) minsize ; CHECK32-NEXT: # fixup A - offset: 1, value: _Z20isValidIntegerSuffixN9__gnu_cxx17__normal_iteratorIPKcSsEES3_, kind: FK_PCRel_4 ; CHECK32-NEXT: addl $28, %esp # encoding: [0x83,0xc4,0x1c] ; CHECK32-NEXT: .cfi_adjust_cfa_offset -28 -; CHECK32-NEXT: jmp .LBB3_16 # encoding: [0xeb,A] -; CHECK32-NEXT: # fixup A - offset: 1, value: .LBB3_16, kind: FK_PCRel_1 +; CHECK32-NEXT: jmp .LBB3_15 # encoding: [0xeb,A] +; CHECK32-NEXT: # fixup A - offset: 1, value: .LBB3_15, kind: FK_PCRel_1 ; ; CHECK64-LABEL: pr31257: ; CHECK64: # %bb.0: # %entry diff --git a/llvm/test/CodeGen/X86/copy-eflags.ll b/llvm/test/CodeGen/X86/copy-eflags.ll index e1711ccdbe13f..dc224c03a8878 100644 --- a/llvm/test/CodeGen/X86/copy-eflags.ll +++ b/llvm/test/CodeGen/X86/copy-eflags.ll @@ -210,14 +210,14 @@ define dso_local void @PR37100(i8 %arg1, i16 %arg2, i64 %arg3, i8 %arg4, ptr %pt ; X32-NEXT: movl {{[0-9]+}}(%esp), %ebp ; X32-NEXT: movb {{[0-9]+}}(%esp), %ch ; X32-NEXT: movb {{[0-9]+}}(%esp), %cl -; X32-NEXT: jmp .LBB3_1 +; X32-NEXT: jmp .LBB3_2 ; X32-NEXT: .p2align 4 -; X32-NEXT: .LBB3_5: # %bb1 -; X32-NEXT: # in Loop: Header=BB3_1 Depth=1 +; X32-NEXT: .LBB3_1: # %bb1 +; X32-NEXT: # in Loop: Header=BB3_2 Depth=1 ; X32-NEXT: movl %esi, %eax ; X32-NEXT: cltd ; X32-NEXT: idivl %edi -; X32-NEXT: .LBB3_1: # %bb1 +; X32-NEXT: .LBB3_2: # %bb1 ; X32-NEXT: # =>This Inner Loop Header: Depth=1 ; X32-NEXT: movsbl %cl, %eax ; X32-NEXT: movl %eax, %edx @@ -230,20 +230,20 @@ define dso_local void @PR37100(i8 %arg1, i16 %arg2, i64 %arg3, i8 %arg4, ptr %pt ; X32-NEXT: movzbl %dl, %edi ; X32-NEXT: negl %edi ; X32-NEXT: testb %al, %al -; X32-NEXT: jne .LBB3_3 -; X32-NEXT: # %bb.2: # %bb1 -; X32-NEXT: # in Loop: Header=BB3_1 Depth=1 +; X32-NEXT: jne .LBB3_4 +; X32-NEXT: # %bb.3: # %bb1 +; X32-NEXT: # in Loop: Header=BB3_2 Depth=1 ; X32-NEXT: movb %ch, %cl -; X32-NEXT: .LBB3_3: # %bb1 -; X32-NEXT: # in Loop: Header=BB3_1 Depth=1 +; X32-NEXT: .LBB3_4: # %bb1 +; X32-NEXT: # in Loop: Header=BB3_2 Depth=1 ; X32-NEXT: movb %cl, (%ebp) ; X32-NEXT: movl (%ebx), %edx ; X32-NEXT: testb %al, %al -; X32-NEXT: jne .LBB3_5 -; X32-NEXT: # %bb.4: # %bb1 -; X32-NEXT: # in Loop: Header=BB3_1 Depth=1 +; X32-NEXT: jne .LBB3_1 +; X32-NEXT: # %bb.5: # %bb1 +; X32-NEXT: # in Loop: Header=BB3_2 Depth=1 ; X32-NEXT: movl %edx, %edi -; X32-NEXT: jmp .LBB3_5 +; X32-NEXT: jmp .LBB3_1 ; ; X64-LABEL: PR37100: ; X64: # %bb.0: # %bb diff --git a/llvm/test/CodeGen/X86/ctlo.ll b/llvm/test/CodeGen/X86/ctlo.ll index c5aa2a9f40239..a03301e948eac 100644 --- a/llvm/test/CodeGen/X86/ctlo.ll +++ b/llvm/test/CodeGen/X86/ctlo.ll @@ -17,14 +17,14 @@ define i8 @ctlo_i8(i8 %x) { ; X86-NOCMOV: # %bb.0: ; X86-NOCMOV-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X86-NOCMOV-NEXT: xorb $-1, %al -; X86-NOCMOV-NEXT: je .LBB0_1 -; X86-NOCMOV-NEXT: # %bb.2: # %cond.false +; X86-NOCMOV-NEXT: je .LBB0_2 +; X86-NOCMOV-NEXT: # %bb.1: # %cond.false ; X86-NOCMOV-NEXT: movzbl %al, %eax ; X86-NOCMOV-NEXT: bsrl %eax, %eax ; X86-NOCMOV-NEXT: xorl $7, %eax ; X86-NOCMOV-NEXT: # kill: def $al killed $al killed $eax ; X86-NOCMOV-NEXT: retl -; X86-NOCMOV-NEXT: .LBB0_1: +; X86-NOCMOV-NEXT: .LBB0_2: ; X86-NOCMOV-NEXT: movb $8, %al ; X86-NOCMOV-NEXT: # kill: def $al killed $al killed $eax ; X86-NOCMOV-NEXT: retl @@ -120,13 +120,13 @@ define i16 @ctlo_i16(i16 %x) { ; X86-NOCMOV: # %bb.0: ; X86-NOCMOV-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-NOCMOV-NEXT: xorw $-1, %ax -; X86-NOCMOV-NEXT: je .LBB2_1 -; X86-NOCMOV-NEXT: # %bb.2: # %cond.false +; X86-NOCMOV-NEXT: je .LBB2_2 +; X86-NOCMOV-NEXT: # %bb.1: # %cond.false ; X86-NOCMOV-NEXT: bsrw %ax, %ax ; X86-NOCMOV-NEXT: xorl $15, %eax ; X86-NOCMOV-NEXT: # kill: def $ax killed $ax killed $eax ; X86-NOCMOV-NEXT: retl -; X86-NOCMOV-NEXT: .LBB2_1: +; X86-NOCMOV-NEXT: .LBB2_2: ; X86-NOCMOV-NEXT: movw $16, %ax ; X86-NOCMOV-NEXT: # kill: def $ax killed $ax killed $eax ; X86-NOCMOV-NEXT: retl @@ -208,12 +208,12 @@ define i32 @ctlo_i32(i32 %x) { ; X86-NOCMOV: # %bb.0: ; X86-NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NOCMOV-NEXT: xorl $-1, %eax -; X86-NOCMOV-NEXT: je .LBB4_1 -; X86-NOCMOV-NEXT: # %bb.2: # %cond.false +; X86-NOCMOV-NEXT: je .LBB4_2 +; X86-NOCMOV-NEXT: # %bb.1: # %cond.false ; X86-NOCMOV-NEXT: bsrl %eax, %eax ; X86-NOCMOV-NEXT: xorl $31, %eax ; X86-NOCMOV-NEXT: retl -; X86-NOCMOV-NEXT: .LBB4_1: +; X86-NOCMOV-NEXT: .LBB4_2: ; X86-NOCMOV-NEXT: movl $32, %eax ; X86-NOCMOV-NEXT: retl ; @@ -294,21 +294,21 @@ define i64 @ctlo_i64(i64 %x) nounwind { ; X86-NOCMOV-NEXT: notl %eax ; X86-NOCMOV-NEXT: movl %eax, %edx ; X86-NOCMOV-NEXT: orl %ecx, %edx -; X86-NOCMOV-NEXT: je .LBB6_1 -; X86-NOCMOV-NEXT: # %bb.2: # %cond.false +; X86-NOCMOV-NEXT: je .LBB6_3 +; X86-NOCMOV-NEXT: # %bb.1: # %cond.false ; X86-NOCMOV-NEXT: testl %ecx, %ecx -; X86-NOCMOV-NEXT: jne .LBB6_3 -; X86-NOCMOV-NEXT: # %bb.4: # %cond.false +; X86-NOCMOV-NEXT: jne .LBB6_4 +; X86-NOCMOV-NEXT: # %bb.2: # %cond.false ; X86-NOCMOV-NEXT: bsrl %eax, %eax ; X86-NOCMOV-NEXT: xorl $31, %eax ; X86-NOCMOV-NEXT: orl $32, %eax ; X86-NOCMOV-NEXT: xorl %edx, %edx ; X86-NOCMOV-NEXT: retl -; X86-NOCMOV-NEXT: .LBB6_1: +; X86-NOCMOV-NEXT: .LBB6_3: ; X86-NOCMOV-NEXT: movl $64, %eax ; X86-NOCMOV-NEXT: xorl %edx, %edx ; X86-NOCMOV-NEXT: retl -; X86-NOCMOV-NEXT: .LBB6_3: +; X86-NOCMOV-NEXT: .LBB6_4: ; X86-NOCMOV-NEXT: bsrl %ecx, %eax ; X86-NOCMOV-NEXT: xorl $31, %eax ; X86-NOCMOV-NEXT: xorl %edx, %edx @@ -345,15 +345,15 @@ define i64 @ctlo_i64(i64 %x) nounwind { ; X86-CLZ-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-CLZ-NEXT: notl %eax ; X86-CLZ-NEXT: testl %eax, %eax -; X86-CLZ-NEXT: jne .LBB6_1 -; X86-CLZ-NEXT: # %bb.2: +; X86-CLZ-NEXT: jne .LBB6_2 +; X86-CLZ-NEXT: # %bb.1: ; X86-CLZ-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-CLZ-NEXT: notl %eax ; X86-CLZ-NEXT: lzcntl %eax, %eax ; X86-CLZ-NEXT: addl $32, %eax ; X86-CLZ-NEXT: xorl %edx, %edx ; X86-CLZ-NEXT: retl -; X86-CLZ-NEXT: .LBB6_1: +; X86-CLZ-NEXT: .LBB6_2: ; X86-CLZ-NEXT: lzcntl %eax, %eax ; X86-CLZ-NEXT: xorl %edx, %edx ; X86-CLZ-NEXT: retl @@ -374,8 +374,8 @@ define i64 @ctlo_i64_undef(i64 %x) { ; X86-NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NOCMOV-NEXT: notl %eax ; X86-NOCMOV-NEXT: testl %eax, %eax -; X86-NOCMOV-NEXT: jne .LBB7_1 -; X86-NOCMOV-NEXT: # %bb.2: +; X86-NOCMOV-NEXT: jne .LBB7_2 +; X86-NOCMOV-NEXT: # %bb.1: ; X86-NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NOCMOV-NEXT: notl %eax ; X86-NOCMOV-NEXT: bsrl %eax, %eax @@ -383,7 +383,7 @@ define i64 @ctlo_i64_undef(i64 %x) { ; X86-NOCMOV-NEXT: orl $32, %eax ; X86-NOCMOV-NEXT: xorl %edx, %edx ; X86-NOCMOV-NEXT: retl -; X86-NOCMOV-NEXT: .LBB7_1: +; X86-NOCMOV-NEXT: .LBB7_2: ; X86-NOCMOV-NEXT: bsrl %eax, %eax ; X86-NOCMOV-NEXT: xorl $31, %eax ; X86-NOCMOV-NEXT: xorl %edx, %edx @@ -417,15 +417,15 @@ define i64 @ctlo_i64_undef(i64 %x) { ; X86-CLZ-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-CLZ-NEXT: notl %eax ; X86-CLZ-NEXT: testl %eax, %eax -; X86-CLZ-NEXT: jne .LBB7_1 -; X86-CLZ-NEXT: # %bb.2: +; X86-CLZ-NEXT: jne .LBB7_2 +; X86-CLZ-NEXT: # %bb.1: ; X86-CLZ-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-CLZ-NEXT: notl %eax ; X86-CLZ-NEXT: lzcntl %eax, %eax ; X86-CLZ-NEXT: addl $32, %eax ; X86-CLZ-NEXT: xorl %edx, %edx ; X86-CLZ-NEXT: retl -; X86-CLZ-NEXT: .LBB7_1: +; X86-CLZ-NEXT: .LBB7_2: ; X86-CLZ-NEXT: lzcntl %eax, %eax ; X86-CLZ-NEXT: xorl %edx, %edx ; X86-CLZ-NEXT: retl diff --git a/llvm/test/CodeGen/X86/ctlz.ll b/llvm/test/CodeGen/X86/ctlz.ll index 789c681174efb..db8b12ef9fafd 100644 --- a/llvm/test/CodeGen/X86/ctlz.ll +++ b/llvm/test/CodeGen/X86/ctlz.ll @@ -141,14 +141,14 @@ define i64 @ctlz_i64(i64 %x) { ; X86-NOCMOV: # %bb.0: ; X86-NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NOCMOV-NEXT: testl %eax, %eax -; X86-NOCMOV-NEXT: jne .LBB3_1 -; X86-NOCMOV-NEXT: # %bb.2: +; X86-NOCMOV-NEXT: jne .LBB3_2 +; X86-NOCMOV-NEXT: # %bb.1: ; X86-NOCMOV-NEXT: bsrl {{[0-9]+}}(%esp), %eax ; X86-NOCMOV-NEXT: xorl $31, %eax ; X86-NOCMOV-NEXT: orl $32, %eax ; X86-NOCMOV-NEXT: xorl %edx, %edx ; X86-NOCMOV-NEXT: retl -; X86-NOCMOV-NEXT: .LBB3_1: +; X86-NOCMOV-NEXT: .LBB3_2: ; X86-NOCMOV-NEXT: bsrl %eax, %eax ; X86-NOCMOV-NEXT: xorl $31, %eax ; X86-NOCMOV-NEXT: xorl %edx, %edx @@ -177,13 +177,13 @@ define i64 @ctlz_i64(i64 %x) { ; X86-CLZ: # %bb.0: ; X86-CLZ-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-CLZ-NEXT: testl %eax, %eax -; X86-CLZ-NEXT: jne .LBB3_1 -; X86-CLZ-NEXT: # %bb.2: +; X86-CLZ-NEXT: jne .LBB3_2 +; X86-CLZ-NEXT: # %bb.1: ; X86-CLZ-NEXT: lzcntl {{[0-9]+}}(%esp), %eax ; X86-CLZ-NEXT: addl $32, %eax ; X86-CLZ-NEXT: xorl %edx, %edx ; X86-CLZ-NEXT: retl -; X86-CLZ-NEXT: .LBB3_1: +; X86-CLZ-NEXT: .LBB3_2: ; X86-CLZ-NEXT: lzcntl %eax, %eax ; X86-CLZ-NEXT: xorl %edx, %edx ; X86-CLZ-NEXT: retl @@ -202,13 +202,13 @@ define i64 @ctlz_i64(i64 %x) { ; X86-FASTLZCNT: # %bb.0: ; X86-FASTLZCNT-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-FASTLZCNT-NEXT: testl %eax, %eax -; X86-FASTLZCNT-NEXT: jne .LBB3_1 -; X86-FASTLZCNT-NEXT: # %bb.2: +; X86-FASTLZCNT-NEXT: jne .LBB3_2 +; X86-FASTLZCNT-NEXT: # %bb.1: ; X86-FASTLZCNT-NEXT: lzcntl {{[0-9]+}}(%esp), %eax ; X86-FASTLZCNT-NEXT: addl $32, %eax ; X86-FASTLZCNT-NEXT: xorl %edx, %edx ; X86-FASTLZCNT-NEXT: retl -; X86-FASTLZCNT-NEXT: .LBB3_1: +; X86-FASTLZCNT-NEXT: .LBB3_2: ; X86-FASTLZCNT-NEXT: lzcntl %eax, %eax ; X86-FASTLZCNT-NEXT: xorl %edx, %edx ; X86-FASTLZCNT-NEXT: retl @@ -222,14 +222,14 @@ define i8 @ctlz_i8_zero_test(i8 %n) { ; X86-NOCMOV: # %bb.0: ; X86-NOCMOV-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X86-NOCMOV-NEXT: testb %al, %al -; X86-NOCMOV-NEXT: je .LBB4_1 -; X86-NOCMOV-NEXT: # %bb.2: # %cond.false +; X86-NOCMOV-NEXT: je .LBB4_2 +; X86-NOCMOV-NEXT: # %bb.1: # %cond.false ; X86-NOCMOV-NEXT: movzbl %al, %eax ; X86-NOCMOV-NEXT: bsrl %eax, %eax ; X86-NOCMOV-NEXT: xorl $7, %eax ; X86-NOCMOV-NEXT: # kill: def $al killed $al killed $eax ; X86-NOCMOV-NEXT: retl -; X86-NOCMOV-NEXT: .LBB4_1: +; X86-NOCMOV-NEXT: .LBB4_2: ; X86-NOCMOV-NEXT: movb $8, %al ; X86-NOCMOV-NEXT: # kill: def $al killed $al killed $eax ; X86-NOCMOV-NEXT: retl @@ -294,13 +294,13 @@ define i16 @ctlz_i16_zero_test(i16 %n) { ; X86-NOCMOV: # %bb.0: ; X86-NOCMOV-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-NOCMOV-NEXT: testw %ax, %ax -; X86-NOCMOV-NEXT: je .LBB5_1 -; X86-NOCMOV-NEXT: # %bb.2: # %cond.false +; X86-NOCMOV-NEXT: je .LBB5_2 +; X86-NOCMOV-NEXT: # %bb.1: # %cond.false ; X86-NOCMOV-NEXT: bsrw %ax, %ax ; X86-NOCMOV-NEXT: xorl $15, %eax ; X86-NOCMOV-NEXT: # kill: def $ax killed $ax killed $eax ; X86-NOCMOV-NEXT: retl -; X86-NOCMOV-NEXT: .LBB5_1: +; X86-NOCMOV-NEXT: .LBB5_2: ; X86-NOCMOV-NEXT: movw $16, %ax ; X86-NOCMOV-NEXT: # kill: def $ax killed $ax killed $eax ; X86-NOCMOV-NEXT: retl @@ -351,12 +351,12 @@ define i32 @ctlz_i32_zero_test(i32 %n) { ; X86-NOCMOV: # %bb.0: ; X86-NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NOCMOV-NEXT: testl %eax, %eax -; X86-NOCMOV-NEXT: je .LBB6_1 -; X86-NOCMOV-NEXT: # %bb.2: # %cond.false +; X86-NOCMOV-NEXT: je .LBB6_2 +; X86-NOCMOV-NEXT: # %bb.1: # %cond.false ; X86-NOCMOV-NEXT: bsrl %eax, %eax ; X86-NOCMOV-NEXT: xorl $31, %eax ; X86-NOCMOV-NEXT: retl -; X86-NOCMOV-NEXT: .LBB6_1: +; X86-NOCMOV-NEXT: .LBB6_2: ; X86-NOCMOV-NEXT: movl $32, %eax ; X86-NOCMOV-NEXT: retl ; @@ -406,21 +406,21 @@ define i64 @ctlz_i64_zero_test(i64 %n) nounwind { ; X86-NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NOCMOV-NEXT: movl %ecx, %edx ; X86-NOCMOV-NEXT: orl %eax, %edx -; X86-NOCMOV-NEXT: je .LBB7_1 -; X86-NOCMOV-NEXT: # %bb.2: # %cond.false +; X86-NOCMOV-NEXT: je .LBB7_3 +; X86-NOCMOV-NEXT: # %bb.1: # %cond.false ; X86-NOCMOV-NEXT: testl %eax, %eax -; X86-NOCMOV-NEXT: jne .LBB7_3 -; X86-NOCMOV-NEXT: # %bb.4: # %cond.false +; X86-NOCMOV-NEXT: jne .LBB7_4 +; X86-NOCMOV-NEXT: # %bb.2: # %cond.false ; X86-NOCMOV-NEXT: bsrl %ecx, %eax ; X86-NOCMOV-NEXT: xorl $31, %eax ; X86-NOCMOV-NEXT: orl $32, %eax ; X86-NOCMOV-NEXT: xorl %edx, %edx ; X86-NOCMOV-NEXT: retl -; X86-NOCMOV-NEXT: .LBB7_1: +; X86-NOCMOV-NEXT: .LBB7_3: ; X86-NOCMOV-NEXT: movl $64, %eax ; X86-NOCMOV-NEXT: xorl %edx, %edx ; X86-NOCMOV-NEXT: retl -; X86-NOCMOV-NEXT: .LBB7_3: +; X86-NOCMOV-NEXT: .LBB7_4: ; X86-NOCMOV-NEXT: bsrl %eax, %eax ; X86-NOCMOV-NEXT: xorl $31, %eax ; X86-NOCMOV-NEXT: xorl %edx, %edx @@ -452,13 +452,13 @@ define i64 @ctlz_i64_zero_test(i64 %n) nounwind { ; X86-CLZ: # %bb.0: ; X86-CLZ-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-CLZ-NEXT: testl %eax, %eax -; X86-CLZ-NEXT: jne .LBB7_1 -; X86-CLZ-NEXT: # %bb.2: +; X86-CLZ-NEXT: jne .LBB7_2 +; X86-CLZ-NEXT: # %bb.1: ; X86-CLZ-NEXT: lzcntl {{[0-9]+}}(%esp), %eax ; X86-CLZ-NEXT: addl $32, %eax ; X86-CLZ-NEXT: xorl %edx, %edx ; X86-CLZ-NEXT: retl -; X86-CLZ-NEXT: .LBB7_1: +; X86-CLZ-NEXT: .LBB7_2: ; X86-CLZ-NEXT: lzcntl %eax, %eax ; X86-CLZ-NEXT: xorl %edx, %edx ; X86-CLZ-NEXT: retl @@ -477,13 +477,13 @@ define i64 @ctlz_i64_zero_test(i64 %n) nounwind { ; X86-FASTLZCNT: # %bb.0: ; X86-FASTLZCNT-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-FASTLZCNT-NEXT: testl %eax, %eax -; X86-FASTLZCNT-NEXT: jne .LBB7_1 -; X86-FASTLZCNT-NEXT: # %bb.2: +; X86-FASTLZCNT-NEXT: jne .LBB7_2 +; X86-FASTLZCNT-NEXT: # %bb.1: ; X86-FASTLZCNT-NEXT: lzcntl {{[0-9]+}}(%esp), %eax ; X86-FASTLZCNT-NEXT: addl $32, %eax ; X86-FASTLZCNT-NEXT: xorl %edx, %edx ; X86-FASTLZCNT-NEXT: retl -; X86-FASTLZCNT-NEXT: .LBB7_1: +; X86-FASTLZCNT-NEXT: .LBB7_2: ; X86-FASTLZCNT-NEXT: lzcntl %eax, %eax ; X86-FASTLZCNT-NEXT: xorl %edx, %edx ; X86-FASTLZCNT-NEXT: retl @@ -593,13 +593,13 @@ define i32 @ctlz_bsr_zero_test(i32 %n) { ; X86-NOCMOV: # %bb.0: ; X86-NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NOCMOV-NEXT: testl %eax, %eax -; X86-NOCMOV-NEXT: je .LBB10_1 -; X86-NOCMOV-NEXT: # %bb.2: # %cond.false +; X86-NOCMOV-NEXT: je .LBB10_2 +; X86-NOCMOV-NEXT: # %bb.1: # %cond.false ; X86-NOCMOV-NEXT: bsrl %eax, %eax ; X86-NOCMOV-NEXT: xorl $31, %eax ; X86-NOCMOV-NEXT: xorl $31, %eax ; X86-NOCMOV-NEXT: retl -; X86-NOCMOV-NEXT: .LBB10_1: +; X86-NOCMOV-NEXT: .LBB10_2: ; X86-NOCMOV-NEXT: movl $32, %eax ; X86-NOCMOV-NEXT: xorl $31, %eax ; X86-NOCMOV-NEXT: retl @@ -716,8 +716,8 @@ define i64 @ctlz_i64_zero_test_knownneverzero(i64 %n) { ; X86-NOCMOV: # %bb.0: ; X86-NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NOCMOV-NEXT: testl %eax, %eax -; X86-NOCMOV-NEXT: jne .LBB12_1 -; X86-NOCMOV-NEXT: # %bb.2: +; X86-NOCMOV-NEXT: jne .LBB12_2 +; X86-NOCMOV-NEXT: # %bb.1: ; X86-NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NOCMOV-NEXT: orl $1, %eax ; X86-NOCMOV-NEXT: bsrl %eax, %eax @@ -725,7 +725,7 @@ define i64 @ctlz_i64_zero_test_knownneverzero(i64 %n) { ; X86-NOCMOV-NEXT: orl $32, %eax ; X86-NOCMOV-NEXT: xorl %edx, %edx ; X86-NOCMOV-NEXT: retl -; X86-NOCMOV-NEXT: .LBB12_1: +; X86-NOCMOV-NEXT: .LBB12_2: ; X86-NOCMOV-NEXT: bsrl %eax, %eax ; X86-NOCMOV-NEXT: xorl $31, %eax ; X86-NOCMOV-NEXT: xorl %edx, %edx @@ -757,15 +757,15 @@ define i64 @ctlz_i64_zero_test_knownneverzero(i64 %n) { ; X86-CLZ: # %bb.0: ; X86-CLZ-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-CLZ-NEXT: testl %eax, %eax -; X86-CLZ-NEXT: jne .LBB12_1 -; X86-CLZ-NEXT: # %bb.2: +; X86-CLZ-NEXT: jne .LBB12_2 +; X86-CLZ-NEXT: # %bb.1: ; X86-CLZ-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-CLZ-NEXT: orl $1, %eax ; X86-CLZ-NEXT: lzcntl %eax, %eax ; X86-CLZ-NEXT: orl $32, %eax ; X86-CLZ-NEXT: xorl %edx, %edx ; X86-CLZ-NEXT: retl -; X86-CLZ-NEXT: .LBB12_1: +; X86-CLZ-NEXT: .LBB12_2: ; X86-CLZ-NEXT: lzcntl %eax, %eax ; X86-CLZ-NEXT: xorl %edx, %edx ; X86-CLZ-NEXT: retl @@ -786,15 +786,15 @@ define i64 @ctlz_i64_zero_test_knownneverzero(i64 %n) { ; X86-FASTLZCNT: # %bb.0: ; X86-FASTLZCNT-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-FASTLZCNT-NEXT: testl %eax, %eax -; X86-FASTLZCNT-NEXT: jne .LBB12_1 -; X86-FASTLZCNT-NEXT: # %bb.2: +; X86-FASTLZCNT-NEXT: jne .LBB12_2 +; X86-FASTLZCNT-NEXT: # %bb.1: ; X86-FASTLZCNT-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-FASTLZCNT-NEXT: orl $1, %eax ; X86-FASTLZCNT-NEXT: lzcntl %eax, %eax ; X86-FASTLZCNT-NEXT: orl $32, %eax ; X86-FASTLZCNT-NEXT: xorl %edx, %edx ; X86-FASTLZCNT-NEXT: retl -; X86-FASTLZCNT-NEXT: .LBB12_1: +; X86-FASTLZCNT-NEXT: .LBB12_2: ; X86-FASTLZCNT-NEXT: lzcntl %eax, %eax ; X86-FASTLZCNT-NEXT: xorl %edx, %edx ; X86-FASTLZCNT-NEXT: retl @@ -957,15 +957,15 @@ define i8 @ctlz_xor7_i8_false(i8 %x) { ; X86-NOCMOV: # %bb.0: ; X86-NOCMOV-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X86-NOCMOV-NEXT: testb %al, %al -; X86-NOCMOV-NEXT: je .LBB16_1 -; X86-NOCMOV-NEXT: # %bb.2: # %cond.false +; X86-NOCMOV-NEXT: je .LBB16_2 +; X86-NOCMOV-NEXT: # %bb.1: # %cond.false ; X86-NOCMOV-NEXT: movzbl %al, %eax ; X86-NOCMOV-NEXT: bsrl %eax, %eax ; X86-NOCMOV-NEXT: xorl $7, %eax ; X86-NOCMOV-NEXT: xorb $7, %al ; X86-NOCMOV-NEXT: # kill: def $al killed $al killed $eax ; X86-NOCMOV-NEXT: retl -; X86-NOCMOV-NEXT: .LBB16_1: +; X86-NOCMOV-NEXT: .LBB16_2: ; X86-NOCMOV-NEXT: movb $8, %al ; X86-NOCMOV-NEXT: xorb $7, %al ; X86-NOCMOV-NEXT: # kill: def $al killed $al killed $eax @@ -1072,13 +1072,13 @@ define i32 @ctlz_xor31_i32_false(i32 %x) { ; X86-NOCMOV: # %bb.0: ; X86-NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NOCMOV-NEXT: testl %eax, %eax -; X86-NOCMOV-NEXT: je .LBB18_1 -; X86-NOCMOV-NEXT: # %bb.2: # %cond.false +; X86-NOCMOV-NEXT: je .LBB18_2 +; X86-NOCMOV-NEXT: # %bb.1: # %cond.false ; X86-NOCMOV-NEXT: bsrl %eax, %eax ; X86-NOCMOV-NEXT: xorl $31, %eax ; X86-NOCMOV-NEXT: xorl $31, %eax ; X86-NOCMOV-NEXT: retl -; X86-NOCMOV-NEXT: .LBB18_1: +; X86-NOCMOV-NEXT: .LBB18_2: ; X86-NOCMOV-NEXT: movl $32, %eax ; X86-NOCMOV-NEXT: xorl $31, %eax ; X86-NOCMOV-NEXT: retl @@ -1129,13 +1129,13 @@ define i64 @ctlz_xor63_i64_true(i64 %x) { ; X86-NOCMOV: # %bb.0: ; X86-NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NOCMOV-NEXT: testl %eax, %eax -; X86-NOCMOV-NEXT: jne .LBB19_1 -; X86-NOCMOV-NEXT: # %bb.2: +; X86-NOCMOV-NEXT: jne .LBB19_2 +; X86-NOCMOV-NEXT: # %bb.1: ; X86-NOCMOV-NEXT: bsrl {{[0-9]+}}(%esp), %eax ; X86-NOCMOV-NEXT: xorl $31, %eax ; X86-NOCMOV-NEXT: orl $32, %eax ; X86-NOCMOV-NEXT: jmp .LBB19_3 -; X86-NOCMOV-NEXT: .LBB19_1: +; X86-NOCMOV-NEXT: .LBB19_2: ; X86-NOCMOV-NEXT: bsrl %eax, %eax ; X86-NOCMOV-NEXT: xorl $31, %eax ; X86-NOCMOV-NEXT: .LBB19_3: @@ -1166,12 +1166,12 @@ define i64 @ctlz_xor63_i64_true(i64 %x) { ; X86-CLZ: # %bb.0: ; X86-CLZ-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-CLZ-NEXT: testl %eax, %eax -; X86-CLZ-NEXT: jne .LBB19_1 -; X86-CLZ-NEXT: # %bb.2: +; X86-CLZ-NEXT: jne .LBB19_2 +; X86-CLZ-NEXT: # %bb.1: ; X86-CLZ-NEXT: lzcntl {{[0-9]+}}(%esp), %eax ; X86-CLZ-NEXT: addl $32, %eax ; X86-CLZ-NEXT: jmp .LBB19_3 -; X86-CLZ-NEXT: .LBB19_1: +; X86-CLZ-NEXT: .LBB19_2: ; X86-CLZ-NEXT: lzcntl %eax, %eax ; X86-CLZ-NEXT: .LBB19_3: ; X86-CLZ-NEXT: xorl $63, %eax @@ -1193,12 +1193,12 @@ define i64 @ctlz_xor63_i64_true(i64 %x) { ; X86-FASTLZCNT: # %bb.0: ; X86-FASTLZCNT-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-FASTLZCNT-NEXT: testl %eax, %eax -; X86-FASTLZCNT-NEXT: jne .LBB19_1 -; X86-FASTLZCNT-NEXT: # %bb.2: +; X86-FASTLZCNT-NEXT: jne .LBB19_2 +; X86-FASTLZCNT-NEXT: # %bb.1: ; X86-FASTLZCNT-NEXT: lzcntl {{[0-9]+}}(%esp), %eax ; X86-FASTLZCNT-NEXT: addl $32, %eax ; X86-FASTLZCNT-NEXT: jmp .LBB19_3 -; X86-FASTLZCNT-NEXT: .LBB19_1: +; X86-FASTLZCNT-NEXT: .LBB19_2: ; X86-FASTLZCNT-NEXT: lzcntl %eax, %eax ; X86-FASTLZCNT-NEXT: .LBB19_3: ; X86-FASTLZCNT-NEXT: xorl $63, %eax @@ -1214,12 +1214,12 @@ define i64 @ctlz_i32_sext(i32 %x) { ; X86-NOCMOV: # %bb.0: ; X86-NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NOCMOV-NEXT: testl %eax, %eax -; X86-NOCMOV-NEXT: je .LBB20_1 -; X86-NOCMOV-NEXT: # %bb.2: # %cond.false +; X86-NOCMOV-NEXT: je .LBB20_2 +; X86-NOCMOV-NEXT: # %bb.1: # %cond.false ; X86-NOCMOV-NEXT: bsrl %eax, %eax ; X86-NOCMOV-NEXT: xorl $31, %eax ; X86-NOCMOV-NEXT: jmp .LBB20_3 -; X86-NOCMOV-NEXT: .LBB20_1: +; X86-NOCMOV-NEXT: .LBB20_2: ; X86-NOCMOV-NEXT: movl $32, %eax ; X86-NOCMOV-NEXT: .LBB20_3: # %cond.end ; X86-NOCMOV-NEXT: xorl $31, %eax @@ -1276,12 +1276,12 @@ define i64 @ctlz_i32_zext(i32 %x) { ; X86-NOCMOV: # %bb.0: ; X86-NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NOCMOV-NEXT: testl %eax, %eax -; X86-NOCMOV-NEXT: je .LBB21_1 -; X86-NOCMOV-NEXT: # %bb.2: # %cond.false +; X86-NOCMOV-NEXT: je .LBB21_2 +; X86-NOCMOV-NEXT: # %bb.1: # %cond.false ; X86-NOCMOV-NEXT: bsrl %eax, %eax ; X86-NOCMOV-NEXT: xorl $31, %eax ; X86-NOCMOV-NEXT: jmp .LBB21_3 -; X86-NOCMOV-NEXT: .LBB21_1: +; X86-NOCMOV-NEXT: .LBB21_2: ; X86-NOCMOV-NEXT: movl $32, %eax ; X86-NOCMOV-NEXT: .LBB21_3: # %cond.end ; X86-NOCMOV-NEXT: xorl $31, %eax diff --git a/llvm/test/CodeGen/X86/cttz.ll b/llvm/test/CodeGen/X86/cttz.ll index a88fb96dd7c8c..f32adaff34f23 100644 --- a/llvm/test/CodeGen/X86/cttz.ll +++ b/llvm/test/CodeGen/X86/cttz.ll @@ -131,13 +131,13 @@ define i64 @cttz_i64(i64 %x) { ; X86-NOCMOV: # %bb.0: ; X86-NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NOCMOV-NEXT: testl %eax, %eax -; X86-NOCMOV-NEXT: jne .LBB3_1 -; X86-NOCMOV-NEXT: # %bb.2: +; X86-NOCMOV-NEXT: jne .LBB3_2 +; X86-NOCMOV-NEXT: # %bb.1: ; X86-NOCMOV-NEXT: rep bsfl {{[0-9]+}}(%esp), %eax ; X86-NOCMOV-NEXT: addl $32, %eax ; X86-NOCMOV-NEXT: xorl %edx, %edx ; X86-NOCMOV-NEXT: retl -; X86-NOCMOV-NEXT: .LBB3_1: +; X86-NOCMOV-NEXT: .LBB3_2: ; X86-NOCMOV-NEXT: rep bsfl %eax, %eax ; X86-NOCMOV-NEXT: xorl %edx, %edx ; X86-NOCMOV-NEXT: retl @@ -162,13 +162,13 @@ define i64 @cttz_i64(i64 %x) { ; X86-CLZ: # %bb.0: ; X86-CLZ-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-CLZ-NEXT: testl %eax, %eax -; X86-CLZ-NEXT: jne .LBB3_1 -; X86-CLZ-NEXT: # %bb.2: +; X86-CLZ-NEXT: jne .LBB3_2 +; X86-CLZ-NEXT: # %bb.1: ; X86-CLZ-NEXT: tzcntl {{[0-9]+}}(%esp), %eax ; X86-CLZ-NEXT: addl $32, %eax ; X86-CLZ-NEXT: xorl %edx, %edx ; X86-CLZ-NEXT: retl -; X86-CLZ-NEXT: .LBB3_1: +; X86-CLZ-NEXT: .LBB3_2: ; X86-CLZ-NEXT: tzcntl %eax, %eax ; X86-CLZ-NEXT: xorl %edx, %edx ; X86-CLZ-NEXT: retl @@ -187,13 +187,13 @@ define i64 @cttz_i64(i64 %x) { ; X86-FASTLZCNT: # %bb.0: ; X86-FASTLZCNT-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-FASTLZCNT-NEXT: testl %eax, %eax -; X86-FASTLZCNT-NEXT: jne .LBB3_1 -; X86-FASTLZCNT-NEXT: # %bb.2: +; X86-FASTLZCNT-NEXT: jne .LBB3_2 +; X86-FASTLZCNT-NEXT: # %bb.1: ; X86-FASTLZCNT-NEXT: tzcntl {{[0-9]+}}(%esp), %eax ; X86-FASTLZCNT-NEXT: addl $32, %eax ; X86-FASTLZCNT-NEXT: xorl %edx, %edx ; X86-FASTLZCNT-NEXT: retl -; X86-FASTLZCNT-NEXT: .LBB3_1: +; X86-FASTLZCNT-NEXT: .LBB3_2: ; X86-FASTLZCNT-NEXT: tzcntl %eax, %eax ; X86-FASTLZCNT-NEXT: xorl %edx, %edx ; X86-FASTLZCNT-NEXT: retl @@ -307,11 +307,11 @@ define i32 @cttz_i32_zero_test(i32 %n) { ; X86-NOCMOV: # %bb.0: ; X86-NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NOCMOV-NEXT: testl %eax, %eax -; X86-NOCMOV-NEXT: je .LBB6_1 -; X86-NOCMOV-NEXT: # %bb.2: # %cond.false +; X86-NOCMOV-NEXT: je .LBB6_2 +; X86-NOCMOV-NEXT: # %bb.1: # %cond.false ; X86-NOCMOV-NEXT: rep bsfl %eax, %eax ; X86-NOCMOV-NEXT: retl -; X86-NOCMOV-NEXT: .LBB6_1: +; X86-NOCMOV-NEXT: .LBB6_2: ; X86-NOCMOV-NEXT: movl $32, %eax ; X86-NOCMOV-NEXT: retl ; @@ -359,20 +359,20 @@ define i64 @cttz_i64_zero_test(i64 %n) nounwind { ; X86-NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NOCMOV-NEXT: movl %ecx, %edx ; X86-NOCMOV-NEXT: orl %eax, %edx -; X86-NOCMOV-NEXT: je .LBB7_1 -; X86-NOCMOV-NEXT: # %bb.2: # %cond.false +; X86-NOCMOV-NEXT: je .LBB7_3 +; X86-NOCMOV-NEXT: # %bb.1: # %cond.false ; X86-NOCMOV-NEXT: testl %ecx, %ecx -; X86-NOCMOV-NEXT: jne .LBB7_3 -; X86-NOCMOV-NEXT: # %bb.4: # %cond.false +; X86-NOCMOV-NEXT: jne .LBB7_4 +; X86-NOCMOV-NEXT: # %bb.2: # %cond.false ; X86-NOCMOV-NEXT: rep bsfl %eax, %eax ; X86-NOCMOV-NEXT: addl $32, %eax ; X86-NOCMOV-NEXT: xorl %edx, %edx ; X86-NOCMOV-NEXT: retl -; X86-NOCMOV-NEXT: .LBB7_1: +; X86-NOCMOV-NEXT: .LBB7_3: ; X86-NOCMOV-NEXT: movl $64, %eax ; X86-NOCMOV-NEXT: xorl %edx, %edx ; X86-NOCMOV-NEXT: retl -; X86-NOCMOV-NEXT: .LBB7_3: +; X86-NOCMOV-NEXT: .LBB7_4: ; X86-NOCMOV-NEXT: rep bsfl %ecx, %eax ; X86-NOCMOV-NEXT: xorl %edx, %edx ; X86-NOCMOV-NEXT: retl @@ -399,13 +399,13 @@ define i64 @cttz_i64_zero_test(i64 %n) nounwind { ; X86-CLZ: # %bb.0: ; X86-CLZ-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-CLZ-NEXT: testl %eax, %eax -; X86-CLZ-NEXT: jne .LBB7_1 -; X86-CLZ-NEXT: # %bb.2: +; X86-CLZ-NEXT: jne .LBB7_2 +; X86-CLZ-NEXT: # %bb.1: ; X86-CLZ-NEXT: tzcntl {{[0-9]+}}(%esp), %eax ; X86-CLZ-NEXT: addl $32, %eax ; X86-CLZ-NEXT: xorl %edx, %edx ; X86-CLZ-NEXT: retl -; X86-CLZ-NEXT: .LBB7_1: +; X86-CLZ-NEXT: .LBB7_2: ; X86-CLZ-NEXT: tzcntl %eax, %eax ; X86-CLZ-NEXT: xorl %edx, %edx ; X86-CLZ-NEXT: retl @@ -424,13 +424,13 @@ define i64 @cttz_i64_zero_test(i64 %n) nounwind { ; X86-FASTLZCNT: # %bb.0: ; X86-FASTLZCNT-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-FASTLZCNT-NEXT: testl %eax, %eax -; X86-FASTLZCNT-NEXT: jne .LBB7_1 -; X86-FASTLZCNT-NEXT: # %bb.2: +; X86-FASTLZCNT-NEXT: jne .LBB7_2 +; X86-FASTLZCNT-NEXT: # %bb.1: ; X86-FASTLZCNT-NEXT: tzcntl {{[0-9]+}}(%esp), %eax ; X86-FASTLZCNT-NEXT: addl $32, %eax ; X86-FASTLZCNT-NEXT: xorl %edx, %edx ; X86-FASTLZCNT-NEXT: retl -; X86-FASTLZCNT-NEXT: .LBB7_1: +; X86-FASTLZCNT-NEXT: .LBB7_2: ; X86-FASTLZCNT-NEXT: tzcntl %eax, %eax ; X86-FASTLZCNT-NEXT: xorl %edx, %edx ; X86-FASTLZCNT-NEXT: retl @@ -502,15 +502,15 @@ define i64 @cttz_i64_zero_test_knownneverzero(i64 %n) { ; X86-NOCMOV: # %bb.0: ; X86-NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NOCMOV-NEXT: testl %eax, %eax -; X86-NOCMOV-NEXT: jne .LBB9_1 -; X86-NOCMOV-NEXT: # %bb.2: +; X86-NOCMOV-NEXT: jne .LBB9_2 +; X86-NOCMOV-NEXT: # %bb.1: ; X86-NOCMOV-NEXT: movl $-2147483648, %eax # imm = 0x80000000 ; X86-NOCMOV-NEXT: orl {{[0-9]+}}(%esp), %eax ; X86-NOCMOV-NEXT: rep bsfl %eax, %eax ; X86-NOCMOV-NEXT: orl $32, %eax ; X86-NOCMOV-NEXT: xorl %edx, %edx ; X86-NOCMOV-NEXT: retl -; X86-NOCMOV-NEXT: .LBB9_1: +; X86-NOCMOV-NEXT: .LBB9_2: ; X86-NOCMOV-NEXT: rep bsfl %eax, %eax ; X86-NOCMOV-NEXT: xorl %edx, %edx ; X86-NOCMOV-NEXT: retl @@ -539,15 +539,15 @@ define i64 @cttz_i64_zero_test_knownneverzero(i64 %n) { ; X86-CLZ: # %bb.0: ; X86-CLZ-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-CLZ-NEXT: testl %eax, %eax -; X86-CLZ-NEXT: jne .LBB9_1 -; X86-CLZ-NEXT: # %bb.2: +; X86-CLZ-NEXT: jne .LBB9_2 +; X86-CLZ-NEXT: # %bb.1: ; X86-CLZ-NEXT: movl $-2147483648, %eax # imm = 0x80000000 ; X86-CLZ-NEXT: orl {{[0-9]+}}(%esp), %eax ; X86-CLZ-NEXT: tzcntl %eax, %eax ; X86-CLZ-NEXT: orl $32, %eax ; X86-CLZ-NEXT: xorl %edx, %edx ; X86-CLZ-NEXT: retl -; X86-CLZ-NEXT: .LBB9_1: +; X86-CLZ-NEXT: .LBB9_2: ; X86-CLZ-NEXT: tzcntl %eax, %eax ; X86-CLZ-NEXT: xorl %edx, %edx ; X86-CLZ-NEXT: retl @@ -570,15 +570,15 @@ define i64 @cttz_i64_zero_test_knownneverzero(i64 %n) { ; X86-FASTLZCNT: # %bb.0: ; X86-FASTLZCNT-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-FASTLZCNT-NEXT: testl %eax, %eax -; X86-FASTLZCNT-NEXT: jne .LBB9_1 -; X86-FASTLZCNT-NEXT: # %bb.2: +; X86-FASTLZCNT-NEXT: jne .LBB9_2 +; X86-FASTLZCNT-NEXT: # %bb.1: ; X86-FASTLZCNT-NEXT: movl $-2147483648, %eax # imm = 0x80000000 ; X86-FASTLZCNT-NEXT: orl {{[0-9]+}}(%esp), %eax ; X86-FASTLZCNT-NEXT: tzcntl %eax, %eax ; X86-FASTLZCNT-NEXT: orl $32, %eax ; X86-FASTLZCNT-NEXT: xorl %edx, %edx ; X86-FASTLZCNT-NEXT: retl -; X86-FASTLZCNT-NEXT: .LBB9_1: +; X86-FASTLZCNT-NEXT: .LBB9_2: ; X86-FASTLZCNT-NEXT: tzcntl %eax, %eax ; X86-FASTLZCNT-NEXT: xorl %edx, %edx ; X86-FASTLZCNT-NEXT: retl @@ -660,12 +660,12 @@ define i64 @cttz_i32_sext(i32 %x) { ; X86-NOCMOV: # %bb.0: ; X86-NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NOCMOV-NEXT: testl %eax, %eax -; X86-NOCMOV-NEXT: je .LBB12_1 -; X86-NOCMOV-NEXT: # %bb.2: # %cond.false +; X86-NOCMOV-NEXT: je .LBB12_2 +; X86-NOCMOV-NEXT: # %bb.1: # %cond.false ; X86-NOCMOV-NEXT: rep bsfl %eax, %eax ; X86-NOCMOV-NEXT: xorl %edx, %edx ; X86-NOCMOV-NEXT: retl -; X86-NOCMOV-NEXT: .LBB12_1: +; X86-NOCMOV-NEXT: .LBB12_2: ; X86-NOCMOV-NEXT: movl $32, %eax ; X86-NOCMOV-NEXT: xorl %edx, %edx ; X86-NOCMOV-NEXT: retl @@ -715,12 +715,12 @@ define i64 @cttz_i32_zext(i32 %x) { ; X86-NOCMOV: # %bb.0: ; X86-NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NOCMOV-NEXT: testl %eax, %eax -; X86-NOCMOV-NEXT: je .LBB13_1 -; X86-NOCMOV-NEXT: # %bb.2: # %cond.false +; X86-NOCMOV-NEXT: je .LBB13_2 +; X86-NOCMOV-NEXT: # %bb.1: # %cond.false ; X86-NOCMOV-NEXT: rep bsfl %eax, %eax ; X86-NOCMOV-NEXT: xorl %edx, %edx ; X86-NOCMOV-NEXT: retl -; X86-NOCMOV-NEXT: .LBB13_1: +; X86-NOCMOV-NEXT: .LBB13_2: ; X86-NOCMOV-NEXT: movl $32, %eax ; X86-NOCMOV-NEXT: xorl %edx, %edx ; X86-NOCMOV-NEXT: retl diff --git a/llvm/test/CodeGen/X86/dag-update-nodetomatch.ll b/llvm/test/CodeGen/X86/dag-update-nodetomatch.ll index 71ad598abe683..c8c6e4413b6a1 100644 --- a/llvm/test/CodeGen/X86/dag-update-nodetomatch.ll +++ b/llvm/test/CodeGen/X86/dag-update-nodetomatch.ll @@ -105,7 +105,7 @@ define void @_Z2x6v() local_unnamed_addr { ; CHECK-NEXT: movq x3@GOTPCREL(%rip), %rcx ; CHECK-NEXT: movl (%rcx), %ecx ; CHECK-NEXT: testl %ecx, %ecx -; CHECK-NEXT: je .LBB1_18 +; CHECK-NEXT: je .LBB1_17 ; CHECK-NEXT: # %bb.1: # %for.cond1thread-pre-split.lr.ph ; CHECK-NEXT: pushq %rbp ; CHECK-NEXT: .cfi_def_cfa_offset 16 @@ -141,26 +141,26 @@ define void @_Z2x6v() local_unnamed_addr { ; CHECK-NEXT: xorl %r15d, %r15d ; CHECK-NEXT: movq x0@GOTPCREL(%rip), %r12 ; CHECK-NEXT: movq %rsi, %r13 -; CHECK-NEXT: jmp .LBB1_2 +; CHECK-NEXT: jmp .LBB1_4 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB1_15: # %for.cond1.for.inc3_crit_edge -; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1 +; CHECK-NEXT: .LBB1_2: # %for.cond1.for.inc3_crit_edge +; CHECK-NEXT: # in Loop: Header=BB1_4 Depth=1 ; CHECK-NEXT: movl %r9d, (%r8) -; CHECK-NEXT: .LBB1_16: # %for.inc3 -; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1 +; CHECK-NEXT: .LBB1_3: # %for.inc3 +; CHECK-NEXT: # in Loop: Header=BB1_4 Depth=1 ; CHECK-NEXT: addq %r14, %r13 ; CHECK-NEXT: incq %r15 ; CHECK-NEXT: addq %r14, %rbx ; CHECK-NEXT: incl %ecx -; CHECK-NEXT: je .LBB1_17 -; CHECK-NEXT: .LBB1_2: # %for.cond1thread-pre-split +; CHECK-NEXT: je .LBB1_16 +; CHECK-NEXT: .LBB1_4: # %for.cond1thread-pre-split ; CHECK-NEXT: # =>This Loop Header: Depth=1 -; CHECK-NEXT: # Child Loop BB1_12 Depth 2 -; CHECK-NEXT: # Child Loop BB1_14 Depth 2 +; CHECK-NEXT: # Child Loop BB1_13 Depth 2 +; CHECK-NEXT: # Child Loop BB1_15 Depth 2 ; CHECK-NEXT: testl %r9d, %r9d -; CHECK-NEXT: jns .LBB1_16 -; CHECK-NEXT: # %bb.3: # %for.body2.preheader -; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1 +; CHECK-NEXT: jns .LBB1_3 +; CHECK-NEXT: # %bb.5: # %for.body2.preheader +; CHECK-NEXT: # in Loop: Header=BB1_4 Depth=1 ; CHECK-NEXT: movslq %r9d, %r9 ; CHECK-NEXT: testq %r9, %r9 ; CHECK-NEXT: movq $-1, %rbp @@ -168,14 +168,14 @@ define void @_Z2x6v() local_unnamed_addr { ; CHECK-NEXT: subq %r9, %rbp ; CHECK-NEXT: incq %rbp ; CHECK-NEXT: cmpq $4, %rbp -; CHECK-NEXT: jb .LBB1_14 -; CHECK-NEXT: # %bb.4: # %min.iters.checked -; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1 +; CHECK-NEXT: jb .LBB1_15 +; CHECK-NEXT: # %bb.6: # %min.iters.checked +; CHECK-NEXT: # in Loop: Header=BB1_4 Depth=1 ; CHECK-NEXT: movq %rbp, %rdx ; CHECK-NEXT: andq $-4, %rdx -; CHECK-NEXT: je .LBB1_14 -; CHECK-NEXT: # %bb.5: # %vector.memcheck -; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1 +; CHECK-NEXT: je .LBB1_15 +; CHECK-NEXT: # %bb.7: # %vector.memcheck +; CHECK-NEXT: # in Loop: Header=BB1_4 Depth=1 ; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload ; CHECK-NEXT: imulq %r15, %rax ; CHECK-NEXT: leaq (%rsi,%rax), %r11 @@ -184,35 +184,35 @@ define void @_Z2x6v() local_unnamed_addr { ; CHECK-NEXT: movq $-1, %r11 ; CHECK-NEXT: cmovnsq %r9, %r11 ; CHECK-NEXT: cmpq %r12, %r10 -; CHECK-NEXT: jae .LBB1_7 -; CHECK-NEXT: # %bb.6: # %vector.memcheck -; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1 +; CHECK-NEXT: jae .LBB1_9 +; CHECK-NEXT: # %bb.8: # %vector.memcheck +; CHECK-NEXT: # in Loop: Header=BB1_4 Depth=1 ; CHECK-NEXT: leaq 8(%rsi), %r10 ; CHECK-NEXT: addq %r10, %rax ; CHECK-NEXT: leaq (%rax,%r11,8), %rax ; CHECK-NEXT: cmpq %r12, %rax -; CHECK-NEXT: ja .LBB1_14 -; CHECK-NEXT: .LBB1_7: # %vector.body.preheader -; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1 +; CHECK-NEXT: ja .LBB1_15 +; CHECK-NEXT: .LBB1_9: # %vector.body.preheader +; CHECK-NEXT: # in Loop: Header=BB1_4 Depth=1 ; CHECK-NEXT: leaq -4(%rdx), %rax ; CHECK-NEXT: btl $2, %eax -; CHECK-NEXT: jb .LBB1_8 -; CHECK-NEXT: # %bb.9: # %vector.body.prol.preheader -; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1 +; CHECK-NEXT: jb .LBB1_11 +; CHECK-NEXT: # %bb.10: # %vector.body.prol.preheader +; CHECK-NEXT: # in Loop: Header=BB1_4 Depth=1 ; CHECK-NEXT: movq {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1] ; CHECK-NEXT: movdqu %xmm0, (%r13,%r9,8) ; CHECK-NEXT: movdqu %xmm0, 16(%r13,%r9,8) ; CHECK-NEXT: movl $4, %r11d ; CHECK-NEXT: shrq $2, %rax -; CHECK-NEXT: jne .LBB1_11 -; CHECK-NEXT: jmp .LBB1_13 -; CHECK-NEXT: .LBB1_8: # in Loop: Header=BB1_2 Depth=1 +; CHECK-NEXT: jne .LBB1_12 +; CHECK-NEXT: jmp .LBB1_14 +; CHECK-NEXT: .LBB1_11: # in Loop: Header=BB1_4 Depth=1 ; CHECK-NEXT: xorl %r11d, %r11d ; CHECK-NEXT: shrq $2, %rax -; CHECK-NEXT: je .LBB1_13 -; CHECK-NEXT: .LBB1_11: # %vector.body.preheader.new -; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1 +; CHECK-NEXT: je .LBB1_14 +; CHECK-NEXT: .LBB1_12: # %vector.body.preheader.new +; CHECK-NEXT: # in Loop: Header=BB1_4 Depth=1 ; CHECK-NEXT: movq {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1] ; CHECK-NEXT: movq %r11, %rax @@ -220,8 +220,8 @@ define void @_Z2x6v() local_unnamed_addr { ; CHECK-NEXT: addq %r9, %r11 ; CHECK-NEXT: leaq (%rbx,%r11,8), %r11 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB1_12: # %vector.body -; CHECK-NEXT: # Parent Loop BB1_2 Depth=1 +; CHECK-NEXT: .LBB1_13: # %vector.body +; CHECK-NEXT: # Parent Loop BB1_4 Depth=1 ; CHECK-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-NEXT: movdqu %xmm0, -32(%r11) ; CHECK-NEXT: movdqu %xmm0, -16(%r11) @@ -229,22 +229,22 @@ define void @_Z2x6v() local_unnamed_addr { ; CHECK-NEXT: movdqu %xmm0, 16(%r11) ; CHECK-NEXT: addq $64, %r11 ; CHECK-NEXT: addq $8, %rax -; CHECK-NEXT: jne .LBB1_12 -; CHECK-NEXT: .LBB1_13: # %middle.block -; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1 +; CHECK-NEXT: jne .LBB1_13 +; CHECK-NEXT: .LBB1_14: # %middle.block +; CHECK-NEXT: # in Loop: Header=BB1_4 Depth=1 ; CHECK-NEXT: addq %rdx, %r9 ; CHECK-NEXT: cmpq %rdx, %rbp -; CHECK-NEXT: je .LBB1_15 +; CHECK-NEXT: je .LBB1_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB1_14: # %for.body2 -; CHECK-NEXT: # Parent Loop BB1_2 Depth=1 +; CHECK-NEXT: .LBB1_15: # %for.body2 +; CHECK-NEXT: # Parent Loop BB1_4 Depth=1 ; CHECK-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-NEXT: movq (%r12), %rax ; CHECK-NEXT: movq %rax, (%r13,%r9,8) ; CHECK-NEXT: incq %r9 -; CHECK-NEXT: jl .LBB1_14 -; CHECK-NEXT: jmp .LBB1_15 -; CHECK-NEXT: .LBB1_17: # %for.cond.for.end5_crit_edge +; CHECK-NEXT: jl .LBB1_15 +; CHECK-NEXT: jmp .LBB1_2 +; CHECK-NEXT: .LBB1_16: # %for.cond.for.end5_crit_edge ; CHECK-NEXT: movq x5@GOTPCREL(%rip), %rax ; CHECK-NEXT: movq %rdi, (%rax) ; CHECK-NEXT: movq x3@GOTPCREL(%rip), %rax @@ -267,7 +267,7 @@ define void @_Z2x6v() local_unnamed_addr { ; CHECK-NEXT: .cfi_restore %r14 ; CHECK-NEXT: .cfi_restore %r15 ; CHECK-NEXT: .cfi_restore %rbp -; CHECK-NEXT: .LBB1_18: # %for.end5 +; CHECK-NEXT: .LBB1_17: # %for.end5 ; CHECK-NEXT: retq entry: %0 = load i32, ptr @x1, align 4 diff --git a/llvm/test/CodeGen/X86/dagcombine-select.ll b/llvm/test/CodeGen/X86/dagcombine-select.ll index 1380c02663ee0..25ce4980db1a8 100644 --- a/llvm/test/CodeGen/X86/dagcombine-select.ll +++ b/llvm/test/CodeGen/X86/dagcombine-select.ll @@ -277,11 +277,11 @@ define double @fsub_constant_sel_constants(i1 %cond) { ; CHECK-LABEL: fsub_constant_sel_constants: ; CHECK: # %bb.0: ; CHECK-NEXT: testb $1, %dil -; CHECK-NEXT: jne .LBB20_1 -; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: jne .LBB20_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: movsd {{.*#+}} xmm0 = [-1.8200000000000003E+1,0.0E+0] ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB20_1: +; CHECK-NEXT: .LBB20_2: ; CHECK-NEXT: movsd {{.*#+}} xmm0 = [9.0999999999999996E+0,0.0E+0] ; CHECK-NEXT: retq %sel = select i1 %cond, double -4.0, double 23.3 @@ -293,11 +293,11 @@ define double @fdiv_constant_sel_constants(i1 %cond) { ; CHECK-LABEL: fdiv_constant_sel_constants: ; CHECK: # %bb.0: ; CHECK-NEXT: testb $1, %dil -; CHECK-NEXT: jne .LBB21_1 -; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: jne .LBB21_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: movsd {{.*#+}} xmm0 = [2.188841201716738E-1,0.0E+0] ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB21_1: +; CHECK-NEXT: .LBB21_2: ; CHECK-NEXT: movsd {{.*#+}} xmm0 = [-1.2749999999999999E+0,0.0E+0] ; CHECK-NEXT: retq %sel = select i1 %cond, double -4.0, double 23.3 @@ -309,11 +309,11 @@ define double @frem_constant_sel_constants(i1 %cond) { ; CHECK-LABEL: frem_constant_sel_constants: ; CHECK: # %bb.0: ; CHECK-NEXT: testb $1, %dil -; CHECK-NEXT: jne .LBB22_1 -; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: jne .LBB22_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: movsd {{.*#+}} xmm0 = [5.0999999999999996E+0,0.0E+0] ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB22_1: +; CHECK-NEXT: .LBB22_2: ; CHECK-NEXT: movsd {{.*#+}} xmm0 = [1.0999999999999996E+0,0.0E+0] ; CHECK-NEXT: retq %sel = select i1 %cond, double -4.0, double 23.3 diff --git a/llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll b/llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll index 00f2e012c8b12..8ae30c8d66bbd 100644 --- a/llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll +++ b/llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll @@ -258,8 +258,8 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: jne .LBB4_1 -; X86-NEXT: # %bb.2: # %select.false.sink +; X86-NEXT: jne .LBB4_9 +; X86-NEXT: # %bb.1: # %select.false.sink ; X86-NEXT: movl $127, %ecx ; X86-NEXT: cmpl %eax, %ecx ; X86-NEXT: movl $0, %ecx @@ -269,7 +269,7 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: movl $0, %ecx ; X86-NEXT: sbbl %edi, %ecx ; X86-NEXT: setb %cl -; X86-NEXT: .LBB4_3: # %select.end +; X86-NEXT: .LBB4_2: # %select.end ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload ; X86-NEXT: xorl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload ; X86-NEXT: testb %cl, %cl @@ -282,8 +282,8 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload ; X86-NEXT: cmovnel %edi, %esi ; X86-NEXT: cmovel {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Folded Reload -; X86-NEXT: jne .LBB4_4 -; X86-NEXT: # %bb.10: # %select.end +; X86-NEXT: jne .LBB4_11 +; X86-NEXT: # %bb.3: # %select.end ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NEXT: xorl $127, %eax ; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload @@ -291,8 +291,8 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload ; X86-NEXT: orl %eax, %ecx ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload -; X86-NEXT: je .LBB4_11 -; X86-NEXT: # %bb.8: # %udiv-bb1 +; X86-NEXT: je .LBB4_8 +; X86-NEXT: # %bb.4: # %udiv-bb1 ; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) @@ -328,7 +328,7 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill -; X86-NEXT: jb .LBB4_9 +; X86-NEXT: jb .LBB4_10 ; X86-NEXT: # %bb.5: # %udiv-preheader ; X86-NEXT: movl %ebx, %ecx ; X86-NEXT: movaps %xmm0, {{[0-9]+}}(%esp) @@ -457,7 +457,7 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: leal (%edi,%edx,2), %ebx ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload ; X86-NEXT: movl %eax, %edi -; X86-NEXT: .LBB4_11: # %udiv-end +; X86-NEXT: .LBB4_8: # %udiv-end ; X86-NEXT: xorl %edx, %edi ; X86-NEXT: xorl %edx, %esi ; X86-NEXT: xorl %edx, %ecx @@ -543,16 +543,16 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: popl %ebx ; X86-NEXT: popl %ebp ; X86-NEXT: retl $4 -; X86-NEXT: .LBB4_1: -; X86-NEXT: movb $1, %cl -; X86-NEXT: jmp .LBB4_3 ; X86-NEXT: .LBB4_9: +; X86-NEXT: movb $1, %cl +; X86-NEXT: jmp .LBB4_2 +; X86-NEXT: .LBB4_10: ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; X86-NEXT: jmp .LBB4_7 -; X86-NEXT: .LBB4_4: +; X86-NEXT: .LBB4_11: ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload -; X86-NEXT: jmp .LBB4_11 +; X86-NEXT: jmp .LBB4_8 ; ; X64-LABEL: scalar_i128: ; X64: # %bb.0: diff --git a/llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll b/llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll index 3d756f3cf2141..4209c2703e5fb 100644 --- a/llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll +++ b/llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll @@ -223,8 +223,8 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: jne .LBB4_1 -; X86-NEXT: # %bb.2: # %select.false.sink +; X86-NEXT: jne .LBB4_9 +; X86-NEXT: # %bb.1: # %select.false.sink ; X86-NEXT: movl $127, %eax ; X86-NEXT: cmpl %edx, %eax ; X86-NEXT: movl $0, %eax @@ -234,7 +234,7 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: movl $0, %eax ; X86-NEXT: sbbl %edi, %eax ; X86-NEXT: setb %al -; X86-NEXT: .LBB4_3: # %select.end +; X86-NEXT: .LBB4_2: # %select.end ; X86-NEXT: testb %al, %al ; X86-NEXT: movl 28(%ebp), %edx ; X86-NEXT: cmovnel %ecx, %edx @@ -245,8 +245,8 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: cmovnel %ecx, %edi ; X86-NEXT: movl 36(%ebp), %ebx ; X86-NEXT: cmovnel %ecx, %ebx -; X86-NEXT: jne .LBB4_9 -; X86-NEXT: # %bb.4: # %select.end +; X86-NEXT: jne .LBB4_8 +; X86-NEXT: # %bb.3: # %select.end ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload ; X86-NEXT: movl %esi, %eax ; X86-NEXT: xorl $127, %eax @@ -255,8 +255,8 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload ; X86-NEXT: orl %eax, %ecx ; X86-NEXT: movl 28(%ebp), %ecx -; X86-NEXT: je .LBB4_9 -; X86-NEXT: # %bb.5: # %udiv-bb1 +; X86-NEXT: je .LBB4_8 +; X86-NEXT: # %bb.4: # %udiv-bb1 ; X86-NEXT: movl 24(%ebp), %edi ; X86-NEXT: movl %edi, {{[0-9]+}}(%esp) ; X86-NEXT: xorps %xmm0, %xmm0 @@ -290,7 +290,7 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; X86-NEXT: jb .LBB4_10 -; X86-NEXT: # %bb.6: # %udiv-preheader +; X86-NEXT: # %bb.5: # %udiv-preheader ; X86-NEXT: movaps %xmm0, {{[0-9]+}}(%esp) ; X86-NEXT: movl 24(%ebp), %eax ; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) @@ -339,7 +339,7 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload ; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; X86-NEXT: .p2align 4 -; X86-NEXT: .LBB4_7: # %udiv-do-while +; X86-NEXT: .LBB4_6: # %udiv-do-while ; X86-NEXT: # =>This Inner Loop Header: Depth=1 ; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload @@ -410,8 +410,8 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: orl %eax, %edx ; X86-NEXT: orl %ecx, %edx ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload -; X86-NEXT: jne .LBB4_7 -; X86-NEXT: .LBB4_8: # %udiv-loop-exit +; X86-NEXT: jne .LBB4_6 +; X86-NEXT: .LBB4_7: # %udiv-loop-exit ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NEXT: shldl $1, %ecx, %eax ; X86-NEXT: shldl $1, %ebx, %ecx @@ -423,7 +423,7 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: movl %ecx, %edi ; X86-NEXT: movl %ebx, %edx ; X86-NEXT: movl %eax, %ebx -; X86-NEXT: .LBB4_9: # %udiv-end +; X86-NEXT: .LBB4_8: # %udiv-end ; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl 56(%ebp), %eax ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload @@ -501,13 +501,13 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: popl %ebx ; X86-NEXT: popl %ebp ; X86-NEXT: retl $4 -; X86-NEXT: .LBB4_1: +; X86-NEXT: .LBB4_9: ; X86-NEXT: movb $1, %al -; X86-NEXT: jmp .LBB4_3 +; X86-NEXT: jmp .LBB4_2 ; X86-NEXT: .LBB4_10: ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill -; X86-NEXT: jmp .LBB4_8 +; X86-NEXT: jmp .LBB4_7 ; ; X64-LABEL: scalar_i128: ; X64: # %bb.0: diff --git a/llvm/test/CodeGen/X86/dup-cost.ll b/llvm/test/CodeGen/X86/dup-cost.ll index ec9d36aa2a11b..131591f4039e6 100644 --- a/llvm/test/CodeGen/X86/dup-cost.ll +++ b/llvm/test/CodeGen/X86/dup-cost.ll @@ -6,20 +6,20 @@ define i32 @cold(i32 %a, ptr %p, ptr %q) !prof !21 { ; CHECK-LABEL: cold: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cmpl $2, %edi -; CHECK-NEXT: jl .LBB0_2 +; CHECK-NEXT: jl .LBB0_4 ; CHECK-NEXT: # %bb.1: # %true1 ; CHECK-NEXT: movl (%rsi), %eax ; CHECK-NEXT: addl $2, %eax -; CHECK-NEXT: .LBB0_3: # %dup +; CHECK-NEXT: .LBB0_2: # %dup ; CHECK-NEXT: cmpl $5, %eax ; CHECK-NEXT: jl .LBB0_5 -; CHECK-NEXT: # %bb.4: # %true2 +; CHECK-NEXT: # %bb.3: # %true2 ; CHECK-NEXT: xorl %edi, %eax ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB0_2: # %false1 +; CHECK-NEXT: .LBB0_4: # %false1 ; CHECK-NEXT: movl (%rdx), %eax ; CHECK-NEXT: addl $-3, %eax -; CHECK-NEXT: jmp .LBB0_3 +; CHECK-NEXT: jmp .LBB0_2 ; CHECK-NEXT: .LBB0_5: # %false2 ; CHECK-NEXT: andl %edi, %eax ; CHECK-NEXT: retq @@ -61,20 +61,20 @@ define i32 @hot(i32 %a, ptr %p, ptr %q) !prof !22 { ; CHECK-LABEL: hot: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cmpl $2, %edi -; CHECK-NEXT: jl .LBB1_2 +; CHECK-NEXT: jl .LBB1_3 ; CHECK-NEXT: # %bb.1: # %true1 ; CHECK-NEXT: movl (%rsi), %eax ; CHECK-NEXT: addl $2, %eax ; CHECK-NEXT: cmpl $5, %eax ; CHECK-NEXT: jge .LBB1_4 -; CHECK-NEXT: .LBB1_5: # %false2 +; CHECK-NEXT: .LBB1_2: # %false2 ; CHECK-NEXT: andl %edi, %eax ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB1_2: # %false1 +; CHECK-NEXT: .LBB1_3: # %false1 ; CHECK-NEXT: movl (%rdx), %eax ; CHECK-NEXT: addl $-3, %eax ; CHECK-NEXT: cmpl $5, %eax -; CHECK-NEXT: jl .LBB1_5 +; CHECK-NEXT: jl .LBB1_2 ; CHECK-NEXT: .LBB1_4: # %true2 ; CHECK-NEXT: xorl %edi, %eax ; CHECK-NEXT: retq diff --git a/llvm/test/CodeGen/X86/expand-large-fp-optnone.ll b/llvm/test/CodeGen/X86/expand-large-fp-optnone.ll index 16fe756bfc4e6..c4bd79bbb33ed 100644 --- a/llvm/test/CodeGen/X86/expand-large-fp-optnone.ll +++ b/llvm/test/CodeGen/X86/expand-large-fp-optnone.ll @@ -34,7 +34,7 @@ define double @main(i224 %0) #0 { ; CHECK-NEXT: orq %rax, %r9 ; CHECK-NEXT: xorps %xmm0, %xmm0 ; CHECK-NEXT: orq %r9, %r8 -; CHECK-NEXT: je .LBB0_10 +; CHECK-NEXT: je .LBB0_11 ; CHECK-NEXT: jmp .LBB0_1 ; CHECK-NEXT: .LBB0_1: # %itofp-if-end ; CHECK-NEXT: movslq %ecx, %rax @@ -79,19 +79,19 @@ define double @main(i224 %0) #0 { ; CHECK-NEXT: movl $223, %r10d ; CHECK-NEXT: subl %eax, %r10d ; CHECK-NEXT: cmpl $53, %r11d -; CHECK-NEXT: jle .LBB0_8 +; CHECK-NEXT: jle .LBB0_9 ; CHECK-NEXT: # %bb.2: # %itofp-if-then4 ; CHECK-NEXT: movl %r11d, %r8d ; CHECK-NEXT: subl $54, %r8d -; CHECK-NEXT: je .LBB0_4 +; CHECK-NEXT: je .LBB0_5 ; CHECK-NEXT: jmp .LBB0_3 ; CHECK-NEXT: .LBB0_3: # %itofp-if-then4 ; CHECK-NEXT: movl %r11d, %r8d ; CHECK-NEXT: subl $55, %r8d -; CHECK-NEXT: jne .LBB0_5 -; CHECK-NEXT: # %bb.11: -; CHECK-NEXT: jmp .LBB0_6 -; CHECK-NEXT: .LBB0_4: # %itofp-sw-bb +; CHECK-NEXT: jne .LBB0_6 +; CHECK-NEXT: # %bb.4: +; CHECK-NEXT: jmp .LBB0_7 +; CHECK-NEXT: .LBB0_5: # %itofp-sw-bb ; CHECK-NEXT: movq %rsi, %rax ; CHECK-NEXT: shldq $1, %rdi, %rax ; CHECK-NEXT: movq %rdx, %r8 @@ -100,8 +100,8 @@ define double @main(i224 %0) #0 { ; CHECK-NEXT: addq %rdi, %rdi ; CHECK-NEXT: movq %rax, %rsi ; CHECK-NEXT: movq %r8, %rdx -; CHECK-NEXT: jmp .LBB0_6 -; CHECK-NEXT: .LBB0_5: # %itofp-sw-default +; CHECK-NEXT: jmp .LBB0_7 +; CHECK-NEXT: .LBB0_6: # %itofp-sw-default ; CHECK-NEXT: movq %rdi, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movq %rsi, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movq %rdx, -{{[0-9]+}}(%rsp) @@ -171,8 +171,8 @@ define double @main(i224 %0) #0 { ; CHECK-NEXT: movq %r14, %rsi ; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload ; CHECK-NEXT: movq %rbx, %rcx -; CHECK-NEXT: jmp .LBB0_6 -; CHECK-NEXT: .LBB0_6: # %itofp-sw-epilog +; CHECK-NEXT: jmp .LBB0_7 +; CHECK-NEXT: .LBB0_7: # %itofp-sw-epilog ; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: shrl $2, %eax ; CHECK-NEXT: andl $1, %eax @@ -186,16 +186,16 @@ define double @main(i224 %0) #0 { ; CHECK-NEXT: movq %rdx, %rax ; CHECK-NEXT: shrq $32, %rax ; CHECK-NEXT: btq $55, %rdi -; CHECK-NEXT: jae .LBB0_9 -; CHECK-NEXT: jmp .LBB0_7 -; CHECK-NEXT: .LBB0_7: # %itofp-if-then20 +; CHECK-NEXT: jae .LBB0_10 +; CHECK-NEXT: jmp .LBB0_8 +; CHECK-NEXT: .LBB0_8: # %itofp-if-then20 ; CHECK-NEXT: shrdq $3, %rsi, %rdi ; CHECK-NEXT: movq %rdi, %rax ; CHECK-NEXT: shrq $32, %rax ; CHECK-NEXT: movq %rdi, %rdx ; CHECK-NEXT: movl %r11d, %r10d -; CHECK-NEXT: jmp .LBB0_9 -; CHECK-NEXT: .LBB0_8: # %itofp-if-else +; CHECK-NEXT: jmp .LBB0_10 +; CHECK-NEXT: .LBB0_9: # %itofp-if-else ; CHECK-NEXT: movq %rdi, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movq %rsi, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movq %rdx, {{[0-9]+}}(%rsp) @@ -215,7 +215,7 @@ define double @main(i224 %0) #0 { ; CHECK-NEXT: shlq %cl, %rdx ; CHECK-NEXT: movq %rdx, %rax ; CHECK-NEXT: shrq $32, %rax -; CHECK-NEXT: .LBB0_9: # %itofp-if-end26 +; CHECK-NEXT: .LBB0_10: # %itofp-if-end26 ; CHECK-NEXT: andl $-2147483648, %r9d # imm = 0x80000000 ; CHECK-NEXT: shll $20, %r10d ; CHECK-NEXT: addl $1072693248, %r10d # imm = 0x3FF00000 @@ -228,7 +228,7 @@ define double @main(i224 %0) #0 { ; CHECK-NEXT: andq %rcx, %rdx ; CHECK-NEXT: orq %rdx, %rax ; CHECK-NEXT: movq %rax, %xmm0 -; CHECK-NEXT: .LBB0_10: # %itofp-return +; CHECK-NEXT: .LBB0_11: # %itofp-return ; CHECK-NEXT: addq $88, %rsp ; CHECK-NEXT: .cfi_def_cfa_offset 56 ; CHECK-NEXT: popq %rbx diff --git a/llvm/test/CodeGen/X86/extract-bits.ll b/llvm/test/CodeGen/X86/extract-bits.ll index 90e075bfabf0a..a33930b9a4949 100644 --- a/llvm/test/CodeGen/X86/extract-bits.ll +++ b/llvm/test/CodeGen/X86/extract-bits.ll @@ -2679,11 +2679,11 @@ define i64 @bextr64_b0(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind { ; X86-NOBMI-NEXT: movb %ch, %cl ; X86-NOBMI-NEXT: shll %cl, %ebx ; X86-NOBMI-NEXT: testb $32, %ch -; X86-NOBMI-NEXT: jne .LBB25_3 -; X86-NOBMI-NEXT: # %bb.4: +; X86-NOBMI-NEXT: jne .LBB25_4 +; X86-NOBMI-NEXT: # %bb.3: ; X86-NOBMI-NEXT: movl %ebx, %eax ; X86-NOBMI-NEXT: jmp .LBB25_5 -; X86-NOBMI-NEXT: .LBB25_3: +; X86-NOBMI-NEXT: .LBB25_4: ; X86-NOBMI-NEXT: movl %ebx, %edx ; X86-NOBMI-NEXT: .LBB25_5: ; X86-NOBMI-NEXT: notl %edx @@ -2817,11 +2817,11 @@ define i64 @bextr64_b1_indexzext(i64 %val, i8 zeroext %numskipbits, i8 zeroext % ; X86-NOBMI-NEXT: movb %ch, %cl ; X86-NOBMI-NEXT: shll %cl, %ebx ; X86-NOBMI-NEXT: testb $32, %ch -; X86-NOBMI-NEXT: jne .LBB26_3 -; X86-NOBMI-NEXT: # %bb.4: +; X86-NOBMI-NEXT: jne .LBB26_4 +; X86-NOBMI-NEXT: # %bb.3: ; X86-NOBMI-NEXT: movl %ebx, %eax ; X86-NOBMI-NEXT: jmp .LBB26_5 -; X86-NOBMI-NEXT: .LBB26_3: +; X86-NOBMI-NEXT: .LBB26_4: ; X86-NOBMI-NEXT: movl %ebx, %edx ; X86-NOBMI-NEXT: .LBB26_5: ; X86-NOBMI-NEXT: notl %edx @@ -2960,11 +2960,11 @@ define i64 @bextr64_b2_load(ptr %w, i64 %numskipbits, i64 %numlowbits) nounwind ; X86-NOBMI-NEXT: movb %ch, %cl ; X86-NOBMI-NEXT: shll %cl, %ebx ; X86-NOBMI-NEXT: testb $32, %ch -; X86-NOBMI-NEXT: jne .LBB27_3 -; X86-NOBMI-NEXT: # %bb.4: +; X86-NOBMI-NEXT: jne .LBB27_4 +; X86-NOBMI-NEXT: # %bb.3: ; X86-NOBMI-NEXT: movl %ebx, %eax ; X86-NOBMI-NEXT: jmp .LBB27_5 -; X86-NOBMI-NEXT: .LBB27_3: +; X86-NOBMI-NEXT: .LBB27_4: ; X86-NOBMI-NEXT: movl %ebx, %edx ; X86-NOBMI-NEXT: .LBB27_5: ; X86-NOBMI-NEXT: notl %edx @@ -3103,11 +3103,11 @@ define i64 @bextr64_b3_load_indexzext(ptr %w, i8 zeroext %numskipbits, i8 zeroex ; X86-NOBMI-NEXT: movb %ch, %cl ; X86-NOBMI-NEXT: shll %cl, %ebx ; X86-NOBMI-NEXT: testb $32, %ch -; X86-NOBMI-NEXT: jne .LBB28_3 -; X86-NOBMI-NEXT: # %bb.4: +; X86-NOBMI-NEXT: jne .LBB28_4 +; X86-NOBMI-NEXT: # %bb.3: ; X86-NOBMI-NEXT: movl %ebx, %eax ; X86-NOBMI-NEXT: jmp .LBB28_5 -; X86-NOBMI-NEXT: .LBB28_3: +; X86-NOBMI-NEXT: .LBB28_4: ; X86-NOBMI-NEXT: movl %ebx, %edx ; X86-NOBMI-NEXT: .LBB28_5: ; X86-NOBMI-NEXT: notl %edx @@ -3249,11 +3249,11 @@ define i64 @bextr64_b4_commutative(i64 %val, i64 %numskipbits, i64 %numlowbits) ; X86-NOBMI-NEXT: movb %ch, %cl ; X86-NOBMI-NEXT: shll %cl, %ebx ; X86-NOBMI-NEXT: testb $32, %ch -; X86-NOBMI-NEXT: jne .LBB29_3 -; X86-NOBMI-NEXT: # %bb.4: +; X86-NOBMI-NEXT: jne .LBB29_4 +; X86-NOBMI-NEXT: # %bb.3: ; X86-NOBMI-NEXT: movl %ebx, %esi ; X86-NOBMI-NEXT: jmp .LBB29_5 -; X86-NOBMI-NEXT: .LBB29_3: +; X86-NOBMI-NEXT: .LBB29_4: ; X86-NOBMI-NEXT: movl %ebx, %edi ; X86-NOBMI-NEXT: .LBB29_5: ; X86-NOBMI-NEXT: notl %edi @@ -3390,11 +3390,11 @@ define i64 @bextr64_b5_skipextrauses(i64 %val, i64 %numskipbits, i64 %numlowbits ; X86-NOBMI-NEXT: movb %ch, %cl ; X86-NOBMI-NEXT: shll %cl, %esi ; X86-NOBMI-NEXT: testb $32, %ch -; X86-NOBMI-NEXT: jne .LBB30_3 -; X86-NOBMI-NEXT: # %bb.4: +; X86-NOBMI-NEXT: jne .LBB30_4 +; X86-NOBMI-NEXT: # %bb.3: ; X86-NOBMI-NEXT: movl %esi, %ebx ; X86-NOBMI-NEXT: jmp .LBB30_5 -; X86-NOBMI-NEXT: .LBB30_3: +; X86-NOBMI-NEXT: .LBB30_4: ; X86-NOBMI-NEXT: movl %esi, %edi ; X86-NOBMI-NEXT: .LBB30_5: ; X86-NOBMI-NEXT: notl %edi diff --git a/llvm/test/CodeGen/X86/extract-lowbits.ll b/llvm/test/CodeGen/X86/extract-lowbits.ll index aff5ac7437a29..a28af90edc76b 100644 --- a/llvm/test/CodeGen/X86/extract-lowbits.ll +++ b/llvm/test/CodeGen/X86/extract-lowbits.ll @@ -1409,11 +1409,11 @@ define i64 @bzhi64_b0(i64 %val, i64 %numlowbits) nounwind { ; X86-NOBMI-NEXT: shll %cl, %esi ; X86-NOBMI-NEXT: xorl %eax, %eax ; X86-NOBMI-NEXT: testb $32, %cl -; X86-NOBMI-NEXT: jne .LBB21_1 -; X86-NOBMI-NEXT: # %bb.2: +; X86-NOBMI-NEXT: jne .LBB21_2 +; X86-NOBMI-NEXT: # %bb.1: ; X86-NOBMI-NEXT: movl %esi, %eax ; X86-NOBMI-NEXT: jmp .LBB21_3 -; X86-NOBMI-NEXT: .LBB21_1: +; X86-NOBMI-NEXT: .LBB21_2: ; X86-NOBMI-NEXT: movl %esi, %edx ; X86-NOBMI-NEXT: .LBB21_3: ; X86-NOBMI-NEXT: notl %edx @@ -1490,11 +1490,11 @@ define i64 @bzhi64_b1_indexzext(i64 %val, i8 zeroext %numlowbits) nounwind { ; X86-NOBMI-NEXT: shll %cl, %esi ; X86-NOBMI-NEXT: xorl %eax, %eax ; X86-NOBMI-NEXT: testb $32, %cl -; X86-NOBMI-NEXT: jne .LBB22_1 -; X86-NOBMI-NEXT: # %bb.2: +; X86-NOBMI-NEXT: jne .LBB22_2 +; X86-NOBMI-NEXT: # %bb.1: ; X86-NOBMI-NEXT: movl %esi, %eax ; X86-NOBMI-NEXT: jmp .LBB22_3 -; X86-NOBMI-NEXT: .LBB22_1: +; X86-NOBMI-NEXT: .LBB22_2: ; X86-NOBMI-NEXT: movl %esi, %edx ; X86-NOBMI-NEXT: .LBB22_3: ; X86-NOBMI-NEXT: notl %edx @@ -1576,11 +1576,11 @@ define i64 @bzhi64_b2_load(ptr %w, i64 %numlowbits) nounwind { ; X86-NOBMI-NEXT: shll %cl, %edi ; X86-NOBMI-NEXT: xorl %eax, %eax ; X86-NOBMI-NEXT: testb $32, %cl -; X86-NOBMI-NEXT: jne .LBB23_1 -; X86-NOBMI-NEXT: # %bb.2: +; X86-NOBMI-NEXT: jne .LBB23_2 +; X86-NOBMI-NEXT: # %bb.1: ; X86-NOBMI-NEXT: movl %edi, %eax ; X86-NOBMI-NEXT: jmp .LBB23_3 -; X86-NOBMI-NEXT: .LBB23_1: +; X86-NOBMI-NEXT: .LBB23_2: ; X86-NOBMI-NEXT: movl %edi, %edx ; X86-NOBMI-NEXT: .LBB23_3: ; X86-NOBMI-NEXT: notl %edx @@ -1667,11 +1667,11 @@ define i64 @bzhi64_b3_load_indexzext(ptr %w, i8 zeroext %numlowbits) nounwind { ; X86-NOBMI-NEXT: shll %cl, %edi ; X86-NOBMI-NEXT: xorl %eax, %eax ; X86-NOBMI-NEXT: testb $32, %cl -; X86-NOBMI-NEXT: jne .LBB24_1 -; X86-NOBMI-NEXT: # %bb.2: +; X86-NOBMI-NEXT: jne .LBB24_2 +; X86-NOBMI-NEXT: # %bb.1: ; X86-NOBMI-NEXT: movl %edi, %eax ; X86-NOBMI-NEXT: jmp .LBB24_3 -; X86-NOBMI-NEXT: .LBB24_1: +; X86-NOBMI-NEXT: .LBB24_2: ; X86-NOBMI-NEXT: movl %edi, %edx ; X86-NOBMI-NEXT: .LBB24_3: ; X86-NOBMI-NEXT: notl %edx @@ -1759,11 +1759,11 @@ define i64 @bzhi64_b4_commutative(i64 %val, i64 %numlowbits) nounwind { ; X86-NOBMI-NEXT: shll %cl, %esi ; X86-NOBMI-NEXT: xorl %eax, %eax ; X86-NOBMI-NEXT: testb $32, %cl -; X86-NOBMI-NEXT: jne .LBB25_1 -; X86-NOBMI-NEXT: # %bb.2: +; X86-NOBMI-NEXT: jne .LBB25_2 +; X86-NOBMI-NEXT: # %bb.1: ; X86-NOBMI-NEXT: movl %esi, %eax ; X86-NOBMI-NEXT: jmp .LBB25_3 -; X86-NOBMI-NEXT: .LBB25_1: +; X86-NOBMI-NEXT: .LBB25_2: ; X86-NOBMI-NEXT: movl %esi, %edx ; X86-NOBMI-NEXT: .LBB25_3: ; X86-NOBMI-NEXT: notl %edx diff --git a/llvm/test/CodeGen/X86/fast-isel-select-pseudo-cmov.ll b/llvm/test/CodeGen/X86/fast-isel-select-pseudo-cmov.ll index 14f8ab6e41d59..a76de48c65a69 100644 --- a/llvm/test/CodeGen/X86/fast-isel-select-pseudo-cmov.ll +++ b/llvm/test/CodeGen/X86/fast-isel-select-pseudo-cmov.ll @@ -485,12 +485,12 @@ define i8 @select_icmp_sle_i8(i64 %a, i64 %b, i8 %c, i8 %d) { ; FASTISEL-LABEL: select_icmp_sle_i8: ; FASTISEL: ## %bb.0: ; FASTISEL-NEXT: cmpq %rsi, %rdi -; FASTISEL-NEXT: jle LBB12_1 -; FASTISEL-NEXT: ## %bb.2: +; FASTISEL-NEXT: jle LBB12_2 +; FASTISEL-NEXT: ## %bb.1: ; FASTISEL-NEXT: movl %ecx, %eax ; FASTISEL-NEXT: ## kill: def $al killed $al killed $eax ; FASTISEL-NEXT: retq -; FASTISEL-NEXT: LBB12_1: +; FASTISEL-NEXT: LBB12_2: ; FASTISEL-NEXT: movl %edx, %eax ; FASTISEL-NEXT: ## kill: def $al killed $al killed $eax ; FASTISEL-NEXT: retq diff --git a/llvm/test/CodeGen/X86/fdiv-combine.ll b/llvm/test/CodeGen/X86/fdiv-combine.ll index 1abcdc3cca9b7..f8b89d99dca65 100644 --- a/llvm/test/CodeGen/X86/fdiv-combine.ll +++ b/llvm/test/CodeGen/X86/fdiv-combine.ll @@ -100,11 +100,11 @@ define float @div_select_constant_fold(i1 zeroext %arg) { ; CHECK-LABEL: div_select_constant_fold: ; CHECK: # %bb.0: ; CHECK-NEXT: testl %edi, %edi -; CHECK-NEXT: jne .LBB6_1 -; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: jne .LBB6_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: movss {{.*#+}} xmm0 = [3.0E+0,0.0E+0,0.0E+0,0.0E+0] ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB6_1: +; CHECK-NEXT: .LBB6_2: ; CHECK-NEXT: movss {{.*#+}} xmm0 = [2.5E+0,0.0E+0,0.0E+0,0.0E+0] ; CHECK-NEXT: retq %tmp = select i1 %arg, float 5.000000e+00, float 6.000000e+00 diff --git a/llvm/test/CodeGen/X86/fma-intrinsics-phi-213-to-231.ll b/llvm/test/CodeGen/X86/fma-intrinsics-phi-213-to-231.ll index 5f1c5a5690ef2..5719ada0dfafc 100644 --- a/llvm/test/CodeGen/X86/fma-intrinsics-phi-213-to-231.ll +++ b/llvm/test/CodeGen/X86/fma-intrinsics-phi-213-to-231.ll @@ -6,15 +6,15 @@ define <2 x double> @fmaddsubpd_loop_128(i32 %iter, <2 x double> %a, <2 x double ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jge .LBB0_3 +; CHECK-NEXT: jge .LBB0_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_2: # %for.body +; CHECK-NEXT: .LBB0_1: # %for.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vfmaddsub231pd {{.*#+}} xmm2 = (xmm0 * xmm1) +/- xmm2 ; CHECK-NEXT: incl %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jl .LBB0_2 -; CHECK-NEXT: .LBB0_3: # %for.end +; CHECK-NEXT: jl .LBB0_1 +; CHECK-NEXT: .LBB0_2: # %for.end ; CHECK-NEXT: vmovapd %xmm2, %xmm0 ; CHECK-NEXT: retq entry: @@ -43,15 +43,15 @@ define <2 x double> @fmsubaddpd_loop_128(i32 %iter, <2 x double> %a, <2 x double ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jge .LBB1_3 +; CHECK-NEXT: jge .LBB1_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB1_2: # %for.body +; CHECK-NEXT: .LBB1_1: # %for.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vfmsubadd231pd {{.*#+}} xmm2 = (xmm0 * xmm1) -/+ xmm2 ; CHECK-NEXT: incl %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jl .LBB1_2 -; CHECK-NEXT: .LBB1_3: # %for.end +; CHECK-NEXT: jl .LBB1_1 +; CHECK-NEXT: .LBB1_2: # %for.end ; CHECK-NEXT: vmovapd %xmm2, %xmm0 ; CHECK-NEXT: retq entry: @@ -80,15 +80,15 @@ define <2 x double> @fmaddpd_loop_128(i32 %iter, <2 x double> %a, <2 x double> % ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jge .LBB2_3 +; CHECK-NEXT: jge .LBB2_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB2_2: # %for.body +; CHECK-NEXT: .LBB2_1: # %for.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vfmadd231pd {{.*#+}} xmm2 = (xmm0 * xmm1) + xmm2 ; CHECK-NEXT: incl %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jl .LBB2_2 -; CHECK-NEXT: .LBB2_3: # %for.end +; CHECK-NEXT: jl .LBB2_1 +; CHECK-NEXT: .LBB2_2: # %for.end ; CHECK-NEXT: vmovapd %xmm2, %xmm0 ; CHECK-NEXT: retq entry: @@ -117,15 +117,15 @@ define <2 x double> @fmsubpd_loop_128(i32 %iter, <2 x double> %a, <2 x double> % ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jge .LBB3_3 +; CHECK-NEXT: jge .LBB3_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB3_2: # %for.body +; CHECK-NEXT: .LBB3_1: # %for.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vfmsub231pd {{.*#+}} xmm2 = (xmm0 * xmm1) - xmm2 ; CHECK-NEXT: incl %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jl .LBB3_2 -; CHECK-NEXT: .LBB3_3: # %for.end +; CHECK-NEXT: jl .LBB3_1 +; CHECK-NEXT: .LBB3_2: # %for.end ; CHECK-NEXT: vmovapd %xmm2, %xmm0 ; CHECK-NEXT: retq entry: @@ -154,15 +154,15 @@ define <2 x double> @fnmaddpd_loop_128(i32 %iter, <2 x double> %a, <2 x double> ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jge .LBB4_3 +; CHECK-NEXT: jge .LBB4_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB4_2: # %for.body +; CHECK-NEXT: .LBB4_1: # %for.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vfnmadd231pd {{.*#+}} xmm2 = -(xmm0 * xmm1) + xmm2 ; CHECK-NEXT: incl %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jl .LBB4_2 -; CHECK-NEXT: .LBB4_3: # %for.end +; CHECK-NEXT: jl .LBB4_1 +; CHECK-NEXT: .LBB4_2: # %for.end ; CHECK-NEXT: vmovapd %xmm2, %xmm0 ; CHECK-NEXT: retq entry: @@ -191,15 +191,15 @@ define <2 x double> @fnmsubpd_loop_128(i32 %iter, <2 x double> %a, <2 x double> ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jge .LBB5_3 +; CHECK-NEXT: jge .LBB5_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB5_2: # %for.body +; CHECK-NEXT: .LBB5_1: # %for.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vfnmsub231pd {{.*#+}} xmm2 = -(xmm0 * xmm1) - xmm2 ; CHECK-NEXT: incl %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jl .LBB5_2 -; CHECK-NEXT: .LBB5_3: # %for.end +; CHECK-NEXT: jl .LBB5_1 +; CHECK-NEXT: .LBB5_2: # %for.end ; CHECK-NEXT: vmovapd %xmm2, %xmm0 ; CHECK-NEXT: retq entry: @@ -235,15 +235,15 @@ define <4 x float> @fmaddsubps_loop_128(i32 %iter, <4 x float> %a, <4 x float> % ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jge .LBB6_3 +; CHECK-NEXT: jge .LBB6_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB6_2: # %for.body +; CHECK-NEXT: .LBB6_1: # %for.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vfmaddsub231ps {{.*#+}} xmm2 = (xmm0 * xmm1) +/- xmm2 ; CHECK-NEXT: incl %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jl .LBB6_2 -; CHECK-NEXT: .LBB6_3: # %for.end +; CHECK-NEXT: jl .LBB6_1 +; CHECK-NEXT: .LBB6_2: # %for.end ; CHECK-NEXT: vmovaps %xmm2, %xmm0 ; CHECK-NEXT: retq entry: @@ -272,15 +272,15 @@ define <4 x float> @fmsubaddps_loop_128(i32 %iter, <4 x float> %a, <4 x float> % ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jge .LBB7_3 +; CHECK-NEXT: jge .LBB7_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB7_2: # %for.body +; CHECK-NEXT: .LBB7_1: # %for.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vfmsubadd231ps {{.*#+}} xmm2 = (xmm0 * xmm1) -/+ xmm2 ; CHECK-NEXT: incl %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jl .LBB7_2 -; CHECK-NEXT: .LBB7_3: # %for.end +; CHECK-NEXT: jl .LBB7_1 +; CHECK-NEXT: .LBB7_2: # %for.end ; CHECK-NEXT: vmovaps %xmm2, %xmm0 ; CHECK-NEXT: retq entry: @@ -309,15 +309,15 @@ define <4 x float> @fmaddps_loop_128(i32 %iter, <4 x float> %a, <4 x float> %b, ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jge .LBB8_3 +; CHECK-NEXT: jge .LBB8_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB8_2: # %for.body +; CHECK-NEXT: .LBB8_1: # %for.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vfmadd231ps {{.*#+}} xmm2 = (xmm0 * xmm1) + xmm2 ; CHECK-NEXT: incl %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jl .LBB8_2 -; CHECK-NEXT: .LBB8_3: # %for.end +; CHECK-NEXT: jl .LBB8_1 +; CHECK-NEXT: .LBB8_2: # %for.end ; CHECK-NEXT: vmovaps %xmm2, %xmm0 ; CHECK-NEXT: retq entry: @@ -346,15 +346,15 @@ define <4 x float> @fmsubps_loop_128(i32 %iter, <4 x float> %a, <4 x float> %b, ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jge .LBB9_3 +; CHECK-NEXT: jge .LBB9_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB9_2: # %for.body +; CHECK-NEXT: .LBB9_1: # %for.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vfmsub231ps {{.*#+}} xmm2 = (xmm0 * xmm1) - xmm2 ; CHECK-NEXT: incl %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jl .LBB9_2 -; CHECK-NEXT: .LBB9_3: # %for.end +; CHECK-NEXT: jl .LBB9_1 +; CHECK-NEXT: .LBB9_2: # %for.end ; CHECK-NEXT: vmovaps %xmm2, %xmm0 ; CHECK-NEXT: retq entry: @@ -383,15 +383,15 @@ define <4 x float> @fnmaddps_loop_128(i32 %iter, <4 x float> %a, <4 x float> %b, ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jge .LBB10_3 +; CHECK-NEXT: jge .LBB10_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB10_2: # %for.body +; CHECK-NEXT: .LBB10_1: # %for.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vfnmadd231ps {{.*#+}} xmm2 = -(xmm0 * xmm1) + xmm2 ; CHECK-NEXT: incl %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jl .LBB10_2 -; CHECK-NEXT: .LBB10_3: # %for.end +; CHECK-NEXT: jl .LBB10_1 +; CHECK-NEXT: .LBB10_2: # %for.end ; CHECK-NEXT: vmovaps %xmm2, %xmm0 ; CHECK-NEXT: retq entry: @@ -420,15 +420,15 @@ define <4 x float> @fnmsubps_loop_128(i32 %iter, <4 x float> %a, <4 x float> %b, ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jge .LBB11_3 +; CHECK-NEXT: jge .LBB11_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB11_2: # %for.body +; CHECK-NEXT: .LBB11_1: # %for.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vfnmsub231ps {{.*#+}} xmm2 = -(xmm0 * xmm1) - xmm2 ; CHECK-NEXT: incl %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jl .LBB11_2 -; CHECK-NEXT: .LBB11_3: # %for.end +; CHECK-NEXT: jl .LBB11_1 +; CHECK-NEXT: .LBB11_2: # %for.end ; CHECK-NEXT: vmovaps %xmm2, %xmm0 ; CHECK-NEXT: retq entry: @@ -464,15 +464,15 @@ define <4 x double> @fmaddsubpd_loop_256(i32 %iter, <4 x double> %a, <4 x double ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jge .LBB12_3 +; CHECK-NEXT: jge .LBB12_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB12_2: # %for.body +; CHECK-NEXT: .LBB12_1: # %for.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vfmaddsub231pd {{.*#+}} ymm2 = (ymm0 * ymm1) +/- ymm2 ; CHECK-NEXT: incl %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jl .LBB12_2 -; CHECK-NEXT: .LBB12_3: # %for.end +; CHECK-NEXT: jl .LBB12_1 +; CHECK-NEXT: .LBB12_2: # %for.end ; CHECK-NEXT: vmovapd %ymm2, %ymm0 ; CHECK-NEXT: retq entry: @@ -501,15 +501,15 @@ define <4 x double> @fmsubaddpd_loop_256(i32 %iter, <4 x double> %a, <4 x double ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jge .LBB13_3 +; CHECK-NEXT: jge .LBB13_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB13_2: # %for.body +; CHECK-NEXT: .LBB13_1: # %for.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vfmsubadd231pd {{.*#+}} ymm2 = (ymm0 * ymm1) -/+ ymm2 ; CHECK-NEXT: incl %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jl .LBB13_2 -; CHECK-NEXT: .LBB13_3: # %for.end +; CHECK-NEXT: jl .LBB13_1 +; CHECK-NEXT: .LBB13_2: # %for.end ; CHECK-NEXT: vmovapd %ymm2, %ymm0 ; CHECK-NEXT: retq entry: @@ -538,15 +538,15 @@ define <4 x double> @fmaddpd_loop_256(i32 %iter, <4 x double> %a, <4 x double> % ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jge .LBB14_3 +; CHECK-NEXT: jge .LBB14_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB14_2: # %for.body +; CHECK-NEXT: .LBB14_1: # %for.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vfmadd231pd {{.*#+}} ymm2 = (ymm0 * ymm1) + ymm2 ; CHECK-NEXT: incl %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jl .LBB14_2 -; CHECK-NEXT: .LBB14_3: # %for.end +; CHECK-NEXT: jl .LBB14_1 +; CHECK-NEXT: .LBB14_2: # %for.end ; CHECK-NEXT: vmovapd %ymm2, %ymm0 ; CHECK-NEXT: retq entry: @@ -575,15 +575,15 @@ define <4 x double> @fmsubpd_loop_256(i32 %iter, <4 x double> %a, <4 x double> % ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jge .LBB15_3 +; CHECK-NEXT: jge .LBB15_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB15_2: # %for.body +; CHECK-NEXT: .LBB15_1: # %for.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vfmsub231pd {{.*#+}} ymm2 = (ymm0 * ymm1) - ymm2 ; CHECK-NEXT: incl %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jl .LBB15_2 -; CHECK-NEXT: .LBB15_3: # %for.end +; CHECK-NEXT: jl .LBB15_1 +; CHECK-NEXT: .LBB15_2: # %for.end ; CHECK-NEXT: vmovapd %ymm2, %ymm0 ; CHECK-NEXT: retq entry: @@ -612,15 +612,15 @@ define <4 x double> @fnmaddpd_loop_256(i32 %iter, <4 x double> %a, <4 x double> ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jge .LBB16_3 +; CHECK-NEXT: jge .LBB16_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB16_2: # %for.body +; CHECK-NEXT: .LBB16_1: # %for.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vfnmadd231pd {{.*#+}} ymm2 = -(ymm0 * ymm1) + ymm2 ; CHECK-NEXT: incl %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jl .LBB16_2 -; CHECK-NEXT: .LBB16_3: # %for.end +; CHECK-NEXT: jl .LBB16_1 +; CHECK-NEXT: .LBB16_2: # %for.end ; CHECK-NEXT: vmovapd %ymm2, %ymm0 ; CHECK-NEXT: retq entry: @@ -649,15 +649,15 @@ define <4 x double> @fnmsubpd_loop_256(i32 %iter, <4 x double> %a, <4 x double> ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jge .LBB17_3 +; CHECK-NEXT: jge .LBB17_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB17_2: # %for.body +; CHECK-NEXT: .LBB17_1: # %for.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vfnmsub231pd {{.*#+}} ymm2 = -(ymm0 * ymm1) - ymm2 ; CHECK-NEXT: incl %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jl .LBB17_2 -; CHECK-NEXT: .LBB17_3: # %for.end +; CHECK-NEXT: jl .LBB17_1 +; CHECK-NEXT: .LBB17_2: # %for.end ; CHECK-NEXT: vmovapd %ymm2, %ymm0 ; CHECK-NEXT: retq entry: @@ -693,15 +693,15 @@ define <8 x float> @fmaddsubps_loop_256(i32 %iter, <8 x float> %a, <8 x float> % ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jge .LBB18_3 +; CHECK-NEXT: jge .LBB18_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB18_2: # %for.body +; CHECK-NEXT: .LBB18_1: # %for.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vfmaddsub231ps {{.*#+}} ymm2 = (ymm0 * ymm1) +/- ymm2 ; CHECK-NEXT: incl %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jl .LBB18_2 -; CHECK-NEXT: .LBB18_3: # %for.end +; CHECK-NEXT: jl .LBB18_1 +; CHECK-NEXT: .LBB18_2: # %for.end ; CHECK-NEXT: vmovaps %ymm2, %ymm0 ; CHECK-NEXT: retq entry: @@ -730,15 +730,15 @@ define <8 x float> @fmsubaddps_loop_256(i32 %iter, <8 x float> %a, <8 x float> % ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jge .LBB19_3 +; CHECK-NEXT: jge .LBB19_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB19_2: # %for.body +; CHECK-NEXT: .LBB19_1: # %for.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vfmsubadd231ps {{.*#+}} ymm2 = (ymm0 * ymm1) -/+ ymm2 ; CHECK-NEXT: incl %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jl .LBB19_2 -; CHECK-NEXT: .LBB19_3: # %for.end +; CHECK-NEXT: jl .LBB19_1 +; CHECK-NEXT: .LBB19_2: # %for.end ; CHECK-NEXT: vmovaps %ymm2, %ymm0 ; CHECK-NEXT: retq entry: @@ -767,15 +767,15 @@ define <8 x float> @fmaddps_loop_256(i32 %iter, <8 x float> %a, <8 x float> %b, ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jge .LBB20_3 +; CHECK-NEXT: jge .LBB20_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB20_2: # %for.body +; CHECK-NEXT: .LBB20_1: # %for.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vfmadd231ps {{.*#+}} ymm2 = (ymm0 * ymm1) + ymm2 ; CHECK-NEXT: incl %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jl .LBB20_2 -; CHECK-NEXT: .LBB20_3: # %for.end +; CHECK-NEXT: jl .LBB20_1 +; CHECK-NEXT: .LBB20_2: # %for.end ; CHECK-NEXT: vmovaps %ymm2, %ymm0 ; CHECK-NEXT: retq entry: @@ -804,15 +804,15 @@ define <8 x float> @fmsubps_loop_256(i32 %iter, <8 x float> %a, <8 x float> %b, ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jge .LBB21_3 +; CHECK-NEXT: jge .LBB21_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB21_2: # %for.body +; CHECK-NEXT: .LBB21_1: # %for.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vfmsub231ps {{.*#+}} ymm2 = (ymm0 * ymm1) - ymm2 ; CHECK-NEXT: incl %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jl .LBB21_2 -; CHECK-NEXT: .LBB21_3: # %for.end +; CHECK-NEXT: jl .LBB21_1 +; CHECK-NEXT: .LBB21_2: # %for.end ; CHECK-NEXT: vmovaps %ymm2, %ymm0 ; CHECK-NEXT: retq entry: @@ -841,15 +841,15 @@ define <8 x float> @fnmaddps_loop_256(i32 %iter, <8 x float> %a, <8 x float> %b, ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jge .LBB22_3 +; CHECK-NEXT: jge .LBB22_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB22_2: # %for.body +; CHECK-NEXT: .LBB22_1: # %for.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vfnmadd231ps {{.*#+}} ymm2 = -(ymm0 * ymm1) + ymm2 ; CHECK-NEXT: incl %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jl .LBB22_2 -; CHECK-NEXT: .LBB22_3: # %for.end +; CHECK-NEXT: jl .LBB22_1 +; CHECK-NEXT: .LBB22_2: # %for.end ; CHECK-NEXT: vmovaps %ymm2, %ymm0 ; CHECK-NEXT: retq entry: @@ -878,15 +878,15 @@ define <8 x float> @fnmsubps_loop_256(i32 %iter, <8 x float> %a, <8 x float> %b, ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jge .LBB23_3 +; CHECK-NEXT: jge .LBB23_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB23_2: # %for.body +; CHECK-NEXT: .LBB23_1: # %for.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vfnmsub231ps {{.*#+}} ymm2 = -(ymm0 * ymm1) - ymm2 ; CHECK-NEXT: incl %eax ; CHECK-NEXT: cmpl %edi, %eax -; CHECK-NEXT: jl .LBB23_2 -; CHECK-NEXT: .LBB23_3: # %for.end +; CHECK-NEXT: jl .LBB23_1 +; CHECK-NEXT: .LBB23_2: # %for.end ; CHECK-NEXT: vmovaps %ymm2, %ymm0 ; CHECK-NEXT: retq entry: diff --git a/llvm/test/CodeGen/X86/fold-add-32.ll b/llvm/test/CodeGen/X86/fold-add-32.ll index 2774a93993153..cf734fb6c2291 100644 --- a/llvm/test/CodeGen/X86/fold-add-32.ll +++ b/llvm/test/CodeGen/X86/fold-add-32.ll @@ -17,11 +17,11 @@ define i32 @foo(i1 %b) #0 { ; CHECK-NEXT: movl __stack_chk_guard, %eax ; CHECK-NEXT: movl %eax, -4(%ebp) ; CHECK-NEXT: testb $1, 8(%ebp) -; CHECK-NEXT: jne .LBB0_1 -; CHECK-NEXT: # %bb.2: # %entry +; CHECK-NEXT: jne .LBB0_2 +; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: jmp .LBB0_3 -; CHECK-NEXT: .LBB0_1: +; CHECK-NEXT: .LBB0_2: ; CHECK-NEXT: movl $-2147483647, %eax # imm = 0x80000001 ; CHECK-NEXT: leal -5(%ebp,%eax), %eax ; CHECK-NEXT: .LBB0_3: # %entry diff --git a/llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll b/llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll index a8a6786d97ea0..584ae7438050c 100644 --- a/llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll +++ b/llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll @@ -1280,11 +1280,11 @@ define float @fdiv_pow_shl_cnt_fail_maybe_z(i64 %cnt) nounwind { ; CHECK-SSE-NEXT: # kill: def $cl killed $cl killed $rcx ; CHECK-SSE-NEXT: shlq %cl, %rax ; CHECK-SSE-NEXT: testq %rax, %rax -; CHECK-SSE-NEXT: js .LBB24_1 -; CHECK-SSE-NEXT: # %bb.2: +; CHECK-SSE-NEXT: js .LBB24_2 +; CHECK-SSE-NEXT: # %bb.1: ; CHECK-SSE-NEXT: cvtsi2ss %rax, %xmm1 ; CHECK-SSE-NEXT: jmp .LBB24_3 -; CHECK-SSE-NEXT: .LBB24_1: +; CHECK-SSE-NEXT: .LBB24_2: ; CHECK-SSE-NEXT: shrq %rax ; CHECK-SSE-NEXT: cvtsi2ss %rax, %xmm1 ; CHECK-SSE-NEXT: addss %xmm1, %xmm1 @@ -1300,11 +1300,11 @@ define float @fdiv_pow_shl_cnt_fail_maybe_z(i64 %cnt) nounwind { ; CHECK-AVX2-NEXT: # kill: def $cl killed $cl killed $rcx ; CHECK-AVX2-NEXT: shlq %cl, %rax ; CHECK-AVX2-NEXT: testq %rax, %rax -; CHECK-AVX2-NEXT: js .LBB24_1 -; CHECK-AVX2-NEXT: # %bb.2: +; CHECK-AVX2-NEXT: js .LBB24_2 +; CHECK-AVX2-NEXT: # %bb.1: ; CHECK-AVX2-NEXT: vcvtsi2ss %rax, %xmm15, %xmm0 ; CHECK-AVX2-NEXT: jmp .LBB24_3 -; CHECK-AVX2-NEXT: .LBB24_1: +; CHECK-AVX2-NEXT: .LBB24_2: ; CHECK-AVX2-NEXT: shrq %rax ; CHECK-AVX2-NEXT: vcvtsi2ss %rax, %xmm15, %xmm0 ; CHECK-AVX2-NEXT: vaddss %xmm0, %xmm0, %xmm0 diff --git a/llvm/test/CodeGen/X86/fold-load.ll b/llvm/test/CodeGen/X86/fold-load.ll index 580278c2a06f2..30662a745d220 100644 --- a/llvm/test/CodeGen/X86/fold-load.ll +++ b/llvm/test/CodeGen/X86/fold-load.ll @@ -9,13 +9,13 @@ define void @test1() nounwind { ; CHECK-LABEL: test1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: testb $1, stmt_obstack+40 -; CHECK-NEXT: jne .LBB0_1 -; CHECK-NEXT: # %bb.2: # %cond_false30.i +; CHECK-NEXT: jne .LBB0_2 +; CHECK-NEXT: # %bb.1: # %cond_false30.i ; CHECK-NEXT: pushl $0 ; CHECK-NEXT: calll 0 ; CHECK-NEXT: addl $4, %esp ; CHECK-NEXT: retl -; CHECK-NEXT: .LBB0_1: # %cond_true23.i +; CHECK-NEXT: .LBB0_2: # %cond_true23.i ; CHECK-NEXT: retl entry: br i1 true, label %cond_true, label %cond_next diff --git a/llvm/test/CodeGen/X86/fold-loop-of-urem.ll b/llvm/test/CodeGen/X86/fold-loop-of-urem.ll index cb1c078ee5129..3dd3c159b9d70 100644 --- a/llvm/test/CodeGen/X86/fold-loop-of-urem.ll +++ b/llvm/test/CodeGen/X86/fold-loop-of-urem.ll @@ -67,22 +67,22 @@ define void @simple_urem_to_sel_fail_not_in_loop(i32 %N, i32 %rem_amt) nounwind ; CHECK-NEXT: pushq %rbx ; CHECK-NEXT: movl %esi, %ebx ; CHECK-NEXT: testl %edi, %edi -; CHECK-NEXT: je .LBB1_1 -; CHECK-NEXT: # %bb.3: # %for.body.preheader +; CHECK-NEXT: je .LBB1_3 +; CHECK-NEXT: # %bb.1: # %for.body.preheader ; CHECK-NEXT: movl %edi, %r14d ; CHECK-NEXT: xorl %ebp, %ebp ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB1_4: # %for.body +; CHECK-NEXT: .LBB1_2: # %for.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: movl %ebp, %edi ; CHECK-NEXT: callq use.i32@PLT ; CHECK-NEXT: incl %ebp ; CHECK-NEXT: cmpl %ebp, %r14d -; CHECK-NEXT: jne .LBB1_4 -; CHECK-NEXT: jmp .LBB1_2 -; CHECK-NEXT: .LBB1_1: +; CHECK-NEXT: jne .LBB1_2 +; CHECK-NEXT: jmp .LBB1_4 +; CHECK-NEXT: .LBB1_3: ; CHECK-NEXT: xorl %ebp, %ebp -; CHECK-NEXT: .LBB1_2: # %for.cond.cleanup +; CHECK-NEXT: .LBB1_4: # %for.cond.cleanup ; CHECK-NEXT: movl %ebp, %eax ; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: divl %ebx @@ -128,10 +128,10 @@ define void @simple_urem_to_sel_inner_loop(i32 %N, i32 %M) nounwind { ; CHECK-NEXT: movl %eax, %r14d ; CHECK-NEXT: xorl %r15d, %r15d ; CHECK-NEXT: xorl %r13d, %r13d -; CHECK-NEXT: jmp .LBB2_2 +; CHECK-NEXT: jmp .LBB2_3 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB2_5: # %for.inner.cond.cleanup -; CHECK-NEXT: # in Loop: Header=BB2_2 Depth=1 +; CHECK-NEXT: .LBB2_2: # %for.inner.cond.cleanup +; CHECK-NEXT: # in Loop: Header=BB2_3 Depth=1 ; CHECK-NEXT: incl %r15d ; CHECK-NEXT: cmpl %r14d, %r15d ; CHECK-NEXT: movl $0, %eax @@ -139,23 +139,23 @@ define void @simple_urem_to_sel_inner_loop(i32 %N, i32 %M) nounwind { ; CHECK-NEXT: incl %r13d ; CHECK-NEXT: cmpl %ebp, %r13d ; CHECK-NEXT: je .LBB2_6 -; CHECK-NEXT: .LBB2_2: # %for.body +; CHECK-NEXT: .LBB2_3: # %for.body ; CHECK-NEXT: # =>This Loop Header: Depth=1 -; CHECK-NEXT: # Child Loop BB2_4 Depth 2 +; CHECK-NEXT: # Child Loop BB2_5 Depth 2 ; CHECK-NEXT: testl %r12d, %r12d -; CHECK-NEXT: je .LBB2_5 -; CHECK-NEXT: # %bb.3: # %for.inner.body.preheader -; CHECK-NEXT: # in Loop: Header=BB2_2 Depth=1 +; CHECK-NEXT: je .LBB2_2 +; CHECK-NEXT: # %bb.4: # %for.inner.body.preheader +; CHECK-NEXT: # in Loop: Header=BB2_3 Depth=1 ; CHECK-NEXT: movl %r12d, %ebx ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB2_4: # %for.inner.body -; CHECK-NEXT: # Parent Loop BB2_2 Depth=1 +; CHECK-NEXT: .LBB2_5: # %for.inner.body +; CHECK-NEXT: # Parent Loop BB2_3 Depth=1 ; CHECK-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-NEXT: movl %r15d, %edi ; CHECK-NEXT: callq use.i32@PLT ; CHECK-NEXT: decl %ebx -; CHECK-NEXT: jne .LBB2_4 -; CHECK-NEXT: jmp .LBB2_5 +; CHECK-NEXT: jne .LBB2_5 +; CHECK-NEXT: jmp .LBB2_2 ; CHECK-NEXT: .LBB2_6: # %for.cond.cleanup ; CHECK-NEXT: addq $8, %rsp ; CHECK-NEXT: popq %rbx @@ -207,26 +207,26 @@ define void @simple_urem_to_sel_inner_loop_fail_not_invariant(i32 %N, i32 %M) no ; CHECK-NEXT: movl %esi, %ebx ; CHECK-NEXT: movl %edi, %ebp ; CHECK-NEXT: xorl %r14d, %r14d -; CHECK-NEXT: jmp .LBB3_2 +; CHECK-NEXT: jmp .LBB3_3 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB3_5: # %for.inner.cond.cleanup -; CHECK-NEXT: # in Loop: Header=BB3_2 Depth=1 +; CHECK-NEXT: .LBB3_2: # %for.inner.cond.cleanup +; CHECK-NEXT: # in Loop: Header=BB3_3 Depth=1 ; CHECK-NEXT: incl %r14d ; CHECK-NEXT: cmpl %ebp, %r14d ; CHECK-NEXT: je .LBB3_6 -; CHECK-NEXT: .LBB3_2: # %for.body +; CHECK-NEXT: .LBB3_3: # %for.body ; CHECK-NEXT: # =>This Loop Header: Depth=1 -; CHECK-NEXT: # Child Loop BB3_4 Depth 2 +; CHECK-NEXT: # Child Loop BB3_5 Depth 2 ; CHECK-NEXT: callq get.i32@PLT ; CHECK-NEXT: testl %ebx, %ebx -; CHECK-NEXT: je .LBB3_5 -; CHECK-NEXT: # %bb.3: # %for.inner.body.preheader -; CHECK-NEXT: # in Loop: Header=BB3_2 Depth=1 +; CHECK-NEXT: je .LBB3_2 +; CHECK-NEXT: # %bb.4: # %for.inner.body.preheader +; CHECK-NEXT: # in Loop: Header=BB3_3 Depth=1 ; CHECK-NEXT: movl %eax, %r15d ; CHECK-NEXT: movl %ebx, %r12d ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB3_4: # %for.inner.body -; CHECK-NEXT: # Parent Loop BB3_2 Depth=1 +; CHECK-NEXT: .LBB3_5: # %for.inner.body +; CHECK-NEXT: # Parent Loop BB3_3 Depth=1 ; CHECK-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-NEXT: movl %r14d, %eax ; CHECK-NEXT: xorl %edx, %edx @@ -234,8 +234,8 @@ define void @simple_urem_to_sel_inner_loop_fail_not_invariant(i32 %N, i32 %M) no ; CHECK-NEXT: movl %edx, %edi ; CHECK-NEXT: callq use.i32@PLT ; CHECK-NEXT: decl %r12d -; CHECK-NEXT: jne .LBB3_4 -; CHECK-NEXT: jmp .LBB3_5 +; CHECK-NEXT: jne .LBB3_5 +; CHECK-NEXT: jmp .LBB3_2 ; CHECK-NEXT: .LBB3_6: ; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %r12 @@ -287,36 +287,36 @@ define void @simple_urem_to_sel_nested2(i32 %N, i32 %rem_amt) nounwind { ; CHECK-NEXT: xorl %r15d, %r15d ; CHECK-NEXT: xorl %r14d, %r14d ; CHECK-NEXT: xorl %r12d, %r12d -; CHECK-NEXT: jmp .LBB4_2 +; CHECK-NEXT: jmp .LBB4_4 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB4_5: # %for.body1 -; CHECK-NEXT: # in Loop: Header=BB4_2 Depth=1 +; CHECK-NEXT: .LBB4_2: # %for.body1 +; CHECK-NEXT: # in Loop: Header=BB4_4 Depth=1 ; CHECK-NEXT: movl %r14d, %edi ; CHECK-NEXT: callq use.i32@PLT -; CHECK-NEXT: .LBB4_6: # %for.body.tail -; CHECK-NEXT: # in Loop: Header=BB4_2 Depth=1 +; CHECK-NEXT: .LBB4_3: # %for.body.tail +; CHECK-NEXT: # in Loop: Header=BB4_4 Depth=1 ; CHECK-NEXT: incl %r14d ; CHECK-NEXT: cmpl %ebx, %r14d ; CHECK-NEXT: cmovel %r15d, %r14d ; CHECK-NEXT: incl %r12d ; CHECK-NEXT: cmpl %r12d, %ebp ; CHECK-NEXT: je .LBB4_7 -; CHECK-NEXT: .LBB4_2: # %for.body +; CHECK-NEXT: .LBB4_4: # %for.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: callq get.i1@PLT ; CHECK-NEXT: testb $1, %al -; CHECK-NEXT: je .LBB4_6 -; CHECK-NEXT: # %bb.3: # %for.body0 -; CHECK-NEXT: # in Loop: Header=BB4_2 Depth=1 +; CHECK-NEXT: je .LBB4_3 +; CHECK-NEXT: # %bb.5: # %for.body0 +; CHECK-NEXT: # in Loop: Header=BB4_4 Depth=1 ; CHECK-NEXT: callq get.i1@PLT ; CHECK-NEXT: testb $1, %al -; CHECK-NEXT: jne .LBB4_5 -; CHECK-NEXT: # %bb.4: # %for.body2 -; CHECK-NEXT: # in Loop: Header=BB4_2 Depth=1 +; CHECK-NEXT: jne .LBB4_2 +; CHECK-NEXT: # %bb.6: # %for.body2 +; CHECK-NEXT: # in Loop: Header=BB4_4 Depth=1 ; CHECK-NEXT: callq get.i1@PLT ; CHECK-NEXT: testb $1, %al -; CHECK-NEXT: jne .LBB4_5 -; CHECK-NEXT: jmp .LBB4_6 +; CHECK-NEXT: jne .LBB4_2 +; CHECK-NEXT: jmp .LBB4_3 ; CHECK-NEXT: .LBB4_7: ; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %r12 @@ -362,44 +362,44 @@ define void @simple_urem_fail_bad_incr3(i32 %N, i32 %rem_amt) nounwind { ; CHECK-NEXT: pushq %r14 ; CHECK-NEXT: pushq %rbx ; CHECK-NEXT: movl %esi, %ebx -; CHECK-NEXT: jmp .LBB5_2 +; CHECK-NEXT: jmp .LBB5_4 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB5_6: # %for.body1 -; CHECK-NEXT: # in Loop: Header=BB5_2 Depth=1 +; CHECK-NEXT: .LBB5_2: # %for.body1 +; CHECK-NEXT: # in Loop: Header=BB5_4 Depth=1 ; CHECK-NEXT: movl %ebp, %eax ; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: divl %ebx ; CHECK-NEXT: movl %edx, %edi ; CHECK-NEXT: callq use.i32@PLT -; CHECK-NEXT: .LBB5_7: # %for.body.tail -; CHECK-NEXT: # in Loop: Header=BB5_2 Depth=1 +; CHECK-NEXT: .LBB5_3: # %for.body.tail +; CHECK-NEXT: # in Loop: Header=BB5_4 Depth=1 ; CHECK-NEXT: callq get.i1@PLT ; CHECK-NEXT: testb $1, %al ; CHECK-NEXT: jne .LBB5_8 -; CHECK-NEXT: .LBB5_2: # %for.body +; CHECK-NEXT: .LBB5_4: # %for.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: callq get.i1@PLT ; CHECK-NEXT: testb $1, %al -; CHECK-NEXT: je .LBB5_5 -; CHECK-NEXT: # %bb.3: # %for.body0 -; CHECK-NEXT: # in Loop: Header=BB5_2 Depth=1 +; CHECK-NEXT: je .LBB5_7 +; CHECK-NEXT: # %bb.5: # %for.body0 +; CHECK-NEXT: # in Loop: Header=BB5_4 Depth=1 ; CHECK-NEXT: callq get.i1@PLT ; CHECK-NEXT: movl %eax, %r14d ; CHECK-NEXT: callq get.i32@PLT ; CHECK-NEXT: testb $1, %r14b -; CHECK-NEXT: je .LBB5_7 -; CHECK-NEXT: # %bb.4: # in Loop: Header=BB5_2 Depth=1 +; CHECK-NEXT: je .LBB5_3 +; CHECK-NEXT: # %bb.6: # in Loop: Header=BB5_4 Depth=1 ; CHECK-NEXT: movl %eax, %ebp ; CHECK-NEXT: incl %ebp -; CHECK-NEXT: jmp .LBB5_6 +; CHECK-NEXT: jmp .LBB5_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB5_5: # %for.body2 -; CHECK-NEXT: # in Loop: Header=BB5_2 Depth=1 +; CHECK-NEXT: .LBB5_7: # %for.body2 +; CHECK-NEXT: # in Loop: Header=BB5_4 Depth=1 ; CHECK-NEXT: xorl %ebp, %ebp ; CHECK-NEXT: callq get.i1@PLT ; CHECK-NEXT: testb $1, %al -; CHECK-NEXT: jne .LBB5_6 -; CHECK-NEXT: jmp .LBB5_7 +; CHECK-NEXT: jne .LBB5_2 +; CHECK-NEXT: jmp .LBB5_3 ; CHECK-NEXT: .LBB5_8: ; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %r14 @@ -495,10 +495,10 @@ define void @simple_urem_fail_bad_incr(i32 %N, i32 %rem_amt) nounwind { ; CHECK-NEXT: movl %esi, %ebx ; CHECK-NEXT: movl %edi, %ebp ; CHECK-NEXT: xorl %r14d, %r14d -; CHECK-NEXT: jmp .LBB7_2 +; CHECK-NEXT: jmp .LBB7_3 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB7_4: # %for.body.tail -; CHECK-NEXT: # in Loop: Header=BB7_2 Depth=1 +; CHECK-NEXT: .LBB7_2: # %for.body.tail +; CHECK-NEXT: # in Loop: Header=BB7_3 Depth=1 ; CHECK-NEXT: movl %r14d, %eax ; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: divl %ebx @@ -507,16 +507,16 @@ define void @simple_urem_fail_bad_incr(i32 %N, i32 %rem_amt) nounwind { ; CHECK-NEXT: incl %r14d ; CHECK-NEXT: cmpl %ebp, %r14d ; CHECK-NEXT: je .LBB7_5 -; CHECK-NEXT: .LBB7_2: # %for.body +; CHECK-NEXT: .LBB7_3: # %for.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: callq get.i1@PLT ; CHECK-NEXT: testb $1, %al -; CHECK-NEXT: je .LBB7_4 -; CHECK-NEXT: # %bb.3: # %for.body0 -; CHECK-NEXT: # in Loop: Header=BB7_2 Depth=1 +; CHECK-NEXT: je .LBB7_2 +; CHECK-NEXT: # %bb.4: # %for.body0 +; CHECK-NEXT: # in Loop: Header=BB7_3 Depth=1 ; CHECK-NEXT: callq get.i32@PLT ; CHECK-NEXT: movl %eax, %r14d -; CHECK-NEXT: jmp .LBB7_4 +; CHECK-NEXT: jmp .LBB7_2 ; CHECK-NEXT: .LBB7_5: ; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %r14 @@ -843,11 +843,11 @@ define void @simple_urem_fail_no_preheader_non_canonical(i32 %N, i32 %rem_amt) n ; CHECK-NEXT: movl %esi, %ebx ; CHECK-NEXT: movl %edi, %ebp ; CHECK-NEXT: testl %edi, %edi -; CHECK-NEXT: je .LBB14_1 -; CHECK-NEXT: # %bb.2: # %for.body1 +; CHECK-NEXT: je .LBB14_2 +; CHECK-NEXT: # %bb.1: # %for.body1 ; CHECK-NEXT: movl $1, %r14d ; CHECK-NEXT: jmp .LBB14_3 -; CHECK-NEXT: .LBB14_1: +; CHECK-NEXT: .LBB14_2: ; CHECK-NEXT: xorl %r14d, %r14d ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .LBB14_3: # %for.body @@ -906,15 +906,15 @@ define void @simple_urem_multi_latch_non_canonical(i32 %N, i32 %rem_amt) nounwin ; CHECK-NEXT: xorl %r12d, %r12d ; CHECK-NEXT: xorl %r14d, %r14d ; CHECK-NEXT: xorl %r13d, %r13d -; CHECK-NEXT: jmp .LBB15_2 +; CHECK-NEXT: jmp .LBB15_3 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB15_3: # %for.body.backedge -; CHECK-NEXT: # in Loop: Header=BB15_2 Depth=1 +; CHECK-NEXT: .LBB15_2: # %for.body.backedge +; CHECK-NEXT: # in Loop: Header=BB15_3 Depth=1 ; CHECK-NEXT: incl %r14d ; CHECK-NEXT: cmpl %ebx, %r14d ; CHECK-NEXT: cmovel %r12d, %r14d ; CHECK-NEXT: incl %r13d -; CHECK-NEXT: .LBB15_2: # %for.body +; CHECK-NEXT: .LBB15_3: # %for.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: movl %r14d, %edi ; CHECK-NEXT: callq use.i32@PLT @@ -922,12 +922,12 @@ define void @simple_urem_multi_latch_non_canonical(i32 %N, i32 %rem_amt) nounwin ; CHECK-NEXT: movl %eax, %r15d ; CHECK-NEXT: callq do_stuff0@PLT ; CHECK-NEXT: testb $1, %r15b -; CHECK-NEXT: je .LBB15_3 +; CHECK-NEXT: je .LBB15_2 ; CHECK-NEXT: # %bb.4: # %for.body0 -; CHECK-NEXT: # in Loop: Header=BB15_2 Depth=1 +; CHECK-NEXT: # in Loop: Header=BB15_3 Depth=1 ; CHECK-NEXT: callq do_stuff1@PLT ; CHECK-NEXT: cmpl %r13d, %ebp -; CHECK-NEXT: jne .LBB15_3 +; CHECK-NEXT: jne .LBB15_2 ; CHECK-NEXT: # %bb.5: ; CHECK-NEXT: addq $8, %rsp ; CHECK-NEXT: popq %rbx diff --git a/llvm/test/CodeGen/X86/fp-int-fp-cvt.ll b/llvm/test/CodeGen/X86/fp-int-fp-cvt.ll index c49676233f7c6..60c90d48e0c90 100644 --- a/llvm/test/CodeGen/X86/fp-int-fp-cvt.ll +++ b/llvm/test/CodeGen/X86/fp-int-fp-cvt.ll @@ -277,12 +277,12 @@ define float @ucvtf32_i64(float %a0) { ; SSE-NEXT: cvttss2si %xmm0, %rax ; SSE-NEXT: andq %rdx, %rax ; SSE-NEXT: orq %rcx, %rax -; SSE-NEXT: js .LBB7_1 -; SSE-NEXT: # %bb.2: +; SSE-NEXT: js .LBB7_2 +; SSE-NEXT: # %bb.1: ; SSE-NEXT: xorps %xmm0, %xmm0 ; SSE-NEXT: cvtsi2ss %rax, %xmm0 ; SSE-NEXT: retq -; SSE-NEXT: .LBB7_1: +; SSE-NEXT: .LBB7_2: ; SSE-NEXT: movq %rax, %rcx ; SSE-NEXT: shrq %rcx ; SSE-NEXT: andl $1, %eax @@ -301,11 +301,11 @@ define float @ucvtf32_i64(float %a0) { ; AVX2-NEXT: vcvttss2si %xmm0, %rax ; AVX2-NEXT: andq %rdx, %rax ; AVX2-NEXT: orq %rcx, %rax -; AVX2-NEXT: js .LBB7_1 -; AVX2-NEXT: # %bb.2: +; AVX2-NEXT: js .LBB7_2 +; AVX2-NEXT: # %bb.1: ; AVX2-NEXT: vcvtsi2ss %rax, %xmm15, %xmm0 ; AVX2-NEXT: retq -; AVX2-NEXT: .LBB7_1: +; AVX2-NEXT: .LBB7_2: ; AVX2-NEXT: movq %rax, %rcx ; AVX2-NEXT: shrq %rcx ; AVX2-NEXT: andl $1, %eax diff --git a/llvm/test/CodeGen/X86/fp-strict-scalar-cmp-fp16.ll b/llvm/test/CodeGen/X86/fp-strict-scalar-cmp-fp16.ll index 6a6b86e8efa7c..80bb410164fcd 100644 --- a/llvm/test/CodeGen/X86/fp-strict-scalar-cmp-fp16.ll +++ b/llvm/test/CodeGen/X86/fp-strict-scalar-cmp-fp16.ll @@ -1757,11 +1757,11 @@ define void @foo(half %0, half %1) #0 { ; SSE2-NEXT: # xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: callq __extendhfsf2@PLT ; SSE2-NEXT: ucomiss (%rsp), %xmm0 # 4-byte Folded Reload -; SSE2-NEXT: jbe .LBB28_1 -; SSE2-NEXT: # %bb.2: +; SSE2-NEXT: jbe .LBB28_2 +; SSE2-NEXT: # %bb.1: ; SSE2-NEXT: popq %rax ; SSE2-NEXT: jmp bar@PLT # TAILCALL -; SSE2-NEXT: .LBB28_1: +; SSE2-NEXT: .LBB28_2: ; SSE2-NEXT: popq %rax ; SSE2-NEXT: retq ; diff --git a/llvm/test/CodeGen/X86/fp-strict-scalar-cmp.ll b/llvm/test/CodeGen/X86/fp-strict-scalar-cmp.ll index e3e2b6225a7ba..751d34596d9ef 100644 --- a/llvm/test/CodeGen/X86/fp-strict-scalar-cmp.ll +++ b/llvm/test/CodeGen/X86/fp-strict-scalar-cmp.ll @@ -130,12 +130,12 @@ define i32 @test_f32_ogt_q(i32 %a, i32 %b, float %f1, float %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: ja .LBB1_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: ja .LBB1_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB1_1: +; X87-NEXT: .LBB1_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -203,12 +203,12 @@ define i32 @test_f32_oge_q(i32 %a, i32 %b, float %f1, float %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: jae .LBB2_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: jae .LBB2_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB2_1: +; X87-NEXT: .LBB2_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -276,12 +276,12 @@ define i32 @test_f32_olt_q(i32 %a, i32 %b, float %f1, float %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: ja .LBB3_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: ja .LBB3_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB3_1: +; X87-NEXT: .LBB3_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -349,12 +349,12 @@ define i32 @test_f32_ole_q(i32 %a, i32 %b, float %f1, float %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: jae .LBB4_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: jae .LBB4_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB4_1: +; X87-NEXT: .LBB4_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -422,12 +422,12 @@ define i32 @test_f32_one_q(i32 %a, i32 %b, float %f1, float %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: jne .LBB5_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: jne .LBB5_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB5_1: +; X87-NEXT: .LBB5_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -495,12 +495,12 @@ define i32 @test_f32_ord_q(i32 %a, i32 %b, float %f1, float %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: jnp .LBB6_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: jnp .LBB6_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB6_1: +; X87-NEXT: .LBB6_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -568,12 +568,12 @@ define i32 @test_f32_ueq_q(i32 %a, i32 %b, float %f1, float %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: je .LBB7_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: je .LBB7_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB7_1: +; X87-NEXT: .LBB7_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -641,12 +641,12 @@ define i32 @test_f32_ugt_q(i32 %a, i32 %b, float %f1, float %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: jb .LBB8_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: jb .LBB8_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB8_1: +; X87-NEXT: .LBB8_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -714,12 +714,12 @@ define i32 @test_f32_uge_q(i32 %a, i32 %b, float %f1, float %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: jbe .LBB9_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: jbe .LBB9_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB9_1: +; X87-NEXT: .LBB9_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -787,12 +787,12 @@ define i32 @test_f32_ult_q(i32 %a, i32 %b, float %f1, float %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: jb .LBB10_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: jb .LBB10_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB10_1: +; X87-NEXT: .LBB10_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -860,12 +860,12 @@ define i32 @test_f32_ule_q(i32 %a, i32 %b, float %f1, float %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: jbe .LBB11_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: jbe .LBB11_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB11_1: +; X87-NEXT: .LBB11_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -1011,12 +1011,12 @@ define i32 @test_f32_uno_q(i32 %a, i32 %b, float %f1, float %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: jp .LBB13_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: jp .LBB13_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB13_1: +; X87-NEXT: .LBB13_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -1162,12 +1162,12 @@ define i32 @test_f64_ogt_q(i32 %a, i32 %b, double %f1, double %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: ja .LBB15_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: ja .LBB15_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB15_1: +; X87-NEXT: .LBB15_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -1235,12 +1235,12 @@ define i32 @test_f64_oge_q(i32 %a, i32 %b, double %f1, double %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: jae .LBB16_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: jae .LBB16_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB16_1: +; X87-NEXT: .LBB16_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -1308,12 +1308,12 @@ define i32 @test_f64_olt_q(i32 %a, i32 %b, double %f1, double %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: ja .LBB17_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: ja .LBB17_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB17_1: +; X87-NEXT: .LBB17_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -1381,12 +1381,12 @@ define i32 @test_f64_ole_q(i32 %a, i32 %b, double %f1, double %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: jae .LBB18_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: jae .LBB18_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB18_1: +; X87-NEXT: .LBB18_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -1454,12 +1454,12 @@ define i32 @test_f64_one_q(i32 %a, i32 %b, double %f1, double %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: jne .LBB19_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: jne .LBB19_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB19_1: +; X87-NEXT: .LBB19_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -1527,12 +1527,12 @@ define i32 @test_f64_ord_q(i32 %a, i32 %b, double %f1, double %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: jnp .LBB20_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: jnp .LBB20_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB20_1: +; X87-NEXT: .LBB20_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -1600,12 +1600,12 @@ define i32 @test_f64_ueq_q(i32 %a, i32 %b, double %f1, double %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: je .LBB21_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: je .LBB21_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB21_1: +; X87-NEXT: .LBB21_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -1673,12 +1673,12 @@ define i32 @test_f64_ugt_q(i32 %a, i32 %b, double %f1, double %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: jb .LBB22_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: jb .LBB22_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB22_1: +; X87-NEXT: .LBB22_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -1746,12 +1746,12 @@ define i32 @test_f64_uge_q(i32 %a, i32 %b, double %f1, double %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: jbe .LBB23_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: jbe .LBB23_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB23_1: +; X87-NEXT: .LBB23_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -1819,12 +1819,12 @@ define i32 @test_f64_ult_q(i32 %a, i32 %b, double %f1, double %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: jb .LBB24_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: jb .LBB24_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB24_1: +; X87-NEXT: .LBB24_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -1892,12 +1892,12 @@ define i32 @test_f64_ule_q(i32 %a, i32 %b, double %f1, double %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: jbe .LBB25_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: jbe .LBB25_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB25_1: +; X87-NEXT: .LBB25_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -2043,12 +2043,12 @@ define i32 @test_f64_uno_q(i32 %a, i32 %b, double %f1, double %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: jp .LBB27_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: jp .LBB27_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB27_1: +; X87-NEXT: .LBB27_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -2194,12 +2194,12 @@ define i32 @test_f32_ogt_s(i32 %a, i32 %b, float %f1, float %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: ja .LBB29_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: ja .LBB29_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB29_1: +; X87-NEXT: .LBB29_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -2267,12 +2267,12 @@ define i32 @test_f32_oge_s(i32 %a, i32 %b, float %f1, float %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: jae .LBB30_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: jae .LBB30_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB30_1: +; X87-NEXT: .LBB30_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -2340,12 +2340,12 @@ define i32 @test_f32_olt_s(i32 %a, i32 %b, float %f1, float %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: ja .LBB31_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: ja .LBB31_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB31_1: +; X87-NEXT: .LBB31_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -2413,12 +2413,12 @@ define i32 @test_f32_ole_s(i32 %a, i32 %b, float %f1, float %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: jae .LBB32_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: jae .LBB32_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB32_1: +; X87-NEXT: .LBB32_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -2486,12 +2486,12 @@ define i32 @test_f32_one_s(i32 %a, i32 %b, float %f1, float %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: jne .LBB33_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: jne .LBB33_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB33_1: +; X87-NEXT: .LBB33_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -2559,12 +2559,12 @@ define i32 @test_f32_ord_s(i32 %a, i32 %b, float %f1, float %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: jnp .LBB34_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: jnp .LBB34_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB34_1: +; X87-NEXT: .LBB34_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -2632,12 +2632,12 @@ define i32 @test_f32_ueq_s(i32 %a, i32 %b, float %f1, float %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: je .LBB35_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: je .LBB35_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB35_1: +; X87-NEXT: .LBB35_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -2705,12 +2705,12 @@ define i32 @test_f32_ugt_s(i32 %a, i32 %b, float %f1, float %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: jb .LBB36_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: jb .LBB36_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB36_1: +; X87-NEXT: .LBB36_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -2778,12 +2778,12 @@ define i32 @test_f32_uge_s(i32 %a, i32 %b, float %f1, float %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: jbe .LBB37_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: jbe .LBB37_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB37_1: +; X87-NEXT: .LBB37_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -2851,12 +2851,12 @@ define i32 @test_f32_ult_s(i32 %a, i32 %b, float %f1, float %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: jb .LBB38_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: jb .LBB38_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB38_1: +; X87-NEXT: .LBB38_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -2924,12 +2924,12 @@ define i32 @test_f32_ule_s(i32 %a, i32 %b, float %f1, float %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: jbe .LBB39_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: jbe .LBB39_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB39_1: +; X87-NEXT: .LBB39_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -3075,12 +3075,12 @@ define i32 @test_f32_uno_s(i32 %a, i32 %b, float %f1, float %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: jp .LBB41_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: jp .LBB41_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB41_1: +; X87-NEXT: .LBB41_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -3226,12 +3226,12 @@ define i32 @test_f64_ogt_s(i32 %a, i32 %b, double %f1, double %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: ja .LBB43_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: ja .LBB43_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB43_1: +; X87-NEXT: .LBB43_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -3299,12 +3299,12 @@ define i32 @test_f64_oge_s(i32 %a, i32 %b, double %f1, double %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: jae .LBB44_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: jae .LBB44_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB44_1: +; X87-NEXT: .LBB44_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -3372,12 +3372,12 @@ define i32 @test_f64_olt_s(i32 %a, i32 %b, double %f1, double %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: ja .LBB45_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: ja .LBB45_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB45_1: +; X87-NEXT: .LBB45_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -3445,12 +3445,12 @@ define i32 @test_f64_ole_s(i32 %a, i32 %b, double %f1, double %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: jae .LBB46_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: jae .LBB46_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB46_1: +; X87-NEXT: .LBB46_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -3518,12 +3518,12 @@ define i32 @test_f64_one_s(i32 %a, i32 %b, double %f1, double %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: jne .LBB47_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: jne .LBB47_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB47_1: +; X87-NEXT: .LBB47_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -3591,12 +3591,12 @@ define i32 @test_f64_ord_s(i32 %a, i32 %b, double %f1, double %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: jnp .LBB48_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: jnp .LBB48_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB48_1: +; X87-NEXT: .LBB48_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -3664,12 +3664,12 @@ define i32 @test_f64_ueq_s(i32 %a, i32 %b, double %f1, double %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: je .LBB49_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: je .LBB49_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB49_1: +; X87-NEXT: .LBB49_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -3737,12 +3737,12 @@ define i32 @test_f64_ugt_s(i32 %a, i32 %b, double %f1, double %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: jb .LBB50_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: jb .LBB50_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB50_1: +; X87-NEXT: .LBB50_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -3810,12 +3810,12 @@ define i32 @test_f64_uge_s(i32 %a, i32 %b, double %f1, double %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: jbe .LBB51_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: jbe .LBB51_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB51_1: +; X87-NEXT: .LBB51_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -3883,12 +3883,12 @@ define i32 @test_f64_ult_s(i32 %a, i32 %b, double %f1, double %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: jb .LBB52_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: jb .LBB52_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB52_1: +; X87-NEXT: .LBB52_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -3956,12 +3956,12 @@ define i32 @test_f64_ule_s(i32 %a, i32 %b, double %f1, double %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: jbe .LBB53_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: jbe .LBB53_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB53_1: +; X87-NEXT: .LBB53_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl @@ -4107,12 +4107,12 @@ define i32 @test_f64_uno_s(i32 %a, i32 %b, double %f1, double %f2) #0 { ; X87-NEXT: fnstsw %ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: sahf -; X87-NEXT: jp .LBB55_1 -; X87-NEXT: # %bb.2: +; X87-NEXT: jp .LBB55_2 +; X87-NEXT: # %bb.1: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl -; X87-NEXT: .LBB55_1: +; X87-NEXT: .LBB55_2: ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl (%eax), %eax ; X87-NEXT: retl diff --git a/llvm/test/CodeGen/X86/fp-une-cmp.ll b/llvm/test/CodeGen/X86/fp-une-cmp.ll index dd32f23d3b9cb..088f86a122834 100644 --- a/llvm/test/CodeGen/X86/fp-une-cmp.ll +++ b/llvm/test/CodeGen/X86/fp-une-cmp.ll @@ -54,11 +54,11 @@ define double @profile_metadata(double %x, double %y) { ; CHECK-NEXT: mulsd %xmm1, %xmm0 ; CHECK-NEXT: xorpd %xmm1, %xmm1 ; CHECK-NEXT: ucomisd %xmm1, %xmm0 -; CHECK-NEXT: jne .LBB1_1 -; CHECK-NEXT: jp .LBB1_1 -; CHECK-NEXT: # %bb.2: # %bb2 +; CHECK-NEXT: jne .LBB1_2 +; CHECK-NEXT: jp .LBB1_2 +; CHECK-NEXT: # %bb.1: # %bb2 ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB1_1: # %bb1 +; CHECK-NEXT: .LBB1_2: # %bb1 ; CHECK-NEXT: addsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; CHECK-NEXT: retq @@ -84,11 +84,11 @@ define void @foo(float %f) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xorps %xmm1, %xmm1 ; CHECK-NEXT: ucomiss %xmm1, %xmm0 -; CHECK-NEXT: jne .LBB2_2 -; CHECK-NEXT: jnp .LBB2_1 -; CHECK-NEXT: .LBB2_2: # %if.then +; CHECK-NEXT: jne .LBB2_1 +; CHECK-NEXT: jnp .LBB2_2 +; CHECK-NEXT: .LBB2_1: # %if.then ; CHECK-NEXT: jmp a # TAILCALL -; CHECK-NEXT: .LBB2_1: # %if.end +; CHECK-NEXT: .LBB2_2: # %if.end ; CHECK-NEXT: retq entry: %cmp = fcmp une float %f, 0.000000e+00 @@ -108,21 +108,21 @@ define void @pr27750(ptr %b, float %x, i1 %y) { ; CHECK-LABEL: pr27750: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xorps %xmm1, %xmm1 -; CHECK-NEXT: jmp .LBB3_1 +; CHECK-NEXT: jmp .LBB3_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB3_3: # %for.end -; CHECK-NEXT: # in Loop: Header=BB3_1 Depth=1 +; CHECK-NEXT: .LBB3_1: # %for.end +; CHECK-NEXT: # in Loop: Header=BB3_2 Depth=1 ; CHECK-NEXT: ucomiss %xmm1, %xmm0 -; CHECK-NEXT: jne .LBB3_1 -; CHECK-NEXT: jp .LBB3_1 -; CHECK-NEXT: .LBB3_1: # %for.cond1 +; CHECK-NEXT: jne .LBB3_2 +; CHECK-NEXT: jp .LBB3_2 +; CHECK-NEXT: .LBB3_2: # %for.cond1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: testb $1, %sil -; CHECK-NEXT: je .LBB3_3 -; CHECK-NEXT: # %bb.2: # %for.body3.lr.ph -; CHECK-NEXT: # in Loop: Header=BB3_1 Depth=1 +; CHECK-NEXT: je .LBB3_1 +; CHECK-NEXT: # %bb.3: # %for.body3.lr.ph +; CHECK-NEXT: # in Loop: Header=BB3_2 Depth=1 ; CHECK-NEXT: movl $0, (%rdi) -; CHECK-NEXT: jmp .LBB3_3 +; CHECK-NEXT: jmp .LBB3_1 entry: br label %for.cond diff --git a/llvm/test/CodeGen/X86/fp128-i128.ll b/llvm/test/CodeGen/X86/fp128-i128.ll index 338950ac4c350..bbd322d9e8585 100644 --- a/llvm/test/CodeGen/X86/fp128-i128.ll +++ b/llvm/test/CodeGen/X86/fp128-i128.ll @@ -445,13 +445,13 @@ define dso_local void @TestCopySign(ptr noalias nocapture sret({ fp128, fp128 }) ; SSE-NEXT: movaps %xmm0, %xmm1 ; SSE-NEXT: callq __subtf3@PLT ; SSE-NEXT: testl %ebp, %ebp -; SSE-NEXT: jle .LBB10_1 -; SSE-NEXT: # %bb.2: # %if.then +; SSE-NEXT: jle .LBB10_2 +; SSE-NEXT: # %bb.1: # %if.then ; SSE-NEXT: movaps %xmm0, %xmm1 ; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload ; SSE-NEXT: jmp .LBB10_3 -; SSE-NEXT: .LBB10_1: +; SSE-NEXT: .LBB10_2: ; SSE-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload ; SSE-NEXT: .LBB10_3: # %cleanup ; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload @@ -482,12 +482,12 @@ define dso_local void @TestCopySign(ptr noalias nocapture sret({ fp128, fp128 }) ; AVX-NEXT: vmovaps %xmm0, %xmm1 ; AVX-NEXT: callq __subtf3@PLT ; AVX-NEXT: testl %ebp, %ebp -; AVX-NEXT: jle .LBB10_1 -; AVX-NEXT: # %bb.2: # %if.then +; AVX-NEXT: jle .LBB10_2 +; AVX-NEXT: # %bb.1: # %if.then ; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2 ; AVX-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload ; AVX-NEXT: jmp .LBB10_3 -; AVX-NEXT: .LBB10_1: +; AVX-NEXT: .LBB10_2: ; AVX-NEXT: vmovaps (%rsp), %xmm2 # 16-byte Reload ; AVX-NEXT: .LBB10_3: # %cleanup ; AVX-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload diff --git a/llvm/test/CodeGen/X86/fp128-libcalls-strict.ll b/llvm/test/CodeGen/X86/fp128-libcalls-strict.ll index ad2d690fd7ed0..5f410b3f21e32 100644 --- a/llvm/test/CodeGen/X86/fp128-libcalls-strict.ll +++ b/llvm/test/CodeGen/X86/fp128-libcalls-strict.ll @@ -3633,11 +3633,11 @@ define i64 @cmp(i64 %a, i64 %b, fp128 %x, fp128 %y) #0 { ; WIN-X86-NEXT: calll ___eqtf2 ; WIN-X86-NEXT: addl $32, %esp ; WIN-X86-NEXT: testl %eax, %eax -; WIN-X86-NEXT: je LBB37_1 -; WIN-X86-NEXT: # %bb.2: +; WIN-X86-NEXT: je LBB37_2 +; WIN-X86-NEXT: # %bb.1: ; WIN-X86-NEXT: leal 16(%ebp), %ecx ; WIN-X86-NEXT: jmp LBB37_3 -; WIN-X86-NEXT: LBB37_1: +; WIN-X86-NEXT: LBB37_2: ; WIN-X86-NEXT: leal 8(%ebp), %ecx ; WIN-X86-NEXT: LBB37_3: ; WIN-X86-NEXT: movl (%ecx), %eax @@ -3763,11 +3763,11 @@ define i64 @cmps(i64 %a, i64 %b, fp128 %x, fp128 %y) #0 { ; WIN-X86-NEXT: calll ___eqtf2 ; WIN-X86-NEXT: addl $32, %esp ; WIN-X86-NEXT: testl %eax, %eax -; WIN-X86-NEXT: je LBB38_1 -; WIN-X86-NEXT: # %bb.2: +; WIN-X86-NEXT: je LBB38_2 +; WIN-X86-NEXT: # %bb.1: ; WIN-X86-NEXT: leal 16(%ebp), %ecx ; WIN-X86-NEXT: jmp LBB38_3 -; WIN-X86-NEXT: LBB38_1: +; WIN-X86-NEXT: LBB38_2: ; WIN-X86-NEXT: leal 8(%ebp), %ecx ; WIN-X86-NEXT: LBB38_3: ; WIN-X86-NEXT: movl (%ecx), %eax @@ -3981,11 +3981,11 @@ define i64 @cmp_ueq_q(i64 %a, i64 %b, fp128 %x, fp128 %y) #0 { ; WIN-X86-NEXT: calll ___unordtf2 ; WIN-X86-NEXT: addl $32, %esp ; WIN-X86-NEXT: orb %bl, %al -; WIN-X86-NEXT: jne LBB39_1 -; WIN-X86-NEXT: # %bb.2: +; WIN-X86-NEXT: jne LBB39_2 +; WIN-X86-NEXT: # %bb.1: ; WIN-X86-NEXT: leal 16(%ebp), %ecx ; WIN-X86-NEXT: jmp LBB39_3 -; WIN-X86-NEXT: LBB39_1: +; WIN-X86-NEXT: LBB39_2: ; WIN-X86-NEXT: leal 8(%ebp), %ecx ; WIN-X86-NEXT: LBB39_3: ; WIN-X86-NEXT: movl (%ecx), %eax @@ -4206,11 +4206,11 @@ define i64 @cmp_one_q(i64 %a, i64 %b, fp128 %x, fp128 %y) #0 { ; WIN-X86-NEXT: testl %eax, %eax ; WIN-X86-NEXT: sete %al ; WIN-X86-NEXT: testb %bl, %al -; WIN-X86-NEXT: jne LBB40_1 -; WIN-X86-NEXT: # %bb.2: +; WIN-X86-NEXT: jne LBB40_2 +; WIN-X86-NEXT: # %bb.1: ; WIN-X86-NEXT: leal 16(%ebp), %ecx ; WIN-X86-NEXT: jmp LBB40_3 -; WIN-X86-NEXT: LBB40_1: +; WIN-X86-NEXT: LBB40_2: ; WIN-X86-NEXT: leal 8(%ebp), %ecx ; WIN-X86-NEXT: LBB40_3: ; WIN-X86-NEXT: movl (%ecx), %eax diff --git a/llvm/test/CodeGen/X86/fp128-select.ll b/llvm/test/CodeGen/X86/fp128-select.ll index 27a651e23f886..a2dcb02dadc32 100644 --- a/llvm/test/CodeGen/X86/fp128-select.ll +++ b/llvm/test/CodeGen/X86/fp128-select.ll @@ -12,12 +12,12 @@ define void @test_select(ptr %p, ptr %q, i1 zeroext %c) nounwind { ; SSE-LABEL: test_select: ; SSE: # %bb.0: ; SSE-NEXT: testl %edx, %edx -; SSE-NEXT: jne .LBB0_1 -; SSE-NEXT: # %bb.2: +; SSE-NEXT: jne .LBB0_2 +; SSE-NEXT: # %bb.1: ; SSE-NEXT: movaps {{.*#+}} xmm0 = [NaN] ; SSE-NEXT: movaps %xmm0, (%rsi) ; SSE-NEXT: retq -; SSE-NEXT: .LBB0_1: +; SSE-NEXT: .LBB0_2: ; SSE-NEXT: movups (%rdi), %xmm0 ; SSE-NEXT: movaps %xmm0, (%rsi) ; SSE-NEXT: retq @@ -53,11 +53,11 @@ define fp128 @test_select_cc(fp128, fp128) nounwind { ; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; SSE-NEXT: callq __eqtf2@PLT ; SSE-NEXT: testl %eax, %eax -; SSE-NEXT: je .LBB1_1 -; SSE-NEXT: # %bb.2: # %BB0 +; SSE-NEXT: je .LBB1_2 +; SSE-NEXT: # %bb.1: # %BB0 ; SSE-NEXT: xorps %xmm1, %xmm1 ; SSE-NEXT: jmp .LBB1_3 -; SSE-NEXT: .LBB1_1: +; SSE-NEXT: .LBB1_2: ; SSE-NEXT: movaps {{.*#+}} xmm1 = [1.0E+0] ; SSE-NEXT: .LBB1_3: # %BB0 ; SSE-NEXT: testl %ebx, %ebx diff --git a/llvm/test/CodeGen/X86/fp80-strict-scalar-cmp.ll b/llvm/test/CodeGen/X86/fp80-strict-scalar-cmp.ll index cb2361fbb8d37..a5a8757303c83 100644 --- a/llvm/test/CodeGen/X86/fp80-strict-scalar-cmp.ll +++ b/llvm/test/CodeGen/X86/fp80-strict-scalar-cmp.ll @@ -50,12 +50,12 @@ define i32 @test_ogt_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 { ; X86-NEXT: fnstsw %ax ; X86-NEXT: # kill: def $ah killed $ah killed $ax ; X86-NEXT: sahf -; X86-NEXT: ja .LBB1_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: ja .LBB1_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB1_1: +; X86-NEXT: .LBB1_2: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl @@ -87,12 +87,12 @@ define i32 @test_oge_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 { ; X86-NEXT: fnstsw %ax ; X86-NEXT: # kill: def $ah killed $ah killed $ax ; X86-NEXT: sahf -; X86-NEXT: jae .LBB2_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: jae .LBB2_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB2_1: +; X86-NEXT: .LBB2_2: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl @@ -124,12 +124,12 @@ define i32 @test_olt_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 { ; X86-NEXT: fnstsw %ax ; X86-NEXT: # kill: def $ah killed $ah killed $ax ; X86-NEXT: sahf -; X86-NEXT: ja .LBB3_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: ja .LBB3_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB3_1: +; X86-NEXT: .LBB3_2: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl @@ -161,12 +161,12 @@ define i32 @test_ole_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 { ; X86-NEXT: fnstsw %ax ; X86-NEXT: # kill: def $ah killed $ah killed $ax ; X86-NEXT: sahf -; X86-NEXT: jae .LBB4_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: jae .LBB4_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB4_1: +; X86-NEXT: .LBB4_2: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl @@ -198,12 +198,12 @@ define i32 @test_one_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 { ; X86-NEXT: fnstsw %ax ; X86-NEXT: # kill: def $ah killed $ah killed $ax ; X86-NEXT: sahf -; X86-NEXT: jne .LBB5_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: jne .LBB5_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB5_1: +; X86-NEXT: .LBB5_2: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl @@ -235,12 +235,12 @@ define i32 @test_ord_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 { ; X86-NEXT: fnstsw %ax ; X86-NEXT: # kill: def $ah killed $ah killed $ax ; X86-NEXT: sahf -; X86-NEXT: jnp .LBB6_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: jnp .LBB6_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB6_1: +; X86-NEXT: .LBB6_2: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl @@ -272,12 +272,12 @@ define i32 @test_ueq_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 { ; X86-NEXT: fnstsw %ax ; X86-NEXT: # kill: def $ah killed $ah killed $ax ; X86-NEXT: sahf -; X86-NEXT: je .LBB7_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: je .LBB7_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB7_1: +; X86-NEXT: .LBB7_2: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl @@ -309,12 +309,12 @@ define i32 @test_ugt_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 { ; X86-NEXT: fnstsw %ax ; X86-NEXT: # kill: def $ah killed $ah killed $ax ; X86-NEXT: sahf -; X86-NEXT: jb .LBB8_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: jb .LBB8_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB8_1: +; X86-NEXT: .LBB8_2: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl @@ -346,12 +346,12 @@ define i32 @test_uge_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 { ; X86-NEXT: fnstsw %ax ; X86-NEXT: # kill: def $ah killed $ah killed $ax ; X86-NEXT: sahf -; X86-NEXT: jbe .LBB9_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: jbe .LBB9_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB9_1: +; X86-NEXT: .LBB9_2: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl @@ -383,12 +383,12 @@ define i32 @test_ult_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 { ; X86-NEXT: fnstsw %ax ; X86-NEXT: # kill: def $ah killed $ah killed $ax ; X86-NEXT: sahf -; X86-NEXT: jb .LBB10_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: jb .LBB10_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB10_1: +; X86-NEXT: .LBB10_2: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl @@ -420,12 +420,12 @@ define i32 @test_ule_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 { ; X86-NEXT: fnstsw %ax ; X86-NEXT: # kill: def $ah killed $ah killed $ax ; X86-NEXT: sahf -; X86-NEXT: jbe .LBB11_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: jbe .LBB11_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB11_1: +; X86-NEXT: .LBB11_2: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl @@ -495,12 +495,12 @@ define i32 @test_uno_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 { ; X86-NEXT: fnstsw %ax ; X86-NEXT: # kill: def $ah killed $ah killed $ax ; X86-NEXT: sahf -; X86-NEXT: jp .LBB13_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: jp .LBB13_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB13_1: +; X86-NEXT: .LBB13_2: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl @@ -570,12 +570,12 @@ define i32 @test_ogt_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 { ; X86-NEXT: fnstsw %ax ; X86-NEXT: # kill: def $ah killed $ah killed $ax ; X86-NEXT: sahf -; X86-NEXT: ja .LBB15_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: ja .LBB15_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB15_1: +; X86-NEXT: .LBB15_2: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl @@ -607,12 +607,12 @@ define i32 @test_oge_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 { ; X86-NEXT: fnstsw %ax ; X86-NEXT: # kill: def $ah killed $ah killed $ax ; X86-NEXT: sahf -; X86-NEXT: jae .LBB16_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: jae .LBB16_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB16_1: +; X86-NEXT: .LBB16_2: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl @@ -644,12 +644,12 @@ define i32 @test_olt_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 { ; X86-NEXT: fnstsw %ax ; X86-NEXT: # kill: def $ah killed $ah killed $ax ; X86-NEXT: sahf -; X86-NEXT: ja .LBB17_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: ja .LBB17_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB17_1: +; X86-NEXT: .LBB17_2: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl @@ -681,12 +681,12 @@ define i32 @test_ole_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 { ; X86-NEXT: fnstsw %ax ; X86-NEXT: # kill: def $ah killed $ah killed $ax ; X86-NEXT: sahf -; X86-NEXT: jae .LBB18_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: jae .LBB18_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB18_1: +; X86-NEXT: .LBB18_2: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl @@ -718,12 +718,12 @@ define i32 @test_one_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 { ; X86-NEXT: fnstsw %ax ; X86-NEXT: # kill: def $ah killed $ah killed $ax ; X86-NEXT: sahf -; X86-NEXT: jne .LBB19_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: jne .LBB19_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB19_1: +; X86-NEXT: .LBB19_2: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl @@ -755,12 +755,12 @@ define i32 @test_ord_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 { ; X86-NEXT: fnstsw %ax ; X86-NEXT: # kill: def $ah killed $ah killed $ax ; X86-NEXT: sahf -; X86-NEXT: jnp .LBB20_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: jnp .LBB20_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB20_1: +; X86-NEXT: .LBB20_2: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl @@ -792,12 +792,12 @@ define i32 @test_ueq_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 { ; X86-NEXT: fnstsw %ax ; X86-NEXT: # kill: def $ah killed $ah killed $ax ; X86-NEXT: sahf -; X86-NEXT: je .LBB21_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: je .LBB21_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB21_1: +; X86-NEXT: .LBB21_2: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl @@ -829,12 +829,12 @@ define i32 @test_ugt_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 { ; X86-NEXT: fnstsw %ax ; X86-NEXT: # kill: def $ah killed $ah killed $ax ; X86-NEXT: sahf -; X86-NEXT: jb .LBB22_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: jb .LBB22_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB22_1: +; X86-NEXT: .LBB22_2: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl @@ -866,12 +866,12 @@ define i32 @test_uge_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 { ; X86-NEXT: fnstsw %ax ; X86-NEXT: # kill: def $ah killed $ah killed $ax ; X86-NEXT: sahf -; X86-NEXT: jbe .LBB23_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: jbe .LBB23_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB23_1: +; X86-NEXT: .LBB23_2: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl @@ -903,12 +903,12 @@ define i32 @test_ult_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 { ; X86-NEXT: fnstsw %ax ; X86-NEXT: # kill: def $ah killed $ah killed $ax ; X86-NEXT: sahf -; X86-NEXT: jb .LBB24_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: jb .LBB24_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB24_1: +; X86-NEXT: .LBB24_2: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl @@ -940,12 +940,12 @@ define i32 @test_ule_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 { ; X86-NEXT: fnstsw %ax ; X86-NEXT: # kill: def $ah killed $ah killed $ax ; X86-NEXT: sahf -; X86-NEXT: jbe .LBB25_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: jbe .LBB25_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB25_1: +; X86-NEXT: .LBB25_2: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl @@ -1015,12 +1015,12 @@ define i32 @test_uno_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 { ; X86-NEXT: fnstsw %ax ; X86-NEXT: # kill: def $ah killed $ah killed $ax ; X86-NEXT: sahf -; X86-NEXT: jp .LBB27_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: jp .LBB27_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB27_1: +; X86-NEXT: .LBB27_2: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl diff --git a/llvm/test/CodeGen/X86/fptosi-sat-scalar.ll b/llvm/test/CodeGen/X86/fptosi-sat-scalar.ll index 9b7a43a29a942..810dd56b35ab6 100644 --- a/llvm/test/CodeGen/X86/fptosi-sat-scalar.ll +++ b/llvm/test/CodeGen/X86/fptosi-sat-scalar.ll @@ -877,16 +877,16 @@ define i128 @test_signed_i128_f32(float %f) nounwind { ; X86-X87-NEXT: sahf ; X86-X87-NEXT: movl $0, %eax ; X86-X87-NEXT: movl $0, %ebx -; X86-X87-NEXT: jae .LBB9_1 -; X86-X87-NEXT: # %bb.2: +; X86-X87-NEXT: jae .LBB9_11 +; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: movl $0, %edx -; X86-X87-NEXT: jae .LBB9_3 -; X86-X87-NEXT: .LBB9_4: +; X86-X87-NEXT: jae .LBB9_12 +; X86-X87-NEXT: .LBB9_2: ; X86-X87-NEXT: movl $-2147483648, %ecx # imm = 0x80000000 -; X86-X87-NEXT: jb .LBB9_6 -; X86-X87-NEXT: .LBB9_5: +; X86-X87-NEXT: jb .LBB9_4 +; X86-X87-NEXT: .LBB9_3: ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X86-X87-NEXT: .LBB9_6: +; X86-X87-NEXT: .LBB9_4: ; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} ; X86-X87-NEXT: flds {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload @@ -896,21 +896,21 @@ define i128 @test_signed_i128_f32(float %f) nounwind { ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: sahf ; X86-X87-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF -; X86-X87-NEXT: ja .LBB9_8 -; X86-X87-NEXT: # %bb.7: +; X86-X87-NEXT: ja .LBB9_6 +; X86-X87-NEXT: # %bb.5: ; X86-X87-NEXT: movl %ecx, %eax -; X86-X87-NEXT: .LBB9_8: +; X86-X87-NEXT: .LBB9_6: ; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl $-1, %ebp ; X86-X87-NEXT: movl $-1, %edi ; X86-X87-NEXT: movl $-1, %esi -; X86-X87-NEXT: ja .LBB9_10 -; X86-X87-NEXT: # %bb.9: +; X86-X87-NEXT: ja .LBB9_8 +; X86-X87-NEXT: # %bb.7: ; X86-X87-NEXT: movl %edx, %ebp ; X86-X87-NEXT: movl %ebx, %edi ; X86-X87-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload -; X86-X87-NEXT: .LBB9_10: +; X86-X87-NEXT: .LBB9_8: ; X86-X87-NEXT: fucomp %st(0) ; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax @@ -918,13 +918,13 @@ define i128 @test_signed_i128_f32(float %f) nounwind { ; X86-X87-NEXT: movl $0, %eax ; X86-X87-NEXT: movl $0, %edx ; X86-X87-NEXT: movl $0, %ebx -; X86-X87-NEXT: jp .LBB9_12 -; X86-X87-NEXT: # %bb.11: +; X86-X87-NEXT: jp .LBB9_10 +; X86-X87-NEXT: # %bb.9: ; X86-X87-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-X87-NEXT: movl %edi, %eax ; X86-X87-NEXT: movl %ebp, %edx ; X86-X87-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload -; X86-X87-NEXT: .LBB9_12: +; X86-X87-NEXT: .LBB9_10: ; X86-X87-NEXT: movl %ebx, 12(%ecx) ; X86-X87-NEXT: movl %edx, 8(%ecx) ; X86-X87-NEXT: movl %eax, 4(%ecx) @@ -937,16 +937,16 @@ define i128 @test_signed_i128_f32(float %f) nounwind { ; X86-X87-NEXT: popl %ebx ; X86-X87-NEXT: popl %ebp ; X86-X87-NEXT: retl $4 -; X86-X87-NEXT: .LBB9_1: +; X86-X87-NEXT: .LBB9_11: ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ebx ; X86-X87-NEXT: movl $0, %edx -; X86-X87-NEXT: jb .LBB9_4 -; X86-X87-NEXT: .LBB9_3: +; X86-X87-NEXT: jb .LBB9_2 +; X86-X87-NEXT: .LBB9_12: ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-X87-NEXT: movl $-2147483648, %ecx # imm = 0x80000000 -; X86-X87-NEXT: jae .LBB9_5 -; X86-X87-NEXT: jmp .LBB9_6 +; X86-X87-NEXT: jae .LBB9_3 +; X86-X87-NEXT: jmp .LBB9_4 ; ; X86-SSE-LABEL: test_signed_i128_f32: ; X86-SSE: # %bb.0: @@ -1886,16 +1886,16 @@ define i128 @test_signed_i128_f64(double %f) nounwind { ; X86-X87-NEXT: sahf ; X86-X87-NEXT: movl $0, %eax ; X86-X87-NEXT: movl $0, %ebx -; X86-X87-NEXT: jae .LBB19_1 -; X86-X87-NEXT: # %bb.2: +; X86-X87-NEXT: jae .LBB19_11 +; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: movl $0, %edx -; X86-X87-NEXT: jae .LBB19_3 -; X86-X87-NEXT: .LBB19_4: +; X86-X87-NEXT: jae .LBB19_12 +; X86-X87-NEXT: .LBB19_2: ; X86-X87-NEXT: movl $-2147483648, %ecx # imm = 0x80000000 -; X86-X87-NEXT: jb .LBB19_6 -; X86-X87-NEXT: .LBB19_5: +; X86-X87-NEXT: jb .LBB19_4 +; X86-X87-NEXT: .LBB19_3: ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X86-X87-NEXT: .LBB19_6: +; X86-X87-NEXT: .LBB19_4: ; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-X87-NEXT: fldl {{\.?LCPI[0-9]+_[0-9]+}} ; X86-X87-NEXT: fldl {{[-0-9]+}}(%e{{[sb]}}p) # 8-byte Folded Reload @@ -1905,21 +1905,21 @@ define i128 @test_signed_i128_f64(double %f) nounwind { ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: sahf ; X86-X87-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF -; X86-X87-NEXT: ja .LBB19_8 -; X86-X87-NEXT: # %bb.7: +; X86-X87-NEXT: ja .LBB19_6 +; X86-X87-NEXT: # %bb.5: ; X86-X87-NEXT: movl %ecx, %eax -; X86-X87-NEXT: .LBB19_8: +; X86-X87-NEXT: .LBB19_6: ; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl $-1, %ebp ; X86-X87-NEXT: movl $-1, %edi ; X86-X87-NEXT: movl $-1, %esi -; X86-X87-NEXT: ja .LBB19_10 -; X86-X87-NEXT: # %bb.9: +; X86-X87-NEXT: ja .LBB19_8 +; X86-X87-NEXT: # %bb.7: ; X86-X87-NEXT: movl %edx, %ebp ; X86-X87-NEXT: movl %ebx, %edi ; X86-X87-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload -; X86-X87-NEXT: .LBB19_10: +; X86-X87-NEXT: .LBB19_8: ; X86-X87-NEXT: fucomp %st(0) ; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax @@ -1927,13 +1927,13 @@ define i128 @test_signed_i128_f64(double %f) nounwind { ; X86-X87-NEXT: movl $0, %eax ; X86-X87-NEXT: movl $0, %edx ; X86-X87-NEXT: movl $0, %ebx -; X86-X87-NEXT: jp .LBB19_12 -; X86-X87-NEXT: # %bb.11: +; X86-X87-NEXT: jp .LBB19_10 +; X86-X87-NEXT: # %bb.9: ; X86-X87-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-X87-NEXT: movl %edi, %eax ; X86-X87-NEXT: movl %ebp, %edx ; X86-X87-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload -; X86-X87-NEXT: .LBB19_12: +; X86-X87-NEXT: .LBB19_10: ; X86-X87-NEXT: movl %ebx, 12(%ecx) ; X86-X87-NEXT: movl %edx, 8(%ecx) ; X86-X87-NEXT: movl %eax, 4(%ecx) @@ -1946,16 +1946,16 @@ define i128 @test_signed_i128_f64(double %f) nounwind { ; X86-X87-NEXT: popl %ebx ; X86-X87-NEXT: popl %ebp ; X86-X87-NEXT: retl $4 -; X86-X87-NEXT: .LBB19_1: +; X86-X87-NEXT: .LBB19_11: ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ebx ; X86-X87-NEXT: movl $0, %edx -; X86-X87-NEXT: jb .LBB19_4 -; X86-X87-NEXT: .LBB19_3: +; X86-X87-NEXT: jb .LBB19_2 +; X86-X87-NEXT: .LBB19_12: ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-X87-NEXT: movl $-2147483648, %ecx # imm = 0x80000000 -; X86-X87-NEXT: jae .LBB19_5 -; X86-X87-NEXT: jmp .LBB19_6 +; X86-X87-NEXT: jae .LBB19_3 +; X86-X87-NEXT: jmp .LBB19_4 ; ; X86-SSE-LABEL: test_signed_i128_f64: ; X86-SSE: # %bb.0: @@ -3038,16 +3038,16 @@ define i128 @test_signed_i128_f16(half %f) nounwind { ; X86-X87-NEXT: sahf ; X86-X87-NEXT: movl $0, %eax ; X86-X87-NEXT: movl $0, %ebx -; X86-X87-NEXT: jae .LBB29_1 -; X86-X87-NEXT: # %bb.2: +; X86-X87-NEXT: jae .LBB29_11 +; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: movl $0, %edx -; X86-X87-NEXT: jae .LBB29_3 -; X86-X87-NEXT: .LBB29_4: +; X86-X87-NEXT: jae .LBB29_12 +; X86-X87-NEXT: .LBB29_2: ; X86-X87-NEXT: movl $-2147483648, %ecx # imm = 0x80000000 -; X86-X87-NEXT: jb .LBB29_6 -; X86-X87-NEXT: .LBB29_5: +; X86-X87-NEXT: jb .LBB29_4 +; X86-X87-NEXT: .LBB29_3: ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X86-X87-NEXT: .LBB29_6: +; X86-X87-NEXT: .LBB29_4: ; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} ; X86-X87-NEXT: flds {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload @@ -3057,21 +3057,21 @@ define i128 @test_signed_i128_f16(half %f) nounwind { ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: sahf ; X86-X87-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF -; X86-X87-NEXT: ja .LBB29_8 -; X86-X87-NEXT: # %bb.7: +; X86-X87-NEXT: ja .LBB29_6 +; X86-X87-NEXT: # %bb.5: ; X86-X87-NEXT: movl %ecx, %eax -; X86-X87-NEXT: .LBB29_8: +; X86-X87-NEXT: .LBB29_6: ; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl $-1, %ebp ; X86-X87-NEXT: movl $-1, %edi ; X86-X87-NEXT: movl $-1, %esi -; X86-X87-NEXT: ja .LBB29_10 -; X86-X87-NEXT: # %bb.9: +; X86-X87-NEXT: ja .LBB29_8 +; X86-X87-NEXT: # %bb.7: ; X86-X87-NEXT: movl %edx, %ebp ; X86-X87-NEXT: movl %ebx, %edi ; X86-X87-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload -; X86-X87-NEXT: .LBB29_10: +; X86-X87-NEXT: .LBB29_8: ; X86-X87-NEXT: fucomp %st(0) ; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax @@ -3079,13 +3079,13 @@ define i128 @test_signed_i128_f16(half %f) nounwind { ; X86-X87-NEXT: movl $0, %eax ; X86-X87-NEXT: movl $0, %edx ; X86-X87-NEXT: movl $0, %ebx -; X86-X87-NEXT: jp .LBB29_12 -; X86-X87-NEXT: # %bb.11: +; X86-X87-NEXT: jp .LBB29_10 +; X86-X87-NEXT: # %bb.9: ; X86-X87-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-X87-NEXT: movl %edi, %eax ; X86-X87-NEXT: movl %ebp, %edx ; X86-X87-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload -; X86-X87-NEXT: .LBB29_12: +; X86-X87-NEXT: .LBB29_10: ; X86-X87-NEXT: movl %ebx, 12(%ecx) ; X86-X87-NEXT: movl %edx, 8(%ecx) ; X86-X87-NEXT: movl %eax, 4(%ecx) @@ -3098,16 +3098,16 @@ define i128 @test_signed_i128_f16(half %f) nounwind { ; X86-X87-NEXT: popl %ebx ; X86-X87-NEXT: popl %ebp ; X86-X87-NEXT: retl $4 -; X86-X87-NEXT: .LBB29_1: +; X86-X87-NEXT: .LBB29_11: ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ebx ; X86-X87-NEXT: movl $0, %edx -; X86-X87-NEXT: jb .LBB29_4 -; X86-X87-NEXT: .LBB29_3: +; X86-X87-NEXT: jb .LBB29_2 +; X86-X87-NEXT: .LBB29_12: ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-X87-NEXT: movl $-2147483648, %ecx # imm = 0x80000000 -; X86-X87-NEXT: jae .LBB29_5 -; X86-X87-NEXT: jmp .LBB29_6 +; X86-X87-NEXT: jae .LBB29_3 +; X86-X87-NEXT: jmp .LBB29_4 ; ; X86-SSE-LABEL: test_signed_i128_f16: ; X86-SSE: # %bb.0: @@ -4003,11 +4003,11 @@ define i50 @test_signed_i50_f80(x86_fp80 %f) nounwind { ; X64-NEXT: fxch %st(1) ; X64-NEXT: fucomi %st(1), %st ; X64-NEXT: fstp %st(1) -; X64-NEXT: jb .LBB36_1 -; X64-NEXT: # %bb.2: +; X64-NEXT: jb .LBB36_2 +; X64-NEXT: # %bb.1: ; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rax ; X64-NEXT: jmp .LBB36_3 -; X64-NEXT: .LBB36_1: +; X64-NEXT: .LBB36_2: ; X64-NEXT: movabsq $-562949953421312, %rax # imm = 0xFFFE000000000000 ; X64-NEXT: .LBB36_3: ; X64-NEXT: fldl {{\.?LCPI[0-9]+_[0-9]+}}(%rip) @@ -4142,11 +4142,11 @@ define i64 @test_signed_i64_f80(x86_fp80 %f) nounwind { ; X64-NEXT: fxch %st(1) ; X64-NEXT: fucomi %st(1), %st ; X64-NEXT: fstp %st(1) -; X64-NEXT: jb .LBB37_1 -; X64-NEXT: # %bb.2: +; X64-NEXT: jb .LBB37_2 +; X64-NEXT: # %bb.1: ; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rax ; X64-NEXT: jmp .LBB37_3 -; X64-NEXT: .LBB37_1: +; X64-NEXT: .LBB37_2: ; X64-NEXT: movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000 ; X64-NEXT: .LBB37_3: ; X64-NEXT: fldt {{\.?LCPI[0-9]+_[0-9]+}}(%rip) @@ -4376,16 +4376,16 @@ define i128 @test_signed_i128_f80(x86_fp80 %f) nounwind { ; X86-X87-NEXT: sahf ; X86-X87-NEXT: movl $0, %eax ; X86-X87-NEXT: movl $0, %ebx -; X86-X87-NEXT: jae .LBB39_1 -; X86-X87-NEXT: # %bb.2: +; X86-X87-NEXT: jae .LBB39_11 +; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: movl $0, %edx -; X86-X87-NEXT: jae .LBB39_3 -; X86-X87-NEXT: .LBB39_4: +; X86-X87-NEXT: jae .LBB39_12 +; X86-X87-NEXT: .LBB39_2: ; X86-X87-NEXT: movl $-2147483648, %ecx # imm = 0x80000000 -; X86-X87-NEXT: jb .LBB39_6 -; X86-X87-NEXT: .LBB39_5: +; X86-X87-NEXT: jb .LBB39_4 +; X86-X87-NEXT: .LBB39_3: ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X86-X87-NEXT: .LBB39_6: +; X86-X87-NEXT: .LBB39_4: ; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-X87-NEXT: fldt {{\.?LCPI[0-9]+_[0-9]+}} ; X86-X87-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Reload @@ -4395,21 +4395,21 @@ define i128 @test_signed_i128_f80(x86_fp80 %f) nounwind { ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: sahf ; X86-X87-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF -; X86-X87-NEXT: ja .LBB39_8 -; X86-X87-NEXT: # %bb.7: +; X86-X87-NEXT: ja .LBB39_6 +; X86-X87-NEXT: # %bb.5: ; X86-X87-NEXT: movl %ecx, %eax -; X86-X87-NEXT: .LBB39_8: +; X86-X87-NEXT: .LBB39_6: ; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl $-1, %ebp ; X86-X87-NEXT: movl $-1, %edi ; X86-X87-NEXT: movl $-1, %esi -; X86-X87-NEXT: ja .LBB39_10 -; X86-X87-NEXT: # %bb.9: +; X86-X87-NEXT: ja .LBB39_8 +; X86-X87-NEXT: # %bb.7: ; X86-X87-NEXT: movl %edx, %ebp ; X86-X87-NEXT: movl %ebx, %edi ; X86-X87-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload -; X86-X87-NEXT: .LBB39_10: +; X86-X87-NEXT: .LBB39_8: ; X86-X87-NEXT: fucomp %st(0) ; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax @@ -4417,13 +4417,13 @@ define i128 @test_signed_i128_f80(x86_fp80 %f) nounwind { ; X86-X87-NEXT: movl $0, %eax ; X86-X87-NEXT: movl $0, %edx ; X86-X87-NEXT: movl $0, %ebx -; X86-X87-NEXT: jp .LBB39_12 -; X86-X87-NEXT: # %bb.11: +; X86-X87-NEXT: jp .LBB39_10 +; X86-X87-NEXT: # %bb.9: ; X86-X87-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-X87-NEXT: movl %edi, %eax ; X86-X87-NEXT: movl %ebp, %edx ; X86-X87-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload -; X86-X87-NEXT: .LBB39_12: +; X86-X87-NEXT: .LBB39_10: ; X86-X87-NEXT: movl %ebx, 12(%ecx) ; X86-X87-NEXT: movl %edx, 8(%ecx) ; X86-X87-NEXT: movl %eax, 4(%ecx) @@ -4436,16 +4436,16 @@ define i128 @test_signed_i128_f80(x86_fp80 %f) nounwind { ; X86-X87-NEXT: popl %ebx ; X86-X87-NEXT: popl %ebp ; X86-X87-NEXT: retl $4 -; X86-X87-NEXT: .LBB39_1: +; X86-X87-NEXT: .LBB39_11: ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ebx ; X86-X87-NEXT: movl $0, %edx -; X86-X87-NEXT: jb .LBB39_4 -; X86-X87-NEXT: .LBB39_3: +; X86-X87-NEXT: jb .LBB39_2 +; X86-X87-NEXT: .LBB39_12: ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-X87-NEXT: movl $-2147483648, %ecx # imm = 0x80000000 -; X86-X87-NEXT: jae .LBB39_5 -; X86-X87-NEXT: jmp .LBB39_6 +; X86-X87-NEXT: jae .LBB39_3 +; X86-X87-NEXT: jmp .LBB39_4 ; ; X86-SSE-LABEL: test_signed_i128_f80: ; X86-SSE: # %bb.0: diff --git a/llvm/test/CodeGen/X86/fptoui-sat-scalar.ll b/llvm/test/CodeGen/X86/fptoui-sat-scalar.ll index a074c78d512f5..802d54621d627 100644 --- a/llvm/test/CodeGen/X86/fptoui-sat-scalar.ll +++ b/llvm/test/CodeGen/X86/fptoui-sat-scalar.ll @@ -37,11 +37,11 @@ define i1 @test_unsigned_i1_f32(float %f) nounwind { ; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: sahf -; X86-X87-NEXT: jb .LBB0_1 -; X86-X87-NEXT: # %bb.2: +; X86-X87-NEXT: jb .LBB0_2 +; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: movzbl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: jmp .LBB0_3 -; X86-X87-NEXT: .LBB0_1: +; X86-X87-NEXT: .LBB0_2: ; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: .LBB0_3: ; X86-X87-NEXT: fld1 @@ -100,11 +100,11 @@ define i8 @test_unsigned_i8_f32(float %f) nounwind { ; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: sahf -; X86-X87-NEXT: jb .LBB1_1 -; X86-X87-NEXT: # %bb.2: +; X86-X87-NEXT: jb .LBB1_2 +; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: movzbl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: jmp .LBB1_3 -; X86-X87-NEXT: .LBB1_1: +; X86-X87-NEXT: .LBB1_2: ; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: .LBB1_3: ; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} @@ -972,11 +972,11 @@ define i1 @test_unsigned_i1_f64(double %f) nounwind { ; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: sahf -; X86-X87-NEXT: jb .LBB10_1 -; X86-X87-NEXT: # %bb.2: +; X86-X87-NEXT: jb .LBB10_2 +; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: movzbl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: jmp .LBB10_3 -; X86-X87-NEXT: .LBB10_1: +; X86-X87-NEXT: .LBB10_2: ; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: .LBB10_3: ; X86-X87-NEXT: fld1 @@ -1035,11 +1035,11 @@ define i8 @test_unsigned_i8_f64(double %f) nounwind { ; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: sahf -; X86-X87-NEXT: jb .LBB11_1 -; X86-X87-NEXT: # %bb.2: +; X86-X87-NEXT: jb .LBB11_2 +; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: movzbl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: jmp .LBB11_3 -; X86-X87-NEXT: .LBB11_1: +; X86-X87-NEXT: .LBB11_2: ; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: .LBB11_3: ; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} @@ -1886,11 +1886,11 @@ define i1 @test_unsigned_i1_f16(half %f) nounwind { ; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: sahf -; X86-X87-NEXT: jb .LBB20_1 -; X86-X87-NEXT: # %bb.2: +; X86-X87-NEXT: jb .LBB20_2 +; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: movzbl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: jmp .LBB20_3 -; X86-X87-NEXT: .LBB20_1: +; X86-X87-NEXT: .LBB20_2: ; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: .LBB20_3: ; X86-X87-NEXT: fld1 @@ -1960,11 +1960,11 @@ define i8 @test_unsigned_i8_f16(half %f) nounwind { ; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: sahf -; X86-X87-NEXT: jb .LBB21_1 -; X86-X87-NEXT: # %bb.2: +; X86-X87-NEXT: jb .LBB21_2 +; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: movzbl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: jmp .LBB21_3 -; X86-X87-NEXT: .LBB21_1: +; X86-X87-NEXT: .LBB21_2: ; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: .LBB21_3: ; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} @@ -2941,11 +2941,11 @@ define i1 @test_unsigned_i1_f80(x86_fp80 %f) nounwind { ; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: sahf -; X86-X87-NEXT: jb .LBB30_1 -; X86-X87-NEXT: # %bb.2: +; X86-X87-NEXT: jb .LBB30_2 +; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: movzbl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: jmp .LBB30_3 -; X86-X87-NEXT: .LBB30_1: +; X86-X87-NEXT: .LBB30_2: ; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: .LBB30_3: ; X86-X87-NEXT: fld1 @@ -3038,11 +3038,11 @@ define i8 @test_unsigned_i8_f80(x86_fp80 %f) nounwind { ; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: sahf -; X86-X87-NEXT: jb .LBB31_1 -; X86-X87-NEXT: # %bb.2: +; X86-X87-NEXT: jb .LBB31_2 +; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: movzbl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: jmp .LBB31_3 -; X86-X87-NEXT: .LBB31_1: +; X86-X87-NEXT: .LBB31_2: ; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: .LBB31_3: ; X86-X87-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} diff --git a/llvm/test/CodeGen/X86/fshl.ll b/llvm/test/CodeGen/X86/fshl.ll index 9da2640ea8392..54540620f8765 100644 --- a/llvm/test/CodeGen/X86/fshl.ll +++ b/llvm/test/CodeGen/X86/fshl.ll @@ -185,12 +185,12 @@ define i64 @var_shift_i64(i64 %x, i64 %y, i64 %z) nounwind { ; X86-FAST-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-FAST-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-FAST-NEXT: testb $32, %cl -; X86-FAST-NEXT: jne .LBB5_1 -; X86-FAST-NEXT: # %bb.2: +; X86-FAST-NEXT: jne .LBB5_2 +; X86-FAST-NEXT: # %bb.1: ; X86-FAST-NEXT: movl %edx, %edi ; X86-FAST-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-FAST-NEXT: jmp .LBB5_3 -; X86-FAST-NEXT: .LBB5_1: +; X86-FAST-NEXT: .LBB5_2: ; X86-FAST-NEXT: movl %esi, %edi ; X86-FAST-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-FAST-NEXT: .LBB5_3: @@ -211,12 +211,12 @@ define i64 @var_shift_i64(i64 %x, i64 %y, i64 %z) nounwind { ; X86-SLOW-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-SLOW-NEXT: movl {{[0-9]+}}(%esp), %ebx ; X86-SLOW-NEXT: testb $32, %bl -; X86-SLOW-NEXT: jne .LBB5_1 -; X86-SLOW-NEXT: # %bb.2: +; X86-SLOW-NEXT: jne .LBB5_2 +; X86-SLOW-NEXT: # %bb.1: ; X86-SLOW-NEXT: movl %edx, %esi ; X86-SLOW-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-SLOW-NEXT: jmp .LBB5_3 -; X86-SLOW-NEXT: .LBB5_1: +; X86-SLOW-NEXT: .LBB5_2: ; X86-SLOW-NEXT: movl %eax, %esi ; X86-SLOW-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SLOW-NEXT: .LBB5_3: @@ -276,8 +276,8 @@ define i128 @var_shift_i128(i128 %x, i128 %y, i128 %z) nounwind { ; X86-FAST-NEXT: movl 56(%ebp), %ecx ; X86-FAST-NEXT: testb $64, %cl ; X86-FAST-NEXT: movl 52(%ebp), %eax -; X86-FAST-NEXT: jne .LBB6_1 -; X86-FAST-NEXT: # %bb.2: +; X86-FAST-NEXT: jne .LBB6_3 +; X86-FAST-NEXT: # %bb.1: ; X86-FAST-NEXT: movl %esi, %ebx ; X86-FAST-NEXT: movl %edi, %esi ; X86-FAST-NEXT: movl 32(%ebp), %edi @@ -285,24 +285,24 @@ define i128 @var_shift_i128(i128 %x, i128 %y, i128 %z) nounwind { ; X86-FAST-NEXT: movl %edx, %eax ; X86-FAST-NEXT: movl 36(%ebp), %edx ; X86-FAST-NEXT: testb $32, %cl -; X86-FAST-NEXT: je .LBB6_5 -; X86-FAST-NEXT: .LBB6_4: +; X86-FAST-NEXT: je .LBB6_4 +; X86-FAST-NEXT: .LBB6_2: ; X86-FAST-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-FAST-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-FAST-NEXT: movl %esi, %eax ; X86-FAST-NEXT: movl (%esp), %esi # 4-byte Reload -; X86-FAST-NEXT: jmp .LBB6_6 -; X86-FAST-NEXT: .LBB6_1: +; X86-FAST-NEXT: jmp .LBB6_5 +; X86-FAST-NEXT: .LBB6_3: ; X86-FAST-NEXT: movl 44(%ebp), %ebx ; X86-FAST-NEXT: movl %ebx, (%esp) # 4-byte Spill ; X86-FAST-NEXT: movl 40(%ebp), %ebx ; X86-FAST-NEXT: testb $32, %cl -; X86-FAST-NEXT: jne .LBB6_4 -; X86-FAST-NEXT: .LBB6_5: +; X86-FAST-NEXT: jne .LBB6_2 +; X86-FAST-NEXT: .LBB6_4: ; X86-FAST-NEXT: movl (%esp), %ebx # 4-byte Reload ; X86-FAST-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-FAST-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-FAST-NEXT: .LBB6_6: +; X86-FAST-NEXT: .LBB6_5: ; X86-FAST-NEXT: movl %esi, %edi ; X86-FAST-NEXT: shldl %cl, %ebx, %edi ; X86-FAST-NEXT: movl %eax, %edx @@ -341,8 +341,8 @@ define i128 @var_shift_i128(i128 %x, i128 %y, i128 %z) nounwind { ; X86-SLOW-NEXT: movl 56(%ebp), %ecx ; X86-SLOW-NEXT: testb $64, %cl ; X86-SLOW-NEXT: movl 52(%ebp), %ebx -; X86-SLOW-NEXT: jne .LBB6_1 -; X86-SLOW-NEXT: # %bb.2: +; X86-SLOW-NEXT: jne .LBB6_2 +; X86-SLOW-NEXT: # %bb.1: ; X86-SLOW-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-SLOW-NEXT: movl %edi, %edx ; X86-SLOW-NEXT: movl 32(%ebp), %edi @@ -350,7 +350,7 @@ define i128 @var_shift_i128(i128 %x, i128 %y, i128 %z) nounwind { ; X86-SLOW-NEXT: movl %eax, %ebx ; X86-SLOW-NEXT: movl 36(%ebp), %eax ; X86-SLOW-NEXT: jmp .LBB6_3 -; X86-SLOW-NEXT: .LBB6_1: +; X86-SLOW-NEXT: .LBB6_2: ; X86-SLOW-NEXT: movl 40(%ebp), %ecx ; X86-SLOW-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-SLOW-NEXT: movl 44(%ebp), %ecx @@ -358,14 +358,14 @@ define i128 @var_shift_i128(i128 %x, i128 %y, i128 %z) nounwind { ; X86-SLOW-NEXT: .LBB6_3: ; X86-SLOW-NEXT: movl 56(%ebp), %ecx ; X86-SLOW-NEXT: testb $32, %cl -; X86-SLOW-NEXT: jne .LBB6_4 -; X86-SLOW-NEXT: # %bb.5: +; X86-SLOW-NEXT: jne .LBB6_5 +; X86-SLOW-NEXT: # %bb.4: ; X86-SLOW-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-SLOW-NEXT: movl %edx, %edi ; X86-SLOW-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload ; X86-SLOW-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-SLOW-NEXT: jmp .LBB6_6 -; X86-SLOW-NEXT: .LBB6_4: +; X86-SLOW-NEXT: .LBB6_5: ; X86-SLOW-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-SLOW-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-SLOW-NEXT: movl %edx, %ebx diff --git a/llvm/test/CodeGen/X86/fshr.ll b/llvm/test/CodeGen/X86/fshr.ll index c307833e488c9..716da34203d28 100644 --- a/llvm/test/CodeGen/X86/fshr.ll +++ b/llvm/test/CodeGen/X86/fshr.ll @@ -181,12 +181,12 @@ define i64 @var_shift_i64(i64 %x, i64 %y, i64 %z) nounwind { ; X86-FAST-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-FAST-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-FAST-NEXT: testb $32, %cl -; X86-FAST-NEXT: je .LBB5_1 -; X86-FAST-NEXT: # %bb.2: +; X86-FAST-NEXT: je .LBB5_2 +; X86-FAST-NEXT: # %bb.1: ; X86-FAST-NEXT: movl %esi, %edx ; X86-FAST-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-FAST-NEXT: jmp .LBB5_3 -; X86-FAST-NEXT: .LBB5_1: +; X86-FAST-NEXT: .LBB5_2: ; X86-FAST-NEXT: movl %eax, %edx ; X86-FAST-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-FAST-NEXT: .LBB5_3: @@ -205,12 +205,12 @@ define i64 @var_shift_i64(i64 %x, i64 %y, i64 %z) nounwind { ; X86-SLOW-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-SLOW-NEXT: movl {{[0-9]+}}(%esp), %ebx ; X86-SLOW-NEXT: testb $32, %bl -; X86-SLOW-NEXT: je .LBB5_1 -; X86-SLOW-NEXT: # %bb.2: +; X86-SLOW-NEXT: je .LBB5_2 +; X86-SLOW-NEXT: # %bb.1: ; X86-SLOW-NEXT: movl %edx, %esi ; X86-SLOW-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-SLOW-NEXT: jmp .LBB5_3 -; X86-SLOW-NEXT: .LBB5_1: +; X86-SLOW-NEXT: .LBB5_2: ; X86-SLOW-NEXT: movl %eax, %esi ; X86-SLOW-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SLOW-NEXT: .LBB5_3: @@ -270,8 +270,8 @@ define i128 @var_shift_i128(i128 %x, i128 %y, i128 %z) nounwind { ; X86-FAST-NEXT: movl 56(%ebp), %ecx ; X86-FAST-NEXT: testb $64, %cl ; X86-FAST-NEXT: movl 52(%ebp), %ebx -; X86-FAST-NEXT: je .LBB6_1 -; X86-FAST-NEXT: # %bb.2: +; X86-FAST-NEXT: je .LBB6_2 +; X86-FAST-NEXT: # %bb.1: ; X86-FAST-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-FAST-NEXT: movl %esi, %edx ; X86-FAST-NEXT: movl 32(%ebp), %esi @@ -279,21 +279,21 @@ define i128 @var_shift_i128(i128 %x, i128 %y, i128 %z) nounwind { ; X86-FAST-NEXT: movl %eax, %ebx ; X86-FAST-NEXT: movl 36(%ebp), %eax ; X86-FAST-NEXT: testb $32, %cl -; X86-FAST-NEXT: je .LBB6_4 -; X86-FAST-NEXT: jmp .LBB6_5 -; X86-FAST-NEXT: .LBB6_1: +; X86-FAST-NEXT: je .LBB6_3 +; X86-FAST-NEXT: jmp .LBB6_4 +; X86-FAST-NEXT: .LBB6_2: ; X86-FAST-NEXT: movl 40(%ebp), %edi ; X86-FAST-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-FAST-NEXT: movl 44(%ebp), %edi ; X86-FAST-NEXT: testb $32, %cl -; X86-FAST-NEXT: jne .LBB6_5 -; X86-FAST-NEXT: .LBB6_4: +; X86-FAST-NEXT: jne .LBB6_4 +; X86-FAST-NEXT: .LBB6_3: ; X86-FAST-NEXT: movl %esi, %eax ; X86-FAST-NEXT: movl %ebx, %esi ; X86-FAST-NEXT: movl %edx, %ebx ; X86-FAST-NEXT: movl %edi, %edx ; X86-FAST-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload -; X86-FAST-NEXT: .LBB6_5: +; X86-FAST-NEXT: .LBB6_4: ; X86-FAST-NEXT: shrdl %cl, %edx, %edi ; X86-FAST-NEXT: shrdl %cl, %ebx, %edx ; X86-FAST-NEXT: shrdl %cl, %esi, %ebx @@ -326,8 +326,8 @@ define i128 @var_shift_i128(i128 %x, i128 %y, i128 %z) nounwind { ; X86-SLOW-NEXT: movl 56(%ebp), %eax ; X86-SLOW-NEXT: testb $64, %al ; X86-SLOW-NEXT: movl 52(%ebp), %eax -; X86-SLOW-NEXT: je .LBB6_1 -; X86-SLOW-NEXT: # %bb.2: +; X86-SLOW-NEXT: je .LBB6_2 +; X86-SLOW-NEXT: # %bb.1: ; X86-SLOW-NEXT: movl %edi, (%esp) # 4-byte Spill ; X86-SLOW-NEXT: movl %edx, %edi ; X86-SLOW-NEXT: movl 32(%ebp), %edx @@ -335,20 +335,20 @@ define i128 @var_shift_i128(i128 %x, i128 %y, i128 %z) nounwind { ; X86-SLOW-NEXT: movl %esi, %eax ; X86-SLOW-NEXT: movl 36(%ebp), %esi ; X86-SLOW-NEXT: jmp .LBB6_3 -; X86-SLOW-NEXT: .LBB6_1: +; X86-SLOW-NEXT: .LBB6_2: ; X86-SLOW-NEXT: movl 40(%ebp), %ecx ; X86-SLOW-NEXT: movl %ecx, (%esp) # 4-byte Spill ; X86-SLOW-NEXT: movl 44(%ebp), %ecx ; X86-SLOW-NEXT: .LBB6_3: ; X86-SLOW-NEXT: movl 56(%ebp), %ebx ; X86-SLOW-NEXT: testb $32, %bl -; X86-SLOW-NEXT: je .LBB6_4 -; X86-SLOW-NEXT: # %bb.5: +; X86-SLOW-NEXT: je .LBB6_5 +; X86-SLOW-NEXT: # %bb.4: ; X86-SLOW-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-SLOW-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-SLOW-NEXT: movl %ecx, %ebx ; X86-SLOW-NEXT: jmp .LBB6_6 -; X86-SLOW-NEXT: .LBB6_4: +; X86-SLOW-NEXT: .LBB6_5: ; X86-SLOW-NEXT: movl %edx, %esi ; X86-SLOW-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-SLOW-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill diff --git a/llvm/test/CodeGen/X86/funnel-shift-i256.ll b/llvm/test/CodeGen/X86/funnel-shift-i256.ll index cc0c1ef23c3a5..65c8c5bcff8f1 100644 --- a/llvm/test/CodeGen/X86/funnel-shift-i256.ll +++ b/llvm/test/CodeGen/X86/funnel-shift-i256.ll @@ -16,12 +16,12 @@ define i256 @fshl_i256(i256 %a0, i256 %a1, i256 %a2) nounwind { ; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rbx ; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rcx ; SSE-NEXT: testb $-128, %cl -; SSE-NEXT: je .LBB0_1 -; SSE-NEXT: # %bb.2: +; SSE-NEXT: je .LBB0_2 +; SSE-NEXT: # %bb.1: ; SSE-NEXT: movq %rbx, %r11 ; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rbx ; SSE-NEXT: jmp .LBB0_3 -; SSE-NEXT: .LBB0_1: +; SSE-NEXT: .LBB0_2: ; SSE-NEXT: movq %rdi, %r9 ; SSE-NEXT: movq %rdx, %r11 ; SSE-NEXT: movq %rsi, %rdi @@ -57,12 +57,12 @@ define i256 @fshl_i256(i256 %a0, i256 %a1, i256 %a2) nounwind { ; AVX-NEXT: movq {{[0-9]+}}(%rsp), %rbx ; AVX-NEXT: movq {{[0-9]+}}(%rsp), %rcx ; AVX-NEXT: testb $-128, %cl -; AVX-NEXT: je .LBB0_1 -; AVX-NEXT: # %bb.2: +; AVX-NEXT: je .LBB0_2 +; AVX-NEXT: # %bb.1: ; AVX-NEXT: movq %rbx, %r11 ; AVX-NEXT: movq {{[0-9]+}}(%rsp), %rbx ; AVX-NEXT: jmp .LBB0_3 -; AVX-NEXT: .LBB0_1: +; AVX-NEXT: .LBB0_2: ; AVX-NEXT: movq %rdi, %r9 ; AVX-NEXT: movq %rdx, %r11 ; AVX-NEXT: movq %rsi, %rdi @@ -102,12 +102,12 @@ define i256 @fshr_i256(i256 %a0, i256 %a1, i256 %a2) nounwind { ; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rbx ; SSE-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx ; SSE-NEXT: testb %cl, %cl -; SSE-NEXT: js .LBB1_1 -; SSE-NEXT: # %bb.2: +; SSE-NEXT: js .LBB1_2 +; SSE-NEXT: # %bb.1: ; SSE-NEXT: movq %rbx, %r11 ; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rbx ; SSE-NEXT: jmp .LBB1_3 -; SSE-NEXT: .LBB1_1: +; SSE-NEXT: .LBB1_2: ; SSE-NEXT: movq %rdi, %r9 ; SSE-NEXT: movq %rsi, %rdi ; SSE-NEXT: movq %rdx, %r11 @@ -141,12 +141,12 @@ define i256 @fshr_i256(i256 %a0, i256 %a1, i256 %a2) nounwind { ; AVX-NEXT: movq {{[0-9]+}}(%rsp), %rbx ; AVX-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx ; AVX-NEXT: testb %cl, %cl -; AVX-NEXT: js .LBB1_1 -; AVX-NEXT: # %bb.2: +; AVX-NEXT: js .LBB1_2 +; AVX-NEXT: # %bb.1: ; AVX-NEXT: movq %rbx, %r11 ; AVX-NEXT: movq {{[0-9]+}}(%rsp), %rbx ; AVX-NEXT: jmp .LBB1_3 -; AVX-NEXT: .LBB1_1: +; AVX-NEXT: .LBB1_2: ; AVX-NEXT: movq %rdi, %r9 ; AVX-NEXT: movq %rsi, %rdi ; AVX-NEXT: movq %rdx, %r11 diff --git a/llvm/test/CodeGen/X86/funnel-shift.ll b/llvm/test/CodeGen/X86/funnel-shift.ll index 318a48b92cb28..0ef5e1c11720f 100644 --- a/llvm/test/CodeGen/X86/funnel-shift.ll +++ b/llvm/test/CodeGen/X86/funnel-shift.ll @@ -169,13 +169,13 @@ define i37 @fshl_i37(i37 %x, i37 %y, i37 %z) nounwind { ; X86-SSE2-NEXT: addl $16, %esp ; X86-SSE2-NEXT: movl %eax, %ecx ; X86-SSE2-NEXT: testb $32, %cl -; X86-SSE2-NEXT: jne .LBB3_1 -; X86-SSE2-NEXT: # %bb.2: +; X86-SSE2-NEXT: jne .LBB3_2 +; X86-SSE2-NEXT: # %bb.1: ; X86-SSE2-NEXT: movl %edi, %ebx ; X86-SSE2-NEXT: movl %esi, %edi ; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-SSE2-NEXT: jmp .LBB3_3 -; X86-SSE2-NEXT: .LBB3_1: +; X86-SSE2-NEXT: .LBB3_2: ; X86-SSE2-NEXT: shll $27, %ebx ; X86-SSE2-NEXT: .LBB3_3: ; X86-SSE2-NEXT: movl %edi, %eax @@ -336,12 +336,12 @@ define i37 @fshr_i37(i37 %x, i37 %y, i37 %z) nounwind { ; X86-SSE2-NEXT: movl %eax, %ecx ; X86-SSE2-NEXT: addl $27, %ecx ; X86-SSE2-NEXT: testb $32, %cl -; X86-SSE2-NEXT: je .LBB10_1 -; X86-SSE2-NEXT: # %bb.2: +; X86-SSE2-NEXT: je .LBB10_2 +; X86-SSE2-NEXT: # %bb.1: ; X86-SSE2-NEXT: movl %edi, %edx ; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-SSE2-NEXT: jmp .LBB10_3 -; X86-SSE2-NEXT: .LBB10_1: +; X86-SSE2-NEXT: .LBB10_2: ; X86-SSE2-NEXT: shll $27, %ebx ; X86-SSE2-NEXT: movl %esi, %edx ; X86-SSE2-NEXT: movl %ebx, %esi @@ -1105,12 +1105,12 @@ define void @PR45265(i32 %0, ptr nocapture readonly %1) nounwind { ; X86-SSE2-NEXT: shldl $24, %edx, %ecx ; X86-SSE2-NEXT: xorl %eax, %ecx ; X86-SSE2-NEXT: orl %ecx, %edi -; X86-SSE2-NEXT: jne .LBB50_1 -; X86-SSE2-NEXT: # %bb.2: +; X86-SSE2-NEXT: jne .LBB50_2 +; X86-SSE2-NEXT: # %bb.1: ; X86-SSE2-NEXT: popl %esi ; X86-SSE2-NEXT: popl %edi ; X86-SSE2-NEXT: jmp _Z3foov # TAILCALL -; X86-SSE2-NEXT: .LBB50_1: +; X86-SSE2-NEXT: .LBB50_2: ; X86-SSE2-NEXT: popl %esi ; X86-SSE2-NEXT: popl %edi ; X86-SSE2-NEXT: retl diff --git a/llvm/test/CodeGen/X86/gc-empty-basic-blocks.ll b/llvm/test/CodeGen/X86/gc-empty-basic-blocks.ll index 3a0c5f10980ee..3a513e440b8bb 100644 --- a/llvm/test/CodeGen/X86/gc-empty-basic-blocks.ll +++ b/llvm/test/CodeGen/X86/gc-empty-basic-blocks.ll @@ -9,25 +9,24 @@ define void @foo(i1 zeroext %0) nounwind { ; CHECK: .text ; CHECK-LABEL: foo: ; CHECK: jne .LBB0_1 -; CHECK-NEXT: jmp .LBB0_3 +; CHECK-NEXT: jmp .LBB0_2 2: ; preds = %1 %3 = call i32 @baz() br label %4 ; CHECK-LABEL: .LBB0_1: -; CHECK: jmp .LBB0_3 +; CHECK: jmp .LBB0_2 empty_block: ; preds = %1 unreachable ; CHECK-NOT: %empty_block -; CHECK-NOT: .LBB0_2 4: ; preds = %2, %empty_block ret void -; CHECK-LABEL: .LBB0_3: +; CHECK-LABEL: .LBB0_2: ; CHECK: retq } diff --git a/llvm/test/CodeGen/X86/half.ll b/llvm/test/CodeGen/X86/half.ll index b6a4a12eb0fac..d36df5d27fd7a 100644 --- a/llvm/test/CodeGen/X86/half.ll +++ b/llvm/test/CodeGen/X86/half.ll @@ -362,11 +362,11 @@ define void @test_uitofp_i64(i64 %a, ptr %p) #0 { ; CHECK-LIBCALL-NEXT: pushq %rbx ; CHECK-LIBCALL-NEXT: movq %rsi, %rbx ; CHECK-LIBCALL-NEXT: testq %rdi, %rdi -; CHECK-LIBCALL-NEXT: js .LBB10_1 -; CHECK-LIBCALL-NEXT: # %bb.2: +; CHECK-LIBCALL-NEXT: js .LBB10_2 +; CHECK-LIBCALL-NEXT: # %bb.1: ; CHECK-LIBCALL-NEXT: cvtsi2ss %rdi, %xmm0 ; CHECK-LIBCALL-NEXT: jmp .LBB10_3 -; CHECK-LIBCALL-NEXT: .LBB10_1: +; CHECK-LIBCALL-NEXT: .LBB10_2: ; CHECK-LIBCALL-NEXT: movq %rdi, %rax ; CHECK-LIBCALL-NEXT: shrq %rax ; CHECK-LIBCALL-NEXT: andl $1, %edi @@ -383,11 +383,11 @@ define void @test_uitofp_i64(i64 %a, ptr %p) #0 { ; BWON-F16C-LABEL: test_uitofp_i64: ; BWON-F16C: # %bb.0: ; BWON-F16C-NEXT: testq %rdi, %rdi -; BWON-F16C-NEXT: js .LBB10_1 -; BWON-F16C-NEXT: # %bb.2: +; BWON-F16C-NEXT: js .LBB10_2 +; BWON-F16C-NEXT: # %bb.1: ; BWON-F16C-NEXT: vcvtsi2ss %rdi, %xmm15, %xmm0 ; BWON-F16C-NEXT: jmp .LBB10_3 -; BWON-F16C-NEXT: .LBB10_1: +; BWON-F16C-NEXT: .LBB10_2: ; BWON-F16C-NEXT: movq %rdi, %rax ; BWON-F16C-NEXT: shrq %rax ; BWON-F16C-NEXT: andl $1, %edi @@ -1692,11 +1692,11 @@ define <8 x half> @maxnum_v8f16(<8 x half> %0, <8 x half> %1) #0 { ; CHECK-I686-NEXT: fstps {{[0-9]+}}(%esp) ; CHECK-I686-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-I686-NEXT: ucomiss {{[0-9]+}}(%esp), %xmm0 -; CHECK-I686-NEXT: ja .LBB26_1 -; CHECK-I686-NEXT: # %bb.2: +; CHECK-I686-NEXT: ja .LBB26_2 +; CHECK-I686-NEXT: # %bb.1: ; CHECK-I686-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-I686-NEXT: jmp .LBB26_3 -; CHECK-I686-NEXT: .LBB26_1: +; CHECK-I686-NEXT: .LBB26_2: ; CHECK-I686-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-I686-NEXT: .LBB26_3: ; CHECK-I686-NEXT: movss %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill @@ -1713,11 +1713,11 @@ define <8 x half> @maxnum_v8f16(<8 x half> %0, <8 x half> %1) #0 { ; CHECK-I686-NEXT: fstps {{[0-9]+}}(%esp) ; CHECK-I686-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-I686-NEXT: ucomiss {{[0-9]+}}(%esp), %xmm0 -; CHECK-I686-NEXT: ja .LBB26_4 -; CHECK-I686-NEXT: # %bb.5: +; CHECK-I686-NEXT: ja .LBB26_5 +; CHECK-I686-NEXT: # %bb.4: ; CHECK-I686-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-I686-NEXT: jmp .LBB26_6 -; CHECK-I686-NEXT: .LBB26_4: +; CHECK-I686-NEXT: .LBB26_5: ; CHECK-I686-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-I686-NEXT: .LBB26_6: ; CHECK-I686-NEXT: movss %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill @@ -1770,11 +1770,11 @@ define <8 x half> @maxnum_v8f16(<8 x half> %0, <8 x half> %1) #0 { ; CHECK-I686-NEXT: fstps {{[0-9]+}}(%esp) ; CHECK-I686-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-I686-NEXT: ucomiss {{[0-9]+}}(%esp), %xmm0 -; CHECK-I686-NEXT: ja .LBB26_7 -; CHECK-I686-NEXT: # %bb.8: +; CHECK-I686-NEXT: ja .LBB26_8 +; CHECK-I686-NEXT: # %bb.7: ; CHECK-I686-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-I686-NEXT: jmp .LBB26_9 -; CHECK-I686-NEXT: .LBB26_7: +; CHECK-I686-NEXT: .LBB26_8: ; CHECK-I686-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-I686-NEXT: .LBB26_9: ; CHECK-I686-NEXT: movss %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill @@ -1791,11 +1791,11 @@ define <8 x half> @maxnum_v8f16(<8 x half> %0, <8 x half> %1) #0 { ; CHECK-I686-NEXT: fstps {{[0-9]+}}(%esp) ; CHECK-I686-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-I686-NEXT: ucomiss {{[0-9]+}}(%esp), %xmm0 -; CHECK-I686-NEXT: ja .LBB26_10 -; CHECK-I686-NEXT: # %bb.11: +; CHECK-I686-NEXT: ja .LBB26_11 +; CHECK-I686-NEXT: # %bb.10: ; CHECK-I686-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-I686-NEXT: jmp .LBB26_12 -; CHECK-I686-NEXT: .LBB26_10: +; CHECK-I686-NEXT: .LBB26_11: ; CHECK-I686-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-I686-NEXT: .LBB26_12: ; CHECK-I686-NEXT: movss %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill @@ -1848,11 +1848,11 @@ define <8 x half> @maxnum_v8f16(<8 x half> %0, <8 x half> %1) #0 { ; CHECK-I686-NEXT: fstps {{[0-9]+}}(%esp) ; CHECK-I686-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-I686-NEXT: ucomiss {{[0-9]+}}(%esp), %xmm0 -; CHECK-I686-NEXT: ja .LBB26_13 -; CHECK-I686-NEXT: # %bb.14: +; CHECK-I686-NEXT: ja .LBB26_14 +; CHECK-I686-NEXT: # %bb.13: ; CHECK-I686-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-I686-NEXT: jmp .LBB26_15 -; CHECK-I686-NEXT: .LBB26_13: +; CHECK-I686-NEXT: .LBB26_14: ; CHECK-I686-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-I686-NEXT: .LBB26_15: ; CHECK-I686-NEXT: movss %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill @@ -1869,11 +1869,11 @@ define <8 x half> @maxnum_v8f16(<8 x half> %0, <8 x half> %1) #0 { ; CHECK-I686-NEXT: fstps {{[0-9]+}}(%esp) ; CHECK-I686-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-I686-NEXT: ucomiss {{[0-9]+}}(%esp), %xmm0 -; CHECK-I686-NEXT: ja .LBB26_16 -; CHECK-I686-NEXT: # %bb.17: +; CHECK-I686-NEXT: ja .LBB26_17 +; CHECK-I686-NEXT: # %bb.16: ; CHECK-I686-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-I686-NEXT: jmp .LBB26_18 -; CHECK-I686-NEXT: .LBB26_16: +; CHECK-I686-NEXT: .LBB26_17: ; CHECK-I686-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-I686-NEXT: .LBB26_18: ; CHECK-I686-NEXT: movss %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill @@ -1926,11 +1926,11 @@ define <8 x half> @maxnum_v8f16(<8 x half> %0, <8 x half> %1) #0 { ; CHECK-I686-NEXT: fstps {{[0-9]+}}(%esp) ; CHECK-I686-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-I686-NEXT: ucomiss {{[0-9]+}}(%esp), %xmm0 -; CHECK-I686-NEXT: ja .LBB26_19 -; CHECK-I686-NEXT: # %bb.20: +; CHECK-I686-NEXT: ja .LBB26_20 +; CHECK-I686-NEXT: # %bb.19: ; CHECK-I686-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-I686-NEXT: jmp .LBB26_21 -; CHECK-I686-NEXT: .LBB26_19: +; CHECK-I686-NEXT: .LBB26_20: ; CHECK-I686-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-I686-NEXT: .LBB26_21: ; CHECK-I686-NEXT: movss %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill @@ -1947,11 +1947,11 @@ define <8 x half> @maxnum_v8f16(<8 x half> %0, <8 x half> %1) #0 { ; CHECK-I686-NEXT: fstps {{[0-9]+}}(%esp) ; CHECK-I686-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-I686-NEXT: ucomiss {{[0-9]+}}(%esp), %xmm0 -; CHECK-I686-NEXT: ja .LBB26_22 -; CHECK-I686-NEXT: # %bb.23: +; CHECK-I686-NEXT: ja .LBB26_23 +; CHECK-I686-NEXT: # %bb.22: ; CHECK-I686-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-I686-NEXT: jmp .LBB26_24 -; CHECK-I686-NEXT: .LBB26_22: +; CHECK-I686-NEXT: .LBB26_23: ; CHECK-I686-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-I686-NEXT: .LBB26_24: ; CHECK-I686-NEXT: movd %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill diff --git a/llvm/test/CodeGen/X86/hipe-prologue.ll b/llvm/test/CodeGen/X86/hipe-prologue.ll index 12c7240cb75da..3a1b0e18f4137 100644 --- a/llvm/test/CodeGen/X86/hipe-prologue.ll +++ b/llvm/test/CodeGen/X86/hipe-prologue.ll @@ -26,21 +26,21 @@ define cc 11 {i32, i32} @test_basic_hipecc(i32 %hp, i32 %p) { ; X32-Linux-LABEL: test_basic_hipecc: ; X32-Linux: leal -140(%esp), %ebx ; X32-Linux-NEXT: cmpl 120(%ebp), %ebx - ; X32-Linux-NEXT: jb .LBB1_1 + ; X32-Linux-NEXT: jb .LBB1_2 ; X32-Linux: ret - ; X32-Linux: .LBB1_1: + ; X32-Linux: .LBB1_2: ; X32-Linux-NEXT: calll inc_stack_0 ; X64-Linux-LABEL: test_basic_hipecc: ; X64-Linux: leaq -184(%rsp), %r14 ; X64-Linux-NEXT: cmpq 120(%rbp), %r14 - ; X64-Linux-NEXT: jb .LBB1_1 + ; X64-Linux-NEXT: jb .LBB1_2 ; X64-Linux: ret - ; X64-Linux: .LBB1_1: + ; X64-Linux: .LBB1_2: ; X64-Linux-NEXT: callq inc_stack_0 %mem = alloca i32, i32 10 diff --git a/llvm/test/CodeGen/X86/hoist-and-by-const-from-shl-in-eqcmp-zero.ll b/llvm/test/CodeGen/X86/hoist-and-by-const-from-shl-in-eqcmp-zero.ll index 05b0a0be2acc8..0226f432415f7 100644 --- a/llvm/test/CodeGen/X86/hoist-and-by-const-from-shl-in-eqcmp-zero.ll +++ b/llvm/test/CodeGen/X86/hoist-and-by-const-from-shl-in-eqcmp-zero.ll @@ -345,11 +345,11 @@ define i1 @scalar_i64_lowestbit_eq(i64 %x, i64 %y) nounwind { ; X86: # %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: testb $32, %al -; X86-NEXT: je .LBB10_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: je .LBB10_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: jmp .LBB10_3 -; X86-NEXT: .LBB10_1: +; X86-NEXT: .LBB10_2: ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: .LBB10_3: ; X86-NEXT: btl %eax, %ecx diff --git a/llvm/test/CodeGen/X86/hoist-invariant-load.ll b/llvm/test/CodeGen/X86/hoist-invariant-load.ll index 68e10c0c98871..0e4deca44119f 100644 --- a/llvm/test/CodeGen/X86/hoist-invariant-load.ll +++ b/llvm/test/CodeGen/X86/hoist-invariant-load.ll @@ -220,17 +220,17 @@ define void @test_multi_def(ptr dereferenceable(8) align(8) %x1, ; CHECK-NEXT: movq (%rdi), %rdx ; CHECK-NEXT: movq (%rsi), %rsi ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: LBB4_2: ## %for.body +; CHECK-NEXT: LBB4_1: ## %for.body ; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: mulxq %rsi, %r9, %rdi ; CHECK-NEXT: addq %r9, (%rax) ; CHECK-NEXT: adcq %rdi, 8(%rax) -; CHECK-NEXT: ## %bb.1: ## %for.check -; CHECK-NEXT: ## in Loop: Header=BB4_2 Depth=1 +; CHECK-NEXT: ## %bb.2: ## %for.check +; CHECK-NEXT: ## in Loop: Header=BB4_1 Depth=1 ; CHECK-NEXT: incq %r8 ; CHECK-NEXT: addq $16, %rax ; CHECK-NEXT: cmpq %rcx, %r8 -; CHECK-NEXT: jl LBB4_2 +; CHECK-NEXT: jl LBB4_1 ; CHECK-NEXT: ## %bb.3: ## %exit ; CHECK-NEXT: retq ptr dereferenceable(8) align(8) %x2, @@ -268,17 +268,17 @@ define void @test_div_def(ptr dereferenceable(8) align(8) %x1, ; CHECK-NEXT: movl (%rdi), %edi ; CHECK-NEXT: movl (%rsi), %esi ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: LBB5_2: ## %for.body +; CHECK-NEXT: LBB5_1: ## %for.body ; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: divl %esi ; CHECK-NEXT: addl %eax, (%r8,%r9,4) -; CHECK-NEXT: ## %bb.1: ## %for.check -; CHECK-NEXT: ## in Loop: Header=BB5_2 Depth=1 +; CHECK-NEXT: ## %bb.2: ## %for.check +; CHECK-NEXT: ## in Loop: Header=BB5_1 Depth=1 ; CHECK-NEXT: incq %r9 ; CHECK-NEXT: cmpl %ecx, %r9d -; CHECK-NEXT: jl LBB5_2 +; CHECK-NEXT: jl LBB5_1 ; CHECK-NEXT: ## %bb.3: ## %exit ; CHECK-NEXT: retq ptr dereferenceable(8) align(8) %x2, diff --git a/llvm/test/CodeGen/X86/icall-branch-funnel.ll b/llvm/test/CodeGen/X86/icall-branch-funnel.ll index b6294e93835f9..712d6fd91a99b 100644 --- a/llvm/test/CodeGen/X86/icall-branch-funnel.ll +++ b/llvm/test/CodeGen/X86/icall-branch-funnel.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 ; RUN: llc -mtriple=x86_64-unknown-linux < %s | FileCheck %s @g = external global i8 @@ -16,14 +17,15 @@ declare void @f9() declare void @llvm.icall.branch.funnel(...) define void @jt2(ptr nest, ...) { - ; CHECK: jt2: - ; CHECK: leaq g+1(%rip), %r11 - ; CHECK-NEXT: cmpq %r11, %r10 - ; CHECK-NEXT: jae .LBB0_1 - ; CHECK-NEXT: # - ; CHECK-NEXT: jmp f0 - ; CHECK-NEXT: .LBB0_1: - ; CHECK-NEXT: jmp f1 +; CHECK-LABEL: jt2: +; CHECK: # %bb.0: +; CHECK-NEXT: leaq g+1(%rip), %r11 +; CHECK-NEXT: cmpq %r11, %r10 +; CHECK-NEXT: jae .LBB0_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: jmp f0 # TAILCALL +; CHECK-NEXT: .LBB0_2: +; CHECK-NEXT: jmp f1 # TAILCALL musttail call void (...) @llvm.icall.branch.funnel( ptr %0, ptr @g, ptr @f0, @@ -34,18 +36,19 @@ define void @jt2(ptr nest, ...) { } define void @jt3(ptr nest, ...) { - ; CHECK: jt3: - ; CHECK: leaq g+1(%rip), %r11 - ; CHECK-NEXT: cmpq %r11, %r10 - ; CHECK-NEXT: jae .LBB1_1 - ; CHECK-NEXT: # - ; CHECK-NEXT: jmp f0 - ; CHECK-NEXT: .LBB1_1: - ; CHECK-NEXT: jne .LBB1_2 - ; CHECK-NEXT: # - ; CHECK-NEXT: jmp f1 - ; CHECK-NEXT: .LBB1_2: - ; CHECK-NEXT: jmp f2 +; CHECK-LABEL: jt3: +; CHECK: # %bb.0: +; CHECK-NEXT: leaq g+1(%rip), %r11 +; CHECK-NEXT: cmpq %r11, %r10 +; CHECK-NEXT: jae .LBB1_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: jmp f0 # TAILCALL +; CHECK-NEXT: .LBB1_2: +; CHECK-NEXT: jne .LBB1_4 +; CHECK-NEXT: # %bb.3: +; CHECK-NEXT: jmp f1 # TAILCALL +; CHECK-NEXT: .LBB1_4: +; CHECK-NEXT: jmp f2 # TAILCALL musttail call void (...) @llvm.icall.branch.funnel( ptr %0, ptr @g, ptr @f0, @@ -57,38 +60,39 @@ define void @jt3(ptr nest, ...) { } define void @jt7(ptr nest, ...) { - ; CHECK: jt7: - ; CHECK: leaq g+3(%rip), %r11 - ; CHECK-NEXT: cmpq %r11, %r10 - ; CHECK-NEXT: jae .LBB2_1 - ; CHECK-NEXT: # - ; CHECK-NEXT: leaq g+1(%rip), %r11 - ; CHECK-NEXT: cmpq %r11, %r10 - ; CHECK-NEXT: jae .LBB2_6 - ; CHECK-NEXT: # - ; CHECK-NEXT: jmp f0 - ; CHECK-NEXT: .LBB2_1: - ; CHECK-NEXT: jne .LBB2_2 - ; CHECK-NEXT: # - ; CHECK-NEXT: jmp f3 - ; CHECK-NEXT: .LBB2_6: - ; CHECK-NEXT: jne .LBB2_7 - ; CHECK-NEXT: # - ; CHECK-NEXT: jmp f1 - ; CHECK-NEXT: .LBB2_2: - ; CHECK-NEXT: leaq g+5(%rip), %r11 - ; CHECK-NEXT: cmpq %r11, %r10 - ; CHECK-NEXT: jae .LBB2_3 - ; CHECK-NEXT: # - ; CHECK-NEXT: jmp f4 - ; CHECK-NEXT: .LBB2_7: - ; CHECK-NEXT: jmp f2 - ; CHECK-NEXT: .LBB2_3: - ; CHECK-NEXT: jne .LBB2_4 - ; CHECK-NEXT: # - ; CHECK-NEXT: jmp f5 - ; CHECK-NEXT: .LBB2_4: - ; CHECK-NEXT: jmp f6 +; CHECK-LABEL: jt7: +; CHECK: # %bb.0: +; CHECK-NEXT: leaq g+3(%rip), %r11 +; CHECK-NEXT: cmpq %r11, %r10 +; CHECK-NEXT: jae .LBB2_3 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: leaq g+1(%rip), %r11 +; CHECK-NEXT: cmpq %r11, %r10 +; CHECK-NEXT: jae .LBB2_5 +; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: jmp f0 # TAILCALL +; CHECK-NEXT: .LBB2_3: +; CHECK-NEXT: jne .LBB2_7 +; CHECK-NEXT: # %bb.4: +; CHECK-NEXT: jmp f3 # TAILCALL +; CHECK-NEXT: .LBB2_5: +; CHECK-NEXT: jne .LBB2_9 +; CHECK-NEXT: # %bb.6: +; CHECK-NEXT: jmp f1 # TAILCALL +; CHECK-NEXT: .LBB2_7: +; CHECK-NEXT: leaq g+5(%rip), %r11 +; CHECK-NEXT: cmpq %r11, %r10 +; CHECK-NEXT: jae .LBB2_10 +; CHECK-NEXT: # %bb.8: +; CHECK-NEXT: jmp f4 # TAILCALL +; CHECK-NEXT: .LBB2_9: +; CHECK-NEXT: jmp f2 # TAILCALL +; CHECK-NEXT: .LBB2_10: +; CHECK-NEXT: jne .LBB2_12 +; CHECK-NEXT: # %bb.11: +; CHECK-NEXT: jmp f5 # TAILCALL +; CHECK-NEXT: .LBB2_12: +; CHECK-NEXT: jmp f6 # TAILCALL musttail call void (...) @llvm.icall.branch.funnel( ptr %0, ptr @g, ptr @f0, @@ -104,54 +108,55 @@ define void @jt7(ptr nest, ...) { } define void @jt10(ptr nest, ...) { - ; CHECK: jt10: - ; CHECK: leaq g+5(%rip), %r11 - ; CHECK-NEXT: cmpq %r11, %r10 - ; CHECK-NEXT: jae .LBB3_1 - ; CHECK-NEXT: # - ; CHECK-NEXT: leaq g+1(%rip), %r11 - ; CHECK-NEXT: cmpq %r11, %r10 - ; CHECK-NEXT: jae .LBB3_7 - ; CHECK-NEXT: # - ; CHECK-NEXT: jmp f0 - ; CHECK-NEXT: .LBB3_1: - ; CHECK-NEXT: jne .LBB3_2 - ; CHECK-NEXT: # - ; CHECK-NEXT: jmp f5 - ; CHECK-NEXT: .LBB3_7: - ; CHECK-NEXT: jne .LBB3_8 - ; CHECK-NEXT: # - ; CHECK-NEXT: jmp f1 - ; CHECK-NEXT: .LBB3_2: - ; CHECK-NEXT: leaq g+7(%rip), %r11 - ; CHECK-NEXT: cmpq %r11, %r10 - ; CHECK-NEXT: jae .LBB3_3 - ; CHECK-NEXT: # - ; CHECK-NEXT: jmp f6 - ; CHECK-NEXT: .LBB3_8: - ; CHECK-NEXT: leaq g+3(%rip), %r11 - ; CHECK-NEXT: cmpq %r11, %r10 - ; CHECK-NEXT: jae .LBB3_9 - ; CHECK-NEXT: # - ; CHECK-NEXT: jmp f2 - ; CHECK-NEXT: .LBB3_3: - ; CHECK-NEXT: jne .LBB3_4 - ; CHECK-NEXT: # - ; CHECK-NEXT: jmp f7 - ; CHECK-NEXT: .LBB3_9: - ; CHECK-NEXT: jne .LBB3_10 - ; CHECK-NEXT: # - ; CHECK-NEXT: jmp f3 - ; CHECK-NEXT: .LBB3_4: - ; CHECK-NEXT: leaq g+9(%rip), %r11 - ; CHECK-NEXT: cmpq %r11, %r10 - ; CHECK-NEXT: jae .LBB3_5 - ; CHECK-NEXT: # - ; CHECK-NEXT: jmp f8 - ; CHECK-NEXT: .LBB3_10: - ; CHECK-NEXT: jmp f4 - ; CHECK-NEXT: .LBB3_5: - ; CHECK-NEXT: jmp f9 +; CHECK-LABEL: jt10: +; CHECK: # %bb.0: +; CHECK-NEXT: leaq g+5(%rip), %r11 +; CHECK-NEXT: cmpq %r11, %r10 +; CHECK-NEXT: jae .LBB3_3 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: leaq g+1(%rip), %r11 +; CHECK-NEXT: cmpq %r11, %r10 +; CHECK-NEXT: jae .LBB3_5 +; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: jmp f0 # TAILCALL +; CHECK-NEXT: .LBB3_3: +; CHECK-NEXT: jne .LBB3_7 +; CHECK-NEXT: # %bb.4: +; CHECK-NEXT: jmp f5 # TAILCALL +; CHECK-NEXT: .LBB3_5: +; CHECK-NEXT: jne .LBB3_9 +; CHECK-NEXT: # %bb.6: +; CHECK-NEXT: jmp f1 # TAILCALL +; CHECK-NEXT: .LBB3_7: +; CHECK-NEXT: leaq g+7(%rip), %r11 +; CHECK-NEXT: cmpq %r11, %r10 +; CHECK-NEXT: jae .LBB3_11 +; CHECK-NEXT: # %bb.8: +; CHECK-NEXT: jmp f6 # TAILCALL +; CHECK-NEXT: .LBB3_9: +; CHECK-NEXT: leaq g+3(%rip), %r11 +; CHECK-NEXT: cmpq %r11, %r10 +; CHECK-NEXT: jae .LBB3_13 +; CHECK-NEXT: # %bb.10: +; CHECK-NEXT: jmp f2 # TAILCALL +; CHECK-NEXT: .LBB3_11: +; CHECK-NEXT: jne .LBB3_15 +; CHECK-NEXT: # %bb.12: +; CHECK-NEXT: jmp f7 # TAILCALL +; CHECK-NEXT: .LBB3_13: +; CHECK-NEXT: jne .LBB3_17 +; CHECK-NEXT: # %bb.14: +; CHECK-NEXT: jmp f3 # TAILCALL +; CHECK-NEXT: .LBB3_15: +; CHECK-NEXT: leaq g+9(%rip), %r11 +; CHECK-NEXT: cmpq %r11, %r10 +; CHECK-NEXT: jae .LBB3_18 +; CHECK-NEXT: # %bb.16: +; CHECK-NEXT: jmp f8 # TAILCALL +; CHECK-NEXT: .LBB3_17: +; CHECK-NEXT: jmp f4 # TAILCALL +; CHECK-NEXT: .LBB3_18: +; CHECK-NEXT: jmp f9 # TAILCALL musttail call void (...) @llvm.icall.branch.funnel( ptr %0, ptr @g, ptr @f0, diff --git a/llvm/test/CodeGen/X86/implicit-null-check.ll b/llvm/test/CodeGen/X86/implicit-null-check.ll index de63c9ae209df..a69049b98649c 100644 --- a/llvm/test/CodeGen/X86/implicit-null-check.ll +++ b/llvm/test/CodeGen/X86/implicit-null-check.ll @@ -5,10 +5,10 @@ define i32 @imp_null_check_load(ptr %x) { ; CHECK-LABEL: imp_null_check_load: ; CHECK: ## %bb.0: ## %entry ; CHECK-NEXT: Ltmp0: -; CHECK-NEXT: movl (%rdi), %eax ## on-fault: LBB0_1 -; CHECK-NEXT: ## %bb.2: ## %not_null +; CHECK-NEXT: movl (%rdi), %eax ## on-fault: LBB0_2 +; CHECK-NEXT: ## %bb.1: ## %not_null ; CHECK-NEXT: retq -; CHECK-NEXT: LBB0_1: ## %is_null +; CHECK-NEXT: LBB0_2: ## %is_null ; CHECK-NEXT: movl $42, %eax ; CHECK-NEXT: retq @@ -29,10 +29,10 @@ define i32 @imp_null_check_unordered_load(ptr %x) { ; CHECK-LABEL: imp_null_check_unordered_load: ; CHECK: ## %bb.0: ## %entry ; CHECK-NEXT: Ltmp1: -; CHECK-NEXT: movl (%rdi), %eax ## on-fault: LBB1_1 -; CHECK-NEXT: ## %bb.2: ## %not_null +; CHECK-NEXT: movl (%rdi), %eax ## on-fault: LBB1_2 +; CHECK-NEXT: ## %bb.1: ## %not_null ; CHECK-NEXT: retq -; CHECK-NEXT: LBB1_1: ## %is_null +; CHECK-NEXT: LBB1_2: ## %is_null ; CHECK-NEXT: movl $42, %eax ; CHECK-NEXT: retq @@ -55,11 +55,11 @@ define i32 @imp_null_check_seq_cst_load(ptr %x) { ; CHECK-LABEL: imp_null_check_seq_cst_load: ; CHECK: ## %bb.0: ## %entry ; CHECK-NEXT: testq %rdi, %rdi -; CHECK-NEXT: je LBB2_1 -; CHECK-NEXT: ## %bb.2: ## %not_null +; CHECK-NEXT: je LBB2_2 +; CHECK-NEXT: ## %bb.1: ## %not_null ; CHECK-NEXT: movl (%rdi), %eax ; CHECK-NEXT: retq -; CHECK-NEXT: LBB2_1: ## %is_null +; CHECK-NEXT: LBB2_2: ## %is_null ; CHECK-NEXT: movl $42, %eax ; CHECK-NEXT: retq @@ -80,11 +80,11 @@ define i32 @imp_null_check_volatile_load(ptr %x) { ; CHECK-LABEL: imp_null_check_volatile_load: ; CHECK: ## %bb.0: ## %entry ; CHECK-NEXT: testq %rdi, %rdi -; CHECK-NEXT: je LBB3_1 -; CHECK-NEXT: ## %bb.2: ## %not_null +; CHECK-NEXT: je LBB3_2 +; CHECK-NEXT: ## %bb.1: ## %not_null ; CHECK-NEXT: movl (%rdi), %eax ; CHECK-NEXT: retq -; CHECK-NEXT: LBB3_1: ## %is_null +; CHECK-NEXT: LBB3_2: ## %is_null ; CHECK-NEXT: movl $42, %eax ; CHECK-NEXT: retq @@ -105,10 +105,10 @@ define i8 @imp_null_check_load_i8(ptr %x) { ; CHECK-LABEL: imp_null_check_load_i8: ; CHECK: ## %bb.0: ## %entry ; CHECK-NEXT: Ltmp2: -; CHECK-NEXT: movb (%rdi), %al ## on-fault: LBB4_1 -; CHECK-NEXT: ## %bb.2: ## %not_null +; CHECK-NEXT: movb (%rdi), %al ## on-fault: LBB4_2 +; CHECK-NEXT: ## %bb.1: ## %not_null ; CHECK-NEXT: retq -; CHECK-NEXT: LBB4_1: ## %is_null +; CHECK-NEXT: LBB4_2: ## %is_null ; CHECK-NEXT: movb $42, %al ; CHECK-NEXT: retq @@ -129,13 +129,13 @@ define i256 @imp_null_check_load_i256(ptr %x) { ; CHECK: ## %bb.0: ## %entry ; CHECK-NEXT: movq %rdi, %rax ; CHECK-NEXT: Ltmp3: -; CHECK-NEXT: movaps (%rsi), %xmm0 ## on-fault: LBB5_1 -; CHECK-NEXT: ## %bb.2: ## %not_null +; CHECK-NEXT: movaps (%rsi), %xmm0 ## on-fault: LBB5_2 +; CHECK-NEXT: ## %bb.1: ## %not_null ; CHECK-NEXT: movaps 16(%rsi), %xmm1 ; CHECK-NEXT: movaps %xmm1, 16(%rax) ; CHECK-NEXT: movaps %xmm0, (%rax) ; CHECK-NEXT: retq -; CHECK-NEXT: LBB5_1: ## %is_null +; CHECK-NEXT: LBB5_2: ## %is_null ; CHECK-NEXT: xorps %xmm0, %xmm0 ; CHECK-NEXT: movaps %xmm0, 16(%rax) ; CHECK-NEXT: movq $0, 8(%rax) @@ -160,10 +160,10 @@ define i32 @imp_null_check_gep_load(ptr %x) { ; CHECK-LABEL: imp_null_check_gep_load: ; CHECK: ## %bb.0: ## %entry ; CHECK-NEXT: Ltmp4: -; CHECK-NEXT: movl 128(%rdi), %eax ## on-fault: LBB6_1 -; CHECK-NEXT: ## %bb.2: ## %not_null +; CHECK-NEXT: movl 128(%rdi), %eax ## on-fault: LBB6_2 +; CHECK-NEXT: ## %bb.1: ## %not_null ; CHECK-NEXT: retq -; CHECK-NEXT: LBB6_1: ## %is_null +; CHECK-NEXT: LBB6_2: ## %is_null ; CHECK-NEXT: movl $42, %eax ; CHECK-NEXT: retq @@ -184,11 +184,11 @@ define i32 @imp_null_check_add_result(ptr %x, i32 %p) { ; CHECK-LABEL: imp_null_check_add_result: ; CHECK: ## %bb.0: ## %entry ; CHECK-NEXT: Ltmp5: -; CHECK-NEXT: addl (%rdi), %esi ## on-fault: LBB7_1 -; CHECK-NEXT: ## %bb.2: ## %not_null +; CHECK-NEXT: addl (%rdi), %esi ## on-fault: LBB7_2 +; CHECK-NEXT: ## %bb.1: ## %not_null ; CHECK-NEXT: movl %esi, %eax ; CHECK-NEXT: retq -; CHECK-NEXT: LBB7_1: ## %is_null +; CHECK-NEXT: LBB7_2: ## %is_null ; CHECK-NEXT: movl $42, %eax ; CHECK-NEXT: retq @@ -209,11 +209,11 @@ define i32 @imp_null_check_sub_result(ptr %x, i32 %p) { ; CHECK-LABEL: imp_null_check_sub_result: ; CHECK: ## %bb.0: ## %entry ; CHECK-NEXT: Ltmp6: -; CHECK-NEXT: movl (%rdi), %eax ## on-fault: LBB8_1 -; CHECK-NEXT: ## %bb.2: ## %not_null +; CHECK-NEXT: movl (%rdi), %eax ## on-fault: LBB8_2 +; CHECK-NEXT: ## %bb.1: ## %not_null ; CHECK-NEXT: subl %esi, %eax ; CHECK-NEXT: retq -; CHECK-NEXT: LBB8_1: ## %is_null +; CHECK-NEXT: LBB8_2: ## %is_null ; CHECK-NEXT: movl $42, %eax ; CHECK-NEXT: retq @@ -234,11 +234,11 @@ define i32 @imp_null_check_mul_result(ptr %x, i32 %p) { ; CHECK-LABEL: imp_null_check_mul_result: ; CHECK: ## %bb.0: ## %entry ; CHECK-NEXT: Ltmp7: -; CHECK-NEXT: imull (%rdi), %esi ## on-fault: LBB9_1 -; CHECK-NEXT: ## %bb.2: ## %not_null +; CHECK-NEXT: imull (%rdi), %esi ## on-fault: LBB9_2 +; CHECK-NEXT: ## %bb.1: ## %not_null ; CHECK-NEXT: movl %esi, %eax ; CHECK-NEXT: retq -; CHECK-NEXT: LBB9_1: ## %is_null +; CHECK-NEXT: LBB9_2: ## %is_null ; CHECK-NEXT: movl $42, %eax ; CHECK-NEXT: retq @@ -259,12 +259,12 @@ define i32 @imp_null_check_udiv_result(ptr %x, i32 %p) { ; CHECK-LABEL: imp_null_check_udiv_result: ; CHECK: ## %bb.0: ## %entry ; CHECK-NEXT: Ltmp8: -; CHECK-NEXT: movl (%rdi), %eax ## on-fault: LBB10_1 -; CHECK-NEXT: ## %bb.2: ## %not_null +; CHECK-NEXT: movl (%rdi), %eax ## on-fault: LBB10_2 +; CHECK-NEXT: ## %bb.1: ## %not_null ; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: divl %esi ; CHECK-NEXT: retq -; CHECK-NEXT: LBB10_1: ## %is_null +; CHECK-NEXT: LBB10_2: ## %is_null ; CHECK-NEXT: movl $42, %eax ; CHECK-NEXT: retq @@ -285,12 +285,12 @@ define i32 @imp_null_check_shl_result(ptr %x, i32 %p) { ; CHECK-LABEL: imp_null_check_shl_result: ; CHECK: ## %bb.0: ## %entry ; CHECK-NEXT: Ltmp9: -; CHECK-NEXT: movl (%rdi), %eax ## on-fault: LBB11_1 -; CHECK-NEXT: ## %bb.2: ## %not_null +; CHECK-NEXT: movl (%rdi), %eax ## on-fault: LBB11_2 +; CHECK-NEXT: ## %bb.1: ## %not_null ; CHECK-NEXT: movl %esi, %ecx ; CHECK-NEXT: shll %cl, %eax ; CHECK-NEXT: retq -; CHECK-NEXT: LBB11_1: ## %is_null +; CHECK-NEXT: LBB11_2: ## %is_null ; CHECK-NEXT: movl $42, %eax ; CHECK-NEXT: retq @@ -311,12 +311,12 @@ define i32 @imp_null_check_lshr_result(ptr %x, i32 %p) { ; CHECK-LABEL: imp_null_check_lshr_result: ; CHECK: ## %bb.0: ## %entry ; CHECK-NEXT: Ltmp10: -; CHECK-NEXT: movl (%rdi), %eax ## on-fault: LBB12_1 -; CHECK-NEXT: ## %bb.2: ## %not_null +; CHECK-NEXT: movl (%rdi), %eax ## on-fault: LBB12_2 +; CHECK-NEXT: ## %bb.1: ## %not_null ; CHECK-NEXT: movl %esi, %ecx ; CHECK-NEXT: shrl %cl, %eax ; CHECK-NEXT: retq -; CHECK-NEXT: LBB12_1: ## %is_null +; CHECK-NEXT: LBB12_2: ## %is_null ; CHECK-NEXT: movl $42, %eax ; CHECK-NEXT: retq @@ -340,12 +340,12 @@ define i32 @imp_null_check_hoist_over_unrelated_load(ptr %x, ptr %y, ptr %z) { ; CHECK-LABEL: imp_null_check_hoist_over_unrelated_load: ; CHECK: ## %bb.0: ## %entry ; CHECK-NEXT: Ltmp11: -; CHECK-NEXT: movl (%rdi), %eax ## on-fault: LBB13_1 -; CHECK-NEXT: ## %bb.2: ## %not_null +; CHECK-NEXT: movl (%rdi), %eax ## on-fault: LBB13_2 +; CHECK-NEXT: ## %bb.1: ## %not_null ; CHECK-NEXT: movl (%rsi), %ecx ; CHECK-NEXT: movl %ecx, (%rdx) ; CHECK-NEXT: retq -; CHECK-NEXT: LBB13_1: ## %is_null +; CHECK-NEXT: LBB13_2: ## %is_null ; CHECK-NEXT: movl $42, %eax ; CHECK-NEXT: retq @@ -369,14 +369,14 @@ define i32 @imp_null_check_via_mem_comparision(ptr %x, i32 %val) { ; CHECK-NEXT: Ltmp12: ; CHECK-NEXT: cmpl %esi, 4(%rdi) ## on-fault: LBB14_3 ; CHECK-NEXT: ## %bb.1: ## %not_null -; CHECK-NEXT: jge LBB14_2 -; CHECK-NEXT: ## %bb.4: ## %ret_100 +; CHECK-NEXT: jge LBB14_4 +; CHECK-NEXT: ## %bb.2: ## %ret_100 ; CHECK-NEXT: movl $100, %eax ; CHECK-NEXT: retq ; CHECK-NEXT: LBB14_3: ## %is_null ; CHECK-NEXT: movl $42, %eax ; CHECK-NEXT: retq -; CHECK-NEXT: LBB14_2: ## %ret_200 +; CHECK-NEXT: LBB14_4: ## %ret_200 ; CHECK-NEXT: movl $200, %eax ; CHECK-NEXT: retq @@ -405,12 +405,12 @@ define i32 @imp_null_check_gep_load_with_use_dep(ptr %x, i32 %a) { ; CHECK: ## %bb.0: ## %entry ; CHECK-NEXT: ## kill: def $esi killed $esi def $rsi ; CHECK-NEXT: Ltmp13: -; CHECK-NEXT: movl (%rdi), %eax ## on-fault: LBB15_1 -; CHECK-NEXT: ## %bb.2: ## %not_null +; CHECK-NEXT: movl (%rdi), %eax ## on-fault: LBB15_2 +; CHECK-NEXT: ## %bb.1: ## %not_null ; CHECK-NEXT: addl %edi, %esi ; CHECK-NEXT: leal 4(%rax,%rsi), %eax ; CHECK-NEXT: retq -; CHECK-NEXT: LBB15_1: ## %is_null +; CHECK-NEXT: LBB15_2: ## %is_null ; CHECK-NEXT: movl $42, %eax ; CHECK-NEXT: retq @@ -436,12 +436,12 @@ define i32 @imp_null_check_load_fence1(ptr %x) { ; CHECK-LABEL: imp_null_check_load_fence1: ; CHECK: ## %bb.0: ## %entry ; CHECK-NEXT: testq %rdi, %rdi -; CHECK-NEXT: je LBB16_1 -; CHECK-NEXT: ## %bb.2: ## %not_null +; CHECK-NEXT: je LBB16_2 +; CHECK-NEXT: ## %bb.1: ## %not_null ; CHECK-NEXT: ##MEMBARRIER ; CHECK-NEXT: movl (%rdi), %eax ; CHECK-NEXT: retq -; CHECK-NEXT: LBB16_1: ## %is_null +; CHECK-NEXT: LBB16_2: ## %is_null ; CHECK-NEXT: movl $42, %eax ; CHECK-NEXT: retq @@ -464,12 +464,12 @@ define i32 @imp_null_check_load_fence2(ptr %x) { ; CHECK-LABEL: imp_null_check_load_fence2: ; CHECK: ## %bb.0: ## %entry ; CHECK-NEXT: testq %rdi, %rdi -; CHECK-NEXT: je LBB17_1 -; CHECK-NEXT: ## %bb.2: ## %not_null +; CHECK-NEXT: je LBB17_2 +; CHECK-NEXT: ## %bb.1: ## %not_null ; CHECK-NEXT: lock orl $0, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movl (%rdi), %eax ; CHECK-NEXT: retq -; CHECK-NEXT: LBB17_1: ## %is_null +; CHECK-NEXT: LBB17_2: ## %is_null ; CHECK-NEXT: movl $42, %eax ; CHECK-NEXT: retq @@ -490,10 +490,10 @@ define void @imp_null_check_store(ptr %x) { ; CHECK-LABEL: imp_null_check_store: ; CHECK: ## %bb.0: ## %entry ; CHECK-NEXT: Ltmp14: -; CHECK-NEXT: movl $1, (%rdi) ## on-fault: LBB18_1 -; CHECK-NEXT: ## %bb.2: ## %not_null +; CHECK-NEXT: movl $1, (%rdi) ## on-fault: LBB18_2 +; CHECK-NEXT: ## %bb.1: ## %not_null ; CHECK-NEXT: retq -; CHECK-NEXT: LBB18_1: ## %is_null +; CHECK-NEXT: LBB18_2: ## %is_null ; CHECK-NEXT: retq entry: @@ -513,10 +513,10 @@ define void @imp_null_check_unordered_store(ptr %x) { ; CHECK-LABEL: imp_null_check_unordered_store: ; CHECK: ## %bb.0: ## %entry ; CHECK-NEXT: Ltmp15: -; CHECK-NEXT: movl $1, (%rdi) ## on-fault: LBB19_1 -; CHECK-NEXT: ## %bb.2: ## %not_null +; CHECK-NEXT: movl $1, (%rdi) ## on-fault: LBB19_2 +; CHECK-NEXT: ## %bb.1: ## %not_null ; CHECK-NEXT: retq -; CHECK-NEXT: LBB19_1: ## %is_null +; CHECK-NEXT: LBB19_2: ## %is_null ; CHECK-NEXT: retq entry: @@ -535,10 +535,10 @@ define i32 @imp_null_check_neg_gep_load(ptr %x) { ; CHECK-LABEL: imp_null_check_neg_gep_load: ; CHECK: ## %bb.0: ## %entry ; CHECK-NEXT: Ltmp16: -; CHECK-NEXT: movl -128(%rdi), %eax ## on-fault: LBB20_1 -; CHECK-NEXT: ## %bb.2: ## %not_null +; CHECK-NEXT: movl -128(%rdi), %eax ## on-fault: LBB20_2 +; CHECK-NEXT: ## %bb.1: ## %not_null ; CHECK-NEXT: retq -; CHECK-NEXT: LBB20_1: ## %is_null +; CHECK-NEXT: LBB20_2: ## %is_null ; CHECK-NEXT: movl $42, %eax ; CHECK-NEXT: retq @@ -564,10 +564,10 @@ define i64 @imp_null_check_load_shift_addr(ptr %x) { ; CHECK: ## %bb.0: ## %entry ; CHECK-NEXT: shlq $6, %rdi ; CHECK-NEXT: Ltmp17: -; CHECK-NEXT: movq 8(%rdi), %rax ## on-fault: LBB21_1 -; CHECK-NEXT: ## %bb.2: ## %not_null +; CHECK-NEXT: movq 8(%rdi), %rax ## on-fault: LBB21_2 +; CHECK-NEXT: ## %bb.1: ## %not_null ; CHECK-NEXT: retq -; CHECK-NEXT: LBB21_1: ## %is_null +; CHECK-NEXT: LBB21_2: ## %is_null ; CHECK-NEXT: movl $42, %eax ; CHECK-NEXT: retq @@ -593,10 +593,10 @@ define i64 @imp_null_check_load_shift_by_3_addr(ptr %x) { ; CHECK-LABEL: imp_null_check_load_shift_by_3_addr: ; CHECK: ## %bb.0: ## %entry ; CHECK-NEXT: Ltmp18: -; CHECK-NEXT: movq 8(,%rdi,8), %rax ## on-fault: LBB22_1 -; CHECK-NEXT: ## %bb.2: ## %not_null +; CHECK-NEXT: movq 8(,%rdi,8), %rax ## on-fault: LBB22_2 +; CHECK-NEXT: ## %bb.1: ## %not_null ; CHECK-NEXT: retq -; CHECK-NEXT: LBB22_1: ## %is_null +; CHECK-NEXT: LBB22_2: ## %is_null ; CHECK-NEXT: movl $42, %eax ; CHECK-NEXT: retq @@ -620,10 +620,10 @@ define i64 @imp_null_check_load_shift_add_addr(ptr %x) { ; CHECK-LABEL: imp_null_check_load_shift_add_addr: ; CHECK: ## %bb.0: ## %entry ; CHECK-NEXT: Ltmp19: -; CHECK-NEXT: movq 3526(,%rdi,8), %rax ## on-fault: LBB23_1 -; CHECK-NEXT: ## %bb.2: ## %not_null +; CHECK-NEXT: movq 3526(,%rdi,8), %rax ## on-fault: LBB23_2 +; CHECK-NEXT: ## %bb.1: ## %not_null ; CHECK-NEXT: retq -; CHECK-NEXT: LBB23_1: ## %is_null +; CHECK-NEXT: LBB23_2: ## %is_null ; CHECK-NEXT: movl $42, %eax ; CHECK-NEXT: retq diff --git a/llvm/test/CodeGen/X86/indirect-branch-tracking-eh.ll b/llvm/test/CodeGen/X86/indirect-branch-tracking-eh.ll index 8403d4b754d80..3c0975a872f42 100644 --- a/llvm/test/CodeGen/X86/indirect-branch-tracking-eh.ll +++ b/llvm/test/CodeGen/X86/indirect-branch-tracking-eh.ll @@ -52,9 +52,9 @@ ; SJLJ-NEXT: leal ; SJLJ-NEXT: movl ; SJLJ-NEXT: cmpl -; SJLJ-NEXT: jb LBB0_4 +; SJLJ-NEXT: jb LBB0_5 -; SJLJ: LBB0_4: +; SJLJ: LBB0_5: ; SJLJ-NEXT: jmpl *LJTI0_0(,%eax,4) ; SJLJ: LBB0_6: # %lpad diff --git a/llvm/test/CodeGen/X86/indirect-branch-tracking-eh2.ll b/llvm/test/CodeGen/X86/indirect-branch-tracking-eh2.ll index 1c48e8c581446..7528c23fcad74 100644 --- a/llvm/test/CodeGen/X86/indirect-branch-tracking-eh2.ll +++ b/llvm/test/CodeGen/X86/indirect-branch-tracking-eh2.ll @@ -23,16 +23,16 @@ define dso_local i32 @main() #0 personality ptr @__gxx_personality_sj0 { ; NUM-NEXT: movq $GCC_except_table0, -112(%rbp) ; NUM-NEXT: movq %rbp, -104(%rbp) ; NUM-NEXT: movq %rsp, -88(%rbp) -; NUM-NEXT: movq $.LBB0_9, -96(%rbp) +; NUM-NEXT: movq $.LBB0_3, -96(%rbp) ; NUM-NEXT: leaq -152(%rbp), %rdi ; NUM-NEXT: callq _Unwind_SjLj_Register@PLT ; NUM-NEXT: movl $1, -144(%rbp) -; NUM-NEXT: .Ltmp0: +; NUM-NEXT: .Ltmp0: # EH_LABEL ; NUM-NEXT: callq _Z3foov -; NUM-NEXT: .Ltmp1: +; NUM-NEXT: .Ltmp1: # EH_LABEL ; NUM-NEXT: # %bb.1: # %invoke.cont ; NUM-NEXT: movl $1, -44(%rbp) -; NUM-NEXT: .LBB0_7: # %return +; NUM-NEXT: .LBB0_2: # %return ; NUM-NEXT: movl -44(%rbp), %ebx ; NUM-NEXT: leaq -152(%rbp), %rdi ; NUM-NEXT: callq _Unwind_SjLj_Unregister@PLT @@ -45,26 +45,26 @@ define dso_local i32 @main() #0 personality ptr @__gxx_personality_sj0 { ; NUM-NEXT: popq %r15 ; NUM-NEXT: popq %rbp ; NUM-NEXT: retq -; NUM-NEXT: .LBB0_9: +; NUM-NEXT: .LBB0_3: ; NUM-NEXT: endbr64 ; NUM-NEXT: movl -144(%rbp), %eax ; NUM-NEXT: cmpl $1, %eax -; NUM-NEXT: jb .LBB0_10 -; NUM-NEXT: # %bb.11: +; NUM-NEXT: jb .LBB0_5 +; NUM-NEXT: # %bb.4: ; NUM-NEXT: ud2 -; NUM-NEXT: .LBB0_10: +; NUM-NEXT: .LBB0_5: ; NUM-NEXT: leaq .LJTI0_0(%rip), %rcx ; NUM-NEXT: jmpq *(%rcx,%rax,8) -; NUM-NEXT: .LBB0_2: # %lpad -; NUM-NEXT: .Ltmp2: +; NUM-NEXT: .LBB0_6: # %lpad +; NUM-NEXT: .Ltmp2: # EH_LABEL ; NUM-NEXT: endbr64 ; NUM-NEXT: movl -140(%rbp), %ecx ; NUM-NEXT: movl -136(%rbp), %eax ; NUM-NEXT: movq %rcx, -56(%rbp) ; NUM-NEXT: movl %eax, -64(%rbp) ; NUM-NEXT: cmpl $2, %eax -; NUM-NEXT: jne .LBB0_4 -; NUM-NEXT: # %bb.3: # %catch3 +; NUM-NEXT: jne .LBB0_8 +; NUM-NEXT: # %bb.7: # %catch3 ; NUM-NEXT: movq -56(%rbp), %rdi ; NUM-NEXT: movl $-1, -144(%rbp) ; NUM-NEXT: callq __cxa_begin_catch @@ -72,11 +72,11 @@ define dso_local i32 @main() #0 personality ptr @__gxx_personality_sj0 { ; NUM-NEXT: movl %eax, -60(%rbp) ; NUM-NEXT: xorl %ecx, %ecx ; NUM-NEXT: cmpl $5, %eax -; NUM-NEXT: jmp .LBB0_6 -; NUM-NEXT: .LBB0_4: # %catch.fallthrough +; NUM-NEXT: jmp .LBB0_10 +; NUM-NEXT: .LBB0_8: # %catch.fallthrough ; NUM-NEXT: cmpl $1, %eax -; NUM-NEXT: jne .LBB0_8 -; NUM-NEXT: # %bb.5: # %catch +; NUM-NEXT: jne .LBB0_11 +; NUM-NEXT: # %bb.9: # %catch ; NUM-NEXT: movq -56(%rbp), %rdi ; NUM-NEXT: movl $-1, -144(%rbp) ; NUM-NEXT: callq __cxa_begin_catch @@ -84,13 +84,13 @@ define dso_local i32 @main() #0 personality ptr @__gxx_personality_sj0 { ; NUM-NEXT: movb %al, -45(%rbp) ; NUM-NEXT: xorl %ecx, %ecx ; NUM-NEXT: cmpb $3, %al -; NUM-NEXT: .LBB0_6: # %return +; NUM-NEXT: .LBB0_10: # %return ; NUM-NEXT: setne %cl ; NUM-NEXT: movl %ecx, -44(%rbp) ; NUM-NEXT: movl $-1, -144(%rbp) ; NUM-NEXT: callq __cxa_end_catch -; NUM-NEXT: jmp .LBB0_7 -; NUM-NEXT: .LBB0_8: # %eh.resume +; NUM-NEXT: jmp .LBB0_2 +; NUM-NEXT: .LBB0_11: # %eh.resume ; NUM-NEXT: movl $-1, -144(%rbp) ; ; SJLJ-LABEL: main: @@ -109,16 +109,16 @@ define dso_local i32 @main() #0 personality ptr @__gxx_personality_sj0 { ; SJLJ-NEXT: movq $GCC_except_table0, -112(%rbp) ; SJLJ-NEXT: movq %rbp, -104(%rbp) ; SJLJ-NEXT: movq %rsp, -88(%rbp) -; SJLJ-NEXT: movq $.LBB0_9, -96(%rbp) +; SJLJ-NEXT: movq $.LBB0_3, -96(%rbp) ; SJLJ-NEXT: leaq -152(%rbp), %rdi ; SJLJ-NEXT: callq _Unwind_SjLj_Register@PLT ; SJLJ-NEXT: movl $1, -144(%rbp) -; SJLJ-NEXT: .Ltmp0: +; SJLJ-NEXT: .Ltmp0: # EH_LABEL ; SJLJ-NEXT: callq _Z3foov -; SJLJ-NEXT: .Ltmp1: +; SJLJ-NEXT: .Ltmp1: # EH_LABEL ; SJLJ-NEXT: # %bb.1: # %invoke.cont ; SJLJ-NEXT: movl $1, -44(%rbp) -; SJLJ-NEXT: .LBB0_7: # %return +; SJLJ-NEXT: .LBB0_2: # %return ; SJLJ-NEXT: movl -44(%rbp), %ebx ; SJLJ-NEXT: leaq -152(%rbp), %rdi ; SJLJ-NEXT: callq _Unwind_SjLj_Unregister@PLT @@ -131,26 +131,26 @@ define dso_local i32 @main() #0 personality ptr @__gxx_personality_sj0 { ; SJLJ-NEXT: popq %r15 ; SJLJ-NEXT: popq %rbp ; SJLJ-NEXT: retq -; SJLJ-NEXT: .LBB0_9: +; SJLJ-NEXT: .LBB0_3: ; SJLJ-NEXT: endbr64 ; SJLJ-NEXT: movl -144(%rbp), %eax ; SJLJ-NEXT: cmpl $1, %eax -; SJLJ-NEXT: jb .LBB0_10 -; SJLJ-NEXT: # %bb.11: +; SJLJ-NEXT: jb .LBB0_5 +; SJLJ-NEXT: # %bb.4: ; SJLJ-NEXT: ud2 -; SJLJ-NEXT: .LBB0_10: +; SJLJ-NEXT: .LBB0_5: ; SJLJ-NEXT: leaq .LJTI0_0(%rip), %rcx ; SJLJ-NEXT: jmpq *(%rcx,%rax,8) -; SJLJ-NEXT: .LBB0_2: # %lpad -; SJLJ-NEXT: .Ltmp2: +; SJLJ-NEXT: .LBB0_6: # %lpad +; SJLJ-NEXT: .Ltmp2: # EH_LABEL ; SJLJ-NEXT: endbr64 ; SJLJ-NEXT: movl -140(%rbp), %ecx ; SJLJ-NEXT: movl -136(%rbp), %eax ; SJLJ-NEXT: movq %rcx, -56(%rbp) ; SJLJ-NEXT: movl %eax, -64(%rbp) ; SJLJ-NEXT: cmpl $2, %eax -; SJLJ-NEXT: jne .LBB0_4 -; SJLJ-NEXT: # %bb.3: # %catch3 +; SJLJ-NEXT: jne .LBB0_8 +; SJLJ-NEXT: # %bb.7: # %catch3 ; SJLJ-NEXT: movq -56(%rbp), %rdi ; SJLJ-NEXT: movl $-1, -144(%rbp) ; SJLJ-NEXT: callq __cxa_begin_catch @@ -158,11 +158,11 @@ define dso_local i32 @main() #0 personality ptr @__gxx_personality_sj0 { ; SJLJ-NEXT: movl %eax, -60(%rbp) ; SJLJ-NEXT: xorl %ecx, %ecx ; SJLJ-NEXT: cmpl $5, %eax -; SJLJ-NEXT: jmp .LBB0_6 -; SJLJ-NEXT: .LBB0_4: # %catch.fallthrough +; SJLJ-NEXT: jmp .LBB0_10 +; SJLJ-NEXT: .LBB0_8: # %catch.fallthrough ; SJLJ-NEXT: cmpl $1, %eax -; SJLJ-NEXT: jne .LBB0_8 -; SJLJ-NEXT: # %bb.5: # %catch +; SJLJ-NEXT: jne .LBB0_11 +; SJLJ-NEXT: # %bb.9: # %catch ; SJLJ-NEXT: movq -56(%rbp), %rdi ; SJLJ-NEXT: movl $-1, -144(%rbp) ; SJLJ-NEXT: callq __cxa_begin_catch @@ -170,13 +170,13 @@ define dso_local i32 @main() #0 personality ptr @__gxx_personality_sj0 { ; SJLJ-NEXT: movb %al, -45(%rbp) ; SJLJ-NEXT: xorl %ecx, %ecx ; SJLJ-NEXT: cmpb $3, %al -; SJLJ-NEXT: .LBB0_6: # %return +; SJLJ-NEXT: .LBB0_10: # %return ; SJLJ-NEXT: setne %cl ; SJLJ-NEXT: movl %ecx, -44(%rbp) ; SJLJ-NEXT: movl $-1, -144(%rbp) ; SJLJ-NEXT: callq __cxa_end_catch -; SJLJ-NEXT: jmp .LBB0_7 -; SJLJ-NEXT: .LBB0_8: # %eh.resume +; SJLJ-NEXT: jmp .LBB0_2 +; SJLJ-NEXT: .LBB0_11: # %eh.resume ; SJLJ-NEXT: movl $-1, -144(%rbp) entry: %retval = alloca i32, align 4 diff --git a/llvm/test/CodeGen/X86/indirect-branch-tracking.ll b/llvm/test/CodeGen/X86/indirect-branch-tracking.ll index d4b0ed3aae69b..a08ca2cfa1f37 100644 --- a/llvm/test/CodeGen/X86/indirect-branch-tracking.ll +++ b/llvm/test/CodeGen/X86/indirect-branch-tracking.ll @@ -132,7 +132,7 @@ define i32 @test4() { ; ALL-LABEL: test4 ; X86_64: endbr64 ; X86: endbr32 -; ALL: .LBB3_3: +; ALL: .LBB3_2: ; X86_64-NEXT: endbr64 ; X86-NEXT: endbr32 %fp = tail call ptr @llvm.frameaddress(i32 0) diff --git a/llvm/test/CodeGen/X86/inline-asm-pic.ll b/llvm/test/CodeGen/X86/inline-asm-pic.ll index 54300a946ec3d..a273e822b90f7 100644 --- a/llvm/test/CodeGen/X86/inline-asm-pic.ll +++ b/llvm/test/CodeGen/X86/inline-asm-pic.ll @@ -26,13 +26,13 @@ define void @x() { ; CHECK-LABEL: x: ; CHECK: ## %bb.0: ; CHECK-NEXT: ## InlineAsm Start -; CHECK-NEXT: ## LBB1_1 +; CHECK-NEXT: ## LBB1_2 ; CHECK-EMPTY: ; CHECK-NEXT: ## InlineAsm End -; CHECK-NEXT: ## %bb.2: ## %return +; CHECK-NEXT: ## %bb.1: ## %return ; CHECK-NEXT: retl ; CHECK-NEXT: Ltmp0: ## Block address taken -; CHECK-NEXT: LBB1_1: ## %overflow +; CHECK-NEXT: LBB1_2: ## %overflow ; CHECK-NEXT: ## Label of block must be emitted ; CHECK-NEXT: retl callbr void asm "# ${0:l}\0A", "!i"() diff --git a/llvm/test/CodeGen/X86/inline-spiller-impdef-on-implicit-def-regression.ll b/llvm/test/CodeGen/X86/inline-spiller-impdef-on-implicit-def-regression.ll index f42c2f8f14476..433bd25597781 100644 --- a/llvm/test/CodeGen/X86/inline-spiller-impdef-on-implicit-def-regression.ll +++ b/llvm/test/CodeGen/X86/inline-spiller-impdef-on-implicit-def-regression.ll @@ -33,7 +33,7 @@ define i32 @decode_sb(ptr %t, i32 %bl, i32 %_msprop1966, i32 %sub.i, i64 %idxpro ; CHECK-NEXT: movl %esi, %r15d ; CHECK-NEXT: # implicit-def: $r12d ; CHECK-NEXT: testb $1, %bl -; CHECK-NEXT: jne .LBB0_6 +; CHECK-NEXT: jne .LBB0_5 ; CHECK-NEXT: # %bb.1: # %if.else ; CHECK-NEXT: movl %ecx, %r12d ; CHECK-NEXT: andl $1, %r12d @@ -73,13 +73,13 @@ define i32 @decode_sb(ptr %t, i32 %bl, i32 %_msprop1966, i32 %sub.i, i64 %idxpro ; CHECK-NEXT: callq *%rax ; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: je .LBB0_4 -; CHECK-NEXT: # %bb.5: # %bb19 +; CHECK-NEXT: je .LBB0_7 +; CHECK-NEXT: # %bb.4: # %bb19 ; CHECK-NEXT: testb $1, %bl ; CHECK-NEXT: movq %r14, %rdi ; CHECK-NEXT: movabsq $87960930222080, %r14 # imm = 0x500000000000 -; CHECK-NEXT: jne .LBB0_7 -; CHECK-NEXT: .LBB0_6: # %if.end69 +; CHECK-NEXT: jne .LBB0_6 +; CHECK-NEXT: .LBB0_5: # %if.end69 ; CHECK-NEXT: movl %r13d, 0 ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %esi, %esi @@ -91,7 +91,7 @@ define i32 @decode_sb(ptr %t, i32 %bl, i32 %_msprop1966, i32 %sub.i, i64 %idxpro ; CHECK-NEXT: movslq %r12d, %rax ; CHECK-NEXT: movzbl (%r15), %ecx ; CHECK-NEXT: movb %cl, 544(%rax) -; CHECK-NEXT: .LBB0_7: # %land.lhs.true56 +; CHECK-NEXT: .LBB0_6: # %land.lhs.true56 ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: addq $8, %rsp ; CHECK-NEXT: popq %rbx @@ -102,7 +102,7 @@ define i32 @decode_sb(ptr %t, i32 %bl, i32 %_msprop1966, i32 %sub.i, i64 %idxpro ; CHECK-NEXT: popq %rbp ; CHECK-NEXT: .cfi_def_cfa %rsp, 8 ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB0_4: # %bb +; CHECK-NEXT: .LBB0_7: # %bb entry: %i = load i32, ptr null, align 8 br i1 %cmp54, label %if.end69, label %if.else diff --git a/llvm/test/CodeGen/X86/isel-br.ll b/llvm/test/CodeGen/X86/isel-br.ll index 5388c89e18199..e1c3dc086ec85 100644 --- a/llvm/test/CodeGen/X86/isel-br.ll +++ b/llvm/test/CodeGen/X86/isel-br.ll @@ -16,12 +16,12 @@ define void @uncondbr() { ; DAG-NEXT: jmp .LBB0_1 ; ; GISEL-LABEL: uncondbr: -; GISEL: # %bb.1: # %entry -; GISEL-NEXT: jmp .LBB0_3 -; GISEL-NEXT: .LBB0_2: # %end -; GISEL-NEXT: ret{{[l|q]}} -; GISEL-NEXT: .LBB0_3: # %bb2 +; GISEL: # %bb.0: # %entry ; GISEL-NEXT: jmp .LBB0_2 +; GISEL-NEXT: .LBB0_1: # %end +; GISEL-NEXT: ret{{[l|q]}} +; GISEL-NEXT: .LBB0_2: # %bb2 +; GISEL-NEXT: jmp .LBB0_1 entry: br label %bb2 end: diff --git a/llvm/test/CodeGen/X86/isel-brcond-fcmp.ll b/llvm/test/CodeGen/X86/isel-brcond-fcmp.ll index c08b85488ff49..a90bfa0154c0c 100644 --- a/llvm/test/CodeGen/X86/isel-brcond-fcmp.ll +++ b/llvm/test/CodeGen/X86/isel-brcond-fcmp.ll @@ -7,12 +7,12 @@ define i32 @fcmp_oeq(float %x, float %y) { ; X64-LABEL: fcmp_oeq: ; X64: ## %bb.0: ; X64-NEXT: ucomiss %xmm1, %xmm0 -; X64-NEXT: jne LBB0_1 -; X64-NEXT: jp LBB0_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: jne LBB0_2 +; X64-NEXT: jp LBB0_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB0_1: ## %bb2 +; X64-NEXT: LBB0_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -23,11 +23,11 @@ define i32 @fcmp_oeq(float %x, float %y) { ; GISEL-X64-NEXT: setnp %cl ; GISEL-X64-NEXT: andb %al, %cl ; GISEL-X64-NEXT: testb $1, %cl -; GISEL-X64-NEXT: je LBB0_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB0_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB0_1: ## %bb2 +; GISEL-X64-NEXT: LBB0_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq %1 = fcmp oeq float %x, %y @@ -42,11 +42,11 @@ define i32 @fcmp_ogt(float %x, float %y) { ; X64-LABEL: fcmp_ogt: ; X64: ## %bb.0: ; X64-NEXT: ucomiss %xmm1, %xmm0 -; X64-NEXT: jbe LBB1_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: jbe LBB1_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB1_1: ## %bb2 +; X64-NEXT: LBB1_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -55,11 +55,11 @@ define i32 @fcmp_ogt(float %x, float %y) { ; GISEL-X64-NEXT: ucomiss %xmm1, %xmm0 ; GISEL-X64-NEXT: seta %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB1_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB1_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB1_1: ## %bb2 +; GISEL-X64-NEXT: LBB1_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq %1 = fcmp ogt float %x, %y @@ -74,11 +74,11 @@ define i32 @fcmp_oge(float %x, float %y) { ; X64-LABEL: fcmp_oge: ; X64: ## %bb.0: ; X64-NEXT: ucomiss %xmm1, %xmm0 -; X64-NEXT: jb LBB2_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: jb LBB2_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB2_1: ## %bb2 +; X64-NEXT: LBB2_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -87,11 +87,11 @@ define i32 @fcmp_oge(float %x, float %y) { ; GISEL-X64-NEXT: ucomiss %xmm1, %xmm0 ; GISEL-X64-NEXT: setae %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB2_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB2_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB2_1: ## %bb2 +; GISEL-X64-NEXT: LBB2_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq %1 = fcmp oge float %x, %y @@ -106,11 +106,11 @@ define i32 @fcmp_olt(float %x, float %y) { ; X64-LABEL: fcmp_olt: ; X64: ## %bb.0: ; X64-NEXT: ucomiss %xmm0, %xmm1 -; X64-NEXT: jbe LBB3_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: jbe LBB3_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB3_1: ## %bb2 +; X64-NEXT: LBB3_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -119,11 +119,11 @@ define i32 @fcmp_olt(float %x, float %y) { ; GISEL-X64-NEXT: ucomiss %xmm0, %xmm1 ; GISEL-X64-NEXT: seta %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB3_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB3_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB3_1: ## %bb2 +; GISEL-X64-NEXT: LBB3_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq %1 = fcmp olt float %x, %y @@ -138,11 +138,11 @@ define i32 @fcmp_ole(float %x, float %y) { ; X64-LABEL: fcmp_ole: ; X64: ## %bb.0: ; X64-NEXT: ucomiss %xmm0, %xmm1 -; X64-NEXT: jb LBB4_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: jb LBB4_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB4_1: ## %bb2 +; X64-NEXT: LBB4_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -151,11 +151,11 @@ define i32 @fcmp_ole(float %x, float %y) { ; GISEL-X64-NEXT: ucomiss %xmm0, %xmm1 ; GISEL-X64-NEXT: setae %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB4_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB4_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB4_1: ## %bb2 +; GISEL-X64-NEXT: LBB4_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq %1 = fcmp ole float %x, %y @@ -170,11 +170,11 @@ define i32 @fcmp_one(float %x, float %y) { ; X64-LABEL: fcmp_one: ; X64: ## %bb.0: ; X64-NEXT: ucomiss %xmm1, %xmm0 -; X64-NEXT: je LBB5_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: je LBB5_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB5_1: ## %bb2 +; X64-NEXT: LBB5_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -183,11 +183,11 @@ define i32 @fcmp_one(float %x, float %y) { ; GISEL-X64-NEXT: ucomiss %xmm1, %xmm0 ; GISEL-X64-NEXT: setne %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB5_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB5_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB5_1: ## %bb2 +; GISEL-X64-NEXT: LBB5_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq %1 = fcmp one float %x, %y @@ -202,11 +202,11 @@ define i32 @fcmp_ord(float %x, float %y) { ; X64-LABEL: fcmp_ord: ; X64: ## %bb.0: ; X64-NEXT: ucomiss %xmm1, %xmm0 -; X64-NEXT: jp LBB6_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: jp LBB6_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB6_1: ## %bb2 +; X64-NEXT: LBB6_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -215,11 +215,11 @@ define i32 @fcmp_ord(float %x, float %y) { ; GISEL-X64-NEXT: ucomiss %xmm1, %xmm0 ; GISEL-X64-NEXT: setnp %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB6_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB6_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB6_1: ## %bb2 +; GISEL-X64-NEXT: LBB6_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq %1 = fcmp ord float %x, %y @@ -298,11 +298,11 @@ define i32 @fcmp_ugt(float %x, float %y) { ; X64-LABEL: fcmp_ugt: ; X64: ## %bb.0: ; X64-NEXT: ucomiss %xmm0, %xmm1 -; X64-NEXT: jae LBB9_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: jae LBB9_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB9_1: ## %bb2 +; X64-NEXT: LBB9_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -311,11 +311,11 @@ define i32 @fcmp_ugt(float %x, float %y) { ; GISEL-X64-NEXT: ucomiss %xmm0, %xmm1 ; GISEL-X64-NEXT: setb %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB9_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB9_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB9_1: ## %bb2 +; GISEL-X64-NEXT: LBB9_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq %1 = fcmp ugt float %x, %y @@ -330,11 +330,11 @@ define i32 @fcmp_uge(float %x, float %y) { ; X64-LABEL: fcmp_uge: ; X64: ## %bb.0: ; X64-NEXT: ucomiss %xmm0, %xmm1 -; X64-NEXT: ja LBB10_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: ja LBB10_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB10_1: ## %bb2 +; X64-NEXT: LBB10_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -343,11 +343,11 @@ define i32 @fcmp_uge(float %x, float %y) { ; GISEL-X64-NEXT: ucomiss %xmm0, %xmm1 ; GISEL-X64-NEXT: setbe %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB10_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB10_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB10_1: ## %bb2 +; GISEL-X64-NEXT: LBB10_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq %1 = fcmp uge float %x, %y @@ -362,11 +362,11 @@ define i32 @fcmp_ult(float %x, float %y) { ; X64-LABEL: fcmp_ult: ; X64: ## %bb.0: ; X64-NEXT: ucomiss %xmm1, %xmm0 -; X64-NEXT: jae LBB11_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: jae LBB11_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB11_1: ## %bb2 +; X64-NEXT: LBB11_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -375,11 +375,11 @@ define i32 @fcmp_ult(float %x, float %y) { ; GISEL-X64-NEXT: ucomiss %xmm1, %xmm0 ; GISEL-X64-NEXT: setb %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB11_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB11_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB11_1: ## %bb2 +; GISEL-X64-NEXT: LBB11_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq %1 = fcmp ult float %x, %y @@ -394,11 +394,11 @@ define i32 @fcmp_ule(float %x, float %y) { ; X64-LABEL: fcmp_ule: ; X64: ## %bb.0: ; X64-NEXT: ucomiss %xmm1, %xmm0 -; X64-NEXT: ja LBB12_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: ja LBB12_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB12_1: ## %bb2 +; X64-NEXT: LBB12_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -407,11 +407,11 @@ define i32 @fcmp_ule(float %x, float %y) { ; GISEL-X64-NEXT: ucomiss %xmm1, %xmm0 ; GISEL-X64-NEXT: setbe %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB12_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB12_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB12_1: ## %bb2 +; GISEL-X64-NEXT: LBB12_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq %1 = fcmp ule float %x, %y @@ -426,12 +426,12 @@ define i32 @fcmp_une(float %x, float %y) { ; X64-LABEL: fcmp_une: ; X64: ## %bb.0: ; X64-NEXT: ucomiss %xmm1, %xmm0 -; X64-NEXT: jne LBB13_2 -; X64-NEXT: jnp LBB13_1 -; X64-NEXT: LBB13_2: ## %bb1 +; X64-NEXT: jne LBB13_1 +; X64-NEXT: jnp LBB13_2 +; X64-NEXT: LBB13_1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB13_1: ## %bb2 +; X64-NEXT: LBB13_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -442,11 +442,11 @@ define i32 @fcmp_une(float %x, float %y) { ; GISEL-X64-NEXT: setp %cl ; GISEL-X64-NEXT: orb %al, %cl ; GISEL-X64-NEXT: testb $1, %cl -; GISEL-X64-NEXT: je LBB13_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB13_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB13_1: ## %bb2 +; GISEL-X64-NEXT: LBB13_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq %1 = fcmp une float %x, %y @@ -461,11 +461,11 @@ define i32 @fcmp_oeq1(float %x) { ; X64-LABEL: fcmp_oeq1: ; X64: ## %bb.0: ; X64-NEXT: ucomiss %xmm0, %xmm0 -; X64-NEXT: jp LBB14_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: jp LBB14_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB14_1: ## %bb2 +; X64-NEXT: LBB14_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -476,11 +476,11 @@ define i32 @fcmp_oeq1(float %x) { ; GISEL-X64-NEXT: setnp %cl ; GISEL-X64-NEXT: andb %al, %cl ; GISEL-X64-NEXT: testb $1, %cl -; GISEL-X64-NEXT: je LBB14_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB14_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB14_1: ## %bb2 +; GISEL-X64-NEXT: LBB14_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq %1 = fcmp oeq float %x, %x @@ -496,12 +496,12 @@ define i32 @fcmp_oeq2(float %x) { ; X64: ## %bb.0: ; X64-NEXT: xorps %xmm1, %xmm1 ; X64-NEXT: ucomiss %xmm1, %xmm0 -; X64-NEXT: jne LBB15_1 -; X64-NEXT: jp LBB15_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: jne LBB15_2 +; X64-NEXT: jp LBB15_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB15_1: ## %bb2 +; X64-NEXT: LBB15_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -513,11 +513,11 @@ define i32 @fcmp_oeq2(float %x) { ; GISEL-X64-NEXT: setnp %cl ; GISEL-X64-NEXT: andb %al, %cl ; GISEL-X64-NEXT: testb $1, %cl -; GISEL-X64-NEXT: je LBB15_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB15_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB15_1: ## %bb2 +; GISEL-X64-NEXT: LBB15_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq %1 = fcmp oeq float %x, 0.000000e+00 @@ -533,11 +533,11 @@ define i32 @fcmp_ogt1(float %x) { ; SDAG-X64: ## %bb.0: ; SDAG-X64-NEXT: xorl %eax, %eax ; SDAG-X64-NEXT: testb %al, %al -; SDAG-X64-NEXT: je LBB16_1 -; SDAG-X64-NEXT: ## %bb.2: ## %bb1 +; SDAG-X64-NEXT: je LBB16_2 +; SDAG-X64-NEXT: ## %bb.1: ## %bb1 ; SDAG-X64-NEXT: xorl %eax, %eax ; SDAG-X64-NEXT: retq -; SDAG-X64-NEXT: LBB16_1: ## %bb2 +; SDAG-X64-NEXT: LBB16_2: ## %bb2 ; SDAG-X64-NEXT: movl $1, %eax ; SDAG-X64-NEXT: retq ; @@ -551,11 +551,11 @@ define i32 @fcmp_ogt1(float %x) { ; GISEL-X64-NEXT: ucomiss %xmm0, %xmm0 ; GISEL-X64-NEXT: seta %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB16_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB16_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB16_1: ## %bb2 +; GISEL-X64-NEXT: LBB16_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq %1 = fcmp ogt float %x, %x @@ -571,11 +571,11 @@ define i32 @fcmp_ogt2(float %x) { ; X64: ## %bb.0: ; X64-NEXT: xorps %xmm1, %xmm1 ; X64-NEXT: ucomiss %xmm1, %xmm0 -; X64-NEXT: jbe LBB17_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: jbe LBB17_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB17_1: ## %bb2 +; X64-NEXT: LBB17_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -585,11 +585,11 @@ define i32 @fcmp_ogt2(float %x) { ; GISEL-X64-NEXT: ucomiss %xmm1, %xmm0 ; GISEL-X64-NEXT: seta %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB17_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB17_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB17_1: ## %bb2 +; GISEL-X64-NEXT: LBB17_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq %1 = fcmp ogt float %x, 0.000000e+00 @@ -604,11 +604,11 @@ define i32 @fcmp_oge1(float %x) { ; X64-LABEL: fcmp_oge1: ; X64: ## %bb.0: ; X64-NEXT: ucomiss %xmm0, %xmm0 -; X64-NEXT: jp LBB18_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: jp LBB18_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB18_1: ## %bb2 +; X64-NEXT: LBB18_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -617,11 +617,11 @@ define i32 @fcmp_oge1(float %x) { ; GISEL-X64-NEXT: ucomiss %xmm0, %xmm0 ; GISEL-X64-NEXT: setae %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB18_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB18_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB18_1: ## %bb2 +; GISEL-X64-NEXT: LBB18_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq %1 = fcmp oge float %x, %x @@ -637,11 +637,11 @@ define i32 @fcmp_oge2(float %x) { ; X64: ## %bb.0: ; X64-NEXT: xorps %xmm1, %xmm1 ; X64-NEXT: ucomiss %xmm1, %xmm0 -; X64-NEXT: jb LBB19_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: jb LBB19_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB19_1: ## %bb2 +; X64-NEXT: LBB19_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -651,11 +651,11 @@ define i32 @fcmp_oge2(float %x) { ; GISEL-X64-NEXT: ucomiss %xmm1, %xmm0 ; GISEL-X64-NEXT: setae %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB19_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB19_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB19_1: ## %bb2 +; GISEL-X64-NEXT: LBB19_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq %1 = fcmp oge float %x, 0.000000e+00 @@ -671,11 +671,11 @@ define i32 @fcmp_olt1(float %x) { ; SDAG-X64: ## %bb.0: ; SDAG-X64-NEXT: xorl %eax, %eax ; SDAG-X64-NEXT: testb %al, %al -; SDAG-X64-NEXT: je LBB20_1 -; SDAG-X64-NEXT: ## %bb.2: ## %bb1 +; SDAG-X64-NEXT: je LBB20_2 +; SDAG-X64-NEXT: ## %bb.1: ## %bb1 ; SDAG-X64-NEXT: xorl %eax, %eax ; SDAG-X64-NEXT: retq -; SDAG-X64-NEXT: LBB20_1: ## %bb2 +; SDAG-X64-NEXT: LBB20_2: ## %bb2 ; SDAG-X64-NEXT: movl $1, %eax ; SDAG-X64-NEXT: retq ; @@ -689,11 +689,11 @@ define i32 @fcmp_olt1(float %x) { ; GISEL-X64-NEXT: ucomiss %xmm0, %xmm0 ; GISEL-X64-NEXT: seta %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB20_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB20_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB20_1: ## %bb2 +; GISEL-X64-NEXT: LBB20_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq %1 = fcmp olt float %x, %x @@ -709,11 +709,11 @@ define i32 @fcmp_olt2(float %x) { ; X64: ## %bb.0: ; X64-NEXT: xorps %xmm1, %xmm1 ; X64-NEXT: ucomiss %xmm0, %xmm1 -; X64-NEXT: jbe LBB21_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: jbe LBB21_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB21_1: ## %bb2 +; X64-NEXT: LBB21_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -723,11 +723,11 @@ define i32 @fcmp_olt2(float %x) { ; GISEL-X64-NEXT: ucomiss %xmm0, %xmm1 ; GISEL-X64-NEXT: seta %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB21_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB21_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB21_1: ## %bb2 +; GISEL-X64-NEXT: LBB21_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq %1 = fcmp olt float %x, 0.000000e+00 @@ -742,11 +742,11 @@ define i32 @fcmp_ole1(float %x) { ; X64-LABEL: fcmp_ole1: ; X64: ## %bb.0: ; X64-NEXT: ucomiss %xmm0, %xmm0 -; X64-NEXT: jp LBB22_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: jp LBB22_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB22_1: ## %bb2 +; X64-NEXT: LBB22_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -755,11 +755,11 @@ define i32 @fcmp_ole1(float %x) { ; GISEL-X64-NEXT: ucomiss %xmm0, %xmm0 ; GISEL-X64-NEXT: setae %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB22_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB22_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB22_1: ## %bb2 +; GISEL-X64-NEXT: LBB22_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq %1 = fcmp ole float %x, %x @@ -775,11 +775,11 @@ define i32 @fcmp_ole2(float %x) { ; X64: ## %bb.0: ; X64-NEXT: xorps %xmm1, %xmm1 ; X64-NEXT: ucomiss %xmm0, %xmm1 -; X64-NEXT: jb LBB23_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: jb LBB23_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB23_1: ## %bb2 +; X64-NEXT: LBB23_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -789,11 +789,11 @@ define i32 @fcmp_ole2(float %x) { ; GISEL-X64-NEXT: ucomiss %xmm0, %xmm1 ; GISEL-X64-NEXT: setae %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB23_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB23_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB23_1: ## %bb2 +; GISEL-X64-NEXT: LBB23_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq %1 = fcmp ole float %x, 0.000000e+00 @@ -809,11 +809,11 @@ define i32 @fcmp_one1(float %x) { ; SDAG-X64: ## %bb.0: ; SDAG-X64-NEXT: xorl %eax, %eax ; SDAG-X64-NEXT: testb %al, %al -; SDAG-X64-NEXT: je LBB24_1 -; SDAG-X64-NEXT: ## %bb.2: ## %bb1 +; SDAG-X64-NEXT: je LBB24_2 +; SDAG-X64-NEXT: ## %bb.1: ## %bb1 ; SDAG-X64-NEXT: xorl %eax, %eax ; SDAG-X64-NEXT: retq -; SDAG-X64-NEXT: LBB24_1: ## %bb2 +; SDAG-X64-NEXT: LBB24_2: ## %bb2 ; SDAG-X64-NEXT: movl $1, %eax ; SDAG-X64-NEXT: retq ; @@ -827,11 +827,11 @@ define i32 @fcmp_one1(float %x) { ; GISEL-X64-NEXT: ucomiss %xmm0, %xmm0 ; GISEL-X64-NEXT: setne %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB24_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB24_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB24_1: ## %bb2 +; GISEL-X64-NEXT: LBB24_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq %1 = fcmp one float %x, %x @@ -847,11 +847,11 @@ define i32 @fcmp_one2(float %x) { ; X64: ## %bb.0: ; X64-NEXT: xorps %xmm1, %xmm1 ; X64-NEXT: ucomiss %xmm1, %xmm0 -; X64-NEXT: je LBB25_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: je LBB25_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB25_1: ## %bb2 +; X64-NEXT: LBB25_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -861,11 +861,11 @@ define i32 @fcmp_one2(float %x) { ; GISEL-X64-NEXT: ucomiss %xmm1, %xmm0 ; GISEL-X64-NEXT: setne %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB25_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB25_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB25_1: ## %bb2 +; GISEL-X64-NEXT: LBB25_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq %1 = fcmp one float %x, 0.000000e+00 @@ -880,11 +880,11 @@ define i32 @fcmp_ord1(float %x) { ; X64-LABEL: fcmp_ord1: ; X64: ## %bb.0: ; X64-NEXT: ucomiss %xmm0, %xmm0 -; X64-NEXT: jp LBB26_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: jp LBB26_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB26_1: ## %bb2 +; X64-NEXT: LBB26_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -893,11 +893,11 @@ define i32 @fcmp_ord1(float %x) { ; GISEL-X64-NEXT: ucomiss %xmm0, %xmm0 ; GISEL-X64-NEXT: setnp %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB26_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB26_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB26_1: ## %bb2 +; GISEL-X64-NEXT: LBB26_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq %1 = fcmp ord float %x, %x @@ -912,11 +912,11 @@ define i32 @fcmp_ord2(float %x) { ; X64-LABEL: fcmp_ord2: ; X64: ## %bb.0: ; X64-NEXT: ucomiss %xmm0, %xmm0 -; X64-NEXT: jp LBB27_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: jp LBB27_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB27_1: ## %bb2 +; X64-NEXT: LBB27_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -926,11 +926,11 @@ define i32 @fcmp_ord2(float %x) { ; GISEL-X64-NEXT: ucomiss %xmm1, %xmm0 ; GISEL-X64-NEXT: setnp %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB27_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB27_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB27_1: ## %bb2 +; GISEL-X64-NEXT: LBB27_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq %1 = fcmp ord float %x, 0.000000e+00 @@ -1082,11 +1082,11 @@ define i32 @fcmp_ugt1(float %x) { ; X64-LABEL: fcmp_ugt1: ; X64: ## %bb.0: ; X64-NEXT: ucomiss %xmm0, %xmm0 -; X64-NEXT: jnp LBB32_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: jnp LBB32_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB32_1: ## %bb2 +; X64-NEXT: LBB32_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -1095,11 +1095,11 @@ define i32 @fcmp_ugt1(float %x) { ; GISEL-X64-NEXT: ucomiss %xmm0, %xmm0 ; GISEL-X64-NEXT: setb %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB32_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB32_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB32_1: ## %bb2 +; GISEL-X64-NEXT: LBB32_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq %1 = fcmp ugt float %x, %x @@ -1115,11 +1115,11 @@ define i32 @fcmp_ugt2(float %x) { ; X64: ## %bb.0: ; X64-NEXT: xorps %xmm1, %xmm1 ; X64-NEXT: ucomiss %xmm0, %xmm1 -; X64-NEXT: jae LBB33_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: jae LBB33_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB33_1: ## %bb2 +; X64-NEXT: LBB33_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -1129,11 +1129,11 @@ define i32 @fcmp_ugt2(float %x) { ; GISEL-X64-NEXT: ucomiss %xmm0, %xmm1 ; GISEL-X64-NEXT: setb %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB33_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB33_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB33_1: ## %bb2 +; GISEL-X64-NEXT: LBB33_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq %1 = fcmp ugt float %x, 0.000000e+00 @@ -1149,11 +1149,11 @@ define i32 @fcmp_uge1(float %x) { ; SDAG-X64: ## %bb.0: ; SDAG-X64-NEXT: movb $1, %al ; SDAG-X64-NEXT: testb %al, %al -; SDAG-X64-NEXT: je LBB34_1 -; SDAG-X64-NEXT: ## %bb.2: ## %bb1 +; SDAG-X64-NEXT: je LBB34_2 +; SDAG-X64-NEXT: ## %bb.1: ## %bb1 ; SDAG-X64-NEXT: xorl %eax, %eax ; SDAG-X64-NEXT: retq -; SDAG-X64-NEXT: LBB34_1: ## %bb2 +; SDAG-X64-NEXT: LBB34_2: ## %bb2 ; SDAG-X64-NEXT: movl $1, %eax ; SDAG-X64-NEXT: retq ; @@ -1167,11 +1167,11 @@ define i32 @fcmp_uge1(float %x) { ; GISEL-X64-NEXT: ucomiss %xmm0, %xmm0 ; GISEL-X64-NEXT: setbe %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB34_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB34_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB34_1: ## %bb2 +; GISEL-X64-NEXT: LBB34_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq %1 = fcmp uge float %x, %x @@ -1187,11 +1187,11 @@ define i32 @fcmp_uge2(float %x) { ; X64: ## %bb.0: ; X64-NEXT: xorps %xmm1, %xmm1 ; X64-NEXT: ucomiss %xmm0, %xmm1 -; X64-NEXT: ja LBB35_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: ja LBB35_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB35_1: ## %bb2 +; X64-NEXT: LBB35_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -1201,11 +1201,11 @@ define i32 @fcmp_uge2(float %x) { ; GISEL-X64-NEXT: ucomiss %xmm0, %xmm1 ; GISEL-X64-NEXT: setbe %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB35_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB35_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB35_1: ## %bb2 +; GISEL-X64-NEXT: LBB35_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq %1 = fcmp uge float %x, 0.000000e+00 @@ -1220,11 +1220,11 @@ define i32 @fcmp_ult1(float %x) { ; X64-LABEL: fcmp_ult1: ; X64: ## %bb.0: ; X64-NEXT: ucomiss %xmm0, %xmm0 -; X64-NEXT: jnp LBB36_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: jnp LBB36_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB36_1: ## %bb2 +; X64-NEXT: LBB36_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -1233,11 +1233,11 @@ define i32 @fcmp_ult1(float %x) { ; GISEL-X64-NEXT: ucomiss %xmm0, %xmm0 ; GISEL-X64-NEXT: setb %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB36_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB36_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB36_1: ## %bb2 +; GISEL-X64-NEXT: LBB36_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq %1 = fcmp ult float %x, %x @@ -1253,11 +1253,11 @@ define i32 @fcmp_ult2(float %x) { ; X64: ## %bb.0: ; X64-NEXT: xorps %xmm1, %xmm1 ; X64-NEXT: ucomiss %xmm1, %xmm0 -; X64-NEXT: jae LBB37_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: jae LBB37_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB37_1: ## %bb2 +; X64-NEXT: LBB37_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -1267,11 +1267,11 @@ define i32 @fcmp_ult2(float %x) { ; GISEL-X64-NEXT: ucomiss %xmm1, %xmm0 ; GISEL-X64-NEXT: setb %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB37_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB37_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB37_1: ## %bb2 +; GISEL-X64-NEXT: LBB37_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq %1 = fcmp ult float %x, 0.000000e+00 @@ -1287,11 +1287,11 @@ define i32 @fcmp_ule1(float %x) { ; SDAG-X64: ## %bb.0: ; SDAG-X64-NEXT: movb $1, %al ; SDAG-X64-NEXT: testb %al, %al -; SDAG-X64-NEXT: je LBB38_1 -; SDAG-X64-NEXT: ## %bb.2: ## %bb1 +; SDAG-X64-NEXT: je LBB38_2 +; SDAG-X64-NEXT: ## %bb.1: ## %bb1 ; SDAG-X64-NEXT: xorl %eax, %eax ; SDAG-X64-NEXT: retq -; SDAG-X64-NEXT: LBB38_1: ## %bb2 +; SDAG-X64-NEXT: LBB38_2: ## %bb2 ; SDAG-X64-NEXT: movl $1, %eax ; SDAG-X64-NEXT: retq ; @@ -1305,11 +1305,11 @@ define i32 @fcmp_ule1(float %x) { ; GISEL-X64-NEXT: ucomiss %xmm0, %xmm0 ; GISEL-X64-NEXT: setbe %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB38_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB38_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB38_1: ## %bb2 +; GISEL-X64-NEXT: LBB38_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq %1 = fcmp ule float %x, %x @@ -1325,11 +1325,11 @@ define i32 @fcmp_ule2(float %x) { ; X64: ## %bb.0: ; X64-NEXT: xorps %xmm1, %xmm1 ; X64-NEXT: ucomiss %xmm1, %xmm0 -; X64-NEXT: ja LBB39_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: ja LBB39_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB39_1: ## %bb2 +; X64-NEXT: LBB39_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -1339,11 +1339,11 @@ define i32 @fcmp_ule2(float %x) { ; GISEL-X64-NEXT: ucomiss %xmm1, %xmm0 ; GISEL-X64-NEXT: setbe %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB39_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB39_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB39_1: ## %bb2 +; GISEL-X64-NEXT: LBB39_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq %1 = fcmp ule float %x, 0.000000e+00 @@ -1358,11 +1358,11 @@ define i32 @fcmp_une1(float %x) { ; X64-LABEL: fcmp_une1: ; X64: ## %bb.0: ; X64-NEXT: ucomiss %xmm0, %xmm0 -; X64-NEXT: jnp LBB40_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: jnp LBB40_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB40_1: ## %bb2 +; X64-NEXT: LBB40_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -1373,11 +1373,11 @@ define i32 @fcmp_une1(float %x) { ; GISEL-X64-NEXT: setp %cl ; GISEL-X64-NEXT: orb %al, %cl ; GISEL-X64-NEXT: testb $1, %cl -; GISEL-X64-NEXT: je LBB40_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB40_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB40_1: ## %bb2 +; GISEL-X64-NEXT: LBB40_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq %1 = fcmp une float %x, %x @@ -1393,12 +1393,12 @@ define i32 @fcmp_une2(float %x) { ; X64: ## %bb.0: ; X64-NEXT: xorps %xmm1, %xmm1 ; X64-NEXT: ucomiss %xmm1, %xmm0 -; X64-NEXT: jne LBB41_2 -; X64-NEXT: jnp LBB41_1 -; X64-NEXT: LBB41_2: ## %bb1 +; X64-NEXT: jne LBB41_1 +; X64-NEXT: jnp LBB41_2 +; X64-NEXT: LBB41_1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB41_1: ## %bb2 +; X64-NEXT: LBB41_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -1410,11 +1410,11 @@ define i32 @fcmp_une2(float %x) { ; GISEL-X64-NEXT: setp %cl ; GISEL-X64-NEXT: orb %al, %cl ; GISEL-X64-NEXT: testb $1, %cl -; GISEL-X64-NEXT: je LBB41_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB41_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB41_1: ## %bb2 +; GISEL-X64-NEXT: LBB41_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq %1 = fcmp une float %x, 0.000000e+00 diff --git a/llvm/test/CodeGen/X86/isel-brcond-icmp.ll b/llvm/test/CodeGen/X86/isel-brcond-icmp.ll index 675ae02d79ba2..ecd1af52165c2 100644 --- a/llvm/test/CodeGen/X86/isel-brcond-icmp.ll +++ b/llvm/test/CodeGen/X86/isel-brcond-icmp.ll @@ -10,11 +10,11 @@ define i32 @icmp_eq_2(i32 %x, i32 %y) { ; X64-LABEL: icmp_eq_2: ; X64: ## %bb.0: ; X64-NEXT: cmpl %esi, %edi -; X64-NEXT: jne LBB0_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: jne LBB0_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB0_1: ## %bb2 +; X64-NEXT: LBB0_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -23,11 +23,11 @@ define i32 @icmp_eq_2(i32 %x, i32 %y) { ; GISEL-X64-NEXT: cmpl %esi, %edi ; GISEL-X64-NEXT: sete %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB0_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB0_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB0_1: ## %bb2 +; GISEL-X64-NEXT: LBB0_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq ; @@ -35,11 +35,11 @@ define i32 @icmp_eq_2(i32 %x, i32 %y) { ; SDAG-X86: ## %bb.0: ; SDAG-X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; SDAG-X86-NEXT: cmpl {{[0-9]+}}(%esp), %eax -; SDAG-X86-NEXT: jne LBB0_1 -; SDAG-X86-NEXT: ## %bb.2: ## %bb1 +; SDAG-X86-NEXT: jne LBB0_2 +; SDAG-X86-NEXT: ## %bb.1: ## %bb1 ; SDAG-X86-NEXT: xorl %eax, %eax ; SDAG-X86-NEXT: retl -; SDAG-X86-NEXT: LBB0_1: ## %bb2 +; SDAG-X86-NEXT: LBB0_2: ## %bb2 ; SDAG-X86-NEXT: movl $1, %eax ; SDAG-X86-NEXT: retl ; @@ -47,11 +47,11 @@ define i32 @icmp_eq_2(i32 %x, i32 %y) { ; FASTISEL-X86: ## %bb.0: ; FASTISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; FASTISEL-X86-NEXT: cmpl %eax, {{[0-9]+}}(%esp) -; FASTISEL-X86-NEXT: jne LBB0_1 -; FASTISEL-X86-NEXT: ## %bb.2: ## %bb1 +; FASTISEL-X86-NEXT: jne LBB0_2 +; FASTISEL-X86-NEXT: ## %bb.1: ## %bb1 ; FASTISEL-X86-NEXT: xorl %eax, %eax ; FASTISEL-X86-NEXT: retl -; FASTISEL-X86-NEXT: LBB0_1: ## %bb2 +; FASTISEL-X86-NEXT: LBB0_2: ## %bb2 ; FASTISEL-X86-NEXT: movl $1, %eax ; FASTISEL-X86-NEXT: retl ; @@ -61,11 +61,11 @@ define i32 @icmp_eq_2(i32 %x, i32 %y) { ; GISEL-X86-NEXT: cmpl %eax, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: sete %al ; GISEL-X86-NEXT: testb $1, %al -; GISEL-X86-NEXT: je LBB0_1 -; GISEL-X86-NEXT: ## %bb.2: ## %bb1 +; GISEL-X86-NEXT: je LBB0_2 +; GISEL-X86-NEXT: ## %bb.1: ## %bb1 ; GISEL-X86-NEXT: xorl %eax, %eax ; GISEL-X86-NEXT: retl -; GISEL-X86-NEXT: LBB0_1: ## %bb2 +; GISEL-X86-NEXT: LBB0_2: ## %bb2 ; GISEL-X86-NEXT: movl $1, %eax ; GISEL-X86-NEXT: retl %1 = icmp eq i32 %x, %y @@ -80,11 +80,11 @@ define i32 @icmp_ne_2(i32 %x, i32 %y) { ; X64-LABEL: icmp_ne_2: ; X64: ## %bb.0: ; X64-NEXT: cmpl %esi, %edi -; X64-NEXT: je LBB1_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: je LBB1_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB1_1: ## %bb2 +; X64-NEXT: LBB1_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -93,11 +93,11 @@ define i32 @icmp_ne_2(i32 %x, i32 %y) { ; GISEL-X64-NEXT: cmpl %esi, %edi ; GISEL-X64-NEXT: setne %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB1_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB1_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB1_1: ## %bb2 +; GISEL-X64-NEXT: LBB1_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq ; @@ -105,11 +105,11 @@ define i32 @icmp_ne_2(i32 %x, i32 %y) { ; SDAG-X86: ## %bb.0: ; SDAG-X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; SDAG-X86-NEXT: cmpl {{[0-9]+}}(%esp), %eax -; SDAG-X86-NEXT: je LBB1_1 -; SDAG-X86-NEXT: ## %bb.2: ## %bb1 +; SDAG-X86-NEXT: je LBB1_2 +; SDAG-X86-NEXT: ## %bb.1: ## %bb1 ; SDAG-X86-NEXT: xorl %eax, %eax ; SDAG-X86-NEXT: retl -; SDAG-X86-NEXT: LBB1_1: ## %bb2 +; SDAG-X86-NEXT: LBB1_2: ## %bb2 ; SDAG-X86-NEXT: movl $1, %eax ; SDAG-X86-NEXT: retl ; @@ -117,11 +117,11 @@ define i32 @icmp_ne_2(i32 %x, i32 %y) { ; FASTISEL-X86: ## %bb.0: ; FASTISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; FASTISEL-X86-NEXT: cmpl %eax, {{[0-9]+}}(%esp) -; FASTISEL-X86-NEXT: je LBB1_1 -; FASTISEL-X86-NEXT: ## %bb.2: ## %bb1 +; FASTISEL-X86-NEXT: je LBB1_2 +; FASTISEL-X86-NEXT: ## %bb.1: ## %bb1 ; FASTISEL-X86-NEXT: xorl %eax, %eax ; FASTISEL-X86-NEXT: retl -; FASTISEL-X86-NEXT: LBB1_1: ## %bb2 +; FASTISEL-X86-NEXT: LBB1_2: ## %bb2 ; FASTISEL-X86-NEXT: movl $1, %eax ; FASTISEL-X86-NEXT: retl ; @@ -131,11 +131,11 @@ define i32 @icmp_ne_2(i32 %x, i32 %y) { ; GISEL-X86-NEXT: cmpl %eax, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: setne %al ; GISEL-X86-NEXT: testb $1, %al -; GISEL-X86-NEXT: je LBB1_1 -; GISEL-X86-NEXT: ## %bb.2: ## %bb1 +; GISEL-X86-NEXT: je LBB1_2 +; GISEL-X86-NEXT: ## %bb.1: ## %bb1 ; GISEL-X86-NEXT: xorl %eax, %eax ; GISEL-X86-NEXT: retl -; GISEL-X86-NEXT: LBB1_1: ## %bb2 +; GISEL-X86-NEXT: LBB1_2: ## %bb2 ; GISEL-X86-NEXT: movl $1, %eax ; GISEL-X86-NEXT: retl %1 = icmp ne i32 %x, %y @@ -150,11 +150,11 @@ define i32 @icmp_ugt_2(i32 %x, i32 %y) { ; X64-LABEL: icmp_ugt_2: ; X64: ## %bb.0: ; X64-NEXT: cmpl %esi, %edi -; X64-NEXT: jbe LBB2_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: jbe LBB2_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB2_1: ## %bb2 +; X64-NEXT: LBB2_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -163,11 +163,11 @@ define i32 @icmp_ugt_2(i32 %x, i32 %y) { ; GISEL-X64-NEXT: cmpl %esi, %edi ; GISEL-X64-NEXT: seta %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB2_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB2_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB2_1: ## %bb2 +; GISEL-X64-NEXT: LBB2_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq ; @@ -175,11 +175,11 @@ define i32 @icmp_ugt_2(i32 %x, i32 %y) { ; SDAG-X86: ## %bb.0: ; SDAG-X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; SDAG-X86-NEXT: cmpl {{[0-9]+}}(%esp), %eax -; SDAG-X86-NEXT: jbe LBB2_1 -; SDAG-X86-NEXT: ## %bb.2: ## %bb1 +; SDAG-X86-NEXT: jbe LBB2_2 +; SDAG-X86-NEXT: ## %bb.1: ## %bb1 ; SDAG-X86-NEXT: xorl %eax, %eax ; SDAG-X86-NEXT: retl -; SDAG-X86-NEXT: LBB2_1: ## %bb2 +; SDAG-X86-NEXT: LBB2_2: ## %bb2 ; SDAG-X86-NEXT: movl $1, %eax ; SDAG-X86-NEXT: retl ; @@ -187,11 +187,11 @@ define i32 @icmp_ugt_2(i32 %x, i32 %y) { ; FASTISEL-X86: ## %bb.0: ; FASTISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; FASTISEL-X86-NEXT: cmpl %eax, {{[0-9]+}}(%esp) -; FASTISEL-X86-NEXT: jbe LBB2_1 -; FASTISEL-X86-NEXT: ## %bb.2: ## %bb1 +; FASTISEL-X86-NEXT: jbe LBB2_2 +; FASTISEL-X86-NEXT: ## %bb.1: ## %bb1 ; FASTISEL-X86-NEXT: xorl %eax, %eax ; FASTISEL-X86-NEXT: retl -; FASTISEL-X86-NEXT: LBB2_1: ## %bb2 +; FASTISEL-X86-NEXT: LBB2_2: ## %bb2 ; FASTISEL-X86-NEXT: movl $1, %eax ; FASTISEL-X86-NEXT: retl ; @@ -201,11 +201,11 @@ define i32 @icmp_ugt_2(i32 %x, i32 %y) { ; GISEL-X86-NEXT: cmpl %eax, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: seta %al ; GISEL-X86-NEXT: testb $1, %al -; GISEL-X86-NEXT: je LBB2_1 -; GISEL-X86-NEXT: ## %bb.2: ## %bb1 +; GISEL-X86-NEXT: je LBB2_2 +; GISEL-X86-NEXT: ## %bb.1: ## %bb1 ; GISEL-X86-NEXT: xorl %eax, %eax ; GISEL-X86-NEXT: retl -; GISEL-X86-NEXT: LBB2_1: ## %bb2 +; GISEL-X86-NEXT: LBB2_2: ## %bb2 ; GISEL-X86-NEXT: movl $1, %eax ; GISEL-X86-NEXT: retl %1 = icmp ugt i32 %x, %y @@ -220,11 +220,11 @@ define i32 @icmp_uge_2(i32 %x, i32 %y) { ; X64-LABEL: icmp_uge_2: ; X64: ## %bb.0: ; X64-NEXT: cmpl %esi, %edi -; X64-NEXT: jb LBB3_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: jb LBB3_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB3_1: ## %bb2 +; X64-NEXT: LBB3_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -233,11 +233,11 @@ define i32 @icmp_uge_2(i32 %x, i32 %y) { ; GISEL-X64-NEXT: cmpl %esi, %edi ; GISEL-X64-NEXT: setae %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB3_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB3_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB3_1: ## %bb2 +; GISEL-X64-NEXT: LBB3_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq ; @@ -245,11 +245,11 @@ define i32 @icmp_uge_2(i32 %x, i32 %y) { ; SDAG-X86: ## %bb.0: ; SDAG-X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; SDAG-X86-NEXT: cmpl {{[0-9]+}}(%esp), %eax -; SDAG-X86-NEXT: jb LBB3_1 -; SDAG-X86-NEXT: ## %bb.2: ## %bb1 +; SDAG-X86-NEXT: jb LBB3_2 +; SDAG-X86-NEXT: ## %bb.1: ## %bb1 ; SDAG-X86-NEXT: xorl %eax, %eax ; SDAG-X86-NEXT: retl -; SDAG-X86-NEXT: LBB3_1: ## %bb2 +; SDAG-X86-NEXT: LBB3_2: ## %bb2 ; SDAG-X86-NEXT: movl $1, %eax ; SDAG-X86-NEXT: retl ; @@ -257,11 +257,11 @@ define i32 @icmp_uge_2(i32 %x, i32 %y) { ; FASTISEL-X86: ## %bb.0: ; FASTISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; FASTISEL-X86-NEXT: cmpl %eax, {{[0-9]+}}(%esp) -; FASTISEL-X86-NEXT: jb LBB3_1 -; FASTISEL-X86-NEXT: ## %bb.2: ## %bb1 +; FASTISEL-X86-NEXT: jb LBB3_2 +; FASTISEL-X86-NEXT: ## %bb.1: ## %bb1 ; FASTISEL-X86-NEXT: xorl %eax, %eax ; FASTISEL-X86-NEXT: retl -; FASTISEL-X86-NEXT: LBB3_1: ## %bb2 +; FASTISEL-X86-NEXT: LBB3_2: ## %bb2 ; FASTISEL-X86-NEXT: movl $1, %eax ; FASTISEL-X86-NEXT: retl ; @@ -271,11 +271,11 @@ define i32 @icmp_uge_2(i32 %x, i32 %y) { ; GISEL-X86-NEXT: cmpl %eax, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: setae %al ; GISEL-X86-NEXT: testb $1, %al -; GISEL-X86-NEXT: je LBB3_1 -; GISEL-X86-NEXT: ## %bb.2: ## %bb1 +; GISEL-X86-NEXT: je LBB3_2 +; GISEL-X86-NEXT: ## %bb.1: ## %bb1 ; GISEL-X86-NEXT: xorl %eax, %eax ; GISEL-X86-NEXT: retl -; GISEL-X86-NEXT: LBB3_1: ## %bb2 +; GISEL-X86-NEXT: LBB3_2: ## %bb2 ; GISEL-X86-NEXT: movl $1, %eax ; GISEL-X86-NEXT: retl %1 = icmp uge i32 %x, %y @@ -290,11 +290,11 @@ define i32 @icmp_ult_2(i32 %x, i32 %y) { ; X64-LABEL: icmp_ult_2: ; X64: ## %bb.0: ; X64-NEXT: cmpl %esi, %edi -; X64-NEXT: jae LBB4_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: jae LBB4_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB4_1: ## %bb2 +; X64-NEXT: LBB4_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -303,11 +303,11 @@ define i32 @icmp_ult_2(i32 %x, i32 %y) { ; GISEL-X64-NEXT: cmpl %esi, %edi ; GISEL-X64-NEXT: setb %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB4_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB4_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB4_1: ## %bb2 +; GISEL-X64-NEXT: LBB4_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq ; @@ -315,11 +315,11 @@ define i32 @icmp_ult_2(i32 %x, i32 %y) { ; SDAG-X86: ## %bb.0: ; SDAG-X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; SDAG-X86-NEXT: cmpl {{[0-9]+}}(%esp), %eax -; SDAG-X86-NEXT: jae LBB4_1 -; SDAG-X86-NEXT: ## %bb.2: ## %bb1 +; SDAG-X86-NEXT: jae LBB4_2 +; SDAG-X86-NEXT: ## %bb.1: ## %bb1 ; SDAG-X86-NEXT: xorl %eax, %eax ; SDAG-X86-NEXT: retl -; SDAG-X86-NEXT: LBB4_1: ## %bb2 +; SDAG-X86-NEXT: LBB4_2: ## %bb2 ; SDAG-X86-NEXT: movl $1, %eax ; SDAG-X86-NEXT: retl ; @@ -327,11 +327,11 @@ define i32 @icmp_ult_2(i32 %x, i32 %y) { ; FASTISEL-X86: ## %bb.0: ; FASTISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; FASTISEL-X86-NEXT: cmpl %eax, {{[0-9]+}}(%esp) -; FASTISEL-X86-NEXT: jae LBB4_1 -; FASTISEL-X86-NEXT: ## %bb.2: ## %bb1 +; FASTISEL-X86-NEXT: jae LBB4_2 +; FASTISEL-X86-NEXT: ## %bb.1: ## %bb1 ; FASTISEL-X86-NEXT: xorl %eax, %eax ; FASTISEL-X86-NEXT: retl -; FASTISEL-X86-NEXT: LBB4_1: ## %bb2 +; FASTISEL-X86-NEXT: LBB4_2: ## %bb2 ; FASTISEL-X86-NEXT: movl $1, %eax ; FASTISEL-X86-NEXT: retl ; @@ -341,11 +341,11 @@ define i32 @icmp_ult_2(i32 %x, i32 %y) { ; GISEL-X86-NEXT: cmpl %eax, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: setb %al ; GISEL-X86-NEXT: testb $1, %al -; GISEL-X86-NEXT: je LBB4_1 -; GISEL-X86-NEXT: ## %bb.2: ## %bb1 +; GISEL-X86-NEXT: je LBB4_2 +; GISEL-X86-NEXT: ## %bb.1: ## %bb1 ; GISEL-X86-NEXT: xorl %eax, %eax ; GISEL-X86-NEXT: retl -; GISEL-X86-NEXT: LBB4_1: ## %bb2 +; GISEL-X86-NEXT: LBB4_2: ## %bb2 ; GISEL-X86-NEXT: movl $1, %eax ; GISEL-X86-NEXT: retl %1 = icmp ult i32 %x, %y @@ -360,11 +360,11 @@ define i32 @icmp_ule_2(i32 %x, i32 %y) { ; X64-LABEL: icmp_ule_2: ; X64: ## %bb.0: ; X64-NEXT: cmpl %esi, %edi -; X64-NEXT: ja LBB5_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: ja LBB5_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB5_1: ## %bb2 +; X64-NEXT: LBB5_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -373,11 +373,11 @@ define i32 @icmp_ule_2(i32 %x, i32 %y) { ; GISEL-X64-NEXT: cmpl %esi, %edi ; GISEL-X64-NEXT: setbe %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB5_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB5_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB5_1: ## %bb2 +; GISEL-X64-NEXT: LBB5_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq ; @@ -385,11 +385,11 @@ define i32 @icmp_ule_2(i32 %x, i32 %y) { ; SDAG-X86: ## %bb.0: ; SDAG-X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; SDAG-X86-NEXT: cmpl {{[0-9]+}}(%esp), %eax -; SDAG-X86-NEXT: ja LBB5_1 -; SDAG-X86-NEXT: ## %bb.2: ## %bb1 +; SDAG-X86-NEXT: ja LBB5_2 +; SDAG-X86-NEXT: ## %bb.1: ## %bb1 ; SDAG-X86-NEXT: xorl %eax, %eax ; SDAG-X86-NEXT: retl -; SDAG-X86-NEXT: LBB5_1: ## %bb2 +; SDAG-X86-NEXT: LBB5_2: ## %bb2 ; SDAG-X86-NEXT: movl $1, %eax ; SDAG-X86-NEXT: retl ; @@ -397,11 +397,11 @@ define i32 @icmp_ule_2(i32 %x, i32 %y) { ; FASTISEL-X86: ## %bb.0: ; FASTISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; FASTISEL-X86-NEXT: cmpl %eax, {{[0-9]+}}(%esp) -; FASTISEL-X86-NEXT: ja LBB5_1 -; FASTISEL-X86-NEXT: ## %bb.2: ## %bb1 +; FASTISEL-X86-NEXT: ja LBB5_2 +; FASTISEL-X86-NEXT: ## %bb.1: ## %bb1 ; FASTISEL-X86-NEXT: xorl %eax, %eax ; FASTISEL-X86-NEXT: retl -; FASTISEL-X86-NEXT: LBB5_1: ## %bb2 +; FASTISEL-X86-NEXT: LBB5_2: ## %bb2 ; FASTISEL-X86-NEXT: movl $1, %eax ; FASTISEL-X86-NEXT: retl ; @@ -411,11 +411,11 @@ define i32 @icmp_ule_2(i32 %x, i32 %y) { ; GISEL-X86-NEXT: cmpl %eax, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: setbe %al ; GISEL-X86-NEXT: testb $1, %al -; GISEL-X86-NEXT: je LBB5_1 -; GISEL-X86-NEXT: ## %bb.2: ## %bb1 +; GISEL-X86-NEXT: je LBB5_2 +; GISEL-X86-NEXT: ## %bb.1: ## %bb1 ; GISEL-X86-NEXT: xorl %eax, %eax ; GISEL-X86-NEXT: retl -; GISEL-X86-NEXT: LBB5_1: ## %bb2 +; GISEL-X86-NEXT: LBB5_2: ## %bb2 ; GISEL-X86-NEXT: movl $1, %eax ; GISEL-X86-NEXT: retl %1 = icmp ule i32 %x, %y @@ -430,11 +430,11 @@ define i32 @icmp_sgt_2(i32 %x, i32 %y) { ; X64-LABEL: icmp_sgt_2: ; X64: ## %bb.0: ; X64-NEXT: cmpl %esi, %edi -; X64-NEXT: jle LBB6_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: jle LBB6_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB6_1: ## %bb2 +; X64-NEXT: LBB6_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -443,11 +443,11 @@ define i32 @icmp_sgt_2(i32 %x, i32 %y) { ; GISEL-X64-NEXT: cmpl %esi, %edi ; GISEL-X64-NEXT: setg %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB6_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB6_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB6_1: ## %bb2 +; GISEL-X64-NEXT: LBB6_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq ; @@ -455,11 +455,11 @@ define i32 @icmp_sgt_2(i32 %x, i32 %y) { ; SDAG-X86: ## %bb.0: ; SDAG-X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; SDAG-X86-NEXT: cmpl {{[0-9]+}}(%esp), %eax -; SDAG-X86-NEXT: jle LBB6_1 -; SDAG-X86-NEXT: ## %bb.2: ## %bb1 +; SDAG-X86-NEXT: jle LBB6_2 +; SDAG-X86-NEXT: ## %bb.1: ## %bb1 ; SDAG-X86-NEXT: xorl %eax, %eax ; SDAG-X86-NEXT: retl -; SDAG-X86-NEXT: LBB6_1: ## %bb2 +; SDAG-X86-NEXT: LBB6_2: ## %bb2 ; SDAG-X86-NEXT: movl $1, %eax ; SDAG-X86-NEXT: retl ; @@ -467,11 +467,11 @@ define i32 @icmp_sgt_2(i32 %x, i32 %y) { ; FASTISEL-X86: ## %bb.0: ; FASTISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; FASTISEL-X86-NEXT: cmpl %eax, {{[0-9]+}}(%esp) -; FASTISEL-X86-NEXT: jle LBB6_1 -; FASTISEL-X86-NEXT: ## %bb.2: ## %bb1 +; FASTISEL-X86-NEXT: jle LBB6_2 +; FASTISEL-X86-NEXT: ## %bb.1: ## %bb1 ; FASTISEL-X86-NEXT: xorl %eax, %eax ; FASTISEL-X86-NEXT: retl -; FASTISEL-X86-NEXT: LBB6_1: ## %bb2 +; FASTISEL-X86-NEXT: LBB6_2: ## %bb2 ; FASTISEL-X86-NEXT: movl $1, %eax ; FASTISEL-X86-NEXT: retl ; @@ -481,11 +481,11 @@ define i32 @icmp_sgt_2(i32 %x, i32 %y) { ; GISEL-X86-NEXT: cmpl %eax, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: setg %al ; GISEL-X86-NEXT: testb $1, %al -; GISEL-X86-NEXT: je LBB6_1 -; GISEL-X86-NEXT: ## %bb.2: ## %bb1 +; GISEL-X86-NEXT: je LBB6_2 +; GISEL-X86-NEXT: ## %bb.1: ## %bb1 ; GISEL-X86-NEXT: xorl %eax, %eax ; GISEL-X86-NEXT: retl -; GISEL-X86-NEXT: LBB6_1: ## %bb2 +; GISEL-X86-NEXT: LBB6_2: ## %bb2 ; GISEL-X86-NEXT: movl $1, %eax ; GISEL-X86-NEXT: retl %1 = icmp sgt i32 %x, %y @@ -500,11 +500,11 @@ define i32 @icmp_sge_2(i32 %x, i32 %y) { ; X64-LABEL: icmp_sge_2: ; X64: ## %bb.0: ; X64-NEXT: cmpl %esi, %edi -; X64-NEXT: jl LBB7_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: jl LBB7_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB7_1: ## %bb2 +; X64-NEXT: LBB7_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -513,11 +513,11 @@ define i32 @icmp_sge_2(i32 %x, i32 %y) { ; GISEL-X64-NEXT: cmpl %esi, %edi ; GISEL-X64-NEXT: setge %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB7_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB7_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB7_1: ## %bb2 +; GISEL-X64-NEXT: LBB7_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq ; @@ -525,11 +525,11 @@ define i32 @icmp_sge_2(i32 %x, i32 %y) { ; SDAG-X86: ## %bb.0: ; SDAG-X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; SDAG-X86-NEXT: cmpl {{[0-9]+}}(%esp), %eax -; SDAG-X86-NEXT: jl LBB7_1 -; SDAG-X86-NEXT: ## %bb.2: ## %bb1 +; SDAG-X86-NEXT: jl LBB7_2 +; SDAG-X86-NEXT: ## %bb.1: ## %bb1 ; SDAG-X86-NEXT: xorl %eax, %eax ; SDAG-X86-NEXT: retl -; SDAG-X86-NEXT: LBB7_1: ## %bb2 +; SDAG-X86-NEXT: LBB7_2: ## %bb2 ; SDAG-X86-NEXT: movl $1, %eax ; SDAG-X86-NEXT: retl ; @@ -537,11 +537,11 @@ define i32 @icmp_sge_2(i32 %x, i32 %y) { ; FASTISEL-X86: ## %bb.0: ; FASTISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; FASTISEL-X86-NEXT: cmpl %eax, {{[0-9]+}}(%esp) -; FASTISEL-X86-NEXT: jl LBB7_1 -; FASTISEL-X86-NEXT: ## %bb.2: ## %bb1 +; FASTISEL-X86-NEXT: jl LBB7_2 +; FASTISEL-X86-NEXT: ## %bb.1: ## %bb1 ; FASTISEL-X86-NEXT: xorl %eax, %eax ; FASTISEL-X86-NEXT: retl -; FASTISEL-X86-NEXT: LBB7_1: ## %bb2 +; FASTISEL-X86-NEXT: LBB7_2: ## %bb2 ; FASTISEL-X86-NEXT: movl $1, %eax ; FASTISEL-X86-NEXT: retl ; @@ -551,11 +551,11 @@ define i32 @icmp_sge_2(i32 %x, i32 %y) { ; GISEL-X86-NEXT: cmpl %eax, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: setge %al ; GISEL-X86-NEXT: testb $1, %al -; GISEL-X86-NEXT: je LBB7_1 -; GISEL-X86-NEXT: ## %bb.2: ## %bb1 +; GISEL-X86-NEXT: je LBB7_2 +; GISEL-X86-NEXT: ## %bb.1: ## %bb1 ; GISEL-X86-NEXT: xorl %eax, %eax ; GISEL-X86-NEXT: retl -; GISEL-X86-NEXT: LBB7_1: ## %bb2 +; GISEL-X86-NEXT: LBB7_2: ## %bb2 ; GISEL-X86-NEXT: movl $1, %eax ; GISEL-X86-NEXT: retl %1 = icmp sge i32 %x, %y @@ -570,11 +570,11 @@ define i32 @icmp_slt_2(i32 %x, i32 %y) { ; X64-LABEL: icmp_slt_2: ; X64: ## %bb.0: ; X64-NEXT: cmpl %esi, %edi -; X64-NEXT: jge LBB8_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: jge LBB8_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB8_1: ## %bb2 +; X64-NEXT: LBB8_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -583,11 +583,11 @@ define i32 @icmp_slt_2(i32 %x, i32 %y) { ; GISEL-X64-NEXT: cmpl %esi, %edi ; GISEL-X64-NEXT: setl %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB8_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB8_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB8_1: ## %bb2 +; GISEL-X64-NEXT: LBB8_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq ; @@ -595,11 +595,11 @@ define i32 @icmp_slt_2(i32 %x, i32 %y) { ; SDAG-X86: ## %bb.0: ; SDAG-X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; SDAG-X86-NEXT: cmpl {{[0-9]+}}(%esp), %eax -; SDAG-X86-NEXT: jge LBB8_1 -; SDAG-X86-NEXT: ## %bb.2: ## %bb1 +; SDAG-X86-NEXT: jge LBB8_2 +; SDAG-X86-NEXT: ## %bb.1: ## %bb1 ; SDAG-X86-NEXT: xorl %eax, %eax ; SDAG-X86-NEXT: retl -; SDAG-X86-NEXT: LBB8_1: ## %bb2 +; SDAG-X86-NEXT: LBB8_2: ## %bb2 ; SDAG-X86-NEXT: movl $1, %eax ; SDAG-X86-NEXT: retl ; @@ -607,11 +607,11 @@ define i32 @icmp_slt_2(i32 %x, i32 %y) { ; FASTISEL-X86: ## %bb.0: ; FASTISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; FASTISEL-X86-NEXT: cmpl %eax, {{[0-9]+}}(%esp) -; FASTISEL-X86-NEXT: jge LBB8_1 -; FASTISEL-X86-NEXT: ## %bb.2: ## %bb1 +; FASTISEL-X86-NEXT: jge LBB8_2 +; FASTISEL-X86-NEXT: ## %bb.1: ## %bb1 ; FASTISEL-X86-NEXT: xorl %eax, %eax ; FASTISEL-X86-NEXT: retl -; FASTISEL-X86-NEXT: LBB8_1: ## %bb2 +; FASTISEL-X86-NEXT: LBB8_2: ## %bb2 ; FASTISEL-X86-NEXT: movl $1, %eax ; FASTISEL-X86-NEXT: retl ; @@ -621,11 +621,11 @@ define i32 @icmp_slt_2(i32 %x, i32 %y) { ; GISEL-X86-NEXT: cmpl %eax, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: setl %al ; GISEL-X86-NEXT: testb $1, %al -; GISEL-X86-NEXT: je LBB8_1 -; GISEL-X86-NEXT: ## %bb.2: ## %bb1 +; GISEL-X86-NEXT: je LBB8_2 +; GISEL-X86-NEXT: ## %bb.1: ## %bb1 ; GISEL-X86-NEXT: xorl %eax, %eax ; GISEL-X86-NEXT: retl -; GISEL-X86-NEXT: LBB8_1: ## %bb2 +; GISEL-X86-NEXT: LBB8_2: ## %bb2 ; GISEL-X86-NEXT: movl $1, %eax ; GISEL-X86-NEXT: retl %1 = icmp slt i32 %x, %y @@ -640,11 +640,11 @@ define i32 @icmp_sle_2(i32 %x, i32 %y) { ; X64-LABEL: icmp_sle_2: ; X64: ## %bb.0: ; X64-NEXT: cmpl %esi, %edi -; X64-NEXT: jg LBB9_1 -; X64-NEXT: ## %bb.2: ## %bb1 +; X64-NEXT: jg LBB9_2 +; X64-NEXT: ## %bb.1: ## %bb1 ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: retq -; X64-NEXT: LBB9_1: ## %bb2 +; X64-NEXT: LBB9_2: ## %bb2 ; X64-NEXT: movl $1, %eax ; X64-NEXT: retq ; @@ -653,11 +653,11 @@ define i32 @icmp_sle_2(i32 %x, i32 %y) { ; GISEL-X64-NEXT: cmpl %esi, %edi ; GISEL-X64-NEXT: setle %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB9_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB9_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB9_1: ## %bb2 +; GISEL-X64-NEXT: LBB9_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq ; @@ -665,11 +665,11 @@ define i32 @icmp_sle_2(i32 %x, i32 %y) { ; SDAG-X86: ## %bb.0: ; SDAG-X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; SDAG-X86-NEXT: cmpl {{[0-9]+}}(%esp), %eax -; SDAG-X86-NEXT: jg LBB9_1 -; SDAG-X86-NEXT: ## %bb.2: ## %bb1 +; SDAG-X86-NEXT: jg LBB9_2 +; SDAG-X86-NEXT: ## %bb.1: ## %bb1 ; SDAG-X86-NEXT: xorl %eax, %eax ; SDAG-X86-NEXT: retl -; SDAG-X86-NEXT: LBB9_1: ## %bb2 +; SDAG-X86-NEXT: LBB9_2: ## %bb2 ; SDAG-X86-NEXT: movl $1, %eax ; SDAG-X86-NEXT: retl ; @@ -677,11 +677,11 @@ define i32 @icmp_sle_2(i32 %x, i32 %y) { ; FASTISEL-X86: ## %bb.0: ; FASTISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; FASTISEL-X86-NEXT: cmpl %eax, {{[0-9]+}}(%esp) -; FASTISEL-X86-NEXT: jg LBB9_1 -; FASTISEL-X86-NEXT: ## %bb.2: ## %bb1 +; FASTISEL-X86-NEXT: jg LBB9_2 +; FASTISEL-X86-NEXT: ## %bb.1: ## %bb1 ; FASTISEL-X86-NEXT: xorl %eax, %eax ; FASTISEL-X86-NEXT: retl -; FASTISEL-X86-NEXT: LBB9_1: ## %bb2 +; FASTISEL-X86-NEXT: LBB9_2: ## %bb2 ; FASTISEL-X86-NEXT: movl $1, %eax ; FASTISEL-X86-NEXT: retl ; @@ -691,11 +691,11 @@ define i32 @icmp_sle_2(i32 %x, i32 %y) { ; GISEL-X86-NEXT: cmpl %eax, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: setle %al ; GISEL-X86-NEXT: testb $1, %al -; GISEL-X86-NEXT: je LBB9_1 -; GISEL-X86-NEXT: ## %bb.2: ## %bb1 +; GISEL-X86-NEXT: je LBB9_2 +; GISEL-X86-NEXT: ## %bb.1: ## %bb1 ; GISEL-X86-NEXT: xorl %eax, %eax ; GISEL-X86-NEXT: retl -; GISEL-X86-NEXT: LBB9_1: ## %bb2 +; GISEL-X86-NEXT: LBB9_2: ## %bb2 ; GISEL-X86-NEXT: movl $1, %eax ; GISEL-X86-NEXT: retl %1 = icmp sle i32 %x, %y @@ -711,11 +711,11 @@ define i32 @icmp_eq(i32 %x) { ; SDAG: ## %bb.0: ; SDAG-NEXT: movb $1, %al ; SDAG-NEXT: testb %al, %al -; SDAG-NEXT: je LBB10_1 -; SDAG-NEXT: ## %bb.2: ## %bb1 +; SDAG-NEXT: je LBB10_2 +; SDAG-NEXT: ## %bb.1: ## %bb1 ; SDAG-NEXT: xorl %eax, %eax ; SDAG-NEXT: ret{{[l|q]}} -; SDAG-NEXT: LBB10_1: ## %bb2 +; SDAG-NEXT: LBB10_2: ## %bb2 ; SDAG-NEXT: movl $1, %eax ; SDAG-NEXT: ret{{[l|q]}} ; @@ -729,11 +729,11 @@ define i32 @icmp_eq(i32 %x) { ; GISEL-X64-NEXT: cmpl %edi, %edi ; GISEL-X64-NEXT: sete %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB10_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB10_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB10_1: ## %bb2 +; GISEL-X64-NEXT: LBB10_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq ; @@ -743,11 +743,11 @@ define i32 @icmp_eq(i32 %x) { ; GISEL-X86-NEXT: cmpl %eax, %eax ; GISEL-X86-NEXT: sete %al ; GISEL-X86-NEXT: testb $1, %al -; GISEL-X86-NEXT: je LBB10_1 -; GISEL-X86-NEXT: ## %bb.2: ## %bb1 +; GISEL-X86-NEXT: je LBB10_2 +; GISEL-X86-NEXT: ## %bb.1: ## %bb1 ; GISEL-X86-NEXT: xorl %eax, %eax ; GISEL-X86-NEXT: retl -; GISEL-X86-NEXT: LBB10_1: ## %bb2 +; GISEL-X86-NEXT: LBB10_2: ## %bb2 ; GISEL-X86-NEXT: movl $1, %eax ; GISEL-X86-NEXT: retl %1 = icmp eq i32 %x, %x @@ -763,11 +763,11 @@ define i32 @icmp_ne(i32 %x) { ; SDAG: ## %bb.0: ; SDAG-NEXT: xorl %eax, %eax ; SDAG-NEXT: testb %al, %al -; SDAG-NEXT: je LBB11_1 -; SDAG-NEXT: ## %bb.2: ## %bb1 +; SDAG-NEXT: je LBB11_2 +; SDAG-NEXT: ## %bb.1: ## %bb1 ; SDAG-NEXT: xorl %eax, %eax ; SDAG-NEXT: ret{{[l|q]}} -; SDAG-NEXT: LBB11_1: ## %bb2 +; SDAG-NEXT: LBB11_2: ## %bb2 ; SDAG-NEXT: movl $1, %eax ; SDAG-NEXT: ret{{[l|q]}} ; @@ -781,11 +781,11 @@ define i32 @icmp_ne(i32 %x) { ; GISEL-X64-NEXT: cmpl %edi, %edi ; GISEL-X64-NEXT: setne %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB11_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB11_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB11_1: ## %bb2 +; GISEL-X64-NEXT: LBB11_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq ; @@ -795,11 +795,11 @@ define i32 @icmp_ne(i32 %x) { ; GISEL-X86-NEXT: cmpl %eax, %eax ; GISEL-X86-NEXT: setne %al ; GISEL-X86-NEXT: testb $1, %al -; GISEL-X86-NEXT: je LBB11_1 -; GISEL-X86-NEXT: ## %bb.2: ## %bb1 +; GISEL-X86-NEXT: je LBB11_2 +; GISEL-X86-NEXT: ## %bb.1: ## %bb1 ; GISEL-X86-NEXT: xorl %eax, %eax ; GISEL-X86-NEXT: retl -; GISEL-X86-NEXT: LBB11_1: ## %bb2 +; GISEL-X86-NEXT: LBB11_2: ## %bb2 ; GISEL-X86-NEXT: movl $1, %eax ; GISEL-X86-NEXT: retl %1 = icmp ne i32 %x, %x @@ -815,11 +815,11 @@ define i32 @icmp_ugt(i32 %x) { ; SDAG: ## %bb.0: ; SDAG-NEXT: xorl %eax, %eax ; SDAG-NEXT: testb %al, %al -; SDAG-NEXT: je LBB12_1 -; SDAG-NEXT: ## %bb.2: ## %bb1 +; SDAG-NEXT: je LBB12_2 +; SDAG-NEXT: ## %bb.1: ## %bb1 ; SDAG-NEXT: xorl %eax, %eax ; SDAG-NEXT: ret{{[l|q]}} -; SDAG-NEXT: LBB12_1: ## %bb2 +; SDAG-NEXT: LBB12_2: ## %bb2 ; SDAG-NEXT: movl $1, %eax ; SDAG-NEXT: ret{{[l|q]}} ; @@ -833,11 +833,11 @@ define i32 @icmp_ugt(i32 %x) { ; GISEL-X64-NEXT: cmpl %edi, %edi ; GISEL-X64-NEXT: seta %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB12_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB12_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB12_1: ## %bb2 +; GISEL-X64-NEXT: LBB12_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq ; @@ -847,11 +847,11 @@ define i32 @icmp_ugt(i32 %x) { ; GISEL-X86-NEXT: cmpl %eax, %eax ; GISEL-X86-NEXT: seta %al ; GISEL-X86-NEXT: testb $1, %al -; GISEL-X86-NEXT: je LBB12_1 -; GISEL-X86-NEXT: ## %bb.2: ## %bb1 +; GISEL-X86-NEXT: je LBB12_2 +; GISEL-X86-NEXT: ## %bb.1: ## %bb1 ; GISEL-X86-NEXT: xorl %eax, %eax ; GISEL-X86-NEXT: retl -; GISEL-X86-NEXT: LBB12_1: ## %bb2 +; GISEL-X86-NEXT: LBB12_2: ## %bb2 ; GISEL-X86-NEXT: movl $1, %eax ; GISEL-X86-NEXT: retl %1 = icmp ugt i32 %x, %x @@ -867,11 +867,11 @@ define i32 @icmp_uge(i32 %x) { ; SDAG: ## %bb.0: ; SDAG-NEXT: movb $1, %al ; SDAG-NEXT: testb %al, %al -; SDAG-NEXT: je LBB13_1 -; SDAG-NEXT: ## %bb.2: ## %bb1 +; SDAG-NEXT: je LBB13_2 +; SDAG-NEXT: ## %bb.1: ## %bb1 ; SDAG-NEXT: xorl %eax, %eax ; SDAG-NEXT: ret{{[l|q]}} -; SDAG-NEXT: LBB13_1: ## %bb2 +; SDAG-NEXT: LBB13_2: ## %bb2 ; SDAG-NEXT: movl $1, %eax ; SDAG-NEXT: ret{{[l|q]}} ; @@ -885,11 +885,11 @@ define i32 @icmp_uge(i32 %x) { ; GISEL-X64-NEXT: cmpl %edi, %edi ; GISEL-X64-NEXT: setae %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB13_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB13_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB13_1: ## %bb2 +; GISEL-X64-NEXT: LBB13_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq ; @@ -899,11 +899,11 @@ define i32 @icmp_uge(i32 %x) { ; GISEL-X86-NEXT: cmpl %eax, %eax ; GISEL-X86-NEXT: setae %al ; GISEL-X86-NEXT: testb $1, %al -; GISEL-X86-NEXT: je LBB13_1 -; GISEL-X86-NEXT: ## %bb.2: ## %bb1 +; GISEL-X86-NEXT: je LBB13_2 +; GISEL-X86-NEXT: ## %bb.1: ## %bb1 ; GISEL-X86-NEXT: xorl %eax, %eax ; GISEL-X86-NEXT: retl -; GISEL-X86-NEXT: LBB13_1: ## %bb2 +; GISEL-X86-NEXT: LBB13_2: ## %bb2 ; GISEL-X86-NEXT: movl $1, %eax ; GISEL-X86-NEXT: retl %1 = icmp uge i32 %x, %x @@ -919,11 +919,11 @@ define i32 @icmp_ult(i32 %x) { ; SDAG: ## %bb.0: ; SDAG-NEXT: xorl %eax, %eax ; SDAG-NEXT: testb %al, %al -; SDAG-NEXT: je LBB14_1 -; SDAG-NEXT: ## %bb.2: ## %bb1 +; SDAG-NEXT: je LBB14_2 +; SDAG-NEXT: ## %bb.1: ## %bb1 ; SDAG-NEXT: xorl %eax, %eax ; SDAG-NEXT: ret{{[l|q]}} -; SDAG-NEXT: LBB14_1: ## %bb2 +; SDAG-NEXT: LBB14_2: ## %bb2 ; SDAG-NEXT: movl $1, %eax ; SDAG-NEXT: ret{{[l|q]}} ; @@ -937,11 +937,11 @@ define i32 @icmp_ult(i32 %x) { ; GISEL-X64-NEXT: cmpl %edi, %edi ; GISEL-X64-NEXT: setb %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB14_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB14_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB14_1: ## %bb2 +; GISEL-X64-NEXT: LBB14_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq ; @@ -951,11 +951,11 @@ define i32 @icmp_ult(i32 %x) { ; GISEL-X86-NEXT: cmpl %eax, %eax ; GISEL-X86-NEXT: setb %al ; GISEL-X86-NEXT: testb $1, %al -; GISEL-X86-NEXT: je LBB14_1 -; GISEL-X86-NEXT: ## %bb.2: ## %bb1 +; GISEL-X86-NEXT: je LBB14_2 +; GISEL-X86-NEXT: ## %bb.1: ## %bb1 ; GISEL-X86-NEXT: xorl %eax, %eax ; GISEL-X86-NEXT: retl -; GISEL-X86-NEXT: LBB14_1: ## %bb2 +; GISEL-X86-NEXT: LBB14_2: ## %bb2 ; GISEL-X86-NEXT: movl $1, %eax ; GISEL-X86-NEXT: retl %1 = icmp ult i32 %x, %x @@ -971,11 +971,11 @@ define i32 @icmp_ule(i32 %x) { ; SDAG: ## %bb.0: ; SDAG-NEXT: movb $1, %al ; SDAG-NEXT: testb %al, %al -; SDAG-NEXT: je LBB15_1 -; SDAG-NEXT: ## %bb.2: ## %bb1 +; SDAG-NEXT: je LBB15_2 +; SDAG-NEXT: ## %bb.1: ## %bb1 ; SDAG-NEXT: xorl %eax, %eax ; SDAG-NEXT: ret{{[l|q]}} -; SDAG-NEXT: LBB15_1: ## %bb2 +; SDAG-NEXT: LBB15_2: ## %bb2 ; SDAG-NEXT: movl $1, %eax ; SDAG-NEXT: ret{{[l|q]}} ; @@ -989,11 +989,11 @@ define i32 @icmp_ule(i32 %x) { ; GISEL-X64-NEXT: cmpl %edi, %edi ; GISEL-X64-NEXT: setbe %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB15_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB15_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB15_1: ## %bb2 +; GISEL-X64-NEXT: LBB15_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq ; @@ -1003,11 +1003,11 @@ define i32 @icmp_ule(i32 %x) { ; GISEL-X86-NEXT: cmpl %eax, %eax ; GISEL-X86-NEXT: setbe %al ; GISEL-X86-NEXT: testb $1, %al -; GISEL-X86-NEXT: je LBB15_1 -; GISEL-X86-NEXT: ## %bb.2: ## %bb1 +; GISEL-X86-NEXT: je LBB15_2 +; GISEL-X86-NEXT: ## %bb.1: ## %bb1 ; GISEL-X86-NEXT: xorl %eax, %eax ; GISEL-X86-NEXT: retl -; GISEL-X86-NEXT: LBB15_1: ## %bb2 +; GISEL-X86-NEXT: LBB15_2: ## %bb2 ; GISEL-X86-NEXT: movl $1, %eax ; GISEL-X86-NEXT: retl %1 = icmp ule i32 %x, %x @@ -1023,11 +1023,11 @@ define i32 @icmp_sgt(i32 %x) { ; SDAG: ## %bb.0: ; SDAG-NEXT: xorl %eax, %eax ; SDAG-NEXT: testb %al, %al -; SDAG-NEXT: je LBB16_1 -; SDAG-NEXT: ## %bb.2: ## %bb1 +; SDAG-NEXT: je LBB16_2 +; SDAG-NEXT: ## %bb.1: ## %bb1 ; SDAG-NEXT: xorl %eax, %eax ; SDAG-NEXT: ret{{[l|q]}} -; SDAG-NEXT: LBB16_1: ## %bb2 +; SDAG-NEXT: LBB16_2: ## %bb2 ; SDAG-NEXT: movl $1, %eax ; SDAG-NEXT: ret{{[l|q]}} ; @@ -1041,11 +1041,11 @@ define i32 @icmp_sgt(i32 %x) { ; GISEL-X64-NEXT: cmpl %edi, %edi ; GISEL-X64-NEXT: setg %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB16_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB16_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB16_1: ## %bb2 +; GISEL-X64-NEXT: LBB16_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq ; @@ -1055,11 +1055,11 @@ define i32 @icmp_sgt(i32 %x) { ; GISEL-X86-NEXT: cmpl %eax, %eax ; GISEL-X86-NEXT: setg %al ; GISEL-X86-NEXT: testb $1, %al -; GISEL-X86-NEXT: je LBB16_1 -; GISEL-X86-NEXT: ## %bb.2: ## %bb1 +; GISEL-X86-NEXT: je LBB16_2 +; GISEL-X86-NEXT: ## %bb.1: ## %bb1 ; GISEL-X86-NEXT: xorl %eax, %eax ; GISEL-X86-NEXT: retl -; GISEL-X86-NEXT: LBB16_1: ## %bb2 +; GISEL-X86-NEXT: LBB16_2: ## %bb2 ; GISEL-X86-NEXT: movl $1, %eax ; GISEL-X86-NEXT: retl %1 = icmp sgt i32 %x, %x @@ -1075,11 +1075,11 @@ define i32 @icmp_sge(i32 %x) { ; SDAG: ## %bb.0: ; SDAG-NEXT: movb $1, %al ; SDAG-NEXT: testb %al, %al -; SDAG-NEXT: je LBB17_1 -; SDAG-NEXT: ## %bb.2: ## %bb1 +; SDAG-NEXT: je LBB17_2 +; SDAG-NEXT: ## %bb.1: ## %bb1 ; SDAG-NEXT: xorl %eax, %eax ; SDAG-NEXT: ret{{[l|q]}} -; SDAG-NEXT: LBB17_1: ## %bb2 +; SDAG-NEXT: LBB17_2: ## %bb2 ; SDAG-NEXT: movl $1, %eax ; SDAG-NEXT: ret{{[l|q]}} ; @@ -1093,11 +1093,11 @@ define i32 @icmp_sge(i32 %x) { ; GISEL-X64-NEXT: cmpl %edi, %edi ; GISEL-X64-NEXT: setge %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB17_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB17_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB17_1: ## %bb2 +; GISEL-X64-NEXT: LBB17_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq ; @@ -1107,11 +1107,11 @@ define i32 @icmp_sge(i32 %x) { ; GISEL-X86-NEXT: cmpl %eax, %eax ; GISEL-X86-NEXT: setge %al ; GISEL-X86-NEXT: testb $1, %al -; GISEL-X86-NEXT: je LBB17_1 -; GISEL-X86-NEXT: ## %bb.2: ## %bb1 +; GISEL-X86-NEXT: je LBB17_2 +; GISEL-X86-NEXT: ## %bb.1: ## %bb1 ; GISEL-X86-NEXT: xorl %eax, %eax ; GISEL-X86-NEXT: retl -; GISEL-X86-NEXT: LBB17_1: ## %bb2 +; GISEL-X86-NEXT: LBB17_2: ## %bb2 ; GISEL-X86-NEXT: movl $1, %eax ; GISEL-X86-NEXT: retl %1 = icmp sge i32 %x, %x @@ -1127,11 +1127,11 @@ define i32 @icmp_slt(i32 %x) { ; SDAG: ## %bb.0: ; SDAG-NEXT: xorl %eax, %eax ; SDAG-NEXT: testb %al, %al -; SDAG-NEXT: je LBB18_1 -; SDAG-NEXT: ## %bb.2: ## %bb1 +; SDAG-NEXT: je LBB18_2 +; SDAG-NEXT: ## %bb.1: ## %bb1 ; SDAG-NEXT: xorl %eax, %eax ; SDAG-NEXT: ret{{[l|q]}} -; SDAG-NEXT: LBB18_1: ## %bb2 +; SDAG-NEXT: LBB18_2: ## %bb2 ; SDAG-NEXT: movl $1, %eax ; SDAG-NEXT: ret{{[l|q]}} ; @@ -1145,11 +1145,11 @@ define i32 @icmp_slt(i32 %x) { ; GISEL-X64-NEXT: cmpl %edi, %edi ; GISEL-X64-NEXT: setl %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB18_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB18_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB18_1: ## %bb2 +; GISEL-X64-NEXT: LBB18_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq ; @@ -1159,11 +1159,11 @@ define i32 @icmp_slt(i32 %x) { ; GISEL-X86-NEXT: cmpl %eax, %eax ; GISEL-X86-NEXT: setl %al ; GISEL-X86-NEXT: testb $1, %al -; GISEL-X86-NEXT: je LBB18_1 -; GISEL-X86-NEXT: ## %bb.2: ## %bb1 +; GISEL-X86-NEXT: je LBB18_2 +; GISEL-X86-NEXT: ## %bb.1: ## %bb1 ; GISEL-X86-NEXT: xorl %eax, %eax ; GISEL-X86-NEXT: retl -; GISEL-X86-NEXT: LBB18_1: ## %bb2 +; GISEL-X86-NEXT: LBB18_2: ## %bb2 ; GISEL-X86-NEXT: movl $1, %eax ; GISEL-X86-NEXT: retl %1 = icmp slt i32 %x, %x @@ -1179,11 +1179,11 @@ define i32 @icmp_sle(i32 %x) { ; SDAG: ## %bb.0: ; SDAG-NEXT: movb $1, %al ; SDAG-NEXT: testb %al, %al -; SDAG-NEXT: je LBB19_1 -; SDAG-NEXT: ## %bb.2: ## %bb1 +; SDAG-NEXT: je LBB19_2 +; SDAG-NEXT: ## %bb.1: ## %bb1 ; SDAG-NEXT: xorl %eax, %eax ; SDAG-NEXT: ret{{[l|q]}} -; SDAG-NEXT: LBB19_1: ## %bb2 +; SDAG-NEXT: LBB19_2: ## %bb2 ; SDAG-NEXT: movl $1, %eax ; SDAG-NEXT: ret{{[l|q]}} ; @@ -1197,11 +1197,11 @@ define i32 @icmp_sle(i32 %x) { ; GISEL-X64-NEXT: cmpl %edi, %edi ; GISEL-X64-NEXT: setle %al ; GISEL-X64-NEXT: testb $1, %al -; GISEL-X64-NEXT: je LBB19_1 -; GISEL-X64-NEXT: ## %bb.2: ## %bb1 +; GISEL-X64-NEXT: je LBB19_2 +; GISEL-X64-NEXT: ## %bb.1: ## %bb1 ; GISEL-X64-NEXT: xorl %eax, %eax ; GISEL-X64-NEXT: retq -; GISEL-X64-NEXT: LBB19_1: ## %bb2 +; GISEL-X64-NEXT: LBB19_2: ## %bb2 ; GISEL-X64-NEXT: movl $1, %eax ; GISEL-X64-NEXT: retq ; @@ -1211,11 +1211,11 @@ define i32 @icmp_sle(i32 %x) { ; GISEL-X86-NEXT: cmpl %eax, %eax ; GISEL-X86-NEXT: setle %al ; GISEL-X86-NEXT: testb $1, %al -; GISEL-X86-NEXT: je LBB19_1 -; GISEL-X86-NEXT: ## %bb.2: ## %bb1 +; GISEL-X86-NEXT: je LBB19_2 +; GISEL-X86-NEXT: ## %bb.1: ## %bb1 ; GISEL-X86-NEXT: xorl %eax, %eax ; GISEL-X86-NEXT: retl -; GISEL-X86-NEXT: LBB19_1: ## %bb2 +; GISEL-X86-NEXT: LBB19_2: ## %bb2 ; GISEL-X86-NEXT: movl $1, %eax ; GISEL-X86-NEXT: retl %1 = icmp sle i32 %x, %x diff --git a/llvm/test/CodeGen/X86/isel-int-to-fp.ll b/llvm/test/CodeGen/X86/isel-int-to-fp.ll index 5884944e41986..8fba1b88e1d88 100644 --- a/llvm/test/CodeGen/X86/isel-int-to-fp.ll +++ b/llvm/test/CodeGen/X86/isel-int-to-fp.ll @@ -100,11 +100,11 @@ define float @test_ui64_to_float(i64 %x) { ; SDAG-X64-LABEL: test_ui64_to_float: ; SDAG-X64: # %bb.0: # %entry ; SDAG-X64-NEXT: testq %rdi, %rdi -; SDAG-X64-NEXT: js .LBB4_1 -; SDAG-X64-NEXT: # %bb.2: # %entry +; SDAG-X64-NEXT: js .LBB4_2 +; SDAG-X64-NEXT: # %bb.1: # %entry ; SDAG-X64-NEXT: cvtsi2ss %rdi, %xmm0 ; SDAG-X64-NEXT: retq -; SDAG-X64-NEXT: .LBB4_1: +; SDAG-X64-NEXT: .LBB4_2: ; SDAG-X64-NEXT: movq %rdi, %rax ; SDAG-X64-NEXT: shrq %rax ; SDAG-X64-NEXT: andl $1, %edi diff --git a/llvm/test/CodeGen/X86/isel-phi.ll b/llvm/test/CodeGen/X86/isel-phi.ll index ee2039492abfd..5239449ca4233 100644 --- a/llvm/test/CodeGen/X86/isel-phi.ll +++ b/llvm/test/CodeGen/X86/isel-phi.ll @@ -11,14 +11,14 @@ define i1 @test_i1(i1 %a, i1 %b, i1 %c, i1 %pred0, i1 %pred1) { ; X86-LABEL: test_i1: ; X86: # %bb.0: # %entry ; X86-NEXT: testb $1, {{[0-9]+}}(%esp) -; X86-NEXT: je .LBB0_1 -; X86-NEXT: # %bb.2: # %cond +; X86-NEXT: je .LBB0_3 +; X86-NEXT: # %bb.1: # %cond ; X86-NEXT: testb $1, {{[0-9]+}}(%esp) ; X86-NEXT: je .LBB0_4 -; X86-NEXT: # %bb.3: +; X86-NEXT: # %bb.2: ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB0_1: +; X86-NEXT: .LBB0_3: ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X86-NEXT: retl ; X86-NEXT: .LBB0_4: # %cond.false @@ -28,17 +28,17 @@ define i1 @test_i1(i1 %a, i1 %b, i1 %c, i1 %pred0, i1 %pred1) { ; X64-LABEL: test_i1: ; X64: # %bb.0: # %entry ; X64-NEXT: testb $1, %cl -; X64-NEXT: je .LBB0_1 -; X64-NEXT: # %bb.2: # %cond +; X64-NEXT: je .LBB0_4 +; X64-NEXT: # %bb.1: # %cond ; X64-NEXT: movl %esi, %eax ; X64-NEXT: testb $1, %r8b -; X64-NEXT: jne .LBB0_4 -; X64-NEXT: # %bb.3: # %cond.false +; X64-NEXT: jne .LBB0_3 +; X64-NEXT: # %bb.2: # %cond.false ; X64-NEXT: movl %edx, %eax -; X64-NEXT: .LBB0_4: # %cond.end +; X64-NEXT: .LBB0_3: # %cond.end ; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq -; X64-NEXT: .LBB0_1: +; X64-NEXT: .LBB0_4: ; X64-NEXT: movl %edi, %eax ; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq @@ -287,38 +287,38 @@ define ptr @test_ptr(ptr %a, ptr %b, ptr %c, ptr %d, ptr %e, ptr %f, ptr %g, i1 ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: testb $1, {{[0-9]+}}(%esp) -; X86-NEXT: je .LBB7_6 +; X86-NEXT: je .LBB7_3 ; X86-NEXT: # %bb.1: # %cond.true ; X86-NEXT: testb $1, %cl -; X86-NEXT: je .LBB7_3 +; X86-NEXT: je .LBB7_6 ; X86-NEXT: # %bb.2: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB7_6: # %cond.false +; X86-NEXT: .LBB7_3: # %cond.false ; X86-NEXT: testb $1, %cl -; X86-NEXT: je .LBB7_10 -; X86-NEXT: # %bb.7: # %cond.false.true +; X86-NEXT: je .LBB7_8 +; X86-NEXT: # %bb.4: # %cond.false.true ; X86-NEXT: testb $1, %al -; X86-NEXT: je .LBB7_9 -; X86-NEXT: # %bb.8: +; X86-NEXT: je .LBB7_10 +; X86-NEXT: # %bb.5: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB7_3: # %cond.true.false +; X86-NEXT: .LBB7_6: # %cond.true.false ; X86-NEXT: testb $1, %al -; X86-NEXT: je .LBB7_5 -; X86-NEXT: # %bb.4: +; X86-NEXT: je .LBB7_11 +; X86-NEXT: # %bb.7: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB7_10: # %cond.false.false +; X86-NEXT: .LBB7_8: # %cond.false.false ; X86-NEXT: testb $1, %al ; X86-NEXT: je .LBB7_12 -; X86-NEXT: # %bb.11: +; X86-NEXT: # %bb.9: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB7_9: # %cond.false.true.false +; X86-NEXT: .LBB7_10: # %cond.false.true.false ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB7_5: # %cond.true.false.false +; X86-NEXT: .LBB7_11: # %cond.true.false.false ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: retl ; X86-NEXT: .LBB7_12: # %cond.false.false.false diff --git a/llvm/test/CodeGen/X86/isel-select-cmov.ll b/llvm/test/CodeGen/X86/isel-select-cmov.ll index d013ad2c7fbff..992b459b7bcdc 100644 --- a/llvm/test/CodeGen/X86/isel-select-cmov.ll +++ b/llvm/test/CodeGen/X86/isel-select-cmov.ll @@ -48,12 +48,12 @@ define zeroext i8 @select_cmov_i8(i1 zeroext %cond, i8 zeroext %a, i8 zeroext %b ; SDAG-X86-LABEL: select_cmov_i8: ; SDAG-X86: ## %bb.0: ; SDAG-X86-NEXT: cmpb $0, {{[0-9]+}}(%esp) -; SDAG-X86-NEXT: jne LBB0_1 -; SDAG-X86-NEXT: ## %bb.2: +; SDAG-X86-NEXT: jne LBB0_2 +; SDAG-X86-NEXT: ## %bb.1: ; SDAG-X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; SDAG-X86-NEXT: movzbl (%eax), %eax ; SDAG-X86-NEXT: retl -; SDAG-X86-NEXT: LBB0_1: +; SDAG-X86-NEXT: LBB0_2: ; SDAG-X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; SDAG-X86-NEXT: movzbl (%eax), %eax ; SDAG-X86-NEXT: retl @@ -70,12 +70,12 @@ define zeroext i8 @select_cmov_i8(i1 zeroext %cond, i8 zeroext %a, i8 zeroext %b ; FAST-X86-LABEL: select_cmov_i8: ; FAST-X86: ## %bb.0: ; FAST-X86-NEXT: testb $1, {{[0-9]+}}(%esp) -; FAST-X86-NEXT: jne LBB0_1 -; FAST-X86-NEXT: ## %bb.2: +; FAST-X86-NEXT: jne LBB0_2 +; FAST-X86-NEXT: ## %bb.1: ; FAST-X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; FAST-X86-NEXT: movzbl %al, %eax ; FAST-X86-NEXT: retl -; FAST-X86-NEXT: LBB0_1: +; FAST-X86-NEXT: LBB0_2: ; FAST-X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; FAST-X86-NEXT: movzbl %al, %eax ; FAST-X86-NEXT: retl @@ -83,12 +83,12 @@ define zeroext i8 @select_cmov_i8(i1 zeroext %cond, i8 zeroext %a, i8 zeroext %b ; FAST-X86-CMOV-LABEL: select_cmov_i8: ; FAST-X86-CMOV: ## %bb.0: ; FAST-X86-CMOV-NEXT: testb $1, {{[0-9]+}}(%esp) -; FAST-X86-CMOV-NEXT: jne LBB0_1 -; FAST-X86-CMOV-NEXT: ## %bb.2: +; FAST-X86-CMOV-NEXT: jne LBB0_2 +; FAST-X86-CMOV-NEXT: ## %bb.1: ; FAST-X86-CMOV-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; FAST-X86-CMOV-NEXT: movzbl %al, %eax ; FAST-X86-CMOV-NEXT: retl -; FAST-X86-CMOV-NEXT: LBB0_1: +; FAST-X86-CMOV-NEXT: LBB0_2: ; FAST-X86-CMOV-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; FAST-X86-CMOV-NEXT: movzbl %al, %eax ; FAST-X86-CMOV-NEXT: retl @@ -97,12 +97,12 @@ define zeroext i8 @select_cmov_i8(i1 zeroext %cond, i8 zeroext %a, i8 zeroext %b ; GISEL-X86: ## %bb.0: ; GISEL-X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; GISEL-X86-NEXT: testl %eax, %eax -; GISEL-X86-NEXT: je LBB0_1 -; GISEL-X86-NEXT: ## %bb.2: +; GISEL-X86-NEXT: je LBB0_2 +; GISEL-X86-NEXT: ## %bb.1: ; GISEL-X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; GISEL-X86-NEXT: ## kill: def $al killed $al killed $eax ; GISEL-X86-NEXT: retl -; GISEL-X86-NEXT: LBB0_1: +; GISEL-X86-NEXT: LBB0_2: ; GISEL-X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; GISEL-X86-NEXT: ## kill: def $al killed $al killed $eax ; GISEL-X86-NEXT: retl @@ -156,12 +156,12 @@ define zeroext i16 @select_cmov_i16(i1 zeroext %cond, i16 zeroext %a, i16 zeroex ; SDAG-X86-LABEL: select_cmov_i16: ; SDAG-X86: ## %bb.0: ; SDAG-X86-NEXT: cmpb $0, {{[0-9]+}}(%esp) -; SDAG-X86-NEXT: jne LBB1_1 -; SDAG-X86-NEXT: ## %bb.2: +; SDAG-X86-NEXT: jne LBB1_2 +; SDAG-X86-NEXT: ## %bb.1: ; SDAG-X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; SDAG-X86-NEXT: movzwl (%eax), %eax ; SDAG-X86-NEXT: retl -; SDAG-X86-NEXT: LBB1_1: +; SDAG-X86-NEXT: LBB1_2: ; SDAG-X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; SDAG-X86-NEXT: movzwl (%eax), %eax ; SDAG-X86-NEXT: retl @@ -178,12 +178,12 @@ define zeroext i16 @select_cmov_i16(i1 zeroext %cond, i16 zeroext %a, i16 zeroex ; FAST-X86-LABEL: select_cmov_i16: ; FAST-X86: ## %bb.0: ; FAST-X86-NEXT: testb $1, {{[0-9]+}}(%esp) -; FAST-X86-NEXT: jne LBB1_1 -; FAST-X86-NEXT: ## %bb.2: +; FAST-X86-NEXT: jne LBB1_2 +; FAST-X86-NEXT: ## %bb.1: ; FAST-X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; FAST-X86-NEXT: movzwl %ax, %eax ; FAST-X86-NEXT: retl -; FAST-X86-NEXT: LBB1_1: +; FAST-X86-NEXT: LBB1_2: ; FAST-X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; FAST-X86-NEXT: movzwl %ax, %eax ; FAST-X86-NEXT: retl @@ -200,12 +200,12 @@ define zeroext i16 @select_cmov_i16(i1 zeroext %cond, i16 zeroext %a, i16 zeroex ; GISEL-X86: ## %bb.0: ; GISEL-X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; GISEL-X86-NEXT: testl %eax, %eax -; GISEL-X86-NEXT: je LBB1_1 -; GISEL-X86-NEXT: ## %bb.2: +; GISEL-X86-NEXT: je LBB1_2 +; GISEL-X86-NEXT: ## %bb.1: ; GISEL-X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; GISEL-X86-NEXT: ## kill: def $ax killed $ax killed $eax ; GISEL-X86-NEXT: retl -; GISEL-X86-NEXT: LBB1_1: +; GISEL-X86-NEXT: LBB1_2: ; GISEL-X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; GISEL-X86-NEXT: ## kill: def $ax killed $ax killed $eax ; GISEL-X86-NEXT: retl @@ -361,12 +361,12 @@ define i32 @select_cmov_i32(i1 zeroext %cond, i32 %a, i32 %b) { ; SDAG-X86-LABEL: select_cmov_i32: ; SDAG-X86: ## %bb.0: ; SDAG-X86-NEXT: cmpb $0, {{[0-9]+}}(%esp) -; SDAG-X86-NEXT: jne LBB3_1 -; SDAG-X86-NEXT: ## %bb.2: +; SDAG-X86-NEXT: jne LBB3_2 +; SDAG-X86-NEXT: ## %bb.1: ; SDAG-X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; SDAG-X86-NEXT: movl (%eax), %eax ; SDAG-X86-NEXT: retl -; SDAG-X86-NEXT: LBB3_1: +; SDAG-X86-NEXT: LBB3_2: ; SDAG-X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; SDAG-X86-NEXT: movl (%eax), %eax ; SDAG-X86-NEXT: retl @@ -383,11 +383,11 @@ define i32 @select_cmov_i32(i1 zeroext %cond, i32 %a, i32 %b) { ; FAST-X86-LABEL: select_cmov_i32: ; FAST-X86: ## %bb.0: ; FAST-X86-NEXT: testb $1, {{[0-9]+}}(%esp) -; FAST-X86-NEXT: jne LBB3_1 -; FAST-X86-NEXT: ## %bb.2: +; FAST-X86-NEXT: jne LBB3_2 +; FAST-X86-NEXT: ## %bb.1: ; FAST-X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; FAST-X86-NEXT: retl -; FAST-X86-NEXT: LBB3_1: +; FAST-X86-NEXT: LBB3_2: ; FAST-X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; FAST-X86-NEXT: retl ; @@ -402,11 +402,11 @@ define i32 @select_cmov_i32(i1 zeroext %cond, i32 %a, i32 %b) { ; GISEL-X86: ## %bb.0: ; GISEL-X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; GISEL-X86-NEXT: testl %eax, %eax -; GISEL-X86-NEXT: je LBB3_1 -; GISEL-X86-NEXT: ## %bb.2: +; GISEL-X86-NEXT: je LBB3_2 +; GISEL-X86-NEXT: ## %bb.1: ; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; GISEL-X86-NEXT: retl -; GISEL-X86-NEXT: LBB3_1: +; GISEL-X86-NEXT: LBB3_2: ; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; GISEL-X86-NEXT: retl ; @@ -550,11 +550,11 @@ define i64 @select_cmov_i64(i1 zeroext %cond, i64 %a, i64 %b) { ; SDAG-X86-LABEL: select_cmov_i64: ; SDAG-X86: ## %bb.0: ; SDAG-X86-NEXT: cmpb $0, {{[0-9]+}}(%esp) -; SDAG-X86-NEXT: jne LBB5_1 -; SDAG-X86-NEXT: ## %bb.2: +; SDAG-X86-NEXT: jne LBB5_2 +; SDAG-X86-NEXT: ## %bb.1: ; SDAG-X86-NEXT: leal {{[0-9]+}}(%esp), %ecx ; SDAG-X86-NEXT: jmp LBB5_3 -; SDAG-X86-NEXT: LBB5_1: +; SDAG-X86-NEXT: LBB5_2: ; SDAG-X86-NEXT: leal {{[0-9]+}}(%esp), %ecx ; SDAG-X86-NEXT: LBB5_3: ; SDAG-X86-NEXT: movl (%ecx), %eax @@ -574,12 +574,12 @@ define i64 @select_cmov_i64(i1 zeroext %cond, i64 %a, i64 %b) { ; FAST-X86-LABEL: select_cmov_i64: ; FAST-X86: ## %bb.0: ; FAST-X86-NEXT: cmpb $0, {{[0-9]+}}(%esp) -; FAST-X86-NEXT: jne LBB5_1 -; FAST-X86-NEXT: ## %bb.2: +; FAST-X86-NEXT: jne LBB5_2 +; FAST-X86-NEXT: ## %bb.1: ; FAST-X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; FAST-X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; FAST-X86-NEXT: retl -; FAST-X86-NEXT: LBB5_1: +; FAST-X86-NEXT: LBB5_2: ; FAST-X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; FAST-X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; FAST-X86-NEXT: retl @@ -597,19 +597,19 @@ define i64 @select_cmov_i64(i1 zeroext %cond, i64 %a, i64 %b) { ; GISEL-X86: ## %bb.0: ; GISEL-X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx ; GISEL-X86-NEXT: testl %ecx, %ecx -; GISEL-X86-NEXT: je LBB5_1 -; GISEL-X86-NEXT: ## %bb.2: +; GISEL-X86-NEXT: je LBB5_3 +; GISEL-X86-NEXT: ## %bb.1: ; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; GISEL-X86-NEXT: testl %ecx, %ecx -; GISEL-X86-NEXT: jne LBB5_5 -; GISEL-X86-NEXT: LBB5_4: +; GISEL-X86-NEXT: jne LBB5_4 +; GISEL-X86-NEXT: LBB5_2: ; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; GISEL-X86-NEXT: retl -; GISEL-X86-NEXT: LBB5_1: +; GISEL-X86-NEXT: LBB5_3: ; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; GISEL-X86-NEXT: testl %ecx, %ecx -; GISEL-X86-NEXT: je LBB5_4 -; GISEL-X86-NEXT: LBB5_5: +; GISEL-X86-NEXT: je LBB5_2 +; GISEL-X86-NEXT: LBB5_4: ; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; GISEL-X86-NEXT: retl ; diff --git a/llvm/test/CodeGen/X86/isel-sink2.ll b/llvm/test/CodeGen/X86/isel-sink2.ll index 46ff70a746434..2df1aa736eae6 100644 --- a/llvm/test/CodeGen/X86/isel-sink2.ll +++ b/llvm/test/CodeGen/X86/isel-sink2.ll @@ -6,11 +6,11 @@ define i8 @test(ptr%P) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: cmpb $0, 4(%eax) -; CHECK-NEXT: je .LBB0_1 -; CHECK-NEXT: # %bb.2: # %F +; CHECK-NEXT: je .LBB0_2 +; CHECK-NEXT: # %bb.1: # %F ; CHECK-NEXT: movzbl 7(%eax), %eax ; CHECK-NEXT: retl -; CHECK-NEXT: .LBB0_1: # %TB +; CHECK-NEXT: .LBB0_2: # %TB ; CHECK-NEXT: movb $4, %al ; CHECK-NEXT: retl %Q = getelementptr i32, ptr %P, i32 1 diff --git a/llvm/test/CodeGen/X86/issue76416.ll b/llvm/test/CodeGen/X86/issue76416.ll index 7193e54a6ad55..eab4c7eebdf82 100644 --- a/llvm/test/CodeGen/X86/issue76416.ll +++ b/llvm/test/CodeGen/X86/issue76416.ll @@ -11,20 +11,20 @@ define dso_local void @vga_load_state() #0 { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movl $0, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: cmpl $3, -{{[0-9]+}}(%rsp) -; CHECK-NEXT: jg .LBB0_3 +; CHECK-NEXT: jg .LBB0_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_2: # %for.body +; CHECK-NEXT: .LBB0_1: # %for.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: #APP ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: incl -{{[0-9]+}}(%rsp) ; CHECK-NEXT: cmpl $3, -{{[0-9]+}}(%rsp) -; CHECK-NEXT: jle .LBB0_2 -; CHECK-NEXT: .LBB0_3: # %for.end +; CHECK-NEXT: jle .LBB0_1 +; CHECK-NEXT: .LBB0_2: # %for.end ; CHECK-NEXT: movl $0, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_4: # %for.cond1 +; CHECK-NEXT: .LBB0_3: # %for.cond1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: #APP ; CHECK-NEXT: #NO_APP @@ -34,7 +34,7 @@ define dso_local void @vga_load_state() #0 { ; CHECK-NEXT: movb %al, vga_load_state_data(%rip) ; CHECK-NEXT: leal 1(%rcx), %eax ; CHECK-NEXT: movl %eax, -{{[0-9]+}}(%rsp) -; CHECK-NEXT: jmp .LBB0_4 +; CHECK-NEXT: jmp .LBB0_3 entry: %i = alloca i32, align 4 store i32 0, ptr %i, align 4 diff --git a/llvm/test/CodeGen/X86/jcc-indirect-thunk-kernel.ll b/llvm/test/CodeGen/X86/jcc-indirect-thunk-kernel.ll index d04ae31a9cb3f..3c414113c47ee 100644 --- a/llvm/test/CodeGen/X86/jcc-indirect-thunk-kernel.ll +++ b/llvm/test/CodeGen/X86/jcc-indirect-thunk-kernel.ll @@ -11,10 +11,10 @@ define dso_local void @foo(ptr %something) #0 { ; CHECK-NEXT: testq %r11, %r11 ; Make sure that a JNE was not generated instead of a JE + JMP sequence ; CHECK-NOT: jne -; CHECK-NEXT: je .LBB0_1 -; CHECK-NEXT: bb.2: # %if.then +; CHECK-NEXT: je .LBB0_2 +; CHECK-NEXT: bb.1: # %if.then ; CHECK-NEXT: jmp __x86_indirect_thunk_r11 -; CHECK-NEXT: LBB0_1: +; CHECK-NEXT: LBB0_2: ; CHECK-NEXT: retq entry: %0 = load ptr, ptr %something, align 8 diff --git a/llvm/test/CodeGen/X86/jump_sign.ll b/llvm/test/CodeGen/X86/jump_sign.ll index d28a93ec3d77c..9316bd72ebd91 100644 --- a/llvm/test/CodeGen/X86/jump_sign.ll +++ b/llvm/test/CodeGen/X86/jump_sign.ll @@ -216,32 +216,32 @@ define void @func_o() nounwind uwtable { ; CHECK-LABEL: func_o: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: je .LBB12_1 -; CHECK-NEXT: # %bb.2: # %if.end.i +; CHECK-NEXT: je .LBB12_8 +; CHECK-NEXT: # %bb.1: # %if.end.i ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB12_5 -; CHECK-NEXT: # %bb.3: # %sw.bb +; CHECK-NEXT: jne .LBB12_6 +; CHECK-NEXT: # %bb.2: # %sw.bb ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB12_8 -; CHECK-NEXT: # %bb.4: # %if.end29 +; CHECK-NEXT: jne .LBB12_4 +; CHECK-NEXT: # %bb.3: # %if.end29 ; CHECK-NEXT: movzwl (%eax), %eax ; CHECK-NEXT: imull $-13107, %eax, %eax # imm = 0xCCCD ; CHECK-NEXT: rorw %ax ; CHECK-NEXT: movzwl %ax, %eax ; CHECK-NEXT: cmpl $6554, %eax # imm = 0x199A -; CHECK-NEXT: jae .LBB12_5 -; CHECK-NEXT: .LBB12_8: # %if.then44 +; CHECK-NEXT: jae .LBB12_6 +; CHECK-NEXT: .LBB12_4: # %if.then44 ; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: je .LBB12_9 -; CHECK-NEXT: # %bb.10: # %if.else.i104 +; CHECK-NEXT: # %bb.5: # %if.else.i104 ; CHECK-NEXT: retl -; CHECK-NEXT: .LBB12_5: # %sw.default +; CHECK-NEXT: .LBB12_6: # %sw.default ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB12_7 -; CHECK-NEXT: # %bb.6: # %if.then.i96 -; CHECK-NEXT: .LBB12_1: # %if.then.i +; CHECK-NEXT: jne .LBB12_10 +; CHECK-NEXT: # %bb.7: # %if.then.i96 +; CHECK-NEXT: .LBB12_8: # %if.then.i ; CHECK-NEXT: .LBB12_9: # %if.then.i103 -; CHECK-NEXT: .LBB12_7: # %if.else.i97 +; CHECK-NEXT: .LBB12_10: # %if.else.i97 entry: %0 = load i16, ptr undef, align 2 br i1 poison, label %if.then.i, label %if.end.i diff --git a/llvm/test/CodeGen/X86/large-constants.ll b/llvm/test/CodeGen/X86/large-constants.ll index ee5b7017900dc..c91d7f1f106ff 100644 --- a/llvm/test/CodeGen/X86/large-constants.ll +++ b/llvm/test/CodeGen/X86/large-constants.ll @@ -6,28 +6,28 @@ define i64 @constant_hoisting(i64 %o0, i64 %o1, i64 %o2, i64 %o3, i64 %o4, i64 % ; CHECK: ## %bb.0: ## %entry ; CHECK-NEXT: movabsq $-281474976710654, %rax ## imm = 0xFFFF000000000002 ; CHECK-NEXT: testq %rax, %rdi -; CHECK-NEXT: jne LBB0_7 +; CHECK-NEXT: jne LBB0_6 ; CHECK-NEXT: ## %bb.1: ## %bb1 ; CHECK-NEXT: testq %rax, %rsi -; CHECK-NEXT: jne LBB0_7 +; CHECK-NEXT: jne LBB0_6 ; CHECK-NEXT: ## %bb.2: ## %bb2 ; CHECK-NEXT: testq %rax, %rdx -; CHECK-NEXT: jne LBB0_7 +; CHECK-NEXT: jne LBB0_6 ; CHECK-NEXT: ## %bb.3: ## %bb3 ; CHECK-NEXT: testq %rax, %rcx -; CHECK-NEXT: jne LBB0_7 +; CHECK-NEXT: jne LBB0_6 ; CHECK-NEXT: ## %bb.4: ## %bb4 ; CHECK-NEXT: leaq 1(%rax), %rcx ; CHECK-NEXT: testq %rcx, %r8 -; CHECK-NEXT: jne LBB0_7 +; CHECK-NEXT: jne LBB0_6 ; CHECK-NEXT: ## %bb.5: ## %bb5 ; CHECK-NEXT: addq $2, %rax ; CHECK-NEXT: andq %rax, %r9 -; CHECK-NEXT: je LBB0_6 -; CHECK-NEXT: LBB0_7: ## %fail +; CHECK-NEXT: je LBB0_7 +; CHECK-NEXT: LBB0_6: ## %fail ; CHECK-NEXT: movq $-1, %rax ; CHECK-NEXT: retq -; CHECK-NEXT: LBB0_6: ## %bb6 +; CHECK-NEXT: LBB0_7: ## %bb6 ; CHECK-NEXT: movq %r9, %rax ; CHECK-NEXT: retq entry: diff --git a/llvm/test/CodeGen/X86/large-pic-jump-table.ll b/llvm/test/CodeGen/X86/large-pic-jump-table.ll index 89e8521e700a0..2bde3c64ec4db 100644 --- a/llvm/test/CodeGen/X86/large-pic-jump-table.ll +++ b/llvm/test/CodeGen/X86/large-pic-jump-table.ll @@ -33,7 +33,7 @@ bb4: ; CHECK-NEXT: jmpq *[[R2]] ; CHECK: .LJTI0_0: -; CHECK-NEXT: .quad .LBB0_2-.LJTI0_0 -; CHECK-NEXT: .quad .LBB0_3-.LJTI0_0 -; CHECK-NEXT: .quad .LBB0_4-.LJTI0_0 -; CHECK-NEXT: .quad .LBB0_5-.LJTI0_0 +; CHECK-NEXT: .quad .LBB0_{{[0-9]+}}-.LJTI0_0 +; CHECK-NEXT: .quad .LBB0_{{[0-9]+}}-.LJTI0_0 +; CHECK-NEXT: .quad .LBB0_{{[0-9]+}}-.LJTI0_0 +; CHECK-NEXT: .quad .LBB0_{{[0-9]+}}-.LJTI0_0 diff --git a/llvm/test/CodeGen/X86/lea-opt-memop-check-2.ll b/llvm/test/CodeGen/X86/lea-opt-memop-check-2.ll index eed26c0901a49..e8d77c6260223 100644 --- a/llvm/test/CodeGen/X86/lea-opt-memop-check-2.ll +++ b/llvm/test/CodeGen/X86/lea-opt-memop-check-2.ll @@ -11,11 +11,11 @@ define i32 @test() nounwind optsize { %r = tail call i32 @llvm.eh.sjlj.setjmp(ptr @buf) ret i32 %r ; CHECK-LABEL: test: -; CHECK: leaq .LBB0_3(%rip), %r[[REG:[a-z]+]] +; CHECK: leaq .LBB0_2(%rip), %r[[REG:[a-z]+]] ; CHECK: movq %r[[REG]], buf+8(%rip) -; CHECK: #EH_SjLj_Setup .LBB0_3 +; CHECK: #EH_SjLj_Setup .LBB0_2 ; CHECK: xorl %e[[REG]], %e[[REG]] -; CHECK: jmp .LBB0_2 -; CHECK-LABEL: .LBB0_3: # Block address taken -; CHECK-LABEL: .LBB0_2: +; CHECK: jmp .LBB0_3 +; CHECK-LABEL: .LBB0_2: # Block address taken +; CHECK-LABEL: .LBB0_3: } diff --git a/llvm/test/CodeGen/X86/legalize-shift-64.ll b/llvm/test/CodeGen/X86/legalize-shift-64.ll index 53208de7ea27e..bd6ea99a5db81 100644 --- a/llvm/test/CodeGen/X86/legalize-shift-64.ll +++ b/llvm/test/CodeGen/X86/legalize-shift-64.ll @@ -145,13 +145,13 @@ define i32 @test6() { ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB5_3 +; CHECK-NEXT: jne .LBB5_2 ; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: movl $1, %eax -; CHECK-NEXT: jmp .LBB5_2 -; CHECK-NEXT: .LBB5_3: # %if.end +; CHECK-NEXT: jmp .LBB5_3 +; CHECK-NEXT: .LBB5_2: # %if.end ; CHECK-NEXT: xorl %eax, %eax -; CHECK-NEXT: .LBB5_2: # %if.then +; CHECK-NEXT: .LBB5_3: # %if.then ; CHECK-NEXT: movl %ebp, %esp ; CHECK-NEXT: popl %ebp ; CHECK-NEXT: .cfi_def_cfa %esp, 4 diff --git a/llvm/test/CodeGen/X86/lifetime-alias.ll b/llvm/test/CodeGen/X86/lifetime-alias.ll index 22e350cb4e0af..9deba89d94bbb 100644 --- a/llvm/test/CodeGen/X86/lifetime-alias.ll +++ b/llvm/test/CodeGen/X86/lifetime-alias.ll @@ -74,11 +74,11 @@ define i8 @main() local_unnamed_addr #0 personality ptr @__gxx_personality_v0 { ; CHECK-NEXT: leaq -{{[0-9]+}}(%rsp), %rax ; CHECK-NEXT: movq %rax, do_not_optimize(%rip) ; CHECK-NEXT: cmpb $0, -{{[0-9]+}}(%rsp) -; CHECK-NEXT: jns .LBB0_1 -; CHECK-NEXT: # %bb.2: # %_ZNSt3__312basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEED2Ev.exit50 +; CHECK-NEXT: jns .LBB0_2 +; CHECK-NEXT: # %bb.1: # %_ZNSt3__312basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEED2Ev.exit50 ; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rax ; CHECK-NEXT: jmp .LBB0_3 -; CHECK-NEXT: .LBB0_1: +; CHECK-NEXT: .LBB0_2: ; CHECK-NEXT: leaq -{{[0-9]+}}(%rsp), %rax ; CHECK-NEXT: .LBB0_3: # %_ZNSt3__312basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEED2Ev.exit50 ; CHECK-NEXT: movzbl 16(%rax), %eax diff --git a/llvm/test/CodeGen/X86/load-local-v3i1.ll b/llvm/test/CodeGen/X86/load-local-v3i1.ll index 52e0eb826d143..2899c2d665571 100644 --- a/llvm/test/CodeGen/X86/load-local-v3i1.ll +++ b/llvm/test/CodeGen/X86/load-local-v3i1.ll @@ -24,24 +24,24 @@ define <3 x i32> @masked_load_v3(ptr addrspace(1), <3 x i1>) { ; CHECK-NEXT: orb %dl, %cl ; CHECK-NEXT: testb $1, %cl ; CHECK-NEXT: # implicit-def: $xmm0 -; CHECK-NEXT: jne .LBB0_1 -; CHECK-NEXT: # %bb.2: # %else +; CHECK-NEXT: jne .LBB0_4 +; CHECK-NEXT: # %bb.1: # %else ; CHECK-NEXT: testb $2, %cl -; CHECK-NEXT: jne .LBB0_3 -; CHECK-NEXT: .LBB0_4: # %else2 -; CHECK-NEXT: testb $4, %cl ; CHECK-NEXT: jne .LBB0_5 -; CHECK-NEXT: .LBB0_6: # %else5 +; CHECK-NEXT: .LBB0_2: # %else2 +; CHECK-NEXT: testb $4, %cl +; CHECK-NEXT: jne .LBB0_6 +; CHECK-NEXT: .LBB0_3: # %else5 ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB0_1: # %cond.load +; CHECK-NEXT: .LBB0_4: # %cond.load ; CHECK-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-NEXT: testb $2, %cl -; CHECK-NEXT: je .LBB0_4 -; CHECK-NEXT: .LBB0_3: # %cond.load1 +; CHECK-NEXT: je .LBB0_2 +; CHECK-NEXT: .LBB0_5: # %cond.load1 ; CHECK-NEXT: pinsrd $1, 4(%rdi), %xmm0 ; CHECK-NEXT: testb $4, %cl -; CHECK-NEXT: je .LBB0_6 -; CHECK-NEXT: .LBB0_5: # %cond.load4 +; CHECK-NEXT: je .LBB0_3 +; CHECK-NEXT: .LBB0_6: # %cond.load4 ; CHECK-NEXT: pinsrd $2, 8(%rdi), %xmm0 ; CHECK-NEXT: retq entry: @@ -60,24 +60,24 @@ define void @masked_store4_v3(<3 x i32>, ptr addrspace(1), <3 x i1>) { ; CHECK-NEXT: shlb $2, %cl ; CHECK-NEXT: orb %dl, %cl ; CHECK-NEXT: testb $1, %cl -; CHECK-NEXT: jne .LBB1_1 -; CHECK-NEXT: # %bb.2: # %else +; CHECK-NEXT: jne .LBB1_4 +; CHECK-NEXT: # %bb.1: # %else ; CHECK-NEXT: testb $2, %cl -; CHECK-NEXT: jne .LBB1_3 -; CHECK-NEXT: .LBB1_4: # %else2 -; CHECK-NEXT: testb $4, %cl ; CHECK-NEXT: jne .LBB1_5 -; CHECK-NEXT: .LBB1_6: # %else4 +; CHECK-NEXT: .LBB1_2: # %else2 +; CHECK-NEXT: testb $4, %cl +; CHECK-NEXT: jne .LBB1_6 +; CHECK-NEXT: .LBB1_3: # %else4 ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB1_1: # %cond.store +; CHECK-NEXT: .LBB1_4: # %cond.store ; CHECK-NEXT: movss %xmm0, (%rdi) ; CHECK-NEXT: testb $2, %cl -; CHECK-NEXT: je .LBB1_4 -; CHECK-NEXT: .LBB1_3: # %cond.store1 +; CHECK-NEXT: je .LBB1_2 +; CHECK-NEXT: .LBB1_5: # %cond.store1 ; CHECK-NEXT: extractps $1, %xmm0, 4(%rdi) ; CHECK-NEXT: testb $4, %cl -; CHECK-NEXT: je .LBB1_6 -; CHECK-NEXT: .LBB1_5: # %cond.store3 +; CHECK-NEXT: je .LBB1_3 +; CHECK-NEXT: .LBB1_6: # %cond.store3 ; CHECK-NEXT: extractps $2, %xmm0, 8(%rdi) ; CHECK-NEXT: retq entry: diff --git a/llvm/test/CodeGen/X86/loop-blocks.ll b/llvm/test/CodeGen/X86/loop-blocks.ll index e970061c0cf70..6c448a3920933 100644 --- a/llvm/test/CodeGen/X86/loop-blocks.ll +++ b/llvm/test/CodeGen/X86/loop-blocks.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -asm-verbose=false | FileCheck %s +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s ; These tests check for loop branching structure, and that the loop align ; directive is placed in the expected place. @@ -6,17 +7,25 @@ ; CodeGen should insert a branch into the middle of the loop in ; order to avoid a branch within the loop. -; CHECK-LABEL: simple: -; CHECK: align -; CHECK-NEXT: .LBB0_1: -; CHECK-NEXT: callq loop_header -; CHECK: js .LBB0_3 -; CHECK-NEXT: callq loop_latch -; CHECK-NEXT: jmp .LBB0_1 -; CHECK-NEXT: .LBB0_3: -; CHECK-NEXT: callq exit - define void @simple() nounwind { +; CHECK-LABEL: simple: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: .p2align 4 +; CHECK-NEXT: .LBB0_1: # %loop +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: callq loop_header@PLT +; CHECK-NEXT: callq get@PLT +; CHECK-NEXT: testl %eax, %eax +; CHECK-NEXT: js .LBB0_3 +; CHECK-NEXT: # %bb.2: # %bb +; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: callq loop_latch@PLT +; CHECK-NEXT: jmp .LBB0_1 +; CHECK-NEXT: .LBB0_3: # %done +; CHECK-NEXT: callq exit@PLT +; CHECK-NEXT: popq %rax +; CHECK-NEXT: retq entry: br label %loop @@ -38,15 +47,30 @@ done: ; CodeGen should move block_a to the top of the loop so that it ; falls through into the loop, avoiding a branch within the loop. -; CHECK-LABEL: slightly_more_involved: -; CHECK: jmp .LBB1_1 -; CHECK-NEXT: align -; CHECK-NEXT: .LBB1_4: -; CHECK-NEXT: callq bar99 -; CHECK-NEXT: .LBB1_1: -; CHECK-NEXT: callq body - define void @slightly_more_involved() nounwind { +; CHECK-LABEL: slightly_more_involved: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: jmp .LBB1_2 +; CHECK-NEXT: .p2align 4 +; CHECK-NEXT: .LBB1_1: # %block_a +; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1 +; CHECK-NEXT: callq bar99@PLT +; CHECK-NEXT: .LBB1_2: # %loop +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: callq body@PLT +; CHECK-NEXT: callq get@PLT +; CHECK-NEXT: cmpl $2, %eax +; CHECK-NEXT: jl .LBB1_1 +; CHECK-NEXT: # %bb.3: # %bb +; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1 +; CHECK-NEXT: callq get@PLT +; CHECK-NEXT: cmpl $99, %eax +; CHECK-NEXT: jge .LBB1_2 +; CHECK-NEXT: # %bb.4: # %exit +; CHECK-NEXT: callq exit@PLT +; CHECK-NEXT: popq %rax +; CHECK-NEXT: retq entry: br label %loop @@ -74,29 +98,44 @@ exit: ; fallthrough edges which should be preserved. ; "callq block_a_merge_func" is tail duped. -; CHECK-LABEL: yet_more_involved: -; CHECK: jmp .LBB2_1 -; CHECK-NEXT: align - -; CHECK: .LBB2_1: -; CHECK-NEXT: callq body -; CHECK-NEXT: callq get -; CHECK-NEXT: cmpl $2, %eax -; CHECK-NEXT: jge .LBB2_2 -; CHECK-NEXT: callq bar99 -; CHECK-NEXT: callq get -; CHECK-NEXT: cmpl $2999, %eax -; CHECK-NEXT: jg .LBB2_6 -; CHECK-NEXT: callq block_a_true_func -; CHECK-NEXT: callq block_a_merge_func -; CHECK-NEXT: jmp .LBB2_1 -; CHECK-NEXT: align -; CHECK-NEXT: .LBB2_6: -; CHECK-NEXT: callq block_a_false_func -; CHECK-NEXT: callq block_a_merge_func -; CHECK-NEXT: jmp .LBB2_1 - define void @yet_more_involved() nounwind { +; CHECK-LABEL: yet_more_involved: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: jmp .LBB2_2 +; CHECK-NEXT: .p2align 4 +; CHECK-NEXT: .LBB2_1: # %bb +; CHECK-NEXT: # in Loop: Header=BB2_2 Depth=1 +; CHECK-NEXT: callq get@PLT +; CHECK-NEXT: cmpl $99, %eax +; CHECK-NEXT: jl .LBB2_6 +; CHECK-NEXT: .LBB2_2: # %loop +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: callq body@PLT +; CHECK-NEXT: callq get@PLT +; CHECK-NEXT: cmpl $2, %eax +; CHECK-NEXT: jge .LBB2_1 +; CHECK-NEXT: # %bb.3: # %block_a +; CHECK-NEXT: # in Loop: Header=BB2_2 Depth=1 +; CHECK-NEXT: callq bar99@PLT +; CHECK-NEXT: callq get@PLT +; CHECK-NEXT: cmpl $2999, %eax # imm = 0xBB7 +; CHECK-NEXT: jg .LBB2_5 +; CHECK-NEXT: # %bb.4: # %block_a_true +; CHECK-NEXT: # in Loop: Header=BB2_2 Depth=1 +; CHECK-NEXT: callq block_a_true_func@PLT +; CHECK-NEXT: callq block_a_merge_func@PLT +; CHECK-NEXT: jmp .LBB2_2 +; CHECK-NEXT: .p2align 4 +; CHECK-NEXT: .LBB2_5: # %block_a_false +; CHECK-NEXT: # in Loop: Header=BB2_2 Depth=1 +; CHECK-NEXT: callq block_a_false_func@PLT +; CHECK-NEXT: callq block_a_merge_func@PLT +; CHECK-NEXT: jmp .LBB2_2 +; CHECK-NEXT: .LBB2_6: # %exit +; CHECK-NEXT: callq exit@PLT +; CHECK-NEXT: popq %rax +; CHECK-NEXT: retq entry: br label %loop @@ -138,29 +177,53 @@ exit: ; conveniently fit anywhere so that they are at least contiguous with the ; loop. -; CHECK-LABEL: cfg_islands: -; CHECK: jmp .LBB3_1 -; CHECK-NEXT: align -; CHECK-NEXT: .LBB3_7: -; CHECK-NEXT: callq bar100 -; CHECK-NEXT: .LBB3_1: -; CHECK-NEXT: callq loop_header -; CHECK: jl .LBB3_7 -; CHECK: jge .LBB3_3 -; CHECK-NEXT: callq bar101 -; CHECK-NEXT: jmp .LBB3_1 -; CHECK-NEXT: align -; CHECK-NEXT: .LBB3_3: -; CHECK: jge .LBB3_4 -; CHECK-NEXT: callq bar102 -; CHECK-NEXT: jmp .LBB3_1 -; CHECK-NEXT: .LBB3_4: -; CHECK: jl .LBB3_6 -; CHECK-NEXT: callq loop_latch -; CHECK-NEXT: jmp .LBB3_1 -; CHECK-NEXT: .LBB3_6: - define void @cfg_islands() nounwind { +; CHECK-LABEL: cfg_islands: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: jmp .LBB3_2 +; CHECK-NEXT: .p2align 4 +; CHECK-NEXT: .LBB3_1: # %block100 +; CHECK-NEXT: # in Loop: Header=BB3_2 Depth=1 +; CHECK-NEXT: callq bar100@PLT +; CHECK-NEXT: .LBB3_2: # %loop +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: callq loop_header@PLT +; CHECK-NEXT: callq get@PLT +; CHECK-NEXT: cmpl $100, %eax +; CHECK-NEXT: jl .LBB3_1 +; CHECK-NEXT: # %bb.3: # %bb +; CHECK-NEXT: # in Loop: Header=BB3_2 Depth=1 +; CHECK-NEXT: callq get@PLT +; CHECK-NEXT: cmpl $101, %eax +; CHECK-NEXT: jge .LBB3_5 +; CHECK-NEXT: # %bb.4: # %block101 +; CHECK-NEXT: # in Loop: Header=BB3_2 Depth=1 +; CHECK-NEXT: callq bar101@PLT +; CHECK-NEXT: jmp .LBB3_2 +; CHECK-NEXT: .p2align 4 +; CHECK-NEXT: .LBB3_5: # %bb1 +; CHECK-NEXT: # in Loop: Header=BB3_2 Depth=1 +; CHECK-NEXT: callq get@PLT +; CHECK-NEXT: cmpl $102, %eax +; CHECK-NEXT: jge .LBB3_7 +; CHECK-NEXT: # %bb.6: # %block102 +; CHECK-NEXT: # in Loop: Header=BB3_2 Depth=1 +; CHECK-NEXT: callq bar102@PLT +; CHECK-NEXT: jmp .LBB3_2 +; CHECK-NEXT: .LBB3_7: # %bb2 +; CHECK-NEXT: # in Loop: Header=BB3_2 Depth=1 +; CHECK-NEXT: callq get@PLT +; CHECK-NEXT: cmpl $103, %eax +; CHECK-NEXT: jl .LBB3_9 +; CHECK-NEXT: # %bb.8: # %bb3 +; CHECK-NEXT: # in Loop: Header=BB3_2 Depth=1 +; CHECK-NEXT: callq loop_latch@PLT +; CHECK-NEXT: jmp .LBB3_2 +; CHECK-NEXT: .LBB3_9: # %exit +; CHECK-NEXT: callq exit@PLT +; CHECK-NEXT: popq %rax +; CHECK-NEXT: retq entry: br label %loop @@ -206,16 +269,24 @@ block102: br label %loop } -; CHECK-LABEL: check_minsize: -; CHECK-NOT: align -; CHECK: .LBB4_1: -; CHECK-NEXT: callq loop_header -; CHECK: callq loop_latch -; CHECK: .LBB4_3: -; CHECK: callq exit - - define void @check_minsize() minsize nounwind { +; CHECK-LABEL: check_minsize: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: .LBB4_1: # %loop +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: callq loop_header@PLT +; CHECK-NEXT: callq get@PLT +; CHECK-NEXT: testl %eax, %eax +; CHECK-NEXT: js .LBB4_3 +; CHECK-NEXT: # %bb.2: # %bb +; CHECK-NEXT: # in Loop: Header=BB4_1 Depth=1 +; CHECK-NEXT: callq loop_latch@PLT +; CHECK-NEXT: jmp .LBB4_1 +; CHECK-NEXT: .LBB4_3: # %done +; CHECK-NEXT: callq exit@PLT +; CHECK-NEXT: popq %rax +; CHECK-NEXT: retq entry: br label %loop @@ -238,12 +309,31 @@ done: ; The difference is that when optimising for size, we do not want ; to see this reordering. -; CHECK-LABEL: slightly_more_involved_2: -; CHECK-NOT: jmp .LBB5_1 -; CHECK: .LBB5_1: -; CHECK-NEXT: callq body - define void @slightly_more_involved_2() #0 { +; CHECK-LABEL: slightly_more_involved_2: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .LBB5_1: # %loop +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: callq body@PLT +; CHECK-NEXT: callq get@PLT +; CHECK-NEXT: cmpl $2, %eax +; CHECK-NEXT: jge .LBB5_3 +; CHECK-NEXT: # %bb.2: # %block_a +; CHECK-NEXT: # in Loop: Header=BB5_1 Depth=1 +; CHECK-NEXT: callq bar99@PLT +; CHECK-NEXT: jmp .LBB5_1 +; CHECK-NEXT: .LBB5_3: # %bb +; CHECK-NEXT: # in Loop: Header=BB5_1 Depth=1 +; CHECK-NEXT: callq get@PLT +; CHECK-NEXT: cmpl $99, %eax +; CHECK-NEXT: jge .LBB5_1 +; CHECK-NEXT: # %bb.4: # %exit +; CHECK-NEXT: callq exit@PLT +; CHECK-NEXT: popq %rax +; CHECK-NEXT: .cfi_def_cfa_offset 8 +; CHECK-NEXT: retq entry: br label %loop @@ -269,12 +359,31 @@ exit: attributes #0 = { minsize norecurse nounwind optsize readnone uwtable } -; CHECK-LABEL: slightly_more_involved_2_pgso: -; CHECK-NOT: jmp .LBB6_1 -; CHECK: .LBB6_1: -; CHECK-NEXT: callq body - define void @slightly_more_involved_2_pgso() norecurse nounwind readnone uwtable !prof !14 { +; CHECK-LABEL: slightly_more_involved_2_pgso: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .LBB6_1: # %loop +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: callq body@PLT +; CHECK-NEXT: callq get@PLT +; CHECK-NEXT: cmpl $2, %eax +; CHECK-NEXT: jge .LBB6_3 +; CHECK-NEXT: # %bb.2: # %block_a +; CHECK-NEXT: # in Loop: Header=BB6_1 Depth=1 +; CHECK-NEXT: callq bar99@PLT +; CHECK-NEXT: jmp .LBB6_1 +; CHECK-NEXT: .LBB6_3: # %bb +; CHECK-NEXT: # in Loop: Header=BB6_1 Depth=1 +; CHECK-NEXT: callq get@PLT +; CHECK-NEXT: cmpl $99, %eax +; CHECK-NEXT: jge .LBB6_1 +; CHECK-NEXT: # %bb.4: # %exit +; CHECK-NEXT: callq exit@PLT +; CHECK-NEXT: popq %rax +; CHECK-NEXT: .cfi_def_cfa_offset 8 +; CHECK-NEXT: retq entry: br label %loop diff --git a/llvm/test/CodeGen/X86/loop-search.ll b/llvm/test/CodeGen/X86/loop-search.ll index 0d5f97d21fb3a..032233bf0552a 100644 --- a/llvm/test/CodeGen/X86/loop-search.ll +++ b/llvm/test/CodeGen/X86/loop-search.ll @@ -8,7 +8,7 @@ define zeroext i1 @search(i32 %needle, ptr nocapture readonly %haystack, i32 %co ; CHECK-LABEL: search: ; CHECK: ## %bb.0: ## %entry ; CHECK-NEXT: testl %edx, %edx -; CHECK-NEXT: jle LBB0_5 +; CHECK-NEXT: jle LBB0_4 ; CHECK-NEXT: ## %bb.1: ## %for.body.preheader ; CHECK-NEXT: movslq %edx, %rax ; CHECK-NEXT: xorl %ecx, %ecx @@ -16,17 +16,17 @@ define zeroext i1 @search(i32 %needle, ptr nocapture readonly %haystack, i32 %co ; CHECK-NEXT: LBB0_2: ## %for.body ; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: cmpl %edi, (%rsi,%rcx,4) -; CHECK-NEXT: je LBB0_6 +; CHECK-NEXT: je LBB0_5 ; CHECK-NEXT: ## %bb.3: ## %for.cond ; CHECK-NEXT: ## in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: incq %rcx ; CHECK-NEXT: cmpq %rax, %rcx ; CHECK-NEXT: jl LBB0_2 -; CHECK-NEXT: LBB0_5: +; CHECK-NEXT: LBB0_4: ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: ## kill: def $al killed $al killed $eax ; CHECK-NEXT: retq -; CHECK-NEXT: LBB0_6: +; CHECK-NEXT: LBB0_5: ; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: ## kill: def $al killed $al killed $eax ; CHECK-NEXT: retq diff --git a/llvm/test/CodeGen/X86/loop-strength-reduce7.ll b/llvm/test/CodeGen/X86/loop-strength-reduce7.ll index 11473bacc56cf..43227101a1dea 100644 --- a/llvm/test/CodeGen/X86/loop-strength-reduce7.ll +++ b/llvm/test/CodeGen/X86/loop-strength-reduce7.ll @@ -14,24 +14,24 @@ define fastcc void @outer_loop(ptr nocapture %gfp, ptr nocapture %xr, i32 %targ_ ; CHECK-NEXT: movl $88, %eax ; CHECK-NEXT: movl $168, %ecx ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: LBB0_2: ## %bb28.i37 +; CHECK-NEXT: LBB0_1: ## %bb28.i37 ; CHECK-NEXT: ## =>This Loop Header: Depth=1 -; CHECK-NEXT: ## Child Loop BB0_3 Depth 2 +; CHECK-NEXT: ## Child Loop BB0_2 Depth 2 ; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: movl %eax, %esi ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: LBB0_3: ## %bb29.i38 -; CHECK-NEXT: ## Parent Loop BB0_2 Depth=1 +; CHECK-NEXT: LBB0_2: ## %bb29.i38 +; CHECK-NEXT: ## Parent Loop BB0_1 Depth=1 ; CHECK-NEXT: ## => This Inner Loop Header: Depth=2 ; CHECK-NEXT: incl %edx ; CHECK-NEXT: addl $12, %esi ; CHECK-NEXT: cmpl $11, %edx -; CHECK-NEXT: jbe LBB0_3 -; CHECK-NEXT: ## %bb.1: ## %bb28.i37.loopexit -; CHECK-NEXT: ## in Loop: Header=BB0_2 Depth=1 +; CHECK-NEXT: jbe LBB0_2 +; CHECK-NEXT: ## %bb.3: ## %bb28.i37.loopexit +; CHECK-NEXT: ## in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: addl $4, %eax ; CHECK-NEXT: addl $168, %ecx -; CHECK-NEXT: jmp LBB0_2 +; CHECK-NEXT: jmp LBB0_1 entry: br label %bb4 diff --git a/llvm/test/CodeGen/X86/lrshrink-debug.ll b/llvm/test/CodeGen/X86/lrshrink-debug.ll index dd52968529902..6ab001fb670fd 100755 --- a/llvm/test/CodeGen/X86/lrshrink-debug.ll +++ b/llvm/test/CodeGen/X86/lrshrink-debug.ll @@ -23,29 +23,29 @@ define noundef i32 @test(i1 %tobool1.not, i32 %sh.012, i1 %cmp, i64 %sh_prom, i6 ; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %edx ; CHECK-NEXT: movb {{[0-9]+}}(%esp), %dh ; CHECK-NEXT: xorl %edi, %edi -; CHECK-NEXT: jmp .LBB0_1 +; CHECK-NEXT: jmp .LBB0_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_4: # %if.end -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: .LBB0_1: # %if.end +; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: orl %ecx, %ebx ; CHECK-NEXT: orl %eax, %ebp ; CHECK-NEXT: movl %ebx, %esi ; CHECK-NEXT: movl %ebp, %edi -; CHECK-NEXT: .LBB0_1: # %for.body +; CHECK-NEXT: .LBB0_2: # %for.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: testb $1, %dh -; CHECK-NEXT: je .LBB0_1 -; CHECK-NEXT: # %bb.2: # %if.end -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: je .LBB0_2 +; CHECK-NEXT: # %bb.3: # %if.end +; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: xorl %ebx, %ebx ; CHECK-NEXT: testb $1, %dl ; CHECK-NEXT: movl $0, %ebp -; CHECK-NEXT: jne .LBB0_4 -; CHECK-NEXT: # %bb.3: # %if.end -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: jne .LBB0_1 +; CHECK-NEXT: # %bb.4: # %if.end +; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: movl %esi, %ebx ; CHECK-NEXT: movl %edi, %ebp -; CHECK-NEXT: jmp .LBB0_4 +; CHECK-NEXT: jmp .LBB0_1 entry: br label %for.body diff --git a/llvm/test/CodeGen/X86/lrshrink-ehpad-phis.ll b/llvm/test/CodeGen/X86/lrshrink-ehpad-phis.ll index b9afb99697354..645aac6a966b1 100755 --- a/llvm/test/CodeGen/X86/lrshrink-ehpad-phis.ll +++ b/llvm/test/CodeGen/X86/lrshrink-ehpad-phis.ll @@ -36,7 +36,7 @@ define void @test() personality ptr @__gxx_personality_v0 { ; CHECK-NEXT: .cfi_offset %rbp, -16 ; CHECK-NEXT: movq external_bool@GOTPCREL(%rip), %rax ; CHECK-NEXT: cmpb $1, (%rax) -; CHECK-NEXT: jne .LBB0_3 +; CHECK-NEXT: jne .LBB0_2 ; CHECK-NEXT: # %bb.1: # %branchA ; CHECK-NEXT: movq externalA@GOTPCREL(%rip), %rax ; CHECK-NEXT: movl (%rax), %eax @@ -46,11 +46,11 @@ define void @test() personality ptr @__gxx_personality_v0 { ; CHECK-NEXT: movl %eax, (%rsp) # 4-byte Spill ; CHECK-NEXT: #APP ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: .Ltmp2: +; CHECK-NEXT: .Ltmp2: # EH_LABEL ; CHECK-NEXT: callq maythrow@PLT -; CHECK-NEXT: .Ltmp3: -; CHECK-NEXT: jmp .LBB0_4 -; CHECK-NEXT: .LBB0_3: # %branchB +; CHECK-NEXT: .Ltmp3: # EH_LABEL +; CHECK-NEXT: jmp .LBB0_3 +; CHECK-NEXT: .LBB0_2: # %branchB ; CHECK-NEXT: movq externalB@GOTPCREL(%rip), %rax ; CHECK-NEXT: movl (%rax), %eax ; CHECK-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill @@ -59,10 +59,10 @@ define void @test() personality ptr @__gxx_personality_v0 { ; CHECK-NEXT: movl %eax, (%rsp) # 4-byte Spill ; CHECK-NEXT: #APP ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: .Ltmp0: +; CHECK-NEXT: .Ltmp0: # EH_LABEL ; CHECK-NEXT: callq maythrow@PLT -; CHECK-NEXT: .Ltmp1: -; CHECK-NEXT: .LBB0_4: # %end +; CHECK-NEXT: .Ltmp1: # EH_LABEL +; CHECK-NEXT: .LBB0_3: # %end ; CHECK-NEXT: addq $8, %rsp ; CHECK-NEXT: .cfi_def_cfa_offset 56 ; CHECK-NEXT: popq %rbx @@ -78,9 +78,9 @@ define void @test() personality ptr @__gxx_personality_v0 { ; CHECK-NEXT: popq %rbp ; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB0_2: # %lpad +; CHECK-NEXT: .LBB0_4: # %lpad ; CHECK-NEXT: .cfi_def_cfa_offset 64 -; CHECK-NEXT: .Ltmp4: +; CHECK-NEXT: .Ltmp4: # EH_LABEL ; CHECK-NEXT: movq %rax, %rbx ; CHECK-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edi # 4-byte Reload ; CHECK-NEXT: addl (%rsp), %edi # 4-byte Folded Reload diff --git a/llvm/test/CodeGen/X86/lsr-addrecloops.ll b/llvm/test/CodeGen/X86/lsr-addrecloops.ll index 98c8f587784c2..2ca888998516f 100644 --- a/llvm/test/CodeGen/X86/lsr-addrecloops.ll +++ b/llvm/test/CodeGen/X86/lsr-addrecloops.ll @@ -15,39 +15,39 @@ define void @in4dob_(ptr nocapture writeonly %0, ptr nocapture readonly %1, ptr ; CHECK-NEXT: movl $1, %r10d ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0 -; CHECK-NEXT: jmp .LBB0_1 +; CHECK-NEXT: jmp .LBB0_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_20: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: .LBB0_1: # in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: incq %r10 ; CHECK-NEXT: addq %r9, %rax ; CHECK-NEXT: cmpq %r10, %rcx -; CHECK-NEXT: je .LBB0_18 -; CHECK-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: je .LBB0_20 +; CHECK-NEXT: .LBB0_2: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; CHECK-NEXT: vucomiss %xmm0, %xmm1 -; CHECK-NEXT: jne .LBB0_20 -; CHECK-NEXT: jp .LBB0_20 -; CHECK-NEXT: # %bb.2: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: jne .LBB0_1 +; CHECK-NEXT: jp .LBB0_1 +; CHECK-NEXT: # %bb.3: # in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; CHECK-NEXT: vucomiss %xmm0, %xmm1 -; CHECK-NEXT: jne .LBB0_20 -; CHECK-NEXT: jp .LBB0_20 -; CHECK-NEXT: # %bb.3: # %vector.body807.preheader +; CHECK-NEXT: jne .LBB0_1 +; CHECK-NEXT: jp .LBB0_1 +; CHECK-NEXT: # %bb.4: # %vector.body807.preheader ; CHECK-NEXT: leaq 1(%rcx), %rdx ; CHECK-NEXT: movl %edx, %esi ; CHECK-NEXT: andl $7, %esi ; CHECK-NEXT: cmpq $7, %rcx -; CHECK-NEXT: jae .LBB0_5 -; CHECK-NEXT: # %bb.4: +; CHECK-NEXT: jae .LBB0_6 +; CHECK-NEXT: # %bb.5: ; CHECK-NEXT: xorl %r9d, %r9d -; CHECK-NEXT: jmp .LBB0_7 -; CHECK-NEXT: .LBB0_5: # %vector.body807.preheader.new +; CHECK-NEXT: jmp .LBB0_8 +; CHECK-NEXT: .LBB0_6: # %vector.body807.preheader.new ; CHECK-NEXT: movq %rdx, %r10 ; CHECK-NEXT: andq $-8, %r10 ; CHECK-NEXT: xorl %r9d, %r9d ; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_6: # %vector.body807 +; CHECK-NEXT: .LBB0_7: # %vector.body807 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: leaq (%rdi,%r9), %r11 ; CHECK-NEXT: vmovups %ymm0, (%rax,%r11) @@ -60,43 +60,43 @@ define void @in4dob_(ptr nocapture writeonly %0, ptr nocapture readonly %1, ptr ; CHECK-NEXT: vmovups %ymm0, 7(%rax,%r11) ; CHECK-NEXT: addq $8, %r9 ; CHECK-NEXT: cmpq %r9, %r10 -; CHECK-NEXT: jne .LBB0_6 -; CHECK-NEXT: .LBB0_7: # %.lr.ph373.unr-lcssa +; CHECK-NEXT: jne .LBB0_7 +; CHECK-NEXT: .LBB0_8: # %.lr.ph373.unr-lcssa ; CHECK-NEXT: testq %rsi, %rsi -; CHECK-NEXT: je .LBB0_10 -; CHECK-NEXT: # %bb.8: # %vector.body807.epil.preheader +; CHECK-NEXT: je .LBB0_11 +; CHECK-NEXT: # %bb.9: # %vector.body807.epil.preheader ; CHECK-NEXT: addq %rdi, %r9 ; CHECK-NEXT: xorl %r10d, %r10d ; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_9: # %vector.body807.epil +; CHECK-NEXT: .LBB0_10: # %vector.body807.epil ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: leaq (%r9,%r10), %r11 ; CHECK-NEXT: vmovups %ymm0, (%rax,%r11) ; CHECK-NEXT: incq %r10 ; CHECK-NEXT: cmpq %r10, %rsi -; CHECK-NEXT: jne .LBB0_9 -; CHECK-NEXT: .LBB0_10: # %.lr.ph373 +; CHECK-NEXT: jne .LBB0_10 +; CHECK-NEXT: .LBB0_11: # %.lr.ph373 ; CHECK-NEXT: testb $1, %r8b -; CHECK-NEXT: je .LBB0_11 -; CHECK-NEXT: # %bb.19: # %scalar.ph839.preheader +; CHECK-NEXT: je .LBB0_13 +; CHECK-NEXT: # %bb.12: # %scalar.ph839.preheader ; CHECK-NEXT: movl $0, (%rdi) ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB0_11: # %vector.body847.preheader +; CHECK-NEXT: .LBB0_13: # %vector.body847.preheader ; CHECK-NEXT: movl %edx, %esi ; CHECK-NEXT: andl $7, %esi ; CHECK-NEXT: cmpq $7, %rcx -; CHECK-NEXT: jae .LBB0_13 -; CHECK-NEXT: # %bb.12: +; CHECK-NEXT: jae .LBB0_15 +; CHECK-NEXT: # %bb.14: ; CHECK-NEXT: xorl %ecx, %ecx -; CHECK-NEXT: jmp .LBB0_15 -; CHECK-NEXT: .LBB0_13: # %vector.body847.preheader.new +; CHECK-NEXT: jmp .LBB0_17 +; CHECK-NEXT: .LBB0_15: # %vector.body847.preheader.new ; CHECK-NEXT: andq $-8, %rdx ; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_14: # %vector.body847 +; CHECK-NEXT: .LBB0_16: # %vector.body847 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: leaq (%rdi,%rcx), %r8 ; CHECK-NEXT: vmovups %ymm0, 96(%rax,%r8) @@ -109,23 +109,23 @@ define void @in4dob_(ptr nocapture writeonly %0, ptr nocapture readonly %1, ptr ; CHECK-NEXT: vmovups %ymm0, 103(%rax,%r8) ; CHECK-NEXT: addq $8, %rcx ; CHECK-NEXT: cmpq %rcx, %rdx -; CHECK-NEXT: jne .LBB0_14 -; CHECK-NEXT: .LBB0_15: # %common.ret.loopexit.unr-lcssa +; CHECK-NEXT: jne .LBB0_16 +; CHECK-NEXT: .LBB0_17: # %common.ret.loopexit.unr-lcssa ; CHECK-NEXT: testq %rsi, %rsi -; CHECK-NEXT: je .LBB0_18 -; CHECK-NEXT: # %bb.16: # %vector.body847.epil.preheader +; CHECK-NEXT: je .LBB0_20 +; CHECK-NEXT: # %bb.18: # %vector.body847.epil.preheader ; CHECK-NEXT: leaq 96(%rcx,%rdi), %rcx ; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_17: # %vector.body847.epil +; CHECK-NEXT: .LBB0_19: # %vector.body847.epil ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: leaq (%rcx,%rdx), %rdi ; CHECK-NEXT: vmovups %ymm0, (%rax,%rdi) ; CHECK-NEXT: incq %rdx ; CHECK-NEXT: cmpq %rdx, %rsi -; CHECK-NEXT: jne .LBB0_17 -; CHECK-NEXT: .LBB0_18: # %common.ret +; CHECK-NEXT: jne .LBB0_19 +; CHECK-NEXT: .LBB0_20: # %common.ret ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq .preheader263: diff --git a/llvm/test/CodeGen/X86/lvi-hardening-loads.ll b/llvm/test/CodeGen/X86/lvi-hardening-loads.ll index 4ecb1bc31f2a8..dfa16a0ffcbc4 100644 --- a/llvm/test/CodeGen/X86/lvi-hardening-loads.ll +++ b/llvm/test/CodeGen/X86/lvi-hardening-loads.ll @@ -23,7 +23,7 @@ entry: ; X64-NEXT: movl $0, -{{[0-9]+}}(%rsp) ; X64-NEXT: lfence ; X64-NEXT: movl $0, -{{[0-9]+}}(%rsp) -; X64-NEXT: jmp .LBB0_1 +; X64-NEXT: jmp .LBB0_2 ; X64-NOOPT: # %bb.0: # %entry ; X64-NOOPT-NEXT: lfence @@ -41,7 +41,7 @@ for.cond: ; preds = %for.inc, %entry %cmp = icmp slt i32 %0, %1 br i1 %cmp, label %for.body, label %for.end -; X64: .LBB0_1: # %for.cond +; X64: .LBB0_2: # %for.cond ; X64-NEXT: # =>This Inner Loop Header: Depth=1 ; X64-NEXT: movl -{{[0-9]+}}(%rsp), %eax ; X64-ALL-NEXT: lfence @@ -64,8 +64,8 @@ for.body: ; preds = %for.cond %cmp1 = icmp eq i32 %rem, 0 br i1 %cmp1, label %if.then, label %if.end -; X64: # %bb.2: # %for.body -; X64-NEXT: # in Loop: Header=BB0_1 Depth=1 +; X64: # %bb.3: # %for.body +; X64-NEXT: # in Loop: Header=BB0_2 Depth=1 ; X64-NEXT: movl -{{[0-9]+}}(%rsp), %eax ; X64-ALL-NEXT: lfence ; X64-NEXT: movl %eax, %ecx @@ -73,7 +73,7 @@ for.body: ; preds = %for.cond ; X64-NEXT: addl %eax, %ecx ; X64-NEXT: andl $-2, %ecx ; X64-NEXT: cmpl %ecx, %eax -; X64-NEXT: jne .LBB0_4 +; X64-NEXT: jne .LBB0_1 ; X64-NOOPT: # %bb.2: # %for.body ; X64-NOOPT-NEXT: # in Loop: Header=BB0_1 Depth=1 @@ -96,8 +96,8 @@ if.then: ; preds = %for.body store i32 %6, ptr %ret_val, align 4 br label %if.end -; X64: # %bb.3: # %if.then -; X64-NEXT: # in Loop: Header=BB0_1 Depth=1 +; X64: # %bb.4: # %if.then +; X64-NEXT: # in Loop: Header=BB0_2 Depth=1 ; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rax ; X64-NEXT: lfence ; X64-NEXT: movslq -{{[0-9]+}}(%rsp), %rcx @@ -106,7 +106,7 @@ if.then: ; preds = %for.body ; X64-NEXT: lfence ; X64-NEXT: movl (%rax), %eax ; X64-NEXT: movl %eax, -{{[0-9]+}}(%rsp) -; X64-NEXT: jmp .LBB0_4 +; X64-NEXT: jmp .LBB0_1 ; X64-NOOPT: # %bb.3: # %if.then ; X64-NOOPT-NEXT: # in Loop: Header=BB0_1 Depth=1 diff --git a/llvm/test/CodeGen/X86/lzcnt.ll b/llvm/test/CodeGen/X86/lzcnt.ll index b000401973416..86ebb4e76616d 100644 --- a/llvm/test/CodeGen/X86/lzcnt.ll +++ b/llvm/test/CodeGen/X86/lzcnt.ll @@ -79,13 +79,13 @@ define i64 @t4(i64 %x) nounwind { ; X86: # %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: testl %eax, %eax -; X86-NEXT: jne .LBB3_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: jne .LBB3_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: lzcntl {{[0-9]+}}(%esp), %eax ; X86-NEXT: addl $32, %eax ; X86-NEXT: xorl %edx, %edx ; X86-NEXT: retl -; X86-NEXT: .LBB3_1: +; X86-NEXT: .LBB3_2: ; X86-NEXT: lzcntl %eax, %eax ; X86-NEXT: xorl %edx, %edx ; X86-NEXT: retl @@ -172,13 +172,13 @@ define i64 @t8(i64 %x) nounwind { ; X86: # %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: testl %eax, %eax -; X86-NEXT: jne .LBB7_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: jne .LBB7_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: lzcntl {{[0-9]+}}(%esp), %eax ; X86-NEXT: addl $32, %eax ; X86-NEXT: xorl %edx, %edx ; X86-NEXT: retl -; X86-NEXT: .LBB7_1: +; X86-NEXT: .LBB7_2: ; X86-NEXT: lzcntl %eax, %eax ; X86-NEXT: xorl %edx, %edx ; X86-NEXT: retl diff --git a/llvm/test/CodeGen/X86/masked_compressstore.ll b/llvm/test/CodeGen/X86/masked_compressstore.ll index 5296c9d0f0777..e9e44ff4b562b 100644 --- a/llvm/test/CodeGen/X86/masked_compressstore.ll +++ b/llvm/test/CodeGen/X86/masked_compressstore.ll @@ -18,66 +18,66 @@ define void @compressstore_v8f64_v8i1(ptr %base, <8 x double> %V, <8 x i1> %mask ; SSE-NEXT: packsswb %xmm4, %xmm4 ; SSE-NEXT: pmovmskb %xmm4, %eax ; SSE-NEXT: testb $1, %al -; SSE-NEXT: jne LBB0_1 -; SSE-NEXT: ## %bb.2: ## %else +; SSE-NEXT: jne LBB0_9 +; SSE-NEXT: ## %bb.1: ## %else ; SSE-NEXT: testb $2, %al -; SSE-NEXT: jne LBB0_3 -; SSE-NEXT: LBB0_4: ## %else2 +; SSE-NEXT: jne LBB0_10 +; SSE-NEXT: LBB0_2: ## %else2 ; SSE-NEXT: testb $4, %al -; SSE-NEXT: jne LBB0_5 -; SSE-NEXT: LBB0_6: ## %else5 +; SSE-NEXT: jne LBB0_11 +; SSE-NEXT: LBB0_3: ## %else5 ; SSE-NEXT: testb $8, %al -; SSE-NEXT: jne LBB0_7 -; SSE-NEXT: LBB0_8: ## %else8 +; SSE-NEXT: jne LBB0_12 +; SSE-NEXT: LBB0_4: ## %else8 ; SSE-NEXT: testb $16, %al -; SSE-NEXT: jne LBB0_9 -; SSE-NEXT: LBB0_10: ## %else11 +; SSE-NEXT: jne LBB0_13 +; SSE-NEXT: LBB0_5: ## %else11 ; SSE-NEXT: testb $32, %al -; SSE-NEXT: jne LBB0_11 -; SSE-NEXT: LBB0_12: ## %else14 +; SSE-NEXT: jne LBB0_14 +; SSE-NEXT: LBB0_6: ## %else14 ; SSE-NEXT: testb $64, %al -; SSE-NEXT: jne LBB0_13 -; SSE-NEXT: LBB0_14: ## %else17 -; SSE-NEXT: testb $-128, %al ; SSE-NEXT: jne LBB0_15 -; SSE-NEXT: LBB0_16: ## %else20 +; SSE-NEXT: LBB0_7: ## %else17 +; SSE-NEXT: testb $-128, %al +; SSE-NEXT: jne LBB0_16 +; SSE-NEXT: LBB0_8: ## %else20 ; SSE-NEXT: retq -; SSE-NEXT: LBB0_1: ## %cond.store +; SSE-NEXT: LBB0_9: ## %cond.store ; SSE-NEXT: movq %xmm0, (%rdi) ; SSE-NEXT: addq $8, %rdi ; SSE-NEXT: testb $2, %al -; SSE-NEXT: je LBB0_4 -; SSE-NEXT: LBB0_3: ## %cond.store1 +; SSE-NEXT: je LBB0_2 +; SSE-NEXT: LBB0_10: ## %cond.store1 ; SSE-NEXT: movhpd %xmm0, (%rdi) ; SSE-NEXT: addq $8, %rdi ; SSE-NEXT: testb $4, %al -; SSE-NEXT: je LBB0_6 -; SSE-NEXT: LBB0_5: ## %cond.store4 +; SSE-NEXT: je LBB0_3 +; SSE-NEXT: LBB0_11: ## %cond.store4 ; SSE-NEXT: movlps %xmm1, (%rdi) ; SSE-NEXT: addq $8, %rdi ; SSE-NEXT: testb $8, %al -; SSE-NEXT: je LBB0_8 -; SSE-NEXT: LBB0_7: ## %cond.store7 +; SSE-NEXT: je LBB0_4 +; SSE-NEXT: LBB0_12: ## %cond.store7 ; SSE-NEXT: movhps %xmm1, (%rdi) ; SSE-NEXT: addq $8, %rdi ; SSE-NEXT: testb $16, %al -; SSE-NEXT: je LBB0_10 -; SSE-NEXT: LBB0_9: ## %cond.store10 +; SSE-NEXT: je LBB0_5 +; SSE-NEXT: LBB0_13: ## %cond.store10 ; SSE-NEXT: movlps %xmm2, (%rdi) ; SSE-NEXT: addq $8, %rdi ; SSE-NEXT: testb $32, %al -; SSE-NEXT: je LBB0_12 -; SSE-NEXT: LBB0_11: ## %cond.store13 +; SSE-NEXT: je LBB0_6 +; SSE-NEXT: LBB0_14: ## %cond.store13 ; SSE-NEXT: movhps %xmm2, (%rdi) ; SSE-NEXT: addq $8, %rdi ; SSE-NEXT: testb $64, %al -; SSE-NEXT: je LBB0_14 -; SSE-NEXT: LBB0_13: ## %cond.store16 +; SSE-NEXT: je LBB0_7 +; SSE-NEXT: LBB0_15: ## %cond.store16 ; SSE-NEXT: movlps %xmm3, (%rdi) ; SSE-NEXT: addq $8, %rdi ; SSE-NEXT: testb $-128, %al -; SSE-NEXT: je LBB0_16 -; SSE-NEXT: LBB0_15: ## %cond.store19 +; SSE-NEXT: je LBB0_8 +; SSE-NEXT: LBB0_16: ## %cond.store19 ; SSE-NEXT: movhps %xmm3, (%rdi) ; SSE-NEXT: retq ; @@ -100,51 +100,51 @@ define void @compressstore_v8f64_v8i1(ptr %base, <8 x double> %V, <8 x i1> %mask ; AVX1-NEXT: LBB0_4: ## %else2 ; AVX1-NEXT: testb $4, %al ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 -; AVX1-NEXT: jne LBB0_5 -; AVX1-NEXT: ## %bb.6: ## %else5 +; AVX1-NEXT: jne LBB0_12 +; AVX1-NEXT: ## %bb.5: ## %else5 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne LBB0_7 -; AVX1-NEXT: LBB0_8: ## %else8 +; AVX1-NEXT: jne LBB0_13 +; AVX1-NEXT: LBB0_6: ## %else8 ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: jne LBB0_9 -; AVX1-NEXT: LBB0_10: ## %else11 +; AVX1-NEXT: jne LBB0_14 +; AVX1-NEXT: LBB0_7: ## %else11 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je LBB0_12 -; AVX1-NEXT: LBB0_11: ## %cond.store13 +; AVX1-NEXT: je LBB0_9 +; AVX1-NEXT: LBB0_8: ## %cond.store13 ; AVX1-NEXT: vmovhps %xmm1, (%rdi) ; AVX1-NEXT: addq $8, %rdi -; AVX1-NEXT: LBB0_12: ## %else14 +; AVX1-NEXT: LBB0_9: ## %else14 ; AVX1-NEXT: testb $64, %al ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm0 -; AVX1-NEXT: jne LBB0_13 -; AVX1-NEXT: ## %bb.14: ## %else17 -; AVX1-NEXT: testb $-128, %al ; AVX1-NEXT: jne LBB0_15 -; AVX1-NEXT: LBB0_16: ## %else20 +; AVX1-NEXT: ## %bb.10: ## %else17 +; AVX1-NEXT: testb $-128, %al +; AVX1-NEXT: jne LBB0_16 +; AVX1-NEXT: LBB0_11: ## %else20 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: LBB0_5: ## %cond.store4 +; AVX1-NEXT: LBB0_12: ## %cond.store4 ; AVX1-NEXT: vmovlps %xmm0, (%rdi) ; AVX1-NEXT: addq $8, %rdi ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je LBB0_8 -; AVX1-NEXT: LBB0_7: ## %cond.store7 +; AVX1-NEXT: je LBB0_6 +; AVX1-NEXT: LBB0_13: ## %cond.store7 ; AVX1-NEXT: vmovhps %xmm0, (%rdi) ; AVX1-NEXT: addq $8, %rdi ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: je LBB0_10 -; AVX1-NEXT: LBB0_9: ## %cond.store10 +; AVX1-NEXT: je LBB0_7 +; AVX1-NEXT: LBB0_14: ## %cond.store10 ; AVX1-NEXT: vmovlps %xmm1, (%rdi) ; AVX1-NEXT: addq $8, %rdi ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: jne LBB0_11 -; AVX1-NEXT: jmp LBB0_12 -; AVX1-NEXT: LBB0_13: ## %cond.store16 +; AVX1-NEXT: jne LBB0_8 +; AVX1-NEXT: jmp LBB0_9 +; AVX1-NEXT: LBB0_15: ## %cond.store16 ; AVX1-NEXT: vmovlps %xmm0, (%rdi) ; AVX1-NEXT: addq $8, %rdi ; AVX1-NEXT: testb $-128, %al -; AVX1-NEXT: je LBB0_16 -; AVX1-NEXT: LBB0_15: ## %cond.store19 +; AVX1-NEXT: je LBB0_11 +; AVX1-NEXT: LBB0_16: ## %cond.store19 ; AVX1-NEXT: vmovhps %xmm0, (%rdi) ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq @@ -168,51 +168,51 @@ define void @compressstore_v8f64_v8i1(ptr %base, <8 x double> %V, <8 x i1> %mask ; AVX2-NEXT: LBB0_4: ## %else2 ; AVX2-NEXT: testb $4, %al ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0 -; AVX2-NEXT: jne LBB0_5 -; AVX2-NEXT: ## %bb.6: ## %else5 +; AVX2-NEXT: jne LBB0_12 +; AVX2-NEXT: ## %bb.5: ## %else5 ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: jne LBB0_7 -; AVX2-NEXT: LBB0_8: ## %else8 +; AVX2-NEXT: jne LBB0_13 +; AVX2-NEXT: LBB0_6: ## %else8 ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: jne LBB0_9 -; AVX2-NEXT: LBB0_10: ## %else11 +; AVX2-NEXT: jne LBB0_14 +; AVX2-NEXT: LBB0_7: ## %else11 ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: je LBB0_12 -; AVX2-NEXT: LBB0_11: ## %cond.store13 +; AVX2-NEXT: je LBB0_9 +; AVX2-NEXT: LBB0_8: ## %cond.store13 ; AVX2-NEXT: vmovhps %xmm1, (%rdi) ; AVX2-NEXT: addq $8, %rdi -; AVX2-NEXT: LBB0_12: ## %else14 +; AVX2-NEXT: LBB0_9: ## %else14 ; AVX2-NEXT: testb $64, %al ; AVX2-NEXT: vextractf128 $1, %ymm1, %xmm0 -; AVX2-NEXT: jne LBB0_13 -; AVX2-NEXT: ## %bb.14: ## %else17 -; AVX2-NEXT: testb $-128, %al ; AVX2-NEXT: jne LBB0_15 -; AVX2-NEXT: LBB0_16: ## %else20 +; AVX2-NEXT: ## %bb.10: ## %else17 +; AVX2-NEXT: testb $-128, %al +; AVX2-NEXT: jne LBB0_16 +; AVX2-NEXT: LBB0_11: ## %else20 ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; AVX2-NEXT: LBB0_5: ## %cond.store4 +; AVX2-NEXT: LBB0_12: ## %cond.store4 ; AVX2-NEXT: vmovq %xmm0, (%rdi) ; AVX2-NEXT: addq $8, %rdi ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je LBB0_8 -; AVX2-NEXT: LBB0_7: ## %cond.store7 +; AVX2-NEXT: je LBB0_6 +; AVX2-NEXT: LBB0_13: ## %cond.store7 ; AVX2-NEXT: vmovhpd %xmm0, (%rdi) ; AVX2-NEXT: addq $8, %rdi ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: je LBB0_10 -; AVX2-NEXT: LBB0_9: ## %cond.store10 +; AVX2-NEXT: je LBB0_7 +; AVX2-NEXT: LBB0_14: ## %cond.store10 ; AVX2-NEXT: vmovlps %xmm1, (%rdi) ; AVX2-NEXT: addq $8, %rdi ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: jne LBB0_11 -; AVX2-NEXT: jmp LBB0_12 -; AVX2-NEXT: LBB0_13: ## %cond.store16 +; AVX2-NEXT: jne LBB0_8 +; AVX2-NEXT: jmp LBB0_9 +; AVX2-NEXT: LBB0_15: ## %cond.store16 ; AVX2-NEXT: vmovlps %xmm0, (%rdi) ; AVX2-NEXT: addq $8, %rdi ; AVX2-NEXT: testb $-128, %al -; AVX2-NEXT: je LBB0_16 -; AVX2-NEXT: LBB0_15: ## %cond.store19 +; AVX2-NEXT: je LBB0_11 +; AVX2-NEXT: LBB0_16: ## %cond.store19 ; AVX2-NEXT: vmovhps %xmm0, (%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq @@ -253,130 +253,130 @@ define void @compressstore_v16f64_v16i1(ptr %base, <16 x double> %V, <16 x i1> % ; SSE-NEXT: psllw $7, %xmm8 ; SSE-NEXT: pmovmskb %xmm8, %eax ; SSE-NEXT: testb $1, %al -; SSE-NEXT: jne LBB1_1 -; SSE-NEXT: ## %bb.2: ## %else +; SSE-NEXT: jne LBB1_17 +; SSE-NEXT: ## %bb.1: ## %else ; SSE-NEXT: testb $2, %al -; SSE-NEXT: jne LBB1_3 -; SSE-NEXT: LBB1_4: ## %else2 +; SSE-NEXT: jne LBB1_18 +; SSE-NEXT: LBB1_2: ## %else2 ; SSE-NEXT: testb $4, %al -; SSE-NEXT: jne LBB1_5 -; SSE-NEXT: LBB1_6: ## %else5 +; SSE-NEXT: jne LBB1_19 +; SSE-NEXT: LBB1_3: ## %else5 ; SSE-NEXT: testb $8, %al -; SSE-NEXT: jne LBB1_7 -; SSE-NEXT: LBB1_8: ## %else8 +; SSE-NEXT: jne LBB1_20 +; SSE-NEXT: LBB1_4: ## %else8 ; SSE-NEXT: testb $16, %al -; SSE-NEXT: jne LBB1_9 -; SSE-NEXT: LBB1_10: ## %else11 +; SSE-NEXT: jne LBB1_21 +; SSE-NEXT: LBB1_5: ## %else11 ; SSE-NEXT: testb $32, %al -; SSE-NEXT: jne LBB1_11 -; SSE-NEXT: LBB1_12: ## %else14 +; SSE-NEXT: jne LBB1_22 +; SSE-NEXT: LBB1_6: ## %else14 ; SSE-NEXT: testb $64, %al -; SSE-NEXT: jne LBB1_13 -; SSE-NEXT: LBB1_14: ## %else17 +; SSE-NEXT: jne LBB1_23 +; SSE-NEXT: LBB1_7: ## %else17 ; SSE-NEXT: testb %al, %al -; SSE-NEXT: js LBB1_15 -; SSE-NEXT: LBB1_16: ## %else20 +; SSE-NEXT: js LBB1_24 +; SSE-NEXT: LBB1_8: ## %else20 ; SSE-NEXT: testl $256, %eax ## imm = 0x100 -; SSE-NEXT: jne LBB1_17 -; SSE-NEXT: LBB1_18: ## %else23 +; SSE-NEXT: jne LBB1_25 +; SSE-NEXT: LBB1_9: ## %else23 ; SSE-NEXT: testl $512, %eax ## imm = 0x200 -; SSE-NEXT: jne LBB1_19 -; SSE-NEXT: LBB1_20: ## %else26 +; SSE-NEXT: jne LBB1_26 +; SSE-NEXT: LBB1_10: ## %else26 ; SSE-NEXT: testl $1024, %eax ## imm = 0x400 -; SSE-NEXT: jne LBB1_21 -; SSE-NEXT: LBB1_22: ## %else29 +; SSE-NEXT: jne LBB1_27 +; SSE-NEXT: LBB1_11: ## %else29 ; SSE-NEXT: testl $2048, %eax ## imm = 0x800 -; SSE-NEXT: jne LBB1_23 -; SSE-NEXT: LBB1_24: ## %else32 +; SSE-NEXT: jne LBB1_28 +; SSE-NEXT: LBB1_12: ## %else32 ; SSE-NEXT: testl $4096, %eax ## imm = 0x1000 -; SSE-NEXT: jne LBB1_25 -; SSE-NEXT: LBB1_26: ## %else35 +; SSE-NEXT: jne LBB1_29 +; SSE-NEXT: LBB1_13: ## %else35 ; SSE-NEXT: testl $8192, %eax ## imm = 0x2000 -; SSE-NEXT: jne LBB1_27 -; SSE-NEXT: LBB1_28: ## %else38 +; SSE-NEXT: jne LBB1_30 +; SSE-NEXT: LBB1_14: ## %else38 ; SSE-NEXT: testl $16384, %eax ## imm = 0x4000 -; SSE-NEXT: jne LBB1_29 -; SSE-NEXT: LBB1_30: ## %else41 -; SSE-NEXT: testl $32768, %eax ## imm = 0x8000 ; SSE-NEXT: jne LBB1_31 -; SSE-NEXT: LBB1_32: ## %else44 +; SSE-NEXT: LBB1_15: ## %else41 +; SSE-NEXT: testl $32768, %eax ## imm = 0x8000 +; SSE-NEXT: jne LBB1_32 +; SSE-NEXT: LBB1_16: ## %else44 ; SSE-NEXT: retq -; SSE-NEXT: LBB1_1: ## %cond.store +; SSE-NEXT: LBB1_17: ## %cond.store ; SSE-NEXT: movlps %xmm0, (%rdi) ; SSE-NEXT: addq $8, %rdi ; SSE-NEXT: testb $2, %al -; SSE-NEXT: je LBB1_4 -; SSE-NEXT: LBB1_3: ## %cond.store1 +; SSE-NEXT: je LBB1_2 +; SSE-NEXT: LBB1_18: ## %cond.store1 ; SSE-NEXT: movhps %xmm0, (%rdi) ; SSE-NEXT: addq $8, %rdi ; SSE-NEXT: testb $4, %al -; SSE-NEXT: je LBB1_6 -; SSE-NEXT: LBB1_5: ## %cond.store4 +; SSE-NEXT: je LBB1_3 +; SSE-NEXT: LBB1_19: ## %cond.store4 ; SSE-NEXT: movlps %xmm1, (%rdi) ; SSE-NEXT: addq $8, %rdi ; SSE-NEXT: testb $8, %al -; SSE-NEXT: je LBB1_8 -; SSE-NEXT: LBB1_7: ## %cond.store7 +; SSE-NEXT: je LBB1_4 +; SSE-NEXT: LBB1_20: ## %cond.store7 ; SSE-NEXT: movhps %xmm1, (%rdi) ; SSE-NEXT: addq $8, %rdi ; SSE-NEXT: testb $16, %al -; SSE-NEXT: je LBB1_10 -; SSE-NEXT: LBB1_9: ## %cond.store10 +; SSE-NEXT: je LBB1_5 +; SSE-NEXT: LBB1_21: ## %cond.store10 ; SSE-NEXT: movlps %xmm2, (%rdi) ; SSE-NEXT: addq $8, %rdi ; SSE-NEXT: testb $32, %al -; SSE-NEXT: je LBB1_12 -; SSE-NEXT: LBB1_11: ## %cond.store13 +; SSE-NEXT: je LBB1_6 +; SSE-NEXT: LBB1_22: ## %cond.store13 ; SSE-NEXT: movhps %xmm2, (%rdi) ; SSE-NEXT: addq $8, %rdi ; SSE-NEXT: testb $64, %al -; SSE-NEXT: je LBB1_14 -; SSE-NEXT: LBB1_13: ## %cond.store16 +; SSE-NEXT: je LBB1_7 +; SSE-NEXT: LBB1_23: ## %cond.store16 ; SSE-NEXT: movlps %xmm3, (%rdi) ; SSE-NEXT: addq $8, %rdi ; SSE-NEXT: testb %al, %al -; SSE-NEXT: jns LBB1_16 -; SSE-NEXT: LBB1_15: ## %cond.store19 +; SSE-NEXT: jns LBB1_8 +; SSE-NEXT: LBB1_24: ## %cond.store19 ; SSE-NEXT: movhps %xmm3, (%rdi) ; SSE-NEXT: addq $8, %rdi ; SSE-NEXT: testl $256, %eax ## imm = 0x100 -; SSE-NEXT: je LBB1_18 -; SSE-NEXT: LBB1_17: ## %cond.store22 +; SSE-NEXT: je LBB1_9 +; SSE-NEXT: LBB1_25: ## %cond.store22 ; SSE-NEXT: movlps %xmm4, (%rdi) ; SSE-NEXT: addq $8, %rdi ; SSE-NEXT: testl $512, %eax ## imm = 0x200 -; SSE-NEXT: je LBB1_20 -; SSE-NEXT: LBB1_19: ## %cond.store25 +; SSE-NEXT: je LBB1_10 +; SSE-NEXT: LBB1_26: ## %cond.store25 ; SSE-NEXT: movhps %xmm4, (%rdi) ; SSE-NEXT: addq $8, %rdi ; SSE-NEXT: testl $1024, %eax ## imm = 0x400 -; SSE-NEXT: je LBB1_22 -; SSE-NEXT: LBB1_21: ## %cond.store28 +; SSE-NEXT: je LBB1_11 +; SSE-NEXT: LBB1_27: ## %cond.store28 ; SSE-NEXT: movlps %xmm5, (%rdi) ; SSE-NEXT: addq $8, %rdi ; SSE-NEXT: testl $2048, %eax ## imm = 0x800 -; SSE-NEXT: je LBB1_24 -; SSE-NEXT: LBB1_23: ## %cond.store31 +; SSE-NEXT: je LBB1_12 +; SSE-NEXT: LBB1_28: ## %cond.store31 ; SSE-NEXT: movhps %xmm5, (%rdi) ; SSE-NEXT: addq $8, %rdi ; SSE-NEXT: testl $4096, %eax ## imm = 0x1000 -; SSE-NEXT: je LBB1_26 -; SSE-NEXT: LBB1_25: ## %cond.store34 +; SSE-NEXT: je LBB1_13 +; SSE-NEXT: LBB1_29: ## %cond.store34 ; SSE-NEXT: movlps %xmm6, (%rdi) ; SSE-NEXT: addq $8, %rdi ; SSE-NEXT: testl $8192, %eax ## imm = 0x2000 -; SSE-NEXT: je LBB1_28 -; SSE-NEXT: LBB1_27: ## %cond.store37 +; SSE-NEXT: je LBB1_14 +; SSE-NEXT: LBB1_30: ## %cond.store37 ; SSE-NEXT: movhps %xmm6, (%rdi) ; SSE-NEXT: addq $8, %rdi ; SSE-NEXT: testl $16384, %eax ## imm = 0x4000 -; SSE-NEXT: je LBB1_30 -; SSE-NEXT: LBB1_29: ## %cond.store40 +; SSE-NEXT: je LBB1_15 +; SSE-NEXT: LBB1_31: ## %cond.store40 ; SSE-NEXT: movlps %xmm7, (%rdi) ; SSE-NEXT: addq $8, %rdi ; SSE-NEXT: testl $32768, %eax ## imm = 0x8000 -; SSE-NEXT: je LBB1_32 -; SSE-NEXT: LBB1_31: ## %cond.store43 +; SSE-NEXT: je LBB1_16 +; SSE-NEXT: LBB1_32: ## %cond.store43 ; SSE-NEXT: movhps %xmm7, (%rdi) ; SSE-NEXT: retq ; @@ -398,115 +398,115 @@ define void @compressstore_v16f64_v16i1(ptr %base, <16 x double> %V, <16 x i1> % ; AVX1OR2-NEXT: LBB1_4: ## %else2 ; AVX1OR2-NEXT: testb $4, %al ; AVX1OR2-NEXT: vextractf128 $1, %ymm0, %xmm0 -; AVX1OR2-NEXT: jne LBB1_5 -; AVX1OR2-NEXT: ## %bb.6: ## %else5 +; AVX1OR2-NEXT: jne LBB1_22 +; AVX1OR2-NEXT: ## %bb.5: ## %else5 ; AVX1OR2-NEXT: testb $8, %al -; AVX1OR2-NEXT: jne LBB1_7 -; AVX1OR2-NEXT: LBB1_8: ## %else8 +; AVX1OR2-NEXT: jne LBB1_23 +; AVX1OR2-NEXT: LBB1_6: ## %else8 ; AVX1OR2-NEXT: testb $16, %al -; AVX1OR2-NEXT: jne LBB1_9 -; AVX1OR2-NEXT: LBB1_10: ## %else11 +; AVX1OR2-NEXT: jne LBB1_24 +; AVX1OR2-NEXT: LBB1_7: ## %else11 ; AVX1OR2-NEXT: testb $32, %al -; AVX1OR2-NEXT: je LBB1_12 -; AVX1OR2-NEXT: LBB1_11: ## %cond.store13 +; AVX1OR2-NEXT: je LBB1_9 +; AVX1OR2-NEXT: LBB1_8: ## %cond.store13 ; AVX1OR2-NEXT: vmovhps %xmm1, (%rdi) ; AVX1OR2-NEXT: addq $8, %rdi -; AVX1OR2-NEXT: LBB1_12: ## %else14 +; AVX1OR2-NEXT: LBB1_9: ## %else14 ; AVX1OR2-NEXT: testb $64, %al ; AVX1OR2-NEXT: vextractf128 $1, %ymm1, %xmm0 -; AVX1OR2-NEXT: jne LBB1_13 -; AVX1OR2-NEXT: ## %bb.14: ## %else17 +; AVX1OR2-NEXT: jne LBB1_25 +; AVX1OR2-NEXT: ## %bb.10: ## %else17 ; AVX1OR2-NEXT: testb %al, %al -; AVX1OR2-NEXT: js LBB1_15 -; AVX1OR2-NEXT: LBB1_16: ## %else20 +; AVX1OR2-NEXT: js LBB1_26 +; AVX1OR2-NEXT: LBB1_11: ## %else20 ; AVX1OR2-NEXT: testl $256, %eax ## imm = 0x100 -; AVX1OR2-NEXT: jne LBB1_17 -; AVX1OR2-NEXT: LBB1_18: ## %else23 +; AVX1OR2-NEXT: jne LBB1_27 +; AVX1OR2-NEXT: LBB1_12: ## %else23 ; AVX1OR2-NEXT: testl $512, %eax ## imm = 0x200 -; AVX1OR2-NEXT: je LBB1_20 -; AVX1OR2-NEXT: LBB1_19: ## %cond.store25 +; AVX1OR2-NEXT: je LBB1_14 +; AVX1OR2-NEXT: LBB1_13: ## %cond.store25 ; AVX1OR2-NEXT: vmovhps %xmm2, (%rdi) ; AVX1OR2-NEXT: addq $8, %rdi -; AVX1OR2-NEXT: LBB1_20: ## %else26 +; AVX1OR2-NEXT: LBB1_14: ## %else26 ; AVX1OR2-NEXT: testl $1024, %eax ## imm = 0x400 ; AVX1OR2-NEXT: vextractf128 $1, %ymm2, %xmm0 -; AVX1OR2-NEXT: jne LBB1_21 -; AVX1OR2-NEXT: ## %bb.22: ## %else29 +; AVX1OR2-NEXT: jne LBB1_28 +; AVX1OR2-NEXT: ## %bb.15: ## %else29 ; AVX1OR2-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX1OR2-NEXT: jne LBB1_23 -; AVX1OR2-NEXT: LBB1_24: ## %else32 +; AVX1OR2-NEXT: jne LBB1_29 +; AVX1OR2-NEXT: LBB1_16: ## %else32 ; AVX1OR2-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX1OR2-NEXT: jne LBB1_25 -; AVX1OR2-NEXT: LBB1_26: ## %else35 +; AVX1OR2-NEXT: jne LBB1_30 +; AVX1OR2-NEXT: LBB1_17: ## %else35 ; AVX1OR2-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX1OR2-NEXT: je LBB1_28 -; AVX1OR2-NEXT: LBB1_27: ## %cond.store37 +; AVX1OR2-NEXT: je LBB1_19 +; AVX1OR2-NEXT: LBB1_18: ## %cond.store37 ; AVX1OR2-NEXT: vmovhps %xmm3, (%rdi) ; AVX1OR2-NEXT: addq $8, %rdi -; AVX1OR2-NEXT: LBB1_28: ## %else38 +; AVX1OR2-NEXT: LBB1_19: ## %else38 ; AVX1OR2-NEXT: testl $16384, %eax ## imm = 0x4000 ; AVX1OR2-NEXT: vextractf128 $1, %ymm3, %xmm0 -; AVX1OR2-NEXT: jne LBB1_29 -; AVX1OR2-NEXT: ## %bb.30: ## %else41 -; AVX1OR2-NEXT: testl $32768, %eax ## imm = 0x8000 ; AVX1OR2-NEXT: jne LBB1_31 -; AVX1OR2-NEXT: LBB1_32: ## %else44 +; AVX1OR2-NEXT: ## %bb.20: ## %else41 +; AVX1OR2-NEXT: testl $32768, %eax ## imm = 0x8000 +; AVX1OR2-NEXT: jne LBB1_32 +; AVX1OR2-NEXT: LBB1_21: ## %else44 ; AVX1OR2-NEXT: vzeroupper ; AVX1OR2-NEXT: retq -; AVX1OR2-NEXT: LBB1_5: ## %cond.store4 +; AVX1OR2-NEXT: LBB1_22: ## %cond.store4 ; AVX1OR2-NEXT: vmovlps %xmm0, (%rdi) ; AVX1OR2-NEXT: addq $8, %rdi ; AVX1OR2-NEXT: testb $8, %al -; AVX1OR2-NEXT: je LBB1_8 -; AVX1OR2-NEXT: LBB1_7: ## %cond.store7 +; AVX1OR2-NEXT: je LBB1_6 +; AVX1OR2-NEXT: LBB1_23: ## %cond.store7 ; AVX1OR2-NEXT: vmovhps %xmm0, (%rdi) ; AVX1OR2-NEXT: addq $8, %rdi ; AVX1OR2-NEXT: testb $16, %al -; AVX1OR2-NEXT: je LBB1_10 -; AVX1OR2-NEXT: LBB1_9: ## %cond.store10 +; AVX1OR2-NEXT: je LBB1_7 +; AVX1OR2-NEXT: LBB1_24: ## %cond.store10 ; AVX1OR2-NEXT: vmovlps %xmm1, (%rdi) ; AVX1OR2-NEXT: addq $8, %rdi ; AVX1OR2-NEXT: testb $32, %al -; AVX1OR2-NEXT: jne LBB1_11 -; AVX1OR2-NEXT: jmp LBB1_12 -; AVX1OR2-NEXT: LBB1_13: ## %cond.store16 +; AVX1OR2-NEXT: jne LBB1_8 +; AVX1OR2-NEXT: jmp LBB1_9 +; AVX1OR2-NEXT: LBB1_25: ## %cond.store16 ; AVX1OR2-NEXT: vmovlps %xmm0, (%rdi) ; AVX1OR2-NEXT: addq $8, %rdi ; AVX1OR2-NEXT: testb %al, %al -; AVX1OR2-NEXT: jns LBB1_16 -; AVX1OR2-NEXT: LBB1_15: ## %cond.store19 +; AVX1OR2-NEXT: jns LBB1_11 +; AVX1OR2-NEXT: LBB1_26: ## %cond.store19 ; AVX1OR2-NEXT: vmovhps %xmm0, (%rdi) ; AVX1OR2-NEXT: addq $8, %rdi ; AVX1OR2-NEXT: testl $256, %eax ## imm = 0x100 -; AVX1OR2-NEXT: je LBB1_18 -; AVX1OR2-NEXT: LBB1_17: ## %cond.store22 +; AVX1OR2-NEXT: je LBB1_12 +; AVX1OR2-NEXT: LBB1_27: ## %cond.store22 ; AVX1OR2-NEXT: vmovlps %xmm2, (%rdi) ; AVX1OR2-NEXT: addq $8, %rdi ; AVX1OR2-NEXT: testl $512, %eax ## imm = 0x200 -; AVX1OR2-NEXT: jne LBB1_19 -; AVX1OR2-NEXT: jmp LBB1_20 -; AVX1OR2-NEXT: LBB1_21: ## %cond.store28 +; AVX1OR2-NEXT: jne LBB1_13 +; AVX1OR2-NEXT: jmp LBB1_14 +; AVX1OR2-NEXT: LBB1_28: ## %cond.store28 ; AVX1OR2-NEXT: vmovlps %xmm0, (%rdi) ; AVX1OR2-NEXT: addq $8, %rdi ; AVX1OR2-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX1OR2-NEXT: je LBB1_24 -; AVX1OR2-NEXT: LBB1_23: ## %cond.store31 +; AVX1OR2-NEXT: je LBB1_16 +; AVX1OR2-NEXT: LBB1_29: ## %cond.store31 ; AVX1OR2-NEXT: vmovhps %xmm0, (%rdi) ; AVX1OR2-NEXT: addq $8, %rdi ; AVX1OR2-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX1OR2-NEXT: je LBB1_26 -; AVX1OR2-NEXT: LBB1_25: ## %cond.store34 +; AVX1OR2-NEXT: je LBB1_17 +; AVX1OR2-NEXT: LBB1_30: ## %cond.store34 ; AVX1OR2-NEXT: vmovlps %xmm3, (%rdi) ; AVX1OR2-NEXT: addq $8, %rdi ; AVX1OR2-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX1OR2-NEXT: jne LBB1_27 -; AVX1OR2-NEXT: jmp LBB1_28 -; AVX1OR2-NEXT: LBB1_29: ## %cond.store40 +; AVX1OR2-NEXT: jne LBB1_18 +; AVX1OR2-NEXT: jmp LBB1_19 +; AVX1OR2-NEXT: LBB1_31: ## %cond.store40 ; AVX1OR2-NEXT: vmovlps %xmm0, (%rdi) ; AVX1OR2-NEXT: addq $8, %rdi ; AVX1OR2-NEXT: testl $32768, %eax ## imm = 0x8000 -; AVX1OR2-NEXT: je LBB1_32 -; AVX1OR2-NEXT: LBB1_31: ## %cond.store43 +; AVX1OR2-NEXT: je LBB1_21 +; AVX1OR2-NEXT: LBB1_32: ## %cond.store43 ; AVX1OR2-NEXT: vmovhps %xmm0, (%rdi) ; AVX1OR2-NEXT: vzeroupper ; AVX1OR2-NEXT: retq @@ -578,18 +578,18 @@ define void @compressstore_v2f32_v2i32(ptr %base, <2 x float> %V, <2 x i32> %tri ; SSE2-NEXT: pcmpeqd %xmm1, %xmm2 ; SSE2-NEXT: movmskpd %xmm2, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB2_1 -; SSE2-NEXT: ## %bb.2: ## %else -; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: jne LBB2_3 -; SSE2-NEXT: LBB2_4: ## %else2 +; SSE2-NEXT: ## %bb.1: ## %else +; SSE2-NEXT: testb $2, %al +; SSE2-NEXT: jne LBB2_4 +; SSE2-NEXT: LBB2_2: ## %else2 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB2_1: ## %cond.store +; SSE2-NEXT: LBB2_3: ## %cond.store ; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB2_4 -; SSE2-NEXT: LBB2_3: ## %cond.store1 +; SSE2-NEXT: je LBB2_2 +; SSE2-NEXT: LBB2_4: ## %cond.store1 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1] ; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: retq @@ -601,18 +601,18 @@ define void @compressstore_v2f32_v2i32(ptr %base, <2 x float> %V, <2 x i32> %tri ; SSE42-NEXT: pmovsxdq %xmm2, %xmm1 ; SSE42-NEXT: movmskpd %xmm1, %eax ; SSE42-NEXT: testb $1, %al -; SSE42-NEXT: jne LBB2_1 -; SSE42-NEXT: ## %bb.2: ## %else -; SSE42-NEXT: testb $2, %al ; SSE42-NEXT: jne LBB2_3 -; SSE42-NEXT: LBB2_4: ## %else2 +; SSE42-NEXT: ## %bb.1: ## %else +; SSE42-NEXT: testb $2, %al +; SSE42-NEXT: jne LBB2_4 +; SSE42-NEXT: LBB2_2: ## %else2 ; SSE42-NEXT: retq -; SSE42-NEXT: LBB2_1: ## %cond.store +; SSE42-NEXT: LBB2_3: ## %cond.store ; SSE42-NEXT: movss %xmm0, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: je LBB2_4 -; SSE42-NEXT: LBB2_3: ## %cond.store1 +; SSE42-NEXT: je LBB2_2 +; SSE42-NEXT: LBB2_4: ## %cond.store1 ; SSE42-NEXT: extractps $1, %xmm0, (%rdi) ; SSE42-NEXT: retq ; @@ -623,18 +623,18 @@ define void @compressstore_v2f32_v2i32(ptr %base, <2 x float> %V, <2 x i32> %tri ; AVX1OR2-NEXT: vpmovsxdq %xmm1, %xmm1 ; AVX1OR2-NEXT: vmovmskpd %xmm1, %eax ; AVX1OR2-NEXT: testb $1, %al -; AVX1OR2-NEXT: jne LBB2_1 -; AVX1OR2-NEXT: ## %bb.2: ## %else -; AVX1OR2-NEXT: testb $2, %al ; AVX1OR2-NEXT: jne LBB2_3 -; AVX1OR2-NEXT: LBB2_4: ## %else2 +; AVX1OR2-NEXT: ## %bb.1: ## %else +; AVX1OR2-NEXT: testb $2, %al +; AVX1OR2-NEXT: jne LBB2_4 +; AVX1OR2-NEXT: LBB2_2: ## %else2 ; AVX1OR2-NEXT: retq -; AVX1OR2-NEXT: LBB2_1: ## %cond.store +; AVX1OR2-NEXT: LBB2_3: ## %cond.store ; AVX1OR2-NEXT: vmovss %xmm0, (%rdi) ; AVX1OR2-NEXT: addq $4, %rdi ; AVX1OR2-NEXT: testb $2, %al -; AVX1OR2-NEXT: je LBB2_4 -; AVX1OR2-NEXT: LBB2_3: ## %cond.store1 +; AVX1OR2-NEXT: je LBB2_2 +; AVX1OR2-NEXT: LBB2_4: ## %cond.store1 ; AVX1OR2-NEXT: vextractps $1, %xmm0, (%rdi) ; AVX1OR2-NEXT: retq ; @@ -675,38 +675,38 @@ define void @compressstore_v4f32_v4i1(ptr %base, <4 x float> %V, <4 x i1> %mask) ; SSE2-NEXT: pslld $31, %xmm1 ; SSE2-NEXT: movmskps %xmm1, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB3_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB3_5 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB3_3 -; SSE2-NEXT: LBB3_4: ## %else2 +; SSE2-NEXT: jne LBB3_6 +; SSE2-NEXT: LBB3_2: ## %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB3_5 -; SSE2-NEXT: LBB3_6: ## %else5 -; SSE2-NEXT: testb $8, %al ; SSE2-NEXT: jne LBB3_7 -; SSE2-NEXT: LBB3_8: ## %else8 +; SSE2-NEXT: LBB3_3: ## %else5 +; SSE2-NEXT: testb $8, %al +; SSE2-NEXT: jne LBB3_8 +; SSE2-NEXT: LBB3_4: ## %else8 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB3_1: ## %cond.store +; SSE2-NEXT: LBB3_5: ## %cond.store ; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB3_4 -; SSE2-NEXT: LBB3_3: ## %cond.store1 +; SSE2-NEXT: je LBB3_2 +; SSE2-NEXT: LBB3_6: ## %cond.store1 ; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1] ; SSE2-NEXT: movss %xmm1, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB3_6 -; SSE2-NEXT: LBB3_5: ## %cond.store4 +; SSE2-NEXT: je LBB3_3 +; SSE2-NEXT: LBB3_7: ## %cond.store4 ; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: movss %xmm1, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB3_8 -; SSE2-NEXT: LBB3_7: ## %cond.store7 +; SSE2-NEXT: je LBB3_4 +; SSE2-NEXT: LBB3_8: ## %cond.store7 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: retq @@ -716,34 +716,34 @@ define void @compressstore_v4f32_v4i1(ptr %base, <4 x float> %V, <4 x i1> %mask) ; SSE42-NEXT: pslld $31, %xmm1 ; SSE42-NEXT: movmskps %xmm1, %eax ; SSE42-NEXT: testb $1, %al -; SSE42-NEXT: jne LBB3_1 -; SSE42-NEXT: ## %bb.2: ## %else +; SSE42-NEXT: jne LBB3_5 +; SSE42-NEXT: ## %bb.1: ## %else ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: jne LBB3_3 -; SSE42-NEXT: LBB3_4: ## %else2 +; SSE42-NEXT: jne LBB3_6 +; SSE42-NEXT: LBB3_2: ## %else2 ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: jne LBB3_5 -; SSE42-NEXT: LBB3_6: ## %else5 -; SSE42-NEXT: testb $8, %al ; SSE42-NEXT: jne LBB3_7 -; SSE42-NEXT: LBB3_8: ## %else8 +; SSE42-NEXT: LBB3_3: ## %else5 +; SSE42-NEXT: testb $8, %al +; SSE42-NEXT: jne LBB3_8 +; SSE42-NEXT: LBB3_4: ## %else8 ; SSE42-NEXT: retq -; SSE42-NEXT: LBB3_1: ## %cond.store +; SSE42-NEXT: LBB3_5: ## %cond.store ; SSE42-NEXT: movss %xmm0, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: je LBB3_4 -; SSE42-NEXT: LBB3_3: ## %cond.store1 +; SSE42-NEXT: je LBB3_2 +; SSE42-NEXT: LBB3_6: ## %cond.store1 ; SSE42-NEXT: extractps $1, %xmm0, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: je LBB3_6 -; SSE42-NEXT: LBB3_5: ## %cond.store4 +; SSE42-NEXT: je LBB3_3 +; SSE42-NEXT: LBB3_7: ## %cond.store4 ; SSE42-NEXT: extractps $2, %xmm0, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: je LBB3_8 -; SSE42-NEXT: LBB3_7: ## %cond.store7 +; SSE42-NEXT: je LBB3_4 +; SSE42-NEXT: LBB3_8: ## %cond.store7 ; SSE42-NEXT: extractps $3, %xmm0, (%rdi) ; SSE42-NEXT: retq ; @@ -752,34 +752,34 @@ define void @compressstore_v4f32_v4i1(ptr %base, <4 x float> %V, <4 x i1> %mask) ; AVX1OR2-NEXT: vpslld $31, %xmm1, %xmm1 ; AVX1OR2-NEXT: vmovmskps %xmm1, %eax ; AVX1OR2-NEXT: testb $1, %al -; AVX1OR2-NEXT: jne LBB3_1 -; AVX1OR2-NEXT: ## %bb.2: ## %else +; AVX1OR2-NEXT: jne LBB3_5 +; AVX1OR2-NEXT: ## %bb.1: ## %else ; AVX1OR2-NEXT: testb $2, %al -; AVX1OR2-NEXT: jne LBB3_3 -; AVX1OR2-NEXT: LBB3_4: ## %else2 +; AVX1OR2-NEXT: jne LBB3_6 +; AVX1OR2-NEXT: LBB3_2: ## %else2 ; AVX1OR2-NEXT: testb $4, %al -; AVX1OR2-NEXT: jne LBB3_5 -; AVX1OR2-NEXT: LBB3_6: ## %else5 -; AVX1OR2-NEXT: testb $8, %al ; AVX1OR2-NEXT: jne LBB3_7 -; AVX1OR2-NEXT: LBB3_8: ## %else8 +; AVX1OR2-NEXT: LBB3_3: ## %else5 +; AVX1OR2-NEXT: testb $8, %al +; AVX1OR2-NEXT: jne LBB3_8 +; AVX1OR2-NEXT: LBB3_4: ## %else8 ; AVX1OR2-NEXT: retq -; AVX1OR2-NEXT: LBB3_1: ## %cond.store +; AVX1OR2-NEXT: LBB3_5: ## %cond.store ; AVX1OR2-NEXT: vmovss %xmm0, (%rdi) ; AVX1OR2-NEXT: addq $4, %rdi ; AVX1OR2-NEXT: testb $2, %al -; AVX1OR2-NEXT: je LBB3_4 -; AVX1OR2-NEXT: LBB3_3: ## %cond.store1 +; AVX1OR2-NEXT: je LBB3_2 +; AVX1OR2-NEXT: LBB3_6: ## %cond.store1 ; AVX1OR2-NEXT: vextractps $1, %xmm0, (%rdi) ; AVX1OR2-NEXT: addq $4, %rdi ; AVX1OR2-NEXT: testb $4, %al -; AVX1OR2-NEXT: je LBB3_6 -; AVX1OR2-NEXT: LBB3_5: ## %cond.store4 +; AVX1OR2-NEXT: je LBB3_3 +; AVX1OR2-NEXT: LBB3_7: ## %cond.store4 ; AVX1OR2-NEXT: vextractps $2, %xmm0, (%rdi) ; AVX1OR2-NEXT: addq $4, %rdi ; AVX1OR2-NEXT: testb $8, %al -; AVX1OR2-NEXT: je LBB3_8 -; AVX1OR2-NEXT: LBB3_7: ## %cond.store7 +; AVX1OR2-NEXT: je LBB3_4 +; AVX1OR2-NEXT: LBB3_8: ## %cond.store7 ; AVX1OR2-NEXT: vextractps $3, %xmm0, (%rdi) ; AVX1OR2-NEXT: retq ; @@ -818,75 +818,75 @@ define void @compressstore_v8f32_v8i1(ptr %base, <8 x float> %V, <8 x i1> %mask) ; SSE2-NEXT: packsswb %xmm2, %xmm2 ; SSE2-NEXT: pmovmskb %xmm2, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB4_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB4_9 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB4_3 -; SSE2-NEXT: LBB4_4: ## %else2 +; SSE2-NEXT: jne LBB4_10 +; SSE2-NEXT: LBB4_2: ## %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB4_5 -; SSE2-NEXT: LBB4_6: ## %else5 +; SSE2-NEXT: jne LBB4_11 +; SSE2-NEXT: LBB4_3: ## %else5 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne LBB4_7 -; SSE2-NEXT: LBB4_8: ## %else8 +; SSE2-NEXT: jne LBB4_12 +; SSE2-NEXT: LBB4_4: ## %else8 ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: jne LBB4_9 -; SSE2-NEXT: LBB4_10: ## %else11 +; SSE2-NEXT: jne LBB4_13 +; SSE2-NEXT: LBB4_5: ## %else11 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: jne LBB4_11 -; SSE2-NEXT: LBB4_12: ## %else14 +; SSE2-NEXT: jne LBB4_14 +; SSE2-NEXT: LBB4_6: ## %else14 ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: jne LBB4_13 -; SSE2-NEXT: LBB4_14: ## %else17 -; SSE2-NEXT: testb $-128, %al ; SSE2-NEXT: jne LBB4_15 -; SSE2-NEXT: LBB4_16: ## %else20 +; SSE2-NEXT: LBB4_7: ## %else17 +; SSE2-NEXT: testb $-128, %al +; SSE2-NEXT: jne LBB4_16 +; SSE2-NEXT: LBB4_8: ## %else20 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB4_1: ## %cond.store +; SSE2-NEXT: LBB4_9: ## %cond.store ; SSE2-NEXT: movd %xmm0, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB4_4 -; SSE2-NEXT: LBB4_3: ## %cond.store1 +; SSE2-NEXT: je LBB4_2 +; SSE2-NEXT: LBB4_10: ## %cond.store1 ; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm0[1,1] ; SSE2-NEXT: movss %xmm2, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB4_6 -; SSE2-NEXT: LBB4_5: ## %cond.store4 +; SSE2-NEXT: je LBB4_3 +; SSE2-NEXT: LBB4_11: ## %cond.store4 ; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: punpckhqdq {{.*#+}} xmm2 = xmm2[1],xmm0[1] ; SSE2-NEXT: movd %xmm2, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB4_8 -; SSE2-NEXT: LBB4_7: ## %cond.store7 +; SSE2-NEXT: je LBB4_4 +; SSE2-NEXT: LBB4_12: ## %cond.store7 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: je LBB4_10 -; SSE2-NEXT: LBB4_9: ## %cond.store10 +; SSE2-NEXT: je LBB4_5 +; SSE2-NEXT: LBB4_13: ## %cond.store10 ; SSE2-NEXT: movss %xmm1, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je LBB4_12 -; SSE2-NEXT: LBB4_11: ## %cond.store13 +; SSE2-NEXT: je LBB4_6 +; SSE2-NEXT: LBB4_14: ## %cond.store13 ; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1] ; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: je LBB4_14 -; SSE2-NEXT: LBB4_13: ## %cond.store16 +; SSE2-NEXT: je LBB4_7 +; SSE2-NEXT: LBB4_15: ## %cond.store16 ; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1] ; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testb $-128, %al -; SSE2-NEXT: je LBB4_16 -; SSE2-NEXT: LBB4_15: ## %cond.store19 +; SSE2-NEXT: je LBB4_8 +; SSE2-NEXT: LBB4_16: ## %cond.store19 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE2-NEXT: movss %xmm1, (%rdi) ; SSE2-NEXT: retq @@ -897,66 +897,66 @@ define void @compressstore_v8f32_v8i1(ptr %base, <8 x float> %V, <8 x i1> %mask) ; SSE42-NEXT: packsswb %xmm2, %xmm2 ; SSE42-NEXT: pmovmskb %xmm2, %eax ; SSE42-NEXT: testb $1, %al -; SSE42-NEXT: jne LBB4_1 -; SSE42-NEXT: ## %bb.2: ## %else +; SSE42-NEXT: jne LBB4_9 +; SSE42-NEXT: ## %bb.1: ## %else ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: jne LBB4_3 -; SSE42-NEXT: LBB4_4: ## %else2 +; SSE42-NEXT: jne LBB4_10 +; SSE42-NEXT: LBB4_2: ## %else2 ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: jne LBB4_5 -; SSE42-NEXT: LBB4_6: ## %else5 +; SSE42-NEXT: jne LBB4_11 +; SSE42-NEXT: LBB4_3: ## %else5 ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: jne LBB4_7 -; SSE42-NEXT: LBB4_8: ## %else8 +; SSE42-NEXT: jne LBB4_12 +; SSE42-NEXT: LBB4_4: ## %else8 ; SSE42-NEXT: testb $16, %al -; SSE42-NEXT: jne LBB4_9 -; SSE42-NEXT: LBB4_10: ## %else11 +; SSE42-NEXT: jne LBB4_13 +; SSE42-NEXT: LBB4_5: ## %else11 ; SSE42-NEXT: testb $32, %al -; SSE42-NEXT: jne LBB4_11 -; SSE42-NEXT: LBB4_12: ## %else14 +; SSE42-NEXT: jne LBB4_14 +; SSE42-NEXT: LBB4_6: ## %else14 ; SSE42-NEXT: testb $64, %al -; SSE42-NEXT: jne LBB4_13 -; SSE42-NEXT: LBB4_14: ## %else17 -; SSE42-NEXT: testb $-128, %al ; SSE42-NEXT: jne LBB4_15 -; SSE42-NEXT: LBB4_16: ## %else20 +; SSE42-NEXT: LBB4_7: ## %else17 +; SSE42-NEXT: testb $-128, %al +; SSE42-NEXT: jne LBB4_16 +; SSE42-NEXT: LBB4_8: ## %else20 ; SSE42-NEXT: retq -; SSE42-NEXT: LBB4_1: ## %cond.store +; SSE42-NEXT: LBB4_9: ## %cond.store ; SSE42-NEXT: movd %xmm0, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: je LBB4_4 -; SSE42-NEXT: LBB4_3: ## %cond.store1 +; SSE42-NEXT: je LBB4_2 +; SSE42-NEXT: LBB4_10: ## %cond.store1 ; SSE42-NEXT: pextrd $1, %xmm0, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: je LBB4_6 -; SSE42-NEXT: LBB4_5: ## %cond.store4 +; SSE42-NEXT: je LBB4_3 +; SSE42-NEXT: LBB4_11: ## %cond.store4 ; SSE42-NEXT: pextrd $2, %xmm0, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: je LBB4_8 -; SSE42-NEXT: LBB4_7: ## %cond.store7 +; SSE42-NEXT: je LBB4_4 +; SSE42-NEXT: LBB4_12: ## %cond.store7 ; SSE42-NEXT: pextrd $3, %xmm0, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testb $16, %al -; SSE42-NEXT: je LBB4_10 -; SSE42-NEXT: LBB4_9: ## %cond.store10 +; SSE42-NEXT: je LBB4_5 +; SSE42-NEXT: LBB4_13: ## %cond.store10 ; SSE42-NEXT: movss %xmm1, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testb $32, %al -; SSE42-NEXT: je LBB4_12 -; SSE42-NEXT: LBB4_11: ## %cond.store13 +; SSE42-NEXT: je LBB4_6 +; SSE42-NEXT: LBB4_14: ## %cond.store13 ; SSE42-NEXT: extractps $1, %xmm1, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testb $64, %al -; SSE42-NEXT: je LBB4_14 -; SSE42-NEXT: LBB4_13: ## %cond.store16 +; SSE42-NEXT: je LBB4_7 +; SSE42-NEXT: LBB4_15: ## %cond.store16 ; SSE42-NEXT: extractps $2, %xmm1, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testb $-128, %al -; SSE42-NEXT: je LBB4_16 -; SSE42-NEXT: LBB4_15: ## %cond.store19 +; SSE42-NEXT: je LBB4_8 +; SSE42-NEXT: LBB4_16: ## %cond.store19 ; SSE42-NEXT: extractps $3, %xmm1, (%rdi) ; SSE42-NEXT: retq ; @@ -966,67 +966,67 @@ define void @compressstore_v8f32_v8i1(ptr %base, <8 x float> %V, <8 x i1> %mask) ; AVX1-NEXT: vpacksswb %xmm1, %xmm1, %xmm1 ; AVX1-NEXT: vpmovmskb %xmm1, %eax ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne LBB4_1 -; AVX1-NEXT: ## %bb.2: ## %else +; AVX1-NEXT: jne LBB4_10 +; AVX1-NEXT: ## %bb.1: ## %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne LBB4_3 -; AVX1-NEXT: LBB4_4: ## %else2 +; AVX1-NEXT: jne LBB4_11 +; AVX1-NEXT: LBB4_2: ## %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne LBB4_5 -; AVX1-NEXT: LBB4_6: ## %else5 +; AVX1-NEXT: jne LBB4_12 +; AVX1-NEXT: LBB4_3: ## %else5 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je LBB4_8 -; AVX1-NEXT: LBB4_7: ## %cond.store7 +; AVX1-NEXT: je LBB4_5 +; AVX1-NEXT: LBB4_4: ## %cond.store7 ; AVX1-NEXT: vpextrd $3, %xmm0, (%rdi) ; AVX1-NEXT: addq $4, %rdi -; AVX1-NEXT: LBB4_8: ## %else8 +; AVX1-NEXT: LBB4_5: ## %else8 ; AVX1-NEXT: testb $16, %al ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 -; AVX1-NEXT: jne LBB4_9 -; AVX1-NEXT: ## %bb.10: ## %else11 +; AVX1-NEXT: jne LBB4_13 +; AVX1-NEXT: ## %bb.6: ## %else11 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: jne LBB4_11 -; AVX1-NEXT: LBB4_12: ## %else14 +; AVX1-NEXT: jne LBB4_14 +; AVX1-NEXT: LBB4_7: ## %else14 ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: jne LBB4_13 -; AVX1-NEXT: LBB4_14: ## %else17 -; AVX1-NEXT: testb $-128, %al ; AVX1-NEXT: jne LBB4_15 -; AVX1-NEXT: LBB4_16: ## %else20 +; AVX1-NEXT: LBB4_8: ## %else17 +; AVX1-NEXT: testb $-128, %al +; AVX1-NEXT: jne LBB4_16 +; AVX1-NEXT: LBB4_9: ## %else20 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: LBB4_1: ## %cond.store +; AVX1-NEXT: LBB4_10: ## %cond.store ; AVX1-NEXT: vmovd %xmm0, (%rdi) ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je LBB4_4 -; AVX1-NEXT: LBB4_3: ## %cond.store1 +; AVX1-NEXT: je LBB4_2 +; AVX1-NEXT: LBB4_11: ## %cond.store1 ; AVX1-NEXT: vpextrd $1, %xmm0, (%rdi) ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je LBB4_6 -; AVX1-NEXT: LBB4_5: ## %cond.store4 +; AVX1-NEXT: je LBB4_3 +; AVX1-NEXT: LBB4_12: ## %cond.store4 ; AVX1-NEXT: vpextrd $2, %xmm0, (%rdi) ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne LBB4_7 -; AVX1-NEXT: jmp LBB4_8 -; AVX1-NEXT: LBB4_9: ## %cond.store10 +; AVX1-NEXT: jne LBB4_4 +; AVX1-NEXT: jmp LBB4_5 +; AVX1-NEXT: LBB4_13: ## %cond.store10 ; AVX1-NEXT: vmovss %xmm0, (%rdi) ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je LBB4_12 -; AVX1-NEXT: LBB4_11: ## %cond.store13 +; AVX1-NEXT: je LBB4_7 +; AVX1-NEXT: LBB4_14: ## %cond.store13 ; AVX1-NEXT: vextractps $1, %xmm0, (%rdi) ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: je LBB4_14 -; AVX1-NEXT: LBB4_13: ## %cond.store16 +; AVX1-NEXT: je LBB4_8 +; AVX1-NEXT: LBB4_15: ## %cond.store16 ; AVX1-NEXT: vextractps $2, %xmm0, (%rdi) ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testb $-128, %al -; AVX1-NEXT: je LBB4_16 -; AVX1-NEXT: LBB4_15: ## %cond.store19 +; AVX1-NEXT: je LBB4_9 +; AVX1-NEXT: LBB4_16: ## %cond.store19 ; AVX1-NEXT: vextractps $3, %xmm0, (%rdi) ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq @@ -1037,67 +1037,67 @@ define void @compressstore_v8f32_v8i1(ptr %base, <8 x float> %V, <8 x i1> %mask) ; AVX2-NEXT: vpacksswb %xmm1, %xmm1, %xmm1 ; AVX2-NEXT: vpmovmskb %xmm1, %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne LBB4_1 -; AVX2-NEXT: ## %bb.2: ## %else +; AVX2-NEXT: jne LBB4_10 +; AVX2-NEXT: ## %bb.1: ## %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne LBB4_3 -; AVX2-NEXT: LBB4_4: ## %else2 +; AVX2-NEXT: jne LBB4_11 +; AVX2-NEXT: LBB4_2: ## %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne LBB4_5 -; AVX2-NEXT: LBB4_6: ## %else5 +; AVX2-NEXT: jne LBB4_12 +; AVX2-NEXT: LBB4_3: ## %else5 ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je LBB4_8 -; AVX2-NEXT: LBB4_7: ## %cond.store7 +; AVX2-NEXT: je LBB4_5 +; AVX2-NEXT: LBB4_4: ## %cond.store7 ; AVX2-NEXT: vpextrd $3, %xmm0, (%rdi) ; AVX2-NEXT: addq $4, %rdi -; AVX2-NEXT: LBB4_8: ## %else8 +; AVX2-NEXT: LBB4_5: ## %else8 ; AVX2-NEXT: testb $16, %al ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0 -; AVX2-NEXT: jne LBB4_9 -; AVX2-NEXT: ## %bb.10: ## %else11 +; AVX2-NEXT: jne LBB4_13 +; AVX2-NEXT: ## %bb.6: ## %else11 ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: jne LBB4_11 -; AVX2-NEXT: LBB4_12: ## %else14 +; AVX2-NEXT: jne LBB4_14 +; AVX2-NEXT: LBB4_7: ## %else14 ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: jne LBB4_13 -; AVX2-NEXT: LBB4_14: ## %else17 -; AVX2-NEXT: testb $-128, %al ; AVX2-NEXT: jne LBB4_15 -; AVX2-NEXT: LBB4_16: ## %else20 +; AVX2-NEXT: LBB4_8: ## %else17 +; AVX2-NEXT: testb $-128, %al +; AVX2-NEXT: jne LBB4_16 +; AVX2-NEXT: LBB4_9: ## %else20 ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; AVX2-NEXT: LBB4_1: ## %cond.store +; AVX2-NEXT: LBB4_10: ## %cond.store ; AVX2-NEXT: vmovd %xmm0, (%rdi) ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je LBB4_4 -; AVX2-NEXT: LBB4_3: ## %cond.store1 +; AVX2-NEXT: je LBB4_2 +; AVX2-NEXT: LBB4_11: ## %cond.store1 ; AVX2-NEXT: vpextrd $1, %xmm0, (%rdi) ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je LBB4_6 -; AVX2-NEXT: LBB4_5: ## %cond.store4 +; AVX2-NEXT: je LBB4_3 +; AVX2-NEXT: LBB4_12: ## %cond.store4 ; AVX2-NEXT: vpextrd $2, %xmm0, (%rdi) ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: jne LBB4_7 -; AVX2-NEXT: jmp LBB4_8 -; AVX2-NEXT: LBB4_9: ## %cond.store10 +; AVX2-NEXT: jne LBB4_4 +; AVX2-NEXT: jmp LBB4_5 +; AVX2-NEXT: LBB4_13: ## %cond.store10 ; AVX2-NEXT: vmovd %xmm0, (%rdi) ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: je LBB4_12 -; AVX2-NEXT: LBB4_11: ## %cond.store13 +; AVX2-NEXT: je LBB4_7 +; AVX2-NEXT: LBB4_14: ## %cond.store13 ; AVX2-NEXT: vpextrd $1, %xmm0, (%rdi) ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: je LBB4_14 -; AVX2-NEXT: LBB4_13: ## %cond.store16 +; AVX2-NEXT: je LBB4_8 +; AVX2-NEXT: LBB4_15: ## %cond.store16 ; AVX2-NEXT: vpextrd $2, %xmm0, (%rdi) ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testb $-128, %al -; AVX2-NEXT: je LBB4_16 -; AVX2-NEXT: LBB4_15: ## %cond.store19 +; AVX2-NEXT: je LBB4_9 +; AVX2-NEXT: LBB4_16: ## %cond.store19 ; AVX2-NEXT: vpextrd $3, %xmm0, (%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq @@ -1263,297 +1263,297 @@ define void @compressstore_v32f32_v32i32(ptr %base, <32 x float> %V, <32 x i32> ; SSE2-NEXT: shll $16, %eax ; SSE2-NEXT: orl %ecx, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB6_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB6_33 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB6_3 -; SSE2-NEXT: LBB6_4: ## %else2 +; SSE2-NEXT: jne LBB6_34 +; SSE2-NEXT: LBB6_2: ## %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB6_5 -; SSE2-NEXT: LBB6_6: ## %else5 +; SSE2-NEXT: jne LBB6_35 +; SSE2-NEXT: LBB6_3: ## %else5 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne LBB6_7 -; SSE2-NEXT: LBB6_8: ## %else8 +; SSE2-NEXT: jne LBB6_36 +; SSE2-NEXT: LBB6_4: ## %else8 ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: jne LBB6_9 -; SSE2-NEXT: LBB6_10: ## %else11 +; SSE2-NEXT: jne LBB6_37 +; SSE2-NEXT: LBB6_5: ## %else11 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: jne LBB6_11 -; SSE2-NEXT: LBB6_12: ## %else14 +; SSE2-NEXT: jne LBB6_38 +; SSE2-NEXT: LBB6_6: ## %else14 ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: jne LBB6_13 -; SSE2-NEXT: LBB6_14: ## %else17 +; SSE2-NEXT: jne LBB6_39 +; SSE2-NEXT: LBB6_7: ## %else17 ; SSE2-NEXT: testb %al, %al -; SSE2-NEXT: js LBB6_15 -; SSE2-NEXT: LBB6_16: ## %else20 +; SSE2-NEXT: js LBB6_40 +; SSE2-NEXT: LBB6_8: ## %else20 ; SSE2-NEXT: testl $256, %eax ## imm = 0x100 -; SSE2-NEXT: jne LBB6_17 -; SSE2-NEXT: LBB6_18: ## %else23 +; SSE2-NEXT: jne LBB6_41 +; SSE2-NEXT: LBB6_9: ## %else23 ; SSE2-NEXT: testl $512, %eax ## imm = 0x200 -; SSE2-NEXT: jne LBB6_19 -; SSE2-NEXT: LBB6_20: ## %else26 +; SSE2-NEXT: jne LBB6_42 +; SSE2-NEXT: LBB6_10: ## %else26 ; SSE2-NEXT: testl $1024, %eax ## imm = 0x400 -; SSE2-NEXT: jne LBB6_21 -; SSE2-NEXT: LBB6_22: ## %else29 +; SSE2-NEXT: jne LBB6_43 +; SSE2-NEXT: LBB6_11: ## %else29 ; SSE2-NEXT: testl $2048, %eax ## imm = 0x800 -; SSE2-NEXT: jne LBB6_23 -; SSE2-NEXT: LBB6_24: ## %else32 +; SSE2-NEXT: jne LBB6_44 +; SSE2-NEXT: LBB6_12: ## %else32 ; SSE2-NEXT: testl $4096, %eax ## imm = 0x1000 -; SSE2-NEXT: jne LBB6_25 -; SSE2-NEXT: LBB6_26: ## %else35 +; SSE2-NEXT: jne LBB6_45 +; SSE2-NEXT: LBB6_13: ## %else35 ; SSE2-NEXT: testl $8192, %eax ## imm = 0x2000 -; SSE2-NEXT: jne LBB6_27 -; SSE2-NEXT: LBB6_28: ## %else38 +; SSE2-NEXT: jne LBB6_46 +; SSE2-NEXT: LBB6_14: ## %else38 ; SSE2-NEXT: testl $16384, %eax ## imm = 0x4000 -; SSE2-NEXT: jne LBB6_29 -; SSE2-NEXT: LBB6_30: ## %else41 +; SSE2-NEXT: jne LBB6_47 +; SSE2-NEXT: LBB6_15: ## %else41 ; SSE2-NEXT: testw %ax, %ax -; SSE2-NEXT: js LBB6_31 -; SSE2-NEXT: LBB6_32: ## %else44 +; SSE2-NEXT: js LBB6_48 +; SSE2-NEXT: LBB6_16: ## %else44 ; SSE2-NEXT: testl $65536, %eax ## imm = 0x10000 -; SSE2-NEXT: jne LBB6_33 -; SSE2-NEXT: LBB6_34: ## %else47 +; SSE2-NEXT: jne LBB6_49 +; SSE2-NEXT: LBB6_17: ## %else47 ; SSE2-NEXT: testl $131072, %eax ## imm = 0x20000 -; SSE2-NEXT: jne LBB6_35 -; SSE2-NEXT: LBB6_36: ## %else50 +; SSE2-NEXT: jne LBB6_50 +; SSE2-NEXT: LBB6_18: ## %else50 ; SSE2-NEXT: testl $262144, %eax ## imm = 0x40000 -; SSE2-NEXT: jne LBB6_37 -; SSE2-NEXT: LBB6_38: ## %else53 +; SSE2-NEXT: jne LBB6_51 +; SSE2-NEXT: LBB6_19: ## %else53 ; SSE2-NEXT: testl $524288, %eax ## imm = 0x80000 -; SSE2-NEXT: jne LBB6_39 -; SSE2-NEXT: LBB6_40: ## %else56 +; SSE2-NEXT: jne LBB6_52 +; SSE2-NEXT: LBB6_20: ## %else56 ; SSE2-NEXT: testl $1048576, %eax ## imm = 0x100000 -; SSE2-NEXT: jne LBB6_41 -; SSE2-NEXT: LBB6_42: ## %else59 +; SSE2-NEXT: jne LBB6_53 +; SSE2-NEXT: LBB6_21: ## %else59 ; SSE2-NEXT: testl $2097152, %eax ## imm = 0x200000 -; SSE2-NEXT: jne LBB6_43 -; SSE2-NEXT: LBB6_44: ## %else62 +; SSE2-NEXT: jne LBB6_54 +; SSE2-NEXT: LBB6_22: ## %else62 ; SSE2-NEXT: testl $4194304, %eax ## imm = 0x400000 -; SSE2-NEXT: jne LBB6_45 -; SSE2-NEXT: LBB6_46: ## %else65 +; SSE2-NEXT: jne LBB6_55 +; SSE2-NEXT: LBB6_23: ## %else65 ; SSE2-NEXT: testl $8388608, %eax ## imm = 0x800000 -; SSE2-NEXT: jne LBB6_47 -; SSE2-NEXT: LBB6_48: ## %else68 +; SSE2-NEXT: jne LBB6_56 +; SSE2-NEXT: LBB6_24: ## %else68 ; SSE2-NEXT: testl $16777216, %eax ## imm = 0x1000000 -; SSE2-NEXT: jne LBB6_49 -; SSE2-NEXT: LBB6_50: ## %else71 +; SSE2-NEXT: jne LBB6_57 +; SSE2-NEXT: LBB6_25: ## %else71 ; SSE2-NEXT: testl $33554432, %eax ## imm = 0x2000000 -; SSE2-NEXT: jne LBB6_51 -; SSE2-NEXT: LBB6_52: ## %else74 +; SSE2-NEXT: jne LBB6_58 +; SSE2-NEXT: LBB6_26: ## %else74 ; SSE2-NEXT: testl $67108864, %eax ## imm = 0x4000000 -; SSE2-NEXT: jne LBB6_53 -; SSE2-NEXT: LBB6_54: ## %else77 +; SSE2-NEXT: jne LBB6_59 +; SSE2-NEXT: LBB6_27: ## %else77 ; SSE2-NEXT: testl $134217728, %eax ## imm = 0x8000000 -; SSE2-NEXT: jne LBB6_55 -; SSE2-NEXT: LBB6_56: ## %else80 +; SSE2-NEXT: jne LBB6_60 +; SSE2-NEXT: LBB6_28: ## %else80 ; SSE2-NEXT: testl $268435456, %eax ## imm = 0x10000000 -; SSE2-NEXT: jne LBB6_57 -; SSE2-NEXT: LBB6_58: ## %else83 +; SSE2-NEXT: jne LBB6_61 +; SSE2-NEXT: LBB6_29: ## %else83 ; SSE2-NEXT: testl $536870912, %eax ## imm = 0x20000000 -; SSE2-NEXT: jne LBB6_59 -; SSE2-NEXT: LBB6_60: ## %else86 +; SSE2-NEXT: jne LBB6_62 +; SSE2-NEXT: LBB6_30: ## %else86 ; SSE2-NEXT: testl $1073741824, %eax ## imm = 0x40000000 -; SSE2-NEXT: jne LBB6_61 -; SSE2-NEXT: LBB6_62: ## %else89 -; SSE2-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 ; SSE2-NEXT: jne LBB6_63 -; SSE2-NEXT: LBB6_64: ## %else92 +; SSE2-NEXT: LBB6_31: ## %else89 +; SSE2-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 +; SSE2-NEXT: jne LBB6_64 +; SSE2-NEXT: LBB6_32: ## %else92 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB6_1: ## %cond.store +; SSE2-NEXT: LBB6_33: ## %cond.store ; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB6_4 -; SSE2-NEXT: LBB6_3: ## %cond.store1 +; SSE2-NEXT: je LBB6_2 +; SSE2-NEXT: LBB6_34: ## %cond.store1 ; SSE2-NEXT: movaps %xmm0, %xmm8 ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[1,1],xmm0[1,1] ; SSE2-NEXT: movss %xmm8, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB6_6 -; SSE2-NEXT: LBB6_5: ## %cond.store4 +; SSE2-NEXT: je LBB6_3 +; SSE2-NEXT: LBB6_35: ## %cond.store4 ; SSE2-NEXT: movaps %xmm0, %xmm8 ; SSE2-NEXT: unpckhpd {{.*#+}} xmm8 = xmm8[1],xmm0[1] ; SSE2-NEXT: movss %xmm8, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB6_8 -; SSE2-NEXT: LBB6_7: ## %cond.store7 +; SSE2-NEXT: je LBB6_4 +; SSE2-NEXT: LBB6_36: ## %cond.store7 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: je LBB6_10 -; SSE2-NEXT: LBB6_9: ## %cond.store10 +; SSE2-NEXT: je LBB6_5 +; SSE2-NEXT: LBB6_37: ## %cond.store10 ; SSE2-NEXT: movss %xmm1, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je LBB6_12 -; SSE2-NEXT: LBB6_11: ## %cond.store13 +; SSE2-NEXT: je LBB6_6 +; SSE2-NEXT: LBB6_38: ## %cond.store13 ; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1] ; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: je LBB6_14 -; SSE2-NEXT: LBB6_13: ## %cond.store16 +; SSE2-NEXT: je LBB6_7 +; SSE2-NEXT: LBB6_39: ## %cond.store16 ; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1] ; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testb %al, %al -; SSE2-NEXT: jns LBB6_16 -; SSE2-NEXT: LBB6_15: ## %cond.store19 +; SSE2-NEXT: jns LBB6_8 +; SSE2-NEXT: LBB6_40: ## %cond.store19 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE2-NEXT: movss %xmm1, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testl $256, %eax ## imm = 0x100 -; SSE2-NEXT: je LBB6_18 -; SSE2-NEXT: LBB6_17: ## %cond.store22 +; SSE2-NEXT: je LBB6_9 +; SSE2-NEXT: LBB6_41: ## %cond.store22 ; SSE2-NEXT: movss %xmm2, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testl $512, %eax ## imm = 0x200 -; SSE2-NEXT: je LBB6_20 -; SSE2-NEXT: LBB6_19: ## %cond.store25 +; SSE2-NEXT: je LBB6_10 +; SSE2-NEXT: LBB6_42: ## %cond.store25 ; SSE2-NEXT: movaps %xmm2, %xmm0 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm2[1,1] ; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testl $1024, %eax ## imm = 0x400 -; SSE2-NEXT: je LBB6_22 -; SSE2-NEXT: LBB6_21: ## %cond.store28 +; SSE2-NEXT: je LBB6_11 +; SSE2-NEXT: LBB6_43: ## %cond.store28 ; SSE2-NEXT: movaps %xmm2, %xmm0 ; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm2[1] ; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testl $2048, %eax ## imm = 0x800 -; SSE2-NEXT: je LBB6_24 -; SSE2-NEXT: LBB6_23: ## %cond.store31 +; SSE2-NEXT: je LBB6_12 +; SSE2-NEXT: LBB6_44: ## %cond.store31 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3] ; SSE2-NEXT: movss %xmm2, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testl $4096, %eax ## imm = 0x1000 -; SSE2-NEXT: je LBB6_26 -; SSE2-NEXT: LBB6_25: ## %cond.store34 +; SSE2-NEXT: je LBB6_13 +; SSE2-NEXT: LBB6_45: ## %cond.store34 ; SSE2-NEXT: movss %xmm3, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testl $8192, %eax ## imm = 0x2000 -; SSE2-NEXT: je LBB6_28 -; SSE2-NEXT: LBB6_27: ## %cond.store37 +; SSE2-NEXT: je LBB6_14 +; SSE2-NEXT: LBB6_46: ## %cond.store37 ; SSE2-NEXT: movaps %xmm3, %xmm0 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm3[1,1] ; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testl $16384, %eax ## imm = 0x4000 -; SSE2-NEXT: je LBB6_30 -; SSE2-NEXT: LBB6_29: ## %cond.store40 +; SSE2-NEXT: je LBB6_15 +; SSE2-NEXT: LBB6_47: ## %cond.store40 ; SSE2-NEXT: movaps %xmm3, %xmm0 ; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm3[1] ; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testw %ax, %ax -; SSE2-NEXT: jns LBB6_32 -; SSE2-NEXT: LBB6_31: ## %cond.store43 +; SSE2-NEXT: jns LBB6_16 +; SSE2-NEXT: LBB6_48: ## %cond.store43 ; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3] ; SSE2-NEXT: movss %xmm3, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testl $65536, %eax ## imm = 0x10000 -; SSE2-NEXT: je LBB6_34 -; SSE2-NEXT: LBB6_33: ## %cond.store46 +; SSE2-NEXT: je LBB6_17 +; SSE2-NEXT: LBB6_49: ## %cond.store46 ; SSE2-NEXT: movss %xmm4, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testl $131072, %eax ## imm = 0x20000 -; SSE2-NEXT: je LBB6_36 -; SSE2-NEXT: LBB6_35: ## %cond.store49 +; SSE2-NEXT: je LBB6_18 +; SSE2-NEXT: LBB6_50: ## %cond.store49 ; SSE2-NEXT: movaps %xmm4, %xmm0 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm4[1,1] ; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testl $262144, %eax ## imm = 0x40000 -; SSE2-NEXT: je LBB6_38 -; SSE2-NEXT: LBB6_37: ## %cond.store52 +; SSE2-NEXT: je LBB6_19 +; SSE2-NEXT: LBB6_51: ## %cond.store52 ; SSE2-NEXT: movaps %xmm4, %xmm0 ; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm4[1] ; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testl $524288, %eax ## imm = 0x80000 -; SSE2-NEXT: je LBB6_40 -; SSE2-NEXT: LBB6_39: ## %cond.store55 +; SSE2-NEXT: je LBB6_20 +; SSE2-NEXT: LBB6_52: ## %cond.store55 ; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[3,3,3,3] ; SSE2-NEXT: movss %xmm4, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testl $1048576, %eax ## imm = 0x100000 -; SSE2-NEXT: je LBB6_42 -; SSE2-NEXT: LBB6_41: ## %cond.store58 +; SSE2-NEXT: je LBB6_21 +; SSE2-NEXT: LBB6_53: ## %cond.store58 ; SSE2-NEXT: movss %xmm5, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testl $2097152, %eax ## imm = 0x200000 -; SSE2-NEXT: je LBB6_44 -; SSE2-NEXT: LBB6_43: ## %cond.store61 +; SSE2-NEXT: je LBB6_22 +; SSE2-NEXT: LBB6_54: ## %cond.store61 ; SSE2-NEXT: movaps %xmm5, %xmm0 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm5[1,1] ; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testl $4194304, %eax ## imm = 0x400000 -; SSE2-NEXT: je LBB6_46 -; SSE2-NEXT: LBB6_45: ## %cond.store64 +; SSE2-NEXT: je LBB6_23 +; SSE2-NEXT: LBB6_55: ## %cond.store64 ; SSE2-NEXT: movaps %xmm5, %xmm0 ; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm5[1] ; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testl $8388608, %eax ## imm = 0x800000 -; SSE2-NEXT: je LBB6_48 -; SSE2-NEXT: LBB6_47: ## %cond.store67 +; SSE2-NEXT: je LBB6_24 +; SSE2-NEXT: LBB6_56: ## %cond.store67 ; SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,3,3,3] ; SSE2-NEXT: movss %xmm5, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testl $16777216, %eax ## imm = 0x1000000 -; SSE2-NEXT: je LBB6_50 -; SSE2-NEXT: LBB6_49: ## %cond.store70 +; SSE2-NEXT: je LBB6_25 +; SSE2-NEXT: LBB6_57: ## %cond.store70 ; SSE2-NEXT: movss %xmm6, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testl $33554432, %eax ## imm = 0x2000000 -; SSE2-NEXT: je LBB6_52 -; SSE2-NEXT: LBB6_51: ## %cond.store73 +; SSE2-NEXT: je LBB6_26 +; SSE2-NEXT: LBB6_58: ## %cond.store73 ; SSE2-NEXT: movaps %xmm6, %xmm0 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm6[1,1] ; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testl $67108864, %eax ## imm = 0x4000000 -; SSE2-NEXT: je LBB6_54 -; SSE2-NEXT: LBB6_53: ## %cond.store76 +; SSE2-NEXT: je LBB6_27 +; SSE2-NEXT: LBB6_59: ## %cond.store76 ; SSE2-NEXT: movaps %xmm6, %xmm0 ; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm6[1] ; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testl $134217728, %eax ## imm = 0x8000000 -; SSE2-NEXT: je LBB6_56 -; SSE2-NEXT: LBB6_55: ## %cond.store79 +; SSE2-NEXT: je LBB6_28 +; SSE2-NEXT: LBB6_60: ## %cond.store79 ; SSE2-NEXT: shufps {{.*#+}} xmm6 = xmm6[3,3,3,3] ; SSE2-NEXT: movss %xmm6, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testl $268435456, %eax ## imm = 0x10000000 -; SSE2-NEXT: je LBB6_58 -; SSE2-NEXT: LBB6_57: ## %cond.store82 +; SSE2-NEXT: je LBB6_29 +; SSE2-NEXT: LBB6_61: ## %cond.store82 ; SSE2-NEXT: movss %xmm7, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testl $536870912, %eax ## imm = 0x20000000 -; SSE2-NEXT: je LBB6_60 -; SSE2-NEXT: LBB6_59: ## %cond.store85 +; SSE2-NEXT: je LBB6_30 +; SSE2-NEXT: LBB6_62: ## %cond.store85 ; SSE2-NEXT: movaps %xmm7, %xmm0 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm7[1,1] ; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testl $1073741824, %eax ## imm = 0x40000000 -; SSE2-NEXT: je LBB6_62 -; SSE2-NEXT: LBB6_61: ## %cond.store88 +; SSE2-NEXT: je LBB6_31 +; SSE2-NEXT: LBB6_63: ## %cond.store88 ; SSE2-NEXT: movaps %xmm7, %xmm0 ; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm7[1] ; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 -; SSE2-NEXT: je LBB6_64 -; SSE2-NEXT: LBB6_63: ## %cond.store91 +; SSE2-NEXT: je LBB6_32 +; SSE2-NEXT: LBB6_64: ## %cond.store91 ; SSE2-NEXT: shufps {{.*#+}} xmm7 = xmm7[3,3,3,3] ; SSE2-NEXT: movss %xmm7, (%rdi) ; SSE2-NEXT: retq @@ -1587,258 +1587,258 @@ define void @compressstore_v32f32_v32i32(ptr %base, <32 x float> %V, <32 x i32> ; SSE42-NEXT: shll $16, %eax ; SSE42-NEXT: orl %ecx, %eax ; SSE42-NEXT: testb $1, %al -; SSE42-NEXT: jne LBB6_1 -; SSE42-NEXT: ## %bb.2: ## %else +; SSE42-NEXT: jne LBB6_33 +; SSE42-NEXT: ## %bb.1: ## %else ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: jne LBB6_3 -; SSE42-NEXT: LBB6_4: ## %else2 +; SSE42-NEXT: jne LBB6_34 +; SSE42-NEXT: LBB6_2: ## %else2 ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: jne LBB6_5 -; SSE42-NEXT: LBB6_6: ## %else5 +; SSE42-NEXT: jne LBB6_35 +; SSE42-NEXT: LBB6_3: ## %else5 ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: jne LBB6_7 -; SSE42-NEXT: LBB6_8: ## %else8 +; SSE42-NEXT: jne LBB6_36 +; SSE42-NEXT: LBB6_4: ## %else8 ; SSE42-NEXT: testb $16, %al -; SSE42-NEXT: jne LBB6_9 -; SSE42-NEXT: LBB6_10: ## %else11 +; SSE42-NEXT: jne LBB6_37 +; SSE42-NEXT: LBB6_5: ## %else11 ; SSE42-NEXT: testb $32, %al -; SSE42-NEXT: jne LBB6_11 -; SSE42-NEXT: LBB6_12: ## %else14 +; SSE42-NEXT: jne LBB6_38 +; SSE42-NEXT: LBB6_6: ## %else14 ; SSE42-NEXT: testb $64, %al -; SSE42-NEXT: jne LBB6_13 -; SSE42-NEXT: LBB6_14: ## %else17 +; SSE42-NEXT: jne LBB6_39 +; SSE42-NEXT: LBB6_7: ## %else17 ; SSE42-NEXT: testb %al, %al -; SSE42-NEXT: js LBB6_15 -; SSE42-NEXT: LBB6_16: ## %else20 +; SSE42-NEXT: js LBB6_40 +; SSE42-NEXT: LBB6_8: ## %else20 ; SSE42-NEXT: testl $256, %eax ## imm = 0x100 -; SSE42-NEXT: jne LBB6_17 -; SSE42-NEXT: LBB6_18: ## %else23 +; SSE42-NEXT: jne LBB6_41 +; SSE42-NEXT: LBB6_9: ## %else23 ; SSE42-NEXT: testl $512, %eax ## imm = 0x200 -; SSE42-NEXT: jne LBB6_19 -; SSE42-NEXT: LBB6_20: ## %else26 +; SSE42-NEXT: jne LBB6_42 +; SSE42-NEXT: LBB6_10: ## %else26 ; SSE42-NEXT: testl $1024, %eax ## imm = 0x400 -; SSE42-NEXT: jne LBB6_21 -; SSE42-NEXT: LBB6_22: ## %else29 +; SSE42-NEXT: jne LBB6_43 +; SSE42-NEXT: LBB6_11: ## %else29 ; SSE42-NEXT: testl $2048, %eax ## imm = 0x800 -; SSE42-NEXT: jne LBB6_23 -; SSE42-NEXT: LBB6_24: ## %else32 +; SSE42-NEXT: jne LBB6_44 +; SSE42-NEXT: LBB6_12: ## %else32 ; SSE42-NEXT: testl $4096, %eax ## imm = 0x1000 -; SSE42-NEXT: jne LBB6_25 -; SSE42-NEXT: LBB6_26: ## %else35 +; SSE42-NEXT: jne LBB6_45 +; SSE42-NEXT: LBB6_13: ## %else35 ; SSE42-NEXT: testl $8192, %eax ## imm = 0x2000 -; SSE42-NEXT: jne LBB6_27 -; SSE42-NEXT: LBB6_28: ## %else38 +; SSE42-NEXT: jne LBB6_46 +; SSE42-NEXT: LBB6_14: ## %else38 ; SSE42-NEXT: testl $16384, %eax ## imm = 0x4000 -; SSE42-NEXT: jne LBB6_29 -; SSE42-NEXT: LBB6_30: ## %else41 +; SSE42-NEXT: jne LBB6_47 +; SSE42-NEXT: LBB6_15: ## %else41 ; SSE42-NEXT: testw %ax, %ax -; SSE42-NEXT: js LBB6_31 -; SSE42-NEXT: LBB6_32: ## %else44 +; SSE42-NEXT: js LBB6_48 +; SSE42-NEXT: LBB6_16: ## %else44 ; SSE42-NEXT: testl $65536, %eax ## imm = 0x10000 -; SSE42-NEXT: jne LBB6_33 -; SSE42-NEXT: LBB6_34: ## %else47 +; SSE42-NEXT: jne LBB6_49 +; SSE42-NEXT: LBB6_17: ## %else47 ; SSE42-NEXT: testl $131072, %eax ## imm = 0x20000 -; SSE42-NEXT: jne LBB6_35 -; SSE42-NEXT: LBB6_36: ## %else50 +; SSE42-NEXT: jne LBB6_50 +; SSE42-NEXT: LBB6_18: ## %else50 ; SSE42-NEXT: testl $262144, %eax ## imm = 0x40000 -; SSE42-NEXT: jne LBB6_37 -; SSE42-NEXT: LBB6_38: ## %else53 +; SSE42-NEXT: jne LBB6_51 +; SSE42-NEXT: LBB6_19: ## %else53 ; SSE42-NEXT: testl $524288, %eax ## imm = 0x80000 -; SSE42-NEXT: jne LBB6_39 -; SSE42-NEXT: LBB6_40: ## %else56 +; SSE42-NEXT: jne LBB6_52 +; SSE42-NEXT: LBB6_20: ## %else56 ; SSE42-NEXT: testl $1048576, %eax ## imm = 0x100000 -; SSE42-NEXT: jne LBB6_41 -; SSE42-NEXT: LBB6_42: ## %else59 +; SSE42-NEXT: jne LBB6_53 +; SSE42-NEXT: LBB6_21: ## %else59 ; SSE42-NEXT: testl $2097152, %eax ## imm = 0x200000 -; SSE42-NEXT: jne LBB6_43 -; SSE42-NEXT: LBB6_44: ## %else62 +; SSE42-NEXT: jne LBB6_54 +; SSE42-NEXT: LBB6_22: ## %else62 ; SSE42-NEXT: testl $4194304, %eax ## imm = 0x400000 -; SSE42-NEXT: jne LBB6_45 -; SSE42-NEXT: LBB6_46: ## %else65 +; SSE42-NEXT: jne LBB6_55 +; SSE42-NEXT: LBB6_23: ## %else65 ; SSE42-NEXT: testl $8388608, %eax ## imm = 0x800000 -; SSE42-NEXT: jne LBB6_47 -; SSE42-NEXT: LBB6_48: ## %else68 +; SSE42-NEXT: jne LBB6_56 +; SSE42-NEXT: LBB6_24: ## %else68 ; SSE42-NEXT: testl $16777216, %eax ## imm = 0x1000000 -; SSE42-NEXT: jne LBB6_49 -; SSE42-NEXT: LBB6_50: ## %else71 +; SSE42-NEXT: jne LBB6_57 +; SSE42-NEXT: LBB6_25: ## %else71 ; SSE42-NEXT: testl $33554432, %eax ## imm = 0x2000000 -; SSE42-NEXT: jne LBB6_51 -; SSE42-NEXT: LBB6_52: ## %else74 +; SSE42-NEXT: jne LBB6_58 +; SSE42-NEXT: LBB6_26: ## %else74 ; SSE42-NEXT: testl $67108864, %eax ## imm = 0x4000000 -; SSE42-NEXT: jne LBB6_53 -; SSE42-NEXT: LBB6_54: ## %else77 +; SSE42-NEXT: jne LBB6_59 +; SSE42-NEXT: LBB6_27: ## %else77 ; SSE42-NEXT: testl $134217728, %eax ## imm = 0x8000000 -; SSE42-NEXT: jne LBB6_55 -; SSE42-NEXT: LBB6_56: ## %else80 +; SSE42-NEXT: jne LBB6_60 +; SSE42-NEXT: LBB6_28: ## %else80 ; SSE42-NEXT: testl $268435456, %eax ## imm = 0x10000000 -; SSE42-NEXT: jne LBB6_57 -; SSE42-NEXT: LBB6_58: ## %else83 +; SSE42-NEXT: jne LBB6_61 +; SSE42-NEXT: LBB6_29: ## %else83 ; SSE42-NEXT: testl $536870912, %eax ## imm = 0x20000000 -; SSE42-NEXT: jne LBB6_59 -; SSE42-NEXT: LBB6_60: ## %else86 +; SSE42-NEXT: jne LBB6_62 +; SSE42-NEXT: LBB6_30: ## %else86 ; SSE42-NEXT: testl $1073741824, %eax ## imm = 0x40000000 -; SSE42-NEXT: jne LBB6_61 -; SSE42-NEXT: LBB6_62: ## %else89 -; SSE42-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 ; SSE42-NEXT: jne LBB6_63 -; SSE42-NEXT: LBB6_64: ## %else92 +; SSE42-NEXT: LBB6_31: ## %else89 +; SSE42-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 +; SSE42-NEXT: jne LBB6_64 +; SSE42-NEXT: LBB6_32: ## %else92 ; SSE42-NEXT: retq -; SSE42-NEXT: LBB6_1: ## %cond.store +; SSE42-NEXT: LBB6_33: ## %cond.store ; SSE42-NEXT: movss %xmm0, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: je LBB6_4 -; SSE42-NEXT: LBB6_3: ## %cond.store1 +; SSE42-NEXT: je LBB6_2 +; SSE42-NEXT: LBB6_34: ## %cond.store1 ; SSE42-NEXT: extractps $1, %xmm0, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: je LBB6_6 -; SSE42-NEXT: LBB6_5: ## %cond.store4 +; SSE42-NEXT: je LBB6_3 +; SSE42-NEXT: LBB6_35: ## %cond.store4 ; SSE42-NEXT: extractps $2, %xmm0, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: je LBB6_8 -; SSE42-NEXT: LBB6_7: ## %cond.store7 +; SSE42-NEXT: je LBB6_4 +; SSE42-NEXT: LBB6_36: ## %cond.store7 ; SSE42-NEXT: extractps $3, %xmm0, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testb $16, %al -; SSE42-NEXT: je LBB6_10 -; SSE42-NEXT: LBB6_9: ## %cond.store10 +; SSE42-NEXT: je LBB6_5 +; SSE42-NEXT: LBB6_37: ## %cond.store10 ; SSE42-NEXT: movss %xmm1, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testb $32, %al -; SSE42-NEXT: je LBB6_12 -; SSE42-NEXT: LBB6_11: ## %cond.store13 +; SSE42-NEXT: je LBB6_6 +; SSE42-NEXT: LBB6_38: ## %cond.store13 ; SSE42-NEXT: extractps $1, %xmm1, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testb $64, %al -; SSE42-NEXT: je LBB6_14 -; SSE42-NEXT: LBB6_13: ## %cond.store16 +; SSE42-NEXT: je LBB6_7 +; SSE42-NEXT: LBB6_39: ## %cond.store16 ; SSE42-NEXT: extractps $2, %xmm1, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testb %al, %al -; SSE42-NEXT: jns LBB6_16 -; SSE42-NEXT: LBB6_15: ## %cond.store19 +; SSE42-NEXT: jns LBB6_8 +; SSE42-NEXT: LBB6_40: ## %cond.store19 ; SSE42-NEXT: extractps $3, %xmm1, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testl $256, %eax ## imm = 0x100 -; SSE42-NEXT: je LBB6_18 -; SSE42-NEXT: LBB6_17: ## %cond.store22 +; SSE42-NEXT: je LBB6_9 +; SSE42-NEXT: LBB6_41: ## %cond.store22 ; SSE42-NEXT: movss %xmm2, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testl $512, %eax ## imm = 0x200 -; SSE42-NEXT: je LBB6_20 -; SSE42-NEXT: LBB6_19: ## %cond.store25 +; SSE42-NEXT: je LBB6_10 +; SSE42-NEXT: LBB6_42: ## %cond.store25 ; SSE42-NEXT: extractps $1, %xmm2, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testl $1024, %eax ## imm = 0x400 -; SSE42-NEXT: je LBB6_22 -; SSE42-NEXT: LBB6_21: ## %cond.store28 +; SSE42-NEXT: je LBB6_11 +; SSE42-NEXT: LBB6_43: ## %cond.store28 ; SSE42-NEXT: extractps $2, %xmm2, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testl $2048, %eax ## imm = 0x800 -; SSE42-NEXT: je LBB6_24 -; SSE42-NEXT: LBB6_23: ## %cond.store31 +; SSE42-NEXT: je LBB6_12 +; SSE42-NEXT: LBB6_44: ## %cond.store31 ; SSE42-NEXT: extractps $3, %xmm2, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testl $4096, %eax ## imm = 0x1000 -; SSE42-NEXT: je LBB6_26 -; SSE42-NEXT: LBB6_25: ## %cond.store34 +; SSE42-NEXT: je LBB6_13 +; SSE42-NEXT: LBB6_45: ## %cond.store34 ; SSE42-NEXT: movss %xmm3, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testl $8192, %eax ## imm = 0x2000 -; SSE42-NEXT: je LBB6_28 -; SSE42-NEXT: LBB6_27: ## %cond.store37 +; SSE42-NEXT: je LBB6_14 +; SSE42-NEXT: LBB6_46: ## %cond.store37 ; SSE42-NEXT: extractps $1, %xmm3, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testl $16384, %eax ## imm = 0x4000 -; SSE42-NEXT: je LBB6_30 -; SSE42-NEXT: LBB6_29: ## %cond.store40 +; SSE42-NEXT: je LBB6_15 +; SSE42-NEXT: LBB6_47: ## %cond.store40 ; SSE42-NEXT: extractps $2, %xmm3, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testw %ax, %ax -; SSE42-NEXT: jns LBB6_32 -; SSE42-NEXT: LBB6_31: ## %cond.store43 +; SSE42-NEXT: jns LBB6_16 +; SSE42-NEXT: LBB6_48: ## %cond.store43 ; SSE42-NEXT: extractps $3, %xmm3, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testl $65536, %eax ## imm = 0x10000 -; SSE42-NEXT: je LBB6_34 -; SSE42-NEXT: LBB6_33: ## %cond.store46 +; SSE42-NEXT: je LBB6_17 +; SSE42-NEXT: LBB6_49: ## %cond.store46 ; SSE42-NEXT: movss %xmm4, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testl $131072, %eax ## imm = 0x20000 -; SSE42-NEXT: je LBB6_36 -; SSE42-NEXT: LBB6_35: ## %cond.store49 +; SSE42-NEXT: je LBB6_18 +; SSE42-NEXT: LBB6_50: ## %cond.store49 ; SSE42-NEXT: extractps $1, %xmm4, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testl $262144, %eax ## imm = 0x40000 -; SSE42-NEXT: je LBB6_38 -; SSE42-NEXT: LBB6_37: ## %cond.store52 +; SSE42-NEXT: je LBB6_19 +; SSE42-NEXT: LBB6_51: ## %cond.store52 ; SSE42-NEXT: extractps $2, %xmm4, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testl $524288, %eax ## imm = 0x80000 -; SSE42-NEXT: je LBB6_40 -; SSE42-NEXT: LBB6_39: ## %cond.store55 +; SSE42-NEXT: je LBB6_20 +; SSE42-NEXT: LBB6_52: ## %cond.store55 ; SSE42-NEXT: extractps $3, %xmm4, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testl $1048576, %eax ## imm = 0x100000 -; SSE42-NEXT: je LBB6_42 -; SSE42-NEXT: LBB6_41: ## %cond.store58 +; SSE42-NEXT: je LBB6_21 +; SSE42-NEXT: LBB6_53: ## %cond.store58 ; SSE42-NEXT: movss %xmm5, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testl $2097152, %eax ## imm = 0x200000 -; SSE42-NEXT: je LBB6_44 -; SSE42-NEXT: LBB6_43: ## %cond.store61 +; SSE42-NEXT: je LBB6_22 +; SSE42-NEXT: LBB6_54: ## %cond.store61 ; SSE42-NEXT: extractps $1, %xmm5, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testl $4194304, %eax ## imm = 0x400000 -; SSE42-NEXT: je LBB6_46 -; SSE42-NEXT: LBB6_45: ## %cond.store64 +; SSE42-NEXT: je LBB6_23 +; SSE42-NEXT: LBB6_55: ## %cond.store64 ; SSE42-NEXT: extractps $2, %xmm5, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testl $8388608, %eax ## imm = 0x800000 -; SSE42-NEXT: je LBB6_48 -; SSE42-NEXT: LBB6_47: ## %cond.store67 +; SSE42-NEXT: je LBB6_24 +; SSE42-NEXT: LBB6_56: ## %cond.store67 ; SSE42-NEXT: extractps $3, %xmm5, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testl $16777216, %eax ## imm = 0x1000000 -; SSE42-NEXT: je LBB6_50 -; SSE42-NEXT: LBB6_49: ## %cond.store70 +; SSE42-NEXT: je LBB6_25 +; SSE42-NEXT: LBB6_57: ## %cond.store70 ; SSE42-NEXT: movss %xmm6, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testl $33554432, %eax ## imm = 0x2000000 -; SSE42-NEXT: je LBB6_52 -; SSE42-NEXT: LBB6_51: ## %cond.store73 +; SSE42-NEXT: je LBB6_26 +; SSE42-NEXT: LBB6_58: ## %cond.store73 ; SSE42-NEXT: extractps $1, %xmm6, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testl $67108864, %eax ## imm = 0x4000000 -; SSE42-NEXT: je LBB6_54 -; SSE42-NEXT: LBB6_53: ## %cond.store76 +; SSE42-NEXT: je LBB6_27 +; SSE42-NEXT: LBB6_59: ## %cond.store76 ; SSE42-NEXT: extractps $2, %xmm6, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testl $134217728, %eax ## imm = 0x8000000 -; SSE42-NEXT: je LBB6_56 -; SSE42-NEXT: LBB6_55: ## %cond.store79 +; SSE42-NEXT: je LBB6_28 +; SSE42-NEXT: LBB6_60: ## %cond.store79 ; SSE42-NEXT: extractps $3, %xmm6, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testl $268435456, %eax ## imm = 0x10000000 -; SSE42-NEXT: je LBB6_58 -; SSE42-NEXT: LBB6_57: ## %cond.store82 +; SSE42-NEXT: je LBB6_29 +; SSE42-NEXT: LBB6_61: ## %cond.store82 ; SSE42-NEXT: movss %xmm7, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testl $536870912, %eax ## imm = 0x20000000 -; SSE42-NEXT: je LBB6_60 -; SSE42-NEXT: LBB6_59: ## %cond.store85 +; SSE42-NEXT: je LBB6_30 +; SSE42-NEXT: LBB6_62: ## %cond.store85 ; SSE42-NEXT: extractps $1, %xmm7, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testl $1073741824, %eax ## imm = 0x40000000 -; SSE42-NEXT: je LBB6_62 -; SSE42-NEXT: LBB6_61: ## %cond.store88 +; SSE42-NEXT: je LBB6_31 +; SSE42-NEXT: LBB6_63: ## %cond.store88 ; SSE42-NEXT: extractps $2, %xmm7, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 -; SSE42-NEXT: je LBB6_64 -; SSE42-NEXT: LBB6_63: ## %cond.store91 +; SSE42-NEXT: je LBB6_32 +; SSE42-NEXT: LBB6_64: ## %cond.store91 ; SSE42-NEXT: extractps $3, %xmm7, (%rdi) ; SSE42-NEXT: retq ; @@ -1868,259 +1868,259 @@ define void @compressstore_v32f32_v32i32(ptr %base, <32 x float> %V, <32 x i32> ; AVX1-NEXT: shll $16, %eax ; AVX1-NEXT: orl %ecx, %eax ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne LBB6_1 -; AVX1-NEXT: ## %bb.2: ## %else +; AVX1-NEXT: jne LBB6_37 +; AVX1-NEXT: ## %bb.1: ## %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne LBB6_3 -; AVX1-NEXT: LBB6_4: ## %else2 +; AVX1-NEXT: jne LBB6_38 +; AVX1-NEXT: LBB6_2: ## %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne LBB6_5 -; AVX1-NEXT: LBB6_6: ## %else5 +; AVX1-NEXT: jne LBB6_39 +; AVX1-NEXT: LBB6_3: ## %else5 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je LBB6_8 -; AVX1-NEXT: LBB6_7: ## %cond.store7 +; AVX1-NEXT: je LBB6_5 +; AVX1-NEXT: LBB6_4: ## %cond.store7 ; AVX1-NEXT: vextractps $3, %xmm0, (%rdi) ; AVX1-NEXT: addq $4, %rdi -; AVX1-NEXT: LBB6_8: ## %else8 +; AVX1-NEXT: LBB6_5: ## %else8 ; AVX1-NEXT: testb $16, %al ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 -; AVX1-NEXT: jne LBB6_9 -; AVX1-NEXT: ## %bb.10: ## %else11 +; AVX1-NEXT: jne LBB6_40 +; AVX1-NEXT: ## %bb.6: ## %else11 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: jne LBB6_11 -; AVX1-NEXT: LBB6_12: ## %else14 +; AVX1-NEXT: jne LBB6_41 +; AVX1-NEXT: LBB6_7: ## %else14 ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: jne LBB6_13 -; AVX1-NEXT: LBB6_14: ## %else17 +; AVX1-NEXT: jne LBB6_42 +; AVX1-NEXT: LBB6_8: ## %else17 ; AVX1-NEXT: testb %al, %al -; AVX1-NEXT: js LBB6_15 -; AVX1-NEXT: LBB6_16: ## %else20 +; AVX1-NEXT: js LBB6_43 +; AVX1-NEXT: LBB6_9: ## %else20 ; AVX1-NEXT: testl $256, %eax ## imm = 0x100 -; AVX1-NEXT: jne LBB6_17 -; AVX1-NEXT: LBB6_18: ## %else23 +; AVX1-NEXT: jne LBB6_44 +; AVX1-NEXT: LBB6_10: ## %else23 ; AVX1-NEXT: testl $512, %eax ## imm = 0x200 -; AVX1-NEXT: jne LBB6_19 -; AVX1-NEXT: LBB6_20: ## %else26 +; AVX1-NEXT: jne LBB6_45 +; AVX1-NEXT: LBB6_11: ## %else26 ; AVX1-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX1-NEXT: jne LBB6_21 -; AVX1-NEXT: LBB6_22: ## %else29 +; AVX1-NEXT: jne LBB6_46 +; AVX1-NEXT: LBB6_12: ## %else29 ; AVX1-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX1-NEXT: je LBB6_24 -; AVX1-NEXT: LBB6_23: ## %cond.store31 +; AVX1-NEXT: je LBB6_14 +; AVX1-NEXT: LBB6_13: ## %cond.store31 ; AVX1-NEXT: vextractps $3, %xmm1, (%rdi) ; AVX1-NEXT: addq $4, %rdi -; AVX1-NEXT: LBB6_24: ## %else32 +; AVX1-NEXT: LBB6_14: ## %else32 ; AVX1-NEXT: testl $4096, %eax ## imm = 0x1000 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm0 -; AVX1-NEXT: jne LBB6_25 -; AVX1-NEXT: ## %bb.26: ## %else35 +; AVX1-NEXT: jne LBB6_47 +; AVX1-NEXT: ## %bb.15: ## %else35 ; AVX1-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX1-NEXT: jne LBB6_27 -; AVX1-NEXT: LBB6_28: ## %else38 +; AVX1-NEXT: jne LBB6_48 +; AVX1-NEXT: LBB6_16: ## %else38 ; AVX1-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX1-NEXT: jne LBB6_29 -; AVX1-NEXT: LBB6_30: ## %else41 +; AVX1-NEXT: jne LBB6_49 +; AVX1-NEXT: LBB6_17: ## %else41 ; AVX1-NEXT: testw %ax, %ax -; AVX1-NEXT: js LBB6_31 -; AVX1-NEXT: LBB6_32: ## %else44 +; AVX1-NEXT: js LBB6_50 +; AVX1-NEXT: LBB6_18: ## %else44 ; AVX1-NEXT: testl $65536, %eax ## imm = 0x10000 -; AVX1-NEXT: jne LBB6_33 -; AVX1-NEXT: LBB6_34: ## %else47 +; AVX1-NEXT: jne LBB6_51 +; AVX1-NEXT: LBB6_19: ## %else47 ; AVX1-NEXT: testl $131072, %eax ## imm = 0x20000 -; AVX1-NEXT: jne LBB6_35 -; AVX1-NEXT: LBB6_36: ## %else50 +; AVX1-NEXT: jne LBB6_52 +; AVX1-NEXT: LBB6_20: ## %else50 ; AVX1-NEXT: testl $262144, %eax ## imm = 0x40000 -; AVX1-NEXT: jne LBB6_37 -; AVX1-NEXT: LBB6_38: ## %else53 +; AVX1-NEXT: jne LBB6_53 +; AVX1-NEXT: LBB6_21: ## %else53 ; AVX1-NEXT: testl $524288, %eax ## imm = 0x80000 -; AVX1-NEXT: je LBB6_40 -; AVX1-NEXT: LBB6_39: ## %cond.store55 +; AVX1-NEXT: je LBB6_23 +; AVX1-NEXT: LBB6_22: ## %cond.store55 ; AVX1-NEXT: vextractps $3, %xmm2, (%rdi) ; AVX1-NEXT: addq $4, %rdi -; AVX1-NEXT: LBB6_40: ## %else56 +; AVX1-NEXT: LBB6_23: ## %else56 ; AVX1-NEXT: testl $1048576, %eax ## imm = 0x100000 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm0 -; AVX1-NEXT: jne LBB6_41 -; AVX1-NEXT: ## %bb.42: ## %else59 +; AVX1-NEXT: jne LBB6_54 +; AVX1-NEXT: ## %bb.24: ## %else59 ; AVX1-NEXT: testl $2097152, %eax ## imm = 0x200000 -; AVX1-NEXT: jne LBB6_43 -; AVX1-NEXT: LBB6_44: ## %else62 +; AVX1-NEXT: jne LBB6_55 +; AVX1-NEXT: LBB6_25: ## %else62 ; AVX1-NEXT: testl $4194304, %eax ## imm = 0x400000 -; AVX1-NEXT: jne LBB6_45 -; AVX1-NEXT: LBB6_46: ## %else65 +; AVX1-NEXT: jne LBB6_56 +; AVX1-NEXT: LBB6_26: ## %else65 ; AVX1-NEXT: testl $8388608, %eax ## imm = 0x800000 -; AVX1-NEXT: jne LBB6_47 -; AVX1-NEXT: LBB6_48: ## %else68 +; AVX1-NEXT: jne LBB6_57 +; AVX1-NEXT: LBB6_27: ## %else68 ; AVX1-NEXT: testl $16777216, %eax ## imm = 0x1000000 -; AVX1-NEXT: jne LBB6_49 -; AVX1-NEXT: LBB6_50: ## %else71 +; AVX1-NEXT: jne LBB6_58 +; AVX1-NEXT: LBB6_28: ## %else71 ; AVX1-NEXT: testl $33554432, %eax ## imm = 0x2000000 -; AVX1-NEXT: jne LBB6_51 -; AVX1-NEXT: LBB6_52: ## %else74 +; AVX1-NEXT: jne LBB6_59 +; AVX1-NEXT: LBB6_29: ## %else74 ; AVX1-NEXT: testl $67108864, %eax ## imm = 0x4000000 -; AVX1-NEXT: jne LBB6_53 -; AVX1-NEXT: LBB6_54: ## %else77 +; AVX1-NEXT: jne LBB6_60 +; AVX1-NEXT: LBB6_30: ## %else77 ; AVX1-NEXT: testl $134217728, %eax ## imm = 0x8000000 -; AVX1-NEXT: je LBB6_56 -; AVX1-NEXT: LBB6_55: ## %cond.store79 +; AVX1-NEXT: je LBB6_32 +; AVX1-NEXT: LBB6_31: ## %cond.store79 ; AVX1-NEXT: vextractps $3, %xmm3, (%rdi) ; AVX1-NEXT: addq $4, %rdi -; AVX1-NEXT: LBB6_56: ## %else80 +; AVX1-NEXT: LBB6_32: ## %else80 ; AVX1-NEXT: testl $268435456, %eax ## imm = 0x10000000 ; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm0 -; AVX1-NEXT: jne LBB6_57 -; AVX1-NEXT: ## %bb.58: ## %else83 +; AVX1-NEXT: jne LBB6_61 +; AVX1-NEXT: ## %bb.33: ## %else83 ; AVX1-NEXT: testl $536870912, %eax ## imm = 0x20000000 -; AVX1-NEXT: jne LBB6_59 -; AVX1-NEXT: LBB6_60: ## %else86 +; AVX1-NEXT: jne LBB6_62 +; AVX1-NEXT: LBB6_34: ## %else86 ; AVX1-NEXT: testl $1073741824, %eax ## imm = 0x40000000 -; AVX1-NEXT: jne LBB6_61 -; AVX1-NEXT: LBB6_62: ## %else89 -; AVX1-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 ; AVX1-NEXT: jne LBB6_63 -; AVX1-NEXT: LBB6_64: ## %else92 +; AVX1-NEXT: LBB6_35: ## %else89 +; AVX1-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 +; AVX1-NEXT: jne LBB6_64 +; AVX1-NEXT: LBB6_36: ## %else92 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: LBB6_1: ## %cond.store +; AVX1-NEXT: LBB6_37: ## %cond.store ; AVX1-NEXT: vmovss %xmm0, (%rdi) ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je LBB6_4 -; AVX1-NEXT: LBB6_3: ## %cond.store1 +; AVX1-NEXT: je LBB6_2 +; AVX1-NEXT: LBB6_38: ## %cond.store1 ; AVX1-NEXT: vextractps $1, %xmm0, (%rdi) ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je LBB6_6 -; AVX1-NEXT: LBB6_5: ## %cond.store4 +; AVX1-NEXT: je LBB6_3 +; AVX1-NEXT: LBB6_39: ## %cond.store4 ; AVX1-NEXT: vextractps $2, %xmm0, (%rdi) ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne LBB6_7 -; AVX1-NEXT: jmp LBB6_8 -; AVX1-NEXT: LBB6_9: ## %cond.store10 +; AVX1-NEXT: jne LBB6_4 +; AVX1-NEXT: jmp LBB6_5 +; AVX1-NEXT: LBB6_40: ## %cond.store10 ; AVX1-NEXT: vmovss %xmm0, (%rdi) ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je LBB6_12 -; AVX1-NEXT: LBB6_11: ## %cond.store13 +; AVX1-NEXT: je LBB6_7 +; AVX1-NEXT: LBB6_41: ## %cond.store13 ; AVX1-NEXT: vextractps $1, %xmm0, (%rdi) ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: je LBB6_14 -; AVX1-NEXT: LBB6_13: ## %cond.store16 +; AVX1-NEXT: je LBB6_8 +; AVX1-NEXT: LBB6_42: ## %cond.store16 ; AVX1-NEXT: vextractps $2, %xmm0, (%rdi) ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testb %al, %al -; AVX1-NEXT: jns LBB6_16 -; AVX1-NEXT: LBB6_15: ## %cond.store19 +; AVX1-NEXT: jns LBB6_9 +; AVX1-NEXT: LBB6_43: ## %cond.store19 ; AVX1-NEXT: vextractps $3, %xmm0, (%rdi) ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $256, %eax ## imm = 0x100 -; AVX1-NEXT: je LBB6_18 -; AVX1-NEXT: LBB6_17: ## %cond.store22 +; AVX1-NEXT: je LBB6_10 +; AVX1-NEXT: LBB6_44: ## %cond.store22 ; AVX1-NEXT: vmovss %xmm1, (%rdi) ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $512, %eax ## imm = 0x200 -; AVX1-NEXT: je LBB6_20 -; AVX1-NEXT: LBB6_19: ## %cond.store25 +; AVX1-NEXT: je LBB6_11 +; AVX1-NEXT: LBB6_45: ## %cond.store25 ; AVX1-NEXT: vextractps $1, %xmm1, (%rdi) ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX1-NEXT: je LBB6_22 -; AVX1-NEXT: LBB6_21: ## %cond.store28 +; AVX1-NEXT: je LBB6_12 +; AVX1-NEXT: LBB6_46: ## %cond.store28 ; AVX1-NEXT: vextractps $2, %xmm1, (%rdi) ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX1-NEXT: jne LBB6_23 -; AVX1-NEXT: jmp LBB6_24 -; AVX1-NEXT: LBB6_25: ## %cond.store34 +; AVX1-NEXT: jne LBB6_13 +; AVX1-NEXT: jmp LBB6_14 +; AVX1-NEXT: LBB6_47: ## %cond.store34 ; AVX1-NEXT: vmovss %xmm0, (%rdi) ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX1-NEXT: je LBB6_28 -; AVX1-NEXT: LBB6_27: ## %cond.store37 +; AVX1-NEXT: je LBB6_16 +; AVX1-NEXT: LBB6_48: ## %cond.store37 ; AVX1-NEXT: vextractps $1, %xmm0, (%rdi) ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX1-NEXT: je LBB6_30 -; AVX1-NEXT: LBB6_29: ## %cond.store40 +; AVX1-NEXT: je LBB6_17 +; AVX1-NEXT: LBB6_49: ## %cond.store40 ; AVX1-NEXT: vextractps $2, %xmm0, (%rdi) ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testw %ax, %ax -; AVX1-NEXT: jns LBB6_32 -; AVX1-NEXT: LBB6_31: ## %cond.store43 +; AVX1-NEXT: jns LBB6_18 +; AVX1-NEXT: LBB6_50: ## %cond.store43 ; AVX1-NEXT: vextractps $3, %xmm0, (%rdi) ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $65536, %eax ## imm = 0x10000 -; AVX1-NEXT: je LBB6_34 -; AVX1-NEXT: LBB6_33: ## %cond.store46 +; AVX1-NEXT: je LBB6_19 +; AVX1-NEXT: LBB6_51: ## %cond.store46 ; AVX1-NEXT: vmovss %xmm2, (%rdi) ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $131072, %eax ## imm = 0x20000 -; AVX1-NEXT: je LBB6_36 -; AVX1-NEXT: LBB6_35: ## %cond.store49 +; AVX1-NEXT: je LBB6_20 +; AVX1-NEXT: LBB6_52: ## %cond.store49 ; AVX1-NEXT: vextractps $1, %xmm2, (%rdi) ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $262144, %eax ## imm = 0x40000 -; AVX1-NEXT: je LBB6_38 -; AVX1-NEXT: LBB6_37: ## %cond.store52 +; AVX1-NEXT: je LBB6_21 +; AVX1-NEXT: LBB6_53: ## %cond.store52 ; AVX1-NEXT: vextractps $2, %xmm2, (%rdi) ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $524288, %eax ## imm = 0x80000 -; AVX1-NEXT: jne LBB6_39 -; AVX1-NEXT: jmp LBB6_40 -; AVX1-NEXT: LBB6_41: ## %cond.store58 +; AVX1-NEXT: jne LBB6_22 +; AVX1-NEXT: jmp LBB6_23 +; AVX1-NEXT: LBB6_54: ## %cond.store58 ; AVX1-NEXT: vmovss %xmm0, (%rdi) ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $2097152, %eax ## imm = 0x200000 -; AVX1-NEXT: je LBB6_44 -; AVX1-NEXT: LBB6_43: ## %cond.store61 +; AVX1-NEXT: je LBB6_25 +; AVX1-NEXT: LBB6_55: ## %cond.store61 ; AVX1-NEXT: vextractps $1, %xmm0, (%rdi) ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $4194304, %eax ## imm = 0x400000 -; AVX1-NEXT: je LBB6_46 -; AVX1-NEXT: LBB6_45: ## %cond.store64 +; AVX1-NEXT: je LBB6_26 +; AVX1-NEXT: LBB6_56: ## %cond.store64 ; AVX1-NEXT: vextractps $2, %xmm0, (%rdi) ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $8388608, %eax ## imm = 0x800000 -; AVX1-NEXT: je LBB6_48 -; AVX1-NEXT: LBB6_47: ## %cond.store67 +; AVX1-NEXT: je LBB6_27 +; AVX1-NEXT: LBB6_57: ## %cond.store67 ; AVX1-NEXT: vextractps $3, %xmm0, (%rdi) ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $16777216, %eax ## imm = 0x1000000 -; AVX1-NEXT: je LBB6_50 -; AVX1-NEXT: LBB6_49: ## %cond.store70 +; AVX1-NEXT: je LBB6_28 +; AVX1-NEXT: LBB6_58: ## %cond.store70 ; AVX1-NEXT: vmovss %xmm3, (%rdi) ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $33554432, %eax ## imm = 0x2000000 -; AVX1-NEXT: je LBB6_52 -; AVX1-NEXT: LBB6_51: ## %cond.store73 +; AVX1-NEXT: je LBB6_29 +; AVX1-NEXT: LBB6_59: ## %cond.store73 ; AVX1-NEXT: vextractps $1, %xmm3, (%rdi) ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $67108864, %eax ## imm = 0x4000000 -; AVX1-NEXT: je LBB6_54 -; AVX1-NEXT: LBB6_53: ## %cond.store76 +; AVX1-NEXT: je LBB6_30 +; AVX1-NEXT: LBB6_60: ## %cond.store76 ; AVX1-NEXT: vextractps $2, %xmm3, (%rdi) ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $134217728, %eax ## imm = 0x8000000 -; AVX1-NEXT: jne LBB6_55 -; AVX1-NEXT: jmp LBB6_56 -; AVX1-NEXT: LBB6_57: ## %cond.store82 +; AVX1-NEXT: jne LBB6_31 +; AVX1-NEXT: jmp LBB6_32 +; AVX1-NEXT: LBB6_61: ## %cond.store82 ; AVX1-NEXT: vmovss %xmm0, (%rdi) ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $536870912, %eax ## imm = 0x20000000 -; AVX1-NEXT: je LBB6_60 -; AVX1-NEXT: LBB6_59: ## %cond.store85 +; AVX1-NEXT: je LBB6_34 +; AVX1-NEXT: LBB6_62: ## %cond.store85 ; AVX1-NEXT: vextractps $1, %xmm0, (%rdi) ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $1073741824, %eax ## imm = 0x40000000 -; AVX1-NEXT: je LBB6_62 -; AVX1-NEXT: LBB6_61: ## %cond.store88 +; AVX1-NEXT: je LBB6_35 +; AVX1-NEXT: LBB6_63: ## %cond.store88 ; AVX1-NEXT: vextractps $2, %xmm0, (%rdi) ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 -; AVX1-NEXT: je LBB6_64 -; AVX1-NEXT: LBB6_63: ## %cond.store91 +; AVX1-NEXT: je LBB6_36 +; AVX1-NEXT: LBB6_64: ## %cond.store91 ; AVX1-NEXT: vextractps $3, %xmm0, (%rdi) ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq @@ -2140,259 +2140,259 @@ define void @compressstore_v32f32_v32i32(ptr %base, <32 x float> %V, <32 x i32> ; AVX2-NEXT: vpermq {{.*#+}} ymm4 = ymm4[0,2,1,3] ; AVX2-NEXT: vpmovmskb %ymm4, %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne LBB6_1 -; AVX2-NEXT: ## %bb.2: ## %else +; AVX2-NEXT: jne LBB6_37 +; AVX2-NEXT: ## %bb.1: ## %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne LBB6_3 -; AVX2-NEXT: LBB6_4: ## %else2 +; AVX2-NEXT: jne LBB6_38 +; AVX2-NEXT: LBB6_2: ## %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne LBB6_5 -; AVX2-NEXT: LBB6_6: ## %else5 +; AVX2-NEXT: jne LBB6_39 +; AVX2-NEXT: LBB6_3: ## %else5 ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je LBB6_8 -; AVX2-NEXT: LBB6_7: ## %cond.store7 +; AVX2-NEXT: je LBB6_5 +; AVX2-NEXT: LBB6_4: ## %cond.store7 ; AVX2-NEXT: vextractps $3, %xmm0, (%rdi) ; AVX2-NEXT: addq $4, %rdi -; AVX2-NEXT: LBB6_8: ## %else8 +; AVX2-NEXT: LBB6_5: ## %else8 ; AVX2-NEXT: testb $16, %al ; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm0 -; AVX2-NEXT: jne LBB6_9 -; AVX2-NEXT: ## %bb.10: ## %else11 +; AVX2-NEXT: jne LBB6_40 +; AVX2-NEXT: ## %bb.6: ## %else11 ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: jne LBB6_11 -; AVX2-NEXT: LBB6_12: ## %else14 +; AVX2-NEXT: jne LBB6_41 +; AVX2-NEXT: LBB6_7: ## %else14 ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: jne LBB6_13 -; AVX2-NEXT: LBB6_14: ## %else17 +; AVX2-NEXT: jne LBB6_42 +; AVX2-NEXT: LBB6_8: ## %else17 ; AVX2-NEXT: testb %al, %al -; AVX2-NEXT: js LBB6_15 -; AVX2-NEXT: LBB6_16: ## %else20 +; AVX2-NEXT: js LBB6_43 +; AVX2-NEXT: LBB6_9: ## %else20 ; AVX2-NEXT: testl $256, %eax ## imm = 0x100 -; AVX2-NEXT: jne LBB6_17 -; AVX2-NEXT: LBB6_18: ## %else23 +; AVX2-NEXT: jne LBB6_44 +; AVX2-NEXT: LBB6_10: ## %else23 ; AVX2-NEXT: testl $512, %eax ## imm = 0x200 -; AVX2-NEXT: jne LBB6_19 -; AVX2-NEXT: LBB6_20: ## %else26 +; AVX2-NEXT: jne LBB6_45 +; AVX2-NEXT: LBB6_11: ## %else26 ; AVX2-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX2-NEXT: jne LBB6_21 -; AVX2-NEXT: LBB6_22: ## %else29 +; AVX2-NEXT: jne LBB6_46 +; AVX2-NEXT: LBB6_12: ## %else29 ; AVX2-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX2-NEXT: je LBB6_24 -; AVX2-NEXT: LBB6_23: ## %cond.store31 +; AVX2-NEXT: je LBB6_14 +; AVX2-NEXT: LBB6_13: ## %cond.store31 ; AVX2-NEXT: vextractps $3, %xmm1, (%rdi) ; AVX2-NEXT: addq $4, %rdi -; AVX2-NEXT: LBB6_24: ## %else32 +; AVX2-NEXT: LBB6_14: ## %else32 ; AVX2-NEXT: testl $4096, %eax ## imm = 0x1000 ; AVX2-NEXT: vextractf128 $1, %ymm1, %xmm0 -; AVX2-NEXT: jne LBB6_25 -; AVX2-NEXT: ## %bb.26: ## %else35 +; AVX2-NEXT: jne LBB6_47 +; AVX2-NEXT: ## %bb.15: ## %else35 ; AVX2-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX2-NEXT: jne LBB6_27 -; AVX2-NEXT: LBB6_28: ## %else38 +; AVX2-NEXT: jne LBB6_48 +; AVX2-NEXT: LBB6_16: ## %else38 ; AVX2-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX2-NEXT: jne LBB6_29 -; AVX2-NEXT: LBB6_30: ## %else41 +; AVX2-NEXT: jne LBB6_49 +; AVX2-NEXT: LBB6_17: ## %else41 ; AVX2-NEXT: testw %ax, %ax -; AVX2-NEXT: js LBB6_31 -; AVX2-NEXT: LBB6_32: ## %else44 +; AVX2-NEXT: js LBB6_50 +; AVX2-NEXT: LBB6_18: ## %else44 ; AVX2-NEXT: testl $65536, %eax ## imm = 0x10000 -; AVX2-NEXT: jne LBB6_33 -; AVX2-NEXT: LBB6_34: ## %else47 +; AVX2-NEXT: jne LBB6_51 +; AVX2-NEXT: LBB6_19: ## %else47 ; AVX2-NEXT: testl $131072, %eax ## imm = 0x20000 -; AVX2-NEXT: jne LBB6_35 -; AVX2-NEXT: LBB6_36: ## %else50 +; AVX2-NEXT: jne LBB6_52 +; AVX2-NEXT: LBB6_20: ## %else50 ; AVX2-NEXT: testl $262144, %eax ## imm = 0x40000 -; AVX2-NEXT: jne LBB6_37 -; AVX2-NEXT: LBB6_38: ## %else53 +; AVX2-NEXT: jne LBB6_53 +; AVX2-NEXT: LBB6_21: ## %else53 ; AVX2-NEXT: testl $524288, %eax ## imm = 0x80000 -; AVX2-NEXT: je LBB6_40 -; AVX2-NEXT: LBB6_39: ## %cond.store55 +; AVX2-NEXT: je LBB6_23 +; AVX2-NEXT: LBB6_22: ## %cond.store55 ; AVX2-NEXT: vextractps $3, %xmm2, (%rdi) ; AVX2-NEXT: addq $4, %rdi -; AVX2-NEXT: LBB6_40: ## %else56 +; AVX2-NEXT: LBB6_23: ## %else56 ; AVX2-NEXT: testl $1048576, %eax ## imm = 0x100000 ; AVX2-NEXT: vextractf128 $1, %ymm2, %xmm0 -; AVX2-NEXT: jne LBB6_41 -; AVX2-NEXT: ## %bb.42: ## %else59 +; AVX2-NEXT: jne LBB6_54 +; AVX2-NEXT: ## %bb.24: ## %else59 ; AVX2-NEXT: testl $2097152, %eax ## imm = 0x200000 -; AVX2-NEXT: jne LBB6_43 -; AVX2-NEXT: LBB6_44: ## %else62 +; AVX2-NEXT: jne LBB6_55 +; AVX2-NEXT: LBB6_25: ## %else62 ; AVX2-NEXT: testl $4194304, %eax ## imm = 0x400000 -; AVX2-NEXT: jne LBB6_45 -; AVX2-NEXT: LBB6_46: ## %else65 +; AVX2-NEXT: jne LBB6_56 +; AVX2-NEXT: LBB6_26: ## %else65 ; AVX2-NEXT: testl $8388608, %eax ## imm = 0x800000 -; AVX2-NEXT: jne LBB6_47 -; AVX2-NEXT: LBB6_48: ## %else68 +; AVX2-NEXT: jne LBB6_57 +; AVX2-NEXT: LBB6_27: ## %else68 ; AVX2-NEXT: testl $16777216, %eax ## imm = 0x1000000 -; AVX2-NEXT: jne LBB6_49 -; AVX2-NEXT: LBB6_50: ## %else71 +; AVX2-NEXT: jne LBB6_58 +; AVX2-NEXT: LBB6_28: ## %else71 ; AVX2-NEXT: testl $33554432, %eax ## imm = 0x2000000 -; AVX2-NEXT: jne LBB6_51 -; AVX2-NEXT: LBB6_52: ## %else74 +; AVX2-NEXT: jne LBB6_59 +; AVX2-NEXT: LBB6_29: ## %else74 ; AVX2-NEXT: testl $67108864, %eax ## imm = 0x4000000 -; AVX2-NEXT: jne LBB6_53 -; AVX2-NEXT: LBB6_54: ## %else77 +; AVX2-NEXT: jne LBB6_60 +; AVX2-NEXT: LBB6_30: ## %else77 ; AVX2-NEXT: testl $134217728, %eax ## imm = 0x8000000 -; AVX2-NEXT: je LBB6_56 -; AVX2-NEXT: LBB6_55: ## %cond.store79 +; AVX2-NEXT: je LBB6_32 +; AVX2-NEXT: LBB6_31: ## %cond.store79 ; AVX2-NEXT: vextractps $3, %xmm3, (%rdi) ; AVX2-NEXT: addq $4, %rdi -; AVX2-NEXT: LBB6_56: ## %else80 +; AVX2-NEXT: LBB6_32: ## %else80 ; AVX2-NEXT: testl $268435456, %eax ## imm = 0x10000000 ; AVX2-NEXT: vextractf128 $1, %ymm3, %xmm0 -; AVX2-NEXT: jne LBB6_57 -; AVX2-NEXT: ## %bb.58: ## %else83 +; AVX2-NEXT: jne LBB6_61 +; AVX2-NEXT: ## %bb.33: ## %else83 ; AVX2-NEXT: testl $536870912, %eax ## imm = 0x20000000 -; AVX2-NEXT: jne LBB6_59 -; AVX2-NEXT: LBB6_60: ## %else86 +; AVX2-NEXT: jne LBB6_62 +; AVX2-NEXT: LBB6_34: ## %else86 ; AVX2-NEXT: testl $1073741824, %eax ## imm = 0x40000000 -; AVX2-NEXT: jne LBB6_61 -; AVX2-NEXT: LBB6_62: ## %else89 -; AVX2-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 ; AVX2-NEXT: jne LBB6_63 -; AVX2-NEXT: LBB6_64: ## %else92 +; AVX2-NEXT: LBB6_35: ## %else89 +; AVX2-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 +; AVX2-NEXT: jne LBB6_64 +; AVX2-NEXT: LBB6_36: ## %else92 ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; AVX2-NEXT: LBB6_1: ## %cond.store +; AVX2-NEXT: LBB6_37: ## %cond.store ; AVX2-NEXT: vmovss %xmm0, (%rdi) ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je LBB6_4 -; AVX2-NEXT: LBB6_3: ## %cond.store1 +; AVX2-NEXT: je LBB6_2 +; AVX2-NEXT: LBB6_38: ## %cond.store1 ; AVX2-NEXT: vextractps $1, %xmm0, (%rdi) ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je LBB6_6 -; AVX2-NEXT: LBB6_5: ## %cond.store4 +; AVX2-NEXT: je LBB6_3 +; AVX2-NEXT: LBB6_39: ## %cond.store4 ; AVX2-NEXT: vextractps $2, %xmm0, (%rdi) ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: jne LBB6_7 -; AVX2-NEXT: jmp LBB6_8 -; AVX2-NEXT: LBB6_9: ## %cond.store10 +; AVX2-NEXT: jne LBB6_4 +; AVX2-NEXT: jmp LBB6_5 +; AVX2-NEXT: LBB6_40: ## %cond.store10 ; AVX2-NEXT: vmovss %xmm0, (%rdi) ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: je LBB6_12 -; AVX2-NEXT: LBB6_11: ## %cond.store13 +; AVX2-NEXT: je LBB6_7 +; AVX2-NEXT: LBB6_41: ## %cond.store13 ; AVX2-NEXT: vextractps $1, %xmm0, (%rdi) ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: je LBB6_14 -; AVX2-NEXT: LBB6_13: ## %cond.store16 +; AVX2-NEXT: je LBB6_8 +; AVX2-NEXT: LBB6_42: ## %cond.store16 ; AVX2-NEXT: vextractps $2, %xmm0, (%rdi) ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testb %al, %al -; AVX2-NEXT: jns LBB6_16 -; AVX2-NEXT: LBB6_15: ## %cond.store19 +; AVX2-NEXT: jns LBB6_9 +; AVX2-NEXT: LBB6_43: ## %cond.store19 ; AVX2-NEXT: vextractps $3, %xmm0, (%rdi) ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $256, %eax ## imm = 0x100 -; AVX2-NEXT: je LBB6_18 -; AVX2-NEXT: LBB6_17: ## %cond.store22 +; AVX2-NEXT: je LBB6_10 +; AVX2-NEXT: LBB6_44: ## %cond.store22 ; AVX2-NEXT: vmovss %xmm1, (%rdi) ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $512, %eax ## imm = 0x200 -; AVX2-NEXT: je LBB6_20 -; AVX2-NEXT: LBB6_19: ## %cond.store25 +; AVX2-NEXT: je LBB6_11 +; AVX2-NEXT: LBB6_45: ## %cond.store25 ; AVX2-NEXT: vextractps $1, %xmm1, (%rdi) ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX2-NEXT: je LBB6_22 -; AVX2-NEXT: LBB6_21: ## %cond.store28 +; AVX2-NEXT: je LBB6_12 +; AVX2-NEXT: LBB6_46: ## %cond.store28 ; AVX2-NEXT: vextractps $2, %xmm1, (%rdi) ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX2-NEXT: jne LBB6_23 -; AVX2-NEXT: jmp LBB6_24 -; AVX2-NEXT: LBB6_25: ## %cond.store34 +; AVX2-NEXT: jne LBB6_13 +; AVX2-NEXT: jmp LBB6_14 +; AVX2-NEXT: LBB6_47: ## %cond.store34 ; AVX2-NEXT: vmovss %xmm0, (%rdi) ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX2-NEXT: je LBB6_28 -; AVX2-NEXT: LBB6_27: ## %cond.store37 +; AVX2-NEXT: je LBB6_16 +; AVX2-NEXT: LBB6_48: ## %cond.store37 ; AVX2-NEXT: vextractps $1, %xmm0, (%rdi) ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX2-NEXT: je LBB6_30 -; AVX2-NEXT: LBB6_29: ## %cond.store40 +; AVX2-NEXT: je LBB6_17 +; AVX2-NEXT: LBB6_49: ## %cond.store40 ; AVX2-NEXT: vextractps $2, %xmm0, (%rdi) ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testw %ax, %ax -; AVX2-NEXT: jns LBB6_32 -; AVX2-NEXT: LBB6_31: ## %cond.store43 +; AVX2-NEXT: jns LBB6_18 +; AVX2-NEXT: LBB6_50: ## %cond.store43 ; AVX2-NEXT: vextractps $3, %xmm0, (%rdi) ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $65536, %eax ## imm = 0x10000 -; AVX2-NEXT: je LBB6_34 -; AVX2-NEXT: LBB6_33: ## %cond.store46 +; AVX2-NEXT: je LBB6_19 +; AVX2-NEXT: LBB6_51: ## %cond.store46 ; AVX2-NEXT: vmovss %xmm2, (%rdi) ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $131072, %eax ## imm = 0x20000 -; AVX2-NEXT: je LBB6_36 -; AVX2-NEXT: LBB6_35: ## %cond.store49 +; AVX2-NEXT: je LBB6_20 +; AVX2-NEXT: LBB6_52: ## %cond.store49 ; AVX2-NEXT: vextractps $1, %xmm2, (%rdi) ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $262144, %eax ## imm = 0x40000 -; AVX2-NEXT: je LBB6_38 -; AVX2-NEXT: LBB6_37: ## %cond.store52 +; AVX2-NEXT: je LBB6_21 +; AVX2-NEXT: LBB6_53: ## %cond.store52 ; AVX2-NEXT: vextractps $2, %xmm2, (%rdi) ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $524288, %eax ## imm = 0x80000 -; AVX2-NEXT: jne LBB6_39 -; AVX2-NEXT: jmp LBB6_40 -; AVX2-NEXT: LBB6_41: ## %cond.store58 +; AVX2-NEXT: jne LBB6_22 +; AVX2-NEXT: jmp LBB6_23 +; AVX2-NEXT: LBB6_54: ## %cond.store58 ; AVX2-NEXT: vmovss %xmm0, (%rdi) ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $2097152, %eax ## imm = 0x200000 -; AVX2-NEXT: je LBB6_44 -; AVX2-NEXT: LBB6_43: ## %cond.store61 +; AVX2-NEXT: je LBB6_25 +; AVX2-NEXT: LBB6_55: ## %cond.store61 ; AVX2-NEXT: vextractps $1, %xmm0, (%rdi) ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $4194304, %eax ## imm = 0x400000 -; AVX2-NEXT: je LBB6_46 -; AVX2-NEXT: LBB6_45: ## %cond.store64 +; AVX2-NEXT: je LBB6_26 +; AVX2-NEXT: LBB6_56: ## %cond.store64 ; AVX2-NEXT: vextractps $2, %xmm0, (%rdi) ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $8388608, %eax ## imm = 0x800000 -; AVX2-NEXT: je LBB6_48 -; AVX2-NEXT: LBB6_47: ## %cond.store67 +; AVX2-NEXT: je LBB6_27 +; AVX2-NEXT: LBB6_57: ## %cond.store67 ; AVX2-NEXT: vextractps $3, %xmm0, (%rdi) ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $16777216, %eax ## imm = 0x1000000 -; AVX2-NEXT: je LBB6_50 -; AVX2-NEXT: LBB6_49: ## %cond.store70 +; AVX2-NEXT: je LBB6_28 +; AVX2-NEXT: LBB6_58: ## %cond.store70 ; AVX2-NEXT: vmovss %xmm3, (%rdi) ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $33554432, %eax ## imm = 0x2000000 -; AVX2-NEXT: je LBB6_52 -; AVX2-NEXT: LBB6_51: ## %cond.store73 +; AVX2-NEXT: je LBB6_29 +; AVX2-NEXT: LBB6_59: ## %cond.store73 ; AVX2-NEXT: vextractps $1, %xmm3, (%rdi) ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $67108864, %eax ## imm = 0x4000000 -; AVX2-NEXT: je LBB6_54 -; AVX2-NEXT: LBB6_53: ## %cond.store76 +; AVX2-NEXT: je LBB6_30 +; AVX2-NEXT: LBB6_60: ## %cond.store76 ; AVX2-NEXT: vextractps $2, %xmm3, (%rdi) ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $134217728, %eax ## imm = 0x8000000 -; AVX2-NEXT: jne LBB6_55 -; AVX2-NEXT: jmp LBB6_56 -; AVX2-NEXT: LBB6_57: ## %cond.store82 +; AVX2-NEXT: jne LBB6_31 +; AVX2-NEXT: jmp LBB6_32 +; AVX2-NEXT: LBB6_61: ## %cond.store82 ; AVX2-NEXT: vmovss %xmm0, (%rdi) ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $536870912, %eax ## imm = 0x20000000 -; AVX2-NEXT: je LBB6_60 -; AVX2-NEXT: LBB6_59: ## %cond.store85 +; AVX2-NEXT: je LBB6_34 +; AVX2-NEXT: LBB6_62: ## %cond.store85 ; AVX2-NEXT: vextractps $1, %xmm0, (%rdi) ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $1073741824, %eax ## imm = 0x40000000 -; AVX2-NEXT: je LBB6_62 -; AVX2-NEXT: LBB6_61: ## %cond.store88 +; AVX2-NEXT: je LBB6_35 +; AVX2-NEXT: LBB6_63: ## %cond.store88 ; AVX2-NEXT: vextractps $2, %xmm0, (%rdi) ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 -; AVX2-NEXT: je LBB6_64 -; AVX2-NEXT: LBB6_63: ## %cond.store91 +; AVX2-NEXT: je LBB6_36 +; AVX2-NEXT: LBB6_64: ## %cond.store91 ; AVX2-NEXT: vextractps $3, %xmm0, (%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq @@ -2436,18 +2436,18 @@ define void @compressstore_v2i64_v2i1(ptr %base, <2 x i64> %V, <2 x i1> %mask) { ; SSE2-NEXT: psllq $63, %xmm1 ; SSE2-NEXT: movmskpd %xmm1, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB7_1 -; SSE2-NEXT: ## %bb.2: ## %else -; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: jne LBB7_3 -; SSE2-NEXT: LBB7_4: ## %else2 +; SSE2-NEXT: ## %bb.1: ## %else +; SSE2-NEXT: testb $2, %al +; SSE2-NEXT: jne LBB7_4 +; SSE2-NEXT: LBB7_2: ## %else2 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB7_1: ## %cond.store +; SSE2-NEXT: LBB7_3: ## %cond.store ; SSE2-NEXT: movq %xmm0, (%rdi) ; SSE2-NEXT: addq $8, %rdi ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB7_4 -; SSE2-NEXT: LBB7_3: ## %cond.store1 +; SSE2-NEXT: je LBB7_2 +; SSE2-NEXT: LBB7_4: ## %cond.store1 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3] ; SSE2-NEXT: movq %xmm0, (%rdi) ; SSE2-NEXT: retq @@ -2457,18 +2457,18 @@ define void @compressstore_v2i64_v2i1(ptr %base, <2 x i64> %V, <2 x i1> %mask) { ; SSE42-NEXT: psllq $63, %xmm1 ; SSE42-NEXT: movmskpd %xmm1, %eax ; SSE42-NEXT: testb $1, %al -; SSE42-NEXT: jne LBB7_1 -; SSE42-NEXT: ## %bb.2: ## %else -; SSE42-NEXT: testb $2, %al ; SSE42-NEXT: jne LBB7_3 -; SSE42-NEXT: LBB7_4: ## %else2 +; SSE42-NEXT: ## %bb.1: ## %else +; SSE42-NEXT: testb $2, %al +; SSE42-NEXT: jne LBB7_4 +; SSE42-NEXT: LBB7_2: ## %else2 ; SSE42-NEXT: retq -; SSE42-NEXT: LBB7_1: ## %cond.store +; SSE42-NEXT: LBB7_3: ## %cond.store ; SSE42-NEXT: movq %xmm0, (%rdi) ; SSE42-NEXT: addq $8, %rdi ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: je LBB7_4 -; SSE42-NEXT: LBB7_3: ## %cond.store1 +; SSE42-NEXT: je LBB7_2 +; SSE42-NEXT: LBB7_4: ## %cond.store1 ; SSE42-NEXT: pextrq $1, %xmm0, (%rdi) ; SSE42-NEXT: retq ; @@ -2477,18 +2477,18 @@ define void @compressstore_v2i64_v2i1(ptr %base, <2 x i64> %V, <2 x i1> %mask) { ; AVX1OR2-NEXT: vpsllq $63, %xmm1, %xmm1 ; AVX1OR2-NEXT: vmovmskpd %xmm1, %eax ; AVX1OR2-NEXT: testb $1, %al -; AVX1OR2-NEXT: jne LBB7_1 -; AVX1OR2-NEXT: ## %bb.2: ## %else -; AVX1OR2-NEXT: testb $2, %al ; AVX1OR2-NEXT: jne LBB7_3 -; AVX1OR2-NEXT: LBB7_4: ## %else2 +; AVX1OR2-NEXT: ## %bb.1: ## %else +; AVX1OR2-NEXT: testb $2, %al +; AVX1OR2-NEXT: jne LBB7_4 +; AVX1OR2-NEXT: LBB7_2: ## %else2 ; AVX1OR2-NEXT: retq -; AVX1OR2-NEXT: LBB7_1: ## %cond.store +; AVX1OR2-NEXT: LBB7_3: ## %cond.store ; AVX1OR2-NEXT: vmovq %xmm0, (%rdi) ; AVX1OR2-NEXT: addq $8, %rdi ; AVX1OR2-NEXT: testb $2, %al -; AVX1OR2-NEXT: je LBB7_4 -; AVX1OR2-NEXT: LBB7_3: ## %cond.store1 +; AVX1OR2-NEXT: je LBB7_2 +; AVX1OR2-NEXT: LBB7_4: ## %cond.store1 ; AVX1OR2-NEXT: vpextrq $1, %xmm0, (%rdi) ; AVX1OR2-NEXT: retq ; @@ -2526,35 +2526,35 @@ define void @compressstore_v4i64_v4i1(ptr %base, <4 x i64> %V, <4 x i1> %mask) { ; SSE2-NEXT: pslld $31, %xmm2 ; SSE2-NEXT: movmskps %xmm2, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB8_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB8_5 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB8_3 -; SSE2-NEXT: LBB8_4: ## %else2 +; SSE2-NEXT: jne LBB8_6 +; SSE2-NEXT: LBB8_2: ## %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB8_5 -; SSE2-NEXT: LBB8_6: ## %else5 -; SSE2-NEXT: testb $8, %al ; SSE2-NEXT: jne LBB8_7 -; SSE2-NEXT: LBB8_8: ## %else8 +; SSE2-NEXT: LBB8_3: ## %else5 +; SSE2-NEXT: testb $8, %al +; SSE2-NEXT: jne LBB8_8 +; SSE2-NEXT: LBB8_4: ## %else8 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB8_1: ## %cond.store +; SSE2-NEXT: LBB8_5: ## %cond.store ; SSE2-NEXT: movq %xmm0, (%rdi) ; SSE2-NEXT: addq $8, %rdi ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB8_4 -; SSE2-NEXT: LBB8_3: ## %cond.store1 +; SSE2-NEXT: je LBB8_2 +; SSE2-NEXT: LBB8_6: ## %cond.store1 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3] ; SSE2-NEXT: movq %xmm0, (%rdi) ; SSE2-NEXT: addq $8, %rdi ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB8_6 -; SSE2-NEXT: LBB8_5: ## %cond.store4 +; SSE2-NEXT: je LBB8_3 +; SSE2-NEXT: LBB8_7: ## %cond.store4 ; SSE2-NEXT: movq %xmm1, (%rdi) ; SSE2-NEXT: addq $8, %rdi ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB8_8 -; SSE2-NEXT: LBB8_7: ## %cond.store7 +; SSE2-NEXT: je LBB8_4 +; SSE2-NEXT: LBB8_8: ## %cond.store7 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3] ; SSE2-NEXT: movq %xmm0, (%rdi) ; SSE2-NEXT: retq @@ -2564,34 +2564,34 @@ define void @compressstore_v4i64_v4i1(ptr %base, <4 x i64> %V, <4 x i1> %mask) { ; SSE42-NEXT: pslld $31, %xmm2 ; SSE42-NEXT: movmskps %xmm2, %eax ; SSE42-NEXT: testb $1, %al -; SSE42-NEXT: jne LBB8_1 -; SSE42-NEXT: ## %bb.2: ## %else +; SSE42-NEXT: jne LBB8_5 +; SSE42-NEXT: ## %bb.1: ## %else ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: jne LBB8_3 -; SSE42-NEXT: LBB8_4: ## %else2 +; SSE42-NEXT: jne LBB8_6 +; SSE42-NEXT: LBB8_2: ## %else2 ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: jne LBB8_5 -; SSE42-NEXT: LBB8_6: ## %else5 -; SSE42-NEXT: testb $8, %al ; SSE42-NEXT: jne LBB8_7 -; SSE42-NEXT: LBB8_8: ## %else8 +; SSE42-NEXT: LBB8_3: ## %else5 +; SSE42-NEXT: testb $8, %al +; SSE42-NEXT: jne LBB8_8 +; SSE42-NEXT: LBB8_4: ## %else8 ; SSE42-NEXT: retq -; SSE42-NEXT: LBB8_1: ## %cond.store +; SSE42-NEXT: LBB8_5: ## %cond.store ; SSE42-NEXT: movq %xmm0, (%rdi) ; SSE42-NEXT: addq $8, %rdi ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: je LBB8_4 -; SSE42-NEXT: LBB8_3: ## %cond.store1 +; SSE42-NEXT: je LBB8_2 +; SSE42-NEXT: LBB8_6: ## %cond.store1 ; SSE42-NEXT: pextrq $1, %xmm0, (%rdi) ; SSE42-NEXT: addq $8, %rdi ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: je LBB8_6 -; SSE42-NEXT: LBB8_5: ## %cond.store4 +; SSE42-NEXT: je LBB8_3 +; SSE42-NEXT: LBB8_7: ## %cond.store4 ; SSE42-NEXT: movq %xmm1, (%rdi) ; SSE42-NEXT: addq $8, %rdi ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: je LBB8_8 -; SSE42-NEXT: LBB8_7: ## %cond.store7 +; SSE42-NEXT: je LBB8_4 +; SSE42-NEXT: LBB8_8: ## %cond.store7 ; SSE42-NEXT: pextrq $1, %xmm1, (%rdi) ; SSE42-NEXT: retq ; @@ -2613,19 +2613,19 @@ define void @compressstore_v4i64_v4i1(ptr %base, <4 x i64> %V, <4 x i1> %mask) { ; AVX1-NEXT: LBB8_4: ## %else2 ; AVX1-NEXT: testb $4, %al ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 -; AVX1-NEXT: jne LBB8_5 -; AVX1-NEXT: ## %bb.6: ## %else5 -; AVX1-NEXT: testb $8, %al ; AVX1-NEXT: jne LBB8_7 -; AVX1-NEXT: LBB8_8: ## %else8 +; AVX1-NEXT: ## %bb.5: ## %else5 +; AVX1-NEXT: testb $8, %al +; AVX1-NEXT: jne LBB8_8 +; AVX1-NEXT: LBB8_6: ## %else8 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: LBB8_5: ## %cond.store4 +; AVX1-NEXT: LBB8_7: ## %cond.store4 ; AVX1-NEXT: vmovq %xmm0, (%rdi) ; AVX1-NEXT: addq $8, %rdi ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je LBB8_8 -; AVX1-NEXT: LBB8_7: ## %cond.store7 +; AVX1-NEXT: je LBB8_6 +; AVX1-NEXT: LBB8_8: ## %cond.store7 ; AVX1-NEXT: vpextrq $1, %xmm0, (%rdi) ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq @@ -2648,19 +2648,19 @@ define void @compressstore_v4i64_v4i1(ptr %base, <4 x i64> %V, <4 x i1> %mask) { ; AVX2-NEXT: LBB8_4: ## %else2 ; AVX2-NEXT: testb $4, %al ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0 -; AVX2-NEXT: jne LBB8_5 -; AVX2-NEXT: ## %bb.6: ## %else5 -; AVX2-NEXT: testb $8, %al ; AVX2-NEXT: jne LBB8_7 -; AVX2-NEXT: LBB8_8: ## %else8 +; AVX2-NEXT: ## %bb.5: ## %else5 +; AVX2-NEXT: testb $8, %al +; AVX2-NEXT: jne LBB8_8 +; AVX2-NEXT: LBB8_6: ## %else8 ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; AVX2-NEXT: LBB8_5: ## %cond.store4 +; AVX2-NEXT: LBB8_7: ## %cond.store4 ; AVX2-NEXT: vmovq %xmm0, (%rdi) ; AVX2-NEXT: addq $8, %rdi ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je LBB8_8 -; AVX2-NEXT: LBB8_7: ## %cond.store7 +; AVX2-NEXT: je LBB8_6 +; AVX2-NEXT: LBB8_8: ## %cond.store7 ; AVX2-NEXT: vpextrq $1, %xmm0, (%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq @@ -2702,69 +2702,69 @@ define void @compressstore_v8i64_v8i1(ptr %base, <8 x i64> %V, <8 x i1> %mask) { ; SSE2-NEXT: packsswb %xmm4, %xmm4 ; SSE2-NEXT: pmovmskb %xmm4, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB9_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB9_9 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB9_3 -; SSE2-NEXT: LBB9_4: ## %else2 +; SSE2-NEXT: jne LBB9_10 +; SSE2-NEXT: LBB9_2: ## %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB9_5 -; SSE2-NEXT: LBB9_6: ## %else5 +; SSE2-NEXT: jne LBB9_11 +; SSE2-NEXT: LBB9_3: ## %else5 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne LBB9_7 -; SSE2-NEXT: LBB9_8: ## %else8 +; SSE2-NEXT: jne LBB9_12 +; SSE2-NEXT: LBB9_4: ## %else8 ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: jne LBB9_9 -; SSE2-NEXT: LBB9_10: ## %else11 +; SSE2-NEXT: jne LBB9_13 +; SSE2-NEXT: LBB9_5: ## %else11 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: jne LBB9_11 -; SSE2-NEXT: LBB9_12: ## %else14 +; SSE2-NEXT: jne LBB9_14 +; SSE2-NEXT: LBB9_6: ## %else14 ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: jne LBB9_13 -; SSE2-NEXT: LBB9_14: ## %else17 -; SSE2-NEXT: testb $-128, %al ; SSE2-NEXT: jne LBB9_15 -; SSE2-NEXT: LBB9_16: ## %else20 +; SSE2-NEXT: LBB9_7: ## %else17 +; SSE2-NEXT: testb $-128, %al +; SSE2-NEXT: jne LBB9_16 +; SSE2-NEXT: LBB9_8: ## %else20 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB9_1: ## %cond.store +; SSE2-NEXT: LBB9_9: ## %cond.store ; SSE2-NEXT: movq %xmm0, (%rdi) ; SSE2-NEXT: addq $8, %rdi ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB9_4 -; SSE2-NEXT: LBB9_3: ## %cond.store1 +; SSE2-NEXT: je LBB9_2 +; SSE2-NEXT: LBB9_10: ## %cond.store1 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3] ; SSE2-NEXT: movq %xmm0, (%rdi) ; SSE2-NEXT: addq $8, %rdi ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB9_6 -; SSE2-NEXT: LBB9_5: ## %cond.store4 +; SSE2-NEXT: je LBB9_3 +; SSE2-NEXT: LBB9_11: ## %cond.store4 ; SSE2-NEXT: movq %xmm1, (%rdi) ; SSE2-NEXT: addq $8, %rdi ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB9_8 -; SSE2-NEXT: LBB9_7: ## %cond.store7 +; SSE2-NEXT: je LBB9_4 +; SSE2-NEXT: LBB9_12: ## %cond.store7 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3] ; SSE2-NEXT: movq %xmm0, (%rdi) ; SSE2-NEXT: addq $8, %rdi ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: je LBB9_10 -; SSE2-NEXT: LBB9_9: ## %cond.store10 +; SSE2-NEXT: je LBB9_5 +; SSE2-NEXT: LBB9_13: ## %cond.store10 ; SSE2-NEXT: movq %xmm2, (%rdi) ; SSE2-NEXT: addq $8, %rdi ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je LBB9_12 -; SSE2-NEXT: LBB9_11: ## %cond.store13 +; SSE2-NEXT: je LBB9_6 +; SSE2-NEXT: LBB9_14: ## %cond.store13 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[2,3,2,3] ; SSE2-NEXT: movq %xmm0, (%rdi) ; SSE2-NEXT: addq $8, %rdi ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: je LBB9_14 -; SSE2-NEXT: LBB9_13: ## %cond.store16 +; SSE2-NEXT: je LBB9_7 +; SSE2-NEXT: LBB9_15: ## %cond.store16 ; SSE2-NEXT: movq %xmm3, (%rdi) ; SSE2-NEXT: addq $8, %rdi ; SSE2-NEXT: testb $-128, %al -; SSE2-NEXT: je LBB9_16 -; SSE2-NEXT: LBB9_15: ## %cond.store19 +; SSE2-NEXT: je LBB9_8 +; SSE2-NEXT: LBB9_16: ## %cond.store19 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[2,3,2,3] ; SSE2-NEXT: movq %xmm0, (%rdi) ; SSE2-NEXT: retq @@ -2775,66 +2775,66 @@ define void @compressstore_v8i64_v8i1(ptr %base, <8 x i64> %V, <8 x i1> %mask) { ; SSE42-NEXT: packsswb %xmm4, %xmm4 ; SSE42-NEXT: pmovmskb %xmm4, %eax ; SSE42-NEXT: testb $1, %al -; SSE42-NEXT: jne LBB9_1 -; SSE42-NEXT: ## %bb.2: ## %else +; SSE42-NEXT: jne LBB9_9 +; SSE42-NEXT: ## %bb.1: ## %else ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: jne LBB9_3 -; SSE42-NEXT: LBB9_4: ## %else2 +; SSE42-NEXT: jne LBB9_10 +; SSE42-NEXT: LBB9_2: ## %else2 ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: jne LBB9_5 -; SSE42-NEXT: LBB9_6: ## %else5 +; SSE42-NEXT: jne LBB9_11 +; SSE42-NEXT: LBB9_3: ## %else5 ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: jne LBB9_7 -; SSE42-NEXT: LBB9_8: ## %else8 +; SSE42-NEXT: jne LBB9_12 +; SSE42-NEXT: LBB9_4: ## %else8 ; SSE42-NEXT: testb $16, %al -; SSE42-NEXT: jne LBB9_9 -; SSE42-NEXT: LBB9_10: ## %else11 +; SSE42-NEXT: jne LBB9_13 +; SSE42-NEXT: LBB9_5: ## %else11 ; SSE42-NEXT: testb $32, %al -; SSE42-NEXT: jne LBB9_11 -; SSE42-NEXT: LBB9_12: ## %else14 +; SSE42-NEXT: jne LBB9_14 +; SSE42-NEXT: LBB9_6: ## %else14 ; SSE42-NEXT: testb $64, %al -; SSE42-NEXT: jne LBB9_13 -; SSE42-NEXT: LBB9_14: ## %else17 -; SSE42-NEXT: testb $-128, %al ; SSE42-NEXT: jne LBB9_15 -; SSE42-NEXT: LBB9_16: ## %else20 +; SSE42-NEXT: LBB9_7: ## %else17 +; SSE42-NEXT: testb $-128, %al +; SSE42-NEXT: jne LBB9_16 +; SSE42-NEXT: LBB9_8: ## %else20 ; SSE42-NEXT: retq -; SSE42-NEXT: LBB9_1: ## %cond.store +; SSE42-NEXT: LBB9_9: ## %cond.store ; SSE42-NEXT: movq %xmm0, (%rdi) ; SSE42-NEXT: addq $8, %rdi ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: je LBB9_4 -; SSE42-NEXT: LBB9_3: ## %cond.store1 +; SSE42-NEXT: je LBB9_2 +; SSE42-NEXT: LBB9_10: ## %cond.store1 ; SSE42-NEXT: pextrq $1, %xmm0, (%rdi) ; SSE42-NEXT: addq $8, %rdi ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: je LBB9_6 -; SSE42-NEXT: LBB9_5: ## %cond.store4 +; SSE42-NEXT: je LBB9_3 +; SSE42-NEXT: LBB9_11: ## %cond.store4 ; SSE42-NEXT: movq %xmm1, (%rdi) ; SSE42-NEXT: addq $8, %rdi ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: je LBB9_8 -; SSE42-NEXT: LBB9_7: ## %cond.store7 +; SSE42-NEXT: je LBB9_4 +; SSE42-NEXT: LBB9_12: ## %cond.store7 ; SSE42-NEXT: pextrq $1, %xmm1, (%rdi) ; SSE42-NEXT: addq $8, %rdi ; SSE42-NEXT: testb $16, %al -; SSE42-NEXT: je LBB9_10 -; SSE42-NEXT: LBB9_9: ## %cond.store10 +; SSE42-NEXT: je LBB9_5 +; SSE42-NEXT: LBB9_13: ## %cond.store10 ; SSE42-NEXT: movq %xmm2, (%rdi) ; SSE42-NEXT: addq $8, %rdi ; SSE42-NEXT: testb $32, %al -; SSE42-NEXT: je LBB9_12 -; SSE42-NEXT: LBB9_11: ## %cond.store13 +; SSE42-NEXT: je LBB9_6 +; SSE42-NEXT: LBB9_14: ## %cond.store13 ; SSE42-NEXT: pextrq $1, %xmm2, (%rdi) ; SSE42-NEXT: addq $8, %rdi ; SSE42-NEXT: testb $64, %al -; SSE42-NEXT: je LBB9_14 -; SSE42-NEXT: LBB9_13: ## %cond.store16 +; SSE42-NEXT: je LBB9_7 +; SSE42-NEXT: LBB9_15: ## %cond.store16 ; SSE42-NEXT: movq %xmm3, (%rdi) ; SSE42-NEXT: addq $8, %rdi ; SSE42-NEXT: testb $-128, %al -; SSE42-NEXT: je LBB9_16 -; SSE42-NEXT: LBB9_15: ## %cond.store19 +; SSE42-NEXT: je LBB9_8 +; SSE42-NEXT: LBB9_16: ## %cond.store19 ; SSE42-NEXT: pextrq $1, %xmm3, (%rdi) ; SSE42-NEXT: retq ; @@ -2857,51 +2857,51 @@ define void @compressstore_v8i64_v8i1(ptr %base, <8 x i64> %V, <8 x i1> %mask) { ; AVX1-NEXT: LBB9_4: ## %else2 ; AVX1-NEXT: testb $4, %al ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 -; AVX1-NEXT: jne LBB9_5 -; AVX1-NEXT: ## %bb.6: ## %else5 +; AVX1-NEXT: jne LBB9_12 +; AVX1-NEXT: ## %bb.5: ## %else5 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne LBB9_7 -; AVX1-NEXT: LBB9_8: ## %else8 +; AVX1-NEXT: jne LBB9_13 +; AVX1-NEXT: LBB9_6: ## %else8 ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: jne LBB9_9 -; AVX1-NEXT: LBB9_10: ## %else11 +; AVX1-NEXT: jne LBB9_14 +; AVX1-NEXT: LBB9_7: ## %else11 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je LBB9_12 -; AVX1-NEXT: LBB9_11: ## %cond.store13 +; AVX1-NEXT: je LBB9_9 +; AVX1-NEXT: LBB9_8: ## %cond.store13 ; AVX1-NEXT: vpextrq $1, %xmm1, (%rdi) ; AVX1-NEXT: addq $8, %rdi -; AVX1-NEXT: LBB9_12: ## %else14 +; AVX1-NEXT: LBB9_9: ## %else14 ; AVX1-NEXT: testb $64, %al ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm0 -; AVX1-NEXT: jne LBB9_13 -; AVX1-NEXT: ## %bb.14: ## %else17 -; AVX1-NEXT: testb $-128, %al ; AVX1-NEXT: jne LBB9_15 -; AVX1-NEXT: LBB9_16: ## %else20 +; AVX1-NEXT: ## %bb.10: ## %else17 +; AVX1-NEXT: testb $-128, %al +; AVX1-NEXT: jne LBB9_16 +; AVX1-NEXT: LBB9_11: ## %else20 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: LBB9_5: ## %cond.store4 +; AVX1-NEXT: LBB9_12: ## %cond.store4 ; AVX1-NEXT: vmovq %xmm0, (%rdi) ; AVX1-NEXT: addq $8, %rdi ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je LBB9_8 -; AVX1-NEXT: LBB9_7: ## %cond.store7 +; AVX1-NEXT: je LBB9_6 +; AVX1-NEXT: LBB9_13: ## %cond.store7 ; AVX1-NEXT: vpextrq $1, %xmm0, (%rdi) ; AVX1-NEXT: addq $8, %rdi ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: je LBB9_10 -; AVX1-NEXT: LBB9_9: ## %cond.store10 +; AVX1-NEXT: je LBB9_7 +; AVX1-NEXT: LBB9_14: ## %cond.store10 ; AVX1-NEXT: vmovq %xmm1, (%rdi) ; AVX1-NEXT: addq $8, %rdi ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: jne LBB9_11 -; AVX1-NEXT: jmp LBB9_12 -; AVX1-NEXT: LBB9_13: ## %cond.store16 +; AVX1-NEXT: jne LBB9_8 +; AVX1-NEXT: jmp LBB9_9 +; AVX1-NEXT: LBB9_15: ## %cond.store16 ; AVX1-NEXT: vmovq %xmm0, (%rdi) ; AVX1-NEXT: addq $8, %rdi ; AVX1-NEXT: testb $-128, %al -; AVX1-NEXT: je LBB9_16 -; AVX1-NEXT: LBB9_15: ## %cond.store19 +; AVX1-NEXT: je LBB9_11 +; AVX1-NEXT: LBB9_16: ## %cond.store19 ; AVX1-NEXT: vpextrq $1, %xmm0, (%rdi) ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq @@ -2925,51 +2925,51 @@ define void @compressstore_v8i64_v8i1(ptr %base, <8 x i64> %V, <8 x i1> %mask) { ; AVX2-NEXT: LBB9_4: ## %else2 ; AVX2-NEXT: testb $4, %al ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0 -; AVX2-NEXT: jne LBB9_5 -; AVX2-NEXT: ## %bb.6: ## %else5 +; AVX2-NEXT: jne LBB9_12 +; AVX2-NEXT: ## %bb.5: ## %else5 ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: jne LBB9_7 -; AVX2-NEXT: LBB9_8: ## %else8 +; AVX2-NEXT: jne LBB9_13 +; AVX2-NEXT: LBB9_6: ## %else8 ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: jne LBB9_9 -; AVX2-NEXT: LBB9_10: ## %else11 +; AVX2-NEXT: jne LBB9_14 +; AVX2-NEXT: LBB9_7: ## %else11 ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: je LBB9_12 -; AVX2-NEXT: LBB9_11: ## %cond.store13 +; AVX2-NEXT: je LBB9_9 +; AVX2-NEXT: LBB9_8: ## %cond.store13 ; AVX2-NEXT: vpextrq $1, %xmm1, (%rdi) ; AVX2-NEXT: addq $8, %rdi -; AVX2-NEXT: LBB9_12: ## %else14 +; AVX2-NEXT: LBB9_9: ## %else14 ; AVX2-NEXT: testb $64, %al ; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm0 -; AVX2-NEXT: jne LBB9_13 -; AVX2-NEXT: ## %bb.14: ## %else17 -; AVX2-NEXT: testb $-128, %al ; AVX2-NEXT: jne LBB9_15 -; AVX2-NEXT: LBB9_16: ## %else20 +; AVX2-NEXT: ## %bb.10: ## %else17 +; AVX2-NEXT: testb $-128, %al +; AVX2-NEXT: jne LBB9_16 +; AVX2-NEXT: LBB9_11: ## %else20 ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; AVX2-NEXT: LBB9_5: ## %cond.store4 +; AVX2-NEXT: LBB9_12: ## %cond.store4 ; AVX2-NEXT: vmovq %xmm0, (%rdi) ; AVX2-NEXT: addq $8, %rdi ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je LBB9_8 -; AVX2-NEXT: LBB9_7: ## %cond.store7 +; AVX2-NEXT: je LBB9_6 +; AVX2-NEXT: LBB9_13: ## %cond.store7 ; AVX2-NEXT: vpextrq $1, %xmm0, (%rdi) ; AVX2-NEXT: addq $8, %rdi ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: je LBB9_10 -; AVX2-NEXT: LBB9_9: ## %cond.store10 +; AVX2-NEXT: je LBB9_7 +; AVX2-NEXT: LBB9_14: ## %cond.store10 ; AVX2-NEXT: vmovq %xmm1, (%rdi) ; AVX2-NEXT: addq $8, %rdi ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: jne LBB9_11 -; AVX2-NEXT: jmp LBB9_12 -; AVX2-NEXT: LBB9_13: ## %cond.store16 +; AVX2-NEXT: jne LBB9_8 +; AVX2-NEXT: jmp LBB9_9 +; AVX2-NEXT: LBB9_15: ## %cond.store16 ; AVX2-NEXT: vmovq %xmm0, (%rdi) ; AVX2-NEXT: addq $8, %rdi ; AVX2-NEXT: testb $-128, %al -; AVX2-NEXT: je LBB9_16 -; AVX2-NEXT: LBB9_15: ## %cond.store19 +; AVX2-NEXT: je LBB9_11 +; AVX2-NEXT: LBB9_16: ## %cond.store19 ; AVX2-NEXT: vpextrq $1, %xmm0, (%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq @@ -3014,36 +3014,36 @@ define void @compressstore_v4i32_v4i32(ptr %base, <4 x i32> %V, <4 x i32> %trigg ; SSE2-NEXT: pcmpeqd %xmm1, %xmm2 ; SSE2-NEXT: movmskps %xmm2, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB10_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB10_5 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB10_3 -; SSE2-NEXT: LBB10_4: ## %else2 +; SSE2-NEXT: jne LBB10_6 +; SSE2-NEXT: LBB10_2: ## %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB10_5 -; SSE2-NEXT: LBB10_6: ## %else5 -; SSE2-NEXT: testb $8, %al ; SSE2-NEXT: jne LBB10_7 -; SSE2-NEXT: LBB10_8: ## %else8 +; SSE2-NEXT: LBB10_3: ## %else5 +; SSE2-NEXT: testb $8, %al +; SSE2-NEXT: jne LBB10_8 +; SSE2-NEXT: LBB10_4: ## %else8 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB10_1: ## %cond.store +; SSE2-NEXT: LBB10_5: ## %cond.store ; SSE2-NEXT: movd %xmm0, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB10_4 -; SSE2-NEXT: LBB10_3: ## %cond.store1 +; SSE2-NEXT: je LBB10_2 +; SSE2-NEXT: LBB10_6: ## %cond.store1 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1] ; SSE2-NEXT: movd %xmm1, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB10_6 -; SSE2-NEXT: LBB10_5: ## %cond.store4 +; SSE2-NEXT: je LBB10_3 +; SSE2-NEXT: LBB10_7: ## %cond.store4 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3] ; SSE2-NEXT: movd %xmm1, (%rdi) ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB10_8 -; SSE2-NEXT: LBB10_7: ## %cond.store7 +; SSE2-NEXT: je LBB10_4 +; SSE2-NEXT: LBB10_8: ## %cond.store7 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: movd %xmm0, (%rdi) ; SSE2-NEXT: retq @@ -3054,34 +3054,34 @@ define void @compressstore_v4i32_v4i32(ptr %base, <4 x i32> %V, <4 x i32> %trigg ; SSE42-NEXT: pcmpeqd %xmm1, %xmm2 ; SSE42-NEXT: movmskps %xmm2, %eax ; SSE42-NEXT: testb $1, %al -; SSE42-NEXT: jne LBB10_1 -; SSE42-NEXT: ## %bb.2: ## %else +; SSE42-NEXT: jne LBB10_5 +; SSE42-NEXT: ## %bb.1: ## %else ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: jne LBB10_3 -; SSE42-NEXT: LBB10_4: ## %else2 +; SSE42-NEXT: jne LBB10_6 +; SSE42-NEXT: LBB10_2: ## %else2 ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: jne LBB10_5 -; SSE42-NEXT: LBB10_6: ## %else5 -; SSE42-NEXT: testb $8, %al ; SSE42-NEXT: jne LBB10_7 -; SSE42-NEXT: LBB10_8: ## %else8 +; SSE42-NEXT: LBB10_3: ## %else5 +; SSE42-NEXT: testb $8, %al +; SSE42-NEXT: jne LBB10_8 +; SSE42-NEXT: LBB10_4: ## %else8 ; SSE42-NEXT: retq -; SSE42-NEXT: LBB10_1: ## %cond.store +; SSE42-NEXT: LBB10_5: ## %cond.store ; SSE42-NEXT: movss %xmm0, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: je LBB10_4 -; SSE42-NEXT: LBB10_3: ## %cond.store1 +; SSE42-NEXT: je LBB10_2 +; SSE42-NEXT: LBB10_6: ## %cond.store1 ; SSE42-NEXT: extractps $1, %xmm0, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: je LBB10_6 -; SSE42-NEXT: LBB10_5: ## %cond.store4 +; SSE42-NEXT: je LBB10_3 +; SSE42-NEXT: LBB10_7: ## %cond.store4 ; SSE42-NEXT: extractps $2, %xmm0, (%rdi) ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: je LBB10_8 -; SSE42-NEXT: LBB10_7: ## %cond.store7 +; SSE42-NEXT: je LBB10_4 +; SSE42-NEXT: LBB10_8: ## %cond.store7 ; SSE42-NEXT: extractps $3, %xmm0, (%rdi) ; SSE42-NEXT: retq ; @@ -3091,34 +3091,34 @@ define void @compressstore_v4i32_v4i32(ptr %base, <4 x i32> %V, <4 x i32> %trigg ; AVX1OR2-NEXT: vpcmpeqd %xmm2, %xmm1, %xmm1 ; AVX1OR2-NEXT: vmovmskps %xmm1, %eax ; AVX1OR2-NEXT: testb $1, %al -; AVX1OR2-NEXT: jne LBB10_1 -; AVX1OR2-NEXT: ## %bb.2: ## %else +; AVX1OR2-NEXT: jne LBB10_5 +; AVX1OR2-NEXT: ## %bb.1: ## %else ; AVX1OR2-NEXT: testb $2, %al -; AVX1OR2-NEXT: jne LBB10_3 -; AVX1OR2-NEXT: LBB10_4: ## %else2 +; AVX1OR2-NEXT: jne LBB10_6 +; AVX1OR2-NEXT: LBB10_2: ## %else2 ; AVX1OR2-NEXT: testb $4, %al -; AVX1OR2-NEXT: jne LBB10_5 -; AVX1OR2-NEXT: LBB10_6: ## %else5 -; AVX1OR2-NEXT: testb $8, %al ; AVX1OR2-NEXT: jne LBB10_7 -; AVX1OR2-NEXT: LBB10_8: ## %else8 +; AVX1OR2-NEXT: LBB10_3: ## %else5 +; AVX1OR2-NEXT: testb $8, %al +; AVX1OR2-NEXT: jne LBB10_8 +; AVX1OR2-NEXT: LBB10_4: ## %else8 ; AVX1OR2-NEXT: retq -; AVX1OR2-NEXT: LBB10_1: ## %cond.store +; AVX1OR2-NEXT: LBB10_5: ## %cond.store ; AVX1OR2-NEXT: vmovss %xmm0, (%rdi) ; AVX1OR2-NEXT: addq $4, %rdi ; AVX1OR2-NEXT: testb $2, %al -; AVX1OR2-NEXT: je LBB10_4 -; AVX1OR2-NEXT: LBB10_3: ## %cond.store1 +; AVX1OR2-NEXT: je LBB10_2 +; AVX1OR2-NEXT: LBB10_6: ## %cond.store1 ; AVX1OR2-NEXT: vextractps $1, %xmm0, (%rdi) ; AVX1OR2-NEXT: addq $4, %rdi ; AVX1OR2-NEXT: testb $4, %al -; AVX1OR2-NEXT: je LBB10_6 -; AVX1OR2-NEXT: LBB10_5: ## %cond.store4 +; AVX1OR2-NEXT: je LBB10_3 +; AVX1OR2-NEXT: LBB10_7: ## %cond.store4 ; AVX1OR2-NEXT: vextractps $2, %xmm0, (%rdi) ; AVX1OR2-NEXT: addq $4, %rdi ; AVX1OR2-NEXT: testb $8, %al -; AVX1OR2-NEXT: je LBB10_8 -; AVX1OR2-NEXT: LBB10_7: ## %cond.store7 +; AVX1OR2-NEXT: je LBB10_4 +; AVX1OR2-NEXT: LBB10_8: ## %cond.store7 ; AVX1OR2-NEXT: vextractps $3, %xmm0, (%rdi) ; AVX1OR2-NEXT: retq ; @@ -3155,73 +3155,73 @@ define void @compressstore_v8i16_v8i16(ptr %base, <8 x i16> %V, <8 x i16> %trigg ; SSE2-NEXT: packsswb %xmm2, %xmm2 ; SSE2-NEXT: pmovmskb %xmm2, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB11_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB11_9 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB11_3 -; SSE2-NEXT: LBB11_4: ## %else2 +; SSE2-NEXT: jne LBB11_10 +; SSE2-NEXT: LBB11_2: ## %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB11_5 -; SSE2-NEXT: LBB11_6: ## %else5 +; SSE2-NEXT: jne LBB11_11 +; SSE2-NEXT: LBB11_3: ## %else5 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne LBB11_7 -; SSE2-NEXT: LBB11_8: ## %else8 +; SSE2-NEXT: jne LBB11_12 +; SSE2-NEXT: LBB11_4: ## %else8 ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: jne LBB11_9 -; SSE2-NEXT: LBB11_10: ## %else11 +; SSE2-NEXT: jne LBB11_13 +; SSE2-NEXT: LBB11_5: ## %else11 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: jne LBB11_11 -; SSE2-NEXT: LBB11_12: ## %else14 +; SSE2-NEXT: jne LBB11_14 +; SSE2-NEXT: LBB11_6: ## %else14 ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: jne LBB11_13 -; SSE2-NEXT: LBB11_14: ## %else17 -; SSE2-NEXT: testb $-128, %al ; SSE2-NEXT: jne LBB11_15 -; SSE2-NEXT: LBB11_16: ## %else20 +; SSE2-NEXT: LBB11_7: ## %else17 +; SSE2-NEXT: testb $-128, %al +; SSE2-NEXT: jne LBB11_16 +; SSE2-NEXT: LBB11_8: ## %else20 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB11_1: ## %cond.store +; SSE2-NEXT: LBB11_9: ## %cond.store ; SSE2-NEXT: movd %xmm0, %ecx ; SSE2-NEXT: movw %cx, (%rdi) ; SSE2-NEXT: addq $2, %rdi ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB11_4 -; SSE2-NEXT: LBB11_3: ## %cond.store1 +; SSE2-NEXT: je LBB11_2 +; SSE2-NEXT: LBB11_10: ## %cond.store1 ; SSE2-NEXT: pextrw $1, %xmm0, %ecx ; SSE2-NEXT: movw %cx, (%rdi) ; SSE2-NEXT: addq $2, %rdi ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB11_6 -; SSE2-NEXT: LBB11_5: ## %cond.store4 +; SSE2-NEXT: je LBB11_3 +; SSE2-NEXT: LBB11_11: ## %cond.store4 ; SSE2-NEXT: pextrw $2, %xmm0, %ecx ; SSE2-NEXT: movw %cx, (%rdi) ; SSE2-NEXT: addq $2, %rdi ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB11_8 -; SSE2-NEXT: LBB11_7: ## %cond.store7 +; SSE2-NEXT: je LBB11_4 +; SSE2-NEXT: LBB11_12: ## %cond.store7 ; SSE2-NEXT: pextrw $3, %xmm0, %ecx ; SSE2-NEXT: movw %cx, (%rdi) ; SSE2-NEXT: addq $2, %rdi ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: je LBB11_10 -; SSE2-NEXT: LBB11_9: ## %cond.store10 +; SSE2-NEXT: je LBB11_5 +; SSE2-NEXT: LBB11_13: ## %cond.store10 ; SSE2-NEXT: pextrw $4, %xmm0, %ecx ; SSE2-NEXT: movw %cx, (%rdi) ; SSE2-NEXT: addq $2, %rdi ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je LBB11_12 -; SSE2-NEXT: LBB11_11: ## %cond.store13 +; SSE2-NEXT: je LBB11_6 +; SSE2-NEXT: LBB11_14: ## %cond.store13 ; SSE2-NEXT: pextrw $5, %xmm0, %ecx ; SSE2-NEXT: movw %cx, (%rdi) ; SSE2-NEXT: addq $2, %rdi ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: je LBB11_14 -; SSE2-NEXT: LBB11_13: ## %cond.store16 +; SSE2-NEXT: je LBB11_7 +; SSE2-NEXT: LBB11_15: ## %cond.store16 ; SSE2-NEXT: pextrw $6, %xmm0, %ecx ; SSE2-NEXT: movw %cx, (%rdi) ; SSE2-NEXT: addq $2, %rdi ; SSE2-NEXT: testb $-128, %al -; SSE2-NEXT: je LBB11_16 -; SSE2-NEXT: LBB11_15: ## %cond.store19 +; SSE2-NEXT: je LBB11_8 +; SSE2-NEXT: LBB11_16: ## %cond.store19 ; SSE2-NEXT: pextrw $7, %xmm0, %eax ; SSE2-NEXT: movw %ax, (%rdi) ; SSE2-NEXT: retq @@ -3233,66 +3233,66 @@ define void @compressstore_v8i16_v8i16(ptr %base, <8 x i16> %V, <8 x i16> %trigg ; SSE42-NEXT: packsswb %xmm2, %xmm2 ; SSE42-NEXT: pmovmskb %xmm2, %eax ; SSE42-NEXT: testb $1, %al -; SSE42-NEXT: jne LBB11_1 -; SSE42-NEXT: ## %bb.2: ## %else +; SSE42-NEXT: jne LBB11_9 +; SSE42-NEXT: ## %bb.1: ## %else ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: jne LBB11_3 -; SSE42-NEXT: LBB11_4: ## %else2 +; SSE42-NEXT: jne LBB11_10 +; SSE42-NEXT: LBB11_2: ## %else2 ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: jne LBB11_5 -; SSE42-NEXT: LBB11_6: ## %else5 +; SSE42-NEXT: jne LBB11_11 +; SSE42-NEXT: LBB11_3: ## %else5 ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: jne LBB11_7 -; SSE42-NEXT: LBB11_8: ## %else8 +; SSE42-NEXT: jne LBB11_12 +; SSE42-NEXT: LBB11_4: ## %else8 ; SSE42-NEXT: testb $16, %al -; SSE42-NEXT: jne LBB11_9 -; SSE42-NEXT: LBB11_10: ## %else11 +; SSE42-NEXT: jne LBB11_13 +; SSE42-NEXT: LBB11_5: ## %else11 ; SSE42-NEXT: testb $32, %al -; SSE42-NEXT: jne LBB11_11 -; SSE42-NEXT: LBB11_12: ## %else14 +; SSE42-NEXT: jne LBB11_14 +; SSE42-NEXT: LBB11_6: ## %else14 ; SSE42-NEXT: testb $64, %al -; SSE42-NEXT: jne LBB11_13 -; SSE42-NEXT: LBB11_14: ## %else17 -; SSE42-NEXT: testb $-128, %al ; SSE42-NEXT: jne LBB11_15 -; SSE42-NEXT: LBB11_16: ## %else20 +; SSE42-NEXT: LBB11_7: ## %else17 +; SSE42-NEXT: testb $-128, %al +; SSE42-NEXT: jne LBB11_16 +; SSE42-NEXT: LBB11_8: ## %else20 ; SSE42-NEXT: retq -; SSE42-NEXT: LBB11_1: ## %cond.store +; SSE42-NEXT: LBB11_9: ## %cond.store ; SSE42-NEXT: pextrw $0, %xmm0, (%rdi) ; SSE42-NEXT: addq $2, %rdi ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: je LBB11_4 -; SSE42-NEXT: LBB11_3: ## %cond.store1 +; SSE42-NEXT: je LBB11_2 +; SSE42-NEXT: LBB11_10: ## %cond.store1 ; SSE42-NEXT: pextrw $1, %xmm0, (%rdi) ; SSE42-NEXT: addq $2, %rdi ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: je LBB11_6 -; SSE42-NEXT: LBB11_5: ## %cond.store4 +; SSE42-NEXT: je LBB11_3 +; SSE42-NEXT: LBB11_11: ## %cond.store4 ; SSE42-NEXT: pextrw $2, %xmm0, (%rdi) ; SSE42-NEXT: addq $2, %rdi ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: je LBB11_8 -; SSE42-NEXT: LBB11_7: ## %cond.store7 +; SSE42-NEXT: je LBB11_4 +; SSE42-NEXT: LBB11_12: ## %cond.store7 ; SSE42-NEXT: pextrw $3, %xmm0, (%rdi) ; SSE42-NEXT: addq $2, %rdi ; SSE42-NEXT: testb $16, %al -; SSE42-NEXT: je LBB11_10 -; SSE42-NEXT: LBB11_9: ## %cond.store10 +; SSE42-NEXT: je LBB11_5 +; SSE42-NEXT: LBB11_13: ## %cond.store10 ; SSE42-NEXT: pextrw $4, %xmm0, (%rdi) ; SSE42-NEXT: addq $2, %rdi ; SSE42-NEXT: testb $32, %al -; SSE42-NEXT: je LBB11_12 -; SSE42-NEXT: LBB11_11: ## %cond.store13 +; SSE42-NEXT: je LBB11_6 +; SSE42-NEXT: LBB11_14: ## %cond.store13 ; SSE42-NEXT: pextrw $5, %xmm0, (%rdi) ; SSE42-NEXT: addq $2, %rdi ; SSE42-NEXT: testb $64, %al -; SSE42-NEXT: je LBB11_14 -; SSE42-NEXT: LBB11_13: ## %cond.store16 +; SSE42-NEXT: je LBB11_7 +; SSE42-NEXT: LBB11_15: ## %cond.store16 ; SSE42-NEXT: pextrw $6, %xmm0, (%rdi) ; SSE42-NEXT: addq $2, %rdi ; SSE42-NEXT: testb $-128, %al -; SSE42-NEXT: je LBB11_16 -; SSE42-NEXT: LBB11_15: ## %cond.store19 +; SSE42-NEXT: je LBB11_8 +; SSE42-NEXT: LBB11_16: ## %cond.store19 ; SSE42-NEXT: pextrw $7, %xmm0, (%rdi) ; SSE42-NEXT: retq ; @@ -3303,66 +3303,66 @@ define void @compressstore_v8i16_v8i16(ptr %base, <8 x i16> %V, <8 x i16> %trigg ; AVX1OR2-NEXT: vpacksswb %xmm1, %xmm1, %xmm1 ; AVX1OR2-NEXT: vpmovmskb %xmm1, %eax ; AVX1OR2-NEXT: testb $1, %al -; AVX1OR2-NEXT: jne LBB11_1 -; AVX1OR2-NEXT: ## %bb.2: ## %else +; AVX1OR2-NEXT: jne LBB11_9 +; AVX1OR2-NEXT: ## %bb.1: ## %else ; AVX1OR2-NEXT: testb $2, %al -; AVX1OR2-NEXT: jne LBB11_3 -; AVX1OR2-NEXT: LBB11_4: ## %else2 +; AVX1OR2-NEXT: jne LBB11_10 +; AVX1OR2-NEXT: LBB11_2: ## %else2 ; AVX1OR2-NEXT: testb $4, %al -; AVX1OR2-NEXT: jne LBB11_5 -; AVX1OR2-NEXT: LBB11_6: ## %else5 +; AVX1OR2-NEXT: jne LBB11_11 +; AVX1OR2-NEXT: LBB11_3: ## %else5 ; AVX1OR2-NEXT: testb $8, %al -; AVX1OR2-NEXT: jne LBB11_7 -; AVX1OR2-NEXT: LBB11_8: ## %else8 +; AVX1OR2-NEXT: jne LBB11_12 +; AVX1OR2-NEXT: LBB11_4: ## %else8 ; AVX1OR2-NEXT: testb $16, %al -; AVX1OR2-NEXT: jne LBB11_9 -; AVX1OR2-NEXT: LBB11_10: ## %else11 +; AVX1OR2-NEXT: jne LBB11_13 +; AVX1OR2-NEXT: LBB11_5: ## %else11 ; AVX1OR2-NEXT: testb $32, %al -; AVX1OR2-NEXT: jne LBB11_11 -; AVX1OR2-NEXT: LBB11_12: ## %else14 +; AVX1OR2-NEXT: jne LBB11_14 +; AVX1OR2-NEXT: LBB11_6: ## %else14 ; AVX1OR2-NEXT: testb $64, %al -; AVX1OR2-NEXT: jne LBB11_13 -; AVX1OR2-NEXT: LBB11_14: ## %else17 -; AVX1OR2-NEXT: testb $-128, %al ; AVX1OR2-NEXT: jne LBB11_15 -; AVX1OR2-NEXT: LBB11_16: ## %else20 +; AVX1OR2-NEXT: LBB11_7: ## %else17 +; AVX1OR2-NEXT: testb $-128, %al +; AVX1OR2-NEXT: jne LBB11_16 +; AVX1OR2-NEXT: LBB11_8: ## %else20 ; AVX1OR2-NEXT: retq -; AVX1OR2-NEXT: LBB11_1: ## %cond.store +; AVX1OR2-NEXT: LBB11_9: ## %cond.store ; AVX1OR2-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX1OR2-NEXT: addq $2, %rdi ; AVX1OR2-NEXT: testb $2, %al -; AVX1OR2-NEXT: je LBB11_4 -; AVX1OR2-NEXT: LBB11_3: ## %cond.store1 +; AVX1OR2-NEXT: je LBB11_2 +; AVX1OR2-NEXT: LBB11_10: ## %cond.store1 ; AVX1OR2-NEXT: vpextrw $1, %xmm0, (%rdi) ; AVX1OR2-NEXT: addq $2, %rdi ; AVX1OR2-NEXT: testb $4, %al -; AVX1OR2-NEXT: je LBB11_6 -; AVX1OR2-NEXT: LBB11_5: ## %cond.store4 +; AVX1OR2-NEXT: je LBB11_3 +; AVX1OR2-NEXT: LBB11_11: ## %cond.store4 ; AVX1OR2-NEXT: vpextrw $2, %xmm0, (%rdi) ; AVX1OR2-NEXT: addq $2, %rdi ; AVX1OR2-NEXT: testb $8, %al -; AVX1OR2-NEXT: je LBB11_8 -; AVX1OR2-NEXT: LBB11_7: ## %cond.store7 +; AVX1OR2-NEXT: je LBB11_4 +; AVX1OR2-NEXT: LBB11_12: ## %cond.store7 ; AVX1OR2-NEXT: vpextrw $3, %xmm0, (%rdi) ; AVX1OR2-NEXT: addq $2, %rdi ; AVX1OR2-NEXT: testb $16, %al -; AVX1OR2-NEXT: je LBB11_10 -; AVX1OR2-NEXT: LBB11_9: ## %cond.store10 +; AVX1OR2-NEXT: je LBB11_5 +; AVX1OR2-NEXT: LBB11_13: ## %cond.store10 ; AVX1OR2-NEXT: vpextrw $4, %xmm0, (%rdi) ; AVX1OR2-NEXT: addq $2, %rdi ; AVX1OR2-NEXT: testb $32, %al -; AVX1OR2-NEXT: je LBB11_12 -; AVX1OR2-NEXT: LBB11_11: ## %cond.store13 +; AVX1OR2-NEXT: je LBB11_6 +; AVX1OR2-NEXT: LBB11_14: ## %cond.store13 ; AVX1OR2-NEXT: vpextrw $5, %xmm0, (%rdi) ; AVX1OR2-NEXT: addq $2, %rdi ; AVX1OR2-NEXT: testb $64, %al -; AVX1OR2-NEXT: je LBB11_14 -; AVX1OR2-NEXT: LBB11_13: ## %cond.store16 +; AVX1OR2-NEXT: je LBB11_7 +; AVX1OR2-NEXT: LBB11_15: ## %cond.store16 ; AVX1OR2-NEXT: vpextrw $6, %xmm0, (%rdi) ; AVX1OR2-NEXT: addq $2, %rdi ; AVX1OR2-NEXT: testb $-128, %al -; AVX1OR2-NEXT: je LBB11_16 -; AVX1OR2-NEXT: LBB11_15: ## %cond.store19 +; AVX1OR2-NEXT: je LBB11_8 +; AVX1OR2-NEXT: LBB11_16: ## %cond.store19 ; AVX1OR2-NEXT: vpextrw $7, %xmm0, (%rdi) ; AVX1OR2-NEXT: retq ; @@ -3374,67 +3374,67 @@ define void @compressstore_v8i16_v8i16(ptr %base, <8 x i16> %V, <8 x i16> %trigg ; AVX512F-NEXT: vptestmq %zmm1, %zmm1, %k0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne LBB11_1 -; AVX512F-NEXT: ## %bb.2: ## %else +; AVX512F-NEXT: jne LBB11_9 +; AVX512F-NEXT: ## %bb.1: ## %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne LBB11_3 -; AVX512F-NEXT: LBB11_4: ## %else2 +; AVX512F-NEXT: jne LBB11_10 +; AVX512F-NEXT: LBB11_2: ## %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne LBB11_5 -; AVX512F-NEXT: LBB11_6: ## %else5 +; AVX512F-NEXT: jne LBB11_11 +; AVX512F-NEXT: LBB11_3: ## %else5 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne LBB11_7 -; AVX512F-NEXT: LBB11_8: ## %else8 +; AVX512F-NEXT: jne LBB11_12 +; AVX512F-NEXT: LBB11_4: ## %else8 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne LBB11_9 -; AVX512F-NEXT: LBB11_10: ## %else11 +; AVX512F-NEXT: jne LBB11_13 +; AVX512F-NEXT: LBB11_5: ## %else11 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne LBB11_11 -; AVX512F-NEXT: LBB11_12: ## %else14 +; AVX512F-NEXT: jne LBB11_14 +; AVX512F-NEXT: LBB11_6: ## %else14 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne LBB11_13 -; AVX512F-NEXT: LBB11_14: ## %else17 -; AVX512F-NEXT: testb $-128, %al ; AVX512F-NEXT: jne LBB11_15 -; AVX512F-NEXT: LBB11_16: ## %else20 +; AVX512F-NEXT: LBB11_7: ## %else17 +; AVX512F-NEXT: testb $-128, %al +; AVX512F-NEXT: jne LBB11_16 +; AVX512F-NEXT: LBB11_8: ## %else20 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: LBB11_1: ## %cond.store +; AVX512F-NEXT: LBB11_9: ## %cond.store ; AVX512F-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512F-NEXT: addq $2, %rdi ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je LBB11_4 -; AVX512F-NEXT: LBB11_3: ## %cond.store1 +; AVX512F-NEXT: je LBB11_2 +; AVX512F-NEXT: LBB11_10: ## %cond.store1 ; AVX512F-NEXT: vpextrw $1, %xmm0, (%rdi) ; AVX512F-NEXT: addq $2, %rdi ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je LBB11_6 -; AVX512F-NEXT: LBB11_5: ## %cond.store4 +; AVX512F-NEXT: je LBB11_3 +; AVX512F-NEXT: LBB11_11: ## %cond.store4 ; AVX512F-NEXT: vpextrw $2, %xmm0, (%rdi) ; AVX512F-NEXT: addq $2, %rdi ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je LBB11_8 -; AVX512F-NEXT: LBB11_7: ## %cond.store7 +; AVX512F-NEXT: je LBB11_4 +; AVX512F-NEXT: LBB11_12: ## %cond.store7 ; AVX512F-NEXT: vpextrw $3, %xmm0, (%rdi) ; AVX512F-NEXT: addq $2, %rdi ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je LBB11_10 -; AVX512F-NEXT: LBB11_9: ## %cond.store10 +; AVX512F-NEXT: je LBB11_5 +; AVX512F-NEXT: LBB11_13: ## %cond.store10 ; AVX512F-NEXT: vpextrw $4, %xmm0, (%rdi) ; AVX512F-NEXT: addq $2, %rdi ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je LBB11_12 -; AVX512F-NEXT: LBB11_11: ## %cond.store13 +; AVX512F-NEXT: je LBB11_6 +; AVX512F-NEXT: LBB11_14: ## %cond.store13 ; AVX512F-NEXT: vpextrw $5, %xmm0, (%rdi) ; AVX512F-NEXT: addq $2, %rdi ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je LBB11_14 -; AVX512F-NEXT: LBB11_13: ## %cond.store16 +; AVX512F-NEXT: je LBB11_7 +; AVX512F-NEXT: LBB11_15: ## %cond.store16 ; AVX512F-NEXT: vpextrw $6, %xmm0, (%rdi) ; AVX512F-NEXT: addq $2, %rdi ; AVX512F-NEXT: testb $-128, %al -; AVX512F-NEXT: je LBB11_16 -; AVX512F-NEXT: LBB11_15: ## %cond.store19 +; AVX512F-NEXT: je LBB11_8 +; AVX512F-NEXT: LBB11_16: ## %cond.store19 ; AVX512F-NEXT: vpextrw $7, %xmm0, (%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -3446,67 +3446,67 @@ define void @compressstore_v8i16_v8i16(ptr %base, <8 x i16> %V, <8 x i16> %trigg ; AVX512VLDQ-NEXT: vpmovsxwd %xmm1, %ymm1 ; AVX512VLDQ-NEXT: vmovmskps %ymm1, %eax ; AVX512VLDQ-NEXT: testb $1, %al -; AVX512VLDQ-NEXT: jne LBB11_1 -; AVX512VLDQ-NEXT: ## %bb.2: ## %else +; AVX512VLDQ-NEXT: jne LBB11_9 +; AVX512VLDQ-NEXT: ## %bb.1: ## %else ; AVX512VLDQ-NEXT: testb $2, %al -; AVX512VLDQ-NEXT: jne LBB11_3 -; AVX512VLDQ-NEXT: LBB11_4: ## %else2 +; AVX512VLDQ-NEXT: jne LBB11_10 +; AVX512VLDQ-NEXT: LBB11_2: ## %else2 ; AVX512VLDQ-NEXT: testb $4, %al -; AVX512VLDQ-NEXT: jne LBB11_5 -; AVX512VLDQ-NEXT: LBB11_6: ## %else5 +; AVX512VLDQ-NEXT: jne LBB11_11 +; AVX512VLDQ-NEXT: LBB11_3: ## %else5 ; AVX512VLDQ-NEXT: testb $8, %al -; AVX512VLDQ-NEXT: jne LBB11_7 -; AVX512VLDQ-NEXT: LBB11_8: ## %else8 +; AVX512VLDQ-NEXT: jne LBB11_12 +; AVX512VLDQ-NEXT: LBB11_4: ## %else8 ; AVX512VLDQ-NEXT: testb $16, %al -; AVX512VLDQ-NEXT: jne LBB11_9 -; AVX512VLDQ-NEXT: LBB11_10: ## %else11 +; AVX512VLDQ-NEXT: jne LBB11_13 +; AVX512VLDQ-NEXT: LBB11_5: ## %else11 ; AVX512VLDQ-NEXT: testb $32, %al -; AVX512VLDQ-NEXT: jne LBB11_11 -; AVX512VLDQ-NEXT: LBB11_12: ## %else14 +; AVX512VLDQ-NEXT: jne LBB11_14 +; AVX512VLDQ-NEXT: LBB11_6: ## %else14 ; AVX512VLDQ-NEXT: testb $64, %al -; AVX512VLDQ-NEXT: jne LBB11_13 -; AVX512VLDQ-NEXT: LBB11_14: ## %else17 -; AVX512VLDQ-NEXT: testb $-128, %al ; AVX512VLDQ-NEXT: jne LBB11_15 -; AVX512VLDQ-NEXT: LBB11_16: ## %else20 +; AVX512VLDQ-NEXT: LBB11_7: ## %else17 +; AVX512VLDQ-NEXT: testb $-128, %al +; AVX512VLDQ-NEXT: jne LBB11_16 +; AVX512VLDQ-NEXT: LBB11_8: ## %else20 ; AVX512VLDQ-NEXT: vzeroupper ; AVX512VLDQ-NEXT: retq -; AVX512VLDQ-NEXT: LBB11_1: ## %cond.store +; AVX512VLDQ-NEXT: LBB11_9: ## %cond.store ; AVX512VLDQ-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512VLDQ-NEXT: addq $2, %rdi ; AVX512VLDQ-NEXT: testb $2, %al -; AVX512VLDQ-NEXT: je LBB11_4 -; AVX512VLDQ-NEXT: LBB11_3: ## %cond.store1 +; AVX512VLDQ-NEXT: je LBB11_2 +; AVX512VLDQ-NEXT: LBB11_10: ## %cond.store1 ; AVX512VLDQ-NEXT: vpextrw $1, %xmm0, (%rdi) ; AVX512VLDQ-NEXT: addq $2, %rdi ; AVX512VLDQ-NEXT: testb $4, %al -; AVX512VLDQ-NEXT: je LBB11_6 -; AVX512VLDQ-NEXT: LBB11_5: ## %cond.store4 +; AVX512VLDQ-NEXT: je LBB11_3 +; AVX512VLDQ-NEXT: LBB11_11: ## %cond.store4 ; AVX512VLDQ-NEXT: vpextrw $2, %xmm0, (%rdi) ; AVX512VLDQ-NEXT: addq $2, %rdi ; AVX512VLDQ-NEXT: testb $8, %al -; AVX512VLDQ-NEXT: je LBB11_8 -; AVX512VLDQ-NEXT: LBB11_7: ## %cond.store7 +; AVX512VLDQ-NEXT: je LBB11_4 +; AVX512VLDQ-NEXT: LBB11_12: ## %cond.store7 ; AVX512VLDQ-NEXT: vpextrw $3, %xmm0, (%rdi) ; AVX512VLDQ-NEXT: addq $2, %rdi ; AVX512VLDQ-NEXT: testb $16, %al -; AVX512VLDQ-NEXT: je LBB11_10 -; AVX512VLDQ-NEXT: LBB11_9: ## %cond.store10 +; AVX512VLDQ-NEXT: je LBB11_5 +; AVX512VLDQ-NEXT: LBB11_13: ## %cond.store10 ; AVX512VLDQ-NEXT: vpextrw $4, %xmm0, (%rdi) ; AVX512VLDQ-NEXT: addq $2, %rdi ; AVX512VLDQ-NEXT: testb $32, %al -; AVX512VLDQ-NEXT: je LBB11_12 -; AVX512VLDQ-NEXT: LBB11_11: ## %cond.store13 +; AVX512VLDQ-NEXT: je LBB11_6 +; AVX512VLDQ-NEXT: LBB11_14: ## %cond.store13 ; AVX512VLDQ-NEXT: vpextrw $5, %xmm0, (%rdi) ; AVX512VLDQ-NEXT: addq $2, %rdi ; AVX512VLDQ-NEXT: testb $64, %al -; AVX512VLDQ-NEXT: je LBB11_14 -; AVX512VLDQ-NEXT: LBB11_13: ## %cond.store16 +; AVX512VLDQ-NEXT: je LBB11_7 +; AVX512VLDQ-NEXT: LBB11_15: ## %cond.store16 ; AVX512VLDQ-NEXT: vpextrw $6, %xmm0, (%rdi) ; AVX512VLDQ-NEXT: addq $2, %rdi ; AVX512VLDQ-NEXT: testb $-128, %al -; AVX512VLDQ-NEXT: je LBB11_16 -; AVX512VLDQ-NEXT: LBB11_15: ## %cond.store19 +; AVX512VLDQ-NEXT: je LBB11_8 +; AVX512VLDQ-NEXT: LBB11_16: ## %cond.store19 ; AVX512VLDQ-NEXT: vpextrw $7, %xmm0, (%rdi) ; AVX512VLDQ-NEXT: vzeroupper ; AVX512VLDQ-NEXT: retq @@ -3516,66 +3516,66 @@ define void @compressstore_v8i16_v8i16(ptr %base, <8 x i16> %V, <8 x i16> %trigg ; AVX512VLBW-NEXT: vptestnmw %xmm1, %xmm1, %k0 ; AVX512VLBW-NEXT: kmovd %k0, %eax ; AVX512VLBW-NEXT: testb $1, %al -; AVX512VLBW-NEXT: jne LBB11_1 -; AVX512VLBW-NEXT: ## %bb.2: ## %else +; AVX512VLBW-NEXT: jne LBB11_9 +; AVX512VLBW-NEXT: ## %bb.1: ## %else ; AVX512VLBW-NEXT: testb $2, %al -; AVX512VLBW-NEXT: jne LBB11_3 -; AVX512VLBW-NEXT: LBB11_4: ## %else2 +; AVX512VLBW-NEXT: jne LBB11_10 +; AVX512VLBW-NEXT: LBB11_2: ## %else2 ; AVX512VLBW-NEXT: testb $4, %al -; AVX512VLBW-NEXT: jne LBB11_5 -; AVX512VLBW-NEXT: LBB11_6: ## %else5 +; AVX512VLBW-NEXT: jne LBB11_11 +; AVX512VLBW-NEXT: LBB11_3: ## %else5 ; AVX512VLBW-NEXT: testb $8, %al -; AVX512VLBW-NEXT: jne LBB11_7 -; AVX512VLBW-NEXT: LBB11_8: ## %else8 +; AVX512VLBW-NEXT: jne LBB11_12 +; AVX512VLBW-NEXT: LBB11_4: ## %else8 ; AVX512VLBW-NEXT: testb $16, %al -; AVX512VLBW-NEXT: jne LBB11_9 -; AVX512VLBW-NEXT: LBB11_10: ## %else11 +; AVX512VLBW-NEXT: jne LBB11_13 +; AVX512VLBW-NEXT: LBB11_5: ## %else11 ; AVX512VLBW-NEXT: testb $32, %al -; AVX512VLBW-NEXT: jne LBB11_11 -; AVX512VLBW-NEXT: LBB11_12: ## %else14 +; AVX512VLBW-NEXT: jne LBB11_14 +; AVX512VLBW-NEXT: LBB11_6: ## %else14 ; AVX512VLBW-NEXT: testb $64, %al -; AVX512VLBW-NEXT: jne LBB11_13 -; AVX512VLBW-NEXT: LBB11_14: ## %else17 -; AVX512VLBW-NEXT: testb $-128, %al ; AVX512VLBW-NEXT: jne LBB11_15 -; AVX512VLBW-NEXT: LBB11_16: ## %else20 +; AVX512VLBW-NEXT: LBB11_7: ## %else17 +; AVX512VLBW-NEXT: testb $-128, %al +; AVX512VLBW-NEXT: jne LBB11_16 +; AVX512VLBW-NEXT: LBB11_8: ## %else20 ; AVX512VLBW-NEXT: retq -; AVX512VLBW-NEXT: LBB11_1: ## %cond.store +; AVX512VLBW-NEXT: LBB11_9: ## %cond.store ; AVX512VLBW-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512VLBW-NEXT: addq $2, %rdi ; AVX512VLBW-NEXT: testb $2, %al -; AVX512VLBW-NEXT: je LBB11_4 -; AVX512VLBW-NEXT: LBB11_3: ## %cond.store1 +; AVX512VLBW-NEXT: je LBB11_2 +; AVX512VLBW-NEXT: LBB11_10: ## %cond.store1 ; AVX512VLBW-NEXT: vpextrw $1, %xmm0, (%rdi) ; AVX512VLBW-NEXT: addq $2, %rdi ; AVX512VLBW-NEXT: testb $4, %al -; AVX512VLBW-NEXT: je LBB11_6 -; AVX512VLBW-NEXT: LBB11_5: ## %cond.store4 +; AVX512VLBW-NEXT: je LBB11_3 +; AVX512VLBW-NEXT: LBB11_11: ## %cond.store4 ; AVX512VLBW-NEXT: vpextrw $2, %xmm0, (%rdi) ; AVX512VLBW-NEXT: addq $2, %rdi ; AVX512VLBW-NEXT: testb $8, %al -; AVX512VLBW-NEXT: je LBB11_8 -; AVX512VLBW-NEXT: LBB11_7: ## %cond.store7 +; AVX512VLBW-NEXT: je LBB11_4 +; AVX512VLBW-NEXT: LBB11_12: ## %cond.store7 ; AVX512VLBW-NEXT: vpextrw $3, %xmm0, (%rdi) ; AVX512VLBW-NEXT: addq $2, %rdi ; AVX512VLBW-NEXT: testb $16, %al -; AVX512VLBW-NEXT: je LBB11_10 -; AVX512VLBW-NEXT: LBB11_9: ## %cond.store10 +; AVX512VLBW-NEXT: je LBB11_5 +; AVX512VLBW-NEXT: LBB11_13: ## %cond.store10 ; AVX512VLBW-NEXT: vpextrw $4, %xmm0, (%rdi) ; AVX512VLBW-NEXT: addq $2, %rdi ; AVX512VLBW-NEXT: testb $32, %al -; AVX512VLBW-NEXT: je LBB11_12 -; AVX512VLBW-NEXT: LBB11_11: ## %cond.store13 +; AVX512VLBW-NEXT: je LBB11_6 +; AVX512VLBW-NEXT: LBB11_14: ## %cond.store13 ; AVX512VLBW-NEXT: vpextrw $5, %xmm0, (%rdi) ; AVX512VLBW-NEXT: addq $2, %rdi ; AVX512VLBW-NEXT: testb $64, %al -; AVX512VLBW-NEXT: je LBB11_14 -; AVX512VLBW-NEXT: LBB11_13: ## %cond.store16 +; AVX512VLBW-NEXT: je LBB11_7 +; AVX512VLBW-NEXT: LBB11_15: ## %cond.store16 ; AVX512VLBW-NEXT: vpextrw $6, %xmm0, (%rdi) ; AVX512VLBW-NEXT: addq $2, %rdi ; AVX512VLBW-NEXT: testb $-128, %al -; AVX512VLBW-NEXT: je LBB11_16 -; AVX512VLBW-NEXT: LBB11_15: ## %cond.store19 +; AVX512VLBW-NEXT: je LBB11_8 +; AVX512VLBW-NEXT: LBB11_16: ## %cond.store19 ; AVX512VLBW-NEXT: vpextrw $7, %xmm0, (%rdi) ; AVX512VLBW-NEXT: retq %mask = icmp eq <8 x i16> %trigger, zeroinitializer @@ -3595,118 +3595,118 @@ define void @compressstore_v16i8_v16i8(ptr %base, <16 x i8> %V, <16 x i8> %trigg ; SSE2-NEXT: pmovmskb %xmm2, %eax ; SSE2-NEXT: testb $1, %al ; SSE2-NEXT: movd %xmm0, %ecx -; SSE2-NEXT: jne LBB12_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB12_28 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB12_3 -; SSE2-NEXT: LBB12_4: ## %else2 +; SSE2-NEXT: jne LBB12_29 +; SSE2-NEXT: LBB12_2: ## %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB12_5 -; SSE2-NEXT: LBB12_6: ## %else5 +; SSE2-NEXT: jne LBB12_30 +; SSE2-NEXT: LBB12_3: ## %else5 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB12_8 -; SSE2-NEXT: LBB12_7: ## %cond.store7 +; SSE2-NEXT: je LBB12_5 +; SSE2-NEXT: LBB12_4: ## %cond.store7 ; SSE2-NEXT: shrl $24, %ecx ; SSE2-NEXT: movb %cl, (%rdi) ; SSE2-NEXT: incq %rdi -; SSE2-NEXT: LBB12_8: ## %else8 +; SSE2-NEXT: LBB12_5: ## %else8 ; SSE2-NEXT: testb $16, %al ; SSE2-NEXT: pextrw $2, %xmm0, %ecx -; SSE2-NEXT: je LBB12_10 -; SSE2-NEXT: ## %bb.9: ## %cond.store10 +; SSE2-NEXT: je LBB12_7 +; SSE2-NEXT: ## %bb.6: ## %cond.store10 ; SSE2-NEXT: movb %cl, (%rdi) ; SSE2-NEXT: incq %rdi -; SSE2-NEXT: LBB12_10: ## %else11 +; SSE2-NEXT: LBB12_7: ## %else11 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je LBB12_12 -; SSE2-NEXT: ## %bb.11: ## %cond.store13 +; SSE2-NEXT: je LBB12_9 +; SSE2-NEXT: ## %bb.8: ## %cond.store13 ; SSE2-NEXT: movb %ch, (%rdi) ; SSE2-NEXT: incq %rdi -; SSE2-NEXT: LBB12_12: ## %else14 +; SSE2-NEXT: LBB12_9: ## %else14 ; SSE2-NEXT: testb $64, %al ; SSE2-NEXT: pextrw $3, %xmm0, %ecx -; SSE2-NEXT: je LBB12_14 -; SSE2-NEXT: ## %bb.13: ## %cond.store16 +; SSE2-NEXT: je LBB12_11 +; SSE2-NEXT: ## %bb.10: ## %cond.store16 ; SSE2-NEXT: movb %cl, (%rdi) ; SSE2-NEXT: incq %rdi -; SSE2-NEXT: LBB12_14: ## %else17 +; SSE2-NEXT: LBB12_11: ## %else17 ; SSE2-NEXT: testb %al, %al -; SSE2-NEXT: jns LBB12_16 -; SSE2-NEXT: ## %bb.15: ## %cond.store19 +; SSE2-NEXT: jns LBB12_13 +; SSE2-NEXT: ## %bb.12: ## %cond.store19 ; SSE2-NEXT: movb %ch, (%rdi) ; SSE2-NEXT: incq %rdi -; SSE2-NEXT: LBB12_16: ## %else20 +; SSE2-NEXT: LBB12_13: ## %else20 ; SSE2-NEXT: testl $256, %eax ## imm = 0x100 ; SSE2-NEXT: pextrw $4, %xmm0, %ecx -; SSE2-NEXT: je LBB12_18 -; SSE2-NEXT: ## %bb.17: ## %cond.store22 +; SSE2-NEXT: je LBB12_15 +; SSE2-NEXT: ## %bb.14: ## %cond.store22 ; SSE2-NEXT: movb %cl, (%rdi) ; SSE2-NEXT: incq %rdi -; SSE2-NEXT: LBB12_18: ## %else23 +; SSE2-NEXT: LBB12_15: ## %else23 ; SSE2-NEXT: testl $512, %eax ## imm = 0x200 -; SSE2-NEXT: je LBB12_20 -; SSE2-NEXT: ## %bb.19: ## %cond.store25 +; SSE2-NEXT: je LBB12_17 +; SSE2-NEXT: ## %bb.16: ## %cond.store25 ; SSE2-NEXT: movb %ch, (%rdi) ; SSE2-NEXT: incq %rdi -; SSE2-NEXT: LBB12_20: ## %else26 +; SSE2-NEXT: LBB12_17: ## %else26 ; SSE2-NEXT: testl $1024, %eax ## imm = 0x400 ; SSE2-NEXT: pextrw $5, %xmm0, %ecx -; SSE2-NEXT: je LBB12_22 -; SSE2-NEXT: ## %bb.21: ## %cond.store28 +; SSE2-NEXT: je LBB12_19 +; SSE2-NEXT: ## %bb.18: ## %cond.store28 ; SSE2-NEXT: movb %cl, (%rdi) ; SSE2-NEXT: incq %rdi -; SSE2-NEXT: LBB12_22: ## %else29 +; SSE2-NEXT: LBB12_19: ## %else29 ; SSE2-NEXT: testl $2048, %eax ## imm = 0x800 -; SSE2-NEXT: je LBB12_24 -; SSE2-NEXT: ## %bb.23: ## %cond.store31 +; SSE2-NEXT: je LBB12_21 +; SSE2-NEXT: ## %bb.20: ## %cond.store31 ; SSE2-NEXT: movb %ch, (%rdi) ; SSE2-NEXT: incq %rdi -; SSE2-NEXT: LBB12_24: ## %else32 +; SSE2-NEXT: LBB12_21: ## %else32 ; SSE2-NEXT: testl $4096, %eax ## imm = 0x1000 ; SSE2-NEXT: pextrw $6, %xmm0, %ecx -; SSE2-NEXT: je LBB12_26 -; SSE2-NEXT: ## %bb.25: ## %cond.store34 +; SSE2-NEXT: je LBB12_23 +; SSE2-NEXT: ## %bb.22: ## %cond.store34 ; SSE2-NEXT: movb %cl, (%rdi) ; SSE2-NEXT: incq %rdi -; SSE2-NEXT: LBB12_26: ## %else35 +; SSE2-NEXT: LBB12_23: ## %else35 ; SSE2-NEXT: testl $8192, %eax ## imm = 0x2000 -; SSE2-NEXT: je LBB12_28 -; SSE2-NEXT: ## %bb.27: ## %cond.store37 +; SSE2-NEXT: je LBB12_25 +; SSE2-NEXT: ## %bb.24: ## %cond.store37 ; SSE2-NEXT: movb %ch, (%rdi) ; SSE2-NEXT: incq %rdi -; SSE2-NEXT: LBB12_28: ## %else38 +; SSE2-NEXT: LBB12_25: ## %else38 ; SSE2-NEXT: testl $16384, %eax ## imm = 0x4000 ; SSE2-NEXT: pextrw $7, %xmm0, %ecx -; SSE2-NEXT: jne LBB12_29 -; SSE2-NEXT: ## %bb.30: ## %else41 -; SSE2-NEXT: testl $32768, %eax ## imm = 0x8000 ; SSE2-NEXT: jne LBB12_31 -; SSE2-NEXT: LBB12_32: ## %else44 +; SSE2-NEXT: ## %bb.26: ## %else41 +; SSE2-NEXT: testl $32768, %eax ## imm = 0x8000 +; SSE2-NEXT: jne LBB12_32 +; SSE2-NEXT: LBB12_27: ## %else44 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB12_1: ## %cond.store +; SSE2-NEXT: LBB12_28: ## %cond.store ; SSE2-NEXT: movb %cl, (%rdi) ; SSE2-NEXT: incq %rdi ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB12_4 -; SSE2-NEXT: LBB12_3: ## %cond.store1 +; SSE2-NEXT: je LBB12_2 +; SSE2-NEXT: LBB12_29: ## %cond.store1 ; SSE2-NEXT: movb %ch, (%rdi) ; SSE2-NEXT: incq %rdi ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB12_6 -; SSE2-NEXT: LBB12_5: ## %cond.store4 +; SSE2-NEXT: je LBB12_3 +; SSE2-NEXT: LBB12_30: ## %cond.store4 ; SSE2-NEXT: movl %ecx, %edx ; SSE2-NEXT: shrl $16, %edx ; SSE2-NEXT: movb %dl, (%rdi) ; SSE2-NEXT: incq %rdi ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne LBB12_7 -; SSE2-NEXT: jmp LBB12_8 -; SSE2-NEXT: LBB12_29: ## %cond.store40 +; SSE2-NEXT: jne LBB12_4 +; SSE2-NEXT: jmp LBB12_5 +; SSE2-NEXT: LBB12_31: ## %cond.store40 ; SSE2-NEXT: movb %cl, (%rdi) ; SSE2-NEXT: incq %rdi ; SSE2-NEXT: testl $32768, %eax ## imm = 0x8000 -; SSE2-NEXT: je LBB12_32 -; SSE2-NEXT: LBB12_31: ## %cond.store43 +; SSE2-NEXT: je LBB12_27 +; SSE2-NEXT: LBB12_32: ## %cond.store43 ; SSE2-NEXT: movb %ch, (%rdi) ; SSE2-NEXT: retq ; @@ -3716,130 +3716,130 @@ define void @compressstore_v16i8_v16i8(ptr %base, <16 x i8> %V, <16 x i8> %trigg ; SSE42-NEXT: pcmpeqb %xmm1, %xmm2 ; SSE42-NEXT: pmovmskb %xmm2, %eax ; SSE42-NEXT: testb $1, %al -; SSE42-NEXT: jne LBB12_1 -; SSE42-NEXT: ## %bb.2: ## %else +; SSE42-NEXT: jne LBB12_17 +; SSE42-NEXT: ## %bb.1: ## %else ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: jne LBB12_3 -; SSE42-NEXT: LBB12_4: ## %else2 +; SSE42-NEXT: jne LBB12_18 +; SSE42-NEXT: LBB12_2: ## %else2 ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: jne LBB12_5 -; SSE42-NEXT: LBB12_6: ## %else5 +; SSE42-NEXT: jne LBB12_19 +; SSE42-NEXT: LBB12_3: ## %else5 ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: jne LBB12_7 -; SSE42-NEXT: LBB12_8: ## %else8 +; SSE42-NEXT: jne LBB12_20 +; SSE42-NEXT: LBB12_4: ## %else8 ; SSE42-NEXT: testb $16, %al -; SSE42-NEXT: jne LBB12_9 -; SSE42-NEXT: LBB12_10: ## %else11 +; SSE42-NEXT: jne LBB12_21 +; SSE42-NEXT: LBB12_5: ## %else11 ; SSE42-NEXT: testb $32, %al -; SSE42-NEXT: jne LBB12_11 -; SSE42-NEXT: LBB12_12: ## %else14 +; SSE42-NEXT: jne LBB12_22 +; SSE42-NEXT: LBB12_6: ## %else14 ; SSE42-NEXT: testb $64, %al -; SSE42-NEXT: jne LBB12_13 -; SSE42-NEXT: LBB12_14: ## %else17 +; SSE42-NEXT: jne LBB12_23 +; SSE42-NEXT: LBB12_7: ## %else17 ; SSE42-NEXT: testb %al, %al -; SSE42-NEXT: js LBB12_15 -; SSE42-NEXT: LBB12_16: ## %else20 +; SSE42-NEXT: js LBB12_24 +; SSE42-NEXT: LBB12_8: ## %else20 ; SSE42-NEXT: testl $256, %eax ## imm = 0x100 -; SSE42-NEXT: jne LBB12_17 -; SSE42-NEXT: LBB12_18: ## %else23 +; SSE42-NEXT: jne LBB12_25 +; SSE42-NEXT: LBB12_9: ## %else23 ; SSE42-NEXT: testl $512, %eax ## imm = 0x200 -; SSE42-NEXT: jne LBB12_19 -; SSE42-NEXT: LBB12_20: ## %else26 +; SSE42-NEXT: jne LBB12_26 +; SSE42-NEXT: LBB12_10: ## %else26 ; SSE42-NEXT: testl $1024, %eax ## imm = 0x400 -; SSE42-NEXT: jne LBB12_21 -; SSE42-NEXT: LBB12_22: ## %else29 +; SSE42-NEXT: jne LBB12_27 +; SSE42-NEXT: LBB12_11: ## %else29 ; SSE42-NEXT: testl $2048, %eax ## imm = 0x800 -; SSE42-NEXT: jne LBB12_23 -; SSE42-NEXT: LBB12_24: ## %else32 +; SSE42-NEXT: jne LBB12_28 +; SSE42-NEXT: LBB12_12: ## %else32 ; SSE42-NEXT: testl $4096, %eax ## imm = 0x1000 -; SSE42-NEXT: jne LBB12_25 -; SSE42-NEXT: LBB12_26: ## %else35 +; SSE42-NEXT: jne LBB12_29 +; SSE42-NEXT: LBB12_13: ## %else35 ; SSE42-NEXT: testl $8192, %eax ## imm = 0x2000 -; SSE42-NEXT: jne LBB12_27 -; SSE42-NEXT: LBB12_28: ## %else38 +; SSE42-NEXT: jne LBB12_30 +; SSE42-NEXT: LBB12_14: ## %else38 ; SSE42-NEXT: testl $16384, %eax ## imm = 0x4000 -; SSE42-NEXT: jne LBB12_29 -; SSE42-NEXT: LBB12_30: ## %else41 -; SSE42-NEXT: testl $32768, %eax ## imm = 0x8000 ; SSE42-NEXT: jne LBB12_31 -; SSE42-NEXT: LBB12_32: ## %else44 +; SSE42-NEXT: LBB12_15: ## %else41 +; SSE42-NEXT: testl $32768, %eax ## imm = 0x8000 +; SSE42-NEXT: jne LBB12_32 +; SSE42-NEXT: LBB12_16: ## %else44 ; SSE42-NEXT: retq -; SSE42-NEXT: LBB12_1: ## %cond.store +; SSE42-NEXT: LBB12_17: ## %cond.store ; SSE42-NEXT: pextrb $0, %xmm0, (%rdi) ; SSE42-NEXT: incq %rdi ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: je LBB12_4 -; SSE42-NEXT: LBB12_3: ## %cond.store1 +; SSE42-NEXT: je LBB12_2 +; SSE42-NEXT: LBB12_18: ## %cond.store1 ; SSE42-NEXT: pextrb $1, %xmm0, (%rdi) ; SSE42-NEXT: incq %rdi ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: je LBB12_6 -; SSE42-NEXT: LBB12_5: ## %cond.store4 +; SSE42-NEXT: je LBB12_3 +; SSE42-NEXT: LBB12_19: ## %cond.store4 ; SSE42-NEXT: pextrb $2, %xmm0, (%rdi) ; SSE42-NEXT: incq %rdi ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: je LBB12_8 -; SSE42-NEXT: LBB12_7: ## %cond.store7 +; SSE42-NEXT: je LBB12_4 +; SSE42-NEXT: LBB12_20: ## %cond.store7 ; SSE42-NEXT: pextrb $3, %xmm0, (%rdi) ; SSE42-NEXT: incq %rdi ; SSE42-NEXT: testb $16, %al -; SSE42-NEXT: je LBB12_10 -; SSE42-NEXT: LBB12_9: ## %cond.store10 +; SSE42-NEXT: je LBB12_5 +; SSE42-NEXT: LBB12_21: ## %cond.store10 ; SSE42-NEXT: pextrb $4, %xmm0, (%rdi) ; SSE42-NEXT: incq %rdi ; SSE42-NEXT: testb $32, %al -; SSE42-NEXT: je LBB12_12 -; SSE42-NEXT: LBB12_11: ## %cond.store13 +; SSE42-NEXT: je LBB12_6 +; SSE42-NEXT: LBB12_22: ## %cond.store13 ; SSE42-NEXT: pextrb $5, %xmm0, (%rdi) ; SSE42-NEXT: incq %rdi ; SSE42-NEXT: testb $64, %al -; SSE42-NEXT: je LBB12_14 -; SSE42-NEXT: LBB12_13: ## %cond.store16 +; SSE42-NEXT: je LBB12_7 +; SSE42-NEXT: LBB12_23: ## %cond.store16 ; SSE42-NEXT: pextrb $6, %xmm0, (%rdi) ; SSE42-NEXT: incq %rdi ; SSE42-NEXT: testb %al, %al -; SSE42-NEXT: jns LBB12_16 -; SSE42-NEXT: LBB12_15: ## %cond.store19 +; SSE42-NEXT: jns LBB12_8 +; SSE42-NEXT: LBB12_24: ## %cond.store19 ; SSE42-NEXT: pextrb $7, %xmm0, (%rdi) ; SSE42-NEXT: incq %rdi ; SSE42-NEXT: testl $256, %eax ## imm = 0x100 -; SSE42-NEXT: je LBB12_18 -; SSE42-NEXT: LBB12_17: ## %cond.store22 +; SSE42-NEXT: je LBB12_9 +; SSE42-NEXT: LBB12_25: ## %cond.store22 ; SSE42-NEXT: pextrb $8, %xmm0, (%rdi) ; SSE42-NEXT: incq %rdi ; SSE42-NEXT: testl $512, %eax ## imm = 0x200 -; SSE42-NEXT: je LBB12_20 -; SSE42-NEXT: LBB12_19: ## %cond.store25 +; SSE42-NEXT: je LBB12_10 +; SSE42-NEXT: LBB12_26: ## %cond.store25 ; SSE42-NEXT: pextrb $9, %xmm0, (%rdi) ; SSE42-NEXT: incq %rdi ; SSE42-NEXT: testl $1024, %eax ## imm = 0x400 -; SSE42-NEXT: je LBB12_22 -; SSE42-NEXT: LBB12_21: ## %cond.store28 +; SSE42-NEXT: je LBB12_11 +; SSE42-NEXT: LBB12_27: ## %cond.store28 ; SSE42-NEXT: pextrb $10, %xmm0, (%rdi) ; SSE42-NEXT: incq %rdi ; SSE42-NEXT: testl $2048, %eax ## imm = 0x800 -; SSE42-NEXT: je LBB12_24 -; SSE42-NEXT: LBB12_23: ## %cond.store31 +; SSE42-NEXT: je LBB12_12 +; SSE42-NEXT: LBB12_28: ## %cond.store31 ; SSE42-NEXT: pextrb $11, %xmm0, (%rdi) ; SSE42-NEXT: incq %rdi ; SSE42-NEXT: testl $4096, %eax ## imm = 0x1000 -; SSE42-NEXT: je LBB12_26 -; SSE42-NEXT: LBB12_25: ## %cond.store34 +; SSE42-NEXT: je LBB12_13 +; SSE42-NEXT: LBB12_29: ## %cond.store34 ; SSE42-NEXT: pextrb $12, %xmm0, (%rdi) ; SSE42-NEXT: incq %rdi ; SSE42-NEXT: testl $8192, %eax ## imm = 0x2000 -; SSE42-NEXT: je LBB12_28 -; SSE42-NEXT: LBB12_27: ## %cond.store37 +; SSE42-NEXT: je LBB12_14 +; SSE42-NEXT: LBB12_30: ## %cond.store37 ; SSE42-NEXT: pextrb $13, %xmm0, (%rdi) ; SSE42-NEXT: incq %rdi ; SSE42-NEXT: testl $16384, %eax ## imm = 0x4000 -; SSE42-NEXT: je LBB12_30 -; SSE42-NEXT: LBB12_29: ## %cond.store40 +; SSE42-NEXT: je LBB12_15 +; SSE42-NEXT: LBB12_31: ## %cond.store40 ; SSE42-NEXT: pextrb $14, %xmm0, (%rdi) ; SSE42-NEXT: incq %rdi ; SSE42-NEXT: testl $32768, %eax ## imm = 0x8000 -; SSE42-NEXT: je LBB12_32 -; SSE42-NEXT: LBB12_31: ## %cond.store43 +; SSE42-NEXT: je LBB12_16 +; SSE42-NEXT: LBB12_32: ## %cond.store43 ; SSE42-NEXT: pextrb $15, %xmm0, (%rdi) ; SSE42-NEXT: retq ; @@ -3849,130 +3849,130 @@ define void @compressstore_v16i8_v16i8(ptr %base, <16 x i8> %V, <16 x i8> %trigg ; AVX1OR2-NEXT: vpcmpeqb %xmm2, %xmm1, %xmm1 ; AVX1OR2-NEXT: vpmovmskb %xmm1, %eax ; AVX1OR2-NEXT: testb $1, %al -; AVX1OR2-NEXT: jne LBB12_1 -; AVX1OR2-NEXT: ## %bb.2: ## %else +; AVX1OR2-NEXT: jne LBB12_17 +; AVX1OR2-NEXT: ## %bb.1: ## %else ; AVX1OR2-NEXT: testb $2, %al -; AVX1OR2-NEXT: jne LBB12_3 -; AVX1OR2-NEXT: LBB12_4: ## %else2 +; AVX1OR2-NEXT: jne LBB12_18 +; AVX1OR2-NEXT: LBB12_2: ## %else2 ; AVX1OR2-NEXT: testb $4, %al -; AVX1OR2-NEXT: jne LBB12_5 -; AVX1OR2-NEXT: LBB12_6: ## %else5 +; AVX1OR2-NEXT: jne LBB12_19 +; AVX1OR2-NEXT: LBB12_3: ## %else5 ; AVX1OR2-NEXT: testb $8, %al -; AVX1OR2-NEXT: jne LBB12_7 -; AVX1OR2-NEXT: LBB12_8: ## %else8 +; AVX1OR2-NEXT: jne LBB12_20 +; AVX1OR2-NEXT: LBB12_4: ## %else8 ; AVX1OR2-NEXT: testb $16, %al -; AVX1OR2-NEXT: jne LBB12_9 -; AVX1OR2-NEXT: LBB12_10: ## %else11 +; AVX1OR2-NEXT: jne LBB12_21 +; AVX1OR2-NEXT: LBB12_5: ## %else11 ; AVX1OR2-NEXT: testb $32, %al -; AVX1OR2-NEXT: jne LBB12_11 -; AVX1OR2-NEXT: LBB12_12: ## %else14 +; AVX1OR2-NEXT: jne LBB12_22 +; AVX1OR2-NEXT: LBB12_6: ## %else14 ; AVX1OR2-NEXT: testb $64, %al -; AVX1OR2-NEXT: jne LBB12_13 -; AVX1OR2-NEXT: LBB12_14: ## %else17 +; AVX1OR2-NEXT: jne LBB12_23 +; AVX1OR2-NEXT: LBB12_7: ## %else17 ; AVX1OR2-NEXT: testb %al, %al -; AVX1OR2-NEXT: js LBB12_15 -; AVX1OR2-NEXT: LBB12_16: ## %else20 +; AVX1OR2-NEXT: js LBB12_24 +; AVX1OR2-NEXT: LBB12_8: ## %else20 ; AVX1OR2-NEXT: testl $256, %eax ## imm = 0x100 -; AVX1OR2-NEXT: jne LBB12_17 -; AVX1OR2-NEXT: LBB12_18: ## %else23 +; AVX1OR2-NEXT: jne LBB12_25 +; AVX1OR2-NEXT: LBB12_9: ## %else23 ; AVX1OR2-NEXT: testl $512, %eax ## imm = 0x200 -; AVX1OR2-NEXT: jne LBB12_19 -; AVX1OR2-NEXT: LBB12_20: ## %else26 +; AVX1OR2-NEXT: jne LBB12_26 +; AVX1OR2-NEXT: LBB12_10: ## %else26 ; AVX1OR2-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX1OR2-NEXT: jne LBB12_21 -; AVX1OR2-NEXT: LBB12_22: ## %else29 +; AVX1OR2-NEXT: jne LBB12_27 +; AVX1OR2-NEXT: LBB12_11: ## %else29 ; AVX1OR2-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX1OR2-NEXT: jne LBB12_23 -; AVX1OR2-NEXT: LBB12_24: ## %else32 +; AVX1OR2-NEXT: jne LBB12_28 +; AVX1OR2-NEXT: LBB12_12: ## %else32 ; AVX1OR2-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX1OR2-NEXT: jne LBB12_25 -; AVX1OR2-NEXT: LBB12_26: ## %else35 +; AVX1OR2-NEXT: jne LBB12_29 +; AVX1OR2-NEXT: LBB12_13: ## %else35 ; AVX1OR2-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX1OR2-NEXT: jne LBB12_27 -; AVX1OR2-NEXT: LBB12_28: ## %else38 +; AVX1OR2-NEXT: jne LBB12_30 +; AVX1OR2-NEXT: LBB12_14: ## %else38 ; AVX1OR2-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX1OR2-NEXT: jne LBB12_29 -; AVX1OR2-NEXT: LBB12_30: ## %else41 -; AVX1OR2-NEXT: testl $32768, %eax ## imm = 0x8000 ; AVX1OR2-NEXT: jne LBB12_31 -; AVX1OR2-NEXT: LBB12_32: ## %else44 +; AVX1OR2-NEXT: LBB12_15: ## %else41 +; AVX1OR2-NEXT: testl $32768, %eax ## imm = 0x8000 +; AVX1OR2-NEXT: jne LBB12_32 +; AVX1OR2-NEXT: LBB12_16: ## %else44 ; AVX1OR2-NEXT: retq -; AVX1OR2-NEXT: LBB12_1: ## %cond.store +; AVX1OR2-NEXT: LBB12_17: ## %cond.store ; AVX1OR2-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX1OR2-NEXT: incq %rdi ; AVX1OR2-NEXT: testb $2, %al -; AVX1OR2-NEXT: je LBB12_4 -; AVX1OR2-NEXT: LBB12_3: ## %cond.store1 +; AVX1OR2-NEXT: je LBB12_2 +; AVX1OR2-NEXT: LBB12_18: ## %cond.store1 ; AVX1OR2-NEXT: vpextrb $1, %xmm0, (%rdi) ; AVX1OR2-NEXT: incq %rdi ; AVX1OR2-NEXT: testb $4, %al -; AVX1OR2-NEXT: je LBB12_6 -; AVX1OR2-NEXT: LBB12_5: ## %cond.store4 +; AVX1OR2-NEXT: je LBB12_3 +; AVX1OR2-NEXT: LBB12_19: ## %cond.store4 ; AVX1OR2-NEXT: vpextrb $2, %xmm0, (%rdi) ; AVX1OR2-NEXT: incq %rdi ; AVX1OR2-NEXT: testb $8, %al -; AVX1OR2-NEXT: je LBB12_8 -; AVX1OR2-NEXT: LBB12_7: ## %cond.store7 +; AVX1OR2-NEXT: je LBB12_4 +; AVX1OR2-NEXT: LBB12_20: ## %cond.store7 ; AVX1OR2-NEXT: vpextrb $3, %xmm0, (%rdi) ; AVX1OR2-NEXT: incq %rdi ; AVX1OR2-NEXT: testb $16, %al -; AVX1OR2-NEXT: je LBB12_10 -; AVX1OR2-NEXT: LBB12_9: ## %cond.store10 +; AVX1OR2-NEXT: je LBB12_5 +; AVX1OR2-NEXT: LBB12_21: ## %cond.store10 ; AVX1OR2-NEXT: vpextrb $4, %xmm0, (%rdi) ; AVX1OR2-NEXT: incq %rdi ; AVX1OR2-NEXT: testb $32, %al -; AVX1OR2-NEXT: je LBB12_12 -; AVX1OR2-NEXT: LBB12_11: ## %cond.store13 +; AVX1OR2-NEXT: je LBB12_6 +; AVX1OR2-NEXT: LBB12_22: ## %cond.store13 ; AVX1OR2-NEXT: vpextrb $5, %xmm0, (%rdi) ; AVX1OR2-NEXT: incq %rdi ; AVX1OR2-NEXT: testb $64, %al -; AVX1OR2-NEXT: je LBB12_14 -; AVX1OR2-NEXT: LBB12_13: ## %cond.store16 +; AVX1OR2-NEXT: je LBB12_7 +; AVX1OR2-NEXT: LBB12_23: ## %cond.store16 ; AVX1OR2-NEXT: vpextrb $6, %xmm0, (%rdi) ; AVX1OR2-NEXT: incq %rdi ; AVX1OR2-NEXT: testb %al, %al -; AVX1OR2-NEXT: jns LBB12_16 -; AVX1OR2-NEXT: LBB12_15: ## %cond.store19 +; AVX1OR2-NEXT: jns LBB12_8 +; AVX1OR2-NEXT: LBB12_24: ## %cond.store19 ; AVX1OR2-NEXT: vpextrb $7, %xmm0, (%rdi) ; AVX1OR2-NEXT: incq %rdi ; AVX1OR2-NEXT: testl $256, %eax ## imm = 0x100 -; AVX1OR2-NEXT: je LBB12_18 -; AVX1OR2-NEXT: LBB12_17: ## %cond.store22 +; AVX1OR2-NEXT: je LBB12_9 +; AVX1OR2-NEXT: LBB12_25: ## %cond.store22 ; AVX1OR2-NEXT: vpextrb $8, %xmm0, (%rdi) ; AVX1OR2-NEXT: incq %rdi ; AVX1OR2-NEXT: testl $512, %eax ## imm = 0x200 -; AVX1OR2-NEXT: je LBB12_20 -; AVX1OR2-NEXT: LBB12_19: ## %cond.store25 +; AVX1OR2-NEXT: je LBB12_10 +; AVX1OR2-NEXT: LBB12_26: ## %cond.store25 ; AVX1OR2-NEXT: vpextrb $9, %xmm0, (%rdi) ; AVX1OR2-NEXT: incq %rdi ; AVX1OR2-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX1OR2-NEXT: je LBB12_22 -; AVX1OR2-NEXT: LBB12_21: ## %cond.store28 +; AVX1OR2-NEXT: je LBB12_11 +; AVX1OR2-NEXT: LBB12_27: ## %cond.store28 ; AVX1OR2-NEXT: vpextrb $10, %xmm0, (%rdi) ; AVX1OR2-NEXT: incq %rdi ; AVX1OR2-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX1OR2-NEXT: je LBB12_24 -; AVX1OR2-NEXT: LBB12_23: ## %cond.store31 +; AVX1OR2-NEXT: je LBB12_12 +; AVX1OR2-NEXT: LBB12_28: ## %cond.store31 ; AVX1OR2-NEXT: vpextrb $11, %xmm0, (%rdi) ; AVX1OR2-NEXT: incq %rdi ; AVX1OR2-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX1OR2-NEXT: je LBB12_26 -; AVX1OR2-NEXT: LBB12_25: ## %cond.store34 +; AVX1OR2-NEXT: je LBB12_13 +; AVX1OR2-NEXT: LBB12_29: ## %cond.store34 ; AVX1OR2-NEXT: vpextrb $12, %xmm0, (%rdi) ; AVX1OR2-NEXT: incq %rdi ; AVX1OR2-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX1OR2-NEXT: je LBB12_28 -; AVX1OR2-NEXT: LBB12_27: ## %cond.store37 +; AVX1OR2-NEXT: je LBB12_14 +; AVX1OR2-NEXT: LBB12_30: ## %cond.store37 ; AVX1OR2-NEXT: vpextrb $13, %xmm0, (%rdi) ; AVX1OR2-NEXT: incq %rdi ; AVX1OR2-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX1OR2-NEXT: je LBB12_30 -; AVX1OR2-NEXT: LBB12_29: ## %cond.store40 +; AVX1OR2-NEXT: je LBB12_15 +; AVX1OR2-NEXT: LBB12_31: ## %cond.store40 ; AVX1OR2-NEXT: vpextrb $14, %xmm0, (%rdi) ; AVX1OR2-NEXT: incq %rdi ; AVX1OR2-NEXT: testl $32768, %eax ## imm = 0x8000 -; AVX1OR2-NEXT: je LBB12_32 -; AVX1OR2-NEXT: LBB12_31: ## %cond.store43 +; AVX1OR2-NEXT: je LBB12_16 +; AVX1OR2-NEXT: LBB12_32: ## %cond.store43 ; AVX1OR2-NEXT: vpextrb $15, %xmm0, (%rdi) ; AVX1OR2-NEXT: retq ; @@ -3982,130 +3982,130 @@ define void @compressstore_v16i8_v16i8(ptr %base, <16 x i8> %V, <16 x i8> %trigg ; AVX512F-NEXT: vpcmpeqb %xmm2, %xmm1, %xmm1 ; AVX512F-NEXT: vpmovmskb %xmm1, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne LBB12_1 -; AVX512F-NEXT: ## %bb.2: ## %else +; AVX512F-NEXT: jne LBB12_17 +; AVX512F-NEXT: ## %bb.1: ## %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne LBB12_3 -; AVX512F-NEXT: LBB12_4: ## %else2 +; AVX512F-NEXT: jne LBB12_18 +; AVX512F-NEXT: LBB12_2: ## %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne LBB12_5 -; AVX512F-NEXT: LBB12_6: ## %else5 +; AVX512F-NEXT: jne LBB12_19 +; AVX512F-NEXT: LBB12_3: ## %else5 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne LBB12_7 -; AVX512F-NEXT: LBB12_8: ## %else8 +; AVX512F-NEXT: jne LBB12_20 +; AVX512F-NEXT: LBB12_4: ## %else8 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne LBB12_9 -; AVX512F-NEXT: LBB12_10: ## %else11 +; AVX512F-NEXT: jne LBB12_21 +; AVX512F-NEXT: LBB12_5: ## %else11 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne LBB12_11 -; AVX512F-NEXT: LBB12_12: ## %else14 +; AVX512F-NEXT: jne LBB12_22 +; AVX512F-NEXT: LBB12_6: ## %else14 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne LBB12_13 -; AVX512F-NEXT: LBB12_14: ## %else17 +; AVX512F-NEXT: jne LBB12_23 +; AVX512F-NEXT: LBB12_7: ## %else17 ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: js LBB12_15 -; AVX512F-NEXT: LBB12_16: ## %else20 +; AVX512F-NEXT: js LBB12_24 +; AVX512F-NEXT: LBB12_8: ## %else20 ; AVX512F-NEXT: testl $256, %eax ## imm = 0x100 -; AVX512F-NEXT: jne LBB12_17 -; AVX512F-NEXT: LBB12_18: ## %else23 +; AVX512F-NEXT: jne LBB12_25 +; AVX512F-NEXT: LBB12_9: ## %else23 ; AVX512F-NEXT: testl $512, %eax ## imm = 0x200 -; AVX512F-NEXT: jne LBB12_19 -; AVX512F-NEXT: LBB12_20: ## %else26 +; AVX512F-NEXT: jne LBB12_26 +; AVX512F-NEXT: LBB12_10: ## %else26 ; AVX512F-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX512F-NEXT: jne LBB12_21 -; AVX512F-NEXT: LBB12_22: ## %else29 +; AVX512F-NEXT: jne LBB12_27 +; AVX512F-NEXT: LBB12_11: ## %else29 ; AVX512F-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX512F-NEXT: jne LBB12_23 -; AVX512F-NEXT: LBB12_24: ## %else32 +; AVX512F-NEXT: jne LBB12_28 +; AVX512F-NEXT: LBB12_12: ## %else32 ; AVX512F-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX512F-NEXT: jne LBB12_25 -; AVX512F-NEXT: LBB12_26: ## %else35 +; AVX512F-NEXT: jne LBB12_29 +; AVX512F-NEXT: LBB12_13: ## %else35 ; AVX512F-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX512F-NEXT: jne LBB12_27 -; AVX512F-NEXT: LBB12_28: ## %else38 +; AVX512F-NEXT: jne LBB12_30 +; AVX512F-NEXT: LBB12_14: ## %else38 ; AVX512F-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX512F-NEXT: jne LBB12_29 -; AVX512F-NEXT: LBB12_30: ## %else41 -; AVX512F-NEXT: testl $32768, %eax ## imm = 0x8000 ; AVX512F-NEXT: jne LBB12_31 -; AVX512F-NEXT: LBB12_32: ## %else44 +; AVX512F-NEXT: LBB12_15: ## %else41 +; AVX512F-NEXT: testl $32768, %eax ## imm = 0x8000 +; AVX512F-NEXT: jne LBB12_32 +; AVX512F-NEXT: LBB12_16: ## %else44 ; AVX512F-NEXT: retq -; AVX512F-NEXT: LBB12_1: ## %cond.store +; AVX512F-NEXT: LBB12_17: ## %cond.store ; AVX512F-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512F-NEXT: incq %rdi ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je LBB12_4 -; AVX512F-NEXT: LBB12_3: ## %cond.store1 +; AVX512F-NEXT: je LBB12_2 +; AVX512F-NEXT: LBB12_18: ## %cond.store1 ; AVX512F-NEXT: vpextrb $1, %xmm0, (%rdi) ; AVX512F-NEXT: incq %rdi ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je LBB12_6 -; AVX512F-NEXT: LBB12_5: ## %cond.store4 +; AVX512F-NEXT: je LBB12_3 +; AVX512F-NEXT: LBB12_19: ## %cond.store4 ; AVX512F-NEXT: vpextrb $2, %xmm0, (%rdi) ; AVX512F-NEXT: incq %rdi ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je LBB12_8 -; AVX512F-NEXT: LBB12_7: ## %cond.store7 +; AVX512F-NEXT: je LBB12_4 +; AVX512F-NEXT: LBB12_20: ## %cond.store7 ; AVX512F-NEXT: vpextrb $3, %xmm0, (%rdi) ; AVX512F-NEXT: incq %rdi ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je LBB12_10 -; AVX512F-NEXT: LBB12_9: ## %cond.store10 +; AVX512F-NEXT: je LBB12_5 +; AVX512F-NEXT: LBB12_21: ## %cond.store10 ; AVX512F-NEXT: vpextrb $4, %xmm0, (%rdi) ; AVX512F-NEXT: incq %rdi ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je LBB12_12 -; AVX512F-NEXT: LBB12_11: ## %cond.store13 +; AVX512F-NEXT: je LBB12_6 +; AVX512F-NEXT: LBB12_22: ## %cond.store13 ; AVX512F-NEXT: vpextrb $5, %xmm0, (%rdi) ; AVX512F-NEXT: incq %rdi ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je LBB12_14 -; AVX512F-NEXT: LBB12_13: ## %cond.store16 +; AVX512F-NEXT: je LBB12_7 +; AVX512F-NEXT: LBB12_23: ## %cond.store16 ; AVX512F-NEXT: vpextrb $6, %xmm0, (%rdi) ; AVX512F-NEXT: incq %rdi ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: jns LBB12_16 -; AVX512F-NEXT: LBB12_15: ## %cond.store19 +; AVX512F-NEXT: jns LBB12_8 +; AVX512F-NEXT: LBB12_24: ## %cond.store19 ; AVX512F-NEXT: vpextrb $7, %xmm0, (%rdi) ; AVX512F-NEXT: incq %rdi ; AVX512F-NEXT: testl $256, %eax ## imm = 0x100 -; AVX512F-NEXT: je LBB12_18 -; AVX512F-NEXT: LBB12_17: ## %cond.store22 +; AVX512F-NEXT: je LBB12_9 +; AVX512F-NEXT: LBB12_25: ## %cond.store22 ; AVX512F-NEXT: vpextrb $8, %xmm0, (%rdi) ; AVX512F-NEXT: incq %rdi ; AVX512F-NEXT: testl $512, %eax ## imm = 0x200 -; AVX512F-NEXT: je LBB12_20 -; AVX512F-NEXT: LBB12_19: ## %cond.store25 +; AVX512F-NEXT: je LBB12_10 +; AVX512F-NEXT: LBB12_26: ## %cond.store25 ; AVX512F-NEXT: vpextrb $9, %xmm0, (%rdi) ; AVX512F-NEXT: incq %rdi ; AVX512F-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX512F-NEXT: je LBB12_22 -; AVX512F-NEXT: LBB12_21: ## %cond.store28 +; AVX512F-NEXT: je LBB12_11 +; AVX512F-NEXT: LBB12_27: ## %cond.store28 ; AVX512F-NEXT: vpextrb $10, %xmm0, (%rdi) ; AVX512F-NEXT: incq %rdi ; AVX512F-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX512F-NEXT: je LBB12_24 -; AVX512F-NEXT: LBB12_23: ## %cond.store31 +; AVX512F-NEXT: je LBB12_12 +; AVX512F-NEXT: LBB12_28: ## %cond.store31 ; AVX512F-NEXT: vpextrb $11, %xmm0, (%rdi) ; AVX512F-NEXT: incq %rdi ; AVX512F-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX512F-NEXT: je LBB12_26 -; AVX512F-NEXT: LBB12_25: ## %cond.store34 +; AVX512F-NEXT: je LBB12_13 +; AVX512F-NEXT: LBB12_29: ## %cond.store34 ; AVX512F-NEXT: vpextrb $12, %xmm0, (%rdi) ; AVX512F-NEXT: incq %rdi ; AVX512F-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX512F-NEXT: je LBB12_28 -; AVX512F-NEXT: LBB12_27: ## %cond.store37 +; AVX512F-NEXT: je LBB12_14 +; AVX512F-NEXT: LBB12_30: ## %cond.store37 ; AVX512F-NEXT: vpextrb $13, %xmm0, (%rdi) ; AVX512F-NEXT: incq %rdi ; AVX512F-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX512F-NEXT: je LBB12_30 -; AVX512F-NEXT: LBB12_29: ## %cond.store40 +; AVX512F-NEXT: je LBB12_15 +; AVX512F-NEXT: LBB12_31: ## %cond.store40 ; AVX512F-NEXT: vpextrb $14, %xmm0, (%rdi) ; AVX512F-NEXT: incq %rdi ; AVX512F-NEXT: testl $32768, %eax ## imm = 0x8000 -; AVX512F-NEXT: je LBB12_32 -; AVX512F-NEXT: LBB12_31: ## %cond.store43 +; AVX512F-NEXT: je LBB12_16 +; AVX512F-NEXT: LBB12_32: ## %cond.store43 ; AVX512F-NEXT: vpextrb $15, %xmm0, (%rdi) ; AVX512F-NEXT: retq ; @@ -4115,130 +4115,130 @@ define void @compressstore_v16i8_v16i8(ptr %base, <16 x i8> %V, <16 x i8> %trigg ; AVX512VLDQ-NEXT: vpcmpeqb %xmm2, %xmm1, %xmm1 ; AVX512VLDQ-NEXT: vpmovmskb %xmm1, %eax ; AVX512VLDQ-NEXT: testb $1, %al -; AVX512VLDQ-NEXT: jne LBB12_1 -; AVX512VLDQ-NEXT: ## %bb.2: ## %else +; AVX512VLDQ-NEXT: jne LBB12_17 +; AVX512VLDQ-NEXT: ## %bb.1: ## %else ; AVX512VLDQ-NEXT: testb $2, %al -; AVX512VLDQ-NEXT: jne LBB12_3 -; AVX512VLDQ-NEXT: LBB12_4: ## %else2 +; AVX512VLDQ-NEXT: jne LBB12_18 +; AVX512VLDQ-NEXT: LBB12_2: ## %else2 ; AVX512VLDQ-NEXT: testb $4, %al -; AVX512VLDQ-NEXT: jne LBB12_5 -; AVX512VLDQ-NEXT: LBB12_6: ## %else5 +; AVX512VLDQ-NEXT: jne LBB12_19 +; AVX512VLDQ-NEXT: LBB12_3: ## %else5 ; AVX512VLDQ-NEXT: testb $8, %al -; AVX512VLDQ-NEXT: jne LBB12_7 -; AVX512VLDQ-NEXT: LBB12_8: ## %else8 +; AVX512VLDQ-NEXT: jne LBB12_20 +; AVX512VLDQ-NEXT: LBB12_4: ## %else8 ; AVX512VLDQ-NEXT: testb $16, %al -; AVX512VLDQ-NEXT: jne LBB12_9 -; AVX512VLDQ-NEXT: LBB12_10: ## %else11 +; AVX512VLDQ-NEXT: jne LBB12_21 +; AVX512VLDQ-NEXT: LBB12_5: ## %else11 ; AVX512VLDQ-NEXT: testb $32, %al -; AVX512VLDQ-NEXT: jne LBB12_11 -; AVX512VLDQ-NEXT: LBB12_12: ## %else14 +; AVX512VLDQ-NEXT: jne LBB12_22 +; AVX512VLDQ-NEXT: LBB12_6: ## %else14 ; AVX512VLDQ-NEXT: testb $64, %al -; AVX512VLDQ-NEXT: jne LBB12_13 -; AVX512VLDQ-NEXT: LBB12_14: ## %else17 +; AVX512VLDQ-NEXT: jne LBB12_23 +; AVX512VLDQ-NEXT: LBB12_7: ## %else17 ; AVX512VLDQ-NEXT: testb %al, %al -; AVX512VLDQ-NEXT: js LBB12_15 -; AVX512VLDQ-NEXT: LBB12_16: ## %else20 +; AVX512VLDQ-NEXT: js LBB12_24 +; AVX512VLDQ-NEXT: LBB12_8: ## %else20 ; AVX512VLDQ-NEXT: testl $256, %eax ## imm = 0x100 -; AVX512VLDQ-NEXT: jne LBB12_17 -; AVX512VLDQ-NEXT: LBB12_18: ## %else23 +; AVX512VLDQ-NEXT: jne LBB12_25 +; AVX512VLDQ-NEXT: LBB12_9: ## %else23 ; AVX512VLDQ-NEXT: testl $512, %eax ## imm = 0x200 -; AVX512VLDQ-NEXT: jne LBB12_19 -; AVX512VLDQ-NEXT: LBB12_20: ## %else26 +; AVX512VLDQ-NEXT: jne LBB12_26 +; AVX512VLDQ-NEXT: LBB12_10: ## %else26 ; AVX512VLDQ-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX512VLDQ-NEXT: jne LBB12_21 -; AVX512VLDQ-NEXT: LBB12_22: ## %else29 +; AVX512VLDQ-NEXT: jne LBB12_27 +; AVX512VLDQ-NEXT: LBB12_11: ## %else29 ; AVX512VLDQ-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX512VLDQ-NEXT: jne LBB12_23 -; AVX512VLDQ-NEXT: LBB12_24: ## %else32 +; AVX512VLDQ-NEXT: jne LBB12_28 +; AVX512VLDQ-NEXT: LBB12_12: ## %else32 ; AVX512VLDQ-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX512VLDQ-NEXT: jne LBB12_25 -; AVX512VLDQ-NEXT: LBB12_26: ## %else35 +; AVX512VLDQ-NEXT: jne LBB12_29 +; AVX512VLDQ-NEXT: LBB12_13: ## %else35 ; AVX512VLDQ-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX512VLDQ-NEXT: jne LBB12_27 -; AVX512VLDQ-NEXT: LBB12_28: ## %else38 +; AVX512VLDQ-NEXT: jne LBB12_30 +; AVX512VLDQ-NEXT: LBB12_14: ## %else38 ; AVX512VLDQ-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX512VLDQ-NEXT: jne LBB12_29 -; AVX512VLDQ-NEXT: LBB12_30: ## %else41 -; AVX512VLDQ-NEXT: testl $32768, %eax ## imm = 0x8000 ; AVX512VLDQ-NEXT: jne LBB12_31 -; AVX512VLDQ-NEXT: LBB12_32: ## %else44 +; AVX512VLDQ-NEXT: LBB12_15: ## %else41 +; AVX512VLDQ-NEXT: testl $32768, %eax ## imm = 0x8000 +; AVX512VLDQ-NEXT: jne LBB12_32 +; AVX512VLDQ-NEXT: LBB12_16: ## %else44 ; AVX512VLDQ-NEXT: retq -; AVX512VLDQ-NEXT: LBB12_1: ## %cond.store +; AVX512VLDQ-NEXT: LBB12_17: ## %cond.store ; AVX512VLDQ-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512VLDQ-NEXT: incq %rdi ; AVX512VLDQ-NEXT: testb $2, %al -; AVX512VLDQ-NEXT: je LBB12_4 -; AVX512VLDQ-NEXT: LBB12_3: ## %cond.store1 +; AVX512VLDQ-NEXT: je LBB12_2 +; AVX512VLDQ-NEXT: LBB12_18: ## %cond.store1 ; AVX512VLDQ-NEXT: vpextrb $1, %xmm0, (%rdi) ; AVX512VLDQ-NEXT: incq %rdi ; AVX512VLDQ-NEXT: testb $4, %al -; AVX512VLDQ-NEXT: je LBB12_6 -; AVX512VLDQ-NEXT: LBB12_5: ## %cond.store4 +; AVX512VLDQ-NEXT: je LBB12_3 +; AVX512VLDQ-NEXT: LBB12_19: ## %cond.store4 ; AVX512VLDQ-NEXT: vpextrb $2, %xmm0, (%rdi) ; AVX512VLDQ-NEXT: incq %rdi ; AVX512VLDQ-NEXT: testb $8, %al -; AVX512VLDQ-NEXT: je LBB12_8 -; AVX512VLDQ-NEXT: LBB12_7: ## %cond.store7 +; AVX512VLDQ-NEXT: je LBB12_4 +; AVX512VLDQ-NEXT: LBB12_20: ## %cond.store7 ; AVX512VLDQ-NEXT: vpextrb $3, %xmm0, (%rdi) ; AVX512VLDQ-NEXT: incq %rdi ; AVX512VLDQ-NEXT: testb $16, %al -; AVX512VLDQ-NEXT: je LBB12_10 -; AVX512VLDQ-NEXT: LBB12_9: ## %cond.store10 +; AVX512VLDQ-NEXT: je LBB12_5 +; AVX512VLDQ-NEXT: LBB12_21: ## %cond.store10 ; AVX512VLDQ-NEXT: vpextrb $4, %xmm0, (%rdi) ; AVX512VLDQ-NEXT: incq %rdi ; AVX512VLDQ-NEXT: testb $32, %al -; AVX512VLDQ-NEXT: je LBB12_12 -; AVX512VLDQ-NEXT: LBB12_11: ## %cond.store13 +; AVX512VLDQ-NEXT: je LBB12_6 +; AVX512VLDQ-NEXT: LBB12_22: ## %cond.store13 ; AVX512VLDQ-NEXT: vpextrb $5, %xmm0, (%rdi) ; AVX512VLDQ-NEXT: incq %rdi ; AVX512VLDQ-NEXT: testb $64, %al -; AVX512VLDQ-NEXT: je LBB12_14 -; AVX512VLDQ-NEXT: LBB12_13: ## %cond.store16 +; AVX512VLDQ-NEXT: je LBB12_7 +; AVX512VLDQ-NEXT: LBB12_23: ## %cond.store16 ; AVX512VLDQ-NEXT: vpextrb $6, %xmm0, (%rdi) ; AVX512VLDQ-NEXT: incq %rdi ; AVX512VLDQ-NEXT: testb %al, %al -; AVX512VLDQ-NEXT: jns LBB12_16 -; AVX512VLDQ-NEXT: LBB12_15: ## %cond.store19 +; AVX512VLDQ-NEXT: jns LBB12_8 +; AVX512VLDQ-NEXT: LBB12_24: ## %cond.store19 ; AVX512VLDQ-NEXT: vpextrb $7, %xmm0, (%rdi) ; AVX512VLDQ-NEXT: incq %rdi ; AVX512VLDQ-NEXT: testl $256, %eax ## imm = 0x100 -; AVX512VLDQ-NEXT: je LBB12_18 -; AVX512VLDQ-NEXT: LBB12_17: ## %cond.store22 +; AVX512VLDQ-NEXT: je LBB12_9 +; AVX512VLDQ-NEXT: LBB12_25: ## %cond.store22 ; AVX512VLDQ-NEXT: vpextrb $8, %xmm0, (%rdi) ; AVX512VLDQ-NEXT: incq %rdi ; AVX512VLDQ-NEXT: testl $512, %eax ## imm = 0x200 -; AVX512VLDQ-NEXT: je LBB12_20 -; AVX512VLDQ-NEXT: LBB12_19: ## %cond.store25 +; AVX512VLDQ-NEXT: je LBB12_10 +; AVX512VLDQ-NEXT: LBB12_26: ## %cond.store25 ; AVX512VLDQ-NEXT: vpextrb $9, %xmm0, (%rdi) ; AVX512VLDQ-NEXT: incq %rdi ; AVX512VLDQ-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX512VLDQ-NEXT: je LBB12_22 -; AVX512VLDQ-NEXT: LBB12_21: ## %cond.store28 +; AVX512VLDQ-NEXT: je LBB12_11 +; AVX512VLDQ-NEXT: LBB12_27: ## %cond.store28 ; AVX512VLDQ-NEXT: vpextrb $10, %xmm0, (%rdi) ; AVX512VLDQ-NEXT: incq %rdi ; AVX512VLDQ-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX512VLDQ-NEXT: je LBB12_24 -; AVX512VLDQ-NEXT: LBB12_23: ## %cond.store31 +; AVX512VLDQ-NEXT: je LBB12_12 +; AVX512VLDQ-NEXT: LBB12_28: ## %cond.store31 ; AVX512VLDQ-NEXT: vpextrb $11, %xmm0, (%rdi) ; AVX512VLDQ-NEXT: incq %rdi ; AVX512VLDQ-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX512VLDQ-NEXT: je LBB12_26 -; AVX512VLDQ-NEXT: LBB12_25: ## %cond.store34 +; AVX512VLDQ-NEXT: je LBB12_13 +; AVX512VLDQ-NEXT: LBB12_29: ## %cond.store34 ; AVX512VLDQ-NEXT: vpextrb $12, %xmm0, (%rdi) ; AVX512VLDQ-NEXT: incq %rdi ; AVX512VLDQ-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX512VLDQ-NEXT: je LBB12_28 -; AVX512VLDQ-NEXT: LBB12_27: ## %cond.store37 +; AVX512VLDQ-NEXT: je LBB12_14 +; AVX512VLDQ-NEXT: LBB12_30: ## %cond.store37 ; AVX512VLDQ-NEXT: vpextrb $13, %xmm0, (%rdi) ; AVX512VLDQ-NEXT: incq %rdi ; AVX512VLDQ-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX512VLDQ-NEXT: je LBB12_30 -; AVX512VLDQ-NEXT: LBB12_29: ## %cond.store40 +; AVX512VLDQ-NEXT: je LBB12_15 +; AVX512VLDQ-NEXT: LBB12_31: ## %cond.store40 ; AVX512VLDQ-NEXT: vpextrb $14, %xmm0, (%rdi) ; AVX512VLDQ-NEXT: incq %rdi ; AVX512VLDQ-NEXT: testl $32768, %eax ## imm = 0x8000 -; AVX512VLDQ-NEXT: je LBB12_32 -; AVX512VLDQ-NEXT: LBB12_31: ## %cond.store43 +; AVX512VLDQ-NEXT: je LBB12_16 +; AVX512VLDQ-NEXT: LBB12_32: ## %cond.store43 ; AVX512VLDQ-NEXT: vpextrb $15, %xmm0, (%rdi) ; AVX512VLDQ-NEXT: retq ; @@ -4247,130 +4247,130 @@ define void @compressstore_v16i8_v16i8(ptr %base, <16 x i8> %V, <16 x i8> %trigg ; AVX512VLBW-NEXT: vptestnmb %xmm1, %xmm1, %k0 ; AVX512VLBW-NEXT: kmovd %k0, %eax ; AVX512VLBW-NEXT: testb $1, %al -; AVX512VLBW-NEXT: jne LBB12_1 -; AVX512VLBW-NEXT: ## %bb.2: ## %else +; AVX512VLBW-NEXT: jne LBB12_17 +; AVX512VLBW-NEXT: ## %bb.1: ## %else ; AVX512VLBW-NEXT: testb $2, %al -; AVX512VLBW-NEXT: jne LBB12_3 -; AVX512VLBW-NEXT: LBB12_4: ## %else2 +; AVX512VLBW-NEXT: jne LBB12_18 +; AVX512VLBW-NEXT: LBB12_2: ## %else2 ; AVX512VLBW-NEXT: testb $4, %al -; AVX512VLBW-NEXT: jne LBB12_5 -; AVX512VLBW-NEXT: LBB12_6: ## %else5 +; AVX512VLBW-NEXT: jne LBB12_19 +; AVX512VLBW-NEXT: LBB12_3: ## %else5 ; AVX512VLBW-NEXT: testb $8, %al -; AVX512VLBW-NEXT: jne LBB12_7 -; AVX512VLBW-NEXT: LBB12_8: ## %else8 +; AVX512VLBW-NEXT: jne LBB12_20 +; AVX512VLBW-NEXT: LBB12_4: ## %else8 ; AVX512VLBW-NEXT: testb $16, %al -; AVX512VLBW-NEXT: jne LBB12_9 -; AVX512VLBW-NEXT: LBB12_10: ## %else11 +; AVX512VLBW-NEXT: jne LBB12_21 +; AVX512VLBW-NEXT: LBB12_5: ## %else11 ; AVX512VLBW-NEXT: testb $32, %al -; AVX512VLBW-NEXT: jne LBB12_11 -; AVX512VLBW-NEXT: LBB12_12: ## %else14 +; AVX512VLBW-NEXT: jne LBB12_22 +; AVX512VLBW-NEXT: LBB12_6: ## %else14 ; AVX512VLBW-NEXT: testb $64, %al -; AVX512VLBW-NEXT: jne LBB12_13 -; AVX512VLBW-NEXT: LBB12_14: ## %else17 +; AVX512VLBW-NEXT: jne LBB12_23 +; AVX512VLBW-NEXT: LBB12_7: ## %else17 ; AVX512VLBW-NEXT: testb %al, %al -; AVX512VLBW-NEXT: js LBB12_15 -; AVX512VLBW-NEXT: LBB12_16: ## %else20 +; AVX512VLBW-NEXT: js LBB12_24 +; AVX512VLBW-NEXT: LBB12_8: ## %else20 ; AVX512VLBW-NEXT: testl $256, %eax ## imm = 0x100 -; AVX512VLBW-NEXT: jne LBB12_17 -; AVX512VLBW-NEXT: LBB12_18: ## %else23 +; AVX512VLBW-NEXT: jne LBB12_25 +; AVX512VLBW-NEXT: LBB12_9: ## %else23 ; AVX512VLBW-NEXT: testl $512, %eax ## imm = 0x200 -; AVX512VLBW-NEXT: jne LBB12_19 -; AVX512VLBW-NEXT: LBB12_20: ## %else26 +; AVX512VLBW-NEXT: jne LBB12_26 +; AVX512VLBW-NEXT: LBB12_10: ## %else26 ; AVX512VLBW-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX512VLBW-NEXT: jne LBB12_21 -; AVX512VLBW-NEXT: LBB12_22: ## %else29 +; AVX512VLBW-NEXT: jne LBB12_27 +; AVX512VLBW-NEXT: LBB12_11: ## %else29 ; AVX512VLBW-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX512VLBW-NEXT: jne LBB12_23 -; AVX512VLBW-NEXT: LBB12_24: ## %else32 +; AVX512VLBW-NEXT: jne LBB12_28 +; AVX512VLBW-NEXT: LBB12_12: ## %else32 ; AVX512VLBW-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX512VLBW-NEXT: jne LBB12_25 -; AVX512VLBW-NEXT: LBB12_26: ## %else35 +; AVX512VLBW-NEXT: jne LBB12_29 +; AVX512VLBW-NEXT: LBB12_13: ## %else35 ; AVX512VLBW-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX512VLBW-NEXT: jne LBB12_27 -; AVX512VLBW-NEXT: LBB12_28: ## %else38 +; AVX512VLBW-NEXT: jne LBB12_30 +; AVX512VLBW-NEXT: LBB12_14: ## %else38 ; AVX512VLBW-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX512VLBW-NEXT: jne LBB12_29 -; AVX512VLBW-NEXT: LBB12_30: ## %else41 -; AVX512VLBW-NEXT: testl $32768, %eax ## imm = 0x8000 ; AVX512VLBW-NEXT: jne LBB12_31 -; AVX512VLBW-NEXT: LBB12_32: ## %else44 +; AVX512VLBW-NEXT: LBB12_15: ## %else41 +; AVX512VLBW-NEXT: testl $32768, %eax ## imm = 0x8000 +; AVX512VLBW-NEXT: jne LBB12_32 +; AVX512VLBW-NEXT: LBB12_16: ## %else44 ; AVX512VLBW-NEXT: retq -; AVX512VLBW-NEXT: LBB12_1: ## %cond.store +; AVX512VLBW-NEXT: LBB12_17: ## %cond.store ; AVX512VLBW-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512VLBW-NEXT: incq %rdi ; AVX512VLBW-NEXT: testb $2, %al -; AVX512VLBW-NEXT: je LBB12_4 -; AVX512VLBW-NEXT: LBB12_3: ## %cond.store1 +; AVX512VLBW-NEXT: je LBB12_2 +; AVX512VLBW-NEXT: LBB12_18: ## %cond.store1 ; AVX512VLBW-NEXT: vpextrb $1, %xmm0, (%rdi) ; AVX512VLBW-NEXT: incq %rdi ; AVX512VLBW-NEXT: testb $4, %al -; AVX512VLBW-NEXT: je LBB12_6 -; AVX512VLBW-NEXT: LBB12_5: ## %cond.store4 +; AVX512VLBW-NEXT: je LBB12_3 +; AVX512VLBW-NEXT: LBB12_19: ## %cond.store4 ; AVX512VLBW-NEXT: vpextrb $2, %xmm0, (%rdi) ; AVX512VLBW-NEXT: incq %rdi ; AVX512VLBW-NEXT: testb $8, %al -; AVX512VLBW-NEXT: je LBB12_8 -; AVX512VLBW-NEXT: LBB12_7: ## %cond.store7 +; AVX512VLBW-NEXT: je LBB12_4 +; AVX512VLBW-NEXT: LBB12_20: ## %cond.store7 ; AVX512VLBW-NEXT: vpextrb $3, %xmm0, (%rdi) ; AVX512VLBW-NEXT: incq %rdi ; AVX512VLBW-NEXT: testb $16, %al -; AVX512VLBW-NEXT: je LBB12_10 -; AVX512VLBW-NEXT: LBB12_9: ## %cond.store10 +; AVX512VLBW-NEXT: je LBB12_5 +; AVX512VLBW-NEXT: LBB12_21: ## %cond.store10 ; AVX512VLBW-NEXT: vpextrb $4, %xmm0, (%rdi) ; AVX512VLBW-NEXT: incq %rdi ; AVX512VLBW-NEXT: testb $32, %al -; AVX512VLBW-NEXT: je LBB12_12 -; AVX512VLBW-NEXT: LBB12_11: ## %cond.store13 +; AVX512VLBW-NEXT: je LBB12_6 +; AVX512VLBW-NEXT: LBB12_22: ## %cond.store13 ; AVX512VLBW-NEXT: vpextrb $5, %xmm0, (%rdi) ; AVX512VLBW-NEXT: incq %rdi ; AVX512VLBW-NEXT: testb $64, %al -; AVX512VLBW-NEXT: je LBB12_14 -; AVX512VLBW-NEXT: LBB12_13: ## %cond.store16 +; AVX512VLBW-NEXT: je LBB12_7 +; AVX512VLBW-NEXT: LBB12_23: ## %cond.store16 ; AVX512VLBW-NEXT: vpextrb $6, %xmm0, (%rdi) ; AVX512VLBW-NEXT: incq %rdi ; AVX512VLBW-NEXT: testb %al, %al -; AVX512VLBW-NEXT: jns LBB12_16 -; AVX512VLBW-NEXT: LBB12_15: ## %cond.store19 +; AVX512VLBW-NEXT: jns LBB12_8 +; AVX512VLBW-NEXT: LBB12_24: ## %cond.store19 ; AVX512VLBW-NEXT: vpextrb $7, %xmm0, (%rdi) ; AVX512VLBW-NEXT: incq %rdi ; AVX512VLBW-NEXT: testl $256, %eax ## imm = 0x100 -; AVX512VLBW-NEXT: je LBB12_18 -; AVX512VLBW-NEXT: LBB12_17: ## %cond.store22 +; AVX512VLBW-NEXT: je LBB12_9 +; AVX512VLBW-NEXT: LBB12_25: ## %cond.store22 ; AVX512VLBW-NEXT: vpextrb $8, %xmm0, (%rdi) ; AVX512VLBW-NEXT: incq %rdi ; AVX512VLBW-NEXT: testl $512, %eax ## imm = 0x200 -; AVX512VLBW-NEXT: je LBB12_20 -; AVX512VLBW-NEXT: LBB12_19: ## %cond.store25 +; AVX512VLBW-NEXT: je LBB12_10 +; AVX512VLBW-NEXT: LBB12_26: ## %cond.store25 ; AVX512VLBW-NEXT: vpextrb $9, %xmm0, (%rdi) ; AVX512VLBW-NEXT: incq %rdi ; AVX512VLBW-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX512VLBW-NEXT: je LBB12_22 -; AVX512VLBW-NEXT: LBB12_21: ## %cond.store28 +; AVX512VLBW-NEXT: je LBB12_11 +; AVX512VLBW-NEXT: LBB12_27: ## %cond.store28 ; AVX512VLBW-NEXT: vpextrb $10, %xmm0, (%rdi) ; AVX512VLBW-NEXT: incq %rdi ; AVX512VLBW-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX512VLBW-NEXT: je LBB12_24 -; AVX512VLBW-NEXT: LBB12_23: ## %cond.store31 +; AVX512VLBW-NEXT: je LBB12_12 +; AVX512VLBW-NEXT: LBB12_28: ## %cond.store31 ; AVX512VLBW-NEXT: vpextrb $11, %xmm0, (%rdi) ; AVX512VLBW-NEXT: incq %rdi ; AVX512VLBW-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX512VLBW-NEXT: je LBB12_26 -; AVX512VLBW-NEXT: LBB12_25: ## %cond.store34 +; AVX512VLBW-NEXT: je LBB12_13 +; AVX512VLBW-NEXT: LBB12_29: ## %cond.store34 ; AVX512VLBW-NEXT: vpextrb $12, %xmm0, (%rdi) ; AVX512VLBW-NEXT: incq %rdi ; AVX512VLBW-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX512VLBW-NEXT: je LBB12_28 -; AVX512VLBW-NEXT: LBB12_27: ## %cond.store37 +; AVX512VLBW-NEXT: je LBB12_14 +; AVX512VLBW-NEXT: LBB12_30: ## %cond.store37 ; AVX512VLBW-NEXT: vpextrb $13, %xmm0, (%rdi) ; AVX512VLBW-NEXT: incq %rdi ; AVX512VLBW-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX512VLBW-NEXT: je LBB12_30 -; AVX512VLBW-NEXT: LBB12_29: ## %cond.store40 +; AVX512VLBW-NEXT: je LBB12_15 +; AVX512VLBW-NEXT: LBB12_31: ## %cond.store40 ; AVX512VLBW-NEXT: vpextrb $14, %xmm0, (%rdi) ; AVX512VLBW-NEXT: incq %rdi ; AVX512VLBW-NEXT: testl $32768, %eax ## imm = 0x8000 -; AVX512VLBW-NEXT: je LBB12_32 -; AVX512VLBW-NEXT: LBB12_31: ## %cond.store43 +; AVX512VLBW-NEXT: je LBB12_16 +; AVX512VLBW-NEXT: LBB12_32: ## %cond.store43 ; AVX512VLBW-NEXT: vpextrb $15, %xmm0, (%rdi) ; AVX512VLBW-NEXT: retq %mask = icmp eq <16 x i8> %trigger, zeroinitializer diff --git a/llvm/test/CodeGen/X86/masked_expandload.ll b/llvm/test/CodeGen/X86/masked_expandload.ll index ce8a34db498df..75c45503fe030 100644 --- a/llvm/test/CodeGen/X86/masked_expandload.ll +++ b/llvm/test/CodeGen/X86/masked_expandload.ll @@ -20,18 +20,18 @@ define <2 x double> @expandload_v2f64_v2i64(ptr %base, <2 x double> %src0, <2 x ; SSE2-NEXT: pand %xmm2, %xmm1 ; SSE2-NEXT: movmskpd %xmm1, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB0_1 -; SSE2-NEXT: ## %bb.2: ## %else -; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: jne LBB0_3 -; SSE2-NEXT: LBB0_4: ## %else2 +; SSE2-NEXT: ## %bb.1: ## %else +; SSE2-NEXT: testb $2, %al +; SSE2-NEXT: jne LBB0_4 +; SSE2-NEXT: LBB0_2: ## %else2 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB0_1: ## %cond.load +; SSE2-NEXT: LBB0_3: ## %cond.load ; SSE2-NEXT: movlps (%rdi), %xmm0 ## xmm0 = mem[0,1],xmm0[2,3] ; SSE2-NEXT: addq $8, %rdi ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB0_4 -; SSE2-NEXT: LBB0_3: ## %cond.load1 +; SSE2-NEXT: je LBB0_2 +; SSE2-NEXT: LBB0_4: ## %cond.load1 ; SSE2-NEXT: movhps (%rdi), %xmm0 ## xmm0 = xmm0[0,1],mem[0,1] ; SSE2-NEXT: retq ; @@ -41,18 +41,18 @@ define <2 x double> @expandload_v2f64_v2i64(ptr %base, <2 x double> %src0, <2 x ; SSE42-NEXT: pcmpeqq %xmm1, %xmm2 ; SSE42-NEXT: movmskpd %xmm2, %eax ; SSE42-NEXT: testb $1, %al -; SSE42-NEXT: jne LBB0_1 -; SSE42-NEXT: ## %bb.2: ## %else -; SSE42-NEXT: testb $2, %al ; SSE42-NEXT: jne LBB0_3 -; SSE42-NEXT: LBB0_4: ## %else2 +; SSE42-NEXT: ## %bb.1: ## %else +; SSE42-NEXT: testb $2, %al +; SSE42-NEXT: jne LBB0_4 +; SSE42-NEXT: LBB0_2: ## %else2 ; SSE42-NEXT: retq -; SSE42-NEXT: LBB0_1: ## %cond.load +; SSE42-NEXT: LBB0_3: ## %cond.load ; SSE42-NEXT: movlps (%rdi), %xmm0 ## xmm0 = mem[0,1],xmm0[2,3] ; SSE42-NEXT: addq $8, %rdi ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: je LBB0_4 -; SSE42-NEXT: LBB0_3: ## %cond.load1 +; SSE42-NEXT: je LBB0_2 +; SSE42-NEXT: LBB0_4: ## %cond.load1 ; SSE42-NEXT: movhps (%rdi), %xmm0 ## xmm0 = xmm0[0,1],mem[0,1] ; SSE42-NEXT: retq ; @@ -62,18 +62,18 @@ define <2 x double> @expandload_v2f64_v2i64(ptr %base, <2 x double> %src0, <2 x ; AVX1OR2-NEXT: vpcmpeqq %xmm2, %xmm1, %xmm1 ; AVX1OR2-NEXT: vmovmskpd %xmm1, %eax ; AVX1OR2-NEXT: testb $1, %al -; AVX1OR2-NEXT: jne LBB0_1 -; AVX1OR2-NEXT: ## %bb.2: ## %else -; AVX1OR2-NEXT: testb $2, %al ; AVX1OR2-NEXT: jne LBB0_3 -; AVX1OR2-NEXT: LBB0_4: ## %else2 +; AVX1OR2-NEXT: ## %bb.1: ## %else +; AVX1OR2-NEXT: testb $2, %al +; AVX1OR2-NEXT: jne LBB0_4 +; AVX1OR2-NEXT: LBB0_2: ## %else2 ; AVX1OR2-NEXT: retq -; AVX1OR2-NEXT: LBB0_1: ## %cond.load +; AVX1OR2-NEXT: LBB0_3: ## %cond.load ; AVX1OR2-NEXT: vmovlps (%rdi), %xmm0, %xmm0 ## xmm0 = mem[0,1],xmm0[2,3] ; AVX1OR2-NEXT: addq $8, %rdi ; AVX1OR2-NEXT: testb $2, %al -; AVX1OR2-NEXT: je LBB0_4 -; AVX1OR2-NEXT: LBB0_3: ## %cond.load1 +; AVX1OR2-NEXT: je LBB0_2 +; AVX1OR2-NEXT: LBB0_4: ## %cond.load1 ; AVX1OR2-NEXT: vmovhps (%rdi), %xmm0, %xmm0 ## xmm0 = xmm0[0,1],mem[0,1] ; AVX1OR2-NEXT: retq ; @@ -111,34 +111,34 @@ define <4 x double> @expandload_v4f64_v4i64(ptr %base, <4 x double> %src0, <4 x ; SSE2-NEXT: andps %xmm4, %xmm2 ; SSE2-NEXT: movmskps %xmm2, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB1_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB1_5 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB1_3 -; SSE2-NEXT: LBB1_4: ## %else2 +; SSE2-NEXT: jne LBB1_6 +; SSE2-NEXT: LBB1_2: ## %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB1_5 -; SSE2-NEXT: LBB1_6: ## %else6 -; SSE2-NEXT: testb $8, %al ; SSE2-NEXT: jne LBB1_7 -; SSE2-NEXT: LBB1_8: ## %else10 +; SSE2-NEXT: LBB1_3: ## %else6 +; SSE2-NEXT: testb $8, %al +; SSE2-NEXT: jne LBB1_8 +; SSE2-NEXT: LBB1_4: ## %else10 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB1_1: ## %cond.load +; SSE2-NEXT: LBB1_5: ## %cond.load ; SSE2-NEXT: movlps (%rdi), %xmm0 ## xmm0 = mem[0,1],xmm0[2,3] ; SSE2-NEXT: addq $8, %rdi ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB1_4 -; SSE2-NEXT: LBB1_3: ## %cond.load1 +; SSE2-NEXT: je LBB1_2 +; SSE2-NEXT: LBB1_6: ## %cond.load1 ; SSE2-NEXT: movhps (%rdi), %xmm0 ## xmm0 = xmm0[0,1],mem[0,1] ; SSE2-NEXT: addq $8, %rdi ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB1_6 -; SSE2-NEXT: LBB1_5: ## %cond.load5 +; SSE2-NEXT: je LBB1_3 +; SSE2-NEXT: LBB1_7: ## %cond.load5 ; SSE2-NEXT: movlps (%rdi), %xmm1 ## xmm1 = mem[0,1],xmm1[2,3] ; SSE2-NEXT: addq $8, %rdi ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB1_8 -; SSE2-NEXT: LBB1_7: ## %cond.load9 +; SSE2-NEXT: je LBB1_4 +; SSE2-NEXT: LBB1_8: ## %cond.load9 ; SSE2-NEXT: movhps (%rdi), %xmm1 ## xmm1 = xmm1[0,1],mem[0,1] ; SSE2-NEXT: retq ; @@ -150,34 +150,34 @@ define <4 x double> @expandload_v4f64_v4i64(ptr %base, <4 x double> %src0, <4 x ; SSE42-NEXT: packssdw %xmm3, %xmm2 ; SSE42-NEXT: movmskps %xmm2, %eax ; SSE42-NEXT: testb $1, %al -; SSE42-NEXT: jne LBB1_1 -; SSE42-NEXT: ## %bb.2: ## %else +; SSE42-NEXT: jne LBB1_5 +; SSE42-NEXT: ## %bb.1: ## %else ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: jne LBB1_3 -; SSE42-NEXT: LBB1_4: ## %else2 +; SSE42-NEXT: jne LBB1_6 +; SSE42-NEXT: LBB1_2: ## %else2 ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: jne LBB1_5 -; SSE42-NEXT: LBB1_6: ## %else6 -; SSE42-NEXT: testb $8, %al ; SSE42-NEXT: jne LBB1_7 -; SSE42-NEXT: LBB1_8: ## %else10 +; SSE42-NEXT: LBB1_3: ## %else6 +; SSE42-NEXT: testb $8, %al +; SSE42-NEXT: jne LBB1_8 +; SSE42-NEXT: LBB1_4: ## %else10 ; SSE42-NEXT: retq -; SSE42-NEXT: LBB1_1: ## %cond.load +; SSE42-NEXT: LBB1_5: ## %cond.load ; SSE42-NEXT: movlps (%rdi), %xmm0 ## xmm0 = mem[0,1],xmm0[2,3] ; SSE42-NEXT: addq $8, %rdi ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: je LBB1_4 -; SSE42-NEXT: LBB1_3: ## %cond.load1 +; SSE42-NEXT: je LBB1_2 +; SSE42-NEXT: LBB1_6: ## %cond.load1 ; SSE42-NEXT: movhps (%rdi), %xmm0 ## xmm0 = xmm0[0,1],mem[0,1] ; SSE42-NEXT: addq $8, %rdi ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: je LBB1_6 -; SSE42-NEXT: LBB1_5: ## %cond.load5 +; SSE42-NEXT: je LBB1_3 +; SSE42-NEXT: LBB1_7: ## %cond.load5 ; SSE42-NEXT: movlps (%rdi), %xmm1 ## xmm1 = mem[0,1],xmm1[2,3] ; SSE42-NEXT: addq $8, %rdi ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: je LBB1_8 -; SSE42-NEXT: LBB1_7: ## %cond.load9 +; SSE42-NEXT: je LBB1_4 +; SSE42-NEXT: LBB1_8: ## %cond.load9 ; SSE42-NEXT: movhps (%rdi), %xmm1 ## xmm1 = xmm1[0,1],mem[0,1] ; SSE42-NEXT: retq ; @@ -190,37 +190,37 @@ define <4 x double> @expandload_v4f64_v4i64(ptr %base, <4 x double> %src0, <4 x ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1 ; AVX1-NEXT: vmovmskpd %ymm1, %eax ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne LBB1_1 -; AVX1-NEXT: ## %bb.2: ## %else +; AVX1-NEXT: jne LBB1_5 +; AVX1-NEXT: ## %bb.1: ## %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne LBB1_3 -; AVX1-NEXT: LBB1_4: ## %else2 +; AVX1-NEXT: jne LBB1_6 +; AVX1-NEXT: LBB1_2: ## %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne LBB1_5 -; AVX1-NEXT: LBB1_6: ## %else6 -; AVX1-NEXT: testb $8, %al ; AVX1-NEXT: jne LBB1_7 -; AVX1-NEXT: LBB1_8: ## %else10 +; AVX1-NEXT: LBB1_3: ## %else6 +; AVX1-NEXT: testb $8, %al +; AVX1-NEXT: jne LBB1_8 +; AVX1-NEXT: LBB1_4: ## %else10 ; AVX1-NEXT: retq -; AVX1-NEXT: LBB1_1: ## %cond.load +; AVX1-NEXT: LBB1_5: ## %cond.load ; AVX1-NEXT: vmovsd (%rdi), %xmm1 ## xmm1 = mem[0],zero ; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3] ; AVX1-NEXT: addq $8, %rdi ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je LBB1_4 -; AVX1-NEXT: LBB1_3: ## %cond.load1 +; AVX1-NEXT: je LBB1_2 +; AVX1-NEXT: LBB1_6: ## %cond.load1 ; AVX1-NEXT: vmovhpd (%rdi), %xmm0, %xmm1 ## xmm1 = xmm0[0],mem[0] ; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3] ; AVX1-NEXT: addq $8, %rdi ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je LBB1_6 -; AVX1-NEXT: LBB1_5: ## %cond.load5 +; AVX1-NEXT: je LBB1_3 +; AVX1-NEXT: LBB1_7: ## %cond.load5 ; AVX1-NEXT: vbroadcastsd (%rdi), %ymm1 ; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2],ymm0[3] ; AVX1-NEXT: addq $8, %rdi ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je LBB1_8 -; AVX1-NEXT: LBB1_7: ## %cond.load9 +; AVX1-NEXT: je LBB1_4 +; AVX1-NEXT: LBB1_8: ## %cond.load9 ; AVX1-NEXT: vbroadcastsd (%rdi), %ymm1 ; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1,2],ymm1[3] ; AVX1-NEXT: retq @@ -231,37 +231,37 @@ define <4 x double> @expandload_v4f64_v4i64(ptr %base, <4 x double> %src0, <4 x ; AVX2-NEXT: vpcmpeqq %ymm2, %ymm1, %ymm1 ; AVX2-NEXT: vmovmskpd %ymm1, %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne LBB1_1 -; AVX2-NEXT: ## %bb.2: ## %else +; AVX2-NEXT: jne LBB1_5 +; AVX2-NEXT: ## %bb.1: ## %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne LBB1_3 -; AVX2-NEXT: LBB1_4: ## %else2 +; AVX2-NEXT: jne LBB1_6 +; AVX2-NEXT: LBB1_2: ## %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne LBB1_5 -; AVX2-NEXT: LBB1_6: ## %else6 -; AVX2-NEXT: testb $8, %al ; AVX2-NEXT: jne LBB1_7 -; AVX2-NEXT: LBB1_8: ## %else10 +; AVX2-NEXT: LBB1_3: ## %else6 +; AVX2-NEXT: testb $8, %al +; AVX2-NEXT: jne LBB1_8 +; AVX2-NEXT: LBB1_4: ## %else10 ; AVX2-NEXT: retq -; AVX2-NEXT: LBB1_1: ## %cond.load +; AVX2-NEXT: LBB1_5: ## %cond.load ; AVX2-NEXT: vmovsd (%rdi), %xmm1 ## xmm1 = mem[0],zero ; AVX2-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0],ymm0[1,2,3] ; AVX2-NEXT: addq $8, %rdi ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je LBB1_4 -; AVX2-NEXT: LBB1_3: ## %cond.load1 +; AVX2-NEXT: je LBB1_2 +; AVX2-NEXT: LBB1_6: ## %cond.load1 ; AVX2-NEXT: vmovhpd (%rdi), %xmm0, %xmm1 ## xmm1 = xmm0[0],mem[0] ; AVX2-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3] ; AVX2-NEXT: addq $8, %rdi ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je LBB1_6 -; AVX2-NEXT: LBB1_5: ## %cond.load5 +; AVX2-NEXT: je LBB1_3 +; AVX2-NEXT: LBB1_7: ## %cond.load5 ; AVX2-NEXT: vbroadcastsd (%rdi), %ymm1 ; AVX2-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2],ymm0[3] ; AVX2-NEXT: addq $8, %rdi ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je LBB1_8 -; AVX2-NEXT: LBB1_7: ## %cond.load9 +; AVX2-NEXT: je LBB1_4 +; AVX2-NEXT: LBB1_8: ## %cond.load9 ; AVX2-NEXT: vbroadcastsd (%rdi), %ymm1 ; AVX2-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0,1,2],ymm1[3] ; AVX2-NEXT: retq @@ -294,66 +294,66 @@ define <8 x double> @expandload_v8f64_v8i1(ptr %base, <8 x double> %src0, <8 x i ; SSE-NEXT: packsswb %xmm4, %xmm4 ; SSE-NEXT: pmovmskb %xmm4, %eax ; SSE-NEXT: testb $1, %al -; SSE-NEXT: jne LBB2_1 -; SSE-NEXT: ## %bb.2: ## %else +; SSE-NEXT: jne LBB2_9 +; SSE-NEXT: ## %bb.1: ## %else ; SSE-NEXT: testb $2, %al -; SSE-NEXT: jne LBB2_3 -; SSE-NEXT: LBB2_4: ## %else2 +; SSE-NEXT: jne LBB2_10 +; SSE-NEXT: LBB2_2: ## %else2 ; SSE-NEXT: testb $4, %al -; SSE-NEXT: jne LBB2_5 -; SSE-NEXT: LBB2_6: ## %else6 +; SSE-NEXT: jne LBB2_11 +; SSE-NEXT: LBB2_3: ## %else6 ; SSE-NEXT: testb $8, %al -; SSE-NEXT: jne LBB2_7 -; SSE-NEXT: LBB2_8: ## %else10 +; SSE-NEXT: jne LBB2_12 +; SSE-NEXT: LBB2_4: ## %else10 ; SSE-NEXT: testb $16, %al -; SSE-NEXT: jne LBB2_9 -; SSE-NEXT: LBB2_10: ## %else14 +; SSE-NEXT: jne LBB2_13 +; SSE-NEXT: LBB2_5: ## %else14 ; SSE-NEXT: testb $32, %al -; SSE-NEXT: jne LBB2_11 -; SSE-NEXT: LBB2_12: ## %else18 +; SSE-NEXT: jne LBB2_14 +; SSE-NEXT: LBB2_6: ## %else18 ; SSE-NEXT: testb $64, %al -; SSE-NEXT: jne LBB2_13 -; SSE-NEXT: LBB2_14: ## %else22 -; SSE-NEXT: testb $-128, %al ; SSE-NEXT: jne LBB2_15 -; SSE-NEXT: LBB2_16: ## %else26 +; SSE-NEXT: LBB2_7: ## %else22 +; SSE-NEXT: testb $-128, %al +; SSE-NEXT: jne LBB2_16 +; SSE-NEXT: LBB2_8: ## %else26 ; SSE-NEXT: retq -; SSE-NEXT: LBB2_1: ## %cond.load +; SSE-NEXT: LBB2_9: ## %cond.load ; SSE-NEXT: movlps (%rdi), %xmm0 ## xmm0 = mem[0,1],xmm0[2,3] ; SSE-NEXT: addq $8, %rdi ; SSE-NEXT: testb $2, %al -; SSE-NEXT: je LBB2_4 -; SSE-NEXT: LBB2_3: ## %cond.load1 +; SSE-NEXT: je LBB2_2 +; SSE-NEXT: LBB2_10: ## %cond.load1 ; SSE-NEXT: movhps (%rdi), %xmm0 ## xmm0 = xmm0[0,1],mem[0,1] ; SSE-NEXT: addq $8, %rdi ; SSE-NEXT: testb $4, %al -; SSE-NEXT: je LBB2_6 -; SSE-NEXT: LBB2_5: ## %cond.load5 +; SSE-NEXT: je LBB2_3 +; SSE-NEXT: LBB2_11: ## %cond.load5 ; SSE-NEXT: movlps (%rdi), %xmm1 ## xmm1 = mem[0,1],xmm1[2,3] ; SSE-NEXT: addq $8, %rdi ; SSE-NEXT: testb $8, %al -; SSE-NEXT: je LBB2_8 -; SSE-NEXT: LBB2_7: ## %cond.load9 +; SSE-NEXT: je LBB2_4 +; SSE-NEXT: LBB2_12: ## %cond.load9 ; SSE-NEXT: movhps (%rdi), %xmm1 ## xmm1 = xmm1[0,1],mem[0,1] ; SSE-NEXT: addq $8, %rdi ; SSE-NEXT: testb $16, %al -; SSE-NEXT: je LBB2_10 -; SSE-NEXT: LBB2_9: ## %cond.load13 +; SSE-NEXT: je LBB2_5 +; SSE-NEXT: LBB2_13: ## %cond.load13 ; SSE-NEXT: movlps (%rdi), %xmm2 ## xmm2 = mem[0,1],xmm2[2,3] ; SSE-NEXT: addq $8, %rdi ; SSE-NEXT: testb $32, %al -; SSE-NEXT: je LBB2_12 -; SSE-NEXT: LBB2_11: ## %cond.load17 +; SSE-NEXT: je LBB2_6 +; SSE-NEXT: LBB2_14: ## %cond.load17 ; SSE-NEXT: movhps (%rdi), %xmm2 ## xmm2 = xmm2[0,1],mem[0,1] ; SSE-NEXT: addq $8, %rdi ; SSE-NEXT: testb $64, %al -; SSE-NEXT: je LBB2_14 -; SSE-NEXT: LBB2_13: ## %cond.load21 +; SSE-NEXT: je LBB2_7 +; SSE-NEXT: LBB2_15: ## %cond.load21 ; SSE-NEXT: movlps (%rdi), %xmm3 ## xmm3 = mem[0,1],xmm3[2,3] ; SSE-NEXT: addq $8, %rdi ; SSE-NEXT: testb $-128, %al -; SSE-NEXT: je LBB2_16 -; SSE-NEXT: LBB2_15: ## %cond.load25 +; SSE-NEXT: je LBB2_8 +; SSE-NEXT: LBB2_16: ## %cond.load25 ; SSE-NEXT: movhps (%rdi), %xmm3 ## xmm3 = xmm3[0,1],mem[0,1] ; SSE-NEXT: retq ; @@ -363,73 +363,73 @@ define <8 x double> @expandload_v8f64_v8i1(ptr %base, <8 x double> %src0, <8 x i ; AVX1-NEXT: vpacksswb %xmm2, %xmm2, %xmm2 ; AVX1-NEXT: vpmovmskb %xmm2, %eax ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne LBB2_1 -; AVX1-NEXT: ## %bb.2: ## %else +; AVX1-NEXT: jne LBB2_9 +; AVX1-NEXT: ## %bb.1: ## %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne LBB2_3 -; AVX1-NEXT: LBB2_4: ## %else2 +; AVX1-NEXT: jne LBB2_10 +; AVX1-NEXT: LBB2_2: ## %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne LBB2_5 -; AVX1-NEXT: LBB2_6: ## %else6 +; AVX1-NEXT: jne LBB2_11 +; AVX1-NEXT: LBB2_3: ## %else6 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne LBB2_7 -; AVX1-NEXT: LBB2_8: ## %else10 +; AVX1-NEXT: jne LBB2_12 +; AVX1-NEXT: LBB2_4: ## %else10 ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: jne LBB2_9 -; AVX1-NEXT: LBB2_10: ## %else14 +; AVX1-NEXT: jne LBB2_13 +; AVX1-NEXT: LBB2_5: ## %else14 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: jne LBB2_11 -; AVX1-NEXT: LBB2_12: ## %else18 +; AVX1-NEXT: jne LBB2_14 +; AVX1-NEXT: LBB2_6: ## %else18 ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: jne LBB2_13 -; AVX1-NEXT: LBB2_14: ## %else22 -; AVX1-NEXT: testb $-128, %al ; AVX1-NEXT: jne LBB2_15 -; AVX1-NEXT: LBB2_16: ## %else26 +; AVX1-NEXT: LBB2_7: ## %else22 +; AVX1-NEXT: testb $-128, %al +; AVX1-NEXT: jne LBB2_16 +; AVX1-NEXT: LBB2_8: ## %else26 ; AVX1-NEXT: retq -; AVX1-NEXT: LBB2_1: ## %cond.load +; AVX1-NEXT: LBB2_9: ## %cond.load ; AVX1-NEXT: vmovsd (%rdi), %xmm2 ## xmm2 = mem[0],zero ; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm2[0,1],ymm0[2,3,4,5,6,7] ; AVX1-NEXT: addq $8, %rdi ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je LBB2_4 -; AVX1-NEXT: LBB2_3: ## %cond.load1 +; AVX1-NEXT: je LBB2_2 +; AVX1-NEXT: LBB2_10: ## %cond.load1 ; AVX1-NEXT: vmovhps (%rdi), %xmm0, %xmm2 ## xmm2 = xmm0[0,1],mem[0,1] ; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm2[0,1,2,3],ymm0[4,5,6,7] ; AVX1-NEXT: addq $8, %rdi ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je LBB2_6 -; AVX1-NEXT: LBB2_5: ## %cond.load5 +; AVX1-NEXT: je LBB2_3 +; AVX1-NEXT: LBB2_11: ## %cond.load5 ; AVX1-NEXT: vbroadcastsd (%rdi), %ymm2 ; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm2[4,5],ymm0[6,7] ; AVX1-NEXT: addq $8, %rdi ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je LBB2_8 -; AVX1-NEXT: LBB2_7: ## %cond.load9 +; AVX1-NEXT: je LBB2_4 +; AVX1-NEXT: LBB2_12: ## %cond.load9 ; AVX1-NEXT: vbroadcastsd (%rdi), %ymm2 ; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5],ymm2[6,7] ; AVX1-NEXT: addq $8, %rdi ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: je LBB2_10 -; AVX1-NEXT: LBB2_9: ## %cond.load13 +; AVX1-NEXT: je LBB2_5 +; AVX1-NEXT: LBB2_13: ## %cond.load13 ; AVX1-NEXT: vmovsd (%rdi), %xmm2 ## xmm2 = mem[0],zero ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm2[0,1],ymm1[2,3,4,5,6,7] ; AVX1-NEXT: addq $8, %rdi ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je LBB2_12 -; AVX1-NEXT: LBB2_11: ## %cond.load17 +; AVX1-NEXT: je LBB2_6 +; AVX1-NEXT: LBB2_14: ## %cond.load17 ; AVX1-NEXT: vmovhps (%rdi), %xmm1, %xmm2 ## xmm2 = xmm1[0,1],mem[0,1] ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm2[0,1,2,3],ymm1[4,5,6,7] ; AVX1-NEXT: addq $8, %rdi ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: je LBB2_14 -; AVX1-NEXT: LBB2_13: ## %cond.load21 +; AVX1-NEXT: je LBB2_7 +; AVX1-NEXT: LBB2_15: ## %cond.load21 ; AVX1-NEXT: vbroadcastsd (%rdi), %ymm2 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm2[4,5],ymm1[6,7] ; AVX1-NEXT: addq $8, %rdi ; AVX1-NEXT: testb $-128, %al -; AVX1-NEXT: je LBB2_16 -; AVX1-NEXT: LBB2_15: ## %cond.load25 +; AVX1-NEXT: je LBB2_8 +; AVX1-NEXT: LBB2_16: ## %cond.load25 ; AVX1-NEXT: vbroadcastsd (%rdi), %ymm2 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1,2,3,4,5],ymm2[6,7] ; AVX1-NEXT: retq @@ -440,73 +440,73 @@ define <8 x double> @expandload_v8f64_v8i1(ptr %base, <8 x double> %src0, <8 x i ; AVX2-NEXT: vpacksswb %xmm2, %xmm2, %xmm2 ; AVX2-NEXT: vpmovmskb %xmm2, %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne LBB2_1 -; AVX2-NEXT: ## %bb.2: ## %else +; AVX2-NEXT: jne LBB2_9 +; AVX2-NEXT: ## %bb.1: ## %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne LBB2_3 -; AVX2-NEXT: LBB2_4: ## %else2 +; AVX2-NEXT: jne LBB2_10 +; AVX2-NEXT: LBB2_2: ## %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne LBB2_5 -; AVX2-NEXT: LBB2_6: ## %else6 +; AVX2-NEXT: jne LBB2_11 +; AVX2-NEXT: LBB2_3: ## %else6 ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: jne LBB2_7 -; AVX2-NEXT: LBB2_8: ## %else10 +; AVX2-NEXT: jne LBB2_12 +; AVX2-NEXT: LBB2_4: ## %else10 ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: jne LBB2_9 -; AVX2-NEXT: LBB2_10: ## %else14 +; AVX2-NEXT: jne LBB2_13 +; AVX2-NEXT: LBB2_5: ## %else14 ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: jne LBB2_11 -; AVX2-NEXT: LBB2_12: ## %else18 +; AVX2-NEXT: jne LBB2_14 +; AVX2-NEXT: LBB2_6: ## %else18 ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: jne LBB2_13 -; AVX2-NEXT: LBB2_14: ## %else22 -; AVX2-NEXT: testb $-128, %al ; AVX2-NEXT: jne LBB2_15 -; AVX2-NEXT: LBB2_16: ## %else26 +; AVX2-NEXT: LBB2_7: ## %else22 +; AVX2-NEXT: testb $-128, %al +; AVX2-NEXT: jne LBB2_16 +; AVX2-NEXT: LBB2_8: ## %else26 ; AVX2-NEXT: retq -; AVX2-NEXT: LBB2_1: ## %cond.load +; AVX2-NEXT: LBB2_9: ## %cond.load ; AVX2-NEXT: vmovq (%rdi), %xmm2 ## xmm2 = mem[0],zero ; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm2[0,1],ymm0[2,3,4,5,6,7] ; AVX2-NEXT: addq $8, %rdi ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je LBB2_4 -; AVX2-NEXT: LBB2_3: ## %cond.load1 +; AVX2-NEXT: je LBB2_2 +; AVX2-NEXT: LBB2_10: ## %cond.load1 ; AVX2-NEXT: vmovhps (%rdi), %xmm0, %xmm2 ## xmm2 = xmm0[0,1],mem[0,1] ; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm2[0,1,2,3],ymm0[4,5,6,7] ; AVX2-NEXT: addq $8, %rdi ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je LBB2_6 -; AVX2-NEXT: LBB2_5: ## %cond.load5 +; AVX2-NEXT: je LBB2_3 +; AVX2-NEXT: LBB2_11: ## %cond.load5 ; AVX2-NEXT: vpbroadcastq (%rdi), %ymm2 ; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm2[4,5],ymm0[6,7] ; AVX2-NEXT: addq $8, %rdi ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je LBB2_8 -; AVX2-NEXT: LBB2_7: ## %cond.load9 +; AVX2-NEXT: je LBB2_4 +; AVX2-NEXT: LBB2_12: ## %cond.load9 ; AVX2-NEXT: vpbroadcastq (%rdi), %ymm2 ; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5],ymm2[6,7] ; AVX2-NEXT: addq $8, %rdi ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: je LBB2_10 -; AVX2-NEXT: LBB2_9: ## %cond.load13 +; AVX2-NEXT: je LBB2_5 +; AVX2-NEXT: LBB2_13: ## %cond.load13 ; AVX2-NEXT: vmovq (%rdi), %xmm2 ## xmm2 = mem[0],zero ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm2[0,1],ymm1[2,3,4,5,6,7] ; AVX2-NEXT: addq $8, %rdi ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: je LBB2_12 -; AVX2-NEXT: LBB2_11: ## %cond.load17 +; AVX2-NEXT: je LBB2_6 +; AVX2-NEXT: LBB2_14: ## %cond.load17 ; AVX2-NEXT: vmovhps (%rdi), %xmm1, %xmm2 ## xmm2 = xmm1[0,1],mem[0,1] ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm2[0,1,2,3],ymm1[4,5,6,7] ; AVX2-NEXT: addq $8, %rdi ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: je LBB2_14 -; AVX2-NEXT: LBB2_13: ## %cond.load21 +; AVX2-NEXT: je LBB2_7 +; AVX2-NEXT: LBB2_15: ## %cond.load21 ; AVX2-NEXT: vpbroadcastq (%rdi), %ymm2 ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm2[4,5],ymm1[6,7] ; AVX2-NEXT: addq $8, %rdi ; AVX2-NEXT: testb $-128, %al -; AVX2-NEXT: je LBB2_16 -; AVX2-NEXT: LBB2_15: ## %cond.load25 +; AVX2-NEXT: je LBB2_8 +; AVX2-NEXT: LBB2_16: ## %cond.load25 ; AVX2-NEXT: vpbroadcastq (%rdi), %ymm2 ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3,4,5],ymm2[6,7] ; AVX2-NEXT: retq @@ -554,55 +554,55 @@ define <16 x double> @expandload_v16f64_v16i32(ptr %base, <16 x double> %src0, < ; SSE-NEXT: packsswb %xmm10, %xmm8 ; SSE-NEXT: pmovmskb %xmm8, %ecx ; SSE-NEXT: testb $1, %cl -; SSE-NEXT: jne LBB3_1 -; SSE-NEXT: ## %bb.2: ## %else +; SSE-NEXT: jne LBB3_18 +; SSE-NEXT: ## %bb.1: ## %else ; SSE-NEXT: testb $2, %cl -; SSE-NEXT: jne LBB3_3 -; SSE-NEXT: LBB3_4: ## %else2 +; SSE-NEXT: jne LBB3_19 +; SSE-NEXT: LBB3_2: ## %else2 ; SSE-NEXT: testb $4, %cl -; SSE-NEXT: jne LBB3_5 -; SSE-NEXT: LBB3_6: ## %else6 +; SSE-NEXT: jne LBB3_20 +; SSE-NEXT: LBB3_3: ## %else6 ; SSE-NEXT: testb $8, %cl -; SSE-NEXT: jne LBB3_7 -; SSE-NEXT: LBB3_8: ## %else10 +; SSE-NEXT: jne LBB3_21 +; SSE-NEXT: LBB3_4: ## %else10 ; SSE-NEXT: testb $16, %cl -; SSE-NEXT: jne LBB3_9 -; SSE-NEXT: LBB3_10: ## %else14 +; SSE-NEXT: jne LBB3_22 +; SSE-NEXT: LBB3_5: ## %else14 ; SSE-NEXT: testb $32, %cl -; SSE-NEXT: jne LBB3_11 -; SSE-NEXT: LBB3_12: ## %else18 +; SSE-NEXT: jne LBB3_23 +; SSE-NEXT: LBB3_6: ## %else18 ; SSE-NEXT: testb $64, %cl -; SSE-NEXT: jne LBB3_13 -; SSE-NEXT: LBB3_14: ## %else22 +; SSE-NEXT: jne LBB3_24 +; SSE-NEXT: LBB3_7: ## %else22 ; SSE-NEXT: testb %cl, %cl -; SSE-NEXT: js LBB3_15 -; SSE-NEXT: LBB3_16: ## %else26 +; SSE-NEXT: js LBB3_25 +; SSE-NEXT: LBB3_8: ## %else26 ; SSE-NEXT: testl $256, %ecx ## imm = 0x100 -; SSE-NEXT: jne LBB3_17 -; SSE-NEXT: LBB3_18: ## %else30 +; SSE-NEXT: jne LBB3_26 +; SSE-NEXT: LBB3_9: ## %else30 ; SSE-NEXT: testl $512, %ecx ## imm = 0x200 -; SSE-NEXT: jne LBB3_19 -; SSE-NEXT: LBB3_20: ## %else34 +; SSE-NEXT: jne LBB3_27 +; SSE-NEXT: LBB3_10: ## %else34 ; SSE-NEXT: testl $1024, %ecx ## imm = 0x400 -; SSE-NEXT: jne LBB3_21 -; SSE-NEXT: LBB3_22: ## %else38 +; SSE-NEXT: jne LBB3_28 +; SSE-NEXT: LBB3_11: ## %else38 ; SSE-NEXT: testl $2048, %ecx ## imm = 0x800 -; SSE-NEXT: jne LBB3_23 -; SSE-NEXT: LBB3_24: ## %else42 +; SSE-NEXT: jne LBB3_29 +; SSE-NEXT: LBB3_12: ## %else42 ; SSE-NEXT: testl $4096, %ecx ## imm = 0x1000 -; SSE-NEXT: jne LBB3_25 -; SSE-NEXT: LBB3_26: ## %else46 +; SSE-NEXT: jne LBB3_30 +; SSE-NEXT: LBB3_13: ## %else46 ; SSE-NEXT: testl $8192, %ecx ## imm = 0x2000 -; SSE-NEXT: jne LBB3_27 -; SSE-NEXT: LBB3_28: ## %else50 +; SSE-NEXT: jne LBB3_31 +; SSE-NEXT: LBB3_14: ## %else50 ; SSE-NEXT: testl $16384, %ecx ## imm = 0x4000 -; SSE-NEXT: jne LBB3_29 -; SSE-NEXT: LBB3_30: ## %else54 +; SSE-NEXT: jne LBB3_32 +; SSE-NEXT: LBB3_15: ## %else54 ; SSE-NEXT: testl $32768, %ecx ## imm = 0x8000 -; SSE-NEXT: je LBB3_32 -; SSE-NEXT: LBB3_31: ## %cond.load57 +; SSE-NEXT: je LBB3_17 +; SSE-NEXT: LBB3_16: ## %cond.load57 ; SSE-NEXT: movhps (%rsi), %xmm7 ## xmm7 = xmm7[0,1],mem[0,1] -; SSE-NEXT: LBB3_32: ## %else58 +; SSE-NEXT: LBB3_17: ## %else58 ; SSE-NEXT: movaps %xmm0, (%rax) ; SSE-NEXT: movaps %xmm1, 16(%rax) ; SSE-NEXT: movaps %xmm2, 32(%rax) @@ -612,82 +612,82 @@ define <16 x double> @expandload_v16f64_v16i32(ptr %base, <16 x double> %src0, < ; SSE-NEXT: movaps %xmm6, 96(%rax) ; SSE-NEXT: movaps %xmm7, 112(%rax) ; SSE-NEXT: retq -; SSE-NEXT: LBB3_1: ## %cond.load +; SSE-NEXT: LBB3_18: ## %cond.load ; SSE-NEXT: movlps (%rsi), %xmm0 ## xmm0 = mem[0,1],xmm0[2,3] ; SSE-NEXT: addq $8, %rsi ; SSE-NEXT: testb $2, %cl -; SSE-NEXT: je LBB3_4 -; SSE-NEXT: LBB3_3: ## %cond.load1 +; SSE-NEXT: je LBB3_2 +; SSE-NEXT: LBB3_19: ## %cond.load1 ; SSE-NEXT: movhps (%rsi), %xmm0 ## xmm0 = xmm0[0,1],mem[0,1] ; SSE-NEXT: addq $8, %rsi ; SSE-NEXT: testb $4, %cl -; SSE-NEXT: je LBB3_6 -; SSE-NEXT: LBB3_5: ## %cond.load5 +; SSE-NEXT: je LBB3_3 +; SSE-NEXT: LBB3_20: ## %cond.load5 ; SSE-NEXT: movlps (%rsi), %xmm1 ## xmm1 = mem[0,1],xmm1[2,3] ; SSE-NEXT: addq $8, %rsi ; SSE-NEXT: testb $8, %cl -; SSE-NEXT: je LBB3_8 -; SSE-NEXT: LBB3_7: ## %cond.load9 +; SSE-NEXT: je LBB3_4 +; SSE-NEXT: LBB3_21: ## %cond.load9 ; SSE-NEXT: movhps (%rsi), %xmm1 ## xmm1 = xmm1[0,1],mem[0,1] ; SSE-NEXT: addq $8, %rsi ; SSE-NEXT: testb $16, %cl -; SSE-NEXT: je LBB3_10 -; SSE-NEXT: LBB3_9: ## %cond.load13 +; SSE-NEXT: je LBB3_5 +; SSE-NEXT: LBB3_22: ## %cond.load13 ; SSE-NEXT: movlps (%rsi), %xmm2 ## xmm2 = mem[0,1],xmm2[2,3] ; SSE-NEXT: addq $8, %rsi ; SSE-NEXT: testb $32, %cl -; SSE-NEXT: je LBB3_12 -; SSE-NEXT: LBB3_11: ## %cond.load17 +; SSE-NEXT: je LBB3_6 +; SSE-NEXT: LBB3_23: ## %cond.load17 ; SSE-NEXT: movhps (%rsi), %xmm2 ## xmm2 = xmm2[0,1],mem[0,1] ; SSE-NEXT: addq $8, %rsi ; SSE-NEXT: testb $64, %cl -; SSE-NEXT: je LBB3_14 -; SSE-NEXT: LBB3_13: ## %cond.load21 +; SSE-NEXT: je LBB3_7 +; SSE-NEXT: LBB3_24: ## %cond.load21 ; SSE-NEXT: movlps (%rsi), %xmm3 ## xmm3 = mem[0,1],xmm3[2,3] ; SSE-NEXT: addq $8, %rsi ; SSE-NEXT: testb %cl, %cl -; SSE-NEXT: jns LBB3_16 -; SSE-NEXT: LBB3_15: ## %cond.load25 +; SSE-NEXT: jns LBB3_8 +; SSE-NEXT: LBB3_25: ## %cond.load25 ; SSE-NEXT: movhps (%rsi), %xmm3 ## xmm3 = xmm3[0,1],mem[0,1] ; SSE-NEXT: addq $8, %rsi ; SSE-NEXT: testl $256, %ecx ## imm = 0x100 -; SSE-NEXT: je LBB3_18 -; SSE-NEXT: LBB3_17: ## %cond.load29 +; SSE-NEXT: je LBB3_9 +; SSE-NEXT: LBB3_26: ## %cond.load29 ; SSE-NEXT: movlps (%rsi), %xmm4 ## xmm4 = mem[0,1],xmm4[2,3] ; SSE-NEXT: addq $8, %rsi ; SSE-NEXT: testl $512, %ecx ## imm = 0x200 -; SSE-NEXT: je LBB3_20 -; SSE-NEXT: LBB3_19: ## %cond.load33 +; SSE-NEXT: je LBB3_10 +; SSE-NEXT: LBB3_27: ## %cond.load33 ; SSE-NEXT: movhps (%rsi), %xmm4 ## xmm4 = xmm4[0,1],mem[0,1] ; SSE-NEXT: addq $8, %rsi ; SSE-NEXT: testl $1024, %ecx ## imm = 0x400 -; SSE-NEXT: je LBB3_22 -; SSE-NEXT: LBB3_21: ## %cond.load37 +; SSE-NEXT: je LBB3_11 +; SSE-NEXT: LBB3_28: ## %cond.load37 ; SSE-NEXT: movlps (%rsi), %xmm5 ## xmm5 = mem[0,1],xmm5[2,3] ; SSE-NEXT: addq $8, %rsi ; SSE-NEXT: testl $2048, %ecx ## imm = 0x800 -; SSE-NEXT: je LBB3_24 -; SSE-NEXT: LBB3_23: ## %cond.load41 +; SSE-NEXT: je LBB3_12 +; SSE-NEXT: LBB3_29: ## %cond.load41 ; SSE-NEXT: movhps (%rsi), %xmm5 ## xmm5 = xmm5[0,1],mem[0,1] ; SSE-NEXT: addq $8, %rsi ; SSE-NEXT: testl $4096, %ecx ## imm = 0x1000 -; SSE-NEXT: je LBB3_26 -; SSE-NEXT: LBB3_25: ## %cond.load45 +; SSE-NEXT: je LBB3_13 +; SSE-NEXT: LBB3_30: ## %cond.load45 ; SSE-NEXT: movlps (%rsi), %xmm6 ## xmm6 = mem[0,1],xmm6[2,3] ; SSE-NEXT: addq $8, %rsi ; SSE-NEXT: testl $8192, %ecx ## imm = 0x2000 -; SSE-NEXT: je LBB3_28 -; SSE-NEXT: LBB3_27: ## %cond.load49 +; SSE-NEXT: je LBB3_14 +; SSE-NEXT: LBB3_31: ## %cond.load49 ; SSE-NEXT: movhps (%rsi), %xmm6 ## xmm6 = xmm6[0,1],mem[0,1] ; SSE-NEXT: addq $8, %rsi ; SSE-NEXT: testl $16384, %ecx ## imm = 0x4000 -; SSE-NEXT: je LBB3_30 -; SSE-NEXT: LBB3_29: ## %cond.load53 +; SSE-NEXT: je LBB3_15 +; SSE-NEXT: LBB3_32: ## %cond.load53 ; SSE-NEXT: movlps (%rsi), %xmm7 ## xmm7 = mem[0,1],xmm7[2,3] ; SSE-NEXT: addq $8, %rsi ; SSE-NEXT: testl $32768, %ecx ## imm = 0x8000 -; SSE-NEXT: jne LBB3_31 -; SSE-NEXT: jmp LBB3_32 +; SSE-NEXT: jne LBB3_16 +; SSE-NEXT: jmp LBB3_17 ; ; AVX1-LABEL: expandload_v16f64_v16i32: ; AVX1: ## %bb.0: @@ -703,145 +703,145 @@ define <16 x double> @expandload_v16f64_v16i32(ptr %base, <16 x double> %src0, < ; AVX1-NEXT: vpacksswb %xmm5, %xmm4, %xmm4 ; AVX1-NEXT: vpmovmskb %xmm4, %eax ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne LBB3_1 -; AVX1-NEXT: ## %bb.2: ## %else +; AVX1-NEXT: jne LBB3_17 +; AVX1-NEXT: ## %bb.1: ## %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne LBB3_3 -; AVX1-NEXT: LBB3_4: ## %else2 +; AVX1-NEXT: jne LBB3_18 +; AVX1-NEXT: LBB3_2: ## %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne LBB3_5 -; AVX1-NEXT: LBB3_6: ## %else6 +; AVX1-NEXT: jne LBB3_19 +; AVX1-NEXT: LBB3_3: ## %else6 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne LBB3_7 -; AVX1-NEXT: LBB3_8: ## %else10 +; AVX1-NEXT: jne LBB3_20 +; AVX1-NEXT: LBB3_4: ## %else10 ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: jne LBB3_9 -; AVX1-NEXT: LBB3_10: ## %else14 +; AVX1-NEXT: jne LBB3_21 +; AVX1-NEXT: LBB3_5: ## %else14 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: jne LBB3_11 -; AVX1-NEXT: LBB3_12: ## %else18 +; AVX1-NEXT: jne LBB3_22 +; AVX1-NEXT: LBB3_6: ## %else18 ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: jne LBB3_13 -; AVX1-NEXT: LBB3_14: ## %else22 +; AVX1-NEXT: jne LBB3_23 +; AVX1-NEXT: LBB3_7: ## %else22 ; AVX1-NEXT: testb %al, %al -; AVX1-NEXT: js LBB3_15 -; AVX1-NEXT: LBB3_16: ## %else26 +; AVX1-NEXT: js LBB3_24 +; AVX1-NEXT: LBB3_8: ## %else26 ; AVX1-NEXT: testl $256, %eax ## imm = 0x100 -; AVX1-NEXT: jne LBB3_17 -; AVX1-NEXT: LBB3_18: ## %else30 +; AVX1-NEXT: jne LBB3_25 +; AVX1-NEXT: LBB3_9: ## %else30 ; AVX1-NEXT: testl $512, %eax ## imm = 0x200 -; AVX1-NEXT: jne LBB3_19 -; AVX1-NEXT: LBB3_20: ## %else34 +; AVX1-NEXT: jne LBB3_26 +; AVX1-NEXT: LBB3_10: ## %else34 ; AVX1-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX1-NEXT: jne LBB3_21 -; AVX1-NEXT: LBB3_22: ## %else38 +; AVX1-NEXT: jne LBB3_27 +; AVX1-NEXT: LBB3_11: ## %else38 ; AVX1-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX1-NEXT: jne LBB3_23 -; AVX1-NEXT: LBB3_24: ## %else42 +; AVX1-NEXT: jne LBB3_28 +; AVX1-NEXT: LBB3_12: ## %else42 ; AVX1-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX1-NEXT: jne LBB3_25 -; AVX1-NEXT: LBB3_26: ## %else46 +; AVX1-NEXT: jne LBB3_29 +; AVX1-NEXT: LBB3_13: ## %else46 ; AVX1-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX1-NEXT: jne LBB3_27 -; AVX1-NEXT: LBB3_28: ## %else50 +; AVX1-NEXT: jne LBB3_30 +; AVX1-NEXT: LBB3_14: ## %else50 ; AVX1-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX1-NEXT: jne LBB3_29 -; AVX1-NEXT: LBB3_30: ## %else54 -; AVX1-NEXT: testl $32768, %eax ## imm = 0x8000 ; AVX1-NEXT: jne LBB3_31 -; AVX1-NEXT: LBB3_32: ## %else58 +; AVX1-NEXT: LBB3_15: ## %else54 +; AVX1-NEXT: testl $32768, %eax ## imm = 0x8000 +; AVX1-NEXT: jne LBB3_32 +; AVX1-NEXT: LBB3_16: ## %else58 ; AVX1-NEXT: retq -; AVX1-NEXT: LBB3_1: ## %cond.load +; AVX1-NEXT: LBB3_17: ## %cond.load ; AVX1-NEXT: vmovsd (%rdi), %xmm4 ## xmm4 = mem[0],zero ; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm4[0,1],ymm0[2,3,4,5,6,7] ; AVX1-NEXT: addq $8, %rdi ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je LBB3_4 -; AVX1-NEXT: LBB3_3: ## %cond.load1 +; AVX1-NEXT: je LBB3_2 +; AVX1-NEXT: LBB3_18: ## %cond.load1 ; AVX1-NEXT: vmovhps (%rdi), %xmm0, %xmm4 ## xmm4 = xmm0[0,1],mem[0,1] ; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm4[0,1,2,3],ymm0[4,5,6,7] ; AVX1-NEXT: addq $8, %rdi ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je LBB3_6 -; AVX1-NEXT: LBB3_5: ## %cond.load5 +; AVX1-NEXT: je LBB3_3 +; AVX1-NEXT: LBB3_19: ## %cond.load5 ; AVX1-NEXT: vbroadcastsd (%rdi), %ymm4 ; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm4[4,5],ymm0[6,7] ; AVX1-NEXT: addq $8, %rdi ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je LBB3_8 -; AVX1-NEXT: LBB3_7: ## %cond.load9 +; AVX1-NEXT: je LBB3_4 +; AVX1-NEXT: LBB3_20: ## %cond.load9 ; AVX1-NEXT: vbroadcastsd (%rdi), %ymm4 ; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5],ymm4[6,7] ; AVX1-NEXT: addq $8, %rdi ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: je LBB3_10 -; AVX1-NEXT: LBB3_9: ## %cond.load13 +; AVX1-NEXT: je LBB3_5 +; AVX1-NEXT: LBB3_21: ## %cond.load13 ; AVX1-NEXT: vmovsd (%rdi), %xmm4 ## xmm4 = mem[0],zero ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm4[0,1],ymm1[2,3,4,5,6,7] ; AVX1-NEXT: addq $8, %rdi ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je LBB3_12 -; AVX1-NEXT: LBB3_11: ## %cond.load17 +; AVX1-NEXT: je LBB3_6 +; AVX1-NEXT: LBB3_22: ## %cond.load17 ; AVX1-NEXT: vmovhps (%rdi), %xmm1, %xmm4 ## xmm4 = xmm1[0,1],mem[0,1] ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm4[0,1,2,3],ymm1[4,5,6,7] ; AVX1-NEXT: addq $8, %rdi ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: je LBB3_14 -; AVX1-NEXT: LBB3_13: ## %cond.load21 +; AVX1-NEXT: je LBB3_7 +; AVX1-NEXT: LBB3_23: ## %cond.load21 ; AVX1-NEXT: vbroadcastsd (%rdi), %ymm4 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm4[4,5],ymm1[6,7] ; AVX1-NEXT: addq $8, %rdi ; AVX1-NEXT: testb %al, %al -; AVX1-NEXT: jns LBB3_16 -; AVX1-NEXT: LBB3_15: ## %cond.load25 +; AVX1-NEXT: jns LBB3_8 +; AVX1-NEXT: LBB3_24: ## %cond.load25 ; AVX1-NEXT: vbroadcastsd (%rdi), %ymm4 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1,2,3,4,5],ymm4[6,7] ; AVX1-NEXT: addq $8, %rdi ; AVX1-NEXT: testl $256, %eax ## imm = 0x100 -; AVX1-NEXT: je LBB3_18 -; AVX1-NEXT: LBB3_17: ## %cond.load29 +; AVX1-NEXT: je LBB3_9 +; AVX1-NEXT: LBB3_25: ## %cond.load29 ; AVX1-NEXT: vmovsd (%rdi), %xmm4 ## xmm4 = mem[0],zero ; AVX1-NEXT: vblendps {{.*#+}} ymm2 = ymm4[0,1],ymm2[2,3,4,5,6,7] ; AVX1-NEXT: addq $8, %rdi ; AVX1-NEXT: testl $512, %eax ## imm = 0x200 -; AVX1-NEXT: je LBB3_20 -; AVX1-NEXT: LBB3_19: ## %cond.load33 +; AVX1-NEXT: je LBB3_10 +; AVX1-NEXT: LBB3_26: ## %cond.load33 ; AVX1-NEXT: vmovhps (%rdi), %xmm2, %xmm4 ## xmm4 = xmm2[0,1],mem[0,1] ; AVX1-NEXT: vblendps {{.*#+}} ymm2 = ymm4[0,1,2,3],ymm2[4,5,6,7] ; AVX1-NEXT: addq $8, %rdi ; AVX1-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX1-NEXT: je LBB3_22 -; AVX1-NEXT: LBB3_21: ## %cond.load37 +; AVX1-NEXT: je LBB3_11 +; AVX1-NEXT: LBB3_27: ## %cond.load37 ; AVX1-NEXT: vbroadcastsd (%rdi), %ymm4 ; AVX1-NEXT: vblendps {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm4[4,5],ymm2[6,7] ; AVX1-NEXT: addq $8, %rdi ; AVX1-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX1-NEXT: je LBB3_24 -; AVX1-NEXT: LBB3_23: ## %cond.load41 +; AVX1-NEXT: je LBB3_12 +; AVX1-NEXT: LBB3_28: ## %cond.load41 ; AVX1-NEXT: vbroadcastsd (%rdi), %ymm4 ; AVX1-NEXT: vblendps {{.*#+}} ymm2 = ymm2[0,1,2,3,4,5],ymm4[6,7] ; AVX1-NEXT: addq $8, %rdi ; AVX1-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX1-NEXT: je LBB3_26 -; AVX1-NEXT: LBB3_25: ## %cond.load45 +; AVX1-NEXT: je LBB3_13 +; AVX1-NEXT: LBB3_29: ## %cond.load45 ; AVX1-NEXT: vmovsd (%rdi), %xmm4 ## xmm4 = mem[0],zero ; AVX1-NEXT: vblendps {{.*#+}} ymm3 = ymm4[0,1],ymm3[2,3,4,5,6,7] ; AVX1-NEXT: addq $8, %rdi ; AVX1-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX1-NEXT: je LBB3_28 -; AVX1-NEXT: LBB3_27: ## %cond.load49 +; AVX1-NEXT: je LBB3_14 +; AVX1-NEXT: LBB3_30: ## %cond.load49 ; AVX1-NEXT: vmovhps (%rdi), %xmm3, %xmm4 ## xmm4 = xmm3[0,1],mem[0,1] ; AVX1-NEXT: vblendps {{.*#+}} ymm3 = ymm4[0,1,2,3],ymm3[4,5,6,7] ; AVX1-NEXT: addq $8, %rdi ; AVX1-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX1-NEXT: je LBB3_30 -; AVX1-NEXT: LBB3_29: ## %cond.load53 +; AVX1-NEXT: je LBB3_15 +; AVX1-NEXT: LBB3_31: ## %cond.load53 ; AVX1-NEXT: vbroadcastsd (%rdi), %ymm4 ; AVX1-NEXT: vblendps {{.*#+}} ymm3 = ymm3[0,1,2,3],ymm4[4,5],ymm3[6,7] ; AVX1-NEXT: addq $8, %rdi ; AVX1-NEXT: testl $32768, %eax ## imm = 0x8000 -; AVX1-NEXT: je LBB3_32 -; AVX1-NEXT: LBB3_31: ## %cond.load57 +; AVX1-NEXT: je LBB3_16 +; AVX1-NEXT: LBB3_32: ## %cond.load57 ; AVX1-NEXT: vbroadcastsd (%rdi), %ymm4 ; AVX1-NEXT: vblendps {{.*#+}} ymm3 = ymm3[0,1,2,3,4,5],ymm4[6,7] ; AVX1-NEXT: retq @@ -857,145 +857,145 @@ define <16 x double> @expandload_v16f64_v16i32(ptr %base, <16 x double> %src0, < ; AVX2-NEXT: vpshufd {{.*#+}} xmm4 = xmm4[0,2,1,3] ; AVX2-NEXT: vpmovmskb %xmm4, %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne LBB3_1 -; AVX2-NEXT: ## %bb.2: ## %else +; AVX2-NEXT: jne LBB3_17 +; AVX2-NEXT: ## %bb.1: ## %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne LBB3_3 -; AVX2-NEXT: LBB3_4: ## %else2 +; AVX2-NEXT: jne LBB3_18 +; AVX2-NEXT: LBB3_2: ## %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne LBB3_5 -; AVX2-NEXT: LBB3_6: ## %else6 +; AVX2-NEXT: jne LBB3_19 +; AVX2-NEXT: LBB3_3: ## %else6 ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: jne LBB3_7 -; AVX2-NEXT: LBB3_8: ## %else10 +; AVX2-NEXT: jne LBB3_20 +; AVX2-NEXT: LBB3_4: ## %else10 ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: jne LBB3_9 -; AVX2-NEXT: LBB3_10: ## %else14 +; AVX2-NEXT: jne LBB3_21 +; AVX2-NEXT: LBB3_5: ## %else14 ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: jne LBB3_11 -; AVX2-NEXT: LBB3_12: ## %else18 +; AVX2-NEXT: jne LBB3_22 +; AVX2-NEXT: LBB3_6: ## %else18 ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: jne LBB3_13 -; AVX2-NEXT: LBB3_14: ## %else22 +; AVX2-NEXT: jne LBB3_23 +; AVX2-NEXT: LBB3_7: ## %else22 ; AVX2-NEXT: testb %al, %al -; AVX2-NEXT: js LBB3_15 -; AVX2-NEXT: LBB3_16: ## %else26 +; AVX2-NEXT: js LBB3_24 +; AVX2-NEXT: LBB3_8: ## %else26 ; AVX2-NEXT: testl $256, %eax ## imm = 0x100 -; AVX2-NEXT: jne LBB3_17 -; AVX2-NEXT: LBB3_18: ## %else30 +; AVX2-NEXT: jne LBB3_25 +; AVX2-NEXT: LBB3_9: ## %else30 ; AVX2-NEXT: testl $512, %eax ## imm = 0x200 -; AVX2-NEXT: jne LBB3_19 -; AVX2-NEXT: LBB3_20: ## %else34 +; AVX2-NEXT: jne LBB3_26 +; AVX2-NEXT: LBB3_10: ## %else34 ; AVX2-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX2-NEXT: jne LBB3_21 -; AVX2-NEXT: LBB3_22: ## %else38 +; AVX2-NEXT: jne LBB3_27 +; AVX2-NEXT: LBB3_11: ## %else38 ; AVX2-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX2-NEXT: jne LBB3_23 -; AVX2-NEXT: LBB3_24: ## %else42 +; AVX2-NEXT: jne LBB3_28 +; AVX2-NEXT: LBB3_12: ## %else42 ; AVX2-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX2-NEXT: jne LBB3_25 -; AVX2-NEXT: LBB3_26: ## %else46 +; AVX2-NEXT: jne LBB3_29 +; AVX2-NEXT: LBB3_13: ## %else46 ; AVX2-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX2-NEXT: jne LBB3_27 -; AVX2-NEXT: LBB3_28: ## %else50 +; AVX2-NEXT: jne LBB3_30 +; AVX2-NEXT: LBB3_14: ## %else50 ; AVX2-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX2-NEXT: jne LBB3_29 -; AVX2-NEXT: LBB3_30: ## %else54 -; AVX2-NEXT: testl $32768, %eax ## imm = 0x8000 ; AVX2-NEXT: jne LBB3_31 -; AVX2-NEXT: LBB3_32: ## %else58 +; AVX2-NEXT: LBB3_15: ## %else54 +; AVX2-NEXT: testl $32768, %eax ## imm = 0x8000 +; AVX2-NEXT: jne LBB3_32 +; AVX2-NEXT: LBB3_16: ## %else58 ; AVX2-NEXT: retq -; AVX2-NEXT: LBB3_1: ## %cond.load +; AVX2-NEXT: LBB3_17: ## %cond.load ; AVX2-NEXT: vmovq (%rdi), %xmm4 ## xmm4 = mem[0],zero ; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm4[0,1],ymm0[2,3,4,5,6,7] ; AVX2-NEXT: addq $8, %rdi ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je LBB3_4 -; AVX2-NEXT: LBB3_3: ## %cond.load1 +; AVX2-NEXT: je LBB3_2 +; AVX2-NEXT: LBB3_18: ## %cond.load1 ; AVX2-NEXT: vmovhps (%rdi), %xmm0, %xmm4 ## xmm4 = xmm0[0,1],mem[0,1] ; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm4[0,1,2,3],ymm0[4,5,6,7] ; AVX2-NEXT: addq $8, %rdi ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je LBB3_6 -; AVX2-NEXT: LBB3_5: ## %cond.load5 +; AVX2-NEXT: je LBB3_3 +; AVX2-NEXT: LBB3_19: ## %cond.load5 ; AVX2-NEXT: vpbroadcastq (%rdi), %ymm4 ; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm4[4,5],ymm0[6,7] ; AVX2-NEXT: addq $8, %rdi ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je LBB3_8 -; AVX2-NEXT: LBB3_7: ## %cond.load9 +; AVX2-NEXT: je LBB3_4 +; AVX2-NEXT: LBB3_20: ## %cond.load9 ; AVX2-NEXT: vpbroadcastq (%rdi), %ymm4 ; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5],ymm4[6,7] ; AVX2-NEXT: addq $8, %rdi ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: je LBB3_10 -; AVX2-NEXT: LBB3_9: ## %cond.load13 +; AVX2-NEXT: je LBB3_5 +; AVX2-NEXT: LBB3_21: ## %cond.load13 ; AVX2-NEXT: vmovq (%rdi), %xmm4 ## xmm4 = mem[0],zero ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm4[0,1],ymm1[2,3,4,5,6,7] ; AVX2-NEXT: addq $8, %rdi ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: je LBB3_12 -; AVX2-NEXT: LBB3_11: ## %cond.load17 +; AVX2-NEXT: je LBB3_6 +; AVX2-NEXT: LBB3_22: ## %cond.load17 ; AVX2-NEXT: vmovhps (%rdi), %xmm1, %xmm4 ## xmm4 = xmm1[0,1],mem[0,1] ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm4[0,1,2,3],ymm1[4,5,6,7] ; AVX2-NEXT: addq $8, %rdi ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: je LBB3_14 -; AVX2-NEXT: LBB3_13: ## %cond.load21 +; AVX2-NEXT: je LBB3_7 +; AVX2-NEXT: LBB3_23: ## %cond.load21 ; AVX2-NEXT: vpbroadcastq (%rdi), %ymm4 ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm4[4,5],ymm1[6,7] ; AVX2-NEXT: addq $8, %rdi ; AVX2-NEXT: testb %al, %al -; AVX2-NEXT: jns LBB3_16 -; AVX2-NEXT: LBB3_15: ## %cond.load25 +; AVX2-NEXT: jns LBB3_8 +; AVX2-NEXT: LBB3_24: ## %cond.load25 ; AVX2-NEXT: vpbroadcastq (%rdi), %ymm4 ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3,4,5],ymm4[6,7] ; AVX2-NEXT: addq $8, %rdi ; AVX2-NEXT: testl $256, %eax ## imm = 0x100 -; AVX2-NEXT: je LBB3_18 -; AVX2-NEXT: LBB3_17: ## %cond.load29 +; AVX2-NEXT: je LBB3_9 +; AVX2-NEXT: LBB3_25: ## %cond.load29 ; AVX2-NEXT: vmovq (%rdi), %xmm4 ## xmm4 = mem[0],zero ; AVX2-NEXT: vpblendd {{.*#+}} ymm2 = ymm4[0,1],ymm2[2,3,4,5,6,7] ; AVX2-NEXT: addq $8, %rdi ; AVX2-NEXT: testl $512, %eax ## imm = 0x200 -; AVX2-NEXT: je LBB3_20 -; AVX2-NEXT: LBB3_19: ## %cond.load33 +; AVX2-NEXT: je LBB3_10 +; AVX2-NEXT: LBB3_26: ## %cond.load33 ; AVX2-NEXT: vmovhps (%rdi), %xmm2, %xmm4 ## xmm4 = xmm2[0,1],mem[0,1] ; AVX2-NEXT: vpblendd {{.*#+}} ymm2 = ymm4[0,1,2,3],ymm2[4,5,6,7] ; AVX2-NEXT: addq $8, %rdi ; AVX2-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX2-NEXT: je LBB3_22 -; AVX2-NEXT: LBB3_21: ## %cond.load37 +; AVX2-NEXT: je LBB3_11 +; AVX2-NEXT: LBB3_27: ## %cond.load37 ; AVX2-NEXT: vpbroadcastq (%rdi), %ymm4 ; AVX2-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm4[4,5],ymm2[6,7] ; AVX2-NEXT: addq $8, %rdi ; AVX2-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX2-NEXT: je LBB3_24 -; AVX2-NEXT: LBB3_23: ## %cond.load41 +; AVX2-NEXT: je LBB3_12 +; AVX2-NEXT: LBB3_28: ## %cond.load41 ; AVX2-NEXT: vpbroadcastq (%rdi), %ymm4 ; AVX2-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3,4,5],ymm4[6,7] ; AVX2-NEXT: addq $8, %rdi ; AVX2-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX2-NEXT: je LBB3_26 -; AVX2-NEXT: LBB3_25: ## %cond.load45 +; AVX2-NEXT: je LBB3_13 +; AVX2-NEXT: LBB3_29: ## %cond.load45 ; AVX2-NEXT: vmovq (%rdi), %xmm4 ## xmm4 = mem[0],zero ; AVX2-NEXT: vpblendd {{.*#+}} ymm3 = ymm4[0,1],ymm3[2,3,4,5,6,7] ; AVX2-NEXT: addq $8, %rdi ; AVX2-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX2-NEXT: je LBB3_28 -; AVX2-NEXT: LBB3_27: ## %cond.load49 +; AVX2-NEXT: je LBB3_14 +; AVX2-NEXT: LBB3_30: ## %cond.load49 ; AVX2-NEXT: vmovhps (%rdi), %xmm3, %xmm4 ## xmm4 = xmm3[0,1],mem[0,1] ; AVX2-NEXT: vpblendd {{.*#+}} ymm3 = ymm4[0,1,2,3],ymm3[4,5,6,7] ; AVX2-NEXT: addq $8, %rdi ; AVX2-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX2-NEXT: je LBB3_30 -; AVX2-NEXT: LBB3_29: ## %cond.load53 +; AVX2-NEXT: je LBB3_15 +; AVX2-NEXT: LBB3_31: ## %cond.load53 ; AVX2-NEXT: vpbroadcastq (%rdi), %ymm4 ; AVX2-NEXT: vpblendd {{.*#+}} ymm3 = ymm3[0,1,2,3],ymm4[4,5],ymm3[6,7] ; AVX2-NEXT: addq $8, %rdi ; AVX2-NEXT: testl $32768, %eax ## imm = 0x8000 -; AVX2-NEXT: je LBB3_32 -; AVX2-NEXT: LBB3_31: ## %cond.load57 +; AVX2-NEXT: je LBB3_16 +; AVX2-NEXT: LBB3_32: ## %cond.load57 ; AVX2-NEXT: vpbroadcastq (%rdi), %ymm4 ; AVX2-NEXT: vpblendd {{.*#+}} ymm3 = ymm3[0,1,2,3,4,5],ymm4[6,7] ; AVX2-NEXT: retq @@ -1063,19 +1063,19 @@ define <2 x float> @expandload_v2f32_v2i1(ptr %base, <2 x float> %src0, <2 x i32 ; SSE2-NEXT: pcmpeqd %xmm1, %xmm2 ; SSE2-NEXT: movmskpd %xmm2, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB4_1 -; SSE2-NEXT: ## %bb.2: ## %else -; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: jne LBB4_3 -; SSE2-NEXT: LBB4_4: ## %else2 +; SSE2-NEXT: ## %bb.1: ## %else +; SSE2-NEXT: testb $2, %al +; SSE2-NEXT: jne LBB4_4 +; SSE2-NEXT: LBB4_2: ## %else2 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB4_1: ## %cond.load +; SSE2-NEXT: LBB4_3: ## %cond.load ; SSE2-NEXT: movss (%rdi), %xmm1 ## xmm1 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB4_4 -; SSE2-NEXT: LBB4_3: ## %cond.load1 +; SSE2-NEXT: je LBB4_2 +; SSE2-NEXT: LBB4_4: ## %cond.load1 ; SSE2-NEXT: movss (%rdi), %xmm1 ## xmm1 = mem[0],zero,zero,zero ; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3] @@ -1089,19 +1089,19 @@ define <2 x float> @expandload_v2f32_v2i1(ptr %base, <2 x float> %src0, <2 x i32 ; SSE42-NEXT: pmovsxdq %xmm2, %xmm1 ; SSE42-NEXT: movmskpd %xmm1, %eax ; SSE42-NEXT: testb $1, %al -; SSE42-NEXT: jne LBB4_1 -; SSE42-NEXT: ## %bb.2: ## %else -; SSE42-NEXT: testb $2, %al ; SSE42-NEXT: jne LBB4_3 -; SSE42-NEXT: LBB4_4: ## %else2 +; SSE42-NEXT: ## %bb.1: ## %else +; SSE42-NEXT: testb $2, %al +; SSE42-NEXT: jne LBB4_4 +; SSE42-NEXT: LBB4_2: ## %else2 ; SSE42-NEXT: retq -; SSE42-NEXT: LBB4_1: ## %cond.load +; SSE42-NEXT: LBB4_3: ## %cond.load ; SSE42-NEXT: movss (%rdi), %xmm1 ## xmm1 = mem[0],zero,zero,zero ; SSE42-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: je LBB4_4 -; SSE42-NEXT: LBB4_3: ## %cond.load1 +; SSE42-NEXT: je LBB4_2 +; SSE42-NEXT: LBB4_4: ## %cond.load1 ; SSE42-NEXT: insertps $16, (%rdi), %xmm0 ## xmm0 = xmm0[0],mem[0],xmm0[2,3] ; SSE42-NEXT: retq ; @@ -1112,19 +1112,19 @@ define <2 x float> @expandload_v2f32_v2i1(ptr %base, <2 x float> %src0, <2 x i32 ; AVX1OR2-NEXT: vpmovsxdq %xmm1, %xmm1 ; AVX1OR2-NEXT: vmovmskpd %xmm1, %eax ; AVX1OR2-NEXT: testb $1, %al -; AVX1OR2-NEXT: jne LBB4_1 -; AVX1OR2-NEXT: ## %bb.2: ## %else -; AVX1OR2-NEXT: testb $2, %al ; AVX1OR2-NEXT: jne LBB4_3 -; AVX1OR2-NEXT: LBB4_4: ## %else2 +; AVX1OR2-NEXT: ## %bb.1: ## %else +; AVX1OR2-NEXT: testb $2, %al +; AVX1OR2-NEXT: jne LBB4_4 +; AVX1OR2-NEXT: LBB4_2: ## %else2 ; AVX1OR2-NEXT: retq -; AVX1OR2-NEXT: LBB4_1: ## %cond.load +; AVX1OR2-NEXT: LBB4_3: ## %cond.load ; AVX1OR2-NEXT: vmovss (%rdi), %xmm1 ## xmm1 = mem[0],zero,zero,zero ; AVX1OR2-NEXT: vmovss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] ; AVX1OR2-NEXT: addq $4, %rdi ; AVX1OR2-NEXT: testb $2, %al -; AVX1OR2-NEXT: je LBB4_4 -; AVX1OR2-NEXT: LBB4_3: ## %cond.load1 +; AVX1OR2-NEXT: je LBB4_2 +; AVX1OR2-NEXT: LBB4_4: ## %cond.load1 ; AVX1OR2-NEXT: vinsertps $16, (%rdi), %xmm0, %xmm0 ## xmm0 = xmm0[0],mem[0],xmm0[2,3] ; AVX1OR2-NEXT: retq ; @@ -1359,105 +1359,105 @@ define <32 x float> @expandload_v32f32_v32i32(ptr %base, <32 x float> %src0, <32 ; SSE2-NEXT: shll $16, %ecx ; SSE2-NEXT: orl %edx, %ecx ; SSE2-NEXT: testb $1, %cl -; SSE2-NEXT: jne LBB8_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB8_34 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %cl -; SSE2-NEXT: jne LBB8_3 -; SSE2-NEXT: LBB8_4: ## %else2 +; SSE2-NEXT: jne LBB8_35 +; SSE2-NEXT: LBB8_2: ## %else2 ; SSE2-NEXT: testb $4, %cl -; SSE2-NEXT: jne LBB8_5 -; SSE2-NEXT: LBB8_6: ## %else6 +; SSE2-NEXT: jne LBB8_36 +; SSE2-NEXT: LBB8_3: ## %else6 ; SSE2-NEXT: testb $8, %cl -; SSE2-NEXT: jne LBB8_7 -; SSE2-NEXT: LBB8_8: ## %else10 +; SSE2-NEXT: jne LBB8_37 +; SSE2-NEXT: LBB8_4: ## %else10 ; SSE2-NEXT: testb $16, %cl -; SSE2-NEXT: jne LBB8_9 -; SSE2-NEXT: LBB8_10: ## %else14 +; SSE2-NEXT: jne LBB8_38 +; SSE2-NEXT: LBB8_5: ## %else14 ; SSE2-NEXT: testb $32, %cl -; SSE2-NEXT: jne LBB8_11 -; SSE2-NEXT: LBB8_12: ## %else18 +; SSE2-NEXT: jne LBB8_39 +; SSE2-NEXT: LBB8_6: ## %else18 ; SSE2-NEXT: testb $64, %cl -; SSE2-NEXT: jne LBB8_13 -; SSE2-NEXT: LBB8_14: ## %else22 +; SSE2-NEXT: jne LBB8_40 +; SSE2-NEXT: LBB8_7: ## %else22 ; SSE2-NEXT: testb %cl, %cl -; SSE2-NEXT: js LBB8_15 -; SSE2-NEXT: LBB8_16: ## %else26 +; SSE2-NEXT: js LBB8_41 +; SSE2-NEXT: LBB8_8: ## %else26 ; SSE2-NEXT: testl $256, %ecx ## imm = 0x100 -; SSE2-NEXT: jne LBB8_17 -; SSE2-NEXT: LBB8_18: ## %else30 +; SSE2-NEXT: jne LBB8_42 +; SSE2-NEXT: LBB8_9: ## %else30 ; SSE2-NEXT: testl $512, %ecx ## imm = 0x200 -; SSE2-NEXT: jne LBB8_19 -; SSE2-NEXT: LBB8_20: ## %else34 +; SSE2-NEXT: jne LBB8_43 +; SSE2-NEXT: LBB8_10: ## %else34 ; SSE2-NEXT: testl $1024, %ecx ## imm = 0x400 -; SSE2-NEXT: jne LBB8_21 -; SSE2-NEXT: LBB8_22: ## %else38 +; SSE2-NEXT: jne LBB8_44 +; SSE2-NEXT: LBB8_11: ## %else38 ; SSE2-NEXT: testl $2048, %ecx ## imm = 0x800 -; SSE2-NEXT: jne LBB8_23 -; SSE2-NEXT: LBB8_24: ## %else42 +; SSE2-NEXT: jne LBB8_45 +; SSE2-NEXT: LBB8_12: ## %else42 ; SSE2-NEXT: testl $4096, %ecx ## imm = 0x1000 -; SSE2-NEXT: jne LBB8_25 -; SSE2-NEXT: LBB8_26: ## %else46 +; SSE2-NEXT: jne LBB8_46 +; SSE2-NEXT: LBB8_13: ## %else46 ; SSE2-NEXT: testl $8192, %ecx ## imm = 0x2000 -; SSE2-NEXT: jne LBB8_27 -; SSE2-NEXT: LBB8_28: ## %else50 +; SSE2-NEXT: jne LBB8_47 +; SSE2-NEXT: LBB8_14: ## %else50 ; SSE2-NEXT: testl $16384, %ecx ## imm = 0x4000 -; SSE2-NEXT: jne LBB8_29 -; SSE2-NEXT: LBB8_30: ## %else54 +; SSE2-NEXT: jne LBB8_48 +; SSE2-NEXT: LBB8_15: ## %else54 ; SSE2-NEXT: testw %cx, %cx -; SSE2-NEXT: js LBB8_31 -; SSE2-NEXT: LBB8_32: ## %else58 +; SSE2-NEXT: js LBB8_49 +; SSE2-NEXT: LBB8_16: ## %else58 ; SSE2-NEXT: testl $65536, %ecx ## imm = 0x10000 -; SSE2-NEXT: jne LBB8_33 -; SSE2-NEXT: LBB8_34: ## %else62 +; SSE2-NEXT: jne LBB8_50 +; SSE2-NEXT: LBB8_17: ## %else62 ; SSE2-NEXT: testl $131072, %ecx ## imm = 0x20000 -; SSE2-NEXT: jne LBB8_35 -; SSE2-NEXT: LBB8_36: ## %else66 +; SSE2-NEXT: jne LBB8_51 +; SSE2-NEXT: LBB8_18: ## %else66 ; SSE2-NEXT: testl $262144, %ecx ## imm = 0x40000 -; SSE2-NEXT: jne LBB8_37 -; SSE2-NEXT: LBB8_38: ## %else70 +; SSE2-NEXT: jne LBB8_52 +; SSE2-NEXT: LBB8_19: ## %else70 ; SSE2-NEXT: testl $524288, %ecx ## imm = 0x80000 -; SSE2-NEXT: jne LBB8_39 -; SSE2-NEXT: LBB8_40: ## %else74 +; SSE2-NEXT: jne LBB8_53 +; SSE2-NEXT: LBB8_20: ## %else74 ; SSE2-NEXT: testl $1048576, %ecx ## imm = 0x100000 -; SSE2-NEXT: jne LBB8_41 -; SSE2-NEXT: LBB8_42: ## %else78 +; SSE2-NEXT: jne LBB8_54 +; SSE2-NEXT: LBB8_21: ## %else78 ; SSE2-NEXT: testl $2097152, %ecx ## imm = 0x200000 -; SSE2-NEXT: jne LBB8_43 -; SSE2-NEXT: LBB8_44: ## %else82 +; SSE2-NEXT: jne LBB8_55 +; SSE2-NEXT: LBB8_22: ## %else82 ; SSE2-NEXT: testl $4194304, %ecx ## imm = 0x400000 -; SSE2-NEXT: jne LBB8_45 -; SSE2-NEXT: LBB8_46: ## %else86 +; SSE2-NEXT: jne LBB8_56 +; SSE2-NEXT: LBB8_23: ## %else86 ; SSE2-NEXT: testl $8388608, %ecx ## imm = 0x800000 -; SSE2-NEXT: jne LBB8_47 -; SSE2-NEXT: LBB8_48: ## %else90 +; SSE2-NEXT: jne LBB8_57 +; SSE2-NEXT: LBB8_24: ## %else90 ; SSE2-NEXT: testl $16777216, %ecx ## imm = 0x1000000 -; SSE2-NEXT: jne LBB8_49 -; SSE2-NEXT: LBB8_50: ## %else94 +; SSE2-NEXT: jne LBB8_58 +; SSE2-NEXT: LBB8_25: ## %else94 ; SSE2-NEXT: testl $33554432, %ecx ## imm = 0x2000000 -; SSE2-NEXT: jne LBB8_51 -; SSE2-NEXT: LBB8_52: ## %else98 +; SSE2-NEXT: jne LBB8_59 +; SSE2-NEXT: LBB8_26: ## %else98 ; SSE2-NEXT: testl $67108864, %ecx ## imm = 0x4000000 -; SSE2-NEXT: jne LBB8_53 -; SSE2-NEXT: LBB8_54: ## %else102 +; SSE2-NEXT: jne LBB8_60 +; SSE2-NEXT: LBB8_27: ## %else102 ; SSE2-NEXT: testl $134217728, %ecx ## imm = 0x8000000 -; SSE2-NEXT: jne LBB8_55 -; SSE2-NEXT: LBB8_56: ## %else106 +; SSE2-NEXT: jne LBB8_61 +; SSE2-NEXT: LBB8_28: ## %else106 ; SSE2-NEXT: testl $268435456, %ecx ## imm = 0x10000000 -; SSE2-NEXT: jne LBB8_57 -; SSE2-NEXT: LBB8_58: ## %else110 +; SSE2-NEXT: jne LBB8_62 +; SSE2-NEXT: LBB8_29: ## %else110 ; SSE2-NEXT: testl $536870912, %ecx ## imm = 0x20000000 -; SSE2-NEXT: jne LBB8_59 -; SSE2-NEXT: LBB8_60: ## %else114 +; SSE2-NEXT: jne LBB8_63 +; SSE2-NEXT: LBB8_30: ## %else114 ; SSE2-NEXT: testl $1073741824, %ecx ## imm = 0x40000000 -; SSE2-NEXT: jne LBB8_61 -; SSE2-NEXT: LBB8_62: ## %else118 +; SSE2-NEXT: jne LBB8_64 +; SSE2-NEXT: LBB8_31: ## %else118 ; SSE2-NEXT: testl $-2147483648, %ecx ## imm = 0x80000000 -; SSE2-NEXT: je LBB8_64 -; SSE2-NEXT: LBB8_63: ## %cond.load121 +; SSE2-NEXT: je LBB8_33 +; SSE2-NEXT: LBB8_32: ## %cond.load121 ; SSE2-NEXT: movss (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,1],xmm7[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm7 = xmm7[0,1],xmm8[2,0] -; SSE2-NEXT: LBB8_64: ## %else122 +; SSE2-NEXT: LBB8_33: ## %else122 ; SSE2-NEXT: movaps %xmm0, (%rax) ; SSE2-NEXT: movaps %xmm1, 16(%rax) ; SSE2-NEXT: movaps %xmm2, 32(%rax) @@ -1467,224 +1467,224 @@ define <32 x float> @expandload_v32f32_v32i32(ptr %base, <32 x float> %src0, <32 ; SSE2-NEXT: movaps %xmm6, 96(%rax) ; SSE2-NEXT: movaps %xmm7, 112(%rax) ; SSE2-NEXT: retq -; SSE2-NEXT: LBB8_1: ## %cond.load +; SSE2-NEXT: LBB8_34: ## %cond.load ; SSE2-NEXT: movss (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm8[0],xmm0[1,2,3] ; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: testb $2, %cl -; SSE2-NEXT: je LBB8_4 -; SSE2-NEXT: LBB8_3: ## %cond.load1 +; SSE2-NEXT: je LBB8_2 +; SSE2-NEXT: LBB8_35: ## %cond.load1 ; SSE2-NEXT: movss (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movlhps {{.*#+}} xmm8 = xmm8[0],xmm0[0] ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[2,0],xmm0[2,3] ; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: movaps %xmm8, %xmm0 ; SSE2-NEXT: testb $4, %cl -; SSE2-NEXT: je LBB8_6 -; SSE2-NEXT: LBB8_5: ## %cond.load5 +; SSE2-NEXT: je LBB8_3 +; SSE2-NEXT: LBB8_36: ## %cond.load5 ; SSE2-NEXT: movss (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm0[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm8[0,2] ; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: testb $8, %cl -; SSE2-NEXT: je LBB8_8 -; SSE2-NEXT: LBB8_7: ## %cond.load9 +; SSE2-NEXT: je LBB8_4 +; SSE2-NEXT: LBB8_37: ## %cond.load9 ; SSE2-NEXT: movss (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,1],xmm0[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm8[2,0] ; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: testb $16, %cl -; SSE2-NEXT: je LBB8_10 -; SSE2-NEXT: LBB8_9: ## %cond.load13 +; SSE2-NEXT: je LBB8_5 +; SSE2-NEXT: LBB8_38: ## %cond.load13 ; SSE2-NEXT: movss (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm8[0],xmm1[1,2,3] ; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: testb $32, %cl -; SSE2-NEXT: je LBB8_12 -; SSE2-NEXT: LBB8_11: ## %cond.load17 +; SSE2-NEXT: je LBB8_6 +; SSE2-NEXT: LBB8_39: ## %cond.load17 ; SSE2-NEXT: movss (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movlhps {{.*#+}} xmm8 = xmm8[0],xmm1[0] ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[2,0],xmm1[2,3] ; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: movaps %xmm8, %xmm1 ; SSE2-NEXT: testb $64, %cl -; SSE2-NEXT: je LBB8_14 -; SSE2-NEXT: LBB8_13: ## %cond.load21 +; SSE2-NEXT: je LBB8_7 +; SSE2-NEXT: LBB8_40: ## %cond.load21 ; SSE2-NEXT: movss (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm1[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm8[0,2] ; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: testb %cl, %cl -; SSE2-NEXT: jns LBB8_16 -; SSE2-NEXT: LBB8_15: ## %cond.load25 +; SSE2-NEXT: jns LBB8_8 +; SSE2-NEXT: LBB8_41: ## %cond.load25 ; SSE2-NEXT: movss (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,1],xmm1[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm8[2,0] ; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: testl $256, %ecx ## imm = 0x100 -; SSE2-NEXT: je LBB8_18 -; SSE2-NEXT: LBB8_17: ## %cond.load29 +; SSE2-NEXT: je LBB8_9 +; SSE2-NEXT: LBB8_42: ## %cond.load29 ; SSE2-NEXT: movss (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm8[0],xmm2[1,2,3] ; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: testl $512, %ecx ## imm = 0x200 -; SSE2-NEXT: je LBB8_20 -; SSE2-NEXT: LBB8_19: ## %cond.load33 +; SSE2-NEXT: je LBB8_10 +; SSE2-NEXT: LBB8_43: ## %cond.load33 ; SSE2-NEXT: movss (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movlhps {{.*#+}} xmm8 = xmm8[0],xmm2[0] ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[2,0],xmm2[2,3] ; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: movaps %xmm8, %xmm2 ; SSE2-NEXT: testl $1024, %ecx ## imm = 0x400 -; SSE2-NEXT: je LBB8_22 -; SSE2-NEXT: LBB8_21: ## %cond.load37 +; SSE2-NEXT: je LBB8_11 +; SSE2-NEXT: LBB8_44: ## %cond.load37 ; SSE2-NEXT: movss (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm2[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm8[0,2] ; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: testl $2048, %ecx ## imm = 0x800 -; SSE2-NEXT: je LBB8_24 -; SSE2-NEXT: LBB8_23: ## %cond.load41 +; SSE2-NEXT: je LBB8_12 +; SSE2-NEXT: LBB8_45: ## %cond.load41 ; SSE2-NEXT: movss (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,1],xmm2[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm8[2,0] ; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: testl $4096, %ecx ## imm = 0x1000 -; SSE2-NEXT: je LBB8_26 -; SSE2-NEXT: LBB8_25: ## %cond.load45 +; SSE2-NEXT: je LBB8_13 +; SSE2-NEXT: LBB8_46: ## %cond.load45 ; SSE2-NEXT: movss (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm3 = xmm8[0],xmm3[1,2,3] ; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: testl $8192, %ecx ## imm = 0x2000 -; SSE2-NEXT: je LBB8_28 -; SSE2-NEXT: LBB8_27: ## %cond.load49 +; SSE2-NEXT: je LBB8_14 +; SSE2-NEXT: LBB8_47: ## %cond.load49 ; SSE2-NEXT: movss (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movlhps {{.*#+}} xmm8 = xmm8[0],xmm3[0] ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[2,0],xmm3[2,3] ; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: movaps %xmm8, %xmm3 ; SSE2-NEXT: testl $16384, %ecx ## imm = 0x4000 -; SSE2-NEXT: je LBB8_30 -; SSE2-NEXT: LBB8_29: ## %cond.load53 +; SSE2-NEXT: je LBB8_15 +; SSE2-NEXT: LBB8_48: ## %cond.load53 ; SSE2-NEXT: movss (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm3[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,1],xmm8[0,2] ; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: testw %cx, %cx -; SSE2-NEXT: jns LBB8_32 -; SSE2-NEXT: LBB8_31: ## %cond.load57 +; SSE2-NEXT: jns LBB8_16 +; SSE2-NEXT: LBB8_49: ## %cond.load57 ; SSE2-NEXT: movss (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,1],xmm3[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,1],xmm8[2,0] ; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: testl $65536, %ecx ## imm = 0x10000 -; SSE2-NEXT: je LBB8_34 -; SSE2-NEXT: LBB8_33: ## %cond.load61 +; SSE2-NEXT: je LBB8_17 +; SSE2-NEXT: LBB8_50: ## %cond.load61 ; SSE2-NEXT: movss (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm4 = xmm8[0],xmm4[1,2,3] ; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: testl $131072, %ecx ## imm = 0x20000 -; SSE2-NEXT: je LBB8_36 -; SSE2-NEXT: LBB8_35: ## %cond.load65 +; SSE2-NEXT: je LBB8_18 +; SSE2-NEXT: LBB8_51: ## %cond.load65 ; SSE2-NEXT: movss (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movlhps {{.*#+}} xmm8 = xmm8[0],xmm4[0] ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[2,0],xmm4[2,3] ; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: movaps %xmm8, %xmm4 ; SSE2-NEXT: testl $262144, %ecx ## imm = 0x40000 -; SSE2-NEXT: je LBB8_38 -; SSE2-NEXT: LBB8_37: ## %cond.load69 +; SSE2-NEXT: je LBB8_19 +; SSE2-NEXT: LBB8_52: ## %cond.load69 ; SSE2-NEXT: movss (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm4[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,1],xmm8[0,2] ; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: testl $524288, %ecx ## imm = 0x80000 -; SSE2-NEXT: je LBB8_40 -; SSE2-NEXT: LBB8_39: ## %cond.load73 +; SSE2-NEXT: je LBB8_20 +; SSE2-NEXT: LBB8_53: ## %cond.load73 ; SSE2-NEXT: movss (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,1],xmm4[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,1],xmm8[2,0] ; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: testl $1048576, %ecx ## imm = 0x100000 -; SSE2-NEXT: je LBB8_42 -; SSE2-NEXT: LBB8_41: ## %cond.load77 +; SSE2-NEXT: je LBB8_21 +; SSE2-NEXT: LBB8_54: ## %cond.load77 ; SSE2-NEXT: movss (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm5 = xmm8[0],xmm5[1,2,3] ; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: testl $2097152, %ecx ## imm = 0x200000 -; SSE2-NEXT: je LBB8_44 -; SSE2-NEXT: LBB8_43: ## %cond.load81 +; SSE2-NEXT: je LBB8_22 +; SSE2-NEXT: LBB8_55: ## %cond.load81 ; SSE2-NEXT: movss (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movlhps {{.*#+}} xmm8 = xmm8[0],xmm5[0] ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[2,0],xmm5[2,3] ; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: movaps %xmm8, %xmm5 ; SSE2-NEXT: testl $4194304, %ecx ## imm = 0x400000 -; SSE2-NEXT: je LBB8_46 -; SSE2-NEXT: LBB8_45: ## %cond.load85 +; SSE2-NEXT: je LBB8_23 +; SSE2-NEXT: LBB8_56: ## %cond.load85 ; SSE2-NEXT: movss (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm5[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,1],xmm8[0,2] ; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: testl $8388608, %ecx ## imm = 0x800000 -; SSE2-NEXT: je LBB8_48 -; SSE2-NEXT: LBB8_47: ## %cond.load89 +; SSE2-NEXT: je LBB8_24 +; SSE2-NEXT: LBB8_57: ## %cond.load89 ; SSE2-NEXT: movss (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,1],xmm5[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,1],xmm8[2,0] ; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: testl $16777216, %ecx ## imm = 0x1000000 -; SSE2-NEXT: je LBB8_50 -; SSE2-NEXT: LBB8_49: ## %cond.load93 +; SSE2-NEXT: je LBB8_25 +; SSE2-NEXT: LBB8_58: ## %cond.load93 ; SSE2-NEXT: movss (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm6 = xmm8[0],xmm6[1,2,3] ; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: testl $33554432, %ecx ## imm = 0x2000000 -; SSE2-NEXT: je LBB8_52 -; SSE2-NEXT: LBB8_51: ## %cond.load97 +; SSE2-NEXT: je LBB8_26 +; SSE2-NEXT: LBB8_59: ## %cond.load97 ; SSE2-NEXT: movss (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movlhps {{.*#+}} xmm8 = xmm8[0],xmm6[0] ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[2,0],xmm6[2,3] ; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: movaps %xmm8, %xmm6 ; SSE2-NEXT: testl $67108864, %ecx ## imm = 0x4000000 -; SSE2-NEXT: je LBB8_54 -; SSE2-NEXT: LBB8_53: ## %cond.load101 +; SSE2-NEXT: je LBB8_27 +; SSE2-NEXT: LBB8_60: ## %cond.load101 ; SSE2-NEXT: movss (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm6[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm6 = xmm6[0,1],xmm8[0,2] ; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: testl $134217728, %ecx ## imm = 0x8000000 -; SSE2-NEXT: je LBB8_56 -; SSE2-NEXT: LBB8_55: ## %cond.load105 +; SSE2-NEXT: je LBB8_28 +; SSE2-NEXT: LBB8_61: ## %cond.load105 ; SSE2-NEXT: movss (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,1],xmm6[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm6 = xmm6[0,1],xmm8[2,0] ; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: testl $268435456, %ecx ## imm = 0x10000000 -; SSE2-NEXT: je LBB8_58 -; SSE2-NEXT: LBB8_57: ## %cond.load109 +; SSE2-NEXT: je LBB8_29 +; SSE2-NEXT: LBB8_62: ## %cond.load109 ; SSE2-NEXT: movss (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm7 = xmm8[0],xmm7[1,2,3] ; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: testl $536870912, %ecx ## imm = 0x20000000 -; SSE2-NEXT: je LBB8_60 -; SSE2-NEXT: LBB8_59: ## %cond.load113 +; SSE2-NEXT: je LBB8_30 +; SSE2-NEXT: LBB8_63: ## %cond.load113 ; SSE2-NEXT: movss (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movlhps {{.*#+}} xmm8 = xmm8[0],xmm7[0] ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[2,0],xmm7[2,3] ; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: movaps %xmm8, %xmm7 ; SSE2-NEXT: testl $1073741824, %ecx ## imm = 0x40000000 -; SSE2-NEXT: je LBB8_62 -; SSE2-NEXT: LBB8_61: ## %cond.load117 +; SSE2-NEXT: je LBB8_31 +; SSE2-NEXT: LBB8_64: ## %cond.load117 ; SSE2-NEXT: movss (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm7[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm7 = xmm7[0,1],xmm8[0,2] ; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: testl $-2147483648, %ecx ## imm = 0x80000000 -; SSE2-NEXT: jne LBB8_63 -; SSE2-NEXT: jmp LBB8_64 +; SSE2-NEXT: jne LBB8_32 +; SSE2-NEXT: jmp LBB8_33 ; ; SSE42-LABEL: expandload_v32f32_v32i32: ; SSE42: ## %bb.0: @@ -1716,103 +1716,103 @@ define <32 x float> @expandload_v32f32_v32i32(ptr %base, <32 x float> %src0, <32 ; SSE42-NEXT: shll $16, %ecx ; SSE42-NEXT: orl %edx, %ecx ; SSE42-NEXT: testb $1, %cl -; SSE42-NEXT: jne LBB8_1 -; SSE42-NEXT: ## %bb.2: ## %else +; SSE42-NEXT: jne LBB8_34 +; SSE42-NEXT: ## %bb.1: ## %else ; SSE42-NEXT: testb $2, %cl -; SSE42-NEXT: jne LBB8_3 -; SSE42-NEXT: LBB8_4: ## %else2 +; SSE42-NEXT: jne LBB8_35 +; SSE42-NEXT: LBB8_2: ## %else2 ; SSE42-NEXT: testb $4, %cl -; SSE42-NEXT: jne LBB8_5 -; SSE42-NEXT: LBB8_6: ## %else6 +; SSE42-NEXT: jne LBB8_36 +; SSE42-NEXT: LBB8_3: ## %else6 ; SSE42-NEXT: testb $8, %cl -; SSE42-NEXT: jne LBB8_7 -; SSE42-NEXT: LBB8_8: ## %else10 +; SSE42-NEXT: jne LBB8_37 +; SSE42-NEXT: LBB8_4: ## %else10 ; SSE42-NEXT: testb $16, %cl -; SSE42-NEXT: jne LBB8_9 -; SSE42-NEXT: LBB8_10: ## %else14 +; SSE42-NEXT: jne LBB8_38 +; SSE42-NEXT: LBB8_5: ## %else14 ; SSE42-NEXT: testb $32, %cl -; SSE42-NEXT: jne LBB8_11 -; SSE42-NEXT: LBB8_12: ## %else18 +; SSE42-NEXT: jne LBB8_39 +; SSE42-NEXT: LBB8_6: ## %else18 ; SSE42-NEXT: testb $64, %cl -; SSE42-NEXT: jne LBB8_13 -; SSE42-NEXT: LBB8_14: ## %else22 +; SSE42-NEXT: jne LBB8_40 +; SSE42-NEXT: LBB8_7: ## %else22 ; SSE42-NEXT: testb %cl, %cl -; SSE42-NEXT: js LBB8_15 -; SSE42-NEXT: LBB8_16: ## %else26 +; SSE42-NEXT: js LBB8_41 +; SSE42-NEXT: LBB8_8: ## %else26 ; SSE42-NEXT: testl $256, %ecx ## imm = 0x100 -; SSE42-NEXT: jne LBB8_17 -; SSE42-NEXT: LBB8_18: ## %else30 +; SSE42-NEXT: jne LBB8_42 +; SSE42-NEXT: LBB8_9: ## %else30 ; SSE42-NEXT: testl $512, %ecx ## imm = 0x200 -; SSE42-NEXT: jne LBB8_19 -; SSE42-NEXT: LBB8_20: ## %else34 +; SSE42-NEXT: jne LBB8_43 +; SSE42-NEXT: LBB8_10: ## %else34 ; SSE42-NEXT: testl $1024, %ecx ## imm = 0x400 -; SSE42-NEXT: jne LBB8_21 -; SSE42-NEXT: LBB8_22: ## %else38 +; SSE42-NEXT: jne LBB8_44 +; SSE42-NEXT: LBB8_11: ## %else38 ; SSE42-NEXT: testl $2048, %ecx ## imm = 0x800 -; SSE42-NEXT: jne LBB8_23 -; SSE42-NEXT: LBB8_24: ## %else42 +; SSE42-NEXT: jne LBB8_45 +; SSE42-NEXT: LBB8_12: ## %else42 ; SSE42-NEXT: testl $4096, %ecx ## imm = 0x1000 -; SSE42-NEXT: jne LBB8_25 -; SSE42-NEXT: LBB8_26: ## %else46 +; SSE42-NEXT: jne LBB8_46 +; SSE42-NEXT: LBB8_13: ## %else46 ; SSE42-NEXT: testl $8192, %ecx ## imm = 0x2000 -; SSE42-NEXT: jne LBB8_27 -; SSE42-NEXT: LBB8_28: ## %else50 +; SSE42-NEXT: jne LBB8_47 +; SSE42-NEXT: LBB8_14: ## %else50 ; SSE42-NEXT: testl $16384, %ecx ## imm = 0x4000 -; SSE42-NEXT: jne LBB8_29 -; SSE42-NEXT: LBB8_30: ## %else54 +; SSE42-NEXT: jne LBB8_48 +; SSE42-NEXT: LBB8_15: ## %else54 ; SSE42-NEXT: testw %cx, %cx -; SSE42-NEXT: js LBB8_31 -; SSE42-NEXT: LBB8_32: ## %else58 +; SSE42-NEXT: js LBB8_49 +; SSE42-NEXT: LBB8_16: ## %else58 ; SSE42-NEXT: testl $65536, %ecx ## imm = 0x10000 -; SSE42-NEXT: jne LBB8_33 -; SSE42-NEXT: LBB8_34: ## %else62 +; SSE42-NEXT: jne LBB8_50 +; SSE42-NEXT: LBB8_17: ## %else62 ; SSE42-NEXT: testl $131072, %ecx ## imm = 0x20000 -; SSE42-NEXT: jne LBB8_35 -; SSE42-NEXT: LBB8_36: ## %else66 +; SSE42-NEXT: jne LBB8_51 +; SSE42-NEXT: LBB8_18: ## %else66 ; SSE42-NEXT: testl $262144, %ecx ## imm = 0x40000 -; SSE42-NEXT: jne LBB8_37 -; SSE42-NEXT: LBB8_38: ## %else70 +; SSE42-NEXT: jne LBB8_52 +; SSE42-NEXT: LBB8_19: ## %else70 ; SSE42-NEXT: testl $524288, %ecx ## imm = 0x80000 -; SSE42-NEXT: jne LBB8_39 -; SSE42-NEXT: LBB8_40: ## %else74 +; SSE42-NEXT: jne LBB8_53 +; SSE42-NEXT: LBB8_20: ## %else74 ; SSE42-NEXT: testl $1048576, %ecx ## imm = 0x100000 -; SSE42-NEXT: jne LBB8_41 -; SSE42-NEXT: LBB8_42: ## %else78 +; SSE42-NEXT: jne LBB8_54 +; SSE42-NEXT: LBB8_21: ## %else78 ; SSE42-NEXT: testl $2097152, %ecx ## imm = 0x200000 -; SSE42-NEXT: jne LBB8_43 -; SSE42-NEXT: LBB8_44: ## %else82 +; SSE42-NEXT: jne LBB8_55 +; SSE42-NEXT: LBB8_22: ## %else82 ; SSE42-NEXT: testl $4194304, %ecx ## imm = 0x400000 -; SSE42-NEXT: jne LBB8_45 -; SSE42-NEXT: LBB8_46: ## %else86 +; SSE42-NEXT: jne LBB8_56 +; SSE42-NEXT: LBB8_23: ## %else86 ; SSE42-NEXT: testl $8388608, %ecx ## imm = 0x800000 -; SSE42-NEXT: jne LBB8_47 -; SSE42-NEXT: LBB8_48: ## %else90 +; SSE42-NEXT: jne LBB8_57 +; SSE42-NEXT: LBB8_24: ## %else90 ; SSE42-NEXT: testl $16777216, %ecx ## imm = 0x1000000 -; SSE42-NEXT: jne LBB8_49 -; SSE42-NEXT: LBB8_50: ## %else94 +; SSE42-NEXT: jne LBB8_58 +; SSE42-NEXT: LBB8_25: ## %else94 ; SSE42-NEXT: testl $33554432, %ecx ## imm = 0x2000000 -; SSE42-NEXT: jne LBB8_51 -; SSE42-NEXT: LBB8_52: ## %else98 +; SSE42-NEXT: jne LBB8_59 +; SSE42-NEXT: LBB8_26: ## %else98 ; SSE42-NEXT: testl $67108864, %ecx ## imm = 0x4000000 -; SSE42-NEXT: jne LBB8_53 -; SSE42-NEXT: LBB8_54: ## %else102 +; SSE42-NEXT: jne LBB8_60 +; SSE42-NEXT: LBB8_27: ## %else102 ; SSE42-NEXT: testl $134217728, %ecx ## imm = 0x8000000 -; SSE42-NEXT: jne LBB8_55 -; SSE42-NEXT: LBB8_56: ## %else106 +; SSE42-NEXT: jne LBB8_61 +; SSE42-NEXT: LBB8_28: ## %else106 ; SSE42-NEXT: testl $268435456, %ecx ## imm = 0x10000000 -; SSE42-NEXT: jne LBB8_57 -; SSE42-NEXT: LBB8_58: ## %else110 +; SSE42-NEXT: jne LBB8_62 +; SSE42-NEXT: LBB8_29: ## %else110 ; SSE42-NEXT: testl $536870912, %ecx ## imm = 0x20000000 -; SSE42-NEXT: jne LBB8_59 -; SSE42-NEXT: LBB8_60: ## %else114 +; SSE42-NEXT: jne LBB8_63 +; SSE42-NEXT: LBB8_30: ## %else114 ; SSE42-NEXT: testl $1073741824, %ecx ## imm = 0x40000000 -; SSE42-NEXT: jne LBB8_61 -; SSE42-NEXT: LBB8_62: ## %else118 +; SSE42-NEXT: jne LBB8_64 +; SSE42-NEXT: LBB8_31: ## %else118 ; SSE42-NEXT: testl $-2147483648, %ecx ## imm = 0x80000000 -; SSE42-NEXT: je LBB8_64 -; SSE42-NEXT: LBB8_63: ## %cond.load121 +; SSE42-NEXT: je LBB8_33 +; SSE42-NEXT: LBB8_32: ## %cond.load121 ; SSE42-NEXT: insertps $48, (%rsi), %xmm7 ## xmm7 = xmm7[0,1,2],mem[0] -; SSE42-NEXT: LBB8_64: ## %else122 +; SSE42-NEXT: LBB8_33: ## %else122 ; SSE42-NEXT: movaps %xmm0, (%rax) ; SSE42-NEXT: movaps %xmm1, 16(%rax) ; SSE42-NEXT: movaps %xmm2, 32(%rax) @@ -1822,170 +1822,170 @@ define <32 x float> @expandload_v32f32_v32i32(ptr %base, <32 x float> %src0, <32 ; SSE42-NEXT: movaps %xmm6, 96(%rax) ; SSE42-NEXT: movaps %xmm7, 112(%rax) ; SSE42-NEXT: retq -; SSE42-NEXT: LBB8_1: ## %cond.load +; SSE42-NEXT: LBB8_34: ## %cond.load ; SSE42-NEXT: movd (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE42-NEXT: pblendw {{.*#+}} xmm0 = xmm8[0,1],xmm0[2,3,4,5,6,7] ; SSE42-NEXT: addq $4, %rsi ; SSE42-NEXT: testb $2, %cl -; SSE42-NEXT: je LBB8_4 -; SSE42-NEXT: LBB8_3: ## %cond.load1 +; SSE42-NEXT: je LBB8_2 +; SSE42-NEXT: LBB8_35: ## %cond.load1 ; SSE42-NEXT: insertps $16, (%rsi), %xmm0 ## xmm0 = xmm0[0],mem[0],xmm0[2,3] ; SSE42-NEXT: addq $4, %rsi ; SSE42-NEXT: testb $4, %cl -; SSE42-NEXT: je LBB8_6 -; SSE42-NEXT: LBB8_5: ## %cond.load5 +; SSE42-NEXT: je LBB8_3 +; SSE42-NEXT: LBB8_36: ## %cond.load5 ; SSE42-NEXT: insertps $32, (%rsi), %xmm0 ## xmm0 = xmm0[0,1],mem[0],xmm0[3] ; SSE42-NEXT: addq $4, %rsi ; SSE42-NEXT: testb $8, %cl -; SSE42-NEXT: je LBB8_8 -; SSE42-NEXT: LBB8_7: ## %cond.load9 +; SSE42-NEXT: je LBB8_4 +; SSE42-NEXT: LBB8_37: ## %cond.load9 ; SSE42-NEXT: insertps $48, (%rsi), %xmm0 ## xmm0 = xmm0[0,1,2],mem[0] ; SSE42-NEXT: addq $4, %rsi ; SSE42-NEXT: testb $16, %cl -; SSE42-NEXT: je LBB8_10 -; SSE42-NEXT: LBB8_9: ## %cond.load13 +; SSE42-NEXT: je LBB8_5 +; SSE42-NEXT: LBB8_38: ## %cond.load13 ; SSE42-NEXT: movd (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE42-NEXT: pblendw {{.*#+}} xmm1 = xmm8[0,1],xmm1[2,3,4,5,6,7] ; SSE42-NEXT: addq $4, %rsi ; SSE42-NEXT: testb $32, %cl -; SSE42-NEXT: je LBB8_12 -; SSE42-NEXT: LBB8_11: ## %cond.load17 +; SSE42-NEXT: je LBB8_6 +; SSE42-NEXT: LBB8_39: ## %cond.load17 ; SSE42-NEXT: insertps $16, (%rsi), %xmm1 ## xmm1 = xmm1[0],mem[0],xmm1[2,3] ; SSE42-NEXT: addq $4, %rsi ; SSE42-NEXT: testb $64, %cl -; SSE42-NEXT: je LBB8_14 -; SSE42-NEXT: LBB8_13: ## %cond.load21 +; SSE42-NEXT: je LBB8_7 +; SSE42-NEXT: LBB8_40: ## %cond.load21 ; SSE42-NEXT: insertps $32, (%rsi), %xmm1 ## xmm1 = xmm1[0,1],mem[0],xmm1[3] ; SSE42-NEXT: addq $4, %rsi ; SSE42-NEXT: testb %cl, %cl -; SSE42-NEXT: jns LBB8_16 -; SSE42-NEXT: LBB8_15: ## %cond.load25 +; SSE42-NEXT: jns LBB8_8 +; SSE42-NEXT: LBB8_41: ## %cond.load25 ; SSE42-NEXT: insertps $48, (%rsi), %xmm1 ## xmm1 = xmm1[0,1,2],mem[0] ; SSE42-NEXT: addq $4, %rsi ; SSE42-NEXT: testl $256, %ecx ## imm = 0x100 -; SSE42-NEXT: je LBB8_18 -; SSE42-NEXT: LBB8_17: ## %cond.load29 +; SSE42-NEXT: je LBB8_9 +; SSE42-NEXT: LBB8_42: ## %cond.load29 ; SSE42-NEXT: movd (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE42-NEXT: pblendw {{.*#+}} xmm2 = xmm8[0,1],xmm2[2,3,4,5,6,7] ; SSE42-NEXT: addq $4, %rsi ; SSE42-NEXT: testl $512, %ecx ## imm = 0x200 -; SSE42-NEXT: je LBB8_20 -; SSE42-NEXT: LBB8_19: ## %cond.load33 +; SSE42-NEXT: je LBB8_10 +; SSE42-NEXT: LBB8_43: ## %cond.load33 ; SSE42-NEXT: insertps $16, (%rsi), %xmm2 ## xmm2 = xmm2[0],mem[0],xmm2[2,3] ; SSE42-NEXT: addq $4, %rsi ; SSE42-NEXT: testl $1024, %ecx ## imm = 0x400 -; SSE42-NEXT: je LBB8_22 -; SSE42-NEXT: LBB8_21: ## %cond.load37 +; SSE42-NEXT: je LBB8_11 +; SSE42-NEXT: LBB8_44: ## %cond.load37 ; SSE42-NEXT: insertps $32, (%rsi), %xmm2 ## xmm2 = xmm2[0,1],mem[0],xmm2[3] ; SSE42-NEXT: addq $4, %rsi ; SSE42-NEXT: testl $2048, %ecx ## imm = 0x800 -; SSE42-NEXT: je LBB8_24 -; SSE42-NEXT: LBB8_23: ## %cond.load41 +; SSE42-NEXT: je LBB8_12 +; SSE42-NEXT: LBB8_45: ## %cond.load41 ; SSE42-NEXT: insertps $48, (%rsi), %xmm2 ## xmm2 = xmm2[0,1,2],mem[0] ; SSE42-NEXT: addq $4, %rsi ; SSE42-NEXT: testl $4096, %ecx ## imm = 0x1000 -; SSE42-NEXT: je LBB8_26 -; SSE42-NEXT: LBB8_25: ## %cond.load45 +; SSE42-NEXT: je LBB8_13 +; SSE42-NEXT: LBB8_46: ## %cond.load45 ; SSE42-NEXT: movd (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE42-NEXT: pblendw {{.*#+}} xmm3 = xmm8[0,1],xmm3[2,3,4,5,6,7] ; SSE42-NEXT: addq $4, %rsi ; SSE42-NEXT: testl $8192, %ecx ## imm = 0x2000 -; SSE42-NEXT: je LBB8_28 -; SSE42-NEXT: LBB8_27: ## %cond.load49 +; SSE42-NEXT: je LBB8_14 +; SSE42-NEXT: LBB8_47: ## %cond.load49 ; SSE42-NEXT: insertps $16, (%rsi), %xmm3 ## xmm3 = xmm3[0],mem[0],xmm3[2,3] ; SSE42-NEXT: addq $4, %rsi ; SSE42-NEXT: testl $16384, %ecx ## imm = 0x4000 -; SSE42-NEXT: je LBB8_30 -; SSE42-NEXT: LBB8_29: ## %cond.load53 +; SSE42-NEXT: je LBB8_15 +; SSE42-NEXT: LBB8_48: ## %cond.load53 ; SSE42-NEXT: insertps $32, (%rsi), %xmm3 ## xmm3 = xmm3[0,1],mem[0],xmm3[3] ; SSE42-NEXT: addq $4, %rsi ; SSE42-NEXT: testw %cx, %cx -; SSE42-NEXT: jns LBB8_32 -; SSE42-NEXT: LBB8_31: ## %cond.load57 +; SSE42-NEXT: jns LBB8_16 +; SSE42-NEXT: LBB8_49: ## %cond.load57 ; SSE42-NEXT: insertps $48, (%rsi), %xmm3 ## xmm3 = xmm3[0,1,2],mem[0] ; SSE42-NEXT: addq $4, %rsi ; SSE42-NEXT: testl $65536, %ecx ## imm = 0x10000 -; SSE42-NEXT: je LBB8_34 -; SSE42-NEXT: LBB8_33: ## %cond.load61 +; SSE42-NEXT: je LBB8_17 +; SSE42-NEXT: LBB8_50: ## %cond.load61 ; SSE42-NEXT: movd (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE42-NEXT: pblendw {{.*#+}} xmm4 = xmm8[0,1],xmm4[2,3,4,5,6,7] ; SSE42-NEXT: addq $4, %rsi ; SSE42-NEXT: testl $131072, %ecx ## imm = 0x20000 -; SSE42-NEXT: je LBB8_36 -; SSE42-NEXT: LBB8_35: ## %cond.load65 +; SSE42-NEXT: je LBB8_18 +; SSE42-NEXT: LBB8_51: ## %cond.load65 ; SSE42-NEXT: insertps $16, (%rsi), %xmm4 ## xmm4 = xmm4[0],mem[0],xmm4[2,3] ; SSE42-NEXT: addq $4, %rsi ; SSE42-NEXT: testl $262144, %ecx ## imm = 0x40000 -; SSE42-NEXT: je LBB8_38 -; SSE42-NEXT: LBB8_37: ## %cond.load69 +; SSE42-NEXT: je LBB8_19 +; SSE42-NEXT: LBB8_52: ## %cond.load69 ; SSE42-NEXT: insertps $32, (%rsi), %xmm4 ## xmm4 = xmm4[0,1],mem[0],xmm4[3] ; SSE42-NEXT: addq $4, %rsi ; SSE42-NEXT: testl $524288, %ecx ## imm = 0x80000 -; SSE42-NEXT: je LBB8_40 -; SSE42-NEXT: LBB8_39: ## %cond.load73 +; SSE42-NEXT: je LBB8_20 +; SSE42-NEXT: LBB8_53: ## %cond.load73 ; SSE42-NEXT: insertps $48, (%rsi), %xmm4 ## xmm4 = xmm4[0,1,2],mem[0] ; SSE42-NEXT: addq $4, %rsi ; SSE42-NEXT: testl $1048576, %ecx ## imm = 0x100000 -; SSE42-NEXT: je LBB8_42 -; SSE42-NEXT: LBB8_41: ## %cond.load77 +; SSE42-NEXT: je LBB8_21 +; SSE42-NEXT: LBB8_54: ## %cond.load77 ; SSE42-NEXT: movd (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE42-NEXT: pblendw {{.*#+}} xmm5 = xmm8[0,1],xmm5[2,3,4,5,6,7] ; SSE42-NEXT: addq $4, %rsi ; SSE42-NEXT: testl $2097152, %ecx ## imm = 0x200000 -; SSE42-NEXT: je LBB8_44 -; SSE42-NEXT: LBB8_43: ## %cond.load81 +; SSE42-NEXT: je LBB8_22 +; SSE42-NEXT: LBB8_55: ## %cond.load81 ; SSE42-NEXT: insertps $16, (%rsi), %xmm5 ## xmm5 = xmm5[0],mem[0],xmm5[2,3] ; SSE42-NEXT: addq $4, %rsi ; SSE42-NEXT: testl $4194304, %ecx ## imm = 0x400000 -; SSE42-NEXT: je LBB8_46 -; SSE42-NEXT: LBB8_45: ## %cond.load85 +; SSE42-NEXT: je LBB8_23 +; SSE42-NEXT: LBB8_56: ## %cond.load85 ; SSE42-NEXT: insertps $32, (%rsi), %xmm5 ## xmm5 = xmm5[0,1],mem[0],xmm5[3] ; SSE42-NEXT: addq $4, %rsi ; SSE42-NEXT: testl $8388608, %ecx ## imm = 0x800000 -; SSE42-NEXT: je LBB8_48 -; SSE42-NEXT: LBB8_47: ## %cond.load89 +; SSE42-NEXT: je LBB8_24 +; SSE42-NEXT: LBB8_57: ## %cond.load89 ; SSE42-NEXT: insertps $48, (%rsi), %xmm5 ## xmm5 = xmm5[0,1,2],mem[0] ; SSE42-NEXT: addq $4, %rsi ; SSE42-NEXT: testl $16777216, %ecx ## imm = 0x1000000 -; SSE42-NEXT: je LBB8_50 -; SSE42-NEXT: LBB8_49: ## %cond.load93 +; SSE42-NEXT: je LBB8_25 +; SSE42-NEXT: LBB8_58: ## %cond.load93 ; SSE42-NEXT: movd (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE42-NEXT: pblendw {{.*#+}} xmm6 = xmm8[0,1],xmm6[2,3,4,5,6,7] ; SSE42-NEXT: addq $4, %rsi ; SSE42-NEXT: testl $33554432, %ecx ## imm = 0x2000000 -; SSE42-NEXT: je LBB8_52 -; SSE42-NEXT: LBB8_51: ## %cond.load97 +; SSE42-NEXT: je LBB8_26 +; SSE42-NEXT: LBB8_59: ## %cond.load97 ; SSE42-NEXT: insertps $16, (%rsi), %xmm6 ## xmm6 = xmm6[0],mem[0],xmm6[2,3] ; SSE42-NEXT: addq $4, %rsi ; SSE42-NEXT: testl $67108864, %ecx ## imm = 0x4000000 -; SSE42-NEXT: je LBB8_54 -; SSE42-NEXT: LBB8_53: ## %cond.load101 +; SSE42-NEXT: je LBB8_27 +; SSE42-NEXT: LBB8_60: ## %cond.load101 ; SSE42-NEXT: insertps $32, (%rsi), %xmm6 ## xmm6 = xmm6[0,1],mem[0],xmm6[3] ; SSE42-NEXT: addq $4, %rsi ; SSE42-NEXT: testl $134217728, %ecx ## imm = 0x8000000 -; SSE42-NEXT: je LBB8_56 -; SSE42-NEXT: LBB8_55: ## %cond.load105 +; SSE42-NEXT: je LBB8_28 +; SSE42-NEXT: LBB8_61: ## %cond.load105 ; SSE42-NEXT: insertps $48, (%rsi), %xmm6 ## xmm6 = xmm6[0,1,2],mem[0] ; SSE42-NEXT: addq $4, %rsi ; SSE42-NEXT: testl $268435456, %ecx ## imm = 0x10000000 -; SSE42-NEXT: je LBB8_58 -; SSE42-NEXT: LBB8_57: ## %cond.load109 +; SSE42-NEXT: je LBB8_29 +; SSE42-NEXT: LBB8_62: ## %cond.load109 ; SSE42-NEXT: movd (%rsi), %xmm8 ## xmm8 = mem[0],zero,zero,zero ; SSE42-NEXT: pblendw {{.*#+}} xmm7 = xmm8[0,1],xmm7[2,3,4,5,6,7] ; SSE42-NEXT: addq $4, %rsi ; SSE42-NEXT: testl $536870912, %ecx ## imm = 0x20000000 -; SSE42-NEXT: je LBB8_60 -; SSE42-NEXT: LBB8_59: ## %cond.load113 +; SSE42-NEXT: je LBB8_30 +; SSE42-NEXT: LBB8_63: ## %cond.load113 ; SSE42-NEXT: insertps $16, (%rsi), %xmm7 ## xmm7 = xmm7[0],mem[0],xmm7[2,3] ; SSE42-NEXT: addq $4, %rsi ; SSE42-NEXT: testl $1073741824, %ecx ## imm = 0x40000000 -; SSE42-NEXT: je LBB8_62 -; SSE42-NEXT: LBB8_61: ## %cond.load117 +; SSE42-NEXT: je LBB8_31 +; SSE42-NEXT: LBB8_64: ## %cond.load117 ; SSE42-NEXT: insertps $32, (%rsi), %xmm7 ## xmm7 = xmm7[0,1],mem[0],xmm7[3] ; SSE42-NEXT: addq $4, %rsi ; SSE42-NEXT: testl $-2147483648, %ecx ## imm = 0x80000000 -; SSE42-NEXT: jne LBB8_63 -; SSE42-NEXT: jmp LBB8_64 +; SSE42-NEXT: jne LBB8_32 +; SSE42-NEXT: jmp LBB8_33 ; ; AVX1-LABEL: expandload_v32f32_v32i32: ; AVX1: ## %bb.0: @@ -2013,289 +2013,289 @@ define <32 x float> @expandload_v32f32_v32i32(ptr %base, <32 x float> %src0, <32 ; AVX1-NEXT: shll $16, %eax ; AVX1-NEXT: orl %ecx, %eax ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne LBB8_1 -; AVX1-NEXT: ## %bb.2: ## %else +; AVX1-NEXT: jne LBB8_33 +; AVX1-NEXT: ## %bb.1: ## %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne LBB8_3 -; AVX1-NEXT: LBB8_4: ## %else2 +; AVX1-NEXT: jne LBB8_34 +; AVX1-NEXT: LBB8_2: ## %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne LBB8_5 -; AVX1-NEXT: LBB8_6: ## %else6 +; AVX1-NEXT: jne LBB8_35 +; AVX1-NEXT: LBB8_3: ## %else6 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne LBB8_7 -; AVX1-NEXT: LBB8_8: ## %else10 +; AVX1-NEXT: jne LBB8_36 +; AVX1-NEXT: LBB8_4: ## %else10 ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: jne LBB8_9 -; AVX1-NEXT: LBB8_10: ## %else14 +; AVX1-NEXT: jne LBB8_37 +; AVX1-NEXT: LBB8_5: ## %else14 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: jne LBB8_11 -; AVX1-NEXT: LBB8_12: ## %else18 +; AVX1-NEXT: jne LBB8_38 +; AVX1-NEXT: LBB8_6: ## %else18 ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: jne LBB8_13 -; AVX1-NEXT: LBB8_14: ## %else22 +; AVX1-NEXT: jne LBB8_39 +; AVX1-NEXT: LBB8_7: ## %else22 ; AVX1-NEXT: testb %al, %al -; AVX1-NEXT: js LBB8_15 -; AVX1-NEXT: LBB8_16: ## %else26 +; AVX1-NEXT: js LBB8_40 +; AVX1-NEXT: LBB8_8: ## %else26 ; AVX1-NEXT: testl $256, %eax ## imm = 0x100 -; AVX1-NEXT: jne LBB8_17 -; AVX1-NEXT: LBB8_18: ## %else30 +; AVX1-NEXT: jne LBB8_41 +; AVX1-NEXT: LBB8_9: ## %else30 ; AVX1-NEXT: testl $512, %eax ## imm = 0x200 -; AVX1-NEXT: jne LBB8_19 -; AVX1-NEXT: LBB8_20: ## %else34 +; AVX1-NEXT: jne LBB8_42 +; AVX1-NEXT: LBB8_10: ## %else34 ; AVX1-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX1-NEXT: jne LBB8_21 -; AVX1-NEXT: LBB8_22: ## %else38 +; AVX1-NEXT: jne LBB8_43 +; AVX1-NEXT: LBB8_11: ## %else38 ; AVX1-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX1-NEXT: jne LBB8_23 -; AVX1-NEXT: LBB8_24: ## %else42 +; AVX1-NEXT: jne LBB8_44 +; AVX1-NEXT: LBB8_12: ## %else42 ; AVX1-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX1-NEXT: jne LBB8_25 -; AVX1-NEXT: LBB8_26: ## %else46 +; AVX1-NEXT: jne LBB8_45 +; AVX1-NEXT: LBB8_13: ## %else46 ; AVX1-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX1-NEXT: jne LBB8_27 -; AVX1-NEXT: LBB8_28: ## %else50 +; AVX1-NEXT: jne LBB8_46 +; AVX1-NEXT: LBB8_14: ## %else50 ; AVX1-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX1-NEXT: jne LBB8_29 -; AVX1-NEXT: LBB8_30: ## %else54 +; AVX1-NEXT: jne LBB8_47 +; AVX1-NEXT: LBB8_15: ## %else54 ; AVX1-NEXT: testw %ax, %ax -; AVX1-NEXT: js LBB8_31 -; AVX1-NEXT: LBB8_32: ## %else58 +; AVX1-NEXT: js LBB8_48 +; AVX1-NEXT: LBB8_16: ## %else58 ; AVX1-NEXT: testl $65536, %eax ## imm = 0x10000 -; AVX1-NEXT: jne LBB8_33 -; AVX1-NEXT: LBB8_34: ## %else62 +; AVX1-NEXT: jne LBB8_49 +; AVX1-NEXT: LBB8_17: ## %else62 ; AVX1-NEXT: testl $131072, %eax ## imm = 0x20000 -; AVX1-NEXT: jne LBB8_35 -; AVX1-NEXT: LBB8_36: ## %else66 +; AVX1-NEXT: jne LBB8_50 +; AVX1-NEXT: LBB8_18: ## %else66 ; AVX1-NEXT: testl $262144, %eax ## imm = 0x40000 -; AVX1-NEXT: jne LBB8_37 -; AVX1-NEXT: LBB8_38: ## %else70 +; AVX1-NEXT: jne LBB8_51 +; AVX1-NEXT: LBB8_19: ## %else70 ; AVX1-NEXT: testl $524288, %eax ## imm = 0x80000 -; AVX1-NEXT: jne LBB8_39 -; AVX1-NEXT: LBB8_40: ## %else74 +; AVX1-NEXT: jne LBB8_52 +; AVX1-NEXT: LBB8_20: ## %else74 ; AVX1-NEXT: testl $1048576, %eax ## imm = 0x100000 -; AVX1-NEXT: jne LBB8_41 -; AVX1-NEXT: LBB8_42: ## %else78 +; AVX1-NEXT: jne LBB8_53 +; AVX1-NEXT: LBB8_21: ## %else78 ; AVX1-NEXT: testl $2097152, %eax ## imm = 0x200000 -; AVX1-NEXT: jne LBB8_43 -; AVX1-NEXT: LBB8_44: ## %else82 +; AVX1-NEXT: jne LBB8_54 +; AVX1-NEXT: LBB8_22: ## %else82 ; AVX1-NEXT: testl $4194304, %eax ## imm = 0x400000 -; AVX1-NEXT: jne LBB8_45 -; AVX1-NEXT: LBB8_46: ## %else86 +; AVX1-NEXT: jne LBB8_55 +; AVX1-NEXT: LBB8_23: ## %else86 ; AVX1-NEXT: testl $8388608, %eax ## imm = 0x800000 -; AVX1-NEXT: jne LBB8_47 -; AVX1-NEXT: LBB8_48: ## %else90 +; AVX1-NEXT: jne LBB8_56 +; AVX1-NEXT: LBB8_24: ## %else90 ; AVX1-NEXT: testl $16777216, %eax ## imm = 0x1000000 -; AVX1-NEXT: jne LBB8_49 -; AVX1-NEXT: LBB8_50: ## %else94 +; AVX1-NEXT: jne LBB8_57 +; AVX1-NEXT: LBB8_25: ## %else94 ; AVX1-NEXT: testl $33554432, %eax ## imm = 0x2000000 -; AVX1-NEXT: jne LBB8_51 -; AVX1-NEXT: LBB8_52: ## %else98 +; AVX1-NEXT: jne LBB8_58 +; AVX1-NEXT: LBB8_26: ## %else98 ; AVX1-NEXT: testl $67108864, %eax ## imm = 0x4000000 -; AVX1-NEXT: jne LBB8_53 -; AVX1-NEXT: LBB8_54: ## %else102 +; AVX1-NEXT: jne LBB8_59 +; AVX1-NEXT: LBB8_27: ## %else102 ; AVX1-NEXT: testl $134217728, %eax ## imm = 0x8000000 -; AVX1-NEXT: jne LBB8_55 -; AVX1-NEXT: LBB8_56: ## %else106 +; AVX1-NEXT: jne LBB8_60 +; AVX1-NEXT: LBB8_28: ## %else106 ; AVX1-NEXT: testl $268435456, %eax ## imm = 0x10000000 -; AVX1-NEXT: jne LBB8_57 -; AVX1-NEXT: LBB8_58: ## %else110 +; AVX1-NEXT: jne LBB8_61 +; AVX1-NEXT: LBB8_29: ## %else110 ; AVX1-NEXT: testl $536870912, %eax ## imm = 0x20000000 -; AVX1-NEXT: jne LBB8_59 -; AVX1-NEXT: LBB8_60: ## %else114 +; AVX1-NEXT: jne LBB8_62 +; AVX1-NEXT: LBB8_30: ## %else114 ; AVX1-NEXT: testl $1073741824, %eax ## imm = 0x40000000 -; AVX1-NEXT: jne LBB8_61 -; AVX1-NEXT: LBB8_62: ## %else118 -; AVX1-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 ; AVX1-NEXT: jne LBB8_63 -; AVX1-NEXT: LBB8_64: ## %else122 +; AVX1-NEXT: LBB8_31: ## %else118 +; AVX1-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 +; AVX1-NEXT: jne LBB8_64 +; AVX1-NEXT: LBB8_32: ## %else122 ; AVX1-NEXT: retq -; AVX1-NEXT: LBB8_1: ## %cond.load +; AVX1-NEXT: LBB8_33: ## %cond.load ; AVX1-NEXT: vmovss (%rdi), %xmm4 ## xmm4 = mem[0],zero,zero,zero ; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm4[0],ymm0[1,2,3,4,5,6,7] ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je LBB8_4 -; AVX1-NEXT: LBB8_3: ## %cond.load1 +; AVX1-NEXT: je LBB8_2 +; AVX1-NEXT: LBB8_34: ## %cond.load1 ; AVX1-NEXT: vinsertps $16, (%rdi), %xmm0, %xmm4 ## xmm4 = xmm0[0],mem[0],xmm0[2,3] ; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm4[0,1,2,3],ymm0[4,5,6,7] ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je LBB8_6 -; AVX1-NEXT: LBB8_5: ## %cond.load5 +; AVX1-NEXT: je LBB8_3 +; AVX1-NEXT: LBB8_35: ## %cond.load5 ; AVX1-NEXT: vinsertps $32, (%rdi), %xmm0, %xmm4 ## xmm4 = xmm0[0,1],mem[0],xmm0[3] ; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm4[0,1,2,3],ymm0[4,5,6,7] ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je LBB8_8 -; AVX1-NEXT: LBB8_7: ## %cond.load9 +; AVX1-NEXT: je LBB8_4 +; AVX1-NEXT: LBB8_36: ## %cond.load9 ; AVX1-NEXT: vinsertps $48, (%rdi), %xmm0, %xmm4 ## xmm4 = xmm0[0,1,2],mem[0] ; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm4[0,1,2,3],ymm0[4,5,6,7] ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: je LBB8_10 -; AVX1-NEXT: LBB8_9: ## %cond.load13 +; AVX1-NEXT: je LBB8_5 +; AVX1-NEXT: LBB8_37: ## %cond.load13 ; AVX1-NEXT: vbroadcastss (%rdi), %ymm4 ; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm4[4],ymm0[5,6,7] ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je LBB8_12 -; AVX1-NEXT: LBB8_11: ## %cond.load17 +; AVX1-NEXT: je LBB8_6 +; AVX1-NEXT: LBB8_38: ## %cond.load17 ; AVX1-NEXT: vbroadcastss (%rdi), %ymm4 ; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3,4],ymm4[5],ymm0[6,7] ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: je LBB8_14 -; AVX1-NEXT: LBB8_13: ## %cond.load21 +; AVX1-NEXT: je LBB8_7 +; AVX1-NEXT: LBB8_39: ## %cond.load21 ; AVX1-NEXT: vbroadcastss (%rdi), %ymm4 ; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5],ymm4[6],ymm0[7] ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testb %al, %al -; AVX1-NEXT: jns LBB8_16 -; AVX1-NEXT: LBB8_15: ## %cond.load25 +; AVX1-NEXT: jns LBB8_8 +; AVX1-NEXT: LBB8_40: ## %cond.load25 ; AVX1-NEXT: vbroadcastss (%rdi), %ymm4 ; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5,6],ymm4[7] ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $256, %eax ## imm = 0x100 -; AVX1-NEXT: je LBB8_18 -; AVX1-NEXT: LBB8_17: ## %cond.load29 +; AVX1-NEXT: je LBB8_9 +; AVX1-NEXT: LBB8_41: ## %cond.load29 ; AVX1-NEXT: vmovss (%rdi), %xmm4 ## xmm4 = mem[0],zero,zero,zero ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm4[0],ymm1[1,2,3,4,5,6,7] ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $512, %eax ## imm = 0x200 -; AVX1-NEXT: je LBB8_20 -; AVX1-NEXT: LBB8_19: ## %cond.load33 +; AVX1-NEXT: je LBB8_10 +; AVX1-NEXT: LBB8_42: ## %cond.load33 ; AVX1-NEXT: vinsertps $16, (%rdi), %xmm1, %xmm4 ## xmm4 = xmm1[0],mem[0],xmm1[2,3] ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm4[0,1,2,3],ymm1[4,5,6,7] ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX1-NEXT: je LBB8_22 -; AVX1-NEXT: LBB8_21: ## %cond.load37 +; AVX1-NEXT: je LBB8_11 +; AVX1-NEXT: LBB8_43: ## %cond.load37 ; AVX1-NEXT: vinsertps $32, (%rdi), %xmm1, %xmm4 ## xmm4 = xmm1[0,1],mem[0],xmm1[3] ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm4[0,1,2,3],ymm1[4,5,6,7] ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX1-NEXT: je LBB8_24 -; AVX1-NEXT: LBB8_23: ## %cond.load41 +; AVX1-NEXT: je LBB8_12 +; AVX1-NEXT: LBB8_44: ## %cond.load41 ; AVX1-NEXT: vinsertps $48, (%rdi), %xmm1, %xmm4 ## xmm4 = xmm1[0,1,2],mem[0] ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm4[0,1,2,3],ymm1[4,5,6,7] ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX1-NEXT: je LBB8_26 -; AVX1-NEXT: LBB8_25: ## %cond.load45 +; AVX1-NEXT: je LBB8_13 +; AVX1-NEXT: LBB8_45: ## %cond.load45 ; AVX1-NEXT: vbroadcastss (%rdi), %ymm4 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm4[4],ymm1[5,6,7] ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX1-NEXT: je LBB8_28 -; AVX1-NEXT: LBB8_27: ## %cond.load49 +; AVX1-NEXT: je LBB8_14 +; AVX1-NEXT: LBB8_46: ## %cond.load49 ; AVX1-NEXT: vbroadcastss (%rdi), %ymm4 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1,2,3,4],ymm4[5],ymm1[6,7] ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX1-NEXT: je LBB8_30 -; AVX1-NEXT: LBB8_29: ## %cond.load53 +; AVX1-NEXT: je LBB8_15 +; AVX1-NEXT: LBB8_47: ## %cond.load53 ; AVX1-NEXT: vbroadcastss (%rdi), %ymm4 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1,2,3,4,5],ymm4[6],ymm1[7] ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testw %ax, %ax -; AVX1-NEXT: jns LBB8_32 -; AVX1-NEXT: LBB8_31: ## %cond.load57 +; AVX1-NEXT: jns LBB8_16 +; AVX1-NEXT: LBB8_48: ## %cond.load57 ; AVX1-NEXT: vbroadcastss (%rdi), %ymm4 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1,2,3,4,5,6],ymm4[7] ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $65536, %eax ## imm = 0x10000 -; AVX1-NEXT: je LBB8_34 -; AVX1-NEXT: LBB8_33: ## %cond.load61 +; AVX1-NEXT: je LBB8_17 +; AVX1-NEXT: LBB8_49: ## %cond.load61 ; AVX1-NEXT: vmovss (%rdi), %xmm4 ## xmm4 = mem[0],zero,zero,zero ; AVX1-NEXT: vblendps {{.*#+}} ymm2 = ymm4[0],ymm2[1,2,3,4,5,6,7] ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $131072, %eax ## imm = 0x20000 -; AVX1-NEXT: je LBB8_36 -; AVX1-NEXT: LBB8_35: ## %cond.load65 +; AVX1-NEXT: je LBB8_18 +; AVX1-NEXT: LBB8_50: ## %cond.load65 ; AVX1-NEXT: vinsertps $16, (%rdi), %xmm2, %xmm4 ## xmm4 = xmm2[0],mem[0],xmm2[2,3] ; AVX1-NEXT: vblendps {{.*#+}} ymm2 = ymm4[0,1,2,3],ymm2[4,5,6,7] ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $262144, %eax ## imm = 0x40000 -; AVX1-NEXT: je LBB8_38 -; AVX1-NEXT: LBB8_37: ## %cond.load69 +; AVX1-NEXT: je LBB8_19 +; AVX1-NEXT: LBB8_51: ## %cond.load69 ; AVX1-NEXT: vinsertps $32, (%rdi), %xmm2, %xmm4 ## xmm4 = xmm2[0,1],mem[0],xmm2[3] ; AVX1-NEXT: vblendps {{.*#+}} ymm2 = ymm4[0,1,2,3],ymm2[4,5,6,7] ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $524288, %eax ## imm = 0x80000 -; AVX1-NEXT: je LBB8_40 -; AVX1-NEXT: LBB8_39: ## %cond.load73 +; AVX1-NEXT: je LBB8_20 +; AVX1-NEXT: LBB8_52: ## %cond.load73 ; AVX1-NEXT: vinsertps $48, (%rdi), %xmm2, %xmm4 ## xmm4 = xmm2[0,1,2],mem[0] ; AVX1-NEXT: vblendps {{.*#+}} ymm2 = ymm4[0,1,2,3],ymm2[4,5,6,7] ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $1048576, %eax ## imm = 0x100000 -; AVX1-NEXT: je LBB8_42 -; AVX1-NEXT: LBB8_41: ## %cond.load77 +; AVX1-NEXT: je LBB8_21 +; AVX1-NEXT: LBB8_53: ## %cond.load77 ; AVX1-NEXT: vbroadcastss (%rdi), %ymm4 ; AVX1-NEXT: vblendps {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm4[4],ymm2[5,6,7] ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $2097152, %eax ## imm = 0x200000 -; AVX1-NEXT: je LBB8_44 -; AVX1-NEXT: LBB8_43: ## %cond.load81 +; AVX1-NEXT: je LBB8_22 +; AVX1-NEXT: LBB8_54: ## %cond.load81 ; AVX1-NEXT: vbroadcastss (%rdi), %ymm4 ; AVX1-NEXT: vblendps {{.*#+}} ymm2 = ymm2[0,1,2,3,4],ymm4[5],ymm2[6,7] ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $4194304, %eax ## imm = 0x400000 -; AVX1-NEXT: je LBB8_46 -; AVX1-NEXT: LBB8_45: ## %cond.load85 +; AVX1-NEXT: je LBB8_23 +; AVX1-NEXT: LBB8_55: ## %cond.load85 ; AVX1-NEXT: vbroadcastss (%rdi), %ymm4 ; AVX1-NEXT: vblendps {{.*#+}} ymm2 = ymm2[0,1,2,3,4,5],ymm4[6],ymm2[7] ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $8388608, %eax ## imm = 0x800000 -; AVX1-NEXT: je LBB8_48 -; AVX1-NEXT: LBB8_47: ## %cond.load89 +; AVX1-NEXT: je LBB8_24 +; AVX1-NEXT: LBB8_56: ## %cond.load89 ; AVX1-NEXT: vbroadcastss (%rdi), %ymm4 ; AVX1-NEXT: vblendps {{.*#+}} ymm2 = ymm2[0,1,2,3,4,5,6],ymm4[7] ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $16777216, %eax ## imm = 0x1000000 -; AVX1-NEXT: je LBB8_50 -; AVX1-NEXT: LBB8_49: ## %cond.load93 +; AVX1-NEXT: je LBB8_25 +; AVX1-NEXT: LBB8_57: ## %cond.load93 ; AVX1-NEXT: vmovss (%rdi), %xmm4 ## xmm4 = mem[0],zero,zero,zero ; AVX1-NEXT: vblendps {{.*#+}} ymm3 = ymm4[0],ymm3[1,2,3,4,5,6,7] ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $33554432, %eax ## imm = 0x2000000 -; AVX1-NEXT: je LBB8_52 -; AVX1-NEXT: LBB8_51: ## %cond.load97 +; AVX1-NEXT: je LBB8_26 +; AVX1-NEXT: LBB8_58: ## %cond.load97 ; AVX1-NEXT: vinsertps $16, (%rdi), %xmm3, %xmm4 ## xmm4 = xmm3[0],mem[0],xmm3[2,3] ; AVX1-NEXT: vblendps {{.*#+}} ymm3 = ymm4[0,1,2,3],ymm3[4,5,6,7] ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $67108864, %eax ## imm = 0x4000000 -; AVX1-NEXT: je LBB8_54 -; AVX1-NEXT: LBB8_53: ## %cond.load101 +; AVX1-NEXT: je LBB8_27 +; AVX1-NEXT: LBB8_59: ## %cond.load101 ; AVX1-NEXT: vinsertps $32, (%rdi), %xmm3, %xmm4 ## xmm4 = xmm3[0,1],mem[0],xmm3[3] ; AVX1-NEXT: vblendps {{.*#+}} ymm3 = ymm4[0,1,2,3],ymm3[4,5,6,7] ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $134217728, %eax ## imm = 0x8000000 -; AVX1-NEXT: je LBB8_56 -; AVX1-NEXT: LBB8_55: ## %cond.load105 +; AVX1-NEXT: je LBB8_28 +; AVX1-NEXT: LBB8_60: ## %cond.load105 ; AVX1-NEXT: vinsertps $48, (%rdi), %xmm3, %xmm4 ## xmm4 = xmm3[0,1,2],mem[0] ; AVX1-NEXT: vblendps {{.*#+}} ymm3 = ymm4[0,1,2,3],ymm3[4,5,6,7] ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $268435456, %eax ## imm = 0x10000000 -; AVX1-NEXT: je LBB8_58 -; AVX1-NEXT: LBB8_57: ## %cond.load109 +; AVX1-NEXT: je LBB8_29 +; AVX1-NEXT: LBB8_61: ## %cond.load109 ; AVX1-NEXT: vbroadcastss (%rdi), %ymm4 ; AVX1-NEXT: vblendps {{.*#+}} ymm3 = ymm3[0,1,2,3],ymm4[4],ymm3[5,6,7] ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $536870912, %eax ## imm = 0x20000000 -; AVX1-NEXT: je LBB8_60 -; AVX1-NEXT: LBB8_59: ## %cond.load113 +; AVX1-NEXT: je LBB8_30 +; AVX1-NEXT: LBB8_62: ## %cond.load113 ; AVX1-NEXT: vbroadcastss (%rdi), %ymm4 ; AVX1-NEXT: vblendps {{.*#+}} ymm3 = ymm3[0,1,2,3,4],ymm4[5],ymm3[6,7] ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $1073741824, %eax ## imm = 0x40000000 -; AVX1-NEXT: je LBB8_62 -; AVX1-NEXT: LBB8_61: ## %cond.load117 +; AVX1-NEXT: je LBB8_31 +; AVX1-NEXT: LBB8_63: ## %cond.load117 ; AVX1-NEXT: vbroadcastss (%rdi), %ymm4 ; AVX1-NEXT: vblendps {{.*#+}} ymm3 = ymm3[0,1,2,3,4,5],ymm4[6],ymm3[7] ; AVX1-NEXT: addq $4, %rdi ; AVX1-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 -; AVX1-NEXT: je LBB8_64 -; AVX1-NEXT: LBB8_63: ## %cond.load121 +; AVX1-NEXT: je LBB8_32 +; AVX1-NEXT: LBB8_64: ## %cond.load121 ; AVX1-NEXT: vbroadcastss (%rdi), %ymm4 ; AVX1-NEXT: vblendps {{.*#+}} ymm3 = ymm3[0,1,2,3,4,5,6],ymm4[7] ; AVX1-NEXT: retq @@ -2315,289 +2315,289 @@ define <32 x float> @expandload_v32f32_v32i32(ptr %base, <32 x float> %src0, <32 ; AVX2-NEXT: vpermq {{.*#+}} ymm4 = ymm4[0,2,1,3] ; AVX2-NEXT: vpmovmskb %ymm4, %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne LBB8_1 -; AVX2-NEXT: ## %bb.2: ## %else +; AVX2-NEXT: jne LBB8_33 +; AVX2-NEXT: ## %bb.1: ## %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne LBB8_3 -; AVX2-NEXT: LBB8_4: ## %else2 +; AVX2-NEXT: jne LBB8_34 +; AVX2-NEXT: LBB8_2: ## %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne LBB8_5 -; AVX2-NEXT: LBB8_6: ## %else6 +; AVX2-NEXT: jne LBB8_35 +; AVX2-NEXT: LBB8_3: ## %else6 ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: jne LBB8_7 -; AVX2-NEXT: LBB8_8: ## %else10 +; AVX2-NEXT: jne LBB8_36 +; AVX2-NEXT: LBB8_4: ## %else10 ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: jne LBB8_9 -; AVX2-NEXT: LBB8_10: ## %else14 +; AVX2-NEXT: jne LBB8_37 +; AVX2-NEXT: LBB8_5: ## %else14 ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: jne LBB8_11 -; AVX2-NEXT: LBB8_12: ## %else18 +; AVX2-NEXT: jne LBB8_38 +; AVX2-NEXT: LBB8_6: ## %else18 ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: jne LBB8_13 -; AVX2-NEXT: LBB8_14: ## %else22 +; AVX2-NEXT: jne LBB8_39 +; AVX2-NEXT: LBB8_7: ## %else22 ; AVX2-NEXT: testb %al, %al -; AVX2-NEXT: js LBB8_15 -; AVX2-NEXT: LBB8_16: ## %else26 +; AVX2-NEXT: js LBB8_40 +; AVX2-NEXT: LBB8_8: ## %else26 ; AVX2-NEXT: testl $256, %eax ## imm = 0x100 -; AVX2-NEXT: jne LBB8_17 -; AVX2-NEXT: LBB8_18: ## %else30 +; AVX2-NEXT: jne LBB8_41 +; AVX2-NEXT: LBB8_9: ## %else30 ; AVX2-NEXT: testl $512, %eax ## imm = 0x200 -; AVX2-NEXT: jne LBB8_19 -; AVX2-NEXT: LBB8_20: ## %else34 +; AVX2-NEXT: jne LBB8_42 +; AVX2-NEXT: LBB8_10: ## %else34 ; AVX2-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX2-NEXT: jne LBB8_21 -; AVX2-NEXT: LBB8_22: ## %else38 +; AVX2-NEXT: jne LBB8_43 +; AVX2-NEXT: LBB8_11: ## %else38 ; AVX2-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX2-NEXT: jne LBB8_23 -; AVX2-NEXT: LBB8_24: ## %else42 +; AVX2-NEXT: jne LBB8_44 +; AVX2-NEXT: LBB8_12: ## %else42 ; AVX2-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX2-NEXT: jne LBB8_25 -; AVX2-NEXT: LBB8_26: ## %else46 +; AVX2-NEXT: jne LBB8_45 +; AVX2-NEXT: LBB8_13: ## %else46 ; AVX2-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX2-NEXT: jne LBB8_27 -; AVX2-NEXT: LBB8_28: ## %else50 +; AVX2-NEXT: jne LBB8_46 +; AVX2-NEXT: LBB8_14: ## %else50 ; AVX2-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX2-NEXT: jne LBB8_29 -; AVX2-NEXT: LBB8_30: ## %else54 +; AVX2-NEXT: jne LBB8_47 +; AVX2-NEXT: LBB8_15: ## %else54 ; AVX2-NEXT: testw %ax, %ax -; AVX2-NEXT: js LBB8_31 -; AVX2-NEXT: LBB8_32: ## %else58 +; AVX2-NEXT: js LBB8_48 +; AVX2-NEXT: LBB8_16: ## %else58 ; AVX2-NEXT: testl $65536, %eax ## imm = 0x10000 -; AVX2-NEXT: jne LBB8_33 -; AVX2-NEXT: LBB8_34: ## %else62 +; AVX2-NEXT: jne LBB8_49 +; AVX2-NEXT: LBB8_17: ## %else62 ; AVX2-NEXT: testl $131072, %eax ## imm = 0x20000 -; AVX2-NEXT: jne LBB8_35 -; AVX2-NEXT: LBB8_36: ## %else66 +; AVX2-NEXT: jne LBB8_50 +; AVX2-NEXT: LBB8_18: ## %else66 ; AVX2-NEXT: testl $262144, %eax ## imm = 0x40000 -; AVX2-NEXT: jne LBB8_37 -; AVX2-NEXT: LBB8_38: ## %else70 +; AVX2-NEXT: jne LBB8_51 +; AVX2-NEXT: LBB8_19: ## %else70 ; AVX2-NEXT: testl $524288, %eax ## imm = 0x80000 -; AVX2-NEXT: jne LBB8_39 -; AVX2-NEXT: LBB8_40: ## %else74 +; AVX2-NEXT: jne LBB8_52 +; AVX2-NEXT: LBB8_20: ## %else74 ; AVX2-NEXT: testl $1048576, %eax ## imm = 0x100000 -; AVX2-NEXT: jne LBB8_41 -; AVX2-NEXT: LBB8_42: ## %else78 +; AVX2-NEXT: jne LBB8_53 +; AVX2-NEXT: LBB8_21: ## %else78 ; AVX2-NEXT: testl $2097152, %eax ## imm = 0x200000 -; AVX2-NEXT: jne LBB8_43 -; AVX2-NEXT: LBB8_44: ## %else82 +; AVX2-NEXT: jne LBB8_54 +; AVX2-NEXT: LBB8_22: ## %else82 ; AVX2-NEXT: testl $4194304, %eax ## imm = 0x400000 -; AVX2-NEXT: jne LBB8_45 -; AVX2-NEXT: LBB8_46: ## %else86 +; AVX2-NEXT: jne LBB8_55 +; AVX2-NEXT: LBB8_23: ## %else86 ; AVX2-NEXT: testl $8388608, %eax ## imm = 0x800000 -; AVX2-NEXT: jne LBB8_47 -; AVX2-NEXT: LBB8_48: ## %else90 +; AVX2-NEXT: jne LBB8_56 +; AVX2-NEXT: LBB8_24: ## %else90 ; AVX2-NEXT: testl $16777216, %eax ## imm = 0x1000000 -; AVX2-NEXT: jne LBB8_49 -; AVX2-NEXT: LBB8_50: ## %else94 +; AVX2-NEXT: jne LBB8_57 +; AVX2-NEXT: LBB8_25: ## %else94 ; AVX2-NEXT: testl $33554432, %eax ## imm = 0x2000000 -; AVX2-NEXT: jne LBB8_51 -; AVX2-NEXT: LBB8_52: ## %else98 +; AVX2-NEXT: jne LBB8_58 +; AVX2-NEXT: LBB8_26: ## %else98 ; AVX2-NEXT: testl $67108864, %eax ## imm = 0x4000000 -; AVX2-NEXT: jne LBB8_53 -; AVX2-NEXT: LBB8_54: ## %else102 +; AVX2-NEXT: jne LBB8_59 +; AVX2-NEXT: LBB8_27: ## %else102 ; AVX2-NEXT: testl $134217728, %eax ## imm = 0x8000000 -; AVX2-NEXT: jne LBB8_55 -; AVX2-NEXT: LBB8_56: ## %else106 +; AVX2-NEXT: jne LBB8_60 +; AVX2-NEXT: LBB8_28: ## %else106 ; AVX2-NEXT: testl $268435456, %eax ## imm = 0x10000000 -; AVX2-NEXT: jne LBB8_57 -; AVX2-NEXT: LBB8_58: ## %else110 +; AVX2-NEXT: jne LBB8_61 +; AVX2-NEXT: LBB8_29: ## %else110 ; AVX2-NEXT: testl $536870912, %eax ## imm = 0x20000000 -; AVX2-NEXT: jne LBB8_59 -; AVX2-NEXT: LBB8_60: ## %else114 +; AVX2-NEXT: jne LBB8_62 +; AVX2-NEXT: LBB8_30: ## %else114 ; AVX2-NEXT: testl $1073741824, %eax ## imm = 0x40000000 -; AVX2-NEXT: jne LBB8_61 -; AVX2-NEXT: LBB8_62: ## %else118 -; AVX2-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 ; AVX2-NEXT: jne LBB8_63 -; AVX2-NEXT: LBB8_64: ## %else122 +; AVX2-NEXT: LBB8_31: ## %else118 +; AVX2-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 +; AVX2-NEXT: jne LBB8_64 +; AVX2-NEXT: LBB8_32: ## %else122 ; AVX2-NEXT: retq -; AVX2-NEXT: LBB8_1: ## %cond.load +; AVX2-NEXT: LBB8_33: ## %cond.load ; AVX2-NEXT: vmovd (%rdi), %xmm4 ## xmm4 = mem[0],zero,zero,zero ; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm4[0],ymm0[1,2,3,4,5,6,7] ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je LBB8_4 -; AVX2-NEXT: LBB8_3: ## %cond.load1 +; AVX2-NEXT: je LBB8_2 +; AVX2-NEXT: LBB8_34: ## %cond.load1 ; AVX2-NEXT: vinsertps $16, (%rdi), %xmm0, %xmm4 ## xmm4 = xmm0[0],mem[0],xmm0[2,3] ; AVX2-NEXT: vblendps {{.*#+}} ymm0 = ymm4[0,1,2,3],ymm0[4,5,6,7] ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je LBB8_6 -; AVX2-NEXT: LBB8_5: ## %cond.load5 +; AVX2-NEXT: je LBB8_3 +; AVX2-NEXT: LBB8_35: ## %cond.load5 ; AVX2-NEXT: vinsertps $32, (%rdi), %xmm0, %xmm4 ## xmm4 = xmm0[0,1],mem[0],xmm0[3] ; AVX2-NEXT: vblendps {{.*#+}} ymm0 = ymm4[0,1,2,3],ymm0[4,5,6,7] ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je LBB8_8 -; AVX2-NEXT: LBB8_7: ## %cond.load9 +; AVX2-NEXT: je LBB8_4 +; AVX2-NEXT: LBB8_36: ## %cond.load9 ; AVX2-NEXT: vinsertps $48, (%rdi), %xmm0, %xmm4 ## xmm4 = xmm0[0,1,2],mem[0] ; AVX2-NEXT: vblendps {{.*#+}} ymm0 = ymm4[0,1,2,3],ymm0[4,5,6,7] ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: je LBB8_10 -; AVX2-NEXT: LBB8_9: ## %cond.load13 +; AVX2-NEXT: je LBB8_5 +; AVX2-NEXT: LBB8_37: ## %cond.load13 ; AVX2-NEXT: vbroadcastss (%rdi), %ymm4 ; AVX2-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm4[4],ymm0[5,6,7] ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: je LBB8_12 -; AVX2-NEXT: LBB8_11: ## %cond.load17 +; AVX2-NEXT: je LBB8_6 +; AVX2-NEXT: LBB8_38: ## %cond.load17 ; AVX2-NEXT: vbroadcastss (%rdi), %ymm4 ; AVX2-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3,4],ymm4[5],ymm0[6,7] ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: je LBB8_14 -; AVX2-NEXT: LBB8_13: ## %cond.load21 +; AVX2-NEXT: je LBB8_7 +; AVX2-NEXT: LBB8_39: ## %cond.load21 ; AVX2-NEXT: vbroadcastss (%rdi), %ymm4 ; AVX2-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5],ymm4[6],ymm0[7] ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testb %al, %al -; AVX2-NEXT: jns LBB8_16 -; AVX2-NEXT: LBB8_15: ## %cond.load25 +; AVX2-NEXT: jns LBB8_8 +; AVX2-NEXT: LBB8_40: ## %cond.load25 ; AVX2-NEXT: vbroadcastss (%rdi), %ymm4 ; AVX2-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5,6],ymm4[7] ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $256, %eax ## imm = 0x100 -; AVX2-NEXT: je LBB8_18 -; AVX2-NEXT: LBB8_17: ## %cond.load29 +; AVX2-NEXT: je LBB8_9 +; AVX2-NEXT: LBB8_41: ## %cond.load29 ; AVX2-NEXT: vmovd (%rdi), %xmm4 ## xmm4 = mem[0],zero,zero,zero ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm4[0],ymm1[1,2,3,4,5,6,7] ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $512, %eax ## imm = 0x200 -; AVX2-NEXT: je LBB8_20 -; AVX2-NEXT: LBB8_19: ## %cond.load33 +; AVX2-NEXT: je LBB8_10 +; AVX2-NEXT: LBB8_42: ## %cond.load33 ; AVX2-NEXT: vinsertps $16, (%rdi), %xmm1, %xmm4 ## xmm4 = xmm1[0],mem[0],xmm1[2,3] ; AVX2-NEXT: vblendps {{.*#+}} ymm1 = ymm4[0,1,2,3],ymm1[4,5,6,7] ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX2-NEXT: je LBB8_22 -; AVX2-NEXT: LBB8_21: ## %cond.load37 +; AVX2-NEXT: je LBB8_11 +; AVX2-NEXT: LBB8_43: ## %cond.load37 ; AVX2-NEXT: vinsertps $32, (%rdi), %xmm1, %xmm4 ## xmm4 = xmm1[0,1],mem[0],xmm1[3] ; AVX2-NEXT: vblendps {{.*#+}} ymm1 = ymm4[0,1,2,3],ymm1[4,5,6,7] ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX2-NEXT: je LBB8_24 -; AVX2-NEXT: LBB8_23: ## %cond.load41 +; AVX2-NEXT: je LBB8_12 +; AVX2-NEXT: LBB8_44: ## %cond.load41 ; AVX2-NEXT: vinsertps $48, (%rdi), %xmm1, %xmm4 ## xmm4 = xmm1[0,1,2],mem[0] ; AVX2-NEXT: vblendps {{.*#+}} ymm1 = ymm4[0,1,2,3],ymm1[4,5,6,7] ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX2-NEXT: je LBB8_26 -; AVX2-NEXT: LBB8_25: ## %cond.load45 +; AVX2-NEXT: je LBB8_13 +; AVX2-NEXT: LBB8_45: ## %cond.load45 ; AVX2-NEXT: vbroadcastss (%rdi), %ymm4 ; AVX2-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm4[4],ymm1[5,6,7] ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX2-NEXT: je LBB8_28 -; AVX2-NEXT: LBB8_27: ## %cond.load49 +; AVX2-NEXT: je LBB8_14 +; AVX2-NEXT: LBB8_46: ## %cond.load49 ; AVX2-NEXT: vbroadcastss (%rdi), %ymm4 ; AVX2-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1,2,3,4],ymm4[5],ymm1[6,7] ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX2-NEXT: je LBB8_30 -; AVX2-NEXT: LBB8_29: ## %cond.load53 +; AVX2-NEXT: je LBB8_15 +; AVX2-NEXT: LBB8_47: ## %cond.load53 ; AVX2-NEXT: vbroadcastss (%rdi), %ymm4 ; AVX2-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1,2,3,4,5],ymm4[6],ymm1[7] ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testw %ax, %ax -; AVX2-NEXT: jns LBB8_32 -; AVX2-NEXT: LBB8_31: ## %cond.load57 +; AVX2-NEXT: jns LBB8_16 +; AVX2-NEXT: LBB8_48: ## %cond.load57 ; AVX2-NEXT: vbroadcastss (%rdi), %ymm4 ; AVX2-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1,2,3,4,5,6],ymm4[7] ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $65536, %eax ## imm = 0x10000 -; AVX2-NEXT: je LBB8_34 -; AVX2-NEXT: LBB8_33: ## %cond.load61 +; AVX2-NEXT: je LBB8_17 +; AVX2-NEXT: LBB8_49: ## %cond.load61 ; AVX2-NEXT: vmovd (%rdi), %xmm4 ## xmm4 = mem[0],zero,zero,zero ; AVX2-NEXT: vpblendd {{.*#+}} ymm2 = ymm4[0],ymm2[1,2,3,4,5,6,7] ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $131072, %eax ## imm = 0x20000 -; AVX2-NEXT: je LBB8_36 -; AVX2-NEXT: LBB8_35: ## %cond.load65 +; AVX2-NEXT: je LBB8_18 +; AVX2-NEXT: LBB8_50: ## %cond.load65 ; AVX2-NEXT: vinsertps $16, (%rdi), %xmm2, %xmm4 ## xmm4 = xmm2[0],mem[0],xmm2[2,3] ; AVX2-NEXT: vblendps {{.*#+}} ymm2 = ymm4[0,1,2,3],ymm2[4,5,6,7] ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $262144, %eax ## imm = 0x40000 -; AVX2-NEXT: je LBB8_38 -; AVX2-NEXT: LBB8_37: ## %cond.load69 +; AVX2-NEXT: je LBB8_19 +; AVX2-NEXT: LBB8_51: ## %cond.load69 ; AVX2-NEXT: vinsertps $32, (%rdi), %xmm2, %xmm4 ## xmm4 = xmm2[0,1],mem[0],xmm2[3] ; AVX2-NEXT: vblendps {{.*#+}} ymm2 = ymm4[0,1,2,3],ymm2[4,5,6,7] ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $524288, %eax ## imm = 0x80000 -; AVX2-NEXT: je LBB8_40 -; AVX2-NEXT: LBB8_39: ## %cond.load73 +; AVX2-NEXT: je LBB8_20 +; AVX2-NEXT: LBB8_52: ## %cond.load73 ; AVX2-NEXT: vinsertps $48, (%rdi), %xmm2, %xmm4 ## xmm4 = xmm2[0,1,2],mem[0] ; AVX2-NEXT: vblendps {{.*#+}} ymm2 = ymm4[0,1,2,3],ymm2[4,5,6,7] ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $1048576, %eax ## imm = 0x100000 -; AVX2-NEXT: je LBB8_42 -; AVX2-NEXT: LBB8_41: ## %cond.load77 +; AVX2-NEXT: je LBB8_21 +; AVX2-NEXT: LBB8_53: ## %cond.load77 ; AVX2-NEXT: vbroadcastss (%rdi), %ymm4 ; AVX2-NEXT: vblendps {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm4[4],ymm2[5,6,7] ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $2097152, %eax ## imm = 0x200000 -; AVX2-NEXT: je LBB8_44 -; AVX2-NEXT: LBB8_43: ## %cond.load81 +; AVX2-NEXT: je LBB8_22 +; AVX2-NEXT: LBB8_54: ## %cond.load81 ; AVX2-NEXT: vbroadcastss (%rdi), %ymm4 ; AVX2-NEXT: vblendps {{.*#+}} ymm2 = ymm2[0,1,2,3,4],ymm4[5],ymm2[6,7] ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $4194304, %eax ## imm = 0x400000 -; AVX2-NEXT: je LBB8_46 -; AVX2-NEXT: LBB8_45: ## %cond.load85 +; AVX2-NEXT: je LBB8_23 +; AVX2-NEXT: LBB8_55: ## %cond.load85 ; AVX2-NEXT: vbroadcastss (%rdi), %ymm4 ; AVX2-NEXT: vblendps {{.*#+}} ymm2 = ymm2[0,1,2,3,4,5],ymm4[6],ymm2[7] ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $8388608, %eax ## imm = 0x800000 -; AVX2-NEXT: je LBB8_48 -; AVX2-NEXT: LBB8_47: ## %cond.load89 +; AVX2-NEXT: je LBB8_24 +; AVX2-NEXT: LBB8_56: ## %cond.load89 ; AVX2-NEXT: vbroadcastss (%rdi), %ymm4 ; AVX2-NEXT: vblendps {{.*#+}} ymm2 = ymm2[0,1,2,3,4,5,6],ymm4[7] ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $16777216, %eax ## imm = 0x1000000 -; AVX2-NEXT: je LBB8_50 -; AVX2-NEXT: LBB8_49: ## %cond.load93 +; AVX2-NEXT: je LBB8_25 +; AVX2-NEXT: LBB8_57: ## %cond.load93 ; AVX2-NEXT: vmovd (%rdi), %xmm4 ## xmm4 = mem[0],zero,zero,zero ; AVX2-NEXT: vpblendd {{.*#+}} ymm3 = ymm4[0],ymm3[1,2,3,4,5,6,7] ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $33554432, %eax ## imm = 0x2000000 -; AVX2-NEXT: je LBB8_52 -; AVX2-NEXT: LBB8_51: ## %cond.load97 +; AVX2-NEXT: je LBB8_26 +; AVX2-NEXT: LBB8_58: ## %cond.load97 ; AVX2-NEXT: vinsertps $16, (%rdi), %xmm3, %xmm4 ## xmm4 = xmm3[0],mem[0],xmm3[2,3] ; AVX2-NEXT: vblendps {{.*#+}} ymm3 = ymm4[0,1,2,3],ymm3[4,5,6,7] ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $67108864, %eax ## imm = 0x4000000 -; AVX2-NEXT: je LBB8_54 -; AVX2-NEXT: LBB8_53: ## %cond.load101 +; AVX2-NEXT: je LBB8_27 +; AVX2-NEXT: LBB8_59: ## %cond.load101 ; AVX2-NEXT: vinsertps $32, (%rdi), %xmm3, %xmm4 ## xmm4 = xmm3[0,1],mem[0],xmm3[3] ; AVX2-NEXT: vblendps {{.*#+}} ymm3 = ymm4[0,1,2,3],ymm3[4,5,6,7] ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $134217728, %eax ## imm = 0x8000000 -; AVX2-NEXT: je LBB8_56 -; AVX2-NEXT: LBB8_55: ## %cond.load105 +; AVX2-NEXT: je LBB8_28 +; AVX2-NEXT: LBB8_60: ## %cond.load105 ; AVX2-NEXT: vinsertps $48, (%rdi), %xmm3, %xmm4 ## xmm4 = xmm3[0,1,2],mem[0] ; AVX2-NEXT: vblendps {{.*#+}} ymm3 = ymm4[0,1,2,3],ymm3[4,5,6,7] ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $268435456, %eax ## imm = 0x10000000 -; AVX2-NEXT: je LBB8_58 -; AVX2-NEXT: LBB8_57: ## %cond.load109 +; AVX2-NEXT: je LBB8_29 +; AVX2-NEXT: LBB8_61: ## %cond.load109 ; AVX2-NEXT: vbroadcastss (%rdi), %ymm4 ; AVX2-NEXT: vblendps {{.*#+}} ymm3 = ymm3[0,1,2,3],ymm4[4],ymm3[5,6,7] ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $536870912, %eax ## imm = 0x20000000 -; AVX2-NEXT: je LBB8_60 -; AVX2-NEXT: LBB8_59: ## %cond.load113 +; AVX2-NEXT: je LBB8_30 +; AVX2-NEXT: LBB8_62: ## %cond.load113 ; AVX2-NEXT: vbroadcastss (%rdi), %ymm4 ; AVX2-NEXT: vblendps {{.*#+}} ymm3 = ymm3[0,1,2,3,4],ymm4[5],ymm3[6,7] ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $1073741824, %eax ## imm = 0x40000000 -; AVX2-NEXT: je LBB8_62 -; AVX2-NEXT: LBB8_61: ## %cond.load117 +; AVX2-NEXT: je LBB8_31 +; AVX2-NEXT: LBB8_63: ## %cond.load117 ; AVX2-NEXT: vbroadcastss (%rdi), %ymm4 ; AVX2-NEXT: vblendps {{.*#+}} ymm3 = ymm3[0,1,2,3,4,5],ymm4[6],ymm3[7] ; AVX2-NEXT: addq $4, %rdi ; AVX2-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 -; AVX2-NEXT: je LBB8_64 -; AVX2-NEXT: LBB8_63: ## %cond.load121 +; AVX2-NEXT: je LBB8_32 +; AVX2-NEXT: LBB8_64: ## %cond.load121 ; AVX2-NEXT: vbroadcastss (%rdi), %ymm4 ; AVX2-NEXT: vblendps {{.*#+}} ymm3 = ymm3[0,1,2,3,4,5,6],ymm4[7] ; AVX2-NEXT: retq @@ -2689,40 +2689,40 @@ define <4 x i32> @expandload_v4i32_v4i32(ptr %base, <4 x i32> %src0, <4 x i32> % ; SSE2-NEXT: pcmpeqd %xmm1, %xmm2 ; SSE2-NEXT: movmskps %xmm2, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB10_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB10_5 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB10_3 -; SSE2-NEXT: LBB10_4: ## %else2 +; SSE2-NEXT: jne LBB10_6 +; SSE2-NEXT: LBB10_2: ## %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB10_5 -; SSE2-NEXT: LBB10_6: ## %else6 -; SSE2-NEXT: testb $8, %al ; SSE2-NEXT: jne LBB10_7 -; SSE2-NEXT: LBB10_8: ## %else10 +; SSE2-NEXT: LBB10_3: ## %else6 +; SSE2-NEXT: testb $8, %al +; SSE2-NEXT: jne LBB10_8 +; SSE2-NEXT: LBB10_4: ## %else10 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB10_1: ## %cond.load +; SSE2-NEXT: LBB10_5: ## %cond.load ; SSE2-NEXT: movss (%rdi), %xmm1 ## xmm1 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB10_4 -; SSE2-NEXT: LBB10_3: ## %cond.load1 +; SSE2-NEXT: je LBB10_2 +; SSE2-NEXT: LBB10_6: ## %cond.load1 ; SSE2-NEXT: movss (%rdi), %xmm1 ## xmm1 = mem[0],zero,zero,zero ; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3] ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB10_6 -; SSE2-NEXT: LBB10_5: ## %cond.load5 +; SSE2-NEXT: je LBB10_3 +; SSE2-NEXT: LBB10_7: ## %cond.load5 ; SSE2-NEXT: movss (%rdi), %xmm1 ## xmm1 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2] ; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB10_8 -; SSE2-NEXT: LBB10_7: ## %cond.load9 +; SSE2-NEXT: je LBB10_4 +; SSE2-NEXT: LBB10_8: ## %cond.load9 ; SSE2-NEXT: movss (%rdi), %xmm1 ## xmm1 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0] @@ -2734,34 +2734,34 @@ define <4 x i32> @expandload_v4i32_v4i32(ptr %base, <4 x i32> %src0, <4 x i32> % ; SSE42-NEXT: pcmpeqd %xmm1, %xmm2 ; SSE42-NEXT: movmskps %xmm2, %eax ; SSE42-NEXT: testb $1, %al -; SSE42-NEXT: jne LBB10_1 -; SSE42-NEXT: ## %bb.2: ## %else +; SSE42-NEXT: jne LBB10_5 +; SSE42-NEXT: ## %bb.1: ## %else ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: jne LBB10_3 -; SSE42-NEXT: LBB10_4: ## %else2 +; SSE42-NEXT: jne LBB10_6 +; SSE42-NEXT: LBB10_2: ## %else2 ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: jne LBB10_5 -; SSE42-NEXT: LBB10_6: ## %else6 -; SSE42-NEXT: testb $8, %al ; SSE42-NEXT: jne LBB10_7 -; SSE42-NEXT: LBB10_8: ## %else10 +; SSE42-NEXT: LBB10_3: ## %else6 +; SSE42-NEXT: testb $8, %al +; SSE42-NEXT: jne LBB10_8 +; SSE42-NEXT: LBB10_4: ## %else10 ; SSE42-NEXT: retq -; SSE42-NEXT: LBB10_1: ## %cond.load +; SSE42-NEXT: LBB10_5: ## %cond.load ; SSE42-NEXT: pinsrd $0, (%rdi), %xmm0 ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: je LBB10_4 -; SSE42-NEXT: LBB10_3: ## %cond.load1 +; SSE42-NEXT: je LBB10_2 +; SSE42-NEXT: LBB10_6: ## %cond.load1 ; SSE42-NEXT: pinsrd $1, (%rdi), %xmm0 ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: je LBB10_6 -; SSE42-NEXT: LBB10_5: ## %cond.load5 +; SSE42-NEXT: je LBB10_3 +; SSE42-NEXT: LBB10_7: ## %cond.load5 ; SSE42-NEXT: pinsrd $2, (%rdi), %xmm0 ; SSE42-NEXT: addq $4, %rdi ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: je LBB10_8 -; SSE42-NEXT: LBB10_7: ## %cond.load9 +; SSE42-NEXT: je LBB10_4 +; SSE42-NEXT: LBB10_8: ## %cond.load9 ; SSE42-NEXT: pinsrd $3, (%rdi), %xmm0 ; SSE42-NEXT: retq ; @@ -2771,34 +2771,34 @@ define <4 x i32> @expandload_v4i32_v4i32(ptr %base, <4 x i32> %src0, <4 x i32> % ; AVX1OR2-NEXT: vpcmpeqd %xmm2, %xmm1, %xmm1 ; AVX1OR2-NEXT: vmovmskps %xmm1, %eax ; AVX1OR2-NEXT: testb $1, %al -; AVX1OR2-NEXT: jne LBB10_1 -; AVX1OR2-NEXT: ## %bb.2: ## %else +; AVX1OR2-NEXT: jne LBB10_5 +; AVX1OR2-NEXT: ## %bb.1: ## %else ; AVX1OR2-NEXT: testb $2, %al -; AVX1OR2-NEXT: jne LBB10_3 -; AVX1OR2-NEXT: LBB10_4: ## %else2 +; AVX1OR2-NEXT: jne LBB10_6 +; AVX1OR2-NEXT: LBB10_2: ## %else2 ; AVX1OR2-NEXT: testb $4, %al -; AVX1OR2-NEXT: jne LBB10_5 -; AVX1OR2-NEXT: LBB10_6: ## %else6 -; AVX1OR2-NEXT: testb $8, %al ; AVX1OR2-NEXT: jne LBB10_7 -; AVX1OR2-NEXT: LBB10_8: ## %else10 +; AVX1OR2-NEXT: LBB10_3: ## %else6 +; AVX1OR2-NEXT: testb $8, %al +; AVX1OR2-NEXT: jne LBB10_8 +; AVX1OR2-NEXT: LBB10_4: ## %else10 ; AVX1OR2-NEXT: retq -; AVX1OR2-NEXT: LBB10_1: ## %cond.load +; AVX1OR2-NEXT: LBB10_5: ## %cond.load ; AVX1OR2-NEXT: vpinsrd $0, (%rdi), %xmm0, %xmm0 ; AVX1OR2-NEXT: addq $4, %rdi ; AVX1OR2-NEXT: testb $2, %al -; AVX1OR2-NEXT: je LBB10_4 -; AVX1OR2-NEXT: LBB10_3: ## %cond.load1 +; AVX1OR2-NEXT: je LBB10_2 +; AVX1OR2-NEXT: LBB10_6: ## %cond.load1 ; AVX1OR2-NEXT: vpinsrd $1, (%rdi), %xmm0, %xmm0 ; AVX1OR2-NEXT: addq $4, %rdi ; AVX1OR2-NEXT: testb $4, %al -; AVX1OR2-NEXT: je LBB10_6 -; AVX1OR2-NEXT: LBB10_5: ## %cond.load5 +; AVX1OR2-NEXT: je LBB10_3 +; AVX1OR2-NEXT: LBB10_7: ## %cond.load5 ; AVX1OR2-NEXT: vpinsrd $2, (%rdi), %xmm0, %xmm0 ; AVX1OR2-NEXT: addq $4, %rdi ; AVX1OR2-NEXT: testb $8, %al -; AVX1OR2-NEXT: je LBB10_8 -; AVX1OR2-NEXT: LBB10_7: ## %cond.load9 +; AVX1OR2-NEXT: je LBB10_4 +; AVX1OR2-NEXT: LBB10_8: ## %cond.load9 ; AVX1OR2-NEXT: vpinsrd $3, (%rdi), %xmm0, %xmm0 ; AVX1OR2-NEXT: retq ; @@ -2836,66 +2836,66 @@ define <8 x i16> @expandload_v8i16_v8i16(ptr %base, <8 x i16> %src0, <8 x i16> % ; SSE-NEXT: packsswb %xmm2, %xmm2 ; SSE-NEXT: pmovmskb %xmm2, %eax ; SSE-NEXT: testb $1, %al -; SSE-NEXT: jne LBB11_1 -; SSE-NEXT: ## %bb.2: ## %else +; SSE-NEXT: jne LBB11_9 +; SSE-NEXT: ## %bb.1: ## %else ; SSE-NEXT: testb $2, %al -; SSE-NEXT: jne LBB11_3 -; SSE-NEXT: LBB11_4: ## %else2 +; SSE-NEXT: jne LBB11_10 +; SSE-NEXT: LBB11_2: ## %else2 ; SSE-NEXT: testb $4, %al -; SSE-NEXT: jne LBB11_5 -; SSE-NEXT: LBB11_6: ## %else6 +; SSE-NEXT: jne LBB11_11 +; SSE-NEXT: LBB11_3: ## %else6 ; SSE-NEXT: testb $8, %al -; SSE-NEXT: jne LBB11_7 -; SSE-NEXT: LBB11_8: ## %else10 +; SSE-NEXT: jne LBB11_12 +; SSE-NEXT: LBB11_4: ## %else10 ; SSE-NEXT: testb $16, %al -; SSE-NEXT: jne LBB11_9 -; SSE-NEXT: LBB11_10: ## %else14 +; SSE-NEXT: jne LBB11_13 +; SSE-NEXT: LBB11_5: ## %else14 ; SSE-NEXT: testb $32, %al -; SSE-NEXT: jne LBB11_11 -; SSE-NEXT: LBB11_12: ## %else18 +; SSE-NEXT: jne LBB11_14 +; SSE-NEXT: LBB11_6: ## %else18 ; SSE-NEXT: testb $64, %al -; SSE-NEXT: jne LBB11_13 -; SSE-NEXT: LBB11_14: ## %else22 -; SSE-NEXT: testb $-128, %al ; SSE-NEXT: jne LBB11_15 -; SSE-NEXT: LBB11_16: ## %else26 +; SSE-NEXT: LBB11_7: ## %else22 +; SSE-NEXT: testb $-128, %al +; SSE-NEXT: jne LBB11_16 +; SSE-NEXT: LBB11_8: ## %else26 ; SSE-NEXT: retq -; SSE-NEXT: LBB11_1: ## %cond.load +; SSE-NEXT: LBB11_9: ## %cond.load ; SSE-NEXT: pinsrw $0, (%rdi), %xmm0 ; SSE-NEXT: addq $2, %rdi ; SSE-NEXT: testb $2, %al -; SSE-NEXT: je LBB11_4 -; SSE-NEXT: LBB11_3: ## %cond.load1 +; SSE-NEXT: je LBB11_2 +; SSE-NEXT: LBB11_10: ## %cond.load1 ; SSE-NEXT: pinsrw $1, (%rdi), %xmm0 ; SSE-NEXT: addq $2, %rdi ; SSE-NEXT: testb $4, %al -; SSE-NEXT: je LBB11_6 -; SSE-NEXT: LBB11_5: ## %cond.load5 +; SSE-NEXT: je LBB11_3 +; SSE-NEXT: LBB11_11: ## %cond.load5 ; SSE-NEXT: pinsrw $2, (%rdi), %xmm0 ; SSE-NEXT: addq $2, %rdi ; SSE-NEXT: testb $8, %al -; SSE-NEXT: je LBB11_8 -; SSE-NEXT: LBB11_7: ## %cond.load9 +; SSE-NEXT: je LBB11_4 +; SSE-NEXT: LBB11_12: ## %cond.load9 ; SSE-NEXT: pinsrw $3, (%rdi), %xmm0 ; SSE-NEXT: addq $2, %rdi ; SSE-NEXT: testb $16, %al -; SSE-NEXT: je LBB11_10 -; SSE-NEXT: LBB11_9: ## %cond.load13 +; SSE-NEXT: je LBB11_5 +; SSE-NEXT: LBB11_13: ## %cond.load13 ; SSE-NEXT: pinsrw $4, (%rdi), %xmm0 ; SSE-NEXT: addq $2, %rdi ; SSE-NEXT: testb $32, %al -; SSE-NEXT: je LBB11_12 -; SSE-NEXT: LBB11_11: ## %cond.load17 +; SSE-NEXT: je LBB11_6 +; SSE-NEXT: LBB11_14: ## %cond.load17 ; SSE-NEXT: pinsrw $5, (%rdi), %xmm0 ; SSE-NEXT: addq $2, %rdi ; SSE-NEXT: testb $64, %al -; SSE-NEXT: je LBB11_14 -; SSE-NEXT: LBB11_13: ## %cond.load21 +; SSE-NEXT: je LBB11_7 +; SSE-NEXT: LBB11_15: ## %cond.load21 ; SSE-NEXT: pinsrw $6, (%rdi), %xmm0 ; SSE-NEXT: addq $2, %rdi ; SSE-NEXT: testb $-128, %al -; SSE-NEXT: je LBB11_16 -; SSE-NEXT: LBB11_15: ## %cond.load25 +; SSE-NEXT: je LBB11_8 +; SSE-NEXT: LBB11_16: ## %cond.load25 ; SSE-NEXT: pinsrw $7, (%rdi), %xmm0 ; SSE-NEXT: retq ; @@ -2906,66 +2906,66 @@ define <8 x i16> @expandload_v8i16_v8i16(ptr %base, <8 x i16> %src0, <8 x i16> % ; AVX1OR2-NEXT: vpacksswb %xmm1, %xmm1, %xmm1 ; AVX1OR2-NEXT: vpmovmskb %xmm1, %eax ; AVX1OR2-NEXT: testb $1, %al -; AVX1OR2-NEXT: jne LBB11_1 -; AVX1OR2-NEXT: ## %bb.2: ## %else +; AVX1OR2-NEXT: jne LBB11_9 +; AVX1OR2-NEXT: ## %bb.1: ## %else ; AVX1OR2-NEXT: testb $2, %al -; AVX1OR2-NEXT: jne LBB11_3 -; AVX1OR2-NEXT: LBB11_4: ## %else2 +; AVX1OR2-NEXT: jne LBB11_10 +; AVX1OR2-NEXT: LBB11_2: ## %else2 ; AVX1OR2-NEXT: testb $4, %al -; AVX1OR2-NEXT: jne LBB11_5 -; AVX1OR2-NEXT: LBB11_6: ## %else6 +; AVX1OR2-NEXT: jne LBB11_11 +; AVX1OR2-NEXT: LBB11_3: ## %else6 ; AVX1OR2-NEXT: testb $8, %al -; AVX1OR2-NEXT: jne LBB11_7 -; AVX1OR2-NEXT: LBB11_8: ## %else10 +; AVX1OR2-NEXT: jne LBB11_12 +; AVX1OR2-NEXT: LBB11_4: ## %else10 ; AVX1OR2-NEXT: testb $16, %al -; AVX1OR2-NEXT: jne LBB11_9 -; AVX1OR2-NEXT: LBB11_10: ## %else14 +; AVX1OR2-NEXT: jne LBB11_13 +; AVX1OR2-NEXT: LBB11_5: ## %else14 ; AVX1OR2-NEXT: testb $32, %al -; AVX1OR2-NEXT: jne LBB11_11 -; AVX1OR2-NEXT: LBB11_12: ## %else18 +; AVX1OR2-NEXT: jne LBB11_14 +; AVX1OR2-NEXT: LBB11_6: ## %else18 ; AVX1OR2-NEXT: testb $64, %al -; AVX1OR2-NEXT: jne LBB11_13 -; AVX1OR2-NEXT: LBB11_14: ## %else22 -; AVX1OR2-NEXT: testb $-128, %al ; AVX1OR2-NEXT: jne LBB11_15 -; AVX1OR2-NEXT: LBB11_16: ## %else26 +; AVX1OR2-NEXT: LBB11_7: ## %else22 +; AVX1OR2-NEXT: testb $-128, %al +; AVX1OR2-NEXT: jne LBB11_16 +; AVX1OR2-NEXT: LBB11_8: ## %else26 ; AVX1OR2-NEXT: retq -; AVX1OR2-NEXT: LBB11_1: ## %cond.load +; AVX1OR2-NEXT: LBB11_9: ## %cond.load ; AVX1OR2-NEXT: vpinsrw $0, (%rdi), %xmm0, %xmm0 ; AVX1OR2-NEXT: addq $2, %rdi ; AVX1OR2-NEXT: testb $2, %al -; AVX1OR2-NEXT: je LBB11_4 -; AVX1OR2-NEXT: LBB11_3: ## %cond.load1 +; AVX1OR2-NEXT: je LBB11_2 +; AVX1OR2-NEXT: LBB11_10: ## %cond.load1 ; AVX1OR2-NEXT: vpinsrw $1, (%rdi), %xmm0, %xmm0 ; AVX1OR2-NEXT: addq $2, %rdi ; AVX1OR2-NEXT: testb $4, %al -; AVX1OR2-NEXT: je LBB11_6 -; AVX1OR2-NEXT: LBB11_5: ## %cond.load5 +; AVX1OR2-NEXT: je LBB11_3 +; AVX1OR2-NEXT: LBB11_11: ## %cond.load5 ; AVX1OR2-NEXT: vpinsrw $2, (%rdi), %xmm0, %xmm0 ; AVX1OR2-NEXT: addq $2, %rdi ; AVX1OR2-NEXT: testb $8, %al -; AVX1OR2-NEXT: je LBB11_8 -; AVX1OR2-NEXT: LBB11_7: ## %cond.load9 +; AVX1OR2-NEXT: je LBB11_4 +; AVX1OR2-NEXT: LBB11_12: ## %cond.load9 ; AVX1OR2-NEXT: vpinsrw $3, (%rdi), %xmm0, %xmm0 ; AVX1OR2-NEXT: addq $2, %rdi ; AVX1OR2-NEXT: testb $16, %al -; AVX1OR2-NEXT: je LBB11_10 -; AVX1OR2-NEXT: LBB11_9: ## %cond.load13 +; AVX1OR2-NEXT: je LBB11_5 +; AVX1OR2-NEXT: LBB11_13: ## %cond.load13 ; AVX1OR2-NEXT: vpinsrw $4, (%rdi), %xmm0, %xmm0 ; AVX1OR2-NEXT: addq $2, %rdi ; AVX1OR2-NEXT: testb $32, %al -; AVX1OR2-NEXT: je LBB11_12 -; AVX1OR2-NEXT: LBB11_11: ## %cond.load17 +; AVX1OR2-NEXT: je LBB11_6 +; AVX1OR2-NEXT: LBB11_14: ## %cond.load17 ; AVX1OR2-NEXT: vpinsrw $5, (%rdi), %xmm0, %xmm0 ; AVX1OR2-NEXT: addq $2, %rdi ; AVX1OR2-NEXT: testb $64, %al -; AVX1OR2-NEXT: je LBB11_14 -; AVX1OR2-NEXT: LBB11_13: ## %cond.load21 +; AVX1OR2-NEXT: je LBB11_7 +; AVX1OR2-NEXT: LBB11_15: ## %cond.load21 ; AVX1OR2-NEXT: vpinsrw $6, (%rdi), %xmm0, %xmm0 ; AVX1OR2-NEXT: addq $2, %rdi ; AVX1OR2-NEXT: testb $-128, %al -; AVX1OR2-NEXT: je LBB11_16 -; AVX1OR2-NEXT: LBB11_15: ## %cond.load25 +; AVX1OR2-NEXT: je LBB11_8 +; AVX1OR2-NEXT: LBB11_16: ## %cond.load25 ; AVX1OR2-NEXT: vpinsrw $7, (%rdi), %xmm0, %xmm0 ; AVX1OR2-NEXT: retq ; @@ -2977,67 +2977,67 @@ define <8 x i16> @expandload_v8i16_v8i16(ptr %base, <8 x i16> %src0, <8 x i16> % ; AVX512F-NEXT: vptestmq %zmm1, %zmm1, %k0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne LBB11_1 -; AVX512F-NEXT: ## %bb.2: ## %else +; AVX512F-NEXT: jne LBB11_9 +; AVX512F-NEXT: ## %bb.1: ## %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne LBB11_3 -; AVX512F-NEXT: LBB11_4: ## %else2 +; AVX512F-NEXT: jne LBB11_10 +; AVX512F-NEXT: LBB11_2: ## %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne LBB11_5 -; AVX512F-NEXT: LBB11_6: ## %else6 +; AVX512F-NEXT: jne LBB11_11 +; AVX512F-NEXT: LBB11_3: ## %else6 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne LBB11_7 -; AVX512F-NEXT: LBB11_8: ## %else10 +; AVX512F-NEXT: jne LBB11_12 +; AVX512F-NEXT: LBB11_4: ## %else10 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne LBB11_9 -; AVX512F-NEXT: LBB11_10: ## %else14 +; AVX512F-NEXT: jne LBB11_13 +; AVX512F-NEXT: LBB11_5: ## %else14 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne LBB11_11 -; AVX512F-NEXT: LBB11_12: ## %else18 +; AVX512F-NEXT: jne LBB11_14 +; AVX512F-NEXT: LBB11_6: ## %else18 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne LBB11_13 -; AVX512F-NEXT: LBB11_14: ## %else22 -; AVX512F-NEXT: testb $-128, %al ; AVX512F-NEXT: jne LBB11_15 -; AVX512F-NEXT: LBB11_16: ## %else26 +; AVX512F-NEXT: LBB11_7: ## %else22 +; AVX512F-NEXT: testb $-128, %al +; AVX512F-NEXT: jne LBB11_16 +; AVX512F-NEXT: LBB11_8: ## %else26 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: LBB11_1: ## %cond.load +; AVX512F-NEXT: LBB11_9: ## %cond.load ; AVX512F-NEXT: vpinsrw $0, (%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: addq $2, %rdi ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je LBB11_4 -; AVX512F-NEXT: LBB11_3: ## %cond.load1 +; AVX512F-NEXT: je LBB11_2 +; AVX512F-NEXT: LBB11_10: ## %cond.load1 ; AVX512F-NEXT: vpinsrw $1, (%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: addq $2, %rdi ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je LBB11_6 -; AVX512F-NEXT: LBB11_5: ## %cond.load5 +; AVX512F-NEXT: je LBB11_3 +; AVX512F-NEXT: LBB11_11: ## %cond.load5 ; AVX512F-NEXT: vpinsrw $2, (%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: addq $2, %rdi ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je LBB11_8 -; AVX512F-NEXT: LBB11_7: ## %cond.load9 +; AVX512F-NEXT: je LBB11_4 +; AVX512F-NEXT: LBB11_12: ## %cond.load9 ; AVX512F-NEXT: vpinsrw $3, (%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: addq $2, %rdi ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je LBB11_10 -; AVX512F-NEXT: LBB11_9: ## %cond.load13 +; AVX512F-NEXT: je LBB11_5 +; AVX512F-NEXT: LBB11_13: ## %cond.load13 ; AVX512F-NEXT: vpinsrw $4, (%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: addq $2, %rdi ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je LBB11_12 -; AVX512F-NEXT: LBB11_11: ## %cond.load17 +; AVX512F-NEXT: je LBB11_6 +; AVX512F-NEXT: LBB11_14: ## %cond.load17 ; AVX512F-NEXT: vpinsrw $5, (%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: addq $2, %rdi ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je LBB11_14 -; AVX512F-NEXT: LBB11_13: ## %cond.load21 +; AVX512F-NEXT: je LBB11_7 +; AVX512F-NEXT: LBB11_15: ## %cond.load21 ; AVX512F-NEXT: vpinsrw $6, (%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: addq $2, %rdi ; AVX512F-NEXT: testb $-128, %al -; AVX512F-NEXT: je LBB11_16 -; AVX512F-NEXT: LBB11_15: ## %cond.load25 +; AVX512F-NEXT: je LBB11_8 +; AVX512F-NEXT: LBB11_16: ## %cond.load25 ; AVX512F-NEXT: vpinsrw $7, (%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -3049,67 +3049,67 @@ define <8 x i16> @expandload_v8i16_v8i16(ptr %base, <8 x i16> %src0, <8 x i16> % ; AVX512VLDQ-NEXT: vpmovsxwd %xmm1, %ymm1 ; AVX512VLDQ-NEXT: vmovmskps %ymm1, %eax ; AVX512VLDQ-NEXT: testb $1, %al -; AVX512VLDQ-NEXT: jne LBB11_1 -; AVX512VLDQ-NEXT: ## %bb.2: ## %else +; AVX512VLDQ-NEXT: jne LBB11_9 +; AVX512VLDQ-NEXT: ## %bb.1: ## %else ; AVX512VLDQ-NEXT: testb $2, %al -; AVX512VLDQ-NEXT: jne LBB11_3 -; AVX512VLDQ-NEXT: LBB11_4: ## %else2 +; AVX512VLDQ-NEXT: jne LBB11_10 +; AVX512VLDQ-NEXT: LBB11_2: ## %else2 ; AVX512VLDQ-NEXT: testb $4, %al -; AVX512VLDQ-NEXT: jne LBB11_5 -; AVX512VLDQ-NEXT: LBB11_6: ## %else6 +; AVX512VLDQ-NEXT: jne LBB11_11 +; AVX512VLDQ-NEXT: LBB11_3: ## %else6 ; AVX512VLDQ-NEXT: testb $8, %al -; AVX512VLDQ-NEXT: jne LBB11_7 -; AVX512VLDQ-NEXT: LBB11_8: ## %else10 +; AVX512VLDQ-NEXT: jne LBB11_12 +; AVX512VLDQ-NEXT: LBB11_4: ## %else10 ; AVX512VLDQ-NEXT: testb $16, %al -; AVX512VLDQ-NEXT: jne LBB11_9 -; AVX512VLDQ-NEXT: LBB11_10: ## %else14 +; AVX512VLDQ-NEXT: jne LBB11_13 +; AVX512VLDQ-NEXT: LBB11_5: ## %else14 ; AVX512VLDQ-NEXT: testb $32, %al -; AVX512VLDQ-NEXT: jne LBB11_11 -; AVX512VLDQ-NEXT: LBB11_12: ## %else18 +; AVX512VLDQ-NEXT: jne LBB11_14 +; AVX512VLDQ-NEXT: LBB11_6: ## %else18 ; AVX512VLDQ-NEXT: testb $64, %al -; AVX512VLDQ-NEXT: jne LBB11_13 -; AVX512VLDQ-NEXT: LBB11_14: ## %else22 -; AVX512VLDQ-NEXT: testb $-128, %al ; AVX512VLDQ-NEXT: jne LBB11_15 -; AVX512VLDQ-NEXT: LBB11_16: ## %else26 +; AVX512VLDQ-NEXT: LBB11_7: ## %else22 +; AVX512VLDQ-NEXT: testb $-128, %al +; AVX512VLDQ-NEXT: jne LBB11_16 +; AVX512VLDQ-NEXT: LBB11_8: ## %else26 ; AVX512VLDQ-NEXT: vzeroupper ; AVX512VLDQ-NEXT: retq -; AVX512VLDQ-NEXT: LBB11_1: ## %cond.load +; AVX512VLDQ-NEXT: LBB11_9: ## %cond.load ; AVX512VLDQ-NEXT: vpinsrw $0, (%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: addq $2, %rdi ; AVX512VLDQ-NEXT: testb $2, %al -; AVX512VLDQ-NEXT: je LBB11_4 -; AVX512VLDQ-NEXT: LBB11_3: ## %cond.load1 +; AVX512VLDQ-NEXT: je LBB11_2 +; AVX512VLDQ-NEXT: LBB11_10: ## %cond.load1 ; AVX512VLDQ-NEXT: vpinsrw $1, (%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: addq $2, %rdi ; AVX512VLDQ-NEXT: testb $4, %al -; AVX512VLDQ-NEXT: je LBB11_6 -; AVX512VLDQ-NEXT: LBB11_5: ## %cond.load5 +; AVX512VLDQ-NEXT: je LBB11_3 +; AVX512VLDQ-NEXT: LBB11_11: ## %cond.load5 ; AVX512VLDQ-NEXT: vpinsrw $2, (%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: addq $2, %rdi ; AVX512VLDQ-NEXT: testb $8, %al -; AVX512VLDQ-NEXT: je LBB11_8 -; AVX512VLDQ-NEXT: LBB11_7: ## %cond.load9 +; AVX512VLDQ-NEXT: je LBB11_4 +; AVX512VLDQ-NEXT: LBB11_12: ## %cond.load9 ; AVX512VLDQ-NEXT: vpinsrw $3, (%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: addq $2, %rdi ; AVX512VLDQ-NEXT: testb $16, %al -; AVX512VLDQ-NEXT: je LBB11_10 -; AVX512VLDQ-NEXT: LBB11_9: ## %cond.load13 +; AVX512VLDQ-NEXT: je LBB11_5 +; AVX512VLDQ-NEXT: LBB11_13: ## %cond.load13 ; AVX512VLDQ-NEXT: vpinsrw $4, (%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: addq $2, %rdi ; AVX512VLDQ-NEXT: testb $32, %al -; AVX512VLDQ-NEXT: je LBB11_12 -; AVX512VLDQ-NEXT: LBB11_11: ## %cond.load17 +; AVX512VLDQ-NEXT: je LBB11_6 +; AVX512VLDQ-NEXT: LBB11_14: ## %cond.load17 ; AVX512VLDQ-NEXT: vpinsrw $5, (%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: addq $2, %rdi ; AVX512VLDQ-NEXT: testb $64, %al -; AVX512VLDQ-NEXT: je LBB11_14 -; AVX512VLDQ-NEXT: LBB11_13: ## %cond.load21 +; AVX512VLDQ-NEXT: je LBB11_7 +; AVX512VLDQ-NEXT: LBB11_15: ## %cond.load21 ; AVX512VLDQ-NEXT: vpinsrw $6, (%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: addq $2, %rdi ; AVX512VLDQ-NEXT: testb $-128, %al -; AVX512VLDQ-NEXT: je LBB11_16 -; AVX512VLDQ-NEXT: LBB11_15: ## %cond.load25 +; AVX512VLDQ-NEXT: je LBB11_8 +; AVX512VLDQ-NEXT: LBB11_16: ## %cond.load25 ; AVX512VLDQ-NEXT: vpinsrw $7, (%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: vzeroupper ; AVX512VLDQ-NEXT: retq @@ -3119,66 +3119,66 @@ define <8 x i16> @expandload_v8i16_v8i16(ptr %base, <8 x i16> %src0, <8 x i16> % ; AVX512VLBW-NEXT: vptestnmw %xmm1, %xmm1, %k0 ; AVX512VLBW-NEXT: kmovd %k0, %eax ; AVX512VLBW-NEXT: testb $1, %al -; AVX512VLBW-NEXT: jne LBB11_1 -; AVX512VLBW-NEXT: ## %bb.2: ## %else +; AVX512VLBW-NEXT: jne LBB11_9 +; AVX512VLBW-NEXT: ## %bb.1: ## %else ; AVX512VLBW-NEXT: testb $2, %al -; AVX512VLBW-NEXT: jne LBB11_3 -; AVX512VLBW-NEXT: LBB11_4: ## %else2 +; AVX512VLBW-NEXT: jne LBB11_10 +; AVX512VLBW-NEXT: LBB11_2: ## %else2 ; AVX512VLBW-NEXT: testb $4, %al -; AVX512VLBW-NEXT: jne LBB11_5 -; AVX512VLBW-NEXT: LBB11_6: ## %else6 +; AVX512VLBW-NEXT: jne LBB11_11 +; AVX512VLBW-NEXT: LBB11_3: ## %else6 ; AVX512VLBW-NEXT: testb $8, %al -; AVX512VLBW-NEXT: jne LBB11_7 -; AVX512VLBW-NEXT: LBB11_8: ## %else10 +; AVX512VLBW-NEXT: jne LBB11_12 +; AVX512VLBW-NEXT: LBB11_4: ## %else10 ; AVX512VLBW-NEXT: testb $16, %al -; AVX512VLBW-NEXT: jne LBB11_9 -; AVX512VLBW-NEXT: LBB11_10: ## %else14 +; AVX512VLBW-NEXT: jne LBB11_13 +; AVX512VLBW-NEXT: LBB11_5: ## %else14 ; AVX512VLBW-NEXT: testb $32, %al -; AVX512VLBW-NEXT: jne LBB11_11 -; AVX512VLBW-NEXT: LBB11_12: ## %else18 +; AVX512VLBW-NEXT: jne LBB11_14 +; AVX512VLBW-NEXT: LBB11_6: ## %else18 ; AVX512VLBW-NEXT: testb $64, %al -; AVX512VLBW-NEXT: jne LBB11_13 -; AVX512VLBW-NEXT: LBB11_14: ## %else22 -; AVX512VLBW-NEXT: testb $-128, %al ; AVX512VLBW-NEXT: jne LBB11_15 -; AVX512VLBW-NEXT: LBB11_16: ## %else26 +; AVX512VLBW-NEXT: LBB11_7: ## %else22 +; AVX512VLBW-NEXT: testb $-128, %al +; AVX512VLBW-NEXT: jne LBB11_16 +; AVX512VLBW-NEXT: LBB11_8: ## %else26 ; AVX512VLBW-NEXT: retq -; AVX512VLBW-NEXT: LBB11_1: ## %cond.load +; AVX512VLBW-NEXT: LBB11_9: ## %cond.load ; AVX512VLBW-NEXT: vpinsrw $0, (%rdi), %xmm0, %xmm0 ; AVX512VLBW-NEXT: addq $2, %rdi ; AVX512VLBW-NEXT: testb $2, %al -; AVX512VLBW-NEXT: je LBB11_4 -; AVX512VLBW-NEXT: LBB11_3: ## %cond.load1 +; AVX512VLBW-NEXT: je LBB11_2 +; AVX512VLBW-NEXT: LBB11_10: ## %cond.load1 ; AVX512VLBW-NEXT: vpinsrw $1, (%rdi), %xmm0, %xmm0 ; AVX512VLBW-NEXT: addq $2, %rdi ; AVX512VLBW-NEXT: testb $4, %al -; AVX512VLBW-NEXT: je LBB11_6 -; AVX512VLBW-NEXT: LBB11_5: ## %cond.load5 +; AVX512VLBW-NEXT: je LBB11_3 +; AVX512VLBW-NEXT: LBB11_11: ## %cond.load5 ; AVX512VLBW-NEXT: vpinsrw $2, (%rdi), %xmm0, %xmm0 ; AVX512VLBW-NEXT: addq $2, %rdi ; AVX512VLBW-NEXT: testb $8, %al -; AVX512VLBW-NEXT: je LBB11_8 -; AVX512VLBW-NEXT: LBB11_7: ## %cond.load9 +; AVX512VLBW-NEXT: je LBB11_4 +; AVX512VLBW-NEXT: LBB11_12: ## %cond.load9 ; AVX512VLBW-NEXT: vpinsrw $3, (%rdi), %xmm0, %xmm0 ; AVX512VLBW-NEXT: addq $2, %rdi ; AVX512VLBW-NEXT: testb $16, %al -; AVX512VLBW-NEXT: je LBB11_10 -; AVX512VLBW-NEXT: LBB11_9: ## %cond.load13 +; AVX512VLBW-NEXT: je LBB11_5 +; AVX512VLBW-NEXT: LBB11_13: ## %cond.load13 ; AVX512VLBW-NEXT: vpinsrw $4, (%rdi), %xmm0, %xmm0 ; AVX512VLBW-NEXT: addq $2, %rdi ; AVX512VLBW-NEXT: testb $32, %al -; AVX512VLBW-NEXT: je LBB11_12 -; AVX512VLBW-NEXT: LBB11_11: ## %cond.load17 +; AVX512VLBW-NEXT: je LBB11_6 +; AVX512VLBW-NEXT: LBB11_14: ## %cond.load17 ; AVX512VLBW-NEXT: vpinsrw $5, (%rdi), %xmm0, %xmm0 ; AVX512VLBW-NEXT: addq $2, %rdi ; AVX512VLBW-NEXT: testb $64, %al -; AVX512VLBW-NEXT: je LBB11_14 -; AVX512VLBW-NEXT: LBB11_13: ## %cond.load21 +; AVX512VLBW-NEXT: je LBB11_7 +; AVX512VLBW-NEXT: LBB11_15: ## %cond.load21 ; AVX512VLBW-NEXT: vpinsrw $6, (%rdi), %xmm0, %xmm0 ; AVX512VLBW-NEXT: addq $2, %rdi ; AVX512VLBW-NEXT: testb $-128, %al -; AVX512VLBW-NEXT: je LBB11_16 -; AVX512VLBW-NEXT: LBB11_15: ## %cond.load25 +; AVX512VLBW-NEXT: je LBB11_8 +; AVX512VLBW-NEXT: LBB11_16: ## %cond.load25 ; AVX512VLBW-NEXT: vpinsrw $7, (%rdi), %xmm0, %xmm0 ; AVX512VLBW-NEXT: retq %mask = icmp eq <8 x i16> %trigger, zeroinitializer @@ -3197,55 +3197,55 @@ define <16 x i8> @expandload_v16i8_v16i8(ptr %base, <16 x i8> %src0, <16 x i8> % ; SSE2-NEXT: pcmpeqb %xmm1, %xmm2 ; SSE2-NEXT: pmovmskb %xmm2, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB12_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB12_17 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB12_3 -; SSE2-NEXT: LBB12_4: ## %else2 +; SSE2-NEXT: jne LBB12_18 +; SSE2-NEXT: LBB12_2: ## %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB12_5 -; SSE2-NEXT: LBB12_6: ## %else6 +; SSE2-NEXT: jne LBB12_19 +; SSE2-NEXT: LBB12_3: ## %else6 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne LBB12_7 -; SSE2-NEXT: LBB12_8: ## %else10 +; SSE2-NEXT: jne LBB12_20 +; SSE2-NEXT: LBB12_4: ## %else10 ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: jne LBB12_9 -; SSE2-NEXT: LBB12_10: ## %else14 +; SSE2-NEXT: jne LBB12_21 +; SSE2-NEXT: LBB12_5: ## %else14 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: jne LBB12_11 -; SSE2-NEXT: LBB12_12: ## %else18 +; SSE2-NEXT: jne LBB12_22 +; SSE2-NEXT: LBB12_6: ## %else18 ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: jne LBB12_13 -; SSE2-NEXT: LBB12_14: ## %else22 +; SSE2-NEXT: jne LBB12_23 +; SSE2-NEXT: LBB12_7: ## %else22 ; SSE2-NEXT: testb %al, %al -; SSE2-NEXT: js LBB12_15 -; SSE2-NEXT: LBB12_16: ## %else26 +; SSE2-NEXT: js LBB12_24 +; SSE2-NEXT: LBB12_8: ## %else26 ; SSE2-NEXT: testl $256, %eax ## imm = 0x100 -; SSE2-NEXT: jne LBB12_17 -; SSE2-NEXT: LBB12_18: ## %else30 +; SSE2-NEXT: jne LBB12_25 +; SSE2-NEXT: LBB12_9: ## %else30 ; SSE2-NEXT: testl $512, %eax ## imm = 0x200 -; SSE2-NEXT: jne LBB12_19 -; SSE2-NEXT: LBB12_20: ## %else34 +; SSE2-NEXT: jne LBB12_26 +; SSE2-NEXT: LBB12_10: ## %else34 ; SSE2-NEXT: testl $1024, %eax ## imm = 0x400 -; SSE2-NEXT: jne LBB12_21 -; SSE2-NEXT: LBB12_22: ## %else38 +; SSE2-NEXT: jne LBB12_27 +; SSE2-NEXT: LBB12_11: ## %else38 ; SSE2-NEXT: testl $2048, %eax ## imm = 0x800 -; SSE2-NEXT: jne LBB12_23 -; SSE2-NEXT: LBB12_24: ## %else42 +; SSE2-NEXT: jne LBB12_28 +; SSE2-NEXT: LBB12_12: ## %else42 ; SSE2-NEXT: testl $4096, %eax ## imm = 0x1000 -; SSE2-NEXT: jne LBB12_25 -; SSE2-NEXT: LBB12_26: ## %else46 +; SSE2-NEXT: jne LBB12_29 +; SSE2-NEXT: LBB12_13: ## %else46 ; SSE2-NEXT: testl $8192, %eax ## imm = 0x2000 -; SSE2-NEXT: jne LBB12_27 -; SSE2-NEXT: LBB12_28: ## %else50 +; SSE2-NEXT: jne LBB12_30 +; SSE2-NEXT: LBB12_14: ## %else50 ; SSE2-NEXT: testl $16384, %eax ## imm = 0x4000 -; SSE2-NEXT: jne LBB12_29 -; SSE2-NEXT: LBB12_30: ## %else54 -; SSE2-NEXT: testl $32768, %eax ## imm = 0x8000 ; SSE2-NEXT: jne LBB12_31 -; SSE2-NEXT: LBB12_32: ## %else58 +; SSE2-NEXT: LBB12_15: ## %else54 +; SSE2-NEXT: testl $32768, %eax ## imm = 0x8000 +; SSE2-NEXT: jne LBB12_32 +; SSE2-NEXT: LBB12_16: ## %else58 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB12_1: ## %cond.load +; SSE2-NEXT: LBB12_17: ## %cond.load ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: movzbl (%rdi), %ecx @@ -3254,8 +3254,8 @@ define <16 x i8> @expandload_v16i8_v16i8(ptr %base, <16 x i8> %src0, <16 x i8> % ; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: incq %rdi ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB12_4 -; SSE2-NEXT: LBB12_3: ## %cond.load1 +; SSE2-NEXT: je LBB12_2 +; SSE2-NEXT: LBB12_18: ## %cond.load1 ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: movzbl (%rdi), %ecx @@ -3265,8 +3265,8 @@ define <16 x i8> @expandload_v16i8_v16i8(ptr %base, <16 x i8> %src0, <16 x i8> % ; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: incq %rdi ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB12_6 -; SSE2-NEXT: LBB12_5: ## %cond.load5 +; SSE2-NEXT: je LBB12_3 +; SSE2-NEXT: LBB12_19: ## %cond.load5 ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: movzbl (%rdi), %ecx @@ -3276,8 +3276,8 @@ define <16 x i8> @expandload_v16i8_v16i8(ptr %base, <16 x i8> %src0, <16 x i8> % ; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: incq %rdi ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB12_8 -; SSE2-NEXT: LBB12_7: ## %cond.load9 +; SSE2-NEXT: je LBB12_4 +; SSE2-NEXT: LBB12_20: ## %cond.load9 ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: movzbl (%rdi), %ecx @@ -3287,8 +3287,8 @@ define <16 x i8> @expandload_v16i8_v16i8(ptr %base, <16 x i8> %src0, <16 x i8> % ; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: incq %rdi ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: je LBB12_10 -; SSE2-NEXT: LBB12_9: ## %cond.load13 +; SSE2-NEXT: je LBB12_5 +; SSE2-NEXT: LBB12_21: ## %cond.load13 ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: movzbl (%rdi), %ecx @@ -3298,8 +3298,8 @@ define <16 x i8> @expandload_v16i8_v16i8(ptr %base, <16 x i8> %src0, <16 x i8> % ; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: incq %rdi ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je LBB12_12 -; SSE2-NEXT: LBB12_11: ## %cond.load17 +; SSE2-NEXT: je LBB12_6 +; SSE2-NEXT: LBB12_22: ## %cond.load17 ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: movzbl (%rdi), %ecx @@ -3309,8 +3309,8 @@ define <16 x i8> @expandload_v16i8_v16i8(ptr %base, <16 x i8> %src0, <16 x i8> % ; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: incq %rdi ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: je LBB12_14 -; SSE2-NEXT: LBB12_13: ## %cond.load21 +; SSE2-NEXT: je LBB12_7 +; SSE2-NEXT: LBB12_23: ## %cond.load21 ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: movzbl (%rdi), %ecx @@ -3320,8 +3320,8 @@ define <16 x i8> @expandload_v16i8_v16i8(ptr %base, <16 x i8> %src0, <16 x i8> % ; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: incq %rdi ; SSE2-NEXT: testb %al, %al -; SSE2-NEXT: jns LBB12_16 -; SSE2-NEXT: LBB12_15: ## %cond.load25 +; SSE2-NEXT: jns LBB12_8 +; SSE2-NEXT: LBB12_24: ## %cond.load25 ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: movzbl (%rdi), %ecx @@ -3331,8 +3331,8 @@ define <16 x i8> @expandload_v16i8_v16i8(ptr %base, <16 x i8> %src0, <16 x i8> % ; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: incq %rdi ; SSE2-NEXT: testl $256, %eax ## imm = 0x100 -; SSE2-NEXT: je LBB12_18 -; SSE2-NEXT: LBB12_17: ## %cond.load29 +; SSE2-NEXT: je LBB12_9 +; SSE2-NEXT: LBB12_25: ## %cond.load29 ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: movzbl (%rdi), %ecx @@ -3342,8 +3342,8 @@ define <16 x i8> @expandload_v16i8_v16i8(ptr %base, <16 x i8> %src0, <16 x i8> % ; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: incq %rdi ; SSE2-NEXT: testl $512, %eax ## imm = 0x200 -; SSE2-NEXT: je LBB12_20 -; SSE2-NEXT: LBB12_19: ## %cond.load33 +; SSE2-NEXT: je LBB12_10 +; SSE2-NEXT: LBB12_26: ## %cond.load33 ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: movzbl (%rdi), %ecx @@ -3353,8 +3353,8 @@ define <16 x i8> @expandload_v16i8_v16i8(ptr %base, <16 x i8> %src0, <16 x i8> % ; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: incq %rdi ; SSE2-NEXT: testl $1024, %eax ## imm = 0x400 -; SSE2-NEXT: je LBB12_22 -; SSE2-NEXT: LBB12_21: ## %cond.load37 +; SSE2-NEXT: je LBB12_11 +; SSE2-NEXT: LBB12_27: ## %cond.load37 ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255] ; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: movzbl (%rdi), %ecx @@ -3364,8 +3364,8 @@ define <16 x i8> @expandload_v16i8_v16i8(ptr %base, <16 x i8> %src0, <16 x i8> % ; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: incq %rdi ; SSE2-NEXT: testl $2048, %eax ## imm = 0x800 -; SSE2-NEXT: je LBB12_24 -; SSE2-NEXT: LBB12_23: ## %cond.load41 +; SSE2-NEXT: je LBB12_12 +; SSE2-NEXT: LBB12_28: ## %cond.load41 ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255] ; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: movzbl (%rdi), %ecx @@ -3375,8 +3375,8 @@ define <16 x i8> @expandload_v16i8_v16i8(ptr %base, <16 x i8> %src0, <16 x i8> % ; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: incq %rdi ; SSE2-NEXT: testl $4096, %eax ## imm = 0x1000 -; SSE2-NEXT: je LBB12_26 -; SSE2-NEXT: LBB12_25: ## %cond.load45 +; SSE2-NEXT: je LBB12_13 +; SSE2-NEXT: LBB12_29: ## %cond.load45 ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255] ; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: movzbl (%rdi), %ecx @@ -3386,8 +3386,8 @@ define <16 x i8> @expandload_v16i8_v16i8(ptr %base, <16 x i8> %src0, <16 x i8> % ; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: incq %rdi ; SSE2-NEXT: testl $8192, %eax ## imm = 0x2000 -; SSE2-NEXT: je LBB12_28 -; SSE2-NEXT: LBB12_27: ## %cond.load49 +; SSE2-NEXT: je LBB12_14 +; SSE2-NEXT: LBB12_30: ## %cond.load49 ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255] ; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: movzbl (%rdi), %ecx @@ -3397,8 +3397,8 @@ define <16 x i8> @expandload_v16i8_v16i8(ptr %base, <16 x i8> %src0, <16 x i8> % ; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: incq %rdi ; SSE2-NEXT: testl $16384, %eax ## imm = 0x4000 -; SSE2-NEXT: je LBB12_30 -; SSE2-NEXT: LBB12_29: ## %cond.load53 +; SSE2-NEXT: je LBB12_15 +; SSE2-NEXT: LBB12_31: ## %cond.load53 ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255] ; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: movzbl (%rdi), %ecx @@ -3408,8 +3408,8 @@ define <16 x i8> @expandload_v16i8_v16i8(ptr %base, <16 x i8> %src0, <16 x i8> % ; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: incq %rdi ; SSE2-NEXT: testl $32768, %eax ## imm = 0x8000 -; SSE2-NEXT: je LBB12_32 -; SSE2-NEXT: LBB12_31: ## %cond.load57 +; SSE2-NEXT: je LBB12_16 +; SSE2-NEXT: LBB12_32: ## %cond.load57 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE2-NEXT: movzbl (%rdi), %eax ; SSE2-NEXT: movd %eax, %xmm1 @@ -3423,130 +3423,130 @@ define <16 x i8> @expandload_v16i8_v16i8(ptr %base, <16 x i8> %src0, <16 x i8> % ; SSE42-NEXT: pcmpeqb %xmm1, %xmm2 ; SSE42-NEXT: pmovmskb %xmm2, %eax ; SSE42-NEXT: testb $1, %al -; SSE42-NEXT: jne LBB12_1 -; SSE42-NEXT: ## %bb.2: ## %else +; SSE42-NEXT: jne LBB12_17 +; SSE42-NEXT: ## %bb.1: ## %else ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: jne LBB12_3 -; SSE42-NEXT: LBB12_4: ## %else2 +; SSE42-NEXT: jne LBB12_18 +; SSE42-NEXT: LBB12_2: ## %else2 ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: jne LBB12_5 -; SSE42-NEXT: LBB12_6: ## %else6 +; SSE42-NEXT: jne LBB12_19 +; SSE42-NEXT: LBB12_3: ## %else6 ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: jne LBB12_7 -; SSE42-NEXT: LBB12_8: ## %else10 +; SSE42-NEXT: jne LBB12_20 +; SSE42-NEXT: LBB12_4: ## %else10 ; SSE42-NEXT: testb $16, %al -; SSE42-NEXT: jne LBB12_9 -; SSE42-NEXT: LBB12_10: ## %else14 +; SSE42-NEXT: jne LBB12_21 +; SSE42-NEXT: LBB12_5: ## %else14 ; SSE42-NEXT: testb $32, %al -; SSE42-NEXT: jne LBB12_11 -; SSE42-NEXT: LBB12_12: ## %else18 +; SSE42-NEXT: jne LBB12_22 +; SSE42-NEXT: LBB12_6: ## %else18 ; SSE42-NEXT: testb $64, %al -; SSE42-NEXT: jne LBB12_13 -; SSE42-NEXT: LBB12_14: ## %else22 +; SSE42-NEXT: jne LBB12_23 +; SSE42-NEXT: LBB12_7: ## %else22 ; SSE42-NEXT: testb %al, %al -; SSE42-NEXT: js LBB12_15 -; SSE42-NEXT: LBB12_16: ## %else26 +; SSE42-NEXT: js LBB12_24 +; SSE42-NEXT: LBB12_8: ## %else26 ; SSE42-NEXT: testl $256, %eax ## imm = 0x100 -; SSE42-NEXT: jne LBB12_17 -; SSE42-NEXT: LBB12_18: ## %else30 +; SSE42-NEXT: jne LBB12_25 +; SSE42-NEXT: LBB12_9: ## %else30 ; SSE42-NEXT: testl $512, %eax ## imm = 0x200 -; SSE42-NEXT: jne LBB12_19 -; SSE42-NEXT: LBB12_20: ## %else34 +; SSE42-NEXT: jne LBB12_26 +; SSE42-NEXT: LBB12_10: ## %else34 ; SSE42-NEXT: testl $1024, %eax ## imm = 0x400 -; SSE42-NEXT: jne LBB12_21 -; SSE42-NEXT: LBB12_22: ## %else38 +; SSE42-NEXT: jne LBB12_27 +; SSE42-NEXT: LBB12_11: ## %else38 ; SSE42-NEXT: testl $2048, %eax ## imm = 0x800 -; SSE42-NEXT: jne LBB12_23 -; SSE42-NEXT: LBB12_24: ## %else42 +; SSE42-NEXT: jne LBB12_28 +; SSE42-NEXT: LBB12_12: ## %else42 ; SSE42-NEXT: testl $4096, %eax ## imm = 0x1000 -; SSE42-NEXT: jne LBB12_25 -; SSE42-NEXT: LBB12_26: ## %else46 +; SSE42-NEXT: jne LBB12_29 +; SSE42-NEXT: LBB12_13: ## %else46 ; SSE42-NEXT: testl $8192, %eax ## imm = 0x2000 -; SSE42-NEXT: jne LBB12_27 -; SSE42-NEXT: LBB12_28: ## %else50 +; SSE42-NEXT: jne LBB12_30 +; SSE42-NEXT: LBB12_14: ## %else50 ; SSE42-NEXT: testl $16384, %eax ## imm = 0x4000 -; SSE42-NEXT: jne LBB12_29 -; SSE42-NEXT: LBB12_30: ## %else54 -; SSE42-NEXT: testl $32768, %eax ## imm = 0x8000 ; SSE42-NEXT: jne LBB12_31 -; SSE42-NEXT: LBB12_32: ## %else58 +; SSE42-NEXT: LBB12_15: ## %else54 +; SSE42-NEXT: testl $32768, %eax ## imm = 0x8000 +; SSE42-NEXT: jne LBB12_32 +; SSE42-NEXT: LBB12_16: ## %else58 ; SSE42-NEXT: retq -; SSE42-NEXT: LBB12_1: ## %cond.load +; SSE42-NEXT: LBB12_17: ## %cond.load ; SSE42-NEXT: pinsrb $0, (%rdi), %xmm0 ; SSE42-NEXT: incq %rdi ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: je LBB12_4 -; SSE42-NEXT: LBB12_3: ## %cond.load1 +; SSE42-NEXT: je LBB12_2 +; SSE42-NEXT: LBB12_18: ## %cond.load1 ; SSE42-NEXT: pinsrb $1, (%rdi), %xmm0 ; SSE42-NEXT: incq %rdi ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: je LBB12_6 -; SSE42-NEXT: LBB12_5: ## %cond.load5 +; SSE42-NEXT: je LBB12_3 +; SSE42-NEXT: LBB12_19: ## %cond.load5 ; SSE42-NEXT: pinsrb $2, (%rdi), %xmm0 ; SSE42-NEXT: incq %rdi ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: je LBB12_8 -; SSE42-NEXT: LBB12_7: ## %cond.load9 +; SSE42-NEXT: je LBB12_4 +; SSE42-NEXT: LBB12_20: ## %cond.load9 ; SSE42-NEXT: pinsrb $3, (%rdi), %xmm0 ; SSE42-NEXT: incq %rdi ; SSE42-NEXT: testb $16, %al -; SSE42-NEXT: je LBB12_10 -; SSE42-NEXT: LBB12_9: ## %cond.load13 +; SSE42-NEXT: je LBB12_5 +; SSE42-NEXT: LBB12_21: ## %cond.load13 ; SSE42-NEXT: pinsrb $4, (%rdi), %xmm0 ; SSE42-NEXT: incq %rdi ; SSE42-NEXT: testb $32, %al -; SSE42-NEXT: je LBB12_12 -; SSE42-NEXT: LBB12_11: ## %cond.load17 +; SSE42-NEXT: je LBB12_6 +; SSE42-NEXT: LBB12_22: ## %cond.load17 ; SSE42-NEXT: pinsrb $5, (%rdi), %xmm0 ; SSE42-NEXT: incq %rdi ; SSE42-NEXT: testb $64, %al -; SSE42-NEXT: je LBB12_14 -; SSE42-NEXT: LBB12_13: ## %cond.load21 +; SSE42-NEXT: je LBB12_7 +; SSE42-NEXT: LBB12_23: ## %cond.load21 ; SSE42-NEXT: pinsrb $6, (%rdi), %xmm0 ; SSE42-NEXT: incq %rdi ; SSE42-NEXT: testb %al, %al -; SSE42-NEXT: jns LBB12_16 -; SSE42-NEXT: LBB12_15: ## %cond.load25 +; SSE42-NEXT: jns LBB12_8 +; SSE42-NEXT: LBB12_24: ## %cond.load25 ; SSE42-NEXT: pinsrb $7, (%rdi), %xmm0 ; SSE42-NEXT: incq %rdi ; SSE42-NEXT: testl $256, %eax ## imm = 0x100 -; SSE42-NEXT: je LBB12_18 -; SSE42-NEXT: LBB12_17: ## %cond.load29 +; SSE42-NEXT: je LBB12_9 +; SSE42-NEXT: LBB12_25: ## %cond.load29 ; SSE42-NEXT: pinsrb $8, (%rdi), %xmm0 ; SSE42-NEXT: incq %rdi ; SSE42-NEXT: testl $512, %eax ## imm = 0x200 -; SSE42-NEXT: je LBB12_20 -; SSE42-NEXT: LBB12_19: ## %cond.load33 +; SSE42-NEXT: je LBB12_10 +; SSE42-NEXT: LBB12_26: ## %cond.load33 ; SSE42-NEXT: pinsrb $9, (%rdi), %xmm0 ; SSE42-NEXT: incq %rdi ; SSE42-NEXT: testl $1024, %eax ## imm = 0x400 -; SSE42-NEXT: je LBB12_22 -; SSE42-NEXT: LBB12_21: ## %cond.load37 +; SSE42-NEXT: je LBB12_11 +; SSE42-NEXT: LBB12_27: ## %cond.load37 ; SSE42-NEXT: pinsrb $10, (%rdi), %xmm0 ; SSE42-NEXT: incq %rdi ; SSE42-NEXT: testl $2048, %eax ## imm = 0x800 -; SSE42-NEXT: je LBB12_24 -; SSE42-NEXT: LBB12_23: ## %cond.load41 +; SSE42-NEXT: je LBB12_12 +; SSE42-NEXT: LBB12_28: ## %cond.load41 ; SSE42-NEXT: pinsrb $11, (%rdi), %xmm0 ; SSE42-NEXT: incq %rdi ; SSE42-NEXT: testl $4096, %eax ## imm = 0x1000 -; SSE42-NEXT: je LBB12_26 -; SSE42-NEXT: LBB12_25: ## %cond.load45 +; SSE42-NEXT: je LBB12_13 +; SSE42-NEXT: LBB12_29: ## %cond.load45 ; SSE42-NEXT: pinsrb $12, (%rdi), %xmm0 ; SSE42-NEXT: incq %rdi ; SSE42-NEXT: testl $8192, %eax ## imm = 0x2000 -; SSE42-NEXT: je LBB12_28 -; SSE42-NEXT: LBB12_27: ## %cond.load49 +; SSE42-NEXT: je LBB12_14 +; SSE42-NEXT: LBB12_30: ## %cond.load49 ; SSE42-NEXT: pinsrb $13, (%rdi), %xmm0 ; SSE42-NEXT: incq %rdi ; SSE42-NEXT: testl $16384, %eax ## imm = 0x4000 -; SSE42-NEXT: je LBB12_30 -; SSE42-NEXT: LBB12_29: ## %cond.load53 +; SSE42-NEXT: je LBB12_15 +; SSE42-NEXT: LBB12_31: ## %cond.load53 ; SSE42-NEXT: pinsrb $14, (%rdi), %xmm0 ; SSE42-NEXT: incq %rdi ; SSE42-NEXT: testl $32768, %eax ## imm = 0x8000 -; SSE42-NEXT: je LBB12_32 -; SSE42-NEXT: LBB12_31: ## %cond.load57 +; SSE42-NEXT: je LBB12_16 +; SSE42-NEXT: LBB12_32: ## %cond.load57 ; SSE42-NEXT: pinsrb $15, (%rdi), %xmm0 ; SSE42-NEXT: retq ; @@ -3556,130 +3556,130 @@ define <16 x i8> @expandload_v16i8_v16i8(ptr %base, <16 x i8> %src0, <16 x i8> % ; AVX1OR2-NEXT: vpcmpeqb %xmm2, %xmm1, %xmm1 ; AVX1OR2-NEXT: vpmovmskb %xmm1, %eax ; AVX1OR2-NEXT: testb $1, %al -; AVX1OR2-NEXT: jne LBB12_1 -; AVX1OR2-NEXT: ## %bb.2: ## %else +; AVX1OR2-NEXT: jne LBB12_17 +; AVX1OR2-NEXT: ## %bb.1: ## %else ; AVX1OR2-NEXT: testb $2, %al -; AVX1OR2-NEXT: jne LBB12_3 -; AVX1OR2-NEXT: LBB12_4: ## %else2 +; AVX1OR2-NEXT: jne LBB12_18 +; AVX1OR2-NEXT: LBB12_2: ## %else2 ; AVX1OR2-NEXT: testb $4, %al -; AVX1OR2-NEXT: jne LBB12_5 -; AVX1OR2-NEXT: LBB12_6: ## %else6 +; AVX1OR2-NEXT: jne LBB12_19 +; AVX1OR2-NEXT: LBB12_3: ## %else6 ; AVX1OR2-NEXT: testb $8, %al -; AVX1OR2-NEXT: jne LBB12_7 -; AVX1OR2-NEXT: LBB12_8: ## %else10 +; AVX1OR2-NEXT: jne LBB12_20 +; AVX1OR2-NEXT: LBB12_4: ## %else10 ; AVX1OR2-NEXT: testb $16, %al -; AVX1OR2-NEXT: jne LBB12_9 -; AVX1OR2-NEXT: LBB12_10: ## %else14 +; AVX1OR2-NEXT: jne LBB12_21 +; AVX1OR2-NEXT: LBB12_5: ## %else14 ; AVX1OR2-NEXT: testb $32, %al -; AVX1OR2-NEXT: jne LBB12_11 -; AVX1OR2-NEXT: LBB12_12: ## %else18 +; AVX1OR2-NEXT: jne LBB12_22 +; AVX1OR2-NEXT: LBB12_6: ## %else18 ; AVX1OR2-NEXT: testb $64, %al -; AVX1OR2-NEXT: jne LBB12_13 -; AVX1OR2-NEXT: LBB12_14: ## %else22 +; AVX1OR2-NEXT: jne LBB12_23 +; AVX1OR2-NEXT: LBB12_7: ## %else22 ; AVX1OR2-NEXT: testb %al, %al -; AVX1OR2-NEXT: js LBB12_15 -; AVX1OR2-NEXT: LBB12_16: ## %else26 +; AVX1OR2-NEXT: js LBB12_24 +; AVX1OR2-NEXT: LBB12_8: ## %else26 ; AVX1OR2-NEXT: testl $256, %eax ## imm = 0x100 -; AVX1OR2-NEXT: jne LBB12_17 -; AVX1OR2-NEXT: LBB12_18: ## %else30 +; AVX1OR2-NEXT: jne LBB12_25 +; AVX1OR2-NEXT: LBB12_9: ## %else30 ; AVX1OR2-NEXT: testl $512, %eax ## imm = 0x200 -; AVX1OR2-NEXT: jne LBB12_19 -; AVX1OR2-NEXT: LBB12_20: ## %else34 +; AVX1OR2-NEXT: jne LBB12_26 +; AVX1OR2-NEXT: LBB12_10: ## %else34 ; AVX1OR2-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX1OR2-NEXT: jne LBB12_21 -; AVX1OR2-NEXT: LBB12_22: ## %else38 +; AVX1OR2-NEXT: jne LBB12_27 +; AVX1OR2-NEXT: LBB12_11: ## %else38 ; AVX1OR2-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX1OR2-NEXT: jne LBB12_23 -; AVX1OR2-NEXT: LBB12_24: ## %else42 +; AVX1OR2-NEXT: jne LBB12_28 +; AVX1OR2-NEXT: LBB12_12: ## %else42 ; AVX1OR2-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX1OR2-NEXT: jne LBB12_25 -; AVX1OR2-NEXT: LBB12_26: ## %else46 +; AVX1OR2-NEXT: jne LBB12_29 +; AVX1OR2-NEXT: LBB12_13: ## %else46 ; AVX1OR2-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX1OR2-NEXT: jne LBB12_27 -; AVX1OR2-NEXT: LBB12_28: ## %else50 +; AVX1OR2-NEXT: jne LBB12_30 +; AVX1OR2-NEXT: LBB12_14: ## %else50 ; AVX1OR2-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX1OR2-NEXT: jne LBB12_29 -; AVX1OR2-NEXT: LBB12_30: ## %else54 -; AVX1OR2-NEXT: testl $32768, %eax ## imm = 0x8000 ; AVX1OR2-NEXT: jne LBB12_31 -; AVX1OR2-NEXT: LBB12_32: ## %else58 +; AVX1OR2-NEXT: LBB12_15: ## %else54 +; AVX1OR2-NEXT: testl $32768, %eax ## imm = 0x8000 +; AVX1OR2-NEXT: jne LBB12_32 +; AVX1OR2-NEXT: LBB12_16: ## %else58 ; AVX1OR2-NEXT: retq -; AVX1OR2-NEXT: LBB12_1: ## %cond.load +; AVX1OR2-NEXT: LBB12_17: ## %cond.load ; AVX1OR2-NEXT: vpinsrb $0, (%rdi), %xmm0, %xmm0 ; AVX1OR2-NEXT: incq %rdi ; AVX1OR2-NEXT: testb $2, %al -; AVX1OR2-NEXT: je LBB12_4 -; AVX1OR2-NEXT: LBB12_3: ## %cond.load1 +; AVX1OR2-NEXT: je LBB12_2 +; AVX1OR2-NEXT: LBB12_18: ## %cond.load1 ; AVX1OR2-NEXT: vpinsrb $1, (%rdi), %xmm0, %xmm0 ; AVX1OR2-NEXT: incq %rdi ; AVX1OR2-NEXT: testb $4, %al -; AVX1OR2-NEXT: je LBB12_6 -; AVX1OR2-NEXT: LBB12_5: ## %cond.load5 +; AVX1OR2-NEXT: je LBB12_3 +; AVX1OR2-NEXT: LBB12_19: ## %cond.load5 ; AVX1OR2-NEXT: vpinsrb $2, (%rdi), %xmm0, %xmm0 ; AVX1OR2-NEXT: incq %rdi ; AVX1OR2-NEXT: testb $8, %al -; AVX1OR2-NEXT: je LBB12_8 -; AVX1OR2-NEXT: LBB12_7: ## %cond.load9 +; AVX1OR2-NEXT: je LBB12_4 +; AVX1OR2-NEXT: LBB12_20: ## %cond.load9 ; AVX1OR2-NEXT: vpinsrb $3, (%rdi), %xmm0, %xmm0 ; AVX1OR2-NEXT: incq %rdi ; AVX1OR2-NEXT: testb $16, %al -; AVX1OR2-NEXT: je LBB12_10 -; AVX1OR2-NEXT: LBB12_9: ## %cond.load13 +; AVX1OR2-NEXT: je LBB12_5 +; AVX1OR2-NEXT: LBB12_21: ## %cond.load13 ; AVX1OR2-NEXT: vpinsrb $4, (%rdi), %xmm0, %xmm0 ; AVX1OR2-NEXT: incq %rdi ; AVX1OR2-NEXT: testb $32, %al -; AVX1OR2-NEXT: je LBB12_12 -; AVX1OR2-NEXT: LBB12_11: ## %cond.load17 +; AVX1OR2-NEXT: je LBB12_6 +; AVX1OR2-NEXT: LBB12_22: ## %cond.load17 ; AVX1OR2-NEXT: vpinsrb $5, (%rdi), %xmm0, %xmm0 ; AVX1OR2-NEXT: incq %rdi ; AVX1OR2-NEXT: testb $64, %al -; AVX1OR2-NEXT: je LBB12_14 -; AVX1OR2-NEXT: LBB12_13: ## %cond.load21 +; AVX1OR2-NEXT: je LBB12_7 +; AVX1OR2-NEXT: LBB12_23: ## %cond.load21 ; AVX1OR2-NEXT: vpinsrb $6, (%rdi), %xmm0, %xmm0 ; AVX1OR2-NEXT: incq %rdi ; AVX1OR2-NEXT: testb %al, %al -; AVX1OR2-NEXT: jns LBB12_16 -; AVX1OR2-NEXT: LBB12_15: ## %cond.load25 +; AVX1OR2-NEXT: jns LBB12_8 +; AVX1OR2-NEXT: LBB12_24: ## %cond.load25 ; AVX1OR2-NEXT: vpinsrb $7, (%rdi), %xmm0, %xmm0 ; AVX1OR2-NEXT: incq %rdi ; AVX1OR2-NEXT: testl $256, %eax ## imm = 0x100 -; AVX1OR2-NEXT: je LBB12_18 -; AVX1OR2-NEXT: LBB12_17: ## %cond.load29 +; AVX1OR2-NEXT: je LBB12_9 +; AVX1OR2-NEXT: LBB12_25: ## %cond.load29 ; AVX1OR2-NEXT: vpinsrb $8, (%rdi), %xmm0, %xmm0 ; AVX1OR2-NEXT: incq %rdi ; AVX1OR2-NEXT: testl $512, %eax ## imm = 0x200 -; AVX1OR2-NEXT: je LBB12_20 -; AVX1OR2-NEXT: LBB12_19: ## %cond.load33 +; AVX1OR2-NEXT: je LBB12_10 +; AVX1OR2-NEXT: LBB12_26: ## %cond.load33 ; AVX1OR2-NEXT: vpinsrb $9, (%rdi), %xmm0, %xmm0 ; AVX1OR2-NEXT: incq %rdi ; AVX1OR2-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX1OR2-NEXT: je LBB12_22 -; AVX1OR2-NEXT: LBB12_21: ## %cond.load37 +; AVX1OR2-NEXT: je LBB12_11 +; AVX1OR2-NEXT: LBB12_27: ## %cond.load37 ; AVX1OR2-NEXT: vpinsrb $10, (%rdi), %xmm0, %xmm0 ; AVX1OR2-NEXT: incq %rdi ; AVX1OR2-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX1OR2-NEXT: je LBB12_24 -; AVX1OR2-NEXT: LBB12_23: ## %cond.load41 +; AVX1OR2-NEXT: je LBB12_12 +; AVX1OR2-NEXT: LBB12_28: ## %cond.load41 ; AVX1OR2-NEXT: vpinsrb $11, (%rdi), %xmm0, %xmm0 ; AVX1OR2-NEXT: incq %rdi ; AVX1OR2-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX1OR2-NEXT: je LBB12_26 -; AVX1OR2-NEXT: LBB12_25: ## %cond.load45 +; AVX1OR2-NEXT: je LBB12_13 +; AVX1OR2-NEXT: LBB12_29: ## %cond.load45 ; AVX1OR2-NEXT: vpinsrb $12, (%rdi), %xmm0, %xmm0 ; AVX1OR2-NEXT: incq %rdi ; AVX1OR2-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX1OR2-NEXT: je LBB12_28 -; AVX1OR2-NEXT: LBB12_27: ## %cond.load49 +; AVX1OR2-NEXT: je LBB12_14 +; AVX1OR2-NEXT: LBB12_30: ## %cond.load49 ; AVX1OR2-NEXT: vpinsrb $13, (%rdi), %xmm0, %xmm0 ; AVX1OR2-NEXT: incq %rdi ; AVX1OR2-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX1OR2-NEXT: je LBB12_30 -; AVX1OR2-NEXT: LBB12_29: ## %cond.load53 +; AVX1OR2-NEXT: je LBB12_15 +; AVX1OR2-NEXT: LBB12_31: ## %cond.load53 ; AVX1OR2-NEXT: vpinsrb $14, (%rdi), %xmm0, %xmm0 ; AVX1OR2-NEXT: incq %rdi ; AVX1OR2-NEXT: testl $32768, %eax ## imm = 0x8000 -; AVX1OR2-NEXT: je LBB12_32 -; AVX1OR2-NEXT: LBB12_31: ## %cond.load57 +; AVX1OR2-NEXT: je LBB12_16 +; AVX1OR2-NEXT: LBB12_32: ## %cond.load57 ; AVX1OR2-NEXT: vpinsrb $15, (%rdi), %xmm0, %xmm0 ; AVX1OR2-NEXT: retq ; @@ -3689,130 +3689,130 @@ define <16 x i8> @expandload_v16i8_v16i8(ptr %base, <16 x i8> %src0, <16 x i8> % ; AVX512F-NEXT: vpcmpeqb %xmm2, %xmm1, %xmm1 ; AVX512F-NEXT: vpmovmskb %xmm1, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne LBB12_1 -; AVX512F-NEXT: ## %bb.2: ## %else +; AVX512F-NEXT: jne LBB12_17 +; AVX512F-NEXT: ## %bb.1: ## %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne LBB12_3 -; AVX512F-NEXT: LBB12_4: ## %else2 +; AVX512F-NEXT: jne LBB12_18 +; AVX512F-NEXT: LBB12_2: ## %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne LBB12_5 -; AVX512F-NEXT: LBB12_6: ## %else6 +; AVX512F-NEXT: jne LBB12_19 +; AVX512F-NEXT: LBB12_3: ## %else6 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne LBB12_7 -; AVX512F-NEXT: LBB12_8: ## %else10 +; AVX512F-NEXT: jne LBB12_20 +; AVX512F-NEXT: LBB12_4: ## %else10 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne LBB12_9 -; AVX512F-NEXT: LBB12_10: ## %else14 +; AVX512F-NEXT: jne LBB12_21 +; AVX512F-NEXT: LBB12_5: ## %else14 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne LBB12_11 -; AVX512F-NEXT: LBB12_12: ## %else18 +; AVX512F-NEXT: jne LBB12_22 +; AVX512F-NEXT: LBB12_6: ## %else18 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne LBB12_13 -; AVX512F-NEXT: LBB12_14: ## %else22 +; AVX512F-NEXT: jne LBB12_23 +; AVX512F-NEXT: LBB12_7: ## %else22 ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: js LBB12_15 -; AVX512F-NEXT: LBB12_16: ## %else26 +; AVX512F-NEXT: js LBB12_24 +; AVX512F-NEXT: LBB12_8: ## %else26 ; AVX512F-NEXT: testl $256, %eax ## imm = 0x100 -; AVX512F-NEXT: jne LBB12_17 -; AVX512F-NEXT: LBB12_18: ## %else30 +; AVX512F-NEXT: jne LBB12_25 +; AVX512F-NEXT: LBB12_9: ## %else30 ; AVX512F-NEXT: testl $512, %eax ## imm = 0x200 -; AVX512F-NEXT: jne LBB12_19 -; AVX512F-NEXT: LBB12_20: ## %else34 +; AVX512F-NEXT: jne LBB12_26 +; AVX512F-NEXT: LBB12_10: ## %else34 ; AVX512F-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX512F-NEXT: jne LBB12_21 -; AVX512F-NEXT: LBB12_22: ## %else38 +; AVX512F-NEXT: jne LBB12_27 +; AVX512F-NEXT: LBB12_11: ## %else38 ; AVX512F-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX512F-NEXT: jne LBB12_23 -; AVX512F-NEXT: LBB12_24: ## %else42 +; AVX512F-NEXT: jne LBB12_28 +; AVX512F-NEXT: LBB12_12: ## %else42 ; AVX512F-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX512F-NEXT: jne LBB12_25 -; AVX512F-NEXT: LBB12_26: ## %else46 +; AVX512F-NEXT: jne LBB12_29 +; AVX512F-NEXT: LBB12_13: ## %else46 ; AVX512F-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX512F-NEXT: jne LBB12_27 -; AVX512F-NEXT: LBB12_28: ## %else50 +; AVX512F-NEXT: jne LBB12_30 +; AVX512F-NEXT: LBB12_14: ## %else50 ; AVX512F-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX512F-NEXT: jne LBB12_29 -; AVX512F-NEXT: LBB12_30: ## %else54 -; AVX512F-NEXT: testl $32768, %eax ## imm = 0x8000 ; AVX512F-NEXT: jne LBB12_31 -; AVX512F-NEXT: LBB12_32: ## %else58 +; AVX512F-NEXT: LBB12_15: ## %else54 +; AVX512F-NEXT: testl $32768, %eax ## imm = 0x8000 +; AVX512F-NEXT: jne LBB12_32 +; AVX512F-NEXT: LBB12_16: ## %else58 ; AVX512F-NEXT: retq -; AVX512F-NEXT: LBB12_1: ## %cond.load +; AVX512F-NEXT: LBB12_17: ## %cond.load ; AVX512F-NEXT: vpinsrb $0, (%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: incq %rdi ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je LBB12_4 -; AVX512F-NEXT: LBB12_3: ## %cond.load1 +; AVX512F-NEXT: je LBB12_2 +; AVX512F-NEXT: LBB12_18: ## %cond.load1 ; AVX512F-NEXT: vpinsrb $1, (%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: incq %rdi ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je LBB12_6 -; AVX512F-NEXT: LBB12_5: ## %cond.load5 +; AVX512F-NEXT: je LBB12_3 +; AVX512F-NEXT: LBB12_19: ## %cond.load5 ; AVX512F-NEXT: vpinsrb $2, (%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: incq %rdi ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je LBB12_8 -; AVX512F-NEXT: LBB12_7: ## %cond.load9 +; AVX512F-NEXT: je LBB12_4 +; AVX512F-NEXT: LBB12_20: ## %cond.load9 ; AVX512F-NEXT: vpinsrb $3, (%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: incq %rdi ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je LBB12_10 -; AVX512F-NEXT: LBB12_9: ## %cond.load13 +; AVX512F-NEXT: je LBB12_5 +; AVX512F-NEXT: LBB12_21: ## %cond.load13 ; AVX512F-NEXT: vpinsrb $4, (%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: incq %rdi ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je LBB12_12 -; AVX512F-NEXT: LBB12_11: ## %cond.load17 +; AVX512F-NEXT: je LBB12_6 +; AVX512F-NEXT: LBB12_22: ## %cond.load17 ; AVX512F-NEXT: vpinsrb $5, (%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: incq %rdi ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je LBB12_14 -; AVX512F-NEXT: LBB12_13: ## %cond.load21 +; AVX512F-NEXT: je LBB12_7 +; AVX512F-NEXT: LBB12_23: ## %cond.load21 ; AVX512F-NEXT: vpinsrb $6, (%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: incq %rdi ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: jns LBB12_16 -; AVX512F-NEXT: LBB12_15: ## %cond.load25 +; AVX512F-NEXT: jns LBB12_8 +; AVX512F-NEXT: LBB12_24: ## %cond.load25 ; AVX512F-NEXT: vpinsrb $7, (%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: incq %rdi ; AVX512F-NEXT: testl $256, %eax ## imm = 0x100 -; AVX512F-NEXT: je LBB12_18 -; AVX512F-NEXT: LBB12_17: ## %cond.load29 +; AVX512F-NEXT: je LBB12_9 +; AVX512F-NEXT: LBB12_25: ## %cond.load29 ; AVX512F-NEXT: vpinsrb $8, (%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: incq %rdi ; AVX512F-NEXT: testl $512, %eax ## imm = 0x200 -; AVX512F-NEXT: je LBB12_20 -; AVX512F-NEXT: LBB12_19: ## %cond.load33 +; AVX512F-NEXT: je LBB12_10 +; AVX512F-NEXT: LBB12_26: ## %cond.load33 ; AVX512F-NEXT: vpinsrb $9, (%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: incq %rdi ; AVX512F-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX512F-NEXT: je LBB12_22 -; AVX512F-NEXT: LBB12_21: ## %cond.load37 +; AVX512F-NEXT: je LBB12_11 +; AVX512F-NEXT: LBB12_27: ## %cond.load37 ; AVX512F-NEXT: vpinsrb $10, (%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: incq %rdi ; AVX512F-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX512F-NEXT: je LBB12_24 -; AVX512F-NEXT: LBB12_23: ## %cond.load41 +; AVX512F-NEXT: je LBB12_12 +; AVX512F-NEXT: LBB12_28: ## %cond.load41 ; AVX512F-NEXT: vpinsrb $11, (%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: incq %rdi ; AVX512F-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX512F-NEXT: je LBB12_26 -; AVX512F-NEXT: LBB12_25: ## %cond.load45 +; AVX512F-NEXT: je LBB12_13 +; AVX512F-NEXT: LBB12_29: ## %cond.load45 ; AVX512F-NEXT: vpinsrb $12, (%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: incq %rdi ; AVX512F-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX512F-NEXT: je LBB12_28 -; AVX512F-NEXT: LBB12_27: ## %cond.load49 +; AVX512F-NEXT: je LBB12_14 +; AVX512F-NEXT: LBB12_30: ## %cond.load49 ; AVX512F-NEXT: vpinsrb $13, (%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: incq %rdi ; AVX512F-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX512F-NEXT: je LBB12_30 -; AVX512F-NEXT: LBB12_29: ## %cond.load53 +; AVX512F-NEXT: je LBB12_15 +; AVX512F-NEXT: LBB12_31: ## %cond.load53 ; AVX512F-NEXT: vpinsrb $14, (%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: incq %rdi ; AVX512F-NEXT: testl $32768, %eax ## imm = 0x8000 -; AVX512F-NEXT: je LBB12_32 -; AVX512F-NEXT: LBB12_31: ## %cond.load57 +; AVX512F-NEXT: je LBB12_16 +; AVX512F-NEXT: LBB12_32: ## %cond.load57 ; AVX512F-NEXT: vpinsrb $15, (%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: retq ; @@ -3822,130 +3822,130 @@ define <16 x i8> @expandload_v16i8_v16i8(ptr %base, <16 x i8> %src0, <16 x i8> % ; AVX512VLDQ-NEXT: vpcmpeqb %xmm2, %xmm1, %xmm1 ; AVX512VLDQ-NEXT: vpmovmskb %xmm1, %eax ; AVX512VLDQ-NEXT: testb $1, %al -; AVX512VLDQ-NEXT: jne LBB12_1 -; AVX512VLDQ-NEXT: ## %bb.2: ## %else +; AVX512VLDQ-NEXT: jne LBB12_17 +; AVX512VLDQ-NEXT: ## %bb.1: ## %else ; AVX512VLDQ-NEXT: testb $2, %al -; AVX512VLDQ-NEXT: jne LBB12_3 -; AVX512VLDQ-NEXT: LBB12_4: ## %else2 +; AVX512VLDQ-NEXT: jne LBB12_18 +; AVX512VLDQ-NEXT: LBB12_2: ## %else2 ; AVX512VLDQ-NEXT: testb $4, %al -; AVX512VLDQ-NEXT: jne LBB12_5 -; AVX512VLDQ-NEXT: LBB12_6: ## %else6 +; AVX512VLDQ-NEXT: jne LBB12_19 +; AVX512VLDQ-NEXT: LBB12_3: ## %else6 ; AVX512VLDQ-NEXT: testb $8, %al -; AVX512VLDQ-NEXT: jne LBB12_7 -; AVX512VLDQ-NEXT: LBB12_8: ## %else10 +; AVX512VLDQ-NEXT: jne LBB12_20 +; AVX512VLDQ-NEXT: LBB12_4: ## %else10 ; AVX512VLDQ-NEXT: testb $16, %al -; AVX512VLDQ-NEXT: jne LBB12_9 -; AVX512VLDQ-NEXT: LBB12_10: ## %else14 +; AVX512VLDQ-NEXT: jne LBB12_21 +; AVX512VLDQ-NEXT: LBB12_5: ## %else14 ; AVX512VLDQ-NEXT: testb $32, %al -; AVX512VLDQ-NEXT: jne LBB12_11 -; AVX512VLDQ-NEXT: LBB12_12: ## %else18 +; AVX512VLDQ-NEXT: jne LBB12_22 +; AVX512VLDQ-NEXT: LBB12_6: ## %else18 ; AVX512VLDQ-NEXT: testb $64, %al -; AVX512VLDQ-NEXT: jne LBB12_13 -; AVX512VLDQ-NEXT: LBB12_14: ## %else22 +; AVX512VLDQ-NEXT: jne LBB12_23 +; AVX512VLDQ-NEXT: LBB12_7: ## %else22 ; AVX512VLDQ-NEXT: testb %al, %al -; AVX512VLDQ-NEXT: js LBB12_15 -; AVX512VLDQ-NEXT: LBB12_16: ## %else26 +; AVX512VLDQ-NEXT: js LBB12_24 +; AVX512VLDQ-NEXT: LBB12_8: ## %else26 ; AVX512VLDQ-NEXT: testl $256, %eax ## imm = 0x100 -; AVX512VLDQ-NEXT: jne LBB12_17 -; AVX512VLDQ-NEXT: LBB12_18: ## %else30 +; AVX512VLDQ-NEXT: jne LBB12_25 +; AVX512VLDQ-NEXT: LBB12_9: ## %else30 ; AVX512VLDQ-NEXT: testl $512, %eax ## imm = 0x200 -; AVX512VLDQ-NEXT: jne LBB12_19 -; AVX512VLDQ-NEXT: LBB12_20: ## %else34 +; AVX512VLDQ-NEXT: jne LBB12_26 +; AVX512VLDQ-NEXT: LBB12_10: ## %else34 ; AVX512VLDQ-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX512VLDQ-NEXT: jne LBB12_21 -; AVX512VLDQ-NEXT: LBB12_22: ## %else38 +; AVX512VLDQ-NEXT: jne LBB12_27 +; AVX512VLDQ-NEXT: LBB12_11: ## %else38 ; AVX512VLDQ-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX512VLDQ-NEXT: jne LBB12_23 -; AVX512VLDQ-NEXT: LBB12_24: ## %else42 +; AVX512VLDQ-NEXT: jne LBB12_28 +; AVX512VLDQ-NEXT: LBB12_12: ## %else42 ; AVX512VLDQ-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX512VLDQ-NEXT: jne LBB12_25 -; AVX512VLDQ-NEXT: LBB12_26: ## %else46 +; AVX512VLDQ-NEXT: jne LBB12_29 +; AVX512VLDQ-NEXT: LBB12_13: ## %else46 ; AVX512VLDQ-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX512VLDQ-NEXT: jne LBB12_27 -; AVX512VLDQ-NEXT: LBB12_28: ## %else50 +; AVX512VLDQ-NEXT: jne LBB12_30 +; AVX512VLDQ-NEXT: LBB12_14: ## %else50 ; AVX512VLDQ-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX512VLDQ-NEXT: jne LBB12_29 -; AVX512VLDQ-NEXT: LBB12_30: ## %else54 -; AVX512VLDQ-NEXT: testl $32768, %eax ## imm = 0x8000 ; AVX512VLDQ-NEXT: jne LBB12_31 -; AVX512VLDQ-NEXT: LBB12_32: ## %else58 +; AVX512VLDQ-NEXT: LBB12_15: ## %else54 +; AVX512VLDQ-NEXT: testl $32768, %eax ## imm = 0x8000 +; AVX512VLDQ-NEXT: jne LBB12_32 +; AVX512VLDQ-NEXT: LBB12_16: ## %else58 ; AVX512VLDQ-NEXT: retq -; AVX512VLDQ-NEXT: LBB12_1: ## %cond.load +; AVX512VLDQ-NEXT: LBB12_17: ## %cond.load ; AVX512VLDQ-NEXT: vpinsrb $0, (%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: incq %rdi ; AVX512VLDQ-NEXT: testb $2, %al -; AVX512VLDQ-NEXT: je LBB12_4 -; AVX512VLDQ-NEXT: LBB12_3: ## %cond.load1 +; AVX512VLDQ-NEXT: je LBB12_2 +; AVX512VLDQ-NEXT: LBB12_18: ## %cond.load1 ; AVX512VLDQ-NEXT: vpinsrb $1, (%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: incq %rdi ; AVX512VLDQ-NEXT: testb $4, %al -; AVX512VLDQ-NEXT: je LBB12_6 -; AVX512VLDQ-NEXT: LBB12_5: ## %cond.load5 +; AVX512VLDQ-NEXT: je LBB12_3 +; AVX512VLDQ-NEXT: LBB12_19: ## %cond.load5 ; AVX512VLDQ-NEXT: vpinsrb $2, (%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: incq %rdi ; AVX512VLDQ-NEXT: testb $8, %al -; AVX512VLDQ-NEXT: je LBB12_8 -; AVX512VLDQ-NEXT: LBB12_7: ## %cond.load9 +; AVX512VLDQ-NEXT: je LBB12_4 +; AVX512VLDQ-NEXT: LBB12_20: ## %cond.load9 ; AVX512VLDQ-NEXT: vpinsrb $3, (%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: incq %rdi ; AVX512VLDQ-NEXT: testb $16, %al -; AVX512VLDQ-NEXT: je LBB12_10 -; AVX512VLDQ-NEXT: LBB12_9: ## %cond.load13 +; AVX512VLDQ-NEXT: je LBB12_5 +; AVX512VLDQ-NEXT: LBB12_21: ## %cond.load13 ; AVX512VLDQ-NEXT: vpinsrb $4, (%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: incq %rdi ; AVX512VLDQ-NEXT: testb $32, %al -; AVX512VLDQ-NEXT: je LBB12_12 -; AVX512VLDQ-NEXT: LBB12_11: ## %cond.load17 +; AVX512VLDQ-NEXT: je LBB12_6 +; AVX512VLDQ-NEXT: LBB12_22: ## %cond.load17 ; AVX512VLDQ-NEXT: vpinsrb $5, (%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: incq %rdi ; AVX512VLDQ-NEXT: testb $64, %al -; AVX512VLDQ-NEXT: je LBB12_14 -; AVX512VLDQ-NEXT: LBB12_13: ## %cond.load21 +; AVX512VLDQ-NEXT: je LBB12_7 +; AVX512VLDQ-NEXT: LBB12_23: ## %cond.load21 ; AVX512VLDQ-NEXT: vpinsrb $6, (%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: incq %rdi ; AVX512VLDQ-NEXT: testb %al, %al -; AVX512VLDQ-NEXT: jns LBB12_16 -; AVX512VLDQ-NEXT: LBB12_15: ## %cond.load25 +; AVX512VLDQ-NEXT: jns LBB12_8 +; AVX512VLDQ-NEXT: LBB12_24: ## %cond.load25 ; AVX512VLDQ-NEXT: vpinsrb $7, (%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: incq %rdi ; AVX512VLDQ-NEXT: testl $256, %eax ## imm = 0x100 -; AVX512VLDQ-NEXT: je LBB12_18 -; AVX512VLDQ-NEXT: LBB12_17: ## %cond.load29 +; AVX512VLDQ-NEXT: je LBB12_9 +; AVX512VLDQ-NEXT: LBB12_25: ## %cond.load29 ; AVX512VLDQ-NEXT: vpinsrb $8, (%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: incq %rdi ; AVX512VLDQ-NEXT: testl $512, %eax ## imm = 0x200 -; AVX512VLDQ-NEXT: je LBB12_20 -; AVX512VLDQ-NEXT: LBB12_19: ## %cond.load33 +; AVX512VLDQ-NEXT: je LBB12_10 +; AVX512VLDQ-NEXT: LBB12_26: ## %cond.load33 ; AVX512VLDQ-NEXT: vpinsrb $9, (%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: incq %rdi ; AVX512VLDQ-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX512VLDQ-NEXT: je LBB12_22 -; AVX512VLDQ-NEXT: LBB12_21: ## %cond.load37 +; AVX512VLDQ-NEXT: je LBB12_11 +; AVX512VLDQ-NEXT: LBB12_27: ## %cond.load37 ; AVX512VLDQ-NEXT: vpinsrb $10, (%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: incq %rdi ; AVX512VLDQ-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX512VLDQ-NEXT: je LBB12_24 -; AVX512VLDQ-NEXT: LBB12_23: ## %cond.load41 +; AVX512VLDQ-NEXT: je LBB12_12 +; AVX512VLDQ-NEXT: LBB12_28: ## %cond.load41 ; AVX512VLDQ-NEXT: vpinsrb $11, (%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: incq %rdi ; AVX512VLDQ-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX512VLDQ-NEXT: je LBB12_26 -; AVX512VLDQ-NEXT: LBB12_25: ## %cond.load45 +; AVX512VLDQ-NEXT: je LBB12_13 +; AVX512VLDQ-NEXT: LBB12_29: ## %cond.load45 ; AVX512VLDQ-NEXT: vpinsrb $12, (%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: incq %rdi ; AVX512VLDQ-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX512VLDQ-NEXT: je LBB12_28 -; AVX512VLDQ-NEXT: LBB12_27: ## %cond.load49 +; AVX512VLDQ-NEXT: je LBB12_14 +; AVX512VLDQ-NEXT: LBB12_30: ## %cond.load49 ; AVX512VLDQ-NEXT: vpinsrb $13, (%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: incq %rdi ; AVX512VLDQ-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX512VLDQ-NEXT: je LBB12_30 -; AVX512VLDQ-NEXT: LBB12_29: ## %cond.load53 +; AVX512VLDQ-NEXT: je LBB12_15 +; AVX512VLDQ-NEXT: LBB12_31: ## %cond.load53 ; AVX512VLDQ-NEXT: vpinsrb $14, (%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: incq %rdi ; AVX512VLDQ-NEXT: testl $32768, %eax ## imm = 0x8000 -; AVX512VLDQ-NEXT: je LBB12_32 -; AVX512VLDQ-NEXT: LBB12_31: ## %cond.load57 +; AVX512VLDQ-NEXT: je LBB12_16 +; AVX512VLDQ-NEXT: LBB12_32: ## %cond.load57 ; AVX512VLDQ-NEXT: vpinsrb $15, (%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: retq ; @@ -3954,130 +3954,130 @@ define <16 x i8> @expandload_v16i8_v16i8(ptr %base, <16 x i8> %src0, <16 x i8> % ; AVX512VLBW-NEXT: vptestnmb %xmm1, %xmm1, %k0 ; AVX512VLBW-NEXT: kmovd %k0, %eax ; AVX512VLBW-NEXT: testb $1, %al -; AVX512VLBW-NEXT: jne LBB12_1 -; AVX512VLBW-NEXT: ## %bb.2: ## %else +; AVX512VLBW-NEXT: jne LBB12_17 +; AVX512VLBW-NEXT: ## %bb.1: ## %else ; AVX512VLBW-NEXT: testb $2, %al -; AVX512VLBW-NEXT: jne LBB12_3 -; AVX512VLBW-NEXT: LBB12_4: ## %else2 +; AVX512VLBW-NEXT: jne LBB12_18 +; AVX512VLBW-NEXT: LBB12_2: ## %else2 ; AVX512VLBW-NEXT: testb $4, %al -; AVX512VLBW-NEXT: jne LBB12_5 -; AVX512VLBW-NEXT: LBB12_6: ## %else6 +; AVX512VLBW-NEXT: jne LBB12_19 +; AVX512VLBW-NEXT: LBB12_3: ## %else6 ; AVX512VLBW-NEXT: testb $8, %al -; AVX512VLBW-NEXT: jne LBB12_7 -; AVX512VLBW-NEXT: LBB12_8: ## %else10 +; AVX512VLBW-NEXT: jne LBB12_20 +; AVX512VLBW-NEXT: LBB12_4: ## %else10 ; AVX512VLBW-NEXT: testb $16, %al -; AVX512VLBW-NEXT: jne LBB12_9 -; AVX512VLBW-NEXT: LBB12_10: ## %else14 +; AVX512VLBW-NEXT: jne LBB12_21 +; AVX512VLBW-NEXT: LBB12_5: ## %else14 ; AVX512VLBW-NEXT: testb $32, %al -; AVX512VLBW-NEXT: jne LBB12_11 -; AVX512VLBW-NEXT: LBB12_12: ## %else18 +; AVX512VLBW-NEXT: jne LBB12_22 +; AVX512VLBW-NEXT: LBB12_6: ## %else18 ; AVX512VLBW-NEXT: testb $64, %al -; AVX512VLBW-NEXT: jne LBB12_13 -; AVX512VLBW-NEXT: LBB12_14: ## %else22 +; AVX512VLBW-NEXT: jne LBB12_23 +; AVX512VLBW-NEXT: LBB12_7: ## %else22 ; AVX512VLBW-NEXT: testb %al, %al -; AVX512VLBW-NEXT: js LBB12_15 -; AVX512VLBW-NEXT: LBB12_16: ## %else26 +; AVX512VLBW-NEXT: js LBB12_24 +; AVX512VLBW-NEXT: LBB12_8: ## %else26 ; AVX512VLBW-NEXT: testl $256, %eax ## imm = 0x100 -; AVX512VLBW-NEXT: jne LBB12_17 -; AVX512VLBW-NEXT: LBB12_18: ## %else30 +; AVX512VLBW-NEXT: jne LBB12_25 +; AVX512VLBW-NEXT: LBB12_9: ## %else30 ; AVX512VLBW-NEXT: testl $512, %eax ## imm = 0x200 -; AVX512VLBW-NEXT: jne LBB12_19 -; AVX512VLBW-NEXT: LBB12_20: ## %else34 +; AVX512VLBW-NEXT: jne LBB12_26 +; AVX512VLBW-NEXT: LBB12_10: ## %else34 ; AVX512VLBW-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX512VLBW-NEXT: jne LBB12_21 -; AVX512VLBW-NEXT: LBB12_22: ## %else38 +; AVX512VLBW-NEXT: jne LBB12_27 +; AVX512VLBW-NEXT: LBB12_11: ## %else38 ; AVX512VLBW-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX512VLBW-NEXT: jne LBB12_23 -; AVX512VLBW-NEXT: LBB12_24: ## %else42 +; AVX512VLBW-NEXT: jne LBB12_28 +; AVX512VLBW-NEXT: LBB12_12: ## %else42 ; AVX512VLBW-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX512VLBW-NEXT: jne LBB12_25 -; AVX512VLBW-NEXT: LBB12_26: ## %else46 +; AVX512VLBW-NEXT: jne LBB12_29 +; AVX512VLBW-NEXT: LBB12_13: ## %else46 ; AVX512VLBW-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX512VLBW-NEXT: jne LBB12_27 -; AVX512VLBW-NEXT: LBB12_28: ## %else50 +; AVX512VLBW-NEXT: jne LBB12_30 +; AVX512VLBW-NEXT: LBB12_14: ## %else50 ; AVX512VLBW-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX512VLBW-NEXT: jne LBB12_29 -; AVX512VLBW-NEXT: LBB12_30: ## %else54 -; AVX512VLBW-NEXT: testl $32768, %eax ## imm = 0x8000 ; AVX512VLBW-NEXT: jne LBB12_31 -; AVX512VLBW-NEXT: LBB12_32: ## %else58 +; AVX512VLBW-NEXT: LBB12_15: ## %else54 +; AVX512VLBW-NEXT: testl $32768, %eax ## imm = 0x8000 +; AVX512VLBW-NEXT: jne LBB12_32 +; AVX512VLBW-NEXT: LBB12_16: ## %else58 ; AVX512VLBW-NEXT: retq -; AVX512VLBW-NEXT: LBB12_1: ## %cond.load +; AVX512VLBW-NEXT: LBB12_17: ## %cond.load ; AVX512VLBW-NEXT: vpinsrb $0, (%rdi), %xmm0, %xmm0 ; AVX512VLBW-NEXT: incq %rdi ; AVX512VLBW-NEXT: testb $2, %al -; AVX512VLBW-NEXT: je LBB12_4 -; AVX512VLBW-NEXT: LBB12_3: ## %cond.load1 +; AVX512VLBW-NEXT: je LBB12_2 +; AVX512VLBW-NEXT: LBB12_18: ## %cond.load1 ; AVX512VLBW-NEXT: vpinsrb $1, (%rdi), %xmm0, %xmm0 ; AVX512VLBW-NEXT: incq %rdi ; AVX512VLBW-NEXT: testb $4, %al -; AVX512VLBW-NEXT: je LBB12_6 -; AVX512VLBW-NEXT: LBB12_5: ## %cond.load5 +; AVX512VLBW-NEXT: je LBB12_3 +; AVX512VLBW-NEXT: LBB12_19: ## %cond.load5 ; AVX512VLBW-NEXT: vpinsrb $2, (%rdi), %xmm0, %xmm0 ; AVX512VLBW-NEXT: incq %rdi ; AVX512VLBW-NEXT: testb $8, %al -; AVX512VLBW-NEXT: je LBB12_8 -; AVX512VLBW-NEXT: LBB12_7: ## %cond.load9 +; AVX512VLBW-NEXT: je LBB12_4 +; AVX512VLBW-NEXT: LBB12_20: ## %cond.load9 ; AVX512VLBW-NEXT: vpinsrb $3, (%rdi), %xmm0, %xmm0 ; AVX512VLBW-NEXT: incq %rdi ; AVX512VLBW-NEXT: testb $16, %al -; AVX512VLBW-NEXT: je LBB12_10 -; AVX512VLBW-NEXT: LBB12_9: ## %cond.load13 +; AVX512VLBW-NEXT: je LBB12_5 +; AVX512VLBW-NEXT: LBB12_21: ## %cond.load13 ; AVX512VLBW-NEXT: vpinsrb $4, (%rdi), %xmm0, %xmm0 ; AVX512VLBW-NEXT: incq %rdi ; AVX512VLBW-NEXT: testb $32, %al -; AVX512VLBW-NEXT: je LBB12_12 -; AVX512VLBW-NEXT: LBB12_11: ## %cond.load17 +; AVX512VLBW-NEXT: je LBB12_6 +; AVX512VLBW-NEXT: LBB12_22: ## %cond.load17 ; AVX512VLBW-NEXT: vpinsrb $5, (%rdi), %xmm0, %xmm0 ; AVX512VLBW-NEXT: incq %rdi ; AVX512VLBW-NEXT: testb $64, %al -; AVX512VLBW-NEXT: je LBB12_14 -; AVX512VLBW-NEXT: LBB12_13: ## %cond.load21 +; AVX512VLBW-NEXT: je LBB12_7 +; AVX512VLBW-NEXT: LBB12_23: ## %cond.load21 ; AVX512VLBW-NEXT: vpinsrb $6, (%rdi), %xmm0, %xmm0 ; AVX512VLBW-NEXT: incq %rdi ; AVX512VLBW-NEXT: testb %al, %al -; AVX512VLBW-NEXT: jns LBB12_16 -; AVX512VLBW-NEXT: LBB12_15: ## %cond.load25 +; AVX512VLBW-NEXT: jns LBB12_8 +; AVX512VLBW-NEXT: LBB12_24: ## %cond.load25 ; AVX512VLBW-NEXT: vpinsrb $7, (%rdi), %xmm0, %xmm0 ; AVX512VLBW-NEXT: incq %rdi ; AVX512VLBW-NEXT: testl $256, %eax ## imm = 0x100 -; AVX512VLBW-NEXT: je LBB12_18 -; AVX512VLBW-NEXT: LBB12_17: ## %cond.load29 +; AVX512VLBW-NEXT: je LBB12_9 +; AVX512VLBW-NEXT: LBB12_25: ## %cond.load29 ; AVX512VLBW-NEXT: vpinsrb $8, (%rdi), %xmm0, %xmm0 ; AVX512VLBW-NEXT: incq %rdi ; AVX512VLBW-NEXT: testl $512, %eax ## imm = 0x200 -; AVX512VLBW-NEXT: je LBB12_20 -; AVX512VLBW-NEXT: LBB12_19: ## %cond.load33 +; AVX512VLBW-NEXT: je LBB12_10 +; AVX512VLBW-NEXT: LBB12_26: ## %cond.load33 ; AVX512VLBW-NEXT: vpinsrb $9, (%rdi), %xmm0, %xmm0 ; AVX512VLBW-NEXT: incq %rdi ; AVX512VLBW-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX512VLBW-NEXT: je LBB12_22 -; AVX512VLBW-NEXT: LBB12_21: ## %cond.load37 +; AVX512VLBW-NEXT: je LBB12_11 +; AVX512VLBW-NEXT: LBB12_27: ## %cond.load37 ; AVX512VLBW-NEXT: vpinsrb $10, (%rdi), %xmm0, %xmm0 ; AVX512VLBW-NEXT: incq %rdi ; AVX512VLBW-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX512VLBW-NEXT: je LBB12_24 -; AVX512VLBW-NEXT: LBB12_23: ## %cond.load41 +; AVX512VLBW-NEXT: je LBB12_12 +; AVX512VLBW-NEXT: LBB12_28: ## %cond.load41 ; AVX512VLBW-NEXT: vpinsrb $11, (%rdi), %xmm0, %xmm0 ; AVX512VLBW-NEXT: incq %rdi ; AVX512VLBW-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX512VLBW-NEXT: je LBB12_26 -; AVX512VLBW-NEXT: LBB12_25: ## %cond.load45 +; AVX512VLBW-NEXT: je LBB12_13 +; AVX512VLBW-NEXT: LBB12_29: ## %cond.load45 ; AVX512VLBW-NEXT: vpinsrb $12, (%rdi), %xmm0, %xmm0 ; AVX512VLBW-NEXT: incq %rdi ; AVX512VLBW-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX512VLBW-NEXT: je LBB12_28 -; AVX512VLBW-NEXT: LBB12_27: ## %cond.load49 +; AVX512VLBW-NEXT: je LBB12_14 +; AVX512VLBW-NEXT: LBB12_30: ## %cond.load49 ; AVX512VLBW-NEXT: vpinsrb $13, (%rdi), %xmm0, %xmm0 ; AVX512VLBW-NEXT: incq %rdi ; AVX512VLBW-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX512VLBW-NEXT: je LBB12_30 -; AVX512VLBW-NEXT: LBB12_29: ## %cond.load53 +; AVX512VLBW-NEXT: je LBB12_15 +; AVX512VLBW-NEXT: LBB12_31: ## %cond.load53 ; AVX512VLBW-NEXT: vpinsrb $14, (%rdi), %xmm0, %xmm0 ; AVX512VLBW-NEXT: incq %rdi ; AVX512VLBW-NEXT: testl $32768, %eax ## imm = 0x8000 -; AVX512VLBW-NEXT: je LBB12_32 -; AVX512VLBW-NEXT: LBB12_31: ## %cond.load57 +; AVX512VLBW-NEXT: je LBB12_16 +; AVX512VLBW-NEXT: LBB12_32: ## %cond.load57 ; AVX512VLBW-NEXT: vpinsrb $15, (%rdi), %xmm0, %xmm0 ; AVX512VLBW-NEXT: retq %mask = icmp eq <16 x i8> %trigger, zeroinitializer diff --git a/llvm/test/CodeGen/X86/masked_gather.ll b/llvm/test/CodeGen/X86/masked_gather.ll index 2913fe13095ca..8f6e6c5f5a874 100644 --- a/llvm/test/CodeGen/X86/masked_gather.ll +++ b/llvm/test/CodeGen/X86/masked_gather.ll @@ -21,36 +21,36 @@ define <4 x float> @gather_v4f32_ptr_v4i32(<4 x ptr> %ptr, <4 x i32> %trigger, < ; SSE-NEXT: pcmpeqd %xmm2, %xmm4 ; SSE-NEXT: movmskps %xmm4, %eax ; SSE-NEXT: testb $1, %al -; SSE-NEXT: jne .LBB0_1 -; SSE-NEXT: # %bb.2: # %else +; SSE-NEXT: jne .LBB0_5 +; SSE-NEXT: # %bb.1: # %else ; SSE-NEXT: testb $2, %al -; SSE-NEXT: jne .LBB0_3 -; SSE-NEXT: .LBB0_4: # %else2 +; SSE-NEXT: jne .LBB0_6 +; SSE-NEXT: .LBB0_2: # %else2 ; SSE-NEXT: testb $4, %al -; SSE-NEXT: jne .LBB0_5 -; SSE-NEXT: .LBB0_6: # %else5 -; SSE-NEXT: testb $8, %al ; SSE-NEXT: jne .LBB0_7 -; SSE-NEXT: .LBB0_8: # %else8 +; SSE-NEXT: .LBB0_3: # %else5 +; SSE-NEXT: testb $8, %al +; SSE-NEXT: jne .LBB0_8 +; SSE-NEXT: .LBB0_4: # %else8 ; SSE-NEXT: movaps %xmm3, %xmm0 ; SSE-NEXT: retq -; SSE-NEXT: .LBB0_1: # %cond.load +; SSE-NEXT: .LBB0_5: # %cond.load ; SSE-NEXT: movq %xmm0, %rcx ; SSE-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE-NEXT: pblendw {{.*#+}} xmm3 = xmm2[0,1],xmm3[2,3,4,5,6,7] ; SSE-NEXT: testb $2, %al -; SSE-NEXT: je .LBB0_4 -; SSE-NEXT: .LBB0_3: # %cond.load1 +; SSE-NEXT: je .LBB0_2 +; SSE-NEXT: .LBB0_6: # %cond.load1 ; SSE-NEXT: pextrq $1, %xmm0, %rcx ; SSE-NEXT: insertps {{.*#+}} xmm3 = xmm3[0],mem[0],xmm3[2,3] ; SSE-NEXT: testb $4, %al -; SSE-NEXT: je .LBB0_6 -; SSE-NEXT: .LBB0_5: # %cond.load4 +; SSE-NEXT: je .LBB0_3 +; SSE-NEXT: .LBB0_7: # %cond.load4 ; SSE-NEXT: movq %xmm1, %rcx ; SSE-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1],mem[0],xmm3[3] ; SSE-NEXT: testb $8, %al -; SSE-NEXT: je .LBB0_8 -; SSE-NEXT: .LBB0_7: # %cond.load7 +; SSE-NEXT: je .LBB0_4 +; SSE-NEXT: .LBB0_8: # %cond.load7 ; SSE-NEXT: pextrq $1, %xmm1, %rax ; SSE-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1,2],mem[0] ; SSE-NEXT: movaps %xmm3, %xmm0 @@ -76,20 +76,20 @@ define <4 x float> @gather_v4f32_ptr_v4i32(<4 x ptr> %ptr, <4 x i32> %trigger, < ; AVX1-NEXT: .LBB0_4: # %else2 ; AVX1-NEXT: testb $4, %al ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 -; AVX1-NEXT: jne .LBB0_5 -; AVX1-NEXT: # %bb.6: # %else5 -; AVX1-NEXT: testb $8, %al ; AVX1-NEXT: jne .LBB0_7 -; AVX1-NEXT: .LBB0_8: # %else8 +; AVX1-NEXT: # %bb.5: # %else5 +; AVX1-NEXT: testb $8, %al +; AVX1-NEXT: jne .LBB0_8 +; AVX1-NEXT: .LBB0_6: # %else8 ; AVX1-NEXT: vmovaps %xmm2, %xmm0 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB0_5: # %cond.load4 +; AVX1-NEXT: .LBB0_7: # %cond.load4 ; AVX1-NEXT: vmovq %xmm0, %rcx ; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3] ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB0_8 -; AVX1-NEXT: .LBB0_7: # %cond.load7 +; AVX1-NEXT: je .LBB0_6 +; AVX1-NEXT: .LBB0_8: # %cond.load7 ; AVX1-NEXT: vpextrq $1, %xmm0, %rax ; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],mem[0] ; AVX1-NEXT: vmovaps %xmm2, %xmm0 @@ -116,20 +116,20 @@ define <4 x float> @gather_v4f32_ptr_v4i32(<4 x ptr> %ptr, <4 x i32> %trigger, < ; AVX2-NOGATHER-NEXT: .LBB0_4: # %else2 ; AVX2-NOGATHER-NEXT: testb $4, %al ; AVX2-NOGATHER-NEXT: vextracti128 $1, %ymm0, %xmm0 -; AVX2-NOGATHER-NEXT: jne .LBB0_5 -; AVX2-NOGATHER-NEXT: # %bb.6: # %else5 -; AVX2-NOGATHER-NEXT: testb $8, %al ; AVX2-NOGATHER-NEXT: jne .LBB0_7 -; AVX2-NOGATHER-NEXT: .LBB0_8: # %else8 +; AVX2-NOGATHER-NEXT: # %bb.5: # %else5 +; AVX2-NOGATHER-NEXT: testb $8, %al +; AVX2-NOGATHER-NEXT: jne .LBB0_8 +; AVX2-NOGATHER-NEXT: .LBB0_6: # %else8 ; AVX2-NOGATHER-NEXT: vmovaps %xmm2, %xmm0 ; AVX2-NOGATHER-NEXT: vzeroupper ; AVX2-NOGATHER-NEXT: retq -; AVX2-NOGATHER-NEXT: .LBB0_5: # %cond.load4 +; AVX2-NOGATHER-NEXT: .LBB0_7: # %cond.load4 ; AVX2-NOGATHER-NEXT: vmovq %xmm0, %rcx ; AVX2-NOGATHER-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3] ; AVX2-NOGATHER-NEXT: testb $8, %al -; AVX2-NOGATHER-NEXT: je .LBB0_8 -; AVX2-NOGATHER-NEXT: .LBB0_7: # %cond.load7 +; AVX2-NOGATHER-NEXT: je .LBB0_6 +; AVX2-NOGATHER-NEXT: .LBB0_8: # %cond.load7 ; AVX2-NOGATHER-NEXT: vpextrq $1, %xmm0, %rax ; AVX2-NOGATHER-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],mem[0] ; AVX2-NOGATHER-NEXT: vmovaps %xmm2, %xmm0 @@ -165,20 +165,20 @@ define <4 x float> @gather_v4f32_ptr_v4i32(<4 x ptr> %ptr, <4 x i32> %trigger, < ; AVX512F-NEXT: .LBB0_4: # %else2 ; AVX512F-NEXT: testb $4, %al ; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm0 -; AVX512F-NEXT: jne .LBB0_5 -; AVX512F-NEXT: # %bb.6: # %else5 -; AVX512F-NEXT: testb $8, %al ; AVX512F-NEXT: jne .LBB0_7 -; AVX512F-NEXT: .LBB0_8: # %else8 +; AVX512F-NEXT: # %bb.5: # %else5 +; AVX512F-NEXT: testb $8, %al +; AVX512F-NEXT: jne .LBB0_8 +; AVX512F-NEXT: .LBB0_6: # %else8 ; AVX512F-NEXT: vmovaps %xmm2, %xmm0 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB0_5: # %cond.load4 +; AVX512F-NEXT: .LBB0_7: # %cond.load4 ; AVX512F-NEXT: vmovq %xmm0, %rcx ; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3] ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB0_8 -; AVX512F-NEXT: .LBB0_7: # %cond.load7 +; AVX512F-NEXT: je .LBB0_6 +; AVX512F-NEXT: .LBB0_8: # %cond.load7 ; AVX512F-NEXT: vpextrq $1, %xmm0, %rax ; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],mem[0] ; AVX512F-NEXT: vmovaps %xmm2, %xmm0 @@ -201,36 +201,36 @@ define <4 x float> @masked_gather_v4f32_ptr_v4i32(<4 x ptr> %ptr, i32 %trigger, ; SSE-LABEL: masked_gather_v4f32_ptr_v4i32: ; SSE: # %bb.0: ; SSE-NEXT: testb $1, %dil -; SSE-NEXT: jne .LBB1_1 -; SSE-NEXT: # %bb.2: # %else +; SSE-NEXT: jne .LBB1_5 +; SSE-NEXT: # %bb.1: # %else ; SSE-NEXT: testb $2, %dil -; SSE-NEXT: jne .LBB1_3 -; SSE-NEXT: .LBB1_4: # %else2 +; SSE-NEXT: jne .LBB1_6 +; SSE-NEXT: .LBB1_2: # %else2 ; SSE-NEXT: testb $4, %dil -; SSE-NEXT: jne .LBB1_5 -; SSE-NEXT: .LBB1_6: # %else5 -; SSE-NEXT: testb $8, %dil ; SSE-NEXT: jne .LBB1_7 -; SSE-NEXT: .LBB1_8: # %else8 +; SSE-NEXT: .LBB1_3: # %else5 +; SSE-NEXT: testb $8, %dil +; SSE-NEXT: jne .LBB1_8 +; SSE-NEXT: .LBB1_4: # %else8 ; SSE-NEXT: movaps %xmm2, %xmm0 ; SSE-NEXT: retq -; SSE-NEXT: .LBB1_1: # %cond.load +; SSE-NEXT: .LBB1_5: # %cond.load ; SSE-NEXT: movq %xmm0, %rax ; SSE-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero ; SSE-NEXT: movss {{.*#+}} xmm2 = xmm3[0],xmm2[1,2,3] ; SSE-NEXT: testb $2, %dil -; SSE-NEXT: je .LBB1_4 -; SSE-NEXT: .LBB1_3: # %cond.load1 +; SSE-NEXT: je .LBB1_2 +; SSE-NEXT: .LBB1_6: # %cond.load1 ; SSE-NEXT: pextrq $1, %xmm0, %rax ; SSE-NEXT: insertps {{.*#+}} xmm2 = xmm2[0],mem[0],xmm2[2,3] ; SSE-NEXT: testb $4, %dil -; SSE-NEXT: je .LBB1_6 -; SSE-NEXT: .LBB1_5: # %cond.load4 +; SSE-NEXT: je .LBB1_3 +; SSE-NEXT: .LBB1_7: # %cond.load4 ; SSE-NEXT: movq %xmm1, %rax ; SSE-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3] ; SSE-NEXT: testb $8, %dil -; SSE-NEXT: je .LBB1_8 -; SSE-NEXT: .LBB1_7: # %cond.load7 +; SSE-NEXT: je .LBB1_4 +; SSE-NEXT: .LBB1_8: # %cond.load7 ; SSE-NEXT: pextrq $1, %xmm1, %rax ; SSE-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1,2],mem[0] ; SSE-NEXT: movaps %xmm2, %xmm0 @@ -253,20 +253,20 @@ define <4 x float> @masked_gather_v4f32_ptr_v4i32(<4 x ptr> %ptr, i32 %trigger, ; AVX1-NEXT: .LBB1_4: # %else2 ; AVX1-NEXT: testb $4, %dil ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 -; AVX1-NEXT: jne .LBB1_5 -; AVX1-NEXT: # %bb.6: # %else5 -; AVX1-NEXT: testb $8, %dil ; AVX1-NEXT: jne .LBB1_7 -; AVX1-NEXT: .LBB1_8: # %else8 +; AVX1-NEXT: # %bb.5: # %else5 +; AVX1-NEXT: testb $8, %dil +; AVX1-NEXT: jne .LBB1_8 +; AVX1-NEXT: .LBB1_6: # %else8 ; AVX1-NEXT: vmovaps %xmm1, %xmm0 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB1_5: # %cond.load4 +; AVX1-NEXT: .LBB1_7: # %cond.load4 ; AVX1-NEXT: vmovq %xmm0, %rax ; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],mem[0],xmm1[3] ; AVX1-NEXT: testb $8, %dil -; AVX1-NEXT: je .LBB1_8 -; AVX1-NEXT: .LBB1_7: # %cond.load7 +; AVX1-NEXT: je .LBB1_6 +; AVX1-NEXT: .LBB1_8: # %cond.load7 ; AVX1-NEXT: vpextrq $1, %xmm0, %rax ; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],mem[0] ; AVX1-NEXT: vmovaps %xmm1, %xmm0 @@ -290,20 +290,20 @@ define <4 x float> @masked_gather_v4f32_ptr_v4i32(<4 x ptr> %ptr, i32 %trigger, ; AVX2-NOGATHER-NEXT: .LBB1_4: # %else2 ; AVX2-NOGATHER-NEXT: testb $4, %dil ; AVX2-NOGATHER-NEXT: vextracti128 $1, %ymm0, %xmm0 -; AVX2-NOGATHER-NEXT: jne .LBB1_5 -; AVX2-NOGATHER-NEXT: # %bb.6: # %else5 -; AVX2-NOGATHER-NEXT: testb $8, %dil ; AVX2-NOGATHER-NEXT: jne .LBB1_7 -; AVX2-NOGATHER-NEXT: .LBB1_8: # %else8 +; AVX2-NOGATHER-NEXT: # %bb.5: # %else5 +; AVX2-NOGATHER-NEXT: testb $8, %dil +; AVX2-NOGATHER-NEXT: jne .LBB1_8 +; AVX2-NOGATHER-NEXT: .LBB1_6: # %else8 ; AVX2-NOGATHER-NEXT: vmovaps %xmm1, %xmm0 ; AVX2-NOGATHER-NEXT: vzeroupper ; AVX2-NOGATHER-NEXT: retq -; AVX2-NOGATHER-NEXT: .LBB1_5: # %cond.load4 +; AVX2-NOGATHER-NEXT: .LBB1_7: # %cond.load4 ; AVX2-NOGATHER-NEXT: vmovq %xmm0, %rax ; AVX2-NOGATHER-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],mem[0],xmm1[3] ; AVX2-NOGATHER-NEXT: testb $8, %dil -; AVX2-NOGATHER-NEXT: je .LBB1_8 -; AVX2-NOGATHER-NEXT: .LBB1_7: # %cond.load7 +; AVX2-NOGATHER-NEXT: je .LBB1_6 +; AVX2-NOGATHER-NEXT: .LBB1_8: # %cond.load7 ; AVX2-NOGATHER-NEXT: vpextrq $1, %xmm0, %rax ; AVX2-NOGATHER-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],mem[0] ; AVX2-NOGATHER-NEXT: vmovaps %xmm1, %xmm0 @@ -339,20 +339,20 @@ define <4 x float> @masked_gather_v4f32_ptr_v4i32(<4 x ptr> %ptr, i32 %trigger, ; AVX512F-NEXT: .LBB1_4: # %else2 ; AVX512F-NEXT: testb $4, %dil ; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm0 -; AVX512F-NEXT: jne .LBB1_5 -; AVX512F-NEXT: # %bb.6: # %else5 -; AVX512F-NEXT: testb $8, %dil ; AVX512F-NEXT: jne .LBB1_7 -; AVX512F-NEXT: .LBB1_8: # %else8 +; AVX512F-NEXT: # %bb.5: # %else5 +; AVX512F-NEXT: testb $8, %dil +; AVX512F-NEXT: jne .LBB1_8 +; AVX512F-NEXT: .LBB1_6: # %else8 ; AVX512F-NEXT: vmovaps %xmm1, %xmm0 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB1_5: # %cond.load4 +; AVX512F-NEXT: .LBB1_7: # %cond.load4 ; AVX512F-NEXT: vmovq %xmm0, %rax ; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],mem[0],xmm1[3] ; AVX512F-NEXT: testb $8, %dil -; AVX512F-NEXT: je .LBB1_8 -; AVX512F-NEXT: .LBB1_7: # %cond.load7 +; AVX512F-NEXT: je .LBB1_6 +; AVX512F-NEXT: .LBB1_8: # %cond.load7 ; AVX512F-NEXT: vpextrq $1, %xmm0, %rax ; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],mem[0] ; AVX512F-NEXT: vmovaps %xmm1, %xmm0 @@ -401,19 +401,19 @@ define <4 x float> @gather_v4f32_v4i32_v4i32(ptr %base, <4 x i32> %idx, <4 x i32 ; SSE-NEXT: .LBB2_4: # %else2 ; SSE-NEXT: paddq %xmm0, %xmm3 ; SSE-NEXT: testb $4, %al -; SSE-NEXT: jne .LBB2_5 -; SSE-NEXT: # %bb.6: # %else5 -; SSE-NEXT: testb $8, %al ; SSE-NEXT: jne .LBB2_7 -; SSE-NEXT: .LBB2_8: # %else8 +; SSE-NEXT: # %bb.5: # %else5 +; SSE-NEXT: testb $8, %al +; SSE-NEXT: jne .LBB2_8 +; SSE-NEXT: .LBB2_6: # %else8 ; SSE-NEXT: movaps %xmm2, %xmm0 ; SSE-NEXT: retq -; SSE-NEXT: .LBB2_5: # %cond.load4 +; SSE-NEXT: .LBB2_7: # %cond.load4 ; SSE-NEXT: movq %xmm3, %rcx ; SSE-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3] ; SSE-NEXT: testb $8, %al -; SSE-NEXT: je .LBB2_8 -; SSE-NEXT: .LBB2_7: # %cond.load7 +; SSE-NEXT: je .LBB2_6 +; SSE-NEXT: .LBB2_8: # %cond.load7 ; SSE-NEXT: pextrq $1, %xmm3, %rax ; SSE-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1,2],mem[0] ; SSE-NEXT: movaps %xmm2, %xmm0 @@ -449,20 +449,20 @@ define <4 x float> @gather_v4f32_v4i32_v4i32(ptr %base, <4 x i32> %idx, <4 x i32 ; AVX1-NEXT: .LBB2_4: # %else2 ; AVX1-NEXT: testb $4, %al ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 -; AVX1-NEXT: jne .LBB2_5 -; AVX1-NEXT: # %bb.6: # %else5 -; AVX1-NEXT: testb $8, %al ; AVX1-NEXT: jne .LBB2_7 -; AVX1-NEXT: .LBB2_8: # %else8 +; AVX1-NEXT: # %bb.5: # %else5 +; AVX1-NEXT: testb $8, %al +; AVX1-NEXT: jne .LBB2_8 +; AVX1-NEXT: .LBB2_6: # %else8 ; AVX1-NEXT: vmovaps %xmm2, %xmm0 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB2_5: # %cond.load4 +; AVX1-NEXT: .LBB2_7: # %cond.load4 ; AVX1-NEXT: vmovq %xmm0, %rcx ; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3] ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB2_8 -; AVX1-NEXT: .LBB2_7: # %cond.load7 +; AVX1-NEXT: je .LBB2_6 +; AVX1-NEXT: .LBB2_8: # %cond.load7 ; AVX1-NEXT: vpextrq $1, %xmm0, %rax ; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],mem[0] ; AVX1-NEXT: vmovaps %xmm2, %xmm0 @@ -494,20 +494,20 @@ define <4 x float> @gather_v4f32_v4i32_v4i32(ptr %base, <4 x i32> %idx, <4 x i32 ; AVX2-NOGATHER-NEXT: .LBB2_4: # %else2 ; AVX2-NOGATHER-NEXT: testb $4, %al ; AVX2-NOGATHER-NEXT: vextracti128 $1, %ymm0, %xmm0 -; AVX2-NOGATHER-NEXT: jne .LBB2_5 -; AVX2-NOGATHER-NEXT: # %bb.6: # %else5 -; AVX2-NOGATHER-NEXT: testb $8, %al ; AVX2-NOGATHER-NEXT: jne .LBB2_7 -; AVX2-NOGATHER-NEXT: .LBB2_8: # %else8 +; AVX2-NOGATHER-NEXT: # %bb.5: # %else5 +; AVX2-NOGATHER-NEXT: testb $8, %al +; AVX2-NOGATHER-NEXT: jne .LBB2_8 +; AVX2-NOGATHER-NEXT: .LBB2_6: # %else8 ; AVX2-NOGATHER-NEXT: vmovaps %xmm2, %xmm0 ; AVX2-NOGATHER-NEXT: vzeroupper ; AVX2-NOGATHER-NEXT: retq -; AVX2-NOGATHER-NEXT: .LBB2_5: # %cond.load4 +; AVX2-NOGATHER-NEXT: .LBB2_7: # %cond.load4 ; AVX2-NOGATHER-NEXT: vmovq %xmm0, %rcx ; AVX2-NOGATHER-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3] ; AVX2-NOGATHER-NEXT: testb $8, %al -; AVX2-NOGATHER-NEXT: je .LBB2_8 -; AVX2-NOGATHER-NEXT: .LBB2_7: # %cond.load7 +; AVX2-NOGATHER-NEXT: je .LBB2_6 +; AVX2-NOGATHER-NEXT: .LBB2_8: # %cond.load7 ; AVX2-NOGATHER-NEXT: vpextrq $1, %xmm0, %rax ; AVX2-NOGATHER-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],mem[0] ; AVX2-NOGATHER-NEXT: vmovaps %xmm2, %xmm0 @@ -547,20 +547,20 @@ define <4 x float> @gather_v4f32_v4i32_v4i32(ptr %base, <4 x i32> %idx, <4 x i32 ; AVX512F-NEXT: .LBB2_4: # %else2 ; AVX512F-NEXT: testb $4, %al ; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm0 -; AVX512F-NEXT: jne .LBB2_5 -; AVX512F-NEXT: # %bb.6: # %else5 -; AVX512F-NEXT: testb $8, %al ; AVX512F-NEXT: jne .LBB2_7 -; AVX512F-NEXT: .LBB2_8: # %else8 +; AVX512F-NEXT: # %bb.5: # %else5 +; AVX512F-NEXT: testb $8, %al +; AVX512F-NEXT: jne .LBB2_8 +; AVX512F-NEXT: .LBB2_6: # %else8 ; AVX512F-NEXT: vmovaps %xmm2, %xmm0 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB2_5: # %cond.load4 +; AVX512F-NEXT: .LBB2_7: # %cond.load4 ; AVX512F-NEXT: vmovq %xmm0, %rcx ; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3] ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB2_8 -; AVX512F-NEXT: .LBB2_7: # %cond.load7 +; AVX512F-NEXT: je .LBB2_6 +; AVX512F-NEXT: .LBB2_8: # %cond.load7 ; AVX512F-NEXT: vpextrq $1, %xmm0, %rax ; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],mem[0] ; AVX512F-NEXT: vmovaps %xmm2, %xmm0 @@ -608,19 +608,19 @@ define <4 x float> @gather_v4f32_v4i64_v4i32(ptr %base, <4 x i64> %idx, <4 x i32 ; SSE-NEXT: .LBB3_4: # %else2 ; SSE-NEXT: paddq %xmm1, %xmm4 ; SSE-NEXT: testb $4, %al -; SSE-NEXT: jne .LBB3_5 -; SSE-NEXT: # %bb.6: # %else5 -; SSE-NEXT: testb $8, %al ; SSE-NEXT: jne .LBB3_7 -; SSE-NEXT: .LBB3_8: # %else8 +; SSE-NEXT: # %bb.5: # %else5 +; SSE-NEXT: testb $8, %al +; SSE-NEXT: jne .LBB3_8 +; SSE-NEXT: .LBB3_6: # %else8 ; SSE-NEXT: movaps %xmm3, %xmm0 ; SSE-NEXT: retq -; SSE-NEXT: .LBB3_5: # %cond.load4 +; SSE-NEXT: .LBB3_7: # %cond.load4 ; SSE-NEXT: movq %xmm4, %rcx ; SSE-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1],mem[0],xmm3[3] ; SSE-NEXT: testb $8, %al -; SSE-NEXT: je .LBB3_8 -; SSE-NEXT: .LBB3_7: # %cond.load7 +; SSE-NEXT: je .LBB3_6 +; SSE-NEXT: .LBB3_8: # %cond.load7 ; SSE-NEXT: pextrq $1, %xmm4, %rax ; SSE-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1,2],mem[0] ; SSE-NEXT: movaps %xmm3, %xmm0 @@ -654,20 +654,20 @@ define <4 x float> @gather_v4f32_v4i64_v4i32(ptr %base, <4 x i64> %idx, <4 x i32 ; AVX1-NEXT: .LBB3_4: # %else2 ; AVX1-NEXT: testb $4, %al ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 -; AVX1-NEXT: jne .LBB3_5 -; AVX1-NEXT: # %bb.6: # %else5 -; AVX1-NEXT: testb $8, %al ; AVX1-NEXT: jne .LBB3_7 -; AVX1-NEXT: .LBB3_8: # %else8 +; AVX1-NEXT: # %bb.5: # %else5 +; AVX1-NEXT: testb $8, %al +; AVX1-NEXT: jne .LBB3_8 +; AVX1-NEXT: .LBB3_6: # %else8 ; AVX1-NEXT: vmovaps %xmm2, %xmm0 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB3_5: # %cond.load4 +; AVX1-NEXT: .LBB3_7: # %cond.load4 ; AVX1-NEXT: vmovq %xmm0, %rcx ; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3] ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB3_8 -; AVX1-NEXT: .LBB3_7: # %cond.load7 +; AVX1-NEXT: je .LBB3_6 +; AVX1-NEXT: .LBB3_8: # %cond.load7 ; AVX1-NEXT: vpextrq $1, %xmm0, %rax ; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],mem[0] ; AVX1-NEXT: vmovaps %xmm2, %xmm0 @@ -698,20 +698,20 @@ define <4 x float> @gather_v4f32_v4i64_v4i32(ptr %base, <4 x i64> %idx, <4 x i32 ; AVX2-NOGATHER-NEXT: .LBB3_4: # %else2 ; AVX2-NOGATHER-NEXT: testb $4, %al ; AVX2-NOGATHER-NEXT: vextracti128 $1, %ymm0, %xmm0 -; AVX2-NOGATHER-NEXT: jne .LBB3_5 -; AVX2-NOGATHER-NEXT: # %bb.6: # %else5 -; AVX2-NOGATHER-NEXT: testb $8, %al ; AVX2-NOGATHER-NEXT: jne .LBB3_7 -; AVX2-NOGATHER-NEXT: .LBB3_8: # %else8 +; AVX2-NOGATHER-NEXT: # %bb.5: # %else5 +; AVX2-NOGATHER-NEXT: testb $8, %al +; AVX2-NOGATHER-NEXT: jne .LBB3_8 +; AVX2-NOGATHER-NEXT: .LBB3_6: # %else8 ; AVX2-NOGATHER-NEXT: vmovaps %xmm2, %xmm0 ; AVX2-NOGATHER-NEXT: vzeroupper ; AVX2-NOGATHER-NEXT: retq -; AVX2-NOGATHER-NEXT: .LBB3_5: # %cond.load4 +; AVX2-NOGATHER-NEXT: .LBB3_7: # %cond.load4 ; AVX2-NOGATHER-NEXT: vmovq %xmm0, %rcx ; AVX2-NOGATHER-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3] ; AVX2-NOGATHER-NEXT: testb $8, %al -; AVX2-NOGATHER-NEXT: je .LBB3_8 -; AVX2-NOGATHER-NEXT: .LBB3_7: # %cond.load7 +; AVX2-NOGATHER-NEXT: je .LBB3_6 +; AVX2-NOGATHER-NEXT: .LBB3_8: # %cond.load7 ; AVX2-NOGATHER-NEXT: vpextrq $1, %xmm0, %rax ; AVX2-NOGATHER-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],mem[0] ; AVX2-NOGATHER-NEXT: vmovaps %xmm2, %xmm0 @@ -751,20 +751,20 @@ define <4 x float> @gather_v4f32_v4i64_v4i32(ptr %base, <4 x i64> %idx, <4 x i32 ; AVX512F-NEXT: .LBB3_4: # %else2 ; AVX512F-NEXT: testb $4, %al ; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm0 -; AVX512F-NEXT: jne .LBB3_5 -; AVX512F-NEXT: # %bb.6: # %else5 -; AVX512F-NEXT: testb $8, %al ; AVX512F-NEXT: jne .LBB3_7 -; AVX512F-NEXT: .LBB3_8: # %else8 +; AVX512F-NEXT: # %bb.5: # %else5 +; AVX512F-NEXT: testb $8, %al +; AVX512F-NEXT: jne .LBB3_8 +; AVX512F-NEXT: .LBB3_6: # %else8 ; AVX512F-NEXT: vmovaps %xmm2, %xmm0 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB3_5: # %cond.load4 +; AVX512F-NEXT: .LBB3_7: # %cond.load4 ; AVX512F-NEXT: vmovq %xmm0, %rcx ; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3] ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB3_8 -; AVX512F-NEXT: .LBB3_7: # %cond.load7 +; AVX512F-NEXT: je .LBB3_6 +; AVX512F-NEXT: .LBB3_8: # %cond.load7 ; AVX512F-NEXT: vpextrq $1, %xmm0, %rax ; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],mem[0] ; AVX512F-NEXT: vmovaps %xmm2, %xmm0 @@ -904,19 +904,19 @@ define <16 x i8> @gather_v16i8_v16i32_v16i8(ptr %base, <16 x i32> %idx, <16 x i8 ; SSE-NEXT: .LBB4_28: # %else38 ; SSE-NEXT: paddq %xmm1, %xmm6 ; SSE-NEXT: testl $16384, %eax # imm = 0x4000 -; SSE-NEXT: jne .LBB4_29 -; SSE-NEXT: # %bb.30: # %else41 -; SSE-NEXT: testl $32768, %eax # imm = 0x8000 ; SSE-NEXT: jne .LBB4_31 -; SSE-NEXT: .LBB4_32: # %else44 +; SSE-NEXT: # %bb.29: # %else41 +; SSE-NEXT: testl $32768, %eax # imm = 0x8000 +; SSE-NEXT: jne .LBB4_32 +; SSE-NEXT: .LBB4_30: # %else44 ; SSE-NEXT: movdqa %xmm5, %xmm0 ; SSE-NEXT: retq -; SSE-NEXT: .LBB4_29: # %cond.load40 +; SSE-NEXT: .LBB4_31: # %cond.load40 ; SSE-NEXT: movq %xmm6, %rcx ; SSE-NEXT: pinsrb $14, (%rcx), %xmm5 ; SSE-NEXT: testl $32768, %eax # imm = 0x8000 -; SSE-NEXT: je .LBB4_32 -; SSE-NEXT: .LBB4_31: # %cond.load43 +; SSE-NEXT: je .LBB4_30 +; SSE-NEXT: .LBB4_32: # %cond.load43 ; SSE-NEXT: pextrq $1, %xmm6, %rax ; SSE-NEXT: pinsrb $15, (%rax), %xmm5 ; SSE-NEXT: movdqa %xmm5, %xmm0 @@ -1044,20 +1044,20 @@ define <16 x i8> @gather_v16i8_v16i32_v16i8(ptr %base, <16 x i32> %idx, <16 x i8 ; AVX1-NEXT: .LBB4_28: # %else38 ; AVX1-NEXT: testl $16384, %eax # imm = 0x4000 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 -; AVX1-NEXT: jne .LBB4_29 -; AVX1-NEXT: # %bb.30: # %else41 -; AVX1-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX1-NEXT: jne .LBB4_31 -; AVX1-NEXT: .LBB4_32: # %else44 +; AVX1-NEXT: # %bb.29: # %else41 +; AVX1-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX1-NEXT: jne .LBB4_32 +; AVX1-NEXT: .LBB4_30: # %else44 ; AVX1-NEXT: vmovdqa %xmm3, %xmm0 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB4_29: # %cond.load40 +; AVX1-NEXT: .LBB4_31: # %cond.load40 ; AVX1-NEXT: vmovq %xmm0, %rcx ; AVX1-NEXT: vpinsrb $14, (%rcx), %xmm3, %xmm3 ; AVX1-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX1-NEXT: je .LBB4_32 -; AVX1-NEXT: .LBB4_31: # %cond.load43 +; AVX1-NEXT: je .LBB4_30 +; AVX1-NEXT: .LBB4_32: # %cond.load43 ; AVX1-NEXT: vpextrq $1, %xmm0, %rax ; AVX1-NEXT: vpinsrb $15, (%rax), %xmm3, %xmm3 ; AVX1-NEXT: vmovdqa %xmm3, %xmm0 @@ -1170,20 +1170,20 @@ define <16 x i8> @gather_v16i8_v16i32_v16i8(ptr %base, <16 x i32> %idx, <16 x i8 ; AVX2-NEXT: .LBB4_28: # %else38 ; AVX2-NEXT: testl $16384, %eax # imm = 0x4000 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0 -; AVX2-NEXT: jne .LBB4_29 -; AVX2-NEXT: # %bb.30: # %else41 -; AVX2-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX2-NEXT: jne .LBB4_31 -; AVX2-NEXT: .LBB4_32: # %else44 +; AVX2-NEXT: # %bb.29: # %else41 +; AVX2-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX2-NEXT: jne .LBB4_32 +; AVX2-NEXT: .LBB4_30: # %else44 ; AVX2-NEXT: vmovdqa %xmm3, %xmm0 ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; AVX2-NEXT: .LBB4_29: # %cond.load40 +; AVX2-NEXT: .LBB4_31: # %cond.load40 ; AVX2-NEXT: vmovq %xmm0, %rcx ; AVX2-NEXT: vpinsrb $14, (%rcx), %xmm3, %xmm3 ; AVX2-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX2-NEXT: je .LBB4_32 -; AVX2-NEXT: .LBB4_31: # %cond.load43 +; AVX2-NEXT: je .LBB4_30 +; AVX2-NEXT: .LBB4_32: # %cond.load43 ; AVX2-NEXT: vpextrq $1, %xmm0, %rax ; AVX2-NEXT: vpinsrb $15, (%rax), %xmm3, %xmm3 ; AVX2-NEXT: vmovdqa %xmm3, %xmm0 @@ -1199,129 +1199,129 @@ define <16 x i8> @gather_v16i8_v16i32_v16i8(ptr %base, <16 x i32> %idx, <16 x i8 ; AVX512-NEXT: vpcmpeqb %xmm5, %xmm1, %xmm1 ; AVX512-NEXT: vpmovmskb %xmm1, %eax ; AVX512-NEXT: testb $1, %al -; AVX512-NEXT: jne .LBB4_1 -; AVX512-NEXT: # %bb.2: # %else +; AVX512-NEXT: jne .LBB4_25 +; AVX512-NEXT: # %bb.1: # %else ; AVX512-NEXT: testb $2, %al -; AVX512-NEXT: jne .LBB4_3 -; AVX512-NEXT: .LBB4_4: # %else2 +; AVX512-NEXT: jne .LBB4_26 +; AVX512-NEXT: .LBB4_2: # %else2 ; AVX512-NEXT: testb $4, %al -; AVX512-NEXT: jne .LBB4_5 -; AVX512-NEXT: .LBB4_6: # %else5 +; AVX512-NEXT: jne .LBB4_27 +; AVX512-NEXT: .LBB4_3: # %else5 ; AVX512-NEXT: testb $8, %al -; AVX512-NEXT: je .LBB4_8 -; AVX512-NEXT: .LBB4_7: # %cond.load7 +; AVX512-NEXT: je .LBB4_5 +; AVX512-NEXT: .LBB4_4: # %cond.load7 ; AVX512-NEXT: vextracti128 $1, %ymm4, %xmm1 ; AVX512-NEXT: vpextrq $1, %xmm1, %rcx ; AVX512-NEXT: vpinsrb $3, (%rcx), %xmm2, %xmm2 -; AVX512-NEXT: .LBB4_8: # %else8 +; AVX512-NEXT: .LBB4_5: # %else8 ; AVX512-NEXT: testb $16, %al ; AVX512-NEXT: vextracti32x4 $2, %zmm4, %xmm1 -; AVX512-NEXT: je .LBB4_10 -; AVX512-NEXT: # %bb.9: # %cond.load10 +; AVX512-NEXT: je .LBB4_7 +; AVX512-NEXT: # %bb.6: # %cond.load10 ; AVX512-NEXT: vmovq %xmm1, %rcx ; AVX512-NEXT: vpinsrb $4, (%rcx), %xmm2, %xmm2 -; AVX512-NEXT: .LBB4_10: # %else11 +; AVX512-NEXT: .LBB4_7: # %else11 ; AVX512-NEXT: testb $32, %al -; AVX512-NEXT: je .LBB4_12 -; AVX512-NEXT: # %bb.11: # %cond.load13 +; AVX512-NEXT: je .LBB4_9 +; AVX512-NEXT: # %bb.8: # %cond.load13 ; AVX512-NEXT: vpextrq $1, %xmm1, %rcx ; AVX512-NEXT: vpinsrb $5, (%rcx), %xmm2, %xmm2 -; AVX512-NEXT: .LBB4_12: # %else14 +; AVX512-NEXT: .LBB4_9: # %else14 ; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm1 ; AVX512-NEXT: testb $64, %al ; AVX512-NEXT: vextracti32x4 $3, %zmm4, %xmm0 -; AVX512-NEXT: je .LBB4_14 -; AVX512-NEXT: # %bb.13: # %cond.load16 +; AVX512-NEXT: je .LBB4_11 +; AVX512-NEXT: # %bb.10: # %cond.load16 ; AVX512-NEXT: vmovq %xmm0, %rcx ; AVX512-NEXT: vpinsrb $6, (%rcx), %xmm2, %xmm2 -; AVX512-NEXT: .LBB4_14: # %else17 +; AVX512-NEXT: .LBB4_11: # %else17 ; AVX512-NEXT: vpmovsxdq %ymm1, %zmm1 ; AVX512-NEXT: testb %al, %al -; AVX512-NEXT: jns .LBB4_16 -; AVX512-NEXT: # %bb.15: # %cond.load19 +; AVX512-NEXT: jns .LBB4_13 +; AVX512-NEXT: # %bb.12: # %cond.load19 ; AVX512-NEXT: vpextrq $1, %xmm0, %rcx ; AVX512-NEXT: vpinsrb $7, (%rcx), %xmm2, %xmm2 -; AVX512-NEXT: .LBB4_16: # %else20 +; AVX512-NEXT: .LBB4_13: # %else20 ; AVX512-NEXT: vpaddq %zmm1, %zmm3, %zmm0 ; AVX512-NEXT: testl $256, %eax # imm = 0x100 -; AVX512-NEXT: jne .LBB4_17 -; AVX512-NEXT: # %bb.18: # %else23 +; AVX512-NEXT: jne .LBB4_28 +; AVX512-NEXT: # %bb.14: # %else23 ; AVX512-NEXT: testl $512, %eax # imm = 0x200 -; AVX512-NEXT: jne .LBB4_19 -; AVX512-NEXT: .LBB4_20: # %else26 +; AVX512-NEXT: jne .LBB4_29 +; AVX512-NEXT: .LBB4_15: # %else26 ; AVX512-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512-NEXT: jne .LBB4_21 -; AVX512-NEXT: .LBB4_22: # %else29 +; AVX512-NEXT: jne .LBB4_30 +; AVX512-NEXT: .LBB4_16: # %else29 ; AVX512-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512-NEXT: je .LBB4_24 -; AVX512-NEXT: .LBB4_23: # %cond.load31 +; AVX512-NEXT: je .LBB4_18 +; AVX512-NEXT: .LBB4_17: # %cond.load31 ; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1 ; AVX512-NEXT: vpextrq $1, %xmm1, %rcx ; AVX512-NEXT: vpinsrb $11, (%rcx), %xmm2, %xmm2 -; AVX512-NEXT: .LBB4_24: # %else32 +; AVX512-NEXT: .LBB4_18: # %else32 ; AVX512-NEXT: testl $4096, %eax # imm = 0x1000 ; AVX512-NEXT: vextracti32x4 $2, %zmm0, %xmm1 -; AVX512-NEXT: je .LBB4_26 -; AVX512-NEXT: # %bb.25: # %cond.load34 +; AVX512-NEXT: je .LBB4_20 +; AVX512-NEXT: # %bb.19: # %cond.load34 ; AVX512-NEXT: vmovq %xmm1, %rcx ; AVX512-NEXT: vpinsrb $12, (%rcx), %xmm2, %xmm2 -; AVX512-NEXT: .LBB4_26: # %else35 +; AVX512-NEXT: .LBB4_20: # %else35 ; AVX512-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512-NEXT: je .LBB4_28 -; AVX512-NEXT: # %bb.27: # %cond.load37 +; AVX512-NEXT: je .LBB4_22 +; AVX512-NEXT: # %bb.21: # %cond.load37 ; AVX512-NEXT: vpextrq $1, %xmm1, %rcx ; AVX512-NEXT: vpinsrb $13, (%rcx), %xmm2, %xmm2 -; AVX512-NEXT: .LBB4_28: # %else38 +; AVX512-NEXT: .LBB4_22: # %else38 ; AVX512-NEXT: testl $16384, %eax # imm = 0x4000 ; AVX512-NEXT: vextracti32x4 $3, %zmm0, %xmm0 -; AVX512-NEXT: jne .LBB4_29 -; AVX512-NEXT: # %bb.30: # %else41 -; AVX512-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX512-NEXT: jne .LBB4_31 -; AVX512-NEXT: .LBB4_32: # %else44 +; AVX512-NEXT: # %bb.23: # %else41 +; AVX512-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX512-NEXT: jne .LBB4_32 +; AVX512-NEXT: .LBB4_24: # %else44 ; AVX512-NEXT: vmovdqa %xmm2, %xmm0 ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq -; AVX512-NEXT: .LBB4_1: # %cond.load +; AVX512-NEXT: .LBB4_25: # %cond.load ; AVX512-NEXT: vmovq %xmm4, %rcx ; AVX512-NEXT: vpinsrb $0, (%rcx), %xmm2, %xmm2 ; AVX512-NEXT: testb $2, %al -; AVX512-NEXT: je .LBB4_4 -; AVX512-NEXT: .LBB4_3: # %cond.load1 +; AVX512-NEXT: je .LBB4_2 +; AVX512-NEXT: .LBB4_26: # %cond.load1 ; AVX512-NEXT: vpextrq $1, %xmm4, %rcx ; AVX512-NEXT: vpinsrb $1, (%rcx), %xmm2, %xmm2 ; AVX512-NEXT: testb $4, %al -; AVX512-NEXT: je .LBB4_6 -; AVX512-NEXT: .LBB4_5: # %cond.load4 +; AVX512-NEXT: je .LBB4_3 +; AVX512-NEXT: .LBB4_27: # %cond.load4 ; AVX512-NEXT: vextracti128 $1, %ymm4, %xmm1 ; AVX512-NEXT: vmovq %xmm1, %rcx ; AVX512-NEXT: vpinsrb $2, (%rcx), %xmm2, %xmm2 ; AVX512-NEXT: testb $8, %al -; AVX512-NEXT: jne .LBB4_7 -; AVX512-NEXT: jmp .LBB4_8 -; AVX512-NEXT: .LBB4_17: # %cond.load22 +; AVX512-NEXT: jne .LBB4_4 +; AVX512-NEXT: jmp .LBB4_5 +; AVX512-NEXT: .LBB4_28: # %cond.load22 ; AVX512-NEXT: vmovq %xmm0, %rcx ; AVX512-NEXT: vpinsrb $8, (%rcx), %xmm2, %xmm2 ; AVX512-NEXT: testl $512, %eax # imm = 0x200 -; AVX512-NEXT: je .LBB4_20 -; AVX512-NEXT: .LBB4_19: # %cond.load25 +; AVX512-NEXT: je .LBB4_15 +; AVX512-NEXT: .LBB4_29: # %cond.load25 ; AVX512-NEXT: vpextrq $1, %xmm0, %rcx ; AVX512-NEXT: vpinsrb $9, (%rcx), %xmm2, %xmm2 ; AVX512-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512-NEXT: je .LBB4_22 -; AVX512-NEXT: .LBB4_21: # %cond.load28 +; AVX512-NEXT: je .LBB4_16 +; AVX512-NEXT: .LBB4_30: # %cond.load28 ; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1 ; AVX512-NEXT: vmovq %xmm1, %rcx ; AVX512-NEXT: vpinsrb $10, (%rcx), %xmm2, %xmm2 ; AVX512-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512-NEXT: jne .LBB4_23 -; AVX512-NEXT: jmp .LBB4_24 -; AVX512-NEXT: .LBB4_29: # %cond.load40 +; AVX512-NEXT: jne .LBB4_17 +; AVX512-NEXT: jmp .LBB4_18 +; AVX512-NEXT: .LBB4_31: # %cond.load40 ; AVX512-NEXT: vmovq %xmm0, %rcx ; AVX512-NEXT: vpinsrb $14, (%rcx), %xmm2, %xmm2 ; AVX512-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX512-NEXT: je .LBB4_32 -; AVX512-NEXT: .LBB4_31: # %cond.load43 +; AVX512-NEXT: je .LBB4_24 +; AVX512-NEXT: .LBB4_32: # %cond.load43 ; AVX512-NEXT: vpextrq $1, %xmm0, %rax ; AVX512-NEXT: vpinsrb $15, (%rax), %xmm2, %xmm2 ; AVX512-NEXT: vmovdqa %xmm2, %xmm0 @@ -1348,55 +1348,55 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) { ; SSE-NEXT: packsswb %xmm0, %xmm0 ; SSE-NEXT: pmovmskb %xmm0, %eax ; SSE-NEXT: testb $1, %al -; SSE-NEXT: je .LBB5_1 -; SSE-NEXT: # %bb.2: # %cond.load +; SSE-NEXT: je .LBB5_2 +; SSE-NEXT: # %bb.1: # %cond.load ; SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE-NEXT: testb $2, %al -; SSE-NEXT: jne .LBB5_4 -; SSE-NEXT: jmp .LBB5_5 -; SSE-NEXT: .LBB5_1: +; SSE-NEXT: jne .LBB5_3 +; SSE-NEXT: jmp .LBB5_4 +; SSE-NEXT: .LBB5_2: ; SSE-NEXT: # implicit-def: $xmm0 ; SSE-NEXT: testb $2, %al -; SSE-NEXT: je .LBB5_5 -; SSE-NEXT: .LBB5_4: # %cond.load1 +; SSE-NEXT: je .LBB5_4 +; SSE-NEXT: .LBB5_3: # %cond.load1 ; SSE-NEXT: pinsrd $1, c+12(%rip), %xmm0 -; SSE-NEXT: .LBB5_5: # %else2 +; SSE-NEXT: .LBB5_4: # %else2 ; SSE-NEXT: testb $4, %al -; SSE-NEXT: jne .LBB5_6 -; SSE-NEXT: # %bb.7: # %else5 -; SSE-NEXT: testb $8, %al ; SSE-NEXT: jne .LBB5_8 -; SSE-NEXT: .LBB5_9: # %else8 +; SSE-NEXT: # %bb.5: # %else5 +; SSE-NEXT: testb $8, %al +; SSE-NEXT: jne .LBB5_9 +; SSE-NEXT: .LBB5_6: # %else8 ; SSE-NEXT: testb $16, %al ; SSE-NEXT: je .LBB5_10 -; SSE-NEXT: .LBB5_11: # %cond.load10 +; SSE-NEXT: .LBB5_7: # %cond.load10 ; SSE-NEXT: pinsrd $0, c+12(%rip), %xmm1 ; SSE-NEXT: testb $32, %al -; SSE-NEXT: jne .LBB5_13 -; SSE-NEXT: jmp .LBB5_14 -; SSE-NEXT: .LBB5_6: # %cond.load4 +; SSE-NEXT: jne .LBB5_11 +; SSE-NEXT: jmp .LBB5_12 +; SSE-NEXT: .LBB5_8: # %cond.load4 ; SSE-NEXT: pinsrd $2, c+12(%rip), %xmm0 ; SSE-NEXT: testb $8, %al -; SSE-NEXT: je .LBB5_9 -; SSE-NEXT: .LBB5_8: # %cond.load7 +; SSE-NEXT: je .LBB5_6 +; SSE-NEXT: .LBB5_9: # %cond.load7 ; SSE-NEXT: pinsrd $3, c+12(%rip), %xmm0 ; SSE-NEXT: testb $16, %al -; SSE-NEXT: jne .LBB5_11 +; SSE-NEXT: jne .LBB5_7 ; SSE-NEXT: .LBB5_10: ; SSE-NEXT: # implicit-def: $xmm1 ; SSE-NEXT: testb $32, %al -; SSE-NEXT: je .LBB5_14 -; SSE-NEXT: .LBB5_13: # %cond.load13 +; SSE-NEXT: je .LBB5_12 +; SSE-NEXT: .LBB5_11: # %cond.load13 ; SSE-NEXT: pinsrd $1, c+12(%rip), %xmm1 -; SSE-NEXT: .LBB5_14: # %else14 +; SSE-NEXT: .LBB5_12: # %else14 ; SSE-NEXT: testb $64, %al -; SSE-NEXT: jne .LBB5_15 -; SSE-NEXT: # %bb.16: # %else17 +; SSE-NEXT: jne .LBB5_17 +; SSE-NEXT: # %bb.13: # %else17 ; SSE-NEXT: testb $-128, %al -; SSE-NEXT: je .LBB5_18 -; SSE-NEXT: .LBB5_17: # %cond.load19 +; SSE-NEXT: je .LBB5_15 +; SSE-NEXT: .LBB5_14: # %cond.load19 ; SSE-NEXT: pinsrd $3, c+12(%rip), %xmm1 -; SSE-NEXT: .LBB5_18: # %else20 +; SSE-NEXT: .LBB5_15: # %else20 ; SSE-NEXT: pxor %xmm4, %xmm4 ; SSE-NEXT: movdqa %xmm2, %xmm5 ; SSE-NEXT: pcmpeqd %xmm4, %xmm5 @@ -1405,60 +1405,60 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) { ; SSE-NEXT: packsswb %xmm5, %xmm5 ; SSE-NEXT: pmovmskb %xmm5, %eax ; SSE-NEXT: testb $1, %al -; SSE-NEXT: je .LBB5_19 -; SSE-NEXT: # %bb.20: # %cond.load23 +; SSE-NEXT: je .LBB5_18 +; SSE-NEXT: # %bb.16: # %cond.load23 ; SSE-NEXT: movd {{.*#+}} xmm4 = mem[0],zero,zero,zero ; SSE-NEXT: testb $2, %al -; SSE-NEXT: jne .LBB5_22 -; SSE-NEXT: jmp .LBB5_23 -; SSE-NEXT: .LBB5_15: # %cond.load16 +; SSE-NEXT: jne .LBB5_19 +; SSE-NEXT: jmp .LBB5_20 +; SSE-NEXT: .LBB5_17: # %cond.load16 ; SSE-NEXT: pinsrd $2, c+12(%rip), %xmm1 ; SSE-NEXT: testb $-128, %al -; SSE-NEXT: jne .LBB5_17 -; SSE-NEXT: jmp .LBB5_18 -; SSE-NEXT: .LBB5_19: +; SSE-NEXT: jne .LBB5_14 +; SSE-NEXT: jmp .LBB5_15 +; SSE-NEXT: .LBB5_18: ; SSE-NEXT: # implicit-def: $xmm4 ; SSE-NEXT: testb $2, %al -; SSE-NEXT: je .LBB5_23 -; SSE-NEXT: .LBB5_22: # %cond.load28 +; SSE-NEXT: je .LBB5_20 +; SSE-NEXT: .LBB5_19: # %cond.load28 ; SSE-NEXT: pinsrd $1, c+28(%rip), %xmm4 -; SSE-NEXT: .LBB5_23: # %else31 +; SSE-NEXT: .LBB5_20: # %else31 ; SSE-NEXT: testb $4, %al ; SSE-NEXT: jne .LBB5_24 -; SSE-NEXT: # %bb.25: # %else36 +; SSE-NEXT: # %bb.21: # %else36 ; SSE-NEXT: testb $8, %al -; SSE-NEXT: jne .LBB5_26 -; SSE-NEXT: .LBB5_27: # %else41 +; SSE-NEXT: jne .LBB5_25 +; SSE-NEXT: .LBB5_22: # %else41 ; SSE-NEXT: testb $16, %al -; SSE-NEXT: je .LBB5_28 -; SSE-NEXT: .LBB5_29: # %cond.load43 +; SSE-NEXT: je .LBB5_26 +; SSE-NEXT: .LBB5_23: # %cond.load43 ; SSE-NEXT: pinsrd $0, c+28(%rip), %xmm5 ; SSE-NEXT: testb $32, %al -; SSE-NEXT: jne .LBB5_31 -; SSE-NEXT: jmp .LBB5_32 +; SSE-NEXT: jne .LBB5_27 +; SSE-NEXT: jmp .LBB5_28 ; SSE-NEXT: .LBB5_24: # %cond.load33 ; SSE-NEXT: pinsrd $2, c+28(%rip), %xmm4 ; SSE-NEXT: testb $8, %al -; SSE-NEXT: je .LBB5_27 -; SSE-NEXT: .LBB5_26: # %cond.load38 +; SSE-NEXT: je .LBB5_22 +; SSE-NEXT: .LBB5_25: # %cond.load38 ; SSE-NEXT: pinsrd $3, c+28(%rip), %xmm4 ; SSE-NEXT: testb $16, %al -; SSE-NEXT: jne .LBB5_29 -; SSE-NEXT: .LBB5_28: +; SSE-NEXT: jne .LBB5_23 +; SSE-NEXT: .LBB5_26: ; SSE-NEXT: # implicit-def: $xmm5 ; SSE-NEXT: testb $32, %al -; SSE-NEXT: je .LBB5_32 -; SSE-NEXT: .LBB5_31: # %cond.load48 +; SSE-NEXT: je .LBB5_28 +; SSE-NEXT: .LBB5_27: # %cond.load48 ; SSE-NEXT: pinsrd $1, c+28(%rip), %xmm5 -; SSE-NEXT: .LBB5_32: # %else51 +; SSE-NEXT: .LBB5_28: # %else51 ; SSE-NEXT: testb $64, %al ; SSE-NEXT: jne .LBB5_33 -; SSE-NEXT: # %bb.34: # %else56 +; SSE-NEXT: # %bb.29: # %else56 ; SSE-NEXT: testb $-128, %al -; SSE-NEXT: je .LBB5_36 -; SSE-NEXT: .LBB5_35: # %cond.load58 +; SSE-NEXT: je .LBB5_31 +; SSE-NEXT: .LBB5_30: # %cond.load58 ; SSE-NEXT: pinsrd $3, c+28(%rip), %xmm5 -; SSE-NEXT: .LBB5_36: # %else61 +; SSE-NEXT: .LBB5_31: # %else61 ; SSE-NEXT: pxor %xmm6, %xmm6 ; SSE-NEXT: pcmpeqd %xmm6, %xmm2 ; SSE-NEXT: pcmpeqd %xmm6, %xmm3 @@ -1466,64 +1466,64 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) { ; SSE-NEXT: packsswb %xmm2, %xmm2 ; SSE-NEXT: pmovmskb %xmm2, %eax ; SSE-NEXT: testb $1, %al -; SSE-NEXT: je .LBB5_37 -; SSE-NEXT: # %bb.38: # %cond.load64 +; SSE-NEXT: je .LBB5_34 +; SSE-NEXT: # %bb.32: # %cond.load64 ; SSE-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE-NEXT: testb $2, %al -; SSE-NEXT: jne .LBB5_40 -; SSE-NEXT: jmp .LBB5_41 +; SSE-NEXT: jne .LBB5_35 +; SSE-NEXT: jmp .LBB5_36 ; SSE-NEXT: .LBB5_33: # %cond.load53 ; SSE-NEXT: pinsrd $2, c+28(%rip), %xmm5 ; SSE-NEXT: testb $-128, %al -; SSE-NEXT: jne .LBB5_35 -; SSE-NEXT: jmp .LBB5_36 -; SSE-NEXT: .LBB5_37: +; SSE-NEXT: jne .LBB5_30 +; SSE-NEXT: jmp .LBB5_31 +; SSE-NEXT: .LBB5_34: ; SSE-NEXT: # implicit-def: $xmm2 ; SSE-NEXT: testb $2, %al -; SSE-NEXT: je .LBB5_41 -; SSE-NEXT: .LBB5_40: # %cond.load69 +; SSE-NEXT: je .LBB5_36 +; SSE-NEXT: .LBB5_35: # %cond.load69 ; SSE-NEXT: pinsrd $1, c+28(%rip), %xmm2 -; SSE-NEXT: .LBB5_41: # %else72 +; SSE-NEXT: .LBB5_36: # %else72 ; SSE-NEXT: testb $4, %al -; SSE-NEXT: jne .LBB5_42 -; SSE-NEXT: # %bb.43: # %else77 +; SSE-NEXT: jne .LBB5_40 +; SSE-NEXT: # %bb.37: # %else77 ; SSE-NEXT: testb $8, %al -; SSE-NEXT: jne .LBB5_44 -; SSE-NEXT: .LBB5_45: # %else82 +; SSE-NEXT: jne .LBB5_41 +; SSE-NEXT: .LBB5_38: # %else82 ; SSE-NEXT: testb $16, %al -; SSE-NEXT: je .LBB5_46 -; SSE-NEXT: .LBB5_47: # %cond.load84 +; SSE-NEXT: je .LBB5_42 +; SSE-NEXT: .LBB5_39: # %cond.load84 ; SSE-NEXT: pinsrd $0, c+28(%rip), %xmm3 ; SSE-NEXT: testb $32, %al -; SSE-NEXT: jne .LBB5_49 -; SSE-NEXT: jmp .LBB5_50 -; SSE-NEXT: .LBB5_42: # %cond.load74 +; SSE-NEXT: jne .LBB5_43 +; SSE-NEXT: jmp .LBB5_44 +; SSE-NEXT: .LBB5_40: # %cond.load74 ; SSE-NEXT: pinsrd $2, c+28(%rip), %xmm2 ; SSE-NEXT: testb $8, %al -; SSE-NEXT: je .LBB5_45 -; SSE-NEXT: .LBB5_44: # %cond.load79 +; SSE-NEXT: je .LBB5_38 +; SSE-NEXT: .LBB5_41: # %cond.load79 ; SSE-NEXT: pinsrd $3, c+28(%rip), %xmm2 ; SSE-NEXT: testb $16, %al -; SSE-NEXT: jne .LBB5_47 -; SSE-NEXT: .LBB5_46: +; SSE-NEXT: jne .LBB5_39 +; SSE-NEXT: .LBB5_42: ; SSE-NEXT: # implicit-def: $xmm3 ; SSE-NEXT: testb $32, %al -; SSE-NEXT: je .LBB5_50 -; SSE-NEXT: .LBB5_49: # %cond.load89 +; SSE-NEXT: je .LBB5_44 +; SSE-NEXT: .LBB5_43: # %cond.load89 ; SSE-NEXT: pinsrd $1, c+28(%rip), %xmm3 -; SSE-NEXT: .LBB5_50: # %else92 +; SSE-NEXT: .LBB5_44: # %else92 ; SSE-NEXT: testb $64, %al -; SSE-NEXT: je .LBB5_52 -; SSE-NEXT: # %bb.51: # %cond.load94 +; SSE-NEXT: je .LBB5_46 +; SSE-NEXT: # %bb.45: # %cond.load94 ; SSE-NEXT: pinsrd $2, c+28(%rip), %xmm3 -; SSE-NEXT: .LBB5_52: # %else97 +; SSE-NEXT: .LBB5_46: # %else97 ; SSE-NEXT: paddd %xmm4, %xmm0 ; SSE-NEXT: paddd %xmm5, %xmm1 ; SSE-NEXT: testb $-128, %al -; SSE-NEXT: je .LBB5_54 -; SSE-NEXT: # %bb.53: # %cond.load99 +; SSE-NEXT: je .LBB5_48 +; SSE-NEXT: # %bb.47: # %cond.load99 ; SSE-NEXT: pinsrd $3, c+28(%rip), %xmm3 -; SSE-NEXT: .LBB5_54: # %else102 +; SSE-NEXT: .LBB5_48: # %else102 ; SSE-NEXT: paddd %xmm3, %xmm1 ; SSE-NEXT: paddd %xmm2, %xmm0 ; SSE-NEXT: retq @@ -1538,32 +1538,32 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) { ; AVX1-NEXT: vmovmskps %ymm1, %eax ; AVX1-NEXT: testb $1, %al ; AVX1-NEXT: # implicit-def: $ymm1 -; AVX1-NEXT: jne .LBB5_1 -; AVX1-NEXT: # %bb.2: # %else +; AVX1-NEXT: jne .LBB5_31 +; AVX1-NEXT: # %bb.1: # %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne .LBB5_3 -; AVX1-NEXT: .LBB5_4: # %else2 +; AVX1-NEXT: jne .LBB5_32 +; AVX1-NEXT: .LBB5_2: # %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne .LBB5_5 -; AVX1-NEXT: .LBB5_6: # %else5 +; AVX1-NEXT: jne .LBB5_33 +; AVX1-NEXT: .LBB5_3: # %else5 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne .LBB5_7 -; AVX1-NEXT: .LBB5_8: # %else8 +; AVX1-NEXT: jne .LBB5_34 +; AVX1-NEXT: .LBB5_4: # %else8 ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: jne .LBB5_9 -; AVX1-NEXT: .LBB5_10: # %else11 +; AVX1-NEXT: jne .LBB5_35 +; AVX1-NEXT: .LBB5_5: # %else11 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: jne .LBB5_11 -; AVX1-NEXT: .LBB5_12: # %else14 +; AVX1-NEXT: jne .LBB5_36 +; AVX1-NEXT: .LBB5_6: # %else14 ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: jne .LBB5_13 -; AVX1-NEXT: .LBB5_14: # %else17 +; AVX1-NEXT: jne .LBB5_37 +; AVX1-NEXT: .LBB5_7: # %else17 ; AVX1-NEXT: testb $-128, %al -; AVX1-NEXT: je .LBB5_16 -; AVX1-NEXT: .LBB5_15: # %cond.load19 +; AVX1-NEXT: je .LBB5_9 +; AVX1-NEXT: .LBB5_8: # %cond.load19 ; AVX1-NEXT: vbroadcastss c+12(%rip), %ymm3 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1,2,3,4,5,6],ymm3[7] -; AVX1-NEXT: .LBB5_16: # %else20 +; AVX1-NEXT: .LBB5_9: # %else20 ; AVX1-NEXT: vxorps %xmm3, %xmm3, %xmm3 ; AVX1-NEXT: vpcmpeqd %xmm3, %xmm2, %xmm4 ; AVX1-NEXT: vpcmpeqd %xmm3, %xmm0, %xmm3 @@ -1571,32 +1571,32 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) { ; AVX1-NEXT: vmovmskps %ymm3, %eax ; AVX1-NEXT: testb $1, %al ; AVX1-NEXT: # implicit-def: $ymm3 -; AVX1-NEXT: jne .LBB5_17 -; AVX1-NEXT: # %bb.18: # %else26 +; AVX1-NEXT: jne .LBB5_38 +; AVX1-NEXT: # %bb.10: # %else26 ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne .LBB5_19 -; AVX1-NEXT: .LBB5_20: # %else31 +; AVX1-NEXT: jne .LBB5_39 +; AVX1-NEXT: .LBB5_11: # %else31 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne .LBB5_21 -; AVX1-NEXT: .LBB5_22: # %else36 +; AVX1-NEXT: jne .LBB5_40 +; AVX1-NEXT: .LBB5_12: # %else36 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne .LBB5_23 -; AVX1-NEXT: .LBB5_24: # %else41 +; AVX1-NEXT: jne .LBB5_41 +; AVX1-NEXT: .LBB5_13: # %else41 ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: jne .LBB5_25 -; AVX1-NEXT: .LBB5_26: # %else46 +; AVX1-NEXT: jne .LBB5_42 +; AVX1-NEXT: .LBB5_14: # %else46 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: jne .LBB5_27 -; AVX1-NEXT: .LBB5_28: # %else51 +; AVX1-NEXT: jne .LBB5_43 +; AVX1-NEXT: .LBB5_15: # %else51 ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: jne .LBB5_29 -; AVX1-NEXT: .LBB5_30: # %else56 +; AVX1-NEXT: jne .LBB5_44 +; AVX1-NEXT: .LBB5_16: # %else56 ; AVX1-NEXT: testb $-128, %al -; AVX1-NEXT: je .LBB5_32 -; AVX1-NEXT: .LBB5_31: # %cond.load58 +; AVX1-NEXT: je .LBB5_18 +; AVX1-NEXT: .LBB5_17: # %cond.load58 ; AVX1-NEXT: vbroadcastss c+28(%rip), %ymm4 ; AVX1-NEXT: vblendps {{.*#+}} ymm3 = ymm3[0,1,2,3,4,5,6],ymm4[7] -; AVX1-NEXT: .LBB5_32: # %else61 +; AVX1-NEXT: .LBB5_18: # %else61 ; AVX1-NEXT: vxorps %xmm4, %xmm4, %xmm4 ; AVX1-NEXT: vpcmpeqd %xmm4, %xmm2, %xmm2 ; AVX1-NEXT: vpcmpeqd %xmm4, %xmm0, %xmm0 @@ -1604,142 +1604,142 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) { ; AVX1-NEXT: vmovmskps %ymm0, %eax ; AVX1-NEXT: testb $1, %al ; AVX1-NEXT: # implicit-def: $ymm0 -; AVX1-NEXT: jne .LBB5_33 -; AVX1-NEXT: # %bb.34: # %else67 +; AVX1-NEXT: jne .LBB5_45 +; AVX1-NEXT: # %bb.19: # %else67 ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne .LBB5_35 -; AVX1-NEXT: .LBB5_36: # %else72 +; AVX1-NEXT: jne .LBB5_46 +; AVX1-NEXT: .LBB5_20: # %else72 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne .LBB5_37 -; AVX1-NEXT: .LBB5_38: # %else77 +; AVX1-NEXT: jne .LBB5_47 +; AVX1-NEXT: .LBB5_21: # %else77 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne .LBB5_39 -; AVX1-NEXT: .LBB5_40: # %else82 +; AVX1-NEXT: jne .LBB5_48 +; AVX1-NEXT: .LBB5_22: # %else82 ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: je .LBB5_42 -; AVX1-NEXT: .LBB5_41: # %cond.load84 +; AVX1-NEXT: je .LBB5_24 +; AVX1-NEXT: .LBB5_23: # %cond.load84 ; AVX1-NEXT: vbroadcastss c+28(%rip), %ymm2 ; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm2[4],ymm0[5,6,7] -; AVX1-NEXT: .LBB5_42: # %else87 +; AVX1-NEXT: .LBB5_24: # %else87 ; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm4 ; AVX1-NEXT: vpaddd %xmm3, %xmm1, %xmm1 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je .LBB5_44 -; AVX1-NEXT: # %bb.43: # %cond.load89 +; AVX1-NEXT: je .LBB5_26 +; AVX1-NEXT: # %bb.25: # %cond.load89 ; AVX1-NEXT: vbroadcastss c+28(%rip), %ymm3 ; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3,4],ymm3[5],ymm0[6,7] -; AVX1-NEXT: .LBB5_44: # %else92 +; AVX1-NEXT: .LBB5_26: # %else92 ; AVX1-NEXT: vpaddd %xmm2, %xmm4, %xmm2 ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: je .LBB5_46 -; AVX1-NEXT: # %bb.45: # %cond.load94 +; AVX1-NEXT: je .LBB5_28 +; AVX1-NEXT: # %bb.27: # %cond.load94 ; AVX1-NEXT: vbroadcastss c+28(%rip), %ymm3 ; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5],ymm3[6],ymm0[7] -; AVX1-NEXT: .LBB5_46: # %else97 +; AVX1-NEXT: .LBB5_28: # %else97 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1 ; AVX1-NEXT: testb $-128, %al -; AVX1-NEXT: je .LBB5_48 -; AVX1-NEXT: # %bb.47: # %cond.load99 +; AVX1-NEXT: je .LBB5_30 +; AVX1-NEXT: # %bb.29: # %cond.load99 ; AVX1-NEXT: vbroadcastss c+28(%rip), %ymm2 ; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5,6],ymm2[7] -; AVX1-NEXT: .LBB5_48: # %else102 +; AVX1-NEXT: .LBB5_30: # %else102 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3 ; AVX1-NEXT: vpaddd %xmm2, %xmm3, %xmm2 ; AVX1-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB5_1: # %cond.load +; AVX1-NEXT: .LBB5_31: # %cond.load ; AVX1-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je .LBB5_4 -; AVX1-NEXT: .LBB5_3: # %cond.load1 +; AVX1-NEXT: je .LBB5_2 +; AVX1-NEXT: .LBB5_32: # %cond.load1 ; AVX1-NEXT: vpinsrd $1, c+12(%rip), %xmm1, %xmm3 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm3[0,1,2,3],ymm1[4,5,6,7] ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je .LBB5_6 -; AVX1-NEXT: .LBB5_5: # %cond.load4 +; AVX1-NEXT: je .LBB5_3 +; AVX1-NEXT: .LBB5_33: # %cond.load4 ; AVX1-NEXT: vpinsrd $2, c+12(%rip), %xmm1, %xmm3 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm3[0,1,2,3],ymm1[4,5,6,7] ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB5_8 -; AVX1-NEXT: .LBB5_7: # %cond.load7 +; AVX1-NEXT: je .LBB5_4 +; AVX1-NEXT: .LBB5_34: # %cond.load7 ; AVX1-NEXT: vpinsrd $3, c+12(%rip), %xmm1, %xmm3 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm3[0,1,2,3],ymm1[4,5,6,7] ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: je .LBB5_10 -; AVX1-NEXT: .LBB5_9: # %cond.load10 +; AVX1-NEXT: je .LBB5_5 +; AVX1-NEXT: .LBB5_35: # %cond.load10 ; AVX1-NEXT: vbroadcastss c+12(%rip), %ymm3 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm3[4],ymm1[5,6,7] ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je .LBB5_12 -; AVX1-NEXT: .LBB5_11: # %cond.load13 +; AVX1-NEXT: je .LBB5_6 +; AVX1-NEXT: .LBB5_36: # %cond.load13 ; AVX1-NEXT: vbroadcastss c+12(%rip), %ymm3 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1,2,3,4],ymm3[5],ymm1[6,7] ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: je .LBB5_14 -; AVX1-NEXT: .LBB5_13: # %cond.load16 +; AVX1-NEXT: je .LBB5_7 +; AVX1-NEXT: .LBB5_37: # %cond.load16 ; AVX1-NEXT: vbroadcastss c+12(%rip), %ymm3 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1,2,3,4,5],ymm3[6],ymm1[7] ; AVX1-NEXT: testb $-128, %al -; AVX1-NEXT: jne .LBB5_15 -; AVX1-NEXT: jmp .LBB5_16 -; AVX1-NEXT: .LBB5_17: # %cond.load23 +; AVX1-NEXT: jne .LBB5_8 +; AVX1-NEXT: jmp .LBB5_9 +; AVX1-NEXT: .LBB5_38: # %cond.load23 ; AVX1-NEXT: vmovd {{.*#+}} xmm3 = mem[0],zero,zero,zero ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je .LBB5_20 -; AVX1-NEXT: .LBB5_19: # %cond.load28 +; AVX1-NEXT: je .LBB5_11 +; AVX1-NEXT: .LBB5_39: # %cond.load28 ; AVX1-NEXT: vpinsrd $1, c+28(%rip), %xmm3, %xmm4 ; AVX1-NEXT: vblendps {{.*#+}} ymm3 = ymm4[0,1,2,3],ymm3[4,5,6,7] ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je .LBB5_22 -; AVX1-NEXT: .LBB5_21: # %cond.load33 +; AVX1-NEXT: je .LBB5_12 +; AVX1-NEXT: .LBB5_40: # %cond.load33 ; AVX1-NEXT: vpinsrd $2, c+28(%rip), %xmm3, %xmm4 ; AVX1-NEXT: vblendps {{.*#+}} ymm3 = ymm4[0,1,2,3],ymm3[4,5,6,7] ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB5_24 -; AVX1-NEXT: .LBB5_23: # %cond.load38 +; AVX1-NEXT: je .LBB5_13 +; AVX1-NEXT: .LBB5_41: # %cond.load38 ; AVX1-NEXT: vpinsrd $3, c+28(%rip), %xmm3, %xmm4 ; AVX1-NEXT: vblendps {{.*#+}} ymm3 = ymm4[0,1,2,3],ymm3[4,5,6,7] ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: je .LBB5_26 -; AVX1-NEXT: .LBB5_25: # %cond.load43 +; AVX1-NEXT: je .LBB5_14 +; AVX1-NEXT: .LBB5_42: # %cond.load43 ; AVX1-NEXT: vbroadcastss c+28(%rip), %ymm4 ; AVX1-NEXT: vblendps {{.*#+}} ymm3 = ymm3[0,1,2,3],ymm4[4],ymm3[5,6,7] ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je .LBB5_28 -; AVX1-NEXT: .LBB5_27: # %cond.load48 +; AVX1-NEXT: je .LBB5_15 +; AVX1-NEXT: .LBB5_43: # %cond.load48 ; AVX1-NEXT: vbroadcastss c+28(%rip), %ymm4 ; AVX1-NEXT: vblendps {{.*#+}} ymm3 = ymm3[0,1,2,3,4],ymm4[5],ymm3[6,7] ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: je .LBB5_30 -; AVX1-NEXT: .LBB5_29: # %cond.load53 +; AVX1-NEXT: je .LBB5_16 +; AVX1-NEXT: .LBB5_44: # %cond.load53 ; AVX1-NEXT: vbroadcastss c+28(%rip), %ymm4 ; AVX1-NEXT: vblendps {{.*#+}} ymm3 = ymm3[0,1,2,3,4,5],ymm4[6],ymm3[7] ; AVX1-NEXT: testb $-128, %al -; AVX1-NEXT: jne .LBB5_31 -; AVX1-NEXT: jmp .LBB5_32 -; AVX1-NEXT: .LBB5_33: # %cond.load64 +; AVX1-NEXT: jne .LBB5_17 +; AVX1-NEXT: jmp .LBB5_18 +; AVX1-NEXT: .LBB5_45: # %cond.load64 ; AVX1-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je .LBB5_36 -; AVX1-NEXT: .LBB5_35: # %cond.load69 +; AVX1-NEXT: je .LBB5_20 +; AVX1-NEXT: .LBB5_46: # %cond.load69 ; AVX1-NEXT: vpinsrd $1, c+28(%rip), %xmm0, %xmm2 ; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm2[0,1,2,3],ymm0[4,5,6,7] ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je .LBB5_38 -; AVX1-NEXT: .LBB5_37: # %cond.load74 +; AVX1-NEXT: je .LBB5_21 +; AVX1-NEXT: .LBB5_47: # %cond.load74 ; AVX1-NEXT: vpinsrd $2, c+28(%rip), %xmm0, %xmm2 ; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm2[0,1,2,3],ymm0[4,5,6,7] ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB5_40 -; AVX1-NEXT: .LBB5_39: # %cond.load79 +; AVX1-NEXT: je .LBB5_22 +; AVX1-NEXT: .LBB5_48: # %cond.load79 ; AVX1-NEXT: vpinsrd $3, c+28(%rip), %xmm0, %xmm2 ; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm2[0,1,2,3],ymm0[4,5,6,7] ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: jne .LBB5_41 -; AVX1-NEXT: jmp .LBB5_42 +; AVX1-NEXT: jne .LBB5_23 +; AVX1-NEXT: jmp .LBB5_24 ; ; AVX2-NOGATHER-LABEL: gather_v8i32_v8i32: ; AVX2-NOGATHER: # %bb.0: @@ -1748,200 +1748,200 @@ define <8 x i32> @gather_v8i32_v8i32(<8 x i32> %trigger) { ; AVX2-NOGATHER-NEXT: vmovmskps %ymm1, %eax ; AVX2-NOGATHER-NEXT: testb $1, %al ; AVX2-NOGATHER-NEXT: # implicit-def: $ymm1 -; AVX2-NOGATHER-NEXT: jne .LBB5_1 -; AVX2-NOGATHER-NEXT: # %bb.2: # %else +; AVX2-NOGATHER-NEXT: jne .LBB5_29 +; AVX2-NOGATHER-NEXT: # %bb.1: # %else ; AVX2-NOGATHER-NEXT: testb $2, %al -; AVX2-NOGATHER-NEXT: jne .LBB5_3 -; AVX2-NOGATHER-NEXT: .LBB5_4: # %else2 +; AVX2-NOGATHER-NEXT: jne .LBB5_30 +; AVX2-NOGATHER-NEXT: .LBB5_2: # %else2 ; AVX2-NOGATHER-NEXT: testb $4, %al -; AVX2-NOGATHER-NEXT: jne .LBB5_5 -; AVX2-NOGATHER-NEXT: .LBB5_6: # %else5 +; AVX2-NOGATHER-NEXT: jne .LBB5_31 +; AVX2-NOGATHER-NEXT: .LBB5_3: # %else5 ; AVX2-NOGATHER-NEXT: testb $8, %al -; AVX2-NOGATHER-NEXT: jne .LBB5_7 -; AVX2-NOGATHER-NEXT: .LBB5_8: # %else8 +; AVX2-NOGATHER-NEXT: jne .LBB5_32 +; AVX2-NOGATHER-NEXT: .LBB5_4: # %else8 ; AVX2-NOGATHER-NEXT: testb $16, %al -; AVX2-NOGATHER-NEXT: jne .LBB5_9 -; AVX2-NOGATHER-NEXT: .LBB5_10: # %else11 +; AVX2-NOGATHER-NEXT: jne .LBB5_33 +; AVX2-NOGATHER-NEXT: .LBB5_5: # %else11 ; AVX2-NOGATHER-NEXT: testb $32, %al -; AVX2-NOGATHER-NEXT: jne .LBB5_11 -; AVX2-NOGATHER-NEXT: .LBB5_12: # %else14 +; AVX2-NOGATHER-NEXT: jne .LBB5_34 +; AVX2-NOGATHER-NEXT: .LBB5_6: # %else14 ; AVX2-NOGATHER-NEXT: testb $64, %al -; AVX2-NOGATHER-NEXT: jne .LBB5_13 -; AVX2-NOGATHER-NEXT: .LBB5_14: # %else17 +; AVX2-NOGATHER-NEXT: jne .LBB5_35 +; AVX2-NOGATHER-NEXT: .LBB5_7: # %else17 ; AVX2-NOGATHER-NEXT: testb $-128, %al -; AVX2-NOGATHER-NEXT: je .LBB5_16 -; AVX2-NOGATHER-NEXT: .LBB5_15: # %cond.load19 +; AVX2-NOGATHER-NEXT: je .LBB5_9 +; AVX2-NOGATHER-NEXT: .LBB5_8: # %cond.load19 ; AVX2-NOGATHER-NEXT: vpbroadcastd c+12(%rip), %ymm2 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3,4,5,6],ymm2[7] -; AVX2-NOGATHER-NEXT: .LBB5_16: # %else20 +; AVX2-NOGATHER-NEXT: .LBB5_9: # %else20 ; AVX2-NOGATHER-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX2-NOGATHER-NEXT: vpcmpeqd %ymm2, %ymm0, %ymm2 ; AVX2-NOGATHER-NEXT: vmovmskps %ymm2, %eax ; AVX2-NOGATHER-NEXT: testb $1, %al ; AVX2-NOGATHER-NEXT: # implicit-def: $ymm2 -; AVX2-NOGATHER-NEXT: jne .LBB5_17 -; AVX2-NOGATHER-NEXT: # %bb.18: # %else26 +; AVX2-NOGATHER-NEXT: jne .LBB5_36 +; AVX2-NOGATHER-NEXT: # %bb.10: # %else26 ; AVX2-NOGATHER-NEXT: testb $2, %al -; AVX2-NOGATHER-NEXT: jne .LBB5_19 -; AVX2-NOGATHER-NEXT: .LBB5_20: # %else31 +; AVX2-NOGATHER-NEXT: jne .LBB5_37 +; AVX2-NOGATHER-NEXT: .LBB5_11: # %else31 ; AVX2-NOGATHER-NEXT: testb $4, %al -; AVX2-NOGATHER-NEXT: jne .LBB5_21 -; AVX2-NOGATHER-NEXT: .LBB5_22: # %else36 +; AVX2-NOGATHER-NEXT: jne .LBB5_38 +; AVX2-NOGATHER-NEXT: .LBB5_12: # %else36 ; AVX2-NOGATHER-NEXT: testb $8, %al -; AVX2-NOGATHER-NEXT: jne .LBB5_23 -; AVX2-NOGATHER-NEXT: .LBB5_24: # %else41 +; AVX2-NOGATHER-NEXT: jne .LBB5_39 +; AVX2-NOGATHER-NEXT: .LBB5_13: # %else41 ; AVX2-NOGATHER-NEXT: testb $16, %al -; AVX2-NOGATHER-NEXT: jne .LBB5_25 -; AVX2-NOGATHER-NEXT: .LBB5_26: # %else46 +; AVX2-NOGATHER-NEXT: jne .LBB5_40 +; AVX2-NOGATHER-NEXT: .LBB5_14: # %else46 ; AVX2-NOGATHER-NEXT: testb $32, %al -; AVX2-NOGATHER-NEXT: jne .LBB5_27 -; AVX2-NOGATHER-NEXT: .LBB5_28: # %else51 +; AVX2-NOGATHER-NEXT: jne .LBB5_41 +; AVX2-NOGATHER-NEXT: .LBB5_15: # %else51 ; AVX2-NOGATHER-NEXT: testb $64, %al -; AVX2-NOGATHER-NEXT: jne .LBB5_29 -; AVX2-NOGATHER-NEXT: .LBB5_30: # %else56 +; AVX2-NOGATHER-NEXT: jne .LBB5_42 +; AVX2-NOGATHER-NEXT: .LBB5_16: # %else56 ; AVX2-NOGATHER-NEXT: testb $-128, %al -; AVX2-NOGATHER-NEXT: je .LBB5_32 -; AVX2-NOGATHER-NEXT: .LBB5_31: # %cond.load58 +; AVX2-NOGATHER-NEXT: je .LBB5_18 +; AVX2-NOGATHER-NEXT: .LBB5_17: # %cond.load58 ; AVX2-NOGATHER-NEXT: vpbroadcastd c+28(%rip), %ymm3 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3,4,5,6],ymm3[7] -; AVX2-NOGATHER-NEXT: .LBB5_32: # %else61 +; AVX2-NOGATHER-NEXT: .LBB5_18: # %else61 ; AVX2-NOGATHER-NEXT: vpxor %xmm3, %xmm3, %xmm3 ; AVX2-NOGATHER-NEXT: vpcmpeqd %ymm3, %ymm0, %ymm0 ; AVX2-NOGATHER-NEXT: vmovmskps %ymm0, %eax ; AVX2-NOGATHER-NEXT: testb $1, %al ; AVX2-NOGATHER-NEXT: # implicit-def: $ymm0 -; AVX2-NOGATHER-NEXT: jne .LBB5_33 -; AVX2-NOGATHER-NEXT: # %bb.34: # %else67 +; AVX2-NOGATHER-NEXT: jne .LBB5_43 +; AVX2-NOGATHER-NEXT: # %bb.19: # %else67 ; AVX2-NOGATHER-NEXT: testb $2, %al -; AVX2-NOGATHER-NEXT: jne .LBB5_35 -; AVX2-NOGATHER-NEXT: .LBB5_36: # %else72 +; AVX2-NOGATHER-NEXT: jne .LBB5_44 +; AVX2-NOGATHER-NEXT: .LBB5_20: # %else72 ; AVX2-NOGATHER-NEXT: testb $4, %al -; AVX2-NOGATHER-NEXT: jne .LBB5_37 -; AVX2-NOGATHER-NEXT: .LBB5_38: # %else77 +; AVX2-NOGATHER-NEXT: jne .LBB5_45 +; AVX2-NOGATHER-NEXT: .LBB5_21: # %else77 ; AVX2-NOGATHER-NEXT: testb $8, %al -; AVX2-NOGATHER-NEXT: jne .LBB5_39 -; AVX2-NOGATHER-NEXT: .LBB5_40: # %else82 +; AVX2-NOGATHER-NEXT: jne .LBB5_46 +; AVX2-NOGATHER-NEXT: .LBB5_22: # %else82 ; AVX2-NOGATHER-NEXT: testb $16, %al -; AVX2-NOGATHER-NEXT: jne .LBB5_41 -; AVX2-NOGATHER-NEXT: .LBB5_42: # %else87 +; AVX2-NOGATHER-NEXT: jne .LBB5_47 +; AVX2-NOGATHER-NEXT: .LBB5_23: # %else87 ; AVX2-NOGATHER-NEXT: testb $32, %al -; AVX2-NOGATHER-NEXT: jne .LBB5_43 -; AVX2-NOGATHER-NEXT: .LBB5_44: # %else92 +; AVX2-NOGATHER-NEXT: jne .LBB5_48 +; AVX2-NOGATHER-NEXT: .LBB5_24: # %else92 ; AVX2-NOGATHER-NEXT: testb $64, %al -; AVX2-NOGATHER-NEXT: je .LBB5_46 -; AVX2-NOGATHER-NEXT: .LBB5_45: # %cond.load94 +; AVX2-NOGATHER-NEXT: je .LBB5_26 +; AVX2-NOGATHER-NEXT: .LBB5_25: # %cond.load94 ; AVX2-NOGATHER-NEXT: vpbroadcastd c+28(%rip), %ymm3 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5],ymm3[6],ymm0[7] -; AVX2-NOGATHER-NEXT: .LBB5_46: # %else97 +; AVX2-NOGATHER-NEXT: .LBB5_26: # %else97 ; AVX2-NOGATHER-NEXT: vpaddd %ymm2, %ymm1, %ymm1 ; AVX2-NOGATHER-NEXT: testb $-128, %al -; AVX2-NOGATHER-NEXT: je .LBB5_48 -; AVX2-NOGATHER-NEXT: # %bb.47: # %cond.load99 +; AVX2-NOGATHER-NEXT: je .LBB5_28 +; AVX2-NOGATHER-NEXT: # %bb.27: # %cond.load99 ; AVX2-NOGATHER-NEXT: vpbroadcastd c+28(%rip), %ymm2 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5,6],ymm2[7] -; AVX2-NOGATHER-NEXT: .LBB5_48: # %else102 +; AVX2-NOGATHER-NEXT: .LBB5_28: # %else102 ; AVX2-NOGATHER-NEXT: vpaddd %ymm0, %ymm1, %ymm0 ; AVX2-NOGATHER-NEXT: retq -; AVX2-NOGATHER-NEXT: .LBB5_1: # %cond.load +; AVX2-NOGATHER-NEXT: .LBB5_29: # %cond.load ; AVX2-NOGATHER-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero ; AVX2-NOGATHER-NEXT: testb $2, %al -; AVX2-NOGATHER-NEXT: je .LBB5_4 -; AVX2-NOGATHER-NEXT: .LBB5_3: # %cond.load1 +; AVX2-NOGATHER-NEXT: je .LBB5_2 +; AVX2-NOGATHER-NEXT: .LBB5_30: # %cond.load1 ; AVX2-NOGATHER-NEXT: vpinsrd $1, c+12(%rip), %xmm1, %xmm2 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm1 = ymm2[0,1,2,3],ymm1[4,5,6,7] ; AVX2-NOGATHER-NEXT: testb $4, %al -; AVX2-NOGATHER-NEXT: je .LBB5_6 -; AVX2-NOGATHER-NEXT: .LBB5_5: # %cond.load4 +; AVX2-NOGATHER-NEXT: je .LBB5_3 +; AVX2-NOGATHER-NEXT: .LBB5_31: # %cond.load4 ; AVX2-NOGATHER-NEXT: vpinsrd $2, c+12(%rip), %xmm1, %xmm2 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm1 = ymm2[0,1,2,3],ymm1[4,5,6,7] ; AVX2-NOGATHER-NEXT: testb $8, %al -; AVX2-NOGATHER-NEXT: je .LBB5_8 -; AVX2-NOGATHER-NEXT: .LBB5_7: # %cond.load7 +; AVX2-NOGATHER-NEXT: je .LBB5_4 +; AVX2-NOGATHER-NEXT: .LBB5_32: # %cond.load7 ; AVX2-NOGATHER-NEXT: vpinsrd $3, c+12(%rip), %xmm1, %xmm2 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm1 = ymm2[0,1,2,3],ymm1[4,5,6,7] ; AVX2-NOGATHER-NEXT: testb $16, %al -; AVX2-NOGATHER-NEXT: je .LBB5_10 -; AVX2-NOGATHER-NEXT: .LBB5_9: # %cond.load10 +; AVX2-NOGATHER-NEXT: je .LBB5_5 +; AVX2-NOGATHER-NEXT: .LBB5_33: # %cond.load10 ; AVX2-NOGATHER-NEXT: vpbroadcastd c+12(%rip), %ymm2 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm2[4],ymm1[5,6,7] ; AVX2-NOGATHER-NEXT: testb $32, %al -; AVX2-NOGATHER-NEXT: je .LBB5_12 -; AVX2-NOGATHER-NEXT: .LBB5_11: # %cond.load13 +; AVX2-NOGATHER-NEXT: je .LBB5_6 +; AVX2-NOGATHER-NEXT: .LBB5_34: # %cond.load13 ; AVX2-NOGATHER-NEXT: vpbroadcastd c+12(%rip), %ymm2 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3,4],ymm2[5],ymm1[6,7] ; AVX2-NOGATHER-NEXT: testb $64, %al -; AVX2-NOGATHER-NEXT: je .LBB5_14 -; AVX2-NOGATHER-NEXT: .LBB5_13: # %cond.load16 +; AVX2-NOGATHER-NEXT: je .LBB5_7 +; AVX2-NOGATHER-NEXT: .LBB5_35: # %cond.load16 ; AVX2-NOGATHER-NEXT: vpbroadcastd c+12(%rip), %ymm2 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3,4,5],ymm2[6],ymm1[7] ; AVX2-NOGATHER-NEXT: testb $-128, %al -; AVX2-NOGATHER-NEXT: jne .LBB5_15 -; AVX2-NOGATHER-NEXT: jmp .LBB5_16 -; AVX2-NOGATHER-NEXT: .LBB5_17: # %cond.load23 +; AVX2-NOGATHER-NEXT: jne .LBB5_8 +; AVX2-NOGATHER-NEXT: jmp .LBB5_9 +; AVX2-NOGATHER-NEXT: .LBB5_36: # %cond.load23 ; AVX2-NOGATHER-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero ; AVX2-NOGATHER-NEXT: testb $2, %al -; AVX2-NOGATHER-NEXT: je .LBB5_20 -; AVX2-NOGATHER-NEXT: .LBB5_19: # %cond.load28 +; AVX2-NOGATHER-NEXT: je .LBB5_11 +; AVX2-NOGATHER-NEXT: .LBB5_37: # %cond.load28 ; AVX2-NOGATHER-NEXT: vpinsrd $1, c+28(%rip), %xmm2, %xmm3 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm2 = ymm3[0,1,2,3],ymm2[4,5,6,7] ; AVX2-NOGATHER-NEXT: testb $4, %al -; AVX2-NOGATHER-NEXT: je .LBB5_22 -; AVX2-NOGATHER-NEXT: .LBB5_21: # %cond.load33 +; AVX2-NOGATHER-NEXT: je .LBB5_12 +; AVX2-NOGATHER-NEXT: .LBB5_38: # %cond.load33 ; AVX2-NOGATHER-NEXT: vpinsrd $2, c+28(%rip), %xmm2, %xmm3 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm2 = ymm3[0,1,2,3],ymm2[4,5,6,7] ; AVX2-NOGATHER-NEXT: testb $8, %al -; AVX2-NOGATHER-NEXT: je .LBB5_24 -; AVX2-NOGATHER-NEXT: .LBB5_23: # %cond.load38 +; AVX2-NOGATHER-NEXT: je .LBB5_13 +; AVX2-NOGATHER-NEXT: .LBB5_39: # %cond.load38 ; AVX2-NOGATHER-NEXT: vpinsrd $3, c+28(%rip), %xmm2, %xmm3 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm2 = ymm3[0,1,2,3],ymm2[4,5,6,7] ; AVX2-NOGATHER-NEXT: testb $16, %al -; AVX2-NOGATHER-NEXT: je .LBB5_26 -; AVX2-NOGATHER-NEXT: .LBB5_25: # %cond.load43 +; AVX2-NOGATHER-NEXT: je .LBB5_14 +; AVX2-NOGATHER-NEXT: .LBB5_40: # %cond.load43 ; AVX2-NOGATHER-NEXT: vpbroadcastd c+28(%rip), %ymm3 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm3[4],ymm2[5,6,7] ; AVX2-NOGATHER-NEXT: testb $32, %al -; AVX2-NOGATHER-NEXT: je .LBB5_28 -; AVX2-NOGATHER-NEXT: .LBB5_27: # %cond.load48 +; AVX2-NOGATHER-NEXT: je .LBB5_15 +; AVX2-NOGATHER-NEXT: .LBB5_41: # %cond.load48 ; AVX2-NOGATHER-NEXT: vpbroadcastd c+28(%rip), %ymm3 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3,4],ymm3[5],ymm2[6,7] ; AVX2-NOGATHER-NEXT: testb $64, %al -; AVX2-NOGATHER-NEXT: je .LBB5_30 -; AVX2-NOGATHER-NEXT: .LBB5_29: # %cond.load53 +; AVX2-NOGATHER-NEXT: je .LBB5_16 +; AVX2-NOGATHER-NEXT: .LBB5_42: # %cond.load53 ; AVX2-NOGATHER-NEXT: vpbroadcastd c+28(%rip), %ymm3 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3,4,5],ymm3[6],ymm2[7] ; AVX2-NOGATHER-NEXT: testb $-128, %al -; AVX2-NOGATHER-NEXT: jne .LBB5_31 -; AVX2-NOGATHER-NEXT: jmp .LBB5_32 -; AVX2-NOGATHER-NEXT: .LBB5_33: # %cond.load64 +; AVX2-NOGATHER-NEXT: jne .LBB5_17 +; AVX2-NOGATHER-NEXT: jmp .LBB5_18 +; AVX2-NOGATHER-NEXT: .LBB5_43: # %cond.load64 ; AVX2-NOGATHER-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; AVX2-NOGATHER-NEXT: testb $2, %al -; AVX2-NOGATHER-NEXT: je .LBB5_36 -; AVX2-NOGATHER-NEXT: .LBB5_35: # %cond.load69 +; AVX2-NOGATHER-NEXT: je .LBB5_20 +; AVX2-NOGATHER-NEXT: .LBB5_44: # %cond.load69 ; AVX2-NOGATHER-NEXT: vpinsrd $1, c+28(%rip), %xmm0, %xmm3 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm0 = ymm3[0,1,2,3],ymm0[4,5,6,7] ; AVX2-NOGATHER-NEXT: testb $4, %al -; AVX2-NOGATHER-NEXT: je .LBB5_38 -; AVX2-NOGATHER-NEXT: .LBB5_37: # %cond.load74 +; AVX2-NOGATHER-NEXT: je .LBB5_21 +; AVX2-NOGATHER-NEXT: .LBB5_45: # %cond.load74 ; AVX2-NOGATHER-NEXT: vpinsrd $2, c+28(%rip), %xmm0, %xmm3 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm0 = ymm3[0,1,2,3],ymm0[4,5,6,7] ; AVX2-NOGATHER-NEXT: testb $8, %al -; AVX2-NOGATHER-NEXT: je .LBB5_40 -; AVX2-NOGATHER-NEXT: .LBB5_39: # %cond.load79 +; AVX2-NOGATHER-NEXT: je .LBB5_22 +; AVX2-NOGATHER-NEXT: .LBB5_46: # %cond.load79 ; AVX2-NOGATHER-NEXT: vpinsrd $3, c+28(%rip), %xmm0, %xmm3 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm0 = ymm3[0,1,2,3],ymm0[4,5,6,7] ; AVX2-NOGATHER-NEXT: testb $16, %al -; AVX2-NOGATHER-NEXT: je .LBB5_42 -; AVX2-NOGATHER-NEXT: .LBB5_41: # %cond.load84 +; AVX2-NOGATHER-NEXT: je .LBB5_23 +; AVX2-NOGATHER-NEXT: .LBB5_47: # %cond.load84 ; AVX2-NOGATHER-NEXT: vpbroadcastd c+28(%rip), %ymm3 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm3[4],ymm0[5,6,7] ; AVX2-NOGATHER-NEXT: testb $32, %al -; AVX2-NOGATHER-NEXT: je .LBB5_44 -; AVX2-NOGATHER-NEXT: .LBB5_43: # %cond.load89 +; AVX2-NOGATHER-NEXT: je .LBB5_24 +; AVX2-NOGATHER-NEXT: .LBB5_48: # %cond.load89 ; AVX2-NOGATHER-NEXT: vpbroadcastd c+28(%rip), %ymm3 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3,4],ymm3[5],ymm0[6,7] ; AVX2-NOGATHER-NEXT: testb $64, %al -; AVX2-NOGATHER-NEXT: jne .LBB5_45 -; AVX2-NOGATHER-NEXT: jmp .LBB5_46 +; AVX2-NOGATHER-NEXT: jne .LBB5_25 +; AVX2-NOGATHER-NEXT: jmp .LBB5_26 ; ; AVX2-GATHER-LABEL: gather_v8i32_v8i32: ; AVX2-GATHER: # %bb.0: @@ -1997,174 +1997,174 @@ define <8 x i32> @masked_gather_v8i32_v8i32(i8 %trigger) { ; SSE-LABEL: masked_gather_v8i32_v8i32: ; SSE: # %bb.0: ; SSE-NEXT: testb $1, %dil -; SSE-NEXT: je .LBB6_1 -; SSE-NEXT: # %bb.2: # %cond.load +; SSE-NEXT: je .LBB6_2 +; SSE-NEXT: # %bb.1: # %cond.load ; SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE-NEXT: testb $2, %dil -; SSE-NEXT: jne .LBB6_4 -; SSE-NEXT: jmp .LBB6_5 -; SSE-NEXT: .LBB6_1: +; SSE-NEXT: jne .LBB6_3 +; SSE-NEXT: jmp .LBB6_4 +; SSE-NEXT: .LBB6_2: ; SSE-NEXT: # implicit-def: $xmm0 ; SSE-NEXT: testb $2, %dil -; SSE-NEXT: je .LBB6_5 -; SSE-NEXT: .LBB6_4: # %cond.load1 +; SSE-NEXT: je .LBB6_4 +; SSE-NEXT: .LBB6_3: # %cond.load1 ; SSE-NEXT: pinsrd $1, c+12(%rip), %xmm0 -; SSE-NEXT: .LBB6_5: # %else2 +; SSE-NEXT: .LBB6_4: # %else2 ; SSE-NEXT: movd %edi, %xmm1 ; SSE-NEXT: testb $4, %dil -; SSE-NEXT: je .LBB6_7 -; SSE-NEXT: # %bb.6: # %cond.load4 +; SSE-NEXT: je .LBB6_6 +; SSE-NEXT: # %bb.5: # %cond.load4 ; SSE-NEXT: pinsrd $2, c+12(%rip), %xmm0 -; SSE-NEXT: .LBB6_7: # %else5 +; SSE-NEXT: .LBB6_6: # %else5 ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,0,0,0,4,5,6,7] ; SSE-NEXT: testb $8, %dil -; SSE-NEXT: je .LBB6_9 -; SSE-NEXT: # %bb.8: # %cond.load7 +; SSE-NEXT: je .LBB6_8 +; SSE-NEXT: # %bb.7: # %cond.load7 ; SSE-NEXT: pinsrd $3, c+12(%rip), %xmm0 -; SSE-NEXT: .LBB6_9: # %else8 +; SSE-NEXT: .LBB6_8: # %else8 ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm1[0,1,0,1] ; SSE-NEXT: pmovzxbw {{.*#+}} xmm2 = [1,2,4,8,16,32,64,128] ; SSE-NEXT: testb $16, %dil ; SSE-NEXT: je .LBB6_10 -; SSE-NEXT: # %bb.11: # %cond.load10 +; SSE-NEXT: # %bb.9: # %cond.load10 ; SSE-NEXT: pinsrd $0, c+12(%rip), %xmm1 -; SSE-NEXT: jmp .LBB6_12 +; SSE-NEXT: jmp .LBB6_11 ; SSE-NEXT: .LBB6_10: ; SSE-NEXT: # implicit-def: $xmm1 -; SSE-NEXT: .LBB6_12: # %else11 +; SSE-NEXT: .LBB6_11: # %else11 ; SSE-NEXT: pand %xmm2, %xmm3 ; SSE-NEXT: testb $32, %dil -; SSE-NEXT: je .LBB6_14 -; SSE-NEXT: # %bb.13: # %cond.load13 +; SSE-NEXT: je .LBB6_13 +; SSE-NEXT: # %bb.12: # %cond.load13 ; SSE-NEXT: pinsrd $1, c+12(%rip), %xmm1 -; SSE-NEXT: .LBB6_14: # %else14 +; SSE-NEXT: .LBB6_13: # %else14 ; SSE-NEXT: pcmpeqw %xmm2, %xmm3 ; SSE-NEXT: testb $64, %dil -; SSE-NEXT: je .LBB6_16 -; SSE-NEXT: # %bb.15: # %cond.load16 +; SSE-NEXT: je .LBB6_15 +; SSE-NEXT: # %bb.14: # %cond.load16 ; SSE-NEXT: pinsrd $2, c+12(%rip), %xmm1 -; SSE-NEXT: .LBB6_16: # %else17 +; SSE-NEXT: .LBB6_15: # %else17 ; SSE-NEXT: psrlw $15, %xmm3 ; SSE-NEXT: testb $-128, %dil -; SSE-NEXT: je .LBB6_18 -; SSE-NEXT: # %bb.17: # %cond.load19 +; SSE-NEXT: je .LBB6_17 +; SSE-NEXT: # %bb.16: # %cond.load19 ; SSE-NEXT: pinsrd $3, c+12(%rip), %xmm1 -; SSE-NEXT: .LBB6_18: # %else20 +; SSE-NEXT: .LBB6_17: # %else20 ; SSE-NEXT: psllw $15, %xmm3 ; SSE-NEXT: movdqa %xmm3, %xmm2 ; SSE-NEXT: packsswb %xmm2, %xmm2 ; SSE-NEXT: pmovmskb %xmm2, %eax ; SSE-NEXT: testb $1, %al ; SSE-NEXT: je .LBB6_19 -; SSE-NEXT: # %bb.20: # %cond.load23 +; SSE-NEXT: # %bb.18: # %cond.load23 ; SSE-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE-NEXT: testb $2, %al -; SSE-NEXT: jne .LBB6_22 -; SSE-NEXT: jmp .LBB6_23 +; SSE-NEXT: jne .LBB6_20 +; SSE-NEXT: jmp .LBB6_21 ; SSE-NEXT: .LBB6_19: ; SSE-NEXT: # implicit-def: $xmm2 ; SSE-NEXT: testb $2, %al -; SSE-NEXT: je .LBB6_23 -; SSE-NEXT: .LBB6_22: # %cond.load28 +; SSE-NEXT: je .LBB6_21 +; SSE-NEXT: .LBB6_20: # %cond.load28 ; SSE-NEXT: pinsrd $1, c+28(%rip), %xmm2 -; SSE-NEXT: .LBB6_23: # %else31 +; SSE-NEXT: .LBB6_21: # %else31 ; SSE-NEXT: testb $4, %al -; SSE-NEXT: jne .LBB6_24 -; SSE-NEXT: # %bb.25: # %else36 +; SSE-NEXT: jne .LBB6_25 +; SSE-NEXT: # %bb.22: # %else36 ; SSE-NEXT: testb $8, %al ; SSE-NEXT: jne .LBB6_26 -; SSE-NEXT: .LBB6_27: # %else41 +; SSE-NEXT: .LBB6_23: # %else41 ; SSE-NEXT: testb $16, %al -; SSE-NEXT: je .LBB6_28 -; SSE-NEXT: .LBB6_29: # %cond.load43 +; SSE-NEXT: je .LBB6_27 +; SSE-NEXT: .LBB6_24: # %cond.load43 ; SSE-NEXT: pinsrd $0, c+28(%rip), %xmm4 ; SSE-NEXT: testb $32, %al -; SSE-NEXT: jne .LBB6_31 -; SSE-NEXT: jmp .LBB6_32 -; SSE-NEXT: .LBB6_24: # %cond.load33 +; SSE-NEXT: jne .LBB6_28 +; SSE-NEXT: jmp .LBB6_29 +; SSE-NEXT: .LBB6_25: # %cond.load33 ; SSE-NEXT: pinsrd $2, c+28(%rip), %xmm2 ; SSE-NEXT: testb $8, %al -; SSE-NEXT: je .LBB6_27 +; SSE-NEXT: je .LBB6_23 ; SSE-NEXT: .LBB6_26: # %cond.load38 ; SSE-NEXT: pinsrd $3, c+28(%rip), %xmm2 ; SSE-NEXT: testb $16, %al -; SSE-NEXT: jne .LBB6_29 -; SSE-NEXT: .LBB6_28: +; SSE-NEXT: jne .LBB6_24 +; SSE-NEXT: .LBB6_27: ; SSE-NEXT: # implicit-def: $xmm4 ; SSE-NEXT: testb $32, %al -; SSE-NEXT: je .LBB6_32 -; SSE-NEXT: .LBB6_31: # %cond.load48 +; SSE-NEXT: je .LBB6_29 +; SSE-NEXT: .LBB6_28: # %cond.load48 ; SSE-NEXT: pinsrd $1, c+28(%rip), %xmm4 -; SSE-NEXT: .LBB6_32: # %else51 +; SSE-NEXT: .LBB6_29: # %else51 ; SSE-NEXT: testb $64, %al -; SSE-NEXT: jne .LBB6_33 -; SSE-NEXT: # %bb.34: # %else56 +; SSE-NEXT: jne .LBB6_34 +; SSE-NEXT: # %bb.30: # %else56 ; SSE-NEXT: testb $-128, %al -; SSE-NEXT: je .LBB6_36 -; SSE-NEXT: .LBB6_35: # %cond.load58 +; SSE-NEXT: je .LBB6_32 +; SSE-NEXT: .LBB6_31: # %cond.load58 ; SSE-NEXT: pinsrd $3, c+28(%rip), %xmm4 -; SSE-NEXT: .LBB6_36: # %else61 +; SSE-NEXT: .LBB6_32: # %else61 ; SSE-NEXT: packsswb %xmm3, %xmm3 ; SSE-NEXT: pmovmskb %xmm3, %eax ; SSE-NEXT: testb $1, %al -; SSE-NEXT: je .LBB6_37 -; SSE-NEXT: # %bb.38: # %cond.load64 +; SSE-NEXT: je .LBB6_35 +; SSE-NEXT: # %bb.33: # %cond.load64 ; SSE-NEXT: movd {{.*#+}} xmm3 = mem[0],zero,zero,zero ; SSE-NEXT: testb $2, %al -; SSE-NEXT: jne .LBB6_40 -; SSE-NEXT: jmp .LBB6_41 -; SSE-NEXT: .LBB6_33: # %cond.load53 +; SSE-NEXT: jne .LBB6_36 +; SSE-NEXT: jmp .LBB6_37 +; SSE-NEXT: .LBB6_34: # %cond.load53 ; SSE-NEXT: pinsrd $2, c+28(%rip), %xmm4 ; SSE-NEXT: testb $-128, %al -; SSE-NEXT: jne .LBB6_35 -; SSE-NEXT: jmp .LBB6_36 -; SSE-NEXT: .LBB6_37: +; SSE-NEXT: jne .LBB6_31 +; SSE-NEXT: jmp .LBB6_32 +; SSE-NEXT: .LBB6_35: ; SSE-NEXT: # implicit-def: $xmm3 ; SSE-NEXT: testb $2, %al -; SSE-NEXT: je .LBB6_41 -; SSE-NEXT: .LBB6_40: # %cond.load69 +; SSE-NEXT: je .LBB6_37 +; SSE-NEXT: .LBB6_36: # %cond.load69 ; SSE-NEXT: pinsrd $1, c+28(%rip), %xmm3 -; SSE-NEXT: .LBB6_41: # %else72 +; SSE-NEXT: .LBB6_37: # %else72 ; SSE-NEXT: testb $4, %al -; SSE-NEXT: jne .LBB6_42 -; SSE-NEXT: # %bb.43: # %else77 +; SSE-NEXT: jne .LBB6_41 +; SSE-NEXT: # %bb.38: # %else77 ; SSE-NEXT: testb $8, %al -; SSE-NEXT: jne .LBB6_44 -; SSE-NEXT: .LBB6_45: # %else82 +; SSE-NEXT: jne .LBB6_42 +; SSE-NEXT: .LBB6_39: # %else82 ; SSE-NEXT: testb $16, %al -; SSE-NEXT: je .LBB6_46 -; SSE-NEXT: .LBB6_47: # %cond.load84 +; SSE-NEXT: je .LBB6_43 +; SSE-NEXT: .LBB6_40: # %cond.load84 ; SSE-NEXT: pinsrd $0, c+28(%rip), %xmm5 ; SSE-NEXT: testb $32, %al -; SSE-NEXT: jne .LBB6_49 -; SSE-NEXT: jmp .LBB6_50 -; SSE-NEXT: .LBB6_42: # %cond.load74 +; SSE-NEXT: jne .LBB6_44 +; SSE-NEXT: jmp .LBB6_45 +; SSE-NEXT: .LBB6_41: # %cond.load74 ; SSE-NEXT: pinsrd $2, c+28(%rip), %xmm3 ; SSE-NEXT: testb $8, %al -; SSE-NEXT: je .LBB6_45 -; SSE-NEXT: .LBB6_44: # %cond.load79 +; SSE-NEXT: je .LBB6_39 +; SSE-NEXT: .LBB6_42: # %cond.load79 ; SSE-NEXT: pinsrd $3, c+28(%rip), %xmm3 ; SSE-NEXT: testb $16, %al -; SSE-NEXT: jne .LBB6_47 -; SSE-NEXT: .LBB6_46: +; SSE-NEXT: jne .LBB6_40 +; SSE-NEXT: .LBB6_43: ; SSE-NEXT: # implicit-def: $xmm5 ; SSE-NEXT: testb $32, %al -; SSE-NEXT: je .LBB6_50 -; SSE-NEXT: .LBB6_49: # %cond.load89 +; SSE-NEXT: je .LBB6_45 +; SSE-NEXT: .LBB6_44: # %cond.load89 ; SSE-NEXT: pinsrd $1, c+28(%rip), %xmm5 -; SSE-NEXT: .LBB6_50: # %else92 +; SSE-NEXT: .LBB6_45: # %else92 ; SSE-NEXT: testb $64, %al -; SSE-NEXT: je .LBB6_52 -; SSE-NEXT: # %bb.51: # %cond.load94 +; SSE-NEXT: je .LBB6_47 +; SSE-NEXT: # %bb.46: # %cond.load94 ; SSE-NEXT: pinsrd $2, c+28(%rip), %xmm5 -; SSE-NEXT: .LBB6_52: # %else97 +; SSE-NEXT: .LBB6_47: # %else97 ; SSE-NEXT: paddd %xmm2, %xmm0 ; SSE-NEXT: paddd %xmm4, %xmm1 ; SSE-NEXT: testb $-128, %al -; SSE-NEXT: je .LBB6_54 -; SSE-NEXT: # %bb.53: # %cond.load99 +; SSE-NEXT: je .LBB6_49 +; SSE-NEXT: # %bb.48: # %cond.load99 ; SSE-NEXT: pinsrd $3, c+28(%rip), %xmm5 -; SSE-NEXT: .LBB6_54: # %else102 +; SSE-NEXT: .LBB6_49: # %else102 ; SSE-NEXT: paddd %xmm5, %xmm1 ; SSE-NEXT: paddd %xmm3, %xmm0 ; SSE-NEXT: retq @@ -2231,331 +2231,331 @@ define <8 x i32> @masked_gather_v8i32_v8i32(i8 %trigger) { ; AVX1-NEXT: vpmovmskb %xmm1, %eax ; AVX1-NEXT: testb $1, %al ; AVX1-NEXT: # implicit-def: $ymm1 -; AVX1-NEXT: jne .LBB6_17 -; AVX1-NEXT: # %bb.18: # %else26 +; AVX1-NEXT: jne .LBB6_38 +; AVX1-NEXT: # %bb.17: # %else26 ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne .LBB6_19 -; AVX1-NEXT: .LBB6_20: # %else31 +; AVX1-NEXT: jne .LBB6_39 +; AVX1-NEXT: .LBB6_18: # %else31 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne .LBB6_21 -; AVX1-NEXT: .LBB6_22: # %else36 +; AVX1-NEXT: jne .LBB6_40 +; AVX1-NEXT: .LBB6_19: # %else36 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne .LBB6_23 -; AVX1-NEXT: .LBB6_24: # %else41 +; AVX1-NEXT: jne .LBB6_41 +; AVX1-NEXT: .LBB6_20: # %else41 ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: jne .LBB6_25 -; AVX1-NEXT: .LBB6_26: # %else46 +; AVX1-NEXT: jne .LBB6_42 +; AVX1-NEXT: .LBB6_21: # %else46 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: jne .LBB6_27 -; AVX1-NEXT: .LBB6_28: # %else51 +; AVX1-NEXT: jne .LBB6_43 +; AVX1-NEXT: .LBB6_22: # %else51 ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: jne .LBB6_29 -; AVX1-NEXT: .LBB6_30: # %else56 +; AVX1-NEXT: jne .LBB6_44 +; AVX1-NEXT: .LBB6_23: # %else56 ; AVX1-NEXT: testb $-128, %al -; AVX1-NEXT: je .LBB6_32 -; AVX1-NEXT: .LBB6_31: # %cond.load58 +; AVX1-NEXT: je .LBB6_25 +; AVX1-NEXT: .LBB6_24: # %cond.load58 ; AVX1-NEXT: vbroadcastss c+28(%rip), %ymm3 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1,2,3,4,5,6],ymm3[7] -; AVX1-NEXT: .LBB6_32: # %else61 +; AVX1-NEXT: .LBB6_25: # %else61 ; AVX1-NEXT: vpacksswb %xmm2, %xmm2, %xmm2 ; AVX1-NEXT: vpmovmskb %xmm2, %eax ; AVX1-NEXT: testb $1, %al ; AVX1-NEXT: # implicit-def: $ymm2 -; AVX1-NEXT: jne .LBB6_33 -; AVX1-NEXT: # %bb.34: # %else67 +; AVX1-NEXT: jne .LBB6_45 +; AVX1-NEXT: # %bb.26: # %else67 ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne .LBB6_35 -; AVX1-NEXT: .LBB6_36: # %else72 +; AVX1-NEXT: jne .LBB6_46 +; AVX1-NEXT: .LBB6_27: # %else72 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne .LBB6_37 -; AVX1-NEXT: .LBB6_38: # %else77 +; AVX1-NEXT: jne .LBB6_47 +; AVX1-NEXT: .LBB6_28: # %else77 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne .LBB6_39 -; AVX1-NEXT: .LBB6_40: # %else82 +; AVX1-NEXT: jne .LBB6_48 +; AVX1-NEXT: .LBB6_29: # %else82 ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: je .LBB6_42 -; AVX1-NEXT: .LBB6_41: # %cond.load84 +; AVX1-NEXT: je .LBB6_31 +; AVX1-NEXT: .LBB6_30: # %cond.load84 ; AVX1-NEXT: vbroadcastss c+28(%rip), %ymm3 ; AVX1-NEXT: vblendps {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm3[4],ymm2[5,6,7] -; AVX1-NEXT: .LBB6_42: # %else87 +; AVX1-NEXT: .LBB6_31: # %else87 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4 ; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je .LBB6_44 -; AVX1-NEXT: # %bb.43: # %cond.load89 +; AVX1-NEXT: je .LBB6_33 +; AVX1-NEXT: # %bb.32: # %cond.load89 ; AVX1-NEXT: vbroadcastss c+28(%rip), %ymm1 ; AVX1-NEXT: vblendps {{.*#+}} ymm2 = ymm2[0,1,2,3,4],ymm1[5],ymm2[6,7] -; AVX1-NEXT: .LBB6_44: # %else92 +; AVX1-NEXT: .LBB6_33: # %else92 ; AVX1-NEXT: vpaddd %xmm3, %xmm4, %xmm1 ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: je .LBB6_46 -; AVX1-NEXT: # %bb.45: # %cond.load94 +; AVX1-NEXT: je .LBB6_35 +; AVX1-NEXT: # %bb.34: # %cond.load94 ; AVX1-NEXT: vbroadcastss c+28(%rip), %ymm3 ; AVX1-NEXT: vblendps {{.*#+}} ymm2 = ymm2[0,1,2,3,4,5],ymm3[6],ymm2[7] -; AVX1-NEXT: .LBB6_46: # %else97 +; AVX1-NEXT: .LBB6_35: # %else97 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: testb $-128, %al -; AVX1-NEXT: je .LBB6_48 -; AVX1-NEXT: # %bb.47: # %cond.load99 +; AVX1-NEXT: je .LBB6_37 +; AVX1-NEXT: # %bb.36: # %cond.load99 ; AVX1-NEXT: vbroadcastss c+28(%rip), %ymm1 ; AVX1-NEXT: vblendps {{.*#+}} ymm2 = ymm2[0,1,2,3,4,5,6],ymm1[7] -; AVX1-NEXT: .LBB6_48: # %else102 +; AVX1-NEXT: .LBB6_37: # %else102 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 ; AVX1-NEXT: vpaddd %xmm1, %xmm3, %xmm1 ; AVX1-NEXT: vpaddd %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB6_17: # %cond.load23 +; AVX1-NEXT: .LBB6_38: # %cond.load23 ; AVX1-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je .LBB6_20 -; AVX1-NEXT: .LBB6_19: # %cond.load28 +; AVX1-NEXT: je .LBB6_18 +; AVX1-NEXT: .LBB6_39: # %cond.load28 ; AVX1-NEXT: vpinsrd $1, c+28(%rip), %xmm1, %xmm3 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm3[0,1,2,3],ymm1[4,5,6,7] ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je .LBB6_22 -; AVX1-NEXT: .LBB6_21: # %cond.load33 +; AVX1-NEXT: je .LBB6_19 +; AVX1-NEXT: .LBB6_40: # %cond.load33 ; AVX1-NEXT: vpinsrd $2, c+28(%rip), %xmm1, %xmm3 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm3[0,1,2,3],ymm1[4,5,6,7] ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB6_24 -; AVX1-NEXT: .LBB6_23: # %cond.load38 +; AVX1-NEXT: je .LBB6_20 +; AVX1-NEXT: .LBB6_41: # %cond.load38 ; AVX1-NEXT: vpinsrd $3, c+28(%rip), %xmm1, %xmm3 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm3[0,1,2,3],ymm1[4,5,6,7] ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: je .LBB6_26 -; AVX1-NEXT: .LBB6_25: # %cond.load43 +; AVX1-NEXT: je .LBB6_21 +; AVX1-NEXT: .LBB6_42: # %cond.load43 ; AVX1-NEXT: vbroadcastss c+28(%rip), %ymm3 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm3[4],ymm1[5,6,7] ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je .LBB6_28 -; AVX1-NEXT: .LBB6_27: # %cond.load48 +; AVX1-NEXT: je .LBB6_22 +; AVX1-NEXT: .LBB6_43: # %cond.load48 ; AVX1-NEXT: vbroadcastss c+28(%rip), %ymm3 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1,2,3,4],ymm3[5],ymm1[6,7] ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: je .LBB6_30 -; AVX1-NEXT: .LBB6_29: # %cond.load53 +; AVX1-NEXT: je .LBB6_23 +; AVX1-NEXT: .LBB6_44: # %cond.load53 ; AVX1-NEXT: vbroadcastss c+28(%rip), %ymm3 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1,2,3,4,5],ymm3[6],ymm1[7] ; AVX1-NEXT: testb $-128, %al -; AVX1-NEXT: jne .LBB6_31 -; AVX1-NEXT: jmp .LBB6_32 -; AVX1-NEXT: .LBB6_33: # %cond.load64 +; AVX1-NEXT: jne .LBB6_24 +; AVX1-NEXT: jmp .LBB6_25 +; AVX1-NEXT: .LBB6_45: # %cond.load64 ; AVX1-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je .LBB6_36 -; AVX1-NEXT: .LBB6_35: # %cond.load69 +; AVX1-NEXT: je .LBB6_27 +; AVX1-NEXT: .LBB6_46: # %cond.load69 ; AVX1-NEXT: vpinsrd $1, c+28(%rip), %xmm2, %xmm3 ; AVX1-NEXT: vblendps {{.*#+}} ymm2 = ymm3[0,1,2,3],ymm2[4,5,6,7] ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je .LBB6_38 -; AVX1-NEXT: .LBB6_37: # %cond.load74 +; AVX1-NEXT: je .LBB6_28 +; AVX1-NEXT: .LBB6_47: # %cond.load74 ; AVX1-NEXT: vpinsrd $2, c+28(%rip), %xmm2, %xmm3 ; AVX1-NEXT: vblendps {{.*#+}} ymm2 = ymm3[0,1,2,3],ymm2[4,5,6,7] ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB6_40 -; AVX1-NEXT: .LBB6_39: # %cond.load79 +; AVX1-NEXT: je .LBB6_29 +; AVX1-NEXT: .LBB6_48: # %cond.load79 ; AVX1-NEXT: vpinsrd $3, c+28(%rip), %xmm2, %xmm3 ; AVX1-NEXT: vblendps {{.*#+}} ymm2 = ymm3[0,1,2,3],ymm2[4,5,6,7] ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: jne .LBB6_41 -; AVX1-NEXT: jmp .LBB6_42 +; AVX1-NEXT: jne .LBB6_30 +; AVX1-NEXT: jmp .LBB6_31 ; ; AVX2-NOGATHER-LABEL: masked_gather_v8i32_v8i32: ; AVX2-NOGATHER: # %bb.0: ; AVX2-NOGATHER-NEXT: testb $1, %dil ; AVX2-NOGATHER-NEXT: # implicit-def: $ymm0 -; AVX2-NOGATHER-NEXT: jne .LBB6_1 -; AVX2-NOGATHER-NEXT: # %bb.2: # %else +; AVX2-NOGATHER-NEXT: jne .LBB6_34 +; AVX2-NOGATHER-NEXT: # %bb.1: # %else ; AVX2-NOGATHER-NEXT: testb $2, %dil -; AVX2-NOGATHER-NEXT: jne .LBB6_3 -; AVX2-NOGATHER-NEXT: .LBB6_4: # %else2 +; AVX2-NOGATHER-NEXT: jne .LBB6_35 +; AVX2-NOGATHER-NEXT: .LBB6_2: # %else2 ; AVX2-NOGATHER-NEXT: testb $4, %dil -; AVX2-NOGATHER-NEXT: je .LBB6_6 -; AVX2-NOGATHER-NEXT: .LBB6_5: # %cond.load4 +; AVX2-NOGATHER-NEXT: je .LBB6_4 +; AVX2-NOGATHER-NEXT: .LBB6_3: # %cond.load4 ; AVX2-NOGATHER-NEXT: vpinsrd $2, c+12(%rip), %xmm0, %xmm1 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7] -; AVX2-NOGATHER-NEXT: .LBB6_6: # %else5 +; AVX2-NOGATHER-NEXT: .LBB6_4: # %else5 ; AVX2-NOGATHER-NEXT: vmovd %edi, %xmm1 ; AVX2-NOGATHER-NEXT: testb $8, %dil -; AVX2-NOGATHER-NEXT: je .LBB6_8 -; AVX2-NOGATHER-NEXT: # %bb.7: # %cond.load7 +; AVX2-NOGATHER-NEXT: je .LBB6_6 +; AVX2-NOGATHER-NEXT: # %bb.5: # %cond.load7 ; AVX2-NOGATHER-NEXT: vpinsrd $3, c+12(%rip), %xmm0, %xmm2 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm0 = ymm2[0,1,2,3],ymm0[4,5,6,7] -; AVX2-NOGATHER-NEXT: .LBB6_8: # %else8 +; AVX2-NOGATHER-NEXT: .LBB6_6: # %else8 ; AVX2-NOGATHER-NEXT: vpbroadcastb %xmm1, %xmm2 ; AVX2-NOGATHER-NEXT: vpmovzxbw {{.*#+}} xmm1 = [1,2,4,8,16,32,64,128] ; AVX2-NOGATHER-NEXT: testb $16, %dil -; AVX2-NOGATHER-NEXT: je .LBB6_10 -; AVX2-NOGATHER-NEXT: # %bb.9: # %cond.load10 +; AVX2-NOGATHER-NEXT: je .LBB6_8 +; AVX2-NOGATHER-NEXT: # %bb.7: # %cond.load10 ; AVX2-NOGATHER-NEXT: vpbroadcastd c+12(%rip), %ymm3 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm3[4],ymm0[5,6,7] -; AVX2-NOGATHER-NEXT: .LBB6_10: # %else11 +; AVX2-NOGATHER-NEXT: .LBB6_8: # %else11 ; AVX2-NOGATHER-NEXT: vpand %xmm1, %xmm2, %xmm2 ; AVX2-NOGATHER-NEXT: testb $32, %dil -; AVX2-NOGATHER-NEXT: je .LBB6_12 -; AVX2-NOGATHER-NEXT: # %bb.11: # %cond.load13 +; AVX2-NOGATHER-NEXT: je .LBB6_10 +; AVX2-NOGATHER-NEXT: # %bb.9: # %cond.load13 ; AVX2-NOGATHER-NEXT: vpbroadcastd c+12(%rip), %ymm3 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3,4],ymm3[5],ymm0[6,7] -; AVX2-NOGATHER-NEXT: .LBB6_12: # %else14 +; AVX2-NOGATHER-NEXT: .LBB6_10: # %else14 ; AVX2-NOGATHER-NEXT: vpcmpeqw %xmm1, %xmm2, %xmm1 ; AVX2-NOGATHER-NEXT: testb $64, %dil -; AVX2-NOGATHER-NEXT: je .LBB6_14 -; AVX2-NOGATHER-NEXT: # %bb.13: # %cond.load16 +; AVX2-NOGATHER-NEXT: je .LBB6_12 +; AVX2-NOGATHER-NEXT: # %bb.11: # %cond.load16 ; AVX2-NOGATHER-NEXT: vpbroadcastd c+12(%rip), %ymm2 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5],ymm2[6],ymm0[7] -; AVX2-NOGATHER-NEXT: .LBB6_14: # %else17 +; AVX2-NOGATHER-NEXT: .LBB6_12: # %else17 ; AVX2-NOGATHER-NEXT: vpsrlw $15, %xmm1, %xmm1 ; AVX2-NOGATHER-NEXT: testb $-128, %dil -; AVX2-NOGATHER-NEXT: je .LBB6_16 -; AVX2-NOGATHER-NEXT: # %bb.15: # %cond.load19 +; AVX2-NOGATHER-NEXT: je .LBB6_14 +; AVX2-NOGATHER-NEXT: # %bb.13: # %cond.load19 ; AVX2-NOGATHER-NEXT: vpbroadcastd c+12(%rip), %ymm2 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5,6],ymm2[7] -; AVX2-NOGATHER-NEXT: .LBB6_16: # %else20 +; AVX2-NOGATHER-NEXT: .LBB6_14: # %else20 ; AVX2-NOGATHER-NEXT: vpsllw $15, %xmm1, %xmm2 ; AVX2-NOGATHER-NEXT: vpacksswb %xmm2, %xmm2, %xmm1 ; AVX2-NOGATHER-NEXT: vpmovmskb %xmm1, %eax ; AVX2-NOGATHER-NEXT: testb $1, %al ; AVX2-NOGATHER-NEXT: # implicit-def: $ymm1 -; AVX2-NOGATHER-NEXT: jne .LBB6_17 -; AVX2-NOGATHER-NEXT: # %bb.18: # %else26 +; AVX2-NOGATHER-NEXT: jne .LBB6_36 +; AVX2-NOGATHER-NEXT: # %bb.15: # %else26 ; AVX2-NOGATHER-NEXT: testb $2, %al -; AVX2-NOGATHER-NEXT: jne .LBB6_19 -; AVX2-NOGATHER-NEXT: .LBB6_20: # %else31 +; AVX2-NOGATHER-NEXT: jne .LBB6_37 +; AVX2-NOGATHER-NEXT: .LBB6_16: # %else31 ; AVX2-NOGATHER-NEXT: testb $4, %al -; AVX2-NOGATHER-NEXT: jne .LBB6_21 -; AVX2-NOGATHER-NEXT: .LBB6_22: # %else36 +; AVX2-NOGATHER-NEXT: jne .LBB6_38 +; AVX2-NOGATHER-NEXT: .LBB6_17: # %else36 ; AVX2-NOGATHER-NEXT: testb $8, %al -; AVX2-NOGATHER-NEXT: jne .LBB6_23 -; AVX2-NOGATHER-NEXT: .LBB6_24: # %else41 +; AVX2-NOGATHER-NEXT: jne .LBB6_39 +; AVX2-NOGATHER-NEXT: .LBB6_18: # %else41 ; AVX2-NOGATHER-NEXT: testb $16, %al -; AVX2-NOGATHER-NEXT: jne .LBB6_25 -; AVX2-NOGATHER-NEXT: .LBB6_26: # %else46 +; AVX2-NOGATHER-NEXT: jne .LBB6_40 +; AVX2-NOGATHER-NEXT: .LBB6_19: # %else46 ; AVX2-NOGATHER-NEXT: testb $32, %al -; AVX2-NOGATHER-NEXT: jne .LBB6_27 -; AVX2-NOGATHER-NEXT: .LBB6_28: # %else51 +; AVX2-NOGATHER-NEXT: jne .LBB6_41 +; AVX2-NOGATHER-NEXT: .LBB6_20: # %else51 ; AVX2-NOGATHER-NEXT: testb $64, %al -; AVX2-NOGATHER-NEXT: jne .LBB6_29 -; AVX2-NOGATHER-NEXT: .LBB6_30: # %else56 +; AVX2-NOGATHER-NEXT: jne .LBB6_42 +; AVX2-NOGATHER-NEXT: .LBB6_21: # %else56 ; AVX2-NOGATHER-NEXT: testb $-128, %al -; AVX2-NOGATHER-NEXT: je .LBB6_32 -; AVX2-NOGATHER-NEXT: .LBB6_31: # %cond.load58 +; AVX2-NOGATHER-NEXT: je .LBB6_23 +; AVX2-NOGATHER-NEXT: .LBB6_22: # %cond.load58 ; AVX2-NOGATHER-NEXT: vpbroadcastd c+28(%rip), %ymm3 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3,4,5,6],ymm3[7] -; AVX2-NOGATHER-NEXT: .LBB6_32: # %else61 +; AVX2-NOGATHER-NEXT: .LBB6_23: # %else61 ; AVX2-NOGATHER-NEXT: vpacksswb %xmm2, %xmm2, %xmm2 ; AVX2-NOGATHER-NEXT: vpmovmskb %xmm2, %eax ; AVX2-NOGATHER-NEXT: testb $1, %al ; AVX2-NOGATHER-NEXT: # implicit-def: $ymm2 -; AVX2-NOGATHER-NEXT: jne .LBB6_33 -; AVX2-NOGATHER-NEXT: # %bb.34: # %else67 +; AVX2-NOGATHER-NEXT: jne .LBB6_43 +; AVX2-NOGATHER-NEXT: # %bb.24: # %else67 ; AVX2-NOGATHER-NEXT: testb $2, %al -; AVX2-NOGATHER-NEXT: jne .LBB6_35 -; AVX2-NOGATHER-NEXT: .LBB6_36: # %else72 +; AVX2-NOGATHER-NEXT: jne .LBB6_44 +; AVX2-NOGATHER-NEXT: .LBB6_25: # %else72 ; AVX2-NOGATHER-NEXT: testb $4, %al -; AVX2-NOGATHER-NEXT: jne .LBB6_37 -; AVX2-NOGATHER-NEXT: .LBB6_38: # %else77 +; AVX2-NOGATHER-NEXT: jne .LBB6_45 +; AVX2-NOGATHER-NEXT: .LBB6_26: # %else77 ; AVX2-NOGATHER-NEXT: testb $8, %al -; AVX2-NOGATHER-NEXT: jne .LBB6_39 -; AVX2-NOGATHER-NEXT: .LBB6_40: # %else82 +; AVX2-NOGATHER-NEXT: jne .LBB6_46 +; AVX2-NOGATHER-NEXT: .LBB6_27: # %else82 ; AVX2-NOGATHER-NEXT: testb $16, %al -; AVX2-NOGATHER-NEXT: jne .LBB6_41 -; AVX2-NOGATHER-NEXT: .LBB6_42: # %else87 +; AVX2-NOGATHER-NEXT: jne .LBB6_47 +; AVX2-NOGATHER-NEXT: .LBB6_28: # %else87 ; AVX2-NOGATHER-NEXT: testb $32, %al -; AVX2-NOGATHER-NEXT: jne .LBB6_43 -; AVX2-NOGATHER-NEXT: .LBB6_44: # %else92 +; AVX2-NOGATHER-NEXT: jne .LBB6_48 +; AVX2-NOGATHER-NEXT: .LBB6_29: # %else92 ; AVX2-NOGATHER-NEXT: testb $64, %al -; AVX2-NOGATHER-NEXT: je .LBB6_46 -; AVX2-NOGATHER-NEXT: .LBB6_45: # %cond.load94 +; AVX2-NOGATHER-NEXT: je .LBB6_31 +; AVX2-NOGATHER-NEXT: .LBB6_30: # %cond.load94 ; AVX2-NOGATHER-NEXT: vpbroadcastd c+28(%rip), %ymm3 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3,4,5],ymm3[6],ymm2[7] -; AVX2-NOGATHER-NEXT: .LBB6_46: # %else97 +; AVX2-NOGATHER-NEXT: .LBB6_31: # %else97 ; AVX2-NOGATHER-NEXT: vpaddd %ymm1, %ymm0, %ymm0 ; AVX2-NOGATHER-NEXT: testb $-128, %al -; AVX2-NOGATHER-NEXT: je .LBB6_48 -; AVX2-NOGATHER-NEXT: # %bb.47: # %cond.load99 +; AVX2-NOGATHER-NEXT: je .LBB6_33 +; AVX2-NOGATHER-NEXT: # %bb.32: # %cond.load99 ; AVX2-NOGATHER-NEXT: vpbroadcastd c+28(%rip), %ymm1 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3,4,5,6],ymm1[7] -; AVX2-NOGATHER-NEXT: .LBB6_48: # %else102 +; AVX2-NOGATHER-NEXT: .LBB6_33: # %else102 ; AVX2-NOGATHER-NEXT: vpaddd %ymm2, %ymm0, %ymm0 ; AVX2-NOGATHER-NEXT: retq -; AVX2-NOGATHER-NEXT: .LBB6_1: # %cond.load +; AVX2-NOGATHER-NEXT: .LBB6_34: # %cond.load ; AVX2-NOGATHER-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; AVX2-NOGATHER-NEXT: testb $2, %dil -; AVX2-NOGATHER-NEXT: je .LBB6_4 -; AVX2-NOGATHER-NEXT: .LBB6_3: # %cond.load1 +; AVX2-NOGATHER-NEXT: je .LBB6_2 +; AVX2-NOGATHER-NEXT: .LBB6_35: # %cond.load1 ; AVX2-NOGATHER-NEXT: vpinsrd $1, c+12(%rip), %xmm0, %xmm1 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7] ; AVX2-NOGATHER-NEXT: testb $4, %dil -; AVX2-NOGATHER-NEXT: jne .LBB6_5 -; AVX2-NOGATHER-NEXT: jmp .LBB6_6 -; AVX2-NOGATHER-NEXT: .LBB6_17: # %cond.load23 +; AVX2-NOGATHER-NEXT: jne .LBB6_3 +; AVX2-NOGATHER-NEXT: jmp .LBB6_4 +; AVX2-NOGATHER-NEXT: .LBB6_36: # %cond.load23 ; AVX2-NOGATHER-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero ; AVX2-NOGATHER-NEXT: testb $2, %al -; AVX2-NOGATHER-NEXT: je .LBB6_20 -; AVX2-NOGATHER-NEXT: .LBB6_19: # %cond.load28 +; AVX2-NOGATHER-NEXT: je .LBB6_16 +; AVX2-NOGATHER-NEXT: .LBB6_37: # %cond.load28 ; AVX2-NOGATHER-NEXT: vpinsrd $1, c+28(%rip), %xmm1, %xmm3 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm1 = ymm3[0,1,2,3],ymm1[4,5,6,7] ; AVX2-NOGATHER-NEXT: testb $4, %al -; AVX2-NOGATHER-NEXT: je .LBB6_22 -; AVX2-NOGATHER-NEXT: .LBB6_21: # %cond.load33 +; AVX2-NOGATHER-NEXT: je .LBB6_17 +; AVX2-NOGATHER-NEXT: .LBB6_38: # %cond.load33 ; AVX2-NOGATHER-NEXT: vpinsrd $2, c+28(%rip), %xmm1, %xmm3 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm1 = ymm3[0,1,2,3],ymm1[4,5,6,7] ; AVX2-NOGATHER-NEXT: testb $8, %al -; AVX2-NOGATHER-NEXT: je .LBB6_24 -; AVX2-NOGATHER-NEXT: .LBB6_23: # %cond.load38 +; AVX2-NOGATHER-NEXT: je .LBB6_18 +; AVX2-NOGATHER-NEXT: .LBB6_39: # %cond.load38 ; AVX2-NOGATHER-NEXT: vpinsrd $3, c+28(%rip), %xmm1, %xmm3 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm1 = ymm3[0,1,2,3],ymm1[4,5,6,7] ; AVX2-NOGATHER-NEXT: testb $16, %al -; AVX2-NOGATHER-NEXT: je .LBB6_26 -; AVX2-NOGATHER-NEXT: .LBB6_25: # %cond.load43 +; AVX2-NOGATHER-NEXT: je .LBB6_19 +; AVX2-NOGATHER-NEXT: .LBB6_40: # %cond.load43 ; AVX2-NOGATHER-NEXT: vpbroadcastd c+28(%rip), %ymm3 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm3[4],ymm1[5,6,7] ; AVX2-NOGATHER-NEXT: testb $32, %al -; AVX2-NOGATHER-NEXT: je .LBB6_28 -; AVX2-NOGATHER-NEXT: .LBB6_27: # %cond.load48 +; AVX2-NOGATHER-NEXT: je .LBB6_20 +; AVX2-NOGATHER-NEXT: .LBB6_41: # %cond.load48 ; AVX2-NOGATHER-NEXT: vpbroadcastd c+28(%rip), %ymm3 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3,4],ymm3[5],ymm1[6,7] ; AVX2-NOGATHER-NEXT: testb $64, %al -; AVX2-NOGATHER-NEXT: je .LBB6_30 -; AVX2-NOGATHER-NEXT: .LBB6_29: # %cond.load53 +; AVX2-NOGATHER-NEXT: je .LBB6_21 +; AVX2-NOGATHER-NEXT: .LBB6_42: # %cond.load53 ; AVX2-NOGATHER-NEXT: vpbroadcastd c+28(%rip), %ymm3 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3,4,5],ymm3[6],ymm1[7] ; AVX2-NOGATHER-NEXT: testb $-128, %al -; AVX2-NOGATHER-NEXT: jne .LBB6_31 -; AVX2-NOGATHER-NEXT: jmp .LBB6_32 -; AVX2-NOGATHER-NEXT: .LBB6_33: # %cond.load64 +; AVX2-NOGATHER-NEXT: jne .LBB6_22 +; AVX2-NOGATHER-NEXT: jmp .LBB6_23 +; AVX2-NOGATHER-NEXT: .LBB6_43: # %cond.load64 ; AVX2-NOGATHER-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero ; AVX2-NOGATHER-NEXT: testb $2, %al -; AVX2-NOGATHER-NEXT: je .LBB6_36 -; AVX2-NOGATHER-NEXT: .LBB6_35: # %cond.load69 +; AVX2-NOGATHER-NEXT: je .LBB6_25 +; AVX2-NOGATHER-NEXT: .LBB6_44: # %cond.load69 ; AVX2-NOGATHER-NEXT: vpinsrd $1, c+28(%rip), %xmm2, %xmm3 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm2 = ymm3[0,1,2,3],ymm2[4,5,6,7] ; AVX2-NOGATHER-NEXT: testb $4, %al -; AVX2-NOGATHER-NEXT: je .LBB6_38 -; AVX2-NOGATHER-NEXT: .LBB6_37: # %cond.load74 +; AVX2-NOGATHER-NEXT: je .LBB6_26 +; AVX2-NOGATHER-NEXT: .LBB6_45: # %cond.load74 ; AVX2-NOGATHER-NEXT: vpinsrd $2, c+28(%rip), %xmm2, %xmm3 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm2 = ymm3[0,1,2,3],ymm2[4,5,6,7] ; AVX2-NOGATHER-NEXT: testb $8, %al -; AVX2-NOGATHER-NEXT: je .LBB6_40 -; AVX2-NOGATHER-NEXT: .LBB6_39: # %cond.load79 +; AVX2-NOGATHER-NEXT: je .LBB6_27 +; AVX2-NOGATHER-NEXT: .LBB6_46: # %cond.load79 ; AVX2-NOGATHER-NEXT: vpinsrd $3, c+28(%rip), %xmm2, %xmm3 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm2 = ymm3[0,1,2,3],ymm2[4,5,6,7] ; AVX2-NOGATHER-NEXT: testb $16, %al -; AVX2-NOGATHER-NEXT: je .LBB6_42 -; AVX2-NOGATHER-NEXT: .LBB6_41: # %cond.load84 +; AVX2-NOGATHER-NEXT: je .LBB6_28 +; AVX2-NOGATHER-NEXT: .LBB6_47: # %cond.load84 ; AVX2-NOGATHER-NEXT: vpbroadcastd c+28(%rip), %ymm3 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm3[4],ymm2[5,6,7] ; AVX2-NOGATHER-NEXT: testb $32, %al -; AVX2-NOGATHER-NEXT: je .LBB6_44 -; AVX2-NOGATHER-NEXT: .LBB6_43: # %cond.load89 +; AVX2-NOGATHER-NEXT: je .LBB6_29 +; AVX2-NOGATHER-NEXT: .LBB6_48: # %cond.load89 ; AVX2-NOGATHER-NEXT: vpbroadcastd c+28(%rip), %ymm3 ; AVX2-NOGATHER-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3,4],ymm3[5],ymm2[6,7] ; AVX2-NOGATHER-NEXT: testb $64, %al -; AVX2-NOGATHER-NEXT: jne .LBB6_45 -; AVX2-NOGATHER-NEXT: jmp .LBB6_46 +; AVX2-NOGATHER-NEXT: jne .LBB6_30 +; AVX2-NOGATHER-NEXT: jmp .LBB6_31 ; ; AVX2-GATHER-LABEL: masked_gather_v8i32_v8i32: ; AVX2-GATHER: # %bb.0: diff --git a/llvm/test/CodeGen/X86/masked_gather_scatter.ll b/llvm/test/CodeGen/X86/masked_gather_scatter.ll index d0a46388b7e76..900c9ea27a6a1 100644 --- a/llvm/test/CodeGen/X86/masked_gather_scatter.ll +++ b/llvm/test/CodeGen/X86/masked_gather_scatter.ll @@ -672,19 +672,19 @@ define <4 x float> @test15(ptr %base, <4 x i32> %ind, <4 x i1> %mask) { ; X64-KNL-NEXT: .LBB14_4: # %else2 ; X64-KNL-NEXT: testb $4, %al ; X64-KNL-NEXT: vextracti128 $1, %ymm1, %xmm1 -; X64-KNL-NEXT: jne .LBB14_5 -; X64-KNL-NEXT: # %bb.6: # %else5 -; X64-KNL-NEXT: testb $8, %al ; X64-KNL-NEXT: jne .LBB14_7 -; X64-KNL-NEXT: .LBB14_8: # %else8 +; X64-KNL-NEXT: # %bb.5: # %else5 +; X64-KNL-NEXT: testb $8, %al +; X64-KNL-NEXT: jne .LBB14_8 +; X64-KNL-NEXT: .LBB14_6: # %else8 ; X64-KNL-NEXT: vzeroupper ; X64-KNL-NEXT: retq -; X64-KNL-NEXT: .LBB14_5: # %cond.load4 +; X64-KNL-NEXT: .LBB14_7: # %cond.load4 ; X64-KNL-NEXT: vmovq %xmm1, %rcx ; X64-KNL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3] ; X64-KNL-NEXT: testb $8, %al -; X64-KNL-NEXT: je .LBB14_8 -; X64-KNL-NEXT: .LBB14_7: # %cond.load7 +; X64-KNL-NEXT: je .LBB14_6 +; X64-KNL-NEXT: .LBB14_8: # %cond.load7 ; X64-KNL-NEXT: vpextrq $1, %xmm1, %rax ; X64-KNL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0] ; X64-KNL-NEXT: vzeroupper @@ -700,35 +700,35 @@ define <4 x float> @test15(ptr %base, <4 x i32> %ind, <4 x i1> %mask) { ; X86-KNL-NEXT: kmovw %k0, %eax ; X86-KNL-NEXT: testb $1, %al ; X86-KNL-NEXT: # implicit-def: $xmm0 -; X86-KNL-NEXT: jne .LBB14_1 -; X86-KNL-NEXT: # %bb.2: # %else +; X86-KNL-NEXT: jne .LBB14_5 +; X86-KNL-NEXT: # %bb.1: # %else ; X86-KNL-NEXT: testb $2, %al -; X86-KNL-NEXT: jne .LBB14_3 -; X86-KNL-NEXT: .LBB14_4: # %else2 +; X86-KNL-NEXT: jne .LBB14_6 +; X86-KNL-NEXT: .LBB14_2: # %else2 ; X86-KNL-NEXT: testb $4, %al -; X86-KNL-NEXT: jne .LBB14_5 -; X86-KNL-NEXT: .LBB14_6: # %else5 -; X86-KNL-NEXT: testb $8, %al ; X86-KNL-NEXT: jne .LBB14_7 -; X86-KNL-NEXT: .LBB14_8: # %else8 +; X86-KNL-NEXT: .LBB14_3: # %else5 +; X86-KNL-NEXT: testb $8, %al +; X86-KNL-NEXT: jne .LBB14_8 +; X86-KNL-NEXT: .LBB14_4: # %else8 ; X86-KNL-NEXT: vzeroupper ; X86-KNL-NEXT: retl -; X86-KNL-NEXT: .LBB14_1: # %cond.load +; X86-KNL-NEXT: .LBB14_5: # %cond.load ; X86-KNL-NEXT: vmovd %xmm1, %ecx ; X86-KNL-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-KNL-NEXT: testb $2, %al -; X86-KNL-NEXT: je .LBB14_4 -; X86-KNL-NEXT: .LBB14_3: # %cond.load1 +; X86-KNL-NEXT: je .LBB14_2 +; X86-KNL-NEXT: .LBB14_6: # %cond.load1 ; X86-KNL-NEXT: vpextrd $1, %xmm1, %ecx ; X86-KNL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3] ; X86-KNL-NEXT: testb $4, %al -; X86-KNL-NEXT: je .LBB14_6 -; X86-KNL-NEXT: .LBB14_5: # %cond.load4 +; X86-KNL-NEXT: je .LBB14_3 +; X86-KNL-NEXT: .LBB14_7: # %cond.load4 ; X86-KNL-NEXT: vpextrd $2, %xmm1, %ecx ; X86-KNL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3] ; X86-KNL-NEXT: testb $8, %al -; X86-KNL-NEXT: je .LBB14_8 -; X86-KNL-NEXT: .LBB14_7: # %cond.load7 +; X86-KNL-NEXT: je .LBB14_4 +; X86-KNL-NEXT: .LBB14_8: # %cond.load7 ; X86-KNL-NEXT: vpextrd $3, %xmm1, %eax ; X86-KNL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0] ; X86-KNL-NEXT: vzeroupper @@ -786,20 +786,20 @@ define <4 x double> @test16(ptr %base, <4 x i32> %ind, <4 x i1> %mask, <4 x doub ; X64-KNL-NEXT: .LBB15_4: # %else2 ; X64-KNL-NEXT: testb $4, %al ; X64-KNL-NEXT: vextracti128 $1, %ymm0, %xmm0 -; X64-KNL-NEXT: jne .LBB15_5 -; X64-KNL-NEXT: # %bb.6: # %else5 -; X64-KNL-NEXT: testb $8, %al ; X64-KNL-NEXT: jne .LBB15_7 -; X64-KNL-NEXT: .LBB15_8: # %else8 +; X64-KNL-NEXT: # %bb.5: # %else5 +; X64-KNL-NEXT: testb $8, %al +; X64-KNL-NEXT: jne .LBB15_8 +; X64-KNL-NEXT: .LBB15_6: # %else8 ; X64-KNL-NEXT: vmovdqa %ymm2, %ymm0 ; X64-KNL-NEXT: retq -; X64-KNL-NEXT: .LBB15_5: # %cond.load4 +; X64-KNL-NEXT: .LBB15_7: # %cond.load4 ; X64-KNL-NEXT: vmovq %xmm0, %rcx ; X64-KNL-NEXT: vpbroadcastq (%rcx), %ymm1 ; X64-KNL-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm1[4,5],ymm2[6,7] ; X64-KNL-NEXT: testb $8, %al -; X64-KNL-NEXT: je .LBB15_8 -; X64-KNL-NEXT: .LBB15_7: # %cond.load7 +; X64-KNL-NEXT: je .LBB15_6 +; X64-KNL-NEXT: .LBB15_8: # %cond.load7 ; X64-KNL-NEXT: vpextrq $1, %xmm0, %rax ; X64-KNL-NEXT: vpbroadcastq (%rax), %ymm0 ; X64-KNL-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3,4,5],ymm0[6,7] @@ -815,38 +815,38 @@ define <4 x double> @test16(ptr %base, <4 x i32> %ind, <4 x i1> %mask, <4 x doub ; X86-KNL-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; X86-KNL-NEXT: kmovw %k0, %eax ; X86-KNL-NEXT: testb $1, %al -; X86-KNL-NEXT: jne .LBB15_1 -; X86-KNL-NEXT: # %bb.2: # %else +; X86-KNL-NEXT: jne .LBB15_5 +; X86-KNL-NEXT: # %bb.1: # %else ; X86-KNL-NEXT: testb $2, %al -; X86-KNL-NEXT: jne .LBB15_3 -; X86-KNL-NEXT: .LBB15_4: # %else2 +; X86-KNL-NEXT: jne .LBB15_6 +; X86-KNL-NEXT: .LBB15_2: # %else2 ; X86-KNL-NEXT: testb $4, %al -; X86-KNL-NEXT: jne .LBB15_5 -; X86-KNL-NEXT: .LBB15_6: # %else5 -; X86-KNL-NEXT: testb $8, %al ; X86-KNL-NEXT: jne .LBB15_7 -; X86-KNL-NEXT: .LBB15_8: # %else8 +; X86-KNL-NEXT: .LBB15_3: # %else5 +; X86-KNL-NEXT: testb $8, %al +; X86-KNL-NEXT: jne .LBB15_8 +; X86-KNL-NEXT: .LBB15_4: # %else8 ; X86-KNL-NEXT: vmovdqa %ymm2, %ymm0 ; X86-KNL-NEXT: retl -; X86-KNL-NEXT: .LBB15_1: # %cond.load +; X86-KNL-NEXT: .LBB15_5: # %cond.load ; X86-KNL-NEXT: vmovd %xmm0, %ecx ; X86-KNL-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero ; X86-KNL-NEXT: vpblendd {{.*#+}} ymm2 = ymm1[0,1],ymm2[2,3,4,5,6,7] ; X86-KNL-NEXT: testb $2, %al -; X86-KNL-NEXT: je .LBB15_4 -; X86-KNL-NEXT: .LBB15_3: # %cond.load1 +; X86-KNL-NEXT: je .LBB15_2 +; X86-KNL-NEXT: .LBB15_6: # %cond.load1 ; X86-KNL-NEXT: vpextrd $1, %xmm0, %ecx ; X86-KNL-NEXT: vmovhps {{.*#+}} xmm1 = xmm2[0,1],mem[0,1] ; X86-KNL-NEXT: vpblendd {{.*#+}} ymm2 = ymm1[0,1,2,3],ymm2[4,5,6,7] ; X86-KNL-NEXT: testb $4, %al -; X86-KNL-NEXT: je .LBB15_6 -; X86-KNL-NEXT: .LBB15_5: # %cond.load4 +; X86-KNL-NEXT: je .LBB15_3 +; X86-KNL-NEXT: .LBB15_7: # %cond.load4 ; X86-KNL-NEXT: vpextrd $2, %xmm0, %ecx ; X86-KNL-NEXT: vpbroadcastq (%ecx), %ymm1 ; X86-KNL-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm1[4,5],ymm2[6,7] ; X86-KNL-NEXT: testb $8, %al -; X86-KNL-NEXT: je .LBB15_8 -; X86-KNL-NEXT: .LBB15_7: # %cond.load7 +; X86-KNL-NEXT: je .LBB15_4 +; X86-KNL-NEXT: .LBB15_8: # %cond.load7 ; X86-KNL-NEXT: vpextrd $3, %xmm0, %eax ; X86-KNL-NEXT: vpbroadcastq (%eax), %ymm0 ; X86-KNL-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3,4,5],ymm0[6,7] @@ -887,20 +887,20 @@ define <2 x double> @test17(ptr %base, <2 x i32> %ind, <2 x i1> %mask, <2 x doub ; X64-KNL-NEXT: vpaddq %xmm0, %xmm1, %xmm0 ; X64-KNL-NEXT: kmovw %k0, %eax ; X64-KNL-NEXT: testb $1, %al -; X64-KNL-NEXT: jne .LBB16_1 -; X64-KNL-NEXT: # %bb.2: # %else -; X64-KNL-NEXT: testb $2, %al ; X64-KNL-NEXT: jne .LBB16_3 -; X64-KNL-NEXT: .LBB16_4: # %else2 +; X64-KNL-NEXT: # %bb.1: # %else +; X64-KNL-NEXT: testb $2, %al +; X64-KNL-NEXT: jne .LBB16_4 +; X64-KNL-NEXT: .LBB16_2: # %else2 ; X64-KNL-NEXT: vmovaps %xmm2, %xmm0 ; X64-KNL-NEXT: vzeroupper ; X64-KNL-NEXT: retq -; X64-KNL-NEXT: .LBB16_1: # %cond.load +; X64-KNL-NEXT: .LBB16_3: # %cond.load ; X64-KNL-NEXT: vmovq %xmm0, %rcx ; X64-KNL-NEXT: vmovlps {{.*#+}} xmm2 = mem[0,1],xmm2[2,3] ; X64-KNL-NEXT: testb $2, %al -; X64-KNL-NEXT: je .LBB16_4 -; X64-KNL-NEXT: .LBB16_3: # %cond.load1 +; X64-KNL-NEXT: je .LBB16_2 +; X64-KNL-NEXT: .LBB16_4: # %cond.load1 ; X64-KNL-NEXT: vpextrq $1, %xmm0, %rax ; X64-KNL-NEXT: vmovhps {{.*#+}} xmm2 = xmm2[0,1],mem[0,1] ; X64-KNL-NEXT: vmovaps %xmm2, %xmm0 @@ -916,20 +916,20 @@ define <2 x double> @test17(ptr %base, <2 x i32> %ind, <2 x i1> %mask, <2 x doub ; X86-KNL-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; X86-KNL-NEXT: kmovw %k0, %eax ; X86-KNL-NEXT: testb $1, %al -; X86-KNL-NEXT: jne .LBB16_1 -; X86-KNL-NEXT: # %bb.2: # %else -; X86-KNL-NEXT: testb $2, %al ; X86-KNL-NEXT: jne .LBB16_3 -; X86-KNL-NEXT: .LBB16_4: # %else2 +; X86-KNL-NEXT: # %bb.1: # %else +; X86-KNL-NEXT: testb $2, %al +; X86-KNL-NEXT: jne .LBB16_4 +; X86-KNL-NEXT: .LBB16_2: # %else2 ; X86-KNL-NEXT: vmovaps %xmm2, %xmm0 ; X86-KNL-NEXT: vzeroupper ; X86-KNL-NEXT: retl -; X86-KNL-NEXT: .LBB16_1: # %cond.load +; X86-KNL-NEXT: .LBB16_3: # %cond.load ; X86-KNL-NEXT: vmovd %xmm0, %ecx ; X86-KNL-NEXT: vmovlps {{.*#+}} xmm2 = mem[0,1],xmm2[2,3] ; X86-KNL-NEXT: testb $2, %al -; X86-KNL-NEXT: je .LBB16_4 -; X86-KNL-NEXT: .LBB16_3: # %cond.load1 +; X86-KNL-NEXT: je .LBB16_2 +; X86-KNL-NEXT: .LBB16_4: # %cond.load1 ; X86-KNL-NEXT: vpextrd $1, %xmm0, %eax ; X86-KNL-NEXT: vmovhps {{.*#+}} xmm2 = xmm2[0,1],mem[0,1] ; X86-KNL-NEXT: vmovaps %xmm2, %xmm0 @@ -946,19 +946,19 @@ define <2 x double> @test17(ptr %base, <2 x i32> %ind, <2 x i1> %mask, <2 x doub ; X64-SKX-NEXT: vpaddq %xmm0, %xmm1, %xmm0 ; X64-SKX-NEXT: kmovw %k0, %eax ; X64-SKX-NEXT: testb $1, %al -; X64-SKX-NEXT: jne .LBB16_1 -; X64-SKX-NEXT: # %bb.2: # %else -; X64-SKX-NEXT: testb $2, %al ; X64-SKX-NEXT: jne .LBB16_3 -; X64-SKX-NEXT: .LBB16_4: # %else2 +; X64-SKX-NEXT: # %bb.1: # %else +; X64-SKX-NEXT: testb $2, %al +; X64-SKX-NEXT: jne .LBB16_4 +; X64-SKX-NEXT: .LBB16_2: # %else2 ; X64-SKX-NEXT: vmovaps %xmm2, %xmm0 ; X64-SKX-NEXT: retq -; X64-SKX-NEXT: .LBB16_1: # %cond.load +; X64-SKX-NEXT: .LBB16_3: # %cond.load ; X64-SKX-NEXT: vmovq %xmm0, %rcx ; X64-SKX-NEXT: vmovlps {{.*#+}} xmm2 = mem[0,1],xmm2[2,3] ; X64-SKX-NEXT: testb $2, %al -; X64-SKX-NEXT: je .LBB16_4 -; X64-SKX-NEXT: .LBB16_3: # %cond.load1 +; X64-SKX-NEXT: je .LBB16_2 +; X64-SKX-NEXT: .LBB16_4: # %cond.load1 ; X64-SKX-NEXT: vpextrq $1, %xmm0, %rax ; X64-SKX-NEXT: vmovhps {{.*#+}} xmm2 = xmm2[0,1],mem[0,1] ; X64-SKX-NEXT: vmovaps %xmm2, %xmm0 @@ -971,19 +971,19 @@ define <2 x double> @test17(ptr %base, <2 x i32> %ind, <2 x i1> %mask, <2 x doub ; X86-SKX-NEXT: vpaddd {{[0-9]+}}(%esp){1to4}, %xmm0, %xmm0 ; X86-SKX-NEXT: vmovmskpd %xmm1, %eax ; X86-SKX-NEXT: testb $1, %al -; X86-SKX-NEXT: jne .LBB16_1 -; X86-SKX-NEXT: # %bb.2: # %else -; X86-SKX-NEXT: testb $2, %al ; X86-SKX-NEXT: jne .LBB16_3 -; X86-SKX-NEXT: .LBB16_4: # %else2 +; X86-SKX-NEXT: # %bb.1: # %else +; X86-SKX-NEXT: testb $2, %al +; X86-SKX-NEXT: jne .LBB16_4 +; X86-SKX-NEXT: .LBB16_2: # %else2 ; X86-SKX-NEXT: vmovaps %xmm2, %xmm0 ; X86-SKX-NEXT: retl -; X86-SKX-NEXT: .LBB16_1: # %cond.load +; X86-SKX-NEXT: .LBB16_3: # %cond.load ; X86-SKX-NEXT: vmovd %xmm0, %ecx ; X86-SKX-NEXT: vmovlps {{.*#+}} xmm2 = mem[0,1],xmm2[2,3] ; X86-SKX-NEXT: testb $2, %al -; X86-SKX-NEXT: je .LBB16_4 -; X86-SKX-NEXT: .LBB16_3: # %cond.load1 +; X86-SKX-NEXT: je .LBB16_2 +; X86-SKX-NEXT: .LBB16_4: # %cond.load1 ; X86-SKX-NEXT: vpextrd $1, %xmm0, %eax ; X86-SKX-NEXT: vmovhps {{.*#+}} xmm2 = xmm2[0,1],mem[0,1] ; X86-SKX-NEXT: vmovaps %xmm2, %xmm0 @@ -1020,19 +1020,19 @@ define void @test18(<4 x i32>%a1, <4 x ptr> %ptr, <4 x i1>%mask) { ; X64-KNL-NEXT: .LBB17_4: # %else2 ; X64-KNL-NEXT: testb $4, %al ; X64-KNL-NEXT: vextracti128 $1, %ymm1, %xmm1 -; X64-KNL-NEXT: jne .LBB17_5 -; X64-KNL-NEXT: # %bb.6: # %else4 -; X64-KNL-NEXT: testb $8, %al ; X64-KNL-NEXT: jne .LBB17_7 -; X64-KNL-NEXT: .LBB17_8: # %else6 +; X64-KNL-NEXT: # %bb.5: # %else4 +; X64-KNL-NEXT: testb $8, %al +; X64-KNL-NEXT: jne .LBB17_8 +; X64-KNL-NEXT: .LBB17_6: # %else6 ; X64-KNL-NEXT: vzeroupper ; X64-KNL-NEXT: retq -; X64-KNL-NEXT: .LBB17_5: # %cond.store3 +; X64-KNL-NEXT: .LBB17_7: # %cond.store3 ; X64-KNL-NEXT: vmovq %xmm1, %rcx ; X64-KNL-NEXT: vextractps $2, %xmm0, (%rcx) ; X64-KNL-NEXT: testb $8, %al -; X64-KNL-NEXT: je .LBB17_8 -; X64-KNL-NEXT: .LBB17_7: # %cond.store5 +; X64-KNL-NEXT: je .LBB17_6 +; X64-KNL-NEXT: .LBB17_8: # %cond.store5 ; X64-KNL-NEXT: vpextrq $1, %xmm1, %rax ; X64-KNL-NEXT: vextractps $3, %xmm0, (%rax) ; X64-KNL-NEXT: vzeroupper @@ -1044,35 +1044,35 @@ define void @test18(<4 x i32>%a1, <4 x ptr> %ptr, <4 x i1>%mask) { ; X86-KNL-NEXT: vptestmd %zmm2, %zmm2, %k0 ; X86-KNL-NEXT: kmovw %k0, %eax ; X86-KNL-NEXT: testb $1, %al -; X86-KNL-NEXT: jne .LBB17_1 -; X86-KNL-NEXT: # %bb.2: # %else +; X86-KNL-NEXT: jne .LBB17_5 +; X86-KNL-NEXT: # %bb.1: # %else ; X86-KNL-NEXT: testb $2, %al -; X86-KNL-NEXT: jne .LBB17_3 -; X86-KNL-NEXT: .LBB17_4: # %else2 +; X86-KNL-NEXT: jne .LBB17_6 +; X86-KNL-NEXT: .LBB17_2: # %else2 ; X86-KNL-NEXT: testb $4, %al -; X86-KNL-NEXT: jne .LBB17_5 -; X86-KNL-NEXT: .LBB17_6: # %else4 -; X86-KNL-NEXT: testb $8, %al ; X86-KNL-NEXT: jne .LBB17_7 -; X86-KNL-NEXT: .LBB17_8: # %else6 +; X86-KNL-NEXT: .LBB17_3: # %else4 +; X86-KNL-NEXT: testb $8, %al +; X86-KNL-NEXT: jne .LBB17_8 +; X86-KNL-NEXT: .LBB17_4: # %else6 ; X86-KNL-NEXT: vzeroupper ; X86-KNL-NEXT: retl -; X86-KNL-NEXT: .LBB17_1: # %cond.store +; X86-KNL-NEXT: .LBB17_5: # %cond.store ; X86-KNL-NEXT: vmovd %xmm1, %ecx ; X86-KNL-NEXT: vmovss %xmm0, (%ecx) ; X86-KNL-NEXT: testb $2, %al -; X86-KNL-NEXT: je .LBB17_4 -; X86-KNL-NEXT: .LBB17_3: # %cond.store1 +; X86-KNL-NEXT: je .LBB17_2 +; X86-KNL-NEXT: .LBB17_6: # %cond.store1 ; X86-KNL-NEXT: vpextrd $1, %xmm1, %ecx ; X86-KNL-NEXT: vextractps $1, %xmm0, (%ecx) ; X86-KNL-NEXT: testb $4, %al -; X86-KNL-NEXT: je .LBB17_6 -; X86-KNL-NEXT: .LBB17_5: # %cond.store3 +; X86-KNL-NEXT: je .LBB17_3 +; X86-KNL-NEXT: .LBB17_7: # %cond.store3 ; X86-KNL-NEXT: vpextrd $2, %xmm1, %ecx ; X86-KNL-NEXT: vextractps $2, %xmm0, (%ecx) ; X86-KNL-NEXT: testb $8, %al -; X86-KNL-NEXT: je .LBB17_8 -; X86-KNL-NEXT: .LBB17_7: # %cond.store5 +; X86-KNL-NEXT: je .LBB17_4 +; X86-KNL-NEXT: .LBB17_8: # %cond.store5 ; X86-KNL-NEXT: vpextrd $3, %xmm1, %eax ; X86-KNL-NEXT: vextractps $3, %xmm0, (%eax) ; X86-KNL-NEXT: vzeroupper @@ -1121,19 +1121,19 @@ define void @test19(<4 x double>%a1, ptr %ptr, <4 x i1>%mask, <4 x i64> %ind) { ; X64-KNL-NEXT: testb $4, %al ; X64-KNL-NEXT: vextractf128 $1, %ymm0, %xmm0 ; X64-KNL-NEXT: vextracti128 $1, %ymm1, %xmm1 -; X64-KNL-NEXT: jne .LBB18_5 -; X64-KNL-NEXT: # %bb.6: # %else4 -; X64-KNL-NEXT: testb $8, %al ; X64-KNL-NEXT: jne .LBB18_7 -; X64-KNL-NEXT: .LBB18_8: # %else6 +; X64-KNL-NEXT: # %bb.5: # %else4 +; X64-KNL-NEXT: testb $8, %al +; X64-KNL-NEXT: jne .LBB18_8 +; X64-KNL-NEXT: .LBB18_6: # %else6 ; X64-KNL-NEXT: vzeroupper ; X64-KNL-NEXT: retq -; X64-KNL-NEXT: .LBB18_5: # %cond.store3 +; X64-KNL-NEXT: .LBB18_7: # %cond.store3 ; X64-KNL-NEXT: vmovq %xmm1, %rcx ; X64-KNL-NEXT: vmovlps %xmm0, (%rcx) ; X64-KNL-NEXT: testb $8, %al -; X64-KNL-NEXT: je .LBB18_8 -; X64-KNL-NEXT: .LBB18_7: # %cond.store5 +; X64-KNL-NEXT: je .LBB18_6 +; X64-KNL-NEXT: .LBB18_8: # %cond.store5 ; X64-KNL-NEXT: vpextrq $1, %xmm1, %rax ; X64-KNL-NEXT: vmovhps %xmm0, (%rax) ; X64-KNL-NEXT: vzeroupper @@ -1163,19 +1163,19 @@ define void @test19(<4 x double>%a1, ptr %ptr, <4 x i1>%mask, <4 x i64> %ind) { ; X86-KNL-NEXT: .LBB18_4: # %else2 ; X86-KNL-NEXT: testb $4, %al ; X86-KNL-NEXT: vextractf128 $1, %ymm0, %xmm0 -; X86-KNL-NEXT: jne .LBB18_5 -; X86-KNL-NEXT: # %bb.6: # %else4 -; X86-KNL-NEXT: testb $8, %al ; X86-KNL-NEXT: jne .LBB18_7 -; X86-KNL-NEXT: .LBB18_8: # %else6 +; X86-KNL-NEXT: # %bb.5: # %else4 +; X86-KNL-NEXT: testb $8, %al +; X86-KNL-NEXT: jne .LBB18_8 +; X86-KNL-NEXT: .LBB18_6: # %else6 ; X86-KNL-NEXT: vzeroupper ; X86-KNL-NEXT: retl -; X86-KNL-NEXT: .LBB18_5: # %cond.store3 +; X86-KNL-NEXT: .LBB18_7: # %cond.store3 ; X86-KNL-NEXT: vpextrd $2, %xmm1, %ecx ; X86-KNL-NEXT: vmovlps %xmm0, (%ecx) ; X86-KNL-NEXT: testb $8, %al -; X86-KNL-NEXT: je .LBB18_8 -; X86-KNL-NEXT: .LBB18_7: # %cond.store5 +; X86-KNL-NEXT: je .LBB18_6 +; X86-KNL-NEXT: .LBB18_8: # %cond.store5 ; X86-KNL-NEXT: vpextrd $3, %xmm1, %eax ; X86-KNL-NEXT: vmovhps %xmm0, (%eax) ; X86-KNL-NEXT: vzeroupper @@ -1210,19 +1210,19 @@ define void @test20(<2 x float>%a1, <2 x ptr> %ptr, <2 x i1> %mask) { ; X64-KNL-NEXT: vptestmq %zmm2, %zmm2, %k0 ; X64-KNL-NEXT: kmovw %k0, %eax ; X64-KNL-NEXT: testb $1, %al -; X64-KNL-NEXT: jne .LBB19_1 -; X64-KNL-NEXT: # %bb.2: # %else -; X64-KNL-NEXT: testb $2, %al ; X64-KNL-NEXT: jne .LBB19_3 -; X64-KNL-NEXT: .LBB19_4: # %else2 +; X64-KNL-NEXT: # %bb.1: # %else +; X64-KNL-NEXT: testb $2, %al +; X64-KNL-NEXT: jne .LBB19_4 +; X64-KNL-NEXT: .LBB19_2: # %else2 ; X64-KNL-NEXT: vzeroupper ; X64-KNL-NEXT: retq -; X64-KNL-NEXT: .LBB19_1: # %cond.store +; X64-KNL-NEXT: .LBB19_3: # %cond.store ; X64-KNL-NEXT: vmovq %xmm1, %rcx ; X64-KNL-NEXT: vmovd %xmm0, (%rcx) ; X64-KNL-NEXT: testb $2, %al -; X64-KNL-NEXT: je .LBB19_4 -; X64-KNL-NEXT: .LBB19_3: # %cond.store1 +; X64-KNL-NEXT: je .LBB19_2 +; X64-KNL-NEXT: .LBB19_4: # %cond.store1 ; X64-KNL-NEXT: vpextrq $1, %xmm1, %rax ; X64-KNL-NEXT: vextractps $1, %xmm0, (%rax) ; X64-KNL-NEXT: vzeroupper @@ -1234,19 +1234,19 @@ define void @test20(<2 x float>%a1, <2 x ptr> %ptr, <2 x i1> %mask) { ; X86-KNL-NEXT: vptestmq %zmm2, %zmm2, %k0 ; X86-KNL-NEXT: kmovw %k0, %eax ; X86-KNL-NEXT: testb $1, %al -; X86-KNL-NEXT: jne .LBB19_1 -; X86-KNL-NEXT: # %bb.2: # %else -; X86-KNL-NEXT: testb $2, %al ; X86-KNL-NEXT: jne .LBB19_3 -; X86-KNL-NEXT: .LBB19_4: # %else2 +; X86-KNL-NEXT: # %bb.1: # %else +; X86-KNL-NEXT: testb $2, %al +; X86-KNL-NEXT: jne .LBB19_4 +; X86-KNL-NEXT: .LBB19_2: # %else2 ; X86-KNL-NEXT: vzeroupper ; X86-KNL-NEXT: retl -; X86-KNL-NEXT: .LBB19_1: # %cond.store +; X86-KNL-NEXT: .LBB19_3: # %cond.store ; X86-KNL-NEXT: vmovd %xmm1, %ecx ; X86-KNL-NEXT: vmovd %xmm0, (%ecx) ; X86-KNL-NEXT: testb $2, %al -; X86-KNL-NEXT: je .LBB19_4 -; X86-KNL-NEXT: .LBB19_3: # %cond.store1 +; X86-KNL-NEXT: je .LBB19_2 +; X86-KNL-NEXT: .LBB19_4: # %cond.store1 ; X86-KNL-NEXT: vpextrd $1, %xmm1, %eax ; X86-KNL-NEXT: vextractps $1, %xmm0, (%eax) ; X86-KNL-NEXT: vzeroupper @@ -1257,18 +1257,18 @@ define void @test20(<2 x float>%a1, <2 x ptr> %ptr, <2 x i1> %mask) { ; X64-SKX-NEXT: vpsllq $63, %xmm2, %xmm2 ; X64-SKX-NEXT: vmovmskpd %xmm2, %eax ; X64-SKX-NEXT: testb $1, %al -; X64-SKX-NEXT: jne .LBB19_1 -; X64-SKX-NEXT: # %bb.2: # %else -; X64-SKX-NEXT: testb $2, %al ; X64-SKX-NEXT: jne .LBB19_3 -; X64-SKX-NEXT: .LBB19_4: # %else2 +; X64-SKX-NEXT: # %bb.1: # %else +; X64-SKX-NEXT: testb $2, %al +; X64-SKX-NEXT: jne .LBB19_4 +; X64-SKX-NEXT: .LBB19_2: # %else2 ; X64-SKX-NEXT: retq -; X64-SKX-NEXT: .LBB19_1: # %cond.store +; X64-SKX-NEXT: .LBB19_3: # %cond.store ; X64-SKX-NEXT: vmovq %xmm1, %rcx ; X64-SKX-NEXT: vmovd %xmm0, (%rcx) ; X64-SKX-NEXT: testb $2, %al -; X64-SKX-NEXT: je .LBB19_4 -; X64-SKX-NEXT: .LBB19_3: # %cond.store1 +; X64-SKX-NEXT: je .LBB19_2 +; X64-SKX-NEXT: .LBB19_4: # %cond.store1 ; X64-SKX-NEXT: vpextrq $1, %xmm1, %rax ; X64-SKX-NEXT: vextractps $1, %xmm0, (%rax) ; X64-SKX-NEXT: retq @@ -1278,18 +1278,18 @@ define void @test20(<2 x float>%a1, <2 x ptr> %ptr, <2 x i1> %mask) { ; X86-SKX-NEXT: vpsllq $63, %xmm2, %xmm2 ; X86-SKX-NEXT: vmovmskpd %xmm2, %eax ; X86-SKX-NEXT: testb $1, %al -; X86-SKX-NEXT: jne .LBB19_1 -; X86-SKX-NEXT: # %bb.2: # %else -; X86-SKX-NEXT: testb $2, %al ; X86-SKX-NEXT: jne .LBB19_3 -; X86-SKX-NEXT: .LBB19_4: # %else2 +; X86-SKX-NEXT: # %bb.1: # %else +; X86-SKX-NEXT: testb $2, %al +; X86-SKX-NEXT: jne .LBB19_4 +; X86-SKX-NEXT: .LBB19_2: # %else2 ; X86-SKX-NEXT: retl -; X86-SKX-NEXT: .LBB19_1: # %cond.store +; X86-SKX-NEXT: .LBB19_3: # %cond.store ; X86-SKX-NEXT: vmovd %xmm1, %ecx ; X86-SKX-NEXT: vmovd %xmm0, (%ecx) ; X86-SKX-NEXT: testb $2, %al -; X86-SKX-NEXT: je .LBB19_4 -; X86-SKX-NEXT: .LBB19_3: # %cond.store1 +; X86-SKX-NEXT: je .LBB19_2 +; X86-SKX-NEXT: .LBB19_4: # %cond.store1 ; X86-SKX-NEXT: vpextrd $1, %xmm1, %eax ; X86-SKX-NEXT: vextractps $1, %xmm0, (%eax) ; X86-SKX-NEXT: retl @@ -1305,19 +1305,19 @@ define void @test21(<2 x i32>%a1, <2 x ptr> %ptr, <2 x i1>%mask) { ; X64-KNL-NEXT: vptestmq %zmm2, %zmm2, %k0 ; X64-KNL-NEXT: kmovw %k0, %eax ; X64-KNL-NEXT: testb $1, %al -; X64-KNL-NEXT: jne .LBB20_1 -; X64-KNL-NEXT: # %bb.2: # %else -; X64-KNL-NEXT: testb $2, %al ; X64-KNL-NEXT: jne .LBB20_3 -; X64-KNL-NEXT: .LBB20_4: # %else2 +; X64-KNL-NEXT: # %bb.1: # %else +; X64-KNL-NEXT: testb $2, %al +; X64-KNL-NEXT: jne .LBB20_4 +; X64-KNL-NEXT: .LBB20_2: # %else2 ; X64-KNL-NEXT: vzeroupper ; X64-KNL-NEXT: retq -; X64-KNL-NEXT: .LBB20_1: # %cond.store +; X64-KNL-NEXT: .LBB20_3: # %cond.store ; X64-KNL-NEXT: vmovq %xmm1, %rcx ; X64-KNL-NEXT: vmovss %xmm0, (%rcx) ; X64-KNL-NEXT: testb $2, %al -; X64-KNL-NEXT: je .LBB20_4 -; X64-KNL-NEXT: .LBB20_3: # %cond.store1 +; X64-KNL-NEXT: je .LBB20_2 +; X64-KNL-NEXT: .LBB20_4: # %cond.store1 ; X64-KNL-NEXT: vpextrq $1, %xmm1, %rax ; X64-KNL-NEXT: vextractps $1, %xmm0, (%rax) ; X64-KNL-NEXT: vzeroupper @@ -1329,19 +1329,19 @@ define void @test21(<2 x i32>%a1, <2 x ptr> %ptr, <2 x i1>%mask) { ; X86-KNL-NEXT: vptestmq %zmm2, %zmm2, %k0 ; X86-KNL-NEXT: kmovw %k0, %eax ; X86-KNL-NEXT: testb $1, %al -; X86-KNL-NEXT: jne .LBB20_1 -; X86-KNL-NEXT: # %bb.2: # %else -; X86-KNL-NEXT: testb $2, %al ; X86-KNL-NEXT: jne .LBB20_3 -; X86-KNL-NEXT: .LBB20_4: # %else2 +; X86-KNL-NEXT: # %bb.1: # %else +; X86-KNL-NEXT: testb $2, %al +; X86-KNL-NEXT: jne .LBB20_4 +; X86-KNL-NEXT: .LBB20_2: # %else2 ; X86-KNL-NEXT: vzeroupper ; X86-KNL-NEXT: retl -; X86-KNL-NEXT: .LBB20_1: # %cond.store +; X86-KNL-NEXT: .LBB20_3: # %cond.store ; X86-KNL-NEXT: vmovd %xmm1, %ecx ; X86-KNL-NEXT: vmovss %xmm0, (%ecx) ; X86-KNL-NEXT: testb $2, %al -; X86-KNL-NEXT: je .LBB20_4 -; X86-KNL-NEXT: .LBB20_3: # %cond.store1 +; X86-KNL-NEXT: je .LBB20_2 +; X86-KNL-NEXT: .LBB20_4: # %cond.store1 ; X86-KNL-NEXT: vpextrd $1, %xmm1, %eax ; X86-KNL-NEXT: vextractps $1, %xmm0, (%eax) ; X86-KNL-NEXT: vzeroupper @@ -1352,18 +1352,18 @@ define void @test21(<2 x i32>%a1, <2 x ptr> %ptr, <2 x i1>%mask) { ; X64-SKX-NEXT: vpsllq $63, %xmm2, %xmm2 ; X64-SKX-NEXT: vmovmskpd %xmm2, %eax ; X64-SKX-NEXT: testb $1, %al -; X64-SKX-NEXT: jne .LBB20_1 -; X64-SKX-NEXT: # %bb.2: # %else -; X64-SKX-NEXT: testb $2, %al ; X64-SKX-NEXT: jne .LBB20_3 -; X64-SKX-NEXT: .LBB20_4: # %else2 +; X64-SKX-NEXT: # %bb.1: # %else +; X64-SKX-NEXT: testb $2, %al +; X64-SKX-NEXT: jne .LBB20_4 +; X64-SKX-NEXT: .LBB20_2: # %else2 ; X64-SKX-NEXT: retq -; X64-SKX-NEXT: .LBB20_1: # %cond.store +; X64-SKX-NEXT: .LBB20_3: # %cond.store ; X64-SKX-NEXT: vmovq %xmm1, %rcx ; X64-SKX-NEXT: vmovss %xmm0, (%rcx) ; X64-SKX-NEXT: testb $2, %al -; X64-SKX-NEXT: je .LBB20_4 -; X64-SKX-NEXT: .LBB20_3: # %cond.store1 +; X64-SKX-NEXT: je .LBB20_2 +; X64-SKX-NEXT: .LBB20_4: # %cond.store1 ; X64-SKX-NEXT: vpextrq $1, %xmm1, %rax ; X64-SKX-NEXT: vextractps $1, %xmm0, (%rax) ; X64-SKX-NEXT: retq @@ -1373,18 +1373,18 @@ define void @test21(<2 x i32>%a1, <2 x ptr> %ptr, <2 x i1>%mask) { ; X86-SKX-NEXT: vpsllq $63, %xmm2, %xmm2 ; X86-SKX-NEXT: vmovmskpd %xmm2, %eax ; X86-SKX-NEXT: testb $1, %al -; X86-SKX-NEXT: jne .LBB20_1 -; X86-SKX-NEXT: # %bb.2: # %else -; X86-SKX-NEXT: testb $2, %al ; X86-SKX-NEXT: jne .LBB20_3 -; X86-SKX-NEXT: .LBB20_4: # %else2 +; X86-SKX-NEXT: # %bb.1: # %else +; X86-SKX-NEXT: testb $2, %al +; X86-SKX-NEXT: jne .LBB20_4 +; X86-SKX-NEXT: .LBB20_2: # %else2 ; X86-SKX-NEXT: retl -; X86-SKX-NEXT: .LBB20_1: # %cond.store +; X86-SKX-NEXT: .LBB20_3: # %cond.store ; X86-SKX-NEXT: vmovd %xmm1, %ecx ; X86-SKX-NEXT: vmovss %xmm0, (%ecx) ; X86-SKX-NEXT: testb $2, %al -; X86-SKX-NEXT: je .LBB20_4 -; X86-SKX-NEXT: .LBB20_3: # %cond.store1 +; X86-SKX-NEXT: je .LBB20_2 +; X86-SKX-NEXT: .LBB20_4: # %cond.store1 ; X86-SKX-NEXT: vpextrd $1, %xmm1, %eax ; X86-SKX-NEXT: vextractps $1, %xmm0, (%eax) ; X86-SKX-NEXT: retl @@ -1407,21 +1407,21 @@ define <2 x float> @test22(ptr %base, <2 x i32> %ind, <2 x i1> %mask, <2 x float ; X64-KNL-NEXT: vpaddq %xmm0, %xmm1, %xmm0 ; X64-KNL-NEXT: kmovw %k0, %eax ; X64-KNL-NEXT: testb $1, %al -; X64-KNL-NEXT: jne .LBB21_1 -; X64-KNL-NEXT: # %bb.2: # %else -; X64-KNL-NEXT: testb $2, %al ; X64-KNL-NEXT: jne .LBB21_3 -; X64-KNL-NEXT: .LBB21_4: # %else2 +; X64-KNL-NEXT: # %bb.1: # %else +; X64-KNL-NEXT: testb $2, %al +; X64-KNL-NEXT: jne .LBB21_4 +; X64-KNL-NEXT: .LBB21_2: # %else2 ; X64-KNL-NEXT: vmovdqa %xmm2, %xmm0 ; X64-KNL-NEXT: vzeroupper ; X64-KNL-NEXT: retq -; X64-KNL-NEXT: .LBB21_1: # %cond.load +; X64-KNL-NEXT: .LBB21_3: # %cond.load ; X64-KNL-NEXT: vmovq %xmm0, %rcx ; X64-KNL-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero ; X64-KNL-NEXT: vpblendd {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3] ; X64-KNL-NEXT: testb $2, %al -; X64-KNL-NEXT: je .LBB21_4 -; X64-KNL-NEXT: .LBB21_3: # %cond.load1 +; X64-KNL-NEXT: je .LBB21_2 +; X64-KNL-NEXT: .LBB21_4: # %cond.load1 ; X64-KNL-NEXT: vpextrq $1, %xmm0, %rax ; X64-KNL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],mem[0],xmm2[2,3] ; X64-KNL-NEXT: vmovaps %xmm2, %xmm0 @@ -1437,21 +1437,21 @@ define <2 x float> @test22(ptr %base, <2 x i32> %ind, <2 x i1> %mask, <2 x float ; X86-KNL-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; X86-KNL-NEXT: kmovw %k0, %eax ; X86-KNL-NEXT: testb $1, %al -; X86-KNL-NEXT: jne .LBB21_1 -; X86-KNL-NEXT: # %bb.2: # %else -; X86-KNL-NEXT: testb $2, %al ; X86-KNL-NEXT: jne .LBB21_3 -; X86-KNL-NEXT: .LBB21_4: # %else2 +; X86-KNL-NEXT: # %bb.1: # %else +; X86-KNL-NEXT: testb $2, %al +; X86-KNL-NEXT: jne .LBB21_4 +; X86-KNL-NEXT: .LBB21_2: # %else2 ; X86-KNL-NEXT: vmovdqa %xmm2, %xmm0 ; X86-KNL-NEXT: vzeroupper ; X86-KNL-NEXT: retl -; X86-KNL-NEXT: .LBB21_1: # %cond.load +; X86-KNL-NEXT: .LBB21_3: # %cond.load ; X86-KNL-NEXT: vmovd %xmm0, %ecx ; X86-KNL-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero ; X86-KNL-NEXT: vpblendd {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3] ; X86-KNL-NEXT: testb $2, %al -; X86-KNL-NEXT: je .LBB21_4 -; X86-KNL-NEXT: .LBB21_3: # %cond.load1 +; X86-KNL-NEXT: je .LBB21_2 +; X86-KNL-NEXT: .LBB21_4: # %cond.load1 ; X86-KNL-NEXT: vpextrd $1, %xmm0, %eax ; X86-KNL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],mem[0],xmm2[2,3] ; X86-KNL-NEXT: vmovaps %xmm2, %xmm0 @@ -1468,20 +1468,20 @@ define <2 x float> @test22(ptr %base, <2 x i32> %ind, <2 x i1> %mask, <2 x float ; X64-SKX-NEXT: vpaddq %xmm0, %xmm1, %xmm0 ; X64-SKX-NEXT: kmovw %k0, %eax ; X64-SKX-NEXT: testb $1, %al -; X64-SKX-NEXT: jne .LBB21_1 -; X64-SKX-NEXT: # %bb.2: # %else -; X64-SKX-NEXT: testb $2, %al ; X64-SKX-NEXT: jne .LBB21_3 -; X64-SKX-NEXT: .LBB21_4: # %else2 +; X64-SKX-NEXT: # %bb.1: # %else +; X64-SKX-NEXT: testb $2, %al +; X64-SKX-NEXT: jne .LBB21_4 +; X64-SKX-NEXT: .LBB21_2: # %else2 ; X64-SKX-NEXT: vmovdqa %xmm2, %xmm0 ; X64-SKX-NEXT: retq -; X64-SKX-NEXT: .LBB21_1: # %cond.load +; X64-SKX-NEXT: .LBB21_3: # %cond.load ; X64-SKX-NEXT: vmovq %xmm0, %rcx ; X64-SKX-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero ; X64-SKX-NEXT: vpblendd {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3] ; X64-SKX-NEXT: testb $2, %al -; X64-SKX-NEXT: je .LBB21_4 -; X64-SKX-NEXT: .LBB21_3: # %cond.load1 +; X64-SKX-NEXT: je .LBB21_2 +; X64-SKX-NEXT: .LBB21_4: # %cond.load1 ; X64-SKX-NEXT: vpextrq $1, %xmm0, %rax ; X64-SKX-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],mem[0],xmm2[2,3] ; X64-SKX-NEXT: vmovaps %xmm2, %xmm0 @@ -1494,20 +1494,20 @@ define <2 x float> @test22(ptr %base, <2 x i32> %ind, <2 x i1> %mask, <2 x float ; X86-SKX-NEXT: vpaddd {{[0-9]+}}(%esp){1to4}, %xmm0, %xmm0 ; X86-SKX-NEXT: vmovmskpd %xmm1, %eax ; X86-SKX-NEXT: testb $1, %al -; X86-SKX-NEXT: jne .LBB21_1 -; X86-SKX-NEXT: # %bb.2: # %else -; X86-SKX-NEXT: testb $2, %al ; X86-SKX-NEXT: jne .LBB21_3 -; X86-SKX-NEXT: .LBB21_4: # %else2 +; X86-SKX-NEXT: # %bb.1: # %else +; X86-SKX-NEXT: testb $2, %al +; X86-SKX-NEXT: jne .LBB21_4 +; X86-SKX-NEXT: .LBB21_2: # %else2 ; X86-SKX-NEXT: vmovdqa %xmm2, %xmm0 ; X86-SKX-NEXT: retl -; X86-SKX-NEXT: .LBB21_1: # %cond.load +; X86-SKX-NEXT: .LBB21_3: # %cond.load ; X86-SKX-NEXT: vmovd %xmm0, %ecx ; X86-SKX-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero ; X86-SKX-NEXT: vpblendd {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3] ; X86-SKX-NEXT: testb $2, %al -; X86-SKX-NEXT: je .LBB21_4 -; X86-SKX-NEXT: .LBB21_3: # %cond.load1 +; X86-SKX-NEXT: je .LBB21_2 +; X86-SKX-NEXT: .LBB21_4: # %cond.load1 ; X86-SKX-NEXT: vpextrd $1, %xmm0, %eax ; X86-SKX-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],mem[0],xmm2[2,3] ; X86-SKX-NEXT: vmovaps %xmm2, %xmm0 @@ -1529,21 +1529,21 @@ define <2 x float> @test22a(ptr %base, <2 x i64> %ind, <2 x i1> %mask, <2 x floa ; X64-KNL-NEXT: vpaddq %xmm0, %xmm1, %xmm0 ; X64-KNL-NEXT: kmovw %k0, %eax ; X64-KNL-NEXT: testb $1, %al -; X64-KNL-NEXT: jne .LBB22_1 -; X64-KNL-NEXT: # %bb.2: # %else -; X64-KNL-NEXT: testb $2, %al ; X64-KNL-NEXT: jne .LBB22_3 -; X64-KNL-NEXT: .LBB22_4: # %else2 +; X64-KNL-NEXT: # %bb.1: # %else +; X64-KNL-NEXT: testb $2, %al +; X64-KNL-NEXT: jne .LBB22_4 +; X64-KNL-NEXT: .LBB22_2: # %else2 ; X64-KNL-NEXT: vmovdqa %xmm2, %xmm0 ; X64-KNL-NEXT: vzeroupper ; X64-KNL-NEXT: retq -; X64-KNL-NEXT: .LBB22_1: # %cond.load +; X64-KNL-NEXT: .LBB22_3: # %cond.load ; X64-KNL-NEXT: vmovq %xmm0, %rcx ; X64-KNL-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero ; X64-KNL-NEXT: vpblendd {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3] ; X64-KNL-NEXT: testb $2, %al -; X64-KNL-NEXT: je .LBB22_4 -; X64-KNL-NEXT: .LBB22_3: # %cond.load1 +; X64-KNL-NEXT: je .LBB22_2 +; X64-KNL-NEXT: .LBB22_4: # %cond.load1 ; X64-KNL-NEXT: vpextrq $1, %xmm0, %rax ; X64-KNL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],mem[0],xmm2[2,3] ; X64-KNL-NEXT: vmovaps %xmm2, %xmm0 @@ -1560,21 +1560,21 @@ define <2 x float> @test22a(ptr %base, <2 x i64> %ind, <2 x i1> %mask, <2 x floa ; X86-KNL-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; X86-KNL-NEXT: kmovw %k0, %eax ; X86-KNL-NEXT: testb $1, %al -; X86-KNL-NEXT: jne .LBB22_1 -; X86-KNL-NEXT: # %bb.2: # %else -; X86-KNL-NEXT: testb $2, %al ; X86-KNL-NEXT: jne .LBB22_3 -; X86-KNL-NEXT: .LBB22_4: # %else2 +; X86-KNL-NEXT: # %bb.1: # %else +; X86-KNL-NEXT: testb $2, %al +; X86-KNL-NEXT: jne .LBB22_4 +; X86-KNL-NEXT: .LBB22_2: # %else2 ; X86-KNL-NEXT: vmovdqa %xmm2, %xmm0 ; X86-KNL-NEXT: vzeroupper ; X86-KNL-NEXT: retl -; X86-KNL-NEXT: .LBB22_1: # %cond.load +; X86-KNL-NEXT: .LBB22_3: # %cond.load ; X86-KNL-NEXT: vmovd %xmm0, %ecx ; X86-KNL-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero ; X86-KNL-NEXT: vpblendd {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3] ; X86-KNL-NEXT: testb $2, %al -; X86-KNL-NEXT: je .LBB22_4 -; X86-KNL-NEXT: .LBB22_3: # %cond.load1 +; X86-KNL-NEXT: je .LBB22_2 +; X86-KNL-NEXT: .LBB22_4: # %cond.load1 ; X86-KNL-NEXT: vpextrd $1, %xmm0, %eax ; X86-KNL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],mem[0],xmm2[2,3] ; X86-KNL-NEXT: vmovaps %xmm2, %xmm0 @@ -1590,20 +1590,20 @@ define <2 x float> @test22a(ptr %base, <2 x i64> %ind, <2 x i1> %mask, <2 x floa ; X64-SKX-NEXT: vpaddq %xmm0, %xmm1, %xmm0 ; X64-SKX-NEXT: kmovw %k0, %eax ; X64-SKX-NEXT: testb $1, %al -; X64-SKX-NEXT: jne .LBB22_1 -; X64-SKX-NEXT: # %bb.2: # %else -; X64-SKX-NEXT: testb $2, %al ; X64-SKX-NEXT: jne .LBB22_3 -; X64-SKX-NEXT: .LBB22_4: # %else2 +; X64-SKX-NEXT: # %bb.1: # %else +; X64-SKX-NEXT: testb $2, %al +; X64-SKX-NEXT: jne .LBB22_4 +; X64-SKX-NEXT: .LBB22_2: # %else2 ; X64-SKX-NEXT: vmovdqa %xmm2, %xmm0 ; X64-SKX-NEXT: retq -; X64-SKX-NEXT: .LBB22_1: # %cond.load +; X64-SKX-NEXT: .LBB22_3: # %cond.load ; X64-SKX-NEXT: vmovq %xmm0, %rcx ; X64-SKX-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero ; X64-SKX-NEXT: vpblendd {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3] ; X64-SKX-NEXT: testb $2, %al -; X64-SKX-NEXT: je .LBB22_4 -; X64-SKX-NEXT: .LBB22_3: # %cond.load1 +; X64-SKX-NEXT: je .LBB22_2 +; X64-SKX-NEXT: .LBB22_4: # %cond.load1 ; X64-SKX-NEXT: vpextrq $1, %xmm0, %rax ; X64-SKX-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],mem[0],xmm2[2,3] ; X64-SKX-NEXT: vmovaps %xmm2, %xmm0 @@ -1617,20 +1617,20 @@ define <2 x float> @test22a(ptr %base, <2 x i64> %ind, <2 x i1> %mask, <2 x floa ; X86-SKX-NEXT: vpaddd {{[0-9]+}}(%esp){1to4}, %xmm0, %xmm0 ; X86-SKX-NEXT: vmovmskpd %xmm1, %eax ; X86-SKX-NEXT: testb $1, %al -; X86-SKX-NEXT: jne .LBB22_1 -; X86-SKX-NEXT: # %bb.2: # %else -; X86-SKX-NEXT: testb $2, %al ; X86-SKX-NEXT: jne .LBB22_3 -; X86-SKX-NEXT: .LBB22_4: # %else2 +; X86-SKX-NEXT: # %bb.1: # %else +; X86-SKX-NEXT: testb $2, %al +; X86-SKX-NEXT: jne .LBB22_4 +; X86-SKX-NEXT: .LBB22_2: # %else2 ; X86-SKX-NEXT: vmovdqa %xmm2, %xmm0 ; X86-SKX-NEXT: retl -; X86-SKX-NEXT: .LBB22_1: # %cond.load +; X86-SKX-NEXT: .LBB22_3: # %cond.load ; X86-SKX-NEXT: vmovd %xmm0, %ecx ; X86-SKX-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero ; X86-SKX-NEXT: vpblendd {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3] ; X86-SKX-NEXT: testb $2, %al -; X86-SKX-NEXT: je .LBB22_4 -; X86-SKX-NEXT: .LBB22_3: # %cond.load1 +; X86-SKX-NEXT: je .LBB22_2 +; X86-SKX-NEXT: .LBB22_4: # %cond.load1 ; X86-SKX-NEXT: vpextrd $1, %xmm0, %eax ; X86-SKX-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],mem[0],xmm2[2,3] ; X86-SKX-NEXT: vmovaps %xmm2, %xmm0 @@ -1655,20 +1655,20 @@ define <2 x i32> @test23(ptr %base, <2 x i32> %ind, <2 x i1> %mask, <2 x i32> %s ; X64-KNL-NEXT: vpaddq %xmm0, %xmm1, %xmm0 ; X64-KNL-NEXT: kmovw %k0, %eax ; X64-KNL-NEXT: testb $1, %al -; X64-KNL-NEXT: jne .LBB23_1 -; X64-KNL-NEXT: # %bb.2: # %else -; X64-KNL-NEXT: testb $2, %al ; X64-KNL-NEXT: jne .LBB23_3 -; X64-KNL-NEXT: .LBB23_4: # %else2 +; X64-KNL-NEXT: # %bb.1: # %else +; X64-KNL-NEXT: testb $2, %al +; X64-KNL-NEXT: jne .LBB23_4 +; X64-KNL-NEXT: .LBB23_2: # %else2 ; X64-KNL-NEXT: vmovdqa %xmm2, %xmm0 ; X64-KNL-NEXT: vzeroupper ; X64-KNL-NEXT: retq -; X64-KNL-NEXT: .LBB23_1: # %cond.load +; X64-KNL-NEXT: .LBB23_3: # %cond.load ; X64-KNL-NEXT: vmovq %xmm0, %rcx ; X64-KNL-NEXT: vpinsrd $0, (%rcx), %xmm2, %xmm2 ; X64-KNL-NEXT: testb $2, %al -; X64-KNL-NEXT: je .LBB23_4 -; X64-KNL-NEXT: .LBB23_3: # %cond.load1 +; X64-KNL-NEXT: je .LBB23_2 +; X64-KNL-NEXT: .LBB23_4: # %cond.load1 ; X64-KNL-NEXT: vpextrq $1, %xmm0, %rax ; X64-KNL-NEXT: vpinsrd $1, (%rax), %xmm2, %xmm2 ; X64-KNL-NEXT: vmovdqa %xmm2, %xmm0 @@ -1684,20 +1684,20 @@ define <2 x i32> @test23(ptr %base, <2 x i32> %ind, <2 x i1> %mask, <2 x i32> %s ; X86-KNL-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; X86-KNL-NEXT: kmovw %k0, %eax ; X86-KNL-NEXT: testb $1, %al -; X86-KNL-NEXT: jne .LBB23_1 -; X86-KNL-NEXT: # %bb.2: # %else -; X86-KNL-NEXT: testb $2, %al ; X86-KNL-NEXT: jne .LBB23_3 -; X86-KNL-NEXT: .LBB23_4: # %else2 +; X86-KNL-NEXT: # %bb.1: # %else +; X86-KNL-NEXT: testb $2, %al +; X86-KNL-NEXT: jne .LBB23_4 +; X86-KNL-NEXT: .LBB23_2: # %else2 ; X86-KNL-NEXT: vmovdqa %xmm2, %xmm0 ; X86-KNL-NEXT: vzeroupper ; X86-KNL-NEXT: retl -; X86-KNL-NEXT: .LBB23_1: # %cond.load +; X86-KNL-NEXT: .LBB23_3: # %cond.load ; X86-KNL-NEXT: vmovd %xmm0, %ecx ; X86-KNL-NEXT: vpinsrd $0, (%ecx), %xmm2, %xmm2 ; X86-KNL-NEXT: testb $2, %al -; X86-KNL-NEXT: je .LBB23_4 -; X86-KNL-NEXT: .LBB23_3: # %cond.load1 +; X86-KNL-NEXT: je .LBB23_2 +; X86-KNL-NEXT: .LBB23_4: # %cond.load1 ; X86-KNL-NEXT: vpextrd $1, %xmm0, %eax ; X86-KNL-NEXT: vpinsrd $1, (%eax), %xmm2, %xmm2 ; X86-KNL-NEXT: vmovdqa %xmm2, %xmm0 @@ -1714,19 +1714,19 @@ define <2 x i32> @test23(ptr %base, <2 x i32> %ind, <2 x i1> %mask, <2 x i32> %s ; X64-SKX-NEXT: vpaddq %xmm0, %xmm1, %xmm0 ; X64-SKX-NEXT: kmovw %k0, %eax ; X64-SKX-NEXT: testb $1, %al -; X64-SKX-NEXT: jne .LBB23_1 -; X64-SKX-NEXT: # %bb.2: # %else -; X64-SKX-NEXT: testb $2, %al ; X64-SKX-NEXT: jne .LBB23_3 -; X64-SKX-NEXT: .LBB23_4: # %else2 +; X64-SKX-NEXT: # %bb.1: # %else +; X64-SKX-NEXT: testb $2, %al +; X64-SKX-NEXT: jne .LBB23_4 +; X64-SKX-NEXT: .LBB23_2: # %else2 ; X64-SKX-NEXT: vmovdqa %xmm2, %xmm0 ; X64-SKX-NEXT: retq -; X64-SKX-NEXT: .LBB23_1: # %cond.load +; X64-SKX-NEXT: .LBB23_3: # %cond.load ; X64-SKX-NEXT: vmovq %xmm0, %rcx ; X64-SKX-NEXT: vpinsrd $0, (%rcx), %xmm2, %xmm2 ; X64-SKX-NEXT: testb $2, %al -; X64-SKX-NEXT: je .LBB23_4 -; X64-SKX-NEXT: .LBB23_3: # %cond.load1 +; X64-SKX-NEXT: je .LBB23_2 +; X64-SKX-NEXT: .LBB23_4: # %cond.load1 ; X64-SKX-NEXT: vpextrq $1, %xmm0, %rax ; X64-SKX-NEXT: vpinsrd $1, (%rax), %xmm2, %xmm2 ; X64-SKX-NEXT: vmovdqa %xmm2, %xmm0 @@ -1739,19 +1739,19 @@ define <2 x i32> @test23(ptr %base, <2 x i32> %ind, <2 x i1> %mask, <2 x i32> %s ; X86-SKX-NEXT: vpaddd {{[0-9]+}}(%esp){1to4}, %xmm0, %xmm0 ; X86-SKX-NEXT: vmovmskpd %xmm1, %eax ; X86-SKX-NEXT: testb $1, %al -; X86-SKX-NEXT: jne .LBB23_1 -; X86-SKX-NEXT: # %bb.2: # %else -; X86-SKX-NEXT: testb $2, %al ; X86-SKX-NEXT: jne .LBB23_3 -; X86-SKX-NEXT: .LBB23_4: # %else2 +; X86-SKX-NEXT: # %bb.1: # %else +; X86-SKX-NEXT: testb $2, %al +; X86-SKX-NEXT: jne .LBB23_4 +; X86-SKX-NEXT: .LBB23_2: # %else2 ; X86-SKX-NEXT: vmovdqa %xmm2, %xmm0 ; X86-SKX-NEXT: retl -; X86-SKX-NEXT: .LBB23_1: # %cond.load +; X86-SKX-NEXT: .LBB23_3: # %cond.load ; X86-SKX-NEXT: vmovd %xmm0, %ecx ; X86-SKX-NEXT: vpinsrd $0, (%ecx), %xmm2, %xmm2 ; X86-SKX-NEXT: testb $2, %al -; X86-SKX-NEXT: je .LBB23_4 -; X86-SKX-NEXT: .LBB23_3: # %cond.load1 +; X86-SKX-NEXT: je .LBB23_2 +; X86-SKX-NEXT: .LBB23_4: # %cond.load1 ; X86-SKX-NEXT: vpextrd $1, %xmm0, %eax ; X86-SKX-NEXT: vpinsrd $1, (%eax), %xmm2, %xmm2 ; X86-SKX-NEXT: vmovdqa %xmm2, %xmm0 @@ -1773,20 +1773,20 @@ define <2 x i32> @test23b(ptr %base, <2 x i64> %ind, <2 x i1> %mask, <2 x i32> % ; X64-KNL-NEXT: vpaddq %xmm0, %xmm1, %xmm0 ; X64-KNL-NEXT: kmovw %k0, %eax ; X64-KNL-NEXT: testb $1, %al -; X64-KNL-NEXT: jne .LBB24_1 -; X64-KNL-NEXT: # %bb.2: # %else -; X64-KNL-NEXT: testb $2, %al ; X64-KNL-NEXT: jne .LBB24_3 -; X64-KNL-NEXT: .LBB24_4: # %else2 +; X64-KNL-NEXT: # %bb.1: # %else +; X64-KNL-NEXT: testb $2, %al +; X64-KNL-NEXT: jne .LBB24_4 +; X64-KNL-NEXT: .LBB24_2: # %else2 ; X64-KNL-NEXT: vmovdqa %xmm2, %xmm0 ; X64-KNL-NEXT: vzeroupper ; X64-KNL-NEXT: retq -; X64-KNL-NEXT: .LBB24_1: # %cond.load +; X64-KNL-NEXT: .LBB24_3: # %cond.load ; X64-KNL-NEXT: vmovq %xmm0, %rcx ; X64-KNL-NEXT: vpinsrd $0, (%rcx), %xmm2, %xmm2 ; X64-KNL-NEXT: testb $2, %al -; X64-KNL-NEXT: je .LBB24_4 -; X64-KNL-NEXT: .LBB24_3: # %cond.load1 +; X64-KNL-NEXT: je .LBB24_2 +; X64-KNL-NEXT: .LBB24_4: # %cond.load1 ; X64-KNL-NEXT: vpextrq $1, %xmm0, %rax ; X64-KNL-NEXT: vpinsrd $1, (%rax), %xmm2, %xmm2 ; X64-KNL-NEXT: vmovdqa %xmm2, %xmm0 @@ -1803,20 +1803,20 @@ define <2 x i32> @test23b(ptr %base, <2 x i64> %ind, <2 x i1> %mask, <2 x i32> % ; X86-KNL-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; X86-KNL-NEXT: kmovw %k0, %eax ; X86-KNL-NEXT: testb $1, %al -; X86-KNL-NEXT: jne .LBB24_1 -; X86-KNL-NEXT: # %bb.2: # %else -; X86-KNL-NEXT: testb $2, %al ; X86-KNL-NEXT: jne .LBB24_3 -; X86-KNL-NEXT: .LBB24_4: # %else2 +; X86-KNL-NEXT: # %bb.1: # %else +; X86-KNL-NEXT: testb $2, %al +; X86-KNL-NEXT: jne .LBB24_4 +; X86-KNL-NEXT: .LBB24_2: # %else2 ; X86-KNL-NEXT: vmovdqa %xmm2, %xmm0 ; X86-KNL-NEXT: vzeroupper ; X86-KNL-NEXT: retl -; X86-KNL-NEXT: .LBB24_1: # %cond.load +; X86-KNL-NEXT: .LBB24_3: # %cond.load ; X86-KNL-NEXT: vmovd %xmm0, %ecx ; X86-KNL-NEXT: vpinsrd $0, (%ecx), %xmm2, %xmm2 ; X86-KNL-NEXT: testb $2, %al -; X86-KNL-NEXT: je .LBB24_4 -; X86-KNL-NEXT: .LBB24_3: # %cond.load1 +; X86-KNL-NEXT: je .LBB24_2 +; X86-KNL-NEXT: .LBB24_4: # %cond.load1 ; X86-KNL-NEXT: vpextrd $1, %xmm0, %eax ; X86-KNL-NEXT: vpinsrd $1, (%eax), %xmm2, %xmm2 ; X86-KNL-NEXT: vmovdqa %xmm2, %xmm0 @@ -1832,19 +1832,19 @@ define <2 x i32> @test23b(ptr %base, <2 x i64> %ind, <2 x i1> %mask, <2 x i32> % ; X64-SKX-NEXT: vpaddq %xmm0, %xmm1, %xmm0 ; X64-SKX-NEXT: kmovw %k0, %eax ; X64-SKX-NEXT: testb $1, %al -; X64-SKX-NEXT: jne .LBB24_1 -; X64-SKX-NEXT: # %bb.2: # %else -; X64-SKX-NEXT: testb $2, %al ; X64-SKX-NEXT: jne .LBB24_3 -; X64-SKX-NEXT: .LBB24_4: # %else2 +; X64-SKX-NEXT: # %bb.1: # %else +; X64-SKX-NEXT: testb $2, %al +; X64-SKX-NEXT: jne .LBB24_4 +; X64-SKX-NEXT: .LBB24_2: # %else2 ; X64-SKX-NEXT: vmovdqa %xmm2, %xmm0 ; X64-SKX-NEXT: retq -; X64-SKX-NEXT: .LBB24_1: # %cond.load +; X64-SKX-NEXT: .LBB24_3: # %cond.load ; X64-SKX-NEXT: vmovq %xmm0, %rcx ; X64-SKX-NEXT: vpinsrd $0, (%rcx), %xmm2, %xmm2 ; X64-SKX-NEXT: testb $2, %al -; X64-SKX-NEXT: je .LBB24_4 -; X64-SKX-NEXT: .LBB24_3: # %cond.load1 +; X64-SKX-NEXT: je .LBB24_2 +; X64-SKX-NEXT: .LBB24_4: # %cond.load1 ; X64-SKX-NEXT: vpextrq $1, %xmm0, %rax ; X64-SKX-NEXT: vpinsrd $1, (%rax), %xmm2, %xmm2 ; X64-SKX-NEXT: vmovdqa %xmm2, %xmm0 @@ -1858,19 +1858,19 @@ define <2 x i32> @test23b(ptr %base, <2 x i64> %ind, <2 x i1> %mask, <2 x i32> % ; X86-SKX-NEXT: vpaddd {{[0-9]+}}(%esp){1to4}, %xmm0, %xmm0 ; X86-SKX-NEXT: vmovmskpd %xmm1, %eax ; X86-SKX-NEXT: testb $1, %al -; X86-SKX-NEXT: jne .LBB24_1 -; X86-SKX-NEXT: # %bb.2: # %else -; X86-SKX-NEXT: testb $2, %al ; X86-SKX-NEXT: jne .LBB24_3 -; X86-SKX-NEXT: .LBB24_4: # %else2 +; X86-SKX-NEXT: # %bb.1: # %else +; X86-SKX-NEXT: testb $2, %al +; X86-SKX-NEXT: jne .LBB24_4 +; X86-SKX-NEXT: .LBB24_2: # %else2 ; X86-SKX-NEXT: vmovdqa %xmm2, %xmm0 ; X86-SKX-NEXT: retl -; X86-SKX-NEXT: .LBB24_1: # %cond.load +; X86-SKX-NEXT: .LBB24_3: # %cond.load ; X86-SKX-NEXT: vmovd %xmm0, %ecx ; X86-SKX-NEXT: vpinsrd $0, (%ecx), %xmm2, %xmm2 ; X86-SKX-NEXT: testb $2, %al -; X86-SKX-NEXT: je .LBB24_4 -; X86-SKX-NEXT: .LBB24_3: # %cond.load1 +; X86-SKX-NEXT: je .LBB24_2 +; X86-SKX-NEXT: .LBB24_4: # %cond.load1 ; X86-SKX-NEXT: vpextrd $1, %xmm0, %eax ; X86-SKX-NEXT: vpinsrd $1, (%eax), %xmm2, %xmm2 ; X86-SKX-NEXT: vmovdqa %xmm2, %xmm0 @@ -1944,20 +1944,20 @@ define <2 x i64> @test25(ptr %base, <2 x i32> %ind, <2 x i1> %mask, <2 x i64> %s ; X64-KNL-NEXT: vpaddq %xmm0, %xmm1, %xmm0 ; X64-KNL-NEXT: kmovw %k0, %eax ; X64-KNL-NEXT: testb $1, %al -; X64-KNL-NEXT: jne .LBB26_1 -; X64-KNL-NEXT: # %bb.2: # %else -; X64-KNL-NEXT: testb $2, %al ; X64-KNL-NEXT: jne .LBB26_3 -; X64-KNL-NEXT: .LBB26_4: # %else2 +; X64-KNL-NEXT: # %bb.1: # %else +; X64-KNL-NEXT: testb $2, %al +; X64-KNL-NEXT: jne .LBB26_4 +; X64-KNL-NEXT: .LBB26_2: # %else2 ; X64-KNL-NEXT: vmovdqa %xmm2, %xmm0 ; X64-KNL-NEXT: vzeroupper ; X64-KNL-NEXT: retq -; X64-KNL-NEXT: .LBB26_1: # %cond.load +; X64-KNL-NEXT: .LBB26_3: # %cond.load ; X64-KNL-NEXT: vmovq %xmm0, %rcx ; X64-KNL-NEXT: vpinsrq $0, (%rcx), %xmm2, %xmm2 ; X64-KNL-NEXT: testb $2, %al -; X64-KNL-NEXT: je .LBB26_4 -; X64-KNL-NEXT: .LBB26_3: # %cond.load1 +; X64-KNL-NEXT: je .LBB26_2 +; X64-KNL-NEXT: .LBB26_4: # %cond.load1 ; X64-KNL-NEXT: vpextrq $1, %xmm0, %rax ; X64-KNL-NEXT: vpinsrq $1, (%rax), %xmm2, %xmm2 ; X64-KNL-NEXT: vmovdqa %xmm2, %xmm0 @@ -1973,21 +1973,21 @@ define <2 x i64> @test25(ptr %base, <2 x i32> %ind, <2 x i1> %mask, <2 x i64> %s ; X86-KNL-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; X86-KNL-NEXT: kmovw %k0, %eax ; X86-KNL-NEXT: testb $1, %al -; X86-KNL-NEXT: jne .LBB26_1 -; X86-KNL-NEXT: # %bb.2: # %else -; X86-KNL-NEXT: testb $2, %al ; X86-KNL-NEXT: jne .LBB26_3 -; X86-KNL-NEXT: .LBB26_4: # %else2 +; X86-KNL-NEXT: # %bb.1: # %else +; X86-KNL-NEXT: testb $2, %al +; X86-KNL-NEXT: jne .LBB26_4 +; X86-KNL-NEXT: .LBB26_2: # %else2 ; X86-KNL-NEXT: vmovdqa %xmm2, %xmm0 ; X86-KNL-NEXT: vzeroupper ; X86-KNL-NEXT: retl -; X86-KNL-NEXT: .LBB26_1: # %cond.load +; X86-KNL-NEXT: .LBB26_3: # %cond.load ; X86-KNL-NEXT: vmovd %xmm0, %ecx ; X86-KNL-NEXT: vpinsrd $0, (%ecx), %xmm2, %xmm1 ; X86-KNL-NEXT: vpinsrd $1, 4(%ecx), %xmm1, %xmm2 ; X86-KNL-NEXT: testb $2, %al -; X86-KNL-NEXT: je .LBB26_4 -; X86-KNL-NEXT: .LBB26_3: # %cond.load1 +; X86-KNL-NEXT: je .LBB26_2 +; X86-KNL-NEXT: .LBB26_4: # %cond.load1 ; X86-KNL-NEXT: vpextrd $1, %xmm0, %eax ; X86-KNL-NEXT: vpinsrd $2, (%eax), %xmm2, %xmm0 ; X86-KNL-NEXT: vpinsrd $3, 4(%eax), %xmm0, %xmm2 @@ -2005,19 +2005,19 @@ define <2 x i64> @test25(ptr %base, <2 x i32> %ind, <2 x i1> %mask, <2 x i64> %s ; X64-SKX-NEXT: vpaddq %xmm0, %xmm1, %xmm0 ; X64-SKX-NEXT: kmovw %k0, %eax ; X64-SKX-NEXT: testb $1, %al -; X64-SKX-NEXT: jne .LBB26_1 -; X64-SKX-NEXT: # %bb.2: # %else -; X64-SKX-NEXT: testb $2, %al ; X64-SKX-NEXT: jne .LBB26_3 -; X64-SKX-NEXT: .LBB26_4: # %else2 +; X64-SKX-NEXT: # %bb.1: # %else +; X64-SKX-NEXT: testb $2, %al +; X64-SKX-NEXT: jne .LBB26_4 +; X64-SKX-NEXT: .LBB26_2: # %else2 ; X64-SKX-NEXT: vmovdqa %xmm2, %xmm0 ; X64-SKX-NEXT: retq -; X64-SKX-NEXT: .LBB26_1: # %cond.load +; X64-SKX-NEXT: .LBB26_3: # %cond.load ; X64-SKX-NEXT: vmovq %xmm0, %rcx ; X64-SKX-NEXT: vpinsrq $0, (%rcx), %xmm2, %xmm2 ; X64-SKX-NEXT: testb $2, %al -; X64-SKX-NEXT: je .LBB26_4 -; X64-SKX-NEXT: .LBB26_3: # %cond.load1 +; X64-SKX-NEXT: je .LBB26_2 +; X64-SKX-NEXT: .LBB26_4: # %cond.load1 ; X64-SKX-NEXT: vpextrq $1, %xmm0, %rax ; X64-SKX-NEXT: vpinsrq $1, (%rax), %xmm2, %xmm2 ; X64-SKX-NEXT: vmovdqa %xmm2, %xmm0 @@ -2030,20 +2030,20 @@ define <2 x i64> @test25(ptr %base, <2 x i32> %ind, <2 x i1> %mask, <2 x i64> %s ; X86-SKX-NEXT: vpaddd {{[0-9]+}}(%esp){1to4}, %xmm0, %xmm0 ; X86-SKX-NEXT: vmovmskpd %xmm1, %eax ; X86-SKX-NEXT: testb $1, %al -; X86-SKX-NEXT: jne .LBB26_1 -; X86-SKX-NEXT: # %bb.2: # %else -; X86-SKX-NEXT: testb $2, %al ; X86-SKX-NEXT: jne .LBB26_3 -; X86-SKX-NEXT: .LBB26_4: # %else2 +; X86-SKX-NEXT: # %bb.1: # %else +; X86-SKX-NEXT: testb $2, %al +; X86-SKX-NEXT: jne .LBB26_4 +; X86-SKX-NEXT: .LBB26_2: # %else2 ; X86-SKX-NEXT: vmovdqa %xmm2, %xmm0 ; X86-SKX-NEXT: retl -; X86-SKX-NEXT: .LBB26_1: # %cond.load +; X86-SKX-NEXT: .LBB26_3: # %cond.load ; X86-SKX-NEXT: vmovd %xmm0, %ecx ; X86-SKX-NEXT: vpinsrd $0, (%ecx), %xmm2, %xmm1 ; X86-SKX-NEXT: vpinsrd $1, 4(%ecx), %xmm1, %xmm2 ; X86-SKX-NEXT: testb $2, %al -; X86-SKX-NEXT: je .LBB26_4 -; X86-SKX-NEXT: .LBB26_3: # %cond.load1 +; X86-SKX-NEXT: je .LBB26_2 +; X86-SKX-NEXT: .LBB26_4: # %cond.load1 ; X86-SKX-NEXT: vpextrd $1, %xmm0, %eax ; X86-SKX-NEXT: vpinsrd $2, (%eax), %xmm2, %xmm0 ; X86-SKX-NEXT: vpinsrd $3, 4(%eax), %xmm0, %xmm2 @@ -3013,78 +3013,78 @@ define <4 x i64> @test_pr28312(<4 x ptr> %p1, <4 x i1> %k, <4 x i1> %k2,<4 x i64 ; X64-KNL-NEXT: kmovw %k0, %eax ; X64-KNL-NEXT: testb $1, %al ; X64-KNL-NEXT: # implicit-def: $ymm3 -; X64-KNL-NEXT: jne .LBB42_9 -; X64-KNL-NEXT: # %bb.10: # %else15 +; X64-KNL-NEXT: jne .LBB42_19 +; X64-KNL-NEXT: # %bb.9: # %else15 ; X64-KNL-NEXT: testb $2, %al -; X64-KNL-NEXT: jne .LBB42_11 -; X64-KNL-NEXT: .LBB42_12: # %else21 +; X64-KNL-NEXT: jne .LBB42_20 +; X64-KNL-NEXT: .LBB42_10: # %else21 ; X64-KNL-NEXT: testb $4, %al -; X64-KNL-NEXT: jne .LBB42_13 -; X64-KNL-NEXT: .LBB42_14: # %else27 +; X64-KNL-NEXT: jne .LBB42_21 +; X64-KNL-NEXT: .LBB42_11: # %else27 ; X64-KNL-NEXT: testb $8, %al -; X64-KNL-NEXT: je .LBB42_16 -; X64-KNL-NEXT: .LBB42_15: # %cond.load29 +; X64-KNL-NEXT: je .LBB42_13 +; X64-KNL-NEXT: .LBB42_12: # %cond.load29 ; X64-KNL-NEXT: vpextrq $1, %xmm2, %rax ; X64-KNL-NEXT: vpbroadcastq (%rax), %ymm4 ; X64-KNL-NEXT: vpblendd {{.*#+}} ymm3 = ymm3[0,1,2,3,4,5],ymm4[6,7] -; X64-KNL-NEXT: .LBB42_16: # %else33 +; X64-KNL-NEXT: .LBB42_13: # %else33 ; X64-KNL-NEXT: kmovw %k0, %eax ; X64-KNL-NEXT: testb $1, %al ; X64-KNL-NEXT: # implicit-def: $ymm4 -; X64-KNL-NEXT: jne .LBB42_17 -; X64-KNL-NEXT: # %bb.18: # %else40 +; X64-KNL-NEXT: jne .LBB42_22 +; X64-KNL-NEXT: # %bb.14: # %else40 ; X64-KNL-NEXT: testb $2, %al -; X64-KNL-NEXT: jne .LBB42_19 -; X64-KNL-NEXT: .LBB42_20: # %else46 +; X64-KNL-NEXT: jne .LBB42_23 +; X64-KNL-NEXT: .LBB42_15: # %else46 ; X64-KNL-NEXT: testb $4, %al -; X64-KNL-NEXT: jne .LBB42_21 -; X64-KNL-NEXT: .LBB42_22: # %else52 +; X64-KNL-NEXT: jne .LBB42_24 +; X64-KNL-NEXT: .LBB42_16: # %else52 ; X64-KNL-NEXT: testb $8, %al -; X64-KNL-NEXT: je .LBB42_24 -; X64-KNL-NEXT: .LBB42_23: # %cond.load54 +; X64-KNL-NEXT: je .LBB42_18 +; X64-KNL-NEXT: .LBB42_17: # %cond.load54 ; X64-KNL-NEXT: vpextrq $1, %xmm2, %rax ; X64-KNL-NEXT: vpbroadcastq (%rax), %ymm0 ; X64-KNL-NEXT: vpblendd {{.*#+}} ymm4 = ymm4[0,1,2,3,4,5],ymm0[6,7] -; X64-KNL-NEXT: .LBB42_24: # %else58 +; X64-KNL-NEXT: .LBB42_18: # %else58 ; X64-KNL-NEXT: vpaddq %ymm3, %ymm1, %ymm0 ; X64-KNL-NEXT: vpaddq %ymm4, %ymm0, %ymm0 ; X64-KNL-NEXT: retq -; X64-KNL-NEXT: .LBB42_9: # %cond.load11 +; X64-KNL-NEXT: .LBB42_19: # %cond.load11 ; X64-KNL-NEXT: vmovq %xmm0, %rcx ; X64-KNL-NEXT: vmovq {{.*#+}} xmm3 = mem[0],zero ; X64-KNL-NEXT: testb $2, %al -; X64-KNL-NEXT: je .LBB42_12 -; X64-KNL-NEXT: .LBB42_11: # %cond.load17 +; X64-KNL-NEXT: je .LBB42_10 +; X64-KNL-NEXT: .LBB42_20: # %cond.load17 ; X64-KNL-NEXT: vpextrq $1, %xmm0, %rcx ; X64-KNL-NEXT: vpinsrq $1, (%rcx), %xmm3, %xmm4 ; X64-KNL-NEXT: vpblendd {{.*#+}} ymm3 = ymm4[0,1,2,3],ymm3[4,5,6,7] ; X64-KNL-NEXT: testb $4, %al -; X64-KNL-NEXT: je .LBB42_14 -; X64-KNL-NEXT: .LBB42_13: # %cond.load23 +; X64-KNL-NEXT: je .LBB42_11 +; X64-KNL-NEXT: .LBB42_21: # %cond.load23 ; X64-KNL-NEXT: vmovq %xmm2, %rcx ; X64-KNL-NEXT: vpbroadcastq (%rcx), %ymm4 ; X64-KNL-NEXT: vpblendd {{.*#+}} ymm3 = ymm3[0,1,2,3],ymm4[4,5],ymm3[6,7] ; X64-KNL-NEXT: testb $8, %al -; X64-KNL-NEXT: jne .LBB42_15 -; X64-KNL-NEXT: jmp .LBB42_16 -; X64-KNL-NEXT: .LBB42_17: # %cond.load36 +; X64-KNL-NEXT: jne .LBB42_12 +; X64-KNL-NEXT: jmp .LBB42_13 +; X64-KNL-NEXT: .LBB42_22: # %cond.load36 ; X64-KNL-NEXT: vmovq %xmm0, %rcx ; X64-KNL-NEXT: vmovq {{.*#+}} xmm4 = mem[0],zero ; X64-KNL-NEXT: testb $2, %al -; X64-KNL-NEXT: je .LBB42_20 -; X64-KNL-NEXT: .LBB42_19: # %cond.load42 +; X64-KNL-NEXT: je .LBB42_15 +; X64-KNL-NEXT: .LBB42_23: # %cond.load42 ; X64-KNL-NEXT: vpextrq $1, %xmm0, %rcx ; X64-KNL-NEXT: vpinsrq $1, (%rcx), %xmm4, %xmm0 ; X64-KNL-NEXT: vpblendd {{.*#+}} ymm4 = ymm0[0,1,2,3],ymm4[4,5,6,7] ; X64-KNL-NEXT: testb $4, %al -; X64-KNL-NEXT: je .LBB42_22 -; X64-KNL-NEXT: .LBB42_21: # %cond.load48 +; X64-KNL-NEXT: je .LBB42_16 +; X64-KNL-NEXT: .LBB42_24: # %cond.load48 ; X64-KNL-NEXT: vmovq %xmm2, %rcx ; X64-KNL-NEXT: vpbroadcastq (%rcx), %ymm0 ; X64-KNL-NEXT: vpblendd {{.*#+}} ymm4 = ymm4[0,1,2,3],ymm0[4,5],ymm4[6,7] ; X64-KNL-NEXT: testb $8, %al -; X64-KNL-NEXT: jne .LBB42_23 -; X64-KNL-NEXT: jmp .LBB42_24 +; X64-KNL-NEXT: jne .LBB42_17 +; X64-KNL-NEXT: jmp .LBB42_18 ; ; X86-KNL-LABEL: test_pr28312: ; X86-KNL: # %bb.0: @@ -3138,41 +3138,41 @@ define <4 x i64> @test_pr28312(<4 x ptr> %p1, <4 x i1> %k, <4 x i1> %k2,<4 x i64 ; X86-KNL-NEXT: kmovw %k0, %ebx ; X86-KNL-NEXT: testb $1, %bl ; X86-KNL-NEXT: # implicit-def: $ymm0 -; X86-KNL-NEXT: jne .LBB42_9 -; X86-KNL-NEXT: # %bb.10: # %else15 +; X86-KNL-NEXT: jne .LBB42_19 +; X86-KNL-NEXT: # %bb.9: # %else15 ; X86-KNL-NEXT: testb $2, %bl -; X86-KNL-NEXT: jne .LBB42_11 -; X86-KNL-NEXT: .LBB42_12: # %else21 +; X86-KNL-NEXT: jne .LBB42_20 +; X86-KNL-NEXT: .LBB42_10: # %else21 ; X86-KNL-NEXT: testb $4, %bl -; X86-KNL-NEXT: jne .LBB42_13 -; X86-KNL-NEXT: .LBB42_14: # %else27 +; X86-KNL-NEXT: jne .LBB42_21 +; X86-KNL-NEXT: .LBB42_11: # %else27 ; X86-KNL-NEXT: testb $8, %bl -; X86-KNL-NEXT: je .LBB42_16 -; X86-KNL-NEXT: .LBB42_15: # %cond.load29 +; X86-KNL-NEXT: je .LBB42_13 +; X86-KNL-NEXT: .LBB42_12: # %cond.load29 ; X86-KNL-NEXT: vpbroadcastd (%esi), %ymm2 ; X86-KNL-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5],ymm2[6],ymm0[7] ; X86-KNL-NEXT: vpbroadcastd 4(%esi), %ymm2 ; X86-KNL-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5,6],ymm2[7] -; X86-KNL-NEXT: .LBB42_16: # %else33 +; X86-KNL-NEXT: .LBB42_13: # %else33 ; X86-KNL-NEXT: kmovw %k0, %ebx ; X86-KNL-NEXT: testb $1, %bl ; X86-KNL-NEXT: # implicit-def: $ymm2 -; X86-KNL-NEXT: jne .LBB42_17 -; X86-KNL-NEXT: # %bb.18: # %else40 +; X86-KNL-NEXT: jne .LBB42_22 +; X86-KNL-NEXT: # %bb.14: # %else40 ; X86-KNL-NEXT: testb $2, %bl -; X86-KNL-NEXT: jne .LBB42_19 -; X86-KNL-NEXT: .LBB42_20: # %else46 +; X86-KNL-NEXT: jne .LBB42_23 +; X86-KNL-NEXT: .LBB42_15: # %else46 ; X86-KNL-NEXT: testb $4, %bl -; X86-KNL-NEXT: jne .LBB42_21 -; X86-KNL-NEXT: .LBB42_22: # %else52 +; X86-KNL-NEXT: jne .LBB42_24 +; X86-KNL-NEXT: .LBB42_16: # %else52 ; X86-KNL-NEXT: testb $8, %bl -; X86-KNL-NEXT: je .LBB42_24 -; X86-KNL-NEXT: .LBB42_23: # %cond.load54 +; X86-KNL-NEXT: je .LBB42_18 +; X86-KNL-NEXT: .LBB42_17: # %cond.load54 ; X86-KNL-NEXT: vpbroadcastd (%esi), %ymm3 ; X86-KNL-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3,4,5],ymm3[6],ymm2[7] ; X86-KNL-NEXT: vpbroadcastd 4(%esi), %ymm3 ; X86-KNL-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3,4,5,6],ymm3[7] -; X86-KNL-NEXT: .LBB42_24: # %else58 +; X86-KNL-NEXT: .LBB42_18: # %else58 ; X86-KNL-NEXT: vpaddq %ymm0, %ymm1, %ymm0 ; X86-KNL-NEXT: vpaddq %ymm2, %ymm0, %ymm0 ; X86-KNL-NEXT: leal -8(%ebp), %esp @@ -3181,43 +3181,43 @@ define <4 x i64> @test_pr28312(<4 x ptr> %p1, <4 x i1> %k, <4 x i1> %k2,<4 x i64 ; X86-KNL-NEXT: popl %ebp ; X86-KNL-NEXT: .cfi_def_cfa %esp, 4 ; X86-KNL-NEXT: retl -; X86-KNL-NEXT: .LBB42_9: # %cond.load11 +; X86-KNL-NEXT: .LBB42_19: # %cond.load11 ; X86-KNL-NEXT: .cfi_def_cfa %ebp, 8 ; X86-KNL-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero ; X86-KNL-NEXT: testb $2, %bl -; X86-KNL-NEXT: je .LBB42_12 -; X86-KNL-NEXT: .LBB42_11: # %cond.load17 +; X86-KNL-NEXT: je .LBB42_10 +; X86-KNL-NEXT: .LBB42_20: # %cond.load17 ; X86-KNL-NEXT: vpinsrd $2, (%ecx), %xmm0, %xmm2 ; X86-KNL-NEXT: vpinsrd $3, 4(%ecx), %xmm2, %xmm2 ; X86-KNL-NEXT: vpblendd {{.*#+}} ymm0 = ymm2[0,1,2,3],ymm0[4,5,6,7] ; X86-KNL-NEXT: testb $4, %bl -; X86-KNL-NEXT: je .LBB42_14 -; X86-KNL-NEXT: .LBB42_13: # %cond.load23 +; X86-KNL-NEXT: je .LBB42_11 +; X86-KNL-NEXT: .LBB42_21: # %cond.load23 ; X86-KNL-NEXT: vpbroadcastd (%edx), %ymm2 ; X86-KNL-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm2[4],ymm0[5,6,7] ; X86-KNL-NEXT: vpbroadcastd 4(%edx), %ymm2 ; X86-KNL-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3,4],ymm2[5],ymm0[6,7] ; X86-KNL-NEXT: testb $8, %bl -; X86-KNL-NEXT: jne .LBB42_15 -; X86-KNL-NEXT: jmp .LBB42_16 -; X86-KNL-NEXT: .LBB42_17: # %cond.load36 +; X86-KNL-NEXT: jne .LBB42_12 +; X86-KNL-NEXT: jmp .LBB42_13 +; X86-KNL-NEXT: .LBB42_22: # %cond.load36 ; X86-KNL-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero ; X86-KNL-NEXT: testb $2, %bl -; X86-KNL-NEXT: je .LBB42_20 -; X86-KNL-NEXT: .LBB42_19: # %cond.load42 +; X86-KNL-NEXT: je .LBB42_15 +; X86-KNL-NEXT: .LBB42_23: # %cond.load42 ; X86-KNL-NEXT: vpinsrd $2, (%ecx), %xmm2, %xmm3 ; X86-KNL-NEXT: vpinsrd $3, 4(%ecx), %xmm3, %xmm3 ; X86-KNL-NEXT: vpblendd {{.*#+}} ymm2 = ymm3[0,1,2,3],ymm2[4,5,6,7] ; X86-KNL-NEXT: testb $4, %bl -; X86-KNL-NEXT: je .LBB42_22 -; X86-KNL-NEXT: .LBB42_21: # %cond.load48 +; X86-KNL-NEXT: je .LBB42_16 +; X86-KNL-NEXT: .LBB42_24: # %cond.load48 ; X86-KNL-NEXT: vpbroadcastd (%edx), %ymm3 ; X86-KNL-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3],ymm3[4],ymm2[5,6,7] ; X86-KNL-NEXT: vpbroadcastd 4(%edx), %ymm3 ; X86-KNL-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0,1,2,3,4],ymm3[5],ymm2[6,7] ; X86-KNL-NEXT: testb $8, %bl -; X86-KNL-NEXT: jne .LBB42_23 -; X86-KNL-NEXT: jmp .LBB42_24 +; X86-KNL-NEXT: jne .LBB42_17 +; X86-KNL-NEXT: jmp .LBB42_18 ; ; X64-SKX-LABEL: test_pr28312: ; X64-SKX: # %bb.0: @@ -3406,21 +3406,21 @@ define <2 x float> @large_index(ptr %base, <2 x i128> %ind, <2 x i1> %mask, <2 x ; X64-KNL-NEXT: vpaddq %xmm0, %xmm2, %xmm0 ; X64-KNL-NEXT: kmovw %k0, %eax ; X64-KNL-NEXT: testb $1, %al -; X64-KNL-NEXT: jne .LBB47_1 -; X64-KNL-NEXT: # %bb.2: # %else -; X64-KNL-NEXT: testb $2, %al ; X64-KNL-NEXT: jne .LBB47_3 -; X64-KNL-NEXT: .LBB47_4: # %else2 +; X64-KNL-NEXT: # %bb.1: # %else +; X64-KNL-NEXT: testb $2, %al +; X64-KNL-NEXT: jne .LBB47_4 +; X64-KNL-NEXT: .LBB47_2: # %else2 ; X64-KNL-NEXT: vmovdqa %xmm1, %xmm0 ; X64-KNL-NEXT: vzeroupper ; X64-KNL-NEXT: retq -; X64-KNL-NEXT: .LBB47_1: # %cond.load +; X64-KNL-NEXT: .LBB47_3: # %cond.load ; X64-KNL-NEXT: vmovq %xmm0, %rcx ; X64-KNL-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero ; X64-KNL-NEXT: vpblendd {{.*#+}} xmm1 = xmm2[0],xmm1[1,2,3] ; X64-KNL-NEXT: testb $2, %al -; X64-KNL-NEXT: je .LBB47_4 -; X64-KNL-NEXT: .LBB47_3: # %cond.load1 +; X64-KNL-NEXT: je .LBB47_2 +; X64-KNL-NEXT: .LBB47_4: # %cond.load1 ; X64-KNL-NEXT: vpextrq $1, %xmm0, %rax ; X64-KNL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[2,3] ; X64-KNL-NEXT: vmovaps %xmm1, %xmm0 @@ -3438,21 +3438,21 @@ define <2 x float> @large_index(ptr %base, <2 x i128> %ind, <2 x i1> %mask, <2 x ; X86-KNL-NEXT: vpaddd %xmm0, %xmm2, %xmm0 ; X86-KNL-NEXT: kmovw %k0, %eax ; X86-KNL-NEXT: testb $1, %al -; X86-KNL-NEXT: jne .LBB47_1 -; X86-KNL-NEXT: # %bb.2: # %else -; X86-KNL-NEXT: testb $2, %al ; X86-KNL-NEXT: jne .LBB47_3 -; X86-KNL-NEXT: .LBB47_4: # %else2 +; X86-KNL-NEXT: # %bb.1: # %else +; X86-KNL-NEXT: testb $2, %al +; X86-KNL-NEXT: jne .LBB47_4 +; X86-KNL-NEXT: .LBB47_2: # %else2 ; X86-KNL-NEXT: vmovdqa %xmm1, %xmm0 ; X86-KNL-NEXT: vzeroupper ; X86-KNL-NEXT: retl -; X86-KNL-NEXT: .LBB47_1: # %cond.load +; X86-KNL-NEXT: .LBB47_3: # %cond.load ; X86-KNL-NEXT: vmovd %xmm0, %ecx ; X86-KNL-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero ; X86-KNL-NEXT: vpblendd {{.*#+}} xmm1 = xmm2[0],xmm1[1,2,3] ; X86-KNL-NEXT: testb $2, %al -; X86-KNL-NEXT: je .LBB47_4 -; X86-KNL-NEXT: .LBB47_3: # %cond.load1 +; X86-KNL-NEXT: je .LBB47_2 +; X86-KNL-NEXT: .LBB47_4: # %cond.load1 ; X86-KNL-NEXT: vpextrd $1, %xmm0, %eax ; X86-KNL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[2,3] ; X86-KNL-NEXT: vmovaps %xmm1, %xmm0 @@ -3471,20 +3471,20 @@ define <2 x float> @large_index(ptr %base, <2 x i128> %ind, <2 x i1> %mask, <2 x ; X64-SKX-NEXT: vpaddq %xmm0, %xmm2, %xmm0 ; X64-SKX-NEXT: kmovw %k0, %eax ; X64-SKX-NEXT: testb $1, %al -; X64-SKX-NEXT: jne .LBB47_1 -; X64-SKX-NEXT: # %bb.2: # %else -; X64-SKX-NEXT: testb $2, %al ; X64-SKX-NEXT: jne .LBB47_3 -; X64-SKX-NEXT: .LBB47_4: # %else2 +; X64-SKX-NEXT: # %bb.1: # %else +; X64-SKX-NEXT: testb $2, %al +; X64-SKX-NEXT: jne .LBB47_4 +; X64-SKX-NEXT: .LBB47_2: # %else2 ; X64-SKX-NEXT: vmovdqa %xmm1, %xmm0 ; X64-SKX-NEXT: retq -; X64-SKX-NEXT: .LBB47_1: # %cond.load +; X64-SKX-NEXT: .LBB47_3: # %cond.load ; X64-SKX-NEXT: vmovq %xmm0, %rcx ; X64-SKX-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero ; X64-SKX-NEXT: vpblendd {{.*#+}} xmm1 = xmm2[0],xmm1[1,2,3] ; X64-SKX-NEXT: testb $2, %al -; X64-SKX-NEXT: je .LBB47_4 -; X64-SKX-NEXT: .LBB47_3: # %cond.load1 +; X64-SKX-NEXT: je .LBB47_2 +; X64-SKX-NEXT: .LBB47_4: # %cond.load1 ; X64-SKX-NEXT: vpextrq $1, %xmm0, %rax ; X64-SKX-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[2,3] ; X64-SKX-NEXT: vmovaps %xmm1, %xmm0 @@ -3500,20 +3500,20 @@ define <2 x float> @large_index(ptr %base, <2 x i128> %ind, <2 x i1> %mask, <2 x ; X86-SKX-NEXT: vpaddd {{[0-9]+}}(%esp){1to4}, %xmm0, %xmm0 ; X86-SKX-NEXT: kmovw %k0, %eax ; X86-SKX-NEXT: testb $1, %al -; X86-SKX-NEXT: jne .LBB47_1 -; X86-SKX-NEXT: # %bb.2: # %else -; X86-SKX-NEXT: testb $2, %al ; X86-SKX-NEXT: jne .LBB47_3 -; X86-SKX-NEXT: .LBB47_4: # %else2 +; X86-SKX-NEXT: # %bb.1: # %else +; X86-SKX-NEXT: testb $2, %al +; X86-SKX-NEXT: jne .LBB47_4 +; X86-SKX-NEXT: .LBB47_2: # %else2 ; X86-SKX-NEXT: vmovaps %xmm1, %xmm0 ; X86-SKX-NEXT: retl -; X86-SKX-NEXT: .LBB47_1: # %cond.load +; X86-SKX-NEXT: .LBB47_3: # %cond.load ; X86-SKX-NEXT: vmovd %xmm0, %ecx ; X86-SKX-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; X86-SKX-NEXT: vmovss {{.*#+}} xmm1 = xmm2[0],xmm1[1,2,3] ; X86-SKX-NEXT: testb $2, %al -; X86-SKX-NEXT: je .LBB47_4 -; X86-SKX-NEXT: .LBB47_3: # %cond.load1 +; X86-SKX-NEXT: je .LBB47_2 +; X86-SKX-NEXT: .LBB47_4: # %cond.load1 ; X86-SKX-NEXT: vpextrd $1, %xmm0, %eax ; X86-SKX-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[2,3] ; X86-SKX-NEXT: vmovaps %xmm1, %xmm0 @@ -3679,19 +3679,19 @@ define void @test_scatter_2i32_index(<2 x double> %a1, ptr %base, <2 x i32> %ind ; X64-KNL-NEXT: vpaddq %xmm1, %xmm2, %xmm1 ; X64-KNL-NEXT: kmovw %k0, %eax ; X64-KNL-NEXT: testb $1, %al -; X64-KNL-NEXT: jne .LBB52_1 -; X64-KNL-NEXT: # %bb.2: # %else -; X64-KNL-NEXT: testb $2, %al ; X64-KNL-NEXT: jne .LBB52_3 -; X64-KNL-NEXT: .LBB52_4: # %else2 +; X64-KNL-NEXT: # %bb.1: # %else +; X64-KNL-NEXT: testb $2, %al +; X64-KNL-NEXT: jne .LBB52_4 +; X64-KNL-NEXT: .LBB52_2: # %else2 ; X64-KNL-NEXT: vzeroupper ; X64-KNL-NEXT: retq -; X64-KNL-NEXT: .LBB52_1: # %cond.store +; X64-KNL-NEXT: .LBB52_3: # %cond.store ; X64-KNL-NEXT: vmovq %xmm1, %rcx ; X64-KNL-NEXT: vmovlps %xmm0, (%rcx) ; X64-KNL-NEXT: testb $2, %al -; X64-KNL-NEXT: je .LBB52_4 -; X64-KNL-NEXT: .LBB52_3: # %cond.store1 +; X64-KNL-NEXT: je .LBB52_2 +; X64-KNL-NEXT: .LBB52_4: # %cond.store1 ; X64-KNL-NEXT: vpextrq $1, %xmm1, %rax ; X64-KNL-NEXT: vmovhps %xmm0, (%rax) ; X64-KNL-NEXT: vzeroupper @@ -3706,19 +3706,19 @@ define void @test_scatter_2i32_index(<2 x double> %a1, ptr %base, <2 x i32> %ind ; X86-KNL-NEXT: vpaddd %xmm1, %xmm2, %xmm1 ; X86-KNL-NEXT: kmovw %k0, %eax ; X86-KNL-NEXT: testb $1, %al -; X86-KNL-NEXT: jne .LBB52_1 -; X86-KNL-NEXT: # %bb.2: # %else -; X86-KNL-NEXT: testb $2, %al ; X86-KNL-NEXT: jne .LBB52_3 -; X86-KNL-NEXT: .LBB52_4: # %else2 +; X86-KNL-NEXT: # %bb.1: # %else +; X86-KNL-NEXT: testb $2, %al +; X86-KNL-NEXT: jne .LBB52_4 +; X86-KNL-NEXT: .LBB52_2: # %else2 ; X86-KNL-NEXT: vzeroupper ; X86-KNL-NEXT: retl -; X86-KNL-NEXT: .LBB52_1: # %cond.store +; X86-KNL-NEXT: .LBB52_3: # %cond.store ; X86-KNL-NEXT: vmovd %xmm1, %ecx ; X86-KNL-NEXT: vmovlps %xmm0, (%ecx) ; X86-KNL-NEXT: testb $2, %al -; X86-KNL-NEXT: je .LBB52_4 -; X86-KNL-NEXT: .LBB52_3: # %cond.store1 +; X86-KNL-NEXT: je .LBB52_2 +; X86-KNL-NEXT: .LBB52_4: # %cond.store1 ; X86-KNL-NEXT: vpextrd $1, %xmm1, %eax ; X86-KNL-NEXT: vmovhps %xmm0, (%eax) ; X86-KNL-NEXT: vzeroupper @@ -3734,18 +3734,18 @@ define void @test_scatter_2i32_index(<2 x double> %a1, ptr %base, <2 x i32> %ind ; X64-SKX-NEXT: vpaddq %xmm1, %xmm2, %xmm1 ; X64-SKX-NEXT: kmovw %k0, %eax ; X64-SKX-NEXT: testb $1, %al -; X64-SKX-NEXT: jne .LBB52_1 -; X64-SKX-NEXT: # %bb.2: # %else -; X64-SKX-NEXT: testb $2, %al ; X64-SKX-NEXT: jne .LBB52_3 -; X64-SKX-NEXT: .LBB52_4: # %else2 +; X64-SKX-NEXT: # %bb.1: # %else +; X64-SKX-NEXT: testb $2, %al +; X64-SKX-NEXT: jne .LBB52_4 +; X64-SKX-NEXT: .LBB52_2: # %else2 ; X64-SKX-NEXT: retq -; X64-SKX-NEXT: .LBB52_1: # %cond.store +; X64-SKX-NEXT: .LBB52_3: # %cond.store ; X64-SKX-NEXT: vmovq %xmm1, %rcx ; X64-SKX-NEXT: vmovlps %xmm0, (%rcx) ; X64-SKX-NEXT: testb $2, %al -; X64-SKX-NEXT: je .LBB52_4 -; X64-SKX-NEXT: .LBB52_3: # %cond.store1 +; X64-SKX-NEXT: je .LBB52_2 +; X64-SKX-NEXT: .LBB52_4: # %cond.store1 ; X64-SKX-NEXT: vpextrq $1, %xmm1, %rax ; X64-SKX-NEXT: vmovhps %xmm0, (%rax) ; X64-SKX-NEXT: retq @@ -3757,18 +3757,18 @@ define void @test_scatter_2i32_index(<2 x double> %a1, ptr %base, <2 x i32> %ind ; X86-SKX-NEXT: vpaddd {{[0-9]+}}(%esp){1to4}, %xmm1, %xmm1 ; X86-SKX-NEXT: vmovmskpd %xmm2, %eax ; X86-SKX-NEXT: testb $1, %al -; X86-SKX-NEXT: jne .LBB52_1 -; X86-SKX-NEXT: # %bb.2: # %else -; X86-SKX-NEXT: testb $2, %al ; X86-SKX-NEXT: jne .LBB52_3 -; X86-SKX-NEXT: .LBB52_4: # %else2 +; X86-SKX-NEXT: # %bb.1: # %else +; X86-SKX-NEXT: testb $2, %al +; X86-SKX-NEXT: jne .LBB52_4 +; X86-SKX-NEXT: .LBB52_2: # %else2 ; X86-SKX-NEXT: retl -; X86-SKX-NEXT: .LBB52_1: # %cond.store +; X86-SKX-NEXT: .LBB52_3: # %cond.store ; X86-SKX-NEXT: vmovd %xmm1, %ecx ; X86-SKX-NEXT: vmovlps %xmm0, (%ecx) ; X86-SKX-NEXT: testb $2, %al -; X86-SKX-NEXT: je .LBB52_4 -; X86-SKX-NEXT: .LBB52_3: # %cond.store1 +; X86-SKX-NEXT: je .LBB52_2 +; X86-SKX-NEXT: .LBB52_4: # %cond.store1 ; X86-SKX-NEXT: vpextrd $1, %xmm1, %eax ; X86-SKX-NEXT: vmovhps %xmm0, (%eax) ; X86-SKX-NEXT: retl @@ -4039,19 +4039,19 @@ define <2 x i64> @gather_2i64_constant_indices(ptr %ptr, <2 x i1> %mask) { ; X64-KNL-NEXT: kmovw %k0, %eax ; X64-KNL-NEXT: vpxor %xmm0, %xmm0, %xmm0 ; X64-KNL-NEXT: testb $1, %al -; X64-KNL-NEXT: jne .LBB58_1 -; X64-KNL-NEXT: # %bb.2: # %else -; X64-KNL-NEXT: testb $2, %al ; X64-KNL-NEXT: jne .LBB58_3 -; X64-KNL-NEXT: .LBB58_4: # %else2 +; X64-KNL-NEXT: # %bb.1: # %else +; X64-KNL-NEXT: testb $2, %al +; X64-KNL-NEXT: jne .LBB58_4 +; X64-KNL-NEXT: .LBB58_2: # %else2 ; X64-KNL-NEXT: vzeroupper ; X64-KNL-NEXT: retq -; X64-KNL-NEXT: .LBB58_1: # %cond.load +; X64-KNL-NEXT: .LBB58_3: # %cond.load ; X64-KNL-NEXT: vmovq %xmm1, %rcx ; X64-KNL-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero ; X64-KNL-NEXT: testb $2, %al -; X64-KNL-NEXT: je .LBB58_4 -; X64-KNL-NEXT: .LBB58_3: # %cond.load1 +; X64-KNL-NEXT: je .LBB58_2 +; X64-KNL-NEXT: .LBB58_4: # %cond.load1 ; X64-KNL-NEXT: vpextrq $1, %xmm1, %rax ; X64-KNL-NEXT: vpinsrq $1, (%rax), %xmm0, %xmm0 ; X64-KNL-NEXT: vzeroupper @@ -4066,19 +4066,19 @@ define <2 x i64> @gather_2i64_constant_indices(ptr %ptr, <2 x i1> %mask) { ; X86-KNL-NEXT: kmovw %k0, %eax ; X86-KNL-NEXT: vpxor %xmm0, %xmm0, %xmm0 ; X86-KNL-NEXT: testb $1, %al -; X86-KNL-NEXT: jne .LBB58_1 -; X86-KNL-NEXT: # %bb.2: # %else -; X86-KNL-NEXT: testb $2, %al ; X86-KNL-NEXT: jne .LBB58_3 -; X86-KNL-NEXT: .LBB58_4: # %else2 +; X86-KNL-NEXT: # %bb.1: # %else +; X86-KNL-NEXT: testb $2, %al +; X86-KNL-NEXT: jne .LBB58_4 +; X86-KNL-NEXT: .LBB58_2: # %else2 ; X86-KNL-NEXT: vzeroupper ; X86-KNL-NEXT: retl -; X86-KNL-NEXT: .LBB58_1: # %cond.load +; X86-KNL-NEXT: .LBB58_3: # %cond.load ; X86-KNL-NEXT: vmovd %xmm1, %ecx ; X86-KNL-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero ; X86-KNL-NEXT: testb $2, %al -; X86-KNL-NEXT: je .LBB58_4 -; X86-KNL-NEXT: .LBB58_3: # %cond.load1 +; X86-KNL-NEXT: je .LBB58_2 +; X86-KNL-NEXT: .LBB58_4: # %cond.load1 ; X86-KNL-NEXT: vpextrd $1, %xmm1, %eax ; X86-KNL-NEXT: vpinsrd $2, (%eax), %xmm0, %xmm0 ; X86-KNL-NEXT: vpinsrd $3, 4(%eax), %xmm0, %xmm0 @@ -4094,18 +4094,18 @@ define <2 x i64> @gather_2i64_constant_indices(ptr %ptr, <2 x i1> %mask) { ; X64-SKX-SMALL-NEXT: kmovw %k0, %eax ; X64-SKX-SMALL-NEXT: vpxor %xmm0, %xmm0, %xmm0 ; X64-SKX-SMALL-NEXT: testb $1, %al -; X64-SKX-SMALL-NEXT: jne .LBB58_1 -; X64-SKX-SMALL-NEXT: # %bb.2: # %else -; X64-SKX-SMALL-NEXT: testb $2, %al ; X64-SKX-SMALL-NEXT: jne .LBB58_3 -; X64-SKX-SMALL-NEXT: .LBB58_4: # %else2 +; X64-SKX-SMALL-NEXT: # %bb.1: # %else +; X64-SKX-SMALL-NEXT: testb $2, %al +; X64-SKX-SMALL-NEXT: jne .LBB58_4 +; X64-SKX-SMALL-NEXT: .LBB58_2: # %else2 ; X64-SKX-SMALL-NEXT: retq -; X64-SKX-SMALL-NEXT: .LBB58_1: # %cond.load +; X64-SKX-SMALL-NEXT: .LBB58_3: # %cond.load ; X64-SKX-SMALL-NEXT: vmovq %xmm1, %rcx ; X64-SKX-SMALL-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero ; X64-SKX-SMALL-NEXT: testb $2, %al -; X64-SKX-SMALL-NEXT: je .LBB58_4 -; X64-SKX-SMALL-NEXT: .LBB58_3: # %cond.load1 +; X64-SKX-SMALL-NEXT: je .LBB58_2 +; X64-SKX-SMALL-NEXT: .LBB58_4: # %cond.load1 ; X64-SKX-SMALL-NEXT: vpextrq $1, %xmm1, %rax ; X64-SKX-SMALL-NEXT: vpinsrq $1, (%rax), %xmm0, %xmm0 ; X64-SKX-SMALL-NEXT: retq @@ -4120,18 +4120,18 @@ define <2 x i64> @gather_2i64_constant_indices(ptr %ptr, <2 x i1> %mask) { ; X64-SKX-LARGE-NEXT: kmovw %k0, %eax ; X64-SKX-LARGE-NEXT: vpxor %xmm0, %xmm0, %xmm0 ; X64-SKX-LARGE-NEXT: testb $1, %al -; X64-SKX-LARGE-NEXT: jne .LBB58_1 -; X64-SKX-LARGE-NEXT: # %bb.2: # %else -; X64-SKX-LARGE-NEXT: testb $2, %al ; X64-SKX-LARGE-NEXT: jne .LBB58_3 -; X64-SKX-LARGE-NEXT: .LBB58_4: # %else2 +; X64-SKX-LARGE-NEXT: # %bb.1: # %else +; X64-SKX-LARGE-NEXT: testb $2, %al +; X64-SKX-LARGE-NEXT: jne .LBB58_4 +; X64-SKX-LARGE-NEXT: .LBB58_2: # %else2 ; X64-SKX-LARGE-NEXT: retq -; X64-SKX-LARGE-NEXT: .LBB58_1: # %cond.load +; X64-SKX-LARGE-NEXT: .LBB58_3: # %cond.load ; X64-SKX-LARGE-NEXT: vmovq %xmm1, %rcx ; X64-SKX-LARGE-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero ; X64-SKX-LARGE-NEXT: testb $2, %al -; X64-SKX-LARGE-NEXT: je .LBB58_4 -; X64-SKX-LARGE-NEXT: .LBB58_3: # %cond.load1 +; X64-SKX-LARGE-NEXT: je .LBB58_2 +; X64-SKX-LARGE-NEXT: .LBB58_4: # %cond.load1 ; X64-SKX-LARGE-NEXT: vpextrq $1, %xmm1, %rax ; X64-SKX-LARGE-NEXT: vpinsrq $1, (%rax), %xmm0, %xmm0 ; X64-SKX-LARGE-NEXT: retq @@ -4145,18 +4145,18 @@ define <2 x i64> @gather_2i64_constant_indices(ptr %ptr, <2 x i1> %mask) { ; X86-SKX-NEXT: kmovw %k0, %eax ; X86-SKX-NEXT: vpxor %xmm0, %xmm0, %xmm0 ; X86-SKX-NEXT: testb $1, %al -; X86-SKX-NEXT: jne .LBB58_1 -; X86-SKX-NEXT: # %bb.2: # %else -; X86-SKX-NEXT: testb $2, %al ; X86-SKX-NEXT: jne .LBB58_3 -; X86-SKX-NEXT: .LBB58_4: # %else2 +; X86-SKX-NEXT: # %bb.1: # %else +; X86-SKX-NEXT: testb $2, %al +; X86-SKX-NEXT: jne .LBB58_4 +; X86-SKX-NEXT: .LBB58_2: # %else2 ; X86-SKX-NEXT: retl -; X86-SKX-NEXT: .LBB58_1: # %cond.load +; X86-SKX-NEXT: .LBB58_3: # %cond.load ; X86-SKX-NEXT: vmovd %xmm1, %ecx ; X86-SKX-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero ; X86-SKX-NEXT: testb $2, %al -; X86-SKX-NEXT: je .LBB58_4 -; X86-SKX-NEXT: .LBB58_3: # %cond.load1 +; X86-SKX-NEXT: je .LBB58_2 +; X86-SKX-NEXT: .LBB58_4: # %cond.load1 ; X86-SKX-NEXT: vpextrd $1, %xmm1, %eax ; X86-SKX-NEXT: vpinsrd $2, (%eax), %xmm0, %xmm0 ; X86-SKX-NEXT: vpinsrd $3, 4(%eax), %xmm0, %xmm0 @@ -4234,19 +4234,19 @@ define void @scatter_2i64_constant_indices(ptr %ptr, <2 x i1> %mask, <2 x i32> % ; X64-KNL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; X64-KNL-NEXT: kmovw %k0, %eax ; X64-KNL-NEXT: testb $1, %al -; X64-KNL-NEXT: jne .LBB60_1 -; X64-KNL-NEXT: # %bb.2: # %else -; X64-KNL-NEXT: testb $2, %al ; X64-KNL-NEXT: jne .LBB60_3 -; X64-KNL-NEXT: .LBB60_4: # %else2 +; X64-KNL-NEXT: # %bb.1: # %else +; X64-KNL-NEXT: testb $2, %al +; X64-KNL-NEXT: jne .LBB60_4 +; X64-KNL-NEXT: .LBB60_2: # %else2 ; X64-KNL-NEXT: vzeroupper ; X64-KNL-NEXT: retq -; X64-KNL-NEXT: .LBB60_1: # %cond.store +; X64-KNL-NEXT: .LBB60_3: # %cond.store ; X64-KNL-NEXT: vmovq %xmm0, %rcx ; X64-KNL-NEXT: vmovss %xmm1, (%rcx) ; X64-KNL-NEXT: testb $2, %al -; X64-KNL-NEXT: je .LBB60_4 -; X64-KNL-NEXT: .LBB60_3: # %cond.store1 +; X64-KNL-NEXT: je .LBB60_2 +; X64-KNL-NEXT: .LBB60_4: # %cond.store1 ; X64-KNL-NEXT: vpextrq $1, %xmm0, %rax ; X64-KNL-NEXT: vextractps $1, %xmm1, (%rax) ; X64-KNL-NEXT: vzeroupper @@ -4260,19 +4260,19 @@ define void @scatter_2i64_constant_indices(ptr %ptr, <2 x i1> %mask, <2 x i32> % ; X86-KNL-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 ; X86-KNL-NEXT: kmovw %k0, %eax ; X86-KNL-NEXT: testb $1, %al -; X86-KNL-NEXT: jne .LBB60_1 -; X86-KNL-NEXT: # %bb.2: # %else -; X86-KNL-NEXT: testb $2, %al ; X86-KNL-NEXT: jne .LBB60_3 -; X86-KNL-NEXT: .LBB60_4: # %else2 +; X86-KNL-NEXT: # %bb.1: # %else +; X86-KNL-NEXT: testb $2, %al +; X86-KNL-NEXT: jne .LBB60_4 +; X86-KNL-NEXT: .LBB60_2: # %else2 ; X86-KNL-NEXT: vzeroupper ; X86-KNL-NEXT: retl -; X86-KNL-NEXT: .LBB60_1: # %cond.store +; X86-KNL-NEXT: .LBB60_3: # %cond.store ; X86-KNL-NEXT: vmovd %xmm0, %ecx ; X86-KNL-NEXT: vmovss %xmm1, (%ecx) ; X86-KNL-NEXT: testb $2, %al -; X86-KNL-NEXT: je .LBB60_4 -; X86-KNL-NEXT: .LBB60_3: # %cond.store1 +; X86-KNL-NEXT: je .LBB60_2 +; X86-KNL-NEXT: .LBB60_4: # %cond.store1 ; X86-KNL-NEXT: vpextrd $1, %xmm0, %eax ; X86-KNL-NEXT: vextractps $1, %xmm1, (%eax) ; X86-KNL-NEXT: vzeroupper @@ -4286,18 +4286,18 @@ define void @scatter_2i64_constant_indices(ptr %ptr, <2 x i1> %mask, <2 x i32> % ; X64-SKX-SMALL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; X64-SKX-SMALL-NEXT: kmovw %k0, %eax ; X64-SKX-SMALL-NEXT: testb $1, %al -; X64-SKX-SMALL-NEXT: jne .LBB60_1 -; X64-SKX-SMALL-NEXT: # %bb.2: # %else -; X64-SKX-SMALL-NEXT: testb $2, %al ; X64-SKX-SMALL-NEXT: jne .LBB60_3 -; X64-SKX-SMALL-NEXT: .LBB60_4: # %else2 +; X64-SKX-SMALL-NEXT: # %bb.1: # %else +; X64-SKX-SMALL-NEXT: testb $2, %al +; X64-SKX-SMALL-NEXT: jne .LBB60_4 +; X64-SKX-SMALL-NEXT: .LBB60_2: # %else2 ; X64-SKX-SMALL-NEXT: retq -; X64-SKX-SMALL-NEXT: .LBB60_1: # %cond.store +; X64-SKX-SMALL-NEXT: .LBB60_3: # %cond.store ; X64-SKX-SMALL-NEXT: vmovq %xmm0, %rcx ; X64-SKX-SMALL-NEXT: vmovss %xmm1, (%rcx) ; X64-SKX-SMALL-NEXT: testb $2, %al -; X64-SKX-SMALL-NEXT: je .LBB60_4 -; X64-SKX-SMALL-NEXT: .LBB60_3: # %cond.store1 +; X64-SKX-SMALL-NEXT: je .LBB60_2 +; X64-SKX-SMALL-NEXT: .LBB60_4: # %cond.store1 ; X64-SKX-SMALL-NEXT: vpextrq $1, %xmm0, %rax ; X64-SKX-SMALL-NEXT: vextractps $1, %xmm1, (%rax) ; X64-SKX-SMALL-NEXT: retq @@ -4311,18 +4311,18 @@ define void @scatter_2i64_constant_indices(ptr %ptr, <2 x i1> %mask, <2 x i32> % ; X64-SKX-LARGE-NEXT: vpaddq (%rax), %xmm0, %xmm0 ; X64-SKX-LARGE-NEXT: kmovw %k0, %eax ; X64-SKX-LARGE-NEXT: testb $1, %al -; X64-SKX-LARGE-NEXT: jne .LBB60_1 -; X64-SKX-LARGE-NEXT: # %bb.2: # %else -; X64-SKX-LARGE-NEXT: testb $2, %al ; X64-SKX-LARGE-NEXT: jne .LBB60_3 -; X64-SKX-LARGE-NEXT: .LBB60_4: # %else2 +; X64-SKX-LARGE-NEXT: # %bb.1: # %else +; X64-SKX-LARGE-NEXT: testb $2, %al +; X64-SKX-LARGE-NEXT: jne .LBB60_4 +; X64-SKX-LARGE-NEXT: .LBB60_2: # %else2 ; X64-SKX-LARGE-NEXT: retq -; X64-SKX-LARGE-NEXT: .LBB60_1: # %cond.store +; X64-SKX-LARGE-NEXT: .LBB60_3: # %cond.store ; X64-SKX-LARGE-NEXT: vmovq %xmm0, %rcx ; X64-SKX-LARGE-NEXT: vmovss %xmm1, (%rcx) ; X64-SKX-LARGE-NEXT: testb $2, %al -; X64-SKX-LARGE-NEXT: je .LBB60_4 -; X64-SKX-LARGE-NEXT: .LBB60_3: # %cond.store1 +; X64-SKX-LARGE-NEXT: je .LBB60_2 +; X64-SKX-LARGE-NEXT: .LBB60_4: # %cond.store1 ; X64-SKX-LARGE-NEXT: vpextrq $1, %xmm0, %rax ; X64-SKX-LARGE-NEXT: vextractps $1, %xmm1, (%rax) ; X64-SKX-LARGE-NEXT: retq @@ -4335,18 +4335,18 @@ define void @scatter_2i64_constant_indices(ptr %ptr, <2 x i1> %mask, <2 x i32> % ; X86-SKX-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 ; X86-SKX-NEXT: kmovw %k0, %eax ; X86-SKX-NEXT: testb $1, %al -; X86-SKX-NEXT: jne .LBB60_1 -; X86-SKX-NEXT: # %bb.2: # %else -; X86-SKX-NEXT: testb $2, %al ; X86-SKX-NEXT: jne .LBB60_3 -; X86-SKX-NEXT: .LBB60_4: # %else2 +; X86-SKX-NEXT: # %bb.1: # %else +; X86-SKX-NEXT: testb $2, %al +; X86-SKX-NEXT: jne .LBB60_4 +; X86-SKX-NEXT: .LBB60_2: # %else2 ; X86-SKX-NEXT: retl -; X86-SKX-NEXT: .LBB60_1: # %cond.store +; X86-SKX-NEXT: .LBB60_3: # %cond.store ; X86-SKX-NEXT: vmovd %xmm0, %ecx ; X86-SKX-NEXT: vmovss %xmm1, (%ecx) ; X86-SKX-NEXT: testb $2, %al -; X86-SKX-NEXT: je .LBB60_4 -; X86-SKX-NEXT: .LBB60_3: # %cond.store1 +; X86-SKX-NEXT: je .LBB60_2 +; X86-SKX-NEXT: .LBB60_4: # %cond.store1 ; X86-SKX-NEXT: vpextrd $1, %xmm0, %eax ; X86-SKX-NEXT: vextractps $1, %xmm1, (%eax) ; X86-SKX-NEXT: retl @@ -4435,20 +4435,20 @@ define <4 x i32> @splat_ptr_gather(ptr %ptr, <4 x i1> %mask, <4 x i32> %passthru ; X64-KNL-NEXT: .LBB62_4: # %else2 ; X64-KNL-NEXT: testb $4, %al ; X64-KNL-NEXT: vextracti128 $1, %ymm0, %xmm0 -; X64-KNL-NEXT: jne .LBB62_5 -; X64-KNL-NEXT: # %bb.6: # %else5 -; X64-KNL-NEXT: testb $8, %al ; X64-KNL-NEXT: jne .LBB62_7 -; X64-KNL-NEXT: .LBB62_8: # %else8 +; X64-KNL-NEXT: # %bb.5: # %else5 +; X64-KNL-NEXT: testb $8, %al +; X64-KNL-NEXT: jne .LBB62_8 +; X64-KNL-NEXT: .LBB62_6: # %else8 ; X64-KNL-NEXT: vmovdqa %xmm1, %xmm0 ; X64-KNL-NEXT: vzeroupper ; X64-KNL-NEXT: retq -; X64-KNL-NEXT: .LBB62_5: # %cond.load4 +; X64-KNL-NEXT: .LBB62_7: # %cond.load4 ; X64-KNL-NEXT: vmovq %xmm0, %rcx ; X64-KNL-NEXT: vpinsrd $2, (%rcx), %xmm1, %xmm1 ; X64-KNL-NEXT: testb $8, %al -; X64-KNL-NEXT: je .LBB62_8 -; X64-KNL-NEXT: .LBB62_7: # %cond.load7 +; X64-KNL-NEXT: je .LBB62_6 +; X64-KNL-NEXT: .LBB62_8: # %cond.load7 ; X64-KNL-NEXT: vpextrq $1, %xmm0, %rax ; X64-KNL-NEXT: vpinsrd $3, (%rax), %xmm1, %xmm1 ; X64-KNL-NEXT: vmovdqa %xmm1, %xmm0 @@ -4462,36 +4462,36 @@ define <4 x i32> @splat_ptr_gather(ptr %ptr, <4 x i1> %mask, <4 x i32> %passthru ; X86-KNL-NEXT: vpbroadcastd {{[0-9]+}}(%esp), %xmm0 ; X86-KNL-NEXT: kmovw %k0, %eax ; X86-KNL-NEXT: testb $1, %al -; X86-KNL-NEXT: jne .LBB62_1 -; X86-KNL-NEXT: # %bb.2: # %else +; X86-KNL-NEXT: jne .LBB62_5 +; X86-KNL-NEXT: # %bb.1: # %else ; X86-KNL-NEXT: testb $2, %al -; X86-KNL-NEXT: jne .LBB62_3 -; X86-KNL-NEXT: .LBB62_4: # %else2 +; X86-KNL-NEXT: jne .LBB62_6 +; X86-KNL-NEXT: .LBB62_2: # %else2 ; X86-KNL-NEXT: testb $4, %al -; X86-KNL-NEXT: jne .LBB62_5 -; X86-KNL-NEXT: .LBB62_6: # %else5 -; X86-KNL-NEXT: testb $8, %al ; X86-KNL-NEXT: jne .LBB62_7 -; X86-KNL-NEXT: .LBB62_8: # %else8 +; X86-KNL-NEXT: .LBB62_3: # %else5 +; X86-KNL-NEXT: testb $8, %al +; X86-KNL-NEXT: jne .LBB62_8 +; X86-KNL-NEXT: .LBB62_4: # %else8 ; X86-KNL-NEXT: vmovdqa %xmm1, %xmm0 ; X86-KNL-NEXT: vzeroupper ; X86-KNL-NEXT: retl -; X86-KNL-NEXT: .LBB62_1: # %cond.load +; X86-KNL-NEXT: .LBB62_5: # %cond.load ; X86-KNL-NEXT: vmovd %xmm0, %ecx ; X86-KNL-NEXT: vpinsrd $0, (%ecx), %xmm1, %xmm1 ; X86-KNL-NEXT: testb $2, %al -; X86-KNL-NEXT: je .LBB62_4 -; X86-KNL-NEXT: .LBB62_3: # %cond.load1 +; X86-KNL-NEXT: je .LBB62_2 +; X86-KNL-NEXT: .LBB62_6: # %cond.load1 ; X86-KNL-NEXT: vpextrd $1, %xmm0, %ecx ; X86-KNL-NEXT: vpinsrd $1, (%ecx), %xmm1, %xmm1 ; X86-KNL-NEXT: testb $4, %al -; X86-KNL-NEXT: je .LBB62_6 -; X86-KNL-NEXT: .LBB62_5: # %cond.load4 +; X86-KNL-NEXT: je .LBB62_3 +; X86-KNL-NEXT: .LBB62_7: # %cond.load4 ; X86-KNL-NEXT: vpextrd $2, %xmm0, %ecx ; X86-KNL-NEXT: vpinsrd $2, (%ecx), %xmm1, %xmm1 ; X86-KNL-NEXT: testb $8, %al -; X86-KNL-NEXT: je .LBB62_8 -; X86-KNL-NEXT: .LBB62_7: # %cond.load7 +; X86-KNL-NEXT: je .LBB62_4 +; X86-KNL-NEXT: .LBB62_8: # %cond.load7 ; X86-KNL-NEXT: vpextrd $3, %xmm0, %eax ; X86-KNL-NEXT: vpinsrd $3, (%eax), %xmm1, %xmm1 ; X86-KNL-NEXT: vmovdqa %xmm1, %xmm0 @@ -4545,19 +4545,19 @@ define void @splat_ptr_scatter(ptr %ptr, <4 x i1> %mask, <4 x i32> %val) { ; X64-KNL-NEXT: .LBB63_4: # %else2 ; X64-KNL-NEXT: testb $4, %al ; X64-KNL-NEXT: vextracti128 $1, %ymm0, %xmm0 -; X64-KNL-NEXT: jne .LBB63_5 -; X64-KNL-NEXT: # %bb.6: # %else4 -; X64-KNL-NEXT: testb $8, %al ; X64-KNL-NEXT: jne .LBB63_7 -; X64-KNL-NEXT: .LBB63_8: # %else6 +; X64-KNL-NEXT: # %bb.5: # %else4 +; X64-KNL-NEXT: testb $8, %al +; X64-KNL-NEXT: jne .LBB63_8 +; X64-KNL-NEXT: .LBB63_6: # %else6 ; X64-KNL-NEXT: vzeroupper ; X64-KNL-NEXT: retq -; X64-KNL-NEXT: .LBB63_5: # %cond.store3 +; X64-KNL-NEXT: .LBB63_7: # %cond.store3 ; X64-KNL-NEXT: vmovq %xmm0, %rcx ; X64-KNL-NEXT: vextractps $2, %xmm1, (%rcx) ; X64-KNL-NEXT: testb $8, %al -; X64-KNL-NEXT: je .LBB63_8 -; X64-KNL-NEXT: .LBB63_7: # %cond.store5 +; X64-KNL-NEXT: je .LBB63_6 +; X64-KNL-NEXT: .LBB63_8: # %cond.store5 ; X64-KNL-NEXT: vpextrq $1, %xmm0, %rax ; X64-KNL-NEXT: vextractps $3, %xmm1, (%rax) ; X64-KNL-NEXT: vzeroupper @@ -4570,35 +4570,35 @@ define void @splat_ptr_scatter(ptr %ptr, <4 x i1> %mask, <4 x i32> %val) { ; X86-KNL-NEXT: vpbroadcastd {{[0-9]+}}(%esp), %xmm0 ; X86-KNL-NEXT: kmovw %k0, %eax ; X86-KNL-NEXT: testb $1, %al -; X86-KNL-NEXT: jne .LBB63_1 -; X86-KNL-NEXT: # %bb.2: # %else +; X86-KNL-NEXT: jne .LBB63_5 +; X86-KNL-NEXT: # %bb.1: # %else ; X86-KNL-NEXT: testb $2, %al -; X86-KNL-NEXT: jne .LBB63_3 -; X86-KNL-NEXT: .LBB63_4: # %else2 +; X86-KNL-NEXT: jne .LBB63_6 +; X86-KNL-NEXT: .LBB63_2: # %else2 ; X86-KNL-NEXT: testb $4, %al -; X86-KNL-NEXT: jne .LBB63_5 -; X86-KNL-NEXT: .LBB63_6: # %else4 -; X86-KNL-NEXT: testb $8, %al ; X86-KNL-NEXT: jne .LBB63_7 -; X86-KNL-NEXT: .LBB63_8: # %else6 +; X86-KNL-NEXT: .LBB63_3: # %else4 +; X86-KNL-NEXT: testb $8, %al +; X86-KNL-NEXT: jne .LBB63_8 +; X86-KNL-NEXT: .LBB63_4: # %else6 ; X86-KNL-NEXT: vzeroupper ; X86-KNL-NEXT: retl -; X86-KNL-NEXT: .LBB63_1: # %cond.store +; X86-KNL-NEXT: .LBB63_5: # %cond.store ; X86-KNL-NEXT: vmovd %xmm0, %ecx ; X86-KNL-NEXT: vmovss %xmm1, (%ecx) ; X86-KNL-NEXT: testb $2, %al -; X86-KNL-NEXT: je .LBB63_4 -; X86-KNL-NEXT: .LBB63_3: # %cond.store1 +; X86-KNL-NEXT: je .LBB63_2 +; X86-KNL-NEXT: .LBB63_6: # %cond.store1 ; X86-KNL-NEXT: vpextrd $1, %xmm0, %ecx ; X86-KNL-NEXT: vextractps $1, %xmm1, (%ecx) ; X86-KNL-NEXT: testb $4, %al -; X86-KNL-NEXT: je .LBB63_6 -; X86-KNL-NEXT: .LBB63_5: # %cond.store3 +; X86-KNL-NEXT: je .LBB63_3 +; X86-KNL-NEXT: .LBB63_7: # %cond.store3 ; X86-KNL-NEXT: vpextrd $2, %xmm0, %ecx ; X86-KNL-NEXT: vextractps $2, %xmm1, (%ecx) ; X86-KNL-NEXT: testb $8, %al -; X86-KNL-NEXT: je .LBB63_8 -; X86-KNL-NEXT: .LBB63_7: # %cond.store5 +; X86-KNL-NEXT: je .LBB63_4 +; X86-KNL-NEXT: .LBB63_8: # %cond.store5 ; X86-KNL-NEXT: vpextrd $3, %xmm0, %eax ; X86-KNL-NEXT: vextractps $3, %xmm1, (%eax) ; X86-KNL-NEXT: vzeroupper diff --git a/llvm/test/CodeGen/X86/masked_gather_scatter_widen.ll b/llvm/test/CodeGen/X86/masked_gather_scatter_widen.ll index 5b5280601ea71..447e85fdbf715 100644 --- a/llvm/test/CodeGen/X86/masked_gather_scatter_widen.ll +++ b/llvm/test/CodeGen/X86/masked_gather_scatter_widen.ll @@ -14,19 +14,19 @@ define <2 x double> @test_gather_v2i32_index(ptr %base, <2 x i32> %ind, <2 x i1> ; WIDEN_SKX-NEXT: vpaddq %xmm0, %xmm1, %xmm0 ; WIDEN_SKX-NEXT: kmovw %k0, %eax ; WIDEN_SKX-NEXT: testb $1, %al -; WIDEN_SKX-NEXT: jne .LBB0_1 -; WIDEN_SKX-NEXT: # %bb.2: # %else -; WIDEN_SKX-NEXT: testb $2, %al ; WIDEN_SKX-NEXT: jne .LBB0_3 -; WIDEN_SKX-NEXT: .LBB0_4: # %else2 +; WIDEN_SKX-NEXT: # %bb.1: # %else +; WIDEN_SKX-NEXT: testb $2, %al +; WIDEN_SKX-NEXT: jne .LBB0_4 +; WIDEN_SKX-NEXT: .LBB0_2: # %else2 ; WIDEN_SKX-NEXT: vmovaps %xmm2, %xmm0 ; WIDEN_SKX-NEXT: retq -; WIDEN_SKX-NEXT: .LBB0_1: # %cond.load +; WIDEN_SKX-NEXT: .LBB0_3: # %cond.load ; WIDEN_SKX-NEXT: vmovq %xmm0, %rcx ; WIDEN_SKX-NEXT: vmovlps {{.*#+}} xmm2 = mem[0,1],xmm2[2,3] ; WIDEN_SKX-NEXT: testb $2, %al -; WIDEN_SKX-NEXT: je .LBB0_4 -; WIDEN_SKX-NEXT: .LBB0_3: # %cond.load1 +; WIDEN_SKX-NEXT: je .LBB0_2 +; WIDEN_SKX-NEXT: .LBB0_4: # %cond.load1 ; WIDEN_SKX-NEXT: vpextrq $1, %xmm0, %rax ; WIDEN_SKX-NEXT: vmovhps {{.*#+}} xmm2 = xmm2[0,1],mem[0,1] ; WIDEN_SKX-NEXT: vmovaps %xmm2, %xmm0 @@ -43,20 +43,20 @@ define <2 x double> @test_gather_v2i32_index(ptr %base, <2 x i32> %ind, <2 x i1> ; WIDEN_KNL-NEXT: vpaddq %xmm0, %xmm1, %xmm0 ; WIDEN_KNL-NEXT: kmovw %k0, %eax ; WIDEN_KNL-NEXT: testb $1, %al -; WIDEN_KNL-NEXT: jne .LBB0_1 -; WIDEN_KNL-NEXT: # %bb.2: # %else -; WIDEN_KNL-NEXT: testb $2, %al ; WIDEN_KNL-NEXT: jne .LBB0_3 -; WIDEN_KNL-NEXT: .LBB0_4: # %else2 +; WIDEN_KNL-NEXT: # %bb.1: # %else +; WIDEN_KNL-NEXT: testb $2, %al +; WIDEN_KNL-NEXT: jne .LBB0_4 +; WIDEN_KNL-NEXT: .LBB0_2: # %else2 ; WIDEN_KNL-NEXT: vmovaps %xmm2, %xmm0 ; WIDEN_KNL-NEXT: vzeroupper ; WIDEN_KNL-NEXT: retq -; WIDEN_KNL-NEXT: .LBB0_1: # %cond.load +; WIDEN_KNL-NEXT: .LBB0_3: # %cond.load ; WIDEN_KNL-NEXT: vmovq %xmm0, %rcx ; WIDEN_KNL-NEXT: vmovlps {{.*#+}} xmm2 = mem[0,1],xmm2[2,3] ; WIDEN_KNL-NEXT: testb $2, %al -; WIDEN_KNL-NEXT: je .LBB0_4 -; WIDEN_KNL-NEXT: .LBB0_3: # %cond.load1 +; WIDEN_KNL-NEXT: je .LBB0_2 +; WIDEN_KNL-NEXT: .LBB0_4: # %cond.load1 ; WIDEN_KNL-NEXT: vpextrq $1, %xmm0, %rax ; WIDEN_KNL-NEXT: vmovhps {{.*#+}} xmm2 = xmm2[0,1],mem[0,1] ; WIDEN_KNL-NEXT: vmovaps %xmm2, %xmm0 @@ -85,18 +85,18 @@ define void @test_scatter_v2i32_index(<2 x double> %a1, ptr %base, <2 x i32> %in ; WIDEN_SKX-NEXT: vpaddq %xmm1, %xmm2, %xmm1 ; WIDEN_SKX-NEXT: kmovw %k0, %eax ; WIDEN_SKX-NEXT: testb $1, %al -; WIDEN_SKX-NEXT: jne .LBB1_1 -; WIDEN_SKX-NEXT: # %bb.2: # %else -; WIDEN_SKX-NEXT: testb $2, %al ; WIDEN_SKX-NEXT: jne .LBB1_3 -; WIDEN_SKX-NEXT: .LBB1_4: # %else2 +; WIDEN_SKX-NEXT: # %bb.1: # %else +; WIDEN_SKX-NEXT: testb $2, %al +; WIDEN_SKX-NEXT: jne .LBB1_4 +; WIDEN_SKX-NEXT: .LBB1_2: # %else2 ; WIDEN_SKX-NEXT: retq -; WIDEN_SKX-NEXT: .LBB1_1: # %cond.store +; WIDEN_SKX-NEXT: .LBB1_3: # %cond.store ; WIDEN_SKX-NEXT: vmovq %xmm1, %rcx ; WIDEN_SKX-NEXT: vmovlps %xmm0, (%rcx) ; WIDEN_SKX-NEXT: testb $2, %al -; WIDEN_SKX-NEXT: je .LBB1_4 -; WIDEN_SKX-NEXT: .LBB1_3: # %cond.store1 +; WIDEN_SKX-NEXT: je .LBB1_2 +; WIDEN_SKX-NEXT: .LBB1_4: # %cond.store1 ; WIDEN_SKX-NEXT: vpextrq $1, %xmm1, %rax ; WIDEN_SKX-NEXT: vmovhps %xmm0, (%rax) ; WIDEN_SKX-NEXT: retq @@ -112,19 +112,19 @@ define void @test_scatter_v2i32_index(<2 x double> %a1, ptr %base, <2 x i32> %in ; WIDEN_KNL-NEXT: vpaddq %xmm1, %xmm2, %xmm1 ; WIDEN_KNL-NEXT: kmovw %k0, %eax ; WIDEN_KNL-NEXT: testb $1, %al -; WIDEN_KNL-NEXT: jne .LBB1_1 -; WIDEN_KNL-NEXT: # %bb.2: # %else -; WIDEN_KNL-NEXT: testb $2, %al ; WIDEN_KNL-NEXT: jne .LBB1_3 -; WIDEN_KNL-NEXT: .LBB1_4: # %else2 +; WIDEN_KNL-NEXT: # %bb.1: # %else +; WIDEN_KNL-NEXT: testb $2, %al +; WIDEN_KNL-NEXT: jne .LBB1_4 +; WIDEN_KNL-NEXT: .LBB1_2: # %else2 ; WIDEN_KNL-NEXT: vzeroupper ; WIDEN_KNL-NEXT: retq -; WIDEN_KNL-NEXT: .LBB1_1: # %cond.store +; WIDEN_KNL-NEXT: .LBB1_3: # %cond.store ; WIDEN_KNL-NEXT: vmovq %xmm1, %rcx ; WIDEN_KNL-NEXT: vmovlps %xmm0, (%rcx) ; WIDEN_KNL-NEXT: testb $2, %al -; WIDEN_KNL-NEXT: je .LBB1_4 -; WIDEN_KNL-NEXT: .LBB1_3: # %cond.store1 +; WIDEN_KNL-NEXT: je .LBB1_2 +; WIDEN_KNL-NEXT: .LBB1_4: # %cond.store1 ; WIDEN_KNL-NEXT: vpextrq $1, %xmm1, %rax ; WIDEN_KNL-NEXT: vmovhps %xmm0, (%rax) ; WIDEN_KNL-NEXT: vzeroupper @@ -140,18 +140,18 @@ define void @test_scatter_v2i32_index(<2 x double> %a1, ptr %base, <2 x i32> %in ; WIDEN_AVX2-NEXT: vpsllq $63, %xmm2, %xmm2 ; WIDEN_AVX2-NEXT: vmovmskpd %xmm2, %eax ; WIDEN_AVX2-NEXT: testb $1, %al -; WIDEN_AVX2-NEXT: jne .LBB1_1 -; WIDEN_AVX2-NEXT: # %bb.2: # %else -; WIDEN_AVX2-NEXT: testb $2, %al ; WIDEN_AVX2-NEXT: jne .LBB1_3 -; WIDEN_AVX2-NEXT: .LBB1_4: # %else2 +; WIDEN_AVX2-NEXT: # %bb.1: # %else +; WIDEN_AVX2-NEXT: testb $2, %al +; WIDEN_AVX2-NEXT: jne .LBB1_4 +; WIDEN_AVX2-NEXT: .LBB1_2: # %else2 ; WIDEN_AVX2-NEXT: retq -; WIDEN_AVX2-NEXT: .LBB1_1: # %cond.store +; WIDEN_AVX2-NEXT: .LBB1_3: # %cond.store ; WIDEN_AVX2-NEXT: vmovq %xmm1, %rcx ; WIDEN_AVX2-NEXT: vmovlps %xmm0, (%rcx) ; WIDEN_AVX2-NEXT: testb $2, %al -; WIDEN_AVX2-NEXT: je .LBB1_4 -; WIDEN_AVX2-NEXT: .LBB1_3: # %cond.store1 +; WIDEN_AVX2-NEXT: je .LBB1_2 +; WIDEN_AVX2-NEXT: .LBB1_4: # %cond.store1 ; WIDEN_AVX2-NEXT: vpextrq $1, %xmm1, %rax ; WIDEN_AVX2-NEXT: vmovhps %xmm0, (%rax) ; WIDEN_AVX2-NEXT: retq @@ -166,19 +166,19 @@ define <2 x i32> @test_gather_v2i32_data(<2 x ptr> %ptr, <2 x i1> %mask, <2 x i3 ; WIDEN_SKX-NEXT: vpsllq $63, %xmm1, %xmm1 ; WIDEN_SKX-NEXT: vmovmskpd %xmm1, %eax ; WIDEN_SKX-NEXT: testb $1, %al -; WIDEN_SKX-NEXT: jne .LBB2_1 -; WIDEN_SKX-NEXT: # %bb.2: # %else -; WIDEN_SKX-NEXT: testb $2, %al ; WIDEN_SKX-NEXT: jne .LBB2_3 -; WIDEN_SKX-NEXT: .LBB2_4: # %else2 +; WIDEN_SKX-NEXT: # %bb.1: # %else +; WIDEN_SKX-NEXT: testb $2, %al +; WIDEN_SKX-NEXT: jne .LBB2_4 +; WIDEN_SKX-NEXT: .LBB2_2: # %else2 ; WIDEN_SKX-NEXT: vmovdqa %xmm2, %xmm0 ; WIDEN_SKX-NEXT: retq -; WIDEN_SKX-NEXT: .LBB2_1: # %cond.load +; WIDEN_SKX-NEXT: .LBB2_3: # %cond.load ; WIDEN_SKX-NEXT: vmovq %xmm0, %rcx ; WIDEN_SKX-NEXT: vpinsrd $0, (%rcx), %xmm2, %xmm2 ; WIDEN_SKX-NEXT: testb $2, %al -; WIDEN_SKX-NEXT: je .LBB2_4 -; WIDEN_SKX-NEXT: .LBB2_3: # %cond.load1 +; WIDEN_SKX-NEXT: je .LBB2_2 +; WIDEN_SKX-NEXT: .LBB2_4: # %cond.load1 ; WIDEN_SKX-NEXT: vpextrq $1, %xmm0, %rax ; WIDEN_SKX-NEXT: vpinsrd $1, (%rax), %xmm2, %xmm2 ; WIDEN_SKX-NEXT: vmovdqa %xmm2, %xmm0 @@ -190,20 +190,20 @@ define <2 x i32> @test_gather_v2i32_data(<2 x ptr> %ptr, <2 x i1> %mask, <2 x i3 ; WIDEN_KNL-NEXT: vptestmq %zmm1, %zmm1, %k0 ; WIDEN_KNL-NEXT: kmovw %k0, %eax ; WIDEN_KNL-NEXT: testb $1, %al -; WIDEN_KNL-NEXT: jne .LBB2_1 -; WIDEN_KNL-NEXT: # %bb.2: # %else -; WIDEN_KNL-NEXT: testb $2, %al ; WIDEN_KNL-NEXT: jne .LBB2_3 -; WIDEN_KNL-NEXT: .LBB2_4: # %else2 +; WIDEN_KNL-NEXT: # %bb.1: # %else +; WIDEN_KNL-NEXT: testb $2, %al +; WIDEN_KNL-NEXT: jne .LBB2_4 +; WIDEN_KNL-NEXT: .LBB2_2: # %else2 ; WIDEN_KNL-NEXT: vmovdqa %xmm2, %xmm0 ; WIDEN_KNL-NEXT: vzeroupper ; WIDEN_KNL-NEXT: retq -; WIDEN_KNL-NEXT: .LBB2_1: # %cond.load +; WIDEN_KNL-NEXT: .LBB2_3: # %cond.load ; WIDEN_KNL-NEXT: vmovq %xmm0, %rcx ; WIDEN_KNL-NEXT: vpinsrd $0, (%rcx), %xmm2, %xmm2 ; WIDEN_KNL-NEXT: testb $2, %al -; WIDEN_KNL-NEXT: je .LBB2_4 -; WIDEN_KNL-NEXT: .LBB2_3: # %cond.load1 +; WIDEN_KNL-NEXT: je .LBB2_2 +; WIDEN_KNL-NEXT: .LBB2_4: # %cond.load1 ; WIDEN_KNL-NEXT: vpextrq $1, %xmm0, %rax ; WIDEN_KNL-NEXT: vpinsrd $1, (%rax), %xmm2, %xmm2 ; WIDEN_KNL-NEXT: vmovdqa %xmm2, %xmm0 @@ -227,18 +227,18 @@ define void @test_scatter_v2i32_data(<2 x i32>%a1, <2 x ptr> %ptr, <2 x i1>%mask ; WIDEN_SKX-NEXT: vpsllq $63, %xmm2, %xmm2 ; WIDEN_SKX-NEXT: vmovmskpd %xmm2, %eax ; WIDEN_SKX-NEXT: testb $1, %al -; WIDEN_SKX-NEXT: jne .LBB3_1 -; WIDEN_SKX-NEXT: # %bb.2: # %else -; WIDEN_SKX-NEXT: testb $2, %al ; WIDEN_SKX-NEXT: jne .LBB3_3 -; WIDEN_SKX-NEXT: .LBB3_4: # %else2 +; WIDEN_SKX-NEXT: # %bb.1: # %else +; WIDEN_SKX-NEXT: testb $2, %al +; WIDEN_SKX-NEXT: jne .LBB3_4 +; WIDEN_SKX-NEXT: .LBB3_2: # %else2 ; WIDEN_SKX-NEXT: retq -; WIDEN_SKX-NEXT: .LBB3_1: # %cond.store +; WIDEN_SKX-NEXT: .LBB3_3: # %cond.store ; WIDEN_SKX-NEXT: vmovq %xmm1, %rcx ; WIDEN_SKX-NEXT: vmovss %xmm0, (%rcx) ; WIDEN_SKX-NEXT: testb $2, %al -; WIDEN_SKX-NEXT: je .LBB3_4 -; WIDEN_SKX-NEXT: .LBB3_3: # %cond.store1 +; WIDEN_SKX-NEXT: je .LBB3_2 +; WIDEN_SKX-NEXT: .LBB3_4: # %cond.store1 ; WIDEN_SKX-NEXT: vpextrq $1, %xmm1, %rax ; WIDEN_SKX-NEXT: vextractps $1, %xmm0, (%rax) ; WIDEN_SKX-NEXT: retq @@ -249,19 +249,19 @@ define void @test_scatter_v2i32_data(<2 x i32>%a1, <2 x ptr> %ptr, <2 x i1>%mask ; WIDEN_KNL-NEXT: vptestmq %zmm2, %zmm2, %k0 ; WIDEN_KNL-NEXT: kmovw %k0, %eax ; WIDEN_KNL-NEXT: testb $1, %al -; WIDEN_KNL-NEXT: jne .LBB3_1 -; WIDEN_KNL-NEXT: # %bb.2: # %else -; WIDEN_KNL-NEXT: testb $2, %al ; WIDEN_KNL-NEXT: jne .LBB3_3 -; WIDEN_KNL-NEXT: .LBB3_4: # %else2 +; WIDEN_KNL-NEXT: # %bb.1: # %else +; WIDEN_KNL-NEXT: testb $2, %al +; WIDEN_KNL-NEXT: jne .LBB3_4 +; WIDEN_KNL-NEXT: .LBB3_2: # %else2 ; WIDEN_KNL-NEXT: vzeroupper ; WIDEN_KNL-NEXT: retq -; WIDEN_KNL-NEXT: .LBB3_1: # %cond.store +; WIDEN_KNL-NEXT: .LBB3_3: # %cond.store ; WIDEN_KNL-NEXT: vmovq %xmm1, %rcx ; WIDEN_KNL-NEXT: vmovss %xmm0, (%rcx) ; WIDEN_KNL-NEXT: testb $2, %al -; WIDEN_KNL-NEXT: je .LBB3_4 -; WIDEN_KNL-NEXT: .LBB3_3: # %cond.store1 +; WIDEN_KNL-NEXT: je .LBB3_2 +; WIDEN_KNL-NEXT: .LBB3_4: # %cond.store1 ; WIDEN_KNL-NEXT: vpextrq $1, %xmm1, %rax ; WIDEN_KNL-NEXT: vextractps $1, %xmm0, (%rax) ; WIDEN_KNL-NEXT: vzeroupper @@ -272,18 +272,18 @@ define void @test_scatter_v2i32_data(<2 x i32>%a1, <2 x ptr> %ptr, <2 x i1>%mask ; WIDEN_AVX2-NEXT: vpsllq $63, %xmm2, %xmm2 ; WIDEN_AVX2-NEXT: vmovmskpd %xmm2, %eax ; WIDEN_AVX2-NEXT: testb $1, %al -; WIDEN_AVX2-NEXT: jne .LBB3_1 -; WIDEN_AVX2-NEXT: # %bb.2: # %else -; WIDEN_AVX2-NEXT: testb $2, %al ; WIDEN_AVX2-NEXT: jne .LBB3_3 -; WIDEN_AVX2-NEXT: .LBB3_4: # %else2 +; WIDEN_AVX2-NEXT: # %bb.1: # %else +; WIDEN_AVX2-NEXT: testb $2, %al +; WIDEN_AVX2-NEXT: jne .LBB3_4 +; WIDEN_AVX2-NEXT: .LBB3_2: # %else2 ; WIDEN_AVX2-NEXT: retq -; WIDEN_AVX2-NEXT: .LBB3_1: # %cond.store +; WIDEN_AVX2-NEXT: .LBB3_3: # %cond.store ; WIDEN_AVX2-NEXT: vmovq %xmm1, %rcx ; WIDEN_AVX2-NEXT: vmovss %xmm0, (%rcx) ; WIDEN_AVX2-NEXT: testb $2, %al -; WIDEN_AVX2-NEXT: je .LBB3_4 -; WIDEN_AVX2-NEXT: .LBB3_3: # %cond.store1 +; WIDEN_AVX2-NEXT: je .LBB3_2 +; WIDEN_AVX2-NEXT: .LBB3_4: # %cond.store1 ; WIDEN_AVX2-NEXT: vpextrq $1, %xmm1, %rax ; WIDEN_AVX2-NEXT: vextractps $1, %xmm0, (%rax) ; WIDEN_AVX2-NEXT: retq @@ -302,19 +302,19 @@ define <2 x i32> @test_gather_v2i32_data_index(ptr %base, <2 x i32> %ind, <2 x i ; WIDEN_SKX-NEXT: vpaddq %xmm0, %xmm1, %xmm0 ; WIDEN_SKX-NEXT: kmovw %k0, %eax ; WIDEN_SKX-NEXT: testb $1, %al -; WIDEN_SKX-NEXT: jne .LBB4_1 -; WIDEN_SKX-NEXT: # %bb.2: # %else -; WIDEN_SKX-NEXT: testb $2, %al ; WIDEN_SKX-NEXT: jne .LBB4_3 -; WIDEN_SKX-NEXT: .LBB4_4: # %else2 +; WIDEN_SKX-NEXT: # %bb.1: # %else +; WIDEN_SKX-NEXT: testb $2, %al +; WIDEN_SKX-NEXT: jne .LBB4_4 +; WIDEN_SKX-NEXT: .LBB4_2: # %else2 ; WIDEN_SKX-NEXT: vmovdqa %xmm2, %xmm0 ; WIDEN_SKX-NEXT: retq -; WIDEN_SKX-NEXT: .LBB4_1: # %cond.load +; WIDEN_SKX-NEXT: .LBB4_3: # %cond.load ; WIDEN_SKX-NEXT: vmovq %xmm0, %rcx ; WIDEN_SKX-NEXT: vpinsrd $0, (%rcx), %xmm2, %xmm2 ; WIDEN_SKX-NEXT: testb $2, %al -; WIDEN_SKX-NEXT: je .LBB4_4 -; WIDEN_SKX-NEXT: .LBB4_3: # %cond.load1 +; WIDEN_SKX-NEXT: je .LBB4_2 +; WIDEN_SKX-NEXT: .LBB4_4: # %cond.load1 ; WIDEN_SKX-NEXT: vpextrq $1, %xmm0, %rax ; WIDEN_SKX-NEXT: vpinsrd $1, (%rax), %xmm2, %xmm2 ; WIDEN_SKX-NEXT: vmovdqa %xmm2, %xmm0 @@ -331,20 +331,20 @@ define <2 x i32> @test_gather_v2i32_data_index(ptr %base, <2 x i32> %ind, <2 x i ; WIDEN_KNL-NEXT: vpaddq %xmm0, %xmm1, %xmm0 ; WIDEN_KNL-NEXT: kmovw %k0, %eax ; WIDEN_KNL-NEXT: testb $1, %al -; WIDEN_KNL-NEXT: jne .LBB4_1 -; WIDEN_KNL-NEXT: # %bb.2: # %else -; WIDEN_KNL-NEXT: testb $2, %al ; WIDEN_KNL-NEXT: jne .LBB4_3 -; WIDEN_KNL-NEXT: .LBB4_4: # %else2 +; WIDEN_KNL-NEXT: # %bb.1: # %else +; WIDEN_KNL-NEXT: testb $2, %al +; WIDEN_KNL-NEXT: jne .LBB4_4 +; WIDEN_KNL-NEXT: .LBB4_2: # %else2 ; WIDEN_KNL-NEXT: vmovdqa %xmm2, %xmm0 ; WIDEN_KNL-NEXT: vzeroupper ; WIDEN_KNL-NEXT: retq -; WIDEN_KNL-NEXT: .LBB4_1: # %cond.load +; WIDEN_KNL-NEXT: .LBB4_3: # %cond.load ; WIDEN_KNL-NEXT: vmovq %xmm0, %rcx ; WIDEN_KNL-NEXT: vpinsrd $0, (%rcx), %xmm2, %xmm2 ; WIDEN_KNL-NEXT: testb $2, %al -; WIDEN_KNL-NEXT: je .LBB4_4 -; WIDEN_KNL-NEXT: .LBB4_3: # %cond.load1 +; WIDEN_KNL-NEXT: je .LBB4_2 +; WIDEN_KNL-NEXT: .LBB4_4: # %cond.load1 ; WIDEN_KNL-NEXT: vpextrq $1, %xmm0, %rax ; WIDEN_KNL-NEXT: vpinsrd $1, (%rax), %xmm2, %xmm2 ; WIDEN_KNL-NEXT: vmovdqa %xmm2, %xmm0 @@ -374,18 +374,18 @@ define void @test_scatter_v2i32_data_index(<2 x i32> %a1, ptr %base, <2 x i32> % ; WIDEN_SKX-NEXT: vpaddq %xmm1, %xmm2, %xmm1 ; WIDEN_SKX-NEXT: kmovw %k0, %eax ; WIDEN_SKX-NEXT: testb $1, %al -; WIDEN_SKX-NEXT: jne .LBB5_1 -; WIDEN_SKX-NEXT: # %bb.2: # %else -; WIDEN_SKX-NEXT: testb $2, %al ; WIDEN_SKX-NEXT: jne .LBB5_3 -; WIDEN_SKX-NEXT: .LBB5_4: # %else2 +; WIDEN_SKX-NEXT: # %bb.1: # %else +; WIDEN_SKX-NEXT: testb $2, %al +; WIDEN_SKX-NEXT: jne .LBB5_4 +; WIDEN_SKX-NEXT: .LBB5_2: # %else2 ; WIDEN_SKX-NEXT: retq -; WIDEN_SKX-NEXT: .LBB5_1: # %cond.store +; WIDEN_SKX-NEXT: .LBB5_3: # %cond.store ; WIDEN_SKX-NEXT: vmovq %xmm1, %rcx ; WIDEN_SKX-NEXT: vmovss %xmm0, (%rcx) ; WIDEN_SKX-NEXT: testb $2, %al -; WIDEN_SKX-NEXT: je .LBB5_4 -; WIDEN_SKX-NEXT: .LBB5_3: # %cond.store1 +; WIDEN_SKX-NEXT: je .LBB5_2 +; WIDEN_SKX-NEXT: .LBB5_4: # %cond.store1 ; WIDEN_SKX-NEXT: vpextrq $1, %xmm1, %rax ; WIDEN_SKX-NEXT: vextractps $1, %xmm0, (%rax) ; WIDEN_SKX-NEXT: retq @@ -401,19 +401,19 @@ define void @test_scatter_v2i32_data_index(<2 x i32> %a1, ptr %base, <2 x i32> % ; WIDEN_KNL-NEXT: vpaddq %xmm1, %xmm2, %xmm1 ; WIDEN_KNL-NEXT: kmovw %k0, %eax ; WIDEN_KNL-NEXT: testb $1, %al -; WIDEN_KNL-NEXT: jne .LBB5_1 -; WIDEN_KNL-NEXT: # %bb.2: # %else -; WIDEN_KNL-NEXT: testb $2, %al ; WIDEN_KNL-NEXT: jne .LBB5_3 -; WIDEN_KNL-NEXT: .LBB5_4: # %else2 +; WIDEN_KNL-NEXT: # %bb.1: # %else +; WIDEN_KNL-NEXT: testb $2, %al +; WIDEN_KNL-NEXT: jne .LBB5_4 +; WIDEN_KNL-NEXT: .LBB5_2: # %else2 ; WIDEN_KNL-NEXT: vzeroupper ; WIDEN_KNL-NEXT: retq -; WIDEN_KNL-NEXT: .LBB5_1: # %cond.store +; WIDEN_KNL-NEXT: .LBB5_3: # %cond.store ; WIDEN_KNL-NEXT: vmovq %xmm1, %rcx ; WIDEN_KNL-NEXT: vmovss %xmm0, (%rcx) ; WIDEN_KNL-NEXT: testb $2, %al -; WIDEN_KNL-NEXT: je .LBB5_4 -; WIDEN_KNL-NEXT: .LBB5_3: # %cond.store1 +; WIDEN_KNL-NEXT: je .LBB5_2 +; WIDEN_KNL-NEXT: .LBB5_4: # %cond.store1 ; WIDEN_KNL-NEXT: vpextrq $1, %xmm1, %rax ; WIDEN_KNL-NEXT: vextractps $1, %xmm0, (%rax) ; WIDEN_KNL-NEXT: vzeroupper @@ -429,18 +429,18 @@ define void @test_scatter_v2i32_data_index(<2 x i32> %a1, ptr %base, <2 x i32> % ; WIDEN_AVX2-NEXT: vpsllq $63, %xmm2, %xmm2 ; WIDEN_AVX2-NEXT: vmovmskpd %xmm2, %eax ; WIDEN_AVX2-NEXT: testb $1, %al -; WIDEN_AVX2-NEXT: jne .LBB5_1 -; WIDEN_AVX2-NEXT: # %bb.2: # %else -; WIDEN_AVX2-NEXT: testb $2, %al ; WIDEN_AVX2-NEXT: jne .LBB5_3 -; WIDEN_AVX2-NEXT: .LBB5_4: # %else2 +; WIDEN_AVX2-NEXT: # %bb.1: # %else +; WIDEN_AVX2-NEXT: testb $2, %al +; WIDEN_AVX2-NEXT: jne .LBB5_4 +; WIDEN_AVX2-NEXT: .LBB5_2: # %else2 ; WIDEN_AVX2-NEXT: retq -; WIDEN_AVX2-NEXT: .LBB5_1: # %cond.store +; WIDEN_AVX2-NEXT: .LBB5_3: # %cond.store ; WIDEN_AVX2-NEXT: vmovq %xmm1, %rcx ; WIDEN_AVX2-NEXT: vmovss %xmm0, (%rcx) ; WIDEN_AVX2-NEXT: testb $2, %al -; WIDEN_AVX2-NEXT: je .LBB5_4 -; WIDEN_AVX2-NEXT: .LBB5_3: # %cond.store1 +; WIDEN_AVX2-NEXT: je .LBB5_2 +; WIDEN_AVX2-NEXT: .LBB5_4: # %cond.store1 ; WIDEN_AVX2-NEXT: vpextrq $1, %xmm1, %rax ; WIDEN_AVX2-NEXT: vextractps $1, %xmm0, (%rax) ; WIDEN_AVX2-NEXT: retq diff --git a/llvm/test/CodeGen/X86/masked_load.ll b/llvm/test/CodeGen/X86/masked_load.ll index 99a8918fef93f..16cfea0ad1e6e 100644 --- a/llvm/test/CodeGen/X86/masked_load.ll +++ b/llvm/test/CodeGen/X86/masked_load.ll @@ -36,12 +36,12 @@ define <1 x double> @load_v1f64_i1(i1 %trigger, ptr %addr, <1 x double> %dst) { ; X86-AVX512-NEXT: subl $12, %esp ; X86-AVX512-NEXT: .cfi_def_cfa_offset 16 ; X86-AVX512-NEXT: testb $1, {{[0-9]+}}(%esp) -; X86-AVX512-NEXT: je LBB0_1 -; X86-AVX512-NEXT: ## %bb.2: ## %cond.load +; X86-AVX512-NEXT: je LBB0_2 +; X86-AVX512-NEXT: ## %bb.1: ## %cond.load ; X86-AVX512-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-AVX512-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; X86-AVX512-NEXT: jmp LBB0_3 -; X86-AVX512-NEXT: LBB0_1: +; X86-AVX512-NEXT: LBB0_2: ; X86-AVX512-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; X86-AVX512-NEXT: LBB0_3: ## %else ; X86-AVX512-NEXT: vmovsd %xmm0, (%esp) @@ -78,12 +78,12 @@ define <1 x double> @load_v1f64_v1i64(<1 x i64> %trigger, ptr %addr, <1 x double ; X86-AVX512-NEXT: .cfi_def_cfa_offset 16 ; X86-AVX512-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-AVX512-NEXT: orl {{[0-9]+}}(%esp), %eax -; X86-AVX512-NEXT: jne LBB1_1 -; X86-AVX512-NEXT: ## %bb.2: ## %cond.load +; X86-AVX512-NEXT: jne LBB1_2 +; X86-AVX512-NEXT: ## %bb.1: ## %cond.load ; X86-AVX512-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-AVX512-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; X86-AVX512-NEXT: jmp LBB1_3 -; X86-AVX512-NEXT: LBB1_1: +; X86-AVX512-NEXT: LBB1_2: ; X86-AVX512-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; X86-AVX512-NEXT: LBB1_3: ## %else ; X86-AVX512-NEXT: vmovsd %xmm0, (%esp) @@ -99,17 +99,17 @@ define <2 x double> @load_v2f64_i2(i2 %trigger, ptr %addr, <2 x double> %dst) { ; SSE-LABEL: load_v2f64_i2: ; SSE: ## %bb.0: ; SSE-NEXT: testb $1, %dil -; SSE-NEXT: jne LBB2_1 -; SSE-NEXT: ## %bb.2: ## %else -; SSE-NEXT: testb $2, %dil ; SSE-NEXT: jne LBB2_3 -; SSE-NEXT: LBB2_4: ## %else2 +; SSE-NEXT: ## %bb.1: ## %else +; SSE-NEXT: testb $2, %dil +; SSE-NEXT: jne LBB2_4 +; SSE-NEXT: LBB2_2: ## %else2 ; SSE-NEXT: retq -; SSE-NEXT: LBB2_1: ## %cond.load +; SSE-NEXT: LBB2_3: ## %cond.load ; SSE-NEXT: movlps {{.*#+}} xmm0 = mem[0,1],xmm0[2,3] ; SSE-NEXT: testb $2, %dil -; SSE-NEXT: je LBB2_4 -; SSE-NEXT: LBB2_3: ## %cond.load1 +; SSE-NEXT: je LBB2_2 +; SSE-NEXT: LBB2_4: ## %cond.load1 ; SSE-NEXT: movhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1] ; SSE-NEXT: retq ; @@ -178,18 +178,18 @@ define <2 x double> @load_v2f64_v2i64(<2 x i64> %trigger, ptr %addr, <2 x double ; SSE2-NEXT: pand %xmm2, %xmm0 ; SSE2-NEXT: movmskpd %xmm0, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB3_1 -; SSE2-NEXT: ## %bb.2: ## %else -; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: jne LBB3_3 -; SSE2-NEXT: LBB3_4: ## %else2 +; SSE2-NEXT: ## %bb.1: ## %else +; SSE2-NEXT: testb $2, %al +; SSE2-NEXT: jne LBB3_4 +; SSE2-NEXT: LBB3_2: ## %else2 ; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB3_1: ## %cond.load +; SSE2-NEXT: LBB3_3: ## %cond.load ; SSE2-NEXT: movlps {{.*#+}} xmm1 = mem[0,1],xmm1[2,3] ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB3_4 -; SSE2-NEXT: LBB3_3: ## %cond.load1 +; SSE2-NEXT: je LBB3_2 +; SSE2-NEXT: LBB3_4: ## %cond.load1 ; SSE2-NEXT: movhps {{.*#+}} xmm1 = xmm1[0,1],mem[0,1] ; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: retq @@ -200,18 +200,18 @@ define <2 x double> @load_v2f64_v2i64(<2 x i64> %trigger, ptr %addr, <2 x double ; SSE42-NEXT: pcmpeqq %xmm0, %xmm2 ; SSE42-NEXT: movmskpd %xmm2, %eax ; SSE42-NEXT: testb $1, %al -; SSE42-NEXT: jne LBB3_1 -; SSE42-NEXT: ## %bb.2: ## %else -; SSE42-NEXT: testb $2, %al ; SSE42-NEXT: jne LBB3_3 -; SSE42-NEXT: LBB3_4: ## %else2 +; SSE42-NEXT: ## %bb.1: ## %else +; SSE42-NEXT: testb $2, %al +; SSE42-NEXT: jne LBB3_4 +; SSE42-NEXT: LBB3_2: ## %else2 ; SSE42-NEXT: movaps %xmm1, %xmm0 ; SSE42-NEXT: retq -; SSE42-NEXT: LBB3_1: ## %cond.load +; SSE42-NEXT: LBB3_3: ## %cond.load ; SSE42-NEXT: movlps {{.*#+}} xmm1 = mem[0,1],xmm1[2,3] ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: je LBB3_4 -; SSE42-NEXT: LBB3_3: ## %cond.load1 +; SSE42-NEXT: je LBB3_2 +; SSE42-NEXT: LBB3_4: ## %cond.load1 ; SSE42-NEXT: movhps {{.*#+}} xmm1 = xmm1[0,1],mem[0,1] ; SSE42-NEXT: movaps %xmm1, %xmm0 ; SSE42-NEXT: retq @@ -257,31 +257,31 @@ define <4 x double> @load_v4f64_i4(i4 %trigger, ptr %addr, <4 x double> %dst) { ; SSE-LABEL: load_v4f64_i4: ; SSE: ## %bb.0: ; SSE-NEXT: testb $1, %dil -; SSE-NEXT: jne LBB4_1 -; SSE-NEXT: ## %bb.2: ## %else +; SSE-NEXT: jne LBB4_5 +; SSE-NEXT: ## %bb.1: ## %else ; SSE-NEXT: testb $2, %dil -; SSE-NEXT: jne LBB4_3 -; SSE-NEXT: LBB4_4: ## %else2 +; SSE-NEXT: jne LBB4_6 +; SSE-NEXT: LBB4_2: ## %else2 ; SSE-NEXT: testb $4, %dil -; SSE-NEXT: jne LBB4_5 -; SSE-NEXT: LBB4_6: ## %else5 -; SSE-NEXT: testb $8, %dil ; SSE-NEXT: jne LBB4_7 -; SSE-NEXT: LBB4_8: ## %else8 +; SSE-NEXT: LBB4_3: ## %else5 +; SSE-NEXT: testb $8, %dil +; SSE-NEXT: jne LBB4_8 +; SSE-NEXT: LBB4_4: ## %else8 ; SSE-NEXT: retq -; SSE-NEXT: LBB4_1: ## %cond.load +; SSE-NEXT: LBB4_5: ## %cond.load ; SSE-NEXT: movlps {{.*#+}} xmm0 = mem[0,1],xmm0[2,3] ; SSE-NEXT: testb $2, %dil -; SSE-NEXT: je LBB4_4 -; SSE-NEXT: LBB4_3: ## %cond.load1 +; SSE-NEXT: je LBB4_2 +; SSE-NEXT: LBB4_6: ## %cond.load1 ; SSE-NEXT: movhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1] ; SSE-NEXT: testb $4, %dil -; SSE-NEXT: je LBB4_6 -; SSE-NEXT: LBB4_5: ## %cond.load4 +; SSE-NEXT: je LBB4_3 +; SSE-NEXT: LBB4_7: ## %cond.load4 ; SSE-NEXT: movlps {{.*#+}} xmm1 = mem[0,1],xmm1[2,3] ; SSE-NEXT: testb $8, %dil -; SSE-NEXT: je LBB4_8 -; SSE-NEXT: LBB4_7: ## %cond.load7 +; SSE-NEXT: je LBB4_4 +; SSE-NEXT: LBB4_8: ## %cond.load7 ; SSE-NEXT: movhps {{.*#+}} xmm1 = xmm1[0,1],mem[0,1] ; SSE-NEXT: retq ; @@ -351,35 +351,35 @@ define <4 x double> @load_v4f64_v4i32(<4 x i32> %trigger, ptr %addr, <4 x double ; SSE-NEXT: pcmpeqd %xmm0, %xmm3 ; SSE-NEXT: movmskps %xmm3, %eax ; SSE-NEXT: testb $1, %al -; SSE-NEXT: jne LBB5_1 -; SSE-NEXT: ## %bb.2: ## %else +; SSE-NEXT: jne LBB5_6 +; SSE-NEXT: ## %bb.1: ## %else ; SSE-NEXT: testb $2, %al -; SSE-NEXT: jne LBB5_3 -; SSE-NEXT: LBB5_4: ## %else2 +; SSE-NEXT: jne LBB5_7 +; SSE-NEXT: LBB5_2: ## %else2 ; SSE-NEXT: testb $4, %al -; SSE-NEXT: jne LBB5_5 -; SSE-NEXT: LBB5_6: ## %else5 +; SSE-NEXT: jne LBB5_8 +; SSE-NEXT: LBB5_3: ## %else5 ; SSE-NEXT: testb $8, %al -; SSE-NEXT: je LBB5_8 -; SSE-NEXT: LBB5_7: ## %cond.load7 +; SSE-NEXT: je LBB5_5 +; SSE-NEXT: LBB5_4: ## %cond.load7 ; SSE-NEXT: movhps {{.*#+}} xmm2 = xmm2[0,1],mem[0,1] -; SSE-NEXT: LBB5_8: ## %else8 +; SSE-NEXT: LBB5_5: ## %else8 ; SSE-NEXT: movaps %xmm1, %xmm0 ; SSE-NEXT: movaps %xmm2, %xmm1 ; SSE-NEXT: retq -; SSE-NEXT: LBB5_1: ## %cond.load +; SSE-NEXT: LBB5_6: ## %cond.load ; SSE-NEXT: movlps {{.*#+}} xmm1 = mem[0,1],xmm1[2,3] ; SSE-NEXT: testb $2, %al -; SSE-NEXT: je LBB5_4 -; SSE-NEXT: LBB5_3: ## %cond.load1 +; SSE-NEXT: je LBB5_2 +; SSE-NEXT: LBB5_7: ## %cond.load1 ; SSE-NEXT: movhps {{.*#+}} xmm1 = xmm1[0,1],mem[0,1] ; SSE-NEXT: testb $4, %al -; SSE-NEXT: je LBB5_6 -; SSE-NEXT: LBB5_5: ## %cond.load4 +; SSE-NEXT: je LBB5_3 +; SSE-NEXT: LBB5_8: ## %cond.load4 ; SSE-NEXT: movlps {{.*#+}} xmm2 = mem[0,1],xmm2[2,3] ; SSE-NEXT: testb $8, %al -; SSE-NEXT: jne LBB5_7 -; SSE-NEXT: jmp LBB5_8 +; SSE-NEXT: jne LBB5_4 +; SSE-NEXT: jmp LBB5_5 ; ; AVX1-LABEL: load_v4f64_v4i32: ; AVX1: ## %bb.0: @@ -438,31 +438,31 @@ define <4 x double> @load_v4f64_v4i32_zero(<4 x i32> %trigger, ptr %addr) { ; SSE-NEXT: movmskps %xmm1, %eax ; SSE-NEXT: testb $1, %al ; SSE-NEXT: xorps %xmm1, %xmm1 -; SSE-NEXT: jne LBB6_1 -; SSE-NEXT: ## %bb.2: ## %else +; SSE-NEXT: jne LBB6_5 +; SSE-NEXT: ## %bb.1: ## %else ; SSE-NEXT: testb $2, %al -; SSE-NEXT: jne LBB6_3 -; SSE-NEXT: LBB6_4: ## %else2 +; SSE-NEXT: jne LBB6_6 +; SSE-NEXT: LBB6_2: ## %else2 ; SSE-NEXT: testb $4, %al -; SSE-NEXT: jne LBB6_5 -; SSE-NEXT: LBB6_6: ## %else5 -; SSE-NEXT: testb $8, %al ; SSE-NEXT: jne LBB6_7 -; SSE-NEXT: LBB6_8: ## %else8 +; SSE-NEXT: LBB6_3: ## %else5 +; SSE-NEXT: testb $8, %al +; SSE-NEXT: jne LBB6_8 +; SSE-NEXT: LBB6_4: ## %else8 ; SSE-NEXT: retq -; SSE-NEXT: LBB6_1: ## %cond.load +; SSE-NEXT: LBB6_5: ## %cond.load ; SSE-NEXT: movq {{.*#+}} xmm0 = mem[0],zero ; SSE-NEXT: testb $2, %al -; SSE-NEXT: je LBB6_4 -; SSE-NEXT: LBB6_3: ## %cond.load1 +; SSE-NEXT: je LBB6_2 +; SSE-NEXT: LBB6_6: ## %cond.load1 ; SSE-NEXT: movhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1] ; SSE-NEXT: testb $4, %al -; SSE-NEXT: je LBB6_6 -; SSE-NEXT: LBB6_5: ## %cond.load4 +; SSE-NEXT: je LBB6_3 +; SSE-NEXT: LBB6_7: ## %cond.load4 ; SSE-NEXT: movlps {{.*#+}} xmm1 = mem[0,1],xmm1[2,3] ; SSE-NEXT: testb $8, %al -; SSE-NEXT: je LBB6_8 -; SSE-NEXT: LBB6_7: ## %cond.load7 +; SSE-NEXT: je LBB6_4 +; SSE-NEXT: LBB6_8: ## %cond.load7 ; SSE-NEXT: movhps {{.*#+}} xmm1 = xmm1[0,1],mem[0,1] ; SSE-NEXT: retq ; @@ -523,35 +523,35 @@ define <4 x double> @load_v4f64_v4i64(<4 x i64> %trigger, ptr %addr, <4 x double ; SSE2-NEXT: andps %xmm4, %xmm0 ; SSE2-NEXT: movmskps %xmm0, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB7_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB7_6 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB7_3 -; SSE2-NEXT: LBB7_4: ## %else2 +; SSE2-NEXT: jne LBB7_7 +; SSE2-NEXT: LBB7_2: ## %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB7_5 -; SSE2-NEXT: LBB7_6: ## %else5 +; SSE2-NEXT: jne LBB7_8 +; SSE2-NEXT: LBB7_3: ## %else5 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB7_8 -; SSE2-NEXT: LBB7_7: ## %cond.load7 +; SSE2-NEXT: je LBB7_5 +; SSE2-NEXT: LBB7_4: ## %cond.load7 ; SSE2-NEXT: movhps {{.*#+}} xmm3 = xmm3[0,1],mem[0,1] -; SSE2-NEXT: LBB7_8: ## %else8 +; SSE2-NEXT: LBB7_5: ## %else8 ; SSE2-NEXT: movaps %xmm2, %xmm0 ; SSE2-NEXT: movaps %xmm3, %xmm1 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB7_1: ## %cond.load +; SSE2-NEXT: LBB7_6: ## %cond.load ; SSE2-NEXT: movlps {{.*#+}} xmm2 = mem[0,1],xmm2[2,3] ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB7_4 -; SSE2-NEXT: LBB7_3: ## %cond.load1 +; SSE2-NEXT: je LBB7_2 +; SSE2-NEXT: LBB7_7: ## %cond.load1 ; SSE2-NEXT: movhps {{.*#+}} xmm2 = xmm2[0,1],mem[0,1] ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB7_6 -; SSE2-NEXT: LBB7_5: ## %cond.load4 +; SSE2-NEXT: je LBB7_3 +; SSE2-NEXT: LBB7_8: ## %cond.load4 ; SSE2-NEXT: movlps {{.*#+}} xmm3 = mem[0,1],xmm3[2,3] ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne LBB7_7 -; SSE2-NEXT: jmp LBB7_8 +; SSE2-NEXT: jne LBB7_4 +; SSE2-NEXT: jmp LBB7_5 ; ; SSE42-LABEL: load_v4f64_v4i64: ; SSE42: ## %bb.0: @@ -561,35 +561,35 @@ define <4 x double> @load_v4f64_v4i64(<4 x i64> %trigger, ptr %addr, <4 x double ; SSE42-NEXT: packssdw %xmm1, %xmm0 ; SSE42-NEXT: movmskps %xmm0, %eax ; SSE42-NEXT: testb $1, %al -; SSE42-NEXT: jne LBB7_1 -; SSE42-NEXT: ## %bb.2: ## %else +; SSE42-NEXT: jne LBB7_6 +; SSE42-NEXT: ## %bb.1: ## %else ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: jne LBB7_3 -; SSE42-NEXT: LBB7_4: ## %else2 +; SSE42-NEXT: jne LBB7_7 +; SSE42-NEXT: LBB7_2: ## %else2 ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: jne LBB7_5 -; SSE42-NEXT: LBB7_6: ## %else5 +; SSE42-NEXT: jne LBB7_8 +; SSE42-NEXT: LBB7_3: ## %else5 ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: je LBB7_8 -; SSE42-NEXT: LBB7_7: ## %cond.load7 +; SSE42-NEXT: je LBB7_5 +; SSE42-NEXT: LBB7_4: ## %cond.load7 ; SSE42-NEXT: movhps {{.*#+}} xmm3 = xmm3[0,1],mem[0,1] -; SSE42-NEXT: LBB7_8: ## %else8 +; SSE42-NEXT: LBB7_5: ## %else8 ; SSE42-NEXT: movaps %xmm2, %xmm0 ; SSE42-NEXT: movaps %xmm3, %xmm1 ; SSE42-NEXT: retq -; SSE42-NEXT: LBB7_1: ## %cond.load +; SSE42-NEXT: LBB7_6: ## %cond.load ; SSE42-NEXT: movlps {{.*#+}} xmm2 = mem[0,1],xmm2[2,3] ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: je LBB7_4 -; SSE42-NEXT: LBB7_3: ## %cond.load1 +; SSE42-NEXT: je LBB7_2 +; SSE42-NEXT: LBB7_7: ## %cond.load1 ; SSE42-NEXT: movhps {{.*#+}} xmm2 = xmm2[0,1],mem[0,1] ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: je LBB7_6 -; SSE42-NEXT: LBB7_5: ## %cond.load4 +; SSE42-NEXT: je LBB7_3 +; SSE42-NEXT: LBB7_8: ## %cond.load4 ; SSE42-NEXT: movlps {{.*#+}} xmm3 = mem[0,1],xmm3[2,3] ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: jne LBB7_7 -; SSE42-NEXT: jmp LBB7_8 +; SSE42-NEXT: jne LBB7_4 +; SSE42-NEXT: jmp LBB7_5 ; ; AVX1-LABEL: load_v4f64_v4i64: ; AVX1: ## %bb.0: @@ -642,59 +642,59 @@ define <8 x double> @load_v8f64_i8(i8 %trigger, ptr %addr, <8 x double> %dst) { ; SSE-LABEL: load_v8f64_i8: ; SSE: ## %bb.0: ; SSE-NEXT: testb $1, %dil -; SSE-NEXT: jne LBB8_1 -; SSE-NEXT: ## %bb.2: ## %else +; SSE-NEXT: jne LBB8_9 +; SSE-NEXT: ## %bb.1: ## %else ; SSE-NEXT: testb $2, %dil -; SSE-NEXT: jne LBB8_3 -; SSE-NEXT: LBB8_4: ## %else2 +; SSE-NEXT: jne LBB8_10 +; SSE-NEXT: LBB8_2: ## %else2 ; SSE-NEXT: testb $4, %dil -; SSE-NEXT: jne LBB8_5 -; SSE-NEXT: LBB8_6: ## %else5 +; SSE-NEXT: jne LBB8_11 +; SSE-NEXT: LBB8_3: ## %else5 ; SSE-NEXT: testb $8, %dil -; SSE-NEXT: jne LBB8_7 -; SSE-NEXT: LBB8_8: ## %else8 +; SSE-NEXT: jne LBB8_12 +; SSE-NEXT: LBB8_4: ## %else8 ; SSE-NEXT: testb $16, %dil -; SSE-NEXT: jne LBB8_9 -; SSE-NEXT: LBB8_10: ## %else11 +; SSE-NEXT: jne LBB8_13 +; SSE-NEXT: LBB8_5: ## %else11 ; SSE-NEXT: testb $32, %dil -; SSE-NEXT: jne LBB8_11 -; SSE-NEXT: LBB8_12: ## %else14 +; SSE-NEXT: jne LBB8_14 +; SSE-NEXT: LBB8_6: ## %else14 ; SSE-NEXT: testb $64, %dil -; SSE-NEXT: jne LBB8_13 -; SSE-NEXT: LBB8_14: ## %else17 -; SSE-NEXT: testb $-128, %dil ; SSE-NEXT: jne LBB8_15 -; SSE-NEXT: LBB8_16: ## %else20 +; SSE-NEXT: LBB8_7: ## %else17 +; SSE-NEXT: testb $-128, %dil +; SSE-NEXT: jne LBB8_16 +; SSE-NEXT: LBB8_8: ## %else20 ; SSE-NEXT: retq -; SSE-NEXT: LBB8_1: ## %cond.load +; SSE-NEXT: LBB8_9: ## %cond.load ; SSE-NEXT: movlps {{.*#+}} xmm0 = mem[0,1],xmm0[2,3] ; SSE-NEXT: testb $2, %dil -; SSE-NEXT: je LBB8_4 -; SSE-NEXT: LBB8_3: ## %cond.load1 +; SSE-NEXT: je LBB8_2 +; SSE-NEXT: LBB8_10: ## %cond.load1 ; SSE-NEXT: movhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1] ; SSE-NEXT: testb $4, %dil -; SSE-NEXT: je LBB8_6 -; SSE-NEXT: LBB8_5: ## %cond.load4 +; SSE-NEXT: je LBB8_3 +; SSE-NEXT: LBB8_11: ## %cond.load4 ; SSE-NEXT: movlps {{.*#+}} xmm1 = mem[0,1],xmm1[2,3] ; SSE-NEXT: testb $8, %dil -; SSE-NEXT: je LBB8_8 -; SSE-NEXT: LBB8_7: ## %cond.load7 +; SSE-NEXT: je LBB8_4 +; SSE-NEXT: LBB8_12: ## %cond.load7 ; SSE-NEXT: movhps {{.*#+}} xmm1 = xmm1[0,1],mem[0,1] ; SSE-NEXT: testb $16, %dil -; SSE-NEXT: je LBB8_10 -; SSE-NEXT: LBB8_9: ## %cond.load10 +; SSE-NEXT: je LBB8_5 +; SSE-NEXT: LBB8_13: ## %cond.load10 ; SSE-NEXT: movlps {{.*#+}} xmm2 = mem[0,1],xmm2[2,3] ; SSE-NEXT: testb $32, %dil -; SSE-NEXT: je LBB8_12 -; SSE-NEXT: LBB8_11: ## %cond.load13 +; SSE-NEXT: je LBB8_6 +; SSE-NEXT: LBB8_14: ## %cond.load13 ; SSE-NEXT: movhps {{.*#+}} xmm2 = xmm2[0,1],mem[0,1] ; SSE-NEXT: testb $64, %dil -; SSE-NEXT: je LBB8_14 -; SSE-NEXT: LBB8_13: ## %cond.load16 +; SSE-NEXT: je LBB8_7 +; SSE-NEXT: LBB8_15: ## %cond.load16 ; SSE-NEXT: movlps {{.*#+}} xmm3 = mem[0,1],xmm3[2,3] ; SSE-NEXT: testb $-128, %dil -; SSE-NEXT: je LBB8_16 -; SSE-NEXT: LBB8_15: ## %cond.load19 +; SSE-NEXT: je LBB8_8 +; SSE-NEXT: LBB8_16: ## %cond.load19 ; SSE-NEXT: movhps {{.*#+}} xmm3 = xmm3[0,1],mem[0,1] ; SSE-NEXT: retq ; @@ -827,65 +827,65 @@ define <8 x double> @load_v8f64_v8i16(<8 x i16> %trigger, ptr %addr, <8 x double ; SSE-NEXT: packsswb %xmm5, %xmm5 ; SSE-NEXT: pmovmskb %xmm5, %eax ; SSE-NEXT: testb $1, %al -; SSE-NEXT: jne LBB9_1 -; SSE-NEXT: ## %bb.2: ## %else +; SSE-NEXT: jne LBB9_10 +; SSE-NEXT: ## %bb.1: ## %else ; SSE-NEXT: testb $2, %al -; SSE-NEXT: jne LBB9_3 -; SSE-NEXT: LBB9_4: ## %else2 +; SSE-NEXT: jne LBB9_11 +; SSE-NEXT: LBB9_2: ## %else2 ; SSE-NEXT: testb $4, %al -; SSE-NEXT: jne LBB9_5 -; SSE-NEXT: LBB9_6: ## %else5 +; SSE-NEXT: jne LBB9_12 +; SSE-NEXT: LBB9_3: ## %else5 ; SSE-NEXT: testb $8, %al -; SSE-NEXT: jne LBB9_7 -; SSE-NEXT: LBB9_8: ## %else8 +; SSE-NEXT: jne LBB9_13 +; SSE-NEXT: LBB9_4: ## %else8 ; SSE-NEXT: testb $16, %al -; SSE-NEXT: jne LBB9_9 -; SSE-NEXT: LBB9_10: ## %else11 +; SSE-NEXT: jne LBB9_14 +; SSE-NEXT: LBB9_5: ## %else11 ; SSE-NEXT: testb $32, %al -; SSE-NEXT: jne LBB9_11 -; SSE-NEXT: LBB9_12: ## %else14 +; SSE-NEXT: jne LBB9_15 +; SSE-NEXT: LBB9_6: ## %else14 ; SSE-NEXT: testb $64, %al -; SSE-NEXT: jne LBB9_13 -; SSE-NEXT: LBB9_14: ## %else17 +; SSE-NEXT: jne LBB9_16 +; SSE-NEXT: LBB9_7: ## %else17 ; SSE-NEXT: testb $-128, %al -; SSE-NEXT: je LBB9_16 -; SSE-NEXT: LBB9_15: ## %cond.load19 +; SSE-NEXT: je LBB9_9 +; SSE-NEXT: LBB9_8: ## %cond.load19 ; SSE-NEXT: movhps {{.*#+}} xmm4 = xmm4[0,1],mem[0,1] -; SSE-NEXT: LBB9_16: ## %else20 +; SSE-NEXT: LBB9_9: ## %else20 ; SSE-NEXT: movaps %xmm1, %xmm0 ; SSE-NEXT: movaps %xmm2, %xmm1 ; SSE-NEXT: movaps %xmm3, %xmm2 ; SSE-NEXT: movaps %xmm4, %xmm3 ; SSE-NEXT: retq -; SSE-NEXT: LBB9_1: ## %cond.load +; SSE-NEXT: LBB9_10: ## %cond.load ; SSE-NEXT: movlps {{.*#+}} xmm1 = mem[0,1],xmm1[2,3] ; SSE-NEXT: testb $2, %al -; SSE-NEXT: je LBB9_4 -; SSE-NEXT: LBB9_3: ## %cond.load1 +; SSE-NEXT: je LBB9_2 +; SSE-NEXT: LBB9_11: ## %cond.load1 ; SSE-NEXT: movhps {{.*#+}} xmm1 = xmm1[0,1],mem[0,1] ; SSE-NEXT: testb $4, %al -; SSE-NEXT: je LBB9_6 -; SSE-NEXT: LBB9_5: ## %cond.load4 +; SSE-NEXT: je LBB9_3 +; SSE-NEXT: LBB9_12: ## %cond.load4 ; SSE-NEXT: movlps {{.*#+}} xmm2 = mem[0,1],xmm2[2,3] ; SSE-NEXT: testb $8, %al -; SSE-NEXT: je LBB9_8 -; SSE-NEXT: LBB9_7: ## %cond.load7 +; SSE-NEXT: je LBB9_4 +; SSE-NEXT: LBB9_13: ## %cond.load7 ; SSE-NEXT: movhps {{.*#+}} xmm2 = xmm2[0,1],mem[0,1] ; SSE-NEXT: testb $16, %al -; SSE-NEXT: je LBB9_10 -; SSE-NEXT: LBB9_9: ## %cond.load10 +; SSE-NEXT: je LBB9_5 +; SSE-NEXT: LBB9_14: ## %cond.load10 ; SSE-NEXT: movlps {{.*#+}} xmm3 = mem[0,1],xmm3[2,3] ; SSE-NEXT: testb $32, %al -; SSE-NEXT: je LBB9_12 -; SSE-NEXT: LBB9_11: ## %cond.load13 +; SSE-NEXT: je LBB9_6 +; SSE-NEXT: LBB9_15: ## %cond.load13 ; SSE-NEXT: movhps {{.*#+}} xmm3 = xmm3[0,1],mem[0,1] ; SSE-NEXT: testb $64, %al -; SSE-NEXT: je LBB9_14 -; SSE-NEXT: LBB9_13: ## %cond.load16 +; SSE-NEXT: je LBB9_7 +; SSE-NEXT: LBB9_16: ## %cond.load16 ; SSE-NEXT: movlps {{.*#+}} xmm4 = mem[0,1],xmm4[2,3] ; SSE-NEXT: testb $-128, %al -; SSE-NEXT: jne LBB9_15 -; SSE-NEXT: jmp LBB9_16 +; SSE-NEXT: jne LBB9_8 +; SSE-NEXT: jmp LBB9_9 ; ; AVX1-LABEL: load_v8f64_v8i16: ; AVX1: ## %bb.0: @@ -978,65 +978,65 @@ define <8 x double> @load_v8f64_v8i64(<8 x i64> %trigger, ptr %addr, <8 x double ; SSE2-NEXT: packsswb %xmm1, %xmm1 ; SSE2-NEXT: pmovmskb %xmm1, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB10_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB10_10 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB10_3 -; SSE2-NEXT: LBB10_4: ## %else2 +; SSE2-NEXT: jne LBB10_11 +; SSE2-NEXT: LBB10_2: ## %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB10_5 -; SSE2-NEXT: LBB10_6: ## %else5 +; SSE2-NEXT: jne LBB10_12 +; SSE2-NEXT: LBB10_3: ## %else5 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne LBB10_7 -; SSE2-NEXT: LBB10_8: ## %else8 +; SSE2-NEXT: jne LBB10_13 +; SSE2-NEXT: LBB10_4: ## %else8 ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: jne LBB10_9 -; SSE2-NEXT: LBB10_10: ## %else11 +; SSE2-NEXT: jne LBB10_14 +; SSE2-NEXT: LBB10_5: ## %else11 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: jne LBB10_11 -; SSE2-NEXT: LBB10_12: ## %else14 +; SSE2-NEXT: jne LBB10_15 +; SSE2-NEXT: LBB10_6: ## %else14 ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: jne LBB10_13 -; SSE2-NEXT: LBB10_14: ## %else17 +; SSE2-NEXT: jne LBB10_16 +; SSE2-NEXT: LBB10_7: ## %else17 ; SSE2-NEXT: testb $-128, %al -; SSE2-NEXT: je LBB10_16 -; SSE2-NEXT: LBB10_15: ## %cond.load19 +; SSE2-NEXT: je LBB10_9 +; SSE2-NEXT: LBB10_8: ## %cond.load19 ; SSE2-NEXT: movhps {{.*#+}} xmm7 = xmm7[0,1],mem[0,1] -; SSE2-NEXT: LBB10_16: ## %else20 +; SSE2-NEXT: LBB10_9: ## %else20 ; SSE2-NEXT: movaps %xmm4, %xmm0 ; SSE2-NEXT: movaps %xmm5, %xmm1 ; SSE2-NEXT: movaps %xmm6, %xmm2 ; SSE2-NEXT: movaps %xmm7, %xmm3 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB10_1: ## %cond.load +; SSE2-NEXT: LBB10_10: ## %cond.load ; SSE2-NEXT: movlps {{.*#+}} xmm4 = mem[0,1],xmm4[2,3] ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB10_4 -; SSE2-NEXT: LBB10_3: ## %cond.load1 +; SSE2-NEXT: je LBB10_2 +; SSE2-NEXT: LBB10_11: ## %cond.load1 ; SSE2-NEXT: movhps {{.*#+}} xmm4 = xmm4[0,1],mem[0,1] ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB10_6 -; SSE2-NEXT: LBB10_5: ## %cond.load4 +; SSE2-NEXT: je LBB10_3 +; SSE2-NEXT: LBB10_12: ## %cond.load4 ; SSE2-NEXT: movlps {{.*#+}} xmm5 = mem[0,1],xmm5[2,3] ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB10_8 -; SSE2-NEXT: LBB10_7: ## %cond.load7 +; SSE2-NEXT: je LBB10_4 +; SSE2-NEXT: LBB10_13: ## %cond.load7 ; SSE2-NEXT: movhps {{.*#+}} xmm5 = xmm5[0,1],mem[0,1] ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: je LBB10_10 -; SSE2-NEXT: LBB10_9: ## %cond.load10 +; SSE2-NEXT: je LBB10_5 +; SSE2-NEXT: LBB10_14: ## %cond.load10 ; SSE2-NEXT: movlps {{.*#+}} xmm6 = mem[0,1],xmm6[2,3] ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je LBB10_12 -; SSE2-NEXT: LBB10_11: ## %cond.load13 +; SSE2-NEXT: je LBB10_6 +; SSE2-NEXT: LBB10_15: ## %cond.load13 ; SSE2-NEXT: movhps {{.*#+}} xmm6 = xmm6[0,1],mem[0,1] ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: je LBB10_14 -; SSE2-NEXT: LBB10_13: ## %cond.load16 +; SSE2-NEXT: je LBB10_7 +; SSE2-NEXT: LBB10_16: ## %cond.load16 ; SSE2-NEXT: movlps {{.*#+}} xmm7 = mem[0,1],xmm7[2,3] ; SSE2-NEXT: testb $-128, %al -; SSE2-NEXT: jne LBB10_15 -; SSE2-NEXT: jmp LBB10_16 +; SSE2-NEXT: jne LBB10_8 +; SSE2-NEXT: jmp LBB10_9 ; ; SSE42-LABEL: load_v8f64_v8i64: ; SSE42: ## %bb.0: @@ -1051,65 +1051,65 @@ define <8 x double> @load_v8f64_v8i64(<8 x i64> %trigger, ptr %addr, <8 x double ; SSE42-NEXT: packsswb %xmm0, %xmm0 ; SSE42-NEXT: pmovmskb %xmm0, %eax ; SSE42-NEXT: testb $1, %al -; SSE42-NEXT: jne LBB10_1 -; SSE42-NEXT: ## %bb.2: ## %else +; SSE42-NEXT: jne LBB10_10 +; SSE42-NEXT: ## %bb.1: ## %else ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: jne LBB10_3 -; SSE42-NEXT: LBB10_4: ## %else2 +; SSE42-NEXT: jne LBB10_11 +; SSE42-NEXT: LBB10_2: ## %else2 ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: jne LBB10_5 -; SSE42-NEXT: LBB10_6: ## %else5 +; SSE42-NEXT: jne LBB10_12 +; SSE42-NEXT: LBB10_3: ## %else5 ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: jne LBB10_7 -; SSE42-NEXT: LBB10_8: ## %else8 +; SSE42-NEXT: jne LBB10_13 +; SSE42-NEXT: LBB10_4: ## %else8 ; SSE42-NEXT: testb $16, %al -; SSE42-NEXT: jne LBB10_9 -; SSE42-NEXT: LBB10_10: ## %else11 +; SSE42-NEXT: jne LBB10_14 +; SSE42-NEXT: LBB10_5: ## %else11 ; SSE42-NEXT: testb $32, %al -; SSE42-NEXT: jne LBB10_11 -; SSE42-NEXT: LBB10_12: ## %else14 +; SSE42-NEXT: jne LBB10_15 +; SSE42-NEXT: LBB10_6: ## %else14 ; SSE42-NEXT: testb $64, %al -; SSE42-NEXT: jne LBB10_13 -; SSE42-NEXT: LBB10_14: ## %else17 +; SSE42-NEXT: jne LBB10_16 +; SSE42-NEXT: LBB10_7: ## %else17 ; SSE42-NEXT: testb $-128, %al -; SSE42-NEXT: je LBB10_16 -; SSE42-NEXT: LBB10_15: ## %cond.load19 +; SSE42-NEXT: je LBB10_9 +; SSE42-NEXT: LBB10_8: ## %cond.load19 ; SSE42-NEXT: movhps {{.*#+}} xmm7 = xmm7[0,1],mem[0,1] -; SSE42-NEXT: LBB10_16: ## %else20 +; SSE42-NEXT: LBB10_9: ## %else20 ; SSE42-NEXT: movaps %xmm4, %xmm0 ; SSE42-NEXT: movaps %xmm5, %xmm1 ; SSE42-NEXT: movaps %xmm6, %xmm2 ; SSE42-NEXT: movaps %xmm7, %xmm3 ; SSE42-NEXT: retq -; SSE42-NEXT: LBB10_1: ## %cond.load +; SSE42-NEXT: LBB10_10: ## %cond.load ; SSE42-NEXT: movlps {{.*#+}} xmm4 = mem[0,1],xmm4[2,3] ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: je LBB10_4 -; SSE42-NEXT: LBB10_3: ## %cond.load1 +; SSE42-NEXT: je LBB10_2 +; SSE42-NEXT: LBB10_11: ## %cond.load1 ; SSE42-NEXT: movhps {{.*#+}} xmm4 = xmm4[0,1],mem[0,1] ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: je LBB10_6 -; SSE42-NEXT: LBB10_5: ## %cond.load4 +; SSE42-NEXT: je LBB10_3 +; SSE42-NEXT: LBB10_12: ## %cond.load4 ; SSE42-NEXT: movlps {{.*#+}} xmm5 = mem[0,1],xmm5[2,3] ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: je LBB10_8 -; SSE42-NEXT: LBB10_7: ## %cond.load7 +; SSE42-NEXT: je LBB10_4 +; SSE42-NEXT: LBB10_13: ## %cond.load7 ; SSE42-NEXT: movhps {{.*#+}} xmm5 = xmm5[0,1],mem[0,1] ; SSE42-NEXT: testb $16, %al -; SSE42-NEXT: je LBB10_10 -; SSE42-NEXT: LBB10_9: ## %cond.load10 +; SSE42-NEXT: je LBB10_5 +; SSE42-NEXT: LBB10_14: ## %cond.load10 ; SSE42-NEXT: movlps {{.*#+}} xmm6 = mem[0,1],xmm6[2,3] ; SSE42-NEXT: testb $32, %al -; SSE42-NEXT: je LBB10_12 -; SSE42-NEXT: LBB10_11: ## %cond.load13 +; SSE42-NEXT: je LBB10_6 +; SSE42-NEXT: LBB10_15: ## %cond.load13 ; SSE42-NEXT: movhps {{.*#+}} xmm6 = xmm6[0,1],mem[0,1] ; SSE42-NEXT: testb $64, %al -; SSE42-NEXT: je LBB10_14 -; SSE42-NEXT: LBB10_13: ## %cond.load16 +; SSE42-NEXT: je LBB10_7 +; SSE42-NEXT: LBB10_16: ## %cond.load16 ; SSE42-NEXT: movlps {{.*#+}} xmm7 = mem[0,1],xmm7[2,3] ; SSE42-NEXT: testb $-128, %al -; SSE42-NEXT: jne LBB10_15 -; SSE42-NEXT: jmp LBB10_16 +; SSE42-NEXT: jne LBB10_8 +; SSE42-NEXT: jmp LBB10_9 ; ; AVX1-LABEL: load_v8f64_v8i64: ; AVX1: ## %bb.0: @@ -1164,18 +1164,18 @@ define <2 x float> @load_v2f32_i2(i2 %trigger, ptr %addr, <2 x float> %dst) { ; SSE2-LABEL: load_v2f32_i2: ; SSE2: ## %bb.0: ; SSE2-NEXT: testb $1, %dil -; SSE2-NEXT: jne LBB11_1 -; SSE2-NEXT: ## %bb.2: ## %else -; SSE2-NEXT: testb $2, %dil ; SSE2-NEXT: jne LBB11_3 -; SSE2-NEXT: LBB11_4: ## %else2 +; SSE2-NEXT: ## %bb.1: ## %else +; SSE2-NEXT: testb $2, %dil +; SSE2-NEXT: jne LBB11_4 +; SSE2-NEXT: LBB11_2: ## %else2 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB11_1: ## %cond.load +; SSE2-NEXT: LBB11_3: ## %cond.load ; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] ; SSE2-NEXT: testb $2, %dil -; SSE2-NEXT: je LBB11_4 -; SSE2-NEXT: LBB11_3: ## %cond.load1 +; SSE2-NEXT: je LBB11_2 +; SSE2-NEXT: LBB11_4: ## %cond.load1 ; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3] @@ -1185,18 +1185,18 @@ define <2 x float> @load_v2f32_i2(i2 %trigger, ptr %addr, <2 x float> %dst) { ; SSE42-LABEL: load_v2f32_i2: ; SSE42: ## %bb.0: ; SSE42-NEXT: testb $1, %dil -; SSE42-NEXT: jne LBB11_1 -; SSE42-NEXT: ## %bb.2: ## %else -; SSE42-NEXT: testb $2, %dil ; SSE42-NEXT: jne LBB11_3 -; SSE42-NEXT: LBB11_4: ## %else2 +; SSE42-NEXT: ## %bb.1: ## %else +; SSE42-NEXT: testb $2, %dil +; SSE42-NEXT: jne LBB11_4 +; SSE42-NEXT: LBB11_2: ## %else2 ; SSE42-NEXT: retq -; SSE42-NEXT: LBB11_1: ## %cond.load +; SSE42-NEXT: LBB11_3: ## %cond.load ; SSE42-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; SSE42-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] ; SSE42-NEXT: testb $2, %dil -; SSE42-NEXT: je LBB11_4 -; SSE42-NEXT: LBB11_3: ## %cond.load1 +; SSE42-NEXT: je LBB11_2 +; SSE42-NEXT: LBB11_4: ## %cond.load1 ; SSE42-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3] ; SSE42-NEXT: retq ; @@ -1262,19 +1262,19 @@ define <2 x float> @load_v2f32_v2i32(<2 x i32> %trigger, ptr %addr, <2 x float> ; SSE2-NEXT: pcmpeqd %xmm0, %xmm2 ; SSE2-NEXT: movmskpd %xmm2, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB12_1 -; SSE2-NEXT: ## %bb.2: ## %else -; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: jne LBB12_3 -; SSE2-NEXT: LBB12_4: ## %else2 +; SSE2-NEXT: ## %bb.1: ## %else +; SSE2-NEXT: testb $2, %al +; SSE2-NEXT: jne LBB12_4 +; SSE2-NEXT: LBB12_2: ## %else2 ; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB12_1: ## %cond.load +; SSE2-NEXT: LBB12_3: ## %cond.load ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3] ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB12_4 -; SSE2-NEXT: LBB12_3: ## %cond.load1 +; SSE2-NEXT: je LBB12_2 +; SSE2-NEXT: LBB12_4: ## %cond.load1 ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3] @@ -1289,19 +1289,19 @@ define <2 x float> @load_v2f32_v2i32(<2 x i32> %trigger, ptr %addr, <2 x float> ; SSE42-NEXT: pmovsxdq %xmm2, %xmm0 ; SSE42-NEXT: movmskpd %xmm0, %eax ; SSE42-NEXT: testb $1, %al -; SSE42-NEXT: jne LBB12_1 -; SSE42-NEXT: ## %bb.2: ## %else -; SSE42-NEXT: testb $2, %al ; SSE42-NEXT: jne LBB12_3 -; SSE42-NEXT: LBB12_4: ## %else2 +; SSE42-NEXT: ## %bb.1: ## %else +; SSE42-NEXT: testb $2, %al +; SSE42-NEXT: jne LBB12_4 +; SSE42-NEXT: LBB12_2: ## %else2 ; SSE42-NEXT: movaps %xmm1, %xmm0 ; SSE42-NEXT: retq -; SSE42-NEXT: LBB12_1: ## %cond.load +; SSE42-NEXT: LBB12_3: ## %cond.load ; SSE42-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE42-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3] ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: je LBB12_4 -; SSE42-NEXT: LBB12_3: ## %cond.load1 +; SSE42-NEXT: je LBB12_2 +; SSE42-NEXT: LBB12_4: ## %cond.load1 ; SSE42-NEXT: insertps {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[2,3] ; SSE42-NEXT: movaps %xmm1, %xmm0 ; SSE42-NEXT: retq @@ -1365,17 +1365,17 @@ define <2 x float> @load_v2f32_v2i32_undef(<2 x i32> %trigger, ptr %addr) { ; SSE2-NEXT: movmskpd %xmm1, %eax ; SSE2-NEXT: testb $1, %al ; SSE2-NEXT: ## implicit-def: $xmm0 -; SSE2-NEXT: jne LBB13_1 -; SSE2-NEXT: ## %bb.2: ## %else -; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: jne LBB13_3 -; SSE2-NEXT: LBB13_4: ## %else2 +; SSE2-NEXT: ## %bb.1: ## %else +; SSE2-NEXT: testb $2, %al +; SSE2-NEXT: jne LBB13_4 +; SSE2-NEXT: LBB13_2: ## %else2 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB13_1: ## %cond.load +; SSE2-NEXT: LBB13_3: ## %cond.load ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB13_4 -; SSE2-NEXT: LBB13_3: ## %cond.load1 +; SSE2-NEXT: je LBB13_2 +; SSE2-NEXT: LBB13_4: ## %cond.load1 ; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3] @@ -1390,17 +1390,17 @@ define <2 x float> @load_v2f32_v2i32_undef(<2 x i32> %trigger, ptr %addr) { ; SSE42-NEXT: movmskpd %xmm0, %eax ; SSE42-NEXT: testb $1, %al ; SSE42-NEXT: ## implicit-def: $xmm0 -; SSE42-NEXT: jne LBB13_1 -; SSE42-NEXT: ## %bb.2: ## %else -; SSE42-NEXT: testb $2, %al ; SSE42-NEXT: jne LBB13_3 -; SSE42-NEXT: LBB13_4: ## %else2 +; SSE42-NEXT: ## %bb.1: ## %else +; SSE42-NEXT: testb $2, %al +; SSE42-NEXT: jne LBB13_4 +; SSE42-NEXT: LBB13_2: ## %else2 ; SSE42-NEXT: retq -; SSE42-NEXT: LBB13_1: ## %cond.load +; SSE42-NEXT: LBB13_3: ## %cond.load ; SSE42-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: je LBB13_4 -; SSE42-NEXT: LBB13_3: ## %cond.load1 +; SSE42-NEXT: je LBB13_2 +; SSE42-NEXT: LBB13_4: ## %cond.load1 ; SSE42-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3] ; SSE42-NEXT: retq ; @@ -1456,37 +1456,37 @@ define <4 x float> @load_v4f32_i4(i4 %trigger, ptr %addr, <4 x float> %dst) { ; SSE2-LABEL: load_v4f32_i4: ; SSE2: ## %bb.0: ; SSE2-NEXT: testb $1, %dil -; SSE2-NEXT: jne LBB14_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB14_5 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %dil -; SSE2-NEXT: jne LBB14_3 -; SSE2-NEXT: LBB14_4: ## %else2 +; SSE2-NEXT: jne LBB14_6 +; SSE2-NEXT: LBB14_2: ## %else2 ; SSE2-NEXT: testb $4, %dil -; SSE2-NEXT: jne LBB14_5 -; SSE2-NEXT: LBB14_6: ## %else5 -; SSE2-NEXT: testb $8, %dil ; SSE2-NEXT: jne LBB14_7 -; SSE2-NEXT: LBB14_8: ## %else8 +; SSE2-NEXT: LBB14_3: ## %else5 +; SSE2-NEXT: testb $8, %dil +; SSE2-NEXT: jne LBB14_8 +; SSE2-NEXT: LBB14_4: ## %else8 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB14_1: ## %cond.load +; SSE2-NEXT: LBB14_5: ## %cond.load ; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] ; SSE2-NEXT: testb $2, %dil -; SSE2-NEXT: je LBB14_4 -; SSE2-NEXT: LBB14_3: ## %cond.load1 +; SSE2-NEXT: je LBB14_2 +; SSE2-NEXT: LBB14_6: ## %cond.load1 ; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3] ; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: testb $4, %dil -; SSE2-NEXT: je LBB14_6 -; SSE2-NEXT: LBB14_5: ## %cond.load4 +; SSE2-NEXT: je LBB14_3 +; SSE2-NEXT: LBB14_7: ## %cond.load4 ; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2] ; SSE2-NEXT: testb $8, %dil -; SSE2-NEXT: je LBB14_8 -; SSE2-NEXT: LBB14_7: ## %cond.load7 +; SSE2-NEXT: je LBB14_4 +; SSE2-NEXT: LBB14_8: ## %cond.load7 ; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0] @@ -1495,32 +1495,32 @@ define <4 x float> @load_v4f32_i4(i4 %trigger, ptr %addr, <4 x float> %dst) { ; SSE42-LABEL: load_v4f32_i4: ; SSE42: ## %bb.0: ; SSE42-NEXT: testb $1, %dil -; SSE42-NEXT: jne LBB14_1 -; SSE42-NEXT: ## %bb.2: ## %else +; SSE42-NEXT: jne LBB14_5 +; SSE42-NEXT: ## %bb.1: ## %else ; SSE42-NEXT: testb $2, %dil -; SSE42-NEXT: jne LBB14_3 -; SSE42-NEXT: LBB14_4: ## %else2 +; SSE42-NEXT: jne LBB14_6 +; SSE42-NEXT: LBB14_2: ## %else2 ; SSE42-NEXT: testb $4, %dil -; SSE42-NEXT: jne LBB14_5 -; SSE42-NEXT: LBB14_6: ## %else5 -; SSE42-NEXT: testb $8, %dil ; SSE42-NEXT: jne LBB14_7 -; SSE42-NEXT: LBB14_8: ## %else8 +; SSE42-NEXT: LBB14_3: ## %else5 +; SSE42-NEXT: testb $8, %dil +; SSE42-NEXT: jne LBB14_8 +; SSE42-NEXT: LBB14_4: ## %else8 ; SSE42-NEXT: retq -; SSE42-NEXT: LBB14_1: ## %cond.load +; SSE42-NEXT: LBB14_5: ## %cond.load ; SSE42-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; SSE42-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] ; SSE42-NEXT: testb $2, %dil -; SSE42-NEXT: je LBB14_4 -; SSE42-NEXT: LBB14_3: ## %cond.load1 +; SSE42-NEXT: je LBB14_2 +; SSE42-NEXT: LBB14_6: ## %cond.load1 ; SSE42-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3] ; SSE42-NEXT: testb $4, %dil -; SSE42-NEXT: je LBB14_6 -; SSE42-NEXT: LBB14_5: ## %cond.load4 +; SSE42-NEXT: je LBB14_3 +; SSE42-NEXT: LBB14_7: ## %cond.load4 ; SSE42-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3] ; SSE42-NEXT: testb $8, %dil -; SSE42-NEXT: je LBB14_8 -; SSE42-NEXT: LBB14_7: ## %cond.load7 +; SSE42-NEXT: je LBB14_4 +; SSE42-NEXT: LBB14_8: ## %cond.load7 ; SSE42-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0] ; SSE42-NEXT: retq ; @@ -1587,38 +1587,38 @@ define <4 x float> @load_v4f32_v4i32(<4 x i32> %trigger, ptr %addr, <4 x float> ; SSE2-NEXT: pcmpeqd %xmm0, %xmm2 ; SSE2-NEXT: movmskps %xmm2, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB15_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB15_5 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB15_3 -; SSE2-NEXT: LBB15_4: ## %else2 +; SSE2-NEXT: jne LBB15_6 +; SSE2-NEXT: LBB15_2: ## %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB15_5 -; SSE2-NEXT: LBB15_6: ## %else5 -; SSE2-NEXT: testb $8, %al ; SSE2-NEXT: jne LBB15_7 -; SSE2-NEXT: LBB15_8: ## %else8 +; SSE2-NEXT: LBB15_3: ## %else5 +; SSE2-NEXT: testb $8, %al +; SSE2-NEXT: jne LBB15_8 +; SSE2-NEXT: LBB15_4: ## %else8 ; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB15_1: ## %cond.load +; SSE2-NEXT: LBB15_5: ## %cond.load ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3] ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB15_4 -; SSE2-NEXT: LBB15_3: ## %cond.load1 +; SSE2-NEXT: je LBB15_2 +; SSE2-NEXT: LBB15_6: ## %cond.load1 ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3] ; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB15_6 -; SSE2-NEXT: LBB15_5: ## %cond.load4 +; SSE2-NEXT: je LBB15_3 +; SSE2-NEXT: LBB15_7: ## %cond.load4 ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[0,2] ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB15_8 -; SSE2-NEXT: LBB15_7: ## %cond.load7 +; SSE2-NEXT: je LBB15_4 +; SSE2-NEXT: LBB15_8: ## %cond.load7 ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0] @@ -1631,33 +1631,33 @@ define <4 x float> @load_v4f32_v4i32(<4 x i32> %trigger, ptr %addr, <4 x float> ; SSE42-NEXT: pcmpeqd %xmm0, %xmm2 ; SSE42-NEXT: movmskps %xmm2, %eax ; SSE42-NEXT: testb $1, %al -; SSE42-NEXT: jne LBB15_1 -; SSE42-NEXT: ## %bb.2: ## %else +; SSE42-NEXT: jne LBB15_5 +; SSE42-NEXT: ## %bb.1: ## %else ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: jne LBB15_3 -; SSE42-NEXT: LBB15_4: ## %else2 +; SSE42-NEXT: jne LBB15_6 +; SSE42-NEXT: LBB15_2: ## %else2 ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: jne LBB15_5 -; SSE42-NEXT: LBB15_6: ## %else5 -; SSE42-NEXT: testb $8, %al ; SSE42-NEXT: jne LBB15_7 -; SSE42-NEXT: LBB15_8: ## %else8 +; SSE42-NEXT: LBB15_3: ## %else5 +; SSE42-NEXT: testb $8, %al +; SSE42-NEXT: jne LBB15_8 +; SSE42-NEXT: LBB15_4: ## %else8 ; SSE42-NEXT: movaps %xmm1, %xmm0 ; SSE42-NEXT: retq -; SSE42-NEXT: LBB15_1: ## %cond.load +; SSE42-NEXT: LBB15_5: ## %cond.load ; SSE42-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE42-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3,4,5,6,7] ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: je LBB15_4 -; SSE42-NEXT: LBB15_3: ## %cond.load1 +; SSE42-NEXT: je LBB15_2 +; SSE42-NEXT: LBB15_6: ## %cond.load1 ; SSE42-NEXT: insertps {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[2,3] ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: je LBB15_6 -; SSE42-NEXT: LBB15_5: ## %cond.load4 +; SSE42-NEXT: je LBB15_3 +; SSE42-NEXT: LBB15_7: ## %cond.load4 ; SSE42-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1],mem[0],xmm1[3] ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: je LBB15_8 -; SSE42-NEXT: LBB15_7: ## %cond.load7 +; SSE42-NEXT: je LBB15_4 +; SSE42-NEXT: LBB15_8: ## %cond.load7 ; SSE42-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1,2],mem[0] ; SSE42-NEXT: movaps %xmm1, %xmm0 ; SSE42-NEXT: retq @@ -1705,72 +1705,72 @@ define <8 x float> @load_v8f32_i8(i8 %trigger, ptr %addr) { ; SSE2-NEXT: xorps %xmm0, %xmm0 ; SSE2-NEXT: testb $1, %dil ; SSE2-NEXT: xorps %xmm1, %xmm1 -; SSE2-NEXT: jne LBB16_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB16_9 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %dil -; SSE2-NEXT: jne LBB16_3 -; SSE2-NEXT: LBB16_4: ## %else2 +; SSE2-NEXT: jne LBB16_10 +; SSE2-NEXT: LBB16_2: ## %else2 ; SSE2-NEXT: testb $4, %dil -; SSE2-NEXT: jne LBB16_5 -; SSE2-NEXT: LBB16_6: ## %else5 +; SSE2-NEXT: jne LBB16_11 +; SSE2-NEXT: LBB16_3: ## %else5 ; SSE2-NEXT: testb $8, %dil -; SSE2-NEXT: jne LBB16_7 -; SSE2-NEXT: LBB16_8: ## %else8 +; SSE2-NEXT: jne LBB16_12 +; SSE2-NEXT: LBB16_4: ## %else8 ; SSE2-NEXT: testb $16, %dil -; SSE2-NEXT: jne LBB16_9 -; SSE2-NEXT: LBB16_10: ## %else11 +; SSE2-NEXT: jne LBB16_13 +; SSE2-NEXT: LBB16_5: ## %else11 ; SSE2-NEXT: testb $32, %dil -; SSE2-NEXT: jne LBB16_11 -; SSE2-NEXT: LBB16_12: ## %else14 +; SSE2-NEXT: jne LBB16_14 +; SSE2-NEXT: LBB16_6: ## %else14 ; SSE2-NEXT: testb $64, %dil -; SSE2-NEXT: jne LBB16_13 -; SSE2-NEXT: LBB16_14: ## %else17 -; SSE2-NEXT: testb $-128, %dil ; SSE2-NEXT: jne LBB16_15 -; SSE2-NEXT: LBB16_16: ## %else20 +; SSE2-NEXT: LBB16_7: ## %else17 +; SSE2-NEXT: testb $-128, %dil +; SSE2-NEXT: jne LBB16_16 +; SSE2-NEXT: LBB16_8: ## %else20 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB16_1: ## %cond.load +; SSE2-NEXT: LBB16_9: ## %cond.load ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: testb $2, %dil -; SSE2-NEXT: je LBB16_4 -; SSE2-NEXT: LBB16_3: ## %cond.load1 +; SSE2-NEXT: je LBB16_2 +; SSE2-NEXT: LBB16_10: ## %cond.load1 ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm0[0] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm0[2,3] ; SSE2-NEXT: movaps %xmm2, %xmm0 ; SSE2-NEXT: testb $4, %dil -; SSE2-NEXT: je LBB16_6 -; SSE2-NEXT: LBB16_5: ## %cond.load4 +; SSE2-NEXT: je LBB16_3 +; SSE2-NEXT: LBB16_11: ## %cond.load4 ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm0[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0,2] ; SSE2-NEXT: testb $8, %dil -; SSE2-NEXT: je LBB16_8 -; SSE2-NEXT: LBB16_7: ## %cond.load7 +; SSE2-NEXT: je LBB16_4 +; SSE2-NEXT: LBB16_12: ## %cond.load7 ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm0[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,0] ; SSE2-NEXT: testb $16, %dil -; SSE2-NEXT: je LBB16_10 -; SSE2-NEXT: LBB16_9: ## %cond.load10 +; SSE2-NEXT: je LBB16_5 +; SSE2-NEXT: LBB16_13: ## %cond.load10 ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm2[0],xmm1[1,2,3] ; SSE2-NEXT: testb $32, %dil -; SSE2-NEXT: je LBB16_12 -; SSE2-NEXT: LBB16_11: ## %cond.load13 +; SSE2-NEXT: je LBB16_6 +; SSE2-NEXT: LBB16_14: ## %cond.load13 ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm1[0] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3] ; SSE2-NEXT: movaps %xmm2, %xmm1 ; SSE2-NEXT: testb $64, %dil -; SSE2-NEXT: je LBB16_14 -; SSE2-NEXT: LBB16_13: ## %cond.load16 +; SSE2-NEXT: je LBB16_7 +; SSE2-NEXT: LBB16_15: ## %cond.load16 ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,2] ; SSE2-NEXT: testb $-128, %dil -; SSE2-NEXT: je LBB16_16 -; SSE2-NEXT: LBB16_15: ## %cond.load19 +; SSE2-NEXT: je LBB16_8 +; SSE2-NEXT: LBB16_16: ## %cond.load19 ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,0] @@ -1781,60 +1781,60 @@ define <8 x float> @load_v8f32_i8(i8 %trigger, ptr %addr) { ; SSE42-NEXT: xorps %xmm0, %xmm0 ; SSE42-NEXT: testb $1, %dil ; SSE42-NEXT: xorps %xmm1, %xmm1 -; SSE42-NEXT: jne LBB16_1 -; SSE42-NEXT: ## %bb.2: ## %else +; SSE42-NEXT: jne LBB16_9 +; SSE42-NEXT: ## %bb.1: ## %else ; SSE42-NEXT: testb $2, %dil -; SSE42-NEXT: jne LBB16_3 -; SSE42-NEXT: LBB16_4: ## %else2 +; SSE42-NEXT: jne LBB16_10 +; SSE42-NEXT: LBB16_2: ## %else2 ; SSE42-NEXT: testb $4, %dil -; SSE42-NEXT: jne LBB16_5 -; SSE42-NEXT: LBB16_6: ## %else5 +; SSE42-NEXT: jne LBB16_11 +; SSE42-NEXT: LBB16_3: ## %else5 ; SSE42-NEXT: testb $8, %dil -; SSE42-NEXT: jne LBB16_7 -; SSE42-NEXT: LBB16_8: ## %else8 +; SSE42-NEXT: jne LBB16_12 +; SSE42-NEXT: LBB16_4: ## %else8 ; SSE42-NEXT: testb $16, %dil -; SSE42-NEXT: jne LBB16_9 -; SSE42-NEXT: LBB16_10: ## %else11 +; SSE42-NEXT: jne LBB16_13 +; SSE42-NEXT: LBB16_5: ## %else11 ; SSE42-NEXT: testb $32, %dil -; SSE42-NEXT: jne LBB16_11 -; SSE42-NEXT: LBB16_12: ## %else14 +; SSE42-NEXT: jne LBB16_14 +; SSE42-NEXT: LBB16_6: ## %else14 ; SSE42-NEXT: testb $64, %dil -; SSE42-NEXT: jne LBB16_13 -; SSE42-NEXT: LBB16_14: ## %else17 -; SSE42-NEXT: testb $-128, %dil ; SSE42-NEXT: jne LBB16_15 -; SSE42-NEXT: LBB16_16: ## %else20 +; SSE42-NEXT: LBB16_7: ## %else17 +; SSE42-NEXT: testb $-128, %dil +; SSE42-NEXT: jne LBB16_16 +; SSE42-NEXT: LBB16_8: ## %else20 ; SSE42-NEXT: retq -; SSE42-NEXT: LBB16_1: ## %cond.load +; SSE42-NEXT: LBB16_9: ## %cond.load ; SSE42-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE42-NEXT: testb $2, %dil -; SSE42-NEXT: je LBB16_4 -; SSE42-NEXT: LBB16_3: ## %cond.load1 +; SSE42-NEXT: je LBB16_2 +; SSE42-NEXT: LBB16_10: ## %cond.load1 ; SSE42-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3] ; SSE42-NEXT: testb $4, %dil -; SSE42-NEXT: je LBB16_6 -; SSE42-NEXT: LBB16_5: ## %cond.load4 +; SSE42-NEXT: je LBB16_3 +; SSE42-NEXT: LBB16_11: ## %cond.load4 ; SSE42-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3] ; SSE42-NEXT: testb $8, %dil -; SSE42-NEXT: je LBB16_8 -; SSE42-NEXT: LBB16_7: ## %cond.load7 +; SSE42-NEXT: je LBB16_4 +; SSE42-NEXT: LBB16_12: ## %cond.load7 ; SSE42-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0] ; SSE42-NEXT: testb $16, %dil -; SSE42-NEXT: je LBB16_10 -; SSE42-NEXT: LBB16_9: ## %cond.load10 +; SSE42-NEXT: je LBB16_5 +; SSE42-NEXT: LBB16_13: ## %cond.load10 ; SSE42-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE42-NEXT: movss {{.*#+}} xmm1 = xmm2[0],xmm1[1,2,3] ; SSE42-NEXT: testb $32, %dil -; SSE42-NEXT: je LBB16_12 -; SSE42-NEXT: LBB16_11: ## %cond.load13 +; SSE42-NEXT: je LBB16_6 +; SSE42-NEXT: LBB16_14: ## %cond.load13 ; SSE42-NEXT: insertps {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[2,3] ; SSE42-NEXT: testb $64, %dil -; SSE42-NEXT: je LBB16_14 -; SSE42-NEXT: LBB16_13: ## %cond.load16 +; SSE42-NEXT: je LBB16_7 +; SSE42-NEXT: LBB16_15: ## %cond.load16 ; SSE42-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1],mem[0],xmm1[3] ; SSE42-NEXT: testb $-128, %dil -; SSE42-NEXT: je LBB16_16 -; SSE42-NEXT: LBB16_15: ## %cond.load19 +; SSE42-NEXT: je LBB16_8 +; SSE42-NEXT: LBB16_16: ## %cond.load19 ; SSE42-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1,2],mem[0] ; SSE42-NEXT: retq ; @@ -1900,72 +1900,72 @@ define <8 x float> @load_v8f32_v8i1_zero(<8 x i1> %mask, ptr %addr) { ; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: testb $1, %al ; SSE2-NEXT: xorps %xmm1, %xmm1 -; SSE2-NEXT: jne LBB17_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB17_9 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB17_3 -; SSE2-NEXT: LBB17_4: ## %else2 +; SSE2-NEXT: jne LBB17_10 +; SSE2-NEXT: LBB17_2: ## %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB17_5 -; SSE2-NEXT: LBB17_6: ## %else5 +; SSE2-NEXT: jne LBB17_11 +; SSE2-NEXT: LBB17_3: ## %else5 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne LBB17_7 -; SSE2-NEXT: LBB17_8: ## %else8 +; SSE2-NEXT: jne LBB17_12 +; SSE2-NEXT: LBB17_4: ## %else8 ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: jne LBB17_9 -; SSE2-NEXT: LBB17_10: ## %else11 +; SSE2-NEXT: jne LBB17_13 +; SSE2-NEXT: LBB17_5: ## %else11 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: jne LBB17_11 -; SSE2-NEXT: LBB17_12: ## %else14 +; SSE2-NEXT: jne LBB17_14 +; SSE2-NEXT: LBB17_6: ## %else14 ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: jne LBB17_13 -; SSE2-NEXT: LBB17_14: ## %else17 -; SSE2-NEXT: testb $-128, %al ; SSE2-NEXT: jne LBB17_15 -; SSE2-NEXT: LBB17_16: ## %else20 +; SSE2-NEXT: LBB17_7: ## %else17 +; SSE2-NEXT: testb $-128, %al +; SSE2-NEXT: jne LBB17_16 +; SSE2-NEXT: LBB17_8: ## %else20 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB17_1: ## %cond.load +; SSE2-NEXT: LBB17_9: ## %cond.load ; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB17_4 -; SSE2-NEXT: LBB17_3: ## %cond.load1 +; SSE2-NEXT: je LBB17_2 +; SSE2-NEXT: LBB17_10: ## %cond.load1 ; SSE2-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm0[2,3] ; SSE2-NEXT: movaps %xmm2, %xmm0 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB17_6 -; SSE2-NEXT: LBB17_5: ## %cond.load4 +; SSE2-NEXT: je LBB17_3 +; SSE2-NEXT: LBB17_11: ## %cond.load4 ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm0[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0,2] ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB17_8 -; SSE2-NEXT: LBB17_7: ## %cond.load7 +; SSE2-NEXT: je LBB17_4 +; SSE2-NEXT: LBB17_12: ## %cond.load7 ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm0[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,0] ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: je LBB17_10 -; SSE2-NEXT: LBB17_9: ## %cond.load10 +; SSE2-NEXT: je LBB17_5 +; SSE2-NEXT: LBB17_13: ## %cond.load10 ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm2[0],xmm1[1,2,3] ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je LBB17_12 -; SSE2-NEXT: LBB17_11: ## %cond.load13 +; SSE2-NEXT: je LBB17_6 +; SSE2-NEXT: LBB17_14: ## %cond.load13 ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm1[0] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3] ; SSE2-NEXT: movaps %xmm2, %xmm1 ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: je LBB17_14 -; SSE2-NEXT: LBB17_13: ## %cond.load16 +; SSE2-NEXT: je LBB17_7 +; SSE2-NEXT: LBB17_15: ## %cond.load16 ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,2] ; SSE2-NEXT: testb $-128, %al -; SSE2-NEXT: je LBB17_16 -; SSE2-NEXT: LBB17_15: ## %cond.load19 +; SSE2-NEXT: je LBB17_8 +; SSE2-NEXT: LBB17_16: ## %cond.load19 ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,0] @@ -1979,60 +1979,60 @@ define <8 x float> @load_v8f32_v8i1_zero(<8 x i1> %mask, ptr %addr) { ; SSE42-NEXT: pxor %xmm0, %xmm0 ; SSE42-NEXT: testb $1, %al ; SSE42-NEXT: xorps %xmm1, %xmm1 -; SSE42-NEXT: jne LBB17_1 -; SSE42-NEXT: ## %bb.2: ## %else +; SSE42-NEXT: jne LBB17_9 +; SSE42-NEXT: ## %bb.1: ## %else ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: jne LBB17_3 -; SSE42-NEXT: LBB17_4: ## %else2 +; SSE42-NEXT: jne LBB17_10 +; SSE42-NEXT: LBB17_2: ## %else2 ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: jne LBB17_5 -; SSE42-NEXT: LBB17_6: ## %else5 +; SSE42-NEXT: jne LBB17_11 +; SSE42-NEXT: LBB17_3: ## %else5 ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: jne LBB17_7 -; SSE42-NEXT: LBB17_8: ## %else8 +; SSE42-NEXT: jne LBB17_12 +; SSE42-NEXT: LBB17_4: ## %else8 ; SSE42-NEXT: testb $16, %al -; SSE42-NEXT: jne LBB17_9 -; SSE42-NEXT: LBB17_10: ## %else11 +; SSE42-NEXT: jne LBB17_13 +; SSE42-NEXT: LBB17_5: ## %else11 ; SSE42-NEXT: testb $32, %al -; SSE42-NEXT: jne LBB17_11 -; SSE42-NEXT: LBB17_12: ## %else14 +; SSE42-NEXT: jne LBB17_14 +; SSE42-NEXT: LBB17_6: ## %else14 ; SSE42-NEXT: testb $64, %al -; SSE42-NEXT: jne LBB17_13 -; SSE42-NEXT: LBB17_14: ## %else17 -; SSE42-NEXT: testb $-128, %al ; SSE42-NEXT: jne LBB17_15 -; SSE42-NEXT: LBB17_16: ## %else20 +; SSE42-NEXT: LBB17_7: ## %else17 +; SSE42-NEXT: testb $-128, %al +; SSE42-NEXT: jne LBB17_16 +; SSE42-NEXT: LBB17_8: ## %else20 ; SSE42-NEXT: retq -; SSE42-NEXT: LBB17_1: ## %cond.load +; SSE42-NEXT: LBB17_9: ## %cond.load ; SSE42-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: je LBB17_4 -; SSE42-NEXT: LBB17_3: ## %cond.load1 +; SSE42-NEXT: je LBB17_2 +; SSE42-NEXT: LBB17_10: ## %cond.load1 ; SSE42-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3] ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: je LBB17_6 -; SSE42-NEXT: LBB17_5: ## %cond.load4 +; SSE42-NEXT: je LBB17_3 +; SSE42-NEXT: LBB17_11: ## %cond.load4 ; SSE42-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3] ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: je LBB17_8 -; SSE42-NEXT: LBB17_7: ## %cond.load7 +; SSE42-NEXT: je LBB17_4 +; SSE42-NEXT: LBB17_12: ## %cond.load7 ; SSE42-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0] ; SSE42-NEXT: testb $16, %al -; SSE42-NEXT: je LBB17_10 -; SSE42-NEXT: LBB17_9: ## %cond.load10 +; SSE42-NEXT: je LBB17_5 +; SSE42-NEXT: LBB17_13: ## %cond.load10 ; SSE42-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE42-NEXT: movss {{.*#+}} xmm1 = xmm2[0],xmm1[1,2,3] ; SSE42-NEXT: testb $32, %al -; SSE42-NEXT: je LBB17_12 -; SSE42-NEXT: LBB17_11: ## %cond.load13 +; SSE42-NEXT: je LBB17_6 +; SSE42-NEXT: LBB17_14: ## %cond.load13 ; SSE42-NEXT: insertps {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[2,3] ; SSE42-NEXT: testb $64, %al -; SSE42-NEXT: je LBB17_14 -; SSE42-NEXT: LBB17_13: ## %cond.load16 +; SSE42-NEXT: je LBB17_7 +; SSE42-NEXT: LBB17_15: ## %cond.load16 ; SSE42-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1],mem[0],xmm1[3] ; SSE42-NEXT: testb $-128, %al -; SSE42-NEXT: je LBB17_16 -; SSE42-NEXT: LBB17_15: ## %cond.load19 +; SSE42-NEXT: je LBB17_8 +; SSE42-NEXT: LBB17_16: ## %cond.load19 ; SSE42-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1,2],mem[0] ; SSE42-NEXT: retq ; @@ -2098,79 +2098,79 @@ define <8 x float> @load_v8f32_v8i32(<8 x i32> %trigger, ptr %addr, <8 x float> ; SSE2-NEXT: packsswb %xmm0, %xmm0 ; SSE2-NEXT: pmovmskb %xmm0, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB18_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB18_10 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB18_3 -; SSE2-NEXT: LBB18_4: ## %else2 +; SSE2-NEXT: jne LBB18_11 +; SSE2-NEXT: LBB18_2: ## %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB18_5 -; SSE2-NEXT: LBB18_6: ## %else5 +; SSE2-NEXT: jne LBB18_12 +; SSE2-NEXT: LBB18_3: ## %else5 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne LBB18_7 -; SSE2-NEXT: LBB18_8: ## %else8 +; SSE2-NEXT: jne LBB18_13 +; SSE2-NEXT: LBB18_4: ## %else8 ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: jne LBB18_9 -; SSE2-NEXT: LBB18_10: ## %else11 +; SSE2-NEXT: jne LBB18_14 +; SSE2-NEXT: LBB18_5: ## %else11 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: jne LBB18_11 -; SSE2-NEXT: LBB18_12: ## %else14 +; SSE2-NEXT: jne LBB18_15 +; SSE2-NEXT: LBB18_6: ## %else14 ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: jne LBB18_13 -; SSE2-NEXT: LBB18_14: ## %else17 +; SSE2-NEXT: jne LBB18_16 +; SSE2-NEXT: LBB18_7: ## %else17 ; SSE2-NEXT: testb $-128, %al -; SSE2-NEXT: je LBB18_16 -; SSE2-NEXT: LBB18_15: ## %cond.load19 +; SSE2-NEXT: je LBB18_9 +; SSE2-NEXT: LBB18_8: ## %cond.load19 ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm3[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,1],xmm0[2,0] -; SSE2-NEXT: LBB18_16: ## %else20 +; SSE2-NEXT: LBB18_9: ## %else20 ; SSE2-NEXT: movaps %xmm2, %xmm0 ; SSE2-NEXT: movaps %xmm3, %xmm1 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB18_1: ## %cond.load +; SSE2-NEXT: LBB18_10: ## %cond.load ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3] ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB18_4 -; SSE2-NEXT: LBB18_3: ## %cond.load1 +; SSE2-NEXT: je LBB18_2 +; SSE2-NEXT: LBB18_11: ## %cond.load1 ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3] ; SSE2-NEXT: movaps %xmm0, %xmm2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB18_6 -; SSE2-NEXT: LBB18_5: ## %cond.load4 +; SSE2-NEXT: je LBB18_3 +; SSE2-NEXT: LBB18_12: ## %cond.load4 ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm2[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm0[0,2] ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB18_8 -; SSE2-NEXT: LBB18_7: ## %cond.load7 +; SSE2-NEXT: je LBB18_4 +; SSE2-NEXT: LBB18_13: ## %cond.load7 ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm0[2,0] ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: je LBB18_10 -; SSE2-NEXT: LBB18_9: ## %cond.load10 +; SSE2-NEXT: je LBB18_5 +; SSE2-NEXT: LBB18_14: ## %cond.load10 ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm3 = xmm0[0],xmm3[1,2,3] ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je LBB18_12 -; SSE2-NEXT: LBB18_11: ## %cond.load13 +; SSE2-NEXT: je LBB18_6 +; SSE2-NEXT: LBB18_15: ## %cond.load13 ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm3[0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm3[2,3] ; SSE2-NEXT: movaps %xmm0, %xmm3 ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: je LBB18_14 -; SSE2-NEXT: LBB18_13: ## %cond.load16 +; SSE2-NEXT: je LBB18_7 +; SSE2-NEXT: LBB18_16: ## %cond.load16 ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm3[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,1],xmm0[0,2] ; SSE2-NEXT: testb $-128, %al -; SSE2-NEXT: jne LBB18_15 -; SSE2-NEXT: jmp LBB18_16 +; SSE2-NEXT: jne LBB18_8 +; SSE2-NEXT: jmp LBB18_9 ; ; SSE42-LABEL: load_v8f32_v8i32: ; SSE42: ## %bb.0: @@ -2181,65 +2181,65 @@ define <8 x float> @load_v8f32_v8i32(<8 x i32> %trigger, ptr %addr, <8 x float> ; SSE42-NEXT: packsswb %xmm0, %xmm0 ; SSE42-NEXT: pmovmskb %xmm0, %eax ; SSE42-NEXT: testb $1, %al -; SSE42-NEXT: jne LBB18_1 -; SSE42-NEXT: ## %bb.2: ## %else +; SSE42-NEXT: jne LBB18_10 +; SSE42-NEXT: ## %bb.1: ## %else ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: jne LBB18_3 -; SSE42-NEXT: LBB18_4: ## %else2 +; SSE42-NEXT: jne LBB18_11 +; SSE42-NEXT: LBB18_2: ## %else2 ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: jne LBB18_5 -; SSE42-NEXT: LBB18_6: ## %else5 +; SSE42-NEXT: jne LBB18_12 +; SSE42-NEXT: LBB18_3: ## %else5 ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: jne LBB18_7 -; SSE42-NEXT: LBB18_8: ## %else8 +; SSE42-NEXT: jne LBB18_13 +; SSE42-NEXT: LBB18_4: ## %else8 ; SSE42-NEXT: testb $16, %al -; SSE42-NEXT: jne LBB18_9 -; SSE42-NEXT: LBB18_10: ## %else11 +; SSE42-NEXT: jne LBB18_14 +; SSE42-NEXT: LBB18_5: ## %else11 ; SSE42-NEXT: testb $32, %al -; SSE42-NEXT: jne LBB18_11 -; SSE42-NEXT: LBB18_12: ## %else14 +; SSE42-NEXT: jne LBB18_15 +; SSE42-NEXT: LBB18_6: ## %else14 ; SSE42-NEXT: testb $64, %al -; SSE42-NEXT: jne LBB18_13 -; SSE42-NEXT: LBB18_14: ## %else17 +; SSE42-NEXT: jne LBB18_16 +; SSE42-NEXT: LBB18_7: ## %else17 ; SSE42-NEXT: testb $-128, %al -; SSE42-NEXT: je LBB18_16 -; SSE42-NEXT: LBB18_15: ## %cond.load19 +; SSE42-NEXT: je LBB18_9 +; SSE42-NEXT: LBB18_8: ## %cond.load19 ; SSE42-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1,2],mem[0] -; SSE42-NEXT: LBB18_16: ## %else20 +; SSE42-NEXT: LBB18_9: ## %else20 ; SSE42-NEXT: movaps %xmm2, %xmm0 ; SSE42-NEXT: movaps %xmm3, %xmm1 ; SSE42-NEXT: retq -; SSE42-NEXT: LBB18_1: ## %cond.load +; SSE42-NEXT: LBB18_10: ## %cond.load ; SSE42-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE42-NEXT: pblendw {{.*#+}} xmm2 = xmm0[0,1],xmm2[2,3,4,5,6,7] ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: je LBB18_4 -; SSE42-NEXT: LBB18_3: ## %cond.load1 +; SSE42-NEXT: je LBB18_2 +; SSE42-NEXT: LBB18_11: ## %cond.load1 ; SSE42-NEXT: insertps {{.*#+}} xmm2 = xmm2[0],mem[0],xmm2[2,3] ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: je LBB18_6 -; SSE42-NEXT: LBB18_5: ## %cond.load4 +; SSE42-NEXT: je LBB18_3 +; SSE42-NEXT: LBB18_12: ## %cond.load4 ; SSE42-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3] ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: je LBB18_8 -; SSE42-NEXT: LBB18_7: ## %cond.load7 +; SSE42-NEXT: je LBB18_4 +; SSE42-NEXT: LBB18_13: ## %cond.load7 ; SSE42-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1,2],mem[0] ; SSE42-NEXT: testb $16, %al -; SSE42-NEXT: je LBB18_10 -; SSE42-NEXT: LBB18_9: ## %cond.load10 +; SSE42-NEXT: je LBB18_5 +; SSE42-NEXT: LBB18_14: ## %cond.load10 ; SSE42-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE42-NEXT: pblendw {{.*#+}} xmm3 = xmm0[0,1],xmm3[2,3,4,5,6,7] ; SSE42-NEXT: testb $32, %al -; SSE42-NEXT: je LBB18_12 -; SSE42-NEXT: LBB18_11: ## %cond.load13 +; SSE42-NEXT: je LBB18_6 +; SSE42-NEXT: LBB18_15: ## %cond.load13 ; SSE42-NEXT: insertps {{.*#+}} xmm3 = xmm3[0],mem[0],xmm3[2,3] ; SSE42-NEXT: testb $64, %al -; SSE42-NEXT: je LBB18_14 -; SSE42-NEXT: LBB18_13: ## %cond.load16 +; SSE42-NEXT: je LBB18_7 +; SSE42-NEXT: LBB18_16: ## %cond.load16 ; SSE42-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1],mem[0],xmm3[3] ; SSE42-NEXT: testb $-128, %al -; SSE42-NEXT: jne LBB18_15 -; SSE42-NEXT: jmp LBB18_16 +; SSE42-NEXT: jne LBB18_8 +; SSE42-NEXT: jmp LBB18_9 ; ; AVX1-LABEL: load_v8f32_v8i32: ; AVX1: ## %bb.0: @@ -2296,22 +2296,22 @@ define <1 x i64> @load_v1i64_v1i64(<1 x i64> %trigger, ptr %addr, <1 x i64> %dst ; SSE-LABEL: load_v1i64_v1i64: ; SSE: ## %bb.0: ; SSE-NEXT: testq %rdi, %rdi -; SSE-NEXT: jne LBB19_1 -; SSE-NEXT: ## %bb.2: ## %cond.load +; SSE-NEXT: jne LBB19_2 +; SSE-NEXT: ## %bb.1: ## %cond.load ; SSE-NEXT: movq (%rsi), %rax ; SSE-NEXT: retq -; SSE-NEXT: LBB19_1: +; SSE-NEXT: LBB19_2: ; SSE-NEXT: movq %rdx, %rax ; SSE-NEXT: retq ; ; AVX-LABEL: load_v1i64_v1i64: ; AVX: ## %bb.0: ; AVX-NEXT: testq %rdi, %rdi -; AVX-NEXT: jne LBB19_1 -; AVX-NEXT: ## %bb.2: ## %cond.load +; AVX-NEXT: jne LBB19_2 +; AVX-NEXT: ## %bb.1: ## %cond.load ; AVX-NEXT: movq (%rsi), %rax ; AVX-NEXT: retq -; AVX-NEXT: LBB19_1: +; AVX-NEXT: LBB19_2: ; AVX-NEXT: movq %rdx, %rax ; AVX-NEXT: retq ; @@ -2319,13 +2319,13 @@ define <1 x i64> @load_v1i64_v1i64(<1 x i64> %trigger, ptr %addr, <1 x i64> %dst ; X86-AVX512: ## %bb.0: ; X86-AVX512-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-AVX512-NEXT: orl {{[0-9]+}}(%esp), %eax -; X86-AVX512-NEXT: jne LBB19_1 -; X86-AVX512-NEXT: ## %bb.2: ## %cond.load +; X86-AVX512-NEXT: jne LBB19_2 +; X86-AVX512-NEXT: ## %bb.1: ## %cond.load ; X86-AVX512-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-AVX512-NEXT: movl (%ecx), %eax ; X86-AVX512-NEXT: movl 4(%ecx), %edx ; X86-AVX512-NEXT: retl -; X86-AVX512-NEXT: LBB19_1: +; X86-AVX512-NEXT: LBB19_2: ; X86-AVX512-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-AVX512-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-AVX512-NEXT: retl @@ -2343,18 +2343,18 @@ define <2 x i64> @load_v2i64_v2i64(<2 x i64> %trigger, ptr %addr, <2 x i64> %dst ; SSE2-NEXT: pand %xmm2, %xmm0 ; SSE2-NEXT: movmskpd %xmm0, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB20_1 -; SSE2-NEXT: ## %bb.2: ## %else -; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: jne LBB20_3 -; SSE2-NEXT: LBB20_4: ## %else2 +; SSE2-NEXT: ## %bb.1: ## %else +; SSE2-NEXT: testb $2, %al +; SSE2-NEXT: jne LBB20_4 +; SSE2-NEXT: LBB20_2: ## %else2 ; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB20_1: ## %cond.load +; SSE2-NEXT: LBB20_3: ## %cond.load ; SSE2-NEXT: movlps {{.*#+}} xmm1 = mem[0,1],xmm1[2,3] ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB20_4 -; SSE2-NEXT: LBB20_3: ## %cond.load1 +; SSE2-NEXT: je LBB20_2 +; SSE2-NEXT: LBB20_4: ## %cond.load1 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; SSE2-NEXT: movaps %xmm1, %xmm0 @@ -2366,18 +2366,18 @@ define <2 x i64> @load_v2i64_v2i64(<2 x i64> %trigger, ptr %addr, <2 x i64> %dst ; SSE42-NEXT: pcmpeqq %xmm0, %xmm2 ; SSE42-NEXT: movmskpd %xmm2, %eax ; SSE42-NEXT: testb $1, %al -; SSE42-NEXT: jne LBB20_1 -; SSE42-NEXT: ## %bb.2: ## %else -; SSE42-NEXT: testb $2, %al ; SSE42-NEXT: jne LBB20_3 -; SSE42-NEXT: LBB20_4: ## %else2 +; SSE42-NEXT: ## %bb.1: ## %else +; SSE42-NEXT: testb $2, %al +; SSE42-NEXT: jne LBB20_4 +; SSE42-NEXT: LBB20_2: ## %else2 ; SSE42-NEXT: movdqa %xmm1, %xmm0 ; SSE42-NEXT: retq -; SSE42-NEXT: LBB20_1: ## %cond.load +; SSE42-NEXT: LBB20_3: ## %cond.load ; SSE42-NEXT: pinsrq $0, (%rdi), %xmm1 ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: je LBB20_4 -; SSE42-NEXT: LBB20_3: ## %cond.load1 +; SSE42-NEXT: je LBB20_2 +; SSE42-NEXT: LBB20_4: ## %cond.load1 ; SSE42-NEXT: pinsrq $1, 8(%rdi), %xmm1 ; SSE42-NEXT: movdqa %xmm1, %xmm0 ; SSE42-NEXT: retq @@ -2439,37 +2439,37 @@ define <4 x i64> @load_v4i64_v4i64(<4 x i64> %trigger, ptr %addr, <4 x i64> %dst ; SSE2-NEXT: andps %xmm4, %xmm0 ; SSE2-NEXT: movmskps %xmm0, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB21_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB21_6 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB21_3 -; SSE2-NEXT: LBB21_4: ## %else2 +; SSE2-NEXT: jne LBB21_7 +; SSE2-NEXT: LBB21_2: ## %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB21_5 -; SSE2-NEXT: LBB21_6: ## %else5 +; SSE2-NEXT: jne LBB21_8 +; SSE2-NEXT: LBB21_3: ## %else5 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB21_8 -; SSE2-NEXT: LBB21_7: ## %cond.load7 +; SSE2-NEXT: je LBB21_5 +; SSE2-NEXT: LBB21_4: ## %cond.load7 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; SSE2-NEXT: movlhps {{.*#+}} xmm3 = xmm3[0],xmm0[0] -; SSE2-NEXT: LBB21_8: ## %else8 +; SSE2-NEXT: LBB21_5: ## %else8 ; SSE2-NEXT: movaps %xmm2, %xmm0 ; SSE2-NEXT: movaps %xmm3, %xmm1 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB21_1: ## %cond.load +; SSE2-NEXT: LBB21_6: ## %cond.load ; SSE2-NEXT: movlps {{.*#+}} xmm2 = mem[0,1],xmm2[2,3] ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB21_4 -; SSE2-NEXT: LBB21_3: ## %cond.load1 +; SSE2-NEXT: je LBB21_2 +; SSE2-NEXT: LBB21_7: ## %cond.load1 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; SSE2-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm0[0] ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB21_6 -; SSE2-NEXT: LBB21_5: ## %cond.load4 +; SSE2-NEXT: je LBB21_3 +; SSE2-NEXT: LBB21_8: ## %cond.load4 ; SSE2-NEXT: movlps {{.*#+}} xmm3 = mem[0,1],xmm3[2,3] ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne LBB21_7 -; SSE2-NEXT: jmp LBB21_8 +; SSE2-NEXT: jne LBB21_4 +; SSE2-NEXT: jmp LBB21_5 ; ; SSE42-LABEL: load_v4i64_v4i64: ; SSE42: ## %bb.0: @@ -2479,35 +2479,35 @@ define <4 x i64> @load_v4i64_v4i64(<4 x i64> %trigger, ptr %addr, <4 x i64> %dst ; SSE42-NEXT: packssdw %xmm1, %xmm0 ; SSE42-NEXT: movmskps %xmm0, %eax ; SSE42-NEXT: testb $1, %al -; SSE42-NEXT: jne LBB21_1 -; SSE42-NEXT: ## %bb.2: ## %else +; SSE42-NEXT: jne LBB21_6 +; SSE42-NEXT: ## %bb.1: ## %else ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: jne LBB21_3 -; SSE42-NEXT: LBB21_4: ## %else2 +; SSE42-NEXT: jne LBB21_7 +; SSE42-NEXT: LBB21_2: ## %else2 ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: jne LBB21_5 -; SSE42-NEXT: LBB21_6: ## %else5 +; SSE42-NEXT: jne LBB21_8 +; SSE42-NEXT: LBB21_3: ## %else5 ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: je LBB21_8 -; SSE42-NEXT: LBB21_7: ## %cond.load7 +; SSE42-NEXT: je LBB21_5 +; SSE42-NEXT: LBB21_4: ## %cond.load7 ; SSE42-NEXT: pinsrq $1, 24(%rdi), %xmm3 -; SSE42-NEXT: LBB21_8: ## %else8 +; SSE42-NEXT: LBB21_5: ## %else8 ; SSE42-NEXT: movdqa %xmm2, %xmm0 ; SSE42-NEXT: movdqa %xmm3, %xmm1 ; SSE42-NEXT: retq -; SSE42-NEXT: LBB21_1: ## %cond.load +; SSE42-NEXT: LBB21_6: ## %cond.load ; SSE42-NEXT: pinsrq $0, (%rdi), %xmm2 ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: je LBB21_4 -; SSE42-NEXT: LBB21_3: ## %cond.load1 +; SSE42-NEXT: je LBB21_2 +; SSE42-NEXT: LBB21_7: ## %cond.load1 ; SSE42-NEXT: pinsrq $1, 8(%rdi), %xmm2 ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: je LBB21_6 -; SSE42-NEXT: LBB21_5: ## %cond.load4 +; SSE42-NEXT: je LBB21_3 +; SSE42-NEXT: LBB21_8: ## %cond.load4 ; SSE42-NEXT: pinsrq $0, 16(%rdi), %xmm3 ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: jne LBB21_7 -; SSE42-NEXT: jmp LBB21_8 +; SSE42-NEXT: jne LBB21_4 +; SSE42-NEXT: jmp LBB21_5 ; ; AVX1-LABEL: load_v4i64_v4i64: ; AVX1: ## %bb.0: @@ -2564,69 +2564,69 @@ define <8 x i64> @load_v8i64_v8i16(<8 x i16> %trigger, ptr %addr, <8 x i64> %dst ; SSE2-NEXT: packsswb %xmm5, %xmm5 ; SSE2-NEXT: pmovmskb %xmm5, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB22_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB22_10 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB22_3 -; SSE2-NEXT: LBB22_4: ## %else2 +; SSE2-NEXT: jne LBB22_11 +; SSE2-NEXT: LBB22_2: ## %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB22_5 -; SSE2-NEXT: LBB22_6: ## %else5 +; SSE2-NEXT: jne LBB22_12 +; SSE2-NEXT: LBB22_3: ## %else5 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne LBB22_7 -; SSE2-NEXT: LBB22_8: ## %else8 +; SSE2-NEXT: jne LBB22_13 +; SSE2-NEXT: LBB22_4: ## %else8 ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: jne LBB22_9 -; SSE2-NEXT: LBB22_10: ## %else11 +; SSE2-NEXT: jne LBB22_14 +; SSE2-NEXT: LBB22_5: ## %else11 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: jne LBB22_11 -; SSE2-NEXT: LBB22_12: ## %else14 +; SSE2-NEXT: jne LBB22_15 +; SSE2-NEXT: LBB22_6: ## %else14 ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: jne LBB22_13 -; SSE2-NEXT: LBB22_14: ## %else17 +; SSE2-NEXT: jne LBB22_16 +; SSE2-NEXT: LBB22_7: ## %else17 ; SSE2-NEXT: testb $-128, %al -; SSE2-NEXT: je LBB22_16 -; SSE2-NEXT: LBB22_15: ## %cond.load19 +; SSE2-NEXT: je LBB22_9 +; SSE2-NEXT: LBB22_8: ## %cond.load19 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; SSE2-NEXT: movlhps {{.*#+}} xmm4 = xmm4[0],xmm0[0] -; SSE2-NEXT: LBB22_16: ## %else20 +; SSE2-NEXT: LBB22_9: ## %else20 ; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm2, %xmm1 ; SSE2-NEXT: movaps %xmm3, %xmm2 ; SSE2-NEXT: movaps %xmm4, %xmm3 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB22_1: ## %cond.load +; SSE2-NEXT: LBB22_10: ## %cond.load ; SSE2-NEXT: movlps {{.*#+}} xmm1 = mem[0,1],xmm1[2,3] ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB22_4 -; SSE2-NEXT: LBB22_3: ## %cond.load1 +; SSE2-NEXT: je LBB22_2 +; SSE2-NEXT: LBB22_11: ## %cond.load1 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB22_6 -; SSE2-NEXT: LBB22_5: ## %cond.load4 +; SSE2-NEXT: je LBB22_3 +; SSE2-NEXT: LBB22_12: ## %cond.load4 ; SSE2-NEXT: movlps {{.*#+}} xmm2 = mem[0,1],xmm2[2,3] ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB22_8 -; SSE2-NEXT: LBB22_7: ## %cond.load7 +; SSE2-NEXT: je LBB22_4 +; SSE2-NEXT: LBB22_13: ## %cond.load7 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; SSE2-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm0[0] ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: je LBB22_10 -; SSE2-NEXT: LBB22_9: ## %cond.load10 +; SSE2-NEXT: je LBB22_5 +; SSE2-NEXT: LBB22_14: ## %cond.load10 ; SSE2-NEXT: movlps {{.*#+}} xmm3 = mem[0,1],xmm3[2,3] ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je LBB22_12 -; SSE2-NEXT: LBB22_11: ## %cond.load13 +; SSE2-NEXT: je LBB22_6 +; SSE2-NEXT: LBB22_15: ## %cond.load13 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; SSE2-NEXT: movlhps {{.*#+}} xmm3 = xmm3[0],xmm0[0] ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: je LBB22_14 -; SSE2-NEXT: LBB22_13: ## %cond.load16 +; SSE2-NEXT: je LBB22_7 +; SSE2-NEXT: LBB22_16: ## %cond.load16 ; SSE2-NEXT: movlps {{.*#+}} xmm4 = mem[0,1],xmm4[2,3] ; SSE2-NEXT: testb $-128, %al -; SSE2-NEXT: jne LBB22_15 -; SSE2-NEXT: jmp LBB22_16 +; SSE2-NEXT: jne LBB22_8 +; SSE2-NEXT: jmp LBB22_9 ; ; SSE42-LABEL: load_v8i64_v8i16: ; SSE42: ## %bb.0: @@ -2635,65 +2635,65 @@ define <8 x i64> @load_v8i64_v8i16(<8 x i16> %trigger, ptr %addr, <8 x i64> %dst ; SSE42-NEXT: packsswb %xmm5, %xmm5 ; SSE42-NEXT: pmovmskb %xmm5, %eax ; SSE42-NEXT: testb $1, %al -; SSE42-NEXT: jne LBB22_1 -; SSE42-NEXT: ## %bb.2: ## %else +; SSE42-NEXT: jne LBB22_10 +; SSE42-NEXT: ## %bb.1: ## %else ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: jne LBB22_3 -; SSE42-NEXT: LBB22_4: ## %else2 +; SSE42-NEXT: jne LBB22_11 +; SSE42-NEXT: LBB22_2: ## %else2 ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: jne LBB22_5 -; SSE42-NEXT: LBB22_6: ## %else5 +; SSE42-NEXT: jne LBB22_12 +; SSE42-NEXT: LBB22_3: ## %else5 ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: jne LBB22_7 -; SSE42-NEXT: LBB22_8: ## %else8 +; SSE42-NEXT: jne LBB22_13 +; SSE42-NEXT: LBB22_4: ## %else8 ; SSE42-NEXT: testb $16, %al -; SSE42-NEXT: jne LBB22_9 -; SSE42-NEXT: LBB22_10: ## %else11 +; SSE42-NEXT: jne LBB22_14 +; SSE42-NEXT: LBB22_5: ## %else11 ; SSE42-NEXT: testb $32, %al -; SSE42-NEXT: jne LBB22_11 -; SSE42-NEXT: LBB22_12: ## %else14 +; SSE42-NEXT: jne LBB22_15 +; SSE42-NEXT: LBB22_6: ## %else14 ; SSE42-NEXT: testb $64, %al -; SSE42-NEXT: jne LBB22_13 -; SSE42-NEXT: LBB22_14: ## %else17 +; SSE42-NEXT: jne LBB22_16 +; SSE42-NEXT: LBB22_7: ## %else17 ; SSE42-NEXT: testb $-128, %al -; SSE42-NEXT: je LBB22_16 -; SSE42-NEXT: LBB22_15: ## %cond.load19 +; SSE42-NEXT: je LBB22_9 +; SSE42-NEXT: LBB22_8: ## %cond.load19 ; SSE42-NEXT: pinsrq $1, 56(%rdi), %xmm4 -; SSE42-NEXT: LBB22_16: ## %else20 +; SSE42-NEXT: LBB22_9: ## %else20 ; SSE42-NEXT: movdqa %xmm1, %xmm0 ; SSE42-NEXT: movdqa %xmm2, %xmm1 ; SSE42-NEXT: movdqa %xmm3, %xmm2 ; SSE42-NEXT: movdqa %xmm4, %xmm3 ; SSE42-NEXT: retq -; SSE42-NEXT: LBB22_1: ## %cond.load +; SSE42-NEXT: LBB22_10: ## %cond.load ; SSE42-NEXT: pinsrq $0, (%rdi), %xmm1 ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: je LBB22_4 -; SSE42-NEXT: LBB22_3: ## %cond.load1 +; SSE42-NEXT: je LBB22_2 +; SSE42-NEXT: LBB22_11: ## %cond.load1 ; SSE42-NEXT: pinsrq $1, 8(%rdi), %xmm1 ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: je LBB22_6 -; SSE42-NEXT: LBB22_5: ## %cond.load4 +; SSE42-NEXT: je LBB22_3 +; SSE42-NEXT: LBB22_12: ## %cond.load4 ; SSE42-NEXT: pinsrq $0, 16(%rdi), %xmm2 ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: je LBB22_8 -; SSE42-NEXT: LBB22_7: ## %cond.load7 +; SSE42-NEXT: je LBB22_4 +; SSE42-NEXT: LBB22_13: ## %cond.load7 ; SSE42-NEXT: pinsrq $1, 24(%rdi), %xmm2 ; SSE42-NEXT: testb $16, %al -; SSE42-NEXT: je LBB22_10 -; SSE42-NEXT: LBB22_9: ## %cond.load10 +; SSE42-NEXT: je LBB22_5 +; SSE42-NEXT: LBB22_14: ## %cond.load10 ; SSE42-NEXT: pinsrq $0, 32(%rdi), %xmm3 ; SSE42-NEXT: testb $32, %al -; SSE42-NEXT: je LBB22_12 -; SSE42-NEXT: LBB22_11: ## %cond.load13 +; SSE42-NEXT: je LBB22_6 +; SSE42-NEXT: LBB22_15: ## %cond.load13 ; SSE42-NEXT: pinsrq $1, 40(%rdi), %xmm3 ; SSE42-NEXT: testb $64, %al -; SSE42-NEXT: je LBB22_14 -; SSE42-NEXT: LBB22_13: ## %cond.load16 +; SSE42-NEXT: je LBB22_7 +; SSE42-NEXT: LBB22_16: ## %cond.load16 ; SSE42-NEXT: pinsrq $0, 48(%rdi), %xmm4 ; SSE42-NEXT: testb $-128, %al -; SSE42-NEXT: jne LBB22_15 -; SSE42-NEXT: jmp LBB22_16 +; SSE42-NEXT: jne LBB22_8 +; SSE42-NEXT: jmp LBB22_9 ; ; AVX1-LABEL: load_v8i64_v8i16: ; AVX1: ## %bb.0: @@ -2786,69 +2786,69 @@ define <8 x i64> @load_v8i64_v8i64(<8 x i64> %trigger, ptr %addr, <8 x i64> %dst ; SSE2-NEXT: packsswb %xmm1, %xmm1 ; SSE2-NEXT: pmovmskb %xmm1, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB23_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB23_10 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB23_3 -; SSE2-NEXT: LBB23_4: ## %else2 +; SSE2-NEXT: jne LBB23_11 +; SSE2-NEXT: LBB23_2: ## %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB23_5 -; SSE2-NEXT: LBB23_6: ## %else5 +; SSE2-NEXT: jne LBB23_12 +; SSE2-NEXT: LBB23_3: ## %else5 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne LBB23_7 -; SSE2-NEXT: LBB23_8: ## %else8 +; SSE2-NEXT: jne LBB23_13 +; SSE2-NEXT: LBB23_4: ## %else8 ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: jne LBB23_9 -; SSE2-NEXT: LBB23_10: ## %else11 +; SSE2-NEXT: jne LBB23_14 +; SSE2-NEXT: LBB23_5: ## %else11 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: jne LBB23_11 -; SSE2-NEXT: LBB23_12: ## %else14 +; SSE2-NEXT: jne LBB23_15 +; SSE2-NEXT: LBB23_6: ## %else14 ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: jne LBB23_13 -; SSE2-NEXT: LBB23_14: ## %else17 +; SSE2-NEXT: jne LBB23_16 +; SSE2-NEXT: LBB23_7: ## %else17 ; SSE2-NEXT: testb $-128, %al -; SSE2-NEXT: je LBB23_16 -; SSE2-NEXT: LBB23_15: ## %cond.load19 +; SSE2-NEXT: je LBB23_9 +; SSE2-NEXT: LBB23_8: ## %cond.load19 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; SSE2-NEXT: movlhps {{.*#+}} xmm7 = xmm7[0],xmm0[0] -; SSE2-NEXT: LBB23_16: ## %else20 +; SSE2-NEXT: LBB23_9: ## %else20 ; SSE2-NEXT: movaps %xmm4, %xmm0 ; SSE2-NEXT: movaps %xmm5, %xmm1 ; SSE2-NEXT: movaps %xmm6, %xmm2 ; SSE2-NEXT: movaps %xmm7, %xmm3 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB23_1: ## %cond.load +; SSE2-NEXT: LBB23_10: ## %cond.load ; SSE2-NEXT: movlps {{.*#+}} xmm4 = mem[0,1],xmm4[2,3] ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB23_4 -; SSE2-NEXT: LBB23_3: ## %cond.load1 +; SSE2-NEXT: je LBB23_2 +; SSE2-NEXT: LBB23_11: ## %cond.load1 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; SSE2-NEXT: movlhps {{.*#+}} xmm4 = xmm4[0],xmm0[0] ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB23_6 -; SSE2-NEXT: LBB23_5: ## %cond.load4 +; SSE2-NEXT: je LBB23_3 +; SSE2-NEXT: LBB23_12: ## %cond.load4 ; SSE2-NEXT: movlps {{.*#+}} xmm5 = mem[0,1],xmm5[2,3] ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB23_8 -; SSE2-NEXT: LBB23_7: ## %cond.load7 +; SSE2-NEXT: je LBB23_4 +; SSE2-NEXT: LBB23_13: ## %cond.load7 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; SSE2-NEXT: movlhps {{.*#+}} xmm5 = xmm5[0],xmm0[0] ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: je LBB23_10 -; SSE2-NEXT: LBB23_9: ## %cond.load10 +; SSE2-NEXT: je LBB23_5 +; SSE2-NEXT: LBB23_14: ## %cond.load10 ; SSE2-NEXT: movlps {{.*#+}} xmm6 = mem[0,1],xmm6[2,3] ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je LBB23_12 -; SSE2-NEXT: LBB23_11: ## %cond.load13 +; SSE2-NEXT: je LBB23_6 +; SSE2-NEXT: LBB23_15: ## %cond.load13 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; SSE2-NEXT: movlhps {{.*#+}} xmm6 = xmm6[0],xmm0[0] ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: je LBB23_14 -; SSE2-NEXT: LBB23_13: ## %cond.load16 +; SSE2-NEXT: je LBB23_7 +; SSE2-NEXT: LBB23_16: ## %cond.load16 ; SSE2-NEXT: movlps {{.*#+}} xmm7 = mem[0,1],xmm7[2,3] ; SSE2-NEXT: testb $-128, %al -; SSE2-NEXT: jne LBB23_15 -; SSE2-NEXT: jmp LBB23_16 +; SSE2-NEXT: jne LBB23_8 +; SSE2-NEXT: jmp LBB23_9 ; ; SSE42-LABEL: load_v8i64_v8i64: ; SSE42: ## %bb.0: @@ -2863,65 +2863,65 @@ define <8 x i64> @load_v8i64_v8i64(<8 x i64> %trigger, ptr %addr, <8 x i64> %dst ; SSE42-NEXT: packsswb %xmm0, %xmm0 ; SSE42-NEXT: pmovmskb %xmm0, %eax ; SSE42-NEXT: testb $1, %al -; SSE42-NEXT: jne LBB23_1 -; SSE42-NEXT: ## %bb.2: ## %else +; SSE42-NEXT: jne LBB23_10 +; SSE42-NEXT: ## %bb.1: ## %else ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: jne LBB23_3 -; SSE42-NEXT: LBB23_4: ## %else2 +; SSE42-NEXT: jne LBB23_11 +; SSE42-NEXT: LBB23_2: ## %else2 ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: jne LBB23_5 -; SSE42-NEXT: LBB23_6: ## %else5 +; SSE42-NEXT: jne LBB23_12 +; SSE42-NEXT: LBB23_3: ## %else5 ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: jne LBB23_7 -; SSE42-NEXT: LBB23_8: ## %else8 +; SSE42-NEXT: jne LBB23_13 +; SSE42-NEXT: LBB23_4: ## %else8 ; SSE42-NEXT: testb $16, %al -; SSE42-NEXT: jne LBB23_9 -; SSE42-NEXT: LBB23_10: ## %else11 +; SSE42-NEXT: jne LBB23_14 +; SSE42-NEXT: LBB23_5: ## %else11 ; SSE42-NEXT: testb $32, %al -; SSE42-NEXT: jne LBB23_11 -; SSE42-NEXT: LBB23_12: ## %else14 +; SSE42-NEXT: jne LBB23_15 +; SSE42-NEXT: LBB23_6: ## %else14 ; SSE42-NEXT: testb $64, %al -; SSE42-NEXT: jne LBB23_13 -; SSE42-NEXT: LBB23_14: ## %else17 +; SSE42-NEXT: jne LBB23_16 +; SSE42-NEXT: LBB23_7: ## %else17 ; SSE42-NEXT: testb $-128, %al -; SSE42-NEXT: je LBB23_16 -; SSE42-NEXT: LBB23_15: ## %cond.load19 +; SSE42-NEXT: je LBB23_9 +; SSE42-NEXT: LBB23_8: ## %cond.load19 ; SSE42-NEXT: pinsrq $1, 56(%rdi), %xmm7 -; SSE42-NEXT: LBB23_16: ## %else20 +; SSE42-NEXT: LBB23_9: ## %else20 ; SSE42-NEXT: movdqa %xmm4, %xmm0 ; SSE42-NEXT: movdqa %xmm5, %xmm1 ; SSE42-NEXT: movdqa %xmm6, %xmm2 ; SSE42-NEXT: movdqa %xmm7, %xmm3 ; SSE42-NEXT: retq -; SSE42-NEXT: LBB23_1: ## %cond.load +; SSE42-NEXT: LBB23_10: ## %cond.load ; SSE42-NEXT: pinsrq $0, (%rdi), %xmm4 ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: je LBB23_4 -; SSE42-NEXT: LBB23_3: ## %cond.load1 +; SSE42-NEXT: je LBB23_2 +; SSE42-NEXT: LBB23_11: ## %cond.load1 ; SSE42-NEXT: pinsrq $1, 8(%rdi), %xmm4 ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: je LBB23_6 -; SSE42-NEXT: LBB23_5: ## %cond.load4 +; SSE42-NEXT: je LBB23_3 +; SSE42-NEXT: LBB23_12: ## %cond.load4 ; SSE42-NEXT: pinsrq $0, 16(%rdi), %xmm5 ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: je LBB23_8 -; SSE42-NEXT: LBB23_7: ## %cond.load7 +; SSE42-NEXT: je LBB23_4 +; SSE42-NEXT: LBB23_13: ## %cond.load7 ; SSE42-NEXT: pinsrq $1, 24(%rdi), %xmm5 ; SSE42-NEXT: testb $16, %al -; SSE42-NEXT: je LBB23_10 -; SSE42-NEXT: LBB23_9: ## %cond.load10 +; SSE42-NEXT: je LBB23_5 +; SSE42-NEXT: LBB23_14: ## %cond.load10 ; SSE42-NEXT: pinsrq $0, 32(%rdi), %xmm6 ; SSE42-NEXT: testb $32, %al -; SSE42-NEXT: je LBB23_12 -; SSE42-NEXT: LBB23_11: ## %cond.load13 +; SSE42-NEXT: je LBB23_6 +; SSE42-NEXT: LBB23_15: ## %cond.load13 ; SSE42-NEXT: pinsrq $1, 40(%rdi), %xmm6 ; SSE42-NEXT: testb $64, %al -; SSE42-NEXT: je LBB23_14 -; SSE42-NEXT: LBB23_13: ## %cond.load16 +; SSE42-NEXT: je LBB23_7 +; SSE42-NEXT: LBB23_16: ## %cond.load16 ; SSE42-NEXT: pinsrq $0, 48(%rdi), %xmm7 ; SSE42-NEXT: testb $-128, %al -; SSE42-NEXT: jne LBB23_15 -; SSE42-NEXT: jmp LBB23_16 +; SSE42-NEXT: jne LBB23_8 +; SSE42-NEXT: jmp LBB23_9 ; ; AVX1-LABEL: load_v8i64_v8i64: ; AVX1: ## %bb.0: @@ -2980,19 +2980,19 @@ define <2 x i32> @load_v2i32_v2i32(<2 x i32> %trigger, ptr %addr, <2 x i32> %dst ; SSE2-NEXT: pcmpeqd %xmm0, %xmm2 ; SSE2-NEXT: movmskpd %xmm2, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB24_1 -; SSE2-NEXT: ## %bb.2: ## %else -; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: jne LBB24_3 -; SSE2-NEXT: LBB24_4: ## %else2 +; SSE2-NEXT: ## %bb.1: ## %else +; SSE2-NEXT: testb $2, %al +; SSE2-NEXT: jne LBB24_4 +; SSE2-NEXT: LBB24_2: ## %else2 ; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB24_1: ## %cond.load +; SSE2-NEXT: LBB24_3: ## %cond.load ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3] ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB24_4 -; SSE2-NEXT: LBB24_3: ## %cond.load1 +; SSE2-NEXT: je LBB24_2 +; SSE2-NEXT: LBB24_4: ## %cond.load1 ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3] @@ -3007,18 +3007,18 @@ define <2 x i32> @load_v2i32_v2i32(<2 x i32> %trigger, ptr %addr, <2 x i32> %dst ; SSE42-NEXT: pmovsxdq %xmm2, %xmm0 ; SSE42-NEXT: movmskpd %xmm0, %eax ; SSE42-NEXT: testb $1, %al -; SSE42-NEXT: jne LBB24_1 -; SSE42-NEXT: ## %bb.2: ## %else -; SSE42-NEXT: testb $2, %al ; SSE42-NEXT: jne LBB24_3 -; SSE42-NEXT: LBB24_4: ## %else2 +; SSE42-NEXT: ## %bb.1: ## %else +; SSE42-NEXT: testb $2, %al +; SSE42-NEXT: jne LBB24_4 +; SSE42-NEXT: LBB24_2: ## %else2 ; SSE42-NEXT: movdqa %xmm1, %xmm0 ; SSE42-NEXT: retq -; SSE42-NEXT: LBB24_1: ## %cond.load +; SSE42-NEXT: LBB24_3: ## %cond.load ; SSE42-NEXT: pinsrd $0, (%rdi), %xmm1 ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: je LBB24_4 -; SSE42-NEXT: LBB24_3: ## %cond.load1 +; SSE42-NEXT: je LBB24_2 +; SSE42-NEXT: LBB24_4: ## %cond.load1 ; SSE42-NEXT: pinsrd $1, 4(%rdi), %xmm1 ; SSE42-NEXT: movdqa %xmm1, %xmm0 ; SSE42-NEXT: retq @@ -3089,38 +3089,38 @@ define <4 x i32> @load_v4i32_v4i32(<4 x i32> %trigger, ptr %addr, <4 x i32> %dst ; SSE2-NEXT: pcmpeqd %xmm0, %xmm2 ; SSE2-NEXT: movmskps %xmm2, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB25_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB25_5 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB25_3 -; SSE2-NEXT: LBB25_4: ## %else2 +; SSE2-NEXT: jne LBB25_6 +; SSE2-NEXT: LBB25_2: ## %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB25_5 -; SSE2-NEXT: LBB25_6: ## %else5 -; SSE2-NEXT: testb $8, %al ; SSE2-NEXT: jne LBB25_7 -; SSE2-NEXT: LBB25_8: ## %else8 +; SSE2-NEXT: LBB25_3: ## %else5 +; SSE2-NEXT: testb $8, %al +; SSE2-NEXT: jne LBB25_8 +; SSE2-NEXT: LBB25_4: ## %else8 ; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB25_1: ## %cond.load +; SSE2-NEXT: LBB25_5: ## %cond.load ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3] ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB25_4 -; SSE2-NEXT: LBB25_3: ## %cond.load1 +; SSE2-NEXT: je LBB25_2 +; SSE2-NEXT: LBB25_6: ## %cond.load1 ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3] ; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB25_6 -; SSE2-NEXT: LBB25_5: ## %cond.load4 +; SSE2-NEXT: je LBB25_3 +; SSE2-NEXT: LBB25_7: ## %cond.load4 ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[0,2] ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB25_8 -; SSE2-NEXT: LBB25_7: ## %cond.load7 +; SSE2-NEXT: je LBB25_4 +; SSE2-NEXT: LBB25_8: ## %cond.load7 ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0] @@ -3133,32 +3133,32 @@ define <4 x i32> @load_v4i32_v4i32(<4 x i32> %trigger, ptr %addr, <4 x i32> %dst ; SSE42-NEXT: pcmpeqd %xmm0, %xmm2 ; SSE42-NEXT: movmskps %xmm2, %eax ; SSE42-NEXT: testb $1, %al -; SSE42-NEXT: jne LBB25_1 -; SSE42-NEXT: ## %bb.2: ## %else +; SSE42-NEXT: jne LBB25_5 +; SSE42-NEXT: ## %bb.1: ## %else ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: jne LBB25_3 -; SSE42-NEXT: LBB25_4: ## %else2 +; SSE42-NEXT: jne LBB25_6 +; SSE42-NEXT: LBB25_2: ## %else2 ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: jne LBB25_5 -; SSE42-NEXT: LBB25_6: ## %else5 -; SSE42-NEXT: testb $8, %al ; SSE42-NEXT: jne LBB25_7 -; SSE42-NEXT: LBB25_8: ## %else8 +; SSE42-NEXT: LBB25_3: ## %else5 +; SSE42-NEXT: testb $8, %al +; SSE42-NEXT: jne LBB25_8 +; SSE42-NEXT: LBB25_4: ## %else8 ; SSE42-NEXT: movdqa %xmm1, %xmm0 ; SSE42-NEXT: retq -; SSE42-NEXT: LBB25_1: ## %cond.load +; SSE42-NEXT: LBB25_5: ## %cond.load ; SSE42-NEXT: pinsrd $0, (%rdi), %xmm1 ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: je LBB25_4 -; SSE42-NEXT: LBB25_3: ## %cond.load1 +; SSE42-NEXT: je LBB25_2 +; SSE42-NEXT: LBB25_6: ## %cond.load1 ; SSE42-NEXT: pinsrd $1, 4(%rdi), %xmm1 ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: je LBB25_6 -; SSE42-NEXT: LBB25_5: ## %cond.load4 +; SSE42-NEXT: je LBB25_3 +; SSE42-NEXT: LBB25_7: ## %cond.load4 ; SSE42-NEXT: pinsrd $2, 8(%rdi), %xmm1 ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: je LBB25_8 -; SSE42-NEXT: LBB25_7: ## %cond.load7 +; SSE42-NEXT: je LBB25_4 +; SSE42-NEXT: LBB25_8: ## %cond.load7 ; SSE42-NEXT: pinsrd $3, 12(%rdi), %xmm1 ; SSE42-NEXT: movdqa %xmm1, %xmm0 ; SSE42-NEXT: retq @@ -3215,79 +3215,79 @@ define <8 x i32> @load_v8i32_v8i1(<8 x i1> %mask, ptr %addr, <8 x i32> %dst) { ; SSE2-NEXT: packsswb %xmm0, %xmm0 ; SSE2-NEXT: pmovmskb %xmm0, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB26_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB26_10 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB26_3 -; SSE2-NEXT: LBB26_4: ## %else2 +; SSE2-NEXT: jne LBB26_11 +; SSE2-NEXT: LBB26_2: ## %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB26_5 -; SSE2-NEXT: LBB26_6: ## %else5 +; SSE2-NEXT: jne LBB26_12 +; SSE2-NEXT: LBB26_3: ## %else5 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne LBB26_7 -; SSE2-NEXT: LBB26_8: ## %else8 +; SSE2-NEXT: jne LBB26_13 +; SSE2-NEXT: LBB26_4: ## %else8 ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: jne LBB26_9 -; SSE2-NEXT: LBB26_10: ## %else11 +; SSE2-NEXT: jne LBB26_14 +; SSE2-NEXT: LBB26_5: ## %else11 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: jne LBB26_11 -; SSE2-NEXT: LBB26_12: ## %else14 +; SSE2-NEXT: jne LBB26_15 +; SSE2-NEXT: LBB26_6: ## %else14 ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: jne LBB26_13 -; SSE2-NEXT: LBB26_14: ## %else17 +; SSE2-NEXT: jne LBB26_16 +; SSE2-NEXT: LBB26_7: ## %else17 ; SSE2-NEXT: testb $-128, %al -; SSE2-NEXT: je LBB26_16 -; SSE2-NEXT: LBB26_15: ## %cond.load19 +; SSE2-NEXT: je LBB26_9 +; SSE2-NEXT: LBB26_8: ## %cond.load19 ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm0[2,0] -; SSE2-NEXT: LBB26_16: ## %else20 +; SSE2-NEXT: LBB26_9: ## %else20 ; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm2, %xmm1 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB26_1: ## %cond.load +; SSE2-NEXT: LBB26_10: ## %cond.load ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3] ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB26_4 -; SSE2-NEXT: LBB26_3: ## %cond.load1 +; SSE2-NEXT: je LBB26_2 +; SSE2-NEXT: LBB26_11: ## %cond.load1 ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3] ; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB26_6 -; SSE2-NEXT: LBB26_5: ## %cond.load4 +; SSE2-NEXT: je LBB26_3 +; SSE2-NEXT: LBB26_12: ## %cond.load4 ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[0,2] ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB26_8 -; SSE2-NEXT: LBB26_7: ## %cond.load7 +; SSE2-NEXT: je LBB26_4 +; SSE2-NEXT: LBB26_13: ## %cond.load7 ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0] ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: je LBB26_10 -; SSE2-NEXT: LBB26_9: ## %cond.load10 +; SSE2-NEXT: je LBB26_5 +; SSE2-NEXT: LBB26_14: ## %cond.load10 ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3] ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je LBB26_12 -; SSE2-NEXT: LBB26_11: ## %cond.load13 +; SSE2-NEXT: je LBB26_6 +; SSE2-NEXT: LBB26_15: ## %cond.load13 ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3] ; SSE2-NEXT: movaps %xmm0, %xmm2 ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: je LBB26_14 -; SSE2-NEXT: LBB26_13: ## %cond.load16 +; SSE2-NEXT: je LBB26_7 +; SSE2-NEXT: LBB26_16: ## %cond.load16 ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm2[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm0[0,2] ; SSE2-NEXT: testb $-128, %al -; SSE2-NEXT: jne LBB26_15 -; SSE2-NEXT: jmp LBB26_16 +; SSE2-NEXT: jne LBB26_8 +; SSE2-NEXT: jmp LBB26_9 ; ; SSE42-LABEL: load_v8i32_v8i1: ; SSE42: ## %bb.0: @@ -3295,63 +3295,63 @@ define <8 x i32> @load_v8i32_v8i1(<8 x i1> %mask, ptr %addr, <8 x i32> %dst) { ; SSE42-NEXT: packsswb %xmm0, %xmm0 ; SSE42-NEXT: pmovmskb %xmm0, %eax ; SSE42-NEXT: testb $1, %al -; SSE42-NEXT: jne LBB26_1 -; SSE42-NEXT: ## %bb.2: ## %else +; SSE42-NEXT: jne LBB26_10 +; SSE42-NEXT: ## %bb.1: ## %else ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: jne LBB26_3 -; SSE42-NEXT: LBB26_4: ## %else2 +; SSE42-NEXT: jne LBB26_11 +; SSE42-NEXT: LBB26_2: ## %else2 ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: jne LBB26_5 -; SSE42-NEXT: LBB26_6: ## %else5 +; SSE42-NEXT: jne LBB26_12 +; SSE42-NEXT: LBB26_3: ## %else5 ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: jne LBB26_7 -; SSE42-NEXT: LBB26_8: ## %else8 +; SSE42-NEXT: jne LBB26_13 +; SSE42-NEXT: LBB26_4: ## %else8 ; SSE42-NEXT: testb $16, %al -; SSE42-NEXT: jne LBB26_9 -; SSE42-NEXT: LBB26_10: ## %else11 +; SSE42-NEXT: jne LBB26_14 +; SSE42-NEXT: LBB26_5: ## %else11 ; SSE42-NEXT: testb $32, %al -; SSE42-NEXT: jne LBB26_11 -; SSE42-NEXT: LBB26_12: ## %else14 +; SSE42-NEXT: jne LBB26_15 +; SSE42-NEXT: LBB26_6: ## %else14 ; SSE42-NEXT: testb $64, %al -; SSE42-NEXT: jne LBB26_13 -; SSE42-NEXT: LBB26_14: ## %else17 +; SSE42-NEXT: jne LBB26_16 +; SSE42-NEXT: LBB26_7: ## %else17 ; SSE42-NEXT: testb $-128, %al -; SSE42-NEXT: je LBB26_16 -; SSE42-NEXT: LBB26_15: ## %cond.load19 +; SSE42-NEXT: je LBB26_9 +; SSE42-NEXT: LBB26_8: ## %cond.load19 ; SSE42-NEXT: pinsrd $3, 28(%rdi), %xmm2 -; SSE42-NEXT: LBB26_16: ## %else20 +; SSE42-NEXT: LBB26_9: ## %else20 ; SSE42-NEXT: movdqa %xmm1, %xmm0 ; SSE42-NEXT: movdqa %xmm2, %xmm1 ; SSE42-NEXT: retq -; SSE42-NEXT: LBB26_1: ## %cond.load +; SSE42-NEXT: LBB26_10: ## %cond.load ; SSE42-NEXT: pinsrd $0, (%rdi), %xmm1 ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: je LBB26_4 -; SSE42-NEXT: LBB26_3: ## %cond.load1 +; SSE42-NEXT: je LBB26_2 +; SSE42-NEXT: LBB26_11: ## %cond.load1 ; SSE42-NEXT: pinsrd $1, 4(%rdi), %xmm1 ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: je LBB26_6 -; SSE42-NEXT: LBB26_5: ## %cond.load4 +; SSE42-NEXT: je LBB26_3 +; SSE42-NEXT: LBB26_12: ## %cond.load4 ; SSE42-NEXT: pinsrd $2, 8(%rdi), %xmm1 ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: je LBB26_8 -; SSE42-NEXT: LBB26_7: ## %cond.load7 +; SSE42-NEXT: je LBB26_4 +; SSE42-NEXT: LBB26_13: ## %cond.load7 ; SSE42-NEXT: pinsrd $3, 12(%rdi), %xmm1 ; SSE42-NEXT: testb $16, %al -; SSE42-NEXT: je LBB26_10 -; SSE42-NEXT: LBB26_9: ## %cond.load10 +; SSE42-NEXT: je LBB26_5 +; SSE42-NEXT: LBB26_14: ## %cond.load10 ; SSE42-NEXT: pinsrd $0, 16(%rdi), %xmm2 ; SSE42-NEXT: testb $32, %al -; SSE42-NEXT: je LBB26_12 -; SSE42-NEXT: LBB26_11: ## %cond.load13 +; SSE42-NEXT: je LBB26_6 +; SSE42-NEXT: LBB26_15: ## %cond.load13 ; SSE42-NEXT: pinsrd $1, 20(%rdi), %xmm2 ; SSE42-NEXT: testb $64, %al -; SSE42-NEXT: je LBB26_14 -; SSE42-NEXT: LBB26_13: ## %cond.load16 +; SSE42-NEXT: je LBB26_7 +; SSE42-NEXT: LBB26_16: ## %cond.load16 ; SSE42-NEXT: pinsrd $2, 24(%rdi), %xmm2 ; SSE42-NEXT: testb $-128, %al -; SSE42-NEXT: jne LBB26_15 -; SSE42-NEXT: jmp LBB26_16 +; SSE42-NEXT: jne LBB26_8 +; SSE42-NEXT: jmp LBB26_9 ; ; AVX1-LABEL: load_v8i32_v8i1: ; AVX1: ## %bb.0: @@ -3417,72 +3417,72 @@ define <8 x i32> @load_v8i32_v8i1_zero(<8 x i1> %mask, ptr %addr) { ; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: testb $1, %al ; SSE2-NEXT: xorps %xmm1, %xmm1 -; SSE2-NEXT: jne LBB27_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB27_9 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB27_3 -; SSE2-NEXT: LBB27_4: ## %else2 +; SSE2-NEXT: jne LBB27_10 +; SSE2-NEXT: LBB27_2: ## %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB27_5 -; SSE2-NEXT: LBB27_6: ## %else5 +; SSE2-NEXT: jne LBB27_11 +; SSE2-NEXT: LBB27_3: ## %else5 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne LBB27_7 -; SSE2-NEXT: LBB27_8: ## %else8 +; SSE2-NEXT: jne LBB27_12 +; SSE2-NEXT: LBB27_4: ## %else8 ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: jne LBB27_9 -; SSE2-NEXT: LBB27_10: ## %else11 +; SSE2-NEXT: jne LBB27_13 +; SSE2-NEXT: LBB27_5: ## %else11 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: jne LBB27_11 -; SSE2-NEXT: LBB27_12: ## %else14 +; SSE2-NEXT: jne LBB27_14 +; SSE2-NEXT: LBB27_6: ## %else14 ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: jne LBB27_13 -; SSE2-NEXT: LBB27_14: ## %else17 -; SSE2-NEXT: testb $-128, %al ; SSE2-NEXT: jne LBB27_15 -; SSE2-NEXT: LBB27_16: ## %else20 +; SSE2-NEXT: LBB27_7: ## %else17 +; SSE2-NEXT: testb $-128, %al +; SSE2-NEXT: jne LBB27_16 +; SSE2-NEXT: LBB27_8: ## %else20 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB27_1: ## %cond.load +; SSE2-NEXT: LBB27_9: ## %cond.load ; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB27_4 -; SSE2-NEXT: LBB27_3: ## %cond.load1 +; SSE2-NEXT: je LBB27_2 +; SSE2-NEXT: LBB27_10: ## %cond.load1 ; SSE2-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm0[2,3] ; SSE2-NEXT: movaps %xmm2, %xmm0 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB27_6 -; SSE2-NEXT: LBB27_5: ## %cond.load4 +; SSE2-NEXT: je LBB27_3 +; SSE2-NEXT: LBB27_11: ## %cond.load4 ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm0[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0,2] ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB27_8 -; SSE2-NEXT: LBB27_7: ## %cond.load7 +; SSE2-NEXT: je LBB27_4 +; SSE2-NEXT: LBB27_12: ## %cond.load7 ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm0[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,0] ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: je LBB27_10 -; SSE2-NEXT: LBB27_9: ## %cond.load10 +; SSE2-NEXT: je LBB27_5 +; SSE2-NEXT: LBB27_13: ## %cond.load10 ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm2[0],xmm1[1,2,3] ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je LBB27_12 -; SSE2-NEXT: LBB27_11: ## %cond.load13 +; SSE2-NEXT: je LBB27_6 +; SSE2-NEXT: LBB27_14: ## %cond.load13 ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm1[0] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3] ; SSE2-NEXT: movaps %xmm2, %xmm1 ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: je LBB27_14 -; SSE2-NEXT: LBB27_13: ## %cond.load16 +; SSE2-NEXT: je LBB27_7 +; SSE2-NEXT: LBB27_15: ## %cond.load16 ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,2] ; SSE2-NEXT: testb $-128, %al -; SSE2-NEXT: je LBB27_16 -; SSE2-NEXT: LBB27_15: ## %cond.load19 +; SSE2-NEXT: je LBB27_8 +; SSE2-NEXT: LBB27_16: ## %cond.load19 ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,0] @@ -3496,59 +3496,59 @@ define <8 x i32> @load_v8i32_v8i1_zero(<8 x i1> %mask, ptr %addr) { ; SSE42-NEXT: pxor %xmm0, %xmm0 ; SSE42-NEXT: testb $1, %al ; SSE42-NEXT: pxor %xmm1, %xmm1 -; SSE42-NEXT: jne LBB27_1 -; SSE42-NEXT: ## %bb.2: ## %else +; SSE42-NEXT: jne LBB27_9 +; SSE42-NEXT: ## %bb.1: ## %else ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: jne LBB27_3 -; SSE42-NEXT: LBB27_4: ## %else2 +; SSE42-NEXT: jne LBB27_10 +; SSE42-NEXT: LBB27_2: ## %else2 ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: jne LBB27_5 -; SSE42-NEXT: LBB27_6: ## %else5 +; SSE42-NEXT: jne LBB27_11 +; SSE42-NEXT: LBB27_3: ## %else5 ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: jne LBB27_7 -; SSE42-NEXT: LBB27_8: ## %else8 +; SSE42-NEXT: jne LBB27_12 +; SSE42-NEXT: LBB27_4: ## %else8 ; SSE42-NEXT: testb $16, %al -; SSE42-NEXT: jne LBB27_9 -; SSE42-NEXT: LBB27_10: ## %else11 +; SSE42-NEXT: jne LBB27_13 +; SSE42-NEXT: LBB27_5: ## %else11 ; SSE42-NEXT: testb $32, %al -; SSE42-NEXT: jne LBB27_11 -; SSE42-NEXT: LBB27_12: ## %else14 +; SSE42-NEXT: jne LBB27_14 +; SSE42-NEXT: LBB27_6: ## %else14 ; SSE42-NEXT: testb $64, %al -; SSE42-NEXT: jne LBB27_13 -; SSE42-NEXT: LBB27_14: ## %else17 -; SSE42-NEXT: testb $-128, %al ; SSE42-NEXT: jne LBB27_15 -; SSE42-NEXT: LBB27_16: ## %else20 +; SSE42-NEXT: LBB27_7: ## %else17 +; SSE42-NEXT: testb $-128, %al +; SSE42-NEXT: jne LBB27_16 +; SSE42-NEXT: LBB27_8: ## %else20 ; SSE42-NEXT: retq -; SSE42-NEXT: LBB27_1: ## %cond.load +; SSE42-NEXT: LBB27_9: ## %cond.load ; SSE42-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: je LBB27_4 -; SSE42-NEXT: LBB27_3: ## %cond.load1 +; SSE42-NEXT: je LBB27_2 +; SSE42-NEXT: LBB27_10: ## %cond.load1 ; SSE42-NEXT: pinsrd $1, 4(%rdi), %xmm0 ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: je LBB27_6 -; SSE42-NEXT: LBB27_5: ## %cond.load4 +; SSE42-NEXT: je LBB27_3 +; SSE42-NEXT: LBB27_11: ## %cond.load4 ; SSE42-NEXT: pinsrd $2, 8(%rdi), %xmm0 ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: je LBB27_8 -; SSE42-NEXT: LBB27_7: ## %cond.load7 +; SSE42-NEXT: je LBB27_4 +; SSE42-NEXT: LBB27_12: ## %cond.load7 ; SSE42-NEXT: pinsrd $3, 12(%rdi), %xmm0 ; SSE42-NEXT: testb $16, %al -; SSE42-NEXT: je LBB27_10 -; SSE42-NEXT: LBB27_9: ## %cond.load10 +; SSE42-NEXT: je LBB27_5 +; SSE42-NEXT: LBB27_13: ## %cond.load10 ; SSE42-NEXT: pinsrd $0, 16(%rdi), %xmm1 ; SSE42-NEXT: testb $32, %al -; SSE42-NEXT: je LBB27_12 -; SSE42-NEXT: LBB27_11: ## %cond.load13 +; SSE42-NEXT: je LBB27_6 +; SSE42-NEXT: LBB27_14: ## %cond.load13 ; SSE42-NEXT: pinsrd $1, 20(%rdi), %xmm1 ; SSE42-NEXT: testb $64, %al -; SSE42-NEXT: je LBB27_14 -; SSE42-NEXT: LBB27_13: ## %cond.load16 +; SSE42-NEXT: je LBB27_7 +; SSE42-NEXT: LBB27_15: ## %cond.load16 ; SSE42-NEXT: pinsrd $2, 24(%rdi), %xmm1 ; SSE42-NEXT: testb $-128, %al -; SSE42-NEXT: je LBB27_16 -; SSE42-NEXT: LBB27_15: ## %cond.load19 +; SSE42-NEXT: je LBB27_8 +; SSE42-NEXT: LBB27_16: ## %cond.load19 ; SSE42-NEXT: pinsrd $3, 28(%rdi), %xmm1 ; SSE42-NEXT: retq ; @@ -3614,60 +3614,60 @@ define <8 x i16> @load_v8i16_v8i16(<8 x i16> %trigger, ptr %addr, <8 x i16> %dst ; SSE-NEXT: packsswb %xmm0, %xmm0 ; SSE-NEXT: pmovmskb %xmm0, %eax ; SSE-NEXT: testb $1, %al -; SSE-NEXT: jne LBB28_1 -; SSE-NEXT: ## %bb.2: ## %else +; SSE-NEXT: jne LBB28_9 +; SSE-NEXT: ## %bb.1: ## %else ; SSE-NEXT: testb $2, %al -; SSE-NEXT: jne LBB28_3 -; SSE-NEXT: LBB28_4: ## %else2 +; SSE-NEXT: jne LBB28_10 +; SSE-NEXT: LBB28_2: ## %else2 ; SSE-NEXT: testb $4, %al -; SSE-NEXT: jne LBB28_5 -; SSE-NEXT: LBB28_6: ## %else5 +; SSE-NEXT: jne LBB28_11 +; SSE-NEXT: LBB28_3: ## %else5 ; SSE-NEXT: testb $8, %al -; SSE-NEXT: jne LBB28_7 -; SSE-NEXT: LBB28_8: ## %else8 +; SSE-NEXT: jne LBB28_12 +; SSE-NEXT: LBB28_4: ## %else8 ; SSE-NEXT: testb $16, %al -; SSE-NEXT: jne LBB28_9 -; SSE-NEXT: LBB28_10: ## %else11 +; SSE-NEXT: jne LBB28_13 +; SSE-NEXT: LBB28_5: ## %else11 ; SSE-NEXT: testb $32, %al -; SSE-NEXT: jne LBB28_11 -; SSE-NEXT: LBB28_12: ## %else14 +; SSE-NEXT: jne LBB28_14 +; SSE-NEXT: LBB28_6: ## %else14 ; SSE-NEXT: testb $64, %al -; SSE-NEXT: jne LBB28_13 -; SSE-NEXT: LBB28_14: ## %else17 -; SSE-NEXT: testb $-128, %al ; SSE-NEXT: jne LBB28_15 -; SSE-NEXT: LBB28_16: ## %else20 +; SSE-NEXT: LBB28_7: ## %else17 +; SSE-NEXT: testb $-128, %al +; SSE-NEXT: jne LBB28_16 +; SSE-NEXT: LBB28_8: ## %else20 ; SSE-NEXT: movdqa %xmm1, %xmm0 ; SSE-NEXT: retq -; SSE-NEXT: LBB28_1: ## %cond.load +; SSE-NEXT: LBB28_9: ## %cond.load ; SSE-NEXT: pinsrw $0, (%rdi), %xmm1 ; SSE-NEXT: testb $2, %al -; SSE-NEXT: je LBB28_4 -; SSE-NEXT: LBB28_3: ## %cond.load1 +; SSE-NEXT: je LBB28_2 +; SSE-NEXT: LBB28_10: ## %cond.load1 ; SSE-NEXT: pinsrw $1, 2(%rdi), %xmm1 ; SSE-NEXT: testb $4, %al -; SSE-NEXT: je LBB28_6 -; SSE-NEXT: LBB28_5: ## %cond.load4 +; SSE-NEXT: je LBB28_3 +; SSE-NEXT: LBB28_11: ## %cond.load4 ; SSE-NEXT: pinsrw $2, 4(%rdi), %xmm1 ; SSE-NEXT: testb $8, %al -; SSE-NEXT: je LBB28_8 -; SSE-NEXT: LBB28_7: ## %cond.load7 +; SSE-NEXT: je LBB28_4 +; SSE-NEXT: LBB28_12: ## %cond.load7 ; SSE-NEXT: pinsrw $3, 6(%rdi), %xmm1 ; SSE-NEXT: testb $16, %al -; SSE-NEXT: je LBB28_10 -; SSE-NEXT: LBB28_9: ## %cond.load10 +; SSE-NEXT: je LBB28_5 +; SSE-NEXT: LBB28_13: ## %cond.load10 ; SSE-NEXT: pinsrw $4, 8(%rdi), %xmm1 ; SSE-NEXT: testb $32, %al -; SSE-NEXT: je LBB28_12 -; SSE-NEXT: LBB28_11: ## %cond.load13 +; SSE-NEXT: je LBB28_6 +; SSE-NEXT: LBB28_14: ## %cond.load13 ; SSE-NEXT: pinsrw $5, 10(%rdi), %xmm1 ; SSE-NEXT: testb $64, %al -; SSE-NEXT: je LBB28_14 -; SSE-NEXT: LBB28_13: ## %cond.load16 +; SSE-NEXT: je LBB28_7 +; SSE-NEXT: LBB28_15: ## %cond.load16 ; SSE-NEXT: pinsrw $6, 12(%rdi), %xmm1 ; SSE-NEXT: testb $-128, %al -; SSE-NEXT: je LBB28_16 -; SSE-NEXT: LBB28_15: ## %cond.load19 +; SSE-NEXT: je LBB28_8 +; SSE-NEXT: LBB28_16: ## %cond.load19 ; SSE-NEXT: pinsrw $7, 14(%rdi), %xmm1 ; SSE-NEXT: movdqa %xmm1, %xmm0 ; SSE-NEXT: retq @@ -3677,60 +3677,60 @@ define <8 x i16> @load_v8i16_v8i16(<8 x i16> %trigger, ptr %addr, <8 x i16> %dst ; AVX1OR2-NEXT: vpacksswb %xmm0, %xmm0, %xmm0 ; AVX1OR2-NEXT: vpmovmskb %xmm0, %eax ; AVX1OR2-NEXT: testb $1, %al -; AVX1OR2-NEXT: jne LBB28_1 -; AVX1OR2-NEXT: ## %bb.2: ## %else +; AVX1OR2-NEXT: jne LBB28_9 +; AVX1OR2-NEXT: ## %bb.1: ## %else ; AVX1OR2-NEXT: testb $2, %al -; AVX1OR2-NEXT: jne LBB28_3 -; AVX1OR2-NEXT: LBB28_4: ## %else2 +; AVX1OR2-NEXT: jne LBB28_10 +; AVX1OR2-NEXT: LBB28_2: ## %else2 ; AVX1OR2-NEXT: testb $4, %al -; AVX1OR2-NEXT: jne LBB28_5 -; AVX1OR2-NEXT: LBB28_6: ## %else5 +; AVX1OR2-NEXT: jne LBB28_11 +; AVX1OR2-NEXT: LBB28_3: ## %else5 ; AVX1OR2-NEXT: testb $8, %al -; AVX1OR2-NEXT: jne LBB28_7 -; AVX1OR2-NEXT: LBB28_8: ## %else8 +; AVX1OR2-NEXT: jne LBB28_12 +; AVX1OR2-NEXT: LBB28_4: ## %else8 ; AVX1OR2-NEXT: testb $16, %al -; AVX1OR2-NEXT: jne LBB28_9 -; AVX1OR2-NEXT: LBB28_10: ## %else11 +; AVX1OR2-NEXT: jne LBB28_13 +; AVX1OR2-NEXT: LBB28_5: ## %else11 ; AVX1OR2-NEXT: testb $32, %al -; AVX1OR2-NEXT: jne LBB28_11 -; AVX1OR2-NEXT: LBB28_12: ## %else14 +; AVX1OR2-NEXT: jne LBB28_14 +; AVX1OR2-NEXT: LBB28_6: ## %else14 ; AVX1OR2-NEXT: testb $64, %al -; AVX1OR2-NEXT: jne LBB28_13 -; AVX1OR2-NEXT: LBB28_14: ## %else17 -; AVX1OR2-NEXT: testb $-128, %al ; AVX1OR2-NEXT: jne LBB28_15 -; AVX1OR2-NEXT: LBB28_16: ## %else20 +; AVX1OR2-NEXT: LBB28_7: ## %else17 +; AVX1OR2-NEXT: testb $-128, %al +; AVX1OR2-NEXT: jne LBB28_16 +; AVX1OR2-NEXT: LBB28_8: ## %else20 ; AVX1OR2-NEXT: vmovdqa %xmm1, %xmm0 ; AVX1OR2-NEXT: retq -; AVX1OR2-NEXT: LBB28_1: ## %cond.load +; AVX1OR2-NEXT: LBB28_9: ## %cond.load ; AVX1OR2-NEXT: vpinsrw $0, (%rdi), %xmm1, %xmm1 ; AVX1OR2-NEXT: testb $2, %al -; AVX1OR2-NEXT: je LBB28_4 -; AVX1OR2-NEXT: LBB28_3: ## %cond.load1 +; AVX1OR2-NEXT: je LBB28_2 +; AVX1OR2-NEXT: LBB28_10: ## %cond.load1 ; AVX1OR2-NEXT: vpinsrw $1, 2(%rdi), %xmm1, %xmm1 ; AVX1OR2-NEXT: testb $4, %al -; AVX1OR2-NEXT: je LBB28_6 -; AVX1OR2-NEXT: LBB28_5: ## %cond.load4 +; AVX1OR2-NEXT: je LBB28_3 +; AVX1OR2-NEXT: LBB28_11: ## %cond.load4 ; AVX1OR2-NEXT: vpinsrw $2, 4(%rdi), %xmm1, %xmm1 ; AVX1OR2-NEXT: testb $8, %al -; AVX1OR2-NEXT: je LBB28_8 -; AVX1OR2-NEXT: LBB28_7: ## %cond.load7 +; AVX1OR2-NEXT: je LBB28_4 +; AVX1OR2-NEXT: LBB28_12: ## %cond.load7 ; AVX1OR2-NEXT: vpinsrw $3, 6(%rdi), %xmm1, %xmm1 ; AVX1OR2-NEXT: testb $16, %al -; AVX1OR2-NEXT: je LBB28_10 -; AVX1OR2-NEXT: LBB28_9: ## %cond.load10 +; AVX1OR2-NEXT: je LBB28_5 +; AVX1OR2-NEXT: LBB28_13: ## %cond.load10 ; AVX1OR2-NEXT: vpinsrw $4, 8(%rdi), %xmm1, %xmm1 ; AVX1OR2-NEXT: testb $32, %al -; AVX1OR2-NEXT: je LBB28_12 -; AVX1OR2-NEXT: LBB28_11: ## %cond.load13 +; AVX1OR2-NEXT: je LBB28_6 +; AVX1OR2-NEXT: LBB28_14: ## %cond.load13 ; AVX1OR2-NEXT: vpinsrw $5, 10(%rdi), %xmm1, %xmm1 ; AVX1OR2-NEXT: testb $64, %al -; AVX1OR2-NEXT: je LBB28_14 -; AVX1OR2-NEXT: LBB28_13: ## %cond.load16 +; AVX1OR2-NEXT: je LBB28_7 +; AVX1OR2-NEXT: LBB28_15: ## %cond.load16 ; AVX1OR2-NEXT: vpinsrw $6, 12(%rdi), %xmm1, %xmm1 ; AVX1OR2-NEXT: testb $-128, %al -; AVX1OR2-NEXT: je LBB28_16 -; AVX1OR2-NEXT: LBB28_15: ## %cond.load19 +; AVX1OR2-NEXT: je LBB28_8 +; AVX1OR2-NEXT: LBB28_16: ## %cond.load19 ; AVX1OR2-NEXT: vpinsrw $7, 14(%rdi), %xmm1, %xmm1 ; AVX1OR2-NEXT: vmovdqa %xmm1, %xmm0 ; AVX1OR2-NEXT: retq @@ -3743,61 +3743,61 @@ define <8 x i16> @load_v8i16_v8i16(<8 x i16> %trigger, ptr %addr, <8 x i16> %dst ; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne LBB28_1 -; AVX512F-NEXT: ## %bb.2: ## %else +; AVX512F-NEXT: jne LBB28_9 +; AVX512F-NEXT: ## %bb.1: ## %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne LBB28_3 -; AVX512F-NEXT: LBB28_4: ## %else2 +; AVX512F-NEXT: jne LBB28_10 +; AVX512F-NEXT: LBB28_2: ## %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne LBB28_5 -; AVX512F-NEXT: LBB28_6: ## %else5 +; AVX512F-NEXT: jne LBB28_11 +; AVX512F-NEXT: LBB28_3: ## %else5 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne LBB28_7 -; AVX512F-NEXT: LBB28_8: ## %else8 +; AVX512F-NEXT: jne LBB28_12 +; AVX512F-NEXT: LBB28_4: ## %else8 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne LBB28_9 -; AVX512F-NEXT: LBB28_10: ## %else11 +; AVX512F-NEXT: jne LBB28_13 +; AVX512F-NEXT: LBB28_5: ## %else11 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne LBB28_11 -; AVX512F-NEXT: LBB28_12: ## %else14 +; AVX512F-NEXT: jne LBB28_14 +; AVX512F-NEXT: LBB28_6: ## %else14 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne LBB28_13 -; AVX512F-NEXT: LBB28_14: ## %else17 -; AVX512F-NEXT: testb $-128, %al ; AVX512F-NEXT: jne LBB28_15 -; AVX512F-NEXT: LBB28_16: ## %else20 +; AVX512F-NEXT: LBB28_7: ## %else17 +; AVX512F-NEXT: testb $-128, %al +; AVX512F-NEXT: jne LBB28_16 +; AVX512F-NEXT: LBB28_8: ## %else20 ; AVX512F-NEXT: vmovdqa %xmm1, %xmm0 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: LBB28_1: ## %cond.load +; AVX512F-NEXT: LBB28_9: ## %cond.load ; AVX512F-NEXT: vpinsrw $0, (%rdi), %xmm1, %xmm1 ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je LBB28_4 -; AVX512F-NEXT: LBB28_3: ## %cond.load1 +; AVX512F-NEXT: je LBB28_2 +; AVX512F-NEXT: LBB28_10: ## %cond.load1 ; AVX512F-NEXT: vpinsrw $1, 2(%rdi), %xmm1, %xmm1 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je LBB28_6 -; AVX512F-NEXT: LBB28_5: ## %cond.load4 +; AVX512F-NEXT: je LBB28_3 +; AVX512F-NEXT: LBB28_11: ## %cond.load4 ; AVX512F-NEXT: vpinsrw $2, 4(%rdi), %xmm1, %xmm1 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je LBB28_8 -; AVX512F-NEXT: LBB28_7: ## %cond.load7 +; AVX512F-NEXT: je LBB28_4 +; AVX512F-NEXT: LBB28_12: ## %cond.load7 ; AVX512F-NEXT: vpinsrw $3, 6(%rdi), %xmm1, %xmm1 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je LBB28_10 -; AVX512F-NEXT: LBB28_9: ## %cond.load10 +; AVX512F-NEXT: je LBB28_5 +; AVX512F-NEXT: LBB28_13: ## %cond.load10 ; AVX512F-NEXT: vpinsrw $4, 8(%rdi), %xmm1, %xmm1 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je LBB28_12 -; AVX512F-NEXT: LBB28_11: ## %cond.load13 +; AVX512F-NEXT: je LBB28_6 +; AVX512F-NEXT: LBB28_14: ## %cond.load13 ; AVX512F-NEXT: vpinsrw $5, 10(%rdi), %xmm1, %xmm1 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je LBB28_14 -; AVX512F-NEXT: LBB28_13: ## %cond.load16 +; AVX512F-NEXT: je LBB28_7 +; AVX512F-NEXT: LBB28_15: ## %cond.load16 ; AVX512F-NEXT: vpinsrw $6, 12(%rdi), %xmm1, %xmm1 ; AVX512F-NEXT: testb $-128, %al -; AVX512F-NEXT: je LBB28_16 -; AVX512F-NEXT: LBB28_15: ## %cond.load19 +; AVX512F-NEXT: je LBB28_8 +; AVX512F-NEXT: LBB28_16: ## %cond.load19 ; AVX512F-NEXT: vpinsrw $7, 14(%rdi), %xmm1, %xmm1 ; AVX512F-NEXT: vmovdqa %xmm1, %xmm0 ; AVX512F-NEXT: vzeroupper @@ -3810,61 +3810,61 @@ define <8 x i16> @load_v8i16_v8i16(<8 x i16> %trigger, ptr %addr, <8 x i16> %dst ; AVX512VLDQ-NEXT: vpmovsxwd %xmm0, %ymm0 ; AVX512VLDQ-NEXT: vmovmskps %ymm0, %eax ; AVX512VLDQ-NEXT: testb $1, %al -; AVX512VLDQ-NEXT: jne LBB28_1 -; AVX512VLDQ-NEXT: ## %bb.2: ## %else +; AVX512VLDQ-NEXT: jne LBB28_9 +; AVX512VLDQ-NEXT: ## %bb.1: ## %else ; AVX512VLDQ-NEXT: testb $2, %al -; AVX512VLDQ-NEXT: jne LBB28_3 -; AVX512VLDQ-NEXT: LBB28_4: ## %else2 +; AVX512VLDQ-NEXT: jne LBB28_10 +; AVX512VLDQ-NEXT: LBB28_2: ## %else2 ; AVX512VLDQ-NEXT: testb $4, %al -; AVX512VLDQ-NEXT: jne LBB28_5 -; AVX512VLDQ-NEXT: LBB28_6: ## %else5 +; AVX512VLDQ-NEXT: jne LBB28_11 +; AVX512VLDQ-NEXT: LBB28_3: ## %else5 ; AVX512VLDQ-NEXT: testb $8, %al -; AVX512VLDQ-NEXT: jne LBB28_7 -; AVX512VLDQ-NEXT: LBB28_8: ## %else8 +; AVX512VLDQ-NEXT: jne LBB28_12 +; AVX512VLDQ-NEXT: LBB28_4: ## %else8 ; AVX512VLDQ-NEXT: testb $16, %al -; AVX512VLDQ-NEXT: jne LBB28_9 -; AVX512VLDQ-NEXT: LBB28_10: ## %else11 +; AVX512VLDQ-NEXT: jne LBB28_13 +; AVX512VLDQ-NEXT: LBB28_5: ## %else11 ; AVX512VLDQ-NEXT: testb $32, %al -; AVX512VLDQ-NEXT: jne LBB28_11 -; AVX512VLDQ-NEXT: LBB28_12: ## %else14 +; AVX512VLDQ-NEXT: jne LBB28_14 +; AVX512VLDQ-NEXT: LBB28_6: ## %else14 ; AVX512VLDQ-NEXT: testb $64, %al -; AVX512VLDQ-NEXT: jne LBB28_13 -; AVX512VLDQ-NEXT: LBB28_14: ## %else17 -; AVX512VLDQ-NEXT: testb $-128, %al ; AVX512VLDQ-NEXT: jne LBB28_15 -; AVX512VLDQ-NEXT: LBB28_16: ## %else20 +; AVX512VLDQ-NEXT: LBB28_7: ## %else17 +; AVX512VLDQ-NEXT: testb $-128, %al +; AVX512VLDQ-NEXT: jne LBB28_16 +; AVX512VLDQ-NEXT: LBB28_8: ## %else20 ; AVX512VLDQ-NEXT: vmovdqa %xmm1, %xmm0 ; AVX512VLDQ-NEXT: vzeroupper ; AVX512VLDQ-NEXT: retq -; AVX512VLDQ-NEXT: LBB28_1: ## %cond.load +; AVX512VLDQ-NEXT: LBB28_9: ## %cond.load ; AVX512VLDQ-NEXT: vpinsrw $0, (%rdi), %xmm1, %xmm1 ; AVX512VLDQ-NEXT: testb $2, %al -; AVX512VLDQ-NEXT: je LBB28_4 -; AVX512VLDQ-NEXT: LBB28_3: ## %cond.load1 +; AVX512VLDQ-NEXT: je LBB28_2 +; AVX512VLDQ-NEXT: LBB28_10: ## %cond.load1 ; AVX512VLDQ-NEXT: vpinsrw $1, 2(%rdi), %xmm1, %xmm1 ; AVX512VLDQ-NEXT: testb $4, %al -; AVX512VLDQ-NEXT: je LBB28_6 -; AVX512VLDQ-NEXT: LBB28_5: ## %cond.load4 +; AVX512VLDQ-NEXT: je LBB28_3 +; AVX512VLDQ-NEXT: LBB28_11: ## %cond.load4 ; AVX512VLDQ-NEXT: vpinsrw $2, 4(%rdi), %xmm1, %xmm1 ; AVX512VLDQ-NEXT: testb $8, %al -; AVX512VLDQ-NEXT: je LBB28_8 -; AVX512VLDQ-NEXT: LBB28_7: ## %cond.load7 +; AVX512VLDQ-NEXT: je LBB28_4 +; AVX512VLDQ-NEXT: LBB28_12: ## %cond.load7 ; AVX512VLDQ-NEXT: vpinsrw $3, 6(%rdi), %xmm1, %xmm1 ; AVX512VLDQ-NEXT: testb $16, %al -; AVX512VLDQ-NEXT: je LBB28_10 -; AVX512VLDQ-NEXT: LBB28_9: ## %cond.load10 +; AVX512VLDQ-NEXT: je LBB28_5 +; AVX512VLDQ-NEXT: LBB28_13: ## %cond.load10 ; AVX512VLDQ-NEXT: vpinsrw $4, 8(%rdi), %xmm1, %xmm1 ; AVX512VLDQ-NEXT: testb $32, %al -; AVX512VLDQ-NEXT: je LBB28_12 -; AVX512VLDQ-NEXT: LBB28_11: ## %cond.load13 +; AVX512VLDQ-NEXT: je LBB28_6 +; AVX512VLDQ-NEXT: LBB28_14: ## %cond.load13 ; AVX512VLDQ-NEXT: vpinsrw $5, 10(%rdi), %xmm1, %xmm1 ; AVX512VLDQ-NEXT: testb $64, %al -; AVX512VLDQ-NEXT: je LBB28_14 -; AVX512VLDQ-NEXT: LBB28_13: ## %cond.load16 +; AVX512VLDQ-NEXT: je LBB28_7 +; AVX512VLDQ-NEXT: LBB28_15: ## %cond.load16 ; AVX512VLDQ-NEXT: vpinsrw $6, 12(%rdi), %xmm1, %xmm1 ; AVX512VLDQ-NEXT: testb $-128, %al -; AVX512VLDQ-NEXT: je LBB28_16 -; AVX512VLDQ-NEXT: LBB28_15: ## %cond.load19 +; AVX512VLDQ-NEXT: je LBB28_8 +; AVX512VLDQ-NEXT: LBB28_16: ## %cond.load19 ; AVX512VLDQ-NEXT: vpinsrw $7, 14(%rdi), %xmm1, %xmm1 ; AVX512VLDQ-NEXT: vmovdqa %xmm1, %xmm0 ; AVX512VLDQ-NEXT: vzeroupper @@ -3893,119 +3893,119 @@ define <16 x i16> @load_v16i16_v16i16(<16 x i16> %trigger, ptr %addr, <16 x i16> ; SSE-NEXT: packsswb %xmm1, %xmm0 ; SSE-NEXT: pmovmskb %xmm0, %eax ; SSE-NEXT: testb $1, %al -; SSE-NEXT: jne LBB29_1 -; SSE-NEXT: ## %bb.2: ## %else +; SSE-NEXT: jne LBB29_18 +; SSE-NEXT: ## %bb.1: ## %else ; SSE-NEXT: testb $2, %al -; SSE-NEXT: jne LBB29_3 -; SSE-NEXT: LBB29_4: ## %else2 +; SSE-NEXT: jne LBB29_19 +; SSE-NEXT: LBB29_2: ## %else2 ; SSE-NEXT: testb $4, %al -; SSE-NEXT: jne LBB29_5 -; SSE-NEXT: LBB29_6: ## %else5 +; SSE-NEXT: jne LBB29_20 +; SSE-NEXT: LBB29_3: ## %else5 ; SSE-NEXT: testb $8, %al -; SSE-NEXT: jne LBB29_7 -; SSE-NEXT: LBB29_8: ## %else8 +; SSE-NEXT: jne LBB29_21 +; SSE-NEXT: LBB29_4: ## %else8 ; SSE-NEXT: testb $16, %al -; SSE-NEXT: jne LBB29_9 -; SSE-NEXT: LBB29_10: ## %else11 +; SSE-NEXT: jne LBB29_22 +; SSE-NEXT: LBB29_5: ## %else11 ; SSE-NEXT: testb $32, %al -; SSE-NEXT: jne LBB29_11 -; SSE-NEXT: LBB29_12: ## %else14 +; SSE-NEXT: jne LBB29_23 +; SSE-NEXT: LBB29_6: ## %else14 ; SSE-NEXT: testb $64, %al -; SSE-NEXT: jne LBB29_13 -; SSE-NEXT: LBB29_14: ## %else17 +; SSE-NEXT: jne LBB29_24 +; SSE-NEXT: LBB29_7: ## %else17 ; SSE-NEXT: testb %al, %al -; SSE-NEXT: js LBB29_15 -; SSE-NEXT: LBB29_16: ## %else20 +; SSE-NEXT: js LBB29_25 +; SSE-NEXT: LBB29_8: ## %else20 ; SSE-NEXT: testl $256, %eax ## imm = 0x100 -; SSE-NEXT: jne LBB29_17 -; SSE-NEXT: LBB29_18: ## %else23 +; SSE-NEXT: jne LBB29_26 +; SSE-NEXT: LBB29_9: ## %else23 ; SSE-NEXT: testl $512, %eax ## imm = 0x200 -; SSE-NEXT: jne LBB29_19 -; SSE-NEXT: LBB29_20: ## %else26 +; SSE-NEXT: jne LBB29_27 +; SSE-NEXT: LBB29_10: ## %else26 ; SSE-NEXT: testl $1024, %eax ## imm = 0x400 -; SSE-NEXT: jne LBB29_21 -; SSE-NEXT: LBB29_22: ## %else29 +; SSE-NEXT: jne LBB29_28 +; SSE-NEXT: LBB29_11: ## %else29 ; SSE-NEXT: testl $2048, %eax ## imm = 0x800 -; SSE-NEXT: jne LBB29_23 -; SSE-NEXT: LBB29_24: ## %else32 +; SSE-NEXT: jne LBB29_29 +; SSE-NEXT: LBB29_12: ## %else32 ; SSE-NEXT: testl $4096, %eax ## imm = 0x1000 -; SSE-NEXT: jne LBB29_25 -; SSE-NEXT: LBB29_26: ## %else35 +; SSE-NEXT: jne LBB29_30 +; SSE-NEXT: LBB29_13: ## %else35 ; SSE-NEXT: testl $8192, %eax ## imm = 0x2000 -; SSE-NEXT: jne LBB29_27 -; SSE-NEXT: LBB29_28: ## %else38 +; SSE-NEXT: jne LBB29_31 +; SSE-NEXT: LBB29_14: ## %else38 ; SSE-NEXT: testl $16384, %eax ## imm = 0x4000 -; SSE-NEXT: jne LBB29_29 -; SSE-NEXT: LBB29_30: ## %else41 +; SSE-NEXT: jne LBB29_32 +; SSE-NEXT: LBB29_15: ## %else41 ; SSE-NEXT: testl $32768, %eax ## imm = 0x8000 -; SSE-NEXT: je LBB29_32 -; SSE-NEXT: LBB29_31: ## %cond.load43 +; SSE-NEXT: je LBB29_17 +; SSE-NEXT: LBB29_16: ## %cond.load43 ; SSE-NEXT: pinsrw $7, 30(%rdi), %xmm3 -; SSE-NEXT: LBB29_32: ## %else44 +; SSE-NEXT: LBB29_17: ## %else44 ; SSE-NEXT: movdqa %xmm2, %xmm0 ; SSE-NEXT: movdqa %xmm3, %xmm1 ; SSE-NEXT: retq -; SSE-NEXT: LBB29_1: ## %cond.load +; SSE-NEXT: LBB29_18: ## %cond.load ; SSE-NEXT: pinsrw $0, (%rdi), %xmm2 ; SSE-NEXT: testb $2, %al -; SSE-NEXT: je LBB29_4 -; SSE-NEXT: LBB29_3: ## %cond.load1 +; SSE-NEXT: je LBB29_2 +; SSE-NEXT: LBB29_19: ## %cond.load1 ; SSE-NEXT: pinsrw $1, 2(%rdi), %xmm2 ; SSE-NEXT: testb $4, %al -; SSE-NEXT: je LBB29_6 -; SSE-NEXT: LBB29_5: ## %cond.load4 +; SSE-NEXT: je LBB29_3 +; SSE-NEXT: LBB29_20: ## %cond.load4 ; SSE-NEXT: pinsrw $2, 4(%rdi), %xmm2 ; SSE-NEXT: testb $8, %al -; SSE-NEXT: je LBB29_8 -; SSE-NEXT: LBB29_7: ## %cond.load7 +; SSE-NEXT: je LBB29_4 +; SSE-NEXT: LBB29_21: ## %cond.load7 ; SSE-NEXT: pinsrw $3, 6(%rdi), %xmm2 ; SSE-NEXT: testb $16, %al -; SSE-NEXT: je LBB29_10 -; SSE-NEXT: LBB29_9: ## %cond.load10 +; SSE-NEXT: je LBB29_5 +; SSE-NEXT: LBB29_22: ## %cond.load10 ; SSE-NEXT: pinsrw $4, 8(%rdi), %xmm2 ; SSE-NEXT: testb $32, %al -; SSE-NEXT: je LBB29_12 -; SSE-NEXT: LBB29_11: ## %cond.load13 +; SSE-NEXT: je LBB29_6 +; SSE-NEXT: LBB29_23: ## %cond.load13 ; SSE-NEXT: pinsrw $5, 10(%rdi), %xmm2 ; SSE-NEXT: testb $64, %al -; SSE-NEXT: je LBB29_14 -; SSE-NEXT: LBB29_13: ## %cond.load16 +; SSE-NEXT: je LBB29_7 +; SSE-NEXT: LBB29_24: ## %cond.load16 ; SSE-NEXT: pinsrw $6, 12(%rdi), %xmm2 ; SSE-NEXT: testb %al, %al -; SSE-NEXT: jns LBB29_16 -; SSE-NEXT: LBB29_15: ## %cond.load19 +; SSE-NEXT: jns LBB29_8 +; SSE-NEXT: LBB29_25: ## %cond.load19 ; SSE-NEXT: pinsrw $7, 14(%rdi), %xmm2 ; SSE-NEXT: testl $256, %eax ## imm = 0x100 -; SSE-NEXT: je LBB29_18 -; SSE-NEXT: LBB29_17: ## %cond.load22 +; SSE-NEXT: je LBB29_9 +; SSE-NEXT: LBB29_26: ## %cond.load22 ; SSE-NEXT: pinsrw $0, 16(%rdi), %xmm3 ; SSE-NEXT: testl $512, %eax ## imm = 0x200 -; SSE-NEXT: je LBB29_20 -; SSE-NEXT: LBB29_19: ## %cond.load25 +; SSE-NEXT: je LBB29_10 +; SSE-NEXT: LBB29_27: ## %cond.load25 ; SSE-NEXT: pinsrw $1, 18(%rdi), %xmm3 ; SSE-NEXT: testl $1024, %eax ## imm = 0x400 -; SSE-NEXT: je LBB29_22 -; SSE-NEXT: LBB29_21: ## %cond.load28 +; SSE-NEXT: je LBB29_11 +; SSE-NEXT: LBB29_28: ## %cond.load28 ; SSE-NEXT: pinsrw $2, 20(%rdi), %xmm3 ; SSE-NEXT: testl $2048, %eax ## imm = 0x800 -; SSE-NEXT: je LBB29_24 -; SSE-NEXT: LBB29_23: ## %cond.load31 +; SSE-NEXT: je LBB29_12 +; SSE-NEXT: LBB29_29: ## %cond.load31 ; SSE-NEXT: pinsrw $3, 22(%rdi), %xmm3 ; SSE-NEXT: testl $4096, %eax ## imm = 0x1000 -; SSE-NEXT: je LBB29_26 -; SSE-NEXT: LBB29_25: ## %cond.load34 +; SSE-NEXT: je LBB29_13 +; SSE-NEXT: LBB29_30: ## %cond.load34 ; SSE-NEXT: pinsrw $4, 24(%rdi), %xmm3 ; SSE-NEXT: testl $8192, %eax ## imm = 0x2000 -; SSE-NEXT: je LBB29_28 -; SSE-NEXT: LBB29_27: ## %cond.load37 +; SSE-NEXT: je LBB29_14 +; SSE-NEXT: LBB29_31: ## %cond.load37 ; SSE-NEXT: pinsrw $5, 26(%rdi), %xmm3 ; SSE-NEXT: testl $16384, %eax ## imm = 0x4000 -; SSE-NEXT: je LBB29_30 -; SSE-NEXT: LBB29_29: ## %cond.load40 +; SSE-NEXT: je LBB29_15 +; SSE-NEXT: LBB29_32: ## %cond.load40 ; SSE-NEXT: pinsrw $6, 28(%rdi), %xmm3 ; SSE-NEXT: testl $32768, %eax ## imm = 0x8000 -; SSE-NEXT: jne LBB29_31 -; SSE-NEXT: jmp LBB29_32 +; SSE-NEXT: jne LBB29_16 +; SSE-NEXT: jmp LBB29_17 ; ; AVX1-LABEL: load_v16i16_v16i16: ; AVX1: ## %bb.0: @@ -4013,138 +4013,138 @@ define <16 x i16> @load_v16i16_v16i16(<16 x i16> %trigger, ptr %addr, <16 x i16> ; AVX1-NEXT: vpacksswb %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vpmovmskb %xmm0, %eax ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne LBB29_1 -; AVX1-NEXT: ## %bb.2: ## %else +; AVX1-NEXT: jne LBB29_17 +; AVX1-NEXT: ## %bb.1: ## %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne LBB29_3 -; AVX1-NEXT: LBB29_4: ## %else2 +; AVX1-NEXT: jne LBB29_18 +; AVX1-NEXT: LBB29_2: ## %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne LBB29_5 -; AVX1-NEXT: LBB29_6: ## %else5 +; AVX1-NEXT: jne LBB29_19 +; AVX1-NEXT: LBB29_3: ## %else5 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne LBB29_7 -; AVX1-NEXT: LBB29_8: ## %else8 +; AVX1-NEXT: jne LBB29_20 +; AVX1-NEXT: LBB29_4: ## %else8 ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: jne LBB29_9 -; AVX1-NEXT: LBB29_10: ## %else11 +; AVX1-NEXT: jne LBB29_21 +; AVX1-NEXT: LBB29_5: ## %else11 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: jne LBB29_11 -; AVX1-NEXT: LBB29_12: ## %else14 +; AVX1-NEXT: jne LBB29_22 +; AVX1-NEXT: LBB29_6: ## %else14 ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: jne LBB29_13 -; AVX1-NEXT: LBB29_14: ## %else17 +; AVX1-NEXT: jne LBB29_23 +; AVX1-NEXT: LBB29_7: ## %else17 ; AVX1-NEXT: testb %al, %al -; AVX1-NEXT: js LBB29_15 -; AVX1-NEXT: LBB29_16: ## %else20 +; AVX1-NEXT: js LBB29_24 +; AVX1-NEXT: LBB29_8: ## %else20 ; AVX1-NEXT: testl $256, %eax ## imm = 0x100 -; AVX1-NEXT: jne LBB29_17 -; AVX1-NEXT: LBB29_18: ## %else23 +; AVX1-NEXT: jne LBB29_25 +; AVX1-NEXT: LBB29_9: ## %else23 ; AVX1-NEXT: testl $512, %eax ## imm = 0x200 -; AVX1-NEXT: jne LBB29_19 -; AVX1-NEXT: LBB29_20: ## %else26 +; AVX1-NEXT: jne LBB29_26 +; AVX1-NEXT: LBB29_10: ## %else26 ; AVX1-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX1-NEXT: jne LBB29_21 -; AVX1-NEXT: LBB29_22: ## %else29 +; AVX1-NEXT: jne LBB29_27 +; AVX1-NEXT: LBB29_11: ## %else29 ; AVX1-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX1-NEXT: jne LBB29_23 -; AVX1-NEXT: LBB29_24: ## %else32 +; AVX1-NEXT: jne LBB29_28 +; AVX1-NEXT: LBB29_12: ## %else32 ; AVX1-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX1-NEXT: jne LBB29_25 -; AVX1-NEXT: LBB29_26: ## %else35 +; AVX1-NEXT: jne LBB29_29 +; AVX1-NEXT: LBB29_13: ## %else35 ; AVX1-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX1-NEXT: jne LBB29_27 -; AVX1-NEXT: LBB29_28: ## %else38 +; AVX1-NEXT: jne LBB29_30 +; AVX1-NEXT: LBB29_14: ## %else38 ; AVX1-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX1-NEXT: jne LBB29_29 -; AVX1-NEXT: LBB29_30: ## %else41 -; AVX1-NEXT: testl $32768, %eax ## imm = 0x8000 ; AVX1-NEXT: jne LBB29_31 -; AVX1-NEXT: LBB29_32: ## %else44 +; AVX1-NEXT: LBB29_15: ## %else41 +; AVX1-NEXT: testl $32768, %eax ## imm = 0x8000 +; AVX1-NEXT: jne LBB29_32 +; AVX1-NEXT: LBB29_16: ## %else44 ; AVX1-NEXT: vmovaps %ymm1, %ymm0 ; AVX1-NEXT: retq -; AVX1-NEXT: LBB29_1: ## %cond.load +; AVX1-NEXT: LBB29_17: ## %cond.load ; AVX1-NEXT: vpinsrw $0, (%rdi), %xmm1, %xmm0 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je LBB29_4 -; AVX1-NEXT: LBB29_3: ## %cond.load1 +; AVX1-NEXT: je LBB29_2 +; AVX1-NEXT: LBB29_18: ## %cond.load1 ; AVX1-NEXT: vpinsrw $1, 2(%rdi), %xmm1, %xmm0 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je LBB29_6 -; AVX1-NEXT: LBB29_5: ## %cond.load4 +; AVX1-NEXT: je LBB29_3 +; AVX1-NEXT: LBB29_19: ## %cond.load4 ; AVX1-NEXT: vpinsrw $2, 4(%rdi), %xmm1, %xmm0 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je LBB29_8 -; AVX1-NEXT: LBB29_7: ## %cond.load7 +; AVX1-NEXT: je LBB29_4 +; AVX1-NEXT: LBB29_20: ## %cond.load7 ; AVX1-NEXT: vpinsrw $3, 6(%rdi), %xmm1, %xmm0 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: je LBB29_10 -; AVX1-NEXT: LBB29_9: ## %cond.load10 +; AVX1-NEXT: je LBB29_5 +; AVX1-NEXT: LBB29_21: ## %cond.load10 ; AVX1-NEXT: vpinsrw $4, 8(%rdi), %xmm1, %xmm0 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je LBB29_12 -; AVX1-NEXT: LBB29_11: ## %cond.load13 +; AVX1-NEXT: je LBB29_6 +; AVX1-NEXT: LBB29_22: ## %cond.load13 ; AVX1-NEXT: vpinsrw $5, 10(%rdi), %xmm1, %xmm0 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: je LBB29_14 -; AVX1-NEXT: LBB29_13: ## %cond.load16 +; AVX1-NEXT: je LBB29_7 +; AVX1-NEXT: LBB29_23: ## %cond.load16 ; AVX1-NEXT: vpinsrw $6, 12(%rdi), %xmm1, %xmm0 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX1-NEXT: testb %al, %al -; AVX1-NEXT: jns LBB29_16 -; AVX1-NEXT: LBB29_15: ## %cond.load19 +; AVX1-NEXT: jns LBB29_8 +; AVX1-NEXT: LBB29_24: ## %cond.load19 ; AVX1-NEXT: vpinsrw $7, 14(%rdi), %xmm1, %xmm0 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX1-NEXT: testl $256, %eax ## imm = 0x100 -; AVX1-NEXT: je LBB29_18 -; AVX1-NEXT: LBB29_17: ## %cond.load22 +; AVX1-NEXT: je LBB29_9 +; AVX1-NEXT: LBB29_25: ## %cond.load22 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm0 ; AVX1-NEXT: vpinsrw $0, 16(%rdi), %xmm0, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm1 ; AVX1-NEXT: testl $512, %eax ## imm = 0x200 -; AVX1-NEXT: je LBB29_20 -; AVX1-NEXT: LBB29_19: ## %cond.load25 +; AVX1-NEXT: je LBB29_10 +; AVX1-NEXT: LBB29_26: ## %cond.load25 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm0 ; AVX1-NEXT: vpinsrw $1, 18(%rdi), %xmm0, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm1 ; AVX1-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX1-NEXT: je LBB29_22 -; AVX1-NEXT: LBB29_21: ## %cond.load28 +; AVX1-NEXT: je LBB29_11 +; AVX1-NEXT: LBB29_27: ## %cond.load28 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm0 ; AVX1-NEXT: vpinsrw $2, 20(%rdi), %xmm0, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm1 ; AVX1-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX1-NEXT: je LBB29_24 -; AVX1-NEXT: LBB29_23: ## %cond.load31 +; AVX1-NEXT: je LBB29_12 +; AVX1-NEXT: LBB29_28: ## %cond.load31 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm0 ; AVX1-NEXT: vpinsrw $3, 22(%rdi), %xmm0, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm1 ; AVX1-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX1-NEXT: je LBB29_26 -; AVX1-NEXT: LBB29_25: ## %cond.load34 +; AVX1-NEXT: je LBB29_13 +; AVX1-NEXT: LBB29_29: ## %cond.load34 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm0 ; AVX1-NEXT: vpinsrw $4, 24(%rdi), %xmm0, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm1 ; AVX1-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX1-NEXT: je LBB29_28 -; AVX1-NEXT: LBB29_27: ## %cond.load37 +; AVX1-NEXT: je LBB29_14 +; AVX1-NEXT: LBB29_30: ## %cond.load37 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm0 ; AVX1-NEXT: vpinsrw $5, 26(%rdi), %xmm0, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm1 ; AVX1-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX1-NEXT: je LBB29_30 -; AVX1-NEXT: LBB29_29: ## %cond.load40 +; AVX1-NEXT: je LBB29_15 +; AVX1-NEXT: LBB29_31: ## %cond.load40 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm0 ; AVX1-NEXT: vpinsrw $6, 28(%rdi), %xmm0, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm1 ; AVX1-NEXT: testl $32768, %eax ## imm = 0x8000 -; AVX1-NEXT: je LBB29_32 -; AVX1-NEXT: LBB29_31: ## %cond.load43 +; AVX1-NEXT: je LBB29_16 +; AVX1-NEXT: LBB29_32: ## %cond.load43 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm0 ; AVX1-NEXT: vpinsrw $7, 30(%rdi), %xmm0, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm1 @@ -4157,138 +4157,138 @@ define <16 x i16> @load_v16i16_v16i16(<16 x i16> %trigger, ptr %addr, <16 x i16> ; AVX2-NEXT: vpacksswb %xmm2, %xmm0, %xmm0 ; AVX2-NEXT: vpmovmskb %xmm0, %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne LBB29_1 -; AVX2-NEXT: ## %bb.2: ## %else +; AVX2-NEXT: jne LBB29_17 +; AVX2-NEXT: ## %bb.1: ## %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne LBB29_3 -; AVX2-NEXT: LBB29_4: ## %else2 +; AVX2-NEXT: jne LBB29_18 +; AVX2-NEXT: LBB29_2: ## %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne LBB29_5 -; AVX2-NEXT: LBB29_6: ## %else5 +; AVX2-NEXT: jne LBB29_19 +; AVX2-NEXT: LBB29_3: ## %else5 ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: jne LBB29_7 -; AVX2-NEXT: LBB29_8: ## %else8 +; AVX2-NEXT: jne LBB29_20 +; AVX2-NEXT: LBB29_4: ## %else8 ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: jne LBB29_9 -; AVX2-NEXT: LBB29_10: ## %else11 +; AVX2-NEXT: jne LBB29_21 +; AVX2-NEXT: LBB29_5: ## %else11 ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: jne LBB29_11 -; AVX2-NEXT: LBB29_12: ## %else14 +; AVX2-NEXT: jne LBB29_22 +; AVX2-NEXT: LBB29_6: ## %else14 ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: jne LBB29_13 -; AVX2-NEXT: LBB29_14: ## %else17 +; AVX2-NEXT: jne LBB29_23 +; AVX2-NEXT: LBB29_7: ## %else17 ; AVX2-NEXT: testb %al, %al -; AVX2-NEXT: js LBB29_15 -; AVX2-NEXT: LBB29_16: ## %else20 +; AVX2-NEXT: js LBB29_24 +; AVX2-NEXT: LBB29_8: ## %else20 ; AVX2-NEXT: testl $256, %eax ## imm = 0x100 -; AVX2-NEXT: jne LBB29_17 -; AVX2-NEXT: LBB29_18: ## %else23 +; AVX2-NEXT: jne LBB29_25 +; AVX2-NEXT: LBB29_9: ## %else23 ; AVX2-NEXT: testl $512, %eax ## imm = 0x200 -; AVX2-NEXT: jne LBB29_19 -; AVX2-NEXT: LBB29_20: ## %else26 +; AVX2-NEXT: jne LBB29_26 +; AVX2-NEXT: LBB29_10: ## %else26 ; AVX2-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX2-NEXT: jne LBB29_21 -; AVX2-NEXT: LBB29_22: ## %else29 +; AVX2-NEXT: jne LBB29_27 +; AVX2-NEXT: LBB29_11: ## %else29 ; AVX2-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX2-NEXT: jne LBB29_23 -; AVX2-NEXT: LBB29_24: ## %else32 +; AVX2-NEXT: jne LBB29_28 +; AVX2-NEXT: LBB29_12: ## %else32 ; AVX2-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX2-NEXT: jne LBB29_25 -; AVX2-NEXT: LBB29_26: ## %else35 +; AVX2-NEXT: jne LBB29_29 +; AVX2-NEXT: LBB29_13: ## %else35 ; AVX2-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX2-NEXT: jne LBB29_27 -; AVX2-NEXT: LBB29_28: ## %else38 +; AVX2-NEXT: jne LBB29_30 +; AVX2-NEXT: LBB29_14: ## %else38 ; AVX2-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX2-NEXT: jne LBB29_29 -; AVX2-NEXT: LBB29_30: ## %else41 -; AVX2-NEXT: testl $32768, %eax ## imm = 0x8000 ; AVX2-NEXT: jne LBB29_31 -; AVX2-NEXT: LBB29_32: ## %else44 +; AVX2-NEXT: LBB29_15: ## %else41 +; AVX2-NEXT: testl $32768, %eax ## imm = 0x8000 +; AVX2-NEXT: jne LBB29_32 +; AVX2-NEXT: LBB29_16: ## %else44 ; AVX2-NEXT: vmovdqa %ymm1, %ymm0 ; AVX2-NEXT: retq -; AVX2-NEXT: LBB29_1: ## %cond.load +; AVX2-NEXT: LBB29_17: ## %cond.load ; AVX2-NEXT: vpinsrw $0, (%rdi), %xmm1, %xmm0 ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je LBB29_4 -; AVX2-NEXT: LBB29_3: ## %cond.load1 +; AVX2-NEXT: je LBB29_2 +; AVX2-NEXT: LBB29_18: ## %cond.load1 ; AVX2-NEXT: vpinsrw $1, 2(%rdi), %xmm1, %xmm0 ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je LBB29_6 -; AVX2-NEXT: LBB29_5: ## %cond.load4 +; AVX2-NEXT: je LBB29_3 +; AVX2-NEXT: LBB29_19: ## %cond.load4 ; AVX2-NEXT: vpinsrw $2, 4(%rdi), %xmm1, %xmm0 ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je LBB29_8 -; AVX2-NEXT: LBB29_7: ## %cond.load7 +; AVX2-NEXT: je LBB29_4 +; AVX2-NEXT: LBB29_20: ## %cond.load7 ; AVX2-NEXT: vpinsrw $3, 6(%rdi), %xmm1, %xmm0 ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: je LBB29_10 -; AVX2-NEXT: LBB29_9: ## %cond.load10 +; AVX2-NEXT: je LBB29_5 +; AVX2-NEXT: LBB29_21: ## %cond.load10 ; AVX2-NEXT: vpinsrw $4, 8(%rdi), %xmm1, %xmm0 ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: je LBB29_12 -; AVX2-NEXT: LBB29_11: ## %cond.load13 +; AVX2-NEXT: je LBB29_6 +; AVX2-NEXT: LBB29_22: ## %cond.load13 ; AVX2-NEXT: vpinsrw $5, 10(%rdi), %xmm1, %xmm0 ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: je LBB29_14 -; AVX2-NEXT: LBB29_13: ## %cond.load16 +; AVX2-NEXT: je LBB29_7 +; AVX2-NEXT: LBB29_23: ## %cond.load16 ; AVX2-NEXT: vpinsrw $6, 12(%rdi), %xmm1, %xmm0 ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX2-NEXT: testb %al, %al -; AVX2-NEXT: jns LBB29_16 -; AVX2-NEXT: LBB29_15: ## %cond.load19 +; AVX2-NEXT: jns LBB29_8 +; AVX2-NEXT: LBB29_24: ## %cond.load19 ; AVX2-NEXT: vpinsrw $7, 14(%rdi), %xmm1, %xmm0 ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX2-NEXT: testl $256, %eax ## imm = 0x100 -; AVX2-NEXT: je LBB29_18 -; AVX2-NEXT: LBB29_17: ## %cond.load22 +; AVX2-NEXT: je LBB29_9 +; AVX2-NEXT: LBB29_25: ## %cond.load22 ; AVX2-NEXT: vpbroadcastw 16(%rdi), %ymm0 ; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3,4,5,6,7],ymm0[8],ymm1[9,10,11,12,13,14,15] ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm0[4,5,6,7] ; AVX2-NEXT: testl $512, %eax ## imm = 0x200 -; AVX2-NEXT: je LBB29_20 -; AVX2-NEXT: LBB29_19: ## %cond.load25 +; AVX2-NEXT: je LBB29_10 +; AVX2-NEXT: LBB29_26: ## %cond.load25 ; AVX2-NEXT: vpbroadcastw 18(%rdi), %ymm0 ; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2,3,4,5,6,7,8],ymm0[9],ymm1[10,11,12,13,14,15] ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm0[4,5,6,7] ; AVX2-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX2-NEXT: je LBB29_22 -; AVX2-NEXT: LBB29_21: ## %cond.load28 +; AVX2-NEXT: je LBB29_11 +; AVX2-NEXT: LBB29_27: ## %cond.load28 ; AVX2-NEXT: vpbroadcastw 20(%rdi), %ymm0 ; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1],ymm0[2],ymm1[3,4,5,6,7,8,9],ymm0[10],ymm1[11,12,13,14,15] ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm0[4,5,6,7] ; AVX2-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX2-NEXT: je LBB29_24 -; AVX2-NEXT: LBB29_23: ## %cond.load31 +; AVX2-NEXT: je LBB29_12 +; AVX2-NEXT: LBB29_28: ## %cond.load31 ; AVX2-NEXT: vpbroadcastw 22(%rdi), %ymm0 ; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3],ymm1[4,5,6,7,8,9,10],ymm0[11],ymm1[12,13,14,15] ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm0[4,5,6,7] ; AVX2-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX2-NEXT: je LBB29_26 -; AVX2-NEXT: LBB29_25: ## %cond.load34 +; AVX2-NEXT: je LBB29_13 +; AVX2-NEXT: LBB29_29: ## %cond.load34 ; AVX2-NEXT: vpbroadcastw 24(%rdi), %ymm0 ; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4],ymm1[5,6,7,8,9,10,11],ymm0[12],ymm1[13,14,15] ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm0[4,5,6,7] ; AVX2-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX2-NEXT: je LBB29_28 -; AVX2-NEXT: LBB29_27: ## %cond.load37 +; AVX2-NEXT: je LBB29_14 +; AVX2-NEXT: LBB29_30: ## %cond.load37 ; AVX2-NEXT: vpbroadcastw 26(%rdi), %ymm0 ; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1,2,3,4],ymm0[5],ymm1[6,7,8,9,10,11,12],ymm0[13],ymm1[14,15] ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm0[4,5,6,7] ; AVX2-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX2-NEXT: je LBB29_30 -; AVX2-NEXT: LBB29_29: ## %cond.load40 +; AVX2-NEXT: je LBB29_15 +; AVX2-NEXT: LBB29_31: ## %cond.load40 ; AVX2-NEXT: vpbroadcastw 28(%rdi), %ymm0 ; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1,2,3,4,5],ymm0[6],ymm1[7,8,9,10,11,12,13],ymm0[14],ymm1[15] ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm0[4,5,6,7] ; AVX2-NEXT: testl $32768, %eax ## imm = 0x8000 -; AVX2-NEXT: je LBB29_32 -; AVX2-NEXT: LBB29_31: ## %cond.load43 +; AVX2-NEXT: je LBB29_16 +; AVX2-NEXT: LBB29_32: ## %cond.load43 ; AVX2-NEXT: vpbroadcastw 30(%rdi), %ymm0 ; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1,2,3,4,5,6],ymm0[7],ymm1[8,9,10,11,12,13,14],ymm0[15] ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm0[4,5,6,7] @@ -4303,138 +4303,138 @@ define <16 x i16> @load_v16i16_v16i16(<16 x i16> %trigger, ptr %addr, <16 x i16> ; AVX512F-NEXT: vptestmd %zmm0, %zmm0, %k0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne LBB29_1 -; AVX512F-NEXT: ## %bb.2: ## %else +; AVX512F-NEXT: jne LBB29_17 +; AVX512F-NEXT: ## %bb.1: ## %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne LBB29_3 -; AVX512F-NEXT: LBB29_4: ## %else2 +; AVX512F-NEXT: jne LBB29_18 +; AVX512F-NEXT: LBB29_2: ## %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne LBB29_5 -; AVX512F-NEXT: LBB29_6: ## %else5 +; AVX512F-NEXT: jne LBB29_19 +; AVX512F-NEXT: LBB29_3: ## %else5 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne LBB29_7 -; AVX512F-NEXT: LBB29_8: ## %else8 +; AVX512F-NEXT: jne LBB29_20 +; AVX512F-NEXT: LBB29_4: ## %else8 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne LBB29_9 -; AVX512F-NEXT: LBB29_10: ## %else11 +; AVX512F-NEXT: jne LBB29_21 +; AVX512F-NEXT: LBB29_5: ## %else11 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne LBB29_11 -; AVX512F-NEXT: LBB29_12: ## %else14 +; AVX512F-NEXT: jne LBB29_22 +; AVX512F-NEXT: LBB29_6: ## %else14 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne LBB29_13 -; AVX512F-NEXT: LBB29_14: ## %else17 +; AVX512F-NEXT: jne LBB29_23 +; AVX512F-NEXT: LBB29_7: ## %else17 ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: js LBB29_15 -; AVX512F-NEXT: LBB29_16: ## %else20 +; AVX512F-NEXT: js LBB29_24 +; AVX512F-NEXT: LBB29_8: ## %else20 ; AVX512F-NEXT: testl $256, %eax ## imm = 0x100 -; AVX512F-NEXT: jne LBB29_17 -; AVX512F-NEXT: LBB29_18: ## %else23 +; AVX512F-NEXT: jne LBB29_25 +; AVX512F-NEXT: LBB29_9: ## %else23 ; AVX512F-NEXT: testl $512, %eax ## imm = 0x200 -; AVX512F-NEXT: jne LBB29_19 -; AVX512F-NEXT: LBB29_20: ## %else26 +; AVX512F-NEXT: jne LBB29_26 +; AVX512F-NEXT: LBB29_10: ## %else26 ; AVX512F-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX512F-NEXT: jne LBB29_21 -; AVX512F-NEXT: LBB29_22: ## %else29 +; AVX512F-NEXT: jne LBB29_27 +; AVX512F-NEXT: LBB29_11: ## %else29 ; AVX512F-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX512F-NEXT: jne LBB29_23 -; AVX512F-NEXT: LBB29_24: ## %else32 +; AVX512F-NEXT: jne LBB29_28 +; AVX512F-NEXT: LBB29_12: ## %else32 ; AVX512F-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX512F-NEXT: jne LBB29_25 -; AVX512F-NEXT: LBB29_26: ## %else35 +; AVX512F-NEXT: jne LBB29_29 +; AVX512F-NEXT: LBB29_13: ## %else35 ; AVX512F-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX512F-NEXT: jne LBB29_27 -; AVX512F-NEXT: LBB29_28: ## %else38 +; AVX512F-NEXT: jne LBB29_30 +; AVX512F-NEXT: LBB29_14: ## %else38 ; AVX512F-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX512F-NEXT: jne LBB29_29 -; AVX512F-NEXT: LBB29_30: ## %else41 -; AVX512F-NEXT: testl $32768, %eax ## imm = 0x8000 ; AVX512F-NEXT: jne LBB29_31 -; AVX512F-NEXT: LBB29_32: ## %else44 +; AVX512F-NEXT: LBB29_15: ## %else41 +; AVX512F-NEXT: testl $32768, %eax ## imm = 0x8000 +; AVX512F-NEXT: jne LBB29_32 +; AVX512F-NEXT: LBB29_16: ## %else44 ; AVX512F-NEXT: vmovdqa %ymm1, %ymm0 ; AVX512F-NEXT: retq -; AVX512F-NEXT: LBB29_1: ## %cond.load +; AVX512F-NEXT: LBB29_17: ## %cond.load ; AVX512F-NEXT: vpinsrw $0, (%rdi), %xmm1, %xmm0 ; AVX512F-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je LBB29_4 -; AVX512F-NEXT: LBB29_3: ## %cond.load1 +; AVX512F-NEXT: je LBB29_2 +; AVX512F-NEXT: LBB29_18: ## %cond.load1 ; AVX512F-NEXT: vpinsrw $1, 2(%rdi), %xmm1, %xmm0 ; AVX512F-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je LBB29_6 -; AVX512F-NEXT: LBB29_5: ## %cond.load4 +; AVX512F-NEXT: je LBB29_3 +; AVX512F-NEXT: LBB29_19: ## %cond.load4 ; AVX512F-NEXT: vpinsrw $2, 4(%rdi), %xmm1, %xmm0 ; AVX512F-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je LBB29_8 -; AVX512F-NEXT: LBB29_7: ## %cond.load7 +; AVX512F-NEXT: je LBB29_4 +; AVX512F-NEXT: LBB29_20: ## %cond.load7 ; AVX512F-NEXT: vpinsrw $3, 6(%rdi), %xmm1, %xmm0 ; AVX512F-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je LBB29_10 -; AVX512F-NEXT: LBB29_9: ## %cond.load10 +; AVX512F-NEXT: je LBB29_5 +; AVX512F-NEXT: LBB29_21: ## %cond.load10 ; AVX512F-NEXT: vpinsrw $4, 8(%rdi), %xmm1, %xmm0 ; AVX512F-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je LBB29_12 -; AVX512F-NEXT: LBB29_11: ## %cond.load13 +; AVX512F-NEXT: je LBB29_6 +; AVX512F-NEXT: LBB29_22: ## %cond.load13 ; AVX512F-NEXT: vpinsrw $5, 10(%rdi), %xmm1, %xmm0 ; AVX512F-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je LBB29_14 -; AVX512F-NEXT: LBB29_13: ## %cond.load16 +; AVX512F-NEXT: je LBB29_7 +; AVX512F-NEXT: LBB29_23: ## %cond.load16 ; AVX512F-NEXT: vpinsrw $6, 12(%rdi), %xmm1, %xmm0 ; AVX512F-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: jns LBB29_16 -; AVX512F-NEXT: LBB29_15: ## %cond.load19 +; AVX512F-NEXT: jns LBB29_8 +; AVX512F-NEXT: LBB29_24: ## %cond.load19 ; AVX512F-NEXT: vpinsrw $7, 14(%rdi), %xmm1, %xmm0 ; AVX512F-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512F-NEXT: testl $256, %eax ## imm = 0x100 -; AVX512F-NEXT: je LBB29_18 -; AVX512F-NEXT: LBB29_17: ## %cond.load22 +; AVX512F-NEXT: je LBB29_9 +; AVX512F-NEXT: LBB29_25: ## %cond.load22 ; AVX512F-NEXT: vpbroadcastw 16(%rdi), %ymm0 ; AVX512F-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3,4,5,6,7],ymm0[8],ymm1[9,10,11,12,13,14,15] ; AVX512F-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm0[4,5,6,7] ; AVX512F-NEXT: testl $512, %eax ## imm = 0x200 -; AVX512F-NEXT: je LBB29_20 -; AVX512F-NEXT: LBB29_19: ## %cond.load25 +; AVX512F-NEXT: je LBB29_10 +; AVX512F-NEXT: LBB29_26: ## %cond.load25 ; AVX512F-NEXT: vpbroadcastw 18(%rdi), %ymm0 ; AVX512F-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2,3,4,5,6,7,8],ymm0[9],ymm1[10,11,12,13,14,15] ; AVX512F-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm0[4,5,6,7] ; AVX512F-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX512F-NEXT: je LBB29_22 -; AVX512F-NEXT: LBB29_21: ## %cond.load28 +; AVX512F-NEXT: je LBB29_11 +; AVX512F-NEXT: LBB29_27: ## %cond.load28 ; AVX512F-NEXT: vpbroadcastw 20(%rdi), %ymm0 ; AVX512F-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1],ymm0[2],ymm1[3,4,5,6,7,8,9],ymm0[10],ymm1[11,12,13,14,15] ; AVX512F-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm0[4,5,6,7] ; AVX512F-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX512F-NEXT: je LBB29_24 -; AVX512F-NEXT: LBB29_23: ## %cond.load31 +; AVX512F-NEXT: je LBB29_12 +; AVX512F-NEXT: LBB29_28: ## %cond.load31 ; AVX512F-NEXT: vpbroadcastw 22(%rdi), %ymm0 ; AVX512F-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3],ymm1[4,5,6,7,8,9,10],ymm0[11],ymm1[12,13,14,15] ; AVX512F-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm0[4,5,6,7] ; AVX512F-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX512F-NEXT: je LBB29_26 -; AVX512F-NEXT: LBB29_25: ## %cond.load34 +; AVX512F-NEXT: je LBB29_13 +; AVX512F-NEXT: LBB29_29: ## %cond.load34 ; AVX512F-NEXT: vpbroadcastw 24(%rdi), %ymm0 ; AVX512F-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4],ymm1[5,6,7,8,9,10,11],ymm0[12],ymm1[13,14,15] ; AVX512F-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm0[4,5,6,7] ; AVX512F-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX512F-NEXT: je LBB29_28 -; AVX512F-NEXT: LBB29_27: ## %cond.load37 +; AVX512F-NEXT: je LBB29_14 +; AVX512F-NEXT: LBB29_30: ## %cond.load37 ; AVX512F-NEXT: vpbroadcastw 26(%rdi), %ymm0 ; AVX512F-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1,2,3,4],ymm0[5],ymm1[6,7,8,9,10,11,12],ymm0[13],ymm1[14,15] ; AVX512F-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm0[4,5,6,7] ; AVX512F-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX512F-NEXT: je LBB29_30 -; AVX512F-NEXT: LBB29_29: ## %cond.load40 +; AVX512F-NEXT: je LBB29_15 +; AVX512F-NEXT: LBB29_31: ## %cond.load40 ; AVX512F-NEXT: vpbroadcastw 28(%rdi), %ymm0 ; AVX512F-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1,2,3,4,5],ymm0[6],ymm1[7,8,9,10,11,12,13],ymm0[14],ymm1[15] ; AVX512F-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm0[4,5,6,7] ; AVX512F-NEXT: testl $32768, %eax ## imm = 0x8000 -; AVX512F-NEXT: je LBB29_32 -; AVX512F-NEXT: LBB29_31: ## %cond.load43 +; AVX512F-NEXT: je LBB29_16 +; AVX512F-NEXT: LBB29_32: ## %cond.load43 ; AVX512F-NEXT: vpbroadcastw 30(%rdi), %ymm0 ; AVX512F-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1,2,3,4,5,6],ymm0[7],ymm1[8,9,10,11,12,13,14],ymm0[15] ; AVX512F-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm0[4,5,6,7] @@ -4449,138 +4449,138 @@ define <16 x i16> @load_v16i16_v16i16(<16 x i16> %trigger, ptr %addr, <16 x i16> ; AVX512VLDQ-NEXT: vpmovd2m %zmm0, %k0 ; AVX512VLDQ-NEXT: kmovw %k0, %eax ; AVX512VLDQ-NEXT: testb $1, %al -; AVX512VLDQ-NEXT: jne LBB29_1 -; AVX512VLDQ-NEXT: ## %bb.2: ## %else +; AVX512VLDQ-NEXT: jne LBB29_17 +; AVX512VLDQ-NEXT: ## %bb.1: ## %else ; AVX512VLDQ-NEXT: testb $2, %al -; AVX512VLDQ-NEXT: jne LBB29_3 -; AVX512VLDQ-NEXT: LBB29_4: ## %else2 +; AVX512VLDQ-NEXT: jne LBB29_18 +; AVX512VLDQ-NEXT: LBB29_2: ## %else2 ; AVX512VLDQ-NEXT: testb $4, %al -; AVX512VLDQ-NEXT: jne LBB29_5 -; AVX512VLDQ-NEXT: LBB29_6: ## %else5 +; AVX512VLDQ-NEXT: jne LBB29_19 +; AVX512VLDQ-NEXT: LBB29_3: ## %else5 ; AVX512VLDQ-NEXT: testb $8, %al -; AVX512VLDQ-NEXT: jne LBB29_7 -; AVX512VLDQ-NEXT: LBB29_8: ## %else8 +; AVX512VLDQ-NEXT: jne LBB29_20 +; AVX512VLDQ-NEXT: LBB29_4: ## %else8 ; AVX512VLDQ-NEXT: testb $16, %al -; AVX512VLDQ-NEXT: jne LBB29_9 -; AVX512VLDQ-NEXT: LBB29_10: ## %else11 +; AVX512VLDQ-NEXT: jne LBB29_21 +; AVX512VLDQ-NEXT: LBB29_5: ## %else11 ; AVX512VLDQ-NEXT: testb $32, %al -; AVX512VLDQ-NEXT: jne LBB29_11 -; AVX512VLDQ-NEXT: LBB29_12: ## %else14 +; AVX512VLDQ-NEXT: jne LBB29_22 +; AVX512VLDQ-NEXT: LBB29_6: ## %else14 ; AVX512VLDQ-NEXT: testb $64, %al -; AVX512VLDQ-NEXT: jne LBB29_13 -; AVX512VLDQ-NEXT: LBB29_14: ## %else17 +; AVX512VLDQ-NEXT: jne LBB29_23 +; AVX512VLDQ-NEXT: LBB29_7: ## %else17 ; AVX512VLDQ-NEXT: testb %al, %al -; AVX512VLDQ-NEXT: js LBB29_15 -; AVX512VLDQ-NEXT: LBB29_16: ## %else20 +; AVX512VLDQ-NEXT: js LBB29_24 +; AVX512VLDQ-NEXT: LBB29_8: ## %else20 ; AVX512VLDQ-NEXT: testl $256, %eax ## imm = 0x100 -; AVX512VLDQ-NEXT: jne LBB29_17 -; AVX512VLDQ-NEXT: LBB29_18: ## %else23 +; AVX512VLDQ-NEXT: jne LBB29_25 +; AVX512VLDQ-NEXT: LBB29_9: ## %else23 ; AVX512VLDQ-NEXT: testl $512, %eax ## imm = 0x200 -; AVX512VLDQ-NEXT: jne LBB29_19 -; AVX512VLDQ-NEXT: LBB29_20: ## %else26 +; AVX512VLDQ-NEXT: jne LBB29_26 +; AVX512VLDQ-NEXT: LBB29_10: ## %else26 ; AVX512VLDQ-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX512VLDQ-NEXT: jne LBB29_21 -; AVX512VLDQ-NEXT: LBB29_22: ## %else29 +; AVX512VLDQ-NEXT: jne LBB29_27 +; AVX512VLDQ-NEXT: LBB29_11: ## %else29 ; AVX512VLDQ-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX512VLDQ-NEXT: jne LBB29_23 -; AVX512VLDQ-NEXT: LBB29_24: ## %else32 +; AVX512VLDQ-NEXT: jne LBB29_28 +; AVX512VLDQ-NEXT: LBB29_12: ## %else32 ; AVX512VLDQ-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX512VLDQ-NEXT: jne LBB29_25 -; AVX512VLDQ-NEXT: LBB29_26: ## %else35 +; AVX512VLDQ-NEXT: jne LBB29_29 +; AVX512VLDQ-NEXT: LBB29_13: ## %else35 ; AVX512VLDQ-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX512VLDQ-NEXT: jne LBB29_27 -; AVX512VLDQ-NEXT: LBB29_28: ## %else38 +; AVX512VLDQ-NEXT: jne LBB29_30 +; AVX512VLDQ-NEXT: LBB29_14: ## %else38 ; AVX512VLDQ-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX512VLDQ-NEXT: jne LBB29_29 -; AVX512VLDQ-NEXT: LBB29_30: ## %else41 -; AVX512VLDQ-NEXT: testl $32768, %eax ## imm = 0x8000 ; AVX512VLDQ-NEXT: jne LBB29_31 -; AVX512VLDQ-NEXT: LBB29_32: ## %else44 +; AVX512VLDQ-NEXT: LBB29_15: ## %else41 +; AVX512VLDQ-NEXT: testl $32768, %eax ## imm = 0x8000 +; AVX512VLDQ-NEXT: jne LBB29_32 +; AVX512VLDQ-NEXT: LBB29_16: ## %else44 ; AVX512VLDQ-NEXT: vmovdqa %ymm1, %ymm0 ; AVX512VLDQ-NEXT: retq -; AVX512VLDQ-NEXT: LBB29_1: ## %cond.load +; AVX512VLDQ-NEXT: LBB29_17: ## %cond.load ; AVX512VLDQ-NEXT: vpinsrw $0, (%rdi), %xmm1, %xmm0 ; AVX512VLDQ-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512VLDQ-NEXT: testb $2, %al -; AVX512VLDQ-NEXT: je LBB29_4 -; AVX512VLDQ-NEXT: LBB29_3: ## %cond.load1 +; AVX512VLDQ-NEXT: je LBB29_2 +; AVX512VLDQ-NEXT: LBB29_18: ## %cond.load1 ; AVX512VLDQ-NEXT: vpinsrw $1, 2(%rdi), %xmm1, %xmm0 ; AVX512VLDQ-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512VLDQ-NEXT: testb $4, %al -; AVX512VLDQ-NEXT: je LBB29_6 -; AVX512VLDQ-NEXT: LBB29_5: ## %cond.load4 +; AVX512VLDQ-NEXT: je LBB29_3 +; AVX512VLDQ-NEXT: LBB29_19: ## %cond.load4 ; AVX512VLDQ-NEXT: vpinsrw $2, 4(%rdi), %xmm1, %xmm0 ; AVX512VLDQ-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512VLDQ-NEXT: testb $8, %al -; AVX512VLDQ-NEXT: je LBB29_8 -; AVX512VLDQ-NEXT: LBB29_7: ## %cond.load7 +; AVX512VLDQ-NEXT: je LBB29_4 +; AVX512VLDQ-NEXT: LBB29_20: ## %cond.load7 ; AVX512VLDQ-NEXT: vpinsrw $3, 6(%rdi), %xmm1, %xmm0 ; AVX512VLDQ-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512VLDQ-NEXT: testb $16, %al -; AVX512VLDQ-NEXT: je LBB29_10 -; AVX512VLDQ-NEXT: LBB29_9: ## %cond.load10 +; AVX512VLDQ-NEXT: je LBB29_5 +; AVX512VLDQ-NEXT: LBB29_21: ## %cond.load10 ; AVX512VLDQ-NEXT: vpinsrw $4, 8(%rdi), %xmm1, %xmm0 ; AVX512VLDQ-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512VLDQ-NEXT: testb $32, %al -; AVX512VLDQ-NEXT: je LBB29_12 -; AVX512VLDQ-NEXT: LBB29_11: ## %cond.load13 +; AVX512VLDQ-NEXT: je LBB29_6 +; AVX512VLDQ-NEXT: LBB29_22: ## %cond.load13 ; AVX512VLDQ-NEXT: vpinsrw $5, 10(%rdi), %xmm1, %xmm0 ; AVX512VLDQ-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512VLDQ-NEXT: testb $64, %al -; AVX512VLDQ-NEXT: je LBB29_14 -; AVX512VLDQ-NEXT: LBB29_13: ## %cond.load16 +; AVX512VLDQ-NEXT: je LBB29_7 +; AVX512VLDQ-NEXT: LBB29_23: ## %cond.load16 ; AVX512VLDQ-NEXT: vpinsrw $6, 12(%rdi), %xmm1, %xmm0 ; AVX512VLDQ-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512VLDQ-NEXT: testb %al, %al -; AVX512VLDQ-NEXT: jns LBB29_16 -; AVX512VLDQ-NEXT: LBB29_15: ## %cond.load19 +; AVX512VLDQ-NEXT: jns LBB29_8 +; AVX512VLDQ-NEXT: LBB29_24: ## %cond.load19 ; AVX512VLDQ-NEXT: vpinsrw $7, 14(%rdi), %xmm1, %xmm0 ; AVX512VLDQ-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512VLDQ-NEXT: testl $256, %eax ## imm = 0x100 -; AVX512VLDQ-NEXT: je LBB29_18 -; AVX512VLDQ-NEXT: LBB29_17: ## %cond.load22 +; AVX512VLDQ-NEXT: je LBB29_9 +; AVX512VLDQ-NEXT: LBB29_25: ## %cond.load22 ; AVX512VLDQ-NEXT: vpbroadcastw 16(%rdi), %ymm0 ; AVX512VLDQ-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3,4,5,6,7],ymm0[8],ymm1[9,10,11,12,13,14,15] ; AVX512VLDQ-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm0[4,5,6,7] ; AVX512VLDQ-NEXT: testl $512, %eax ## imm = 0x200 -; AVX512VLDQ-NEXT: je LBB29_20 -; AVX512VLDQ-NEXT: LBB29_19: ## %cond.load25 +; AVX512VLDQ-NEXT: je LBB29_10 +; AVX512VLDQ-NEXT: LBB29_26: ## %cond.load25 ; AVX512VLDQ-NEXT: vpbroadcastw 18(%rdi), %ymm0 ; AVX512VLDQ-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2,3,4,5,6,7,8],ymm0[9],ymm1[10,11,12,13,14,15] ; AVX512VLDQ-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm0[4,5,6,7] ; AVX512VLDQ-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX512VLDQ-NEXT: je LBB29_22 -; AVX512VLDQ-NEXT: LBB29_21: ## %cond.load28 +; AVX512VLDQ-NEXT: je LBB29_11 +; AVX512VLDQ-NEXT: LBB29_27: ## %cond.load28 ; AVX512VLDQ-NEXT: vpbroadcastw 20(%rdi), %ymm0 ; AVX512VLDQ-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1],ymm0[2],ymm1[3,4,5,6,7,8,9],ymm0[10],ymm1[11,12,13,14,15] ; AVX512VLDQ-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm0[4,5,6,7] ; AVX512VLDQ-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX512VLDQ-NEXT: je LBB29_24 -; AVX512VLDQ-NEXT: LBB29_23: ## %cond.load31 +; AVX512VLDQ-NEXT: je LBB29_12 +; AVX512VLDQ-NEXT: LBB29_28: ## %cond.load31 ; AVX512VLDQ-NEXT: vpbroadcastw 22(%rdi), %ymm0 ; AVX512VLDQ-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3],ymm1[4,5,6,7,8,9,10],ymm0[11],ymm1[12,13,14,15] ; AVX512VLDQ-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm0[4,5,6,7] ; AVX512VLDQ-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX512VLDQ-NEXT: je LBB29_26 -; AVX512VLDQ-NEXT: LBB29_25: ## %cond.load34 +; AVX512VLDQ-NEXT: je LBB29_13 +; AVX512VLDQ-NEXT: LBB29_29: ## %cond.load34 ; AVX512VLDQ-NEXT: vpbroadcastw 24(%rdi), %ymm0 ; AVX512VLDQ-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4],ymm1[5,6,7,8,9,10,11],ymm0[12],ymm1[13,14,15] ; AVX512VLDQ-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm0[4,5,6,7] ; AVX512VLDQ-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX512VLDQ-NEXT: je LBB29_28 -; AVX512VLDQ-NEXT: LBB29_27: ## %cond.load37 +; AVX512VLDQ-NEXT: je LBB29_14 +; AVX512VLDQ-NEXT: LBB29_30: ## %cond.load37 ; AVX512VLDQ-NEXT: vpbroadcastw 26(%rdi), %ymm0 ; AVX512VLDQ-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1,2,3,4],ymm0[5],ymm1[6,7,8,9,10,11,12],ymm0[13],ymm1[14,15] ; AVX512VLDQ-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm0[4,5,6,7] ; AVX512VLDQ-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX512VLDQ-NEXT: je LBB29_30 -; AVX512VLDQ-NEXT: LBB29_29: ## %cond.load40 +; AVX512VLDQ-NEXT: je LBB29_15 +; AVX512VLDQ-NEXT: LBB29_31: ## %cond.load40 ; AVX512VLDQ-NEXT: vpbroadcastw 28(%rdi), %ymm0 ; AVX512VLDQ-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1,2,3,4,5],ymm0[6],ymm1[7,8,9,10,11,12,13],ymm0[14],ymm1[15] ; AVX512VLDQ-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm0[4,5,6,7] ; AVX512VLDQ-NEXT: testl $32768, %eax ## imm = 0x8000 -; AVX512VLDQ-NEXT: je LBB29_32 -; AVX512VLDQ-NEXT: LBB29_31: ## %cond.load43 +; AVX512VLDQ-NEXT: je LBB29_16 +; AVX512VLDQ-NEXT: LBB29_32: ## %cond.load43 ; AVX512VLDQ-NEXT: vpbroadcastw 30(%rdi), %ymm0 ; AVX512VLDQ-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1,2,3,4,5,6],ymm0[7],ymm1[8,9,10,11,12,13,14],ymm0[15] ; AVX512VLDQ-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm0[4,5,6,7] @@ -4613,56 +4613,56 @@ define <16 x i8> @load_v16i8_v16i8(<16 x i8> %trigger, ptr %addr, <16 x i8> %dst ; SSE2: ## %bb.0: ; SSE2-NEXT: pmovmskb %xmm0, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB30_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB30_17 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB30_3 -; SSE2-NEXT: LBB30_4: ## %else2 +; SSE2-NEXT: jne LBB30_18 +; SSE2-NEXT: LBB30_2: ## %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB30_5 -; SSE2-NEXT: LBB30_6: ## %else5 +; SSE2-NEXT: jne LBB30_19 +; SSE2-NEXT: LBB30_3: ## %else5 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne LBB30_7 -; SSE2-NEXT: LBB30_8: ## %else8 +; SSE2-NEXT: jne LBB30_20 +; SSE2-NEXT: LBB30_4: ## %else8 ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: jne LBB30_9 -; SSE2-NEXT: LBB30_10: ## %else11 +; SSE2-NEXT: jne LBB30_21 +; SSE2-NEXT: LBB30_5: ## %else11 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: jne LBB30_11 -; SSE2-NEXT: LBB30_12: ## %else14 +; SSE2-NEXT: jne LBB30_22 +; SSE2-NEXT: LBB30_6: ## %else14 ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: jne LBB30_13 -; SSE2-NEXT: LBB30_14: ## %else17 +; SSE2-NEXT: jne LBB30_23 +; SSE2-NEXT: LBB30_7: ## %else17 ; SSE2-NEXT: testb %al, %al -; SSE2-NEXT: js LBB30_15 -; SSE2-NEXT: LBB30_16: ## %else20 +; SSE2-NEXT: js LBB30_24 +; SSE2-NEXT: LBB30_8: ## %else20 ; SSE2-NEXT: testl $256, %eax ## imm = 0x100 -; SSE2-NEXT: jne LBB30_17 -; SSE2-NEXT: LBB30_18: ## %else23 +; SSE2-NEXT: jne LBB30_25 +; SSE2-NEXT: LBB30_9: ## %else23 ; SSE2-NEXT: testl $512, %eax ## imm = 0x200 -; SSE2-NEXT: jne LBB30_19 -; SSE2-NEXT: LBB30_20: ## %else26 +; SSE2-NEXT: jne LBB30_26 +; SSE2-NEXT: LBB30_10: ## %else26 ; SSE2-NEXT: testl $1024, %eax ## imm = 0x400 -; SSE2-NEXT: jne LBB30_21 -; SSE2-NEXT: LBB30_22: ## %else29 +; SSE2-NEXT: jne LBB30_27 +; SSE2-NEXT: LBB30_11: ## %else29 ; SSE2-NEXT: testl $2048, %eax ## imm = 0x800 -; SSE2-NEXT: jne LBB30_23 -; SSE2-NEXT: LBB30_24: ## %else32 +; SSE2-NEXT: jne LBB30_28 +; SSE2-NEXT: LBB30_12: ## %else32 ; SSE2-NEXT: testl $4096, %eax ## imm = 0x1000 -; SSE2-NEXT: jne LBB30_25 -; SSE2-NEXT: LBB30_26: ## %else35 +; SSE2-NEXT: jne LBB30_29 +; SSE2-NEXT: LBB30_13: ## %else35 ; SSE2-NEXT: testl $8192, %eax ## imm = 0x2000 -; SSE2-NEXT: jne LBB30_27 -; SSE2-NEXT: LBB30_28: ## %else38 +; SSE2-NEXT: jne LBB30_30 +; SSE2-NEXT: LBB30_14: ## %else38 ; SSE2-NEXT: testl $16384, %eax ## imm = 0x4000 -; SSE2-NEXT: jne LBB30_29 -; SSE2-NEXT: LBB30_30: ## %else41 -; SSE2-NEXT: testl $32768, %eax ## imm = 0x8000 ; SSE2-NEXT: jne LBB30_31 -; SSE2-NEXT: LBB30_32: ## %else44 +; SSE2-NEXT: LBB30_15: ## %else41 +; SSE2-NEXT: testl $32768, %eax ## imm = 0x8000 +; SSE2-NEXT: jne LBB30_32 +; SSE2-NEXT: LBB30_16: ## %else44 ; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB30_1: ## %cond.load +; SSE2-NEXT: LBB30_17: ## %cond.load ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm1 ; SSE2-NEXT: movzbl (%rdi), %ecx @@ -4670,8 +4670,8 @@ define <16 x i8> @load_v16i8_v16i8(<16 x i8> %trigger, ptr %addr, <16 x i8> %dst ; SSE2-NEXT: pandn %xmm2, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB30_4 -; SSE2-NEXT: LBB30_3: ## %cond.load1 +; SSE2-NEXT: je LBB30_2 +; SSE2-NEXT: LBB30_18: ## %cond.load1 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm1 ; SSE2-NEXT: movzbl 1(%rdi), %ecx @@ -4680,8 +4680,8 @@ define <16 x i8> @load_v16i8_v16i8(<16 x i8> %trigger, ptr %addr, <16 x i8> %dst ; SSE2-NEXT: pandn %xmm2, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB30_6 -; SSE2-NEXT: LBB30_5: ## %cond.load4 +; SSE2-NEXT: je LBB30_3 +; SSE2-NEXT: LBB30_19: ## %cond.load4 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm1 ; SSE2-NEXT: movzbl 2(%rdi), %ecx @@ -4690,8 +4690,8 @@ define <16 x i8> @load_v16i8_v16i8(<16 x i8> %trigger, ptr %addr, <16 x i8> %dst ; SSE2-NEXT: pandn %xmm2, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB30_8 -; SSE2-NEXT: LBB30_7: ## %cond.load7 +; SSE2-NEXT: je LBB30_4 +; SSE2-NEXT: LBB30_20: ## %cond.load7 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm1 ; SSE2-NEXT: movzbl 3(%rdi), %ecx @@ -4700,8 +4700,8 @@ define <16 x i8> @load_v16i8_v16i8(<16 x i8> %trigger, ptr %addr, <16 x i8> %dst ; SSE2-NEXT: pandn %xmm2, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: je LBB30_10 -; SSE2-NEXT: LBB30_9: ## %cond.load10 +; SSE2-NEXT: je LBB30_5 +; SSE2-NEXT: LBB30_21: ## %cond.load10 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm1 ; SSE2-NEXT: movzbl 4(%rdi), %ecx @@ -4710,8 +4710,8 @@ define <16 x i8> @load_v16i8_v16i8(<16 x i8> %trigger, ptr %addr, <16 x i8> %dst ; SSE2-NEXT: pandn %xmm2, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je LBB30_12 -; SSE2-NEXT: LBB30_11: ## %cond.load13 +; SSE2-NEXT: je LBB30_6 +; SSE2-NEXT: LBB30_22: ## %cond.load13 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm1 ; SSE2-NEXT: movzbl 5(%rdi), %ecx @@ -4720,8 +4720,8 @@ define <16 x i8> @load_v16i8_v16i8(<16 x i8> %trigger, ptr %addr, <16 x i8> %dst ; SSE2-NEXT: pandn %xmm2, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: je LBB30_14 -; SSE2-NEXT: LBB30_13: ## %cond.load16 +; SSE2-NEXT: je LBB30_7 +; SSE2-NEXT: LBB30_23: ## %cond.load16 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm1 ; SSE2-NEXT: movzbl 6(%rdi), %ecx @@ -4730,8 +4730,8 @@ define <16 x i8> @load_v16i8_v16i8(<16 x i8> %trigger, ptr %addr, <16 x i8> %dst ; SSE2-NEXT: pandn %xmm2, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: testb %al, %al -; SSE2-NEXT: jns LBB30_16 -; SSE2-NEXT: LBB30_15: ## %cond.load19 +; SSE2-NEXT: jns LBB30_8 +; SSE2-NEXT: LBB30_24: ## %cond.load19 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm1 ; SSE2-NEXT: movzbl 7(%rdi), %ecx @@ -4740,8 +4740,8 @@ define <16 x i8> @load_v16i8_v16i8(<16 x i8> %trigger, ptr %addr, <16 x i8> %dst ; SSE2-NEXT: pandn %xmm2, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: testl $256, %eax ## imm = 0x100 -; SSE2-NEXT: je LBB30_18 -; SSE2-NEXT: LBB30_17: ## %cond.load22 +; SSE2-NEXT: je LBB30_9 +; SSE2-NEXT: LBB30_25: ## %cond.load22 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm1 ; SSE2-NEXT: movzbl 8(%rdi), %ecx @@ -4750,8 +4750,8 @@ define <16 x i8> @load_v16i8_v16i8(<16 x i8> %trigger, ptr %addr, <16 x i8> %dst ; SSE2-NEXT: pandn %xmm2, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: testl $512, %eax ## imm = 0x200 -; SSE2-NEXT: je LBB30_20 -; SSE2-NEXT: LBB30_19: ## %cond.load25 +; SSE2-NEXT: je LBB30_10 +; SSE2-NEXT: LBB30_26: ## %cond.load25 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm1 ; SSE2-NEXT: movzbl 9(%rdi), %ecx @@ -4760,8 +4760,8 @@ define <16 x i8> @load_v16i8_v16i8(<16 x i8> %trigger, ptr %addr, <16 x i8> %dst ; SSE2-NEXT: pandn %xmm2, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: testl $1024, %eax ## imm = 0x400 -; SSE2-NEXT: je LBB30_22 -; SSE2-NEXT: LBB30_21: ## %cond.load28 +; SSE2-NEXT: je LBB30_11 +; SSE2-NEXT: LBB30_27: ## %cond.load28 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm1 ; SSE2-NEXT: movzbl 10(%rdi), %ecx @@ -4770,8 +4770,8 @@ define <16 x i8> @load_v16i8_v16i8(<16 x i8> %trigger, ptr %addr, <16 x i8> %dst ; SSE2-NEXT: pandn %xmm2, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: testl $2048, %eax ## imm = 0x800 -; SSE2-NEXT: je LBB30_24 -; SSE2-NEXT: LBB30_23: ## %cond.load31 +; SSE2-NEXT: je LBB30_12 +; SSE2-NEXT: LBB30_28: ## %cond.load31 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm1 ; SSE2-NEXT: movzbl 11(%rdi), %ecx @@ -4780,8 +4780,8 @@ define <16 x i8> @load_v16i8_v16i8(<16 x i8> %trigger, ptr %addr, <16 x i8> %dst ; SSE2-NEXT: pandn %xmm2, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: testl $4096, %eax ## imm = 0x1000 -; SSE2-NEXT: je LBB30_26 -; SSE2-NEXT: LBB30_25: ## %cond.load34 +; SSE2-NEXT: je LBB30_13 +; SSE2-NEXT: LBB30_29: ## %cond.load34 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm1 ; SSE2-NEXT: movzbl 12(%rdi), %ecx @@ -4790,8 +4790,8 @@ define <16 x i8> @load_v16i8_v16i8(<16 x i8> %trigger, ptr %addr, <16 x i8> %dst ; SSE2-NEXT: pandn %xmm2, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: testl $8192, %eax ## imm = 0x2000 -; SSE2-NEXT: je LBB30_28 -; SSE2-NEXT: LBB30_27: ## %cond.load37 +; SSE2-NEXT: je LBB30_14 +; SSE2-NEXT: LBB30_30: ## %cond.load37 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255] ; SSE2-NEXT: pand %xmm0, %xmm1 ; SSE2-NEXT: movzbl 13(%rdi), %ecx @@ -4800,8 +4800,8 @@ define <16 x i8> @load_v16i8_v16i8(<16 x i8> %trigger, ptr %addr, <16 x i8> %dst ; SSE2-NEXT: pandn %xmm2, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: testl $16384, %eax ## imm = 0x4000 -; SSE2-NEXT: je LBB30_30 -; SSE2-NEXT: LBB30_29: ## %cond.load40 +; SSE2-NEXT: je LBB30_15 +; SSE2-NEXT: LBB30_31: ## %cond.load40 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255] ; SSE2-NEXT: pand %xmm0, %xmm1 ; SSE2-NEXT: movzbl 14(%rdi), %ecx @@ -4810,8 +4810,8 @@ define <16 x i8> @load_v16i8_v16i8(<16 x i8> %trigger, ptr %addr, <16 x i8> %dst ; SSE2-NEXT: pandn %xmm2, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm1 ; SSE2-NEXT: testl $32768, %eax ## imm = 0x8000 -; SSE2-NEXT: je LBB30_32 -; SSE2-NEXT: LBB30_31: ## %cond.load43 +; SSE2-NEXT: je LBB30_16 +; SSE2-NEXT: LBB30_32: ## %cond.load43 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 ; SSE2-NEXT: movzbl 15(%rdi), %eax ; SSE2-NEXT: movd %eax, %xmm0 @@ -4824,116 +4824,116 @@ define <16 x i8> @load_v16i8_v16i8(<16 x i8> %trigger, ptr %addr, <16 x i8> %dst ; SSE42: ## %bb.0: ; SSE42-NEXT: pmovmskb %xmm0, %eax ; SSE42-NEXT: testb $1, %al -; SSE42-NEXT: jne LBB30_1 -; SSE42-NEXT: ## %bb.2: ## %else +; SSE42-NEXT: jne LBB30_17 +; SSE42-NEXT: ## %bb.1: ## %else ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: jne LBB30_3 -; SSE42-NEXT: LBB30_4: ## %else2 +; SSE42-NEXT: jne LBB30_18 +; SSE42-NEXT: LBB30_2: ## %else2 ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: jne LBB30_5 -; SSE42-NEXT: LBB30_6: ## %else5 +; SSE42-NEXT: jne LBB30_19 +; SSE42-NEXT: LBB30_3: ## %else5 ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: jne LBB30_7 -; SSE42-NEXT: LBB30_8: ## %else8 +; SSE42-NEXT: jne LBB30_20 +; SSE42-NEXT: LBB30_4: ## %else8 ; SSE42-NEXT: testb $16, %al -; SSE42-NEXT: jne LBB30_9 -; SSE42-NEXT: LBB30_10: ## %else11 +; SSE42-NEXT: jne LBB30_21 +; SSE42-NEXT: LBB30_5: ## %else11 ; SSE42-NEXT: testb $32, %al -; SSE42-NEXT: jne LBB30_11 -; SSE42-NEXT: LBB30_12: ## %else14 +; SSE42-NEXT: jne LBB30_22 +; SSE42-NEXT: LBB30_6: ## %else14 ; SSE42-NEXT: testb $64, %al -; SSE42-NEXT: jne LBB30_13 -; SSE42-NEXT: LBB30_14: ## %else17 +; SSE42-NEXT: jne LBB30_23 +; SSE42-NEXT: LBB30_7: ## %else17 ; SSE42-NEXT: testb %al, %al -; SSE42-NEXT: js LBB30_15 -; SSE42-NEXT: LBB30_16: ## %else20 +; SSE42-NEXT: js LBB30_24 +; SSE42-NEXT: LBB30_8: ## %else20 ; SSE42-NEXT: testl $256, %eax ## imm = 0x100 -; SSE42-NEXT: jne LBB30_17 -; SSE42-NEXT: LBB30_18: ## %else23 +; SSE42-NEXT: jne LBB30_25 +; SSE42-NEXT: LBB30_9: ## %else23 ; SSE42-NEXT: testl $512, %eax ## imm = 0x200 -; SSE42-NEXT: jne LBB30_19 -; SSE42-NEXT: LBB30_20: ## %else26 +; SSE42-NEXT: jne LBB30_26 +; SSE42-NEXT: LBB30_10: ## %else26 ; SSE42-NEXT: testl $1024, %eax ## imm = 0x400 -; SSE42-NEXT: jne LBB30_21 -; SSE42-NEXT: LBB30_22: ## %else29 +; SSE42-NEXT: jne LBB30_27 +; SSE42-NEXT: LBB30_11: ## %else29 ; SSE42-NEXT: testl $2048, %eax ## imm = 0x800 -; SSE42-NEXT: jne LBB30_23 -; SSE42-NEXT: LBB30_24: ## %else32 +; SSE42-NEXT: jne LBB30_28 +; SSE42-NEXT: LBB30_12: ## %else32 ; SSE42-NEXT: testl $4096, %eax ## imm = 0x1000 -; SSE42-NEXT: jne LBB30_25 -; SSE42-NEXT: LBB30_26: ## %else35 +; SSE42-NEXT: jne LBB30_29 +; SSE42-NEXT: LBB30_13: ## %else35 ; SSE42-NEXT: testl $8192, %eax ## imm = 0x2000 -; SSE42-NEXT: jne LBB30_27 -; SSE42-NEXT: LBB30_28: ## %else38 +; SSE42-NEXT: jne LBB30_30 +; SSE42-NEXT: LBB30_14: ## %else38 ; SSE42-NEXT: testl $16384, %eax ## imm = 0x4000 -; SSE42-NEXT: jne LBB30_29 -; SSE42-NEXT: LBB30_30: ## %else41 -; SSE42-NEXT: testl $32768, %eax ## imm = 0x8000 ; SSE42-NEXT: jne LBB30_31 -; SSE42-NEXT: LBB30_32: ## %else44 +; SSE42-NEXT: LBB30_15: ## %else41 +; SSE42-NEXT: testl $32768, %eax ## imm = 0x8000 +; SSE42-NEXT: jne LBB30_32 +; SSE42-NEXT: LBB30_16: ## %else44 ; SSE42-NEXT: movdqa %xmm1, %xmm0 ; SSE42-NEXT: retq -; SSE42-NEXT: LBB30_1: ## %cond.load +; SSE42-NEXT: LBB30_17: ## %cond.load ; SSE42-NEXT: pinsrb $0, (%rdi), %xmm1 ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: je LBB30_4 -; SSE42-NEXT: LBB30_3: ## %cond.load1 +; SSE42-NEXT: je LBB30_2 +; SSE42-NEXT: LBB30_18: ## %cond.load1 ; SSE42-NEXT: pinsrb $1, 1(%rdi), %xmm1 ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: je LBB30_6 -; SSE42-NEXT: LBB30_5: ## %cond.load4 +; SSE42-NEXT: je LBB30_3 +; SSE42-NEXT: LBB30_19: ## %cond.load4 ; SSE42-NEXT: pinsrb $2, 2(%rdi), %xmm1 ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: je LBB30_8 -; SSE42-NEXT: LBB30_7: ## %cond.load7 +; SSE42-NEXT: je LBB30_4 +; SSE42-NEXT: LBB30_20: ## %cond.load7 ; SSE42-NEXT: pinsrb $3, 3(%rdi), %xmm1 ; SSE42-NEXT: testb $16, %al -; SSE42-NEXT: je LBB30_10 -; SSE42-NEXT: LBB30_9: ## %cond.load10 +; SSE42-NEXT: je LBB30_5 +; SSE42-NEXT: LBB30_21: ## %cond.load10 ; SSE42-NEXT: pinsrb $4, 4(%rdi), %xmm1 ; SSE42-NEXT: testb $32, %al -; SSE42-NEXT: je LBB30_12 -; SSE42-NEXT: LBB30_11: ## %cond.load13 +; SSE42-NEXT: je LBB30_6 +; SSE42-NEXT: LBB30_22: ## %cond.load13 ; SSE42-NEXT: pinsrb $5, 5(%rdi), %xmm1 ; SSE42-NEXT: testb $64, %al -; SSE42-NEXT: je LBB30_14 -; SSE42-NEXT: LBB30_13: ## %cond.load16 +; SSE42-NEXT: je LBB30_7 +; SSE42-NEXT: LBB30_23: ## %cond.load16 ; SSE42-NEXT: pinsrb $6, 6(%rdi), %xmm1 ; SSE42-NEXT: testb %al, %al -; SSE42-NEXT: jns LBB30_16 -; SSE42-NEXT: LBB30_15: ## %cond.load19 +; SSE42-NEXT: jns LBB30_8 +; SSE42-NEXT: LBB30_24: ## %cond.load19 ; SSE42-NEXT: pinsrb $7, 7(%rdi), %xmm1 ; SSE42-NEXT: testl $256, %eax ## imm = 0x100 -; SSE42-NEXT: je LBB30_18 -; SSE42-NEXT: LBB30_17: ## %cond.load22 +; SSE42-NEXT: je LBB30_9 +; SSE42-NEXT: LBB30_25: ## %cond.load22 ; SSE42-NEXT: pinsrb $8, 8(%rdi), %xmm1 ; SSE42-NEXT: testl $512, %eax ## imm = 0x200 -; SSE42-NEXT: je LBB30_20 -; SSE42-NEXT: LBB30_19: ## %cond.load25 +; SSE42-NEXT: je LBB30_10 +; SSE42-NEXT: LBB30_26: ## %cond.load25 ; SSE42-NEXT: pinsrb $9, 9(%rdi), %xmm1 ; SSE42-NEXT: testl $1024, %eax ## imm = 0x400 -; SSE42-NEXT: je LBB30_22 -; SSE42-NEXT: LBB30_21: ## %cond.load28 +; SSE42-NEXT: je LBB30_11 +; SSE42-NEXT: LBB30_27: ## %cond.load28 ; SSE42-NEXT: pinsrb $10, 10(%rdi), %xmm1 ; SSE42-NEXT: testl $2048, %eax ## imm = 0x800 -; SSE42-NEXT: je LBB30_24 -; SSE42-NEXT: LBB30_23: ## %cond.load31 +; SSE42-NEXT: je LBB30_12 +; SSE42-NEXT: LBB30_28: ## %cond.load31 ; SSE42-NEXT: pinsrb $11, 11(%rdi), %xmm1 ; SSE42-NEXT: testl $4096, %eax ## imm = 0x1000 -; SSE42-NEXT: je LBB30_26 -; SSE42-NEXT: LBB30_25: ## %cond.load34 +; SSE42-NEXT: je LBB30_13 +; SSE42-NEXT: LBB30_29: ## %cond.load34 ; SSE42-NEXT: pinsrb $12, 12(%rdi), %xmm1 ; SSE42-NEXT: testl $8192, %eax ## imm = 0x2000 -; SSE42-NEXT: je LBB30_28 -; SSE42-NEXT: LBB30_27: ## %cond.load37 +; SSE42-NEXT: je LBB30_14 +; SSE42-NEXT: LBB30_30: ## %cond.load37 ; SSE42-NEXT: pinsrb $13, 13(%rdi), %xmm1 ; SSE42-NEXT: testl $16384, %eax ## imm = 0x4000 -; SSE42-NEXT: je LBB30_30 -; SSE42-NEXT: LBB30_29: ## %cond.load40 +; SSE42-NEXT: je LBB30_15 +; SSE42-NEXT: LBB30_31: ## %cond.load40 ; SSE42-NEXT: pinsrb $14, 14(%rdi), %xmm1 ; SSE42-NEXT: testl $32768, %eax ## imm = 0x8000 -; SSE42-NEXT: je LBB30_32 -; SSE42-NEXT: LBB30_31: ## %cond.load43 +; SSE42-NEXT: je LBB30_16 +; SSE42-NEXT: LBB30_32: ## %cond.load43 ; SSE42-NEXT: pinsrb $15, 15(%rdi), %xmm1 ; SSE42-NEXT: movdqa %xmm1, %xmm0 ; SSE42-NEXT: retq @@ -4942,116 +4942,116 @@ define <16 x i8> @load_v16i8_v16i8(<16 x i8> %trigger, ptr %addr, <16 x i8> %dst ; AVX1OR2: ## %bb.0: ; AVX1OR2-NEXT: vpmovmskb %xmm0, %eax ; AVX1OR2-NEXT: testb $1, %al -; AVX1OR2-NEXT: jne LBB30_1 -; AVX1OR2-NEXT: ## %bb.2: ## %else +; AVX1OR2-NEXT: jne LBB30_17 +; AVX1OR2-NEXT: ## %bb.1: ## %else ; AVX1OR2-NEXT: testb $2, %al -; AVX1OR2-NEXT: jne LBB30_3 -; AVX1OR2-NEXT: LBB30_4: ## %else2 +; AVX1OR2-NEXT: jne LBB30_18 +; AVX1OR2-NEXT: LBB30_2: ## %else2 ; AVX1OR2-NEXT: testb $4, %al -; AVX1OR2-NEXT: jne LBB30_5 -; AVX1OR2-NEXT: LBB30_6: ## %else5 +; AVX1OR2-NEXT: jne LBB30_19 +; AVX1OR2-NEXT: LBB30_3: ## %else5 ; AVX1OR2-NEXT: testb $8, %al -; AVX1OR2-NEXT: jne LBB30_7 -; AVX1OR2-NEXT: LBB30_8: ## %else8 +; AVX1OR2-NEXT: jne LBB30_20 +; AVX1OR2-NEXT: LBB30_4: ## %else8 ; AVX1OR2-NEXT: testb $16, %al -; AVX1OR2-NEXT: jne LBB30_9 -; AVX1OR2-NEXT: LBB30_10: ## %else11 +; AVX1OR2-NEXT: jne LBB30_21 +; AVX1OR2-NEXT: LBB30_5: ## %else11 ; AVX1OR2-NEXT: testb $32, %al -; AVX1OR2-NEXT: jne LBB30_11 -; AVX1OR2-NEXT: LBB30_12: ## %else14 +; AVX1OR2-NEXT: jne LBB30_22 +; AVX1OR2-NEXT: LBB30_6: ## %else14 ; AVX1OR2-NEXT: testb $64, %al -; AVX1OR2-NEXT: jne LBB30_13 -; AVX1OR2-NEXT: LBB30_14: ## %else17 +; AVX1OR2-NEXT: jne LBB30_23 +; AVX1OR2-NEXT: LBB30_7: ## %else17 ; AVX1OR2-NEXT: testb %al, %al -; AVX1OR2-NEXT: js LBB30_15 -; AVX1OR2-NEXT: LBB30_16: ## %else20 +; AVX1OR2-NEXT: js LBB30_24 +; AVX1OR2-NEXT: LBB30_8: ## %else20 ; AVX1OR2-NEXT: testl $256, %eax ## imm = 0x100 -; AVX1OR2-NEXT: jne LBB30_17 -; AVX1OR2-NEXT: LBB30_18: ## %else23 +; AVX1OR2-NEXT: jne LBB30_25 +; AVX1OR2-NEXT: LBB30_9: ## %else23 ; AVX1OR2-NEXT: testl $512, %eax ## imm = 0x200 -; AVX1OR2-NEXT: jne LBB30_19 -; AVX1OR2-NEXT: LBB30_20: ## %else26 +; AVX1OR2-NEXT: jne LBB30_26 +; AVX1OR2-NEXT: LBB30_10: ## %else26 ; AVX1OR2-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX1OR2-NEXT: jne LBB30_21 -; AVX1OR2-NEXT: LBB30_22: ## %else29 +; AVX1OR2-NEXT: jne LBB30_27 +; AVX1OR2-NEXT: LBB30_11: ## %else29 ; AVX1OR2-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX1OR2-NEXT: jne LBB30_23 -; AVX1OR2-NEXT: LBB30_24: ## %else32 +; AVX1OR2-NEXT: jne LBB30_28 +; AVX1OR2-NEXT: LBB30_12: ## %else32 ; AVX1OR2-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX1OR2-NEXT: jne LBB30_25 -; AVX1OR2-NEXT: LBB30_26: ## %else35 +; AVX1OR2-NEXT: jne LBB30_29 +; AVX1OR2-NEXT: LBB30_13: ## %else35 ; AVX1OR2-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX1OR2-NEXT: jne LBB30_27 -; AVX1OR2-NEXT: LBB30_28: ## %else38 +; AVX1OR2-NEXT: jne LBB30_30 +; AVX1OR2-NEXT: LBB30_14: ## %else38 ; AVX1OR2-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX1OR2-NEXT: jne LBB30_29 -; AVX1OR2-NEXT: LBB30_30: ## %else41 -; AVX1OR2-NEXT: testl $32768, %eax ## imm = 0x8000 ; AVX1OR2-NEXT: jne LBB30_31 -; AVX1OR2-NEXT: LBB30_32: ## %else44 +; AVX1OR2-NEXT: LBB30_15: ## %else41 +; AVX1OR2-NEXT: testl $32768, %eax ## imm = 0x8000 +; AVX1OR2-NEXT: jne LBB30_32 +; AVX1OR2-NEXT: LBB30_16: ## %else44 ; AVX1OR2-NEXT: vmovdqa %xmm1, %xmm0 ; AVX1OR2-NEXT: retq -; AVX1OR2-NEXT: LBB30_1: ## %cond.load +; AVX1OR2-NEXT: LBB30_17: ## %cond.load ; AVX1OR2-NEXT: vpinsrb $0, (%rdi), %xmm1, %xmm1 ; AVX1OR2-NEXT: testb $2, %al -; AVX1OR2-NEXT: je LBB30_4 -; AVX1OR2-NEXT: LBB30_3: ## %cond.load1 +; AVX1OR2-NEXT: je LBB30_2 +; AVX1OR2-NEXT: LBB30_18: ## %cond.load1 ; AVX1OR2-NEXT: vpinsrb $1, 1(%rdi), %xmm1, %xmm1 ; AVX1OR2-NEXT: testb $4, %al -; AVX1OR2-NEXT: je LBB30_6 -; AVX1OR2-NEXT: LBB30_5: ## %cond.load4 +; AVX1OR2-NEXT: je LBB30_3 +; AVX1OR2-NEXT: LBB30_19: ## %cond.load4 ; AVX1OR2-NEXT: vpinsrb $2, 2(%rdi), %xmm1, %xmm1 ; AVX1OR2-NEXT: testb $8, %al -; AVX1OR2-NEXT: je LBB30_8 -; AVX1OR2-NEXT: LBB30_7: ## %cond.load7 +; AVX1OR2-NEXT: je LBB30_4 +; AVX1OR2-NEXT: LBB30_20: ## %cond.load7 ; AVX1OR2-NEXT: vpinsrb $3, 3(%rdi), %xmm1, %xmm1 ; AVX1OR2-NEXT: testb $16, %al -; AVX1OR2-NEXT: je LBB30_10 -; AVX1OR2-NEXT: LBB30_9: ## %cond.load10 +; AVX1OR2-NEXT: je LBB30_5 +; AVX1OR2-NEXT: LBB30_21: ## %cond.load10 ; AVX1OR2-NEXT: vpinsrb $4, 4(%rdi), %xmm1, %xmm1 ; AVX1OR2-NEXT: testb $32, %al -; AVX1OR2-NEXT: je LBB30_12 -; AVX1OR2-NEXT: LBB30_11: ## %cond.load13 +; AVX1OR2-NEXT: je LBB30_6 +; AVX1OR2-NEXT: LBB30_22: ## %cond.load13 ; AVX1OR2-NEXT: vpinsrb $5, 5(%rdi), %xmm1, %xmm1 ; AVX1OR2-NEXT: testb $64, %al -; AVX1OR2-NEXT: je LBB30_14 -; AVX1OR2-NEXT: LBB30_13: ## %cond.load16 +; AVX1OR2-NEXT: je LBB30_7 +; AVX1OR2-NEXT: LBB30_23: ## %cond.load16 ; AVX1OR2-NEXT: vpinsrb $6, 6(%rdi), %xmm1, %xmm1 ; AVX1OR2-NEXT: testb %al, %al -; AVX1OR2-NEXT: jns LBB30_16 -; AVX1OR2-NEXT: LBB30_15: ## %cond.load19 +; AVX1OR2-NEXT: jns LBB30_8 +; AVX1OR2-NEXT: LBB30_24: ## %cond.load19 ; AVX1OR2-NEXT: vpinsrb $7, 7(%rdi), %xmm1, %xmm1 ; AVX1OR2-NEXT: testl $256, %eax ## imm = 0x100 -; AVX1OR2-NEXT: je LBB30_18 -; AVX1OR2-NEXT: LBB30_17: ## %cond.load22 +; AVX1OR2-NEXT: je LBB30_9 +; AVX1OR2-NEXT: LBB30_25: ## %cond.load22 ; AVX1OR2-NEXT: vpinsrb $8, 8(%rdi), %xmm1, %xmm1 ; AVX1OR2-NEXT: testl $512, %eax ## imm = 0x200 -; AVX1OR2-NEXT: je LBB30_20 -; AVX1OR2-NEXT: LBB30_19: ## %cond.load25 +; AVX1OR2-NEXT: je LBB30_10 +; AVX1OR2-NEXT: LBB30_26: ## %cond.load25 ; AVX1OR2-NEXT: vpinsrb $9, 9(%rdi), %xmm1, %xmm1 ; AVX1OR2-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX1OR2-NEXT: je LBB30_22 -; AVX1OR2-NEXT: LBB30_21: ## %cond.load28 +; AVX1OR2-NEXT: je LBB30_11 +; AVX1OR2-NEXT: LBB30_27: ## %cond.load28 ; AVX1OR2-NEXT: vpinsrb $10, 10(%rdi), %xmm1, %xmm1 ; AVX1OR2-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX1OR2-NEXT: je LBB30_24 -; AVX1OR2-NEXT: LBB30_23: ## %cond.load31 +; AVX1OR2-NEXT: je LBB30_12 +; AVX1OR2-NEXT: LBB30_28: ## %cond.load31 ; AVX1OR2-NEXT: vpinsrb $11, 11(%rdi), %xmm1, %xmm1 ; AVX1OR2-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX1OR2-NEXT: je LBB30_26 -; AVX1OR2-NEXT: LBB30_25: ## %cond.load34 +; AVX1OR2-NEXT: je LBB30_13 +; AVX1OR2-NEXT: LBB30_29: ## %cond.load34 ; AVX1OR2-NEXT: vpinsrb $12, 12(%rdi), %xmm1, %xmm1 ; AVX1OR2-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX1OR2-NEXT: je LBB30_28 -; AVX1OR2-NEXT: LBB30_27: ## %cond.load37 +; AVX1OR2-NEXT: je LBB30_14 +; AVX1OR2-NEXT: LBB30_30: ## %cond.load37 ; AVX1OR2-NEXT: vpinsrb $13, 13(%rdi), %xmm1, %xmm1 ; AVX1OR2-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX1OR2-NEXT: je LBB30_30 -; AVX1OR2-NEXT: LBB30_29: ## %cond.load40 +; AVX1OR2-NEXT: je LBB30_15 +; AVX1OR2-NEXT: LBB30_31: ## %cond.load40 ; AVX1OR2-NEXT: vpinsrb $14, 14(%rdi), %xmm1, %xmm1 ; AVX1OR2-NEXT: testl $32768, %eax ## imm = 0x8000 -; AVX1OR2-NEXT: je LBB30_32 -; AVX1OR2-NEXT: LBB30_31: ## %cond.load43 +; AVX1OR2-NEXT: je LBB30_16 +; AVX1OR2-NEXT: LBB30_32: ## %cond.load43 ; AVX1OR2-NEXT: vpinsrb $15, 15(%rdi), %xmm1, %xmm1 ; AVX1OR2-NEXT: vmovdqa %xmm1, %xmm0 ; AVX1OR2-NEXT: retq @@ -5060,116 +5060,116 @@ define <16 x i8> @load_v16i8_v16i8(<16 x i8> %trigger, ptr %addr, <16 x i8> %dst ; AVX512F: ## %bb.0: ; AVX512F-NEXT: vpmovmskb %xmm0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne LBB30_1 -; AVX512F-NEXT: ## %bb.2: ## %else +; AVX512F-NEXT: jne LBB30_17 +; AVX512F-NEXT: ## %bb.1: ## %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne LBB30_3 -; AVX512F-NEXT: LBB30_4: ## %else2 +; AVX512F-NEXT: jne LBB30_18 +; AVX512F-NEXT: LBB30_2: ## %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne LBB30_5 -; AVX512F-NEXT: LBB30_6: ## %else5 +; AVX512F-NEXT: jne LBB30_19 +; AVX512F-NEXT: LBB30_3: ## %else5 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne LBB30_7 -; AVX512F-NEXT: LBB30_8: ## %else8 +; AVX512F-NEXT: jne LBB30_20 +; AVX512F-NEXT: LBB30_4: ## %else8 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne LBB30_9 -; AVX512F-NEXT: LBB30_10: ## %else11 +; AVX512F-NEXT: jne LBB30_21 +; AVX512F-NEXT: LBB30_5: ## %else11 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne LBB30_11 -; AVX512F-NEXT: LBB30_12: ## %else14 +; AVX512F-NEXT: jne LBB30_22 +; AVX512F-NEXT: LBB30_6: ## %else14 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne LBB30_13 -; AVX512F-NEXT: LBB30_14: ## %else17 +; AVX512F-NEXT: jne LBB30_23 +; AVX512F-NEXT: LBB30_7: ## %else17 ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: js LBB30_15 -; AVX512F-NEXT: LBB30_16: ## %else20 +; AVX512F-NEXT: js LBB30_24 +; AVX512F-NEXT: LBB30_8: ## %else20 ; AVX512F-NEXT: testl $256, %eax ## imm = 0x100 -; AVX512F-NEXT: jne LBB30_17 -; AVX512F-NEXT: LBB30_18: ## %else23 +; AVX512F-NEXT: jne LBB30_25 +; AVX512F-NEXT: LBB30_9: ## %else23 ; AVX512F-NEXT: testl $512, %eax ## imm = 0x200 -; AVX512F-NEXT: jne LBB30_19 -; AVX512F-NEXT: LBB30_20: ## %else26 +; AVX512F-NEXT: jne LBB30_26 +; AVX512F-NEXT: LBB30_10: ## %else26 ; AVX512F-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX512F-NEXT: jne LBB30_21 -; AVX512F-NEXT: LBB30_22: ## %else29 +; AVX512F-NEXT: jne LBB30_27 +; AVX512F-NEXT: LBB30_11: ## %else29 ; AVX512F-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX512F-NEXT: jne LBB30_23 -; AVX512F-NEXT: LBB30_24: ## %else32 +; AVX512F-NEXT: jne LBB30_28 +; AVX512F-NEXT: LBB30_12: ## %else32 ; AVX512F-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX512F-NEXT: jne LBB30_25 -; AVX512F-NEXT: LBB30_26: ## %else35 +; AVX512F-NEXT: jne LBB30_29 +; AVX512F-NEXT: LBB30_13: ## %else35 ; AVX512F-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX512F-NEXT: jne LBB30_27 -; AVX512F-NEXT: LBB30_28: ## %else38 +; AVX512F-NEXT: jne LBB30_30 +; AVX512F-NEXT: LBB30_14: ## %else38 ; AVX512F-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX512F-NEXT: jne LBB30_29 -; AVX512F-NEXT: LBB30_30: ## %else41 -; AVX512F-NEXT: testl $32768, %eax ## imm = 0x8000 ; AVX512F-NEXT: jne LBB30_31 -; AVX512F-NEXT: LBB30_32: ## %else44 +; AVX512F-NEXT: LBB30_15: ## %else41 +; AVX512F-NEXT: testl $32768, %eax ## imm = 0x8000 +; AVX512F-NEXT: jne LBB30_32 +; AVX512F-NEXT: LBB30_16: ## %else44 ; AVX512F-NEXT: vmovdqa %xmm1, %xmm0 ; AVX512F-NEXT: retq -; AVX512F-NEXT: LBB30_1: ## %cond.load +; AVX512F-NEXT: LBB30_17: ## %cond.load ; AVX512F-NEXT: vpinsrb $0, (%rdi), %xmm1, %xmm1 ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je LBB30_4 -; AVX512F-NEXT: LBB30_3: ## %cond.load1 +; AVX512F-NEXT: je LBB30_2 +; AVX512F-NEXT: LBB30_18: ## %cond.load1 ; AVX512F-NEXT: vpinsrb $1, 1(%rdi), %xmm1, %xmm1 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je LBB30_6 -; AVX512F-NEXT: LBB30_5: ## %cond.load4 +; AVX512F-NEXT: je LBB30_3 +; AVX512F-NEXT: LBB30_19: ## %cond.load4 ; AVX512F-NEXT: vpinsrb $2, 2(%rdi), %xmm1, %xmm1 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je LBB30_8 -; AVX512F-NEXT: LBB30_7: ## %cond.load7 +; AVX512F-NEXT: je LBB30_4 +; AVX512F-NEXT: LBB30_20: ## %cond.load7 ; AVX512F-NEXT: vpinsrb $3, 3(%rdi), %xmm1, %xmm1 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je LBB30_10 -; AVX512F-NEXT: LBB30_9: ## %cond.load10 +; AVX512F-NEXT: je LBB30_5 +; AVX512F-NEXT: LBB30_21: ## %cond.load10 ; AVX512F-NEXT: vpinsrb $4, 4(%rdi), %xmm1, %xmm1 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je LBB30_12 -; AVX512F-NEXT: LBB30_11: ## %cond.load13 +; AVX512F-NEXT: je LBB30_6 +; AVX512F-NEXT: LBB30_22: ## %cond.load13 ; AVX512F-NEXT: vpinsrb $5, 5(%rdi), %xmm1, %xmm1 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je LBB30_14 -; AVX512F-NEXT: LBB30_13: ## %cond.load16 +; AVX512F-NEXT: je LBB30_7 +; AVX512F-NEXT: LBB30_23: ## %cond.load16 ; AVX512F-NEXT: vpinsrb $6, 6(%rdi), %xmm1, %xmm1 ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: jns LBB30_16 -; AVX512F-NEXT: LBB30_15: ## %cond.load19 +; AVX512F-NEXT: jns LBB30_8 +; AVX512F-NEXT: LBB30_24: ## %cond.load19 ; AVX512F-NEXT: vpinsrb $7, 7(%rdi), %xmm1, %xmm1 ; AVX512F-NEXT: testl $256, %eax ## imm = 0x100 -; AVX512F-NEXT: je LBB30_18 -; AVX512F-NEXT: LBB30_17: ## %cond.load22 +; AVX512F-NEXT: je LBB30_9 +; AVX512F-NEXT: LBB30_25: ## %cond.load22 ; AVX512F-NEXT: vpinsrb $8, 8(%rdi), %xmm1, %xmm1 ; AVX512F-NEXT: testl $512, %eax ## imm = 0x200 -; AVX512F-NEXT: je LBB30_20 -; AVX512F-NEXT: LBB30_19: ## %cond.load25 +; AVX512F-NEXT: je LBB30_10 +; AVX512F-NEXT: LBB30_26: ## %cond.load25 ; AVX512F-NEXT: vpinsrb $9, 9(%rdi), %xmm1, %xmm1 ; AVX512F-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX512F-NEXT: je LBB30_22 -; AVX512F-NEXT: LBB30_21: ## %cond.load28 +; AVX512F-NEXT: je LBB30_11 +; AVX512F-NEXT: LBB30_27: ## %cond.load28 ; AVX512F-NEXT: vpinsrb $10, 10(%rdi), %xmm1, %xmm1 ; AVX512F-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX512F-NEXT: je LBB30_24 -; AVX512F-NEXT: LBB30_23: ## %cond.load31 +; AVX512F-NEXT: je LBB30_12 +; AVX512F-NEXT: LBB30_28: ## %cond.load31 ; AVX512F-NEXT: vpinsrb $11, 11(%rdi), %xmm1, %xmm1 ; AVX512F-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX512F-NEXT: je LBB30_26 -; AVX512F-NEXT: LBB30_25: ## %cond.load34 +; AVX512F-NEXT: je LBB30_13 +; AVX512F-NEXT: LBB30_29: ## %cond.load34 ; AVX512F-NEXT: vpinsrb $12, 12(%rdi), %xmm1, %xmm1 ; AVX512F-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX512F-NEXT: je LBB30_28 -; AVX512F-NEXT: LBB30_27: ## %cond.load37 +; AVX512F-NEXT: je LBB30_14 +; AVX512F-NEXT: LBB30_30: ## %cond.load37 ; AVX512F-NEXT: vpinsrb $13, 13(%rdi), %xmm1, %xmm1 ; AVX512F-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX512F-NEXT: je LBB30_30 -; AVX512F-NEXT: LBB30_29: ## %cond.load40 +; AVX512F-NEXT: je LBB30_15 +; AVX512F-NEXT: LBB30_31: ## %cond.load40 ; AVX512F-NEXT: vpinsrb $14, 14(%rdi), %xmm1, %xmm1 ; AVX512F-NEXT: testl $32768, %eax ## imm = 0x8000 -; AVX512F-NEXT: je LBB30_32 -; AVX512F-NEXT: LBB30_31: ## %cond.load43 +; AVX512F-NEXT: je LBB30_16 +; AVX512F-NEXT: LBB30_32: ## %cond.load43 ; AVX512F-NEXT: vpinsrb $15, 15(%rdi), %xmm1, %xmm1 ; AVX512F-NEXT: vmovdqa %xmm1, %xmm0 ; AVX512F-NEXT: retq @@ -5178,116 +5178,116 @@ define <16 x i8> @load_v16i8_v16i8(<16 x i8> %trigger, ptr %addr, <16 x i8> %dst ; AVX512VLDQ: ## %bb.0: ; AVX512VLDQ-NEXT: vpmovmskb %xmm0, %eax ; AVX512VLDQ-NEXT: testb $1, %al -; AVX512VLDQ-NEXT: jne LBB30_1 -; AVX512VLDQ-NEXT: ## %bb.2: ## %else +; AVX512VLDQ-NEXT: jne LBB30_17 +; AVX512VLDQ-NEXT: ## %bb.1: ## %else ; AVX512VLDQ-NEXT: testb $2, %al -; AVX512VLDQ-NEXT: jne LBB30_3 -; AVX512VLDQ-NEXT: LBB30_4: ## %else2 +; AVX512VLDQ-NEXT: jne LBB30_18 +; AVX512VLDQ-NEXT: LBB30_2: ## %else2 ; AVX512VLDQ-NEXT: testb $4, %al -; AVX512VLDQ-NEXT: jne LBB30_5 -; AVX512VLDQ-NEXT: LBB30_6: ## %else5 +; AVX512VLDQ-NEXT: jne LBB30_19 +; AVX512VLDQ-NEXT: LBB30_3: ## %else5 ; AVX512VLDQ-NEXT: testb $8, %al -; AVX512VLDQ-NEXT: jne LBB30_7 -; AVX512VLDQ-NEXT: LBB30_8: ## %else8 +; AVX512VLDQ-NEXT: jne LBB30_20 +; AVX512VLDQ-NEXT: LBB30_4: ## %else8 ; AVX512VLDQ-NEXT: testb $16, %al -; AVX512VLDQ-NEXT: jne LBB30_9 -; AVX512VLDQ-NEXT: LBB30_10: ## %else11 +; AVX512VLDQ-NEXT: jne LBB30_21 +; AVX512VLDQ-NEXT: LBB30_5: ## %else11 ; AVX512VLDQ-NEXT: testb $32, %al -; AVX512VLDQ-NEXT: jne LBB30_11 -; AVX512VLDQ-NEXT: LBB30_12: ## %else14 +; AVX512VLDQ-NEXT: jne LBB30_22 +; AVX512VLDQ-NEXT: LBB30_6: ## %else14 ; AVX512VLDQ-NEXT: testb $64, %al -; AVX512VLDQ-NEXT: jne LBB30_13 -; AVX512VLDQ-NEXT: LBB30_14: ## %else17 +; AVX512VLDQ-NEXT: jne LBB30_23 +; AVX512VLDQ-NEXT: LBB30_7: ## %else17 ; AVX512VLDQ-NEXT: testb %al, %al -; AVX512VLDQ-NEXT: js LBB30_15 -; AVX512VLDQ-NEXT: LBB30_16: ## %else20 +; AVX512VLDQ-NEXT: js LBB30_24 +; AVX512VLDQ-NEXT: LBB30_8: ## %else20 ; AVX512VLDQ-NEXT: testl $256, %eax ## imm = 0x100 -; AVX512VLDQ-NEXT: jne LBB30_17 -; AVX512VLDQ-NEXT: LBB30_18: ## %else23 +; AVX512VLDQ-NEXT: jne LBB30_25 +; AVX512VLDQ-NEXT: LBB30_9: ## %else23 ; AVX512VLDQ-NEXT: testl $512, %eax ## imm = 0x200 -; AVX512VLDQ-NEXT: jne LBB30_19 -; AVX512VLDQ-NEXT: LBB30_20: ## %else26 +; AVX512VLDQ-NEXT: jne LBB30_26 +; AVX512VLDQ-NEXT: LBB30_10: ## %else26 ; AVX512VLDQ-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX512VLDQ-NEXT: jne LBB30_21 -; AVX512VLDQ-NEXT: LBB30_22: ## %else29 +; AVX512VLDQ-NEXT: jne LBB30_27 +; AVX512VLDQ-NEXT: LBB30_11: ## %else29 ; AVX512VLDQ-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX512VLDQ-NEXT: jne LBB30_23 -; AVX512VLDQ-NEXT: LBB30_24: ## %else32 +; AVX512VLDQ-NEXT: jne LBB30_28 +; AVX512VLDQ-NEXT: LBB30_12: ## %else32 ; AVX512VLDQ-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX512VLDQ-NEXT: jne LBB30_25 -; AVX512VLDQ-NEXT: LBB30_26: ## %else35 +; AVX512VLDQ-NEXT: jne LBB30_29 +; AVX512VLDQ-NEXT: LBB30_13: ## %else35 ; AVX512VLDQ-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX512VLDQ-NEXT: jne LBB30_27 -; AVX512VLDQ-NEXT: LBB30_28: ## %else38 +; AVX512VLDQ-NEXT: jne LBB30_30 +; AVX512VLDQ-NEXT: LBB30_14: ## %else38 ; AVX512VLDQ-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX512VLDQ-NEXT: jne LBB30_29 -; AVX512VLDQ-NEXT: LBB30_30: ## %else41 -; AVX512VLDQ-NEXT: testl $32768, %eax ## imm = 0x8000 ; AVX512VLDQ-NEXT: jne LBB30_31 -; AVX512VLDQ-NEXT: LBB30_32: ## %else44 +; AVX512VLDQ-NEXT: LBB30_15: ## %else41 +; AVX512VLDQ-NEXT: testl $32768, %eax ## imm = 0x8000 +; AVX512VLDQ-NEXT: jne LBB30_32 +; AVX512VLDQ-NEXT: LBB30_16: ## %else44 ; AVX512VLDQ-NEXT: vmovdqa %xmm1, %xmm0 ; AVX512VLDQ-NEXT: retq -; AVX512VLDQ-NEXT: LBB30_1: ## %cond.load +; AVX512VLDQ-NEXT: LBB30_17: ## %cond.load ; AVX512VLDQ-NEXT: vpinsrb $0, (%rdi), %xmm1, %xmm1 ; AVX512VLDQ-NEXT: testb $2, %al -; AVX512VLDQ-NEXT: je LBB30_4 -; AVX512VLDQ-NEXT: LBB30_3: ## %cond.load1 +; AVX512VLDQ-NEXT: je LBB30_2 +; AVX512VLDQ-NEXT: LBB30_18: ## %cond.load1 ; AVX512VLDQ-NEXT: vpinsrb $1, 1(%rdi), %xmm1, %xmm1 ; AVX512VLDQ-NEXT: testb $4, %al -; AVX512VLDQ-NEXT: je LBB30_6 -; AVX512VLDQ-NEXT: LBB30_5: ## %cond.load4 +; AVX512VLDQ-NEXT: je LBB30_3 +; AVX512VLDQ-NEXT: LBB30_19: ## %cond.load4 ; AVX512VLDQ-NEXT: vpinsrb $2, 2(%rdi), %xmm1, %xmm1 ; AVX512VLDQ-NEXT: testb $8, %al -; AVX512VLDQ-NEXT: je LBB30_8 -; AVX512VLDQ-NEXT: LBB30_7: ## %cond.load7 +; AVX512VLDQ-NEXT: je LBB30_4 +; AVX512VLDQ-NEXT: LBB30_20: ## %cond.load7 ; AVX512VLDQ-NEXT: vpinsrb $3, 3(%rdi), %xmm1, %xmm1 ; AVX512VLDQ-NEXT: testb $16, %al -; AVX512VLDQ-NEXT: je LBB30_10 -; AVX512VLDQ-NEXT: LBB30_9: ## %cond.load10 +; AVX512VLDQ-NEXT: je LBB30_5 +; AVX512VLDQ-NEXT: LBB30_21: ## %cond.load10 ; AVX512VLDQ-NEXT: vpinsrb $4, 4(%rdi), %xmm1, %xmm1 ; AVX512VLDQ-NEXT: testb $32, %al -; AVX512VLDQ-NEXT: je LBB30_12 -; AVX512VLDQ-NEXT: LBB30_11: ## %cond.load13 +; AVX512VLDQ-NEXT: je LBB30_6 +; AVX512VLDQ-NEXT: LBB30_22: ## %cond.load13 ; AVX512VLDQ-NEXT: vpinsrb $5, 5(%rdi), %xmm1, %xmm1 ; AVX512VLDQ-NEXT: testb $64, %al -; AVX512VLDQ-NEXT: je LBB30_14 -; AVX512VLDQ-NEXT: LBB30_13: ## %cond.load16 +; AVX512VLDQ-NEXT: je LBB30_7 +; AVX512VLDQ-NEXT: LBB30_23: ## %cond.load16 ; AVX512VLDQ-NEXT: vpinsrb $6, 6(%rdi), %xmm1, %xmm1 ; AVX512VLDQ-NEXT: testb %al, %al -; AVX512VLDQ-NEXT: jns LBB30_16 -; AVX512VLDQ-NEXT: LBB30_15: ## %cond.load19 +; AVX512VLDQ-NEXT: jns LBB30_8 +; AVX512VLDQ-NEXT: LBB30_24: ## %cond.load19 ; AVX512VLDQ-NEXT: vpinsrb $7, 7(%rdi), %xmm1, %xmm1 ; AVX512VLDQ-NEXT: testl $256, %eax ## imm = 0x100 -; AVX512VLDQ-NEXT: je LBB30_18 -; AVX512VLDQ-NEXT: LBB30_17: ## %cond.load22 +; AVX512VLDQ-NEXT: je LBB30_9 +; AVX512VLDQ-NEXT: LBB30_25: ## %cond.load22 ; AVX512VLDQ-NEXT: vpinsrb $8, 8(%rdi), %xmm1, %xmm1 ; AVX512VLDQ-NEXT: testl $512, %eax ## imm = 0x200 -; AVX512VLDQ-NEXT: je LBB30_20 -; AVX512VLDQ-NEXT: LBB30_19: ## %cond.load25 +; AVX512VLDQ-NEXT: je LBB30_10 +; AVX512VLDQ-NEXT: LBB30_26: ## %cond.load25 ; AVX512VLDQ-NEXT: vpinsrb $9, 9(%rdi), %xmm1, %xmm1 ; AVX512VLDQ-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX512VLDQ-NEXT: je LBB30_22 -; AVX512VLDQ-NEXT: LBB30_21: ## %cond.load28 +; AVX512VLDQ-NEXT: je LBB30_11 +; AVX512VLDQ-NEXT: LBB30_27: ## %cond.load28 ; AVX512VLDQ-NEXT: vpinsrb $10, 10(%rdi), %xmm1, %xmm1 ; AVX512VLDQ-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX512VLDQ-NEXT: je LBB30_24 -; AVX512VLDQ-NEXT: LBB30_23: ## %cond.load31 +; AVX512VLDQ-NEXT: je LBB30_12 +; AVX512VLDQ-NEXT: LBB30_28: ## %cond.load31 ; AVX512VLDQ-NEXT: vpinsrb $11, 11(%rdi), %xmm1, %xmm1 ; AVX512VLDQ-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX512VLDQ-NEXT: je LBB30_26 -; AVX512VLDQ-NEXT: LBB30_25: ## %cond.load34 +; AVX512VLDQ-NEXT: je LBB30_13 +; AVX512VLDQ-NEXT: LBB30_29: ## %cond.load34 ; AVX512VLDQ-NEXT: vpinsrb $12, 12(%rdi), %xmm1, %xmm1 ; AVX512VLDQ-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX512VLDQ-NEXT: je LBB30_28 -; AVX512VLDQ-NEXT: LBB30_27: ## %cond.load37 +; AVX512VLDQ-NEXT: je LBB30_14 +; AVX512VLDQ-NEXT: LBB30_30: ## %cond.load37 ; AVX512VLDQ-NEXT: vpinsrb $13, 13(%rdi), %xmm1, %xmm1 ; AVX512VLDQ-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX512VLDQ-NEXT: je LBB30_30 -; AVX512VLDQ-NEXT: LBB30_29: ## %cond.load40 +; AVX512VLDQ-NEXT: je LBB30_15 +; AVX512VLDQ-NEXT: LBB30_31: ## %cond.load40 ; AVX512VLDQ-NEXT: vpinsrb $14, 14(%rdi), %xmm1, %xmm1 ; AVX512VLDQ-NEXT: testl $32768, %eax ## imm = 0x8000 -; AVX512VLDQ-NEXT: je LBB30_32 -; AVX512VLDQ-NEXT: LBB30_31: ## %cond.load43 +; AVX512VLDQ-NEXT: je LBB30_16 +; AVX512VLDQ-NEXT: LBB30_32: ## %cond.load43 ; AVX512VLDQ-NEXT: vpinsrb $15, 15(%rdi), %xmm1, %xmm1 ; AVX512VLDQ-NEXT: vmovdqa %xmm1, %xmm0 ; AVX512VLDQ-NEXT: retq @@ -5317,111 +5317,111 @@ define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %dst ; SSE2-NEXT: shll $16, %eax ; SSE2-NEXT: orl %ecx, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB31_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB31_34 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB31_3 -; SSE2-NEXT: LBB31_4: ## %else2 +; SSE2-NEXT: jne LBB31_35 +; SSE2-NEXT: LBB31_2: ## %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB31_5 -; SSE2-NEXT: LBB31_6: ## %else5 +; SSE2-NEXT: jne LBB31_36 +; SSE2-NEXT: LBB31_3: ## %else5 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne LBB31_7 -; SSE2-NEXT: LBB31_8: ## %else8 +; SSE2-NEXT: jne LBB31_37 +; SSE2-NEXT: LBB31_4: ## %else8 ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: jne LBB31_9 -; SSE2-NEXT: LBB31_10: ## %else11 +; SSE2-NEXT: jne LBB31_38 +; SSE2-NEXT: LBB31_5: ## %else11 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: jne LBB31_11 -; SSE2-NEXT: LBB31_12: ## %else14 +; SSE2-NEXT: jne LBB31_39 +; SSE2-NEXT: LBB31_6: ## %else14 ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: jne LBB31_13 -; SSE2-NEXT: LBB31_14: ## %else17 +; SSE2-NEXT: jne LBB31_40 +; SSE2-NEXT: LBB31_7: ## %else17 ; SSE2-NEXT: testb %al, %al -; SSE2-NEXT: js LBB31_15 -; SSE2-NEXT: LBB31_16: ## %else20 +; SSE2-NEXT: js LBB31_41 +; SSE2-NEXT: LBB31_8: ## %else20 ; SSE2-NEXT: testl $256, %eax ## imm = 0x100 -; SSE2-NEXT: jne LBB31_17 -; SSE2-NEXT: LBB31_18: ## %else23 +; SSE2-NEXT: jne LBB31_42 +; SSE2-NEXT: LBB31_9: ## %else23 ; SSE2-NEXT: testl $512, %eax ## imm = 0x200 -; SSE2-NEXT: jne LBB31_19 -; SSE2-NEXT: LBB31_20: ## %else26 +; SSE2-NEXT: jne LBB31_43 +; SSE2-NEXT: LBB31_10: ## %else26 ; SSE2-NEXT: testl $1024, %eax ## imm = 0x400 -; SSE2-NEXT: jne LBB31_21 -; SSE2-NEXT: LBB31_22: ## %else29 +; SSE2-NEXT: jne LBB31_44 +; SSE2-NEXT: LBB31_11: ## %else29 ; SSE2-NEXT: testl $2048, %eax ## imm = 0x800 -; SSE2-NEXT: jne LBB31_23 -; SSE2-NEXT: LBB31_24: ## %else32 +; SSE2-NEXT: jne LBB31_45 +; SSE2-NEXT: LBB31_12: ## %else32 ; SSE2-NEXT: testl $4096, %eax ## imm = 0x1000 -; SSE2-NEXT: jne LBB31_25 -; SSE2-NEXT: LBB31_26: ## %else35 +; SSE2-NEXT: jne LBB31_46 +; SSE2-NEXT: LBB31_13: ## %else35 ; SSE2-NEXT: testl $8192, %eax ## imm = 0x2000 -; SSE2-NEXT: jne LBB31_27 -; SSE2-NEXT: LBB31_28: ## %else38 +; SSE2-NEXT: jne LBB31_47 +; SSE2-NEXT: LBB31_14: ## %else38 ; SSE2-NEXT: testl $16384, %eax ## imm = 0x4000 -; SSE2-NEXT: jne LBB31_29 -; SSE2-NEXT: LBB31_30: ## %else41 +; SSE2-NEXT: jne LBB31_48 +; SSE2-NEXT: LBB31_15: ## %else41 ; SSE2-NEXT: testw %ax, %ax -; SSE2-NEXT: js LBB31_31 -; SSE2-NEXT: LBB31_32: ## %else44 +; SSE2-NEXT: js LBB31_49 +; SSE2-NEXT: LBB31_16: ## %else44 ; SSE2-NEXT: testl $65536, %eax ## imm = 0x10000 -; SSE2-NEXT: jne LBB31_33 -; SSE2-NEXT: LBB31_34: ## %else47 +; SSE2-NEXT: jne LBB31_50 +; SSE2-NEXT: LBB31_17: ## %else47 ; SSE2-NEXT: testl $131072, %eax ## imm = 0x20000 -; SSE2-NEXT: jne LBB31_35 -; SSE2-NEXT: LBB31_36: ## %else50 +; SSE2-NEXT: jne LBB31_51 +; SSE2-NEXT: LBB31_18: ## %else50 ; SSE2-NEXT: testl $262144, %eax ## imm = 0x40000 -; SSE2-NEXT: jne LBB31_37 -; SSE2-NEXT: LBB31_38: ## %else53 +; SSE2-NEXT: jne LBB31_52 +; SSE2-NEXT: LBB31_19: ## %else53 ; SSE2-NEXT: testl $524288, %eax ## imm = 0x80000 -; SSE2-NEXT: jne LBB31_39 -; SSE2-NEXT: LBB31_40: ## %else56 +; SSE2-NEXT: jne LBB31_53 +; SSE2-NEXT: LBB31_20: ## %else56 ; SSE2-NEXT: testl $1048576, %eax ## imm = 0x100000 -; SSE2-NEXT: jne LBB31_41 -; SSE2-NEXT: LBB31_42: ## %else59 +; SSE2-NEXT: jne LBB31_54 +; SSE2-NEXT: LBB31_21: ## %else59 ; SSE2-NEXT: testl $2097152, %eax ## imm = 0x200000 -; SSE2-NEXT: jne LBB31_43 -; SSE2-NEXT: LBB31_44: ## %else62 +; SSE2-NEXT: jne LBB31_55 +; SSE2-NEXT: LBB31_22: ## %else62 ; SSE2-NEXT: testl $4194304, %eax ## imm = 0x400000 -; SSE2-NEXT: jne LBB31_45 -; SSE2-NEXT: LBB31_46: ## %else65 +; SSE2-NEXT: jne LBB31_56 +; SSE2-NEXT: LBB31_23: ## %else65 ; SSE2-NEXT: testl $8388608, %eax ## imm = 0x800000 -; SSE2-NEXT: jne LBB31_47 -; SSE2-NEXT: LBB31_48: ## %else68 +; SSE2-NEXT: jne LBB31_57 +; SSE2-NEXT: LBB31_24: ## %else68 ; SSE2-NEXT: testl $16777216, %eax ## imm = 0x1000000 -; SSE2-NEXT: jne LBB31_49 -; SSE2-NEXT: LBB31_50: ## %else71 +; SSE2-NEXT: jne LBB31_58 +; SSE2-NEXT: LBB31_25: ## %else71 ; SSE2-NEXT: testl $33554432, %eax ## imm = 0x2000000 -; SSE2-NEXT: jne LBB31_51 -; SSE2-NEXT: LBB31_52: ## %else74 +; SSE2-NEXT: jne LBB31_59 +; SSE2-NEXT: LBB31_26: ## %else74 ; SSE2-NEXT: testl $67108864, %eax ## imm = 0x4000000 -; SSE2-NEXT: jne LBB31_53 -; SSE2-NEXT: LBB31_54: ## %else77 +; SSE2-NEXT: jne LBB31_60 +; SSE2-NEXT: LBB31_27: ## %else77 ; SSE2-NEXT: testl $134217728, %eax ## imm = 0x8000000 -; SSE2-NEXT: jne LBB31_55 -; SSE2-NEXT: LBB31_56: ## %else80 +; SSE2-NEXT: jne LBB31_61 +; SSE2-NEXT: LBB31_28: ## %else80 ; SSE2-NEXT: testl $268435456, %eax ## imm = 0x10000000 -; SSE2-NEXT: jne LBB31_57 -; SSE2-NEXT: LBB31_58: ## %else83 +; SSE2-NEXT: jne LBB31_62 +; SSE2-NEXT: LBB31_29: ## %else83 ; SSE2-NEXT: testl $536870912, %eax ## imm = 0x20000000 -; SSE2-NEXT: jne LBB31_59 -; SSE2-NEXT: LBB31_60: ## %else86 +; SSE2-NEXT: jne LBB31_63 +; SSE2-NEXT: LBB31_30: ## %else86 ; SSE2-NEXT: testl $1073741824, %eax ## imm = 0x40000000 -; SSE2-NEXT: jne LBB31_61 -; SSE2-NEXT: LBB31_62: ## %else89 +; SSE2-NEXT: jne LBB31_64 +; SSE2-NEXT: LBB31_31: ## %else89 ; SSE2-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 -; SSE2-NEXT: je LBB31_64 -; SSE2-NEXT: LBB31_63: ## %cond.load91 +; SSE2-NEXT: je LBB31_33 +; SSE2-NEXT: LBB31_32: ## %cond.load91 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3 ; SSE2-NEXT: movzbl 31(%rdi), %eax ; SSE2-NEXT: movd %eax, %xmm0 ; SSE2-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0] ; SSE2-NEXT: por %xmm0, %xmm3 -; SSE2-NEXT: LBB31_64: ## %else92 +; SSE2-NEXT: LBB31_33: ## %else92 ; SSE2-NEXT: movdqa %xmm2, %xmm0 ; SSE2-NEXT: movdqa %xmm3, %xmm1 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB31_1: ## %cond.load +; SSE2-NEXT: LBB31_34: ## %cond.load ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm2 ; SSE2-NEXT: movzbl (%rdi), %ecx @@ -5429,8 +5429,8 @@ define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %dst ; SSE2-NEXT: pandn %xmm1, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm2 ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB31_4 -; SSE2-NEXT: LBB31_3: ## %cond.load1 +; SSE2-NEXT: je LBB31_2 +; SSE2-NEXT: LBB31_35: ## %cond.load1 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm2 ; SSE2-NEXT: movzbl 1(%rdi), %ecx @@ -5439,8 +5439,8 @@ define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %dst ; SSE2-NEXT: pandn %xmm1, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB31_6 -; SSE2-NEXT: LBB31_5: ## %cond.load4 +; SSE2-NEXT: je LBB31_3 +; SSE2-NEXT: LBB31_36: ## %cond.load4 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm2 ; SSE2-NEXT: movzbl 2(%rdi), %ecx @@ -5449,8 +5449,8 @@ define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %dst ; SSE2-NEXT: pandn %xmm1, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm2 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB31_8 -; SSE2-NEXT: LBB31_7: ## %cond.load7 +; SSE2-NEXT: je LBB31_4 +; SSE2-NEXT: LBB31_37: ## %cond.load7 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm2 ; SSE2-NEXT: movzbl 3(%rdi), %ecx @@ -5459,8 +5459,8 @@ define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %dst ; SSE2-NEXT: pandn %xmm1, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm2 ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: je LBB31_10 -; SSE2-NEXT: LBB31_9: ## %cond.load10 +; SSE2-NEXT: je LBB31_5 +; SSE2-NEXT: LBB31_38: ## %cond.load10 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm2 ; SSE2-NEXT: movzbl 4(%rdi), %ecx @@ -5469,8 +5469,8 @@ define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %dst ; SSE2-NEXT: pandn %xmm1, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm2 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je LBB31_12 -; SSE2-NEXT: LBB31_11: ## %cond.load13 +; SSE2-NEXT: je LBB31_6 +; SSE2-NEXT: LBB31_39: ## %cond.load13 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm2 ; SSE2-NEXT: movzbl 5(%rdi), %ecx @@ -5479,8 +5479,8 @@ define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %dst ; SSE2-NEXT: pandn %xmm1, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm2 ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: je LBB31_14 -; SSE2-NEXT: LBB31_13: ## %cond.load16 +; SSE2-NEXT: je LBB31_7 +; SSE2-NEXT: LBB31_40: ## %cond.load16 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm2 ; SSE2-NEXT: movzbl 6(%rdi), %ecx @@ -5489,8 +5489,8 @@ define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %dst ; SSE2-NEXT: pandn %xmm1, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm2 ; SSE2-NEXT: testb %al, %al -; SSE2-NEXT: jns LBB31_16 -; SSE2-NEXT: LBB31_15: ## %cond.load19 +; SSE2-NEXT: jns LBB31_8 +; SSE2-NEXT: LBB31_41: ## %cond.load19 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm2 ; SSE2-NEXT: movzbl 7(%rdi), %ecx @@ -5499,8 +5499,8 @@ define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %dst ; SSE2-NEXT: pandn %xmm1, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm2 ; SSE2-NEXT: testl $256, %eax ## imm = 0x100 -; SSE2-NEXT: je LBB31_18 -; SSE2-NEXT: LBB31_17: ## %cond.load22 +; SSE2-NEXT: je LBB31_9 +; SSE2-NEXT: LBB31_42: ## %cond.load22 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm2 ; SSE2-NEXT: movzbl 8(%rdi), %ecx @@ -5509,8 +5509,8 @@ define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %dst ; SSE2-NEXT: pandn %xmm1, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm2 ; SSE2-NEXT: testl $512, %eax ## imm = 0x200 -; SSE2-NEXT: je LBB31_20 -; SSE2-NEXT: LBB31_19: ## %cond.load25 +; SSE2-NEXT: je LBB31_10 +; SSE2-NEXT: LBB31_43: ## %cond.load25 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm2 ; SSE2-NEXT: movzbl 9(%rdi), %ecx @@ -5519,8 +5519,8 @@ define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %dst ; SSE2-NEXT: pandn %xmm1, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm2 ; SSE2-NEXT: testl $1024, %eax ## imm = 0x400 -; SSE2-NEXT: je LBB31_22 -; SSE2-NEXT: LBB31_21: ## %cond.load28 +; SSE2-NEXT: je LBB31_11 +; SSE2-NEXT: LBB31_44: ## %cond.load28 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm2 ; SSE2-NEXT: movzbl 10(%rdi), %ecx @@ -5529,8 +5529,8 @@ define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %dst ; SSE2-NEXT: pandn %xmm1, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm2 ; SSE2-NEXT: testl $2048, %eax ## imm = 0x800 -; SSE2-NEXT: je LBB31_24 -; SSE2-NEXT: LBB31_23: ## %cond.load31 +; SSE2-NEXT: je LBB31_12 +; SSE2-NEXT: LBB31_45: ## %cond.load31 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm2 ; SSE2-NEXT: movzbl 11(%rdi), %ecx @@ -5539,8 +5539,8 @@ define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %dst ; SSE2-NEXT: pandn %xmm1, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm2 ; SSE2-NEXT: testl $4096, %eax ## imm = 0x1000 -; SSE2-NEXT: je LBB31_26 -; SSE2-NEXT: LBB31_25: ## %cond.load34 +; SSE2-NEXT: je LBB31_13 +; SSE2-NEXT: LBB31_46: ## %cond.load34 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm2 ; SSE2-NEXT: movzbl 12(%rdi), %ecx @@ -5549,8 +5549,8 @@ define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %dst ; SSE2-NEXT: pandn %xmm1, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm2 ; SSE2-NEXT: testl $8192, %eax ## imm = 0x2000 -; SSE2-NEXT: je LBB31_28 -; SSE2-NEXT: LBB31_27: ## %cond.load37 +; SSE2-NEXT: je LBB31_14 +; SSE2-NEXT: LBB31_47: ## %cond.load37 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255] ; SSE2-NEXT: pand %xmm0, %xmm2 ; SSE2-NEXT: movzbl 13(%rdi), %ecx @@ -5559,8 +5559,8 @@ define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %dst ; SSE2-NEXT: pandn %xmm1, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm2 ; SSE2-NEXT: testl $16384, %eax ## imm = 0x4000 -; SSE2-NEXT: je LBB31_30 -; SSE2-NEXT: LBB31_29: ## %cond.load40 +; SSE2-NEXT: je LBB31_15 +; SSE2-NEXT: LBB31_48: ## %cond.load40 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255] ; SSE2-NEXT: pand %xmm0, %xmm2 ; SSE2-NEXT: movzbl 14(%rdi), %ecx @@ -5569,16 +5569,16 @@ define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %dst ; SSE2-NEXT: pandn %xmm1, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm2 ; SSE2-NEXT: testw %ax, %ax -; SSE2-NEXT: jns LBB31_32 -; SSE2-NEXT: LBB31_31: ## %cond.load43 +; SSE2-NEXT: jns LBB31_16 +; SSE2-NEXT: LBB31_49: ## %cond.load43 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 ; SSE2-NEXT: movzbl 15(%rdi), %ecx ; SSE2-NEXT: movd %ecx, %xmm0 ; SSE2-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0] ; SSE2-NEXT: por %xmm0, %xmm2 ; SSE2-NEXT: testl $65536, %eax ## imm = 0x10000 -; SSE2-NEXT: je LBB31_34 -; SSE2-NEXT: LBB31_33: ## %cond.load46 +; SSE2-NEXT: je LBB31_17 +; SSE2-NEXT: LBB31_50: ## %cond.load46 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm3 ; SSE2-NEXT: movzbl 16(%rdi), %ecx @@ -5586,8 +5586,8 @@ define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %dst ; SSE2-NEXT: pandn %xmm1, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm3 ; SSE2-NEXT: testl $131072, %eax ## imm = 0x20000 -; SSE2-NEXT: je LBB31_36 -; SSE2-NEXT: LBB31_35: ## %cond.load49 +; SSE2-NEXT: je LBB31_18 +; SSE2-NEXT: LBB31_51: ## %cond.load49 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,0,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm3 ; SSE2-NEXT: movzbl 17(%rdi), %ecx @@ -5596,8 +5596,8 @@ define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %dst ; SSE2-NEXT: pandn %xmm1, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm3 ; SSE2-NEXT: testl $262144, %eax ## imm = 0x40000 -; SSE2-NEXT: je LBB31_38 -; SSE2-NEXT: LBB31_37: ## %cond.load52 +; SSE2-NEXT: je LBB31_19 +; SSE2-NEXT: LBB31_52: ## %cond.load52 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm3 ; SSE2-NEXT: movzbl 18(%rdi), %ecx @@ -5606,8 +5606,8 @@ define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %dst ; SSE2-NEXT: pandn %xmm1, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm3 ; SSE2-NEXT: testl $524288, %eax ## imm = 0x80000 -; SSE2-NEXT: je LBB31_40 -; SSE2-NEXT: LBB31_39: ## %cond.load55 +; SSE2-NEXT: je LBB31_20 +; SSE2-NEXT: LBB31_53: ## %cond.load55 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,0,255,255,255,255,255,255,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm3 ; SSE2-NEXT: movzbl 19(%rdi), %ecx @@ -5616,8 +5616,8 @@ define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %dst ; SSE2-NEXT: pandn %xmm1, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm3 ; SSE2-NEXT: testl $1048576, %eax ## imm = 0x100000 -; SSE2-NEXT: je LBB31_42 -; SSE2-NEXT: LBB31_41: ## %cond.load58 +; SSE2-NEXT: je LBB31_21 +; SSE2-NEXT: LBB31_54: ## %cond.load58 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,255,0,255,255,255,255,255,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm3 ; SSE2-NEXT: movzbl 20(%rdi), %ecx @@ -5626,8 +5626,8 @@ define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %dst ; SSE2-NEXT: pandn %xmm1, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm3 ; SSE2-NEXT: testl $2097152, %eax ## imm = 0x200000 -; SSE2-NEXT: je LBB31_44 -; SSE2-NEXT: LBB31_43: ## %cond.load61 +; SSE2-NEXT: je LBB31_22 +; SSE2-NEXT: LBB31_55: ## %cond.load61 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm3 ; SSE2-NEXT: movzbl 21(%rdi), %ecx @@ -5636,8 +5636,8 @@ define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %dst ; SSE2-NEXT: pandn %xmm1, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm3 ; SSE2-NEXT: testl $4194304, %eax ## imm = 0x400000 -; SSE2-NEXT: je LBB31_46 -; SSE2-NEXT: LBB31_45: ## %cond.load64 +; SSE2-NEXT: je LBB31_23 +; SSE2-NEXT: LBB31_56: ## %cond.load64 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,255,255,255,0,255,255,255,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm3 ; SSE2-NEXT: movzbl 22(%rdi), %ecx @@ -5646,8 +5646,8 @@ define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %dst ; SSE2-NEXT: pandn %xmm1, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm3 ; SSE2-NEXT: testl $8388608, %eax ## imm = 0x800000 -; SSE2-NEXT: je LBB31_48 -; SSE2-NEXT: LBB31_47: ## %cond.load67 +; SSE2-NEXT: je LBB31_24 +; SSE2-NEXT: LBB31_57: ## %cond.load67 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm3 ; SSE2-NEXT: movzbl 23(%rdi), %ecx @@ -5656,8 +5656,8 @@ define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %dst ; SSE2-NEXT: pandn %xmm1, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm3 ; SSE2-NEXT: testl $16777216, %eax ## imm = 0x1000000 -; SSE2-NEXT: je LBB31_50 -; SSE2-NEXT: LBB31_49: ## %cond.load70 +; SSE2-NEXT: je LBB31_25 +; SSE2-NEXT: LBB31_58: ## %cond.load70 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,255,255,255,255,255,0,255,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm3 ; SSE2-NEXT: movzbl 24(%rdi), %ecx @@ -5666,8 +5666,8 @@ define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %dst ; SSE2-NEXT: pandn %xmm1, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm3 ; SSE2-NEXT: testl $33554432, %eax ## imm = 0x2000000 -; SSE2-NEXT: je LBB31_52 -; SSE2-NEXT: LBB31_51: ## %cond.load73 +; SSE2-NEXT: je LBB31_26 +; SSE2-NEXT: LBB31_59: ## %cond.load73 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,255,255,255,255,255,255,0,255,255,255,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm3 ; SSE2-NEXT: movzbl 25(%rdi), %ecx @@ -5676,8 +5676,8 @@ define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %dst ; SSE2-NEXT: pandn %xmm1, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm3 ; SSE2-NEXT: testl $67108864, %eax ## imm = 0x4000000 -; SSE2-NEXT: je LBB31_54 -; SSE2-NEXT: LBB31_53: ## %cond.load76 +; SSE2-NEXT: je LBB31_27 +; SSE2-NEXT: LBB31_60: ## %cond.load76 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,255,255,255,255,255,255,255,0,255,255,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm3 ; SSE2-NEXT: movzbl 26(%rdi), %ecx @@ -5686,8 +5686,8 @@ define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %dst ; SSE2-NEXT: pandn %xmm1, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm3 ; SSE2-NEXT: testl $134217728, %eax ## imm = 0x8000000 -; SSE2-NEXT: je LBB31_56 -; SSE2-NEXT: LBB31_55: ## %cond.load79 +; SSE2-NEXT: je LBB31_28 +; SSE2-NEXT: LBB31_61: ## %cond.load79 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,255,255,255,255,255,255,255,255,0,255,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm3 ; SSE2-NEXT: movzbl 27(%rdi), %ecx @@ -5696,8 +5696,8 @@ define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %dst ; SSE2-NEXT: pandn %xmm1, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm3 ; SSE2-NEXT: testl $268435456, %eax ## imm = 0x10000000 -; SSE2-NEXT: je LBB31_58 -; SSE2-NEXT: LBB31_57: ## %cond.load82 +; SSE2-NEXT: je LBB31_29 +; SSE2-NEXT: LBB31_62: ## %cond.load82 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,255,255,255,255,255,255,255,255,255,0,255,255,255] ; SSE2-NEXT: pand %xmm0, %xmm3 ; SSE2-NEXT: movzbl 28(%rdi), %ecx @@ -5706,8 +5706,8 @@ define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %dst ; SSE2-NEXT: pandn %xmm1, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm3 ; SSE2-NEXT: testl $536870912, %eax ## imm = 0x20000000 -; SSE2-NEXT: je LBB31_60 -; SSE2-NEXT: LBB31_59: ## %cond.load85 +; SSE2-NEXT: je LBB31_30 +; SSE2-NEXT: LBB31_63: ## %cond.load85 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,255,255,255,255,255,255,255,255,255,255,0,255,255] ; SSE2-NEXT: pand %xmm0, %xmm3 ; SSE2-NEXT: movzbl 29(%rdi), %ecx @@ -5716,8 +5716,8 @@ define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %dst ; SSE2-NEXT: pandn %xmm1, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm3 ; SSE2-NEXT: testl $1073741824, %eax ## imm = 0x40000000 -; SSE2-NEXT: je LBB31_62 -; SSE2-NEXT: LBB31_61: ## %cond.load88 +; SSE2-NEXT: je LBB31_31 +; SSE2-NEXT: LBB31_64: ## %cond.load88 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,0,255] ; SSE2-NEXT: pand %xmm0, %xmm3 ; SSE2-NEXT: movzbl 30(%rdi), %ecx @@ -5726,8 +5726,8 @@ define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %dst ; SSE2-NEXT: pandn %xmm1, %xmm0 ; SSE2-NEXT: por %xmm0, %xmm3 ; SSE2-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 -; SSE2-NEXT: jne LBB31_63 -; SSE2-NEXT: jmp LBB31_64 +; SSE2-NEXT: jne LBB31_32 +; SSE2-NEXT: jmp LBB31_33 ; ; SSE42-LABEL: load_v32i8_v32i8: ; SSE42: ## %bb.0: @@ -5736,231 +5736,231 @@ define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %dst ; SSE42-NEXT: shll $16, %eax ; SSE42-NEXT: orl %ecx, %eax ; SSE42-NEXT: testb $1, %al -; SSE42-NEXT: jne LBB31_1 -; SSE42-NEXT: ## %bb.2: ## %else +; SSE42-NEXT: jne LBB31_34 +; SSE42-NEXT: ## %bb.1: ## %else ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: jne LBB31_3 -; SSE42-NEXT: LBB31_4: ## %else2 +; SSE42-NEXT: jne LBB31_35 +; SSE42-NEXT: LBB31_2: ## %else2 ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: jne LBB31_5 -; SSE42-NEXT: LBB31_6: ## %else5 +; SSE42-NEXT: jne LBB31_36 +; SSE42-NEXT: LBB31_3: ## %else5 ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: jne LBB31_7 -; SSE42-NEXT: LBB31_8: ## %else8 +; SSE42-NEXT: jne LBB31_37 +; SSE42-NEXT: LBB31_4: ## %else8 ; SSE42-NEXT: testb $16, %al -; SSE42-NEXT: jne LBB31_9 -; SSE42-NEXT: LBB31_10: ## %else11 +; SSE42-NEXT: jne LBB31_38 +; SSE42-NEXT: LBB31_5: ## %else11 ; SSE42-NEXT: testb $32, %al -; SSE42-NEXT: jne LBB31_11 -; SSE42-NEXT: LBB31_12: ## %else14 +; SSE42-NEXT: jne LBB31_39 +; SSE42-NEXT: LBB31_6: ## %else14 ; SSE42-NEXT: testb $64, %al -; SSE42-NEXT: jne LBB31_13 -; SSE42-NEXT: LBB31_14: ## %else17 +; SSE42-NEXT: jne LBB31_40 +; SSE42-NEXT: LBB31_7: ## %else17 ; SSE42-NEXT: testb %al, %al -; SSE42-NEXT: js LBB31_15 -; SSE42-NEXT: LBB31_16: ## %else20 +; SSE42-NEXT: js LBB31_41 +; SSE42-NEXT: LBB31_8: ## %else20 ; SSE42-NEXT: testl $256, %eax ## imm = 0x100 -; SSE42-NEXT: jne LBB31_17 -; SSE42-NEXT: LBB31_18: ## %else23 +; SSE42-NEXT: jne LBB31_42 +; SSE42-NEXT: LBB31_9: ## %else23 ; SSE42-NEXT: testl $512, %eax ## imm = 0x200 -; SSE42-NEXT: jne LBB31_19 -; SSE42-NEXT: LBB31_20: ## %else26 +; SSE42-NEXT: jne LBB31_43 +; SSE42-NEXT: LBB31_10: ## %else26 ; SSE42-NEXT: testl $1024, %eax ## imm = 0x400 -; SSE42-NEXT: jne LBB31_21 -; SSE42-NEXT: LBB31_22: ## %else29 +; SSE42-NEXT: jne LBB31_44 +; SSE42-NEXT: LBB31_11: ## %else29 ; SSE42-NEXT: testl $2048, %eax ## imm = 0x800 -; SSE42-NEXT: jne LBB31_23 -; SSE42-NEXT: LBB31_24: ## %else32 +; SSE42-NEXT: jne LBB31_45 +; SSE42-NEXT: LBB31_12: ## %else32 ; SSE42-NEXT: testl $4096, %eax ## imm = 0x1000 -; SSE42-NEXT: jne LBB31_25 -; SSE42-NEXT: LBB31_26: ## %else35 +; SSE42-NEXT: jne LBB31_46 +; SSE42-NEXT: LBB31_13: ## %else35 ; SSE42-NEXT: testl $8192, %eax ## imm = 0x2000 -; SSE42-NEXT: jne LBB31_27 -; SSE42-NEXT: LBB31_28: ## %else38 +; SSE42-NEXT: jne LBB31_47 +; SSE42-NEXT: LBB31_14: ## %else38 ; SSE42-NEXT: testl $16384, %eax ## imm = 0x4000 -; SSE42-NEXT: jne LBB31_29 -; SSE42-NEXT: LBB31_30: ## %else41 +; SSE42-NEXT: jne LBB31_48 +; SSE42-NEXT: LBB31_15: ## %else41 ; SSE42-NEXT: testw %ax, %ax -; SSE42-NEXT: js LBB31_31 -; SSE42-NEXT: LBB31_32: ## %else44 +; SSE42-NEXT: js LBB31_49 +; SSE42-NEXT: LBB31_16: ## %else44 ; SSE42-NEXT: testl $65536, %eax ## imm = 0x10000 -; SSE42-NEXT: jne LBB31_33 -; SSE42-NEXT: LBB31_34: ## %else47 +; SSE42-NEXT: jne LBB31_50 +; SSE42-NEXT: LBB31_17: ## %else47 ; SSE42-NEXT: testl $131072, %eax ## imm = 0x20000 -; SSE42-NEXT: jne LBB31_35 -; SSE42-NEXT: LBB31_36: ## %else50 +; SSE42-NEXT: jne LBB31_51 +; SSE42-NEXT: LBB31_18: ## %else50 ; SSE42-NEXT: testl $262144, %eax ## imm = 0x40000 -; SSE42-NEXT: jne LBB31_37 -; SSE42-NEXT: LBB31_38: ## %else53 +; SSE42-NEXT: jne LBB31_52 +; SSE42-NEXT: LBB31_19: ## %else53 ; SSE42-NEXT: testl $524288, %eax ## imm = 0x80000 -; SSE42-NEXT: jne LBB31_39 -; SSE42-NEXT: LBB31_40: ## %else56 +; SSE42-NEXT: jne LBB31_53 +; SSE42-NEXT: LBB31_20: ## %else56 ; SSE42-NEXT: testl $1048576, %eax ## imm = 0x100000 -; SSE42-NEXT: jne LBB31_41 -; SSE42-NEXT: LBB31_42: ## %else59 +; SSE42-NEXT: jne LBB31_54 +; SSE42-NEXT: LBB31_21: ## %else59 ; SSE42-NEXT: testl $2097152, %eax ## imm = 0x200000 -; SSE42-NEXT: jne LBB31_43 -; SSE42-NEXT: LBB31_44: ## %else62 +; SSE42-NEXT: jne LBB31_55 +; SSE42-NEXT: LBB31_22: ## %else62 ; SSE42-NEXT: testl $4194304, %eax ## imm = 0x400000 -; SSE42-NEXT: jne LBB31_45 -; SSE42-NEXT: LBB31_46: ## %else65 +; SSE42-NEXT: jne LBB31_56 +; SSE42-NEXT: LBB31_23: ## %else65 ; SSE42-NEXT: testl $8388608, %eax ## imm = 0x800000 -; SSE42-NEXT: jne LBB31_47 -; SSE42-NEXT: LBB31_48: ## %else68 +; SSE42-NEXT: jne LBB31_57 +; SSE42-NEXT: LBB31_24: ## %else68 ; SSE42-NEXT: testl $16777216, %eax ## imm = 0x1000000 -; SSE42-NEXT: jne LBB31_49 -; SSE42-NEXT: LBB31_50: ## %else71 +; SSE42-NEXT: jne LBB31_58 +; SSE42-NEXT: LBB31_25: ## %else71 ; SSE42-NEXT: testl $33554432, %eax ## imm = 0x2000000 -; SSE42-NEXT: jne LBB31_51 -; SSE42-NEXT: LBB31_52: ## %else74 +; SSE42-NEXT: jne LBB31_59 +; SSE42-NEXT: LBB31_26: ## %else74 ; SSE42-NEXT: testl $67108864, %eax ## imm = 0x4000000 -; SSE42-NEXT: jne LBB31_53 -; SSE42-NEXT: LBB31_54: ## %else77 +; SSE42-NEXT: jne LBB31_60 +; SSE42-NEXT: LBB31_27: ## %else77 ; SSE42-NEXT: testl $134217728, %eax ## imm = 0x8000000 -; SSE42-NEXT: jne LBB31_55 -; SSE42-NEXT: LBB31_56: ## %else80 +; SSE42-NEXT: jne LBB31_61 +; SSE42-NEXT: LBB31_28: ## %else80 ; SSE42-NEXT: testl $268435456, %eax ## imm = 0x10000000 -; SSE42-NEXT: jne LBB31_57 -; SSE42-NEXT: LBB31_58: ## %else83 +; SSE42-NEXT: jne LBB31_62 +; SSE42-NEXT: LBB31_29: ## %else83 ; SSE42-NEXT: testl $536870912, %eax ## imm = 0x20000000 -; SSE42-NEXT: jne LBB31_59 -; SSE42-NEXT: LBB31_60: ## %else86 +; SSE42-NEXT: jne LBB31_63 +; SSE42-NEXT: LBB31_30: ## %else86 ; SSE42-NEXT: testl $1073741824, %eax ## imm = 0x40000000 -; SSE42-NEXT: jne LBB31_61 -; SSE42-NEXT: LBB31_62: ## %else89 +; SSE42-NEXT: jne LBB31_64 +; SSE42-NEXT: LBB31_31: ## %else89 ; SSE42-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 -; SSE42-NEXT: je LBB31_64 -; SSE42-NEXT: LBB31_63: ## %cond.load91 +; SSE42-NEXT: je LBB31_33 +; SSE42-NEXT: LBB31_32: ## %cond.load91 ; SSE42-NEXT: pinsrb $15, 31(%rdi), %xmm3 -; SSE42-NEXT: LBB31_64: ## %else92 +; SSE42-NEXT: LBB31_33: ## %else92 ; SSE42-NEXT: movdqa %xmm2, %xmm0 ; SSE42-NEXT: movdqa %xmm3, %xmm1 ; SSE42-NEXT: retq -; SSE42-NEXT: LBB31_1: ## %cond.load +; SSE42-NEXT: LBB31_34: ## %cond.load ; SSE42-NEXT: pinsrb $0, (%rdi), %xmm2 ; SSE42-NEXT: testb $2, %al -; SSE42-NEXT: je LBB31_4 -; SSE42-NEXT: LBB31_3: ## %cond.load1 +; SSE42-NEXT: je LBB31_2 +; SSE42-NEXT: LBB31_35: ## %cond.load1 ; SSE42-NEXT: pinsrb $1, 1(%rdi), %xmm2 ; SSE42-NEXT: testb $4, %al -; SSE42-NEXT: je LBB31_6 -; SSE42-NEXT: LBB31_5: ## %cond.load4 +; SSE42-NEXT: je LBB31_3 +; SSE42-NEXT: LBB31_36: ## %cond.load4 ; SSE42-NEXT: pinsrb $2, 2(%rdi), %xmm2 ; SSE42-NEXT: testb $8, %al -; SSE42-NEXT: je LBB31_8 -; SSE42-NEXT: LBB31_7: ## %cond.load7 +; SSE42-NEXT: je LBB31_4 +; SSE42-NEXT: LBB31_37: ## %cond.load7 ; SSE42-NEXT: pinsrb $3, 3(%rdi), %xmm2 ; SSE42-NEXT: testb $16, %al -; SSE42-NEXT: je LBB31_10 -; SSE42-NEXT: LBB31_9: ## %cond.load10 +; SSE42-NEXT: je LBB31_5 +; SSE42-NEXT: LBB31_38: ## %cond.load10 ; SSE42-NEXT: pinsrb $4, 4(%rdi), %xmm2 ; SSE42-NEXT: testb $32, %al -; SSE42-NEXT: je LBB31_12 -; SSE42-NEXT: LBB31_11: ## %cond.load13 +; SSE42-NEXT: je LBB31_6 +; SSE42-NEXT: LBB31_39: ## %cond.load13 ; SSE42-NEXT: pinsrb $5, 5(%rdi), %xmm2 ; SSE42-NEXT: testb $64, %al -; SSE42-NEXT: je LBB31_14 -; SSE42-NEXT: LBB31_13: ## %cond.load16 +; SSE42-NEXT: je LBB31_7 +; SSE42-NEXT: LBB31_40: ## %cond.load16 ; SSE42-NEXT: pinsrb $6, 6(%rdi), %xmm2 ; SSE42-NEXT: testb %al, %al -; SSE42-NEXT: jns LBB31_16 -; SSE42-NEXT: LBB31_15: ## %cond.load19 +; SSE42-NEXT: jns LBB31_8 +; SSE42-NEXT: LBB31_41: ## %cond.load19 ; SSE42-NEXT: pinsrb $7, 7(%rdi), %xmm2 ; SSE42-NEXT: testl $256, %eax ## imm = 0x100 -; SSE42-NEXT: je LBB31_18 -; SSE42-NEXT: LBB31_17: ## %cond.load22 +; SSE42-NEXT: je LBB31_9 +; SSE42-NEXT: LBB31_42: ## %cond.load22 ; SSE42-NEXT: pinsrb $8, 8(%rdi), %xmm2 ; SSE42-NEXT: testl $512, %eax ## imm = 0x200 -; SSE42-NEXT: je LBB31_20 -; SSE42-NEXT: LBB31_19: ## %cond.load25 +; SSE42-NEXT: je LBB31_10 +; SSE42-NEXT: LBB31_43: ## %cond.load25 ; SSE42-NEXT: pinsrb $9, 9(%rdi), %xmm2 ; SSE42-NEXT: testl $1024, %eax ## imm = 0x400 -; SSE42-NEXT: je LBB31_22 -; SSE42-NEXT: LBB31_21: ## %cond.load28 +; SSE42-NEXT: je LBB31_11 +; SSE42-NEXT: LBB31_44: ## %cond.load28 ; SSE42-NEXT: pinsrb $10, 10(%rdi), %xmm2 ; SSE42-NEXT: testl $2048, %eax ## imm = 0x800 -; SSE42-NEXT: je LBB31_24 -; SSE42-NEXT: LBB31_23: ## %cond.load31 +; SSE42-NEXT: je LBB31_12 +; SSE42-NEXT: LBB31_45: ## %cond.load31 ; SSE42-NEXT: pinsrb $11, 11(%rdi), %xmm2 ; SSE42-NEXT: testl $4096, %eax ## imm = 0x1000 -; SSE42-NEXT: je LBB31_26 -; SSE42-NEXT: LBB31_25: ## %cond.load34 +; SSE42-NEXT: je LBB31_13 +; SSE42-NEXT: LBB31_46: ## %cond.load34 ; SSE42-NEXT: pinsrb $12, 12(%rdi), %xmm2 ; SSE42-NEXT: testl $8192, %eax ## imm = 0x2000 -; SSE42-NEXT: je LBB31_28 -; SSE42-NEXT: LBB31_27: ## %cond.load37 +; SSE42-NEXT: je LBB31_14 +; SSE42-NEXT: LBB31_47: ## %cond.load37 ; SSE42-NEXT: pinsrb $13, 13(%rdi), %xmm2 ; SSE42-NEXT: testl $16384, %eax ## imm = 0x4000 -; SSE42-NEXT: je LBB31_30 -; SSE42-NEXT: LBB31_29: ## %cond.load40 +; SSE42-NEXT: je LBB31_15 +; SSE42-NEXT: LBB31_48: ## %cond.load40 ; SSE42-NEXT: pinsrb $14, 14(%rdi), %xmm2 ; SSE42-NEXT: testw %ax, %ax -; SSE42-NEXT: jns LBB31_32 -; SSE42-NEXT: LBB31_31: ## %cond.load43 +; SSE42-NEXT: jns LBB31_16 +; SSE42-NEXT: LBB31_49: ## %cond.load43 ; SSE42-NEXT: pinsrb $15, 15(%rdi), %xmm2 ; SSE42-NEXT: testl $65536, %eax ## imm = 0x10000 -; SSE42-NEXT: je LBB31_34 -; SSE42-NEXT: LBB31_33: ## %cond.load46 +; SSE42-NEXT: je LBB31_17 +; SSE42-NEXT: LBB31_50: ## %cond.load46 ; SSE42-NEXT: pinsrb $0, 16(%rdi), %xmm3 ; SSE42-NEXT: testl $131072, %eax ## imm = 0x20000 -; SSE42-NEXT: je LBB31_36 -; SSE42-NEXT: LBB31_35: ## %cond.load49 +; SSE42-NEXT: je LBB31_18 +; SSE42-NEXT: LBB31_51: ## %cond.load49 ; SSE42-NEXT: pinsrb $1, 17(%rdi), %xmm3 ; SSE42-NEXT: testl $262144, %eax ## imm = 0x40000 -; SSE42-NEXT: je LBB31_38 -; SSE42-NEXT: LBB31_37: ## %cond.load52 +; SSE42-NEXT: je LBB31_19 +; SSE42-NEXT: LBB31_52: ## %cond.load52 ; SSE42-NEXT: pinsrb $2, 18(%rdi), %xmm3 ; SSE42-NEXT: testl $524288, %eax ## imm = 0x80000 -; SSE42-NEXT: je LBB31_40 -; SSE42-NEXT: LBB31_39: ## %cond.load55 +; SSE42-NEXT: je LBB31_20 +; SSE42-NEXT: LBB31_53: ## %cond.load55 ; SSE42-NEXT: pinsrb $3, 19(%rdi), %xmm3 ; SSE42-NEXT: testl $1048576, %eax ## imm = 0x100000 -; SSE42-NEXT: je LBB31_42 -; SSE42-NEXT: LBB31_41: ## %cond.load58 +; SSE42-NEXT: je LBB31_21 +; SSE42-NEXT: LBB31_54: ## %cond.load58 ; SSE42-NEXT: pinsrb $4, 20(%rdi), %xmm3 ; SSE42-NEXT: testl $2097152, %eax ## imm = 0x200000 -; SSE42-NEXT: je LBB31_44 -; SSE42-NEXT: LBB31_43: ## %cond.load61 +; SSE42-NEXT: je LBB31_22 +; SSE42-NEXT: LBB31_55: ## %cond.load61 ; SSE42-NEXT: pinsrb $5, 21(%rdi), %xmm3 ; SSE42-NEXT: testl $4194304, %eax ## imm = 0x400000 -; SSE42-NEXT: je LBB31_46 -; SSE42-NEXT: LBB31_45: ## %cond.load64 +; SSE42-NEXT: je LBB31_23 +; SSE42-NEXT: LBB31_56: ## %cond.load64 ; SSE42-NEXT: pinsrb $6, 22(%rdi), %xmm3 ; SSE42-NEXT: testl $8388608, %eax ## imm = 0x800000 -; SSE42-NEXT: je LBB31_48 -; SSE42-NEXT: LBB31_47: ## %cond.load67 +; SSE42-NEXT: je LBB31_24 +; SSE42-NEXT: LBB31_57: ## %cond.load67 ; SSE42-NEXT: pinsrb $7, 23(%rdi), %xmm3 ; SSE42-NEXT: testl $16777216, %eax ## imm = 0x1000000 -; SSE42-NEXT: je LBB31_50 -; SSE42-NEXT: LBB31_49: ## %cond.load70 +; SSE42-NEXT: je LBB31_25 +; SSE42-NEXT: LBB31_58: ## %cond.load70 ; SSE42-NEXT: pinsrb $8, 24(%rdi), %xmm3 ; SSE42-NEXT: testl $33554432, %eax ## imm = 0x2000000 -; SSE42-NEXT: je LBB31_52 -; SSE42-NEXT: LBB31_51: ## %cond.load73 +; SSE42-NEXT: je LBB31_26 +; SSE42-NEXT: LBB31_59: ## %cond.load73 ; SSE42-NEXT: pinsrb $9, 25(%rdi), %xmm3 ; SSE42-NEXT: testl $67108864, %eax ## imm = 0x4000000 -; SSE42-NEXT: je LBB31_54 -; SSE42-NEXT: LBB31_53: ## %cond.load76 +; SSE42-NEXT: je LBB31_27 +; SSE42-NEXT: LBB31_60: ## %cond.load76 ; SSE42-NEXT: pinsrb $10, 26(%rdi), %xmm3 ; SSE42-NEXT: testl $134217728, %eax ## imm = 0x8000000 -; SSE42-NEXT: je LBB31_56 -; SSE42-NEXT: LBB31_55: ## %cond.load79 +; SSE42-NEXT: je LBB31_28 +; SSE42-NEXT: LBB31_61: ## %cond.load79 ; SSE42-NEXT: pinsrb $11, 27(%rdi), %xmm3 ; SSE42-NEXT: testl $268435456, %eax ## imm = 0x10000000 -; SSE42-NEXT: je LBB31_58 -; SSE42-NEXT: LBB31_57: ## %cond.load82 +; SSE42-NEXT: je LBB31_29 +; SSE42-NEXT: LBB31_62: ## %cond.load82 ; SSE42-NEXT: pinsrb $12, 28(%rdi), %xmm3 ; SSE42-NEXT: testl $536870912, %eax ## imm = 0x20000000 -; SSE42-NEXT: je LBB31_60 -; SSE42-NEXT: LBB31_59: ## %cond.load85 +; SSE42-NEXT: je LBB31_30 +; SSE42-NEXT: LBB31_63: ## %cond.load85 ; SSE42-NEXT: pinsrb $13, 29(%rdi), %xmm3 ; SSE42-NEXT: testl $1073741824, %eax ## imm = 0x40000000 -; SSE42-NEXT: je LBB31_62 -; SSE42-NEXT: LBB31_61: ## %cond.load88 +; SSE42-NEXT: je LBB31_31 +; SSE42-NEXT: LBB31_64: ## %cond.load88 ; SSE42-NEXT: pinsrb $14, 30(%rdi), %xmm3 ; SSE42-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 -; SSE42-NEXT: jne LBB31_63 -; SSE42-NEXT: jmp LBB31_64 +; SSE42-NEXT: jne LBB31_32 +; SSE42-NEXT: jmp LBB31_33 ; ; AVX1-LABEL: load_v32i8_v32i8: ; AVX1: ## %bb.0: @@ -5970,274 +5970,274 @@ define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %dst ; AVX1-NEXT: shll $16, %eax ; AVX1-NEXT: orl %ecx, %eax ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne LBB31_1 -; AVX1-NEXT: ## %bb.2: ## %else +; AVX1-NEXT: jne LBB31_33 +; AVX1-NEXT: ## %bb.1: ## %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne LBB31_3 -; AVX1-NEXT: LBB31_4: ## %else2 +; AVX1-NEXT: jne LBB31_34 +; AVX1-NEXT: LBB31_2: ## %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne LBB31_5 -; AVX1-NEXT: LBB31_6: ## %else5 +; AVX1-NEXT: jne LBB31_35 +; AVX1-NEXT: LBB31_3: ## %else5 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne LBB31_7 -; AVX1-NEXT: LBB31_8: ## %else8 +; AVX1-NEXT: jne LBB31_36 +; AVX1-NEXT: LBB31_4: ## %else8 ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: jne LBB31_9 -; AVX1-NEXT: LBB31_10: ## %else11 +; AVX1-NEXT: jne LBB31_37 +; AVX1-NEXT: LBB31_5: ## %else11 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: jne LBB31_11 -; AVX1-NEXT: LBB31_12: ## %else14 +; AVX1-NEXT: jne LBB31_38 +; AVX1-NEXT: LBB31_6: ## %else14 ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: jne LBB31_13 -; AVX1-NEXT: LBB31_14: ## %else17 +; AVX1-NEXT: jne LBB31_39 +; AVX1-NEXT: LBB31_7: ## %else17 ; AVX1-NEXT: testb %al, %al -; AVX1-NEXT: js LBB31_15 -; AVX1-NEXT: LBB31_16: ## %else20 +; AVX1-NEXT: js LBB31_40 +; AVX1-NEXT: LBB31_8: ## %else20 ; AVX1-NEXT: testl $256, %eax ## imm = 0x100 -; AVX1-NEXT: jne LBB31_17 -; AVX1-NEXT: LBB31_18: ## %else23 +; AVX1-NEXT: jne LBB31_41 +; AVX1-NEXT: LBB31_9: ## %else23 ; AVX1-NEXT: testl $512, %eax ## imm = 0x200 -; AVX1-NEXT: jne LBB31_19 -; AVX1-NEXT: LBB31_20: ## %else26 +; AVX1-NEXT: jne LBB31_42 +; AVX1-NEXT: LBB31_10: ## %else26 ; AVX1-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX1-NEXT: jne LBB31_21 -; AVX1-NEXT: LBB31_22: ## %else29 +; AVX1-NEXT: jne LBB31_43 +; AVX1-NEXT: LBB31_11: ## %else29 ; AVX1-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX1-NEXT: jne LBB31_23 -; AVX1-NEXT: LBB31_24: ## %else32 +; AVX1-NEXT: jne LBB31_44 +; AVX1-NEXT: LBB31_12: ## %else32 ; AVX1-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX1-NEXT: jne LBB31_25 -; AVX1-NEXT: LBB31_26: ## %else35 +; AVX1-NEXT: jne LBB31_45 +; AVX1-NEXT: LBB31_13: ## %else35 ; AVX1-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX1-NEXT: jne LBB31_27 -; AVX1-NEXT: LBB31_28: ## %else38 +; AVX1-NEXT: jne LBB31_46 +; AVX1-NEXT: LBB31_14: ## %else38 ; AVX1-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX1-NEXT: jne LBB31_29 -; AVX1-NEXT: LBB31_30: ## %else41 +; AVX1-NEXT: jne LBB31_47 +; AVX1-NEXT: LBB31_15: ## %else41 ; AVX1-NEXT: testw %ax, %ax -; AVX1-NEXT: js LBB31_31 -; AVX1-NEXT: LBB31_32: ## %else44 +; AVX1-NEXT: js LBB31_48 +; AVX1-NEXT: LBB31_16: ## %else44 ; AVX1-NEXT: testl $65536, %eax ## imm = 0x10000 -; AVX1-NEXT: jne LBB31_33 -; AVX1-NEXT: LBB31_34: ## %else47 +; AVX1-NEXT: jne LBB31_49 +; AVX1-NEXT: LBB31_17: ## %else47 ; AVX1-NEXT: testl $131072, %eax ## imm = 0x20000 -; AVX1-NEXT: jne LBB31_35 -; AVX1-NEXT: LBB31_36: ## %else50 +; AVX1-NEXT: jne LBB31_50 +; AVX1-NEXT: LBB31_18: ## %else50 ; AVX1-NEXT: testl $262144, %eax ## imm = 0x40000 -; AVX1-NEXT: jne LBB31_37 -; AVX1-NEXT: LBB31_38: ## %else53 +; AVX1-NEXT: jne LBB31_51 +; AVX1-NEXT: LBB31_19: ## %else53 ; AVX1-NEXT: testl $524288, %eax ## imm = 0x80000 -; AVX1-NEXT: jne LBB31_39 -; AVX1-NEXT: LBB31_40: ## %else56 +; AVX1-NEXT: jne LBB31_52 +; AVX1-NEXT: LBB31_20: ## %else56 ; AVX1-NEXT: testl $1048576, %eax ## imm = 0x100000 -; AVX1-NEXT: jne LBB31_41 -; AVX1-NEXT: LBB31_42: ## %else59 +; AVX1-NEXT: jne LBB31_53 +; AVX1-NEXT: LBB31_21: ## %else59 ; AVX1-NEXT: testl $2097152, %eax ## imm = 0x200000 -; AVX1-NEXT: jne LBB31_43 -; AVX1-NEXT: LBB31_44: ## %else62 +; AVX1-NEXT: jne LBB31_54 +; AVX1-NEXT: LBB31_22: ## %else62 ; AVX1-NEXT: testl $4194304, %eax ## imm = 0x400000 -; AVX1-NEXT: jne LBB31_45 -; AVX1-NEXT: LBB31_46: ## %else65 +; AVX1-NEXT: jne LBB31_55 +; AVX1-NEXT: LBB31_23: ## %else65 ; AVX1-NEXT: testl $8388608, %eax ## imm = 0x800000 -; AVX1-NEXT: jne LBB31_47 -; AVX1-NEXT: LBB31_48: ## %else68 +; AVX1-NEXT: jne LBB31_56 +; AVX1-NEXT: LBB31_24: ## %else68 ; AVX1-NEXT: testl $16777216, %eax ## imm = 0x1000000 -; AVX1-NEXT: jne LBB31_49 -; AVX1-NEXT: LBB31_50: ## %else71 +; AVX1-NEXT: jne LBB31_57 +; AVX1-NEXT: LBB31_25: ## %else71 ; AVX1-NEXT: testl $33554432, %eax ## imm = 0x2000000 -; AVX1-NEXT: jne LBB31_51 -; AVX1-NEXT: LBB31_52: ## %else74 +; AVX1-NEXT: jne LBB31_58 +; AVX1-NEXT: LBB31_26: ## %else74 ; AVX1-NEXT: testl $67108864, %eax ## imm = 0x4000000 -; AVX1-NEXT: jne LBB31_53 -; AVX1-NEXT: LBB31_54: ## %else77 +; AVX1-NEXT: jne LBB31_59 +; AVX1-NEXT: LBB31_27: ## %else77 ; AVX1-NEXT: testl $134217728, %eax ## imm = 0x8000000 -; AVX1-NEXT: jne LBB31_55 -; AVX1-NEXT: LBB31_56: ## %else80 +; AVX1-NEXT: jne LBB31_60 +; AVX1-NEXT: LBB31_28: ## %else80 ; AVX1-NEXT: testl $268435456, %eax ## imm = 0x10000000 -; AVX1-NEXT: jne LBB31_57 -; AVX1-NEXT: LBB31_58: ## %else83 +; AVX1-NEXT: jne LBB31_61 +; AVX1-NEXT: LBB31_29: ## %else83 ; AVX1-NEXT: testl $536870912, %eax ## imm = 0x20000000 -; AVX1-NEXT: jne LBB31_59 -; AVX1-NEXT: LBB31_60: ## %else86 +; AVX1-NEXT: jne LBB31_62 +; AVX1-NEXT: LBB31_30: ## %else86 ; AVX1-NEXT: testl $1073741824, %eax ## imm = 0x40000000 -; AVX1-NEXT: jne LBB31_61 -; AVX1-NEXT: LBB31_62: ## %else89 -; AVX1-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 ; AVX1-NEXT: jne LBB31_63 -; AVX1-NEXT: LBB31_64: ## %else92 +; AVX1-NEXT: LBB31_31: ## %else89 +; AVX1-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 +; AVX1-NEXT: jne LBB31_64 +; AVX1-NEXT: LBB31_32: ## %else92 ; AVX1-NEXT: vmovaps %ymm1, %ymm0 ; AVX1-NEXT: retq -; AVX1-NEXT: LBB31_1: ## %cond.load +; AVX1-NEXT: LBB31_33: ## %cond.load ; AVX1-NEXT: vpinsrb $0, (%rdi), %xmm1, %xmm0 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je LBB31_4 -; AVX1-NEXT: LBB31_3: ## %cond.load1 +; AVX1-NEXT: je LBB31_2 +; AVX1-NEXT: LBB31_34: ## %cond.load1 ; AVX1-NEXT: vpinsrb $1, 1(%rdi), %xmm1, %xmm0 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je LBB31_6 -; AVX1-NEXT: LBB31_5: ## %cond.load4 +; AVX1-NEXT: je LBB31_3 +; AVX1-NEXT: LBB31_35: ## %cond.load4 ; AVX1-NEXT: vpinsrb $2, 2(%rdi), %xmm1, %xmm0 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je LBB31_8 -; AVX1-NEXT: LBB31_7: ## %cond.load7 +; AVX1-NEXT: je LBB31_4 +; AVX1-NEXT: LBB31_36: ## %cond.load7 ; AVX1-NEXT: vpinsrb $3, 3(%rdi), %xmm1, %xmm0 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: je LBB31_10 -; AVX1-NEXT: LBB31_9: ## %cond.load10 +; AVX1-NEXT: je LBB31_5 +; AVX1-NEXT: LBB31_37: ## %cond.load10 ; AVX1-NEXT: vpinsrb $4, 4(%rdi), %xmm1, %xmm0 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je LBB31_12 -; AVX1-NEXT: LBB31_11: ## %cond.load13 +; AVX1-NEXT: je LBB31_6 +; AVX1-NEXT: LBB31_38: ## %cond.load13 ; AVX1-NEXT: vpinsrb $5, 5(%rdi), %xmm1, %xmm0 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: je LBB31_14 -; AVX1-NEXT: LBB31_13: ## %cond.load16 +; AVX1-NEXT: je LBB31_7 +; AVX1-NEXT: LBB31_39: ## %cond.load16 ; AVX1-NEXT: vpinsrb $6, 6(%rdi), %xmm1, %xmm0 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX1-NEXT: testb %al, %al -; AVX1-NEXT: jns LBB31_16 -; AVX1-NEXT: LBB31_15: ## %cond.load19 +; AVX1-NEXT: jns LBB31_8 +; AVX1-NEXT: LBB31_40: ## %cond.load19 ; AVX1-NEXT: vpinsrb $7, 7(%rdi), %xmm1, %xmm0 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX1-NEXT: testl $256, %eax ## imm = 0x100 -; AVX1-NEXT: je LBB31_18 -; AVX1-NEXT: LBB31_17: ## %cond.load22 +; AVX1-NEXT: je LBB31_9 +; AVX1-NEXT: LBB31_41: ## %cond.load22 ; AVX1-NEXT: vpinsrb $8, 8(%rdi), %xmm1, %xmm0 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX1-NEXT: testl $512, %eax ## imm = 0x200 -; AVX1-NEXT: je LBB31_20 -; AVX1-NEXT: LBB31_19: ## %cond.load25 +; AVX1-NEXT: je LBB31_10 +; AVX1-NEXT: LBB31_42: ## %cond.load25 ; AVX1-NEXT: vpinsrb $9, 9(%rdi), %xmm1, %xmm0 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX1-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX1-NEXT: je LBB31_22 -; AVX1-NEXT: LBB31_21: ## %cond.load28 +; AVX1-NEXT: je LBB31_11 +; AVX1-NEXT: LBB31_43: ## %cond.load28 ; AVX1-NEXT: vpinsrb $10, 10(%rdi), %xmm1, %xmm0 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX1-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX1-NEXT: je LBB31_24 -; AVX1-NEXT: LBB31_23: ## %cond.load31 +; AVX1-NEXT: je LBB31_12 +; AVX1-NEXT: LBB31_44: ## %cond.load31 ; AVX1-NEXT: vpinsrb $11, 11(%rdi), %xmm1, %xmm0 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX1-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX1-NEXT: je LBB31_26 -; AVX1-NEXT: LBB31_25: ## %cond.load34 +; AVX1-NEXT: je LBB31_13 +; AVX1-NEXT: LBB31_45: ## %cond.load34 ; AVX1-NEXT: vpinsrb $12, 12(%rdi), %xmm1, %xmm0 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX1-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX1-NEXT: je LBB31_28 -; AVX1-NEXT: LBB31_27: ## %cond.load37 +; AVX1-NEXT: je LBB31_14 +; AVX1-NEXT: LBB31_46: ## %cond.load37 ; AVX1-NEXT: vpinsrb $13, 13(%rdi), %xmm1, %xmm0 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX1-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX1-NEXT: je LBB31_30 -; AVX1-NEXT: LBB31_29: ## %cond.load40 +; AVX1-NEXT: je LBB31_15 +; AVX1-NEXT: LBB31_47: ## %cond.load40 ; AVX1-NEXT: vpinsrb $14, 14(%rdi), %xmm1, %xmm0 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX1-NEXT: testw %ax, %ax -; AVX1-NEXT: jns LBB31_32 -; AVX1-NEXT: LBB31_31: ## %cond.load43 +; AVX1-NEXT: jns LBB31_16 +; AVX1-NEXT: LBB31_48: ## %cond.load43 ; AVX1-NEXT: vpinsrb $15, 15(%rdi), %xmm1, %xmm0 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX1-NEXT: testl $65536, %eax ## imm = 0x10000 -; AVX1-NEXT: je LBB31_34 -; AVX1-NEXT: LBB31_33: ## %cond.load46 +; AVX1-NEXT: je LBB31_17 +; AVX1-NEXT: LBB31_49: ## %cond.load46 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm0 ; AVX1-NEXT: vpinsrb $0, 16(%rdi), %xmm0, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm1 ; AVX1-NEXT: testl $131072, %eax ## imm = 0x20000 -; AVX1-NEXT: je LBB31_36 -; AVX1-NEXT: LBB31_35: ## %cond.load49 +; AVX1-NEXT: je LBB31_18 +; AVX1-NEXT: LBB31_50: ## %cond.load49 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm0 ; AVX1-NEXT: vpinsrb $1, 17(%rdi), %xmm0, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm1 ; AVX1-NEXT: testl $262144, %eax ## imm = 0x40000 -; AVX1-NEXT: je LBB31_38 -; AVX1-NEXT: LBB31_37: ## %cond.load52 +; AVX1-NEXT: je LBB31_19 +; AVX1-NEXT: LBB31_51: ## %cond.load52 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm0 ; AVX1-NEXT: vpinsrb $2, 18(%rdi), %xmm0, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm1 ; AVX1-NEXT: testl $524288, %eax ## imm = 0x80000 -; AVX1-NEXT: je LBB31_40 -; AVX1-NEXT: LBB31_39: ## %cond.load55 +; AVX1-NEXT: je LBB31_20 +; AVX1-NEXT: LBB31_52: ## %cond.load55 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm0 ; AVX1-NEXT: vpinsrb $3, 19(%rdi), %xmm0, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm1 ; AVX1-NEXT: testl $1048576, %eax ## imm = 0x100000 -; AVX1-NEXT: je LBB31_42 -; AVX1-NEXT: LBB31_41: ## %cond.load58 +; AVX1-NEXT: je LBB31_21 +; AVX1-NEXT: LBB31_53: ## %cond.load58 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm0 ; AVX1-NEXT: vpinsrb $4, 20(%rdi), %xmm0, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm1 ; AVX1-NEXT: testl $2097152, %eax ## imm = 0x200000 -; AVX1-NEXT: je LBB31_44 -; AVX1-NEXT: LBB31_43: ## %cond.load61 +; AVX1-NEXT: je LBB31_22 +; AVX1-NEXT: LBB31_54: ## %cond.load61 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm0 ; AVX1-NEXT: vpinsrb $5, 21(%rdi), %xmm0, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm1 ; AVX1-NEXT: testl $4194304, %eax ## imm = 0x400000 -; AVX1-NEXT: je LBB31_46 -; AVX1-NEXT: LBB31_45: ## %cond.load64 +; AVX1-NEXT: je LBB31_23 +; AVX1-NEXT: LBB31_55: ## %cond.load64 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm0 ; AVX1-NEXT: vpinsrb $6, 22(%rdi), %xmm0, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm1 ; AVX1-NEXT: testl $8388608, %eax ## imm = 0x800000 -; AVX1-NEXT: je LBB31_48 -; AVX1-NEXT: LBB31_47: ## %cond.load67 +; AVX1-NEXT: je LBB31_24 +; AVX1-NEXT: LBB31_56: ## %cond.load67 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm0 ; AVX1-NEXT: vpinsrb $7, 23(%rdi), %xmm0, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm1 ; AVX1-NEXT: testl $16777216, %eax ## imm = 0x1000000 -; AVX1-NEXT: je LBB31_50 -; AVX1-NEXT: LBB31_49: ## %cond.load70 +; AVX1-NEXT: je LBB31_25 +; AVX1-NEXT: LBB31_57: ## %cond.load70 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm0 ; AVX1-NEXT: vpinsrb $8, 24(%rdi), %xmm0, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm1 ; AVX1-NEXT: testl $33554432, %eax ## imm = 0x2000000 -; AVX1-NEXT: je LBB31_52 -; AVX1-NEXT: LBB31_51: ## %cond.load73 +; AVX1-NEXT: je LBB31_26 +; AVX1-NEXT: LBB31_58: ## %cond.load73 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm0 ; AVX1-NEXT: vpinsrb $9, 25(%rdi), %xmm0, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm1 ; AVX1-NEXT: testl $67108864, %eax ## imm = 0x4000000 -; AVX1-NEXT: je LBB31_54 -; AVX1-NEXT: LBB31_53: ## %cond.load76 +; AVX1-NEXT: je LBB31_27 +; AVX1-NEXT: LBB31_59: ## %cond.load76 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm0 ; AVX1-NEXT: vpinsrb $10, 26(%rdi), %xmm0, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm1 ; AVX1-NEXT: testl $134217728, %eax ## imm = 0x8000000 -; AVX1-NEXT: je LBB31_56 -; AVX1-NEXT: LBB31_55: ## %cond.load79 +; AVX1-NEXT: je LBB31_28 +; AVX1-NEXT: LBB31_60: ## %cond.load79 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm0 ; AVX1-NEXT: vpinsrb $11, 27(%rdi), %xmm0, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm1 ; AVX1-NEXT: testl $268435456, %eax ## imm = 0x10000000 -; AVX1-NEXT: je LBB31_58 -; AVX1-NEXT: LBB31_57: ## %cond.load82 +; AVX1-NEXT: je LBB31_29 +; AVX1-NEXT: LBB31_61: ## %cond.load82 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm0 ; AVX1-NEXT: vpinsrb $12, 28(%rdi), %xmm0, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm1 ; AVX1-NEXT: testl $536870912, %eax ## imm = 0x20000000 -; AVX1-NEXT: je LBB31_60 -; AVX1-NEXT: LBB31_59: ## %cond.load85 +; AVX1-NEXT: je LBB31_30 +; AVX1-NEXT: LBB31_62: ## %cond.load85 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm0 ; AVX1-NEXT: vpinsrb $13, 29(%rdi), %xmm0, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm1 ; AVX1-NEXT: testl $1073741824, %eax ## imm = 0x40000000 -; AVX1-NEXT: je LBB31_62 -; AVX1-NEXT: LBB31_61: ## %cond.load88 +; AVX1-NEXT: je LBB31_31 +; AVX1-NEXT: LBB31_63: ## %cond.load88 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm0 ; AVX1-NEXT: vpinsrb $14, 30(%rdi), %xmm0, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm1 ; AVX1-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 -; AVX1-NEXT: je LBB31_64 -; AVX1-NEXT: LBB31_63: ## %cond.load91 +; AVX1-NEXT: je LBB31_32 +; AVX1-NEXT: LBB31_64: ## %cond.load91 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm0 ; AVX1-NEXT: vpinsrb $15, 31(%rdi), %xmm0, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm1 @@ -6248,274 +6248,274 @@ define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %dst ; AVX2: ## %bb.0: ; AVX2-NEXT: vpmovmskb %ymm0, %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne LBB31_1 -; AVX2-NEXT: ## %bb.2: ## %else +; AVX2-NEXT: jne LBB31_33 +; AVX2-NEXT: ## %bb.1: ## %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne LBB31_3 -; AVX2-NEXT: LBB31_4: ## %else2 +; AVX2-NEXT: jne LBB31_34 +; AVX2-NEXT: LBB31_2: ## %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne LBB31_5 -; AVX2-NEXT: LBB31_6: ## %else5 +; AVX2-NEXT: jne LBB31_35 +; AVX2-NEXT: LBB31_3: ## %else5 ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: jne LBB31_7 -; AVX2-NEXT: LBB31_8: ## %else8 +; AVX2-NEXT: jne LBB31_36 +; AVX2-NEXT: LBB31_4: ## %else8 ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: jne LBB31_9 -; AVX2-NEXT: LBB31_10: ## %else11 +; AVX2-NEXT: jne LBB31_37 +; AVX2-NEXT: LBB31_5: ## %else11 ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: jne LBB31_11 -; AVX2-NEXT: LBB31_12: ## %else14 +; AVX2-NEXT: jne LBB31_38 +; AVX2-NEXT: LBB31_6: ## %else14 ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: jne LBB31_13 -; AVX2-NEXT: LBB31_14: ## %else17 +; AVX2-NEXT: jne LBB31_39 +; AVX2-NEXT: LBB31_7: ## %else17 ; AVX2-NEXT: testb %al, %al -; AVX2-NEXT: js LBB31_15 -; AVX2-NEXT: LBB31_16: ## %else20 +; AVX2-NEXT: js LBB31_40 +; AVX2-NEXT: LBB31_8: ## %else20 ; AVX2-NEXT: testl $256, %eax ## imm = 0x100 -; AVX2-NEXT: jne LBB31_17 -; AVX2-NEXT: LBB31_18: ## %else23 +; AVX2-NEXT: jne LBB31_41 +; AVX2-NEXT: LBB31_9: ## %else23 ; AVX2-NEXT: testl $512, %eax ## imm = 0x200 -; AVX2-NEXT: jne LBB31_19 -; AVX2-NEXT: LBB31_20: ## %else26 +; AVX2-NEXT: jne LBB31_42 +; AVX2-NEXT: LBB31_10: ## %else26 ; AVX2-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX2-NEXT: jne LBB31_21 -; AVX2-NEXT: LBB31_22: ## %else29 +; AVX2-NEXT: jne LBB31_43 +; AVX2-NEXT: LBB31_11: ## %else29 ; AVX2-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX2-NEXT: jne LBB31_23 -; AVX2-NEXT: LBB31_24: ## %else32 +; AVX2-NEXT: jne LBB31_44 +; AVX2-NEXT: LBB31_12: ## %else32 ; AVX2-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX2-NEXT: jne LBB31_25 -; AVX2-NEXT: LBB31_26: ## %else35 +; AVX2-NEXT: jne LBB31_45 +; AVX2-NEXT: LBB31_13: ## %else35 ; AVX2-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX2-NEXT: jne LBB31_27 -; AVX2-NEXT: LBB31_28: ## %else38 +; AVX2-NEXT: jne LBB31_46 +; AVX2-NEXT: LBB31_14: ## %else38 ; AVX2-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX2-NEXT: jne LBB31_29 -; AVX2-NEXT: LBB31_30: ## %else41 +; AVX2-NEXT: jne LBB31_47 +; AVX2-NEXT: LBB31_15: ## %else41 ; AVX2-NEXT: testw %ax, %ax -; AVX2-NEXT: js LBB31_31 -; AVX2-NEXT: LBB31_32: ## %else44 +; AVX2-NEXT: js LBB31_48 +; AVX2-NEXT: LBB31_16: ## %else44 ; AVX2-NEXT: testl $65536, %eax ## imm = 0x10000 -; AVX2-NEXT: jne LBB31_33 -; AVX2-NEXT: LBB31_34: ## %else47 +; AVX2-NEXT: jne LBB31_49 +; AVX2-NEXT: LBB31_17: ## %else47 ; AVX2-NEXT: testl $131072, %eax ## imm = 0x20000 -; AVX2-NEXT: jne LBB31_35 -; AVX2-NEXT: LBB31_36: ## %else50 +; AVX2-NEXT: jne LBB31_50 +; AVX2-NEXT: LBB31_18: ## %else50 ; AVX2-NEXT: testl $262144, %eax ## imm = 0x40000 -; AVX2-NEXT: jne LBB31_37 -; AVX2-NEXT: LBB31_38: ## %else53 +; AVX2-NEXT: jne LBB31_51 +; AVX2-NEXT: LBB31_19: ## %else53 ; AVX2-NEXT: testl $524288, %eax ## imm = 0x80000 -; AVX2-NEXT: jne LBB31_39 -; AVX2-NEXT: LBB31_40: ## %else56 +; AVX2-NEXT: jne LBB31_52 +; AVX2-NEXT: LBB31_20: ## %else56 ; AVX2-NEXT: testl $1048576, %eax ## imm = 0x100000 -; AVX2-NEXT: jne LBB31_41 -; AVX2-NEXT: LBB31_42: ## %else59 +; AVX2-NEXT: jne LBB31_53 +; AVX2-NEXT: LBB31_21: ## %else59 ; AVX2-NEXT: testl $2097152, %eax ## imm = 0x200000 -; AVX2-NEXT: jne LBB31_43 -; AVX2-NEXT: LBB31_44: ## %else62 +; AVX2-NEXT: jne LBB31_54 +; AVX2-NEXT: LBB31_22: ## %else62 ; AVX2-NEXT: testl $4194304, %eax ## imm = 0x400000 -; AVX2-NEXT: jne LBB31_45 -; AVX2-NEXT: LBB31_46: ## %else65 +; AVX2-NEXT: jne LBB31_55 +; AVX2-NEXT: LBB31_23: ## %else65 ; AVX2-NEXT: testl $8388608, %eax ## imm = 0x800000 -; AVX2-NEXT: jne LBB31_47 -; AVX2-NEXT: LBB31_48: ## %else68 +; AVX2-NEXT: jne LBB31_56 +; AVX2-NEXT: LBB31_24: ## %else68 ; AVX2-NEXT: testl $16777216, %eax ## imm = 0x1000000 -; AVX2-NEXT: jne LBB31_49 -; AVX2-NEXT: LBB31_50: ## %else71 +; AVX2-NEXT: jne LBB31_57 +; AVX2-NEXT: LBB31_25: ## %else71 ; AVX2-NEXT: testl $33554432, %eax ## imm = 0x2000000 -; AVX2-NEXT: jne LBB31_51 -; AVX2-NEXT: LBB31_52: ## %else74 +; AVX2-NEXT: jne LBB31_58 +; AVX2-NEXT: LBB31_26: ## %else74 ; AVX2-NEXT: testl $67108864, %eax ## imm = 0x4000000 -; AVX2-NEXT: jne LBB31_53 -; AVX2-NEXT: LBB31_54: ## %else77 +; AVX2-NEXT: jne LBB31_59 +; AVX2-NEXT: LBB31_27: ## %else77 ; AVX2-NEXT: testl $134217728, %eax ## imm = 0x8000000 -; AVX2-NEXT: jne LBB31_55 -; AVX2-NEXT: LBB31_56: ## %else80 +; AVX2-NEXT: jne LBB31_60 +; AVX2-NEXT: LBB31_28: ## %else80 ; AVX2-NEXT: testl $268435456, %eax ## imm = 0x10000000 -; AVX2-NEXT: jne LBB31_57 -; AVX2-NEXT: LBB31_58: ## %else83 +; AVX2-NEXT: jne LBB31_61 +; AVX2-NEXT: LBB31_29: ## %else83 ; AVX2-NEXT: testl $536870912, %eax ## imm = 0x20000000 -; AVX2-NEXT: jne LBB31_59 -; AVX2-NEXT: LBB31_60: ## %else86 +; AVX2-NEXT: jne LBB31_62 +; AVX2-NEXT: LBB31_30: ## %else86 ; AVX2-NEXT: testl $1073741824, %eax ## imm = 0x40000000 -; AVX2-NEXT: jne LBB31_61 -; AVX2-NEXT: LBB31_62: ## %else89 -; AVX2-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 ; AVX2-NEXT: jne LBB31_63 -; AVX2-NEXT: LBB31_64: ## %else92 +; AVX2-NEXT: LBB31_31: ## %else89 +; AVX2-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 +; AVX2-NEXT: jne LBB31_64 +; AVX2-NEXT: LBB31_32: ## %else92 ; AVX2-NEXT: vmovdqa %ymm1, %ymm0 ; AVX2-NEXT: retq -; AVX2-NEXT: LBB31_1: ## %cond.load +; AVX2-NEXT: LBB31_33: ## %cond.load ; AVX2-NEXT: vpinsrb $0, (%rdi), %xmm1, %xmm0 ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je LBB31_4 -; AVX2-NEXT: LBB31_3: ## %cond.load1 +; AVX2-NEXT: je LBB31_2 +; AVX2-NEXT: LBB31_34: ## %cond.load1 ; AVX2-NEXT: vpinsrb $1, 1(%rdi), %xmm1, %xmm0 ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je LBB31_6 -; AVX2-NEXT: LBB31_5: ## %cond.load4 +; AVX2-NEXT: je LBB31_3 +; AVX2-NEXT: LBB31_35: ## %cond.load4 ; AVX2-NEXT: vpinsrb $2, 2(%rdi), %xmm1, %xmm0 ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je LBB31_8 -; AVX2-NEXT: LBB31_7: ## %cond.load7 +; AVX2-NEXT: je LBB31_4 +; AVX2-NEXT: LBB31_36: ## %cond.load7 ; AVX2-NEXT: vpinsrb $3, 3(%rdi), %xmm1, %xmm0 ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: je LBB31_10 -; AVX2-NEXT: LBB31_9: ## %cond.load10 +; AVX2-NEXT: je LBB31_5 +; AVX2-NEXT: LBB31_37: ## %cond.load10 ; AVX2-NEXT: vpinsrb $4, 4(%rdi), %xmm1, %xmm0 ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: je LBB31_12 -; AVX2-NEXT: LBB31_11: ## %cond.load13 +; AVX2-NEXT: je LBB31_6 +; AVX2-NEXT: LBB31_38: ## %cond.load13 ; AVX2-NEXT: vpinsrb $5, 5(%rdi), %xmm1, %xmm0 ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: je LBB31_14 -; AVX2-NEXT: LBB31_13: ## %cond.load16 +; AVX2-NEXT: je LBB31_7 +; AVX2-NEXT: LBB31_39: ## %cond.load16 ; AVX2-NEXT: vpinsrb $6, 6(%rdi), %xmm1, %xmm0 ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX2-NEXT: testb %al, %al -; AVX2-NEXT: jns LBB31_16 -; AVX2-NEXT: LBB31_15: ## %cond.load19 +; AVX2-NEXT: jns LBB31_8 +; AVX2-NEXT: LBB31_40: ## %cond.load19 ; AVX2-NEXT: vpinsrb $7, 7(%rdi), %xmm1, %xmm0 ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX2-NEXT: testl $256, %eax ## imm = 0x100 -; AVX2-NEXT: je LBB31_18 -; AVX2-NEXT: LBB31_17: ## %cond.load22 +; AVX2-NEXT: je LBB31_9 +; AVX2-NEXT: LBB31_41: ## %cond.load22 ; AVX2-NEXT: vpinsrb $8, 8(%rdi), %xmm1, %xmm0 ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX2-NEXT: testl $512, %eax ## imm = 0x200 -; AVX2-NEXT: je LBB31_20 -; AVX2-NEXT: LBB31_19: ## %cond.load25 +; AVX2-NEXT: je LBB31_10 +; AVX2-NEXT: LBB31_42: ## %cond.load25 ; AVX2-NEXT: vpinsrb $9, 9(%rdi), %xmm1, %xmm0 ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX2-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX2-NEXT: je LBB31_22 -; AVX2-NEXT: LBB31_21: ## %cond.load28 +; AVX2-NEXT: je LBB31_11 +; AVX2-NEXT: LBB31_43: ## %cond.load28 ; AVX2-NEXT: vpinsrb $10, 10(%rdi), %xmm1, %xmm0 ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX2-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX2-NEXT: je LBB31_24 -; AVX2-NEXT: LBB31_23: ## %cond.load31 +; AVX2-NEXT: je LBB31_12 +; AVX2-NEXT: LBB31_44: ## %cond.load31 ; AVX2-NEXT: vpinsrb $11, 11(%rdi), %xmm1, %xmm0 ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX2-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX2-NEXT: je LBB31_26 -; AVX2-NEXT: LBB31_25: ## %cond.load34 +; AVX2-NEXT: je LBB31_13 +; AVX2-NEXT: LBB31_45: ## %cond.load34 ; AVX2-NEXT: vpinsrb $12, 12(%rdi), %xmm1, %xmm0 ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX2-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX2-NEXT: je LBB31_28 -; AVX2-NEXT: LBB31_27: ## %cond.load37 +; AVX2-NEXT: je LBB31_14 +; AVX2-NEXT: LBB31_46: ## %cond.load37 ; AVX2-NEXT: vpinsrb $13, 13(%rdi), %xmm1, %xmm0 ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX2-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX2-NEXT: je LBB31_30 -; AVX2-NEXT: LBB31_29: ## %cond.load40 +; AVX2-NEXT: je LBB31_15 +; AVX2-NEXT: LBB31_47: ## %cond.load40 ; AVX2-NEXT: vpinsrb $14, 14(%rdi), %xmm1, %xmm0 ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX2-NEXT: testw %ax, %ax -; AVX2-NEXT: jns LBB31_32 -; AVX2-NEXT: LBB31_31: ## %cond.load43 +; AVX2-NEXT: jns LBB31_16 +; AVX2-NEXT: LBB31_48: ## %cond.load43 ; AVX2-NEXT: vpinsrb $15, 15(%rdi), %xmm1, %xmm0 ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX2-NEXT: testl $65536, %eax ## imm = 0x10000 -; AVX2-NEXT: je LBB31_34 -; AVX2-NEXT: LBB31_33: ## %cond.load46 +; AVX2-NEXT: je LBB31_17 +; AVX2-NEXT: LBB31_49: ## %cond.load46 ; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX2-NEXT: vpinsrb $0, 16(%rdi), %xmm0, %xmm0 ; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX2-NEXT: testl $131072, %eax ## imm = 0x20000 -; AVX2-NEXT: je LBB31_36 -; AVX2-NEXT: LBB31_35: ## %cond.load49 +; AVX2-NEXT: je LBB31_18 +; AVX2-NEXT: LBB31_50: ## %cond.load49 ; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX2-NEXT: vpinsrb $1, 17(%rdi), %xmm0, %xmm0 ; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX2-NEXT: testl $262144, %eax ## imm = 0x40000 -; AVX2-NEXT: je LBB31_38 -; AVX2-NEXT: LBB31_37: ## %cond.load52 +; AVX2-NEXT: je LBB31_19 +; AVX2-NEXT: LBB31_51: ## %cond.load52 ; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX2-NEXT: vpinsrb $2, 18(%rdi), %xmm0, %xmm0 ; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX2-NEXT: testl $524288, %eax ## imm = 0x80000 -; AVX2-NEXT: je LBB31_40 -; AVX2-NEXT: LBB31_39: ## %cond.load55 +; AVX2-NEXT: je LBB31_20 +; AVX2-NEXT: LBB31_52: ## %cond.load55 ; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX2-NEXT: vpinsrb $3, 19(%rdi), %xmm0, %xmm0 ; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX2-NEXT: testl $1048576, %eax ## imm = 0x100000 -; AVX2-NEXT: je LBB31_42 -; AVX2-NEXT: LBB31_41: ## %cond.load58 +; AVX2-NEXT: je LBB31_21 +; AVX2-NEXT: LBB31_53: ## %cond.load58 ; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX2-NEXT: vpinsrb $4, 20(%rdi), %xmm0, %xmm0 ; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX2-NEXT: testl $2097152, %eax ## imm = 0x200000 -; AVX2-NEXT: je LBB31_44 -; AVX2-NEXT: LBB31_43: ## %cond.load61 +; AVX2-NEXT: je LBB31_22 +; AVX2-NEXT: LBB31_54: ## %cond.load61 ; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX2-NEXT: vpinsrb $5, 21(%rdi), %xmm0, %xmm0 ; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX2-NEXT: testl $4194304, %eax ## imm = 0x400000 -; AVX2-NEXT: je LBB31_46 -; AVX2-NEXT: LBB31_45: ## %cond.load64 +; AVX2-NEXT: je LBB31_23 +; AVX2-NEXT: LBB31_55: ## %cond.load64 ; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX2-NEXT: vpinsrb $6, 22(%rdi), %xmm0, %xmm0 ; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX2-NEXT: testl $8388608, %eax ## imm = 0x800000 -; AVX2-NEXT: je LBB31_48 -; AVX2-NEXT: LBB31_47: ## %cond.load67 +; AVX2-NEXT: je LBB31_24 +; AVX2-NEXT: LBB31_56: ## %cond.load67 ; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX2-NEXT: vpinsrb $7, 23(%rdi), %xmm0, %xmm0 ; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX2-NEXT: testl $16777216, %eax ## imm = 0x1000000 -; AVX2-NEXT: je LBB31_50 -; AVX2-NEXT: LBB31_49: ## %cond.load70 +; AVX2-NEXT: je LBB31_25 +; AVX2-NEXT: LBB31_57: ## %cond.load70 ; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX2-NEXT: vpinsrb $8, 24(%rdi), %xmm0, %xmm0 ; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX2-NEXT: testl $33554432, %eax ## imm = 0x2000000 -; AVX2-NEXT: je LBB31_52 -; AVX2-NEXT: LBB31_51: ## %cond.load73 +; AVX2-NEXT: je LBB31_26 +; AVX2-NEXT: LBB31_58: ## %cond.load73 ; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX2-NEXT: vpinsrb $9, 25(%rdi), %xmm0, %xmm0 ; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX2-NEXT: testl $67108864, %eax ## imm = 0x4000000 -; AVX2-NEXT: je LBB31_54 -; AVX2-NEXT: LBB31_53: ## %cond.load76 +; AVX2-NEXT: je LBB31_27 +; AVX2-NEXT: LBB31_59: ## %cond.load76 ; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX2-NEXT: vpinsrb $10, 26(%rdi), %xmm0, %xmm0 ; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX2-NEXT: testl $134217728, %eax ## imm = 0x8000000 -; AVX2-NEXT: je LBB31_56 -; AVX2-NEXT: LBB31_55: ## %cond.load79 +; AVX2-NEXT: je LBB31_28 +; AVX2-NEXT: LBB31_60: ## %cond.load79 ; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX2-NEXT: vpinsrb $11, 27(%rdi), %xmm0, %xmm0 ; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX2-NEXT: testl $268435456, %eax ## imm = 0x10000000 -; AVX2-NEXT: je LBB31_58 -; AVX2-NEXT: LBB31_57: ## %cond.load82 +; AVX2-NEXT: je LBB31_29 +; AVX2-NEXT: LBB31_61: ## %cond.load82 ; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX2-NEXT: vpinsrb $12, 28(%rdi), %xmm0, %xmm0 ; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX2-NEXT: testl $536870912, %eax ## imm = 0x20000000 -; AVX2-NEXT: je LBB31_60 -; AVX2-NEXT: LBB31_59: ## %cond.load85 +; AVX2-NEXT: je LBB31_30 +; AVX2-NEXT: LBB31_62: ## %cond.load85 ; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX2-NEXT: vpinsrb $13, 29(%rdi), %xmm0, %xmm0 ; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX2-NEXT: testl $1073741824, %eax ## imm = 0x40000000 -; AVX2-NEXT: je LBB31_62 -; AVX2-NEXT: LBB31_61: ## %cond.load88 +; AVX2-NEXT: je LBB31_31 +; AVX2-NEXT: LBB31_63: ## %cond.load88 ; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX2-NEXT: vpinsrb $14, 30(%rdi), %xmm0, %xmm0 ; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX2-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 -; AVX2-NEXT: je LBB31_64 -; AVX2-NEXT: LBB31_63: ## %cond.load91 +; AVX2-NEXT: je LBB31_32 +; AVX2-NEXT: LBB31_64: ## %cond.load91 ; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX2-NEXT: vpinsrb $15, 31(%rdi), %xmm0, %xmm0 ; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 @@ -6526,274 +6526,274 @@ define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %dst ; AVX512F: ## %bb.0: ; AVX512F-NEXT: vpmovmskb %ymm0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne LBB31_1 -; AVX512F-NEXT: ## %bb.2: ## %else +; AVX512F-NEXT: jne LBB31_33 +; AVX512F-NEXT: ## %bb.1: ## %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne LBB31_3 -; AVX512F-NEXT: LBB31_4: ## %else2 +; AVX512F-NEXT: jne LBB31_34 +; AVX512F-NEXT: LBB31_2: ## %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne LBB31_5 -; AVX512F-NEXT: LBB31_6: ## %else5 +; AVX512F-NEXT: jne LBB31_35 +; AVX512F-NEXT: LBB31_3: ## %else5 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne LBB31_7 -; AVX512F-NEXT: LBB31_8: ## %else8 +; AVX512F-NEXT: jne LBB31_36 +; AVX512F-NEXT: LBB31_4: ## %else8 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne LBB31_9 -; AVX512F-NEXT: LBB31_10: ## %else11 +; AVX512F-NEXT: jne LBB31_37 +; AVX512F-NEXT: LBB31_5: ## %else11 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne LBB31_11 -; AVX512F-NEXT: LBB31_12: ## %else14 +; AVX512F-NEXT: jne LBB31_38 +; AVX512F-NEXT: LBB31_6: ## %else14 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne LBB31_13 -; AVX512F-NEXT: LBB31_14: ## %else17 +; AVX512F-NEXT: jne LBB31_39 +; AVX512F-NEXT: LBB31_7: ## %else17 ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: js LBB31_15 -; AVX512F-NEXT: LBB31_16: ## %else20 +; AVX512F-NEXT: js LBB31_40 +; AVX512F-NEXT: LBB31_8: ## %else20 ; AVX512F-NEXT: testl $256, %eax ## imm = 0x100 -; AVX512F-NEXT: jne LBB31_17 -; AVX512F-NEXT: LBB31_18: ## %else23 +; AVX512F-NEXT: jne LBB31_41 +; AVX512F-NEXT: LBB31_9: ## %else23 ; AVX512F-NEXT: testl $512, %eax ## imm = 0x200 -; AVX512F-NEXT: jne LBB31_19 -; AVX512F-NEXT: LBB31_20: ## %else26 +; AVX512F-NEXT: jne LBB31_42 +; AVX512F-NEXT: LBB31_10: ## %else26 ; AVX512F-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX512F-NEXT: jne LBB31_21 -; AVX512F-NEXT: LBB31_22: ## %else29 +; AVX512F-NEXT: jne LBB31_43 +; AVX512F-NEXT: LBB31_11: ## %else29 ; AVX512F-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX512F-NEXT: jne LBB31_23 -; AVX512F-NEXT: LBB31_24: ## %else32 +; AVX512F-NEXT: jne LBB31_44 +; AVX512F-NEXT: LBB31_12: ## %else32 ; AVX512F-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX512F-NEXT: jne LBB31_25 -; AVX512F-NEXT: LBB31_26: ## %else35 +; AVX512F-NEXT: jne LBB31_45 +; AVX512F-NEXT: LBB31_13: ## %else35 ; AVX512F-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX512F-NEXT: jne LBB31_27 -; AVX512F-NEXT: LBB31_28: ## %else38 +; AVX512F-NEXT: jne LBB31_46 +; AVX512F-NEXT: LBB31_14: ## %else38 ; AVX512F-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX512F-NEXT: jne LBB31_29 -; AVX512F-NEXT: LBB31_30: ## %else41 +; AVX512F-NEXT: jne LBB31_47 +; AVX512F-NEXT: LBB31_15: ## %else41 ; AVX512F-NEXT: testw %ax, %ax -; AVX512F-NEXT: js LBB31_31 -; AVX512F-NEXT: LBB31_32: ## %else44 +; AVX512F-NEXT: js LBB31_48 +; AVX512F-NEXT: LBB31_16: ## %else44 ; AVX512F-NEXT: testl $65536, %eax ## imm = 0x10000 -; AVX512F-NEXT: jne LBB31_33 -; AVX512F-NEXT: LBB31_34: ## %else47 +; AVX512F-NEXT: jne LBB31_49 +; AVX512F-NEXT: LBB31_17: ## %else47 ; AVX512F-NEXT: testl $131072, %eax ## imm = 0x20000 -; AVX512F-NEXT: jne LBB31_35 -; AVX512F-NEXT: LBB31_36: ## %else50 +; AVX512F-NEXT: jne LBB31_50 +; AVX512F-NEXT: LBB31_18: ## %else50 ; AVX512F-NEXT: testl $262144, %eax ## imm = 0x40000 -; AVX512F-NEXT: jne LBB31_37 -; AVX512F-NEXT: LBB31_38: ## %else53 +; AVX512F-NEXT: jne LBB31_51 +; AVX512F-NEXT: LBB31_19: ## %else53 ; AVX512F-NEXT: testl $524288, %eax ## imm = 0x80000 -; AVX512F-NEXT: jne LBB31_39 -; AVX512F-NEXT: LBB31_40: ## %else56 +; AVX512F-NEXT: jne LBB31_52 +; AVX512F-NEXT: LBB31_20: ## %else56 ; AVX512F-NEXT: testl $1048576, %eax ## imm = 0x100000 -; AVX512F-NEXT: jne LBB31_41 -; AVX512F-NEXT: LBB31_42: ## %else59 +; AVX512F-NEXT: jne LBB31_53 +; AVX512F-NEXT: LBB31_21: ## %else59 ; AVX512F-NEXT: testl $2097152, %eax ## imm = 0x200000 -; AVX512F-NEXT: jne LBB31_43 -; AVX512F-NEXT: LBB31_44: ## %else62 +; AVX512F-NEXT: jne LBB31_54 +; AVX512F-NEXT: LBB31_22: ## %else62 ; AVX512F-NEXT: testl $4194304, %eax ## imm = 0x400000 -; AVX512F-NEXT: jne LBB31_45 -; AVX512F-NEXT: LBB31_46: ## %else65 +; AVX512F-NEXT: jne LBB31_55 +; AVX512F-NEXT: LBB31_23: ## %else65 ; AVX512F-NEXT: testl $8388608, %eax ## imm = 0x800000 -; AVX512F-NEXT: jne LBB31_47 -; AVX512F-NEXT: LBB31_48: ## %else68 +; AVX512F-NEXT: jne LBB31_56 +; AVX512F-NEXT: LBB31_24: ## %else68 ; AVX512F-NEXT: testl $16777216, %eax ## imm = 0x1000000 -; AVX512F-NEXT: jne LBB31_49 -; AVX512F-NEXT: LBB31_50: ## %else71 +; AVX512F-NEXT: jne LBB31_57 +; AVX512F-NEXT: LBB31_25: ## %else71 ; AVX512F-NEXT: testl $33554432, %eax ## imm = 0x2000000 -; AVX512F-NEXT: jne LBB31_51 -; AVX512F-NEXT: LBB31_52: ## %else74 +; AVX512F-NEXT: jne LBB31_58 +; AVX512F-NEXT: LBB31_26: ## %else74 ; AVX512F-NEXT: testl $67108864, %eax ## imm = 0x4000000 -; AVX512F-NEXT: jne LBB31_53 -; AVX512F-NEXT: LBB31_54: ## %else77 +; AVX512F-NEXT: jne LBB31_59 +; AVX512F-NEXT: LBB31_27: ## %else77 ; AVX512F-NEXT: testl $134217728, %eax ## imm = 0x8000000 -; AVX512F-NEXT: jne LBB31_55 -; AVX512F-NEXT: LBB31_56: ## %else80 +; AVX512F-NEXT: jne LBB31_60 +; AVX512F-NEXT: LBB31_28: ## %else80 ; AVX512F-NEXT: testl $268435456, %eax ## imm = 0x10000000 -; AVX512F-NEXT: jne LBB31_57 -; AVX512F-NEXT: LBB31_58: ## %else83 +; AVX512F-NEXT: jne LBB31_61 +; AVX512F-NEXT: LBB31_29: ## %else83 ; AVX512F-NEXT: testl $536870912, %eax ## imm = 0x20000000 -; AVX512F-NEXT: jne LBB31_59 -; AVX512F-NEXT: LBB31_60: ## %else86 +; AVX512F-NEXT: jne LBB31_62 +; AVX512F-NEXT: LBB31_30: ## %else86 ; AVX512F-NEXT: testl $1073741824, %eax ## imm = 0x40000000 -; AVX512F-NEXT: jne LBB31_61 -; AVX512F-NEXT: LBB31_62: ## %else89 -; AVX512F-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 ; AVX512F-NEXT: jne LBB31_63 -; AVX512F-NEXT: LBB31_64: ## %else92 +; AVX512F-NEXT: LBB31_31: ## %else89 +; AVX512F-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 +; AVX512F-NEXT: jne LBB31_64 +; AVX512F-NEXT: LBB31_32: ## %else92 ; AVX512F-NEXT: vmovdqa %ymm1, %ymm0 ; AVX512F-NEXT: retq -; AVX512F-NEXT: LBB31_1: ## %cond.load +; AVX512F-NEXT: LBB31_33: ## %cond.load ; AVX512F-NEXT: vpinsrb $0, (%rdi), %xmm1, %xmm0 ; AVX512F-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je LBB31_4 -; AVX512F-NEXT: LBB31_3: ## %cond.load1 +; AVX512F-NEXT: je LBB31_2 +; AVX512F-NEXT: LBB31_34: ## %cond.load1 ; AVX512F-NEXT: vpinsrb $1, 1(%rdi), %xmm1, %xmm0 ; AVX512F-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je LBB31_6 -; AVX512F-NEXT: LBB31_5: ## %cond.load4 +; AVX512F-NEXT: je LBB31_3 +; AVX512F-NEXT: LBB31_35: ## %cond.load4 ; AVX512F-NEXT: vpinsrb $2, 2(%rdi), %xmm1, %xmm0 ; AVX512F-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je LBB31_8 -; AVX512F-NEXT: LBB31_7: ## %cond.load7 +; AVX512F-NEXT: je LBB31_4 +; AVX512F-NEXT: LBB31_36: ## %cond.load7 ; AVX512F-NEXT: vpinsrb $3, 3(%rdi), %xmm1, %xmm0 ; AVX512F-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je LBB31_10 -; AVX512F-NEXT: LBB31_9: ## %cond.load10 +; AVX512F-NEXT: je LBB31_5 +; AVX512F-NEXT: LBB31_37: ## %cond.load10 ; AVX512F-NEXT: vpinsrb $4, 4(%rdi), %xmm1, %xmm0 ; AVX512F-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je LBB31_12 -; AVX512F-NEXT: LBB31_11: ## %cond.load13 +; AVX512F-NEXT: je LBB31_6 +; AVX512F-NEXT: LBB31_38: ## %cond.load13 ; AVX512F-NEXT: vpinsrb $5, 5(%rdi), %xmm1, %xmm0 ; AVX512F-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je LBB31_14 -; AVX512F-NEXT: LBB31_13: ## %cond.load16 +; AVX512F-NEXT: je LBB31_7 +; AVX512F-NEXT: LBB31_39: ## %cond.load16 ; AVX512F-NEXT: vpinsrb $6, 6(%rdi), %xmm1, %xmm0 ; AVX512F-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: jns LBB31_16 -; AVX512F-NEXT: LBB31_15: ## %cond.load19 +; AVX512F-NEXT: jns LBB31_8 +; AVX512F-NEXT: LBB31_40: ## %cond.load19 ; AVX512F-NEXT: vpinsrb $7, 7(%rdi), %xmm1, %xmm0 ; AVX512F-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512F-NEXT: testl $256, %eax ## imm = 0x100 -; AVX512F-NEXT: je LBB31_18 -; AVX512F-NEXT: LBB31_17: ## %cond.load22 +; AVX512F-NEXT: je LBB31_9 +; AVX512F-NEXT: LBB31_41: ## %cond.load22 ; AVX512F-NEXT: vpinsrb $8, 8(%rdi), %xmm1, %xmm0 ; AVX512F-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512F-NEXT: testl $512, %eax ## imm = 0x200 -; AVX512F-NEXT: je LBB31_20 -; AVX512F-NEXT: LBB31_19: ## %cond.load25 +; AVX512F-NEXT: je LBB31_10 +; AVX512F-NEXT: LBB31_42: ## %cond.load25 ; AVX512F-NEXT: vpinsrb $9, 9(%rdi), %xmm1, %xmm0 ; AVX512F-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512F-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX512F-NEXT: je LBB31_22 -; AVX512F-NEXT: LBB31_21: ## %cond.load28 +; AVX512F-NEXT: je LBB31_11 +; AVX512F-NEXT: LBB31_43: ## %cond.load28 ; AVX512F-NEXT: vpinsrb $10, 10(%rdi), %xmm1, %xmm0 ; AVX512F-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512F-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX512F-NEXT: je LBB31_24 -; AVX512F-NEXT: LBB31_23: ## %cond.load31 +; AVX512F-NEXT: je LBB31_12 +; AVX512F-NEXT: LBB31_44: ## %cond.load31 ; AVX512F-NEXT: vpinsrb $11, 11(%rdi), %xmm1, %xmm0 ; AVX512F-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512F-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX512F-NEXT: je LBB31_26 -; AVX512F-NEXT: LBB31_25: ## %cond.load34 +; AVX512F-NEXT: je LBB31_13 +; AVX512F-NEXT: LBB31_45: ## %cond.load34 ; AVX512F-NEXT: vpinsrb $12, 12(%rdi), %xmm1, %xmm0 ; AVX512F-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512F-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX512F-NEXT: je LBB31_28 -; AVX512F-NEXT: LBB31_27: ## %cond.load37 +; AVX512F-NEXT: je LBB31_14 +; AVX512F-NEXT: LBB31_46: ## %cond.load37 ; AVX512F-NEXT: vpinsrb $13, 13(%rdi), %xmm1, %xmm0 ; AVX512F-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512F-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX512F-NEXT: je LBB31_30 -; AVX512F-NEXT: LBB31_29: ## %cond.load40 +; AVX512F-NEXT: je LBB31_15 +; AVX512F-NEXT: LBB31_47: ## %cond.load40 ; AVX512F-NEXT: vpinsrb $14, 14(%rdi), %xmm1, %xmm0 ; AVX512F-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512F-NEXT: testw %ax, %ax -; AVX512F-NEXT: jns LBB31_32 -; AVX512F-NEXT: LBB31_31: ## %cond.load43 +; AVX512F-NEXT: jns LBB31_16 +; AVX512F-NEXT: LBB31_48: ## %cond.load43 ; AVX512F-NEXT: vpinsrb $15, 15(%rdi), %xmm1, %xmm0 ; AVX512F-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512F-NEXT: testl $65536, %eax ## imm = 0x10000 -; AVX512F-NEXT: je LBB31_34 -; AVX512F-NEXT: LBB31_33: ## %cond.load46 +; AVX512F-NEXT: je LBB31_17 +; AVX512F-NEXT: LBB31_49: ## %cond.load46 ; AVX512F-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX512F-NEXT: vpinsrb $0, 16(%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX512F-NEXT: testl $131072, %eax ## imm = 0x20000 -; AVX512F-NEXT: je LBB31_36 -; AVX512F-NEXT: LBB31_35: ## %cond.load49 +; AVX512F-NEXT: je LBB31_18 +; AVX512F-NEXT: LBB31_50: ## %cond.load49 ; AVX512F-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX512F-NEXT: vpinsrb $1, 17(%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX512F-NEXT: testl $262144, %eax ## imm = 0x40000 -; AVX512F-NEXT: je LBB31_38 -; AVX512F-NEXT: LBB31_37: ## %cond.load52 +; AVX512F-NEXT: je LBB31_19 +; AVX512F-NEXT: LBB31_51: ## %cond.load52 ; AVX512F-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX512F-NEXT: vpinsrb $2, 18(%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX512F-NEXT: testl $524288, %eax ## imm = 0x80000 -; AVX512F-NEXT: je LBB31_40 -; AVX512F-NEXT: LBB31_39: ## %cond.load55 +; AVX512F-NEXT: je LBB31_20 +; AVX512F-NEXT: LBB31_52: ## %cond.load55 ; AVX512F-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX512F-NEXT: vpinsrb $3, 19(%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX512F-NEXT: testl $1048576, %eax ## imm = 0x100000 -; AVX512F-NEXT: je LBB31_42 -; AVX512F-NEXT: LBB31_41: ## %cond.load58 +; AVX512F-NEXT: je LBB31_21 +; AVX512F-NEXT: LBB31_53: ## %cond.load58 ; AVX512F-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX512F-NEXT: vpinsrb $4, 20(%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX512F-NEXT: testl $2097152, %eax ## imm = 0x200000 -; AVX512F-NEXT: je LBB31_44 -; AVX512F-NEXT: LBB31_43: ## %cond.load61 +; AVX512F-NEXT: je LBB31_22 +; AVX512F-NEXT: LBB31_54: ## %cond.load61 ; AVX512F-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX512F-NEXT: vpinsrb $5, 21(%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX512F-NEXT: testl $4194304, %eax ## imm = 0x400000 -; AVX512F-NEXT: je LBB31_46 -; AVX512F-NEXT: LBB31_45: ## %cond.load64 +; AVX512F-NEXT: je LBB31_23 +; AVX512F-NEXT: LBB31_55: ## %cond.load64 ; AVX512F-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX512F-NEXT: vpinsrb $6, 22(%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX512F-NEXT: testl $8388608, %eax ## imm = 0x800000 -; AVX512F-NEXT: je LBB31_48 -; AVX512F-NEXT: LBB31_47: ## %cond.load67 +; AVX512F-NEXT: je LBB31_24 +; AVX512F-NEXT: LBB31_56: ## %cond.load67 ; AVX512F-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX512F-NEXT: vpinsrb $7, 23(%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX512F-NEXT: testl $16777216, %eax ## imm = 0x1000000 -; AVX512F-NEXT: je LBB31_50 -; AVX512F-NEXT: LBB31_49: ## %cond.load70 +; AVX512F-NEXT: je LBB31_25 +; AVX512F-NEXT: LBB31_57: ## %cond.load70 ; AVX512F-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX512F-NEXT: vpinsrb $8, 24(%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX512F-NEXT: testl $33554432, %eax ## imm = 0x2000000 -; AVX512F-NEXT: je LBB31_52 -; AVX512F-NEXT: LBB31_51: ## %cond.load73 +; AVX512F-NEXT: je LBB31_26 +; AVX512F-NEXT: LBB31_58: ## %cond.load73 ; AVX512F-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX512F-NEXT: vpinsrb $9, 25(%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX512F-NEXT: testl $67108864, %eax ## imm = 0x4000000 -; AVX512F-NEXT: je LBB31_54 -; AVX512F-NEXT: LBB31_53: ## %cond.load76 +; AVX512F-NEXT: je LBB31_27 +; AVX512F-NEXT: LBB31_59: ## %cond.load76 ; AVX512F-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX512F-NEXT: vpinsrb $10, 26(%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX512F-NEXT: testl $134217728, %eax ## imm = 0x8000000 -; AVX512F-NEXT: je LBB31_56 -; AVX512F-NEXT: LBB31_55: ## %cond.load79 +; AVX512F-NEXT: je LBB31_28 +; AVX512F-NEXT: LBB31_60: ## %cond.load79 ; AVX512F-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX512F-NEXT: vpinsrb $11, 27(%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX512F-NEXT: testl $268435456, %eax ## imm = 0x10000000 -; AVX512F-NEXT: je LBB31_58 -; AVX512F-NEXT: LBB31_57: ## %cond.load82 +; AVX512F-NEXT: je LBB31_29 +; AVX512F-NEXT: LBB31_61: ## %cond.load82 ; AVX512F-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX512F-NEXT: vpinsrb $12, 28(%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX512F-NEXT: testl $536870912, %eax ## imm = 0x20000000 -; AVX512F-NEXT: je LBB31_60 -; AVX512F-NEXT: LBB31_59: ## %cond.load85 +; AVX512F-NEXT: je LBB31_30 +; AVX512F-NEXT: LBB31_62: ## %cond.load85 ; AVX512F-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX512F-NEXT: vpinsrb $13, 29(%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX512F-NEXT: testl $1073741824, %eax ## imm = 0x40000000 -; AVX512F-NEXT: je LBB31_62 -; AVX512F-NEXT: LBB31_61: ## %cond.load88 +; AVX512F-NEXT: je LBB31_31 +; AVX512F-NEXT: LBB31_63: ## %cond.load88 ; AVX512F-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX512F-NEXT: vpinsrb $14, 30(%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX512F-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 -; AVX512F-NEXT: je LBB31_64 -; AVX512F-NEXT: LBB31_63: ## %cond.load91 +; AVX512F-NEXT: je LBB31_32 +; AVX512F-NEXT: LBB31_64: ## %cond.load91 ; AVX512F-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX512F-NEXT: vpinsrb $15, 31(%rdi), %xmm0, %xmm0 ; AVX512F-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 @@ -6804,274 +6804,274 @@ define <32 x i8> @load_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %dst ; AVX512VLDQ: ## %bb.0: ; AVX512VLDQ-NEXT: vpmovmskb %ymm0, %eax ; AVX512VLDQ-NEXT: testb $1, %al -; AVX512VLDQ-NEXT: jne LBB31_1 -; AVX512VLDQ-NEXT: ## %bb.2: ## %else +; AVX512VLDQ-NEXT: jne LBB31_33 +; AVX512VLDQ-NEXT: ## %bb.1: ## %else ; AVX512VLDQ-NEXT: testb $2, %al -; AVX512VLDQ-NEXT: jne LBB31_3 -; AVX512VLDQ-NEXT: LBB31_4: ## %else2 +; AVX512VLDQ-NEXT: jne LBB31_34 +; AVX512VLDQ-NEXT: LBB31_2: ## %else2 ; AVX512VLDQ-NEXT: testb $4, %al -; AVX512VLDQ-NEXT: jne LBB31_5 -; AVX512VLDQ-NEXT: LBB31_6: ## %else5 +; AVX512VLDQ-NEXT: jne LBB31_35 +; AVX512VLDQ-NEXT: LBB31_3: ## %else5 ; AVX512VLDQ-NEXT: testb $8, %al -; AVX512VLDQ-NEXT: jne LBB31_7 -; AVX512VLDQ-NEXT: LBB31_8: ## %else8 +; AVX512VLDQ-NEXT: jne LBB31_36 +; AVX512VLDQ-NEXT: LBB31_4: ## %else8 ; AVX512VLDQ-NEXT: testb $16, %al -; AVX512VLDQ-NEXT: jne LBB31_9 -; AVX512VLDQ-NEXT: LBB31_10: ## %else11 +; AVX512VLDQ-NEXT: jne LBB31_37 +; AVX512VLDQ-NEXT: LBB31_5: ## %else11 ; AVX512VLDQ-NEXT: testb $32, %al -; AVX512VLDQ-NEXT: jne LBB31_11 -; AVX512VLDQ-NEXT: LBB31_12: ## %else14 +; AVX512VLDQ-NEXT: jne LBB31_38 +; AVX512VLDQ-NEXT: LBB31_6: ## %else14 ; AVX512VLDQ-NEXT: testb $64, %al -; AVX512VLDQ-NEXT: jne LBB31_13 -; AVX512VLDQ-NEXT: LBB31_14: ## %else17 +; AVX512VLDQ-NEXT: jne LBB31_39 +; AVX512VLDQ-NEXT: LBB31_7: ## %else17 ; AVX512VLDQ-NEXT: testb %al, %al -; AVX512VLDQ-NEXT: js LBB31_15 -; AVX512VLDQ-NEXT: LBB31_16: ## %else20 +; AVX512VLDQ-NEXT: js LBB31_40 +; AVX512VLDQ-NEXT: LBB31_8: ## %else20 ; AVX512VLDQ-NEXT: testl $256, %eax ## imm = 0x100 -; AVX512VLDQ-NEXT: jne LBB31_17 -; AVX512VLDQ-NEXT: LBB31_18: ## %else23 +; AVX512VLDQ-NEXT: jne LBB31_41 +; AVX512VLDQ-NEXT: LBB31_9: ## %else23 ; AVX512VLDQ-NEXT: testl $512, %eax ## imm = 0x200 -; AVX512VLDQ-NEXT: jne LBB31_19 -; AVX512VLDQ-NEXT: LBB31_20: ## %else26 +; AVX512VLDQ-NEXT: jne LBB31_42 +; AVX512VLDQ-NEXT: LBB31_10: ## %else26 ; AVX512VLDQ-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX512VLDQ-NEXT: jne LBB31_21 -; AVX512VLDQ-NEXT: LBB31_22: ## %else29 +; AVX512VLDQ-NEXT: jne LBB31_43 +; AVX512VLDQ-NEXT: LBB31_11: ## %else29 ; AVX512VLDQ-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX512VLDQ-NEXT: jne LBB31_23 -; AVX512VLDQ-NEXT: LBB31_24: ## %else32 +; AVX512VLDQ-NEXT: jne LBB31_44 +; AVX512VLDQ-NEXT: LBB31_12: ## %else32 ; AVX512VLDQ-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX512VLDQ-NEXT: jne LBB31_25 -; AVX512VLDQ-NEXT: LBB31_26: ## %else35 +; AVX512VLDQ-NEXT: jne LBB31_45 +; AVX512VLDQ-NEXT: LBB31_13: ## %else35 ; AVX512VLDQ-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX512VLDQ-NEXT: jne LBB31_27 -; AVX512VLDQ-NEXT: LBB31_28: ## %else38 +; AVX512VLDQ-NEXT: jne LBB31_46 +; AVX512VLDQ-NEXT: LBB31_14: ## %else38 ; AVX512VLDQ-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX512VLDQ-NEXT: jne LBB31_29 -; AVX512VLDQ-NEXT: LBB31_30: ## %else41 +; AVX512VLDQ-NEXT: jne LBB31_47 +; AVX512VLDQ-NEXT: LBB31_15: ## %else41 ; AVX512VLDQ-NEXT: testw %ax, %ax -; AVX512VLDQ-NEXT: js LBB31_31 -; AVX512VLDQ-NEXT: LBB31_32: ## %else44 +; AVX512VLDQ-NEXT: js LBB31_48 +; AVX512VLDQ-NEXT: LBB31_16: ## %else44 ; AVX512VLDQ-NEXT: testl $65536, %eax ## imm = 0x10000 -; AVX512VLDQ-NEXT: jne LBB31_33 -; AVX512VLDQ-NEXT: LBB31_34: ## %else47 +; AVX512VLDQ-NEXT: jne LBB31_49 +; AVX512VLDQ-NEXT: LBB31_17: ## %else47 ; AVX512VLDQ-NEXT: testl $131072, %eax ## imm = 0x20000 -; AVX512VLDQ-NEXT: jne LBB31_35 -; AVX512VLDQ-NEXT: LBB31_36: ## %else50 +; AVX512VLDQ-NEXT: jne LBB31_50 +; AVX512VLDQ-NEXT: LBB31_18: ## %else50 ; AVX512VLDQ-NEXT: testl $262144, %eax ## imm = 0x40000 -; AVX512VLDQ-NEXT: jne LBB31_37 -; AVX512VLDQ-NEXT: LBB31_38: ## %else53 +; AVX512VLDQ-NEXT: jne LBB31_51 +; AVX512VLDQ-NEXT: LBB31_19: ## %else53 ; AVX512VLDQ-NEXT: testl $524288, %eax ## imm = 0x80000 -; AVX512VLDQ-NEXT: jne LBB31_39 -; AVX512VLDQ-NEXT: LBB31_40: ## %else56 +; AVX512VLDQ-NEXT: jne LBB31_52 +; AVX512VLDQ-NEXT: LBB31_20: ## %else56 ; AVX512VLDQ-NEXT: testl $1048576, %eax ## imm = 0x100000 -; AVX512VLDQ-NEXT: jne LBB31_41 -; AVX512VLDQ-NEXT: LBB31_42: ## %else59 +; AVX512VLDQ-NEXT: jne LBB31_53 +; AVX512VLDQ-NEXT: LBB31_21: ## %else59 ; AVX512VLDQ-NEXT: testl $2097152, %eax ## imm = 0x200000 -; AVX512VLDQ-NEXT: jne LBB31_43 -; AVX512VLDQ-NEXT: LBB31_44: ## %else62 +; AVX512VLDQ-NEXT: jne LBB31_54 +; AVX512VLDQ-NEXT: LBB31_22: ## %else62 ; AVX512VLDQ-NEXT: testl $4194304, %eax ## imm = 0x400000 -; AVX512VLDQ-NEXT: jne LBB31_45 -; AVX512VLDQ-NEXT: LBB31_46: ## %else65 +; AVX512VLDQ-NEXT: jne LBB31_55 +; AVX512VLDQ-NEXT: LBB31_23: ## %else65 ; AVX512VLDQ-NEXT: testl $8388608, %eax ## imm = 0x800000 -; AVX512VLDQ-NEXT: jne LBB31_47 -; AVX512VLDQ-NEXT: LBB31_48: ## %else68 +; AVX512VLDQ-NEXT: jne LBB31_56 +; AVX512VLDQ-NEXT: LBB31_24: ## %else68 ; AVX512VLDQ-NEXT: testl $16777216, %eax ## imm = 0x1000000 -; AVX512VLDQ-NEXT: jne LBB31_49 -; AVX512VLDQ-NEXT: LBB31_50: ## %else71 +; AVX512VLDQ-NEXT: jne LBB31_57 +; AVX512VLDQ-NEXT: LBB31_25: ## %else71 ; AVX512VLDQ-NEXT: testl $33554432, %eax ## imm = 0x2000000 -; AVX512VLDQ-NEXT: jne LBB31_51 -; AVX512VLDQ-NEXT: LBB31_52: ## %else74 +; AVX512VLDQ-NEXT: jne LBB31_58 +; AVX512VLDQ-NEXT: LBB31_26: ## %else74 ; AVX512VLDQ-NEXT: testl $67108864, %eax ## imm = 0x4000000 -; AVX512VLDQ-NEXT: jne LBB31_53 -; AVX512VLDQ-NEXT: LBB31_54: ## %else77 +; AVX512VLDQ-NEXT: jne LBB31_59 +; AVX512VLDQ-NEXT: LBB31_27: ## %else77 ; AVX512VLDQ-NEXT: testl $134217728, %eax ## imm = 0x8000000 -; AVX512VLDQ-NEXT: jne LBB31_55 -; AVX512VLDQ-NEXT: LBB31_56: ## %else80 +; AVX512VLDQ-NEXT: jne LBB31_60 +; AVX512VLDQ-NEXT: LBB31_28: ## %else80 ; AVX512VLDQ-NEXT: testl $268435456, %eax ## imm = 0x10000000 -; AVX512VLDQ-NEXT: jne LBB31_57 -; AVX512VLDQ-NEXT: LBB31_58: ## %else83 +; AVX512VLDQ-NEXT: jne LBB31_61 +; AVX512VLDQ-NEXT: LBB31_29: ## %else83 ; AVX512VLDQ-NEXT: testl $536870912, %eax ## imm = 0x20000000 -; AVX512VLDQ-NEXT: jne LBB31_59 -; AVX512VLDQ-NEXT: LBB31_60: ## %else86 +; AVX512VLDQ-NEXT: jne LBB31_62 +; AVX512VLDQ-NEXT: LBB31_30: ## %else86 ; AVX512VLDQ-NEXT: testl $1073741824, %eax ## imm = 0x40000000 -; AVX512VLDQ-NEXT: jne LBB31_61 -; AVX512VLDQ-NEXT: LBB31_62: ## %else89 -; AVX512VLDQ-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 ; AVX512VLDQ-NEXT: jne LBB31_63 -; AVX512VLDQ-NEXT: LBB31_64: ## %else92 +; AVX512VLDQ-NEXT: LBB31_31: ## %else89 +; AVX512VLDQ-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 +; AVX512VLDQ-NEXT: jne LBB31_64 +; AVX512VLDQ-NEXT: LBB31_32: ## %else92 ; AVX512VLDQ-NEXT: vmovdqa %ymm1, %ymm0 ; AVX512VLDQ-NEXT: retq -; AVX512VLDQ-NEXT: LBB31_1: ## %cond.load +; AVX512VLDQ-NEXT: LBB31_33: ## %cond.load ; AVX512VLDQ-NEXT: vpinsrb $0, (%rdi), %xmm1, %xmm0 ; AVX512VLDQ-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512VLDQ-NEXT: testb $2, %al -; AVX512VLDQ-NEXT: je LBB31_4 -; AVX512VLDQ-NEXT: LBB31_3: ## %cond.load1 +; AVX512VLDQ-NEXT: je LBB31_2 +; AVX512VLDQ-NEXT: LBB31_34: ## %cond.load1 ; AVX512VLDQ-NEXT: vpinsrb $1, 1(%rdi), %xmm1, %xmm0 ; AVX512VLDQ-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512VLDQ-NEXT: testb $4, %al -; AVX512VLDQ-NEXT: je LBB31_6 -; AVX512VLDQ-NEXT: LBB31_5: ## %cond.load4 +; AVX512VLDQ-NEXT: je LBB31_3 +; AVX512VLDQ-NEXT: LBB31_35: ## %cond.load4 ; AVX512VLDQ-NEXT: vpinsrb $2, 2(%rdi), %xmm1, %xmm0 ; AVX512VLDQ-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512VLDQ-NEXT: testb $8, %al -; AVX512VLDQ-NEXT: je LBB31_8 -; AVX512VLDQ-NEXT: LBB31_7: ## %cond.load7 +; AVX512VLDQ-NEXT: je LBB31_4 +; AVX512VLDQ-NEXT: LBB31_36: ## %cond.load7 ; AVX512VLDQ-NEXT: vpinsrb $3, 3(%rdi), %xmm1, %xmm0 ; AVX512VLDQ-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512VLDQ-NEXT: testb $16, %al -; AVX512VLDQ-NEXT: je LBB31_10 -; AVX512VLDQ-NEXT: LBB31_9: ## %cond.load10 +; AVX512VLDQ-NEXT: je LBB31_5 +; AVX512VLDQ-NEXT: LBB31_37: ## %cond.load10 ; AVX512VLDQ-NEXT: vpinsrb $4, 4(%rdi), %xmm1, %xmm0 ; AVX512VLDQ-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512VLDQ-NEXT: testb $32, %al -; AVX512VLDQ-NEXT: je LBB31_12 -; AVX512VLDQ-NEXT: LBB31_11: ## %cond.load13 +; AVX512VLDQ-NEXT: je LBB31_6 +; AVX512VLDQ-NEXT: LBB31_38: ## %cond.load13 ; AVX512VLDQ-NEXT: vpinsrb $5, 5(%rdi), %xmm1, %xmm0 ; AVX512VLDQ-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512VLDQ-NEXT: testb $64, %al -; AVX512VLDQ-NEXT: je LBB31_14 -; AVX512VLDQ-NEXT: LBB31_13: ## %cond.load16 +; AVX512VLDQ-NEXT: je LBB31_7 +; AVX512VLDQ-NEXT: LBB31_39: ## %cond.load16 ; AVX512VLDQ-NEXT: vpinsrb $6, 6(%rdi), %xmm1, %xmm0 ; AVX512VLDQ-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512VLDQ-NEXT: testb %al, %al -; AVX512VLDQ-NEXT: jns LBB31_16 -; AVX512VLDQ-NEXT: LBB31_15: ## %cond.load19 +; AVX512VLDQ-NEXT: jns LBB31_8 +; AVX512VLDQ-NEXT: LBB31_40: ## %cond.load19 ; AVX512VLDQ-NEXT: vpinsrb $7, 7(%rdi), %xmm1, %xmm0 ; AVX512VLDQ-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512VLDQ-NEXT: testl $256, %eax ## imm = 0x100 -; AVX512VLDQ-NEXT: je LBB31_18 -; AVX512VLDQ-NEXT: LBB31_17: ## %cond.load22 +; AVX512VLDQ-NEXT: je LBB31_9 +; AVX512VLDQ-NEXT: LBB31_41: ## %cond.load22 ; AVX512VLDQ-NEXT: vpinsrb $8, 8(%rdi), %xmm1, %xmm0 ; AVX512VLDQ-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512VLDQ-NEXT: testl $512, %eax ## imm = 0x200 -; AVX512VLDQ-NEXT: je LBB31_20 -; AVX512VLDQ-NEXT: LBB31_19: ## %cond.load25 +; AVX512VLDQ-NEXT: je LBB31_10 +; AVX512VLDQ-NEXT: LBB31_42: ## %cond.load25 ; AVX512VLDQ-NEXT: vpinsrb $9, 9(%rdi), %xmm1, %xmm0 ; AVX512VLDQ-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512VLDQ-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX512VLDQ-NEXT: je LBB31_22 -; AVX512VLDQ-NEXT: LBB31_21: ## %cond.load28 +; AVX512VLDQ-NEXT: je LBB31_11 +; AVX512VLDQ-NEXT: LBB31_43: ## %cond.load28 ; AVX512VLDQ-NEXT: vpinsrb $10, 10(%rdi), %xmm1, %xmm0 ; AVX512VLDQ-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512VLDQ-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX512VLDQ-NEXT: je LBB31_24 -; AVX512VLDQ-NEXT: LBB31_23: ## %cond.load31 +; AVX512VLDQ-NEXT: je LBB31_12 +; AVX512VLDQ-NEXT: LBB31_44: ## %cond.load31 ; AVX512VLDQ-NEXT: vpinsrb $11, 11(%rdi), %xmm1, %xmm0 ; AVX512VLDQ-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512VLDQ-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX512VLDQ-NEXT: je LBB31_26 -; AVX512VLDQ-NEXT: LBB31_25: ## %cond.load34 +; AVX512VLDQ-NEXT: je LBB31_13 +; AVX512VLDQ-NEXT: LBB31_45: ## %cond.load34 ; AVX512VLDQ-NEXT: vpinsrb $12, 12(%rdi), %xmm1, %xmm0 ; AVX512VLDQ-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512VLDQ-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX512VLDQ-NEXT: je LBB31_28 -; AVX512VLDQ-NEXT: LBB31_27: ## %cond.load37 +; AVX512VLDQ-NEXT: je LBB31_14 +; AVX512VLDQ-NEXT: LBB31_46: ## %cond.load37 ; AVX512VLDQ-NEXT: vpinsrb $13, 13(%rdi), %xmm1, %xmm0 ; AVX512VLDQ-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512VLDQ-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX512VLDQ-NEXT: je LBB31_30 -; AVX512VLDQ-NEXT: LBB31_29: ## %cond.load40 +; AVX512VLDQ-NEXT: je LBB31_15 +; AVX512VLDQ-NEXT: LBB31_47: ## %cond.load40 ; AVX512VLDQ-NEXT: vpinsrb $14, 14(%rdi), %xmm1, %xmm0 ; AVX512VLDQ-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512VLDQ-NEXT: testw %ax, %ax -; AVX512VLDQ-NEXT: jns LBB31_32 -; AVX512VLDQ-NEXT: LBB31_31: ## %cond.load43 +; AVX512VLDQ-NEXT: jns LBB31_16 +; AVX512VLDQ-NEXT: LBB31_48: ## %cond.load43 ; AVX512VLDQ-NEXT: vpinsrb $15, 15(%rdi), %xmm1, %xmm0 ; AVX512VLDQ-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; AVX512VLDQ-NEXT: testl $65536, %eax ## imm = 0x10000 -; AVX512VLDQ-NEXT: je LBB31_34 -; AVX512VLDQ-NEXT: LBB31_33: ## %cond.load46 +; AVX512VLDQ-NEXT: je LBB31_17 +; AVX512VLDQ-NEXT: LBB31_49: ## %cond.load46 ; AVX512VLDQ-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX512VLDQ-NEXT: vpinsrb $0, 16(%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX512VLDQ-NEXT: testl $131072, %eax ## imm = 0x20000 -; AVX512VLDQ-NEXT: je LBB31_36 -; AVX512VLDQ-NEXT: LBB31_35: ## %cond.load49 +; AVX512VLDQ-NEXT: je LBB31_18 +; AVX512VLDQ-NEXT: LBB31_50: ## %cond.load49 ; AVX512VLDQ-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX512VLDQ-NEXT: vpinsrb $1, 17(%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX512VLDQ-NEXT: testl $262144, %eax ## imm = 0x40000 -; AVX512VLDQ-NEXT: je LBB31_38 -; AVX512VLDQ-NEXT: LBB31_37: ## %cond.load52 +; AVX512VLDQ-NEXT: je LBB31_19 +; AVX512VLDQ-NEXT: LBB31_51: ## %cond.load52 ; AVX512VLDQ-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX512VLDQ-NEXT: vpinsrb $2, 18(%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX512VLDQ-NEXT: testl $524288, %eax ## imm = 0x80000 -; AVX512VLDQ-NEXT: je LBB31_40 -; AVX512VLDQ-NEXT: LBB31_39: ## %cond.load55 +; AVX512VLDQ-NEXT: je LBB31_20 +; AVX512VLDQ-NEXT: LBB31_52: ## %cond.load55 ; AVX512VLDQ-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX512VLDQ-NEXT: vpinsrb $3, 19(%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX512VLDQ-NEXT: testl $1048576, %eax ## imm = 0x100000 -; AVX512VLDQ-NEXT: je LBB31_42 -; AVX512VLDQ-NEXT: LBB31_41: ## %cond.load58 +; AVX512VLDQ-NEXT: je LBB31_21 +; AVX512VLDQ-NEXT: LBB31_53: ## %cond.load58 ; AVX512VLDQ-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX512VLDQ-NEXT: vpinsrb $4, 20(%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX512VLDQ-NEXT: testl $2097152, %eax ## imm = 0x200000 -; AVX512VLDQ-NEXT: je LBB31_44 -; AVX512VLDQ-NEXT: LBB31_43: ## %cond.load61 +; AVX512VLDQ-NEXT: je LBB31_22 +; AVX512VLDQ-NEXT: LBB31_54: ## %cond.load61 ; AVX512VLDQ-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX512VLDQ-NEXT: vpinsrb $5, 21(%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX512VLDQ-NEXT: testl $4194304, %eax ## imm = 0x400000 -; AVX512VLDQ-NEXT: je LBB31_46 -; AVX512VLDQ-NEXT: LBB31_45: ## %cond.load64 +; AVX512VLDQ-NEXT: je LBB31_23 +; AVX512VLDQ-NEXT: LBB31_55: ## %cond.load64 ; AVX512VLDQ-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX512VLDQ-NEXT: vpinsrb $6, 22(%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX512VLDQ-NEXT: testl $8388608, %eax ## imm = 0x800000 -; AVX512VLDQ-NEXT: je LBB31_48 -; AVX512VLDQ-NEXT: LBB31_47: ## %cond.load67 +; AVX512VLDQ-NEXT: je LBB31_24 +; AVX512VLDQ-NEXT: LBB31_56: ## %cond.load67 ; AVX512VLDQ-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX512VLDQ-NEXT: vpinsrb $7, 23(%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX512VLDQ-NEXT: testl $16777216, %eax ## imm = 0x1000000 -; AVX512VLDQ-NEXT: je LBB31_50 -; AVX512VLDQ-NEXT: LBB31_49: ## %cond.load70 +; AVX512VLDQ-NEXT: je LBB31_25 +; AVX512VLDQ-NEXT: LBB31_57: ## %cond.load70 ; AVX512VLDQ-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX512VLDQ-NEXT: vpinsrb $8, 24(%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX512VLDQ-NEXT: testl $33554432, %eax ## imm = 0x2000000 -; AVX512VLDQ-NEXT: je LBB31_52 -; AVX512VLDQ-NEXT: LBB31_51: ## %cond.load73 +; AVX512VLDQ-NEXT: je LBB31_26 +; AVX512VLDQ-NEXT: LBB31_58: ## %cond.load73 ; AVX512VLDQ-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX512VLDQ-NEXT: vpinsrb $9, 25(%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX512VLDQ-NEXT: testl $67108864, %eax ## imm = 0x4000000 -; AVX512VLDQ-NEXT: je LBB31_54 -; AVX512VLDQ-NEXT: LBB31_53: ## %cond.load76 +; AVX512VLDQ-NEXT: je LBB31_27 +; AVX512VLDQ-NEXT: LBB31_59: ## %cond.load76 ; AVX512VLDQ-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX512VLDQ-NEXT: vpinsrb $10, 26(%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX512VLDQ-NEXT: testl $134217728, %eax ## imm = 0x8000000 -; AVX512VLDQ-NEXT: je LBB31_56 -; AVX512VLDQ-NEXT: LBB31_55: ## %cond.load79 +; AVX512VLDQ-NEXT: je LBB31_28 +; AVX512VLDQ-NEXT: LBB31_60: ## %cond.load79 ; AVX512VLDQ-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX512VLDQ-NEXT: vpinsrb $11, 27(%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX512VLDQ-NEXT: testl $268435456, %eax ## imm = 0x10000000 -; AVX512VLDQ-NEXT: je LBB31_58 -; AVX512VLDQ-NEXT: LBB31_57: ## %cond.load82 +; AVX512VLDQ-NEXT: je LBB31_29 +; AVX512VLDQ-NEXT: LBB31_61: ## %cond.load82 ; AVX512VLDQ-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX512VLDQ-NEXT: vpinsrb $12, 28(%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX512VLDQ-NEXT: testl $536870912, %eax ## imm = 0x20000000 -; AVX512VLDQ-NEXT: je LBB31_60 -; AVX512VLDQ-NEXT: LBB31_59: ## %cond.load85 +; AVX512VLDQ-NEXT: je LBB31_30 +; AVX512VLDQ-NEXT: LBB31_62: ## %cond.load85 ; AVX512VLDQ-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX512VLDQ-NEXT: vpinsrb $13, 29(%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX512VLDQ-NEXT: testl $1073741824, %eax ## imm = 0x40000000 -; AVX512VLDQ-NEXT: je LBB31_62 -; AVX512VLDQ-NEXT: LBB31_61: ## %cond.load88 +; AVX512VLDQ-NEXT: je LBB31_31 +; AVX512VLDQ-NEXT: LBB31_63: ## %cond.load88 ; AVX512VLDQ-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX512VLDQ-NEXT: vpinsrb $14, 30(%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 ; AVX512VLDQ-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 -; AVX512VLDQ-NEXT: je LBB31_64 -; AVX512VLDQ-NEXT: LBB31_63: ## %cond.load91 +; AVX512VLDQ-NEXT: je LBB31_32 +; AVX512VLDQ-NEXT: LBB31_64: ## %cond.load91 ; AVX512VLDQ-NEXT: vextracti128 $1, %ymm1, %xmm0 ; AVX512VLDQ-NEXT: vpinsrb $15, 31(%rdi), %xmm0, %xmm0 ; AVX512VLDQ-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm1 diff --git a/llvm/test/CodeGen/X86/masked_store.ll b/llvm/test/CodeGen/X86/masked_store.ll index bdbb912a71d36..5ad827f486089 100644 --- a/llvm/test/CodeGen/X86/masked_store.ll +++ b/llvm/test/CodeGen/X86/masked_store.ll @@ -84,17 +84,17 @@ define void @store_v2f64_i2(i2 %trigger, ptr %addr, <2 x double> %val) nounwind ; SSE-LABEL: store_v2f64_i2: ; SSE: ## %bb.0: ; SSE-NEXT: testb $1, %dil -; SSE-NEXT: jne LBB2_1 -; SSE-NEXT: ## %bb.2: ## %else -; SSE-NEXT: testb $2, %dil ; SSE-NEXT: jne LBB2_3 -; SSE-NEXT: LBB2_4: ## %else2 +; SSE-NEXT: ## %bb.1: ## %else +; SSE-NEXT: testb $2, %dil +; SSE-NEXT: jne LBB2_4 +; SSE-NEXT: LBB2_2: ## %else2 ; SSE-NEXT: retq -; SSE-NEXT: LBB2_1: ## %cond.store +; SSE-NEXT: LBB2_3: ## %cond.store ; SSE-NEXT: movlps %xmm0, (%rsi) ; SSE-NEXT: testb $2, %dil -; SSE-NEXT: je LBB2_4 -; SSE-NEXT: LBB2_3: ## %cond.store1 +; SSE-NEXT: je LBB2_2 +; SSE-NEXT: LBB2_4: ## %cond.store1 ; SSE-NEXT: movhps %xmm0, 8(%rsi) ; SSE-NEXT: retq ; @@ -156,17 +156,17 @@ define void @store_v2f64_v2i64(<2 x i64> %trigger, ptr %addr, <2 x double> %val) ; SSE: ## %bb.0: ; SSE-NEXT: movmskpd %xmm0, %eax ; SSE-NEXT: testb $1, %al -; SSE-NEXT: jne LBB3_1 -; SSE-NEXT: ## %bb.2: ## %else -; SSE-NEXT: testb $2, %al ; SSE-NEXT: jne LBB3_3 -; SSE-NEXT: LBB3_4: ## %else2 +; SSE-NEXT: ## %bb.1: ## %else +; SSE-NEXT: testb $2, %al +; SSE-NEXT: jne LBB3_4 +; SSE-NEXT: LBB3_2: ## %else2 ; SSE-NEXT: retq -; SSE-NEXT: LBB3_1: ## %cond.store +; SSE-NEXT: LBB3_3: ## %cond.store ; SSE-NEXT: movlps %xmm1, (%rdi) ; SSE-NEXT: testb $2, %al -; SSE-NEXT: je LBB3_4 -; SSE-NEXT: LBB3_3: ## %cond.store1 +; SSE-NEXT: je LBB3_2 +; SSE-NEXT: LBB3_4: ## %cond.store1 ; SSE-NEXT: movhps %xmm1, 8(%rdi) ; SSE-NEXT: retq ; @@ -215,31 +215,31 @@ define void @store_v4f64_i4(i4 %trigger, ptr %addr, <4 x double> %val) nounwind ; SSE-LABEL: store_v4f64_i4: ; SSE: ## %bb.0: ; SSE-NEXT: testb $1, %dil -; SSE-NEXT: jne LBB4_1 -; SSE-NEXT: ## %bb.2: ## %else +; SSE-NEXT: jne LBB4_5 +; SSE-NEXT: ## %bb.1: ## %else ; SSE-NEXT: testb $2, %dil -; SSE-NEXT: jne LBB4_3 -; SSE-NEXT: LBB4_4: ## %else2 +; SSE-NEXT: jne LBB4_6 +; SSE-NEXT: LBB4_2: ## %else2 ; SSE-NEXT: testb $4, %dil -; SSE-NEXT: jne LBB4_5 -; SSE-NEXT: LBB4_6: ## %else4 -; SSE-NEXT: testb $8, %dil ; SSE-NEXT: jne LBB4_7 -; SSE-NEXT: LBB4_8: ## %else6 +; SSE-NEXT: LBB4_3: ## %else4 +; SSE-NEXT: testb $8, %dil +; SSE-NEXT: jne LBB4_8 +; SSE-NEXT: LBB4_4: ## %else6 ; SSE-NEXT: retq -; SSE-NEXT: LBB4_1: ## %cond.store +; SSE-NEXT: LBB4_5: ## %cond.store ; SSE-NEXT: movlps %xmm0, (%rsi) ; SSE-NEXT: testb $2, %dil -; SSE-NEXT: je LBB4_4 -; SSE-NEXT: LBB4_3: ## %cond.store1 +; SSE-NEXT: je LBB4_2 +; SSE-NEXT: LBB4_6: ## %cond.store1 ; SSE-NEXT: movhps %xmm0, 8(%rsi) ; SSE-NEXT: testb $4, %dil -; SSE-NEXT: je LBB4_6 -; SSE-NEXT: LBB4_5: ## %cond.store3 +; SSE-NEXT: je LBB4_3 +; SSE-NEXT: LBB4_7: ## %cond.store3 ; SSE-NEXT: movlps %xmm1, 16(%rsi) ; SSE-NEXT: testb $8, %dil -; SSE-NEXT: je LBB4_8 -; SSE-NEXT: LBB4_7: ## %cond.store5 +; SSE-NEXT: je LBB4_4 +; SSE-NEXT: LBB4_8: ## %cond.store5 ; SSE-NEXT: movhps %xmm1, 24(%rsi) ; SSE-NEXT: retq ; @@ -311,31 +311,31 @@ define void @store_v4f64_v4i64(<4 x i64> %trigger, ptr %addr, <4 x double> %val) ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[1,3] ; SSE2-NEXT: movmskps %xmm0, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB5_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB5_5 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB5_3 -; SSE2-NEXT: LBB5_4: ## %else2 +; SSE2-NEXT: jne LBB5_6 +; SSE2-NEXT: LBB5_2: ## %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB5_5 -; SSE2-NEXT: LBB5_6: ## %else4 -; SSE2-NEXT: testb $8, %al ; SSE2-NEXT: jne LBB5_7 -; SSE2-NEXT: LBB5_8: ## %else6 +; SSE2-NEXT: LBB5_3: ## %else4 +; SSE2-NEXT: testb $8, %al +; SSE2-NEXT: jne LBB5_8 +; SSE2-NEXT: LBB5_4: ## %else6 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB5_1: ## %cond.store +; SSE2-NEXT: LBB5_5: ## %cond.store ; SSE2-NEXT: movlps %xmm2, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB5_4 -; SSE2-NEXT: LBB5_3: ## %cond.store1 +; SSE2-NEXT: je LBB5_2 +; SSE2-NEXT: LBB5_6: ## %cond.store1 ; SSE2-NEXT: movhps %xmm2, 8(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB5_6 -; SSE2-NEXT: LBB5_5: ## %cond.store3 +; SSE2-NEXT: je LBB5_3 +; SSE2-NEXT: LBB5_7: ## %cond.store3 ; SSE2-NEXT: movlps %xmm3, 16(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB5_8 -; SSE2-NEXT: LBB5_7: ## %cond.store5 +; SSE2-NEXT: je LBB5_4 +; SSE2-NEXT: LBB5_8: ## %cond.store5 ; SSE2-NEXT: movhps %xmm3, 24(%rdi) ; SSE2-NEXT: retq ; @@ -348,31 +348,31 @@ define void @store_v4f64_v4i64(<4 x i64> %trigger, ptr %addr, <4 x double> %val) ; SSE4-NEXT: packssdw %xmm5, %xmm4 ; SSE4-NEXT: movmskps %xmm4, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne LBB5_1 -; SSE4-NEXT: ## %bb.2: ## %else +; SSE4-NEXT: jne LBB5_5 +; SSE4-NEXT: ## %bb.1: ## %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne LBB5_3 -; SSE4-NEXT: LBB5_4: ## %else2 +; SSE4-NEXT: jne LBB5_6 +; SSE4-NEXT: LBB5_2: ## %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne LBB5_5 -; SSE4-NEXT: LBB5_6: ## %else4 -; SSE4-NEXT: testb $8, %al ; SSE4-NEXT: jne LBB5_7 -; SSE4-NEXT: LBB5_8: ## %else6 +; SSE4-NEXT: LBB5_3: ## %else4 +; SSE4-NEXT: testb $8, %al +; SSE4-NEXT: jne LBB5_8 +; SSE4-NEXT: LBB5_4: ## %else6 ; SSE4-NEXT: retq -; SSE4-NEXT: LBB5_1: ## %cond.store +; SSE4-NEXT: LBB5_5: ## %cond.store ; SSE4-NEXT: movlps %xmm2, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je LBB5_4 -; SSE4-NEXT: LBB5_3: ## %cond.store1 +; SSE4-NEXT: je LBB5_2 +; SSE4-NEXT: LBB5_6: ## %cond.store1 ; SSE4-NEXT: movhps %xmm2, 8(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je LBB5_6 -; SSE4-NEXT: LBB5_5: ## %cond.store3 +; SSE4-NEXT: je LBB5_3 +; SSE4-NEXT: LBB5_7: ## %cond.store3 ; SSE4-NEXT: movlps %xmm3, 16(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je LBB5_8 -; SSE4-NEXT: LBB5_7: ## %cond.store5 +; SSE4-NEXT: je LBB5_4 +; SSE4-NEXT: LBB5_8: ## %cond.store5 ; SSE4-NEXT: movhps %xmm3, 24(%rdi) ; SSE4-NEXT: retq ; @@ -429,17 +429,17 @@ define void @store_v2f32_i2(i2 %trigger, ptr %addr, <2 x float> %val) nounwind { ; SSE2-LABEL: store_v2f32_i2: ; SSE2: ## %bb.0: ; SSE2-NEXT: testb $1, %dil -; SSE2-NEXT: jne LBB6_1 -; SSE2-NEXT: ## %bb.2: ## %else -; SSE2-NEXT: testb $2, %dil ; SSE2-NEXT: jne LBB6_3 -; SSE2-NEXT: LBB6_4: ## %else2 +; SSE2-NEXT: ## %bb.1: ## %else +; SSE2-NEXT: testb $2, %dil +; SSE2-NEXT: jne LBB6_4 +; SSE2-NEXT: LBB6_2: ## %else2 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB6_1: ## %cond.store +; SSE2-NEXT: LBB6_3: ## %cond.store ; SSE2-NEXT: movss %xmm0, (%rsi) ; SSE2-NEXT: testb $2, %dil -; SSE2-NEXT: je LBB6_4 -; SSE2-NEXT: LBB6_3: ## %cond.store1 +; SSE2-NEXT: je LBB6_2 +; SSE2-NEXT: LBB6_4: ## %cond.store1 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1] ; SSE2-NEXT: movss %xmm0, 4(%rsi) ; SSE2-NEXT: retq @@ -447,17 +447,17 @@ define void @store_v2f32_i2(i2 %trigger, ptr %addr, <2 x float> %val) nounwind { ; SSE4-LABEL: store_v2f32_i2: ; SSE4: ## %bb.0: ; SSE4-NEXT: testb $1, %dil -; SSE4-NEXT: jne LBB6_1 -; SSE4-NEXT: ## %bb.2: ## %else -; SSE4-NEXT: testb $2, %dil ; SSE4-NEXT: jne LBB6_3 -; SSE4-NEXT: LBB6_4: ## %else2 +; SSE4-NEXT: ## %bb.1: ## %else +; SSE4-NEXT: testb $2, %dil +; SSE4-NEXT: jne LBB6_4 +; SSE4-NEXT: LBB6_2: ## %else2 ; SSE4-NEXT: retq -; SSE4-NEXT: LBB6_1: ## %cond.store +; SSE4-NEXT: LBB6_3: ## %cond.store ; SSE4-NEXT: movss %xmm0, (%rsi) ; SSE4-NEXT: testb $2, %dil -; SSE4-NEXT: je LBB6_4 -; SSE4-NEXT: LBB6_3: ## %cond.store1 +; SSE4-NEXT: je LBB6_2 +; SSE4-NEXT: LBB6_4: ## %cond.store1 ; SSE4-NEXT: extractps $1, %xmm0, 4(%rsi) ; SSE4-NEXT: retq ; @@ -521,17 +521,17 @@ define void @store_v2f32_v2i32(<2 x i32> %trigger, ptr %addr, <2 x float> %val) ; SSE2-NEXT: pcmpeqd %xmm0, %xmm2 ; SSE2-NEXT: movmskpd %xmm2, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB7_1 -; SSE2-NEXT: ## %bb.2: ## %else -; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: jne LBB7_3 -; SSE2-NEXT: LBB7_4: ## %else2 +; SSE2-NEXT: ## %bb.1: ## %else +; SSE2-NEXT: testb $2, %al +; SSE2-NEXT: jne LBB7_4 +; SSE2-NEXT: LBB7_2: ## %else2 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB7_1: ## %cond.store +; SSE2-NEXT: LBB7_3: ## %cond.store ; SSE2-NEXT: movss %xmm1, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB7_4 -; SSE2-NEXT: LBB7_3: ## %cond.store1 +; SSE2-NEXT: je LBB7_2 +; SSE2-NEXT: LBB7_4: ## %cond.store1 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,1,1] ; SSE2-NEXT: movss %xmm1, 4(%rdi) ; SSE2-NEXT: retq @@ -543,17 +543,17 @@ define void @store_v2f32_v2i32(<2 x i32> %trigger, ptr %addr, <2 x float> %val) ; SSE4-NEXT: pmovsxdq %xmm2, %xmm0 ; SSE4-NEXT: movmskpd %xmm0, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne LBB7_1 -; SSE4-NEXT: ## %bb.2: ## %else -; SSE4-NEXT: testb $2, %al ; SSE4-NEXT: jne LBB7_3 -; SSE4-NEXT: LBB7_4: ## %else2 +; SSE4-NEXT: ## %bb.1: ## %else +; SSE4-NEXT: testb $2, %al +; SSE4-NEXT: jne LBB7_4 +; SSE4-NEXT: LBB7_2: ## %else2 ; SSE4-NEXT: retq -; SSE4-NEXT: LBB7_1: ## %cond.store +; SSE4-NEXT: LBB7_3: ## %cond.store ; SSE4-NEXT: movss %xmm1, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je LBB7_4 -; SSE4-NEXT: LBB7_3: ## %cond.store1 +; SSE4-NEXT: je LBB7_2 +; SSE4-NEXT: LBB7_4: ## %cond.store1 ; SSE4-NEXT: extractps $1, %xmm1, 4(%rdi) ; SSE4-NEXT: retq ; @@ -609,35 +609,35 @@ define void @store_v4f32_i4(<4 x float> %x, ptr %ptr, <4 x float> %y, i4 %trigge ; SSE2-LABEL: store_v4f32_i4: ; SSE2: ## %bb.0: ; SSE2-NEXT: testb $1, %sil -; SSE2-NEXT: jne LBB8_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB8_5 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %sil -; SSE2-NEXT: jne LBB8_3 -; SSE2-NEXT: LBB8_4: ## %else2 +; SSE2-NEXT: jne LBB8_6 +; SSE2-NEXT: LBB8_2: ## %else2 ; SSE2-NEXT: testb $4, %sil -; SSE2-NEXT: jne LBB8_5 -; SSE2-NEXT: LBB8_6: ## %else4 -; SSE2-NEXT: testb $8, %sil ; SSE2-NEXT: jne LBB8_7 -; SSE2-NEXT: LBB8_8: ## %else6 +; SSE2-NEXT: LBB8_3: ## %else4 +; SSE2-NEXT: testb $8, %sil +; SSE2-NEXT: jne LBB8_8 +; SSE2-NEXT: LBB8_4: ## %else6 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB8_1: ## %cond.store +; SSE2-NEXT: LBB8_5: ## %cond.store ; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: testb $2, %sil -; SSE2-NEXT: je LBB8_4 -; SSE2-NEXT: LBB8_3: ## %cond.store1 +; SSE2-NEXT: je LBB8_2 +; SSE2-NEXT: LBB8_6: ## %cond.store1 ; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1] ; SSE2-NEXT: movss %xmm1, 4(%rdi) ; SSE2-NEXT: testb $4, %sil -; SSE2-NEXT: je LBB8_6 -; SSE2-NEXT: LBB8_5: ## %cond.store3 +; SSE2-NEXT: je LBB8_3 +; SSE2-NEXT: LBB8_7: ## %cond.store3 ; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: movss %xmm1, 8(%rdi) ; SSE2-NEXT: testb $8, %sil -; SSE2-NEXT: je LBB8_8 -; SSE2-NEXT: LBB8_7: ## %cond.store5 +; SSE2-NEXT: je LBB8_4 +; SSE2-NEXT: LBB8_8: ## %cond.store5 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: movss %xmm0, 12(%rdi) ; SSE2-NEXT: retq @@ -645,31 +645,31 @@ define void @store_v4f32_i4(<4 x float> %x, ptr %ptr, <4 x float> %y, i4 %trigge ; SSE4-LABEL: store_v4f32_i4: ; SSE4: ## %bb.0: ; SSE4-NEXT: testb $1, %sil -; SSE4-NEXT: jne LBB8_1 -; SSE4-NEXT: ## %bb.2: ## %else +; SSE4-NEXT: jne LBB8_5 +; SSE4-NEXT: ## %bb.1: ## %else ; SSE4-NEXT: testb $2, %sil -; SSE4-NEXT: jne LBB8_3 -; SSE4-NEXT: LBB8_4: ## %else2 +; SSE4-NEXT: jne LBB8_6 +; SSE4-NEXT: LBB8_2: ## %else2 ; SSE4-NEXT: testb $4, %sil -; SSE4-NEXT: jne LBB8_5 -; SSE4-NEXT: LBB8_6: ## %else4 -; SSE4-NEXT: testb $8, %sil ; SSE4-NEXT: jne LBB8_7 -; SSE4-NEXT: LBB8_8: ## %else6 +; SSE4-NEXT: LBB8_3: ## %else4 +; SSE4-NEXT: testb $8, %sil +; SSE4-NEXT: jne LBB8_8 +; SSE4-NEXT: LBB8_4: ## %else6 ; SSE4-NEXT: retq -; SSE4-NEXT: LBB8_1: ## %cond.store +; SSE4-NEXT: LBB8_5: ## %cond.store ; SSE4-NEXT: movss %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %sil -; SSE4-NEXT: je LBB8_4 -; SSE4-NEXT: LBB8_3: ## %cond.store1 +; SSE4-NEXT: je LBB8_2 +; SSE4-NEXT: LBB8_6: ## %cond.store1 ; SSE4-NEXT: extractps $1, %xmm0, 4(%rdi) ; SSE4-NEXT: testb $4, %sil -; SSE4-NEXT: je LBB8_6 -; SSE4-NEXT: LBB8_5: ## %cond.store3 +; SSE4-NEXT: je LBB8_3 +; SSE4-NEXT: LBB8_7: ## %cond.store3 ; SSE4-NEXT: extractps $2, %xmm0, 8(%rdi) ; SSE4-NEXT: testb $8, %sil -; SSE4-NEXT: je LBB8_8 -; SSE4-NEXT: LBB8_7: ## %cond.store5 +; SSE4-NEXT: je LBB8_4 +; SSE4-NEXT: LBB8_8: ## %cond.store5 ; SSE4-NEXT: extractps $3, %xmm0, 12(%rdi) ; SSE4-NEXT: retq ; @@ -731,35 +731,35 @@ define void @store_v4f32_v4i32(<4 x float> %x, ptr %ptr, <4 x float> %y, <4 x i3 ; SSE2: ## %bb.0: ; SSE2-NEXT: movmskps %xmm2, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB9_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB9_5 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB9_3 -; SSE2-NEXT: LBB9_4: ## %else2 +; SSE2-NEXT: jne LBB9_6 +; SSE2-NEXT: LBB9_2: ## %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB9_5 -; SSE2-NEXT: LBB9_6: ## %else4 -; SSE2-NEXT: testb $8, %al ; SSE2-NEXT: jne LBB9_7 -; SSE2-NEXT: LBB9_8: ## %else6 +; SSE2-NEXT: LBB9_3: ## %else4 +; SSE2-NEXT: testb $8, %al +; SSE2-NEXT: jne LBB9_8 +; SSE2-NEXT: LBB9_4: ## %else6 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB9_1: ## %cond.store +; SSE2-NEXT: LBB9_5: ## %cond.store ; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB9_4 -; SSE2-NEXT: LBB9_3: ## %cond.store1 +; SSE2-NEXT: je LBB9_2 +; SSE2-NEXT: LBB9_6: ## %cond.store1 ; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1] ; SSE2-NEXT: movss %xmm1, 4(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB9_6 -; SSE2-NEXT: LBB9_5: ## %cond.store3 +; SSE2-NEXT: je LBB9_3 +; SSE2-NEXT: LBB9_7: ## %cond.store3 ; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: movss %xmm1, 8(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB9_8 -; SSE2-NEXT: LBB9_7: ## %cond.store5 +; SSE2-NEXT: je LBB9_4 +; SSE2-NEXT: LBB9_8: ## %cond.store5 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: movss %xmm0, 12(%rdi) ; SSE2-NEXT: retq @@ -768,31 +768,31 @@ define void @store_v4f32_v4i32(<4 x float> %x, ptr %ptr, <4 x float> %y, <4 x i3 ; SSE4: ## %bb.0: ; SSE4-NEXT: movmskps %xmm2, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne LBB9_1 -; SSE4-NEXT: ## %bb.2: ## %else +; SSE4-NEXT: jne LBB9_5 +; SSE4-NEXT: ## %bb.1: ## %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne LBB9_3 -; SSE4-NEXT: LBB9_4: ## %else2 +; SSE4-NEXT: jne LBB9_6 +; SSE4-NEXT: LBB9_2: ## %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne LBB9_5 -; SSE4-NEXT: LBB9_6: ## %else4 -; SSE4-NEXT: testb $8, %al ; SSE4-NEXT: jne LBB9_7 -; SSE4-NEXT: LBB9_8: ## %else6 +; SSE4-NEXT: LBB9_3: ## %else4 +; SSE4-NEXT: testb $8, %al +; SSE4-NEXT: jne LBB9_8 +; SSE4-NEXT: LBB9_4: ## %else6 ; SSE4-NEXT: retq -; SSE4-NEXT: LBB9_1: ## %cond.store +; SSE4-NEXT: LBB9_5: ## %cond.store ; SSE4-NEXT: movss %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je LBB9_4 -; SSE4-NEXT: LBB9_3: ## %cond.store1 +; SSE4-NEXT: je LBB9_2 +; SSE4-NEXT: LBB9_6: ## %cond.store1 ; SSE4-NEXT: extractps $1, %xmm0, 4(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je LBB9_6 -; SSE4-NEXT: LBB9_5: ## %cond.store3 +; SSE4-NEXT: je LBB9_3 +; SSE4-NEXT: LBB9_7: ## %cond.store3 ; SSE4-NEXT: extractps $2, %xmm0, 8(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je LBB9_8 -; SSE4-NEXT: LBB9_7: ## %cond.store5 +; SSE4-NEXT: je LBB9_4 +; SSE4-NEXT: LBB9_8: ## %cond.store5 ; SSE4-NEXT: extractps $3, %xmm0, 12(%rdi) ; SSE4-NEXT: retq ; @@ -841,68 +841,68 @@ define void @store_v8f32_i8(<8 x float> %x, ptr %ptr, <8 x float> %y, i8 %trigge ; SSE2-LABEL: store_v8f32_i8: ; SSE2: ## %bb.0: ; SSE2-NEXT: testb $1, %sil -; SSE2-NEXT: jne LBB10_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB10_9 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %sil -; SSE2-NEXT: jne LBB10_3 -; SSE2-NEXT: LBB10_4: ## %else2 +; SSE2-NEXT: jne LBB10_10 +; SSE2-NEXT: LBB10_2: ## %else2 ; SSE2-NEXT: testb $4, %sil -; SSE2-NEXT: jne LBB10_5 -; SSE2-NEXT: LBB10_6: ## %else4 +; SSE2-NEXT: jne LBB10_11 +; SSE2-NEXT: LBB10_3: ## %else4 ; SSE2-NEXT: testb $8, %sil -; SSE2-NEXT: jne LBB10_7 -; SSE2-NEXT: LBB10_8: ## %else6 +; SSE2-NEXT: jne LBB10_12 +; SSE2-NEXT: LBB10_4: ## %else6 ; SSE2-NEXT: testb $16, %sil -; SSE2-NEXT: jne LBB10_9 -; SSE2-NEXT: LBB10_10: ## %else8 +; SSE2-NEXT: jne LBB10_13 +; SSE2-NEXT: LBB10_5: ## %else8 ; SSE2-NEXT: testb $32, %sil -; SSE2-NEXT: jne LBB10_11 -; SSE2-NEXT: LBB10_12: ## %else10 +; SSE2-NEXT: jne LBB10_14 +; SSE2-NEXT: LBB10_6: ## %else10 ; SSE2-NEXT: testb $64, %sil -; SSE2-NEXT: jne LBB10_13 -; SSE2-NEXT: LBB10_14: ## %else12 -; SSE2-NEXT: testb $-128, %sil ; SSE2-NEXT: jne LBB10_15 -; SSE2-NEXT: LBB10_16: ## %else14 +; SSE2-NEXT: LBB10_7: ## %else12 +; SSE2-NEXT: testb $-128, %sil +; SSE2-NEXT: jne LBB10_16 +; SSE2-NEXT: LBB10_8: ## %else14 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB10_1: ## %cond.store +; SSE2-NEXT: LBB10_9: ## %cond.store ; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: testb $2, %sil -; SSE2-NEXT: je LBB10_4 -; SSE2-NEXT: LBB10_3: ## %cond.store1 +; SSE2-NEXT: je LBB10_2 +; SSE2-NEXT: LBB10_10: ## %cond.store1 ; SSE2-NEXT: movaps %xmm0, %xmm2 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm0[1,1] ; SSE2-NEXT: movss %xmm2, 4(%rdi) ; SSE2-NEXT: testb $4, %sil -; SSE2-NEXT: je LBB10_6 -; SSE2-NEXT: LBB10_5: ## %cond.store3 +; SSE2-NEXT: je LBB10_3 +; SSE2-NEXT: LBB10_11: ## %cond.store3 ; SSE2-NEXT: movaps %xmm0, %xmm2 ; SSE2-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1] ; SSE2-NEXT: movss %xmm2, 8(%rdi) ; SSE2-NEXT: testb $8, %sil -; SSE2-NEXT: je LBB10_8 -; SSE2-NEXT: LBB10_7: ## %cond.store5 +; SSE2-NEXT: je LBB10_4 +; SSE2-NEXT: LBB10_12: ## %cond.store5 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: movss %xmm0, 12(%rdi) ; SSE2-NEXT: testb $16, %sil -; SSE2-NEXT: je LBB10_10 -; SSE2-NEXT: LBB10_9: ## %cond.store7 +; SSE2-NEXT: je LBB10_5 +; SSE2-NEXT: LBB10_13: ## %cond.store7 ; SSE2-NEXT: movss %xmm1, 16(%rdi) ; SSE2-NEXT: testb $32, %sil -; SSE2-NEXT: je LBB10_12 -; SSE2-NEXT: LBB10_11: ## %cond.store9 +; SSE2-NEXT: je LBB10_6 +; SSE2-NEXT: LBB10_14: ## %cond.store9 ; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1] ; SSE2-NEXT: movss %xmm0, 20(%rdi) ; SSE2-NEXT: testb $64, %sil -; SSE2-NEXT: je LBB10_14 -; SSE2-NEXT: LBB10_13: ## %cond.store11 +; SSE2-NEXT: je LBB10_7 +; SSE2-NEXT: LBB10_15: ## %cond.store11 ; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1] ; SSE2-NEXT: movss %xmm0, 24(%rdi) ; SSE2-NEXT: testb $-128, %sil -; SSE2-NEXT: je LBB10_16 -; SSE2-NEXT: LBB10_15: ## %cond.store13 +; SSE2-NEXT: je LBB10_8 +; SSE2-NEXT: LBB10_16: ## %cond.store13 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE2-NEXT: movss %xmm1, 28(%rdi) ; SSE2-NEXT: retq @@ -910,59 +910,59 @@ define void @store_v8f32_i8(<8 x float> %x, ptr %ptr, <8 x float> %y, i8 %trigge ; SSE4-LABEL: store_v8f32_i8: ; SSE4: ## %bb.0: ; SSE4-NEXT: testb $1, %sil -; SSE4-NEXT: jne LBB10_1 -; SSE4-NEXT: ## %bb.2: ## %else +; SSE4-NEXT: jne LBB10_9 +; SSE4-NEXT: ## %bb.1: ## %else ; SSE4-NEXT: testb $2, %sil -; SSE4-NEXT: jne LBB10_3 -; SSE4-NEXT: LBB10_4: ## %else2 +; SSE4-NEXT: jne LBB10_10 +; SSE4-NEXT: LBB10_2: ## %else2 ; SSE4-NEXT: testb $4, %sil -; SSE4-NEXT: jne LBB10_5 -; SSE4-NEXT: LBB10_6: ## %else4 +; SSE4-NEXT: jne LBB10_11 +; SSE4-NEXT: LBB10_3: ## %else4 ; SSE4-NEXT: testb $8, %sil -; SSE4-NEXT: jne LBB10_7 -; SSE4-NEXT: LBB10_8: ## %else6 +; SSE4-NEXT: jne LBB10_12 +; SSE4-NEXT: LBB10_4: ## %else6 ; SSE4-NEXT: testb $16, %sil -; SSE4-NEXT: jne LBB10_9 -; SSE4-NEXT: LBB10_10: ## %else8 +; SSE4-NEXT: jne LBB10_13 +; SSE4-NEXT: LBB10_5: ## %else8 ; SSE4-NEXT: testb $32, %sil -; SSE4-NEXT: jne LBB10_11 -; SSE4-NEXT: LBB10_12: ## %else10 +; SSE4-NEXT: jne LBB10_14 +; SSE4-NEXT: LBB10_6: ## %else10 ; SSE4-NEXT: testb $64, %sil -; SSE4-NEXT: jne LBB10_13 -; SSE4-NEXT: LBB10_14: ## %else12 -; SSE4-NEXT: testb $-128, %sil ; SSE4-NEXT: jne LBB10_15 -; SSE4-NEXT: LBB10_16: ## %else14 +; SSE4-NEXT: LBB10_7: ## %else12 +; SSE4-NEXT: testb $-128, %sil +; SSE4-NEXT: jne LBB10_16 +; SSE4-NEXT: LBB10_8: ## %else14 ; SSE4-NEXT: retq -; SSE4-NEXT: LBB10_1: ## %cond.store +; SSE4-NEXT: LBB10_9: ## %cond.store ; SSE4-NEXT: movss %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %sil -; SSE4-NEXT: je LBB10_4 -; SSE4-NEXT: LBB10_3: ## %cond.store1 +; SSE4-NEXT: je LBB10_2 +; SSE4-NEXT: LBB10_10: ## %cond.store1 ; SSE4-NEXT: extractps $1, %xmm0, 4(%rdi) ; SSE4-NEXT: testb $4, %sil -; SSE4-NEXT: je LBB10_6 -; SSE4-NEXT: LBB10_5: ## %cond.store3 +; SSE4-NEXT: je LBB10_3 +; SSE4-NEXT: LBB10_11: ## %cond.store3 ; SSE4-NEXT: extractps $2, %xmm0, 8(%rdi) ; SSE4-NEXT: testb $8, %sil -; SSE4-NEXT: je LBB10_8 -; SSE4-NEXT: LBB10_7: ## %cond.store5 +; SSE4-NEXT: je LBB10_4 +; SSE4-NEXT: LBB10_12: ## %cond.store5 ; SSE4-NEXT: extractps $3, %xmm0, 12(%rdi) ; SSE4-NEXT: testb $16, %sil -; SSE4-NEXT: je LBB10_10 -; SSE4-NEXT: LBB10_9: ## %cond.store7 +; SSE4-NEXT: je LBB10_5 +; SSE4-NEXT: LBB10_13: ## %cond.store7 ; SSE4-NEXT: movss %xmm1, 16(%rdi) ; SSE4-NEXT: testb $32, %sil -; SSE4-NEXT: je LBB10_12 -; SSE4-NEXT: LBB10_11: ## %cond.store9 +; SSE4-NEXT: je LBB10_6 +; SSE4-NEXT: LBB10_14: ## %cond.store9 ; SSE4-NEXT: extractps $1, %xmm1, 20(%rdi) ; SSE4-NEXT: testb $64, %sil -; SSE4-NEXT: je LBB10_14 -; SSE4-NEXT: LBB10_13: ## %cond.store11 +; SSE4-NEXT: je LBB10_7 +; SSE4-NEXT: LBB10_15: ## %cond.store11 ; SSE4-NEXT: extractps $2, %xmm1, 24(%rdi) ; SSE4-NEXT: testb $-128, %sil -; SSE4-NEXT: je LBB10_16 -; SSE4-NEXT: LBB10_15: ## %cond.store13 +; SSE4-NEXT: je LBB10_8 +; SSE4-NEXT: LBB10_16: ## %cond.store13 ; SSE4-NEXT: extractps $3, %xmm1, 28(%rdi) ; SSE4-NEXT: retq ; @@ -1032,68 +1032,68 @@ define void @store_v8f32_v8i32(<8 x float> %x, ptr %ptr, <8 x float> %y, <8 x i3 ; SSE2-NEXT: packsswb %xmm4, %xmm4 ; SSE2-NEXT: pmovmskb %xmm4, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB11_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB11_9 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB11_3 -; SSE2-NEXT: LBB11_4: ## %else2 +; SSE2-NEXT: jne LBB11_10 +; SSE2-NEXT: LBB11_2: ## %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB11_5 -; SSE2-NEXT: LBB11_6: ## %else4 +; SSE2-NEXT: jne LBB11_11 +; SSE2-NEXT: LBB11_3: ## %else4 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne LBB11_7 -; SSE2-NEXT: LBB11_8: ## %else6 +; SSE2-NEXT: jne LBB11_12 +; SSE2-NEXT: LBB11_4: ## %else6 ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: jne LBB11_9 -; SSE2-NEXT: LBB11_10: ## %else8 +; SSE2-NEXT: jne LBB11_13 +; SSE2-NEXT: LBB11_5: ## %else8 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: jne LBB11_11 -; SSE2-NEXT: LBB11_12: ## %else10 +; SSE2-NEXT: jne LBB11_14 +; SSE2-NEXT: LBB11_6: ## %else10 ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: jne LBB11_13 -; SSE2-NEXT: LBB11_14: ## %else12 -; SSE2-NEXT: testb $-128, %al ; SSE2-NEXT: jne LBB11_15 -; SSE2-NEXT: LBB11_16: ## %else14 +; SSE2-NEXT: LBB11_7: ## %else12 +; SSE2-NEXT: testb $-128, %al +; SSE2-NEXT: jne LBB11_16 +; SSE2-NEXT: LBB11_8: ## %else14 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB11_1: ## %cond.store +; SSE2-NEXT: LBB11_9: ## %cond.store ; SSE2-NEXT: movd %xmm0, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB11_4 -; SSE2-NEXT: LBB11_3: ## %cond.store1 +; SSE2-NEXT: je LBB11_2 +; SSE2-NEXT: LBB11_10: ## %cond.store1 ; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm0[1,1] ; SSE2-NEXT: movss %xmm2, 4(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB11_6 -; SSE2-NEXT: LBB11_5: ## %cond.store3 +; SSE2-NEXT: je LBB11_3 +; SSE2-NEXT: LBB11_11: ## %cond.store3 ; SSE2-NEXT: movaps %xmm0, %xmm2 ; SSE2-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1] ; SSE2-NEXT: movss %xmm2, 8(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB11_8 -; SSE2-NEXT: LBB11_7: ## %cond.store5 +; SSE2-NEXT: je LBB11_4 +; SSE2-NEXT: LBB11_12: ## %cond.store5 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: movss %xmm0, 12(%rdi) ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: je LBB11_10 -; SSE2-NEXT: LBB11_9: ## %cond.store7 +; SSE2-NEXT: je LBB11_5 +; SSE2-NEXT: LBB11_13: ## %cond.store7 ; SSE2-NEXT: movss %xmm1, 16(%rdi) ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je LBB11_12 -; SSE2-NEXT: LBB11_11: ## %cond.store9 +; SSE2-NEXT: je LBB11_6 +; SSE2-NEXT: LBB11_14: ## %cond.store9 ; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1] ; SSE2-NEXT: movss %xmm0, 20(%rdi) ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: je LBB11_14 -; SSE2-NEXT: LBB11_13: ## %cond.store11 +; SSE2-NEXT: je LBB11_7 +; SSE2-NEXT: LBB11_15: ## %cond.store11 ; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1] ; SSE2-NEXT: movss %xmm0, 24(%rdi) ; SSE2-NEXT: testb $-128, %al -; SSE2-NEXT: je LBB11_16 -; SSE2-NEXT: LBB11_15: ## %cond.store13 +; SSE2-NEXT: je LBB11_8 +; SSE2-NEXT: LBB11_16: ## %cond.store13 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE2-NEXT: movss %xmm1, 28(%rdi) ; SSE2-NEXT: retq @@ -1104,59 +1104,59 @@ define void @store_v8f32_v8i32(<8 x float> %x, ptr %ptr, <8 x float> %y, <8 x i3 ; SSE4-NEXT: packsswb %xmm4, %xmm4 ; SSE4-NEXT: pmovmskb %xmm4, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne LBB11_1 -; SSE4-NEXT: ## %bb.2: ## %else +; SSE4-NEXT: jne LBB11_9 +; SSE4-NEXT: ## %bb.1: ## %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne LBB11_3 -; SSE4-NEXT: LBB11_4: ## %else2 +; SSE4-NEXT: jne LBB11_10 +; SSE4-NEXT: LBB11_2: ## %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne LBB11_5 -; SSE4-NEXT: LBB11_6: ## %else4 +; SSE4-NEXT: jne LBB11_11 +; SSE4-NEXT: LBB11_3: ## %else4 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne LBB11_7 -; SSE4-NEXT: LBB11_8: ## %else6 +; SSE4-NEXT: jne LBB11_12 +; SSE4-NEXT: LBB11_4: ## %else6 ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: jne LBB11_9 -; SSE4-NEXT: LBB11_10: ## %else8 +; SSE4-NEXT: jne LBB11_13 +; SSE4-NEXT: LBB11_5: ## %else8 ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: jne LBB11_11 -; SSE4-NEXT: LBB11_12: ## %else10 +; SSE4-NEXT: jne LBB11_14 +; SSE4-NEXT: LBB11_6: ## %else10 ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: jne LBB11_13 -; SSE4-NEXT: LBB11_14: ## %else12 -; SSE4-NEXT: testb $-128, %al ; SSE4-NEXT: jne LBB11_15 -; SSE4-NEXT: LBB11_16: ## %else14 +; SSE4-NEXT: LBB11_7: ## %else12 +; SSE4-NEXT: testb $-128, %al +; SSE4-NEXT: jne LBB11_16 +; SSE4-NEXT: LBB11_8: ## %else14 ; SSE4-NEXT: retq -; SSE4-NEXT: LBB11_1: ## %cond.store +; SSE4-NEXT: LBB11_9: ## %cond.store ; SSE4-NEXT: movd %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je LBB11_4 -; SSE4-NEXT: LBB11_3: ## %cond.store1 +; SSE4-NEXT: je LBB11_2 +; SSE4-NEXT: LBB11_10: ## %cond.store1 ; SSE4-NEXT: pextrd $1, %xmm0, 4(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je LBB11_6 -; SSE4-NEXT: LBB11_5: ## %cond.store3 +; SSE4-NEXT: je LBB11_3 +; SSE4-NEXT: LBB11_11: ## %cond.store3 ; SSE4-NEXT: pextrd $2, %xmm0, 8(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je LBB11_8 -; SSE4-NEXT: LBB11_7: ## %cond.store5 +; SSE4-NEXT: je LBB11_4 +; SSE4-NEXT: LBB11_12: ## %cond.store5 ; SSE4-NEXT: pextrd $3, %xmm0, 12(%rdi) ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: je LBB11_10 -; SSE4-NEXT: LBB11_9: ## %cond.store7 +; SSE4-NEXT: je LBB11_5 +; SSE4-NEXT: LBB11_13: ## %cond.store7 ; SSE4-NEXT: movss %xmm1, 16(%rdi) ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: je LBB11_12 -; SSE4-NEXT: LBB11_11: ## %cond.store9 +; SSE4-NEXT: je LBB11_6 +; SSE4-NEXT: LBB11_14: ## %cond.store9 ; SSE4-NEXT: extractps $1, %xmm1, 20(%rdi) ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: je LBB11_14 -; SSE4-NEXT: LBB11_13: ## %cond.store11 +; SSE4-NEXT: je LBB11_7 +; SSE4-NEXT: LBB11_15: ## %cond.store11 ; SSE4-NEXT: extractps $2, %xmm1, 24(%rdi) ; SSE4-NEXT: testb $-128, %al -; SSE4-NEXT: je LBB11_16 -; SSE4-NEXT: LBB11_15: ## %cond.store13 +; SSE4-NEXT: je LBB11_8 +; SSE4-NEXT: LBB11_16: ## %cond.store13 ; SSE4-NEXT: extractps $3, %xmm1, 28(%rdi) ; SSE4-NEXT: retq ; @@ -1209,134 +1209,134 @@ define void @store_v16f32_i16(<16 x float> %x, ptr %ptr, <16 x float> %y, i16 %t ; SSE2-LABEL: store_v16f32_i16: ; SSE2: ## %bb.0: ; SSE2-NEXT: testb $1, %sil -; SSE2-NEXT: jne LBB12_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB12_17 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %sil -; SSE2-NEXT: jne LBB12_3 -; SSE2-NEXT: LBB12_4: ## %else2 +; SSE2-NEXT: jne LBB12_18 +; SSE2-NEXT: LBB12_2: ## %else2 ; SSE2-NEXT: testb $4, %sil -; SSE2-NEXT: jne LBB12_5 -; SSE2-NEXT: LBB12_6: ## %else4 +; SSE2-NEXT: jne LBB12_19 +; SSE2-NEXT: LBB12_3: ## %else4 ; SSE2-NEXT: testb $8, %sil -; SSE2-NEXT: jne LBB12_7 -; SSE2-NEXT: LBB12_8: ## %else6 +; SSE2-NEXT: jne LBB12_20 +; SSE2-NEXT: LBB12_4: ## %else6 ; SSE2-NEXT: testb $16, %sil -; SSE2-NEXT: jne LBB12_9 -; SSE2-NEXT: LBB12_10: ## %else8 +; SSE2-NEXT: jne LBB12_21 +; SSE2-NEXT: LBB12_5: ## %else8 ; SSE2-NEXT: testb $32, %sil -; SSE2-NEXT: jne LBB12_11 -; SSE2-NEXT: LBB12_12: ## %else10 +; SSE2-NEXT: jne LBB12_22 +; SSE2-NEXT: LBB12_6: ## %else10 ; SSE2-NEXT: testb $64, %sil -; SSE2-NEXT: jne LBB12_13 -; SSE2-NEXT: LBB12_14: ## %else12 +; SSE2-NEXT: jne LBB12_23 +; SSE2-NEXT: LBB12_7: ## %else12 ; SSE2-NEXT: testb %sil, %sil -; SSE2-NEXT: js LBB12_15 -; SSE2-NEXT: LBB12_16: ## %else14 +; SSE2-NEXT: js LBB12_24 +; SSE2-NEXT: LBB12_8: ## %else14 ; SSE2-NEXT: testl $256, %esi ## imm = 0x100 -; SSE2-NEXT: jne LBB12_17 -; SSE2-NEXT: LBB12_18: ## %else16 +; SSE2-NEXT: jne LBB12_25 +; SSE2-NEXT: LBB12_9: ## %else16 ; SSE2-NEXT: testl $512, %esi ## imm = 0x200 -; SSE2-NEXT: jne LBB12_19 -; SSE2-NEXT: LBB12_20: ## %else18 +; SSE2-NEXT: jne LBB12_26 +; SSE2-NEXT: LBB12_10: ## %else18 ; SSE2-NEXT: testl $1024, %esi ## imm = 0x400 -; SSE2-NEXT: jne LBB12_21 -; SSE2-NEXT: LBB12_22: ## %else20 +; SSE2-NEXT: jne LBB12_27 +; SSE2-NEXT: LBB12_11: ## %else20 ; SSE2-NEXT: testl $2048, %esi ## imm = 0x800 -; SSE2-NEXT: jne LBB12_23 -; SSE2-NEXT: LBB12_24: ## %else22 +; SSE2-NEXT: jne LBB12_28 +; SSE2-NEXT: LBB12_12: ## %else22 ; SSE2-NEXT: testl $4096, %esi ## imm = 0x1000 -; SSE2-NEXT: jne LBB12_25 -; SSE2-NEXT: LBB12_26: ## %else24 +; SSE2-NEXT: jne LBB12_29 +; SSE2-NEXT: LBB12_13: ## %else24 ; SSE2-NEXT: testl $8192, %esi ## imm = 0x2000 -; SSE2-NEXT: jne LBB12_27 -; SSE2-NEXT: LBB12_28: ## %else26 +; SSE2-NEXT: jne LBB12_30 +; SSE2-NEXT: LBB12_14: ## %else26 ; SSE2-NEXT: testl $16384, %esi ## imm = 0x4000 -; SSE2-NEXT: jne LBB12_29 -; SSE2-NEXT: LBB12_30: ## %else28 -; SSE2-NEXT: testl $32768, %esi ## imm = 0x8000 ; SSE2-NEXT: jne LBB12_31 -; SSE2-NEXT: LBB12_32: ## %else30 +; SSE2-NEXT: LBB12_15: ## %else28 +; SSE2-NEXT: testl $32768, %esi ## imm = 0x8000 +; SSE2-NEXT: jne LBB12_32 +; SSE2-NEXT: LBB12_16: ## %else30 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB12_1: ## %cond.store +; SSE2-NEXT: LBB12_17: ## %cond.store ; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: testb $2, %sil -; SSE2-NEXT: je LBB12_4 -; SSE2-NEXT: LBB12_3: ## %cond.store1 +; SSE2-NEXT: je LBB12_2 +; SSE2-NEXT: LBB12_18: ## %cond.store1 ; SSE2-NEXT: movaps %xmm0, %xmm4 ; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,1],xmm0[1,1] ; SSE2-NEXT: movss %xmm4, 4(%rdi) ; SSE2-NEXT: testb $4, %sil -; SSE2-NEXT: je LBB12_6 -; SSE2-NEXT: LBB12_5: ## %cond.store3 +; SSE2-NEXT: je LBB12_3 +; SSE2-NEXT: LBB12_19: ## %cond.store3 ; SSE2-NEXT: movaps %xmm0, %xmm4 ; SSE2-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm0[1] ; SSE2-NEXT: movss %xmm4, 8(%rdi) ; SSE2-NEXT: testb $8, %sil -; SSE2-NEXT: je LBB12_8 -; SSE2-NEXT: LBB12_7: ## %cond.store5 +; SSE2-NEXT: je LBB12_4 +; SSE2-NEXT: LBB12_20: ## %cond.store5 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: movss %xmm0, 12(%rdi) ; SSE2-NEXT: testb $16, %sil -; SSE2-NEXT: je LBB12_10 -; SSE2-NEXT: LBB12_9: ## %cond.store7 +; SSE2-NEXT: je LBB12_5 +; SSE2-NEXT: LBB12_21: ## %cond.store7 ; SSE2-NEXT: movss %xmm1, 16(%rdi) ; SSE2-NEXT: testb $32, %sil -; SSE2-NEXT: je LBB12_12 -; SSE2-NEXT: LBB12_11: ## %cond.store9 +; SSE2-NEXT: je LBB12_6 +; SSE2-NEXT: LBB12_22: ## %cond.store9 ; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1] ; SSE2-NEXT: movss %xmm0, 20(%rdi) ; SSE2-NEXT: testb $64, %sil -; SSE2-NEXT: je LBB12_14 -; SSE2-NEXT: LBB12_13: ## %cond.store11 +; SSE2-NEXT: je LBB12_7 +; SSE2-NEXT: LBB12_23: ## %cond.store11 ; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1] ; SSE2-NEXT: movss %xmm0, 24(%rdi) ; SSE2-NEXT: testb %sil, %sil -; SSE2-NEXT: jns LBB12_16 -; SSE2-NEXT: LBB12_15: ## %cond.store13 +; SSE2-NEXT: jns LBB12_8 +; SSE2-NEXT: LBB12_24: ## %cond.store13 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE2-NEXT: movss %xmm1, 28(%rdi) ; SSE2-NEXT: testl $256, %esi ## imm = 0x100 -; SSE2-NEXT: je LBB12_18 -; SSE2-NEXT: LBB12_17: ## %cond.store15 +; SSE2-NEXT: je LBB12_9 +; SSE2-NEXT: LBB12_25: ## %cond.store15 ; SSE2-NEXT: movss %xmm2, 32(%rdi) ; SSE2-NEXT: testl $512, %esi ## imm = 0x200 -; SSE2-NEXT: je LBB12_20 -; SSE2-NEXT: LBB12_19: ## %cond.store17 +; SSE2-NEXT: je LBB12_10 +; SSE2-NEXT: LBB12_26: ## %cond.store17 ; SSE2-NEXT: movaps %xmm2, %xmm0 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm2[1,1] ; SSE2-NEXT: movss %xmm0, 36(%rdi) ; SSE2-NEXT: testl $1024, %esi ## imm = 0x400 -; SSE2-NEXT: je LBB12_22 -; SSE2-NEXT: LBB12_21: ## %cond.store19 +; SSE2-NEXT: je LBB12_11 +; SSE2-NEXT: LBB12_27: ## %cond.store19 ; SSE2-NEXT: movaps %xmm2, %xmm0 ; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm2[1] ; SSE2-NEXT: movss %xmm0, 40(%rdi) ; SSE2-NEXT: testl $2048, %esi ## imm = 0x800 -; SSE2-NEXT: je LBB12_24 -; SSE2-NEXT: LBB12_23: ## %cond.store21 +; SSE2-NEXT: je LBB12_12 +; SSE2-NEXT: LBB12_28: ## %cond.store21 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3] ; SSE2-NEXT: movss %xmm2, 44(%rdi) ; SSE2-NEXT: testl $4096, %esi ## imm = 0x1000 -; SSE2-NEXT: je LBB12_26 -; SSE2-NEXT: LBB12_25: ## %cond.store23 +; SSE2-NEXT: je LBB12_13 +; SSE2-NEXT: LBB12_29: ## %cond.store23 ; SSE2-NEXT: movss %xmm3, 48(%rdi) ; SSE2-NEXT: testl $8192, %esi ## imm = 0x2000 -; SSE2-NEXT: je LBB12_28 -; SSE2-NEXT: LBB12_27: ## %cond.store25 +; SSE2-NEXT: je LBB12_14 +; SSE2-NEXT: LBB12_30: ## %cond.store25 ; SSE2-NEXT: movaps %xmm3, %xmm0 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm3[1,1] ; SSE2-NEXT: movss %xmm0, 52(%rdi) ; SSE2-NEXT: testl $16384, %esi ## imm = 0x4000 -; SSE2-NEXT: je LBB12_30 -; SSE2-NEXT: LBB12_29: ## %cond.store27 +; SSE2-NEXT: je LBB12_15 +; SSE2-NEXT: LBB12_31: ## %cond.store27 ; SSE2-NEXT: movaps %xmm3, %xmm0 ; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm3[1] ; SSE2-NEXT: movss %xmm0, 56(%rdi) ; SSE2-NEXT: testl $32768, %esi ## imm = 0x8000 -; SSE2-NEXT: je LBB12_32 -; SSE2-NEXT: LBB12_31: ## %cond.store29 +; SSE2-NEXT: je LBB12_16 +; SSE2-NEXT: LBB12_32: ## %cond.store29 ; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3] ; SSE2-NEXT: movss %xmm3, 60(%rdi) ; SSE2-NEXT: retq @@ -1344,115 +1344,115 @@ define void @store_v16f32_i16(<16 x float> %x, ptr %ptr, <16 x float> %y, i16 %t ; SSE4-LABEL: store_v16f32_i16: ; SSE4: ## %bb.0: ; SSE4-NEXT: testb $1, %sil -; SSE4-NEXT: jne LBB12_1 -; SSE4-NEXT: ## %bb.2: ## %else +; SSE4-NEXT: jne LBB12_17 +; SSE4-NEXT: ## %bb.1: ## %else ; SSE4-NEXT: testb $2, %sil -; SSE4-NEXT: jne LBB12_3 -; SSE4-NEXT: LBB12_4: ## %else2 +; SSE4-NEXT: jne LBB12_18 +; SSE4-NEXT: LBB12_2: ## %else2 ; SSE4-NEXT: testb $4, %sil -; SSE4-NEXT: jne LBB12_5 -; SSE4-NEXT: LBB12_6: ## %else4 +; SSE4-NEXT: jne LBB12_19 +; SSE4-NEXT: LBB12_3: ## %else4 ; SSE4-NEXT: testb $8, %sil -; SSE4-NEXT: jne LBB12_7 -; SSE4-NEXT: LBB12_8: ## %else6 +; SSE4-NEXT: jne LBB12_20 +; SSE4-NEXT: LBB12_4: ## %else6 ; SSE4-NEXT: testb $16, %sil -; SSE4-NEXT: jne LBB12_9 -; SSE4-NEXT: LBB12_10: ## %else8 +; SSE4-NEXT: jne LBB12_21 +; SSE4-NEXT: LBB12_5: ## %else8 ; SSE4-NEXT: testb $32, %sil -; SSE4-NEXT: jne LBB12_11 -; SSE4-NEXT: LBB12_12: ## %else10 +; SSE4-NEXT: jne LBB12_22 +; SSE4-NEXT: LBB12_6: ## %else10 ; SSE4-NEXT: testb $64, %sil -; SSE4-NEXT: jne LBB12_13 -; SSE4-NEXT: LBB12_14: ## %else12 +; SSE4-NEXT: jne LBB12_23 +; SSE4-NEXT: LBB12_7: ## %else12 ; SSE4-NEXT: testb %sil, %sil -; SSE4-NEXT: js LBB12_15 -; SSE4-NEXT: LBB12_16: ## %else14 +; SSE4-NEXT: js LBB12_24 +; SSE4-NEXT: LBB12_8: ## %else14 ; SSE4-NEXT: testl $256, %esi ## imm = 0x100 -; SSE4-NEXT: jne LBB12_17 -; SSE4-NEXT: LBB12_18: ## %else16 +; SSE4-NEXT: jne LBB12_25 +; SSE4-NEXT: LBB12_9: ## %else16 ; SSE4-NEXT: testl $512, %esi ## imm = 0x200 -; SSE4-NEXT: jne LBB12_19 -; SSE4-NEXT: LBB12_20: ## %else18 +; SSE4-NEXT: jne LBB12_26 +; SSE4-NEXT: LBB12_10: ## %else18 ; SSE4-NEXT: testl $1024, %esi ## imm = 0x400 -; SSE4-NEXT: jne LBB12_21 -; SSE4-NEXT: LBB12_22: ## %else20 +; SSE4-NEXT: jne LBB12_27 +; SSE4-NEXT: LBB12_11: ## %else20 ; SSE4-NEXT: testl $2048, %esi ## imm = 0x800 -; SSE4-NEXT: jne LBB12_23 -; SSE4-NEXT: LBB12_24: ## %else22 +; SSE4-NEXT: jne LBB12_28 +; SSE4-NEXT: LBB12_12: ## %else22 ; SSE4-NEXT: testl $4096, %esi ## imm = 0x1000 -; SSE4-NEXT: jne LBB12_25 -; SSE4-NEXT: LBB12_26: ## %else24 +; SSE4-NEXT: jne LBB12_29 +; SSE4-NEXT: LBB12_13: ## %else24 ; SSE4-NEXT: testl $8192, %esi ## imm = 0x2000 -; SSE4-NEXT: jne LBB12_27 -; SSE4-NEXT: LBB12_28: ## %else26 +; SSE4-NEXT: jne LBB12_30 +; SSE4-NEXT: LBB12_14: ## %else26 ; SSE4-NEXT: testl $16384, %esi ## imm = 0x4000 -; SSE4-NEXT: jne LBB12_29 -; SSE4-NEXT: LBB12_30: ## %else28 -; SSE4-NEXT: testl $32768, %esi ## imm = 0x8000 ; SSE4-NEXT: jne LBB12_31 -; SSE4-NEXT: LBB12_32: ## %else30 +; SSE4-NEXT: LBB12_15: ## %else28 +; SSE4-NEXT: testl $32768, %esi ## imm = 0x8000 +; SSE4-NEXT: jne LBB12_32 +; SSE4-NEXT: LBB12_16: ## %else30 ; SSE4-NEXT: retq -; SSE4-NEXT: LBB12_1: ## %cond.store +; SSE4-NEXT: LBB12_17: ## %cond.store ; SSE4-NEXT: movss %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %sil -; SSE4-NEXT: je LBB12_4 -; SSE4-NEXT: LBB12_3: ## %cond.store1 +; SSE4-NEXT: je LBB12_2 +; SSE4-NEXT: LBB12_18: ## %cond.store1 ; SSE4-NEXT: extractps $1, %xmm0, 4(%rdi) ; SSE4-NEXT: testb $4, %sil -; SSE4-NEXT: je LBB12_6 -; SSE4-NEXT: LBB12_5: ## %cond.store3 +; SSE4-NEXT: je LBB12_3 +; SSE4-NEXT: LBB12_19: ## %cond.store3 ; SSE4-NEXT: extractps $2, %xmm0, 8(%rdi) ; SSE4-NEXT: testb $8, %sil -; SSE4-NEXT: je LBB12_8 -; SSE4-NEXT: LBB12_7: ## %cond.store5 +; SSE4-NEXT: je LBB12_4 +; SSE4-NEXT: LBB12_20: ## %cond.store5 ; SSE4-NEXT: extractps $3, %xmm0, 12(%rdi) ; SSE4-NEXT: testb $16, %sil -; SSE4-NEXT: je LBB12_10 -; SSE4-NEXT: LBB12_9: ## %cond.store7 +; SSE4-NEXT: je LBB12_5 +; SSE4-NEXT: LBB12_21: ## %cond.store7 ; SSE4-NEXT: movss %xmm1, 16(%rdi) ; SSE4-NEXT: testb $32, %sil -; SSE4-NEXT: je LBB12_12 -; SSE4-NEXT: LBB12_11: ## %cond.store9 +; SSE4-NEXT: je LBB12_6 +; SSE4-NEXT: LBB12_22: ## %cond.store9 ; SSE4-NEXT: extractps $1, %xmm1, 20(%rdi) ; SSE4-NEXT: testb $64, %sil -; SSE4-NEXT: je LBB12_14 -; SSE4-NEXT: LBB12_13: ## %cond.store11 +; SSE4-NEXT: je LBB12_7 +; SSE4-NEXT: LBB12_23: ## %cond.store11 ; SSE4-NEXT: extractps $2, %xmm1, 24(%rdi) ; SSE4-NEXT: testb %sil, %sil -; SSE4-NEXT: jns LBB12_16 -; SSE4-NEXT: LBB12_15: ## %cond.store13 +; SSE4-NEXT: jns LBB12_8 +; SSE4-NEXT: LBB12_24: ## %cond.store13 ; SSE4-NEXT: extractps $3, %xmm1, 28(%rdi) ; SSE4-NEXT: testl $256, %esi ## imm = 0x100 -; SSE4-NEXT: je LBB12_18 -; SSE4-NEXT: LBB12_17: ## %cond.store15 +; SSE4-NEXT: je LBB12_9 +; SSE4-NEXT: LBB12_25: ## %cond.store15 ; SSE4-NEXT: movss %xmm2, 32(%rdi) ; SSE4-NEXT: testl $512, %esi ## imm = 0x200 -; SSE4-NEXT: je LBB12_20 -; SSE4-NEXT: LBB12_19: ## %cond.store17 +; SSE4-NEXT: je LBB12_10 +; SSE4-NEXT: LBB12_26: ## %cond.store17 ; SSE4-NEXT: extractps $1, %xmm2, 36(%rdi) ; SSE4-NEXT: testl $1024, %esi ## imm = 0x400 -; SSE4-NEXT: je LBB12_22 -; SSE4-NEXT: LBB12_21: ## %cond.store19 +; SSE4-NEXT: je LBB12_11 +; SSE4-NEXT: LBB12_27: ## %cond.store19 ; SSE4-NEXT: extractps $2, %xmm2, 40(%rdi) ; SSE4-NEXT: testl $2048, %esi ## imm = 0x800 -; SSE4-NEXT: je LBB12_24 -; SSE4-NEXT: LBB12_23: ## %cond.store21 +; SSE4-NEXT: je LBB12_12 +; SSE4-NEXT: LBB12_28: ## %cond.store21 ; SSE4-NEXT: extractps $3, %xmm2, 44(%rdi) ; SSE4-NEXT: testl $4096, %esi ## imm = 0x1000 -; SSE4-NEXT: je LBB12_26 -; SSE4-NEXT: LBB12_25: ## %cond.store23 +; SSE4-NEXT: je LBB12_13 +; SSE4-NEXT: LBB12_29: ## %cond.store23 ; SSE4-NEXT: movss %xmm3, 48(%rdi) ; SSE4-NEXT: testl $8192, %esi ## imm = 0x2000 -; SSE4-NEXT: je LBB12_28 -; SSE4-NEXT: LBB12_27: ## %cond.store25 +; SSE4-NEXT: je LBB12_14 +; SSE4-NEXT: LBB12_30: ## %cond.store25 ; SSE4-NEXT: extractps $1, %xmm3, 52(%rdi) ; SSE4-NEXT: testl $16384, %esi ## imm = 0x4000 -; SSE4-NEXT: je LBB12_30 -; SSE4-NEXT: LBB12_29: ## %cond.store27 +; SSE4-NEXT: je LBB12_15 +; SSE4-NEXT: LBB12_31: ## %cond.store27 ; SSE4-NEXT: extractps $2, %xmm3, 56(%rdi) ; SSE4-NEXT: testl $32768, %esi ## imm = 0x8000 -; SSE4-NEXT: je LBB12_32 -; SSE4-NEXT: LBB12_31: ## %cond.store29 +; SSE4-NEXT: je LBB12_16 +; SSE4-NEXT: LBB12_32: ## %cond.store29 ; SSE4-NEXT: extractps $3, %xmm3, 60(%rdi) ; SSE4-NEXT: retq ; @@ -1678,134 +1678,134 @@ define void @store_v16f32_v16i32(<16 x float> %x, ptr %ptr, <16 x float> %y, <16 ; SSE2-NEXT: packsswb %xmm5, %xmm4 ; SSE2-NEXT: pmovmskb %xmm4, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB13_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB13_17 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB13_3 -; SSE2-NEXT: LBB13_4: ## %else2 +; SSE2-NEXT: jne LBB13_18 +; SSE2-NEXT: LBB13_2: ## %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB13_5 -; SSE2-NEXT: LBB13_6: ## %else4 +; SSE2-NEXT: jne LBB13_19 +; SSE2-NEXT: LBB13_3: ## %else4 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne LBB13_7 -; SSE2-NEXT: LBB13_8: ## %else6 +; SSE2-NEXT: jne LBB13_20 +; SSE2-NEXT: LBB13_4: ## %else6 ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: jne LBB13_9 -; SSE2-NEXT: LBB13_10: ## %else8 +; SSE2-NEXT: jne LBB13_21 +; SSE2-NEXT: LBB13_5: ## %else8 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: jne LBB13_11 -; SSE2-NEXT: LBB13_12: ## %else10 +; SSE2-NEXT: jne LBB13_22 +; SSE2-NEXT: LBB13_6: ## %else10 ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: jne LBB13_13 -; SSE2-NEXT: LBB13_14: ## %else12 +; SSE2-NEXT: jne LBB13_23 +; SSE2-NEXT: LBB13_7: ## %else12 ; SSE2-NEXT: testb %al, %al -; SSE2-NEXT: js LBB13_15 -; SSE2-NEXT: LBB13_16: ## %else14 +; SSE2-NEXT: js LBB13_24 +; SSE2-NEXT: LBB13_8: ## %else14 ; SSE2-NEXT: testl $256, %eax ## imm = 0x100 -; SSE2-NEXT: jne LBB13_17 -; SSE2-NEXT: LBB13_18: ## %else16 +; SSE2-NEXT: jne LBB13_25 +; SSE2-NEXT: LBB13_9: ## %else16 ; SSE2-NEXT: testl $512, %eax ## imm = 0x200 -; SSE2-NEXT: jne LBB13_19 -; SSE2-NEXT: LBB13_20: ## %else18 +; SSE2-NEXT: jne LBB13_26 +; SSE2-NEXT: LBB13_10: ## %else18 ; SSE2-NEXT: testl $1024, %eax ## imm = 0x400 -; SSE2-NEXT: jne LBB13_21 -; SSE2-NEXT: LBB13_22: ## %else20 +; SSE2-NEXT: jne LBB13_27 +; SSE2-NEXT: LBB13_11: ## %else20 ; SSE2-NEXT: testl $2048, %eax ## imm = 0x800 -; SSE2-NEXT: jne LBB13_23 -; SSE2-NEXT: LBB13_24: ## %else22 +; SSE2-NEXT: jne LBB13_28 +; SSE2-NEXT: LBB13_12: ## %else22 ; SSE2-NEXT: testl $4096, %eax ## imm = 0x1000 -; SSE2-NEXT: jne LBB13_25 -; SSE2-NEXT: LBB13_26: ## %else24 +; SSE2-NEXT: jne LBB13_29 +; SSE2-NEXT: LBB13_13: ## %else24 ; SSE2-NEXT: testl $8192, %eax ## imm = 0x2000 -; SSE2-NEXT: jne LBB13_27 -; SSE2-NEXT: LBB13_28: ## %else26 +; SSE2-NEXT: jne LBB13_30 +; SSE2-NEXT: LBB13_14: ## %else26 ; SSE2-NEXT: testl $16384, %eax ## imm = 0x4000 -; SSE2-NEXT: jne LBB13_29 -; SSE2-NEXT: LBB13_30: ## %else28 -; SSE2-NEXT: testl $32768, %eax ## imm = 0x8000 ; SSE2-NEXT: jne LBB13_31 -; SSE2-NEXT: LBB13_32: ## %else30 +; SSE2-NEXT: LBB13_15: ## %else28 +; SSE2-NEXT: testl $32768, %eax ## imm = 0x8000 +; SSE2-NEXT: jne LBB13_32 +; SSE2-NEXT: LBB13_16: ## %else30 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB13_1: ## %cond.store +; SSE2-NEXT: LBB13_17: ## %cond.store ; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB13_4 -; SSE2-NEXT: LBB13_3: ## %cond.store1 +; SSE2-NEXT: je LBB13_2 +; SSE2-NEXT: LBB13_18: ## %cond.store1 ; SSE2-NEXT: movaps %xmm0, %xmm4 ; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,1],xmm0[1,1] ; SSE2-NEXT: movss %xmm4, 4(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB13_6 -; SSE2-NEXT: LBB13_5: ## %cond.store3 +; SSE2-NEXT: je LBB13_3 +; SSE2-NEXT: LBB13_19: ## %cond.store3 ; SSE2-NEXT: movaps %xmm0, %xmm4 ; SSE2-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm0[1] ; SSE2-NEXT: movss %xmm4, 8(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB13_8 -; SSE2-NEXT: LBB13_7: ## %cond.store5 +; SSE2-NEXT: je LBB13_4 +; SSE2-NEXT: LBB13_20: ## %cond.store5 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: movss %xmm0, 12(%rdi) ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: je LBB13_10 -; SSE2-NEXT: LBB13_9: ## %cond.store7 +; SSE2-NEXT: je LBB13_5 +; SSE2-NEXT: LBB13_21: ## %cond.store7 ; SSE2-NEXT: movss %xmm1, 16(%rdi) ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je LBB13_12 -; SSE2-NEXT: LBB13_11: ## %cond.store9 +; SSE2-NEXT: je LBB13_6 +; SSE2-NEXT: LBB13_22: ## %cond.store9 ; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1] ; SSE2-NEXT: movss %xmm0, 20(%rdi) ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: je LBB13_14 -; SSE2-NEXT: LBB13_13: ## %cond.store11 +; SSE2-NEXT: je LBB13_7 +; SSE2-NEXT: LBB13_23: ## %cond.store11 ; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1] ; SSE2-NEXT: movss %xmm0, 24(%rdi) ; SSE2-NEXT: testb %al, %al -; SSE2-NEXT: jns LBB13_16 -; SSE2-NEXT: LBB13_15: ## %cond.store13 +; SSE2-NEXT: jns LBB13_8 +; SSE2-NEXT: LBB13_24: ## %cond.store13 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE2-NEXT: movss %xmm1, 28(%rdi) ; SSE2-NEXT: testl $256, %eax ## imm = 0x100 -; SSE2-NEXT: je LBB13_18 -; SSE2-NEXT: LBB13_17: ## %cond.store15 +; SSE2-NEXT: je LBB13_9 +; SSE2-NEXT: LBB13_25: ## %cond.store15 ; SSE2-NEXT: movss %xmm2, 32(%rdi) ; SSE2-NEXT: testl $512, %eax ## imm = 0x200 -; SSE2-NEXT: je LBB13_20 -; SSE2-NEXT: LBB13_19: ## %cond.store17 +; SSE2-NEXT: je LBB13_10 +; SSE2-NEXT: LBB13_26: ## %cond.store17 ; SSE2-NEXT: movaps %xmm2, %xmm0 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm2[1,1] ; SSE2-NEXT: movss %xmm0, 36(%rdi) ; SSE2-NEXT: testl $1024, %eax ## imm = 0x400 -; SSE2-NEXT: je LBB13_22 -; SSE2-NEXT: LBB13_21: ## %cond.store19 +; SSE2-NEXT: je LBB13_11 +; SSE2-NEXT: LBB13_27: ## %cond.store19 ; SSE2-NEXT: movaps %xmm2, %xmm0 ; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm2[1] ; SSE2-NEXT: movss %xmm0, 40(%rdi) ; SSE2-NEXT: testl $2048, %eax ## imm = 0x800 -; SSE2-NEXT: je LBB13_24 -; SSE2-NEXT: LBB13_23: ## %cond.store21 +; SSE2-NEXT: je LBB13_12 +; SSE2-NEXT: LBB13_28: ## %cond.store21 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3,3,3] ; SSE2-NEXT: movss %xmm2, 44(%rdi) ; SSE2-NEXT: testl $4096, %eax ## imm = 0x1000 -; SSE2-NEXT: je LBB13_26 -; SSE2-NEXT: LBB13_25: ## %cond.store23 +; SSE2-NEXT: je LBB13_13 +; SSE2-NEXT: LBB13_29: ## %cond.store23 ; SSE2-NEXT: movss %xmm3, 48(%rdi) ; SSE2-NEXT: testl $8192, %eax ## imm = 0x2000 -; SSE2-NEXT: je LBB13_28 -; SSE2-NEXT: LBB13_27: ## %cond.store25 +; SSE2-NEXT: je LBB13_14 +; SSE2-NEXT: LBB13_30: ## %cond.store25 ; SSE2-NEXT: movaps %xmm3, %xmm0 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm3[1,1] ; SSE2-NEXT: movss %xmm0, 52(%rdi) ; SSE2-NEXT: testl $16384, %eax ## imm = 0x4000 -; SSE2-NEXT: je LBB13_30 -; SSE2-NEXT: LBB13_29: ## %cond.store27 +; SSE2-NEXT: je LBB13_15 +; SSE2-NEXT: LBB13_31: ## %cond.store27 ; SSE2-NEXT: movaps %xmm3, %xmm0 ; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm3[1] ; SSE2-NEXT: movss %xmm0, 56(%rdi) ; SSE2-NEXT: testl $32768, %eax ## imm = 0x8000 -; SSE2-NEXT: je LBB13_32 -; SSE2-NEXT: LBB13_31: ## %cond.store29 +; SSE2-NEXT: je LBB13_16 +; SSE2-NEXT: LBB13_32: ## %cond.store29 ; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,3,3,3] ; SSE2-NEXT: movss %xmm3, 60(%rdi) ; SSE2-NEXT: retq @@ -1819,115 +1819,115 @@ define void @store_v16f32_v16i32(<16 x float> %x, ptr %ptr, <16 x float> %y, <16 ; SSE4-NEXT: packsswb %xmm5, %xmm4 ; SSE4-NEXT: pmovmskb %xmm4, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne LBB13_1 -; SSE4-NEXT: ## %bb.2: ## %else +; SSE4-NEXT: jne LBB13_17 +; SSE4-NEXT: ## %bb.1: ## %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne LBB13_3 -; SSE4-NEXT: LBB13_4: ## %else2 +; SSE4-NEXT: jne LBB13_18 +; SSE4-NEXT: LBB13_2: ## %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne LBB13_5 -; SSE4-NEXT: LBB13_6: ## %else4 +; SSE4-NEXT: jne LBB13_19 +; SSE4-NEXT: LBB13_3: ## %else4 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne LBB13_7 -; SSE4-NEXT: LBB13_8: ## %else6 +; SSE4-NEXT: jne LBB13_20 +; SSE4-NEXT: LBB13_4: ## %else6 ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: jne LBB13_9 -; SSE4-NEXT: LBB13_10: ## %else8 +; SSE4-NEXT: jne LBB13_21 +; SSE4-NEXT: LBB13_5: ## %else8 ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: jne LBB13_11 -; SSE4-NEXT: LBB13_12: ## %else10 +; SSE4-NEXT: jne LBB13_22 +; SSE4-NEXT: LBB13_6: ## %else10 ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: jne LBB13_13 -; SSE4-NEXT: LBB13_14: ## %else12 +; SSE4-NEXT: jne LBB13_23 +; SSE4-NEXT: LBB13_7: ## %else12 ; SSE4-NEXT: testb %al, %al -; SSE4-NEXT: js LBB13_15 -; SSE4-NEXT: LBB13_16: ## %else14 +; SSE4-NEXT: js LBB13_24 +; SSE4-NEXT: LBB13_8: ## %else14 ; SSE4-NEXT: testl $256, %eax ## imm = 0x100 -; SSE4-NEXT: jne LBB13_17 -; SSE4-NEXT: LBB13_18: ## %else16 +; SSE4-NEXT: jne LBB13_25 +; SSE4-NEXT: LBB13_9: ## %else16 ; SSE4-NEXT: testl $512, %eax ## imm = 0x200 -; SSE4-NEXT: jne LBB13_19 -; SSE4-NEXT: LBB13_20: ## %else18 +; SSE4-NEXT: jne LBB13_26 +; SSE4-NEXT: LBB13_10: ## %else18 ; SSE4-NEXT: testl $1024, %eax ## imm = 0x400 -; SSE4-NEXT: jne LBB13_21 -; SSE4-NEXT: LBB13_22: ## %else20 +; SSE4-NEXT: jne LBB13_27 +; SSE4-NEXT: LBB13_11: ## %else20 ; SSE4-NEXT: testl $2048, %eax ## imm = 0x800 -; SSE4-NEXT: jne LBB13_23 -; SSE4-NEXT: LBB13_24: ## %else22 +; SSE4-NEXT: jne LBB13_28 +; SSE4-NEXT: LBB13_12: ## %else22 ; SSE4-NEXT: testl $4096, %eax ## imm = 0x1000 -; SSE4-NEXT: jne LBB13_25 -; SSE4-NEXT: LBB13_26: ## %else24 +; SSE4-NEXT: jne LBB13_29 +; SSE4-NEXT: LBB13_13: ## %else24 ; SSE4-NEXT: testl $8192, %eax ## imm = 0x2000 -; SSE4-NEXT: jne LBB13_27 -; SSE4-NEXT: LBB13_28: ## %else26 +; SSE4-NEXT: jne LBB13_30 +; SSE4-NEXT: LBB13_14: ## %else26 ; SSE4-NEXT: testl $16384, %eax ## imm = 0x4000 -; SSE4-NEXT: jne LBB13_29 -; SSE4-NEXT: LBB13_30: ## %else28 -; SSE4-NEXT: testl $32768, %eax ## imm = 0x8000 ; SSE4-NEXT: jne LBB13_31 -; SSE4-NEXT: LBB13_32: ## %else30 +; SSE4-NEXT: LBB13_15: ## %else28 +; SSE4-NEXT: testl $32768, %eax ## imm = 0x8000 +; SSE4-NEXT: jne LBB13_32 +; SSE4-NEXT: LBB13_16: ## %else30 ; SSE4-NEXT: retq -; SSE4-NEXT: LBB13_1: ## %cond.store +; SSE4-NEXT: LBB13_17: ## %cond.store ; SSE4-NEXT: movss %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je LBB13_4 -; SSE4-NEXT: LBB13_3: ## %cond.store1 +; SSE4-NEXT: je LBB13_2 +; SSE4-NEXT: LBB13_18: ## %cond.store1 ; SSE4-NEXT: extractps $1, %xmm0, 4(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je LBB13_6 -; SSE4-NEXT: LBB13_5: ## %cond.store3 +; SSE4-NEXT: je LBB13_3 +; SSE4-NEXT: LBB13_19: ## %cond.store3 ; SSE4-NEXT: extractps $2, %xmm0, 8(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je LBB13_8 -; SSE4-NEXT: LBB13_7: ## %cond.store5 +; SSE4-NEXT: je LBB13_4 +; SSE4-NEXT: LBB13_20: ## %cond.store5 ; SSE4-NEXT: extractps $3, %xmm0, 12(%rdi) ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: je LBB13_10 -; SSE4-NEXT: LBB13_9: ## %cond.store7 +; SSE4-NEXT: je LBB13_5 +; SSE4-NEXT: LBB13_21: ## %cond.store7 ; SSE4-NEXT: movss %xmm1, 16(%rdi) ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: je LBB13_12 -; SSE4-NEXT: LBB13_11: ## %cond.store9 +; SSE4-NEXT: je LBB13_6 +; SSE4-NEXT: LBB13_22: ## %cond.store9 ; SSE4-NEXT: extractps $1, %xmm1, 20(%rdi) ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: je LBB13_14 -; SSE4-NEXT: LBB13_13: ## %cond.store11 +; SSE4-NEXT: je LBB13_7 +; SSE4-NEXT: LBB13_23: ## %cond.store11 ; SSE4-NEXT: extractps $2, %xmm1, 24(%rdi) ; SSE4-NEXT: testb %al, %al -; SSE4-NEXT: jns LBB13_16 -; SSE4-NEXT: LBB13_15: ## %cond.store13 +; SSE4-NEXT: jns LBB13_8 +; SSE4-NEXT: LBB13_24: ## %cond.store13 ; SSE4-NEXT: extractps $3, %xmm1, 28(%rdi) ; SSE4-NEXT: testl $256, %eax ## imm = 0x100 -; SSE4-NEXT: je LBB13_18 -; SSE4-NEXT: LBB13_17: ## %cond.store15 +; SSE4-NEXT: je LBB13_9 +; SSE4-NEXT: LBB13_25: ## %cond.store15 ; SSE4-NEXT: movss %xmm2, 32(%rdi) ; SSE4-NEXT: testl $512, %eax ## imm = 0x200 -; SSE4-NEXT: je LBB13_20 -; SSE4-NEXT: LBB13_19: ## %cond.store17 +; SSE4-NEXT: je LBB13_10 +; SSE4-NEXT: LBB13_26: ## %cond.store17 ; SSE4-NEXT: extractps $1, %xmm2, 36(%rdi) ; SSE4-NEXT: testl $1024, %eax ## imm = 0x400 -; SSE4-NEXT: je LBB13_22 -; SSE4-NEXT: LBB13_21: ## %cond.store19 +; SSE4-NEXT: je LBB13_11 +; SSE4-NEXT: LBB13_27: ## %cond.store19 ; SSE4-NEXT: extractps $2, %xmm2, 40(%rdi) ; SSE4-NEXT: testl $2048, %eax ## imm = 0x800 -; SSE4-NEXT: je LBB13_24 -; SSE4-NEXT: LBB13_23: ## %cond.store21 +; SSE4-NEXT: je LBB13_12 +; SSE4-NEXT: LBB13_28: ## %cond.store21 ; SSE4-NEXT: extractps $3, %xmm2, 44(%rdi) ; SSE4-NEXT: testl $4096, %eax ## imm = 0x1000 -; SSE4-NEXT: je LBB13_26 -; SSE4-NEXT: LBB13_25: ## %cond.store23 +; SSE4-NEXT: je LBB13_13 +; SSE4-NEXT: LBB13_29: ## %cond.store23 ; SSE4-NEXT: movss %xmm3, 48(%rdi) ; SSE4-NEXT: testl $8192, %eax ## imm = 0x2000 -; SSE4-NEXT: je LBB13_28 -; SSE4-NEXT: LBB13_27: ## %cond.store25 +; SSE4-NEXT: je LBB13_14 +; SSE4-NEXT: LBB13_30: ## %cond.store25 ; SSE4-NEXT: extractps $1, %xmm3, 52(%rdi) ; SSE4-NEXT: testl $16384, %eax ## imm = 0x4000 -; SSE4-NEXT: je LBB13_30 -; SSE4-NEXT: LBB13_29: ## %cond.store27 +; SSE4-NEXT: je LBB13_15 +; SSE4-NEXT: LBB13_31: ## %cond.store27 ; SSE4-NEXT: extractps $2, %xmm3, 56(%rdi) ; SSE4-NEXT: testl $32768, %eax ## imm = 0x8000 -; SSE4-NEXT: je LBB13_32 -; SSE4-NEXT: LBB13_31: ## %cond.store29 +; SSE4-NEXT: je LBB13_16 +; SSE4-NEXT: LBB13_32: ## %cond.store29 ; SSE4-NEXT: extractps $3, %xmm3, 60(%rdi) ; SSE4-NEXT: retq ; @@ -1982,17 +1982,17 @@ define void @store_v2i64_v2i64(<2 x i64> %trigger, ptr %addr, <2 x i64> %val) no ; SSE2: ## %bb.0: ; SSE2-NEXT: movmskpd %xmm0, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB14_1 -; SSE2-NEXT: ## %bb.2: ## %else -; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: jne LBB14_3 -; SSE2-NEXT: LBB14_4: ## %else2 +; SSE2-NEXT: ## %bb.1: ## %else +; SSE2-NEXT: testb $2, %al +; SSE2-NEXT: jne LBB14_4 +; SSE2-NEXT: LBB14_2: ## %else2 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB14_1: ## %cond.store +; SSE2-NEXT: LBB14_3: ## %cond.store ; SSE2-NEXT: movq %xmm1, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB14_4 -; SSE2-NEXT: LBB14_3: ## %cond.store1 +; SSE2-NEXT: je LBB14_2 +; SSE2-NEXT: LBB14_4: ## %cond.store1 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3] ; SSE2-NEXT: movq %xmm0, 8(%rdi) ; SSE2-NEXT: retq @@ -2001,17 +2001,17 @@ define void @store_v2i64_v2i64(<2 x i64> %trigger, ptr %addr, <2 x i64> %val) no ; SSE4: ## %bb.0: ; SSE4-NEXT: movmskpd %xmm0, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne LBB14_1 -; SSE4-NEXT: ## %bb.2: ## %else -; SSE4-NEXT: testb $2, %al ; SSE4-NEXT: jne LBB14_3 -; SSE4-NEXT: LBB14_4: ## %else2 +; SSE4-NEXT: ## %bb.1: ## %else +; SSE4-NEXT: testb $2, %al +; SSE4-NEXT: jne LBB14_4 +; SSE4-NEXT: LBB14_2: ## %else2 ; SSE4-NEXT: retq -; SSE4-NEXT: LBB14_1: ## %cond.store +; SSE4-NEXT: LBB14_3: ## %cond.store ; SSE4-NEXT: movq %xmm1, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je LBB14_4 -; SSE4-NEXT: LBB14_3: ## %cond.store1 +; SSE4-NEXT: je LBB14_2 +; SSE4-NEXT: LBB14_4: ## %cond.store1 ; SSE4-NEXT: pextrq $1, %xmm1, 8(%rdi) ; SSE4-NEXT: retq ; @@ -2067,32 +2067,32 @@ define void @store_v4i64_v4i64(<4 x i64> %trigger, ptr %addr, <4 x i64> %val) no ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[1,3] ; SSE2-NEXT: movmskps %xmm0, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB15_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB15_5 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB15_3 -; SSE2-NEXT: LBB15_4: ## %else2 +; SSE2-NEXT: jne LBB15_6 +; SSE2-NEXT: LBB15_2: ## %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB15_5 -; SSE2-NEXT: LBB15_6: ## %else4 -; SSE2-NEXT: testb $8, %al ; SSE2-NEXT: jne LBB15_7 -; SSE2-NEXT: LBB15_8: ## %else6 +; SSE2-NEXT: LBB15_3: ## %else4 +; SSE2-NEXT: testb $8, %al +; SSE2-NEXT: jne LBB15_8 +; SSE2-NEXT: LBB15_4: ## %else6 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB15_1: ## %cond.store +; SSE2-NEXT: LBB15_5: ## %cond.store ; SSE2-NEXT: movq %xmm2, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB15_4 -; SSE2-NEXT: LBB15_3: ## %cond.store1 +; SSE2-NEXT: je LBB15_2 +; SSE2-NEXT: LBB15_6: ## %cond.store1 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[2,3,2,3] ; SSE2-NEXT: movq %xmm0, 8(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB15_6 -; SSE2-NEXT: LBB15_5: ## %cond.store3 +; SSE2-NEXT: je LBB15_3 +; SSE2-NEXT: LBB15_7: ## %cond.store3 ; SSE2-NEXT: movq %xmm3, 16(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB15_8 -; SSE2-NEXT: LBB15_7: ## %cond.store5 +; SSE2-NEXT: je LBB15_4 +; SSE2-NEXT: LBB15_8: ## %cond.store5 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[2,3,2,3] ; SSE2-NEXT: movq %xmm0, 24(%rdi) ; SSE2-NEXT: retq @@ -2106,31 +2106,31 @@ define void @store_v4i64_v4i64(<4 x i64> %trigger, ptr %addr, <4 x i64> %val) no ; SSE4-NEXT: packssdw %xmm5, %xmm4 ; SSE4-NEXT: movmskps %xmm4, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne LBB15_1 -; SSE4-NEXT: ## %bb.2: ## %else +; SSE4-NEXT: jne LBB15_5 +; SSE4-NEXT: ## %bb.1: ## %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne LBB15_3 -; SSE4-NEXT: LBB15_4: ## %else2 +; SSE4-NEXT: jne LBB15_6 +; SSE4-NEXT: LBB15_2: ## %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne LBB15_5 -; SSE4-NEXT: LBB15_6: ## %else4 -; SSE4-NEXT: testb $8, %al ; SSE4-NEXT: jne LBB15_7 -; SSE4-NEXT: LBB15_8: ## %else6 +; SSE4-NEXT: LBB15_3: ## %else4 +; SSE4-NEXT: testb $8, %al +; SSE4-NEXT: jne LBB15_8 +; SSE4-NEXT: LBB15_4: ## %else6 ; SSE4-NEXT: retq -; SSE4-NEXT: LBB15_1: ## %cond.store +; SSE4-NEXT: LBB15_5: ## %cond.store ; SSE4-NEXT: movq %xmm2, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je LBB15_4 -; SSE4-NEXT: LBB15_3: ## %cond.store1 +; SSE4-NEXT: je LBB15_2 +; SSE4-NEXT: LBB15_6: ## %cond.store1 ; SSE4-NEXT: pextrq $1, %xmm2, 8(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je LBB15_6 -; SSE4-NEXT: LBB15_5: ## %cond.store3 +; SSE4-NEXT: je LBB15_3 +; SSE4-NEXT: LBB15_7: ## %cond.store3 ; SSE4-NEXT: movq %xmm3, 16(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je LBB15_8 -; SSE4-NEXT: LBB15_7: ## %cond.store5 +; SSE4-NEXT: je LBB15_4 +; SSE4-NEXT: LBB15_8: ## %cond.store5 ; SSE4-NEXT: pextrq $1, %xmm3, 24(%rdi) ; SSE4-NEXT: retq ; @@ -2231,17 +2231,17 @@ define void @store_v2i32_v2i32(<2 x i32> %trigger, ptr %addr, <2 x i32> %val) no ; SSE2-NEXT: pcmpeqd %xmm0, %xmm2 ; SSE2-NEXT: movmskpd %xmm2, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB17_1 -; SSE2-NEXT: ## %bb.2: ## %else -; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: jne LBB17_3 -; SSE2-NEXT: LBB17_4: ## %else2 +; SSE2-NEXT: ## %bb.1: ## %else +; SSE2-NEXT: testb $2, %al +; SSE2-NEXT: jne LBB17_4 +; SSE2-NEXT: LBB17_2: ## %else2 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB17_1: ## %cond.store +; SSE2-NEXT: LBB17_3: ## %cond.store ; SSE2-NEXT: movd %xmm1, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB17_4 -; SSE2-NEXT: LBB17_3: ## %cond.store1 +; SSE2-NEXT: je LBB17_2 +; SSE2-NEXT: LBB17_4: ## %cond.store1 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1] ; SSE2-NEXT: movd %xmm0, 4(%rdi) ; SSE2-NEXT: retq @@ -2253,17 +2253,17 @@ define void @store_v2i32_v2i32(<2 x i32> %trigger, ptr %addr, <2 x i32> %val) no ; SSE4-NEXT: pmovsxdq %xmm2, %xmm0 ; SSE4-NEXT: movmskpd %xmm0, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne LBB17_1 -; SSE4-NEXT: ## %bb.2: ## %else -; SSE4-NEXT: testb $2, %al ; SSE4-NEXT: jne LBB17_3 -; SSE4-NEXT: LBB17_4: ## %else2 +; SSE4-NEXT: ## %bb.1: ## %else +; SSE4-NEXT: testb $2, %al +; SSE4-NEXT: jne LBB17_4 +; SSE4-NEXT: LBB17_2: ## %else2 ; SSE4-NEXT: retq -; SSE4-NEXT: LBB17_1: ## %cond.store +; SSE4-NEXT: LBB17_3: ## %cond.store ; SSE4-NEXT: movss %xmm1, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je LBB17_4 -; SSE4-NEXT: LBB17_3: ## %cond.store1 +; SSE4-NEXT: je LBB17_2 +; SSE4-NEXT: LBB17_4: ## %cond.store1 ; SSE4-NEXT: extractps $1, %xmm1, 4(%rdi) ; SSE4-NEXT: retq ; @@ -2330,33 +2330,33 @@ define void @store_v4i32_v4i32(<4 x i32> %trigger, ptr %addr, <4 x i32> %val) no ; SSE2-NEXT: pcmpeqd %xmm0, %xmm2 ; SSE2-NEXT: movmskps %xmm2, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB18_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB18_5 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB18_3 -; SSE2-NEXT: LBB18_4: ## %else2 +; SSE2-NEXT: jne LBB18_6 +; SSE2-NEXT: LBB18_2: ## %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB18_5 -; SSE2-NEXT: LBB18_6: ## %else4 -; SSE2-NEXT: testb $8, %al ; SSE2-NEXT: jne LBB18_7 -; SSE2-NEXT: LBB18_8: ## %else6 +; SSE2-NEXT: LBB18_3: ## %else4 +; SSE2-NEXT: testb $8, %al +; SSE2-NEXT: jne LBB18_8 +; SSE2-NEXT: LBB18_4: ## %else6 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB18_1: ## %cond.store +; SSE2-NEXT: LBB18_5: ## %cond.store ; SSE2-NEXT: movd %xmm1, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB18_4 -; SSE2-NEXT: LBB18_3: ## %cond.store1 +; SSE2-NEXT: je LBB18_2 +; SSE2-NEXT: LBB18_6: ## %cond.store1 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1] ; SSE2-NEXT: movd %xmm0, 4(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB18_6 -; SSE2-NEXT: LBB18_5: ## %cond.store3 +; SSE2-NEXT: je LBB18_3 +; SSE2-NEXT: LBB18_7: ## %cond.store3 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3] ; SSE2-NEXT: movd %xmm0, 8(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB18_8 -; SSE2-NEXT: LBB18_7: ## %cond.store5 +; SSE2-NEXT: je LBB18_4 +; SSE2-NEXT: LBB18_8: ## %cond.store5 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[3,3,3,3] ; SSE2-NEXT: movd %xmm0, 12(%rdi) ; SSE2-NEXT: retq @@ -2367,31 +2367,31 @@ define void @store_v4i32_v4i32(<4 x i32> %trigger, ptr %addr, <4 x i32> %val) no ; SSE4-NEXT: pcmpeqd %xmm0, %xmm2 ; SSE4-NEXT: movmskps %xmm2, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne LBB18_1 -; SSE4-NEXT: ## %bb.2: ## %else +; SSE4-NEXT: jne LBB18_5 +; SSE4-NEXT: ## %bb.1: ## %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne LBB18_3 -; SSE4-NEXT: LBB18_4: ## %else2 +; SSE4-NEXT: jne LBB18_6 +; SSE4-NEXT: LBB18_2: ## %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne LBB18_5 -; SSE4-NEXT: LBB18_6: ## %else4 -; SSE4-NEXT: testb $8, %al ; SSE4-NEXT: jne LBB18_7 -; SSE4-NEXT: LBB18_8: ## %else6 +; SSE4-NEXT: LBB18_3: ## %else4 +; SSE4-NEXT: testb $8, %al +; SSE4-NEXT: jne LBB18_8 +; SSE4-NEXT: LBB18_4: ## %else6 ; SSE4-NEXT: retq -; SSE4-NEXT: LBB18_1: ## %cond.store +; SSE4-NEXT: LBB18_5: ## %cond.store ; SSE4-NEXT: movss %xmm1, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je LBB18_4 -; SSE4-NEXT: LBB18_3: ## %cond.store1 +; SSE4-NEXT: je LBB18_2 +; SSE4-NEXT: LBB18_6: ## %cond.store1 ; SSE4-NEXT: extractps $1, %xmm1, 4(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je LBB18_6 -; SSE4-NEXT: LBB18_5: ## %cond.store3 +; SSE4-NEXT: je LBB18_3 +; SSE4-NEXT: LBB18_7: ## %cond.store3 ; SSE4-NEXT: extractps $2, %xmm1, 8(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je LBB18_8 -; SSE4-NEXT: LBB18_7: ## %cond.store5 +; SSE4-NEXT: je LBB18_4 +; SSE4-NEXT: LBB18_8: ## %cond.store5 ; SSE4-NEXT: extractps $3, %xmm1, 12(%rdi) ; SSE4-NEXT: retq ; @@ -2447,64 +2447,64 @@ define void @store_v8i32_v8i32(<8 x i32> %trigger, ptr %addr, <8 x i32> %val) no ; SSE2-NEXT: packsswb %xmm0, %xmm0 ; SSE2-NEXT: pmovmskb %xmm0, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB19_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB19_9 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB19_3 -; SSE2-NEXT: LBB19_4: ## %else2 +; SSE2-NEXT: jne LBB19_10 +; SSE2-NEXT: LBB19_2: ## %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB19_5 -; SSE2-NEXT: LBB19_6: ## %else4 +; SSE2-NEXT: jne LBB19_11 +; SSE2-NEXT: LBB19_3: ## %else4 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne LBB19_7 -; SSE2-NEXT: LBB19_8: ## %else6 +; SSE2-NEXT: jne LBB19_12 +; SSE2-NEXT: LBB19_4: ## %else6 ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: jne LBB19_9 -; SSE2-NEXT: LBB19_10: ## %else8 +; SSE2-NEXT: jne LBB19_13 +; SSE2-NEXT: LBB19_5: ## %else8 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: jne LBB19_11 -; SSE2-NEXT: LBB19_12: ## %else10 +; SSE2-NEXT: jne LBB19_14 +; SSE2-NEXT: LBB19_6: ## %else10 ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: jne LBB19_13 -; SSE2-NEXT: LBB19_14: ## %else12 -; SSE2-NEXT: testb $-128, %al ; SSE2-NEXT: jne LBB19_15 -; SSE2-NEXT: LBB19_16: ## %else14 +; SSE2-NEXT: LBB19_7: ## %else12 +; SSE2-NEXT: testb $-128, %al +; SSE2-NEXT: jne LBB19_16 +; SSE2-NEXT: LBB19_8: ## %else14 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB19_1: ## %cond.store +; SSE2-NEXT: LBB19_9: ## %cond.store ; SSE2-NEXT: movd %xmm2, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB19_4 -; SSE2-NEXT: LBB19_3: ## %cond.store1 +; SSE2-NEXT: je LBB19_2 +; SSE2-NEXT: LBB19_10: ## %cond.store1 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,1,1] ; SSE2-NEXT: movd %xmm0, 4(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB19_6 -; SSE2-NEXT: LBB19_5: ## %cond.store3 +; SSE2-NEXT: je LBB19_3 +; SSE2-NEXT: LBB19_11: ## %cond.store3 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[2,3,2,3] ; SSE2-NEXT: movd %xmm0, 8(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB19_8 -; SSE2-NEXT: LBB19_7: ## %cond.store5 +; SSE2-NEXT: je LBB19_4 +; SSE2-NEXT: LBB19_12: ## %cond.store5 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[3,3,3,3] ; SSE2-NEXT: movd %xmm0, 12(%rdi) ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: je LBB19_10 -; SSE2-NEXT: LBB19_9: ## %cond.store7 +; SSE2-NEXT: je LBB19_5 +; SSE2-NEXT: LBB19_13: ## %cond.store7 ; SSE2-NEXT: movd %xmm3, 16(%rdi) ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je LBB19_12 -; SSE2-NEXT: LBB19_11: ## %cond.store9 +; SSE2-NEXT: je LBB19_6 +; SSE2-NEXT: LBB19_14: ## %cond.store9 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,1,1] ; SSE2-NEXT: movd %xmm0, 20(%rdi) ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: je LBB19_14 -; SSE2-NEXT: LBB19_13: ## %cond.store11 +; SSE2-NEXT: je LBB19_7 +; SSE2-NEXT: LBB19_15: ## %cond.store11 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[2,3,2,3] ; SSE2-NEXT: movd %xmm0, 24(%rdi) ; SSE2-NEXT: testb $-128, %al -; SSE2-NEXT: je LBB19_16 -; SSE2-NEXT: LBB19_15: ## %cond.store13 +; SSE2-NEXT: je LBB19_8 +; SSE2-NEXT: LBB19_16: ## %cond.store13 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[3,3,3,3] ; SSE2-NEXT: movd %xmm0, 28(%rdi) ; SSE2-NEXT: retq @@ -2518,59 +2518,59 @@ define void @store_v8i32_v8i32(<8 x i32> %trigger, ptr %addr, <8 x i32> %val) no ; SSE4-NEXT: packsswb %xmm0, %xmm0 ; SSE4-NEXT: pmovmskb %xmm0, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne LBB19_1 -; SSE4-NEXT: ## %bb.2: ## %else +; SSE4-NEXT: jne LBB19_9 +; SSE4-NEXT: ## %bb.1: ## %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne LBB19_3 -; SSE4-NEXT: LBB19_4: ## %else2 +; SSE4-NEXT: jne LBB19_10 +; SSE4-NEXT: LBB19_2: ## %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne LBB19_5 -; SSE4-NEXT: LBB19_6: ## %else4 +; SSE4-NEXT: jne LBB19_11 +; SSE4-NEXT: LBB19_3: ## %else4 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne LBB19_7 -; SSE4-NEXT: LBB19_8: ## %else6 +; SSE4-NEXT: jne LBB19_12 +; SSE4-NEXT: LBB19_4: ## %else6 ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: jne LBB19_9 -; SSE4-NEXT: LBB19_10: ## %else8 +; SSE4-NEXT: jne LBB19_13 +; SSE4-NEXT: LBB19_5: ## %else8 ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: jne LBB19_11 -; SSE4-NEXT: LBB19_12: ## %else10 +; SSE4-NEXT: jne LBB19_14 +; SSE4-NEXT: LBB19_6: ## %else10 ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: jne LBB19_13 -; SSE4-NEXT: LBB19_14: ## %else12 -; SSE4-NEXT: testb $-128, %al ; SSE4-NEXT: jne LBB19_15 -; SSE4-NEXT: LBB19_16: ## %else14 +; SSE4-NEXT: LBB19_7: ## %else12 +; SSE4-NEXT: testb $-128, %al +; SSE4-NEXT: jne LBB19_16 +; SSE4-NEXT: LBB19_8: ## %else14 ; SSE4-NEXT: retq -; SSE4-NEXT: LBB19_1: ## %cond.store +; SSE4-NEXT: LBB19_9: ## %cond.store ; SSE4-NEXT: movss %xmm2, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je LBB19_4 -; SSE4-NEXT: LBB19_3: ## %cond.store1 +; SSE4-NEXT: je LBB19_2 +; SSE4-NEXT: LBB19_10: ## %cond.store1 ; SSE4-NEXT: extractps $1, %xmm2, 4(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je LBB19_6 -; SSE4-NEXT: LBB19_5: ## %cond.store3 +; SSE4-NEXT: je LBB19_3 +; SSE4-NEXT: LBB19_11: ## %cond.store3 ; SSE4-NEXT: extractps $2, %xmm2, 8(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je LBB19_8 -; SSE4-NEXT: LBB19_7: ## %cond.store5 +; SSE4-NEXT: je LBB19_4 +; SSE4-NEXT: LBB19_12: ## %cond.store5 ; SSE4-NEXT: extractps $3, %xmm2, 12(%rdi) ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: je LBB19_10 -; SSE4-NEXT: LBB19_9: ## %cond.store7 +; SSE4-NEXT: je LBB19_5 +; SSE4-NEXT: LBB19_13: ## %cond.store7 ; SSE4-NEXT: movss %xmm3, 16(%rdi) ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: je LBB19_12 -; SSE4-NEXT: LBB19_11: ## %cond.store9 +; SSE4-NEXT: je LBB19_6 +; SSE4-NEXT: LBB19_14: ## %cond.store9 ; SSE4-NEXT: extractps $1, %xmm3, 20(%rdi) ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: je LBB19_14 -; SSE4-NEXT: LBB19_13: ## %cond.store11 +; SSE4-NEXT: je LBB19_7 +; SSE4-NEXT: LBB19_15: ## %cond.store11 ; SSE4-NEXT: extractps $2, %xmm3, 24(%rdi) ; SSE4-NEXT: testb $-128, %al -; SSE4-NEXT: je LBB19_16 -; SSE4-NEXT: LBB19_15: ## %cond.store13 +; SSE4-NEXT: je LBB19_8 +; SSE4-NEXT: LBB19_16: ## %cond.store13 ; SSE4-NEXT: extractps $3, %xmm3, 28(%rdi) ; SSE4-NEXT: retq ; @@ -2635,66 +2635,66 @@ define void @store_v8i16_v8i16(<8 x i16> %trigger, ptr %addr, <8 x i16> %val) no ; SSE2-NEXT: packsswb %xmm2, %xmm2 ; SSE2-NEXT: pmovmskb %xmm2, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB20_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB20_9 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB20_3 -; SSE2-NEXT: LBB20_4: ## %else2 +; SSE2-NEXT: jne LBB20_10 +; SSE2-NEXT: LBB20_2: ## %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB20_5 -; SSE2-NEXT: LBB20_6: ## %else4 +; SSE2-NEXT: jne LBB20_11 +; SSE2-NEXT: LBB20_3: ## %else4 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne LBB20_7 -; SSE2-NEXT: LBB20_8: ## %else6 +; SSE2-NEXT: jne LBB20_12 +; SSE2-NEXT: LBB20_4: ## %else6 ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: jne LBB20_9 -; SSE2-NEXT: LBB20_10: ## %else8 +; SSE2-NEXT: jne LBB20_13 +; SSE2-NEXT: LBB20_5: ## %else8 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: jne LBB20_11 -; SSE2-NEXT: LBB20_12: ## %else10 +; SSE2-NEXT: jne LBB20_14 +; SSE2-NEXT: LBB20_6: ## %else10 ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: jne LBB20_13 -; SSE2-NEXT: LBB20_14: ## %else12 -; SSE2-NEXT: testb $-128, %al ; SSE2-NEXT: jne LBB20_15 -; SSE2-NEXT: LBB20_16: ## %else14 +; SSE2-NEXT: LBB20_7: ## %else12 +; SSE2-NEXT: testb $-128, %al +; SSE2-NEXT: jne LBB20_16 +; SSE2-NEXT: LBB20_8: ## %else14 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB20_1: ## %cond.store +; SSE2-NEXT: LBB20_9: ## %cond.store ; SSE2-NEXT: movd %xmm1, %ecx ; SSE2-NEXT: movw %cx, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB20_4 -; SSE2-NEXT: LBB20_3: ## %cond.store1 +; SSE2-NEXT: je LBB20_2 +; SSE2-NEXT: LBB20_10: ## %cond.store1 ; SSE2-NEXT: pextrw $1, %xmm1, %ecx ; SSE2-NEXT: movw %cx, 2(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB20_6 -; SSE2-NEXT: LBB20_5: ## %cond.store3 +; SSE2-NEXT: je LBB20_3 +; SSE2-NEXT: LBB20_11: ## %cond.store3 ; SSE2-NEXT: pextrw $2, %xmm1, %ecx ; SSE2-NEXT: movw %cx, 4(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB20_8 -; SSE2-NEXT: LBB20_7: ## %cond.store5 +; SSE2-NEXT: je LBB20_4 +; SSE2-NEXT: LBB20_12: ## %cond.store5 ; SSE2-NEXT: pextrw $3, %xmm1, %ecx ; SSE2-NEXT: movw %cx, 6(%rdi) ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: je LBB20_10 -; SSE2-NEXT: LBB20_9: ## %cond.store7 +; SSE2-NEXT: je LBB20_5 +; SSE2-NEXT: LBB20_13: ## %cond.store7 ; SSE2-NEXT: pextrw $4, %xmm1, %ecx ; SSE2-NEXT: movw %cx, 8(%rdi) ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je LBB20_12 -; SSE2-NEXT: LBB20_11: ## %cond.store9 +; SSE2-NEXT: je LBB20_6 +; SSE2-NEXT: LBB20_14: ## %cond.store9 ; SSE2-NEXT: pextrw $5, %xmm1, %ecx ; SSE2-NEXT: movw %cx, 10(%rdi) ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: je LBB20_14 -; SSE2-NEXT: LBB20_13: ## %cond.store11 +; SSE2-NEXT: je LBB20_7 +; SSE2-NEXT: LBB20_15: ## %cond.store11 ; SSE2-NEXT: pextrw $6, %xmm1, %ecx ; SSE2-NEXT: movw %cx, 12(%rdi) ; SSE2-NEXT: testb $-128, %al -; SSE2-NEXT: je LBB20_16 -; SSE2-NEXT: LBB20_15: ## %cond.store13 +; SSE2-NEXT: je LBB20_8 +; SSE2-NEXT: LBB20_16: ## %cond.store13 ; SSE2-NEXT: pextrw $7, %xmm1, %eax ; SSE2-NEXT: movw %ax, 14(%rdi) ; SSE2-NEXT: retq @@ -2706,59 +2706,59 @@ define void @store_v8i16_v8i16(<8 x i16> %trigger, ptr %addr, <8 x i16> %val) no ; SSE4-NEXT: packsswb %xmm2, %xmm2 ; SSE4-NEXT: pmovmskb %xmm2, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne LBB20_1 -; SSE4-NEXT: ## %bb.2: ## %else +; SSE4-NEXT: jne LBB20_9 +; SSE4-NEXT: ## %bb.1: ## %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne LBB20_3 -; SSE4-NEXT: LBB20_4: ## %else2 +; SSE4-NEXT: jne LBB20_10 +; SSE4-NEXT: LBB20_2: ## %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne LBB20_5 -; SSE4-NEXT: LBB20_6: ## %else4 +; SSE4-NEXT: jne LBB20_11 +; SSE4-NEXT: LBB20_3: ## %else4 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne LBB20_7 -; SSE4-NEXT: LBB20_8: ## %else6 +; SSE4-NEXT: jne LBB20_12 +; SSE4-NEXT: LBB20_4: ## %else6 ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: jne LBB20_9 -; SSE4-NEXT: LBB20_10: ## %else8 +; SSE4-NEXT: jne LBB20_13 +; SSE4-NEXT: LBB20_5: ## %else8 ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: jne LBB20_11 -; SSE4-NEXT: LBB20_12: ## %else10 +; SSE4-NEXT: jne LBB20_14 +; SSE4-NEXT: LBB20_6: ## %else10 ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: jne LBB20_13 -; SSE4-NEXT: LBB20_14: ## %else12 -; SSE4-NEXT: testb $-128, %al ; SSE4-NEXT: jne LBB20_15 -; SSE4-NEXT: LBB20_16: ## %else14 +; SSE4-NEXT: LBB20_7: ## %else12 +; SSE4-NEXT: testb $-128, %al +; SSE4-NEXT: jne LBB20_16 +; SSE4-NEXT: LBB20_8: ## %else14 ; SSE4-NEXT: retq -; SSE4-NEXT: LBB20_1: ## %cond.store +; SSE4-NEXT: LBB20_9: ## %cond.store ; SSE4-NEXT: pextrw $0, %xmm1, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je LBB20_4 -; SSE4-NEXT: LBB20_3: ## %cond.store1 +; SSE4-NEXT: je LBB20_2 +; SSE4-NEXT: LBB20_10: ## %cond.store1 ; SSE4-NEXT: pextrw $1, %xmm1, 2(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je LBB20_6 -; SSE4-NEXT: LBB20_5: ## %cond.store3 +; SSE4-NEXT: je LBB20_3 +; SSE4-NEXT: LBB20_11: ## %cond.store3 ; SSE4-NEXT: pextrw $2, %xmm1, 4(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je LBB20_8 -; SSE4-NEXT: LBB20_7: ## %cond.store5 +; SSE4-NEXT: je LBB20_4 +; SSE4-NEXT: LBB20_12: ## %cond.store5 ; SSE4-NEXT: pextrw $3, %xmm1, 6(%rdi) ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: je LBB20_10 -; SSE4-NEXT: LBB20_9: ## %cond.store7 +; SSE4-NEXT: je LBB20_5 +; SSE4-NEXT: LBB20_13: ## %cond.store7 ; SSE4-NEXT: pextrw $4, %xmm1, 8(%rdi) ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: je LBB20_12 -; SSE4-NEXT: LBB20_11: ## %cond.store9 +; SSE4-NEXT: je LBB20_6 +; SSE4-NEXT: LBB20_14: ## %cond.store9 ; SSE4-NEXT: pextrw $5, %xmm1, 10(%rdi) ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: je LBB20_14 -; SSE4-NEXT: LBB20_13: ## %cond.store11 +; SSE4-NEXT: je LBB20_7 +; SSE4-NEXT: LBB20_15: ## %cond.store11 ; SSE4-NEXT: pextrw $6, %xmm1, 12(%rdi) ; SSE4-NEXT: testb $-128, %al -; SSE4-NEXT: je LBB20_16 -; SSE4-NEXT: LBB20_15: ## %cond.store13 +; SSE4-NEXT: je LBB20_8 +; SSE4-NEXT: LBB20_16: ## %cond.store13 ; SSE4-NEXT: pextrw $7, %xmm1, 14(%rdi) ; SSE4-NEXT: retq ; @@ -2769,59 +2769,59 @@ define void @store_v8i16_v8i16(<8 x i16> %trigger, ptr %addr, <8 x i16> %val) no ; AVX1OR2-NEXT: vpacksswb %xmm0, %xmm0, %xmm0 ; AVX1OR2-NEXT: vpmovmskb %xmm0, %eax ; AVX1OR2-NEXT: testb $1, %al -; AVX1OR2-NEXT: jne LBB20_1 -; AVX1OR2-NEXT: ## %bb.2: ## %else +; AVX1OR2-NEXT: jne LBB20_9 +; AVX1OR2-NEXT: ## %bb.1: ## %else ; AVX1OR2-NEXT: testb $2, %al -; AVX1OR2-NEXT: jne LBB20_3 -; AVX1OR2-NEXT: LBB20_4: ## %else2 +; AVX1OR2-NEXT: jne LBB20_10 +; AVX1OR2-NEXT: LBB20_2: ## %else2 ; AVX1OR2-NEXT: testb $4, %al -; AVX1OR2-NEXT: jne LBB20_5 -; AVX1OR2-NEXT: LBB20_6: ## %else4 +; AVX1OR2-NEXT: jne LBB20_11 +; AVX1OR2-NEXT: LBB20_3: ## %else4 ; AVX1OR2-NEXT: testb $8, %al -; AVX1OR2-NEXT: jne LBB20_7 -; AVX1OR2-NEXT: LBB20_8: ## %else6 +; AVX1OR2-NEXT: jne LBB20_12 +; AVX1OR2-NEXT: LBB20_4: ## %else6 ; AVX1OR2-NEXT: testb $16, %al -; AVX1OR2-NEXT: jne LBB20_9 -; AVX1OR2-NEXT: LBB20_10: ## %else8 +; AVX1OR2-NEXT: jne LBB20_13 +; AVX1OR2-NEXT: LBB20_5: ## %else8 ; AVX1OR2-NEXT: testb $32, %al -; AVX1OR2-NEXT: jne LBB20_11 -; AVX1OR2-NEXT: LBB20_12: ## %else10 +; AVX1OR2-NEXT: jne LBB20_14 +; AVX1OR2-NEXT: LBB20_6: ## %else10 ; AVX1OR2-NEXT: testb $64, %al -; AVX1OR2-NEXT: jne LBB20_13 -; AVX1OR2-NEXT: LBB20_14: ## %else12 -; AVX1OR2-NEXT: testb $-128, %al ; AVX1OR2-NEXT: jne LBB20_15 -; AVX1OR2-NEXT: LBB20_16: ## %else14 +; AVX1OR2-NEXT: LBB20_7: ## %else12 +; AVX1OR2-NEXT: testb $-128, %al +; AVX1OR2-NEXT: jne LBB20_16 +; AVX1OR2-NEXT: LBB20_8: ## %else14 ; AVX1OR2-NEXT: retq -; AVX1OR2-NEXT: LBB20_1: ## %cond.store +; AVX1OR2-NEXT: LBB20_9: ## %cond.store ; AVX1OR2-NEXT: vpextrw $0, %xmm1, (%rdi) ; AVX1OR2-NEXT: testb $2, %al -; AVX1OR2-NEXT: je LBB20_4 -; AVX1OR2-NEXT: LBB20_3: ## %cond.store1 +; AVX1OR2-NEXT: je LBB20_2 +; AVX1OR2-NEXT: LBB20_10: ## %cond.store1 ; AVX1OR2-NEXT: vpextrw $1, %xmm1, 2(%rdi) ; AVX1OR2-NEXT: testb $4, %al -; AVX1OR2-NEXT: je LBB20_6 -; AVX1OR2-NEXT: LBB20_5: ## %cond.store3 +; AVX1OR2-NEXT: je LBB20_3 +; AVX1OR2-NEXT: LBB20_11: ## %cond.store3 ; AVX1OR2-NEXT: vpextrw $2, %xmm1, 4(%rdi) ; AVX1OR2-NEXT: testb $8, %al -; AVX1OR2-NEXT: je LBB20_8 -; AVX1OR2-NEXT: LBB20_7: ## %cond.store5 +; AVX1OR2-NEXT: je LBB20_4 +; AVX1OR2-NEXT: LBB20_12: ## %cond.store5 ; AVX1OR2-NEXT: vpextrw $3, %xmm1, 6(%rdi) ; AVX1OR2-NEXT: testb $16, %al -; AVX1OR2-NEXT: je LBB20_10 -; AVX1OR2-NEXT: LBB20_9: ## %cond.store7 +; AVX1OR2-NEXT: je LBB20_5 +; AVX1OR2-NEXT: LBB20_13: ## %cond.store7 ; AVX1OR2-NEXT: vpextrw $4, %xmm1, 8(%rdi) ; AVX1OR2-NEXT: testb $32, %al -; AVX1OR2-NEXT: je LBB20_12 -; AVX1OR2-NEXT: LBB20_11: ## %cond.store9 +; AVX1OR2-NEXT: je LBB20_6 +; AVX1OR2-NEXT: LBB20_14: ## %cond.store9 ; AVX1OR2-NEXT: vpextrw $5, %xmm1, 10(%rdi) ; AVX1OR2-NEXT: testb $64, %al -; AVX1OR2-NEXT: je LBB20_14 -; AVX1OR2-NEXT: LBB20_13: ## %cond.store11 +; AVX1OR2-NEXT: je LBB20_7 +; AVX1OR2-NEXT: LBB20_15: ## %cond.store11 ; AVX1OR2-NEXT: vpextrw $6, %xmm1, 12(%rdi) ; AVX1OR2-NEXT: testb $-128, %al -; AVX1OR2-NEXT: je LBB20_16 -; AVX1OR2-NEXT: LBB20_15: ## %cond.store13 +; AVX1OR2-NEXT: je LBB20_8 +; AVX1OR2-NEXT: LBB20_16: ## %cond.store13 ; AVX1OR2-NEXT: vpextrw $7, %xmm1, 14(%rdi) ; AVX1OR2-NEXT: retq ; @@ -2833,60 +2833,60 @@ define void @store_v8i16_v8i16(<8 x i16> %trigger, ptr %addr, <8 x i16> %val) no ; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne LBB20_1 -; AVX512F-NEXT: ## %bb.2: ## %else +; AVX512F-NEXT: jne LBB20_9 +; AVX512F-NEXT: ## %bb.1: ## %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne LBB20_3 -; AVX512F-NEXT: LBB20_4: ## %else2 +; AVX512F-NEXT: jne LBB20_10 +; AVX512F-NEXT: LBB20_2: ## %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne LBB20_5 -; AVX512F-NEXT: LBB20_6: ## %else4 +; AVX512F-NEXT: jne LBB20_11 +; AVX512F-NEXT: LBB20_3: ## %else4 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne LBB20_7 -; AVX512F-NEXT: LBB20_8: ## %else6 +; AVX512F-NEXT: jne LBB20_12 +; AVX512F-NEXT: LBB20_4: ## %else6 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne LBB20_9 -; AVX512F-NEXT: LBB20_10: ## %else8 +; AVX512F-NEXT: jne LBB20_13 +; AVX512F-NEXT: LBB20_5: ## %else8 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne LBB20_11 -; AVX512F-NEXT: LBB20_12: ## %else10 +; AVX512F-NEXT: jne LBB20_14 +; AVX512F-NEXT: LBB20_6: ## %else10 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne LBB20_13 -; AVX512F-NEXT: LBB20_14: ## %else12 -; AVX512F-NEXT: testb $-128, %al ; AVX512F-NEXT: jne LBB20_15 -; AVX512F-NEXT: LBB20_16: ## %else14 +; AVX512F-NEXT: LBB20_7: ## %else12 +; AVX512F-NEXT: testb $-128, %al +; AVX512F-NEXT: jne LBB20_16 +; AVX512F-NEXT: LBB20_8: ## %else14 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: LBB20_1: ## %cond.store +; AVX512F-NEXT: LBB20_9: ## %cond.store ; AVX512F-NEXT: vpextrw $0, %xmm1, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je LBB20_4 -; AVX512F-NEXT: LBB20_3: ## %cond.store1 +; AVX512F-NEXT: je LBB20_2 +; AVX512F-NEXT: LBB20_10: ## %cond.store1 ; AVX512F-NEXT: vpextrw $1, %xmm1, 2(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je LBB20_6 -; AVX512F-NEXT: LBB20_5: ## %cond.store3 +; AVX512F-NEXT: je LBB20_3 +; AVX512F-NEXT: LBB20_11: ## %cond.store3 ; AVX512F-NEXT: vpextrw $2, %xmm1, 4(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je LBB20_8 -; AVX512F-NEXT: LBB20_7: ## %cond.store5 +; AVX512F-NEXT: je LBB20_4 +; AVX512F-NEXT: LBB20_12: ## %cond.store5 ; AVX512F-NEXT: vpextrw $3, %xmm1, 6(%rdi) ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je LBB20_10 -; AVX512F-NEXT: LBB20_9: ## %cond.store7 +; AVX512F-NEXT: je LBB20_5 +; AVX512F-NEXT: LBB20_13: ## %cond.store7 ; AVX512F-NEXT: vpextrw $4, %xmm1, 8(%rdi) ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je LBB20_12 -; AVX512F-NEXT: LBB20_11: ## %cond.store9 +; AVX512F-NEXT: je LBB20_6 +; AVX512F-NEXT: LBB20_14: ## %cond.store9 ; AVX512F-NEXT: vpextrw $5, %xmm1, 10(%rdi) ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je LBB20_14 -; AVX512F-NEXT: LBB20_13: ## %cond.store11 +; AVX512F-NEXT: je LBB20_7 +; AVX512F-NEXT: LBB20_15: ## %cond.store11 ; AVX512F-NEXT: vpextrw $6, %xmm1, 12(%rdi) ; AVX512F-NEXT: testb $-128, %al -; AVX512F-NEXT: je LBB20_16 -; AVX512F-NEXT: LBB20_15: ## %cond.store13 +; AVX512F-NEXT: je LBB20_8 +; AVX512F-NEXT: LBB20_16: ## %cond.store13 ; AVX512F-NEXT: vpextrw $7, %xmm1, 14(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -2898,60 +2898,60 @@ define void @store_v8i16_v8i16(<8 x i16> %trigger, ptr %addr, <8 x i16> %val) no ; AVX512VLDQ-NEXT: vpmovsxwd %xmm0, %ymm0 ; AVX512VLDQ-NEXT: vmovmskps %ymm0, %eax ; AVX512VLDQ-NEXT: testb $1, %al -; AVX512VLDQ-NEXT: jne LBB20_1 -; AVX512VLDQ-NEXT: ## %bb.2: ## %else +; AVX512VLDQ-NEXT: jne LBB20_9 +; AVX512VLDQ-NEXT: ## %bb.1: ## %else ; AVX512VLDQ-NEXT: testb $2, %al -; AVX512VLDQ-NEXT: jne LBB20_3 -; AVX512VLDQ-NEXT: LBB20_4: ## %else2 +; AVX512VLDQ-NEXT: jne LBB20_10 +; AVX512VLDQ-NEXT: LBB20_2: ## %else2 ; AVX512VLDQ-NEXT: testb $4, %al -; AVX512VLDQ-NEXT: jne LBB20_5 -; AVX512VLDQ-NEXT: LBB20_6: ## %else4 +; AVX512VLDQ-NEXT: jne LBB20_11 +; AVX512VLDQ-NEXT: LBB20_3: ## %else4 ; AVX512VLDQ-NEXT: testb $8, %al -; AVX512VLDQ-NEXT: jne LBB20_7 -; AVX512VLDQ-NEXT: LBB20_8: ## %else6 +; AVX512VLDQ-NEXT: jne LBB20_12 +; AVX512VLDQ-NEXT: LBB20_4: ## %else6 ; AVX512VLDQ-NEXT: testb $16, %al -; AVX512VLDQ-NEXT: jne LBB20_9 -; AVX512VLDQ-NEXT: LBB20_10: ## %else8 +; AVX512VLDQ-NEXT: jne LBB20_13 +; AVX512VLDQ-NEXT: LBB20_5: ## %else8 ; AVX512VLDQ-NEXT: testb $32, %al -; AVX512VLDQ-NEXT: jne LBB20_11 -; AVX512VLDQ-NEXT: LBB20_12: ## %else10 +; AVX512VLDQ-NEXT: jne LBB20_14 +; AVX512VLDQ-NEXT: LBB20_6: ## %else10 ; AVX512VLDQ-NEXT: testb $64, %al -; AVX512VLDQ-NEXT: jne LBB20_13 -; AVX512VLDQ-NEXT: LBB20_14: ## %else12 -; AVX512VLDQ-NEXT: testb $-128, %al ; AVX512VLDQ-NEXT: jne LBB20_15 -; AVX512VLDQ-NEXT: LBB20_16: ## %else14 +; AVX512VLDQ-NEXT: LBB20_7: ## %else12 +; AVX512VLDQ-NEXT: testb $-128, %al +; AVX512VLDQ-NEXT: jne LBB20_16 +; AVX512VLDQ-NEXT: LBB20_8: ## %else14 ; AVX512VLDQ-NEXT: vzeroupper ; AVX512VLDQ-NEXT: retq -; AVX512VLDQ-NEXT: LBB20_1: ## %cond.store +; AVX512VLDQ-NEXT: LBB20_9: ## %cond.store ; AVX512VLDQ-NEXT: vpextrw $0, %xmm1, (%rdi) ; AVX512VLDQ-NEXT: testb $2, %al -; AVX512VLDQ-NEXT: je LBB20_4 -; AVX512VLDQ-NEXT: LBB20_3: ## %cond.store1 +; AVX512VLDQ-NEXT: je LBB20_2 +; AVX512VLDQ-NEXT: LBB20_10: ## %cond.store1 ; AVX512VLDQ-NEXT: vpextrw $1, %xmm1, 2(%rdi) ; AVX512VLDQ-NEXT: testb $4, %al -; AVX512VLDQ-NEXT: je LBB20_6 -; AVX512VLDQ-NEXT: LBB20_5: ## %cond.store3 +; AVX512VLDQ-NEXT: je LBB20_3 +; AVX512VLDQ-NEXT: LBB20_11: ## %cond.store3 ; AVX512VLDQ-NEXT: vpextrw $2, %xmm1, 4(%rdi) ; AVX512VLDQ-NEXT: testb $8, %al -; AVX512VLDQ-NEXT: je LBB20_8 -; AVX512VLDQ-NEXT: LBB20_7: ## %cond.store5 +; AVX512VLDQ-NEXT: je LBB20_4 +; AVX512VLDQ-NEXT: LBB20_12: ## %cond.store5 ; AVX512VLDQ-NEXT: vpextrw $3, %xmm1, 6(%rdi) ; AVX512VLDQ-NEXT: testb $16, %al -; AVX512VLDQ-NEXT: je LBB20_10 -; AVX512VLDQ-NEXT: LBB20_9: ## %cond.store7 +; AVX512VLDQ-NEXT: je LBB20_5 +; AVX512VLDQ-NEXT: LBB20_13: ## %cond.store7 ; AVX512VLDQ-NEXT: vpextrw $4, %xmm1, 8(%rdi) ; AVX512VLDQ-NEXT: testb $32, %al -; AVX512VLDQ-NEXT: je LBB20_12 -; AVX512VLDQ-NEXT: LBB20_11: ## %cond.store9 +; AVX512VLDQ-NEXT: je LBB20_6 +; AVX512VLDQ-NEXT: LBB20_14: ## %cond.store9 ; AVX512VLDQ-NEXT: vpextrw $5, %xmm1, 10(%rdi) ; AVX512VLDQ-NEXT: testb $64, %al -; AVX512VLDQ-NEXT: je LBB20_14 -; AVX512VLDQ-NEXT: LBB20_13: ## %cond.store11 +; AVX512VLDQ-NEXT: je LBB20_7 +; AVX512VLDQ-NEXT: LBB20_15: ## %cond.store11 ; AVX512VLDQ-NEXT: vpextrw $6, %xmm1, 12(%rdi) ; AVX512VLDQ-NEXT: testb $-128, %al -; AVX512VLDQ-NEXT: je LBB20_16 -; AVX512VLDQ-NEXT: LBB20_15: ## %cond.store13 +; AVX512VLDQ-NEXT: je LBB20_8 +; AVX512VLDQ-NEXT: LBB20_16: ## %cond.store13 ; AVX512VLDQ-NEXT: vpextrw $7, %xmm1, 14(%rdi) ; AVX512VLDQ-NEXT: vzeroupper ; AVX512VLDQ-NEXT: retq @@ -2982,130 +2982,130 @@ define void @store_v16i16_v16i16(<16 x i16> %trigger, ptr %addr, <16 x i16> %val ; SSE2-NEXT: packsswb %xmm1, %xmm0 ; SSE2-NEXT: pmovmskb %xmm0, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB21_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB21_17 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB21_3 -; SSE2-NEXT: LBB21_4: ## %else2 +; SSE2-NEXT: jne LBB21_18 +; SSE2-NEXT: LBB21_2: ## %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB21_5 -; SSE2-NEXT: LBB21_6: ## %else4 +; SSE2-NEXT: jne LBB21_19 +; SSE2-NEXT: LBB21_3: ## %else4 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne LBB21_7 -; SSE2-NEXT: LBB21_8: ## %else6 +; SSE2-NEXT: jne LBB21_20 +; SSE2-NEXT: LBB21_4: ## %else6 ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: jne LBB21_9 -; SSE2-NEXT: LBB21_10: ## %else8 +; SSE2-NEXT: jne LBB21_21 +; SSE2-NEXT: LBB21_5: ## %else8 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: jne LBB21_11 -; SSE2-NEXT: LBB21_12: ## %else10 +; SSE2-NEXT: jne LBB21_22 +; SSE2-NEXT: LBB21_6: ## %else10 ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: jne LBB21_13 -; SSE2-NEXT: LBB21_14: ## %else12 +; SSE2-NEXT: jne LBB21_23 +; SSE2-NEXT: LBB21_7: ## %else12 ; SSE2-NEXT: testb %al, %al -; SSE2-NEXT: js LBB21_15 -; SSE2-NEXT: LBB21_16: ## %else14 +; SSE2-NEXT: js LBB21_24 +; SSE2-NEXT: LBB21_8: ## %else14 ; SSE2-NEXT: testl $256, %eax ## imm = 0x100 -; SSE2-NEXT: jne LBB21_17 -; SSE2-NEXT: LBB21_18: ## %else16 +; SSE2-NEXT: jne LBB21_25 +; SSE2-NEXT: LBB21_9: ## %else16 ; SSE2-NEXT: testl $512, %eax ## imm = 0x200 -; SSE2-NEXT: jne LBB21_19 -; SSE2-NEXT: LBB21_20: ## %else18 +; SSE2-NEXT: jne LBB21_26 +; SSE2-NEXT: LBB21_10: ## %else18 ; SSE2-NEXT: testl $1024, %eax ## imm = 0x400 -; SSE2-NEXT: jne LBB21_21 -; SSE2-NEXT: LBB21_22: ## %else20 +; SSE2-NEXT: jne LBB21_27 +; SSE2-NEXT: LBB21_11: ## %else20 ; SSE2-NEXT: testl $2048, %eax ## imm = 0x800 -; SSE2-NEXT: jne LBB21_23 -; SSE2-NEXT: LBB21_24: ## %else22 +; SSE2-NEXT: jne LBB21_28 +; SSE2-NEXT: LBB21_12: ## %else22 ; SSE2-NEXT: testl $4096, %eax ## imm = 0x1000 -; SSE2-NEXT: jne LBB21_25 -; SSE2-NEXT: LBB21_26: ## %else24 +; SSE2-NEXT: jne LBB21_29 +; SSE2-NEXT: LBB21_13: ## %else24 ; SSE2-NEXT: testl $8192, %eax ## imm = 0x2000 -; SSE2-NEXT: jne LBB21_27 -; SSE2-NEXT: LBB21_28: ## %else26 +; SSE2-NEXT: jne LBB21_30 +; SSE2-NEXT: LBB21_14: ## %else26 ; SSE2-NEXT: testl $16384, %eax ## imm = 0x4000 -; SSE2-NEXT: jne LBB21_29 -; SSE2-NEXT: LBB21_30: ## %else28 -; SSE2-NEXT: testl $32768, %eax ## imm = 0x8000 ; SSE2-NEXT: jne LBB21_31 -; SSE2-NEXT: LBB21_32: ## %else30 +; SSE2-NEXT: LBB21_15: ## %else28 +; SSE2-NEXT: testl $32768, %eax ## imm = 0x8000 +; SSE2-NEXT: jne LBB21_32 +; SSE2-NEXT: LBB21_16: ## %else30 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB21_1: ## %cond.store +; SSE2-NEXT: LBB21_17: ## %cond.store ; SSE2-NEXT: movd %xmm2, %ecx ; SSE2-NEXT: movw %cx, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB21_4 -; SSE2-NEXT: LBB21_3: ## %cond.store1 +; SSE2-NEXT: je LBB21_2 +; SSE2-NEXT: LBB21_18: ## %cond.store1 ; SSE2-NEXT: pextrw $1, %xmm2, %ecx ; SSE2-NEXT: movw %cx, 2(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB21_6 -; SSE2-NEXT: LBB21_5: ## %cond.store3 +; SSE2-NEXT: je LBB21_3 +; SSE2-NEXT: LBB21_19: ## %cond.store3 ; SSE2-NEXT: pextrw $2, %xmm2, %ecx ; SSE2-NEXT: movw %cx, 4(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB21_8 -; SSE2-NEXT: LBB21_7: ## %cond.store5 +; SSE2-NEXT: je LBB21_4 +; SSE2-NEXT: LBB21_20: ## %cond.store5 ; SSE2-NEXT: pextrw $3, %xmm2, %ecx ; SSE2-NEXT: movw %cx, 6(%rdi) ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: je LBB21_10 -; SSE2-NEXT: LBB21_9: ## %cond.store7 +; SSE2-NEXT: je LBB21_5 +; SSE2-NEXT: LBB21_21: ## %cond.store7 ; SSE2-NEXT: pextrw $4, %xmm2, %ecx ; SSE2-NEXT: movw %cx, 8(%rdi) ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je LBB21_12 -; SSE2-NEXT: LBB21_11: ## %cond.store9 +; SSE2-NEXT: je LBB21_6 +; SSE2-NEXT: LBB21_22: ## %cond.store9 ; SSE2-NEXT: pextrw $5, %xmm2, %ecx ; SSE2-NEXT: movw %cx, 10(%rdi) ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: je LBB21_14 -; SSE2-NEXT: LBB21_13: ## %cond.store11 +; SSE2-NEXT: je LBB21_7 +; SSE2-NEXT: LBB21_23: ## %cond.store11 ; SSE2-NEXT: pextrw $6, %xmm2, %ecx ; SSE2-NEXT: movw %cx, 12(%rdi) ; SSE2-NEXT: testb %al, %al -; SSE2-NEXT: jns LBB21_16 -; SSE2-NEXT: LBB21_15: ## %cond.store13 +; SSE2-NEXT: jns LBB21_8 +; SSE2-NEXT: LBB21_24: ## %cond.store13 ; SSE2-NEXT: pextrw $7, %xmm2, %ecx ; SSE2-NEXT: movw %cx, 14(%rdi) ; SSE2-NEXT: testl $256, %eax ## imm = 0x100 -; SSE2-NEXT: je LBB21_18 -; SSE2-NEXT: LBB21_17: ## %cond.store15 +; SSE2-NEXT: je LBB21_9 +; SSE2-NEXT: LBB21_25: ## %cond.store15 ; SSE2-NEXT: movd %xmm3, %ecx ; SSE2-NEXT: movw %cx, 16(%rdi) ; SSE2-NEXT: testl $512, %eax ## imm = 0x200 -; SSE2-NEXT: je LBB21_20 -; SSE2-NEXT: LBB21_19: ## %cond.store17 +; SSE2-NEXT: je LBB21_10 +; SSE2-NEXT: LBB21_26: ## %cond.store17 ; SSE2-NEXT: pextrw $1, %xmm3, %ecx ; SSE2-NEXT: movw %cx, 18(%rdi) ; SSE2-NEXT: testl $1024, %eax ## imm = 0x400 -; SSE2-NEXT: je LBB21_22 -; SSE2-NEXT: LBB21_21: ## %cond.store19 +; SSE2-NEXT: je LBB21_11 +; SSE2-NEXT: LBB21_27: ## %cond.store19 ; SSE2-NEXT: pextrw $2, %xmm3, %ecx ; SSE2-NEXT: movw %cx, 20(%rdi) ; SSE2-NEXT: testl $2048, %eax ## imm = 0x800 -; SSE2-NEXT: je LBB21_24 -; SSE2-NEXT: LBB21_23: ## %cond.store21 +; SSE2-NEXT: je LBB21_12 +; SSE2-NEXT: LBB21_28: ## %cond.store21 ; SSE2-NEXT: pextrw $3, %xmm3, %ecx ; SSE2-NEXT: movw %cx, 22(%rdi) ; SSE2-NEXT: testl $4096, %eax ## imm = 0x1000 -; SSE2-NEXT: je LBB21_26 -; SSE2-NEXT: LBB21_25: ## %cond.store23 +; SSE2-NEXT: je LBB21_13 +; SSE2-NEXT: LBB21_29: ## %cond.store23 ; SSE2-NEXT: pextrw $4, %xmm3, %ecx ; SSE2-NEXT: movw %cx, 24(%rdi) ; SSE2-NEXT: testl $8192, %eax ## imm = 0x2000 -; SSE2-NEXT: je LBB21_28 -; SSE2-NEXT: LBB21_27: ## %cond.store25 +; SSE2-NEXT: je LBB21_14 +; SSE2-NEXT: LBB21_30: ## %cond.store25 ; SSE2-NEXT: pextrw $5, %xmm3, %ecx ; SSE2-NEXT: movw %cx, 26(%rdi) ; SSE2-NEXT: testl $16384, %eax ## imm = 0x4000 -; SSE2-NEXT: je LBB21_30 -; SSE2-NEXT: LBB21_29: ## %cond.store27 +; SSE2-NEXT: je LBB21_15 +; SSE2-NEXT: LBB21_31: ## %cond.store27 ; SSE2-NEXT: pextrw $6, %xmm3, %ecx ; SSE2-NEXT: movw %cx, 28(%rdi) ; SSE2-NEXT: testl $32768, %eax ## imm = 0x8000 -; SSE2-NEXT: je LBB21_32 -; SSE2-NEXT: LBB21_31: ## %cond.store29 +; SSE2-NEXT: je LBB21_16 +; SSE2-NEXT: LBB21_32: ## %cond.store29 ; SSE2-NEXT: pextrw $7, %xmm3, %eax ; SSE2-NEXT: movw %ax, 30(%rdi) ; SSE2-NEXT: retq @@ -3118,115 +3118,115 @@ define void @store_v16i16_v16i16(<16 x i16> %trigger, ptr %addr, <16 x i16> %val ; SSE4-NEXT: packsswb %xmm1, %xmm0 ; SSE4-NEXT: pmovmskb %xmm0, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne LBB21_1 -; SSE4-NEXT: ## %bb.2: ## %else +; SSE4-NEXT: jne LBB21_17 +; SSE4-NEXT: ## %bb.1: ## %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne LBB21_3 -; SSE4-NEXT: LBB21_4: ## %else2 +; SSE4-NEXT: jne LBB21_18 +; SSE4-NEXT: LBB21_2: ## %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne LBB21_5 -; SSE4-NEXT: LBB21_6: ## %else4 +; SSE4-NEXT: jne LBB21_19 +; SSE4-NEXT: LBB21_3: ## %else4 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne LBB21_7 -; SSE4-NEXT: LBB21_8: ## %else6 +; SSE4-NEXT: jne LBB21_20 +; SSE4-NEXT: LBB21_4: ## %else6 ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: jne LBB21_9 -; SSE4-NEXT: LBB21_10: ## %else8 +; SSE4-NEXT: jne LBB21_21 +; SSE4-NEXT: LBB21_5: ## %else8 ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: jne LBB21_11 -; SSE4-NEXT: LBB21_12: ## %else10 +; SSE4-NEXT: jne LBB21_22 +; SSE4-NEXT: LBB21_6: ## %else10 ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: jne LBB21_13 -; SSE4-NEXT: LBB21_14: ## %else12 +; SSE4-NEXT: jne LBB21_23 +; SSE4-NEXT: LBB21_7: ## %else12 ; SSE4-NEXT: testb %al, %al -; SSE4-NEXT: js LBB21_15 -; SSE4-NEXT: LBB21_16: ## %else14 +; SSE4-NEXT: js LBB21_24 +; SSE4-NEXT: LBB21_8: ## %else14 ; SSE4-NEXT: testl $256, %eax ## imm = 0x100 -; SSE4-NEXT: jne LBB21_17 -; SSE4-NEXT: LBB21_18: ## %else16 +; SSE4-NEXT: jne LBB21_25 +; SSE4-NEXT: LBB21_9: ## %else16 ; SSE4-NEXT: testl $512, %eax ## imm = 0x200 -; SSE4-NEXT: jne LBB21_19 -; SSE4-NEXT: LBB21_20: ## %else18 +; SSE4-NEXT: jne LBB21_26 +; SSE4-NEXT: LBB21_10: ## %else18 ; SSE4-NEXT: testl $1024, %eax ## imm = 0x400 -; SSE4-NEXT: jne LBB21_21 -; SSE4-NEXT: LBB21_22: ## %else20 +; SSE4-NEXT: jne LBB21_27 +; SSE4-NEXT: LBB21_11: ## %else20 ; SSE4-NEXT: testl $2048, %eax ## imm = 0x800 -; SSE4-NEXT: jne LBB21_23 -; SSE4-NEXT: LBB21_24: ## %else22 +; SSE4-NEXT: jne LBB21_28 +; SSE4-NEXT: LBB21_12: ## %else22 ; SSE4-NEXT: testl $4096, %eax ## imm = 0x1000 -; SSE4-NEXT: jne LBB21_25 -; SSE4-NEXT: LBB21_26: ## %else24 +; SSE4-NEXT: jne LBB21_29 +; SSE4-NEXT: LBB21_13: ## %else24 ; SSE4-NEXT: testl $8192, %eax ## imm = 0x2000 -; SSE4-NEXT: jne LBB21_27 -; SSE4-NEXT: LBB21_28: ## %else26 +; SSE4-NEXT: jne LBB21_30 +; SSE4-NEXT: LBB21_14: ## %else26 ; SSE4-NEXT: testl $16384, %eax ## imm = 0x4000 -; SSE4-NEXT: jne LBB21_29 -; SSE4-NEXT: LBB21_30: ## %else28 -; SSE4-NEXT: testl $32768, %eax ## imm = 0x8000 ; SSE4-NEXT: jne LBB21_31 -; SSE4-NEXT: LBB21_32: ## %else30 +; SSE4-NEXT: LBB21_15: ## %else28 +; SSE4-NEXT: testl $32768, %eax ## imm = 0x8000 +; SSE4-NEXT: jne LBB21_32 +; SSE4-NEXT: LBB21_16: ## %else30 ; SSE4-NEXT: retq -; SSE4-NEXT: LBB21_1: ## %cond.store +; SSE4-NEXT: LBB21_17: ## %cond.store ; SSE4-NEXT: pextrw $0, %xmm2, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je LBB21_4 -; SSE4-NEXT: LBB21_3: ## %cond.store1 +; SSE4-NEXT: je LBB21_2 +; SSE4-NEXT: LBB21_18: ## %cond.store1 ; SSE4-NEXT: pextrw $1, %xmm2, 2(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je LBB21_6 -; SSE4-NEXT: LBB21_5: ## %cond.store3 +; SSE4-NEXT: je LBB21_3 +; SSE4-NEXT: LBB21_19: ## %cond.store3 ; SSE4-NEXT: pextrw $2, %xmm2, 4(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je LBB21_8 -; SSE4-NEXT: LBB21_7: ## %cond.store5 +; SSE4-NEXT: je LBB21_4 +; SSE4-NEXT: LBB21_20: ## %cond.store5 ; SSE4-NEXT: pextrw $3, %xmm2, 6(%rdi) ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: je LBB21_10 -; SSE4-NEXT: LBB21_9: ## %cond.store7 +; SSE4-NEXT: je LBB21_5 +; SSE4-NEXT: LBB21_21: ## %cond.store7 ; SSE4-NEXT: pextrw $4, %xmm2, 8(%rdi) ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: je LBB21_12 -; SSE4-NEXT: LBB21_11: ## %cond.store9 +; SSE4-NEXT: je LBB21_6 +; SSE4-NEXT: LBB21_22: ## %cond.store9 ; SSE4-NEXT: pextrw $5, %xmm2, 10(%rdi) ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: je LBB21_14 -; SSE4-NEXT: LBB21_13: ## %cond.store11 +; SSE4-NEXT: je LBB21_7 +; SSE4-NEXT: LBB21_23: ## %cond.store11 ; SSE4-NEXT: pextrw $6, %xmm2, 12(%rdi) ; SSE4-NEXT: testb %al, %al -; SSE4-NEXT: jns LBB21_16 -; SSE4-NEXT: LBB21_15: ## %cond.store13 +; SSE4-NEXT: jns LBB21_8 +; SSE4-NEXT: LBB21_24: ## %cond.store13 ; SSE4-NEXT: pextrw $7, %xmm2, 14(%rdi) ; SSE4-NEXT: testl $256, %eax ## imm = 0x100 -; SSE4-NEXT: je LBB21_18 -; SSE4-NEXT: LBB21_17: ## %cond.store15 +; SSE4-NEXT: je LBB21_9 +; SSE4-NEXT: LBB21_25: ## %cond.store15 ; SSE4-NEXT: pextrw $0, %xmm3, 16(%rdi) ; SSE4-NEXT: testl $512, %eax ## imm = 0x200 -; SSE4-NEXT: je LBB21_20 -; SSE4-NEXT: LBB21_19: ## %cond.store17 +; SSE4-NEXT: je LBB21_10 +; SSE4-NEXT: LBB21_26: ## %cond.store17 ; SSE4-NEXT: pextrw $1, %xmm3, 18(%rdi) ; SSE4-NEXT: testl $1024, %eax ## imm = 0x400 -; SSE4-NEXT: je LBB21_22 -; SSE4-NEXT: LBB21_21: ## %cond.store19 +; SSE4-NEXT: je LBB21_11 +; SSE4-NEXT: LBB21_27: ## %cond.store19 ; SSE4-NEXT: pextrw $2, %xmm3, 20(%rdi) ; SSE4-NEXT: testl $2048, %eax ## imm = 0x800 -; SSE4-NEXT: je LBB21_24 -; SSE4-NEXT: LBB21_23: ## %cond.store21 +; SSE4-NEXT: je LBB21_12 +; SSE4-NEXT: LBB21_28: ## %cond.store21 ; SSE4-NEXT: pextrw $3, %xmm3, 22(%rdi) ; SSE4-NEXT: testl $4096, %eax ## imm = 0x1000 -; SSE4-NEXT: je LBB21_26 -; SSE4-NEXT: LBB21_25: ## %cond.store23 +; SSE4-NEXT: je LBB21_13 +; SSE4-NEXT: LBB21_29: ## %cond.store23 ; SSE4-NEXT: pextrw $4, %xmm3, 24(%rdi) ; SSE4-NEXT: testl $8192, %eax ## imm = 0x2000 -; SSE4-NEXT: je LBB21_28 -; SSE4-NEXT: LBB21_27: ## %cond.store25 +; SSE4-NEXT: je LBB21_14 +; SSE4-NEXT: LBB21_30: ## %cond.store25 ; SSE4-NEXT: pextrw $5, %xmm3, 26(%rdi) ; SSE4-NEXT: testl $16384, %eax ## imm = 0x4000 -; SSE4-NEXT: je LBB21_30 -; SSE4-NEXT: LBB21_29: ## %cond.store27 +; SSE4-NEXT: je LBB21_15 +; SSE4-NEXT: LBB21_31: ## %cond.store27 ; SSE4-NEXT: pextrw $6, %xmm3, 28(%rdi) ; SSE4-NEXT: testl $32768, %eax ## imm = 0x8000 -; SSE4-NEXT: je LBB21_32 -; SSE4-NEXT: LBB21_31: ## %cond.store29 +; SSE4-NEXT: je LBB21_16 +; SSE4-NEXT: LBB21_32: ## %cond.store29 ; SSE4-NEXT: pextrw $7, %xmm3, 30(%rdi) ; SSE4-NEXT: retq ; @@ -3239,116 +3239,116 @@ define void @store_v16i16_v16i16(<16 x i16> %trigger, ptr %addr, <16 x i16> %val ; AVX1-NEXT: vpacksswb %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vpmovmskb %xmm0, %eax ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne LBB21_1 -; AVX1-NEXT: ## %bb.2: ## %else +; AVX1-NEXT: jne LBB21_18 +; AVX1-NEXT: ## %bb.1: ## %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne LBB21_3 -; AVX1-NEXT: LBB21_4: ## %else2 +; AVX1-NEXT: jne LBB21_19 +; AVX1-NEXT: LBB21_2: ## %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne LBB21_5 -; AVX1-NEXT: LBB21_6: ## %else4 +; AVX1-NEXT: jne LBB21_20 +; AVX1-NEXT: LBB21_3: ## %else4 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne LBB21_7 -; AVX1-NEXT: LBB21_8: ## %else6 +; AVX1-NEXT: jne LBB21_21 +; AVX1-NEXT: LBB21_4: ## %else6 ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: jne LBB21_9 -; AVX1-NEXT: LBB21_10: ## %else8 +; AVX1-NEXT: jne LBB21_22 +; AVX1-NEXT: LBB21_5: ## %else8 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: jne LBB21_11 -; AVX1-NEXT: LBB21_12: ## %else10 +; AVX1-NEXT: jne LBB21_23 +; AVX1-NEXT: LBB21_6: ## %else10 ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: jne LBB21_13 -; AVX1-NEXT: LBB21_14: ## %else12 +; AVX1-NEXT: jne LBB21_24 +; AVX1-NEXT: LBB21_7: ## %else12 ; AVX1-NEXT: testb %al, %al -; AVX1-NEXT: jns LBB21_16 -; AVX1-NEXT: LBB21_15: ## %cond.store13 +; AVX1-NEXT: jns LBB21_9 +; AVX1-NEXT: LBB21_8: ## %cond.store13 ; AVX1-NEXT: vpextrw $7, %xmm1, 14(%rdi) -; AVX1-NEXT: LBB21_16: ## %else14 +; AVX1-NEXT: LBB21_9: ## %else14 ; AVX1-NEXT: testl $256, %eax ## imm = 0x100 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm0 -; AVX1-NEXT: jne LBB21_17 -; AVX1-NEXT: ## %bb.18: ## %else16 +; AVX1-NEXT: jne LBB21_25 +; AVX1-NEXT: ## %bb.10: ## %else16 ; AVX1-NEXT: testl $512, %eax ## imm = 0x200 -; AVX1-NEXT: jne LBB21_19 -; AVX1-NEXT: LBB21_20: ## %else18 +; AVX1-NEXT: jne LBB21_26 +; AVX1-NEXT: LBB21_11: ## %else18 ; AVX1-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX1-NEXT: jne LBB21_21 -; AVX1-NEXT: LBB21_22: ## %else20 +; AVX1-NEXT: jne LBB21_27 +; AVX1-NEXT: LBB21_12: ## %else20 ; AVX1-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX1-NEXT: jne LBB21_23 -; AVX1-NEXT: LBB21_24: ## %else22 +; AVX1-NEXT: jne LBB21_28 +; AVX1-NEXT: LBB21_13: ## %else22 ; AVX1-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX1-NEXT: jne LBB21_25 -; AVX1-NEXT: LBB21_26: ## %else24 +; AVX1-NEXT: jne LBB21_29 +; AVX1-NEXT: LBB21_14: ## %else24 ; AVX1-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX1-NEXT: jne LBB21_27 -; AVX1-NEXT: LBB21_28: ## %else26 +; AVX1-NEXT: jne LBB21_30 +; AVX1-NEXT: LBB21_15: ## %else26 ; AVX1-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX1-NEXT: jne LBB21_29 -; AVX1-NEXT: LBB21_30: ## %else28 -; AVX1-NEXT: testl $32768, %eax ## imm = 0x8000 ; AVX1-NEXT: jne LBB21_31 -; AVX1-NEXT: LBB21_32: ## %else30 +; AVX1-NEXT: LBB21_16: ## %else28 +; AVX1-NEXT: testl $32768, %eax ## imm = 0x8000 +; AVX1-NEXT: jne LBB21_32 +; AVX1-NEXT: LBB21_17: ## %else30 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: LBB21_1: ## %cond.store +; AVX1-NEXT: LBB21_18: ## %cond.store ; AVX1-NEXT: vpextrw $0, %xmm1, (%rdi) ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je LBB21_4 -; AVX1-NEXT: LBB21_3: ## %cond.store1 +; AVX1-NEXT: je LBB21_2 +; AVX1-NEXT: LBB21_19: ## %cond.store1 ; AVX1-NEXT: vpextrw $1, %xmm1, 2(%rdi) ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je LBB21_6 -; AVX1-NEXT: LBB21_5: ## %cond.store3 +; AVX1-NEXT: je LBB21_3 +; AVX1-NEXT: LBB21_20: ## %cond.store3 ; AVX1-NEXT: vpextrw $2, %xmm1, 4(%rdi) ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je LBB21_8 -; AVX1-NEXT: LBB21_7: ## %cond.store5 +; AVX1-NEXT: je LBB21_4 +; AVX1-NEXT: LBB21_21: ## %cond.store5 ; AVX1-NEXT: vpextrw $3, %xmm1, 6(%rdi) ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: je LBB21_10 -; AVX1-NEXT: LBB21_9: ## %cond.store7 +; AVX1-NEXT: je LBB21_5 +; AVX1-NEXT: LBB21_22: ## %cond.store7 ; AVX1-NEXT: vpextrw $4, %xmm1, 8(%rdi) ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je LBB21_12 -; AVX1-NEXT: LBB21_11: ## %cond.store9 +; AVX1-NEXT: je LBB21_6 +; AVX1-NEXT: LBB21_23: ## %cond.store9 ; AVX1-NEXT: vpextrw $5, %xmm1, 10(%rdi) ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: je LBB21_14 -; AVX1-NEXT: LBB21_13: ## %cond.store11 +; AVX1-NEXT: je LBB21_7 +; AVX1-NEXT: LBB21_24: ## %cond.store11 ; AVX1-NEXT: vpextrw $6, %xmm1, 12(%rdi) ; AVX1-NEXT: testb %al, %al -; AVX1-NEXT: js LBB21_15 -; AVX1-NEXT: jmp LBB21_16 -; AVX1-NEXT: LBB21_17: ## %cond.store15 +; AVX1-NEXT: js LBB21_8 +; AVX1-NEXT: jmp LBB21_9 +; AVX1-NEXT: LBB21_25: ## %cond.store15 ; AVX1-NEXT: vpextrw $0, %xmm0, 16(%rdi) ; AVX1-NEXT: testl $512, %eax ## imm = 0x200 -; AVX1-NEXT: je LBB21_20 -; AVX1-NEXT: LBB21_19: ## %cond.store17 +; AVX1-NEXT: je LBB21_11 +; AVX1-NEXT: LBB21_26: ## %cond.store17 ; AVX1-NEXT: vpextrw $1, %xmm0, 18(%rdi) ; AVX1-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX1-NEXT: je LBB21_22 -; AVX1-NEXT: LBB21_21: ## %cond.store19 +; AVX1-NEXT: je LBB21_12 +; AVX1-NEXT: LBB21_27: ## %cond.store19 ; AVX1-NEXT: vpextrw $2, %xmm0, 20(%rdi) ; AVX1-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX1-NEXT: je LBB21_24 -; AVX1-NEXT: LBB21_23: ## %cond.store21 +; AVX1-NEXT: je LBB21_13 +; AVX1-NEXT: LBB21_28: ## %cond.store21 ; AVX1-NEXT: vpextrw $3, %xmm0, 22(%rdi) ; AVX1-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX1-NEXT: je LBB21_26 -; AVX1-NEXT: LBB21_25: ## %cond.store23 +; AVX1-NEXT: je LBB21_14 +; AVX1-NEXT: LBB21_29: ## %cond.store23 ; AVX1-NEXT: vpextrw $4, %xmm0, 24(%rdi) ; AVX1-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX1-NEXT: je LBB21_28 -; AVX1-NEXT: LBB21_27: ## %cond.store25 +; AVX1-NEXT: je LBB21_15 +; AVX1-NEXT: LBB21_30: ## %cond.store25 ; AVX1-NEXT: vpextrw $5, %xmm0, 26(%rdi) ; AVX1-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX1-NEXT: je LBB21_30 -; AVX1-NEXT: LBB21_29: ## %cond.store27 +; AVX1-NEXT: je LBB21_16 +; AVX1-NEXT: LBB21_31: ## %cond.store27 ; AVX1-NEXT: vpextrw $6, %xmm0, 28(%rdi) ; AVX1-NEXT: testl $32768, %eax ## imm = 0x8000 -; AVX1-NEXT: je LBB21_32 -; AVX1-NEXT: LBB21_31: ## %cond.store29 +; AVX1-NEXT: je LBB21_17 +; AVX1-NEXT: LBB21_32: ## %cond.store29 ; AVX1-NEXT: vpextrw $7, %xmm0, 30(%rdi) ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq @@ -3361,116 +3361,116 @@ define void @store_v16i16_v16i16(<16 x i16> %trigger, ptr %addr, <16 x i16> %val ; AVX2-NEXT: vpacksswb %xmm2, %xmm0, %xmm0 ; AVX2-NEXT: vpmovmskb %xmm0, %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne LBB21_1 -; AVX2-NEXT: ## %bb.2: ## %else +; AVX2-NEXT: jne LBB21_18 +; AVX2-NEXT: ## %bb.1: ## %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne LBB21_3 -; AVX2-NEXT: LBB21_4: ## %else2 +; AVX2-NEXT: jne LBB21_19 +; AVX2-NEXT: LBB21_2: ## %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne LBB21_5 -; AVX2-NEXT: LBB21_6: ## %else4 +; AVX2-NEXT: jne LBB21_20 +; AVX2-NEXT: LBB21_3: ## %else4 ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: jne LBB21_7 -; AVX2-NEXT: LBB21_8: ## %else6 +; AVX2-NEXT: jne LBB21_21 +; AVX2-NEXT: LBB21_4: ## %else6 ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: jne LBB21_9 -; AVX2-NEXT: LBB21_10: ## %else8 +; AVX2-NEXT: jne LBB21_22 +; AVX2-NEXT: LBB21_5: ## %else8 ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: jne LBB21_11 -; AVX2-NEXT: LBB21_12: ## %else10 +; AVX2-NEXT: jne LBB21_23 +; AVX2-NEXT: LBB21_6: ## %else10 ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: jne LBB21_13 -; AVX2-NEXT: LBB21_14: ## %else12 +; AVX2-NEXT: jne LBB21_24 +; AVX2-NEXT: LBB21_7: ## %else12 ; AVX2-NEXT: testb %al, %al -; AVX2-NEXT: jns LBB21_16 -; AVX2-NEXT: LBB21_15: ## %cond.store13 +; AVX2-NEXT: jns LBB21_9 +; AVX2-NEXT: LBB21_8: ## %cond.store13 ; AVX2-NEXT: vpextrw $7, %xmm1, 14(%rdi) -; AVX2-NEXT: LBB21_16: ## %else14 +; AVX2-NEXT: LBB21_9: ## %else14 ; AVX2-NEXT: testl $256, %eax ## imm = 0x100 ; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm0 -; AVX2-NEXT: jne LBB21_17 -; AVX2-NEXT: ## %bb.18: ## %else16 +; AVX2-NEXT: jne LBB21_25 +; AVX2-NEXT: ## %bb.10: ## %else16 ; AVX2-NEXT: testl $512, %eax ## imm = 0x200 -; AVX2-NEXT: jne LBB21_19 -; AVX2-NEXT: LBB21_20: ## %else18 +; AVX2-NEXT: jne LBB21_26 +; AVX2-NEXT: LBB21_11: ## %else18 ; AVX2-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX2-NEXT: jne LBB21_21 -; AVX2-NEXT: LBB21_22: ## %else20 +; AVX2-NEXT: jne LBB21_27 +; AVX2-NEXT: LBB21_12: ## %else20 ; AVX2-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX2-NEXT: jne LBB21_23 -; AVX2-NEXT: LBB21_24: ## %else22 +; AVX2-NEXT: jne LBB21_28 +; AVX2-NEXT: LBB21_13: ## %else22 ; AVX2-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX2-NEXT: jne LBB21_25 -; AVX2-NEXT: LBB21_26: ## %else24 +; AVX2-NEXT: jne LBB21_29 +; AVX2-NEXT: LBB21_14: ## %else24 ; AVX2-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX2-NEXT: jne LBB21_27 -; AVX2-NEXT: LBB21_28: ## %else26 +; AVX2-NEXT: jne LBB21_30 +; AVX2-NEXT: LBB21_15: ## %else26 ; AVX2-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX2-NEXT: jne LBB21_29 -; AVX2-NEXT: LBB21_30: ## %else28 -; AVX2-NEXT: testl $32768, %eax ## imm = 0x8000 ; AVX2-NEXT: jne LBB21_31 -; AVX2-NEXT: LBB21_32: ## %else30 +; AVX2-NEXT: LBB21_16: ## %else28 +; AVX2-NEXT: testl $32768, %eax ## imm = 0x8000 +; AVX2-NEXT: jne LBB21_32 +; AVX2-NEXT: LBB21_17: ## %else30 ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; AVX2-NEXT: LBB21_1: ## %cond.store +; AVX2-NEXT: LBB21_18: ## %cond.store ; AVX2-NEXT: vpextrw $0, %xmm1, (%rdi) ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je LBB21_4 -; AVX2-NEXT: LBB21_3: ## %cond.store1 +; AVX2-NEXT: je LBB21_2 +; AVX2-NEXT: LBB21_19: ## %cond.store1 ; AVX2-NEXT: vpextrw $1, %xmm1, 2(%rdi) ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je LBB21_6 -; AVX2-NEXT: LBB21_5: ## %cond.store3 +; AVX2-NEXT: je LBB21_3 +; AVX2-NEXT: LBB21_20: ## %cond.store3 ; AVX2-NEXT: vpextrw $2, %xmm1, 4(%rdi) ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je LBB21_8 -; AVX2-NEXT: LBB21_7: ## %cond.store5 +; AVX2-NEXT: je LBB21_4 +; AVX2-NEXT: LBB21_21: ## %cond.store5 ; AVX2-NEXT: vpextrw $3, %xmm1, 6(%rdi) ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: je LBB21_10 -; AVX2-NEXT: LBB21_9: ## %cond.store7 +; AVX2-NEXT: je LBB21_5 +; AVX2-NEXT: LBB21_22: ## %cond.store7 ; AVX2-NEXT: vpextrw $4, %xmm1, 8(%rdi) ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: je LBB21_12 -; AVX2-NEXT: LBB21_11: ## %cond.store9 +; AVX2-NEXT: je LBB21_6 +; AVX2-NEXT: LBB21_23: ## %cond.store9 ; AVX2-NEXT: vpextrw $5, %xmm1, 10(%rdi) ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: je LBB21_14 -; AVX2-NEXT: LBB21_13: ## %cond.store11 +; AVX2-NEXT: je LBB21_7 +; AVX2-NEXT: LBB21_24: ## %cond.store11 ; AVX2-NEXT: vpextrw $6, %xmm1, 12(%rdi) ; AVX2-NEXT: testb %al, %al -; AVX2-NEXT: js LBB21_15 -; AVX2-NEXT: jmp LBB21_16 -; AVX2-NEXT: LBB21_17: ## %cond.store15 +; AVX2-NEXT: js LBB21_8 +; AVX2-NEXT: jmp LBB21_9 +; AVX2-NEXT: LBB21_25: ## %cond.store15 ; AVX2-NEXT: vpextrw $0, %xmm0, 16(%rdi) ; AVX2-NEXT: testl $512, %eax ## imm = 0x200 -; AVX2-NEXT: je LBB21_20 -; AVX2-NEXT: LBB21_19: ## %cond.store17 +; AVX2-NEXT: je LBB21_11 +; AVX2-NEXT: LBB21_26: ## %cond.store17 ; AVX2-NEXT: vpextrw $1, %xmm0, 18(%rdi) ; AVX2-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX2-NEXT: je LBB21_22 -; AVX2-NEXT: LBB21_21: ## %cond.store19 +; AVX2-NEXT: je LBB21_12 +; AVX2-NEXT: LBB21_27: ## %cond.store19 ; AVX2-NEXT: vpextrw $2, %xmm0, 20(%rdi) ; AVX2-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX2-NEXT: je LBB21_24 -; AVX2-NEXT: LBB21_23: ## %cond.store21 +; AVX2-NEXT: je LBB21_13 +; AVX2-NEXT: LBB21_28: ## %cond.store21 ; AVX2-NEXT: vpextrw $3, %xmm0, 22(%rdi) ; AVX2-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX2-NEXT: je LBB21_26 -; AVX2-NEXT: LBB21_25: ## %cond.store23 +; AVX2-NEXT: je LBB21_14 +; AVX2-NEXT: LBB21_29: ## %cond.store23 ; AVX2-NEXT: vpextrw $4, %xmm0, 24(%rdi) ; AVX2-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX2-NEXT: je LBB21_28 -; AVX2-NEXT: LBB21_27: ## %cond.store25 +; AVX2-NEXT: je LBB21_15 +; AVX2-NEXT: LBB21_30: ## %cond.store25 ; AVX2-NEXT: vpextrw $5, %xmm0, 26(%rdi) ; AVX2-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX2-NEXT: je LBB21_30 -; AVX2-NEXT: LBB21_29: ## %cond.store27 +; AVX2-NEXT: je LBB21_16 +; AVX2-NEXT: LBB21_31: ## %cond.store27 ; AVX2-NEXT: vpextrw $6, %xmm0, 28(%rdi) ; AVX2-NEXT: testl $32768, %eax ## imm = 0x8000 -; AVX2-NEXT: je LBB21_32 -; AVX2-NEXT: LBB21_31: ## %cond.store29 +; AVX2-NEXT: je LBB21_17 +; AVX2-NEXT: LBB21_32: ## %cond.store29 ; AVX2-NEXT: vpextrw $7, %xmm0, 30(%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq @@ -3483,116 +3483,116 @@ define void @store_v16i16_v16i16(<16 x i16> %trigger, ptr %addr, <16 x i16> %val ; AVX512F-NEXT: vptestmd %zmm0, %zmm0, %k0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne LBB21_1 -; AVX512F-NEXT: ## %bb.2: ## %else +; AVX512F-NEXT: jne LBB21_18 +; AVX512F-NEXT: ## %bb.1: ## %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne LBB21_3 -; AVX512F-NEXT: LBB21_4: ## %else2 +; AVX512F-NEXT: jne LBB21_19 +; AVX512F-NEXT: LBB21_2: ## %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne LBB21_5 -; AVX512F-NEXT: LBB21_6: ## %else4 +; AVX512F-NEXT: jne LBB21_20 +; AVX512F-NEXT: LBB21_3: ## %else4 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne LBB21_7 -; AVX512F-NEXT: LBB21_8: ## %else6 +; AVX512F-NEXT: jne LBB21_21 +; AVX512F-NEXT: LBB21_4: ## %else6 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne LBB21_9 -; AVX512F-NEXT: LBB21_10: ## %else8 +; AVX512F-NEXT: jne LBB21_22 +; AVX512F-NEXT: LBB21_5: ## %else8 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne LBB21_11 -; AVX512F-NEXT: LBB21_12: ## %else10 +; AVX512F-NEXT: jne LBB21_23 +; AVX512F-NEXT: LBB21_6: ## %else10 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne LBB21_13 -; AVX512F-NEXT: LBB21_14: ## %else12 +; AVX512F-NEXT: jne LBB21_24 +; AVX512F-NEXT: LBB21_7: ## %else12 ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: jns LBB21_16 -; AVX512F-NEXT: LBB21_15: ## %cond.store13 +; AVX512F-NEXT: jns LBB21_9 +; AVX512F-NEXT: LBB21_8: ## %cond.store13 ; AVX512F-NEXT: vpextrw $7, %xmm1, 14(%rdi) -; AVX512F-NEXT: LBB21_16: ## %else14 +; AVX512F-NEXT: LBB21_9: ## %else14 ; AVX512F-NEXT: testl $256, %eax ## imm = 0x100 ; AVX512F-NEXT: vextracti128 $1, %ymm1, %xmm0 -; AVX512F-NEXT: jne LBB21_17 -; AVX512F-NEXT: ## %bb.18: ## %else16 +; AVX512F-NEXT: jne LBB21_25 +; AVX512F-NEXT: ## %bb.10: ## %else16 ; AVX512F-NEXT: testl $512, %eax ## imm = 0x200 -; AVX512F-NEXT: jne LBB21_19 -; AVX512F-NEXT: LBB21_20: ## %else18 +; AVX512F-NEXT: jne LBB21_26 +; AVX512F-NEXT: LBB21_11: ## %else18 ; AVX512F-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX512F-NEXT: jne LBB21_21 -; AVX512F-NEXT: LBB21_22: ## %else20 +; AVX512F-NEXT: jne LBB21_27 +; AVX512F-NEXT: LBB21_12: ## %else20 ; AVX512F-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX512F-NEXT: jne LBB21_23 -; AVX512F-NEXT: LBB21_24: ## %else22 +; AVX512F-NEXT: jne LBB21_28 +; AVX512F-NEXT: LBB21_13: ## %else22 ; AVX512F-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX512F-NEXT: jne LBB21_25 -; AVX512F-NEXT: LBB21_26: ## %else24 +; AVX512F-NEXT: jne LBB21_29 +; AVX512F-NEXT: LBB21_14: ## %else24 ; AVX512F-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX512F-NEXT: jne LBB21_27 -; AVX512F-NEXT: LBB21_28: ## %else26 +; AVX512F-NEXT: jne LBB21_30 +; AVX512F-NEXT: LBB21_15: ## %else26 ; AVX512F-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX512F-NEXT: jne LBB21_29 -; AVX512F-NEXT: LBB21_30: ## %else28 -; AVX512F-NEXT: testl $32768, %eax ## imm = 0x8000 ; AVX512F-NEXT: jne LBB21_31 -; AVX512F-NEXT: LBB21_32: ## %else30 +; AVX512F-NEXT: LBB21_16: ## %else28 +; AVX512F-NEXT: testl $32768, %eax ## imm = 0x8000 +; AVX512F-NEXT: jne LBB21_32 +; AVX512F-NEXT: LBB21_17: ## %else30 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: LBB21_1: ## %cond.store +; AVX512F-NEXT: LBB21_18: ## %cond.store ; AVX512F-NEXT: vpextrw $0, %xmm1, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je LBB21_4 -; AVX512F-NEXT: LBB21_3: ## %cond.store1 +; AVX512F-NEXT: je LBB21_2 +; AVX512F-NEXT: LBB21_19: ## %cond.store1 ; AVX512F-NEXT: vpextrw $1, %xmm1, 2(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je LBB21_6 -; AVX512F-NEXT: LBB21_5: ## %cond.store3 +; AVX512F-NEXT: je LBB21_3 +; AVX512F-NEXT: LBB21_20: ## %cond.store3 ; AVX512F-NEXT: vpextrw $2, %xmm1, 4(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je LBB21_8 -; AVX512F-NEXT: LBB21_7: ## %cond.store5 +; AVX512F-NEXT: je LBB21_4 +; AVX512F-NEXT: LBB21_21: ## %cond.store5 ; AVX512F-NEXT: vpextrw $3, %xmm1, 6(%rdi) ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je LBB21_10 -; AVX512F-NEXT: LBB21_9: ## %cond.store7 +; AVX512F-NEXT: je LBB21_5 +; AVX512F-NEXT: LBB21_22: ## %cond.store7 ; AVX512F-NEXT: vpextrw $4, %xmm1, 8(%rdi) ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je LBB21_12 -; AVX512F-NEXT: LBB21_11: ## %cond.store9 +; AVX512F-NEXT: je LBB21_6 +; AVX512F-NEXT: LBB21_23: ## %cond.store9 ; AVX512F-NEXT: vpextrw $5, %xmm1, 10(%rdi) ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je LBB21_14 -; AVX512F-NEXT: LBB21_13: ## %cond.store11 +; AVX512F-NEXT: je LBB21_7 +; AVX512F-NEXT: LBB21_24: ## %cond.store11 ; AVX512F-NEXT: vpextrw $6, %xmm1, 12(%rdi) ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: js LBB21_15 -; AVX512F-NEXT: jmp LBB21_16 -; AVX512F-NEXT: LBB21_17: ## %cond.store15 +; AVX512F-NEXT: js LBB21_8 +; AVX512F-NEXT: jmp LBB21_9 +; AVX512F-NEXT: LBB21_25: ## %cond.store15 ; AVX512F-NEXT: vpextrw $0, %xmm0, 16(%rdi) ; AVX512F-NEXT: testl $512, %eax ## imm = 0x200 -; AVX512F-NEXT: je LBB21_20 -; AVX512F-NEXT: LBB21_19: ## %cond.store17 +; AVX512F-NEXT: je LBB21_11 +; AVX512F-NEXT: LBB21_26: ## %cond.store17 ; AVX512F-NEXT: vpextrw $1, %xmm0, 18(%rdi) ; AVX512F-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX512F-NEXT: je LBB21_22 -; AVX512F-NEXT: LBB21_21: ## %cond.store19 +; AVX512F-NEXT: je LBB21_12 +; AVX512F-NEXT: LBB21_27: ## %cond.store19 ; AVX512F-NEXT: vpextrw $2, %xmm0, 20(%rdi) ; AVX512F-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX512F-NEXT: je LBB21_24 -; AVX512F-NEXT: LBB21_23: ## %cond.store21 +; AVX512F-NEXT: je LBB21_13 +; AVX512F-NEXT: LBB21_28: ## %cond.store21 ; AVX512F-NEXT: vpextrw $3, %xmm0, 22(%rdi) ; AVX512F-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX512F-NEXT: je LBB21_26 -; AVX512F-NEXT: LBB21_25: ## %cond.store23 +; AVX512F-NEXT: je LBB21_14 +; AVX512F-NEXT: LBB21_29: ## %cond.store23 ; AVX512F-NEXT: vpextrw $4, %xmm0, 24(%rdi) ; AVX512F-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX512F-NEXT: je LBB21_28 -; AVX512F-NEXT: LBB21_27: ## %cond.store25 +; AVX512F-NEXT: je LBB21_15 +; AVX512F-NEXT: LBB21_30: ## %cond.store25 ; AVX512F-NEXT: vpextrw $5, %xmm0, 26(%rdi) ; AVX512F-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX512F-NEXT: je LBB21_30 -; AVX512F-NEXT: LBB21_29: ## %cond.store27 +; AVX512F-NEXT: je LBB21_16 +; AVX512F-NEXT: LBB21_31: ## %cond.store27 ; AVX512F-NEXT: vpextrw $6, %xmm0, 28(%rdi) ; AVX512F-NEXT: testl $32768, %eax ## imm = 0x8000 -; AVX512F-NEXT: je LBB21_32 -; AVX512F-NEXT: LBB21_31: ## %cond.store29 +; AVX512F-NEXT: je LBB21_17 +; AVX512F-NEXT: LBB21_32: ## %cond.store29 ; AVX512F-NEXT: vpextrw $7, %xmm0, 30(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -3605,116 +3605,116 @@ define void @store_v16i16_v16i16(<16 x i16> %trigger, ptr %addr, <16 x i16> %val ; AVX512VLDQ-NEXT: vpmovd2m %zmm0, %k0 ; AVX512VLDQ-NEXT: kmovw %k0, %eax ; AVX512VLDQ-NEXT: testb $1, %al -; AVX512VLDQ-NEXT: jne LBB21_1 -; AVX512VLDQ-NEXT: ## %bb.2: ## %else +; AVX512VLDQ-NEXT: jne LBB21_18 +; AVX512VLDQ-NEXT: ## %bb.1: ## %else ; AVX512VLDQ-NEXT: testb $2, %al -; AVX512VLDQ-NEXT: jne LBB21_3 -; AVX512VLDQ-NEXT: LBB21_4: ## %else2 +; AVX512VLDQ-NEXT: jne LBB21_19 +; AVX512VLDQ-NEXT: LBB21_2: ## %else2 ; AVX512VLDQ-NEXT: testb $4, %al -; AVX512VLDQ-NEXT: jne LBB21_5 -; AVX512VLDQ-NEXT: LBB21_6: ## %else4 +; AVX512VLDQ-NEXT: jne LBB21_20 +; AVX512VLDQ-NEXT: LBB21_3: ## %else4 ; AVX512VLDQ-NEXT: testb $8, %al -; AVX512VLDQ-NEXT: jne LBB21_7 -; AVX512VLDQ-NEXT: LBB21_8: ## %else6 +; AVX512VLDQ-NEXT: jne LBB21_21 +; AVX512VLDQ-NEXT: LBB21_4: ## %else6 ; AVX512VLDQ-NEXT: testb $16, %al -; AVX512VLDQ-NEXT: jne LBB21_9 -; AVX512VLDQ-NEXT: LBB21_10: ## %else8 +; AVX512VLDQ-NEXT: jne LBB21_22 +; AVX512VLDQ-NEXT: LBB21_5: ## %else8 ; AVX512VLDQ-NEXT: testb $32, %al -; AVX512VLDQ-NEXT: jne LBB21_11 -; AVX512VLDQ-NEXT: LBB21_12: ## %else10 +; AVX512VLDQ-NEXT: jne LBB21_23 +; AVX512VLDQ-NEXT: LBB21_6: ## %else10 ; AVX512VLDQ-NEXT: testb $64, %al -; AVX512VLDQ-NEXT: jne LBB21_13 -; AVX512VLDQ-NEXT: LBB21_14: ## %else12 +; AVX512VLDQ-NEXT: jne LBB21_24 +; AVX512VLDQ-NEXT: LBB21_7: ## %else12 ; AVX512VLDQ-NEXT: testb %al, %al -; AVX512VLDQ-NEXT: jns LBB21_16 -; AVX512VLDQ-NEXT: LBB21_15: ## %cond.store13 +; AVX512VLDQ-NEXT: jns LBB21_9 +; AVX512VLDQ-NEXT: LBB21_8: ## %cond.store13 ; AVX512VLDQ-NEXT: vpextrw $7, %xmm1, 14(%rdi) -; AVX512VLDQ-NEXT: LBB21_16: ## %else14 +; AVX512VLDQ-NEXT: LBB21_9: ## %else14 ; AVX512VLDQ-NEXT: testl $256, %eax ## imm = 0x100 ; AVX512VLDQ-NEXT: vextracti128 $1, %ymm1, %xmm0 -; AVX512VLDQ-NEXT: jne LBB21_17 -; AVX512VLDQ-NEXT: ## %bb.18: ## %else16 +; AVX512VLDQ-NEXT: jne LBB21_25 +; AVX512VLDQ-NEXT: ## %bb.10: ## %else16 ; AVX512VLDQ-NEXT: testl $512, %eax ## imm = 0x200 -; AVX512VLDQ-NEXT: jne LBB21_19 -; AVX512VLDQ-NEXT: LBB21_20: ## %else18 +; AVX512VLDQ-NEXT: jne LBB21_26 +; AVX512VLDQ-NEXT: LBB21_11: ## %else18 ; AVX512VLDQ-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX512VLDQ-NEXT: jne LBB21_21 -; AVX512VLDQ-NEXT: LBB21_22: ## %else20 +; AVX512VLDQ-NEXT: jne LBB21_27 +; AVX512VLDQ-NEXT: LBB21_12: ## %else20 ; AVX512VLDQ-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX512VLDQ-NEXT: jne LBB21_23 -; AVX512VLDQ-NEXT: LBB21_24: ## %else22 +; AVX512VLDQ-NEXT: jne LBB21_28 +; AVX512VLDQ-NEXT: LBB21_13: ## %else22 ; AVX512VLDQ-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX512VLDQ-NEXT: jne LBB21_25 -; AVX512VLDQ-NEXT: LBB21_26: ## %else24 +; AVX512VLDQ-NEXT: jne LBB21_29 +; AVX512VLDQ-NEXT: LBB21_14: ## %else24 ; AVX512VLDQ-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX512VLDQ-NEXT: jne LBB21_27 -; AVX512VLDQ-NEXT: LBB21_28: ## %else26 +; AVX512VLDQ-NEXT: jne LBB21_30 +; AVX512VLDQ-NEXT: LBB21_15: ## %else26 ; AVX512VLDQ-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX512VLDQ-NEXT: jne LBB21_29 -; AVX512VLDQ-NEXT: LBB21_30: ## %else28 -; AVX512VLDQ-NEXT: testl $32768, %eax ## imm = 0x8000 ; AVX512VLDQ-NEXT: jne LBB21_31 -; AVX512VLDQ-NEXT: LBB21_32: ## %else30 +; AVX512VLDQ-NEXT: LBB21_16: ## %else28 +; AVX512VLDQ-NEXT: testl $32768, %eax ## imm = 0x8000 +; AVX512VLDQ-NEXT: jne LBB21_32 +; AVX512VLDQ-NEXT: LBB21_17: ## %else30 ; AVX512VLDQ-NEXT: vzeroupper ; AVX512VLDQ-NEXT: retq -; AVX512VLDQ-NEXT: LBB21_1: ## %cond.store +; AVX512VLDQ-NEXT: LBB21_18: ## %cond.store ; AVX512VLDQ-NEXT: vpextrw $0, %xmm1, (%rdi) ; AVX512VLDQ-NEXT: testb $2, %al -; AVX512VLDQ-NEXT: je LBB21_4 -; AVX512VLDQ-NEXT: LBB21_3: ## %cond.store1 +; AVX512VLDQ-NEXT: je LBB21_2 +; AVX512VLDQ-NEXT: LBB21_19: ## %cond.store1 ; AVX512VLDQ-NEXT: vpextrw $1, %xmm1, 2(%rdi) ; AVX512VLDQ-NEXT: testb $4, %al -; AVX512VLDQ-NEXT: je LBB21_6 -; AVX512VLDQ-NEXT: LBB21_5: ## %cond.store3 +; AVX512VLDQ-NEXT: je LBB21_3 +; AVX512VLDQ-NEXT: LBB21_20: ## %cond.store3 ; AVX512VLDQ-NEXT: vpextrw $2, %xmm1, 4(%rdi) ; AVX512VLDQ-NEXT: testb $8, %al -; AVX512VLDQ-NEXT: je LBB21_8 -; AVX512VLDQ-NEXT: LBB21_7: ## %cond.store5 +; AVX512VLDQ-NEXT: je LBB21_4 +; AVX512VLDQ-NEXT: LBB21_21: ## %cond.store5 ; AVX512VLDQ-NEXT: vpextrw $3, %xmm1, 6(%rdi) ; AVX512VLDQ-NEXT: testb $16, %al -; AVX512VLDQ-NEXT: je LBB21_10 -; AVX512VLDQ-NEXT: LBB21_9: ## %cond.store7 +; AVX512VLDQ-NEXT: je LBB21_5 +; AVX512VLDQ-NEXT: LBB21_22: ## %cond.store7 ; AVX512VLDQ-NEXT: vpextrw $4, %xmm1, 8(%rdi) ; AVX512VLDQ-NEXT: testb $32, %al -; AVX512VLDQ-NEXT: je LBB21_12 -; AVX512VLDQ-NEXT: LBB21_11: ## %cond.store9 +; AVX512VLDQ-NEXT: je LBB21_6 +; AVX512VLDQ-NEXT: LBB21_23: ## %cond.store9 ; AVX512VLDQ-NEXT: vpextrw $5, %xmm1, 10(%rdi) ; AVX512VLDQ-NEXT: testb $64, %al -; AVX512VLDQ-NEXT: je LBB21_14 -; AVX512VLDQ-NEXT: LBB21_13: ## %cond.store11 +; AVX512VLDQ-NEXT: je LBB21_7 +; AVX512VLDQ-NEXT: LBB21_24: ## %cond.store11 ; AVX512VLDQ-NEXT: vpextrw $6, %xmm1, 12(%rdi) ; AVX512VLDQ-NEXT: testb %al, %al -; AVX512VLDQ-NEXT: js LBB21_15 -; AVX512VLDQ-NEXT: jmp LBB21_16 -; AVX512VLDQ-NEXT: LBB21_17: ## %cond.store15 +; AVX512VLDQ-NEXT: js LBB21_8 +; AVX512VLDQ-NEXT: jmp LBB21_9 +; AVX512VLDQ-NEXT: LBB21_25: ## %cond.store15 ; AVX512VLDQ-NEXT: vpextrw $0, %xmm0, 16(%rdi) ; AVX512VLDQ-NEXT: testl $512, %eax ## imm = 0x200 -; AVX512VLDQ-NEXT: je LBB21_20 -; AVX512VLDQ-NEXT: LBB21_19: ## %cond.store17 +; AVX512VLDQ-NEXT: je LBB21_11 +; AVX512VLDQ-NEXT: LBB21_26: ## %cond.store17 ; AVX512VLDQ-NEXT: vpextrw $1, %xmm0, 18(%rdi) ; AVX512VLDQ-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX512VLDQ-NEXT: je LBB21_22 -; AVX512VLDQ-NEXT: LBB21_21: ## %cond.store19 +; AVX512VLDQ-NEXT: je LBB21_12 +; AVX512VLDQ-NEXT: LBB21_27: ## %cond.store19 ; AVX512VLDQ-NEXT: vpextrw $2, %xmm0, 20(%rdi) ; AVX512VLDQ-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX512VLDQ-NEXT: je LBB21_24 -; AVX512VLDQ-NEXT: LBB21_23: ## %cond.store21 +; AVX512VLDQ-NEXT: je LBB21_13 +; AVX512VLDQ-NEXT: LBB21_28: ## %cond.store21 ; AVX512VLDQ-NEXT: vpextrw $3, %xmm0, 22(%rdi) ; AVX512VLDQ-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX512VLDQ-NEXT: je LBB21_26 -; AVX512VLDQ-NEXT: LBB21_25: ## %cond.store23 +; AVX512VLDQ-NEXT: je LBB21_14 +; AVX512VLDQ-NEXT: LBB21_29: ## %cond.store23 ; AVX512VLDQ-NEXT: vpextrw $4, %xmm0, 24(%rdi) ; AVX512VLDQ-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX512VLDQ-NEXT: je LBB21_28 -; AVX512VLDQ-NEXT: LBB21_27: ## %cond.store25 +; AVX512VLDQ-NEXT: je LBB21_15 +; AVX512VLDQ-NEXT: LBB21_30: ## %cond.store25 ; AVX512VLDQ-NEXT: vpextrw $5, %xmm0, 26(%rdi) ; AVX512VLDQ-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX512VLDQ-NEXT: je LBB21_30 -; AVX512VLDQ-NEXT: LBB21_29: ## %cond.store27 +; AVX512VLDQ-NEXT: je LBB21_16 +; AVX512VLDQ-NEXT: LBB21_31: ## %cond.store27 ; AVX512VLDQ-NEXT: vpextrw $6, %xmm0, 28(%rdi) ; AVX512VLDQ-NEXT: testl $32768, %eax ## imm = 0x8000 -; AVX512VLDQ-NEXT: je LBB21_32 -; AVX512VLDQ-NEXT: LBB21_31: ## %cond.store29 +; AVX512VLDQ-NEXT: je LBB21_17 +; AVX512VLDQ-NEXT: LBB21_32: ## %cond.store29 ; AVX512VLDQ-NEXT: vpextrw $7, %xmm0, 30(%rdi) ; AVX512VLDQ-NEXT: vzeroupper ; AVX512VLDQ-NEXT: retq @@ -3750,103 +3750,103 @@ define void @store_v16i8_v16i8(<16 x i8> %trigger, ptr %addr, <16 x i8> %val) no ; SSE2-NEXT: pmovmskb %xmm2, %eax ; SSE2-NEXT: testb $1, %al ; SSE2-NEXT: movd %xmm1, %ecx -; SSE2-NEXT: jne LBB22_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB22_28 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB22_3 -; SSE2-NEXT: LBB22_4: ## %else2 +; SSE2-NEXT: jne LBB22_29 +; SSE2-NEXT: LBB22_2: ## %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB22_5 -; SSE2-NEXT: LBB22_6: ## %else4 +; SSE2-NEXT: jne LBB22_30 +; SSE2-NEXT: LBB22_3: ## %else4 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB22_8 -; SSE2-NEXT: LBB22_7: ## %cond.store5 +; SSE2-NEXT: je LBB22_5 +; SSE2-NEXT: LBB22_4: ## %cond.store5 ; SSE2-NEXT: shrl $24, %ecx ; SSE2-NEXT: movb %cl, 3(%rdi) -; SSE2-NEXT: LBB22_8: ## %else6 +; SSE2-NEXT: LBB22_5: ## %else6 ; SSE2-NEXT: testb $16, %al ; SSE2-NEXT: pextrw $2, %xmm1, %ecx -; SSE2-NEXT: je LBB22_10 -; SSE2-NEXT: ## %bb.9: ## %cond.store7 +; SSE2-NEXT: je LBB22_7 +; SSE2-NEXT: ## %bb.6: ## %cond.store7 ; SSE2-NEXT: movb %cl, 4(%rdi) -; SSE2-NEXT: LBB22_10: ## %else8 +; SSE2-NEXT: LBB22_7: ## %else8 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je LBB22_12 -; SSE2-NEXT: ## %bb.11: ## %cond.store9 +; SSE2-NEXT: je LBB22_9 +; SSE2-NEXT: ## %bb.8: ## %cond.store9 ; SSE2-NEXT: movb %ch, 5(%rdi) -; SSE2-NEXT: LBB22_12: ## %else10 +; SSE2-NEXT: LBB22_9: ## %else10 ; SSE2-NEXT: testb $64, %al ; SSE2-NEXT: pextrw $3, %xmm1, %ecx -; SSE2-NEXT: je LBB22_14 -; SSE2-NEXT: ## %bb.13: ## %cond.store11 +; SSE2-NEXT: je LBB22_11 +; SSE2-NEXT: ## %bb.10: ## %cond.store11 ; SSE2-NEXT: movb %cl, 6(%rdi) -; SSE2-NEXT: LBB22_14: ## %else12 +; SSE2-NEXT: LBB22_11: ## %else12 ; SSE2-NEXT: testb %al, %al -; SSE2-NEXT: jns LBB22_16 -; SSE2-NEXT: ## %bb.15: ## %cond.store13 +; SSE2-NEXT: jns LBB22_13 +; SSE2-NEXT: ## %bb.12: ## %cond.store13 ; SSE2-NEXT: movb %ch, 7(%rdi) -; SSE2-NEXT: LBB22_16: ## %else14 +; SSE2-NEXT: LBB22_13: ## %else14 ; SSE2-NEXT: testl $256, %eax ## imm = 0x100 ; SSE2-NEXT: pextrw $4, %xmm1, %ecx -; SSE2-NEXT: je LBB22_18 -; SSE2-NEXT: ## %bb.17: ## %cond.store15 +; SSE2-NEXT: je LBB22_15 +; SSE2-NEXT: ## %bb.14: ## %cond.store15 ; SSE2-NEXT: movb %cl, 8(%rdi) -; SSE2-NEXT: LBB22_18: ## %else16 +; SSE2-NEXT: LBB22_15: ## %else16 ; SSE2-NEXT: testl $512, %eax ## imm = 0x200 -; SSE2-NEXT: je LBB22_20 -; SSE2-NEXT: ## %bb.19: ## %cond.store17 +; SSE2-NEXT: je LBB22_17 +; SSE2-NEXT: ## %bb.16: ## %cond.store17 ; SSE2-NEXT: movb %ch, 9(%rdi) -; SSE2-NEXT: LBB22_20: ## %else18 +; SSE2-NEXT: LBB22_17: ## %else18 ; SSE2-NEXT: testl $1024, %eax ## imm = 0x400 ; SSE2-NEXT: pextrw $5, %xmm1, %ecx -; SSE2-NEXT: je LBB22_22 -; SSE2-NEXT: ## %bb.21: ## %cond.store19 +; SSE2-NEXT: je LBB22_19 +; SSE2-NEXT: ## %bb.18: ## %cond.store19 ; SSE2-NEXT: movb %cl, 10(%rdi) -; SSE2-NEXT: LBB22_22: ## %else20 +; SSE2-NEXT: LBB22_19: ## %else20 ; SSE2-NEXT: testl $2048, %eax ## imm = 0x800 -; SSE2-NEXT: je LBB22_24 -; SSE2-NEXT: ## %bb.23: ## %cond.store21 +; SSE2-NEXT: je LBB22_21 +; SSE2-NEXT: ## %bb.20: ## %cond.store21 ; SSE2-NEXT: movb %ch, 11(%rdi) -; SSE2-NEXT: LBB22_24: ## %else22 +; SSE2-NEXT: LBB22_21: ## %else22 ; SSE2-NEXT: testl $4096, %eax ## imm = 0x1000 ; SSE2-NEXT: pextrw $6, %xmm1, %ecx -; SSE2-NEXT: je LBB22_26 -; SSE2-NEXT: ## %bb.25: ## %cond.store23 +; SSE2-NEXT: je LBB22_23 +; SSE2-NEXT: ## %bb.22: ## %cond.store23 ; SSE2-NEXT: movb %cl, 12(%rdi) -; SSE2-NEXT: LBB22_26: ## %else24 +; SSE2-NEXT: LBB22_23: ## %else24 ; SSE2-NEXT: testl $8192, %eax ## imm = 0x2000 -; SSE2-NEXT: je LBB22_28 -; SSE2-NEXT: ## %bb.27: ## %cond.store25 +; SSE2-NEXT: je LBB22_25 +; SSE2-NEXT: ## %bb.24: ## %cond.store25 ; SSE2-NEXT: movb %ch, 13(%rdi) -; SSE2-NEXT: LBB22_28: ## %else26 +; SSE2-NEXT: LBB22_25: ## %else26 ; SSE2-NEXT: testl $16384, %eax ## imm = 0x4000 ; SSE2-NEXT: pextrw $7, %xmm1, %ecx -; SSE2-NEXT: jne LBB22_29 -; SSE2-NEXT: ## %bb.30: ## %else28 -; SSE2-NEXT: testl $32768, %eax ## imm = 0x8000 ; SSE2-NEXT: jne LBB22_31 -; SSE2-NEXT: LBB22_32: ## %else30 +; SSE2-NEXT: ## %bb.26: ## %else28 +; SSE2-NEXT: testl $32768, %eax ## imm = 0x8000 +; SSE2-NEXT: jne LBB22_32 +; SSE2-NEXT: LBB22_27: ## %else30 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB22_1: ## %cond.store +; SSE2-NEXT: LBB22_28: ## %cond.store ; SSE2-NEXT: movb %cl, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB22_4 -; SSE2-NEXT: LBB22_3: ## %cond.store1 +; SSE2-NEXT: je LBB22_2 +; SSE2-NEXT: LBB22_29: ## %cond.store1 ; SSE2-NEXT: movb %ch, 1(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB22_6 -; SSE2-NEXT: LBB22_5: ## %cond.store3 +; SSE2-NEXT: je LBB22_3 +; SSE2-NEXT: LBB22_30: ## %cond.store3 ; SSE2-NEXT: movl %ecx, %edx ; SSE2-NEXT: shrl $16, %edx ; SSE2-NEXT: movb %dl, 2(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne LBB22_7 -; SSE2-NEXT: jmp LBB22_8 -; SSE2-NEXT: LBB22_29: ## %cond.store27 +; SSE2-NEXT: jne LBB22_4 +; SSE2-NEXT: jmp LBB22_5 +; SSE2-NEXT: LBB22_31: ## %cond.store27 ; SSE2-NEXT: movb %cl, 14(%rdi) ; SSE2-NEXT: testl $32768, %eax ## imm = 0x8000 -; SSE2-NEXT: je LBB22_32 -; SSE2-NEXT: LBB22_31: ## %cond.store29 +; SSE2-NEXT: je LBB22_27 +; SSE2-NEXT: LBB22_32: ## %cond.store29 ; SSE2-NEXT: movb %ch, 15(%rdi) ; SSE2-NEXT: retq ; @@ -3856,115 +3856,115 @@ define void @store_v16i8_v16i8(<16 x i8> %trigger, ptr %addr, <16 x i8> %val) no ; SSE4-NEXT: pcmpeqb %xmm0, %xmm2 ; SSE4-NEXT: pmovmskb %xmm2, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne LBB22_1 -; SSE4-NEXT: ## %bb.2: ## %else +; SSE4-NEXT: jne LBB22_17 +; SSE4-NEXT: ## %bb.1: ## %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne LBB22_3 -; SSE4-NEXT: LBB22_4: ## %else2 +; SSE4-NEXT: jne LBB22_18 +; SSE4-NEXT: LBB22_2: ## %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne LBB22_5 -; SSE4-NEXT: LBB22_6: ## %else4 +; SSE4-NEXT: jne LBB22_19 +; SSE4-NEXT: LBB22_3: ## %else4 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne LBB22_7 -; SSE4-NEXT: LBB22_8: ## %else6 +; SSE4-NEXT: jne LBB22_20 +; SSE4-NEXT: LBB22_4: ## %else6 ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: jne LBB22_9 -; SSE4-NEXT: LBB22_10: ## %else8 +; SSE4-NEXT: jne LBB22_21 +; SSE4-NEXT: LBB22_5: ## %else8 ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: jne LBB22_11 -; SSE4-NEXT: LBB22_12: ## %else10 +; SSE4-NEXT: jne LBB22_22 +; SSE4-NEXT: LBB22_6: ## %else10 ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: jne LBB22_13 -; SSE4-NEXT: LBB22_14: ## %else12 +; SSE4-NEXT: jne LBB22_23 +; SSE4-NEXT: LBB22_7: ## %else12 ; SSE4-NEXT: testb %al, %al -; SSE4-NEXT: js LBB22_15 -; SSE4-NEXT: LBB22_16: ## %else14 +; SSE4-NEXT: js LBB22_24 +; SSE4-NEXT: LBB22_8: ## %else14 ; SSE4-NEXT: testl $256, %eax ## imm = 0x100 -; SSE4-NEXT: jne LBB22_17 -; SSE4-NEXT: LBB22_18: ## %else16 +; SSE4-NEXT: jne LBB22_25 +; SSE4-NEXT: LBB22_9: ## %else16 ; SSE4-NEXT: testl $512, %eax ## imm = 0x200 -; SSE4-NEXT: jne LBB22_19 -; SSE4-NEXT: LBB22_20: ## %else18 +; SSE4-NEXT: jne LBB22_26 +; SSE4-NEXT: LBB22_10: ## %else18 ; SSE4-NEXT: testl $1024, %eax ## imm = 0x400 -; SSE4-NEXT: jne LBB22_21 -; SSE4-NEXT: LBB22_22: ## %else20 +; SSE4-NEXT: jne LBB22_27 +; SSE4-NEXT: LBB22_11: ## %else20 ; SSE4-NEXT: testl $2048, %eax ## imm = 0x800 -; SSE4-NEXT: jne LBB22_23 -; SSE4-NEXT: LBB22_24: ## %else22 +; SSE4-NEXT: jne LBB22_28 +; SSE4-NEXT: LBB22_12: ## %else22 ; SSE4-NEXT: testl $4096, %eax ## imm = 0x1000 -; SSE4-NEXT: jne LBB22_25 -; SSE4-NEXT: LBB22_26: ## %else24 +; SSE4-NEXT: jne LBB22_29 +; SSE4-NEXT: LBB22_13: ## %else24 ; SSE4-NEXT: testl $8192, %eax ## imm = 0x2000 -; SSE4-NEXT: jne LBB22_27 -; SSE4-NEXT: LBB22_28: ## %else26 +; SSE4-NEXT: jne LBB22_30 +; SSE4-NEXT: LBB22_14: ## %else26 ; SSE4-NEXT: testl $16384, %eax ## imm = 0x4000 -; SSE4-NEXT: jne LBB22_29 -; SSE4-NEXT: LBB22_30: ## %else28 -; SSE4-NEXT: testl $32768, %eax ## imm = 0x8000 ; SSE4-NEXT: jne LBB22_31 -; SSE4-NEXT: LBB22_32: ## %else30 +; SSE4-NEXT: LBB22_15: ## %else28 +; SSE4-NEXT: testl $32768, %eax ## imm = 0x8000 +; SSE4-NEXT: jne LBB22_32 +; SSE4-NEXT: LBB22_16: ## %else30 ; SSE4-NEXT: retq -; SSE4-NEXT: LBB22_1: ## %cond.store +; SSE4-NEXT: LBB22_17: ## %cond.store ; SSE4-NEXT: pextrb $0, %xmm1, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je LBB22_4 -; SSE4-NEXT: LBB22_3: ## %cond.store1 +; SSE4-NEXT: je LBB22_2 +; SSE4-NEXT: LBB22_18: ## %cond.store1 ; SSE4-NEXT: pextrb $1, %xmm1, 1(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je LBB22_6 -; SSE4-NEXT: LBB22_5: ## %cond.store3 +; SSE4-NEXT: je LBB22_3 +; SSE4-NEXT: LBB22_19: ## %cond.store3 ; SSE4-NEXT: pextrb $2, %xmm1, 2(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je LBB22_8 -; SSE4-NEXT: LBB22_7: ## %cond.store5 +; SSE4-NEXT: je LBB22_4 +; SSE4-NEXT: LBB22_20: ## %cond.store5 ; SSE4-NEXT: pextrb $3, %xmm1, 3(%rdi) ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: je LBB22_10 -; SSE4-NEXT: LBB22_9: ## %cond.store7 +; SSE4-NEXT: je LBB22_5 +; SSE4-NEXT: LBB22_21: ## %cond.store7 ; SSE4-NEXT: pextrb $4, %xmm1, 4(%rdi) ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: je LBB22_12 -; SSE4-NEXT: LBB22_11: ## %cond.store9 +; SSE4-NEXT: je LBB22_6 +; SSE4-NEXT: LBB22_22: ## %cond.store9 ; SSE4-NEXT: pextrb $5, %xmm1, 5(%rdi) ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: je LBB22_14 -; SSE4-NEXT: LBB22_13: ## %cond.store11 +; SSE4-NEXT: je LBB22_7 +; SSE4-NEXT: LBB22_23: ## %cond.store11 ; SSE4-NEXT: pextrb $6, %xmm1, 6(%rdi) ; SSE4-NEXT: testb %al, %al -; SSE4-NEXT: jns LBB22_16 -; SSE4-NEXT: LBB22_15: ## %cond.store13 +; SSE4-NEXT: jns LBB22_8 +; SSE4-NEXT: LBB22_24: ## %cond.store13 ; SSE4-NEXT: pextrb $7, %xmm1, 7(%rdi) ; SSE4-NEXT: testl $256, %eax ## imm = 0x100 -; SSE4-NEXT: je LBB22_18 -; SSE4-NEXT: LBB22_17: ## %cond.store15 +; SSE4-NEXT: je LBB22_9 +; SSE4-NEXT: LBB22_25: ## %cond.store15 ; SSE4-NEXT: pextrb $8, %xmm1, 8(%rdi) ; SSE4-NEXT: testl $512, %eax ## imm = 0x200 -; SSE4-NEXT: je LBB22_20 -; SSE4-NEXT: LBB22_19: ## %cond.store17 +; SSE4-NEXT: je LBB22_10 +; SSE4-NEXT: LBB22_26: ## %cond.store17 ; SSE4-NEXT: pextrb $9, %xmm1, 9(%rdi) ; SSE4-NEXT: testl $1024, %eax ## imm = 0x400 -; SSE4-NEXT: je LBB22_22 -; SSE4-NEXT: LBB22_21: ## %cond.store19 +; SSE4-NEXT: je LBB22_11 +; SSE4-NEXT: LBB22_27: ## %cond.store19 ; SSE4-NEXT: pextrb $10, %xmm1, 10(%rdi) ; SSE4-NEXT: testl $2048, %eax ## imm = 0x800 -; SSE4-NEXT: je LBB22_24 -; SSE4-NEXT: LBB22_23: ## %cond.store21 +; SSE4-NEXT: je LBB22_12 +; SSE4-NEXT: LBB22_28: ## %cond.store21 ; SSE4-NEXT: pextrb $11, %xmm1, 11(%rdi) ; SSE4-NEXT: testl $4096, %eax ## imm = 0x1000 -; SSE4-NEXT: je LBB22_26 -; SSE4-NEXT: LBB22_25: ## %cond.store23 +; SSE4-NEXT: je LBB22_13 +; SSE4-NEXT: LBB22_29: ## %cond.store23 ; SSE4-NEXT: pextrb $12, %xmm1, 12(%rdi) ; SSE4-NEXT: testl $8192, %eax ## imm = 0x2000 -; SSE4-NEXT: je LBB22_28 -; SSE4-NEXT: LBB22_27: ## %cond.store25 +; SSE4-NEXT: je LBB22_14 +; SSE4-NEXT: LBB22_30: ## %cond.store25 ; SSE4-NEXT: pextrb $13, %xmm1, 13(%rdi) ; SSE4-NEXT: testl $16384, %eax ## imm = 0x4000 -; SSE4-NEXT: je LBB22_30 -; SSE4-NEXT: LBB22_29: ## %cond.store27 +; SSE4-NEXT: je LBB22_15 +; SSE4-NEXT: LBB22_31: ## %cond.store27 ; SSE4-NEXT: pextrb $14, %xmm1, 14(%rdi) ; SSE4-NEXT: testl $32768, %eax ## imm = 0x8000 -; SSE4-NEXT: je LBB22_32 -; SSE4-NEXT: LBB22_31: ## %cond.store29 +; SSE4-NEXT: je LBB22_16 +; SSE4-NEXT: LBB22_32: ## %cond.store29 ; SSE4-NEXT: pextrb $15, %xmm1, 15(%rdi) ; SSE4-NEXT: retq ; @@ -3974,115 +3974,115 @@ define void @store_v16i8_v16i8(<16 x i8> %trigger, ptr %addr, <16 x i8> %val) no ; AVX1OR2-NEXT: vpcmpeqb %xmm2, %xmm0, %xmm0 ; AVX1OR2-NEXT: vpmovmskb %xmm0, %eax ; AVX1OR2-NEXT: testb $1, %al -; AVX1OR2-NEXT: jne LBB22_1 -; AVX1OR2-NEXT: ## %bb.2: ## %else +; AVX1OR2-NEXT: jne LBB22_17 +; AVX1OR2-NEXT: ## %bb.1: ## %else ; AVX1OR2-NEXT: testb $2, %al -; AVX1OR2-NEXT: jne LBB22_3 -; AVX1OR2-NEXT: LBB22_4: ## %else2 +; AVX1OR2-NEXT: jne LBB22_18 +; AVX1OR2-NEXT: LBB22_2: ## %else2 ; AVX1OR2-NEXT: testb $4, %al -; AVX1OR2-NEXT: jne LBB22_5 -; AVX1OR2-NEXT: LBB22_6: ## %else4 +; AVX1OR2-NEXT: jne LBB22_19 +; AVX1OR2-NEXT: LBB22_3: ## %else4 ; AVX1OR2-NEXT: testb $8, %al -; AVX1OR2-NEXT: jne LBB22_7 -; AVX1OR2-NEXT: LBB22_8: ## %else6 +; AVX1OR2-NEXT: jne LBB22_20 +; AVX1OR2-NEXT: LBB22_4: ## %else6 ; AVX1OR2-NEXT: testb $16, %al -; AVX1OR2-NEXT: jne LBB22_9 -; AVX1OR2-NEXT: LBB22_10: ## %else8 +; AVX1OR2-NEXT: jne LBB22_21 +; AVX1OR2-NEXT: LBB22_5: ## %else8 ; AVX1OR2-NEXT: testb $32, %al -; AVX1OR2-NEXT: jne LBB22_11 -; AVX1OR2-NEXT: LBB22_12: ## %else10 +; AVX1OR2-NEXT: jne LBB22_22 +; AVX1OR2-NEXT: LBB22_6: ## %else10 ; AVX1OR2-NEXT: testb $64, %al -; AVX1OR2-NEXT: jne LBB22_13 -; AVX1OR2-NEXT: LBB22_14: ## %else12 +; AVX1OR2-NEXT: jne LBB22_23 +; AVX1OR2-NEXT: LBB22_7: ## %else12 ; AVX1OR2-NEXT: testb %al, %al -; AVX1OR2-NEXT: js LBB22_15 -; AVX1OR2-NEXT: LBB22_16: ## %else14 +; AVX1OR2-NEXT: js LBB22_24 +; AVX1OR2-NEXT: LBB22_8: ## %else14 ; AVX1OR2-NEXT: testl $256, %eax ## imm = 0x100 -; AVX1OR2-NEXT: jne LBB22_17 -; AVX1OR2-NEXT: LBB22_18: ## %else16 +; AVX1OR2-NEXT: jne LBB22_25 +; AVX1OR2-NEXT: LBB22_9: ## %else16 ; AVX1OR2-NEXT: testl $512, %eax ## imm = 0x200 -; AVX1OR2-NEXT: jne LBB22_19 -; AVX1OR2-NEXT: LBB22_20: ## %else18 +; AVX1OR2-NEXT: jne LBB22_26 +; AVX1OR2-NEXT: LBB22_10: ## %else18 ; AVX1OR2-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX1OR2-NEXT: jne LBB22_21 -; AVX1OR2-NEXT: LBB22_22: ## %else20 +; AVX1OR2-NEXT: jne LBB22_27 +; AVX1OR2-NEXT: LBB22_11: ## %else20 ; AVX1OR2-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX1OR2-NEXT: jne LBB22_23 -; AVX1OR2-NEXT: LBB22_24: ## %else22 +; AVX1OR2-NEXT: jne LBB22_28 +; AVX1OR2-NEXT: LBB22_12: ## %else22 ; AVX1OR2-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX1OR2-NEXT: jne LBB22_25 -; AVX1OR2-NEXT: LBB22_26: ## %else24 +; AVX1OR2-NEXT: jne LBB22_29 +; AVX1OR2-NEXT: LBB22_13: ## %else24 ; AVX1OR2-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX1OR2-NEXT: jne LBB22_27 -; AVX1OR2-NEXT: LBB22_28: ## %else26 +; AVX1OR2-NEXT: jne LBB22_30 +; AVX1OR2-NEXT: LBB22_14: ## %else26 ; AVX1OR2-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX1OR2-NEXT: jne LBB22_29 -; AVX1OR2-NEXT: LBB22_30: ## %else28 -; AVX1OR2-NEXT: testl $32768, %eax ## imm = 0x8000 ; AVX1OR2-NEXT: jne LBB22_31 -; AVX1OR2-NEXT: LBB22_32: ## %else30 +; AVX1OR2-NEXT: LBB22_15: ## %else28 +; AVX1OR2-NEXT: testl $32768, %eax ## imm = 0x8000 +; AVX1OR2-NEXT: jne LBB22_32 +; AVX1OR2-NEXT: LBB22_16: ## %else30 ; AVX1OR2-NEXT: retq -; AVX1OR2-NEXT: LBB22_1: ## %cond.store +; AVX1OR2-NEXT: LBB22_17: ## %cond.store ; AVX1OR2-NEXT: vpextrb $0, %xmm1, (%rdi) ; AVX1OR2-NEXT: testb $2, %al -; AVX1OR2-NEXT: je LBB22_4 -; AVX1OR2-NEXT: LBB22_3: ## %cond.store1 +; AVX1OR2-NEXT: je LBB22_2 +; AVX1OR2-NEXT: LBB22_18: ## %cond.store1 ; AVX1OR2-NEXT: vpextrb $1, %xmm1, 1(%rdi) ; AVX1OR2-NEXT: testb $4, %al -; AVX1OR2-NEXT: je LBB22_6 -; AVX1OR2-NEXT: LBB22_5: ## %cond.store3 +; AVX1OR2-NEXT: je LBB22_3 +; AVX1OR2-NEXT: LBB22_19: ## %cond.store3 ; AVX1OR2-NEXT: vpextrb $2, %xmm1, 2(%rdi) ; AVX1OR2-NEXT: testb $8, %al -; AVX1OR2-NEXT: je LBB22_8 -; AVX1OR2-NEXT: LBB22_7: ## %cond.store5 +; AVX1OR2-NEXT: je LBB22_4 +; AVX1OR2-NEXT: LBB22_20: ## %cond.store5 ; AVX1OR2-NEXT: vpextrb $3, %xmm1, 3(%rdi) ; AVX1OR2-NEXT: testb $16, %al -; AVX1OR2-NEXT: je LBB22_10 -; AVX1OR2-NEXT: LBB22_9: ## %cond.store7 +; AVX1OR2-NEXT: je LBB22_5 +; AVX1OR2-NEXT: LBB22_21: ## %cond.store7 ; AVX1OR2-NEXT: vpextrb $4, %xmm1, 4(%rdi) ; AVX1OR2-NEXT: testb $32, %al -; AVX1OR2-NEXT: je LBB22_12 -; AVX1OR2-NEXT: LBB22_11: ## %cond.store9 +; AVX1OR2-NEXT: je LBB22_6 +; AVX1OR2-NEXT: LBB22_22: ## %cond.store9 ; AVX1OR2-NEXT: vpextrb $5, %xmm1, 5(%rdi) ; AVX1OR2-NEXT: testb $64, %al -; AVX1OR2-NEXT: je LBB22_14 -; AVX1OR2-NEXT: LBB22_13: ## %cond.store11 +; AVX1OR2-NEXT: je LBB22_7 +; AVX1OR2-NEXT: LBB22_23: ## %cond.store11 ; AVX1OR2-NEXT: vpextrb $6, %xmm1, 6(%rdi) ; AVX1OR2-NEXT: testb %al, %al -; AVX1OR2-NEXT: jns LBB22_16 -; AVX1OR2-NEXT: LBB22_15: ## %cond.store13 +; AVX1OR2-NEXT: jns LBB22_8 +; AVX1OR2-NEXT: LBB22_24: ## %cond.store13 ; AVX1OR2-NEXT: vpextrb $7, %xmm1, 7(%rdi) ; AVX1OR2-NEXT: testl $256, %eax ## imm = 0x100 -; AVX1OR2-NEXT: je LBB22_18 -; AVX1OR2-NEXT: LBB22_17: ## %cond.store15 +; AVX1OR2-NEXT: je LBB22_9 +; AVX1OR2-NEXT: LBB22_25: ## %cond.store15 ; AVX1OR2-NEXT: vpextrb $8, %xmm1, 8(%rdi) ; AVX1OR2-NEXT: testl $512, %eax ## imm = 0x200 -; AVX1OR2-NEXT: je LBB22_20 -; AVX1OR2-NEXT: LBB22_19: ## %cond.store17 +; AVX1OR2-NEXT: je LBB22_10 +; AVX1OR2-NEXT: LBB22_26: ## %cond.store17 ; AVX1OR2-NEXT: vpextrb $9, %xmm1, 9(%rdi) ; AVX1OR2-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX1OR2-NEXT: je LBB22_22 -; AVX1OR2-NEXT: LBB22_21: ## %cond.store19 +; AVX1OR2-NEXT: je LBB22_11 +; AVX1OR2-NEXT: LBB22_27: ## %cond.store19 ; AVX1OR2-NEXT: vpextrb $10, %xmm1, 10(%rdi) ; AVX1OR2-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX1OR2-NEXT: je LBB22_24 -; AVX1OR2-NEXT: LBB22_23: ## %cond.store21 +; AVX1OR2-NEXT: je LBB22_12 +; AVX1OR2-NEXT: LBB22_28: ## %cond.store21 ; AVX1OR2-NEXT: vpextrb $11, %xmm1, 11(%rdi) ; AVX1OR2-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX1OR2-NEXT: je LBB22_26 -; AVX1OR2-NEXT: LBB22_25: ## %cond.store23 +; AVX1OR2-NEXT: je LBB22_13 +; AVX1OR2-NEXT: LBB22_29: ## %cond.store23 ; AVX1OR2-NEXT: vpextrb $12, %xmm1, 12(%rdi) ; AVX1OR2-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX1OR2-NEXT: je LBB22_28 -; AVX1OR2-NEXT: LBB22_27: ## %cond.store25 +; AVX1OR2-NEXT: je LBB22_14 +; AVX1OR2-NEXT: LBB22_30: ## %cond.store25 ; AVX1OR2-NEXT: vpextrb $13, %xmm1, 13(%rdi) ; AVX1OR2-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX1OR2-NEXT: je LBB22_30 -; AVX1OR2-NEXT: LBB22_29: ## %cond.store27 +; AVX1OR2-NEXT: je LBB22_15 +; AVX1OR2-NEXT: LBB22_31: ## %cond.store27 ; AVX1OR2-NEXT: vpextrb $14, %xmm1, 14(%rdi) ; AVX1OR2-NEXT: testl $32768, %eax ## imm = 0x8000 -; AVX1OR2-NEXT: je LBB22_32 -; AVX1OR2-NEXT: LBB22_31: ## %cond.store29 +; AVX1OR2-NEXT: je LBB22_16 +; AVX1OR2-NEXT: LBB22_32: ## %cond.store29 ; AVX1OR2-NEXT: vpextrb $15, %xmm1, 15(%rdi) ; AVX1OR2-NEXT: retq ; @@ -4092,115 +4092,115 @@ define void @store_v16i8_v16i8(<16 x i8> %trigger, ptr %addr, <16 x i8> %val) no ; AVX512F-NEXT: vpcmpeqb %xmm2, %xmm0, %xmm0 ; AVX512F-NEXT: vpmovmskb %xmm0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne LBB22_1 -; AVX512F-NEXT: ## %bb.2: ## %else +; AVX512F-NEXT: jne LBB22_17 +; AVX512F-NEXT: ## %bb.1: ## %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne LBB22_3 -; AVX512F-NEXT: LBB22_4: ## %else2 +; AVX512F-NEXT: jne LBB22_18 +; AVX512F-NEXT: LBB22_2: ## %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne LBB22_5 -; AVX512F-NEXT: LBB22_6: ## %else4 +; AVX512F-NEXT: jne LBB22_19 +; AVX512F-NEXT: LBB22_3: ## %else4 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne LBB22_7 -; AVX512F-NEXT: LBB22_8: ## %else6 +; AVX512F-NEXT: jne LBB22_20 +; AVX512F-NEXT: LBB22_4: ## %else6 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne LBB22_9 -; AVX512F-NEXT: LBB22_10: ## %else8 +; AVX512F-NEXT: jne LBB22_21 +; AVX512F-NEXT: LBB22_5: ## %else8 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne LBB22_11 -; AVX512F-NEXT: LBB22_12: ## %else10 +; AVX512F-NEXT: jne LBB22_22 +; AVX512F-NEXT: LBB22_6: ## %else10 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne LBB22_13 -; AVX512F-NEXT: LBB22_14: ## %else12 +; AVX512F-NEXT: jne LBB22_23 +; AVX512F-NEXT: LBB22_7: ## %else12 ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: js LBB22_15 -; AVX512F-NEXT: LBB22_16: ## %else14 +; AVX512F-NEXT: js LBB22_24 +; AVX512F-NEXT: LBB22_8: ## %else14 ; AVX512F-NEXT: testl $256, %eax ## imm = 0x100 -; AVX512F-NEXT: jne LBB22_17 -; AVX512F-NEXT: LBB22_18: ## %else16 +; AVX512F-NEXT: jne LBB22_25 +; AVX512F-NEXT: LBB22_9: ## %else16 ; AVX512F-NEXT: testl $512, %eax ## imm = 0x200 -; AVX512F-NEXT: jne LBB22_19 -; AVX512F-NEXT: LBB22_20: ## %else18 +; AVX512F-NEXT: jne LBB22_26 +; AVX512F-NEXT: LBB22_10: ## %else18 ; AVX512F-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX512F-NEXT: jne LBB22_21 -; AVX512F-NEXT: LBB22_22: ## %else20 +; AVX512F-NEXT: jne LBB22_27 +; AVX512F-NEXT: LBB22_11: ## %else20 ; AVX512F-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX512F-NEXT: jne LBB22_23 -; AVX512F-NEXT: LBB22_24: ## %else22 +; AVX512F-NEXT: jne LBB22_28 +; AVX512F-NEXT: LBB22_12: ## %else22 ; AVX512F-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX512F-NEXT: jne LBB22_25 -; AVX512F-NEXT: LBB22_26: ## %else24 +; AVX512F-NEXT: jne LBB22_29 +; AVX512F-NEXT: LBB22_13: ## %else24 ; AVX512F-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX512F-NEXT: jne LBB22_27 -; AVX512F-NEXT: LBB22_28: ## %else26 +; AVX512F-NEXT: jne LBB22_30 +; AVX512F-NEXT: LBB22_14: ## %else26 ; AVX512F-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX512F-NEXT: jne LBB22_29 -; AVX512F-NEXT: LBB22_30: ## %else28 -; AVX512F-NEXT: testl $32768, %eax ## imm = 0x8000 ; AVX512F-NEXT: jne LBB22_31 -; AVX512F-NEXT: LBB22_32: ## %else30 +; AVX512F-NEXT: LBB22_15: ## %else28 +; AVX512F-NEXT: testl $32768, %eax ## imm = 0x8000 +; AVX512F-NEXT: jne LBB22_32 +; AVX512F-NEXT: LBB22_16: ## %else30 ; AVX512F-NEXT: retq -; AVX512F-NEXT: LBB22_1: ## %cond.store +; AVX512F-NEXT: LBB22_17: ## %cond.store ; AVX512F-NEXT: vpextrb $0, %xmm1, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je LBB22_4 -; AVX512F-NEXT: LBB22_3: ## %cond.store1 +; AVX512F-NEXT: je LBB22_2 +; AVX512F-NEXT: LBB22_18: ## %cond.store1 ; AVX512F-NEXT: vpextrb $1, %xmm1, 1(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je LBB22_6 -; AVX512F-NEXT: LBB22_5: ## %cond.store3 +; AVX512F-NEXT: je LBB22_3 +; AVX512F-NEXT: LBB22_19: ## %cond.store3 ; AVX512F-NEXT: vpextrb $2, %xmm1, 2(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je LBB22_8 -; AVX512F-NEXT: LBB22_7: ## %cond.store5 +; AVX512F-NEXT: je LBB22_4 +; AVX512F-NEXT: LBB22_20: ## %cond.store5 ; AVX512F-NEXT: vpextrb $3, %xmm1, 3(%rdi) ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je LBB22_10 -; AVX512F-NEXT: LBB22_9: ## %cond.store7 +; AVX512F-NEXT: je LBB22_5 +; AVX512F-NEXT: LBB22_21: ## %cond.store7 ; AVX512F-NEXT: vpextrb $4, %xmm1, 4(%rdi) ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je LBB22_12 -; AVX512F-NEXT: LBB22_11: ## %cond.store9 +; AVX512F-NEXT: je LBB22_6 +; AVX512F-NEXT: LBB22_22: ## %cond.store9 ; AVX512F-NEXT: vpextrb $5, %xmm1, 5(%rdi) ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je LBB22_14 -; AVX512F-NEXT: LBB22_13: ## %cond.store11 +; AVX512F-NEXT: je LBB22_7 +; AVX512F-NEXT: LBB22_23: ## %cond.store11 ; AVX512F-NEXT: vpextrb $6, %xmm1, 6(%rdi) ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: jns LBB22_16 -; AVX512F-NEXT: LBB22_15: ## %cond.store13 +; AVX512F-NEXT: jns LBB22_8 +; AVX512F-NEXT: LBB22_24: ## %cond.store13 ; AVX512F-NEXT: vpextrb $7, %xmm1, 7(%rdi) ; AVX512F-NEXT: testl $256, %eax ## imm = 0x100 -; AVX512F-NEXT: je LBB22_18 -; AVX512F-NEXT: LBB22_17: ## %cond.store15 +; AVX512F-NEXT: je LBB22_9 +; AVX512F-NEXT: LBB22_25: ## %cond.store15 ; AVX512F-NEXT: vpextrb $8, %xmm1, 8(%rdi) ; AVX512F-NEXT: testl $512, %eax ## imm = 0x200 -; AVX512F-NEXT: je LBB22_20 -; AVX512F-NEXT: LBB22_19: ## %cond.store17 +; AVX512F-NEXT: je LBB22_10 +; AVX512F-NEXT: LBB22_26: ## %cond.store17 ; AVX512F-NEXT: vpextrb $9, %xmm1, 9(%rdi) ; AVX512F-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX512F-NEXT: je LBB22_22 -; AVX512F-NEXT: LBB22_21: ## %cond.store19 +; AVX512F-NEXT: je LBB22_11 +; AVX512F-NEXT: LBB22_27: ## %cond.store19 ; AVX512F-NEXT: vpextrb $10, %xmm1, 10(%rdi) ; AVX512F-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX512F-NEXT: je LBB22_24 -; AVX512F-NEXT: LBB22_23: ## %cond.store21 +; AVX512F-NEXT: je LBB22_12 +; AVX512F-NEXT: LBB22_28: ## %cond.store21 ; AVX512F-NEXT: vpextrb $11, %xmm1, 11(%rdi) ; AVX512F-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX512F-NEXT: je LBB22_26 -; AVX512F-NEXT: LBB22_25: ## %cond.store23 +; AVX512F-NEXT: je LBB22_13 +; AVX512F-NEXT: LBB22_29: ## %cond.store23 ; AVX512F-NEXT: vpextrb $12, %xmm1, 12(%rdi) ; AVX512F-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX512F-NEXT: je LBB22_28 -; AVX512F-NEXT: LBB22_27: ## %cond.store25 +; AVX512F-NEXT: je LBB22_14 +; AVX512F-NEXT: LBB22_30: ## %cond.store25 ; AVX512F-NEXT: vpextrb $13, %xmm1, 13(%rdi) ; AVX512F-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX512F-NEXT: je LBB22_30 -; AVX512F-NEXT: LBB22_29: ## %cond.store27 +; AVX512F-NEXT: je LBB22_15 +; AVX512F-NEXT: LBB22_31: ## %cond.store27 ; AVX512F-NEXT: vpextrb $14, %xmm1, 14(%rdi) ; AVX512F-NEXT: testl $32768, %eax ## imm = 0x8000 -; AVX512F-NEXT: je LBB22_32 -; AVX512F-NEXT: LBB22_31: ## %cond.store29 +; AVX512F-NEXT: je LBB22_16 +; AVX512F-NEXT: LBB22_32: ## %cond.store29 ; AVX512F-NEXT: vpextrb $15, %xmm1, 15(%rdi) ; AVX512F-NEXT: retq ; @@ -4210,115 +4210,115 @@ define void @store_v16i8_v16i8(<16 x i8> %trigger, ptr %addr, <16 x i8> %val) no ; AVX512VLDQ-NEXT: vpcmpeqb %xmm2, %xmm0, %xmm0 ; AVX512VLDQ-NEXT: vpmovmskb %xmm0, %eax ; AVX512VLDQ-NEXT: testb $1, %al -; AVX512VLDQ-NEXT: jne LBB22_1 -; AVX512VLDQ-NEXT: ## %bb.2: ## %else +; AVX512VLDQ-NEXT: jne LBB22_17 +; AVX512VLDQ-NEXT: ## %bb.1: ## %else ; AVX512VLDQ-NEXT: testb $2, %al -; AVX512VLDQ-NEXT: jne LBB22_3 -; AVX512VLDQ-NEXT: LBB22_4: ## %else2 +; AVX512VLDQ-NEXT: jne LBB22_18 +; AVX512VLDQ-NEXT: LBB22_2: ## %else2 ; AVX512VLDQ-NEXT: testb $4, %al -; AVX512VLDQ-NEXT: jne LBB22_5 -; AVX512VLDQ-NEXT: LBB22_6: ## %else4 +; AVX512VLDQ-NEXT: jne LBB22_19 +; AVX512VLDQ-NEXT: LBB22_3: ## %else4 ; AVX512VLDQ-NEXT: testb $8, %al -; AVX512VLDQ-NEXT: jne LBB22_7 -; AVX512VLDQ-NEXT: LBB22_8: ## %else6 +; AVX512VLDQ-NEXT: jne LBB22_20 +; AVX512VLDQ-NEXT: LBB22_4: ## %else6 ; AVX512VLDQ-NEXT: testb $16, %al -; AVX512VLDQ-NEXT: jne LBB22_9 -; AVX512VLDQ-NEXT: LBB22_10: ## %else8 +; AVX512VLDQ-NEXT: jne LBB22_21 +; AVX512VLDQ-NEXT: LBB22_5: ## %else8 ; AVX512VLDQ-NEXT: testb $32, %al -; AVX512VLDQ-NEXT: jne LBB22_11 -; AVX512VLDQ-NEXT: LBB22_12: ## %else10 +; AVX512VLDQ-NEXT: jne LBB22_22 +; AVX512VLDQ-NEXT: LBB22_6: ## %else10 ; AVX512VLDQ-NEXT: testb $64, %al -; AVX512VLDQ-NEXT: jne LBB22_13 -; AVX512VLDQ-NEXT: LBB22_14: ## %else12 +; AVX512VLDQ-NEXT: jne LBB22_23 +; AVX512VLDQ-NEXT: LBB22_7: ## %else12 ; AVX512VLDQ-NEXT: testb %al, %al -; AVX512VLDQ-NEXT: js LBB22_15 -; AVX512VLDQ-NEXT: LBB22_16: ## %else14 +; AVX512VLDQ-NEXT: js LBB22_24 +; AVX512VLDQ-NEXT: LBB22_8: ## %else14 ; AVX512VLDQ-NEXT: testl $256, %eax ## imm = 0x100 -; AVX512VLDQ-NEXT: jne LBB22_17 -; AVX512VLDQ-NEXT: LBB22_18: ## %else16 +; AVX512VLDQ-NEXT: jne LBB22_25 +; AVX512VLDQ-NEXT: LBB22_9: ## %else16 ; AVX512VLDQ-NEXT: testl $512, %eax ## imm = 0x200 -; AVX512VLDQ-NEXT: jne LBB22_19 -; AVX512VLDQ-NEXT: LBB22_20: ## %else18 +; AVX512VLDQ-NEXT: jne LBB22_26 +; AVX512VLDQ-NEXT: LBB22_10: ## %else18 ; AVX512VLDQ-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX512VLDQ-NEXT: jne LBB22_21 -; AVX512VLDQ-NEXT: LBB22_22: ## %else20 +; AVX512VLDQ-NEXT: jne LBB22_27 +; AVX512VLDQ-NEXT: LBB22_11: ## %else20 ; AVX512VLDQ-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX512VLDQ-NEXT: jne LBB22_23 -; AVX512VLDQ-NEXT: LBB22_24: ## %else22 +; AVX512VLDQ-NEXT: jne LBB22_28 +; AVX512VLDQ-NEXT: LBB22_12: ## %else22 ; AVX512VLDQ-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX512VLDQ-NEXT: jne LBB22_25 -; AVX512VLDQ-NEXT: LBB22_26: ## %else24 +; AVX512VLDQ-NEXT: jne LBB22_29 +; AVX512VLDQ-NEXT: LBB22_13: ## %else24 ; AVX512VLDQ-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX512VLDQ-NEXT: jne LBB22_27 -; AVX512VLDQ-NEXT: LBB22_28: ## %else26 +; AVX512VLDQ-NEXT: jne LBB22_30 +; AVX512VLDQ-NEXT: LBB22_14: ## %else26 ; AVX512VLDQ-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX512VLDQ-NEXT: jne LBB22_29 -; AVX512VLDQ-NEXT: LBB22_30: ## %else28 -; AVX512VLDQ-NEXT: testl $32768, %eax ## imm = 0x8000 ; AVX512VLDQ-NEXT: jne LBB22_31 -; AVX512VLDQ-NEXT: LBB22_32: ## %else30 +; AVX512VLDQ-NEXT: LBB22_15: ## %else28 +; AVX512VLDQ-NEXT: testl $32768, %eax ## imm = 0x8000 +; AVX512VLDQ-NEXT: jne LBB22_32 +; AVX512VLDQ-NEXT: LBB22_16: ## %else30 ; AVX512VLDQ-NEXT: retq -; AVX512VLDQ-NEXT: LBB22_1: ## %cond.store +; AVX512VLDQ-NEXT: LBB22_17: ## %cond.store ; AVX512VLDQ-NEXT: vpextrb $0, %xmm1, (%rdi) ; AVX512VLDQ-NEXT: testb $2, %al -; AVX512VLDQ-NEXT: je LBB22_4 -; AVX512VLDQ-NEXT: LBB22_3: ## %cond.store1 +; AVX512VLDQ-NEXT: je LBB22_2 +; AVX512VLDQ-NEXT: LBB22_18: ## %cond.store1 ; AVX512VLDQ-NEXT: vpextrb $1, %xmm1, 1(%rdi) ; AVX512VLDQ-NEXT: testb $4, %al -; AVX512VLDQ-NEXT: je LBB22_6 -; AVX512VLDQ-NEXT: LBB22_5: ## %cond.store3 +; AVX512VLDQ-NEXT: je LBB22_3 +; AVX512VLDQ-NEXT: LBB22_19: ## %cond.store3 ; AVX512VLDQ-NEXT: vpextrb $2, %xmm1, 2(%rdi) ; AVX512VLDQ-NEXT: testb $8, %al -; AVX512VLDQ-NEXT: je LBB22_8 -; AVX512VLDQ-NEXT: LBB22_7: ## %cond.store5 +; AVX512VLDQ-NEXT: je LBB22_4 +; AVX512VLDQ-NEXT: LBB22_20: ## %cond.store5 ; AVX512VLDQ-NEXT: vpextrb $3, %xmm1, 3(%rdi) ; AVX512VLDQ-NEXT: testb $16, %al -; AVX512VLDQ-NEXT: je LBB22_10 -; AVX512VLDQ-NEXT: LBB22_9: ## %cond.store7 +; AVX512VLDQ-NEXT: je LBB22_5 +; AVX512VLDQ-NEXT: LBB22_21: ## %cond.store7 ; AVX512VLDQ-NEXT: vpextrb $4, %xmm1, 4(%rdi) ; AVX512VLDQ-NEXT: testb $32, %al -; AVX512VLDQ-NEXT: je LBB22_12 -; AVX512VLDQ-NEXT: LBB22_11: ## %cond.store9 +; AVX512VLDQ-NEXT: je LBB22_6 +; AVX512VLDQ-NEXT: LBB22_22: ## %cond.store9 ; AVX512VLDQ-NEXT: vpextrb $5, %xmm1, 5(%rdi) ; AVX512VLDQ-NEXT: testb $64, %al -; AVX512VLDQ-NEXT: je LBB22_14 -; AVX512VLDQ-NEXT: LBB22_13: ## %cond.store11 +; AVX512VLDQ-NEXT: je LBB22_7 +; AVX512VLDQ-NEXT: LBB22_23: ## %cond.store11 ; AVX512VLDQ-NEXT: vpextrb $6, %xmm1, 6(%rdi) ; AVX512VLDQ-NEXT: testb %al, %al -; AVX512VLDQ-NEXT: jns LBB22_16 -; AVX512VLDQ-NEXT: LBB22_15: ## %cond.store13 +; AVX512VLDQ-NEXT: jns LBB22_8 +; AVX512VLDQ-NEXT: LBB22_24: ## %cond.store13 ; AVX512VLDQ-NEXT: vpextrb $7, %xmm1, 7(%rdi) ; AVX512VLDQ-NEXT: testl $256, %eax ## imm = 0x100 -; AVX512VLDQ-NEXT: je LBB22_18 -; AVX512VLDQ-NEXT: LBB22_17: ## %cond.store15 +; AVX512VLDQ-NEXT: je LBB22_9 +; AVX512VLDQ-NEXT: LBB22_25: ## %cond.store15 ; AVX512VLDQ-NEXT: vpextrb $8, %xmm1, 8(%rdi) ; AVX512VLDQ-NEXT: testl $512, %eax ## imm = 0x200 -; AVX512VLDQ-NEXT: je LBB22_20 -; AVX512VLDQ-NEXT: LBB22_19: ## %cond.store17 +; AVX512VLDQ-NEXT: je LBB22_10 +; AVX512VLDQ-NEXT: LBB22_26: ## %cond.store17 ; AVX512VLDQ-NEXT: vpextrb $9, %xmm1, 9(%rdi) ; AVX512VLDQ-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX512VLDQ-NEXT: je LBB22_22 -; AVX512VLDQ-NEXT: LBB22_21: ## %cond.store19 +; AVX512VLDQ-NEXT: je LBB22_11 +; AVX512VLDQ-NEXT: LBB22_27: ## %cond.store19 ; AVX512VLDQ-NEXT: vpextrb $10, %xmm1, 10(%rdi) ; AVX512VLDQ-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX512VLDQ-NEXT: je LBB22_24 -; AVX512VLDQ-NEXT: LBB22_23: ## %cond.store21 +; AVX512VLDQ-NEXT: je LBB22_12 +; AVX512VLDQ-NEXT: LBB22_28: ## %cond.store21 ; AVX512VLDQ-NEXT: vpextrb $11, %xmm1, 11(%rdi) ; AVX512VLDQ-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX512VLDQ-NEXT: je LBB22_26 -; AVX512VLDQ-NEXT: LBB22_25: ## %cond.store23 +; AVX512VLDQ-NEXT: je LBB22_13 +; AVX512VLDQ-NEXT: LBB22_29: ## %cond.store23 ; AVX512VLDQ-NEXT: vpextrb $12, %xmm1, 12(%rdi) ; AVX512VLDQ-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX512VLDQ-NEXT: je LBB22_28 -; AVX512VLDQ-NEXT: LBB22_27: ## %cond.store25 +; AVX512VLDQ-NEXT: je LBB22_14 +; AVX512VLDQ-NEXT: LBB22_30: ## %cond.store25 ; AVX512VLDQ-NEXT: vpextrb $13, %xmm1, 13(%rdi) ; AVX512VLDQ-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX512VLDQ-NEXT: je LBB22_30 -; AVX512VLDQ-NEXT: LBB22_29: ## %cond.store27 +; AVX512VLDQ-NEXT: je LBB22_15 +; AVX512VLDQ-NEXT: LBB22_31: ## %cond.store27 ; AVX512VLDQ-NEXT: vpextrb $14, %xmm1, 14(%rdi) ; AVX512VLDQ-NEXT: testl $32768, %eax ## imm = 0x8000 -; AVX512VLDQ-NEXT: je LBB22_32 -; AVX512VLDQ-NEXT: LBB22_31: ## %cond.store29 +; AVX512VLDQ-NEXT: je LBB22_16 +; AVX512VLDQ-NEXT: LBB22_32: ## %cond.store29 ; AVX512VLDQ-NEXT: vpextrb $15, %xmm1, 15(%rdi) ; AVX512VLDQ-NEXT: retq ; @@ -4351,200 +4351,200 @@ define void @store_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %val) no ; SSE2-NEXT: orl %ecx, %eax ; SSE2-NEXT: testb $1, %al ; SSE2-NEXT: movd %xmm2, %ecx -; SSE2-NEXT: jne LBB23_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB23_57 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB23_3 -; SSE2-NEXT: LBB23_4: ## %else2 +; SSE2-NEXT: jne LBB23_58 +; SSE2-NEXT: LBB23_2: ## %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB23_5 -; SSE2-NEXT: LBB23_6: ## %else4 +; SSE2-NEXT: jne LBB23_59 +; SSE2-NEXT: LBB23_3: ## %else4 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB23_8 -; SSE2-NEXT: LBB23_7: ## %cond.store5 +; SSE2-NEXT: je LBB23_5 +; SSE2-NEXT: LBB23_4: ## %cond.store5 ; SSE2-NEXT: shrl $24, %ecx ; SSE2-NEXT: movb %cl, 3(%rdi) -; SSE2-NEXT: LBB23_8: ## %else6 +; SSE2-NEXT: LBB23_5: ## %else6 ; SSE2-NEXT: testb $16, %al ; SSE2-NEXT: pextrw $2, %xmm2, %ecx -; SSE2-NEXT: je LBB23_10 -; SSE2-NEXT: ## %bb.9: ## %cond.store7 +; SSE2-NEXT: je LBB23_7 +; SSE2-NEXT: ## %bb.6: ## %cond.store7 ; SSE2-NEXT: movb %cl, 4(%rdi) -; SSE2-NEXT: LBB23_10: ## %else8 +; SSE2-NEXT: LBB23_7: ## %else8 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je LBB23_12 -; SSE2-NEXT: ## %bb.11: ## %cond.store9 +; SSE2-NEXT: je LBB23_9 +; SSE2-NEXT: ## %bb.8: ## %cond.store9 ; SSE2-NEXT: movb %ch, 5(%rdi) -; SSE2-NEXT: LBB23_12: ## %else10 +; SSE2-NEXT: LBB23_9: ## %else10 ; SSE2-NEXT: testb $64, %al ; SSE2-NEXT: pextrw $3, %xmm2, %ecx -; SSE2-NEXT: je LBB23_14 -; SSE2-NEXT: ## %bb.13: ## %cond.store11 +; SSE2-NEXT: je LBB23_11 +; SSE2-NEXT: ## %bb.10: ## %cond.store11 ; SSE2-NEXT: movb %cl, 6(%rdi) -; SSE2-NEXT: LBB23_14: ## %else12 +; SSE2-NEXT: LBB23_11: ## %else12 ; SSE2-NEXT: testb %al, %al -; SSE2-NEXT: jns LBB23_16 -; SSE2-NEXT: ## %bb.15: ## %cond.store13 +; SSE2-NEXT: jns LBB23_13 +; SSE2-NEXT: ## %bb.12: ## %cond.store13 ; SSE2-NEXT: movb %ch, 7(%rdi) -; SSE2-NEXT: LBB23_16: ## %else14 +; SSE2-NEXT: LBB23_13: ## %else14 ; SSE2-NEXT: testl $256, %eax ## imm = 0x100 ; SSE2-NEXT: pextrw $4, %xmm2, %ecx -; SSE2-NEXT: je LBB23_18 -; SSE2-NEXT: ## %bb.17: ## %cond.store15 +; SSE2-NEXT: je LBB23_15 +; SSE2-NEXT: ## %bb.14: ## %cond.store15 ; SSE2-NEXT: movb %cl, 8(%rdi) -; SSE2-NEXT: LBB23_18: ## %else16 +; SSE2-NEXT: LBB23_15: ## %else16 ; SSE2-NEXT: testl $512, %eax ## imm = 0x200 -; SSE2-NEXT: je LBB23_20 -; SSE2-NEXT: ## %bb.19: ## %cond.store17 +; SSE2-NEXT: je LBB23_17 +; SSE2-NEXT: ## %bb.16: ## %cond.store17 ; SSE2-NEXT: movb %ch, 9(%rdi) -; SSE2-NEXT: LBB23_20: ## %else18 +; SSE2-NEXT: LBB23_17: ## %else18 ; SSE2-NEXT: testl $1024, %eax ## imm = 0x400 ; SSE2-NEXT: pextrw $5, %xmm2, %ecx -; SSE2-NEXT: je LBB23_22 -; SSE2-NEXT: ## %bb.21: ## %cond.store19 +; SSE2-NEXT: je LBB23_19 +; SSE2-NEXT: ## %bb.18: ## %cond.store19 ; SSE2-NEXT: movb %cl, 10(%rdi) -; SSE2-NEXT: LBB23_22: ## %else20 +; SSE2-NEXT: LBB23_19: ## %else20 ; SSE2-NEXT: testl $2048, %eax ## imm = 0x800 -; SSE2-NEXT: je LBB23_24 -; SSE2-NEXT: ## %bb.23: ## %cond.store21 +; SSE2-NEXT: je LBB23_21 +; SSE2-NEXT: ## %bb.20: ## %cond.store21 ; SSE2-NEXT: movb %ch, 11(%rdi) -; SSE2-NEXT: LBB23_24: ## %else22 +; SSE2-NEXT: LBB23_21: ## %else22 ; SSE2-NEXT: testl $4096, %eax ## imm = 0x1000 ; SSE2-NEXT: pextrw $6, %xmm2, %ecx -; SSE2-NEXT: je LBB23_26 -; SSE2-NEXT: ## %bb.25: ## %cond.store23 +; SSE2-NEXT: je LBB23_23 +; SSE2-NEXT: ## %bb.22: ## %cond.store23 ; SSE2-NEXT: movb %cl, 12(%rdi) -; SSE2-NEXT: LBB23_26: ## %else24 +; SSE2-NEXT: LBB23_23: ## %else24 ; SSE2-NEXT: testl $8192, %eax ## imm = 0x2000 -; SSE2-NEXT: je LBB23_28 -; SSE2-NEXT: ## %bb.27: ## %cond.store25 +; SSE2-NEXT: je LBB23_25 +; SSE2-NEXT: ## %bb.24: ## %cond.store25 ; SSE2-NEXT: movb %ch, 13(%rdi) -; SSE2-NEXT: LBB23_28: ## %else26 +; SSE2-NEXT: LBB23_25: ## %else26 ; SSE2-NEXT: testl $16384, %eax ## imm = 0x4000 ; SSE2-NEXT: pextrw $7, %xmm2, %ecx -; SSE2-NEXT: je LBB23_30 -; SSE2-NEXT: ## %bb.29: ## %cond.store27 +; SSE2-NEXT: je LBB23_27 +; SSE2-NEXT: ## %bb.26: ## %cond.store27 ; SSE2-NEXT: movb %cl, 14(%rdi) -; SSE2-NEXT: LBB23_30: ## %else28 +; SSE2-NEXT: LBB23_27: ## %else28 ; SSE2-NEXT: testw %ax, %ax -; SSE2-NEXT: jns LBB23_32 -; SSE2-NEXT: ## %bb.31: ## %cond.store29 +; SSE2-NEXT: jns LBB23_29 +; SSE2-NEXT: ## %bb.28: ## %cond.store29 ; SSE2-NEXT: movb %ch, 15(%rdi) -; SSE2-NEXT: LBB23_32: ## %else30 +; SSE2-NEXT: LBB23_29: ## %else30 ; SSE2-NEXT: testl $65536, %eax ## imm = 0x10000 ; SSE2-NEXT: movd %xmm3, %ecx -; SSE2-NEXT: jne LBB23_33 -; SSE2-NEXT: ## %bb.34: ## %else32 +; SSE2-NEXT: jne LBB23_60 +; SSE2-NEXT: ## %bb.30: ## %else32 ; SSE2-NEXT: testl $131072, %eax ## imm = 0x20000 -; SSE2-NEXT: jne LBB23_35 -; SSE2-NEXT: LBB23_36: ## %else34 +; SSE2-NEXT: jne LBB23_61 +; SSE2-NEXT: LBB23_31: ## %else34 ; SSE2-NEXT: testl $262144, %eax ## imm = 0x40000 -; SSE2-NEXT: jne LBB23_37 -; SSE2-NEXT: LBB23_38: ## %else36 +; SSE2-NEXT: jne LBB23_62 +; SSE2-NEXT: LBB23_32: ## %else36 ; SSE2-NEXT: testl $524288, %eax ## imm = 0x80000 -; SSE2-NEXT: je LBB23_40 -; SSE2-NEXT: LBB23_39: ## %cond.store37 +; SSE2-NEXT: je LBB23_34 +; SSE2-NEXT: LBB23_33: ## %cond.store37 ; SSE2-NEXT: shrl $24, %ecx ; SSE2-NEXT: movb %cl, 19(%rdi) -; SSE2-NEXT: LBB23_40: ## %else38 +; SSE2-NEXT: LBB23_34: ## %else38 ; SSE2-NEXT: testl $1048576, %eax ## imm = 0x100000 ; SSE2-NEXT: pextrw $2, %xmm3, %ecx -; SSE2-NEXT: je LBB23_42 -; SSE2-NEXT: ## %bb.41: ## %cond.store39 +; SSE2-NEXT: je LBB23_36 +; SSE2-NEXT: ## %bb.35: ## %cond.store39 ; SSE2-NEXT: movb %cl, 20(%rdi) -; SSE2-NEXT: LBB23_42: ## %else40 +; SSE2-NEXT: LBB23_36: ## %else40 ; SSE2-NEXT: testl $2097152, %eax ## imm = 0x200000 -; SSE2-NEXT: je LBB23_44 -; SSE2-NEXT: ## %bb.43: ## %cond.store41 +; SSE2-NEXT: je LBB23_38 +; SSE2-NEXT: ## %bb.37: ## %cond.store41 ; SSE2-NEXT: movb %ch, 21(%rdi) -; SSE2-NEXT: LBB23_44: ## %else42 +; SSE2-NEXT: LBB23_38: ## %else42 ; SSE2-NEXT: testl $4194304, %eax ## imm = 0x400000 ; SSE2-NEXT: pextrw $3, %xmm3, %ecx -; SSE2-NEXT: je LBB23_46 -; SSE2-NEXT: ## %bb.45: ## %cond.store43 +; SSE2-NEXT: je LBB23_40 +; SSE2-NEXT: ## %bb.39: ## %cond.store43 ; SSE2-NEXT: movb %cl, 22(%rdi) -; SSE2-NEXT: LBB23_46: ## %else44 +; SSE2-NEXT: LBB23_40: ## %else44 ; SSE2-NEXT: testl $8388608, %eax ## imm = 0x800000 -; SSE2-NEXT: je LBB23_48 -; SSE2-NEXT: ## %bb.47: ## %cond.store45 +; SSE2-NEXT: je LBB23_42 +; SSE2-NEXT: ## %bb.41: ## %cond.store45 ; SSE2-NEXT: movb %ch, 23(%rdi) -; SSE2-NEXT: LBB23_48: ## %else46 +; SSE2-NEXT: LBB23_42: ## %else46 ; SSE2-NEXT: testl $16777216, %eax ## imm = 0x1000000 ; SSE2-NEXT: pextrw $4, %xmm3, %ecx -; SSE2-NEXT: je LBB23_50 -; SSE2-NEXT: ## %bb.49: ## %cond.store47 +; SSE2-NEXT: je LBB23_44 +; SSE2-NEXT: ## %bb.43: ## %cond.store47 ; SSE2-NEXT: movb %cl, 24(%rdi) -; SSE2-NEXT: LBB23_50: ## %else48 +; SSE2-NEXT: LBB23_44: ## %else48 ; SSE2-NEXT: testl $33554432, %eax ## imm = 0x2000000 -; SSE2-NEXT: je LBB23_52 -; SSE2-NEXT: ## %bb.51: ## %cond.store49 +; SSE2-NEXT: je LBB23_46 +; SSE2-NEXT: ## %bb.45: ## %cond.store49 ; SSE2-NEXT: movb %ch, 25(%rdi) -; SSE2-NEXT: LBB23_52: ## %else50 +; SSE2-NEXT: LBB23_46: ## %else50 ; SSE2-NEXT: testl $67108864, %eax ## imm = 0x4000000 ; SSE2-NEXT: pextrw $5, %xmm3, %ecx -; SSE2-NEXT: je LBB23_54 -; SSE2-NEXT: ## %bb.53: ## %cond.store51 +; SSE2-NEXT: je LBB23_48 +; SSE2-NEXT: ## %bb.47: ## %cond.store51 ; SSE2-NEXT: movb %cl, 26(%rdi) -; SSE2-NEXT: LBB23_54: ## %else52 +; SSE2-NEXT: LBB23_48: ## %else52 ; SSE2-NEXT: testl $134217728, %eax ## imm = 0x8000000 -; SSE2-NEXT: je LBB23_56 -; SSE2-NEXT: ## %bb.55: ## %cond.store53 +; SSE2-NEXT: je LBB23_50 +; SSE2-NEXT: ## %bb.49: ## %cond.store53 ; SSE2-NEXT: movb %ch, 27(%rdi) -; SSE2-NEXT: LBB23_56: ## %else54 +; SSE2-NEXT: LBB23_50: ## %else54 ; SSE2-NEXT: testl $268435456, %eax ## imm = 0x10000000 ; SSE2-NEXT: pextrw $6, %xmm3, %ecx -; SSE2-NEXT: je LBB23_58 -; SSE2-NEXT: ## %bb.57: ## %cond.store55 +; SSE2-NEXT: je LBB23_52 +; SSE2-NEXT: ## %bb.51: ## %cond.store55 ; SSE2-NEXT: movb %cl, 28(%rdi) -; SSE2-NEXT: LBB23_58: ## %else56 +; SSE2-NEXT: LBB23_52: ## %else56 ; SSE2-NEXT: testl $536870912, %eax ## imm = 0x20000000 -; SSE2-NEXT: je LBB23_60 -; SSE2-NEXT: ## %bb.59: ## %cond.store57 +; SSE2-NEXT: je LBB23_54 +; SSE2-NEXT: ## %bb.53: ## %cond.store57 ; SSE2-NEXT: movb %ch, 29(%rdi) -; SSE2-NEXT: LBB23_60: ## %else58 +; SSE2-NEXT: LBB23_54: ## %else58 ; SSE2-NEXT: testl $1073741824, %eax ## imm = 0x40000000 ; SSE2-NEXT: pextrw $7, %xmm3, %ecx -; SSE2-NEXT: jne LBB23_61 -; SSE2-NEXT: ## %bb.62: ## %else60 -; SSE2-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 ; SSE2-NEXT: jne LBB23_63 -; SSE2-NEXT: LBB23_64: ## %else62 +; SSE2-NEXT: ## %bb.55: ## %else60 +; SSE2-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 +; SSE2-NEXT: jne LBB23_64 +; SSE2-NEXT: LBB23_56: ## %else62 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB23_1: ## %cond.store +; SSE2-NEXT: LBB23_57: ## %cond.store ; SSE2-NEXT: movb %cl, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB23_4 -; SSE2-NEXT: LBB23_3: ## %cond.store1 +; SSE2-NEXT: je LBB23_2 +; SSE2-NEXT: LBB23_58: ## %cond.store1 ; SSE2-NEXT: movb %ch, 1(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB23_6 -; SSE2-NEXT: LBB23_5: ## %cond.store3 +; SSE2-NEXT: je LBB23_3 +; SSE2-NEXT: LBB23_59: ## %cond.store3 ; SSE2-NEXT: movl %ecx, %edx ; SSE2-NEXT: shrl $16, %edx ; SSE2-NEXT: movb %dl, 2(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne LBB23_7 -; SSE2-NEXT: jmp LBB23_8 -; SSE2-NEXT: LBB23_33: ## %cond.store31 +; SSE2-NEXT: jne LBB23_4 +; SSE2-NEXT: jmp LBB23_5 +; SSE2-NEXT: LBB23_60: ## %cond.store31 ; SSE2-NEXT: movb %cl, 16(%rdi) ; SSE2-NEXT: testl $131072, %eax ## imm = 0x20000 -; SSE2-NEXT: je LBB23_36 -; SSE2-NEXT: LBB23_35: ## %cond.store33 +; SSE2-NEXT: je LBB23_31 +; SSE2-NEXT: LBB23_61: ## %cond.store33 ; SSE2-NEXT: movb %ch, 17(%rdi) ; SSE2-NEXT: testl $262144, %eax ## imm = 0x40000 -; SSE2-NEXT: je LBB23_38 -; SSE2-NEXT: LBB23_37: ## %cond.store35 +; SSE2-NEXT: je LBB23_32 +; SSE2-NEXT: LBB23_62: ## %cond.store35 ; SSE2-NEXT: movl %ecx, %edx ; SSE2-NEXT: shrl $16, %edx ; SSE2-NEXT: movb %dl, 18(%rdi) ; SSE2-NEXT: testl $524288, %eax ## imm = 0x80000 -; SSE2-NEXT: jne LBB23_39 -; SSE2-NEXT: jmp LBB23_40 -; SSE2-NEXT: LBB23_61: ## %cond.store59 +; SSE2-NEXT: jne LBB23_33 +; SSE2-NEXT: jmp LBB23_34 +; SSE2-NEXT: LBB23_63: ## %cond.store59 ; SSE2-NEXT: movb %cl, 30(%rdi) ; SSE2-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 -; SSE2-NEXT: je LBB23_64 -; SSE2-NEXT: LBB23_63: ## %cond.store61 +; SSE2-NEXT: je LBB23_56 +; SSE2-NEXT: LBB23_64: ## %cond.store61 ; SSE2-NEXT: movb %ch, 31(%rdi) ; SSE2-NEXT: retq ; @@ -4558,227 +4558,227 @@ define void @store_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %val) no ; SSE4-NEXT: shll $16, %eax ; SSE4-NEXT: orl %ecx, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne LBB23_1 -; SSE4-NEXT: ## %bb.2: ## %else +; SSE4-NEXT: jne LBB23_33 +; SSE4-NEXT: ## %bb.1: ## %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne LBB23_3 -; SSE4-NEXT: LBB23_4: ## %else2 +; SSE4-NEXT: jne LBB23_34 +; SSE4-NEXT: LBB23_2: ## %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne LBB23_5 -; SSE4-NEXT: LBB23_6: ## %else4 +; SSE4-NEXT: jne LBB23_35 +; SSE4-NEXT: LBB23_3: ## %else4 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne LBB23_7 -; SSE4-NEXT: LBB23_8: ## %else6 +; SSE4-NEXT: jne LBB23_36 +; SSE4-NEXT: LBB23_4: ## %else6 ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: jne LBB23_9 -; SSE4-NEXT: LBB23_10: ## %else8 +; SSE4-NEXT: jne LBB23_37 +; SSE4-NEXT: LBB23_5: ## %else8 ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: jne LBB23_11 -; SSE4-NEXT: LBB23_12: ## %else10 +; SSE4-NEXT: jne LBB23_38 +; SSE4-NEXT: LBB23_6: ## %else10 ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: jne LBB23_13 -; SSE4-NEXT: LBB23_14: ## %else12 +; SSE4-NEXT: jne LBB23_39 +; SSE4-NEXT: LBB23_7: ## %else12 ; SSE4-NEXT: testb %al, %al -; SSE4-NEXT: js LBB23_15 -; SSE4-NEXT: LBB23_16: ## %else14 +; SSE4-NEXT: js LBB23_40 +; SSE4-NEXT: LBB23_8: ## %else14 ; SSE4-NEXT: testl $256, %eax ## imm = 0x100 -; SSE4-NEXT: jne LBB23_17 -; SSE4-NEXT: LBB23_18: ## %else16 +; SSE4-NEXT: jne LBB23_41 +; SSE4-NEXT: LBB23_9: ## %else16 ; SSE4-NEXT: testl $512, %eax ## imm = 0x200 -; SSE4-NEXT: jne LBB23_19 -; SSE4-NEXT: LBB23_20: ## %else18 +; SSE4-NEXT: jne LBB23_42 +; SSE4-NEXT: LBB23_10: ## %else18 ; SSE4-NEXT: testl $1024, %eax ## imm = 0x400 -; SSE4-NEXT: jne LBB23_21 -; SSE4-NEXT: LBB23_22: ## %else20 +; SSE4-NEXT: jne LBB23_43 +; SSE4-NEXT: LBB23_11: ## %else20 ; SSE4-NEXT: testl $2048, %eax ## imm = 0x800 -; SSE4-NEXT: jne LBB23_23 -; SSE4-NEXT: LBB23_24: ## %else22 +; SSE4-NEXT: jne LBB23_44 +; SSE4-NEXT: LBB23_12: ## %else22 ; SSE4-NEXT: testl $4096, %eax ## imm = 0x1000 -; SSE4-NEXT: jne LBB23_25 -; SSE4-NEXT: LBB23_26: ## %else24 +; SSE4-NEXT: jne LBB23_45 +; SSE4-NEXT: LBB23_13: ## %else24 ; SSE4-NEXT: testl $8192, %eax ## imm = 0x2000 -; SSE4-NEXT: jne LBB23_27 -; SSE4-NEXT: LBB23_28: ## %else26 +; SSE4-NEXT: jne LBB23_46 +; SSE4-NEXT: LBB23_14: ## %else26 ; SSE4-NEXT: testl $16384, %eax ## imm = 0x4000 -; SSE4-NEXT: jne LBB23_29 -; SSE4-NEXT: LBB23_30: ## %else28 +; SSE4-NEXT: jne LBB23_47 +; SSE4-NEXT: LBB23_15: ## %else28 ; SSE4-NEXT: testw %ax, %ax -; SSE4-NEXT: js LBB23_31 -; SSE4-NEXT: LBB23_32: ## %else30 +; SSE4-NEXT: js LBB23_48 +; SSE4-NEXT: LBB23_16: ## %else30 ; SSE4-NEXT: testl $65536, %eax ## imm = 0x10000 -; SSE4-NEXT: jne LBB23_33 -; SSE4-NEXT: LBB23_34: ## %else32 +; SSE4-NEXT: jne LBB23_49 +; SSE4-NEXT: LBB23_17: ## %else32 ; SSE4-NEXT: testl $131072, %eax ## imm = 0x20000 -; SSE4-NEXT: jne LBB23_35 -; SSE4-NEXT: LBB23_36: ## %else34 +; SSE4-NEXT: jne LBB23_50 +; SSE4-NEXT: LBB23_18: ## %else34 ; SSE4-NEXT: testl $262144, %eax ## imm = 0x40000 -; SSE4-NEXT: jne LBB23_37 -; SSE4-NEXT: LBB23_38: ## %else36 +; SSE4-NEXT: jne LBB23_51 +; SSE4-NEXT: LBB23_19: ## %else36 ; SSE4-NEXT: testl $524288, %eax ## imm = 0x80000 -; SSE4-NEXT: jne LBB23_39 -; SSE4-NEXT: LBB23_40: ## %else38 +; SSE4-NEXT: jne LBB23_52 +; SSE4-NEXT: LBB23_20: ## %else38 ; SSE4-NEXT: testl $1048576, %eax ## imm = 0x100000 -; SSE4-NEXT: jne LBB23_41 -; SSE4-NEXT: LBB23_42: ## %else40 +; SSE4-NEXT: jne LBB23_53 +; SSE4-NEXT: LBB23_21: ## %else40 ; SSE4-NEXT: testl $2097152, %eax ## imm = 0x200000 -; SSE4-NEXT: jne LBB23_43 -; SSE4-NEXT: LBB23_44: ## %else42 +; SSE4-NEXT: jne LBB23_54 +; SSE4-NEXT: LBB23_22: ## %else42 ; SSE4-NEXT: testl $4194304, %eax ## imm = 0x400000 -; SSE4-NEXT: jne LBB23_45 -; SSE4-NEXT: LBB23_46: ## %else44 +; SSE4-NEXT: jne LBB23_55 +; SSE4-NEXT: LBB23_23: ## %else44 ; SSE4-NEXT: testl $8388608, %eax ## imm = 0x800000 -; SSE4-NEXT: jne LBB23_47 -; SSE4-NEXT: LBB23_48: ## %else46 +; SSE4-NEXT: jne LBB23_56 +; SSE4-NEXT: LBB23_24: ## %else46 ; SSE4-NEXT: testl $16777216, %eax ## imm = 0x1000000 -; SSE4-NEXT: jne LBB23_49 -; SSE4-NEXT: LBB23_50: ## %else48 +; SSE4-NEXT: jne LBB23_57 +; SSE4-NEXT: LBB23_25: ## %else48 ; SSE4-NEXT: testl $33554432, %eax ## imm = 0x2000000 -; SSE4-NEXT: jne LBB23_51 -; SSE4-NEXT: LBB23_52: ## %else50 +; SSE4-NEXT: jne LBB23_58 +; SSE4-NEXT: LBB23_26: ## %else50 ; SSE4-NEXT: testl $67108864, %eax ## imm = 0x4000000 -; SSE4-NEXT: jne LBB23_53 -; SSE4-NEXT: LBB23_54: ## %else52 +; SSE4-NEXT: jne LBB23_59 +; SSE4-NEXT: LBB23_27: ## %else52 ; SSE4-NEXT: testl $134217728, %eax ## imm = 0x8000000 -; SSE4-NEXT: jne LBB23_55 -; SSE4-NEXT: LBB23_56: ## %else54 +; SSE4-NEXT: jne LBB23_60 +; SSE4-NEXT: LBB23_28: ## %else54 ; SSE4-NEXT: testl $268435456, %eax ## imm = 0x10000000 -; SSE4-NEXT: jne LBB23_57 -; SSE4-NEXT: LBB23_58: ## %else56 +; SSE4-NEXT: jne LBB23_61 +; SSE4-NEXT: LBB23_29: ## %else56 ; SSE4-NEXT: testl $536870912, %eax ## imm = 0x20000000 -; SSE4-NEXT: jne LBB23_59 -; SSE4-NEXT: LBB23_60: ## %else58 +; SSE4-NEXT: jne LBB23_62 +; SSE4-NEXT: LBB23_30: ## %else58 ; SSE4-NEXT: testl $1073741824, %eax ## imm = 0x40000000 -; SSE4-NEXT: jne LBB23_61 -; SSE4-NEXT: LBB23_62: ## %else60 -; SSE4-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 ; SSE4-NEXT: jne LBB23_63 -; SSE4-NEXT: LBB23_64: ## %else62 +; SSE4-NEXT: LBB23_31: ## %else60 +; SSE4-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 +; SSE4-NEXT: jne LBB23_64 +; SSE4-NEXT: LBB23_32: ## %else62 ; SSE4-NEXT: retq -; SSE4-NEXT: LBB23_1: ## %cond.store +; SSE4-NEXT: LBB23_33: ## %cond.store ; SSE4-NEXT: pextrb $0, %xmm2, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je LBB23_4 -; SSE4-NEXT: LBB23_3: ## %cond.store1 +; SSE4-NEXT: je LBB23_2 +; SSE4-NEXT: LBB23_34: ## %cond.store1 ; SSE4-NEXT: pextrb $1, %xmm2, 1(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je LBB23_6 -; SSE4-NEXT: LBB23_5: ## %cond.store3 +; SSE4-NEXT: je LBB23_3 +; SSE4-NEXT: LBB23_35: ## %cond.store3 ; SSE4-NEXT: pextrb $2, %xmm2, 2(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je LBB23_8 -; SSE4-NEXT: LBB23_7: ## %cond.store5 +; SSE4-NEXT: je LBB23_4 +; SSE4-NEXT: LBB23_36: ## %cond.store5 ; SSE4-NEXT: pextrb $3, %xmm2, 3(%rdi) ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: je LBB23_10 -; SSE4-NEXT: LBB23_9: ## %cond.store7 +; SSE4-NEXT: je LBB23_5 +; SSE4-NEXT: LBB23_37: ## %cond.store7 ; SSE4-NEXT: pextrb $4, %xmm2, 4(%rdi) ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: je LBB23_12 -; SSE4-NEXT: LBB23_11: ## %cond.store9 +; SSE4-NEXT: je LBB23_6 +; SSE4-NEXT: LBB23_38: ## %cond.store9 ; SSE4-NEXT: pextrb $5, %xmm2, 5(%rdi) ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: je LBB23_14 -; SSE4-NEXT: LBB23_13: ## %cond.store11 +; SSE4-NEXT: je LBB23_7 +; SSE4-NEXT: LBB23_39: ## %cond.store11 ; SSE4-NEXT: pextrb $6, %xmm2, 6(%rdi) ; SSE4-NEXT: testb %al, %al -; SSE4-NEXT: jns LBB23_16 -; SSE4-NEXT: LBB23_15: ## %cond.store13 +; SSE4-NEXT: jns LBB23_8 +; SSE4-NEXT: LBB23_40: ## %cond.store13 ; SSE4-NEXT: pextrb $7, %xmm2, 7(%rdi) ; SSE4-NEXT: testl $256, %eax ## imm = 0x100 -; SSE4-NEXT: je LBB23_18 -; SSE4-NEXT: LBB23_17: ## %cond.store15 +; SSE4-NEXT: je LBB23_9 +; SSE4-NEXT: LBB23_41: ## %cond.store15 ; SSE4-NEXT: pextrb $8, %xmm2, 8(%rdi) ; SSE4-NEXT: testl $512, %eax ## imm = 0x200 -; SSE4-NEXT: je LBB23_20 -; SSE4-NEXT: LBB23_19: ## %cond.store17 +; SSE4-NEXT: je LBB23_10 +; SSE4-NEXT: LBB23_42: ## %cond.store17 ; SSE4-NEXT: pextrb $9, %xmm2, 9(%rdi) ; SSE4-NEXT: testl $1024, %eax ## imm = 0x400 -; SSE4-NEXT: je LBB23_22 -; SSE4-NEXT: LBB23_21: ## %cond.store19 +; SSE4-NEXT: je LBB23_11 +; SSE4-NEXT: LBB23_43: ## %cond.store19 ; SSE4-NEXT: pextrb $10, %xmm2, 10(%rdi) ; SSE4-NEXT: testl $2048, %eax ## imm = 0x800 -; SSE4-NEXT: je LBB23_24 -; SSE4-NEXT: LBB23_23: ## %cond.store21 +; SSE4-NEXT: je LBB23_12 +; SSE4-NEXT: LBB23_44: ## %cond.store21 ; SSE4-NEXT: pextrb $11, %xmm2, 11(%rdi) ; SSE4-NEXT: testl $4096, %eax ## imm = 0x1000 -; SSE4-NEXT: je LBB23_26 -; SSE4-NEXT: LBB23_25: ## %cond.store23 +; SSE4-NEXT: je LBB23_13 +; SSE4-NEXT: LBB23_45: ## %cond.store23 ; SSE4-NEXT: pextrb $12, %xmm2, 12(%rdi) ; SSE4-NEXT: testl $8192, %eax ## imm = 0x2000 -; SSE4-NEXT: je LBB23_28 -; SSE4-NEXT: LBB23_27: ## %cond.store25 +; SSE4-NEXT: je LBB23_14 +; SSE4-NEXT: LBB23_46: ## %cond.store25 ; SSE4-NEXT: pextrb $13, %xmm2, 13(%rdi) ; SSE4-NEXT: testl $16384, %eax ## imm = 0x4000 -; SSE4-NEXT: je LBB23_30 -; SSE4-NEXT: LBB23_29: ## %cond.store27 +; SSE4-NEXT: je LBB23_15 +; SSE4-NEXT: LBB23_47: ## %cond.store27 ; SSE4-NEXT: pextrb $14, %xmm2, 14(%rdi) ; SSE4-NEXT: testw %ax, %ax -; SSE4-NEXT: jns LBB23_32 -; SSE4-NEXT: LBB23_31: ## %cond.store29 +; SSE4-NEXT: jns LBB23_16 +; SSE4-NEXT: LBB23_48: ## %cond.store29 ; SSE4-NEXT: pextrb $15, %xmm2, 15(%rdi) ; SSE4-NEXT: testl $65536, %eax ## imm = 0x10000 -; SSE4-NEXT: je LBB23_34 -; SSE4-NEXT: LBB23_33: ## %cond.store31 +; SSE4-NEXT: je LBB23_17 +; SSE4-NEXT: LBB23_49: ## %cond.store31 ; SSE4-NEXT: pextrb $0, %xmm3, 16(%rdi) ; SSE4-NEXT: testl $131072, %eax ## imm = 0x20000 -; SSE4-NEXT: je LBB23_36 -; SSE4-NEXT: LBB23_35: ## %cond.store33 +; SSE4-NEXT: je LBB23_18 +; SSE4-NEXT: LBB23_50: ## %cond.store33 ; SSE4-NEXT: pextrb $1, %xmm3, 17(%rdi) ; SSE4-NEXT: testl $262144, %eax ## imm = 0x40000 -; SSE4-NEXT: je LBB23_38 -; SSE4-NEXT: LBB23_37: ## %cond.store35 +; SSE4-NEXT: je LBB23_19 +; SSE4-NEXT: LBB23_51: ## %cond.store35 ; SSE4-NEXT: pextrb $2, %xmm3, 18(%rdi) ; SSE4-NEXT: testl $524288, %eax ## imm = 0x80000 -; SSE4-NEXT: je LBB23_40 -; SSE4-NEXT: LBB23_39: ## %cond.store37 +; SSE4-NEXT: je LBB23_20 +; SSE4-NEXT: LBB23_52: ## %cond.store37 ; SSE4-NEXT: pextrb $3, %xmm3, 19(%rdi) ; SSE4-NEXT: testl $1048576, %eax ## imm = 0x100000 -; SSE4-NEXT: je LBB23_42 -; SSE4-NEXT: LBB23_41: ## %cond.store39 +; SSE4-NEXT: je LBB23_21 +; SSE4-NEXT: LBB23_53: ## %cond.store39 ; SSE4-NEXT: pextrb $4, %xmm3, 20(%rdi) ; SSE4-NEXT: testl $2097152, %eax ## imm = 0x200000 -; SSE4-NEXT: je LBB23_44 -; SSE4-NEXT: LBB23_43: ## %cond.store41 +; SSE4-NEXT: je LBB23_22 +; SSE4-NEXT: LBB23_54: ## %cond.store41 ; SSE4-NEXT: pextrb $5, %xmm3, 21(%rdi) ; SSE4-NEXT: testl $4194304, %eax ## imm = 0x400000 -; SSE4-NEXT: je LBB23_46 -; SSE4-NEXT: LBB23_45: ## %cond.store43 +; SSE4-NEXT: je LBB23_23 +; SSE4-NEXT: LBB23_55: ## %cond.store43 ; SSE4-NEXT: pextrb $6, %xmm3, 22(%rdi) ; SSE4-NEXT: testl $8388608, %eax ## imm = 0x800000 -; SSE4-NEXT: je LBB23_48 -; SSE4-NEXT: LBB23_47: ## %cond.store45 +; SSE4-NEXT: je LBB23_24 +; SSE4-NEXT: LBB23_56: ## %cond.store45 ; SSE4-NEXT: pextrb $7, %xmm3, 23(%rdi) ; SSE4-NEXT: testl $16777216, %eax ## imm = 0x1000000 -; SSE4-NEXT: je LBB23_50 -; SSE4-NEXT: LBB23_49: ## %cond.store47 +; SSE4-NEXT: je LBB23_25 +; SSE4-NEXT: LBB23_57: ## %cond.store47 ; SSE4-NEXT: pextrb $8, %xmm3, 24(%rdi) ; SSE4-NEXT: testl $33554432, %eax ## imm = 0x2000000 -; SSE4-NEXT: je LBB23_52 -; SSE4-NEXT: LBB23_51: ## %cond.store49 +; SSE4-NEXT: je LBB23_26 +; SSE4-NEXT: LBB23_58: ## %cond.store49 ; SSE4-NEXT: pextrb $9, %xmm3, 25(%rdi) ; SSE4-NEXT: testl $67108864, %eax ## imm = 0x4000000 -; SSE4-NEXT: je LBB23_54 -; SSE4-NEXT: LBB23_53: ## %cond.store51 +; SSE4-NEXT: je LBB23_27 +; SSE4-NEXT: LBB23_59: ## %cond.store51 ; SSE4-NEXT: pextrb $10, %xmm3, 26(%rdi) ; SSE4-NEXT: testl $134217728, %eax ## imm = 0x8000000 -; SSE4-NEXT: je LBB23_56 -; SSE4-NEXT: LBB23_55: ## %cond.store53 +; SSE4-NEXT: je LBB23_28 +; SSE4-NEXT: LBB23_60: ## %cond.store53 ; SSE4-NEXT: pextrb $11, %xmm3, 27(%rdi) ; SSE4-NEXT: testl $268435456, %eax ## imm = 0x10000000 -; SSE4-NEXT: je LBB23_58 -; SSE4-NEXT: LBB23_57: ## %cond.store55 +; SSE4-NEXT: je LBB23_29 +; SSE4-NEXT: LBB23_61: ## %cond.store55 ; SSE4-NEXT: pextrb $12, %xmm3, 28(%rdi) ; SSE4-NEXT: testl $536870912, %eax ## imm = 0x20000000 -; SSE4-NEXT: je LBB23_60 -; SSE4-NEXT: LBB23_59: ## %cond.store57 +; SSE4-NEXT: je LBB23_30 +; SSE4-NEXT: LBB23_62: ## %cond.store57 ; SSE4-NEXT: pextrb $13, %xmm3, 29(%rdi) ; SSE4-NEXT: testl $1073741824, %eax ## imm = 0x40000000 -; SSE4-NEXT: je LBB23_62 -; SSE4-NEXT: LBB23_61: ## %cond.store59 +; SSE4-NEXT: je LBB23_31 +; SSE4-NEXT: LBB23_63: ## %cond.store59 ; SSE4-NEXT: pextrb $14, %xmm3, 30(%rdi) ; SSE4-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 -; SSE4-NEXT: je LBB23_64 -; SSE4-NEXT: LBB23_63: ## %cond.store61 +; SSE4-NEXT: je LBB23_32 +; SSE4-NEXT: LBB23_64: ## %cond.store61 ; SSE4-NEXT: pextrb $15, %xmm3, 31(%rdi) ; SSE4-NEXT: retq ; @@ -4793,228 +4793,228 @@ define void @store_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %val) no ; AVX1-NEXT: shll $16, %eax ; AVX1-NEXT: orl %ecx, %eax ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne LBB23_1 -; AVX1-NEXT: ## %bb.2: ## %else +; AVX1-NEXT: jne LBB23_34 +; AVX1-NEXT: ## %bb.1: ## %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne LBB23_3 -; AVX1-NEXT: LBB23_4: ## %else2 +; AVX1-NEXT: jne LBB23_35 +; AVX1-NEXT: LBB23_2: ## %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne LBB23_5 -; AVX1-NEXT: LBB23_6: ## %else4 +; AVX1-NEXT: jne LBB23_36 +; AVX1-NEXT: LBB23_3: ## %else4 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne LBB23_7 -; AVX1-NEXT: LBB23_8: ## %else6 +; AVX1-NEXT: jne LBB23_37 +; AVX1-NEXT: LBB23_4: ## %else6 ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: jne LBB23_9 -; AVX1-NEXT: LBB23_10: ## %else8 +; AVX1-NEXT: jne LBB23_38 +; AVX1-NEXT: LBB23_5: ## %else8 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: jne LBB23_11 -; AVX1-NEXT: LBB23_12: ## %else10 +; AVX1-NEXT: jne LBB23_39 +; AVX1-NEXT: LBB23_6: ## %else10 ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: jne LBB23_13 -; AVX1-NEXT: LBB23_14: ## %else12 +; AVX1-NEXT: jne LBB23_40 +; AVX1-NEXT: LBB23_7: ## %else12 ; AVX1-NEXT: testb %al, %al -; AVX1-NEXT: js LBB23_15 -; AVX1-NEXT: LBB23_16: ## %else14 +; AVX1-NEXT: js LBB23_41 +; AVX1-NEXT: LBB23_8: ## %else14 ; AVX1-NEXT: testl $256, %eax ## imm = 0x100 -; AVX1-NEXT: jne LBB23_17 -; AVX1-NEXT: LBB23_18: ## %else16 +; AVX1-NEXT: jne LBB23_42 +; AVX1-NEXT: LBB23_9: ## %else16 ; AVX1-NEXT: testl $512, %eax ## imm = 0x200 -; AVX1-NEXT: jne LBB23_19 -; AVX1-NEXT: LBB23_20: ## %else18 +; AVX1-NEXT: jne LBB23_43 +; AVX1-NEXT: LBB23_10: ## %else18 ; AVX1-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX1-NEXT: jne LBB23_21 -; AVX1-NEXT: LBB23_22: ## %else20 +; AVX1-NEXT: jne LBB23_44 +; AVX1-NEXT: LBB23_11: ## %else20 ; AVX1-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX1-NEXT: jne LBB23_23 -; AVX1-NEXT: LBB23_24: ## %else22 +; AVX1-NEXT: jne LBB23_45 +; AVX1-NEXT: LBB23_12: ## %else22 ; AVX1-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX1-NEXT: jne LBB23_25 -; AVX1-NEXT: LBB23_26: ## %else24 +; AVX1-NEXT: jne LBB23_46 +; AVX1-NEXT: LBB23_13: ## %else24 ; AVX1-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX1-NEXT: jne LBB23_27 -; AVX1-NEXT: LBB23_28: ## %else26 +; AVX1-NEXT: jne LBB23_47 +; AVX1-NEXT: LBB23_14: ## %else26 ; AVX1-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX1-NEXT: jne LBB23_29 -; AVX1-NEXT: LBB23_30: ## %else28 +; AVX1-NEXT: jne LBB23_48 +; AVX1-NEXT: LBB23_15: ## %else28 ; AVX1-NEXT: testw %ax, %ax -; AVX1-NEXT: jns LBB23_32 -; AVX1-NEXT: LBB23_31: ## %cond.store29 +; AVX1-NEXT: jns LBB23_17 +; AVX1-NEXT: LBB23_16: ## %cond.store29 ; AVX1-NEXT: vpextrb $15, %xmm1, 15(%rdi) -; AVX1-NEXT: LBB23_32: ## %else30 +; AVX1-NEXT: LBB23_17: ## %else30 ; AVX1-NEXT: testl $65536, %eax ## imm = 0x10000 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm0 -; AVX1-NEXT: jne LBB23_33 -; AVX1-NEXT: ## %bb.34: ## %else32 +; AVX1-NEXT: jne LBB23_49 +; AVX1-NEXT: ## %bb.18: ## %else32 ; AVX1-NEXT: testl $131072, %eax ## imm = 0x20000 -; AVX1-NEXT: jne LBB23_35 -; AVX1-NEXT: LBB23_36: ## %else34 +; AVX1-NEXT: jne LBB23_50 +; AVX1-NEXT: LBB23_19: ## %else34 ; AVX1-NEXT: testl $262144, %eax ## imm = 0x40000 -; AVX1-NEXT: jne LBB23_37 -; AVX1-NEXT: LBB23_38: ## %else36 +; AVX1-NEXT: jne LBB23_51 +; AVX1-NEXT: LBB23_20: ## %else36 ; AVX1-NEXT: testl $524288, %eax ## imm = 0x80000 -; AVX1-NEXT: jne LBB23_39 -; AVX1-NEXT: LBB23_40: ## %else38 +; AVX1-NEXT: jne LBB23_52 +; AVX1-NEXT: LBB23_21: ## %else38 ; AVX1-NEXT: testl $1048576, %eax ## imm = 0x100000 -; AVX1-NEXT: jne LBB23_41 -; AVX1-NEXT: LBB23_42: ## %else40 +; AVX1-NEXT: jne LBB23_53 +; AVX1-NEXT: LBB23_22: ## %else40 ; AVX1-NEXT: testl $2097152, %eax ## imm = 0x200000 -; AVX1-NEXT: jne LBB23_43 -; AVX1-NEXT: LBB23_44: ## %else42 +; AVX1-NEXT: jne LBB23_54 +; AVX1-NEXT: LBB23_23: ## %else42 ; AVX1-NEXT: testl $4194304, %eax ## imm = 0x400000 -; AVX1-NEXT: jne LBB23_45 -; AVX1-NEXT: LBB23_46: ## %else44 +; AVX1-NEXT: jne LBB23_55 +; AVX1-NEXT: LBB23_24: ## %else44 ; AVX1-NEXT: testl $8388608, %eax ## imm = 0x800000 -; AVX1-NEXT: jne LBB23_47 -; AVX1-NEXT: LBB23_48: ## %else46 +; AVX1-NEXT: jne LBB23_56 +; AVX1-NEXT: LBB23_25: ## %else46 ; AVX1-NEXT: testl $16777216, %eax ## imm = 0x1000000 -; AVX1-NEXT: jne LBB23_49 -; AVX1-NEXT: LBB23_50: ## %else48 +; AVX1-NEXT: jne LBB23_57 +; AVX1-NEXT: LBB23_26: ## %else48 ; AVX1-NEXT: testl $33554432, %eax ## imm = 0x2000000 -; AVX1-NEXT: jne LBB23_51 -; AVX1-NEXT: LBB23_52: ## %else50 +; AVX1-NEXT: jne LBB23_58 +; AVX1-NEXT: LBB23_27: ## %else50 ; AVX1-NEXT: testl $67108864, %eax ## imm = 0x4000000 -; AVX1-NEXT: jne LBB23_53 -; AVX1-NEXT: LBB23_54: ## %else52 +; AVX1-NEXT: jne LBB23_59 +; AVX1-NEXT: LBB23_28: ## %else52 ; AVX1-NEXT: testl $134217728, %eax ## imm = 0x8000000 -; AVX1-NEXT: jne LBB23_55 -; AVX1-NEXT: LBB23_56: ## %else54 +; AVX1-NEXT: jne LBB23_60 +; AVX1-NEXT: LBB23_29: ## %else54 ; AVX1-NEXT: testl $268435456, %eax ## imm = 0x10000000 -; AVX1-NEXT: jne LBB23_57 -; AVX1-NEXT: LBB23_58: ## %else56 +; AVX1-NEXT: jne LBB23_61 +; AVX1-NEXT: LBB23_30: ## %else56 ; AVX1-NEXT: testl $536870912, %eax ## imm = 0x20000000 -; AVX1-NEXT: jne LBB23_59 -; AVX1-NEXT: LBB23_60: ## %else58 +; AVX1-NEXT: jne LBB23_62 +; AVX1-NEXT: LBB23_31: ## %else58 ; AVX1-NEXT: testl $1073741824, %eax ## imm = 0x40000000 -; AVX1-NEXT: jne LBB23_61 -; AVX1-NEXT: LBB23_62: ## %else60 -; AVX1-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 ; AVX1-NEXT: jne LBB23_63 -; AVX1-NEXT: LBB23_64: ## %else62 +; AVX1-NEXT: LBB23_32: ## %else60 +; AVX1-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 +; AVX1-NEXT: jne LBB23_64 +; AVX1-NEXT: LBB23_33: ## %else62 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: LBB23_1: ## %cond.store +; AVX1-NEXT: LBB23_34: ## %cond.store ; AVX1-NEXT: vpextrb $0, %xmm1, (%rdi) ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je LBB23_4 -; AVX1-NEXT: LBB23_3: ## %cond.store1 +; AVX1-NEXT: je LBB23_2 +; AVX1-NEXT: LBB23_35: ## %cond.store1 ; AVX1-NEXT: vpextrb $1, %xmm1, 1(%rdi) ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je LBB23_6 -; AVX1-NEXT: LBB23_5: ## %cond.store3 +; AVX1-NEXT: je LBB23_3 +; AVX1-NEXT: LBB23_36: ## %cond.store3 ; AVX1-NEXT: vpextrb $2, %xmm1, 2(%rdi) ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je LBB23_8 -; AVX1-NEXT: LBB23_7: ## %cond.store5 +; AVX1-NEXT: je LBB23_4 +; AVX1-NEXT: LBB23_37: ## %cond.store5 ; AVX1-NEXT: vpextrb $3, %xmm1, 3(%rdi) ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: je LBB23_10 -; AVX1-NEXT: LBB23_9: ## %cond.store7 +; AVX1-NEXT: je LBB23_5 +; AVX1-NEXT: LBB23_38: ## %cond.store7 ; AVX1-NEXT: vpextrb $4, %xmm1, 4(%rdi) ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je LBB23_12 -; AVX1-NEXT: LBB23_11: ## %cond.store9 +; AVX1-NEXT: je LBB23_6 +; AVX1-NEXT: LBB23_39: ## %cond.store9 ; AVX1-NEXT: vpextrb $5, %xmm1, 5(%rdi) ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: je LBB23_14 -; AVX1-NEXT: LBB23_13: ## %cond.store11 +; AVX1-NEXT: je LBB23_7 +; AVX1-NEXT: LBB23_40: ## %cond.store11 ; AVX1-NEXT: vpextrb $6, %xmm1, 6(%rdi) ; AVX1-NEXT: testb %al, %al -; AVX1-NEXT: jns LBB23_16 -; AVX1-NEXT: LBB23_15: ## %cond.store13 +; AVX1-NEXT: jns LBB23_8 +; AVX1-NEXT: LBB23_41: ## %cond.store13 ; AVX1-NEXT: vpextrb $7, %xmm1, 7(%rdi) ; AVX1-NEXT: testl $256, %eax ## imm = 0x100 -; AVX1-NEXT: je LBB23_18 -; AVX1-NEXT: LBB23_17: ## %cond.store15 +; AVX1-NEXT: je LBB23_9 +; AVX1-NEXT: LBB23_42: ## %cond.store15 ; AVX1-NEXT: vpextrb $8, %xmm1, 8(%rdi) ; AVX1-NEXT: testl $512, %eax ## imm = 0x200 -; AVX1-NEXT: je LBB23_20 -; AVX1-NEXT: LBB23_19: ## %cond.store17 +; AVX1-NEXT: je LBB23_10 +; AVX1-NEXT: LBB23_43: ## %cond.store17 ; AVX1-NEXT: vpextrb $9, %xmm1, 9(%rdi) ; AVX1-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX1-NEXT: je LBB23_22 -; AVX1-NEXT: LBB23_21: ## %cond.store19 +; AVX1-NEXT: je LBB23_11 +; AVX1-NEXT: LBB23_44: ## %cond.store19 ; AVX1-NEXT: vpextrb $10, %xmm1, 10(%rdi) ; AVX1-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX1-NEXT: je LBB23_24 -; AVX1-NEXT: LBB23_23: ## %cond.store21 +; AVX1-NEXT: je LBB23_12 +; AVX1-NEXT: LBB23_45: ## %cond.store21 ; AVX1-NEXT: vpextrb $11, %xmm1, 11(%rdi) ; AVX1-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX1-NEXT: je LBB23_26 -; AVX1-NEXT: LBB23_25: ## %cond.store23 +; AVX1-NEXT: je LBB23_13 +; AVX1-NEXT: LBB23_46: ## %cond.store23 ; AVX1-NEXT: vpextrb $12, %xmm1, 12(%rdi) ; AVX1-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX1-NEXT: je LBB23_28 -; AVX1-NEXT: LBB23_27: ## %cond.store25 +; AVX1-NEXT: je LBB23_14 +; AVX1-NEXT: LBB23_47: ## %cond.store25 ; AVX1-NEXT: vpextrb $13, %xmm1, 13(%rdi) ; AVX1-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX1-NEXT: je LBB23_30 -; AVX1-NEXT: LBB23_29: ## %cond.store27 +; AVX1-NEXT: je LBB23_15 +; AVX1-NEXT: LBB23_48: ## %cond.store27 ; AVX1-NEXT: vpextrb $14, %xmm1, 14(%rdi) ; AVX1-NEXT: testw %ax, %ax -; AVX1-NEXT: js LBB23_31 -; AVX1-NEXT: jmp LBB23_32 -; AVX1-NEXT: LBB23_33: ## %cond.store31 +; AVX1-NEXT: js LBB23_16 +; AVX1-NEXT: jmp LBB23_17 +; AVX1-NEXT: LBB23_49: ## %cond.store31 ; AVX1-NEXT: vpextrb $0, %xmm0, 16(%rdi) ; AVX1-NEXT: testl $131072, %eax ## imm = 0x20000 -; AVX1-NEXT: je LBB23_36 -; AVX1-NEXT: LBB23_35: ## %cond.store33 +; AVX1-NEXT: je LBB23_19 +; AVX1-NEXT: LBB23_50: ## %cond.store33 ; AVX1-NEXT: vpextrb $1, %xmm0, 17(%rdi) ; AVX1-NEXT: testl $262144, %eax ## imm = 0x40000 -; AVX1-NEXT: je LBB23_38 -; AVX1-NEXT: LBB23_37: ## %cond.store35 +; AVX1-NEXT: je LBB23_20 +; AVX1-NEXT: LBB23_51: ## %cond.store35 ; AVX1-NEXT: vpextrb $2, %xmm0, 18(%rdi) ; AVX1-NEXT: testl $524288, %eax ## imm = 0x80000 -; AVX1-NEXT: je LBB23_40 -; AVX1-NEXT: LBB23_39: ## %cond.store37 +; AVX1-NEXT: je LBB23_21 +; AVX1-NEXT: LBB23_52: ## %cond.store37 ; AVX1-NEXT: vpextrb $3, %xmm0, 19(%rdi) ; AVX1-NEXT: testl $1048576, %eax ## imm = 0x100000 -; AVX1-NEXT: je LBB23_42 -; AVX1-NEXT: LBB23_41: ## %cond.store39 +; AVX1-NEXT: je LBB23_22 +; AVX1-NEXT: LBB23_53: ## %cond.store39 ; AVX1-NEXT: vpextrb $4, %xmm0, 20(%rdi) ; AVX1-NEXT: testl $2097152, %eax ## imm = 0x200000 -; AVX1-NEXT: je LBB23_44 -; AVX1-NEXT: LBB23_43: ## %cond.store41 +; AVX1-NEXT: je LBB23_23 +; AVX1-NEXT: LBB23_54: ## %cond.store41 ; AVX1-NEXT: vpextrb $5, %xmm0, 21(%rdi) ; AVX1-NEXT: testl $4194304, %eax ## imm = 0x400000 -; AVX1-NEXT: je LBB23_46 -; AVX1-NEXT: LBB23_45: ## %cond.store43 +; AVX1-NEXT: je LBB23_24 +; AVX1-NEXT: LBB23_55: ## %cond.store43 ; AVX1-NEXT: vpextrb $6, %xmm0, 22(%rdi) ; AVX1-NEXT: testl $8388608, %eax ## imm = 0x800000 -; AVX1-NEXT: je LBB23_48 -; AVX1-NEXT: LBB23_47: ## %cond.store45 +; AVX1-NEXT: je LBB23_25 +; AVX1-NEXT: LBB23_56: ## %cond.store45 ; AVX1-NEXT: vpextrb $7, %xmm0, 23(%rdi) ; AVX1-NEXT: testl $16777216, %eax ## imm = 0x1000000 -; AVX1-NEXT: je LBB23_50 -; AVX1-NEXT: LBB23_49: ## %cond.store47 +; AVX1-NEXT: je LBB23_26 +; AVX1-NEXT: LBB23_57: ## %cond.store47 ; AVX1-NEXT: vpextrb $8, %xmm0, 24(%rdi) ; AVX1-NEXT: testl $33554432, %eax ## imm = 0x2000000 -; AVX1-NEXT: je LBB23_52 -; AVX1-NEXT: LBB23_51: ## %cond.store49 +; AVX1-NEXT: je LBB23_27 +; AVX1-NEXT: LBB23_58: ## %cond.store49 ; AVX1-NEXT: vpextrb $9, %xmm0, 25(%rdi) ; AVX1-NEXT: testl $67108864, %eax ## imm = 0x4000000 -; AVX1-NEXT: je LBB23_54 -; AVX1-NEXT: LBB23_53: ## %cond.store51 +; AVX1-NEXT: je LBB23_28 +; AVX1-NEXT: LBB23_59: ## %cond.store51 ; AVX1-NEXT: vpextrb $10, %xmm0, 26(%rdi) ; AVX1-NEXT: testl $134217728, %eax ## imm = 0x8000000 -; AVX1-NEXT: je LBB23_56 -; AVX1-NEXT: LBB23_55: ## %cond.store53 +; AVX1-NEXT: je LBB23_29 +; AVX1-NEXT: LBB23_60: ## %cond.store53 ; AVX1-NEXT: vpextrb $11, %xmm0, 27(%rdi) ; AVX1-NEXT: testl $268435456, %eax ## imm = 0x10000000 -; AVX1-NEXT: je LBB23_58 -; AVX1-NEXT: LBB23_57: ## %cond.store55 +; AVX1-NEXT: je LBB23_30 +; AVX1-NEXT: LBB23_61: ## %cond.store55 ; AVX1-NEXT: vpextrb $12, %xmm0, 28(%rdi) ; AVX1-NEXT: testl $536870912, %eax ## imm = 0x20000000 -; AVX1-NEXT: je LBB23_60 -; AVX1-NEXT: LBB23_59: ## %cond.store57 +; AVX1-NEXT: je LBB23_31 +; AVX1-NEXT: LBB23_62: ## %cond.store57 ; AVX1-NEXT: vpextrb $13, %xmm0, 29(%rdi) ; AVX1-NEXT: testl $1073741824, %eax ## imm = 0x40000000 -; AVX1-NEXT: je LBB23_62 -; AVX1-NEXT: LBB23_61: ## %cond.store59 +; AVX1-NEXT: je LBB23_32 +; AVX1-NEXT: LBB23_63: ## %cond.store59 ; AVX1-NEXT: vpextrb $14, %xmm0, 30(%rdi) ; AVX1-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 -; AVX1-NEXT: je LBB23_64 -; AVX1-NEXT: LBB23_63: ## %cond.store61 +; AVX1-NEXT: je LBB23_33 +; AVX1-NEXT: LBB23_64: ## %cond.store61 ; AVX1-NEXT: vpextrb $15, %xmm0, 31(%rdi) ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq @@ -5025,228 +5025,228 @@ define void @store_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %val) no ; AVX2-NEXT: vpcmpeqb %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpmovmskb %ymm0, %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne LBB23_1 -; AVX2-NEXT: ## %bb.2: ## %else +; AVX2-NEXT: jne LBB23_34 +; AVX2-NEXT: ## %bb.1: ## %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne LBB23_3 -; AVX2-NEXT: LBB23_4: ## %else2 +; AVX2-NEXT: jne LBB23_35 +; AVX2-NEXT: LBB23_2: ## %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne LBB23_5 -; AVX2-NEXT: LBB23_6: ## %else4 +; AVX2-NEXT: jne LBB23_36 +; AVX2-NEXT: LBB23_3: ## %else4 ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: jne LBB23_7 -; AVX2-NEXT: LBB23_8: ## %else6 +; AVX2-NEXT: jne LBB23_37 +; AVX2-NEXT: LBB23_4: ## %else6 ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: jne LBB23_9 -; AVX2-NEXT: LBB23_10: ## %else8 +; AVX2-NEXT: jne LBB23_38 +; AVX2-NEXT: LBB23_5: ## %else8 ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: jne LBB23_11 -; AVX2-NEXT: LBB23_12: ## %else10 +; AVX2-NEXT: jne LBB23_39 +; AVX2-NEXT: LBB23_6: ## %else10 ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: jne LBB23_13 -; AVX2-NEXT: LBB23_14: ## %else12 +; AVX2-NEXT: jne LBB23_40 +; AVX2-NEXT: LBB23_7: ## %else12 ; AVX2-NEXT: testb %al, %al -; AVX2-NEXT: js LBB23_15 -; AVX2-NEXT: LBB23_16: ## %else14 +; AVX2-NEXT: js LBB23_41 +; AVX2-NEXT: LBB23_8: ## %else14 ; AVX2-NEXT: testl $256, %eax ## imm = 0x100 -; AVX2-NEXT: jne LBB23_17 -; AVX2-NEXT: LBB23_18: ## %else16 +; AVX2-NEXT: jne LBB23_42 +; AVX2-NEXT: LBB23_9: ## %else16 ; AVX2-NEXT: testl $512, %eax ## imm = 0x200 -; AVX2-NEXT: jne LBB23_19 -; AVX2-NEXT: LBB23_20: ## %else18 +; AVX2-NEXT: jne LBB23_43 +; AVX2-NEXT: LBB23_10: ## %else18 ; AVX2-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX2-NEXT: jne LBB23_21 -; AVX2-NEXT: LBB23_22: ## %else20 +; AVX2-NEXT: jne LBB23_44 +; AVX2-NEXT: LBB23_11: ## %else20 ; AVX2-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX2-NEXT: jne LBB23_23 -; AVX2-NEXT: LBB23_24: ## %else22 +; AVX2-NEXT: jne LBB23_45 +; AVX2-NEXT: LBB23_12: ## %else22 ; AVX2-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX2-NEXT: jne LBB23_25 -; AVX2-NEXT: LBB23_26: ## %else24 +; AVX2-NEXT: jne LBB23_46 +; AVX2-NEXT: LBB23_13: ## %else24 ; AVX2-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX2-NEXT: jne LBB23_27 -; AVX2-NEXT: LBB23_28: ## %else26 +; AVX2-NEXT: jne LBB23_47 +; AVX2-NEXT: LBB23_14: ## %else26 ; AVX2-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX2-NEXT: jne LBB23_29 -; AVX2-NEXT: LBB23_30: ## %else28 +; AVX2-NEXT: jne LBB23_48 +; AVX2-NEXT: LBB23_15: ## %else28 ; AVX2-NEXT: testw %ax, %ax -; AVX2-NEXT: jns LBB23_32 -; AVX2-NEXT: LBB23_31: ## %cond.store29 +; AVX2-NEXT: jns LBB23_17 +; AVX2-NEXT: LBB23_16: ## %cond.store29 ; AVX2-NEXT: vpextrb $15, %xmm1, 15(%rdi) -; AVX2-NEXT: LBB23_32: ## %else30 +; AVX2-NEXT: LBB23_17: ## %else30 ; AVX2-NEXT: testl $65536, %eax ## imm = 0x10000 ; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm0 -; AVX2-NEXT: jne LBB23_33 -; AVX2-NEXT: ## %bb.34: ## %else32 +; AVX2-NEXT: jne LBB23_49 +; AVX2-NEXT: ## %bb.18: ## %else32 ; AVX2-NEXT: testl $131072, %eax ## imm = 0x20000 -; AVX2-NEXT: jne LBB23_35 -; AVX2-NEXT: LBB23_36: ## %else34 +; AVX2-NEXT: jne LBB23_50 +; AVX2-NEXT: LBB23_19: ## %else34 ; AVX2-NEXT: testl $262144, %eax ## imm = 0x40000 -; AVX2-NEXT: jne LBB23_37 -; AVX2-NEXT: LBB23_38: ## %else36 +; AVX2-NEXT: jne LBB23_51 +; AVX2-NEXT: LBB23_20: ## %else36 ; AVX2-NEXT: testl $524288, %eax ## imm = 0x80000 -; AVX2-NEXT: jne LBB23_39 -; AVX2-NEXT: LBB23_40: ## %else38 +; AVX2-NEXT: jne LBB23_52 +; AVX2-NEXT: LBB23_21: ## %else38 ; AVX2-NEXT: testl $1048576, %eax ## imm = 0x100000 -; AVX2-NEXT: jne LBB23_41 -; AVX2-NEXT: LBB23_42: ## %else40 +; AVX2-NEXT: jne LBB23_53 +; AVX2-NEXT: LBB23_22: ## %else40 ; AVX2-NEXT: testl $2097152, %eax ## imm = 0x200000 -; AVX2-NEXT: jne LBB23_43 -; AVX2-NEXT: LBB23_44: ## %else42 +; AVX2-NEXT: jne LBB23_54 +; AVX2-NEXT: LBB23_23: ## %else42 ; AVX2-NEXT: testl $4194304, %eax ## imm = 0x400000 -; AVX2-NEXT: jne LBB23_45 -; AVX2-NEXT: LBB23_46: ## %else44 +; AVX2-NEXT: jne LBB23_55 +; AVX2-NEXT: LBB23_24: ## %else44 ; AVX2-NEXT: testl $8388608, %eax ## imm = 0x800000 -; AVX2-NEXT: jne LBB23_47 -; AVX2-NEXT: LBB23_48: ## %else46 +; AVX2-NEXT: jne LBB23_56 +; AVX2-NEXT: LBB23_25: ## %else46 ; AVX2-NEXT: testl $16777216, %eax ## imm = 0x1000000 -; AVX2-NEXT: jne LBB23_49 -; AVX2-NEXT: LBB23_50: ## %else48 +; AVX2-NEXT: jne LBB23_57 +; AVX2-NEXT: LBB23_26: ## %else48 ; AVX2-NEXT: testl $33554432, %eax ## imm = 0x2000000 -; AVX2-NEXT: jne LBB23_51 -; AVX2-NEXT: LBB23_52: ## %else50 +; AVX2-NEXT: jne LBB23_58 +; AVX2-NEXT: LBB23_27: ## %else50 ; AVX2-NEXT: testl $67108864, %eax ## imm = 0x4000000 -; AVX2-NEXT: jne LBB23_53 -; AVX2-NEXT: LBB23_54: ## %else52 +; AVX2-NEXT: jne LBB23_59 +; AVX2-NEXT: LBB23_28: ## %else52 ; AVX2-NEXT: testl $134217728, %eax ## imm = 0x8000000 -; AVX2-NEXT: jne LBB23_55 -; AVX2-NEXT: LBB23_56: ## %else54 +; AVX2-NEXT: jne LBB23_60 +; AVX2-NEXT: LBB23_29: ## %else54 ; AVX2-NEXT: testl $268435456, %eax ## imm = 0x10000000 -; AVX2-NEXT: jne LBB23_57 -; AVX2-NEXT: LBB23_58: ## %else56 +; AVX2-NEXT: jne LBB23_61 +; AVX2-NEXT: LBB23_30: ## %else56 ; AVX2-NEXT: testl $536870912, %eax ## imm = 0x20000000 -; AVX2-NEXT: jne LBB23_59 -; AVX2-NEXT: LBB23_60: ## %else58 +; AVX2-NEXT: jne LBB23_62 +; AVX2-NEXT: LBB23_31: ## %else58 ; AVX2-NEXT: testl $1073741824, %eax ## imm = 0x40000000 -; AVX2-NEXT: jne LBB23_61 -; AVX2-NEXT: LBB23_62: ## %else60 -; AVX2-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 ; AVX2-NEXT: jne LBB23_63 -; AVX2-NEXT: LBB23_64: ## %else62 +; AVX2-NEXT: LBB23_32: ## %else60 +; AVX2-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 +; AVX2-NEXT: jne LBB23_64 +; AVX2-NEXT: LBB23_33: ## %else62 ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; AVX2-NEXT: LBB23_1: ## %cond.store +; AVX2-NEXT: LBB23_34: ## %cond.store ; AVX2-NEXT: vpextrb $0, %xmm1, (%rdi) ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je LBB23_4 -; AVX2-NEXT: LBB23_3: ## %cond.store1 +; AVX2-NEXT: je LBB23_2 +; AVX2-NEXT: LBB23_35: ## %cond.store1 ; AVX2-NEXT: vpextrb $1, %xmm1, 1(%rdi) ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je LBB23_6 -; AVX2-NEXT: LBB23_5: ## %cond.store3 +; AVX2-NEXT: je LBB23_3 +; AVX2-NEXT: LBB23_36: ## %cond.store3 ; AVX2-NEXT: vpextrb $2, %xmm1, 2(%rdi) ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je LBB23_8 -; AVX2-NEXT: LBB23_7: ## %cond.store5 +; AVX2-NEXT: je LBB23_4 +; AVX2-NEXT: LBB23_37: ## %cond.store5 ; AVX2-NEXT: vpextrb $3, %xmm1, 3(%rdi) ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: je LBB23_10 -; AVX2-NEXT: LBB23_9: ## %cond.store7 +; AVX2-NEXT: je LBB23_5 +; AVX2-NEXT: LBB23_38: ## %cond.store7 ; AVX2-NEXT: vpextrb $4, %xmm1, 4(%rdi) ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: je LBB23_12 -; AVX2-NEXT: LBB23_11: ## %cond.store9 +; AVX2-NEXT: je LBB23_6 +; AVX2-NEXT: LBB23_39: ## %cond.store9 ; AVX2-NEXT: vpextrb $5, %xmm1, 5(%rdi) ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: je LBB23_14 -; AVX2-NEXT: LBB23_13: ## %cond.store11 +; AVX2-NEXT: je LBB23_7 +; AVX2-NEXT: LBB23_40: ## %cond.store11 ; AVX2-NEXT: vpextrb $6, %xmm1, 6(%rdi) ; AVX2-NEXT: testb %al, %al -; AVX2-NEXT: jns LBB23_16 -; AVX2-NEXT: LBB23_15: ## %cond.store13 +; AVX2-NEXT: jns LBB23_8 +; AVX2-NEXT: LBB23_41: ## %cond.store13 ; AVX2-NEXT: vpextrb $7, %xmm1, 7(%rdi) ; AVX2-NEXT: testl $256, %eax ## imm = 0x100 -; AVX2-NEXT: je LBB23_18 -; AVX2-NEXT: LBB23_17: ## %cond.store15 +; AVX2-NEXT: je LBB23_9 +; AVX2-NEXT: LBB23_42: ## %cond.store15 ; AVX2-NEXT: vpextrb $8, %xmm1, 8(%rdi) ; AVX2-NEXT: testl $512, %eax ## imm = 0x200 -; AVX2-NEXT: je LBB23_20 -; AVX2-NEXT: LBB23_19: ## %cond.store17 +; AVX2-NEXT: je LBB23_10 +; AVX2-NEXT: LBB23_43: ## %cond.store17 ; AVX2-NEXT: vpextrb $9, %xmm1, 9(%rdi) ; AVX2-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX2-NEXT: je LBB23_22 -; AVX2-NEXT: LBB23_21: ## %cond.store19 +; AVX2-NEXT: je LBB23_11 +; AVX2-NEXT: LBB23_44: ## %cond.store19 ; AVX2-NEXT: vpextrb $10, %xmm1, 10(%rdi) ; AVX2-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX2-NEXT: je LBB23_24 -; AVX2-NEXT: LBB23_23: ## %cond.store21 +; AVX2-NEXT: je LBB23_12 +; AVX2-NEXT: LBB23_45: ## %cond.store21 ; AVX2-NEXT: vpextrb $11, %xmm1, 11(%rdi) ; AVX2-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX2-NEXT: je LBB23_26 -; AVX2-NEXT: LBB23_25: ## %cond.store23 +; AVX2-NEXT: je LBB23_13 +; AVX2-NEXT: LBB23_46: ## %cond.store23 ; AVX2-NEXT: vpextrb $12, %xmm1, 12(%rdi) ; AVX2-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX2-NEXT: je LBB23_28 -; AVX2-NEXT: LBB23_27: ## %cond.store25 +; AVX2-NEXT: je LBB23_14 +; AVX2-NEXT: LBB23_47: ## %cond.store25 ; AVX2-NEXT: vpextrb $13, %xmm1, 13(%rdi) ; AVX2-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX2-NEXT: je LBB23_30 -; AVX2-NEXT: LBB23_29: ## %cond.store27 +; AVX2-NEXT: je LBB23_15 +; AVX2-NEXT: LBB23_48: ## %cond.store27 ; AVX2-NEXT: vpextrb $14, %xmm1, 14(%rdi) ; AVX2-NEXT: testw %ax, %ax -; AVX2-NEXT: js LBB23_31 -; AVX2-NEXT: jmp LBB23_32 -; AVX2-NEXT: LBB23_33: ## %cond.store31 +; AVX2-NEXT: js LBB23_16 +; AVX2-NEXT: jmp LBB23_17 +; AVX2-NEXT: LBB23_49: ## %cond.store31 ; AVX2-NEXT: vpextrb $0, %xmm0, 16(%rdi) ; AVX2-NEXT: testl $131072, %eax ## imm = 0x20000 -; AVX2-NEXT: je LBB23_36 -; AVX2-NEXT: LBB23_35: ## %cond.store33 +; AVX2-NEXT: je LBB23_19 +; AVX2-NEXT: LBB23_50: ## %cond.store33 ; AVX2-NEXT: vpextrb $1, %xmm0, 17(%rdi) ; AVX2-NEXT: testl $262144, %eax ## imm = 0x40000 -; AVX2-NEXT: je LBB23_38 -; AVX2-NEXT: LBB23_37: ## %cond.store35 +; AVX2-NEXT: je LBB23_20 +; AVX2-NEXT: LBB23_51: ## %cond.store35 ; AVX2-NEXT: vpextrb $2, %xmm0, 18(%rdi) ; AVX2-NEXT: testl $524288, %eax ## imm = 0x80000 -; AVX2-NEXT: je LBB23_40 -; AVX2-NEXT: LBB23_39: ## %cond.store37 +; AVX2-NEXT: je LBB23_21 +; AVX2-NEXT: LBB23_52: ## %cond.store37 ; AVX2-NEXT: vpextrb $3, %xmm0, 19(%rdi) ; AVX2-NEXT: testl $1048576, %eax ## imm = 0x100000 -; AVX2-NEXT: je LBB23_42 -; AVX2-NEXT: LBB23_41: ## %cond.store39 +; AVX2-NEXT: je LBB23_22 +; AVX2-NEXT: LBB23_53: ## %cond.store39 ; AVX2-NEXT: vpextrb $4, %xmm0, 20(%rdi) ; AVX2-NEXT: testl $2097152, %eax ## imm = 0x200000 -; AVX2-NEXT: je LBB23_44 -; AVX2-NEXT: LBB23_43: ## %cond.store41 +; AVX2-NEXT: je LBB23_23 +; AVX2-NEXT: LBB23_54: ## %cond.store41 ; AVX2-NEXT: vpextrb $5, %xmm0, 21(%rdi) ; AVX2-NEXT: testl $4194304, %eax ## imm = 0x400000 -; AVX2-NEXT: je LBB23_46 -; AVX2-NEXT: LBB23_45: ## %cond.store43 +; AVX2-NEXT: je LBB23_24 +; AVX2-NEXT: LBB23_55: ## %cond.store43 ; AVX2-NEXT: vpextrb $6, %xmm0, 22(%rdi) ; AVX2-NEXT: testl $8388608, %eax ## imm = 0x800000 -; AVX2-NEXT: je LBB23_48 -; AVX2-NEXT: LBB23_47: ## %cond.store45 +; AVX2-NEXT: je LBB23_25 +; AVX2-NEXT: LBB23_56: ## %cond.store45 ; AVX2-NEXT: vpextrb $7, %xmm0, 23(%rdi) ; AVX2-NEXT: testl $16777216, %eax ## imm = 0x1000000 -; AVX2-NEXT: je LBB23_50 -; AVX2-NEXT: LBB23_49: ## %cond.store47 +; AVX2-NEXT: je LBB23_26 +; AVX2-NEXT: LBB23_57: ## %cond.store47 ; AVX2-NEXT: vpextrb $8, %xmm0, 24(%rdi) ; AVX2-NEXT: testl $33554432, %eax ## imm = 0x2000000 -; AVX2-NEXT: je LBB23_52 -; AVX2-NEXT: LBB23_51: ## %cond.store49 +; AVX2-NEXT: je LBB23_27 +; AVX2-NEXT: LBB23_58: ## %cond.store49 ; AVX2-NEXT: vpextrb $9, %xmm0, 25(%rdi) ; AVX2-NEXT: testl $67108864, %eax ## imm = 0x4000000 -; AVX2-NEXT: je LBB23_54 -; AVX2-NEXT: LBB23_53: ## %cond.store51 +; AVX2-NEXT: je LBB23_28 +; AVX2-NEXT: LBB23_59: ## %cond.store51 ; AVX2-NEXT: vpextrb $10, %xmm0, 26(%rdi) ; AVX2-NEXT: testl $134217728, %eax ## imm = 0x8000000 -; AVX2-NEXT: je LBB23_56 -; AVX2-NEXT: LBB23_55: ## %cond.store53 +; AVX2-NEXT: je LBB23_29 +; AVX2-NEXT: LBB23_60: ## %cond.store53 ; AVX2-NEXT: vpextrb $11, %xmm0, 27(%rdi) ; AVX2-NEXT: testl $268435456, %eax ## imm = 0x10000000 -; AVX2-NEXT: je LBB23_58 -; AVX2-NEXT: LBB23_57: ## %cond.store55 +; AVX2-NEXT: je LBB23_30 +; AVX2-NEXT: LBB23_61: ## %cond.store55 ; AVX2-NEXT: vpextrb $12, %xmm0, 28(%rdi) ; AVX2-NEXT: testl $536870912, %eax ## imm = 0x20000000 -; AVX2-NEXT: je LBB23_60 -; AVX2-NEXT: LBB23_59: ## %cond.store57 +; AVX2-NEXT: je LBB23_31 +; AVX2-NEXT: LBB23_62: ## %cond.store57 ; AVX2-NEXT: vpextrb $13, %xmm0, 29(%rdi) ; AVX2-NEXT: testl $1073741824, %eax ## imm = 0x40000000 -; AVX2-NEXT: je LBB23_62 -; AVX2-NEXT: LBB23_61: ## %cond.store59 +; AVX2-NEXT: je LBB23_32 +; AVX2-NEXT: LBB23_63: ## %cond.store59 ; AVX2-NEXT: vpextrb $14, %xmm0, 30(%rdi) ; AVX2-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 -; AVX2-NEXT: je LBB23_64 -; AVX2-NEXT: LBB23_63: ## %cond.store61 +; AVX2-NEXT: je LBB23_33 +; AVX2-NEXT: LBB23_64: ## %cond.store61 ; AVX2-NEXT: vpextrb $15, %xmm0, 31(%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq @@ -5257,228 +5257,228 @@ define void @store_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %val) no ; AVX512F-NEXT: vpcmpeqb %ymm2, %ymm0, %ymm0 ; AVX512F-NEXT: vpmovmskb %ymm0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne LBB23_1 -; AVX512F-NEXT: ## %bb.2: ## %else +; AVX512F-NEXT: jne LBB23_34 +; AVX512F-NEXT: ## %bb.1: ## %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne LBB23_3 -; AVX512F-NEXT: LBB23_4: ## %else2 +; AVX512F-NEXT: jne LBB23_35 +; AVX512F-NEXT: LBB23_2: ## %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne LBB23_5 -; AVX512F-NEXT: LBB23_6: ## %else4 +; AVX512F-NEXT: jne LBB23_36 +; AVX512F-NEXT: LBB23_3: ## %else4 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne LBB23_7 -; AVX512F-NEXT: LBB23_8: ## %else6 +; AVX512F-NEXT: jne LBB23_37 +; AVX512F-NEXT: LBB23_4: ## %else6 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne LBB23_9 -; AVX512F-NEXT: LBB23_10: ## %else8 +; AVX512F-NEXT: jne LBB23_38 +; AVX512F-NEXT: LBB23_5: ## %else8 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne LBB23_11 -; AVX512F-NEXT: LBB23_12: ## %else10 +; AVX512F-NEXT: jne LBB23_39 +; AVX512F-NEXT: LBB23_6: ## %else10 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne LBB23_13 -; AVX512F-NEXT: LBB23_14: ## %else12 +; AVX512F-NEXT: jne LBB23_40 +; AVX512F-NEXT: LBB23_7: ## %else12 ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: js LBB23_15 -; AVX512F-NEXT: LBB23_16: ## %else14 +; AVX512F-NEXT: js LBB23_41 +; AVX512F-NEXT: LBB23_8: ## %else14 ; AVX512F-NEXT: testl $256, %eax ## imm = 0x100 -; AVX512F-NEXT: jne LBB23_17 -; AVX512F-NEXT: LBB23_18: ## %else16 +; AVX512F-NEXT: jne LBB23_42 +; AVX512F-NEXT: LBB23_9: ## %else16 ; AVX512F-NEXT: testl $512, %eax ## imm = 0x200 -; AVX512F-NEXT: jne LBB23_19 -; AVX512F-NEXT: LBB23_20: ## %else18 +; AVX512F-NEXT: jne LBB23_43 +; AVX512F-NEXT: LBB23_10: ## %else18 ; AVX512F-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX512F-NEXT: jne LBB23_21 -; AVX512F-NEXT: LBB23_22: ## %else20 +; AVX512F-NEXT: jne LBB23_44 +; AVX512F-NEXT: LBB23_11: ## %else20 ; AVX512F-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX512F-NEXT: jne LBB23_23 -; AVX512F-NEXT: LBB23_24: ## %else22 +; AVX512F-NEXT: jne LBB23_45 +; AVX512F-NEXT: LBB23_12: ## %else22 ; AVX512F-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX512F-NEXT: jne LBB23_25 -; AVX512F-NEXT: LBB23_26: ## %else24 +; AVX512F-NEXT: jne LBB23_46 +; AVX512F-NEXT: LBB23_13: ## %else24 ; AVX512F-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX512F-NEXT: jne LBB23_27 -; AVX512F-NEXT: LBB23_28: ## %else26 +; AVX512F-NEXT: jne LBB23_47 +; AVX512F-NEXT: LBB23_14: ## %else26 ; AVX512F-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX512F-NEXT: jne LBB23_29 -; AVX512F-NEXT: LBB23_30: ## %else28 +; AVX512F-NEXT: jne LBB23_48 +; AVX512F-NEXT: LBB23_15: ## %else28 ; AVX512F-NEXT: testw %ax, %ax -; AVX512F-NEXT: jns LBB23_32 -; AVX512F-NEXT: LBB23_31: ## %cond.store29 +; AVX512F-NEXT: jns LBB23_17 +; AVX512F-NEXT: LBB23_16: ## %cond.store29 ; AVX512F-NEXT: vpextrb $15, %xmm1, 15(%rdi) -; AVX512F-NEXT: LBB23_32: ## %else30 +; AVX512F-NEXT: LBB23_17: ## %else30 ; AVX512F-NEXT: testl $65536, %eax ## imm = 0x10000 ; AVX512F-NEXT: vextracti128 $1, %ymm1, %xmm0 -; AVX512F-NEXT: jne LBB23_33 -; AVX512F-NEXT: ## %bb.34: ## %else32 +; AVX512F-NEXT: jne LBB23_49 +; AVX512F-NEXT: ## %bb.18: ## %else32 ; AVX512F-NEXT: testl $131072, %eax ## imm = 0x20000 -; AVX512F-NEXT: jne LBB23_35 -; AVX512F-NEXT: LBB23_36: ## %else34 +; AVX512F-NEXT: jne LBB23_50 +; AVX512F-NEXT: LBB23_19: ## %else34 ; AVX512F-NEXT: testl $262144, %eax ## imm = 0x40000 -; AVX512F-NEXT: jne LBB23_37 -; AVX512F-NEXT: LBB23_38: ## %else36 +; AVX512F-NEXT: jne LBB23_51 +; AVX512F-NEXT: LBB23_20: ## %else36 ; AVX512F-NEXT: testl $524288, %eax ## imm = 0x80000 -; AVX512F-NEXT: jne LBB23_39 -; AVX512F-NEXT: LBB23_40: ## %else38 +; AVX512F-NEXT: jne LBB23_52 +; AVX512F-NEXT: LBB23_21: ## %else38 ; AVX512F-NEXT: testl $1048576, %eax ## imm = 0x100000 -; AVX512F-NEXT: jne LBB23_41 -; AVX512F-NEXT: LBB23_42: ## %else40 +; AVX512F-NEXT: jne LBB23_53 +; AVX512F-NEXT: LBB23_22: ## %else40 ; AVX512F-NEXT: testl $2097152, %eax ## imm = 0x200000 -; AVX512F-NEXT: jne LBB23_43 -; AVX512F-NEXT: LBB23_44: ## %else42 +; AVX512F-NEXT: jne LBB23_54 +; AVX512F-NEXT: LBB23_23: ## %else42 ; AVX512F-NEXT: testl $4194304, %eax ## imm = 0x400000 -; AVX512F-NEXT: jne LBB23_45 -; AVX512F-NEXT: LBB23_46: ## %else44 +; AVX512F-NEXT: jne LBB23_55 +; AVX512F-NEXT: LBB23_24: ## %else44 ; AVX512F-NEXT: testl $8388608, %eax ## imm = 0x800000 -; AVX512F-NEXT: jne LBB23_47 -; AVX512F-NEXT: LBB23_48: ## %else46 +; AVX512F-NEXT: jne LBB23_56 +; AVX512F-NEXT: LBB23_25: ## %else46 ; AVX512F-NEXT: testl $16777216, %eax ## imm = 0x1000000 -; AVX512F-NEXT: jne LBB23_49 -; AVX512F-NEXT: LBB23_50: ## %else48 +; AVX512F-NEXT: jne LBB23_57 +; AVX512F-NEXT: LBB23_26: ## %else48 ; AVX512F-NEXT: testl $33554432, %eax ## imm = 0x2000000 -; AVX512F-NEXT: jne LBB23_51 -; AVX512F-NEXT: LBB23_52: ## %else50 +; AVX512F-NEXT: jne LBB23_58 +; AVX512F-NEXT: LBB23_27: ## %else50 ; AVX512F-NEXT: testl $67108864, %eax ## imm = 0x4000000 -; AVX512F-NEXT: jne LBB23_53 -; AVX512F-NEXT: LBB23_54: ## %else52 +; AVX512F-NEXT: jne LBB23_59 +; AVX512F-NEXT: LBB23_28: ## %else52 ; AVX512F-NEXT: testl $134217728, %eax ## imm = 0x8000000 -; AVX512F-NEXT: jne LBB23_55 -; AVX512F-NEXT: LBB23_56: ## %else54 +; AVX512F-NEXT: jne LBB23_60 +; AVX512F-NEXT: LBB23_29: ## %else54 ; AVX512F-NEXT: testl $268435456, %eax ## imm = 0x10000000 -; AVX512F-NEXT: jne LBB23_57 -; AVX512F-NEXT: LBB23_58: ## %else56 +; AVX512F-NEXT: jne LBB23_61 +; AVX512F-NEXT: LBB23_30: ## %else56 ; AVX512F-NEXT: testl $536870912, %eax ## imm = 0x20000000 -; AVX512F-NEXT: jne LBB23_59 -; AVX512F-NEXT: LBB23_60: ## %else58 +; AVX512F-NEXT: jne LBB23_62 +; AVX512F-NEXT: LBB23_31: ## %else58 ; AVX512F-NEXT: testl $1073741824, %eax ## imm = 0x40000000 -; AVX512F-NEXT: jne LBB23_61 -; AVX512F-NEXT: LBB23_62: ## %else60 -; AVX512F-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 ; AVX512F-NEXT: jne LBB23_63 -; AVX512F-NEXT: LBB23_64: ## %else62 +; AVX512F-NEXT: LBB23_32: ## %else60 +; AVX512F-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 +; AVX512F-NEXT: jne LBB23_64 +; AVX512F-NEXT: LBB23_33: ## %else62 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: LBB23_1: ## %cond.store +; AVX512F-NEXT: LBB23_34: ## %cond.store ; AVX512F-NEXT: vpextrb $0, %xmm1, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je LBB23_4 -; AVX512F-NEXT: LBB23_3: ## %cond.store1 +; AVX512F-NEXT: je LBB23_2 +; AVX512F-NEXT: LBB23_35: ## %cond.store1 ; AVX512F-NEXT: vpextrb $1, %xmm1, 1(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je LBB23_6 -; AVX512F-NEXT: LBB23_5: ## %cond.store3 +; AVX512F-NEXT: je LBB23_3 +; AVX512F-NEXT: LBB23_36: ## %cond.store3 ; AVX512F-NEXT: vpextrb $2, %xmm1, 2(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je LBB23_8 -; AVX512F-NEXT: LBB23_7: ## %cond.store5 +; AVX512F-NEXT: je LBB23_4 +; AVX512F-NEXT: LBB23_37: ## %cond.store5 ; AVX512F-NEXT: vpextrb $3, %xmm1, 3(%rdi) ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je LBB23_10 -; AVX512F-NEXT: LBB23_9: ## %cond.store7 +; AVX512F-NEXT: je LBB23_5 +; AVX512F-NEXT: LBB23_38: ## %cond.store7 ; AVX512F-NEXT: vpextrb $4, %xmm1, 4(%rdi) ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je LBB23_12 -; AVX512F-NEXT: LBB23_11: ## %cond.store9 +; AVX512F-NEXT: je LBB23_6 +; AVX512F-NEXT: LBB23_39: ## %cond.store9 ; AVX512F-NEXT: vpextrb $5, %xmm1, 5(%rdi) ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je LBB23_14 -; AVX512F-NEXT: LBB23_13: ## %cond.store11 +; AVX512F-NEXT: je LBB23_7 +; AVX512F-NEXT: LBB23_40: ## %cond.store11 ; AVX512F-NEXT: vpextrb $6, %xmm1, 6(%rdi) ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: jns LBB23_16 -; AVX512F-NEXT: LBB23_15: ## %cond.store13 +; AVX512F-NEXT: jns LBB23_8 +; AVX512F-NEXT: LBB23_41: ## %cond.store13 ; AVX512F-NEXT: vpextrb $7, %xmm1, 7(%rdi) ; AVX512F-NEXT: testl $256, %eax ## imm = 0x100 -; AVX512F-NEXT: je LBB23_18 -; AVX512F-NEXT: LBB23_17: ## %cond.store15 +; AVX512F-NEXT: je LBB23_9 +; AVX512F-NEXT: LBB23_42: ## %cond.store15 ; AVX512F-NEXT: vpextrb $8, %xmm1, 8(%rdi) ; AVX512F-NEXT: testl $512, %eax ## imm = 0x200 -; AVX512F-NEXT: je LBB23_20 -; AVX512F-NEXT: LBB23_19: ## %cond.store17 +; AVX512F-NEXT: je LBB23_10 +; AVX512F-NEXT: LBB23_43: ## %cond.store17 ; AVX512F-NEXT: vpextrb $9, %xmm1, 9(%rdi) ; AVX512F-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX512F-NEXT: je LBB23_22 -; AVX512F-NEXT: LBB23_21: ## %cond.store19 +; AVX512F-NEXT: je LBB23_11 +; AVX512F-NEXT: LBB23_44: ## %cond.store19 ; AVX512F-NEXT: vpextrb $10, %xmm1, 10(%rdi) ; AVX512F-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX512F-NEXT: je LBB23_24 -; AVX512F-NEXT: LBB23_23: ## %cond.store21 +; AVX512F-NEXT: je LBB23_12 +; AVX512F-NEXT: LBB23_45: ## %cond.store21 ; AVX512F-NEXT: vpextrb $11, %xmm1, 11(%rdi) ; AVX512F-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX512F-NEXT: je LBB23_26 -; AVX512F-NEXT: LBB23_25: ## %cond.store23 +; AVX512F-NEXT: je LBB23_13 +; AVX512F-NEXT: LBB23_46: ## %cond.store23 ; AVX512F-NEXT: vpextrb $12, %xmm1, 12(%rdi) ; AVX512F-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX512F-NEXT: je LBB23_28 -; AVX512F-NEXT: LBB23_27: ## %cond.store25 +; AVX512F-NEXT: je LBB23_14 +; AVX512F-NEXT: LBB23_47: ## %cond.store25 ; AVX512F-NEXT: vpextrb $13, %xmm1, 13(%rdi) ; AVX512F-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX512F-NEXT: je LBB23_30 -; AVX512F-NEXT: LBB23_29: ## %cond.store27 +; AVX512F-NEXT: je LBB23_15 +; AVX512F-NEXT: LBB23_48: ## %cond.store27 ; AVX512F-NEXT: vpextrb $14, %xmm1, 14(%rdi) ; AVX512F-NEXT: testw %ax, %ax -; AVX512F-NEXT: js LBB23_31 -; AVX512F-NEXT: jmp LBB23_32 -; AVX512F-NEXT: LBB23_33: ## %cond.store31 +; AVX512F-NEXT: js LBB23_16 +; AVX512F-NEXT: jmp LBB23_17 +; AVX512F-NEXT: LBB23_49: ## %cond.store31 ; AVX512F-NEXT: vpextrb $0, %xmm0, 16(%rdi) ; AVX512F-NEXT: testl $131072, %eax ## imm = 0x20000 -; AVX512F-NEXT: je LBB23_36 -; AVX512F-NEXT: LBB23_35: ## %cond.store33 +; AVX512F-NEXT: je LBB23_19 +; AVX512F-NEXT: LBB23_50: ## %cond.store33 ; AVX512F-NEXT: vpextrb $1, %xmm0, 17(%rdi) ; AVX512F-NEXT: testl $262144, %eax ## imm = 0x40000 -; AVX512F-NEXT: je LBB23_38 -; AVX512F-NEXT: LBB23_37: ## %cond.store35 +; AVX512F-NEXT: je LBB23_20 +; AVX512F-NEXT: LBB23_51: ## %cond.store35 ; AVX512F-NEXT: vpextrb $2, %xmm0, 18(%rdi) ; AVX512F-NEXT: testl $524288, %eax ## imm = 0x80000 -; AVX512F-NEXT: je LBB23_40 -; AVX512F-NEXT: LBB23_39: ## %cond.store37 +; AVX512F-NEXT: je LBB23_21 +; AVX512F-NEXT: LBB23_52: ## %cond.store37 ; AVX512F-NEXT: vpextrb $3, %xmm0, 19(%rdi) ; AVX512F-NEXT: testl $1048576, %eax ## imm = 0x100000 -; AVX512F-NEXT: je LBB23_42 -; AVX512F-NEXT: LBB23_41: ## %cond.store39 +; AVX512F-NEXT: je LBB23_22 +; AVX512F-NEXT: LBB23_53: ## %cond.store39 ; AVX512F-NEXT: vpextrb $4, %xmm0, 20(%rdi) ; AVX512F-NEXT: testl $2097152, %eax ## imm = 0x200000 -; AVX512F-NEXT: je LBB23_44 -; AVX512F-NEXT: LBB23_43: ## %cond.store41 +; AVX512F-NEXT: je LBB23_23 +; AVX512F-NEXT: LBB23_54: ## %cond.store41 ; AVX512F-NEXT: vpextrb $5, %xmm0, 21(%rdi) ; AVX512F-NEXT: testl $4194304, %eax ## imm = 0x400000 -; AVX512F-NEXT: je LBB23_46 -; AVX512F-NEXT: LBB23_45: ## %cond.store43 +; AVX512F-NEXT: je LBB23_24 +; AVX512F-NEXT: LBB23_55: ## %cond.store43 ; AVX512F-NEXT: vpextrb $6, %xmm0, 22(%rdi) ; AVX512F-NEXT: testl $8388608, %eax ## imm = 0x800000 -; AVX512F-NEXT: je LBB23_48 -; AVX512F-NEXT: LBB23_47: ## %cond.store45 +; AVX512F-NEXT: je LBB23_25 +; AVX512F-NEXT: LBB23_56: ## %cond.store45 ; AVX512F-NEXT: vpextrb $7, %xmm0, 23(%rdi) ; AVX512F-NEXT: testl $16777216, %eax ## imm = 0x1000000 -; AVX512F-NEXT: je LBB23_50 -; AVX512F-NEXT: LBB23_49: ## %cond.store47 +; AVX512F-NEXT: je LBB23_26 +; AVX512F-NEXT: LBB23_57: ## %cond.store47 ; AVX512F-NEXT: vpextrb $8, %xmm0, 24(%rdi) ; AVX512F-NEXT: testl $33554432, %eax ## imm = 0x2000000 -; AVX512F-NEXT: je LBB23_52 -; AVX512F-NEXT: LBB23_51: ## %cond.store49 +; AVX512F-NEXT: je LBB23_27 +; AVX512F-NEXT: LBB23_58: ## %cond.store49 ; AVX512F-NEXT: vpextrb $9, %xmm0, 25(%rdi) ; AVX512F-NEXT: testl $67108864, %eax ## imm = 0x4000000 -; AVX512F-NEXT: je LBB23_54 -; AVX512F-NEXT: LBB23_53: ## %cond.store51 +; AVX512F-NEXT: je LBB23_28 +; AVX512F-NEXT: LBB23_59: ## %cond.store51 ; AVX512F-NEXT: vpextrb $10, %xmm0, 26(%rdi) ; AVX512F-NEXT: testl $134217728, %eax ## imm = 0x8000000 -; AVX512F-NEXT: je LBB23_56 -; AVX512F-NEXT: LBB23_55: ## %cond.store53 +; AVX512F-NEXT: je LBB23_29 +; AVX512F-NEXT: LBB23_60: ## %cond.store53 ; AVX512F-NEXT: vpextrb $11, %xmm0, 27(%rdi) ; AVX512F-NEXT: testl $268435456, %eax ## imm = 0x10000000 -; AVX512F-NEXT: je LBB23_58 -; AVX512F-NEXT: LBB23_57: ## %cond.store55 +; AVX512F-NEXT: je LBB23_30 +; AVX512F-NEXT: LBB23_61: ## %cond.store55 ; AVX512F-NEXT: vpextrb $12, %xmm0, 28(%rdi) ; AVX512F-NEXT: testl $536870912, %eax ## imm = 0x20000000 -; AVX512F-NEXT: je LBB23_60 -; AVX512F-NEXT: LBB23_59: ## %cond.store57 +; AVX512F-NEXT: je LBB23_31 +; AVX512F-NEXT: LBB23_62: ## %cond.store57 ; AVX512F-NEXT: vpextrb $13, %xmm0, 29(%rdi) ; AVX512F-NEXT: testl $1073741824, %eax ## imm = 0x40000000 -; AVX512F-NEXT: je LBB23_62 -; AVX512F-NEXT: LBB23_61: ## %cond.store59 +; AVX512F-NEXT: je LBB23_32 +; AVX512F-NEXT: LBB23_63: ## %cond.store59 ; AVX512F-NEXT: vpextrb $14, %xmm0, 30(%rdi) ; AVX512F-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 -; AVX512F-NEXT: je LBB23_64 -; AVX512F-NEXT: LBB23_63: ## %cond.store61 +; AVX512F-NEXT: je LBB23_33 +; AVX512F-NEXT: LBB23_64: ## %cond.store61 ; AVX512F-NEXT: vpextrb $15, %xmm0, 31(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -5489,228 +5489,228 @@ define void @store_v32i8_v32i8(<32 x i8> %trigger, ptr %addr, <32 x i8> %val) no ; AVX512VLDQ-NEXT: vpcmpeqb %ymm2, %ymm0, %ymm0 ; AVX512VLDQ-NEXT: vpmovmskb %ymm0, %eax ; AVX512VLDQ-NEXT: testb $1, %al -; AVX512VLDQ-NEXT: jne LBB23_1 -; AVX512VLDQ-NEXT: ## %bb.2: ## %else +; AVX512VLDQ-NEXT: jne LBB23_34 +; AVX512VLDQ-NEXT: ## %bb.1: ## %else ; AVX512VLDQ-NEXT: testb $2, %al -; AVX512VLDQ-NEXT: jne LBB23_3 -; AVX512VLDQ-NEXT: LBB23_4: ## %else2 +; AVX512VLDQ-NEXT: jne LBB23_35 +; AVX512VLDQ-NEXT: LBB23_2: ## %else2 ; AVX512VLDQ-NEXT: testb $4, %al -; AVX512VLDQ-NEXT: jne LBB23_5 -; AVX512VLDQ-NEXT: LBB23_6: ## %else4 +; AVX512VLDQ-NEXT: jne LBB23_36 +; AVX512VLDQ-NEXT: LBB23_3: ## %else4 ; AVX512VLDQ-NEXT: testb $8, %al -; AVX512VLDQ-NEXT: jne LBB23_7 -; AVX512VLDQ-NEXT: LBB23_8: ## %else6 +; AVX512VLDQ-NEXT: jne LBB23_37 +; AVX512VLDQ-NEXT: LBB23_4: ## %else6 ; AVX512VLDQ-NEXT: testb $16, %al -; AVX512VLDQ-NEXT: jne LBB23_9 -; AVX512VLDQ-NEXT: LBB23_10: ## %else8 +; AVX512VLDQ-NEXT: jne LBB23_38 +; AVX512VLDQ-NEXT: LBB23_5: ## %else8 ; AVX512VLDQ-NEXT: testb $32, %al -; AVX512VLDQ-NEXT: jne LBB23_11 -; AVX512VLDQ-NEXT: LBB23_12: ## %else10 +; AVX512VLDQ-NEXT: jne LBB23_39 +; AVX512VLDQ-NEXT: LBB23_6: ## %else10 ; AVX512VLDQ-NEXT: testb $64, %al -; AVX512VLDQ-NEXT: jne LBB23_13 -; AVX512VLDQ-NEXT: LBB23_14: ## %else12 +; AVX512VLDQ-NEXT: jne LBB23_40 +; AVX512VLDQ-NEXT: LBB23_7: ## %else12 ; AVX512VLDQ-NEXT: testb %al, %al -; AVX512VLDQ-NEXT: js LBB23_15 -; AVX512VLDQ-NEXT: LBB23_16: ## %else14 +; AVX512VLDQ-NEXT: js LBB23_41 +; AVX512VLDQ-NEXT: LBB23_8: ## %else14 ; AVX512VLDQ-NEXT: testl $256, %eax ## imm = 0x100 -; AVX512VLDQ-NEXT: jne LBB23_17 -; AVX512VLDQ-NEXT: LBB23_18: ## %else16 +; AVX512VLDQ-NEXT: jne LBB23_42 +; AVX512VLDQ-NEXT: LBB23_9: ## %else16 ; AVX512VLDQ-NEXT: testl $512, %eax ## imm = 0x200 -; AVX512VLDQ-NEXT: jne LBB23_19 -; AVX512VLDQ-NEXT: LBB23_20: ## %else18 +; AVX512VLDQ-NEXT: jne LBB23_43 +; AVX512VLDQ-NEXT: LBB23_10: ## %else18 ; AVX512VLDQ-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX512VLDQ-NEXT: jne LBB23_21 -; AVX512VLDQ-NEXT: LBB23_22: ## %else20 +; AVX512VLDQ-NEXT: jne LBB23_44 +; AVX512VLDQ-NEXT: LBB23_11: ## %else20 ; AVX512VLDQ-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX512VLDQ-NEXT: jne LBB23_23 -; AVX512VLDQ-NEXT: LBB23_24: ## %else22 +; AVX512VLDQ-NEXT: jne LBB23_45 +; AVX512VLDQ-NEXT: LBB23_12: ## %else22 ; AVX512VLDQ-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX512VLDQ-NEXT: jne LBB23_25 -; AVX512VLDQ-NEXT: LBB23_26: ## %else24 +; AVX512VLDQ-NEXT: jne LBB23_46 +; AVX512VLDQ-NEXT: LBB23_13: ## %else24 ; AVX512VLDQ-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX512VLDQ-NEXT: jne LBB23_27 -; AVX512VLDQ-NEXT: LBB23_28: ## %else26 +; AVX512VLDQ-NEXT: jne LBB23_47 +; AVX512VLDQ-NEXT: LBB23_14: ## %else26 ; AVX512VLDQ-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX512VLDQ-NEXT: jne LBB23_29 -; AVX512VLDQ-NEXT: LBB23_30: ## %else28 +; AVX512VLDQ-NEXT: jne LBB23_48 +; AVX512VLDQ-NEXT: LBB23_15: ## %else28 ; AVX512VLDQ-NEXT: testw %ax, %ax -; AVX512VLDQ-NEXT: jns LBB23_32 -; AVX512VLDQ-NEXT: LBB23_31: ## %cond.store29 +; AVX512VLDQ-NEXT: jns LBB23_17 +; AVX512VLDQ-NEXT: LBB23_16: ## %cond.store29 ; AVX512VLDQ-NEXT: vpextrb $15, %xmm1, 15(%rdi) -; AVX512VLDQ-NEXT: LBB23_32: ## %else30 +; AVX512VLDQ-NEXT: LBB23_17: ## %else30 ; AVX512VLDQ-NEXT: testl $65536, %eax ## imm = 0x10000 ; AVX512VLDQ-NEXT: vextracti128 $1, %ymm1, %xmm0 -; AVX512VLDQ-NEXT: jne LBB23_33 -; AVX512VLDQ-NEXT: ## %bb.34: ## %else32 +; AVX512VLDQ-NEXT: jne LBB23_49 +; AVX512VLDQ-NEXT: ## %bb.18: ## %else32 ; AVX512VLDQ-NEXT: testl $131072, %eax ## imm = 0x20000 -; AVX512VLDQ-NEXT: jne LBB23_35 -; AVX512VLDQ-NEXT: LBB23_36: ## %else34 +; AVX512VLDQ-NEXT: jne LBB23_50 +; AVX512VLDQ-NEXT: LBB23_19: ## %else34 ; AVX512VLDQ-NEXT: testl $262144, %eax ## imm = 0x40000 -; AVX512VLDQ-NEXT: jne LBB23_37 -; AVX512VLDQ-NEXT: LBB23_38: ## %else36 +; AVX512VLDQ-NEXT: jne LBB23_51 +; AVX512VLDQ-NEXT: LBB23_20: ## %else36 ; AVX512VLDQ-NEXT: testl $524288, %eax ## imm = 0x80000 -; AVX512VLDQ-NEXT: jne LBB23_39 -; AVX512VLDQ-NEXT: LBB23_40: ## %else38 +; AVX512VLDQ-NEXT: jne LBB23_52 +; AVX512VLDQ-NEXT: LBB23_21: ## %else38 ; AVX512VLDQ-NEXT: testl $1048576, %eax ## imm = 0x100000 -; AVX512VLDQ-NEXT: jne LBB23_41 -; AVX512VLDQ-NEXT: LBB23_42: ## %else40 +; AVX512VLDQ-NEXT: jne LBB23_53 +; AVX512VLDQ-NEXT: LBB23_22: ## %else40 ; AVX512VLDQ-NEXT: testl $2097152, %eax ## imm = 0x200000 -; AVX512VLDQ-NEXT: jne LBB23_43 -; AVX512VLDQ-NEXT: LBB23_44: ## %else42 +; AVX512VLDQ-NEXT: jne LBB23_54 +; AVX512VLDQ-NEXT: LBB23_23: ## %else42 ; AVX512VLDQ-NEXT: testl $4194304, %eax ## imm = 0x400000 -; AVX512VLDQ-NEXT: jne LBB23_45 -; AVX512VLDQ-NEXT: LBB23_46: ## %else44 +; AVX512VLDQ-NEXT: jne LBB23_55 +; AVX512VLDQ-NEXT: LBB23_24: ## %else44 ; AVX512VLDQ-NEXT: testl $8388608, %eax ## imm = 0x800000 -; AVX512VLDQ-NEXT: jne LBB23_47 -; AVX512VLDQ-NEXT: LBB23_48: ## %else46 +; AVX512VLDQ-NEXT: jne LBB23_56 +; AVX512VLDQ-NEXT: LBB23_25: ## %else46 ; AVX512VLDQ-NEXT: testl $16777216, %eax ## imm = 0x1000000 -; AVX512VLDQ-NEXT: jne LBB23_49 -; AVX512VLDQ-NEXT: LBB23_50: ## %else48 +; AVX512VLDQ-NEXT: jne LBB23_57 +; AVX512VLDQ-NEXT: LBB23_26: ## %else48 ; AVX512VLDQ-NEXT: testl $33554432, %eax ## imm = 0x2000000 -; AVX512VLDQ-NEXT: jne LBB23_51 -; AVX512VLDQ-NEXT: LBB23_52: ## %else50 +; AVX512VLDQ-NEXT: jne LBB23_58 +; AVX512VLDQ-NEXT: LBB23_27: ## %else50 ; AVX512VLDQ-NEXT: testl $67108864, %eax ## imm = 0x4000000 -; AVX512VLDQ-NEXT: jne LBB23_53 -; AVX512VLDQ-NEXT: LBB23_54: ## %else52 +; AVX512VLDQ-NEXT: jne LBB23_59 +; AVX512VLDQ-NEXT: LBB23_28: ## %else52 ; AVX512VLDQ-NEXT: testl $134217728, %eax ## imm = 0x8000000 -; AVX512VLDQ-NEXT: jne LBB23_55 -; AVX512VLDQ-NEXT: LBB23_56: ## %else54 +; AVX512VLDQ-NEXT: jne LBB23_60 +; AVX512VLDQ-NEXT: LBB23_29: ## %else54 ; AVX512VLDQ-NEXT: testl $268435456, %eax ## imm = 0x10000000 -; AVX512VLDQ-NEXT: jne LBB23_57 -; AVX512VLDQ-NEXT: LBB23_58: ## %else56 +; AVX512VLDQ-NEXT: jne LBB23_61 +; AVX512VLDQ-NEXT: LBB23_30: ## %else56 ; AVX512VLDQ-NEXT: testl $536870912, %eax ## imm = 0x20000000 -; AVX512VLDQ-NEXT: jne LBB23_59 -; AVX512VLDQ-NEXT: LBB23_60: ## %else58 +; AVX512VLDQ-NEXT: jne LBB23_62 +; AVX512VLDQ-NEXT: LBB23_31: ## %else58 ; AVX512VLDQ-NEXT: testl $1073741824, %eax ## imm = 0x40000000 -; AVX512VLDQ-NEXT: jne LBB23_61 -; AVX512VLDQ-NEXT: LBB23_62: ## %else60 -; AVX512VLDQ-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 ; AVX512VLDQ-NEXT: jne LBB23_63 -; AVX512VLDQ-NEXT: LBB23_64: ## %else62 +; AVX512VLDQ-NEXT: LBB23_32: ## %else60 +; AVX512VLDQ-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 +; AVX512VLDQ-NEXT: jne LBB23_64 +; AVX512VLDQ-NEXT: LBB23_33: ## %else62 ; AVX512VLDQ-NEXT: vzeroupper ; AVX512VLDQ-NEXT: retq -; AVX512VLDQ-NEXT: LBB23_1: ## %cond.store +; AVX512VLDQ-NEXT: LBB23_34: ## %cond.store ; AVX512VLDQ-NEXT: vpextrb $0, %xmm1, (%rdi) ; AVX512VLDQ-NEXT: testb $2, %al -; AVX512VLDQ-NEXT: je LBB23_4 -; AVX512VLDQ-NEXT: LBB23_3: ## %cond.store1 +; AVX512VLDQ-NEXT: je LBB23_2 +; AVX512VLDQ-NEXT: LBB23_35: ## %cond.store1 ; AVX512VLDQ-NEXT: vpextrb $1, %xmm1, 1(%rdi) ; AVX512VLDQ-NEXT: testb $4, %al -; AVX512VLDQ-NEXT: je LBB23_6 -; AVX512VLDQ-NEXT: LBB23_5: ## %cond.store3 +; AVX512VLDQ-NEXT: je LBB23_3 +; AVX512VLDQ-NEXT: LBB23_36: ## %cond.store3 ; AVX512VLDQ-NEXT: vpextrb $2, %xmm1, 2(%rdi) ; AVX512VLDQ-NEXT: testb $8, %al -; AVX512VLDQ-NEXT: je LBB23_8 -; AVX512VLDQ-NEXT: LBB23_7: ## %cond.store5 +; AVX512VLDQ-NEXT: je LBB23_4 +; AVX512VLDQ-NEXT: LBB23_37: ## %cond.store5 ; AVX512VLDQ-NEXT: vpextrb $3, %xmm1, 3(%rdi) ; AVX512VLDQ-NEXT: testb $16, %al -; AVX512VLDQ-NEXT: je LBB23_10 -; AVX512VLDQ-NEXT: LBB23_9: ## %cond.store7 +; AVX512VLDQ-NEXT: je LBB23_5 +; AVX512VLDQ-NEXT: LBB23_38: ## %cond.store7 ; AVX512VLDQ-NEXT: vpextrb $4, %xmm1, 4(%rdi) ; AVX512VLDQ-NEXT: testb $32, %al -; AVX512VLDQ-NEXT: je LBB23_12 -; AVX512VLDQ-NEXT: LBB23_11: ## %cond.store9 +; AVX512VLDQ-NEXT: je LBB23_6 +; AVX512VLDQ-NEXT: LBB23_39: ## %cond.store9 ; AVX512VLDQ-NEXT: vpextrb $5, %xmm1, 5(%rdi) ; AVX512VLDQ-NEXT: testb $64, %al -; AVX512VLDQ-NEXT: je LBB23_14 -; AVX512VLDQ-NEXT: LBB23_13: ## %cond.store11 +; AVX512VLDQ-NEXT: je LBB23_7 +; AVX512VLDQ-NEXT: LBB23_40: ## %cond.store11 ; AVX512VLDQ-NEXT: vpextrb $6, %xmm1, 6(%rdi) ; AVX512VLDQ-NEXT: testb %al, %al -; AVX512VLDQ-NEXT: jns LBB23_16 -; AVX512VLDQ-NEXT: LBB23_15: ## %cond.store13 +; AVX512VLDQ-NEXT: jns LBB23_8 +; AVX512VLDQ-NEXT: LBB23_41: ## %cond.store13 ; AVX512VLDQ-NEXT: vpextrb $7, %xmm1, 7(%rdi) ; AVX512VLDQ-NEXT: testl $256, %eax ## imm = 0x100 -; AVX512VLDQ-NEXT: je LBB23_18 -; AVX512VLDQ-NEXT: LBB23_17: ## %cond.store15 +; AVX512VLDQ-NEXT: je LBB23_9 +; AVX512VLDQ-NEXT: LBB23_42: ## %cond.store15 ; AVX512VLDQ-NEXT: vpextrb $8, %xmm1, 8(%rdi) ; AVX512VLDQ-NEXT: testl $512, %eax ## imm = 0x200 -; AVX512VLDQ-NEXT: je LBB23_20 -; AVX512VLDQ-NEXT: LBB23_19: ## %cond.store17 +; AVX512VLDQ-NEXT: je LBB23_10 +; AVX512VLDQ-NEXT: LBB23_43: ## %cond.store17 ; AVX512VLDQ-NEXT: vpextrb $9, %xmm1, 9(%rdi) ; AVX512VLDQ-NEXT: testl $1024, %eax ## imm = 0x400 -; AVX512VLDQ-NEXT: je LBB23_22 -; AVX512VLDQ-NEXT: LBB23_21: ## %cond.store19 +; AVX512VLDQ-NEXT: je LBB23_11 +; AVX512VLDQ-NEXT: LBB23_44: ## %cond.store19 ; AVX512VLDQ-NEXT: vpextrb $10, %xmm1, 10(%rdi) ; AVX512VLDQ-NEXT: testl $2048, %eax ## imm = 0x800 -; AVX512VLDQ-NEXT: je LBB23_24 -; AVX512VLDQ-NEXT: LBB23_23: ## %cond.store21 +; AVX512VLDQ-NEXT: je LBB23_12 +; AVX512VLDQ-NEXT: LBB23_45: ## %cond.store21 ; AVX512VLDQ-NEXT: vpextrb $11, %xmm1, 11(%rdi) ; AVX512VLDQ-NEXT: testl $4096, %eax ## imm = 0x1000 -; AVX512VLDQ-NEXT: je LBB23_26 -; AVX512VLDQ-NEXT: LBB23_25: ## %cond.store23 +; AVX512VLDQ-NEXT: je LBB23_13 +; AVX512VLDQ-NEXT: LBB23_46: ## %cond.store23 ; AVX512VLDQ-NEXT: vpextrb $12, %xmm1, 12(%rdi) ; AVX512VLDQ-NEXT: testl $8192, %eax ## imm = 0x2000 -; AVX512VLDQ-NEXT: je LBB23_28 -; AVX512VLDQ-NEXT: LBB23_27: ## %cond.store25 +; AVX512VLDQ-NEXT: je LBB23_14 +; AVX512VLDQ-NEXT: LBB23_47: ## %cond.store25 ; AVX512VLDQ-NEXT: vpextrb $13, %xmm1, 13(%rdi) ; AVX512VLDQ-NEXT: testl $16384, %eax ## imm = 0x4000 -; AVX512VLDQ-NEXT: je LBB23_30 -; AVX512VLDQ-NEXT: LBB23_29: ## %cond.store27 +; AVX512VLDQ-NEXT: je LBB23_15 +; AVX512VLDQ-NEXT: LBB23_48: ## %cond.store27 ; AVX512VLDQ-NEXT: vpextrb $14, %xmm1, 14(%rdi) ; AVX512VLDQ-NEXT: testw %ax, %ax -; AVX512VLDQ-NEXT: js LBB23_31 -; AVX512VLDQ-NEXT: jmp LBB23_32 -; AVX512VLDQ-NEXT: LBB23_33: ## %cond.store31 +; AVX512VLDQ-NEXT: js LBB23_16 +; AVX512VLDQ-NEXT: jmp LBB23_17 +; AVX512VLDQ-NEXT: LBB23_49: ## %cond.store31 ; AVX512VLDQ-NEXT: vpextrb $0, %xmm0, 16(%rdi) ; AVX512VLDQ-NEXT: testl $131072, %eax ## imm = 0x20000 -; AVX512VLDQ-NEXT: je LBB23_36 -; AVX512VLDQ-NEXT: LBB23_35: ## %cond.store33 +; AVX512VLDQ-NEXT: je LBB23_19 +; AVX512VLDQ-NEXT: LBB23_50: ## %cond.store33 ; AVX512VLDQ-NEXT: vpextrb $1, %xmm0, 17(%rdi) ; AVX512VLDQ-NEXT: testl $262144, %eax ## imm = 0x40000 -; AVX512VLDQ-NEXT: je LBB23_38 -; AVX512VLDQ-NEXT: LBB23_37: ## %cond.store35 +; AVX512VLDQ-NEXT: je LBB23_20 +; AVX512VLDQ-NEXT: LBB23_51: ## %cond.store35 ; AVX512VLDQ-NEXT: vpextrb $2, %xmm0, 18(%rdi) ; AVX512VLDQ-NEXT: testl $524288, %eax ## imm = 0x80000 -; AVX512VLDQ-NEXT: je LBB23_40 -; AVX512VLDQ-NEXT: LBB23_39: ## %cond.store37 +; AVX512VLDQ-NEXT: je LBB23_21 +; AVX512VLDQ-NEXT: LBB23_52: ## %cond.store37 ; AVX512VLDQ-NEXT: vpextrb $3, %xmm0, 19(%rdi) ; AVX512VLDQ-NEXT: testl $1048576, %eax ## imm = 0x100000 -; AVX512VLDQ-NEXT: je LBB23_42 -; AVX512VLDQ-NEXT: LBB23_41: ## %cond.store39 +; AVX512VLDQ-NEXT: je LBB23_22 +; AVX512VLDQ-NEXT: LBB23_53: ## %cond.store39 ; AVX512VLDQ-NEXT: vpextrb $4, %xmm0, 20(%rdi) ; AVX512VLDQ-NEXT: testl $2097152, %eax ## imm = 0x200000 -; AVX512VLDQ-NEXT: je LBB23_44 -; AVX512VLDQ-NEXT: LBB23_43: ## %cond.store41 +; AVX512VLDQ-NEXT: je LBB23_23 +; AVX512VLDQ-NEXT: LBB23_54: ## %cond.store41 ; AVX512VLDQ-NEXT: vpextrb $5, %xmm0, 21(%rdi) ; AVX512VLDQ-NEXT: testl $4194304, %eax ## imm = 0x400000 -; AVX512VLDQ-NEXT: je LBB23_46 -; AVX512VLDQ-NEXT: LBB23_45: ## %cond.store43 +; AVX512VLDQ-NEXT: je LBB23_24 +; AVX512VLDQ-NEXT: LBB23_55: ## %cond.store43 ; AVX512VLDQ-NEXT: vpextrb $6, %xmm0, 22(%rdi) ; AVX512VLDQ-NEXT: testl $8388608, %eax ## imm = 0x800000 -; AVX512VLDQ-NEXT: je LBB23_48 -; AVX512VLDQ-NEXT: LBB23_47: ## %cond.store45 +; AVX512VLDQ-NEXT: je LBB23_25 +; AVX512VLDQ-NEXT: LBB23_56: ## %cond.store45 ; AVX512VLDQ-NEXT: vpextrb $7, %xmm0, 23(%rdi) ; AVX512VLDQ-NEXT: testl $16777216, %eax ## imm = 0x1000000 -; AVX512VLDQ-NEXT: je LBB23_50 -; AVX512VLDQ-NEXT: LBB23_49: ## %cond.store47 +; AVX512VLDQ-NEXT: je LBB23_26 +; AVX512VLDQ-NEXT: LBB23_57: ## %cond.store47 ; AVX512VLDQ-NEXT: vpextrb $8, %xmm0, 24(%rdi) ; AVX512VLDQ-NEXT: testl $33554432, %eax ## imm = 0x2000000 -; AVX512VLDQ-NEXT: je LBB23_52 -; AVX512VLDQ-NEXT: LBB23_51: ## %cond.store49 +; AVX512VLDQ-NEXT: je LBB23_27 +; AVX512VLDQ-NEXT: LBB23_58: ## %cond.store49 ; AVX512VLDQ-NEXT: vpextrb $9, %xmm0, 25(%rdi) ; AVX512VLDQ-NEXT: testl $67108864, %eax ## imm = 0x4000000 -; AVX512VLDQ-NEXT: je LBB23_54 -; AVX512VLDQ-NEXT: LBB23_53: ## %cond.store51 +; AVX512VLDQ-NEXT: je LBB23_28 +; AVX512VLDQ-NEXT: LBB23_59: ## %cond.store51 ; AVX512VLDQ-NEXT: vpextrb $10, %xmm0, 26(%rdi) ; AVX512VLDQ-NEXT: testl $134217728, %eax ## imm = 0x8000000 -; AVX512VLDQ-NEXT: je LBB23_56 -; AVX512VLDQ-NEXT: LBB23_55: ## %cond.store53 +; AVX512VLDQ-NEXT: je LBB23_29 +; AVX512VLDQ-NEXT: LBB23_60: ## %cond.store53 ; AVX512VLDQ-NEXT: vpextrb $11, %xmm0, 27(%rdi) ; AVX512VLDQ-NEXT: testl $268435456, %eax ## imm = 0x10000000 -; AVX512VLDQ-NEXT: je LBB23_58 -; AVX512VLDQ-NEXT: LBB23_57: ## %cond.store55 +; AVX512VLDQ-NEXT: je LBB23_30 +; AVX512VLDQ-NEXT: LBB23_61: ## %cond.store55 ; AVX512VLDQ-NEXT: vpextrb $12, %xmm0, 28(%rdi) ; AVX512VLDQ-NEXT: testl $536870912, %eax ## imm = 0x20000000 -; AVX512VLDQ-NEXT: je LBB23_60 -; AVX512VLDQ-NEXT: LBB23_59: ## %cond.store57 +; AVX512VLDQ-NEXT: je LBB23_31 +; AVX512VLDQ-NEXT: LBB23_62: ## %cond.store57 ; AVX512VLDQ-NEXT: vpextrb $13, %xmm0, 29(%rdi) ; AVX512VLDQ-NEXT: testl $1073741824, %eax ## imm = 0x40000000 -; AVX512VLDQ-NEXT: je LBB23_62 -; AVX512VLDQ-NEXT: LBB23_61: ## %cond.store59 +; AVX512VLDQ-NEXT: je LBB23_32 +; AVX512VLDQ-NEXT: LBB23_63: ## %cond.store59 ; AVX512VLDQ-NEXT: vpextrb $14, %xmm0, 30(%rdi) ; AVX512VLDQ-NEXT: testl $-2147483648, %eax ## imm = 0x80000000 -; AVX512VLDQ-NEXT: je LBB23_64 -; AVX512VLDQ-NEXT: LBB23_63: ## %cond.store61 +; AVX512VLDQ-NEXT: je LBB23_33 +; AVX512VLDQ-NEXT: LBB23_64: ## %cond.store61 ; AVX512VLDQ-NEXT: vpextrb $15, %xmm0, 31(%rdi) ; AVX512VLDQ-NEXT: vzeroupper ; AVX512VLDQ-NEXT: retq @@ -6135,31 +6135,31 @@ define void @masked_store_bool_mask_demand_trunc_sext(<4 x double> %x, ptr %p, < ; SSE-NEXT: pslld $31, %xmm2 ; SSE-NEXT: movmskps %xmm2, %eax ; SSE-NEXT: testb $1, %al -; SSE-NEXT: jne LBB33_1 -; SSE-NEXT: ## %bb.2: ## %else +; SSE-NEXT: jne LBB33_5 +; SSE-NEXT: ## %bb.1: ## %else ; SSE-NEXT: testb $2, %al -; SSE-NEXT: jne LBB33_3 -; SSE-NEXT: LBB33_4: ## %else2 +; SSE-NEXT: jne LBB33_6 +; SSE-NEXT: LBB33_2: ## %else2 ; SSE-NEXT: testb $4, %al -; SSE-NEXT: jne LBB33_5 -; SSE-NEXT: LBB33_6: ## %else4 -; SSE-NEXT: testb $8, %al ; SSE-NEXT: jne LBB33_7 -; SSE-NEXT: LBB33_8: ## %else6 +; SSE-NEXT: LBB33_3: ## %else4 +; SSE-NEXT: testb $8, %al +; SSE-NEXT: jne LBB33_8 +; SSE-NEXT: LBB33_4: ## %else6 ; SSE-NEXT: retq -; SSE-NEXT: LBB33_1: ## %cond.store +; SSE-NEXT: LBB33_5: ## %cond.store ; SSE-NEXT: movlps %xmm0, (%rdi) ; SSE-NEXT: testb $2, %al -; SSE-NEXT: je LBB33_4 -; SSE-NEXT: LBB33_3: ## %cond.store1 +; SSE-NEXT: je LBB33_2 +; SSE-NEXT: LBB33_6: ## %cond.store1 ; SSE-NEXT: movhps %xmm0, 8(%rdi) ; SSE-NEXT: testb $4, %al -; SSE-NEXT: je LBB33_6 -; SSE-NEXT: LBB33_5: ## %cond.store3 +; SSE-NEXT: je LBB33_3 +; SSE-NEXT: LBB33_7: ## %cond.store3 ; SSE-NEXT: movlps %xmm1, 16(%rdi) ; SSE-NEXT: testb $8, %al -; SSE-NEXT: je LBB33_8 -; SSE-NEXT: LBB33_7: ## %cond.store5 +; SSE-NEXT: je LBB33_4 +; SSE-NEXT: LBB33_8: ## %cond.store5 ; SSE-NEXT: movhps %xmm1, 24(%rdi) ; SSE-NEXT: retq ; @@ -6230,35 +6230,35 @@ define void @one_mask_bit_set1_variable(ptr %addr, <4 x float> %val, <4 x i32> % ; SSE2: ## %bb.0: ; SSE2-NEXT: movmskps %xmm1, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB34_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB34_5 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB34_3 -; SSE2-NEXT: LBB34_4: ## %else2 +; SSE2-NEXT: jne LBB34_6 +; SSE2-NEXT: LBB34_2: ## %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB34_5 -; SSE2-NEXT: LBB34_6: ## %else4 -; SSE2-NEXT: testb $8, %al ; SSE2-NEXT: jne LBB34_7 -; SSE2-NEXT: LBB34_8: ## %else6 +; SSE2-NEXT: LBB34_3: ## %else4 +; SSE2-NEXT: testb $8, %al +; SSE2-NEXT: jne LBB34_8 +; SSE2-NEXT: LBB34_4: ## %else6 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB34_1: ## %cond.store +; SSE2-NEXT: LBB34_5: ## %cond.store ; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB34_4 -; SSE2-NEXT: LBB34_3: ## %cond.store1 +; SSE2-NEXT: je LBB34_2 +; SSE2-NEXT: LBB34_6: ## %cond.store1 ; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1] ; SSE2-NEXT: movss %xmm1, 4(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB34_6 -; SSE2-NEXT: LBB34_5: ## %cond.store3 +; SSE2-NEXT: je LBB34_3 +; SSE2-NEXT: LBB34_7: ## %cond.store3 ; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: movss %xmm1, 8(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB34_8 -; SSE2-NEXT: LBB34_7: ## %cond.store5 +; SSE2-NEXT: je LBB34_4 +; SSE2-NEXT: LBB34_8: ## %cond.store5 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: movss %xmm0, 12(%rdi) ; SSE2-NEXT: retq @@ -6267,31 +6267,31 @@ define void @one_mask_bit_set1_variable(ptr %addr, <4 x float> %val, <4 x i32> % ; SSE4: ## %bb.0: ; SSE4-NEXT: movmskps %xmm1, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne LBB34_1 -; SSE4-NEXT: ## %bb.2: ## %else +; SSE4-NEXT: jne LBB34_5 +; SSE4-NEXT: ## %bb.1: ## %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne LBB34_3 -; SSE4-NEXT: LBB34_4: ## %else2 +; SSE4-NEXT: jne LBB34_6 +; SSE4-NEXT: LBB34_2: ## %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne LBB34_5 -; SSE4-NEXT: LBB34_6: ## %else4 -; SSE4-NEXT: testb $8, %al ; SSE4-NEXT: jne LBB34_7 -; SSE4-NEXT: LBB34_8: ## %else6 +; SSE4-NEXT: LBB34_3: ## %else4 +; SSE4-NEXT: testb $8, %al +; SSE4-NEXT: jne LBB34_8 +; SSE4-NEXT: LBB34_4: ## %else6 ; SSE4-NEXT: retq -; SSE4-NEXT: LBB34_1: ## %cond.store +; SSE4-NEXT: LBB34_5: ## %cond.store ; SSE4-NEXT: movss %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je LBB34_4 -; SSE4-NEXT: LBB34_3: ## %cond.store1 +; SSE4-NEXT: je LBB34_2 +; SSE4-NEXT: LBB34_6: ## %cond.store1 ; SSE4-NEXT: extractps $1, %xmm0, 4(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je LBB34_6 -; SSE4-NEXT: LBB34_5: ## %cond.store3 +; SSE4-NEXT: je LBB34_3 +; SSE4-NEXT: LBB34_7: ## %cond.store3 ; SSE4-NEXT: extractps $2, %xmm0, 8(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je LBB34_8 -; SSE4-NEXT: LBB34_7: ## %cond.store5 +; SSE4-NEXT: je LBB34_4 +; SSE4-NEXT: LBB34_8: ## %cond.store5 ; SSE4-NEXT: extractps $3, %xmm0, 12(%rdi) ; SSE4-NEXT: retq ; @@ -6343,25 +6343,25 @@ define void @widen_masked_store(<3 x i32> %v, ptr %p, <3 x i1> %mask) nounwind { ; SSE2-NEXT: shlb $2, %cl ; SSE2-NEXT: orb %dl, %cl ; SSE2-NEXT: testb $1, %cl -; SSE2-NEXT: jne LBB35_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB35_4 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %cl -; SSE2-NEXT: jne LBB35_3 -; SSE2-NEXT: LBB35_4: ## %else2 -; SSE2-NEXT: testb $4, %cl ; SSE2-NEXT: jne LBB35_5 -; SSE2-NEXT: LBB35_6: ## %else4 +; SSE2-NEXT: LBB35_2: ## %else2 +; SSE2-NEXT: testb $4, %cl +; SSE2-NEXT: jne LBB35_6 +; SSE2-NEXT: LBB35_3: ## %else4 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB35_1: ## %cond.store +; SSE2-NEXT: LBB35_4: ## %cond.store ; SSE2-NEXT: movd %xmm0, (%rdi) ; SSE2-NEXT: testb $2, %cl -; SSE2-NEXT: je LBB35_4 -; SSE2-NEXT: LBB35_3: ## %cond.store1 +; SSE2-NEXT: je LBB35_2 +; SSE2-NEXT: LBB35_5: ## %cond.store1 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1] ; SSE2-NEXT: movd %xmm1, 4(%rdi) ; SSE2-NEXT: testb $4, %cl -; SSE2-NEXT: je LBB35_6 -; SSE2-NEXT: LBB35_5: ## %cond.store3 +; SSE2-NEXT: je LBB35_3 +; SSE2-NEXT: LBB35_6: ## %cond.store3 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3] ; SSE2-NEXT: movd %xmm0, 8(%rdi) ; SSE2-NEXT: retq @@ -6376,24 +6376,24 @@ define void @widen_masked_store(<3 x i32> %v, ptr %p, <3 x i1> %mask) nounwind { ; SSE4-NEXT: shlb $2, %cl ; SSE4-NEXT: orb %dl, %cl ; SSE4-NEXT: testb $1, %cl -; SSE4-NEXT: jne LBB35_1 -; SSE4-NEXT: ## %bb.2: ## %else +; SSE4-NEXT: jne LBB35_4 +; SSE4-NEXT: ## %bb.1: ## %else ; SSE4-NEXT: testb $2, %cl -; SSE4-NEXT: jne LBB35_3 -; SSE4-NEXT: LBB35_4: ## %else2 -; SSE4-NEXT: testb $4, %cl ; SSE4-NEXT: jne LBB35_5 -; SSE4-NEXT: LBB35_6: ## %else4 +; SSE4-NEXT: LBB35_2: ## %else2 +; SSE4-NEXT: testb $4, %cl +; SSE4-NEXT: jne LBB35_6 +; SSE4-NEXT: LBB35_3: ## %else4 ; SSE4-NEXT: retq -; SSE4-NEXT: LBB35_1: ## %cond.store +; SSE4-NEXT: LBB35_4: ## %cond.store ; SSE4-NEXT: movss %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %cl -; SSE4-NEXT: je LBB35_4 -; SSE4-NEXT: LBB35_3: ## %cond.store1 +; SSE4-NEXT: je LBB35_2 +; SSE4-NEXT: LBB35_5: ## %cond.store1 ; SSE4-NEXT: extractps $1, %xmm0, 4(%rdi) ; SSE4-NEXT: testb $4, %cl -; SSE4-NEXT: je LBB35_6 -; SSE4-NEXT: LBB35_5: ## %cond.store3 +; SSE4-NEXT: je LBB35_3 +; SSE4-NEXT: LBB35_6: ## %cond.store3 ; SSE4-NEXT: extractps $2, %xmm0, 8(%rdi) ; SSE4-NEXT: retq ; @@ -6534,68 +6534,68 @@ define void @PR11210(<4 x float> %x, ptr %ptr, <4 x float> %y, <2 x i64> %mask) ; SSE2: ## %bb.0: ; SSE2-NEXT: movmskps %xmm2, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB37_1 -; SSE2-NEXT: ## %bb.2: ## %else +; SSE2-NEXT: jne LBB37_9 +; SSE2-NEXT: ## %bb.1: ## %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB37_3 -; SSE2-NEXT: LBB37_4: ## %else2 +; SSE2-NEXT: jne LBB37_10 +; SSE2-NEXT: LBB37_2: ## %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB37_5 -; SSE2-NEXT: LBB37_6: ## %else4 +; SSE2-NEXT: jne LBB37_11 +; SSE2-NEXT: LBB37_3: ## %else4 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne LBB37_7 -; SSE2-NEXT: LBB37_8: ## %else6 +; SSE2-NEXT: jne LBB37_12 +; SSE2-NEXT: LBB37_4: ## %else6 ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB37_9 -; SSE2-NEXT: LBB37_10: ## %else9 +; SSE2-NEXT: jne LBB37_13 +; SSE2-NEXT: LBB37_5: ## %else9 ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB37_11 -; SSE2-NEXT: LBB37_12: ## %else11 +; SSE2-NEXT: jne LBB37_14 +; SSE2-NEXT: LBB37_6: ## %else11 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB37_13 -; SSE2-NEXT: LBB37_14: ## %else13 -; SSE2-NEXT: testb $8, %al ; SSE2-NEXT: jne LBB37_15 -; SSE2-NEXT: LBB37_16: ## %else15 +; SSE2-NEXT: LBB37_7: ## %else13 +; SSE2-NEXT: testb $8, %al +; SSE2-NEXT: jne LBB37_16 +; SSE2-NEXT: LBB37_8: ## %else15 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB37_1: ## %cond.store +; SSE2-NEXT: LBB37_9: ## %cond.store ; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB37_4 -; SSE2-NEXT: LBB37_3: ## %cond.store1 +; SSE2-NEXT: je LBB37_2 +; SSE2-NEXT: LBB37_10: ## %cond.store1 ; SSE2-NEXT: movaps %xmm0, %xmm2 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm0[1,1] ; SSE2-NEXT: movss %xmm2, 4(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB37_6 -; SSE2-NEXT: LBB37_5: ## %cond.store3 +; SSE2-NEXT: je LBB37_3 +; SSE2-NEXT: LBB37_11: ## %cond.store3 ; SSE2-NEXT: movaps %xmm0, %xmm2 ; SSE2-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1] ; SSE2-NEXT: movss %xmm2, 8(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB37_8 -; SSE2-NEXT: LBB37_7: ## %cond.store5 +; SSE2-NEXT: je LBB37_4 +; SSE2-NEXT: LBB37_12: ## %cond.store5 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: movss %xmm0, 12(%rdi) ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: je LBB37_10 -; SSE2-NEXT: LBB37_9: ## %cond.store8 +; SSE2-NEXT: je LBB37_5 +; SSE2-NEXT: LBB37_13: ## %cond.store8 ; SSE2-NEXT: movss %xmm1, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB37_12 -; SSE2-NEXT: LBB37_11: ## %cond.store10 +; SSE2-NEXT: je LBB37_6 +; SSE2-NEXT: LBB37_14: ## %cond.store10 ; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1] ; SSE2-NEXT: movss %xmm0, 4(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB37_14 -; SSE2-NEXT: LBB37_13: ## %cond.store12 +; SSE2-NEXT: je LBB37_7 +; SSE2-NEXT: LBB37_15: ## %cond.store12 ; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1] ; SSE2-NEXT: movss %xmm0, 8(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB37_16 -; SSE2-NEXT: LBB37_15: ## %cond.store14 +; SSE2-NEXT: je LBB37_8 +; SSE2-NEXT: LBB37_16: ## %cond.store14 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3,3,3] ; SSE2-NEXT: movss %xmm1, 12(%rdi) ; SSE2-NEXT: retq @@ -6604,59 +6604,59 @@ define void @PR11210(<4 x float> %x, ptr %ptr, <4 x float> %y, <2 x i64> %mask) ; SSE4: ## %bb.0: ; SSE4-NEXT: movmskps %xmm2, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne LBB37_1 -; SSE4-NEXT: ## %bb.2: ## %else +; SSE4-NEXT: jne LBB37_9 +; SSE4-NEXT: ## %bb.1: ## %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne LBB37_3 -; SSE4-NEXT: LBB37_4: ## %else2 +; SSE4-NEXT: jne LBB37_10 +; SSE4-NEXT: LBB37_2: ## %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne LBB37_5 -; SSE4-NEXT: LBB37_6: ## %else4 +; SSE4-NEXT: jne LBB37_11 +; SSE4-NEXT: LBB37_3: ## %else4 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne LBB37_7 -; SSE4-NEXT: LBB37_8: ## %else6 +; SSE4-NEXT: jne LBB37_12 +; SSE4-NEXT: LBB37_4: ## %else6 ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne LBB37_9 -; SSE4-NEXT: LBB37_10: ## %else9 +; SSE4-NEXT: jne LBB37_13 +; SSE4-NEXT: LBB37_5: ## %else9 ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne LBB37_11 -; SSE4-NEXT: LBB37_12: ## %else11 +; SSE4-NEXT: jne LBB37_14 +; SSE4-NEXT: LBB37_6: ## %else11 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne LBB37_13 -; SSE4-NEXT: LBB37_14: ## %else13 -; SSE4-NEXT: testb $8, %al ; SSE4-NEXT: jne LBB37_15 -; SSE4-NEXT: LBB37_16: ## %else15 +; SSE4-NEXT: LBB37_7: ## %else13 +; SSE4-NEXT: testb $8, %al +; SSE4-NEXT: jne LBB37_16 +; SSE4-NEXT: LBB37_8: ## %else15 ; SSE4-NEXT: retq -; SSE4-NEXT: LBB37_1: ## %cond.store +; SSE4-NEXT: LBB37_9: ## %cond.store ; SSE4-NEXT: movss %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je LBB37_4 -; SSE4-NEXT: LBB37_3: ## %cond.store1 +; SSE4-NEXT: je LBB37_2 +; SSE4-NEXT: LBB37_10: ## %cond.store1 ; SSE4-NEXT: extractps $1, %xmm0, 4(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je LBB37_6 -; SSE4-NEXT: LBB37_5: ## %cond.store3 +; SSE4-NEXT: je LBB37_3 +; SSE4-NEXT: LBB37_11: ## %cond.store3 ; SSE4-NEXT: extractps $2, %xmm0, 8(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je LBB37_8 -; SSE4-NEXT: LBB37_7: ## %cond.store5 +; SSE4-NEXT: je LBB37_4 +; SSE4-NEXT: LBB37_12: ## %cond.store5 ; SSE4-NEXT: extractps $3, %xmm0, 12(%rdi) ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: je LBB37_10 -; SSE4-NEXT: LBB37_9: ## %cond.store8 +; SSE4-NEXT: je LBB37_5 +; SSE4-NEXT: LBB37_13: ## %cond.store8 ; SSE4-NEXT: movss %xmm1, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je LBB37_12 -; SSE4-NEXT: LBB37_11: ## %cond.store10 +; SSE4-NEXT: je LBB37_6 +; SSE4-NEXT: LBB37_14: ## %cond.store10 ; SSE4-NEXT: extractps $1, %xmm1, 4(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je LBB37_14 -; SSE4-NEXT: LBB37_13: ## %cond.store12 +; SSE4-NEXT: je LBB37_7 +; SSE4-NEXT: LBB37_15: ## %cond.store12 ; SSE4-NEXT: extractps $2, %xmm1, 8(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je LBB37_16 -; SSE4-NEXT: LBB37_15: ## %cond.store14 +; SSE4-NEXT: je LBB37_8 +; SSE4-NEXT: LBB37_16: ## %cond.store14 ; SSE4-NEXT: extractps $3, %xmm1, 12(%rdi) ; SSE4-NEXT: retq ; @@ -6761,84 +6761,84 @@ define void @store_v24i32_v24i32_stride6_vf4_only_even_numbered_elts(ptr %trigge ; SSE-NEXT: movl 12(%rsi), %r14d ; SSE-NEXT: movl 8(%rsi), %r15d ; SSE-NEXT: movl 4(%rsi), %r12d -; SSE-NEXT: jne LBB38_1 -; SSE-NEXT: ## %bb.2: ## %else +; SSE-NEXT: jne LBB38_27 +; SSE-NEXT: ## %bb.1: ## %else ; SSE-NEXT: testb $2, %dil -; SSE-NEXT: jne LBB38_3 -; SSE-NEXT: LBB38_4: ## %else2 +; SSE-NEXT: jne LBB38_28 +; SSE-NEXT: LBB38_2: ## %else2 ; SSE-NEXT: testb $4, %dil -; SSE-NEXT: jne LBB38_5 -; SSE-NEXT: LBB38_6: ## %else4 +; SSE-NEXT: jne LBB38_29 +; SSE-NEXT: LBB38_3: ## %else4 ; SSE-NEXT: testb $8, %dil -; SSE-NEXT: jne LBB38_7 -; SSE-NEXT: LBB38_8: ## %else6 +; SSE-NEXT: jne LBB38_30 +; SSE-NEXT: LBB38_4: ## %else6 ; SSE-NEXT: testb $16, %dil -; SSE-NEXT: jne LBB38_9 -; SSE-NEXT: LBB38_10: ## %else8 +; SSE-NEXT: jne LBB38_31 +; SSE-NEXT: LBB38_5: ## %else8 ; SSE-NEXT: testb $32, %dil -; SSE-NEXT: jne LBB38_11 -; SSE-NEXT: LBB38_12: ## %else10 +; SSE-NEXT: jne LBB38_32 +; SSE-NEXT: LBB38_6: ## %else10 ; SSE-NEXT: testb $64, %dil -; SSE-NEXT: jne LBB38_13 -; SSE-NEXT: LBB38_14: ## %else12 +; SSE-NEXT: jne LBB38_33 +; SSE-NEXT: LBB38_7: ## %else12 ; SSE-NEXT: testb %dil, %dil -; SSE-NEXT: js LBB38_15 -; SSE-NEXT: LBB38_16: ## %else14 +; SSE-NEXT: js LBB38_34 +; SSE-NEXT: LBB38_8: ## %else14 ; SSE-NEXT: testl $256, %edi ## imm = 0x100 -; SSE-NEXT: jne LBB38_17 -; SSE-NEXT: LBB38_18: ## %else16 +; SSE-NEXT: jne LBB38_35 +; SSE-NEXT: LBB38_9: ## %else16 ; SSE-NEXT: testl $512, %edi ## imm = 0x200 -; SSE-NEXT: jne LBB38_19 -; SSE-NEXT: LBB38_20: ## %else18 +; SSE-NEXT: jne LBB38_36 +; SSE-NEXT: LBB38_10: ## %else18 ; SSE-NEXT: testl $1024, %edi ## imm = 0x400 -; SSE-NEXT: jne LBB38_21 -; SSE-NEXT: LBB38_22: ## %else20 +; SSE-NEXT: jne LBB38_37 +; SSE-NEXT: LBB38_11: ## %else20 ; SSE-NEXT: testl $2048, %edi ## imm = 0x800 -; SSE-NEXT: jne LBB38_23 -; SSE-NEXT: LBB38_24: ## %else22 +; SSE-NEXT: jne LBB38_38 +; SSE-NEXT: LBB38_12: ## %else22 ; SSE-NEXT: testl $4096, %edi ## imm = 0x1000 -; SSE-NEXT: jne LBB38_25 -; SSE-NEXT: LBB38_26: ## %else24 +; SSE-NEXT: jne LBB38_39 +; SSE-NEXT: LBB38_13: ## %else24 ; SSE-NEXT: testl $8192, %edi ## imm = 0x2000 -; SSE-NEXT: jne LBB38_27 -; SSE-NEXT: LBB38_28: ## %else26 +; SSE-NEXT: jne LBB38_40 +; SSE-NEXT: LBB38_14: ## %else26 ; SSE-NEXT: testl $16384, %edi ## imm = 0x4000 -; SSE-NEXT: jne LBB38_29 -; SSE-NEXT: LBB38_30: ## %else28 +; SSE-NEXT: jne LBB38_41 +; SSE-NEXT: LBB38_15: ## %else28 ; SSE-NEXT: testw %di, %di -; SSE-NEXT: js LBB38_31 -; SSE-NEXT: LBB38_32: ## %else30 +; SSE-NEXT: js LBB38_42 +; SSE-NEXT: LBB38_16: ## %else30 ; SSE-NEXT: testl $65536, %edi ## imm = 0x10000 -; SSE-NEXT: jne LBB38_33 -; SSE-NEXT: LBB38_34: ## %else32 +; SSE-NEXT: jne LBB38_43 +; SSE-NEXT: LBB38_17: ## %else32 ; SSE-NEXT: testl $131072, %edi ## imm = 0x20000 -; SSE-NEXT: jne LBB38_35 -; SSE-NEXT: LBB38_36: ## %else34 +; SSE-NEXT: jne LBB38_44 +; SSE-NEXT: LBB38_18: ## %else34 ; SSE-NEXT: testl $262144, %edi ## imm = 0x40000 -; SSE-NEXT: jne LBB38_37 -; SSE-NEXT: LBB38_38: ## %else36 +; SSE-NEXT: jne LBB38_45 +; SSE-NEXT: LBB38_19: ## %else36 ; SSE-NEXT: testl $524288, %edi ## imm = 0x80000 -; SSE-NEXT: jne LBB38_39 -; SSE-NEXT: LBB38_40: ## %else38 +; SSE-NEXT: jne LBB38_46 +; SSE-NEXT: LBB38_20: ## %else38 ; SSE-NEXT: testl $1048576, %edi ## imm = 0x100000 -; SSE-NEXT: jne LBB38_41 -; SSE-NEXT: LBB38_42: ## %else40 +; SSE-NEXT: jne LBB38_47 +; SSE-NEXT: LBB38_21: ## %else40 ; SSE-NEXT: testl $2097152, %edi ## imm = 0x200000 -; SSE-NEXT: jne LBB38_43 -; SSE-NEXT: LBB38_44: ## %else42 +; SSE-NEXT: jne LBB38_48 +; SSE-NEXT: LBB38_22: ## %else42 ; SSE-NEXT: testl $4194304, %edi ## imm = 0x400000 -; SSE-NEXT: je LBB38_46 -; SSE-NEXT: LBB38_45: ## %cond.store43 +; SSE-NEXT: je LBB38_24 +; SSE-NEXT: LBB38_23: ## %cond.store43 ; SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax ## 4-byte Reload ; SSE-NEXT: movl %eax, 88(%rdx) -; SSE-NEXT: LBB38_46: ## %else44 +; SSE-NEXT: LBB38_24: ## %else44 ; SSE-NEXT: movb $1, %al ; SSE-NEXT: testb %al, %al -; SSE-NEXT: jne LBB38_48 -; SSE-NEXT: ## %bb.47: ## %cond.store45 +; SSE-NEXT: jne LBB38_26 +; SSE-NEXT: ## %bb.25: ## %cond.store45 ; SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax ## 4-byte Reload ; SSE-NEXT: movl %eax, 92(%rdx) -; SSE-NEXT: LBB38_48: ## %else46 +; SSE-NEXT: LBB38_26: ## %else46 ; SSE-NEXT: popq %rbx ; SSE-NEXT: popq %r12 ; SSE-NEXT: popq %r13 @@ -6846,105 +6846,105 @@ define void @store_v24i32_v24i32_stride6_vf4_only_even_numbered_elts(ptr %trigge ; SSE-NEXT: popq %r15 ; SSE-NEXT: popq %rbp ; SSE-NEXT: retq -; SSE-NEXT: LBB38_1: ## %cond.store +; SSE-NEXT: LBB38_27: ## %cond.store ; SSE-NEXT: movl (%rsi), %esi ; SSE-NEXT: movl %esi, (%rdx) ; SSE-NEXT: testb $2, %dil -; SSE-NEXT: je LBB38_4 -; SSE-NEXT: LBB38_3: ## %cond.store1 +; SSE-NEXT: je LBB38_2 +; SSE-NEXT: LBB38_28: ## %cond.store1 ; SSE-NEXT: movl %r12d, 4(%rdx) ; SSE-NEXT: testb $4, %dil -; SSE-NEXT: je LBB38_6 -; SSE-NEXT: LBB38_5: ## %cond.store3 +; SSE-NEXT: je LBB38_3 +; SSE-NEXT: LBB38_29: ## %cond.store3 ; SSE-NEXT: movl %r15d, 8(%rdx) ; SSE-NEXT: testb $8, %dil -; SSE-NEXT: je LBB38_8 -; SSE-NEXT: LBB38_7: ## %cond.store5 +; SSE-NEXT: je LBB38_4 +; SSE-NEXT: LBB38_30: ## %cond.store5 ; SSE-NEXT: movl %r14d, 12(%rdx) ; SSE-NEXT: testb $16, %dil -; SSE-NEXT: je LBB38_10 -; SSE-NEXT: LBB38_9: ## %cond.store7 +; SSE-NEXT: je LBB38_5 +; SSE-NEXT: LBB38_31: ## %cond.store7 ; SSE-NEXT: movl %ebp, 16(%rdx) ; SSE-NEXT: testb $32, %dil -; SSE-NEXT: je LBB38_12 -; SSE-NEXT: LBB38_11: ## %cond.store9 +; SSE-NEXT: je LBB38_6 +; SSE-NEXT: LBB38_32: ## %cond.store9 ; SSE-NEXT: movl %ebx, 20(%rdx) ; SSE-NEXT: testb $64, %dil -; SSE-NEXT: je LBB38_14 -; SSE-NEXT: LBB38_13: ## %cond.store11 +; SSE-NEXT: je LBB38_7 +; SSE-NEXT: LBB38_33: ## %cond.store11 ; SSE-NEXT: movl %r11d, 24(%rdx) ; SSE-NEXT: testb %dil, %dil -; SSE-NEXT: jns LBB38_16 -; SSE-NEXT: LBB38_15: ## %cond.store13 +; SSE-NEXT: jns LBB38_8 +; SSE-NEXT: LBB38_34: ## %cond.store13 ; SSE-NEXT: movl %r10d, 28(%rdx) ; SSE-NEXT: testl $256, %edi ## imm = 0x100 -; SSE-NEXT: je LBB38_18 -; SSE-NEXT: LBB38_17: ## %cond.store15 +; SSE-NEXT: je LBB38_9 +; SSE-NEXT: LBB38_35: ## %cond.store15 ; SSE-NEXT: movl %r9d, 32(%rdx) ; SSE-NEXT: testl $512, %edi ## imm = 0x200 -; SSE-NEXT: je LBB38_20 -; SSE-NEXT: LBB38_19: ## %cond.store17 +; SSE-NEXT: je LBB38_10 +; SSE-NEXT: LBB38_36: ## %cond.store17 ; SSE-NEXT: movl %r8d, 36(%rdx) ; SSE-NEXT: testl $1024, %edi ## imm = 0x400 -; SSE-NEXT: je LBB38_22 -; SSE-NEXT: LBB38_21: ## %cond.store19 +; SSE-NEXT: je LBB38_11 +; SSE-NEXT: LBB38_37: ## %cond.store19 ; SSE-NEXT: movl %ecx, 40(%rdx) ; SSE-NEXT: testl $2048, %edi ## imm = 0x800 -; SSE-NEXT: je LBB38_24 -; SSE-NEXT: LBB38_23: ## %cond.store21 +; SSE-NEXT: je LBB38_12 +; SSE-NEXT: LBB38_38: ## %cond.store21 ; SSE-NEXT: movl %eax, 44(%rdx) ; SSE-NEXT: testl $4096, %edi ## imm = 0x1000 -; SSE-NEXT: je LBB38_26 -; SSE-NEXT: LBB38_25: ## %cond.store23 +; SSE-NEXT: je LBB38_13 +; SSE-NEXT: LBB38_39: ## %cond.store23 ; SSE-NEXT: movl %r13d, 48(%rdx) ; SSE-NEXT: testl $8192, %edi ## imm = 0x2000 -; SSE-NEXT: je LBB38_28 -; SSE-NEXT: LBB38_27: ## %cond.store25 +; SSE-NEXT: je LBB38_14 +; SSE-NEXT: LBB38_40: ## %cond.store25 ; SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax ## 4-byte Reload ; SSE-NEXT: movl %eax, 52(%rdx) ; SSE-NEXT: testl $16384, %edi ## imm = 0x4000 -; SSE-NEXT: je LBB38_30 -; SSE-NEXT: LBB38_29: ## %cond.store27 +; SSE-NEXT: je LBB38_15 +; SSE-NEXT: LBB38_41: ## %cond.store27 ; SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax ## 4-byte Reload ; SSE-NEXT: movl %eax, 56(%rdx) ; SSE-NEXT: testw %di, %di -; SSE-NEXT: jns LBB38_32 -; SSE-NEXT: LBB38_31: ## %cond.store29 +; SSE-NEXT: jns LBB38_16 +; SSE-NEXT: LBB38_42: ## %cond.store29 ; SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax ## 4-byte Reload ; SSE-NEXT: movl %eax, 60(%rdx) ; SSE-NEXT: testl $65536, %edi ## imm = 0x10000 -; SSE-NEXT: je LBB38_34 -; SSE-NEXT: LBB38_33: ## %cond.store31 +; SSE-NEXT: je LBB38_17 +; SSE-NEXT: LBB38_43: ## %cond.store31 ; SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax ## 4-byte Reload ; SSE-NEXT: movl %eax, 64(%rdx) ; SSE-NEXT: testl $131072, %edi ## imm = 0x20000 -; SSE-NEXT: je LBB38_36 -; SSE-NEXT: LBB38_35: ## %cond.store33 +; SSE-NEXT: je LBB38_18 +; SSE-NEXT: LBB38_44: ## %cond.store33 ; SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax ## 4-byte Reload ; SSE-NEXT: movl %eax, 68(%rdx) ; SSE-NEXT: testl $262144, %edi ## imm = 0x40000 -; SSE-NEXT: je LBB38_38 -; SSE-NEXT: LBB38_37: ## %cond.store35 +; SSE-NEXT: je LBB38_19 +; SSE-NEXT: LBB38_45: ## %cond.store35 ; SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax ## 4-byte Reload ; SSE-NEXT: movl %eax, 72(%rdx) ; SSE-NEXT: testl $524288, %edi ## imm = 0x80000 -; SSE-NEXT: je LBB38_40 -; SSE-NEXT: LBB38_39: ## %cond.store37 +; SSE-NEXT: je LBB38_20 +; SSE-NEXT: LBB38_46: ## %cond.store37 ; SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax ## 4-byte Reload ; SSE-NEXT: movl %eax, 76(%rdx) ; SSE-NEXT: testl $1048576, %edi ## imm = 0x100000 -; SSE-NEXT: je LBB38_42 -; SSE-NEXT: LBB38_41: ## %cond.store39 +; SSE-NEXT: je LBB38_21 +; SSE-NEXT: LBB38_47: ## %cond.store39 ; SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax ## 4-byte Reload ; SSE-NEXT: movl %eax, 80(%rdx) ; SSE-NEXT: testl $2097152, %edi ## imm = 0x200000 -; SSE-NEXT: je LBB38_44 -; SSE-NEXT: LBB38_43: ## %cond.store41 +; SSE-NEXT: je LBB38_22 +; SSE-NEXT: LBB38_48: ## %cond.store41 ; SSE-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax ## 4-byte Reload ; SSE-NEXT: movl %eax, 84(%rdx) ; SSE-NEXT: testl $4194304, %edi ## imm = 0x400000 -; SSE-NEXT: jne LBB38_45 -; SSE-NEXT: jmp LBB38_46 +; SSE-NEXT: jne LBB38_23 +; SSE-NEXT: jmp LBB38_24 ; ; AVX1-LABEL: store_v24i32_v24i32_stride6_vf4_only_even_numbered_elts: ; AVX1: ## %bb.0: @@ -7105,59 +7105,59 @@ define void @undefshuffle(<8 x i1> %i0, ptr %src, ptr %dst) nounwind { ; SSE2-NEXT: packsswb %xmm0, %xmm0 ; SSE2-NEXT: pmovmskb %xmm0, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne LBB39_1 -; SSE2-NEXT: ## %bb.2: ## %else23 +; SSE2-NEXT: jne LBB39_9 +; SSE2-NEXT: ## %bb.1: ## %else23 ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne LBB39_3 -; SSE2-NEXT: LBB39_4: ## %else25 +; SSE2-NEXT: jne LBB39_10 +; SSE2-NEXT: LBB39_2: ## %else25 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne LBB39_5 -; SSE2-NEXT: LBB39_6: ## %else27 +; SSE2-NEXT: jne LBB39_11 +; SSE2-NEXT: LBB39_3: ## %else27 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne LBB39_7 -; SSE2-NEXT: LBB39_8: ## %else29 +; SSE2-NEXT: jne LBB39_12 +; SSE2-NEXT: LBB39_4: ## %else29 ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: jne LBB39_9 -; SSE2-NEXT: LBB39_10: ## %else31 +; SSE2-NEXT: jne LBB39_13 +; SSE2-NEXT: LBB39_5: ## %else31 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: jne LBB39_11 -; SSE2-NEXT: LBB39_12: ## %else33 +; SSE2-NEXT: jne LBB39_14 +; SSE2-NEXT: LBB39_6: ## %else33 ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: jne LBB39_13 -; SSE2-NEXT: LBB39_14: ## %else35 -; SSE2-NEXT: testb $-128, %al ; SSE2-NEXT: jne LBB39_15 -; SSE2-NEXT: LBB39_16: ## %else37 +; SSE2-NEXT: LBB39_7: ## %else35 +; SSE2-NEXT: testb $-128, %al +; SSE2-NEXT: jne LBB39_16 +; SSE2-NEXT: LBB39_8: ## %else37 ; SSE2-NEXT: retq -; SSE2-NEXT: LBB39_1: ## %cond.store +; SSE2-NEXT: LBB39_9: ## %cond.store ; SSE2-NEXT: movl $0, (%rsi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je LBB39_4 -; SSE2-NEXT: LBB39_3: ## %cond.store24 +; SSE2-NEXT: je LBB39_2 +; SSE2-NEXT: LBB39_10: ## %cond.store24 ; SSE2-NEXT: movl $0, 4(%rsi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je LBB39_6 -; SSE2-NEXT: LBB39_5: ## %cond.store26 +; SSE2-NEXT: je LBB39_3 +; SSE2-NEXT: LBB39_11: ## %cond.store26 ; SSE2-NEXT: movl $0, 8(%rsi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je LBB39_8 -; SSE2-NEXT: LBB39_7: ## %cond.store28 +; SSE2-NEXT: je LBB39_4 +; SSE2-NEXT: LBB39_12: ## %cond.store28 ; SSE2-NEXT: movl $0, 12(%rsi) ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: je LBB39_10 -; SSE2-NEXT: LBB39_9: ## %cond.store30 +; SSE2-NEXT: je LBB39_5 +; SSE2-NEXT: LBB39_13: ## %cond.store30 ; SSE2-NEXT: movl $0, 16(%rsi) ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je LBB39_12 -; SSE2-NEXT: LBB39_11: ## %cond.store32 +; SSE2-NEXT: je LBB39_6 +; SSE2-NEXT: LBB39_14: ## %cond.store32 ; SSE2-NEXT: movl $0, 20(%rsi) ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: je LBB39_14 -; SSE2-NEXT: LBB39_13: ## %cond.store34 +; SSE2-NEXT: je LBB39_7 +; SSE2-NEXT: LBB39_15: ## %cond.store34 ; SSE2-NEXT: movl $0, 24(%rsi) ; SSE2-NEXT: testb $-128, %al -; SSE2-NEXT: je LBB39_16 -; SSE2-NEXT: LBB39_15: ## %cond.store36 +; SSE2-NEXT: je LBB39_8 +; SSE2-NEXT: LBB39_16: ## %cond.store36 ; SSE2-NEXT: movl $0, 28(%rsi) ; SSE2-NEXT: retq ; @@ -7168,59 +7168,59 @@ define void @undefshuffle(<8 x i1> %i0, ptr %src, ptr %dst) nounwind { ; SSE4-NEXT: packsswb %xmm0, %xmm0 ; SSE4-NEXT: pmovmskb %xmm0, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne LBB39_1 -; SSE4-NEXT: ## %bb.2: ## %else23 +; SSE4-NEXT: jne LBB39_9 +; SSE4-NEXT: ## %bb.1: ## %else23 ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne LBB39_3 -; SSE4-NEXT: LBB39_4: ## %else25 +; SSE4-NEXT: jne LBB39_10 +; SSE4-NEXT: LBB39_2: ## %else25 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne LBB39_5 -; SSE4-NEXT: LBB39_6: ## %else27 +; SSE4-NEXT: jne LBB39_11 +; SSE4-NEXT: LBB39_3: ## %else27 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne LBB39_7 -; SSE4-NEXT: LBB39_8: ## %else29 +; SSE4-NEXT: jne LBB39_12 +; SSE4-NEXT: LBB39_4: ## %else29 ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: jne LBB39_9 -; SSE4-NEXT: LBB39_10: ## %else31 +; SSE4-NEXT: jne LBB39_13 +; SSE4-NEXT: LBB39_5: ## %else31 ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: jne LBB39_11 -; SSE4-NEXT: LBB39_12: ## %else33 +; SSE4-NEXT: jne LBB39_14 +; SSE4-NEXT: LBB39_6: ## %else33 ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: jne LBB39_13 -; SSE4-NEXT: LBB39_14: ## %else35 -; SSE4-NEXT: testb $-128, %al ; SSE4-NEXT: jne LBB39_15 -; SSE4-NEXT: LBB39_16: ## %else37 +; SSE4-NEXT: LBB39_7: ## %else35 +; SSE4-NEXT: testb $-128, %al +; SSE4-NEXT: jne LBB39_16 +; SSE4-NEXT: LBB39_8: ## %else37 ; SSE4-NEXT: retq -; SSE4-NEXT: LBB39_1: ## %cond.store +; SSE4-NEXT: LBB39_9: ## %cond.store ; SSE4-NEXT: movl $0, (%rsi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je LBB39_4 -; SSE4-NEXT: LBB39_3: ## %cond.store24 +; SSE4-NEXT: je LBB39_2 +; SSE4-NEXT: LBB39_10: ## %cond.store24 ; SSE4-NEXT: movl $0, 4(%rsi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je LBB39_6 -; SSE4-NEXT: LBB39_5: ## %cond.store26 +; SSE4-NEXT: je LBB39_3 +; SSE4-NEXT: LBB39_11: ## %cond.store26 ; SSE4-NEXT: movl $0, 8(%rsi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je LBB39_8 -; SSE4-NEXT: LBB39_7: ## %cond.store28 +; SSE4-NEXT: je LBB39_4 +; SSE4-NEXT: LBB39_12: ## %cond.store28 ; SSE4-NEXT: movl $0, 12(%rsi) ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: je LBB39_10 -; SSE4-NEXT: LBB39_9: ## %cond.store30 +; SSE4-NEXT: je LBB39_5 +; SSE4-NEXT: LBB39_13: ## %cond.store30 ; SSE4-NEXT: movl $0, 16(%rsi) ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: je LBB39_12 -; SSE4-NEXT: LBB39_11: ## %cond.store32 +; SSE4-NEXT: je LBB39_6 +; SSE4-NEXT: LBB39_14: ## %cond.store32 ; SSE4-NEXT: movl $0, 20(%rsi) ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: je LBB39_14 -; SSE4-NEXT: LBB39_13: ## %cond.store34 +; SSE4-NEXT: je LBB39_7 +; SSE4-NEXT: LBB39_15: ## %cond.store34 ; SSE4-NEXT: movl $0, 24(%rsi) ; SSE4-NEXT: testb $-128, %al -; SSE4-NEXT: je LBB39_16 -; SSE4-NEXT: LBB39_15: ## %cond.store36 +; SSE4-NEXT: je LBB39_8 +; SSE4-NEXT: LBB39_16: ## %cond.store36 ; SSE4-NEXT: movl $0, 28(%rsi) ; SSE4-NEXT: retq ; diff --git a/llvm/test/CodeGen/X86/masked_store_trunc.ll b/llvm/test/CodeGen/X86/masked_store_trunc.ll index ecf4fbb603a8f..d5744bb58b4b8 100644 --- a/llvm/test/CodeGen/X86/masked_store_trunc.ll +++ b/llvm/test/CodeGen/X86/masked_store_trunc.ll @@ -20,64 +20,64 @@ define void @truncstore_v8i64_v8i32(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; SSE2-NEXT: pmovmskb %xmm4, %eax ; SSE2-NEXT: notl %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne .LBB0_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB0_10 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne .LBB0_3 -; SSE2-NEXT: .LBB0_4: # %else2 +; SSE2-NEXT: jne .LBB0_11 +; SSE2-NEXT: .LBB0_2: # %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne .LBB0_5 -; SSE2-NEXT: .LBB0_6: # %else4 +; SSE2-NEXT: jne .LBB0_12 +; SSE2-NEXT: .LBB0_3: # %else4 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je .LBB0_8 -; SSE2-NEXT: .LBB0_7: # %cond.store5 +; SSE2-NEXT: je .LBB0_5 +; SSE2-NEXT: .LBB0_4: # %cond.store5 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: movd %xmm0, 12(%rdi) -; SSE2-NEXT: .LBB0_8: # %else6 +; SSE2-NEXT: .LBB0_5: # %else6 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm3[0,2] ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: jne .LBB0_9 -; SSE2-NEXT: # %bb.10: # %else8 +; SSE2-NEXT: jne .LBB0_13 +; SSE2-NEXT: # %bb.6: # %else8 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: jne .LBB0_11 -; SSE2-NEXT: .LBB0_12: # %else10 +; SSE2-NEXT: jne .LBB0_14 +; SSE2-NEXT: .LBB0_7: # %else10 ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: jne .LBB0_13 -; SSE2-NEXT: .LBB0_14: # %else12 -; SSE2-NEXT: testb $-128, %al ; SSE2-NEXT: jne .LBB0_15 -; SSE2-NEXT: .LBB0_16: # %else14 +; SSE2-NEXT: .LBB0_8: # %else12 +; SSE2-NEXT: testb $-128, %al +; SSE2-NEXT: jne .LBB0_16 +; SSE2-NEXT: .LBB0_9: # %else14 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB0_1: # %cond.store +; SSE2-NEXT: .LBB0_10: # %cond.store ; SSE2-NEXT: movd %xmm0, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB0_4 -; SSE2-NEXT: .LBB0_3: # %cond.store1 +; SSE2-NEXT: je .LBB0_2 +; SSE2-NEXT: .LBB0_11: # %cond.store1 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1] ; SSE2-NEXT: movd %xmm1, 4(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je .LBB0_6 -; SSE2-NEXT: .LBB0_5: # %cond.store3 +; SSE2-NEXT: je .LBB0_3 +; SSE2-NEXT: .LBB0_12: # %cond.store3 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3] ; SSE2-NEXT: movd %xmm1, 8(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne .LBB0_7 -; SSE2-NEXT: jmp .LBB0_8 -; SSE2-NEXT: .LBB0_9: # %cond.store7 +; SSE2-NEXT: jne .LBB0_4 +; SSE2-NEXT: jmp .LBB0_5 +; SSE2-NEXT: .LBB0_13: # %cond.store7 ; SSE2-NEXT: movss %xmm2, 16(%rdi) ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je .LBB0_12 -; SSE2-NEXT: .LBB0_11: # %cond.store9 +; SSE2-NEXT: je .LBB0_7 +; SSE2-NEXT: .LBB0_14: # %cond.store9 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,1,1] ; SSE2-NEXT: movd %xmm0, 20(%rdi) ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: je .LBB0_14 -; SSE2-NEXT: .LBB0_13: # %cond.store11 +; SSE2-NEXT: je .LBB0_8 +; SSE2-NEXT: .LBB0_15: # %cond.store11 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[2,3,2,3] ; SSE2-NEXT: movd %xmm0, 24(%rdi) ; SSE2-NEXT: testb $-128, %al -; SSE2-NEXT: je .LBB0_16 -; SSE2-NEXT: .LBB0_15: # %cond.store13 +; SSE2-NEXT: je .LBB0_9 +; SSE2-NEXT: .LBB0_16: # %cond.store13 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[3,3,3,3] ; SSE2-NEXT: movd %xmm0, 28(%rdi) ; SSE2-NEXT: retq @@ -93,59 +93,59 @@ define void @truncstore_v8i64_v8i32(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; SSE4-NEXT: pmovmskb %xmm4, %eax ; SSE4-NEXT: notl %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB0_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB0_10 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB0_3 -; SSE4-NEXT: .LBB0_4: # %else2 +; SSE4-NEXT: jne .LBB0_11 +; SSE4-NEXT: .LBB0_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB0_5 -; SSE4-NEXT: .LBB0_6: # %else4 +; SSE4-NEXT: jne .LBB0_12 +; SSE4-NEXT: .LBB0_3: # %else4 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB0_8 -; SSE4-NEXT: .LBB0_7: # %cond.store5 +; SSE4-NEXT: je .LBB0_5 +; SSE4-NEXT: .LBB0_4: # %cond.store5 ; SSE4-NEXT: pextrd $3, %xmm0, 12(%rdi) -; SSE4-NEXT: .LBB0_8: # %else6 +; SSE4-NEXT: .LBB0_5: # %else6 ; SSE4-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm3[0,2] ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: jne .LBB0_9 -; SSE4-NEXT: # %bb.10: # %else8 +; SSE4-NEXT: jne .LBB0_13 +; SSE4-NEXT: # %bb.6: # %else8 ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: jne .LBB0_11 -; SSE4-NEXT: .LBB0_12: # %else10 +; SSE4-NEXT: jne .LBB0_14 +; SSE4-NEXT: .LBB0_7: # %else10 ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: jne .LBB0_13 -; SSE4-NEXT: .LBB0_14: # %else12 -; SSE4-NEXT: testb $-128, %al ; SSE4-NEXT: jne .LBB0_15 -; SSE4-NEXT: .LBB0_16: # %else14 +; SSE4-NEXT: .LBB0_8: # %else12 +; SSE4-NEXT: testb $-128, %al +; SSE4-NEXT: jne .LBB0_16 +; SSE4-NEXT: .LBB0_9: # %else14 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB0_1: # %cond.store +; SSE4-NEXT: .LBB0_10: # %cond.store ; SSE4-NEXT: movd %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB0_4 -; SSE4-NEXT: .LBB0_3: # %cond.store1 +; SSE4-NEXT: je .LBB0_2 +; SSE4-NEXT: .LBB0_11: # %cond.store1 ; SSE4-NEXT: pextrd $1, %xmm0, 4(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB0_6 -; SSE4-NEXT: .LBB0_5: # %cond.store3 +; SSE4-NEXT: je .LBB0_3 +; SSE4-NEXT: .LBB0_12: # %cond.store3 ; SSE4-NEXT: pextrd $2, %xmm0, 8(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne .LBB0_7 -; SSE4-NEXT: jmp .LBB0_8 -; SSE4-NEXT: .LBB0_9: # %cond.store7 +; SSE4-NEXT: jne .LBB0_4 +; SSE4-NEXT: jmp .LBB0_5 +; SSE4-NEXT: .LBB0_13: # %cond.store7 ; SSE4-NEXT: movss %xmm2, 16(%rdi) ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: je .LBB0_12 -; SSE4-NEXT: .LBB0_11: # %cond.store9 +; SSE4-NEXT: je .LBB0_7 +; SSE4-NEXT: .LBB0_14: # %cond.store9 ; SSE4-NEXT: extractps $1, %xmm2, 20(%rdi) ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: je .LBB0_14 -; SSE4-NEXT: .LBB0_13: # %cond.store11 +; SSE4-NEXT: je .LBB0_8 +; SSE4-NEXT: .LBB0_15: # %cond.store11 ; SSE4-NEXT: extractps $2, %xmm2, 24(%rdi) ; SSE4-NEXT: testb $-128, %al -; SSE4-NEXT: je .LBB0_16 -; SSE4-NEXT: .LBB0_15: # %cond.store13 +; SSE4-NEXT: je .LBB0_9 +; SSE4-NEXT: .LBB0_16: # %cond.store13 ; SSE4-NEXT: extractps $3, %xmm2, 28(%rdi) ; SSE4-NEXT: retq ; @@ -216,66 +216,66 @@ define void @truncstore_v8i64_v8i16(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; SSE2-NEXT: pmovmskb %xmm4, %eax ; SSE2-NEXT: notl %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne .LBB1_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB1_9 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne .LBB1_3 -; SSE2-NEXT: .LBB1_4: # %else2 +; SSE2-NEXT: jne .LBB1_10 +; SSE2-NEXT: .LBB1_2: # %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne .LBB1_5 -; SSE2-NEXT: .LBB1_6: # %else4 +; SSE2-NEXT: jne .LBB1_11 +; SSE2-NEXT: .LBB1_3: # %else4 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne .LBB1_7 -; SSE2-NEXT: .LBB1_8: # %else6 +; SSE2-NEXT: jne .LBB1_12 +; SSE2-NEXT: .LBB1_4: # %else6 ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: jne .LBB1_9 -; SSE2-NEXT: .LBB1_10: # %else8 +; SSE2-NEXT: jne .LBB1_13 +; SSE2-NEXT: .LBB1_5: # %else8 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: jne .LBB1_11 -; SSE2-NEXT: .LBB1_12: # %else10 +; SSE2-NEXT: jne .LBB1_14 +; SSE2-NEXT: .LBB1_6: # %else10 ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: jne .LBB1_13 -; SSE2-NEXT: .LBB1_14: # %else12 -; SSE2-NEXT: testb $-128, %al ; SSE2-NEXT: jne .LBB1_15 -; SSE2-NEXT: .LBB1_16: # %else14 +; SSE2-NEXT: .LBB1_7: # %else12 +; SSE2-NEXT: testb $-128, %al +; SSE2-NEXT: jne .LBB1_16 +; SSE2-NEXT: .LBB1_8: # %else14 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB1_1: # %cond.store +; SSE2-NEXT: .LBB1_9: # %cond.store ; SSE2-NEXT: movd %xmm0, %ecx ; SSE2-NEXT: movw %cx, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB1_4 -; SSE2-NEXT: .LBB1_3: # %cond.store1 +; SSE2-NEXT: je .LBB1_2 +; SSE2-NEXT: .LBB1_10: # %cond.store1 ; SSE2-NEXT: pextrw $1, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 2(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je .LBB1_6 -; SSE2-NEXT: .LBB1_5: # %cond.store3 +; SSE2-NEXT: je .LBB1_3 +; SSE2-NEXT: .LBB1_11: # %cond.store3 ; SSE2-NEXT: pextrw $2, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 4(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je .LBB1_8 -; SSE2-NEXT: .LBB1_7: # %cond.store5 +; SSE2-NEXT: je .LBB1_4 +; SSE2-NEXT: .LBB1_12: # %cond.store5 ; SSE2-NEXT: pextrw $3, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 6(%rdi) ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: je .LBB1_10 -; SSE2-NEXT: .LBB1_9: # %cond.store7 +; SSE2-NEXT: je .LBB1_5 +; SSE2-NEXT: .LBB1_13: # %cond.store7 ; SSE2-NEXT: pextrw $4, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 8(%rdi) ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je .LBB1_12 -; SSE2-NEXT: .LBB1_11: # %cond.store9 +; SSE2-NEXT: je .LBB1_6 +; SSE2-NEXT: .LBB1_14: # %cond.store9 ; SSE2-NEXT: pextrw $5, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 10(%rdi) ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: je .LBB1_14 -; SSE2-NEXT: .LBB1_13: # %cond.store11 +; SSE2-NEXT: je .LBB1_7 +; SSE2-NEXT: .LBB1_15: # %cond.store11 ; SSE2-NEXT: pextrw $6, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 12(%rdi) ; SSE2-NEXT: testb $-128, %al -; SSE2-NEXT: je .LBB1_16 -; SSE2-NEXT: .LBB1_15: # %cond.store13 +; SSE2-NEXT: je .LBB1_8 +; SSE2-NEXT: .LBB1_16: # %cond.store13 ; SSE2-NEXT: pextrw $7, %xmm0, %eax ; SSE2-NEXT: movw %ax, 14(%rdi) ; SSE2-NEXT: retq @@ -297,59 +297,59 @@ define void @truncstore_v8i64_v8i16(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; SSE4-NEXT: pmovmskb %xmm4, %eax ; SSE4-NEXT: notl %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB1_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB1_9 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB1_3 -; SSE4-NEXT: .LBB1_4: # %else2 +; SSE4-NEXT: jne .LBB1_10 +; SSE4-NEXT: .LBB1_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB1_5 -; SSE4-NEXT: .LBB1_6: # %else4 +; SSE4-NEXT: jne .LBB1_11 +; SSE4-NEXT: .LBB1_3: # %else4 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne .LBB1_7 -; SSE4-NEXT: .LBB1_8: # %else6 +; SSE4-NEXT: jne .LBB1_12 +; SSE4-NEXT: .LBB1_4: # %else6 ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: jne .LBB1_9 -; SSE4-NEXT: .LBB1_10: # %else8 +; SSE4-NEXT: jne .LBB1_13 +; SSE4-NEXT: .LBB1_5: # %else8 ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: jne .LBB1_11 -; SSE4-NEXT: .LBB1_12: # %else10 +; SSE4-NEXT: jne .LBB1_14 +; SSE4-NEXT: .LBB1_6: # %else10 ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: jne .LBB1_13 -; SSE4-NEXT: .LBB1_14: # %else12 -; SSE4-NEXT: testb $-128, %al ; SSE4-NEXT: jne .LBB1_15 -; SSE4-NEXT: .LBB1_16: # %else14 +; SSE4-NEXT: .LBB1_7: # %else12 +; SSE4-NEXT: testb $-128, %al +; SSE4-NEXT: jne .LBB1_16 +; SSE4-NEXT: .LBB1_8: # %else14 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB1_1: # %cond.store +; SSE4-NEXT: .LBB1_9: # %cond.store ; SSE4-NEXT: pextrw $0, %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB1_4 -; SSE4-NEXT: .LBB1_3: # %cond.store1 +; SSE4-NEXT: je .LBB1_2 +; SSE4-NEXT: .LBB1_10: # %cond.store1 ; SSE4-NEXT: pextrw $1, %xmm0, 2(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB1_6 -; SSE4-NEXT: .LBB1_5: # %cond.store3 +; SSE4-NEXT: je .LBB1_3 +; SSE4-NEXT: .LBB1_11: # %cond.store3 ; SSE4-NEXT: pextrw $2, %xmm0, 4(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB1_8 -; SSE4-NEXT: .LBB1_7: # %cond.store5 +; SSE4-NEXT: je .LBB1_4 +; SSE4-NEXT: .LBB1_12: # %cond.store5 ; SSE4-NEXT: pextrw $3, %xmm0, 6(%rdi) ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: je .LBB1_10 -; SSE4-NEXT: .LBB1_9: # %cond.store7 +; SSE4-NEXT: je .LBB1_5 +; SSE4-NEXT: .LBB1_13: # %cond.store7 ; SSE4-NEXT: pextrw $4, %xmm0, 8(%rdi) ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: je .LBB1_12 -; SSE4-NEXT: .LBB1_11: # %cond.store9 +; SSE4-NEXT: je .LBB1_6 +; SSE4-NEXT: .LBB1_14: # %cond.store9 ; SSE4-NEXT: pextrw $5, %xmm0, 10(%rdi) ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: je .LBB1_14 -; SSE4-NEXT: .LBB1_13: # %cond.store11 +; SSE4-NEXT: je .LBB1_7 +; SSE4-NEXT: .LBB1_15: # %cond.store11 ; SSE4-NEXT: pextrw $6, %xmm0, 12(%rdi) ; SSE4-NEXT: testb $-128, %al -; SSE4-NEXT: je .LBB1_16 -; SSE4-NEXT: .LBB1_15: # %cond.store13 +; SSE4-NEXT: je .LBB1_8 +; SSE4-NEXT: .LBB1_16: # %cond.store13 ; SSE4-NEXT: pextrw $7, %xmm0, 14(%rdi) ; SSE4-NEXT: retq ; @@ -371,60 +371,60 @@ define void @truncstore_v8i64_v8i16(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; AVX1-NEXT: vmovmskps %ymm1, %eax ; AVX1-NEXT: notl %eax ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne .LBB1_1 -; AVX1-NEXT: # %bb.2: # %else +; AVX1-NEXT: jne .LBB1_9 +; AVX1-NEXT: # %bb.1: # %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne .LBB1_3 -; AVX1-NEXT: .LBB1_4: # %else2 +; AVX1-NEXT: jne .LBB1_10 +; AVX1-NEXT: .LBB1_2: # %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne .LBB1_5 -; AVX1-NEXT: .LBB1_6: # %else4 +; AVX1-NEXT: jne .LBB1_11 +; AVX1-NEXT: .LBB1_3: # %else4 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne .LBB1_7 -; AVX1-NEXT: .LBB1_8: # %else6 +; AVX1-NEXT: jne .LBB1_12 +; AVX1-NEXT: .LBB1_4: # %else6 ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: jne .LBB1_9 -; AVX1-NEXT: .LBB1_10: # %else8 +; AVX1-NEXT: jne .LBB1_13 +; AVX1-NEXT: .LBB1_5: # %else8 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: jne .LBB1_11 -; AVX1-NEXT: .LBB1_12: # %else10 +; AVX1-NEXT: jne .LBB1_14 +; AVX1-NEXT: .LBB1_6: # %else10 ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: jne .LBB1_13 -; AVX1-NEXT: .LBB1_14: # %else12 -; AVX1-NEXT: testb $-128, %al ; AVX1-NEXT: jne .LBB1_15 -; AVX1-NEXT: .LBB1_16: # %else14 +; AVX1-NEXT: .LBB1_7: # %else12 +; AVX1-NEXT: testb $-128, %al +; AVX1-NEXT: jne .LBB1_16 +; AVX1-NEXT: .LBB1_8: # %else14 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB1_1: # %cond.store +; AVX1-NEXT: .LBB1_9: # %cond.store ; AVX1-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je .LBB1_4 -; AVX1-NEXT: .LBB1_3: # %cond.store1 +; AVX1-NEXT: je .LBB1_2 +; AVX1-NEXT: .LBB1_10: # %cond.store1 ; AVX1-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je .LBB1_6 -; AVX1-NEXT: .LBB1_5: # %cond.store3 +; AVX1-NEXT: je .LBB1_3 +; AVX1-NEXT: .LBB1_11: # %cond.store3 ; AVX1-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB1_8 -; AVX1-NEXT: .LBB1_7: # %cond.store5 +; AVX1-NEXT: je .LBB1_4 +; AVX1-NEXT: .LBB1_12: # %cond.store5 ; AVX1-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: je .LBB1_10 -; AVX1-NEXT: .LBB1_9: # %cond.store7 +; AVX1-NEXT: je .LBB1_5 +; AVX1-NEXT: .LBB1_13: # %cond.store7 ; AVX1-NEXT: vpextrw $4, %xmm0, 8(%rdi) ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je .LBB1_12 -; AVX1-NEXT: .LBB1_11: # %cond.store9 +; AVX1-NEXT: je .LBB1_6 +; AVX1-NEXT: .LBB1_14: # %cond.store9 ; AVX1-NEXT: vpextrw $5, %xmm0, 10(%rdi) ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: je .LBB1_14 -; AVX1-NEXT: .LBB1_13: # %cond.store11 +; AVX1-NEXT: je .LBB1_7 +; AVX1-NEXT: .LBB1_15: # %cond.store11 ; AVX1-NEXT: vpextrw $6, %xmm0, 12(%rdi) ; AVX1-NEXT: testb $-128, %al -; AVX1-NEXT: je .LBB1_16 -; AVX1-NEXT: .LBB1_15: # %cond.store13 +; AVX1-NEXT: je .LBB1_8 +; AVX1-NEXT: .LBB1_16: # %cond.store13 ; AVX1-NEXT: vpextrw $7, %xmm0, 14(%rdi) ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq @@ -442,60 +442,60 @@ define void @truncstore_v8i64_v8i16(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; AVX2-NEXT: vmovmskps %ymm1, %eax ; AVX2-NEXT: notl %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne .LBB1_1 -; AVX2-NEXT: # %bb.2: # %else +; AVX2-NEXT: jne .LBB1_9 +; AVX2-NEXT: # %bb.1: # %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne .LBB1_3 -; AVX2-NEXT: .LBB1_4: # %else2 +; AVX2-NEXT: jne .LBB1_10 +; AVX2-NEXT: .LBB1_2: # %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne .LBB1_5 -; AVX2-NEXT: .LBB1_6: # %else4 +; AVX2-NEXT: jne .LBB1_11 +; AVX2-NEXT: .LBB1_3: # %else4 ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: jne .LBB1_7 -; AVX2-NEXT: .LBB1_8: # %else6 +; AVX2-NEXT: jne .LBB1_12 +; AVX2-NEXT: .LBB1_4: # %else6 ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: jne .LBB1_9 -; AVX2-NEXT: .LBB1_10: # %else8 +; AVX2-NEXT: jne .LBB1_13 +; AVX2-NEXT: .LBB1_5: # %else8 ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: jne .LBB1_11 -; AVX2-NEXT: .LBB1_12: # %else10 +; AVX2-NEXT: jne .LBB1_14 +; AVX2-NEXT: .LBB1_6: # %else10 ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: jne .LBB1_13 -; AVX2-NEXT: .LBB1_14: # %else12 -; AVX2-NEXT: testb $-128, %al ; AVX2-NEXT: jne .LBB1_15 -; AVX2-NEXT: .LBB1_16: # %else14 +; AVX2-NEXT: .LBB1_7: # %else12 +; AVX2-NEXT: testb $-128, %al +; AVX2-NEXT: jne .LBB1_16 +; AVX2-NEXT: .LBB1_8: # %else14 ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; AVX2-NEXT: .LBB1_1: # %cond.store +; AVX2-NEXT: .LBB1_9: # %cond.store ; AVX2-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je .LBB1_4 -; AVX2-NEXT: .LBB1_3: # %cond.store1 +; AVX2-NEXT: je .LBB1_2 +; AVX2-NEXT: .LBB1_10: # %cond.store1 ; AVX2-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je .LBB1_6 -; AVX2-NEXT: .LBB1_5: # %cond.store3 +; AVX2-NEXT: je .LBB1_3 +; AVX2-NEXT: .LBB1_11: # %cond.store3 ; AVX2-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je .LBB1_8 -; AVX2-NEXT: .LBB1_7: # %cond.store5 +; AVX2-NEXT: je .LBB1_4 +; AVX2-NEXT: .LBB1_12: # %cond.store5 ; AVX2-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: je .LBB1_10 -; AVX2-NEXT: .LBB1_9: # %cond.store7 +; AVX2-NEXT: je .LBB1_5 +; AVX2-NEXT: .LBB1_13: # %cond.store7 ; AVX2-NEXT: vpextrw $4, %xmm0, 8(%rdi) ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: je .LBB1_12 -; AVX2-NEXT: .LBB1_11: # %cond.store9 +; AVX2-NEXT: je .LBB1_6 +; AVX2-NEXT: .LBB1_14: # %cond.store9 ; AVX2-NEXT: vpextrw $5, %xmm0, 10(%rdi) ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: je .LBB1_14 -; AVX2-NEXT: .LBB1_13: # %cond.store11 +; AVX2-NEXT: je .LBB1_7 +; AVX2-NEXT: .LBB1_15: # %cond.store11 ; AVX2-NEXT: vpextrw $6, %xmm0, 12(%rdi) ; AVX2-NEXT: testb $-128, %al -; AVX2-NEXT: je .LBB1_16 -; AVX2-NEXT: .LBB1_15: # %cond.store13 +; AVX2-NEXT: je .LBB1_8 +; AVX2-NEXT: .LBB1_16: # %cond.store13 ; AVX2-NEXT: vpextrw $7, %xmm0, 14(%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq @@ -507,60 +507,60 @@ define void @truncstore_v8i64_v8i16(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; AVX512F-NEXT: vpmovqw %zmm0, %xmm0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB1_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB1_9 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB1_3 -; AVX512F-NEXT: .LBB1_4: # %else2 +; AVX512F-NEXT: jne .LBB1_10 +; AVX512F-NEXT: .LBB1_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB1_5 -; AVX512F-NEXT: .LBB1_6: # %else4 +; AVX512F-NEXT: jne .LBB1_11 +; AVX512F-NEXT: .LBB1_3: # %else4 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne .LBB1_7 -; AVX512F-NEXT: .LBB1_8: # %else6 +; AVX512F-NEXT: jne .LBB1_12 +; AVX512F-NEXT: .LBB1_4: # %else6 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne .LBB1_9 -; AVX512F-NEXT: .LBB1_10: # %else8 +; AVX512F-NEXT: jne .LBB1_13 +; AVX512F-NEXT: .LBB1_5: # %else8 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne .LBB1_11 -; AVX512F-NEXT: .LBB1_12: # %else10 +; AVX512F-NEXT: jne .LBB1_14 +; AVX512F-NEXT: .LBB1_6: # %else10 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne .LBB1_13 -; AVX512F-NEXT: .LBB1_14: # %else12 -; AVX512F-NEXT: testb $-128, %al ; AVX512F-NEXT: jne .LBB1_15 -; AVX512F-NEXT: .LBB1_16: # %else14 +; AVX512F-NEXT: .LBB1_7: # %else12 +; AVX512F-NEXT: testb $-128, %al +; AVX512F-NEXT: jne .LBB1_16 +; AVX512F-NEXT: .LBB1_8: # %else14 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB1_1: # %cond.store +; AVX512F-NEXT: .LBB1_9: # %cond.store ; AVX512F-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB1_4 -; AVX512F-NEXT: .LBB1_3: # %cond.store1 +; AVX512F-NEXT: je .LBB1_2 +; AVX512F-NEXT: .LBB1_10: # %cond.store1 ; AVX512F-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB1_6 -; AVX512F-NEXT: .LBB1_5: # %cond.store3 +; AVX512F-NEXT: je .LBB1_3 +; AVX512F-NEXT: .LBB1_11: # %cond.store3 ; AVX512F-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB1_8 -; AVX512F-NEXT: .LBB1_7: # %cond.store5 +; AVX512F-NEXT: je .LBB1_4 +; AVX512F-NEXT: .LBB1_12: # %cond.store5 ; AVX512F-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je .LBB1_10 -; AVX512F-NEXT: .LBB1_9: # %cond.store7 +; AVX512F-NEXT: je .LBB1_5 +; AVX512F-NEXT: .LBB1_13: # %cond.store7 ; AVX512F-NEXT: vpextrw $4, %xmm0, 8(%rdi) ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je .LBB1_12 -; AVX512F-NEXT: .LBB1_11: # %cond.store9 +; AVX512F-NEXT: je .LBB1_6 +; AVX512F-NEXT: .LBB1_14: # %cond.store9 ; AVX512F-NEXT: vpextrw $5, %xmm0, 10(%rdi) ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je .LBB1_14 -; AVX512F-NEXT: .LBB1_13: # %cond.store11 +; AVX512F-NEXT: je .LBB1_7 +; AVX512F-NEXT: .LBB1_15: # %cond.store11 ; AVX512F-NEXT: vpextrw $6, %xmm0, 12(%rdi) ; AVX512F-NEXT: testb $-128, %al -; AVX512F-NEXT: je .LBB1_16 -; AVX512F-NEXT: .LBB1_15: # %cond.store13 +; AVX512F-NEXT: je .LBB1_8 +; AVX512F-NEXT: .LBB1_16: # %cond.store13 ; AVX512F-NEXT: vpextrw $7, %xmm0, 14(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -571,60 +571,60 @@ define void @truncstore_v8i64_v8i16(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; AVX512FVL-NEXT: vpmovqw %zmm0, %xmm0 ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB1_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB1_9 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB1_3 -; AVX512FVL-NEXT: .LBB1_4: # %else2 +; AVX512FVL-NEXT: jne .LBB1_10 +; AVX512FVL-NEXT: .LBB1_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB1_5 -; AVX512FVL-NEXT: .LBB1_6: # %else4 +; AVX512FVL-NEXT: jne .LBB1_11 +; AVX512FVL-NEXT: .LBB1_3: # %else4 ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: jne .LBB1_7 -; AVX512FVL-NEXT: .LBB1_8: # %else6 +; AVX512FVL-NEXT: jne .LBB1_12 +; AVX512FVL-NEXT: .LBB1_4: # %else6 ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: jne .LBB1_9 -; AVX512FVL-NEXT: .LBB1_10: # %else8 +; AVX512FVL-NEXT: jne .LBB1_13 +; AVX512FVL-NEXT: .LBB1_5: # %else8 ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: jne .LBB1_11 -; AVX512FVL-NEXT: .LBB1_12: # %else10 +; AVX512FVL-NEXT: jne .LBB1_14 +; AVX512FVL-NEXT: .LBB1_6: # %else10 ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: jne .LBB1_13 -; AVX512FVL-NEXT: .LBB1_14: # %else12 -; AVX512FVL-NEXT: testb $-128, %al ; AVX512FVL-NEXT: jne .LBB1_15 -; AVX512FVL-NEXT: .LBB1_16: # %else14 +; AVX512FVL-NEXT: .LBB1_7: # %else12 +; AVX512FVL-NEXT: testb $-128, %al +; AVX512FVL-NEXT: jne .LBB1_16 +; AVX512FVL-NEXT: .LBB1_8: # %else14 ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB1_1: # %cond.store +; AVX512FVL-NEXT: .LBB1_9: # %cond.store ; AVX512FVL-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB1_4 -; AVX512FVL-NEXT: .LBB1_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB1_2 +; AVX512FVL-NEXT: .LBB1_10: # %cond.store1 ; AVX512FVL-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB1_6 -; AVX512FVL-NEXT: .LBB1_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB1_3 +; AVX512FVL-NEXT: .LBB1_11: # %cond.store3 ; AVX512FVL-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB1_8 -; AVX512FVL-NEXT: .LBB1_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB1_4 +; AVX512FVL-NEXT: .LBB1_12: # %cond.store5 ; AVX512FVL-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: je .LBB1_10 -; AVX512FVL-NEXT: .LBB1_9: # %cond.store7 +; AVX512FVL-NEXT: je .LBB1_5 +; AVX512FVL-NEXT: .LBB1_13: # %cond.store7 ; AVX512FVL-NEXT: vpextrw $4, %xmm0, 8(%rdi) ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: je .LBB1_12 -; AVX512FVL-NEXT: .LBB1_11: # %cond.store9 +; AVX512FVL-NEXT: je .LBB1_6 +; AVX512FVL-NEXT: .LBB1_14: # %cond.store9 ; AVX512FVL-NEXT: vpextrw $5, %xmm0, 10(%rdi) ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: je .LBB1_14 -; AVX512FVL-NEXT: .LBB1_13: # %cond.store11 +; AVX512FVL-NEXT: je .LBB1_7 +; AVX512FVL-NEXT: .LBB1_15: # %cond.store11 ; AVX512FVL-NEXT: vpextrw $6, %xmm0, 12(%rdi) ; AVX512FVL-NEXT: testb $-128, %al -; AVX512FVL-NEXT: je .LBB1_16 -; AVX512FVL-NEXT: .LBB1_15: # %cond.store13 +; AVX512FVL-NEXT: je .LBB1_8 +; AVX512FVL-NEXT: .LBB1_16: # %cond.store13 ; AVX512FVL-NEXT: vpextrw $7, %xmm0, 14(%rdi) ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq @@ -670,59 +670,59 @@ define void @truncstore_v8i64_v8i8(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; SSE2-NEXT: notl %eax ; SSE2-NEXT: testb $1, %al ; SSE2-NEXT: movd %xmm0, %ecx -; SSE2-NEXT: jne .LBB2_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB2_12 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne .LBB2_3 -; SSE2-NEXT: .LBB2_4: # %else2 +; SSE2-NEXT: jne .LBB2_13 +; SSE2-NEXT: .LBB2_2: # %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne .LBB2_5 -; SSE2-NEXT: .LBB2_6: # %else4 +; SSE2-NEXT: jne .LBB2_14 +; SSE2-NEXT: .LBB2_3: # %else4 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je .LBB2_8 -; SSE2-NEXT: .LBB2_7: # %cond.store5 +; SSE2-NEXT: je .LBB2_5 +; SSE2-NEXT: .LBB2_4: # %cond.store5 ; SSE2-NEXT: shrl $24, %ecx ; SSE2-NEXT: movb %cl, 3(%rdi) -; SSE2-NEXT: .LBB2_8: # %else6 +; SSE2-NEXT: .LBB2_5: # %else6 ; SSE2-NEXT: testb $16, %al ; SSE2-NEXT: pextrw $2, %xmm0, %ecx -; SSE2-NEXT: je .LBB2_10 -; SSE2-NEXT: # %bb.9: # %cond.store7 +; SSE2-NEXT: je .LBB2_7 +; SSE2-NEXT: # %bb.6: # %cond.store7 ; SSE2-NEXT: movb %cl, 4(%rdi) -; SSE2-NEXT: .LBB2_10: # %else8 +; SSE2-NEXT: .LBB2_7: # %else8 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je .LBB2_12 -; SSE2-NEXT: # %bb.11: # %cond.store9 +; SSE2-NEXT: je .LBB2_9 +; SSE2-NEXT: # %bb.8: # %cond.store9 ; SSE2-NEXT: movb %ch, 5(%rdi) -; SSE2-NEXT: .LBB2_12: # %else10 +; SSE2-NEXT: .LBB2_9: # %else10 ; SSE2-NEXT: testb $64, %al ; SSE2-NEXT: pextrw $3, %xmm0, %ecx -; SSE2-NEXT: jne .LBB2_13 -; SSE2-NEXT: # %bb.14: # %else12 -; SSE2-NEXT: testb $-128, %al ; SSE2-NEXT: jne .LBB2_15 -; SSE2-NEXT: .LBB2_16: # %else14 +; SSE2-NEXT: # %bb.10: # %else12 +; SSE2-NEXT: testb $-128, %al +; SSE2-NEXT: jne .LBB2_16 +; SSE2-NEXT: .LBB2_11: # %else14 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB2_1: # %cond.store +; SSE2-NEXT: .LBB2_12: # %cond.store ; SSE2-NEXT: movb %cl, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB2_4 -; SSE2-NEXT: .LBB2_3: # %cond.store1 +; SSE2-NEXT: je .LBB2_2 +; SSE2-NEXT: .LBB2_13: # %cond.store1 ; SSE2-NEXT: movb %ch, 1(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je .LBB2_6 -; SSE2-NEXT: .LBB2_5: # %cond.store3 +; SSE2-NEXT: je .LBB2_3 +; SSE2-NEXT: .LBB2_14: # %cond.store3 ; SSE2-NEXT: movl %ecx, %edx ; SSE2-NEXT: shrl $16, %edx ; SSE2-NEXT: movb %dl, 2(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne .LBB2_7 -; SSE2-NEXT: jmp .LBB2_8 -; SSE2-NEXT: .LBB2_13: # %cond.store11 +; SSE2-NEXT: jne .LBB2_4 +; SSE2-NEXT: jmp .LBB2_5 +; SSE2-NEXT: .LBB2_15: # %cond.store11 ; SSE2-NEXT: movb %cl, 6(%rdi) ; SSE2-NEXT: testb $-128, %al -; SSE2-NEXT: je .LBB2_16 -; SSE2-NEXT: .LBB2_15: # %cond.store13 +; SSE2-NEXT: je .LBB2_11 +; SSE2-NEXT: .LBB2_16: # %cond.store13 ; SSE2-NEXT: movb %ch, 7(%rdi) ; SSE2-NEXT: retq ; @@ -745,59 +745,59 @@ define void @truncstore_v8i64_v8i8(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; SSE4-NEXT: pmovmskb %xmm4, %eax ; SSE4-NEXT: notl %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB2_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB2_9 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB2_3 -; SSE4-NEXT: .LBB2_4: # %else2 +; SSE4-NEXT: jne .LBB2_10 +; SSE4-NEXT: .LBB2_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB2_5 -; SSE4-NEXT: .LBB2_6: # %else4 +; SSE4-NEXT: jne .LBB2_11 +; SSE4-NEXT: .LBB2_3: # %else4 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne .LBB2_7 -; SSE4-NEXT: .LBB2_8: # %else6 +; SSE4-NEXT: jne .LBB2_12 +; SSE4-NEXT: .LBB2_4: # %else6 ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: jne .LBB2_9 -; SSE4-NEXT: .LBB2_10: # %else8 +; SSE4-NEXT: jne .LBB2_13 +; SSE4-NEXT: .LBB2_5: # %else8 ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: jne .LBB2_11 -; SSE4-NEXT: .LBB2_12: # %else10 +; SSE4-NEXT: jne .LBB2_14 +; SSE4-NEXT: .LBB2_6: # %else10 ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: jne .LBB2_13 -; SSE4-NEXT: .LBB2_14: # %else12 -; SSE4-NEXT: testb $-128, %al ; SSE4-NEXT: jne .LBB2_15 -; SSE4-NEXT: .LBB2_16: # %else14 +; SSE4-NEXT: .LBB2_7: # %else12 +; SSE4-NEXT: testb $-128, %al +; SSE4-NEXT: jne .LBB2_16 +; SSE4-NEXT: .LBB2_8: # %else14 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB2_1: # %cond.store +; SSE4-NEXT: .LBB2_9: # %cond.store ; SSE4-NEXT: pextrb $0, %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB2_4 -; SSE4-NEXT: .LBB2_3: # %cond.store1 +; SSE4-NEXT: je .LBB2_2 +; SSE4-NEXT: .LBB2_10: # %cond.store1 ; SSE4-NEXT: pextrb $1, %xmm0, 1(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB2_6 -; SSE4-NEXT: .LBB2_5: # %cond.store3 +; SSE4-NEXT: je .LBB2_3 +; SSE4-NEXT: .LBB2_11: # %cond.store3 ; SSE4-NEXT: pextrb $2, %xmm0, 2(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB2_8 -; SSE4-NEXT: .LBB2_7: # %cond.store5 +; SSE4-NEXT: je .LBB2_4 +; SSE4-NEXT: .LBB2_12: # %cond.store5 ; SSE4-NEXT: pextrb $3, %xmm0, 3(%rdi) ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: je .LBB2_10 -; SSE4-NEXT: .LBB2_9: # %cond.store7 +; SSE4-NEXT: je .LBB2_5 +; SSE4-NEXT: .LBB2_13: # %cond.store7 ; SSE4-NEXT: pextrb $4, %xmm0, 4(%rdi) ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: je .LBB2_12 -; SSE4-NEXT: .LBB2_11: # %cond.store9 +; SSE4-NEXT: je .LBB2_6 +; SSE4-NEXT: .LBB2_14: # %cond.store9 ; SSE4-NEXT: pextrb $5, %xmm0, 5(%rdi) ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: je .LBB2_14 -; SSE4-NEXT: .LBB2_13: # %cond.store11 +; SSE4-NEXT: je .LBB2_7 +; SSE4-NEXT: .LBB2_15: # %cond.store11 ; SSE4-NEXT: pextrb $6, %xmm0, 6(%rdi) ; SSE4-NEXT: testb $-128, %al -; SSE4-NEXT: je .LBB2_16 -; SSE4-NEXT: .LBB2_15: # %cond.store13 +; SSE4-NEXT: je .LBB2_8 +; SSE4-NEXT: .LBB2_16: # %cond.store13 ; SSE4-NEXT: pextrb $7, %xmm0, 7(%rdi) ; SSE4-NEXT: retq ; @@ -820,60 +820,60 @@ define void @truncstore_v8i64_v8i8(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; AVX1-NEXT: vmovmskps %ymm1, %eax ; AVX1-NEXT: notl %eax ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne .LBB2_1 -; AVX1-NEXT: # %bb.2: # %else +; AVX1-NEXT: jne .LBB2_9 +; AVX1-NEXT: # %bb.1: # %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne .LBB2_3 -; AVX1-NEXT: .LBB2_4: # %else2 +; AVX1-NEXT: jne .LBB2_10 +; AVX1-NEXT: .LBB2_2: # %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne .LBB2_5 -; AVX1-NEXT: .LBB2_6: # %else4 +; AVX1-NEXT: jne .LBB2_11 +; AVX1-NEXT: .LBB2_3: # %else4 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne .LBB2_7 -; AVX1-NEXT: .LBB2_8: # %else6 +; AVX1-NEXT: jne .LBB2_12 +; AVX1-NEXT: .LBB2_4: # %else6 ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: jne .LBB2_9 -; AVX1-NEXT: .LBB2_10: # %else8 +; AVX1-NEXT: jne .LBB2_13 +; AVX1-NEXT: .LBB2_5: # %else8 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: jne .LBB2_11 -; AVX1-NEXT: .LBB2_12: # %else10 +; AVX1-NEXT: jne .LBB2_14 +; AVX1-NEXT: .LBB2_6: # %else10 ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: jne .LBB2_13 -; AVX1-NEXT: .LBB2_14: # %else12 -; AVX1-NEXT: testb $-128, %al ; AVX1-NEXT: jne .LBB2_15 -; AVX1-NEXT: .LBB2_16: # %else14 +; AVX1-NEXT: .LBB2_7: # %else12 +; AVX1-NEXT: testb $-128, %al +; AVX1-NEXT: jne .LBB2_16 +; AVX1-NEXT: .LBB2_8: # %else14 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB2_1: # %cond.store +; AVX1-NEXT: .LBB2_9: # %cond.store ; AVX1-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je .LBB2_4 -; AVX1-NEXT: .LBB2_3: # %cond.store1 +; AVX1-NEXT: je .LBB2_2 +; AVX1-NEXT: .LBB2_10: # %cond.store1 ; AVX1-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je .LBB2_6 -; AVX1-NEXT: .LBB2_5: # %cond.store3 +; AVX1-NEXT: je .LBB2_3 +; AVX1-NEXT: .LBB2_11: # %cond.store3 ; AVX1-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB2_8 -; AVX1-NEXT: .LBB2_7: # %cond.store5 +; AVX1-NEXT: je .LBB2_4 +; AVX1-NEXT: .LBB2_12: # %cond.store5 ; AVX1-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: je .LBB2_10 -; AVX1-NEXT: .LBB2_9: # %cond.store7 +; AVX1-NEXT: je .LBB2_5 +; AVX1-NEXT: .LBB2_13: # %cond.store7 ; AVX1-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je .LBB2_12 -; AVX1-NEXT: .LBB2_11: # %cond.store9 +; AVX1-NEXT: je .LBB2_6 +; AVX1-NEXT: .LBB2_14: # %cond.store9 ; AVX1-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: je .LBB2_14 -; AVX1-NEXT: .LBB2_13: # %cond.store11 +; AVX1-NEXT: je .LBB2_7 +; AVX1-NEXT: .LBB2_15: # %cond.store11 ; AVX1-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX1-NEXT: testb $-128, %al -; AVX1-NEXT: je .LBB2_16 -; AVX1-NEXT: .LBB2_15: # %cond.store13 +; AVX1-NEXT: je .LBB2_8 +; AVX1-NEXT: .LBB2_16: # %cond.store13 ; AVX1-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq @@ -893,60 +893,60 @@ define void @truncstore_v8i64_v8i8(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; AVX2-NEXT: vmovmskps %ymm1, %eax ; AVX2-NEXT: notl %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne .LBB2_1 -; AVX2-NEXT: # %bb.2: # %else +; AVX2-NEXT: jne .LBB2_9 +; AVX2-NEXT: # %bb.1: # %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne .LBB2_3 -; AVX2-NEXT: .LBB2_4: # %else2 +; AVX2-NEXT: jne .LBB2_10 +; AVX2-NEXT: .LBB2_2: # %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne .LBB2_5 -; AVX2-NEXT: .LBB2_6: # %else4 +; AVX2-NEXT: jne .LBB2_11 +; AVX2-NEXT: .LBB2_3: # %else4 ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: jne .LBB2_7 -; AVX2-NEXT: .LBB2_8: # %else6 +; AVX2-NEXT: jne .LBB2_12 +; AVX2-NEXT: .LBB2_4: # %else6 ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: jne .LBB2_9 -; AVX2-NEXT: .LBB2_10: # %else8 +; AVX2-NEXT: jne .LBB2_13 +; AVX2-NEXT: .LBB2_5: # %else8 ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: jne .LBB2_11 -; AVX2-NEXT: .LBB2_12: # %else10 +; AVX2-NEXT: jne .LBB2_14 +; AVX2-NEXT: .LBB2_6: # %else10 ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: jne .LBB2_13 -; AVX2-NEXT: .LBB2_14: # %else12 -; AVX2-NEXT: testb $-128, %al ; AVX2-NEXT: jne .LBB2_15 -; AVX2-NEXT: .LBB2_16: # %else14 +; AVX2-NEXT: .LBB2_7: # %else12 +; AVX2-NEXT: testb $-128, %al +; AVX2-NEXT: jne .LBB2_16 +; AVX2-NEXT: .LBB2_8: # %else14 ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; AVX2-NEXT: .LBB2_1: # %cond.store +; AVX2-NEXT: .LBB2_9: # %cond.store ; AVX2-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je .LBB2_4 -; AVX2-NEXT: .LBB2_3: # %cond.store1 +; AVX2-NEXT: je .LBB2_2 +; AVX2-NEXT: .LBB2_10: # %cond.store1 ; AVX2-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je .LBB2_6 -; AVX2-NEXT: .LBB2_5: # %cond.store3 +; AVX2-NEXT: je .LBB2_3 +; AVX2-NEXT: .LBB2_11: # %cond.store3 ; AVX2-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je .LBB2_8 -; AVX2-NEXT: .LBB2_7: # %cond.store5 +; AVX2-NEXT: je .LBB2_4 +; AVX2-NEXT: .LBB2_12: # %cond.store5 ; AVX2-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: je .LBB2_10 -; AVX2-NEXT: .LBB2_9: # %cond.store7 +; AVX2-NEXT: je .LBB2_5 +; AVX2-NEXT: .LBB2_13: # %cond.store7 ; AVX2-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: je .LBB2_12 -; AVX2-NEXT: .LBB2_11: # %cond.store9 +; AVX2-NEXT: je .LBB2_6 +; AVX2-NEXT: .LBB2_14: # %cond.store9 ; AVX2-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: je .LBB2_14 -; AVX2-NEXT: .LBB2_13: # %cond.store11 +; AVX2-NEXT: je .LBB2_7 +; AVX2-NEXT: .LBB2_15: # %cond.store11 ; AVX2-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX2-NEXT: testb $-128, %al -; AVX2-NEXT: je .LBB2_16 -; AVX2-NEXT: .LBB2_15: # %cond.store13 +; AVX2-NEXT: je .LBB2_8 +; AVX2-NEXT: .LBB2_16: # %cond.store13 ; AVX2-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq @@ -958,60 +958,60 @@ define void @truncstore_v8i64_v8i8(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; AVX512F-NEXT: vpmovqb %zmm0, %xmm0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB2_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB2_9 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB2_3 -; AVX512F-NEXT: .LBB2_4: # %else2 +; AVX512F-NEXT: jne .LBB2_10 +; AVX512F-NEXT: .LBB2_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB2_5 -; AVX512F-NEXT: .LBB2_6: # %else4 +; AVX512F-NEXT: jne .LBB2_11 +; AVX512F-NEXT: .LBB2_3: # %else4 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne .LBB2_7 -; AVX512F-NEXT: .LBB2_8: # %else6 +; AVX512F-NEXT: jne .LBB2_12 +; AVX512F-NEXT: .LBB2_4: # %else6 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne .LBB2_9 -; AVX512F-NEXT: .LBB2_10: # %else8 +; AVX512F-NEXT: jne .LBB2_13 +; AVX512F-NEXT: .LBB2_5: # %else8 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne .LBB2_11 -; AVX512F-NEXT: .LBB2_12: # %else10 +; AVX512F-NEXT: jne .LBB2_14 +; AVX512F-NEXT: .LBB2_6: # %else10 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne .LBB2_13 -; AVX512F-NEXT: .LBB2_14: # %else12 -; AVX512F-NEXT: testb $-128, %al ; AVX512F-NEXT: jne .LBB2_15 -; AVX512F-NEXT: .LBB2_16: # %else14 +; AVX512F-NEXT: .LBB2_7: # %else12 +; AVX512F-NEXT: testb $-128, %al +; AVX512F-NEXT: jne .LBB2_16 +; AVX512F-NEXT: .LBB2_8: # %else14 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB2_1: # %cond.store +; AVX512F-NEXT: .LBB2_9: # %cond.store ; AVX512F-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB2_4 -; AVX512F-NEXT: .LBB2_3: # %cond.store1 +; AVX512F-NEXT: je .LBB2_2 +; AVX512F-NEXT: .LBB2_10: # %cond.store1 ; AVX512F-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB2_6 -; AVX512F-NEXT: .LBB2_5: # %cond.store3 +; AVX512F-NEXT: je .LBB2_3 +; AVX512F-NEXT: .LBB2_11: # %cond.store3 ; AVX512F-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB2_8 -; AVX512F-NEXT: .LBB2_7: # %cond.store5 +; AVX512F-NEXT: je .LBB2_4 +; AVX512F-NEXT: .LBB2_12: # %cond.store5 ; AVX512F-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je .LBB2_10 -; AVX512F-NEXT: .LBB2_9: # %cond.store7 +; AVX512F-NEXT: je .LBB2_5 +; AVX512F-NEXT: .LBB2_13: # %cond.store7 ; AVX512F-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je .LBB2_12 -; AVX512F-NEXT: .LBB2_11: # %cond.store9 +; AVX512F-NEXT: je .LBB2_6 +; AVX512F-NEXT: .LBB2_14: # %cond.store9 ; AVX512F-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je .LBB2_14 -; AVX512F-NEXT: .LBB2_13: # %cond.store11 +; AVX512F-NEXT: je .LBB2_7 +; AVX512F-NEXT: .LBB2_15: # %cond.store11 ; AVX512F-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX512F-NEXT: testb $-128, %al -; AVX512F-NEXT: je .LBB2_16 -; AVX512F-NEXT: .LBB2_15: # %cond.store13 +; AVX512F-NEXT: je .LBB2_8 +; AVX512F-NEXT: .LBB2_16: # %cond.store13 ; AVX512F-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -1022,60 +1022,60 @@ define void @truncstore_v8i64_v8i8(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; AVX512FVL-NEXT: vpmovqb %zmm0, %xmm0 ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB2_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB2_9 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB2_3 -; AVX512FVL-NEXT: .LBB2_4: # %else2 +; AVX512FVL-NEXT: jne .LBB2_10 +; AVX512FVL-NEXT: .LBB2_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB2_5 -; AVX512FVL-NEXT: .LBB2_6: # %else4 +; AVX512FVL-NEXT: jne .LBB2_11 +; AVX512FVL-NEXT: .LBB2_3: # %else4 ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: jne .LBB2_7 -; AVX512FVL-NEXT: .LBB2_8: # %else6 +; AVX512FVL-NEXT: jne .LBB2_12 +; AVX512FVL-NEXT: .LBB2_4: # %else6 ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: jne .LBB2_9 -; AVX512FVL-NEXT: .LBB2_10: # %else8 +; AVX512FVL-NEXT: jne .LBB2_13 +; AVX512FVL-NEXT: .LBB2_5: # %else8 ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: jne .LBB2_11 -; AVX512FVL-NEXT: .LBB2_12: # %else10 +; AVX512FVL-NEXT: jne .LBB2_14 +; AVX512FVL-NEXT: .LBB2_6: # %else10 ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: jne .LBB2_13 -; AVX512FVL-NEXT: .LBB2_14: # %else12 -; AVX512FVL-NEXT: testb $-128, %al ; AVX512FVL-NEXT: jne .LBB2_15 -; AVX512FVL-NEXT: .LBB2_16: # %else14 +; AVX512FVL-NEXT: .LBB2_7: # %else12 +; AVX512FVL-NEXT: testb $-128, %al +; AVX512FVL-NEXT: jne .LBB2_16 +; AVX512FVL-NEXT: .LBB2_8: # %else14 ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB2_1: # %cond.store +; AVX512FVL-NEXT: .LBB2_9: # %cond.store ; AVX512FVL-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB2_4 -; AVX512FVL-NEXT: .LBB2_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB2_2 +; AVX512FVL-NEXT: .LBB2_10: # %cond.store1 ; AVX512FVL-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB2_6 -; AVX512FVL-NEXT: .LBB2_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB2_3 +; AVX512FVL-NEXT: .LBB2_11: # %cond.store3 ; AVX512FVL-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB2_8 -; AVX512FVL-NEXT: .LBB2_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB2_4 +; AVX512FVL-NEXT: .LBB2_12: # %cond.store5 ; AVX512FVL-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: je .LBB2_10 -; AVX512FVL-NEXT: .LBB2_9: # %cond.store7 +; AVX512FVL-NEXT: je .LBB2_5 +; AVX512FVL-NEXT: .LBB2_13: # %cond.store7 ; AVX512FVL-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: je .LBB2_12 -; AVX512FVL-NEXT: .LBB2_11: # %cond.store9 +; AVX512FVL-NEXT: je .LBB2_6 +; AVX512FVL-NEXT: .LBB2_14: # %cond.store9 ; AVX512FVL-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: je .LBB2_14 -; AVX512FVL-NEXT: .LBB2_13: # %cond.store11 +; AVX512FVL-NEXT: je .LBB2_7 +; AVX512FVL-NEXT: .LBB2_15: # %cond.store11 ; AVX512FVL-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX512FVL-NEXT: testb $-128, %al -; AVX512FVL-NEXT: je .LBB2_16 -; AVX512FVL-NEXT: .LBB2_15: # %cond.store13 +; AVX512FVL-NEXT: je .LBB2_8 +; AVX512FVL-NEXT: .LBB2_16: # %cond.store13 ; AVX512FVL-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq @@ -1109,33 +1109,33 @@ define void @truncstore_v4i64_v4i32(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; SSE2-NEXT: movmskps %xmm3, %eax ; SSE2-NEXT: xorl $15, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne .LBB3_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB3_5 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne .LBB3_3 -; SSE2-NEXT: .LBB3_4: # %else2 +; SSE2-NEXT: jne .LBB3_6 +; SSE2-NEXT: .LBB3_2: # %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne .LBB3_5 -; SSE2-NEXT: .LBB3_6: # %else4 -; SSE2-NEXT: testb $8, %al ; SSE2-NEXT: jne .LBB3_7 -; SSE2-NEXT: .LBB3_8: # %else6 +; SSE2-NEXT: .LBB3_3: # %else4 +; SSE2-NEXT: testb $8, %al +; SSE2-NEXT: jne .LBB3_8 +; SSE2-NEXT: .LBB3_4: # %else6 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB3_1: # %cond.store +; SSE2-NEXT: .LBB3_5: # %cond.store ; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB3_4 -; SSE2-NEXT: .LBB3_3: # %cond.store1 +; SSE2-NEXT: je .LBB3_2 +; SSE2-NEXT: .LBB3_6: # %cond.store1 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1] ; SSE2-NEXT: movd %xmm1, 4(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je .LBB3_6 -; SSE2-NEXT: .LBB3_5: # %cond.store3 +; SSE2-NEXT: je .LBB3_3 +; SSE2-NEXT: .LBB3_7: # %cond.store3 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3] ; SSE2-NEXT: movd %xmm1, 8(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je .LBB3_8 -; SSE2-NEXT: .LBB3_7: # %cond.store5 +; SSE2-NEXT: je .LBB3_4 +; SSE2-NEXT: .LBB3_8: # %cond.store5 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: movd %xmm0, 12(%rdi) ; SSE2-NEXT: retq @@ -1148,31 +1148,31 @@ define void @truncstore_v4i64_v4i32(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; SSE4-NEXT: movmskps %xmm3, %eax ; SSE4-NEXT: xorl $15, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB3_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB3_5 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB3_3 -; SSE4-NEXT: .LBB3_4: # %else2 +; SSE4-NEXT: jne .LBB3_6 +; SSE4-NEXT: .LBB3_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB3_5 -; SSE4-NEXT: .LBB3_6: # %else4 -; SSE4-NEXT: testb $8, %al ; SSE4-NEXT: jne .LBB3_7 -; SSE4-NEXT: .LBB3_8: # %else6 +; SSE4-NEXT: .LBB3_3: # %else4 +; SSE4-NEXT: testb $8, %al +; SSE4-NEXT: jne .LBB3_8 +; SSE4-NEXT: .LBB3_4: # %else6 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB3_1: # %cond.store +; SSE4-NEXT: .LBB3_5: # %cond.store ; SSE4-NEXT: movss %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB3_4 -; SSE4-NEXT: .LBB3_3: # %cond.store1 +; SSE4-NEXT: je .LBB3_2 +; SSE4-NEXT: .LBB3_6: # %cond.store1 ; SSE4-NEXT: extractps $1, %xmm0, 4(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB3_6 -; SSE4-NEXT: .LBB3_5: # %cond.store3 +; SSE4-NEXT: je .LBB3_3 +; SSE4-NEXT: .LBB3_7: # %cond.store3 ; SSE4-NEXT: extractps $2, %xmm0, 8(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB3_8 -; SSE4-NEXT: .LBB3_7: # %cond.store5 +; SSE4-NEXT: je .LBB3_4 +; SSE4-NEXT: .LBB3_8: # %cond.store5 ; SSE4-NEXT: extractps $3, %xmm0, 12(%rdi) ; SSE4-NEXT: retq ; @@ -1236,34 +1236,34 @@ define void @truncstore_v4i64_v4i16(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; SSE2-NEXT: movmskps %xmm2, %eax ; SSE2-NEXT: xorl $15, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne .LBB4_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB4_5 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne .LBB4_3 -; SSE2-NEXT: .LBB4_4: # %else2 +; SSE2-NEXT: jne .LBB4_6 +; SSE2-NEXT: .LBB4_2: # %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne .LBB4_5 -; SSE2-NEXT: .LBB4_6: # %else4 -; SSE2-NEXT: testb $8, %al ; SSE2-NEXT: jne .LBB4_7 -; SSE2-NEXT: .LBB4_8: # %else6 +; SSE2-NEXT: .LBB4_3: # %else4 +; SSE2-NEXT: testb $8, %al +; SSE2-NEXT: jne .LBB4_8 +; SSE2-NEXT: .LBB4_4: # %else6 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB4_1: # %cond.store +; SSE2-NEXT: .LBB4_5: # %cond.store ; SSE2-NEXT: movd %xmm0, %ecx ; SSE2-NEXT: movw %cx, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB4_4 -; SSE2-NEXT: .LBB4_3: # %cond.store1 +; SSE2-NEXT: je .LBB4_2 +; SSE2-NEXT: .LBB4_6: # %cond.store1 ; SSE2-NEXT: pextrw $1, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 2(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je .LBB4_6 -; SSE2-NEXT: .LBB4_5: # %cond.store3 +; SSE2-NEXT: je .LBB4_3 +; SSE2-NEXT: .LBB4_7: # %cond.store3 ; SSE2-NEXT: pextrw $2, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 4(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je .LBB4_8 -; SSE2-NEXT: .LBB4_7: # %cond.store5 +; SSE2-NEXT: je .LBB4_4 +; SSE2-NEXT: .LBB4_8: # %cond.store5 ; SSE2-NEXT: pextrw $3, %xmm0, %eax ; SSE2-NEXT: movw %ax, 6(%rdi) ; SSE2-NEXT: retq @@ -1279,31 +1279,31 @@ define void @truncstore_v4i64_v4i16(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; SSE4-NEXT: movmskps %xmm2, %eax ; SSE4-NEXT: xorl $15, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB4_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB4_5 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB4_3 -; SSE4-NEXT: .LBB4_4: # %else2 +; SSE4-NEXT: jne .LBB4_6 +; SSE4-NEXT: .LBB4_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB4_5 -; SSE4-NEXT: .LBB4_6: # %else4 -; SSE4-NEXT: testb $8, %al ; SSE4-NEXT: jne .LBB4_7 -; SSE4-NEXT: .LBB4_8: # %else6 +; SSE4-NEXT: .LBB4_3: # %else4 +; SSE4-NEXT: testb $8, %al +; SSE4-NEXT: jne .LBB4_8 +; SSE4-NEXT: .LBB4_4: # %else6 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB4_1: # %cond.store +; SSE4-NEXT: .LBB4_5: # %cond.store ; SSE4-NEXT: pextrw $0, %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB4_4 -; SSE4-NEXT: .LBB4_3: # %cond.store1 +; SSE4-NEXT: je .LBB4_2 +; SSE4-NEXT: .LBB4_6: # %cond.store1 ; SSE4-NEXT: pextrw $1, %xmm0, 2(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB4_6 -; SSE4-NEXT: .LBB4_5: # %cond.store3 +; SSE4-NEXT: je .LBB4_3 +; SSE4-NEXT: .LBB4_7: # %cond.store3 ; SSE4-NEXT: pextrw $2, %xmm0, 4(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB4_8 -; SSE4-NEXT: .LBB4_7: # %cond.store5 +; SSE4-NEXT: je .LBB4_4 +; SSE4-NEXT: .LBB4_8: # %cond.store5 ; SSE4-NEXT: pextrw $3, %xmm0, 6(%rdi) ; SSE4-NEXT: retq ; @@ -1319,32 +1319,32 @@ define void @truncstore_v4i64_v4i16(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; AVX1-NEXT: vmovmskps %xmm1, %eax ; AVX1-NEXT: xorl $15, %eax ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne .LBB4_1 -; AVX1-NEXT: # %bb.2: # %else +; AVX1-NEXT: jne .LBB4_5 +; AVX1-NEXT: # %bb.1: # %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne .LBB4_3 -; AVX1-NEXT: .LBB4_4: # %else2 +; AVX1-NEXT: jne .LBB4_6 +; AVX1-NEXT: .LBB4_2: # %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne .LBB4_5 -; AVX1-NEXT: .LBB4_6: # %else4 -; AVX1-NEXT: testb $8, %al ; AVX1-NEXT: jne .LBB4_7 -; AVX1-NEXT: .LBB4_8: # %else6 +; AVX1-NEXT: .LBB4_3: # %else4 +; AVX1-NEXT: testb $8, %al +; AVX1-NEXT: jne .LBB4_8 +; AVX1-NEXT: .LBB4_4: # %else6 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB4_1: # %cond.store +; AVX1-NEXT: .LBB4_5: # %cond.store ; AVX1-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je .LBB4_4 -; AVX1-NEXT: .LBB4_3: # %cond.store1 +; AVX1-NEXT: je .LBB4_2 +; AVX1-NEXT: .LBB4_6: # %cond.store1 ; AVX1-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je .LBB4_6 -; AVX1-NEXT: .LBB4_5: # %cond.store3 +; AVX1-NEXT: je .LBB4_3 +; AVX1-NEXT: .LBB4_7: # %cond.store3 ; AVX1-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB4_8 -; AVX1-NEXT: .LBB4_7: # %cond.store5 +; AVX1-NEXT: je .LBB4_4 +; AVX1-NEXT: .LBB4_8: # %cond.store5 ; AVX1-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq @@ -1361,32 +1361,32 @@ define void @truncstore_v4i64_v4i16(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; AVX2-NEXT: vmovmskps %xmm1, %eax ; AVX2-NEXT: xorl $15, %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne .LBB4_1 -; AVX2-NEXT: # %bb.2: # %else +; AVX2-NEXT: jne .LBB4_5 +; AVX2-NEXT: # %bb.1: # %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne .LBB4_3 -; AVX2-NEXT: .LBB4_4: # %else2 +; AVX2-NEXT: jne .LBB4_6 +; AVX2-NEXT: .LBB4_2: # %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne .LBB4_5 -; AVX2-NEXT: .LBB4_6: # %else4 -; AVX2-NEXT: testb $8, %al ; AVX2-NEXT: jne .LBB4_7 -; AVX2-NEXT: .LBB4_8: # %else6 +; AVX2-NEXT: .LBB4_3: # %else4 +; AVX2-NEXT: testb $8, %al +; AVX2-NEXT: jne .LBB4_8 +; AVX2-NEXT: .LBB4_4: # %else6 ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; AVX2-NEXT: .LBB4_1: # %cond.store +; AVX2-NEXT: .LBB4_5: # %cond.store ; AVX2-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je .LBB4_4 -; AVX2-NEXT: .LBB4_3: # %cond.store1 +; AVX2-NEXT: je .LBB4_2 +; AVX2-NEXT: .LBB4_6: # %cond.store1 ; AVX2-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je .LBB4_6 -; AVX2-NEXT: .LBB4_5: # %cond.store3 +; AVX2-NEXT: je .LBB4_3 +; AVX2-NEXT: .LBB4_7: # %cond.store3 ; AVX2-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je .LBB4_8 -; AVX2-NEXT: .LBB4_7: # %cond.store5 +; AVX2-NEXT: je .LBB4_4 +; AVX2-NEXT: .LBB4_8: # %cond.store5 ; AVX2-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq @@ -1399,32 +1399,32 @@ define void @truncstore_v4i64_v4i16(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; AVX512F-NEXT: vpmovqw %zmm0, %xmm0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB4_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB4_5 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB4_3 -; AVX512F-NEXT: .LBB4_4: # %else2 +; AVX512F-NEXT: jne .LBB4_6 +; AVX512F-NEXT: .LBB4_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB4_5 -; AVX512F-NEXT: .LBB4_6: # %else4 -; AVX512F-NEXT: testb $8, %al ; AVX512F-NEXT: jne .LBB4_7 -; AVX512F-NEXT: .LBB4_8: # %else6 +; AVX512F-NEXT: .LBB4_3: # %else4 +; AVX512F-NEXT: testb $8, %al +; AVX512F-NEXT: jne .LBB4_8 +; AVX512F-NEXT: .LBB4_4: # %else6 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB4_1: # %cond.store +; AVX512F-NEXT: .LBB4_5: # %cond.store ; AVX512F-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB4_4 -; AVX512F-NEXT: .LBB4_3: # %cond.store1 +; AVX512F-NEXT: je .LBB4_2 +; AVX512F-NEXT: .LBB4_6: # %cond.store1 ; AVX512F-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB4_6 -; AVX512F-NEXT: .LBB4_5: # %cond.store3 +; AVX512F-NEXT: je .LBB4_3 +; AVX512F-NEXT: .LBB4_7: # %cond.store3 ; AVX512F-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB4_8 -; AVX512F-NEXT: .LBB4_7: # %cond.store5 +; AVX512F-NEXT: je .LBB4_4 +; AVX512F-NEXT: .LBB4_8: # %cond.store5 ; AVX512F-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -1435,32 +1435,32 @@ define void @truncstore_v4i64_v4i16(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; AVX512FVL-NEXT: vpmovqw %ymm0, %xmm0 ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB4_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB4_5 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB4_3 -; AVX512FVL-NEXT: .LBB4_4: # %else2 +; AVX512FVL-NEXT: jne .LBB4_6 +; AVX512FVL-NEXT: .LBB4_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB4_5 -; AVX512FVL-NEXT: .LBB4_6: # %else4 -; AVX512FVL-NEXT: testb $8, %al ; AVX512FVL-NEXT: jne .LBB4_7 -; AVX512FVL-NEXT: .LBB4_8: # %else6 +; AVX512FVL-NEXT: .LBB4_3: # %else4 +; AVX512FVL-NEXT: testb $8, %al +; AVX512FVL-NEXT: jne .LBB4_8 +; AVX512FVL-NEXT: .LBB4_4: # %else6 ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB4_1: # %cond.store +; AVX512FVL-NEXT: .LBB4_5: # %cond.store ; AVX512FVL-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB4_4 -; AVX512FVL-NEXT: .LBB4_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB4_2 +; AVX512FVL-NEXT: .LBB4_6: # %cond.store1 ; AVX512FVL-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB4_6 -; AVX512FVL-NEXT: .LBB4_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB4_3 +; AVX512FVL-NEXT: .LBB4_7: # %cond.store3 ; AVX512FVL-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB4_8 -; AVX512FVL-NEXT: .LBB4_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB4_4 +; AVX512FVL-NEXT: .LBB4_8: # %cond.store5 ; AVX512FVL-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq @@ -1504,33 +1504,33 @@ define void @truncstore_v4i64_v4i8(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; SSE2-NEXT: xorl $15, %ecx ; SSE2-NEXT: testb $1, %cl ; SSE2-NEXT: movd %xmm0, %eax -; SSE2-NEXT: jne .LBB5_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB5_5 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %cl -; SSE2-NEXT: jne .LBB5_3 -; SSE2-NEXT: .LBB5_4: # %else2 +; SSE2-NEXT: jne .LBB5_6 +; SSE2-NEXT: .LBB5_2: # %else2 ; SSE2-NEXT: testb $4, %cl -; SSE2-NEXT: jne .LBB5_5 -; SSE2-NEXT: .LBB5_6: # %else4 -; SSE2-NEXT: testb $8, %cl ; SSE2-NEXT: jne .LBB5_7 -; SSE2-NEXT: .LBB5_8: # %else6 +; SSE2-NEXT: .LBB5_3: # %else4 +; SSE2-NEXT: testb $8, %cl +; SSE2-NEXT: jne .LBB5_8 +; SSE2-NEXT: .LBB5_4: # %else6 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB5_1: # %cond.store +; SSE2-NEXT: .LBB5_5: # %cond.store ; SSE2-NEXT: movb %al, (%rdi) ; SSE2-NEXT: testb $2, %cl -; SSE2-NEXT: je .LBB5_4 -; SSE2-NEXT: .LBB5_3: # %cond.store1 +; SSE2-NEXT: je .LBB5_2 +; SSE2-NEXT: .LBB5_6: # %cond.store1 ; SSE2-NEXT: movb %ah, 1(%rdi) ; SSE2-NEXT: testb $4, %cl -; SSE2-NEXT: je .LBB5_6 -; SSE2-NEXT: .LBB5_5: # %cond.store3 +; SSE2-NEXT: je .LBB5_3 +; SSE2-NEXT: .LBB5_7: # %cond.store3 ; SSE2-NEXT: movl %eax, %edx ; SSE2-NEXT: shrl $16, %edx ; SSE2-NEXT: movb %dl, 2(%rdi) ; SSE2-NEXT: testb $8, %cl -; SSE2-NEXT: je .LBB5_8 -; SSE2-NEXT: .LBB5_7: # %cond.store5 +; SSE2-NEXT: je .LBB5_4 +; SSE2-NEXT: .LBB5_8: # %cond.store5 ; SSE2-NEXT: shrl $24, %eax ; SSE2-NEXT: movb %al, 3(%rdi) ; SSE2-NEXT: retq @@ -1546,31 +1546,31 @@ define void @truncstore_v4i64_v4i8(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; SSE4-NEXT: movmskps %xmm3, %eax ; SSE4-NEXT: xorl $15, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB5_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB5_5 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB5_3 -; SSE4-NEXT: .LBB5_4: # %else2 +; SSE4-NEXT: jne .LBB5_6 +; SSE4-NEXT: .LBB5_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB5_5 -; SSE4-NEXT: .LBB5_6: # %else4 -; SSE4-NEXT: testb $8, %al ; SSE4-NEXT: jne .LBB5_7 -; SSE4-NEXT: .LBB5_8: # %else6 +; SSE4-NEXT: .LBB5_3: # %else4 +; SSE4-NEXT: testb $8, %al +; SSE4-NEXT: jne .LBB5_8 +; SSE4-NEXT: .LBB5_4: # %else6 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB5_1: # %cond.store +; SSE4-NEXT: .LBB5_5: # %cond.store ; SSE4-NEXT: pextrb $0, %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB5_4 -; SSE4-NEXT: .LBB5_3: # %cond.store1 +; SSE4-NEXT: je .LBB5_2 +; SSE4-NEXT: .LBB5_6: # %cond.store1 ; SSE4-NEXT: pextrb $1, %xmm0, 1(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB5_6 -; SSE4-NEXT: .LBB5_5: # %cond.store3 +; SSE4-NEXT: je .LBB5_3 +; SSE4-NEXT: .LBB5_7: # %cond.store3 ; SSE4-NEXT: pextrb $2, %xmm0, 2(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB5_8 -; SSE4-NEXT: .LBB5_7: # %cond.store5 +; SSE4-NEXT: je .LBB5_4 +; SSE4-NEXT: .LBB5_8: # %cond.store5 ; SSE4-NEXT: pextrb $3, %xmm0, 3(%rdi) ; SSE4-NEXT: retq ; @@ -1586,32 +1586,32 @@ define void @truncstore_v4i64_v4i8(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; AVX1-NEXT: vmovmskps %xmm1, %eax ; AVX1-NEXT: xorl $15, %eax ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne .LBB5_1 -; AVX1-NEXT: # %bb.2: # %else +; AVX1-NEXT: jne .LBB5_5 +; AVX1-NEXT: # %bb.1: # %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne .LBB5_3 -; AVX1-NEXT: .LBB5_4: # %else2 +; AVX1-NEXT: jne .LBB5_6 +; AVX1-NEXT: .LBB5_2: # %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne .LBB5_5 -; AVX1-NEXT: .LBB5_6: # %else4 -; AVX1-NEXT: testb $8, %al ; AVX1-NEXT: jne .LBB5_7 -; AVX1-NEXT: .LBB5_8: # %else6 +; AVX1-NEXT: .LBB5_3: # %else4 +; AVX1-NEXT: testb $8, %al +; AVX1-NEXT: jne .LBB5_8 +; AVX1-NEXT: .LBB5_4: # %else6 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB5_1: # %cond.store +; AVX1-NEXT: .LBB5_5: # %cond.store ; AVX1-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je .LBB5_4 -; AVX1-NEXT: .LBB5_3: # %cond.store1 +; AVX1-NEXT: je .LBB5_2 +; AVX1-NEXT: .LBB5_6: # %cond.store1 ; AVX1-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je .LBB5_6 -; AVX1-NEXT: .LBB5_5: # %cond.store3 +; AVX1-NEXT: je .LBB5_3 +; AVX1-NEXT: .LBB5_7: # %cond.store3 ; AVX1-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB5_8 -; AVX1-NEXT: .LBB5_7: # %cond.store5 +; AVX1-NEXT: je .LBB5_4 +; AVX1-NEXT: .LBB5_8: # %cond.store5 ; AVX1-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq @@ -1628,32 +1628,32 @@ define void @truncstore_v4i64_v4i8(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; AVX2-NEXT: vmovmskps %xmm1, %eax ; AVX2-NEXT: xorl $15, %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne .LBB5_1 -; AVX2-NEXT: # %bb.2: # %else +; AVX2-NEXT: jne .LBB5_5 +; AVX2-NEXT: # %bb.1: # %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne .LBB5_3 -; AVX2-NEXT: .LBB5_4: # %else2 +; AVX2-NEXT: jne .LBB5_6 +; AVX2-NEXT: .LBB5_2: # %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne .LBB5_5 -; AVX2-NEXT: .LBB5_6: # %else4 -; AVX2-NEXT: testb $8, %al ; AVX2-NEXT: jne .LBB5_7 -; AVX2-NEXT: .LBB5_8: # %else6 +; AVX2-NEXT: .LBB5_3: # %else4 +; AVX2-NEXT: testb $8, %al +; AVX2-NEXT: jne .LBB5_8 +; AVX2-NEXT: .LBB5_4: # %else6 ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; AVX2-NEXT: .LBB5_1: # %cond.store +; AVX2-NEXT: .LBB5_5: # %cond.store ; AVX2-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je .LBB5_4 -; AVX2-NEXT: .LBB5_3: # %cond.store1 +; AVX2-NEXT: je .LBB5_2 +; AVX2-NEXT: .LBB5_6: # %cond.store1 ; AVX2-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je .LBB5_6 -; AVX2-NEXT: .LBB5_5: # %cond.store3 +; AVX2-NEXT: je .LBB5_3 +; AVX2-NEXT: .LBB5_7: # %cond.store3 ; AVX2-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je .LBB5_8 -; AVX2-NEXT: .LBB5_7: # %cond.store5 +; AVX2-NEXT: je .LBB5_4 +; AVX2-NEXT: .LBB5_8: # %cond.store5 ; AVX2-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq @@ -1666,32 +1666,32 @@ define void @truncstore_v4i64_v4i8(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; AVX512F-NEXT: vpmovqb %zmm0, %xmm0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB5_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB5_5 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB5_3 -; AVX512F-NEXT: .LBB5_4: # %else2 +; AVX512F-NEXT: jne .LBB5_6 +; AVX512F-NEXT: .LBB5_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB5_5 -; AVX512F-NEXT: .LBB5_6: # %else4 -; AVX512F-NEXT: testb $8, %al ; AVX512F-NEXT: jne .LBB5_7 -; AVX512F-NEXT: .LBB5_8: # %else6 +; AVX512F-NEXT: .LBB5_3: # %else4 +; AVX512F-NEXT: testb $8, %al +; AVX512F-NEXT: jne .LBB5_8 +; AVX512F-NEXT: .LBB5_4: # %else6 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB5_1: # %cond.store +; AVX512F-NEXT: .LBB5_5: # %cond.store ; AVX512F-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB5_4 -; AVX512F-NEXT: .LBB5_3: # %cond.store1 +; AVX512F-NEXT: je .LBB5_2 +; AVX512F-NEXT: .LBB5_6: # %cond.store1 ; AVX512F-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB5_6 -; AVX512F-NEXT: .LBB5_5: # %cond.store3 +; AVX512F-NEXT: je .LBB5_3 +; AVX512F-NEXT: .LBB5_7: # %cond.store3 ; AVX512F-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB5_8 -; AVX512F-NEXT: .LBB5_7: # %cond.store5 +; AVX512F-NEXT: je .LBB5_4 +; AVX512F-NEXT: .LBB5_8: # %cond.store5 ; AVX512F-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -1702,32 +1702,32 @@ define void @truncstore_v4i64_v4i8(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; AVX512FVL-NEXT: vpmovqb %ymm0, %xmm0 ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB5_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB5_5 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB5_3 -; AVX512FVL-NEXT: .LBB5_4: # %else2 +; AVX512FVL-NEXT: jne .LBB5_6 +; AVX512FVL-NEXT: .LBB5_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB5_5 -; AVX512FVL-NEXT: .LBB5_6: # %else4 -; AVX512FVL-NEXT: testb $8, %al ; AVX512FVL-NEXT: jne .LBB5_7 -; AVX512FVL-NEXT: .LBB5_8: # %else6 +; AVX512FVL-NEXT: .LBB5_3: # %else4 +; AVX512FVL-NEXT: testb $8, %al +; AVX512FVL-NEXT: jne .LBB5_8 +; AVX512FVL-NEXT: .LBB5_4: # %else6 ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB5_1: # %cond.store +; AVX512FVL-NEXT: .LBB5_5: # %cond.store ; AVX512FVL-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB5_4 -; AVX512FVL-NEXT: .LBB5_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB5_2 +; AVX512FVL-NEXT: .LBB5_6: # %cond.store1 ; AVX512FVL-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB5_6 -; AVX512FVL-NEXT: .LBB5_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB5_3 +; AVX512FVL-NEXT: .LBB5_7: # %cond.store3 ; AVX512FVL-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB5_8 -; AVX512FVL-NEXT: .LBB5_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB5_4 +; AVX512FVL-NEXT: .LBB5_8: # %cond.store5 ; AVX512FVL-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq @@ -1767,17 +1767,17 @@ define void @truncstore_v2i64_v2i32(<2 x i64> %x, ptr %p, <2 x i64> %mask) { ; SSE2-NEXT: movmskpd %xmm1, %eax ; SSE2-NEXT: xorl $3, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne .LBB6_1 -; SSE2-NEXT: # %bb.2: # %else -; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: jne .LBB6_3 -; SSE2-NEXT: .LBB6_4: # %else2 +; SSE2-NEXT: # %bb.1: # %else +; SSE2-NEXT: testb $2, %al +; SSE2-NEXT: jne .LBB6_4 +; SSE2-NEXT: .LBB6_2: # %else2 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB6_1: # %cond.store +; SSE2-NEXT: .LBB6_3: # %cond.store ; SSE2-NEXT: movd %xmm0, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB6_4 -; SSE2-NEXT: .LBB6_3: # %cond.store1 +; SSE2-NEXT: je .LBB6_2 +; SSE2-NEXT: .LBB6_4: # %cond.store1 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1] ; SSE2-NEXT: movd %xmm0, 4(%rdi) ; SSE2-NEXT: retq @@ -1790,17 +1790,17 @@ define void @truncstore_v2i64_v2i32(<2 x i64> %x, ptr %p, <2 x i64> %mask) { ; SSE4-NEXT: movmskpd %xmm2, %eax ; SSE4-NEXT: xorl $3, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB6_1 -; SSE4-NEXT: # %bb.2: # %else -; SSE4-NEXT: testb $2, %al ; SSE4-NEXT: jne .LBB6_3 -; SSE4-NEXT: .LBB6_4: # %else2 +; SSE4-NEXT: # %bb.1: # %else +; SSE4-NEXT: testb $2, %al +; SSE4-NEXT: jne .LBB6_4 +; SSE4-NEXT: .LBB6_2: # %else2 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB6_1: # %cond.store +; SSE4-NEXT: .LBB6_3: # %cond.store ; SSE4-NEXT: movd %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB6_4 -; SSE4-NEXT: .LBB6_3: # %cond.store1 +; SSE4-NEXT: je .LBB6_2 +; SSE4-NEXT: .LBB6_4: # %cond.store1 ; SSE4-NEXT: pextrd $1, %xmm0, 4(%rdi) ; SSE4-NEXT: retq ; @@ -1860,18 +1860,18 @@ define void @truncstore_v2i64_v2i16(<2 x i64> %x, ptr %p, <2 x i64> %mask) { ; SSE2-NEXT: movmskpd %xmm1, %eax ; SSE2-NEXT: xorl $3, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne .LBB7_1 -; SSE2-NEXT: # %bb.2: # %else -; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: jne .LBB7_3 -; SSE2-NEXT: .LBB7_4: # %else2 +; SSE2-NEXT: # %bb.1: # %else +; SSE2-NEXT: testb $2, %al +; SSE2-NEXT: jne .LBB7_4 +; SSE2-NEXT: .LBB7_2: # %else2 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB7_1: # %cond.store +; SSE2-NEXT: .LBB7_3: # %cond.store ; SSE2-NEXT: movd %xmm0, %ecx ; SSE2-NEXT: movw %cx, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB7_4 -; SSE2-NEXT: .LBB7_3: # %cond.store1 +; SSE2-NEXT: je .LBB7_2 +; SSE2-NEXT: .LBB7_4: # %cond.store1 ; SSE2-NEXT: pextrw $1, %xmm0, %eax ; SSE2-NEXT: movw %ax, 2(%rdi) ; SSE2-NEXT: retq @@ -1885,17 +1885,17 @@ define void @truncstore_v2i64_v2i16(<2 x i64> %x, ptr %p, <2 x i64> %mask) { ; SSE4-NEXT: movmskpd %xmm2, %eax ; SSE4-NEXT: xorl $3, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB7_1 -; SSE4-NEXT: # %bb.2: # %else -; SSE4-NEXT: testb $2, %al ; SSE4-NEXT: jne .LBB7_3 -; SSE4-NEXT: .LBB7_4: # %else2 +; SSE4-NEXT: # %bb.1: # %else +; SSE4-NEXT: testb $2, %al +; SSE4-NEXT: jne .LBB7_4 +; SSE4-NEXT: .LBB7_2: # %else2 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB7_1: # %cond.store +; SSE4-NEXT: .LBB7_3: # %cond.store ; SSE4-NEXT: pextrw $0, %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB7_4 -; SSE4-NEXT: .LBB7_3: # %cond.store1 +; SSE4-NEXT: je .LBB7_2 +; SSE4-NEXT: .LBB7_4: # %cond.store1 ; SSE4-NEXT: pextrw $1, %xmm0, 2(%rdi) ; SSE4-NEXT: retq ; @@ -1908,17 +1908,17 @@ define void @truncstore_v2i64_v2i16(<2 x i64> %x, ptr %p, <2 x i64> %mask) { ; AVX-NEXT: vmovmskpd %xmm1, %eax ; AVX-NEXT: xorl $3, %eax ; AVX-NEXT: testb $1, %al -; AVX-NEXT: jne .LBB7_1 -; AVX-NEXT: # %bb.2: # %else -; AVX-NEXT: testb $2, %al ; AVX-NEXT: jne .LBB7_3 -; AVX-NEXT: .LBB7_4: # %else2 +; AVX-NEXT: # %bb.1: # %else +; AVX-NEXT: testb $2, %al +; AVX-NEXT: jne .LBB7_4 +; AVX-NEXT: .LBB7_2: # %else2 ; AVX-NEXT: retq -; AVX-NEXT: .LBB7_1: # %cond.store +; AVX-NEXT: .LBB7_3: # %cond.store ; AVX-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX-NEXT: testb $2, %al -; AVX-NEXT: je .LBB7_4 -; AVX-NEXT: .LBB7_3: # %cond.store1 +; AVX-NEXT: je .LBB7_2 +; AVX-NEXT: .LBB7_4: # %cond.store1 ; AVX-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX-NEXT: retq ; @@ -1930,18 +1930,18 @@ define void @truncstore_v2i64_v2i16(<2 x i64> %x, ptr %p, <2 x i64> %mask) { ; AVX512F-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7] ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB7_1 -; AVX512F-NEXT: # %bb.2: # %else -; AVX512F-NEXT: testb $2, %al ; AVX512F-NEXT: jne .LBB7_3 -; AVX512F-NEXT: .LBB7_4: # %else2 +; AVX512F-NEXT: # %bb.1: # %else +; AVX512F-NEXT: testb $2, %al +; AVX512F-NEXT: jne .LBB7_4 +; AVX512F-NEXT: .LBB7_2: # %else2 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB7_1: # %cond.store +; AVX512F-NEXT: .LBB7_3: # %cond.store ; AVX512F-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB7_4 -; AVX512F-NEXT: .LBB7_3: # %cond.store1 +; AVX512F-NEXT: je .LBB7_2 +; AVX512F-NEXT: .LBB7_4: # %cond.store1 ; AVX512F-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -1952,17 +1952,17 @@ define void @truncstore_v2i64_v2i16(<2 x i64> %x, ptr %p, <2 x i64> %mask) { ; AVX512FVL-NEXT: vpmovqw %xmm0, %xmm0 ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB7_1 -; AVX512FVL-NEXT: # %bb.2: # %else -; AVX512FVL-NEXT: testb $2, %al ; AVX512FVL-NEXT: jne .LBB7_3 -; AVX512FVL-NEXT: .LBB7_4: # %else2 +; AVX512FVL-NEXT: # %bb.1: # %else +; AVX512FVL-NEXT: testb $2, %al +; AVX512FVL-NEXT: jne .LBB7_4 +; AVX512FVL-NEXT: .LBB7_2: # %else2 ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB7_1: # %cond.store +; AVX512FVL-NEXT: .LBB7_3: # %cond.store ; AVX512FVL-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB7_4 -; AVX512FVL-NEXT: .LBB7_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB7_2 +; AVX512FVL-NEXT: .LBB7_4: # %cond.store1 ; AVX512FVL-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: retq ; @@ -2004,17 +2004,17 @@ define void @truncstore_v2i64_v2i8(<2 x i64> %x, ptr %p, <2 x i64> %mask) { ; SSE2-NEXT: xorl $3, %eax ; SSE2-NEXT: testb $1, %al ; SSE2-NEXT: movd %xmm0, %ecx -; SSE2-NEXT: jne .LBB8_1 -; SSE2-NEXT: # %bb.2: # %else -; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: jne .LBB8_3 -; SSE2-NEXT: .LBB8_4: # %else2 +; SSE2-NEXT: # %bb.1: # %else +; SSE2-NEXT: testb $2, %al +; SSE2-NEXT: jne .LBB8_4 +; SSE2-NEXT: .LBB8_2: # %else2 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB8_1: # %cond.store +; SSE2-NEXT: .LBB8_3: # %cond.store ; SSE2-NEXT: movb %cl, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB8_4 -; SSE2-NEXT: .LBB8_3: # %cond.store1 +; SSE2-NEXT: je .LBB8_2 +; SSE2-NEXT: .LBB8_4: # %cond.store1 ; SSE2-NEXT: movb %ch, 1(%rdi) ; SSE2-NEXT: retq ; @@ -2026,17 +2026,17 @@ define void @truncstore_v2i64_v2i8(<2 x i64> %x, ptr %p, <2 x i64> %mask) { ; SSE4-NEXT: movmskpd %xmm2, %eax ; SSE4-NEXT: xorl $3, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB8_1 -; SSE4-NEXT: # %bb.2: # %else -; SSE4-NEXT: testb $2, %al ; SSE4-NEXT: jne .LBB8_3 -; SSE4-NEXT: .LBB8_4: # %else2 +; SSE4-NEXT: # %bb.1: # %else +; SSE4-NEXT: testb $2, %al +; SSE4-NEXT: jne .LBB8_4 +; SSE4-NEXT: .LBB8_2: # %else2 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB8_1: # %cond.store +; SSE4-NEXT: .LBB8_3: # %cond.store ; SSE4-NEXT: pextrb $0, %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB8_4 -; SSE4-NEXT: .LBB8_3: # %cond.store1 +; SSE4-NEXT: je .LBB8_2 +; SSE4-NEXT: .LBB8_4: # %cond.store1 ; SSE4-NEXT: pextrb $1, %xmm0, 1(%rdi) ; SSE4-NEXT: retq ; @@ -2048,17 +2048,17 @@ define void @truncstore_v2i64_v2i8(<2 x i64> %x, ptr %p, <2 x i64> %mask) { ; AVX-NEXT: vmovmskpd %xmm1, %eax ; AVX-NEXT: xorl $3, %eax ; AVX-NEXT: testb $1, %al -; AVX-NEXT: jne .LBB8_1 -; AVX-NEXT: # %bb.2: # %else -; AVX-NEXT: testb $2, %al ; AVX-NEXT: jne .LBB8_3 -; AVX-NEXT: .LBB8_4: # %else2 +; AVX-NEXT: # %bb.1: # %else +; AVX-NEXT: testb $2, %al +; AVX-NEXT: jne .LBB8_4 +; AVX-NEXT: .LBB8_2: # %else2 ; AVX-NEXT: retq -; AVX-NEXT: .LBB8_1: # %cond.store +; AVX-NEXT: .LBB8_3: # %cond.store ; AVX-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX-NEXT: testb $2, %al -; AVX-NEXT: je .LBB8_4 -; AVX-NEXT: .LBB8_3: # %cond.store1 +; AVX-NEXT: je .LBB8_2 +; AVX-NEXT: .LBB8_4: # %cond.store1 ; AVX-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX-NEXT: retq ; @@ -2069,18 +2069,18 @@ define void @truncstore_v2i64_v2i8(<2 x i64> %x, ptr %p, <2 x i64> %mask) { ; AVX512F-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,8,u,u,u,u,u,u,u,u,u,u,u,u,u,u] ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB8_1 -; AVX512F-NEXT: # %bb.2: # %else -; AVX512F-NEXT: testb $2, %al ; AVX512F-NEXT: jne .LBB8_3 -; AVX512F-NEXT: .LBB8_4: # %else2 +; AVX512F-NEXT: # %bb.1: # %else +; AVX512F-NEXT: testb $2, %al +; AVX512F-NEXT: jne .LBB8_4 +; AVX512F-NEXT: .LBB8_2: # %else2 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB8_1: # %cond.store +; AVX512F-NEXT: .LBB8_3: # %cond.store ; AVX512F-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB8_4 -; AVX512F-NEXT: .LBB8_3: # %cond.store1 +; AVX512F-NEXT: je .LBB8_2 +; AVX512F-NEXT: .LBB8_4: # %cond.store1 ; AVX512F-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -2091,17 +2091,17 @@ define void @truncstore_v2i64_v2i8(<2 x i64> %x, ptr %p, <2 x i64> %mask) { ; AVX512FVL-NEXT: vpmovqb %xmm0, %xmm0 ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB8_1 -; AVX512FVL-NEXT: # %bb.2: # %else -; AVX512FVL-NEXT: testb $2, %al ; AVX512FVL-NEXT: jne .LBB8_3 -; AVX512FVL-NEXT: .LBB8_4: # %else2 +; AVX512FVL-NEXT: # %bb.1: # %else +; AVX512FVL-NEXT: testb $2, %al +; AVX512FVL-NEXT: jne .LBB8_4 +; AVX512FVL-NEXT: .LBB8_2: # %else2 ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB8_1: # %cond.store +; AVX512FVL-NEXT: .LBB8_3: # %cond.store ; AVX512FVL-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB8_4 -; AVX512FVL-NEXT: .LBB8_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB8_2 +; AVX512FVL-NEXT: .LBB8_4: # %cond.store1 ; AVX512FVL-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512FVL-NEXT: retq ; @@ -2146,130 +2146,130 @@ define void @truncstore_v16i32_v16i16(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; SSE2-NEXT: pmovmskb %xmm4, %eax ; SSE2-NEXT: xorl $65535, %eax # imm = 0xFFFF ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne .LBB9_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB9_20 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne .LBB9_3 -; SSE2-NEXT: .LBB9_4: # %else2 +; SSE2-NEXT: jne .LBB9_21 +; SSE2-NEXT: .LBB9_2: # %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne .LBB9_5 -; SSE2-NEXT: .LBB9_6: # %else4 +; SSE2-NEXT: jne .LBB9_22 +; SSE2-NEXT: .LBB9_3: # %else4 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne .LBB9_7 -; SSE2-NEXT: .LBB9_8: # %else6 +; SSE2-NEXT: jne .LBB9_23 +; SSE2-NEXT: .LBB9_4: # %else6 ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: jne .LBB9_9 -; SSE2-NEXT: .LBB9_10: # %else8 +; SSE2-NEXT: jne .LBB9_24 +; SSE2-NEXT: .LBB9_5: # %else8 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je .LBB9_12 -; SSE2-NEXT: .LBB9_11: # %cond.store9 +; SSE2-NEXT: je .LBB9_7 +; SSE2-NEXT: .LBB9_6: # %cond.store9 ; SSE2-NEXT: pextrw $5, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 10(%rdi) -; SSE2-NEXT: .LBB9_12: # %else10 +; SSE2-NEXT: .LBB9_7: # %else10 ; SSE2-NEXT: pslld $16, %xmm3 ; SSE2-NEXT: pslld $16, %xmm2 ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: je .LBB9_14 -; SSE2-NEXT: # %bb.13: # %cond.store11 +; SSE2-NEXT: je .LBB9_9 +; SSE2-NEXT: # %bb.8: # %cond.store11 ; SSE2-NEXT: pextrw $6, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 12(%rdi) -; SSE2-NEXT: .LBB9_14: # %else12 +; SSE2-NEXT: .LBB9_9: # %else12 ; SSE2-NEXT: psrad $16, %xmm3 ; SSE2-NEXT: psrad $16, %xmm2 ; SSE2-NEXT: testb %al, %al -; SSE2-NEXT: jns .LBB9_16 -; SSE2-NEXT: # %bb.15: # %cond.store13 +; SSE2-NEXT: jns .LBB9_11 +; SSE2-NEXT: # %bb.10: # %cond.store13 ; SSE2-NEXT: pextrw $7, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 14(%rdi) -; SSE2-NEXT: .LBB9_16: # %else14 +; SSE2-NEXT: .LBB9_11: # %else14 ; SSE2-NEXT: packssdw %xmm3, %xmm2 ; SSE2-NEXT: testl $256, %eax # imm = 0x100 -; SSE2-NEXT: jne .LBB9_17 -; SSE2-NEXT: # %bb.18: # %else16 +; SSE2-NEXT: jne .LBB9_25 +; SSE2-NEXT: # %bb.12: # %else16 ; SSE2-NEXT: testl $512, %eax # imm = 0x200 -; SSE2-NEXT: jne .LBB9_19 -; SSE2-NEXT: .LBB9_20: # %else18 +; SSE2-NEXT: jne .LBB9_26 +; SSE2-NEXT: .LBB9_13: # %else18 ; SSE2-NEXT: testl $1024, %eax # imm = 0x400 -; SSE2-NEXT: jne .LBB9_21 -; SSE2-NEXT: .LBB9_22: # %else20 +; SSE2-NEXT: jne .LBB9_27 +; SSE2-NEXT: .LBB9_14: # %else20 ; SSE2-NEXT: testl $2048, %eax # imm = 0x800 -; SSE2-NEXT: jne .LBB9_23 -; SSE2-NEXT: .LBB9_24: # %else22 +; SSE2-NEXT: jne .LBB9_28 +; SSE2-NEXT: .LBB9_15: # %else22 ; SSE2-NEXT: testl $4096, %eax # imm = 0x1000 -; SSE2-NEXT: jne .LBB9_25 -; SSE2-NEXT: .LBB9_26: # %else24 +; SSE2-NEXT: jne .LBB9_29 +; SSE2-NEXT: .LBB9_16: # %else24 ; SSE2-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE2-NEXT: jne .LBB9_27 -; SSE2-NEXT: .LBB9_28: # %else26 +; SSE2-NEXT: jne .LBB9_30 +; SSE2-NEXT: .LBB9_17: # %else26 ; SSE2-NEXT: testl $16384, %eax # imm = 0x4000 -; SSE2-NEXT: jne .LBB9_29 -; SSE2-NEXT: .LBB9_30: # %else28 -; SSE2-NEXT: testl $32768, %eax # imm = 0x8000 ; SSE2-NEXT: jne .LBB9_31 -; SSE2-NEXT: .LBB9_32: # %else30 +; SSE2-NEXT: .LBB9_18: # %else28 +; SSE2-NEXT: testl $32768, %eax # imm = 0x8000 +; SSE2-NEXT: jne .LBB9_32 +; SSE2-NEXT: .LBB9_19: # %else30 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB9_1: # %cond.store +; SSE2-NEXT: .LBB9_20: # %cond.store ; SSE2-NEXT: movd %xmm0, %ecx ; SSE2-NEXT: movw %cx, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB9_4 -; SSE2-NEXT: .LBB9_3: # %cond.store1 +; SSE2-NEXT: je .LBB9_2 +; SSE2-NEXT: .LBB9_21: # %cond.store1 ; SSE2-NEXT: pextrw $1, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 2(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je .LBB9_6 -; SSE2-NEXT: .LBB9_5: # %cond.store3 +; SSE2-NEXT: je .LBB9_3 +; SSE2-NEXT: .LBB9_22: # %cond.store3 ; SSE2-NEXT: pextrw $2, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 4(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je .LBB9_8 -; SSE2-NEXT: .LBB9_7: # %cond.store5 +; SSE2-NEXT: je .LBB9_4 +; SSE2-NEXT: .LBB9_23: # %cond.store5 ; SSE2-NEXT: pextrw $3, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 6(%rdi) ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: je .LBB9_10 -; SSE2-NEXT: .LBB9_9: # %cond.store7 +; SSE2-NEXT: je .LBB9_5 +; SSE2-NEXT: .LBB9_24: # %cond.store7 ; SSE2-NEXT: pextrw $4, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 8(%rdi) ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: jne .LBB9_11 -; SSE2-NEXT: jmp .LBB9_12 -; SSE2-NEXT: .LBB9_17: # %cond.store15 +; SSE2-NEXT: jne .LBB9_6 +; SSE2-NEXT: jmp .LBB9_7 +; SSE2-NEXT: .LBB9_25: # %cond.store15 ; SSE2-NEXT: movd %xmm2, %ecx ; SSE2-NEXT: movw %cx, 16(%rdi) ; SSE2-NEXT: testl $512, %eax # imm = 0x200 -; SSE2-NEXT: je .LBB9_20 -; SSE2-NEXT: .LBB9_19: # %cond.store17 +; SSE2-NEXT: je .LBB9_13 +; SSE2-NEXT: .LBB9_26: # %cond.store17 ; SSE2-NEXT: pextrw $1, %xmm2, %ecx ; SSE2-NEXT: movw %cx, 18(%rdi) ; SSE2-NEXT: testl $1024, %eax # imm = 0x400 -; SSE2-NEXT: je .LBB9_22 -; SSE2-NEXT: .LBB9_21: # %cond.store19 +; SSE2-NEXT: je .LBB9_14 +; SSE2-NEXT: .LBB9_27: # %cond.store19 ; SSE2-NEXT: pextrw $2, %xmm2, %ecx ; SSE2-NEXT: movw %cx, 20(%rdi) ; SSE2-NEXT: testl $2048, %eax # imm = 0x800 -; SSE2-NEXT: je .LBB9_24 -; SSE2-NEXT: .LBB9_23: # %cond.store21 +; SSE2-NEXT: je .LBB9_15 +; SSE2-NEXT: .LBB9_28: # %cond.store21 ; SSE2-NEXT: pextrw $3, %xmm2, %ecx ; SSE2-NEXT: movw %cx, 22(%rdi) ; SSE2-NEXT: testl $4096, %eax # imm = 0x1000 -; SSE2-NEXT: je .LBB9_26 -; SSE2-NEXT: .LBB9_25: # %cond.store23 +; SSE2-NEXT: je .LBB9_16 +; SSE2-NEXT: .LBB9_29: # %cond.store23 ; SSE2-NEXT: pextrw $4, %xmm2, %ecx ; SSE2-NEXT: movw %cx, 24(%rdi) ; SSE2-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE2-NEXT: je .LBB9_28 -; SSE2-NEXT: .LBB9_27: # %cond.store25 +; SSE2-NEXT: je .LBB9_17 +; SSE2-NEXT: .LBB9_30: # %cond.store25 ; SSE2-NEXT: pextrw $5, %xmm2, %ecx ; SSE2-NEXT: movw %cx, 26(%rdi) ; SSE2-NEXT: testl $16384, %eax # imm = 0x4000 -; SSE2-NEXT: je .LBB9_30 -; SSE2-NEXT: .LBB9_29: # %cond.store27 +; SSE2-NEXT: je .LBB9_18 +; SSE2-NEXT: .LBB9_31: # %cond.store27 ; SSE2-NEXT: pextrw $6, %xmm2, %ecx ; SSE2-NEXT: movw %cx, 28(%rdi) ; SSE2-NEXT: testl $32768, %eax # imm = 0x8000 -; SSE2-NEXT: je .LBB9_32 -; SSE2-NEXT: .LBB9_31: # %cond.store29 +; SSE2-NEXT: je .LBB9_19 +; SSE2-NEXT: .LBB9_32: # %cond.store29 ; SSE2-NEXT: pextrw $7, %xmm2, %eax ; SSE2-NEXT: movw %ax, 30(%rdi) ; SSE2-NEXT: retq @@ -2290,115 +2290,115 @@ define void @truncstore_v16i32_v16i16(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; SSE4-NEXT: pmovmskb %xmm4, %eax ; SSE4-NEXT: xorl $65535, %eax # imm = 0xFFFF ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB9_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB9_19 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB9_3 -; SSE4-NEXT: .LBB9_4: # %else2 +; SSE4-NEXT: jne .LBB9_20 +; SSE4-NEXT: .LBB9_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB9_5 -; SSE4-NEXT: .LBB9_6: # %else4 +; SSE4-NEXT: jne .LBB9_21 +; SSE4-NEXT: .LBB9_3: # %else4 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne .LBB9_7 -; SSE4-NEXT: .LBB9_8: # %else6 +; SSE4-NEXT: jne .LBB9_22 +; SSE4-NEXT: .LBB9_4: # %else6 ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: jne .LBB9_9 -; SSE4-NEXT: .LBB9_10: # %else8 +; SSE4-NEXT: jne .LBB9_23 +; SSE4-NEXT: .LBB9_5: # %else8 ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: jne .LBB9_11 -; SSE4-NEXT: .LBB9_12: # %else10 +; SSE4-NEXT: jne .LBB9_24 +; SSE4-NEXT: .LBB9_6: # %else10 ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: je .LBB9_14 -; SSE4-NEXT: .LBB9_13: # %cond.store11 +; SSE4-NEXT: je .LBB9_8 +; SSE4-NEXT: .LBB9_7: # %cond.store11 ; SSE4-NEXT: pextrw $6, %xmm0, 12(%rdi) -; SSE4-NEXT: .LBB9_14: # %else12 +; SSE4-NEXT: .LBB9_8: # %else12 ; SSE4-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0],xmm8[1],xmm3[2],xmm8[3],xmm3[4],xmm8[5],xmm3[6],xmm8[7] ; SSE4-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0],xmm8[1],xmm2[2],xmm8[3],xmm2[4],xmm8[5],xmm2[6],xmm8[7] ; SSE4-NEXT: testb %al, %al -; SSE4-NEXT: jns .LBB9_16 -; SSE4-NEXT: # %bb.15: # %cond.store13 +; SSE4-NEXT: jns .LBB9_10 +; SSE4-NEXT: # %bb.9: # %cond.store13 ; SSE4-NEXT: pextrw $7, %xmm0, 14(%rdi) -; SSE4-NEXT: .LBB9_16: # %else14 +; SSE4-NEXT: .LBB9_10: # %else14 ; SSE4-NEXT: packusdw %xmm3, %xmm2 ; SSE4-NEXT: testl $256, %eax # imm = 0x100 -; SSE4-NEXT: jne .LBB9_17 -; SSE4-NEXT: # %bb.18: # %else16 +; SSE4-NEXT: jne .LBB9_25 +; SSE4-NEXT: # %bb.11: # %else16 ; SSE4-NEXT: testl $512, %eax # imm = 0x200 -; SSE4-NEXT: jne .LBB9_19 -; SSE4-NEXT: .LBB9_20: # %else18 +; SSE4-NEXT: jne .LBB9_26 +; SSE4-NEXT: .LBB9_12: # %else18 ; SSE4-NEXT: testl $1024, %eax # imm = 0x400 -; SSE4-NEXT: jne .LBB9_21 -; SSE4-NEXT: .LBB9_22: # %else20 +; SSE4-NEXT: jne .LBB9_27 +; SSE4-NEXT: .LBB9_13: # %else20 ; SSE4-NEXT: testl $2048, %eax # imm = 0x800 -; SSE4-NEXT: jne .LBB9_23 -; SSE4-NEXT: .LBB9_24: # %else22 +; SSE4-NEXT: jne .LBB9_28 +; SSE4-NEXT: .LBB9_14: # %else22 ; SSE4-NEXT: testl $4096, %eax # imm = 0x1000 -; SSE4-NEXT: jne .LBB9_25 -; SSE4-NEXT: .LBB9_26: # %else24 +; SSE4-NEXT: jne .LBB9_29 +; SSE4-NEXT: .LBB9_15: # %else24 ; SSE4-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE4-NEXT: jne .LBB9_27 -; SSE4-NEXT: .LBB9_28: # %else26 +; SSE4-NEXT: jne .LBB9_30 +; SSE4-NEXT: .LBB9_16: # %else26 ; SSE4-NEXT: testl $16384, %eax # imm = 0x4000 -; SSE4-NEXT: jne .LBB9_29 -; SSE4-NEXT: .LBB9_30: # %else28 -; SSE4-NEXT: testl $32768, %eax # imm = 0x8000 ; SSE4-NEXT: jne .LBB9_31 -; SSE4-NEXT: .LBB9_32: # %else30 +; SSE4-NEXT: .LBB9_17: # %else28 +; SSE4-NEXT: testl $32768, %eax # imm = 0x8000 +; SSE4-NEXT: jne .LBB9_32 +; SSE4-NEXT: .LBB9_18: # %else30 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB9_1: # %cond.store +; SSE4-NEXT: .LBB9_19: # %cond.store ; SSE4-NEXT: pextrw $0, %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB9_4 -; SSE4-NEXT: .LBB9_3: # %cond.store1 +; SSE4-NEXT: je .LBB9_2 +; SSE4-NEXT: .LBB9_20: # %cond.store1 ; SSE4-NEXT: pextrw $1, %xmm0, 2(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB9_6 -; SSE4-NEXT: .LBB9_5: # %cond.store3 +; SSE4-NEXT: je .LBB9_3 +; SSE4-NEXT: .LBB9_21: # %cond.store3 ; SSE4-NEXT: pextrw $2, %xmm0, 4(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB9_8 -; SSE4-NEXT: .LBB9_7: # %cond.store5 +; SSE4-NEXT: je .LBB9_4 +; SSE4-NEXT: .LBB9_22: # %cond.store5 ; SSE4-NEXT: pextrw $3, %xmm0, 6(%rdi) ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: je .LBB9_10 -; SSE4-NEXT: .LBB9_9: # %cond.store7 +; SSE4-NEXT: je .LBB9_5 +; SSE4-NEXT: .LBB9_23: # %cond.store7 ; SSE4-NEXT: pextrw $4, %xmm0, 8(%rdi) ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: je .LBB9_12 -; SSE4-NEXT: .LBB9_11: # %cond.store9 +; SSE4-NEXT: je .LBB9_6 +; SSE4-NEXT: .LBB9_24: # %cond.store9 ; SSE4-NEXT: pextrw $5, %xmm0, 10(%rdi) ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: jne .LBB9_13 -; SSE4-NEXT: jmp .LBB9_14 -; SSE4-NEXT: .LBB9_17: # %cond.store15 +; SSE4-NEXT: jne .LBB9_7 +; SSE4-NEXT: jmp .LBB9_8 +; SSE4-NEXT: .LBB9_25: # %cond.store15 ; SSE4-NEXT: pextrw $0, %xmm2, 16(%rdi) ; SSE4-NEXT: testl $512, %eax # imm = 0x200 -; SSE4-NEXT: je .LBB9_20 -; SSE4-NEXT: .LBB9_19: # %cond.store17 +; SSE4-NEXT: je .LBB9_12 +; SSE4-NEXT: .LBB9_26: # %cond.store17 ; SSE4-NEXT: pextrw $1, %xmm2, 18(%rdi) ; SSE4-NEXT: testl $1024, %eax # imm = 0x400 -; SSE4-NEXT: je .LBB9_22 -; SSE4-NEXT: .LBB9_21: # %cond.store19 +; SSE4-NEXT: je .LBB9_13 +; SSE4-NEXT: .LBB9_27: # %cond.store19 ; SSE4-NEXT: pextrw $2, %xmm2, 20(%rdi) ; SSE4-NEXT: testl $2048, %eax # imm = 0x800 -; SSE4-NEXT: je .LBB9_24 -; SSE4-NEXT: .LBB9_23: # %cond.store21 +; SSE4-NEXT: je .LBB9_14 +; SSE4-NEXT: .LBB9_28: # %cond.store21 ; SSE4-NEXT: pextrw $3, %xmm2, 22(%rdi) ; SSE4-NEXT: testl $4096, %eax # imm = 0x1000 -; SSE4-NEXT: je .LBB9_26 -; SSE4-NEXT: .LBB9_25: # %cond.store23 +; SSE4-NEXT: je .LBB9_15 +; SSE4-NEXT: .LBB9_29: # %cond.store23 ; SSE4-NEXT: pextrw $4, %xmm2, 24(%rdi) ; SSE4-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE4-NEXT: je .LBB9_28 -; SSE4-NEXT: .LBB9_27: # %cond.store25 +; SSE4-NEXT: je .LBB9_16 +; SSE4-NEXT: .LBB9_30: # %cond.store25 ; SSE4-NEXT: pextrw $5, %xmm2, 26(%rdi) ; SSE4-NEXT: testl $16384, %eax # imm = 0x4000 -; SSE4-NEXT: je .LBB9_30 -; SSE4-NEXT: .LBB9_29: # %cond.store27 +; SSE4-NEXT: je .LBB9_17 +; SSE4-NEXT: .LBB9_31: # %cond.store27 ; SSE4-NEXT: pextrw $6, %xmm2, 28(%rdi) ; SSE4-NEXT: testl $32768, %eax # imm = 0x8000 -; SSE4-NEXT: je .LBB9_32 -; SSE4-NEXT: .LBB9_31: # %cond.store29 +; SSE4-NEXT: je .LBB9_18 +; SSE4-NEXT: .LBB9_32: # %cond.store29 ; SSE4-NEXT: pextrw $7, %xmm2, 30(%rdi) ; SSE4-NEXT: retq ; @@ -2425,116 +2425,116 @@ define void @truncstore_v16i32_v16i16(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; AVX1-NEXT: vpmovmskb %xmm1, %eax ; AVX1-NEXT: xorl $65535, %eax # imm = 0xFFFF ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne .LBB9_1 -; AVX1-NEXT: # %bb.2: # %else +; AVX1-NEXT: jne .LBB9_18 +; AVX1-NEXT: # %bb.1: # %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne .LBB9_3 -; AVX1-NEXT: .LBB9_4: # %else2 +; AVX1-NEXT: jne .LBB9_19 +; AVX1-NEXT: .LBB9_2: # %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne .LBB9_5 -; AVX1-NEXT: .LBB9_6: # %else4 +; AVX1-NEXT: jne .LBB9_20 +; AVX1-NEXT: .LBB9_3: # %else4 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne .LBB9_7 -; AVX1-NEXT: .LBB9_8: # %else6 +; AVX1-NEXT: jne .LBB9_21 +; AVX1-NEXT: .LBB9_4: # %else6 ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: jne .LBB9_9 -; AVX1-NEXT: .LBB9_10: # %else8 +; AVX1-NEXT: jne .LBB9_22 +; AVX1-NEXT: .LBB9_5: # %else8 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: jne .LBB9_11 -; AVX1-NEXT: .LBB9_12: # %else10 +; AVX1-NEXT: jne .LBB9_23 +; AVX1-NEXT: .LBB9_6: # %else10 ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: jne .LBB9_13 -; AVX1-NEXT: .LBB9_14: # %else12 +; AVX1-NEXT: jne .LBB9_24 +; AVX1-NEXT: .LBB9_7: # %else12 ; AVX1-NEXT: testb %al, %al -; AVX1-NEXT: jns .LBB9_16 -; AVX1-NEXT: .LBB9_15: # %cond.store13 +; AVX1-NEXT: jns .LBB9_9 +; AVX1-NEXT: .LBB9_8: # %cond.store13 ; AVX1-NEXT: vpextrw $7, %xmm0, 14(%rdi) -; AVX1-NEXT: .LBB9_16: # %else14 +; AVX1-NEXT: .LBB9_9: # %else14 ; AVX1-NEXT: testl $256, %eax # imm = 0x100 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 -; AVX1-NEXT: jne .LBB9_17 -; AVX1-NEXT: # %bb.18: # %else16 +; AVX1-NEXT: jne .LBB9_25 +; AVX1-NEXT: # %bb.10: # %else16 ; AVX1-NEXT: testl $512, %eax # imm = 0x200 -; AVX1-NEXT: jne .LBB9_19 -; AVX1-NEXT: .LBB9_20: # %else18 +; AVX1-NEXT: jne .LBB9_26 +; AVX1-NEXT: .LBB9_11: # %else18 ; AVX1-NEXT: testl $1024, %eax # imm = 0x400 -; AVX1-NEXT: jne .LBB9_21 -; AVX1-NEXT: .LBB9_22: # %else20 +; AVX1-NEXT: jne .LBB9_27 +; AVX1-NEXT: .LBB9_12: # %else20 ; AVX1-NEXT: testl $2048, %eax # imm = 0x800 -; AVX1-NEXT: jne .LBB9_23 -; AVX1-NEXT: .LBB9_24: # %else22 +; AVX1-NEXT: jne .LBB9_28 +; AVX1-NEXT: .LBB9_13: # %else22 ; AVX1-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX1-NEXT: jne .LBB9_25 -; AVX1-NEXT: .LBB9_26: # %else24 +; AVX1-NEXT: jne .LBB9_29 +; AVX1-NEXT: .LBB9_14: # %else24 ; AVX1-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX1-NEXT: jne .LBB9_27 -; AVX1-NEXT: .LBB9_28: # %else26 +; AVX1-NEXT: jne .LBB9_30 +; AVX1-NEXT: .LBB9_15: # %else26 ; AVX1-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX1-NEXT: jne .LBB9_29 -; AVX1-NEXT: .LBB9_30: # %else28 -; AVX1-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX1-NEXT: jne .LBB9_31 -; AVX1-NEXT: .LBB9_32: # %else30 +; AVX1-NEXT: .LBB9_16: # %else28 +; AVX1-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX1-NEXT: jne .LBB9_32 +; AVX1-NEXT: .LBB9_17: # %else30 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB9_1: # %cond.store +; AVX1-NEXT: .LBB9_18: # %cond.store ; AVX1-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je .LBB9_4 -; AVX1-NEXT: .LBB9_3: # %cond.store1 +; AVX1-NEXT: je .LBB9_2 +; AVX1-NEXT: .LBB9_19: # %cond.store1 ; AVX1-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je .LBB9_6 -; AVX1-NEXT: .LBB9_5: # %cond.store3 +; AVX1-NEXT: je .LBB9_3 +; AVX1-NEXT: .LBB9_20: # %cond.store3 ; AVX1-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB9_8 -; AVX1-NEXT: .LBB9_7: # %cond.store5 +; AVX1-NEXT: je .LBB9_4 +; AVX1-NEXT: .LBB9_21: # %cond.store5 ; AVX1-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: je .LBB9_10 -; AVX1-NEXT: .LBB9_9: # %cond.store7 +; AVX1-NEXT: je .LBB9_5 +; AVX1-NEXT: .LBB9_22: # %cond.store7 ; AVX1-NEXT: vpextrw $4, %xmm0, 8(%rdi) ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je .LBB9_12 -; AVX1-NEXT: .LBB9_11: # %cond.store9 +; AVX1-NEXT: je .LBB9_6 +; AVX1-NEXT: .LBB9_23: # %cond.store9 ; AVX1-NEXT: vpextrw $5, %xmm0, 10(%rdi) ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: je .LBB9_14 -; AVX1-NEXT: .LBB9_13: # %cond.store11 +; AVX1-NEXT: je .LBB9_7 +; AVX1-NEXT: .LBB9_24: # %cond.store11 ; AVX1-NEXT: vpextrw $6, %xmm0, 12(%rdi) ; AVX1-NEXT: testb %al, %al -; AVX1-NEXT: js .LBB9_15 -; AVX1-NEXT: jmp .LBB9_16 -; AVX1-NEXT: .LBB9_17: # %cond.store15 +; AVX1-NEXT: js .LBB9_8 +; AVX1-NEXT: jmp .LBB9_9 +; AVX1-NEXT: .LBB9_25: # %cond.store15 ; AVX1-NEXT: vpextrw $0, %xmm0, 16(%rdi) ; AVX1-NEXT: testl $512, %eax # imm = 0x200 -; AVX1-NEXT: je .LBB9_20 -; AVX1-NEXT: .LBB9_19: # %cond.store17 +; AVX1-NEXT: je .LBB9_11 +; AVX1-NEXT: .LBB9_26: # %cond.store17 ; AVX1-NEXT: vpextrw $1, %xmm0, 18(%rdi) ; AVX1-NEXT: testl $1024, %eax # imm = 0x400 -; AVX1-NEXT: je .LBB9_22 -; AVX1-NEXT: .LBB9_21: # %cond.store19 +; AVX1-NEXT: je .LBB9_12 +; AVX1-NEXT: .LBB9_27: # %cond.store19 ; AVX1-NEXT: vpextrw $2, %xmm0, 20(%rdi) ; AVX1-NEXT: testl $2048, %eax # imm = 0x800 -; AVX1-NEXT: je .LBB9_24 -; AVX1-NEXT: .LBB9_23: # %cond.store21 +; AVX1-NEXT: je .LBB9_13 +; AVX1-NEXT: .LBB9_28: # %cond.store21 ; AVX1-NEXT: vpextrw $3, %xmm0, 22(%rdi) ; AVX1-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX1-NEXT: je .LBB9_26 -; AVX1-NEXT: .LBB9_25: # %cond.store23 +; AVX1-NEXT: je .LBB9_14 +; AVX1-NEXT: .LBB9_29: # %cond.store23 ; AVX1-NEXT: vpextrw $4, %xmm0, 24(%rdi) ; AVX1-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX1-NEXT: je .LBB9_28 -; AVX1-NEXT: .LBB9_27: # %cond.store25 +; AVX1-NEXT: je .LBB9_15 +; AVX1-NEXT: .LBB9_30: # %cond.store25 ; AVX1-NEXT: vpextrw $5, %xmm0, 26(%rdi) ; AVX1-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX1-NEXT: je .LBB9_30 -; AVX1-NEXT: .LBB9_29: # %cond.store27 +; AVX1-NEXT: je .LBB9_16 +; AVX1-NEXT: .LBB9_31: # %cond.store27 ; AVX1-NEXT: vpextrw $6, %xmm0, 28(%rdi) ; AVX1-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX1-NEXT: je .LBB9_32 -; AVX1-NEXT: .LBB9_31: # %cond.store29 +; AVX1-NEXT: je .LBB9_17 +; AVX1-NEXT: .LBB9_32: # %cond.store29 ; AVX1-NEXT: vpextrw $7, %xmm0, 30(%rdi) ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq @@ -2556,116 +2556,116 @@ define void @truncstore_v16i32_v16i16(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,2,1,3] ; AVX2-NEXT: vpmovmskb %xmm1, %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne .LBB9_1 -; AVX2-NEXT: # %bb.2: # %else +; AVX2-NEXT: jne .LBB9_18 +; AVX2-NEXT: # %bb.1: # %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne .LBB9_3 -; AVX2-NEXT: .LBB9_4: # %else2 +; AVX2-NEXT: jne .LBB9_19 +; AVX2-NEXT: .LBB9_2: # %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne .LBB9_5 -; AVX2-NEXT: .LBB9_6: # %else4 +; AVX2-NEXT: jne .LBB9_20 +; AVX2-NEXT: .LBB9_3: # %else4 ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: jne .LBB9_7 -; AVX2-NEXT: .LBB9_8: # %else6 +; AVX2-NEXT: jne .LBB9_21 +; AVX2-NEXT: .LBB9_4: # %else6 ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: jne .LBB9_9 -; AVX2-NEXT: .LBB9_10: # %else8 +; AVX2-NEXT: jne .LBB9_22 +; AVX2-NEXT: .LBB9_5: # %else8 ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: jne .LBB9_11 -; AVX2-NEXT: .LBB9_12: # %else10 +; AVX2-NEXT: jne .LBB9_23 +; AVX2-NEXT: .LBB9_6: # %else10 ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: jne .LBB9_13 -; AVX2-NEXT: .LBB9_14: # %else12 +; AVX2-NEXT: jne .LBB9_24 +; AVX2-NEXT: .LBB9_7: # %else12 ; AVX2-NEXT: testb %al, %al -; AVX2-NEXT: jns .LBB9_16 -; AVX2-NEXT: .LBB9_15: # %cond.store13 +; AVX2-NEXT: jns .LBB9_9 +; AVX2-NEXT: .LBB9_8: # %cond.store13 ; AVX2-NEXT: vpextrw $7, %xmm0, 14(%rdi) -; AVX2-NEXT: .LBB9_16: # %else14 +; AVX2-NEXT: .LBB9_9: # %else14 ; AVX2-NEXT: testl $256, %eax # imm = 0x100 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0 -; AVX2-NEXT: jne .LBB9_17 -; AVX2-NEXT: # %bb.18: # %else16 +; AVX2-NEXT: jne .LBB9_25 +; AVX2-NEXT: # %bb.10: # %else16 ; AVX2-NEXT: testl $512, %eax # imm = 0x200 -; AVX2-NEXT: jne .LBB9_19 -; AVX2-NEXT: .LBB9_20: # %else18 +; AVX2-NEXT: jne .LBB9_26 +; AVX2-NEXT: .LBB9_11: # %else18 ; AVX2-NEXT: testl $1024, %eax # imm = 0x400 -; AVX2-NEXT: jne .LBB9_21 -; AVX2-NEXT: .LBB9_22: # %else20 +; AVX2-NEXT: jne .LBB9_27 +; AVX2-NEXT: .LBB9_12: # %else20 ; AVX2-NEXT: testl $2048, %eax # imm = 0x800 -; AVX2-NEXT: jne .LBB9_23 -; AVX2-NEXT: .LBB9_24: # %else22 +; AVX2-NEXT: jne .LBB9_28 +; AVX2-NEXT: .LBB9_13: # %else22 ; AVX2-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX2-NEXT: jne .LBB9_25 -; AVX2-NEXT: .LBB9_26: # %else24 +; AVX2-NEXT: jne .LBB9_29 +; AVX2-NEXT: .LBB9_14: # %else24 ; AVX2-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX2-NEXT: jne .LBB9_27 -; AVX2-NEXT: .LBB9_28: # %else26 +; AVX2-NEXT: jne .LBB9_30 +; AVX2-NEXT: .LBB9_15: # %else26 ; AVX2-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX2-NEXT: jne .LBB9_29 -; AVX2-NEXT: .LBB9_30: # %else28 -; AVX2-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX2-NEXT: jne .LBB9_31 -; AVX2-NEXT: .LBB9_32: # %else30 +; AVX2-NEXT: .LBB9_16: # %else28 +; AVX2-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX2-NEXT: jne .LBB9_32 +; AVX2-NEXT: .LBB9_17: # %else30 ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; AVX2-NEXT: .LBB9_1: # %cond.store +; AVX2-NEXT: .LBB9_18: # %cond.store ; AVX2-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je .LBB9_4 -; AVX2-NEXT: .LBB9_3: # %cond.store1 +; AVX2-NEXT: je .LBB9_2 +; AVX2-NEXT: .LBB9_19: # %cond.store1 ; AVX2-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je .LBB9_6 -; AVX2-NEXT: .LBB9_5: # %cond.store3 +; AVX2-NEXT: je .LBB9_3 +; AVX2-NEXT: .LBB9_20: # %cond.store3 ; AVX2-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je .LBB9_8 -; AVX2-NEXT: .LBB9_7: # %cond.store5 +; AVX2-NEXT: je .LBB9_4 +; AVX2-NEXT: .LBB9_21: # %cond.store5 ; AVX2-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: je .LBB9_10 -; AVX2-NEXT: .LBB9_9: # %cond.store7 +; AVX2-NEXT: je .LBB9_5 +; AVX2-NEXT: .LBB9_22: # %cond.store7 ; AVX2-NEXT: vpextrw $4, %xmm0, 8(%rdi) ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: je .LBB9_12 -; AVX2-NEXT: .LBB9_11: # %cond.store9 +; AVX2-NEXT: je .LBB9_6 +; AVX2-NEXT: .LBB9_23: # %cond.store9 ; AVX2-NEXT: vpextrw $5, %xmm0, 10(%rdi) ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: je .LBB9_14 -; AVX2-NEXT: .LBB9_13: # %cond.store11 +; AVX2-NEXT: je .LBB9_7 +; AVX2-NEXT: .LBB9_24: # %cond.store11 ; AVX2-NEXT: vpextrw $6, %xmm0, 12(%rdi) ; AVX2-NEXT: testb %al, %al -; AVX2-NEXT: js .LBB9_15 -; AVX2-NEXT: jmp .LBB9_16 -; AVX2-NEXT: .LBB9_17: # %cond.store15 +; AVX2-NEXT: js .LBB9_8 +; AVX2-NEXT: jmp .LBB9_9 +; AVX2-NEXT: .LBB9_25: # %cond.store15 ; AVX2-NEXT: vpextrw $0, %xmm0, 16(%rdi) ; AVX2-NEXT: testl $512, %eax # imm = 0x200 -; AVX2-NEXT: je .LBB9_20 -; AVX2-NEXT: .LBB9_19: # %cond.store17 +; AVX2-NEXT: je .LBB9_11 +; AVX2-NEXT: .LBB9_26: # %cond.store17 ; AVX2-NEXT: vpextrw $1, %xmm0, 18(%rdi) ; AVX2-NEXT: testl $1024, %eax # imm = 0x400 -; AVX2-NEXT: je .LBB9_22 -; AVX2-NEXT: .LBB9_21: # %cond.store19 +; AVX2-NEXT: je .LBB9_12 +; AVX2-NEXT: .LBB9_27: # %cond.store19 ; AVX2-NEXT: vpextrw $2, %xmm0, 20(%rdi) ; AVX2-NEXT: testl $2048, %eax # imm = 0x800 -; AVX2-NEXT: je .LBB9_24 -; AVX2-NEXT: .LBB9_23: # %cond.store21 +; AVX2-NEXT: je .LBB9_13 +; AVX2-NEXT: .LBB9_28: # %cond.store21 ; AVX2-NEXT: vpextrw $3, %xmm0, 22(%rdi) ; AVX2-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX2-NEXT: je .LBB9_26 -; AVX2-NEXT: .LBB9_25: # %cond.store23 +; AVX2-NEXT: je .LBB9_14 +; AVX2-NEXT: .LBB9_29: # %cond.store23 ; AVX2-NEXT: vpextrw $4, %xmm0, 24(%rdi) ; AVX2-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX2-NEXT: je .LBB9_28 -; AVX2-NEXT: .LBB9_27: # %cond.store25 +; AVX2-NEXT: je .LBB9_15 +; AVX2-NEXT: .LBB9_30: # %cond.store25 ; AVX2-NEXT: vpextrw $5, %xmm0, 26(%rdi) ; AVX2-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX2-NEXT: je .LBB9_30 -; AVX2-NEXT: .LBB9_29: # %cond.store27 +; AVX2-NEXT: je .LBB9_16 +; AVX2-NEXT: .LBB9_31: # %cond.store27 ; AVX2-NEXT: vpextrw $6, %xmm0, 28(%rdi) ; AVX2-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX2-NEXT: je .LBB9_32 -; AVX2-NEXT: .LBB9_31: # %cond.store29 +; AVX2-NEXT: je .LBB9_17 +; AVX2-NEXT: .LBB9_32: # %cond.store29 ; AVX2-NEXT: vpextrw $7, %xmm0, 30(%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq @@ -2676,116 +2676,116 @@ define void @truncstore_v16i32_v16i16(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; AVX512F-NEXT: vpmovdw %zmm0, %ymm0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB9_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB9_18 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB9_3 -; AVX512F-NEXT: .LBB9_4: # %else2 +; AVX512F-NEXT: jne .LBB9_19 +; AVX512F-NEXT: .LBB9_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB9_5 -; AVX512F-NEXT: .LBB9_6: # %else4 +; AVX512F-NEXT: jne .LBB9_20 +; AVX512F-NEXT: .LBB9_3: # %else4 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne .LBB9_7 -; AVX512F-NEXT: .LBB9_8: # %else6 +; AVX512F-NEXT: jne .LBB9_21 +; AVX512F-NEXT: .LBB9_4: # %else6 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne .LBB9_9 -; AVX512F-NEXT: .LBB9_10: # %else8 +; AVX512F-NEXT: jne .LBB9_22 +; AVX512F-NEXT: .LBB9_5: # %else8 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne .LBB9_11 -; AVX512F-NEXT: .LBB9_12: # %else10 +; AVX512F-NEXT: jne .LBB9_23 +; AVX512F-NEXT: .LBB9_6: # %else10 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne .LBB9_13 -; AVX512F-NEXT: .LBB9_14: # %else12 +; AVX512F-NEXT: jne .LBB9_24 +; AVX512F-NEXT: .LBB9_7: # %else12 ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: jns .LBB9_16 -; AVX512F-NEXT: .LBB9_15: # %cond.store13 +; AVX512F-NEXT: jns .LBB9_9 +; AVX512F-NEXT: .LBB9_8: # %cond.store13 ; AVX512F-NEXT: vpextrw $7, %xmm0, 14(%rdi) -; AVX512F-NEXT: .LBB9_16: # %else14 +; AVX512F-NEXT: .LBB9_9: # %else14 ; AVX512F-NEXT: testl $256, %eax # imm = 0x100 ; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm0 -; AVX512F-NEXT: jne .LBB9_17 -; AVX512F-NEXT: # %bb.18: # %else16 +; AVX512F-NEXT: jne .LBB9_25 +; AVX512F-NEXT: # %bb.10: # %else16 ; AVX512F-NEXT: testl $512, %eax # imm = 0x200 -; AVX512F-NEXT: jne .LBB9_19 -; AVX512F-NEXT: .LBB9_20: # %else18 +; AVX512F-NEXT: jne .LBB9_26 +; AVX512F-NEXT: .LBB9_11: # %else18 ; AVX512F-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512F-NEXT: jne .LBB9_21 -; AVX512F-NEXT: .LBB9_22: # %else20 +; AVX512F-NEXT: jne .LBB9_27 +; AVX512F-NEXT: .LBB9_12: # %else20 ; AVX512F-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512F-NEXT: jne .LBB9_23 -; AVX512F-NEXT: .LBB9_24: # %else22 +; AVX512F-NEXT: jne .LBB9_28 +; AVX512F-NEXT: .LBB9_13: # %else22 ; AVX512F-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512F-NEXT: jne .LBB9_25 -; AVX512F-NEXT: .LBB9_26: # %else24 +; AVX512F-NEXT: jne .LBB9_29 +; AVX512F-NEXT: .LBB9_14: # %else24 ; AVX512F-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512F-NEXT: jne .LBB9_27 -; AVX512F-NEXT: .LBB9_28: # %else26 +; AVX512F-NEXT: jne .LBB9_30 +; AVX512F-NEXT: .LBB9_15: # %else26 ; AVX512F-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512F-NEXT: jne .LBB9_29 -; AVX512F-NEXT: .LBB9_30: # %else28 -; AVX512F-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX512F-NEXT: jne .LBB9_31 -; AVX512F-NEXT: .LBB9_32: # %else30 +; AVX512F-NEXT: .LBB9_16: # %else28 +; AVX512F-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX512F-NEXT: jne .LBB9_32 +; AVX512F-NEXT: .LBB9_17: # %else30 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB9_1: # %cond.store +; AVX512F-NEXT: .LBB9_18: # %cond.store ; AVX512F-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB9_4 -; AVX512F-NEXT: .LBB9_3: # %cond.store1 +; AVX512F-NEXT: je .LBB9_2 +; AVX512F-NEXT: .LBB9_19: # %cond.store1 ; AVX512F-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB9_6 -; AVX512F-NEXT: .LBB9_5: # %cond.store3 +; AVX512F-NEXT: je .LBB9_3 +; AVX512F-NEXT: .LBB9_20: # %cond.store3 ; AVX512F-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB9_8 -; AVX512F-NEXT: .LBB9_7: # %cond.store5 +; AVX512F-NEXT: je .LBB9_4 +; AVX512F-NEXT: .LBB9_21: # %cond.store5 ; AVX512F-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je .LBB9_10 -; AVX512F-NEXT: .LBB9_9: # %cond.store7 +; AVX512F-NEXT: je .LBB9_5 +; AVX512F-NEXT: .LBB9_22: # %cond.store7 ; AVX512F-NEXT: vpextrw $4, %xmm0, 8(%rdi) ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je .LBB9_12 -; AVX512F-NEXT: .LBB9_11: # %cond.store9 +; AVX512F-NEXT: je .LBB9_6 +; AVX512F-NEXT: .LBB9_23: # %cond.store9 ; AVX512F-NEXT: vpextrw $5, %xmm0, 10(%rdi) ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je .LBB9_14 -; AVX512F-NEXT: .LBB9_13: # %cond.store11 +; AVX512F-NEXT: je .LBB9_7 +; AVX512F-NEXT: .LBB9_24: # %cond.store11 ; AVX512F-NEXT: vpextrw $6, %xmm0, 12(%rdi) ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: js .LBB9_15 -; AVX512F-NEXT: jmp .LBB9_16 -; AVX512F-NEXT: .LBB9_17: # %cond.store15 +; AVX512F-NEXT: js .LBB9_8 +; AVX512F-NEXT: jmp .LBB9_9 +; AVX512F-NEXT: .LBB9_25: # %cond.store15 ; AVX512F-NEXT: vpextrw $0, %xmm0, 16(%rdi) ; AVX512F-NEXT: testl $512, %eax # imm = 0x200 -; AVX512F-NEXT: je .LBB9_20 -; AVX512F-NEXT: .LBB9_19: # %cond.store17 +; AVX512F-NEXT: je .LBB9_11 +; AVX512F-NEXT: .LBB9_26: # %cond.store17 ; AVX512F-NEXT: vpextrw $1, %xmm0, 18(%rdi) ; AVX512F-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512F-NEXT: je .LBB9_22 -; AVX512F-NEXT: .LBB9_21: # %cond.store19 +; AVX512F-NEXT: je .LBB9_12 +; AVX512F-NEXT: .LBB9_27: # %cond.store19 ; AVX512F-NEXT: vpextrw $2, %xmm0, 20(%rdi) ; AVX512F-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512F-NEXT: je .LBB9_24 -; AVX512F-NEXT: .LBB9_23: # %cond.store21 +; AVX512F-NEXT: je .LBB9_13 +; AVX512F-NEXT: .LBB9_28: # %cond.store21 ; AVX512F-NEXT: vpextrw $3, %xmm0, 22(%rdi) ; AVX512F-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512F-NEXT: je .LBB9_26 -; AVX512F-NEXT: .LBB9_25: # %cond.store23 +; AVX512F-NEXT: je .LBB9_14 +; AVX512F-NEXT: .LBB9_29: # %cond.store23 ; AVX512F-NEXT: vpextrw $4, %xmm0, 24(%rdi) ; AVX512F-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512F-NEXT: je .LBB9_28 -; AVX512F-NEXT: .LBB9_27: # %cond.store25 +; AVX512F-NEXT: je .LBB9_15 +; AVX512F-NEXT: .LBB9_30: # %cond.store25 ; AVX512F-NEXT: vpextrw $5, %xmm0, 26(%rdi) ; AVX512F-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512F-NEXT: je .LBB9_30 -; AVX512F-NEXT: .LBB9_29: # %cond.store27 +; AVX512F-NEXT: je .LBB9_16 +; AVX512F-NEXT: .LBB9_31: # %cond.store27 ; AVX512F-NEXT: vpextrw $6, %xmm0, 28(%rdi) ; AVX512F-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX512F-NEXT: je .LBB9_32 -; AVX512F-NEXT: .LBB9_31: # %cond.store29 +; AVX512F-NEXT: je .LBB9_17 +; AVX512F-NEXT: .LBB9_32: # %cond.store29 ; AVX512F-NEXT: vpextrw $7, %xmm0, 30(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -2796,116 +2796,116 @@ define void @truncstore_v16i32_v16i16(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; AVX512FVL-NEXT: vpmovdw %zmm0, %ymm0 ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB9_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB9_18 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB9_3 -; AVX512FVL-NEXT: .LBB9_4: # %else2 +; AVX512FVL-NEXT: jne .LBB9_19 +; AVX512FVL-NEXT: .LBB9_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB9_5 -; AVX512FVL-NEXT: .LBB9_6: # %else4 +; AVX512FVL-NEXT: jne .LBB9_20 +; AVX512FVL-NEXT: .LBB9_3: # %else4 ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: jne .LBB9_7 -; AVX512FVL-NEXT: .LBB9_8: # %else6 +; AVX512FVL-NEXT: jne .LBB9_21 +; AVX512FVL-NEXT: .LBB9_4: # %else6 ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: jne .LBB9_9 -; AVX512FVL-NEXT: .LBB9_10: # %else8 +; AVX512FVL-NEXT: jne .LBB9_22 +; AVX512FVL-NEXT: .LBB9_5: # %else8 ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: jne .LBB9_11 -; AVX512FVL-NEXT: .LBB9_12: # %else10 +; AVX512FVL-NEXT: jne .LBB9_23 +; AVX512FVL-NEXT: .LBB9_6: # %else10 ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: jne .LBB9_13 -; AVX512FVL-NEXT: .LBB9_14: # %else12 +; AVX512FVL-NEXT: jne .LBB9_24 +; AVX512FVL-NEXT: .LBB9_7: # %else12 ; AVX512FVL-NEXT: testb %al, %al -; AVX512FVL-NEXT: jns .LBB9_16 -; AVX512FVL-NEXT: .LBB9_15: # %cond.store13 +; AVX512FVL-NEXT: jns .LBB9_9 +; AVX512FVL-NEXT: .LBB9_8: # %cond.store13 ; AVX512FVL-NEXT: vpextrw $7, %xmm0, 14(%rdi) -; AVX512FVL-NEXT: .LBB9_16: # %else14 +; AVX512FVL-NEXT: .LBB9_9: # %else14 ; AVX512FVL-NEXT: testl $256, %eax # imm = 0x100 ; AVX512FVL-NEXT: vextracti128 $1, %ymm0, %xmm0 -; AVX512FVL-NEXT: jne .LBB9_17 -; AVX512FVL-NEXT: # %bb.18: # %else16 +; AVX512FVL-NEXT: jne .LBB9_25 +; AVX512FVL-NEXT: # %bb.10: # %else16 ; AVX512FVL-NEXT: testl $512, %eax # imm = 0x200 -; AVX512FVL-NEXT: jne .LBB9_19 -; AVX512FVL-NEXT: .LBB9_20: # %else18 +; AVX512FVL-NEXT: jne .LBB9_26 +; AVX512FVL-NEXT: .LBB9_11: # %else18 ; AVX512FVL-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512FVL-NEXT: jne .LBB9_21 -; AVX512FVL-NEXT: .LBB9_22: # %else20 +; AVX512FVL-NEXT: jne .LBB9_27 +; AVX512FVL-NEXT: .LBB9_12: # %else20 ; AVX512FVL-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512FVL-NEXT: jne .LBB9_23 -; AVX512FVL-NEXT: .LBB9_24: # %else22 +; AVX512FVL-NEXT: jne .LBB9_28 +; AVX512FVL-NEXT: .LBB9_13: # %else22 ; AVX512FVL-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512FVL-NEXT: jne .LBB9_25 -; AVX512FVL-NEXT: .LBB9_26: # %else24 +; AVX512FVL-NEXT: jne .LBB9_29 +; AVX512FVL-NEXT: .LBB9_14: # %else24 ; AVX512FVL-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512FVL-NEXT: jne .LBB9_27 -; AVX512FVL-NEXT: .LBB9_28: # %else26 +; AVX512FVL-NEXT: jne .LBB9_30 +; AVX512FVL-NEXT: .LBB9_15: # %else26 ; AVX512FVL-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512FVL-NEXT: jne .LBB9_29 -; AVX512FVL-NEXT: .LBB9_30: # %else28 -; AVX512FVL-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX512FVL-NEXT: jne .LBB9_31 -; AVX512FVL-NEXT: .LBB9_32: # %else30 +; AVX512FVL-NEXT: .LBB9_16: # %else28 +; AVX512FVL-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX512FVL-NEXT: jne .LBB9_32 +; AVX512FVL-NEXT: .LBB9_17: # %else30 ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB9_1: # %cond.store +; AVX512FVL-NEXT: .LBB9_18: # %cond.store ; AVX512FVL-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB9_4 -; AVX512FVL-NEXT: .LBB9_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB9_2 +; AVX512FVL-NEXT: .LBB9_19: # %cond.store1 ; AVX512FVL-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB9_6 -; AVX512FVL-NEXT: .LBB9_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB9_3 +; AVX512FVL-NEXT: .LBB9_20: # %cond.store3 ; AVX512FVL-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB9_8 -; AVX512FVL-NEXT: .LBB9_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB9_4 +; AVX512FVL-NEXT: .LBB9_21: # %cond.store5 ; AVX512FVL-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: je .LBB9_10 -; AVX512FVL-NEXT: .LBB9_9: # %cond.store7 +; AVX512FVL-NEXT: je .LBB9_5 +; AVX512FVL-NEXT: .LBB9_22: # %cond.store7 ; AVX512FVL-NEXT: vpextrw $4, %xmm0, 8(%rdi) ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: je .LBB9_12 -; AVX512FVL-NEXT: .LBB9_11: # %cond.store9 +; AVX512FVL-NEXT: je .LBB9_6 +; AVX512FVL-NEXT: .LBB9_23: # %cond.store9 ; AVX512FVL-NEXT: vpextrw $5, %xmm0, 10(%rdi) ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: je .LBB9_14 -; AVX512FVL-NEXT: .LBB9_13: # %cond.store11 +; AVX512FVL-NEXT: je .LBB9_7 +; AVX512FVL-NEXT: .LBB9_24: # %cond.store11 ; AVX512FVL-NEXT: vpextrw $6, %xmm0, 12(%rdi) ; AVX512FVL-NEXT: testb %al, %al -; AVX512FVL-NEXT: js .LBB9_15 -; AVX512FVL-NEXT: jmp .LBB9_16 -; AVX512FVL-NEXT: .LBB9_17: # %cond.store15 +; AVX512FVL-NEXT: js .LBB9_8 +; AVX512FVL-NEXT: jmp .LBB9_9 +; AVX512FVL-NEXT: .LBB9_25: # %cond.store15 ; AVX512FVL-NEXT: vpextrw $0, %xmm0, 16(%rdi) ; AVX512FVL-NEXT: testl $512, %eax # imm = 0x200 -; AVX512FVL-NEXT: je .LBB9_20 -; AVX512FVL-NEXT: .LBB9_19: # %cond.store17 +; AVX512FVL-NEXT: je .LBB9_11 +; AVX512FVL-NEXT: .LBB9_26: # %cond.store17 ; AVX512FVL-NEXT: vpextrw $1, %xmm0, 18(%rdi) ; AVX512FVL-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512FVL-NEXT: je .LBB9_22 -; AVX512FVL-NEXT: .LBB9_21: # %cond.store19 +; AVX512FVL-NEXT: je .LBB9_12 +; AVX512FVL-NEXT: .LBB9_27: # %cond.store19 ; AVX512FVL-NEXT: vpextrw $2, %xmm0, 20(%rdi) ; AVX512FVL-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512FVL-NEXT: je .LBB9_24 -; AVX512FVL-NEXT: .LBB9_23: # %cond.store21 +; AVX512FVL-NEXT: je .LBB9_13 +; AVX512FVL-NEXT: .LBB9_28: # %cond.store21 ; AVX512FVL-NEXT: vpextrw $3, %xmm0, 22(%rdi) ; AVX512FVL-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512FVL-NEXT: je .LBB9_26 -; AVX512FVL-NEXT: .LBB9_25: # %cond.store23 +; AVX512FVL-NEXT: je .LBB9_14 +; AVX512FVL-NEXT: .LBB9_29: # %cond.store23 ; AVX512FVL-NEXT: vpextrw $4, %xmm0, 24(%rdi) ; AVX512FVL-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512FVL-NEXT: je .LBB9_28 -; AVX512FVL-NEXT: .LBB9_27: # %cond.store25 +; AVX512FVL-NEXT: je .LBB9_15 +; AVX512FVL-NEXT: .LBB9_30: # %cond.store25 ; AVX512FVL-NEXT: vpextrw $5, %xmm0, 26(%rdi) ; AVX512FVL-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512FVL-NEXT: je .LBB9_30 -; AVX512FVL-NEXT: .LBB9_29: # %cond.store27 +; AVX512FVL-NEXT: je .LBB9_16 +; AVX512FVL-NEXT: .LBB9_31: # %cond.store27 ; AVX512FVL-NEXT: vpextrw $6, %xmm0, 28(%rdi) ; AVX512FVL-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX512FVL-NEXT: je .LBB9_32 -; AVX512FVL-NEXT: .LBB9_31: # %cond.store29 +; AVX512FVL-NEXT: je .LBB9_17 +; AVX512FVL-NEXT: .LBB9_32: # %cond.store29 ; AVX512FVL-NEXT: vpextrw $7, %xmm0, 30(%rdi) ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq @@ -2952,103 +2952,103 @@ define void @truncstore_v16i32_v16i8(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; SSE2-NEXT: xorl $65535, %eax # imm = 0xFFFF ; SSE2-NEXT: testb $1, %al ; SSE2-NEXT: movd %xmm0, %ecx -; SSE2-NEXT: jne .LBB10_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB10_28 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne .LBB10_3 -; SSE2-NEXT: .LBB10_4: # %else2 +; SSE2-NEXT: jne .LBB10_29 +; SSE2-NEXT: .LBB10_2: # %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne .LBB10_5 -; SSE2-NEXT: .LBB10_6: # %else4 +; SSE2-NEXT: jne .LBB10_30 +; SSE2-NEXT: .LBB10_3: # %else4 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je .LBB10_8 -; SSE2-NEXT: .LBB10_7: # %cond.store5 +; SSE2-NEXT: je .LBB10_5 +; SSE2-NEXT: .LBB10_4: # %cond.store5 ; SSE2-NEXT: shrl $24, %ecx ; SSE2-NEXT: movb %cl, 3(%rdi) -; SSE2-NEXT: .LBB10_8: # %else6 +; SSE2-NEXT: .LBB10_5: # %else6 ; SSE2-NEXT: testb $16, %al ; SSE2-NEXT: pextrw $2, %xmm0, %ecx -; SSE2-NEXT: je .LBB10_10 -; SSE2-NEXT: # %bb.9: # %cond.store7 +; SSE2-NEXT: je .LBB10_7 +; SSE2-NEXT: # %bb.6: # %cond.store7 ; SSE2-NEXT: movb %cl, 4(%rdi) -; SSE2-NEXT: .LBB10_10: # %else8 +; SSE2-NEXT: .LBB10_7: # %else8 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je .LBB10_12 -; SSE2-NEXT: # %bb.11: # %cond.store9 +; SSE2-NEXT: je .LBB10_9 +; SSE2-NEXT: # %bb.8: # %cond.store9 ; SSE2-NEXT: movb %ch, 5(%rdi) -; SSE2-NEXT: .LBB10_12: # %else10 +; SSE2-NEXT: .LBB10_9: # %else10 ; SSE2-NEXT: testb $64, %al ; SSE2-NEXT: pextrw $3, %xmm0, %ecx -; SSE2-NEXT: je .LBB10_14 -; SSE2-NEXT: # %bb.13: # %cond.store11 +; SSE2-NEXT: je .LBB10_11 +; SSE2-NEXT: # %bb.10: # %cond.store11 ; SSE2-NEXT: movb %cl, 6(%rdi) -; SSE2-NEXT: .LBB10_14: # %else12 +; SSE2-NEXT: .LBB10_11: # %else12 ; SSE2-NEXT: testb %al, %al -; SSE2-NEXT: jns .LBB10_16 -; SSE2-NEXT: # %bb.15: # %cond.store13 +; SSE2-NEXT: jns .LBB10_13 +; SSE2-NEXT: # %bb.12: # %cond.store13 ; SSE2-NEXT: movb %ch, 7(%rdi) -; SSE2-NEXT: .LBB10_16: # %else14 +; SSE2-NEXT: .LBB10_13: # %else14 ; SSE2-NEXT: testl $256, %eax # imm = 0x100 ; SSE2-NEXT: pextrw $4, %xmm0, %ecx -; SSE2-NEXT: je .LBB10_18 -; SSE2-NEXT: # %bb.17: # %cond.store15 +; SSE2-NEXT: je .LBB10_15 +; SSE2-NEXT: # %bb.14: # %cond.store15 ; SSE2-NEXT: movb %cl, 8(%rdi) -; SSE2-NEXT: .LBB10_18: # %else16 +; SSE2-NEXT: .LBB10_15: # %else16 ; SSE2-NEXT: testl $512, %eax # imm = 0x200 -; SSE2-NEXT: je .LBB10_20 -; SSE2-NEXT: # %bb.19: # %cond.store17 +; SSE2-NEXT: je .LBB10_17 +; SSE2-NEXT: # %bb.16: # %cond.store17 ; SSE2-NEXT: movb %ch, 9(%rdi) -; SSE2-NEXT: .LBB10_20: # %else18 +; SSE2-NEXT: .LBB10_17: # %else18 ; SSE2-NEXT: testl $1024, %eax # imm = 0x400 ; SSE2-NEXT: pextrw $5, %xmm0, %ecx -; SSE2-NEXT: je .LBB10_22 -; SSE2-NEXT: # %bb.21: # %cond.store19 +; SSE2-NEXT: je .LBB10_19 +; SSE2-NEXT: # %bb.18: # %cond.store19 ; SSE2-NEXT: movb %cl, 10(%rdi) -; SSE2-NEXT: .LBB10_22: # %else20 +; SSE2-NEXT: .LBB10_19: # %else20 ; SSE2-NEXT: testl $2048, %eax # imm = 0x800 -; SSE2-NEXT: je .LBB10_24 -; SSE2-NEXT: # %bb.23: # %cond.store21 +; SSE2-NEXT: je .LBB10_21 +; SSE2-NEXT: # %bb.20: # %cond.store21 ; SSE2-NEXT: movb %ch, 11(%rdi) -; SSE2-NEXT: .LBB10_24: # %else22 +; SSE2-NEXT: .LBB10_21: # %else22 ; SSE2-NEXT: testl $4096, %eax # imm = 0x1000 ; SSE2-NEXT: pextrw $6, %xmm0, %ecx -; SSE2-NEXT: je .LBB10_26 -; SSE2-NEXT: # %bb.25: # %cond.store23 +; SSE2-NEXT: je .LBB10_23 +; SSE2-NEXT: # %bb.22: # %cond.store23 ; SSE2-NEXT: movb %cl, 12(%rdi) -; SSE2-NEXT: .LBB10_26: # %else24 +; SSE2-NEXT: .LBB10_23: # %else24 ; SSE2-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE2-NEXT: je .LBB10_28 -; SSE2-NEXT: # %bb.27: # %cond.store25 +; SSE2-NEXT: je .LBB10_25 +; SSE2-NEXT: # %bb.24: # %cond.store25 ; SSE2-NEXT: movb %ch, 13(%rdi) -; SSE2-NEXT: .LBB10_28: # %else26 +; SSE2-NEXT: .LBB10_25: # %else26 ; SSE2-NEXT: testl $16384, %eax # imm = 0x4000 ; SSE2-NEXT: pextrw $7, %xmm0, %ecx -; SSE2-NEXT: jne .LBB10_29 -; SSE2-NEXT: # %bb.30: # %else28 -; SSE2-NEXT: testl $32768, %eax # imm = 0x8000 ; SSE2-NEXT: jne .LBB10_31 -; SSE2-NEXT: .LBB10_32: # %else30 +; SSE2-NEXT: # %bb.26: # %else28 +; SSE2-NEXT: testl $32768, %eax # imm = 0x8000 +; SSE2-NEXT: jne .LBB10_32 +; SSE2-NEXT: .LBB10_27: # %else30 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB10_1: # %cond.store +; SSE2-NEXT: .LBB10_28: # %cond.store ; SSE2-NEXT: movb %cl, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB10_4 -; SSE2-NEXT: .LBB10_3: # %cond.store1 +; SSE2-NEXT: je .LBB10_2 +; SSE2-NEXT: .LBB10_29: # %cond.store1 ; SSE2-NEXT: movb %ch, 1(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je .LBB10_6 -; SSE2-NEXT: .LBB10_5: # %cond.store3 +; SSE2-NEXT: je .LBB10_3 +; SSE2-NEXT: .LBB10_30: # %cond.store3 ; SSE2-NEXT: movl %ecx, %edx ; SSE2-NEXT: shrl $16, %edx ; SSE2-NEXT: movb %dl, 2(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne .LBB10_7 -; SSE2-NEXT: jmp .LBB10_8 -; SSE2-NEXT: .LBB10_29: # %cond.store27 +; SSE2-NEXT: jne .LBB10_4 +; SSE2-NEXT: jmp .LBB10_5 +; SSE2-NEXT: .LBB10_31: # %cond.store27 ; SSE2-NEXT: movb %cl, 14(%rdi) ; SSE2-NEXT: testl $32768, %eax # imm = 0x8000 -; SSE2-NEXT: je .LBB10_32 -; SSE2-NEXT: .LBB10_31: # %cond.store29 +; SSE2-NEXT: je .LBB10_27 +; SSE2-NEXT: .LBB10_32: # %cond.store29 ; SSE2-NEXT: movb %ch, 15(%rdi) ; SSE2-NEXT: retq ; @@ -3073,115 +3073,115 @@ define void @truncstore_v16i32_v16i8(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; SSE4-NEXT: pmovmskb %xmm4, %eax ; SSE4-NEXT: xorl $65535, %eax # imm = 0xFFFF ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB10_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB10_17 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB10_3 -; SSE4-NEXT: .LBB10_4: # %else2 +; SSE4-NEXT: jne .LBB10_18 +; SSE4-NEXT: .LBB10_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB10_5 -; SSE4-NEXT: .LBB10_6: # %else4 +; SSE4-NEXT: jne .LBB10_19 +; SSE4-NEXT: .LBB10_3: # %else4 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne .LBB10_7 -; SSE4-NEXT: .LBB10_8: # %else6 +; SSE4-NEXT: jne .LBB10_20 +; SSE4-NEXT: .LBB10_4: # %else6 ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: jne .LBB10_9 -; SSE4-NEXT: .LBB10_10: # %else8 +; SSE4-NEXT: jne .LBB10_21 +; SSE4-NEXT: .LBB10_5: # %else8 ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: jne .LBB10_11 -; SSE4-NEXT: .LBB10_12: # %else10 +; SSE4-NEXT: jne .LBB10_22 +; SSE4-NEXT: .LBB10_6: # %else10 ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: jne .LBB10_13 -; SSE4-NEXT: .LBB10_14: # %else12 +; SSE4-NEXT: jne .LBB10_23 +; SSE4-NEXT: .LBB10_7: # %else12 ; SSE4-NEXT: testb %al, %al -; SSE4-NEXT: js .LBB10_15 -; SSE4-NEXT: .LBB10_16: # %else14 +; SSE4-NEXT: js .LBB10_24 +; SSE4-NEXT: .LBB10_8: # %else14 ; SSE4-NEXT: testl $256, %eax # imm = 0x100 -; SSE4-NEXT: jne .LBB10_17 -; SSE4-NEXT: .LBB10_18: # %else16 +; SSE4-NEXT: jne .LBB10_25 +; SSE4-NEXT: .LBB10_9: # %else16 ; SSE4-NEXT: testl $512, %eax # imm = 0x200 -; SSE4-NEXT: jne .LBB10_19 -; SSE4-NEXT: .LBB10_20: # %else18 +; SSE4-NEXT: jne .LBB10_26 +; SSE4-NEXT: .LBB10_10: # %else18 ; SSE4-NEXT: testl $1024, %eax # imm = 0x400 -; SSE4-NEXT: jne .LBB10_21 -; SSE4-NEXT: .LBB10_22: # %else20 +; SSE4-NEXT: jne .LBB10_27 +; SSE4-NEXT: .LBB10_11: # %else20 ; SSE4-NEXT: testl $2048, %eax # imm = 0x800 -; SSE4-NEXT: jne .LBB10_23 -; SSE4-NEXT: .LBB10_24: # %else22 +; SSE4-NEXT: jne .LBB10_28 +; SSE4-NEXT: .LBB10_12: # %else22 ; SSE4-NEXT: testl $4096, %eax # imm = 0x1000 -; SSE4-NEXT: jne .LBB10_25 -; SSE4-NEXT: .LBB10_26: # %else24 +; SSE4-NEXT: jne .LBB10_29 +; SSE4-NEXT: .LBB10_13: # %else24 ; SSE4-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE4-NEXT: jne .LBB10_27 -; SSE4-NEXT: .LBB10_28: # %else26 +; SSE4-NEXT: jne .LBB10_30 +; SSE4-NEXT: .LBB10_14: # %else26 ; SSE4-NEXT: testl $16384, %eax # imm = 0x4000 -; SSE4-NEXT: jne .LBB10_29 -; SSE4-NEXT: .LBB10_30: # %else28 -; SSE4-NEXT: testl $32768, %eax # imm = 0x8000 ; SSE4-NEXT: jne .LBB10_31 -; SSE4-NEXT: .LBB10_32: # %else30 +; SSE4-NEXT: .LBB10_15: # %else28 +; SSE4-NEXT: testl $32768, %eax # imm = 0x8000 +; SSE4-NEXT: jne .LBB10_32 +; SSE4-NEXT: .LBB10_16: # %else30 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB10_1: # %cond.store +; SSE4-NEXT: .LBB10_17: # %cond.store ; SSE4-NEXT: pextrb $0, %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB10_4 -; SSE4-NEXT: .LBB10_3: # %cond.store1 +; SSE4-NEXT: je .LBB10_2 +; SSE4-NEXT: .LBB10_18: # %cond.store1 ; SSE4-NEXT: pextrb $1, %xmm0, 1(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB10_6 -; SSE4-NEXT: .LBB10_5: # %cond.store3 +; SSE4-NEXT: je .LBB10_3 +; SSE4-NEXT: .LBB10_19: # %cond.store3 ; SSE4-NEXT: pextrb $2, %xmm0, 2(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB10_8 -; SSE4-NEXT: .LBB10_7: # %cond.store5 +; SSE4-NEXT: je .LBB10_4 +; SSE4-NEXT: .LBB10_20: # %cond.store5 ; SSE4-NEXT: pextrb $3, %xmm0, 3(%rdi) ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: je .LBB10_10 -; SSE4-NEXT: .LBB10_9: # %cond.store7 +; SSE4-NEXT: je .LBB10_5 +; SSE4-NEXT: .LBB10_21: # %cond.store7 ; SSE4-NEXT: pextrb $4, %xmm0, 4(%rdi) ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: je .LBB10_12 -; SSE4-NEXT: .LBB10_11: # %cond.store9 +; SSE4-NEXT: je .LBB10_6 +; SSE4-NEXT: .LBB10_22: # %cond.store9 ; SSE4-NEXT: pextrb $5, %xmm0, 5(%rdi) ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: je .LBB10_14 -; SSE4-NEXT: .LBB10_13: # %cond.store11 +; SSE4-NEXT: je .LBB10_7 +; SSE4-NEXT: .LBB10_23: # %cond.store11 ; SSE4-NEXT: pextrb $6, %xmm0, 6(%rdi) ; SSE4-NEXT: testb %al, %al -; SSE4-NEXT: jns .LBB10_16 -; SSE4-NEXT: .LBB10_15: # %cond.store13 +; SSE4-NEXT: jns .LBB10_8 +; SSE4-NEXT: .LBB10_24: # %cond.store13 ; SSE4-NEXT: pextrb $7, %xmm0, 7(%rdi) ; SSE4-NEXT: testl $256, %eax # imm = 0x100 -; SSE4-NEXT: je .LBB10_18 -; SSE4-NEXT: .LBB10_17: # %cond.store15 +; SSE4-NEXT: je .LBB10_9 +; SSE4-NEXT: .LBB10_25: # %cond.store15 ; SSE4-NEXT: pextrb $8, %xmm0, 8(%rdi) ; SSE4-NEXT: testl $512, %eax # imm = 0x200 -; SSE4-NEXT: je .LBB10_20 -; SSE4-NEXT: .LBB10_19: # %cond.store17 +; SSE4-NEXT: je .LBB10_10 +; SSE4-NEXT: .LBB10_26: # %cond.store17 ; SSE4-NEXT: pextrb $9, %xmm0, 9(%rdi) ; SSE4-NEXT: testl $1024, %eax # imm = 0x400 -; SSE4-NEXT: je .LBB10_22 -; SSE4-NEXT: .LBB10_21: # %cond.store19 +; SSE4-NEXT: je .LBB10_11 +; SSE4-NEXT: .LBB10_27: # %cond.store19 ; SSE4-NEXT: pextrb $10, %xmm0, 10(%rdi) ; SSE4-NEXT: testl $2048, %eax # imm = 0x800 -; SSE4-NEXT: je .LBB10_24 -; SSE4-NEXT: .LBB10_23: # %cond.store21 +; SSE4-NEXT: je .LBB10_12 +; SSE4-NEXT: .LBB10_28: # %cond.store21 ; SSE4-NEXT: pextrb $11, %xmm0, 11(%rdi) ; SSE4-NEXT: testl $4096, %eax # imm = 0x1000 -; SSE4-NEXT: je .LBB10_26 -; SSE4-NEXT: .LBB10_25: # %cond.store23 +; SSE4-NEXT: je .LBB10_13 +; SSE4-NEXT: .LBB10_29: # %cond.store23 ; SSE4-NEXT: pextrb $12, %xmm0, 12(%rdi) ; SSE4-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE4-NEXT: je .LBB10_28 -; SSE4-NEXT: .LBB10_27: # %cond.store25 +; SSE4-NEXT: je .LBB10_14 +; SSE4-NEXT: .LBB10_30: # %cond.store25 ; SSE4-NEXT: pextrb $13, %xmm0, 13(%rdi) ; SSE4-NEXT: testl $16384, %eax # imm = 0x4000 -; SSE4-NEXT: je .LBB10_30 -; SSE4-NEXT: .LBB10_29: # %cond.store27 +; SSE4-NEXT: je .LBB10_15 +; SSE4-NEXT: .LBB10_31: # %cond.store27 ; SSE4-NEXT: pextrb $14, %xmm0, 14(%rdi) ; SSE4-NEXT: testl $32768, %eax # imm = 0x8000 -; SSE4-NEXT: je .LBB10_32 -; SSE4-NEXT: .LBB10_31: # %cond.store29 +; SSE4-NEXT: je .LBB10_16 +; SSE4-NEXT: .LBB10_32: # %cond.store29 ; SSE4-NEXT: pextrb $15, %xmm0, 15(%rdi) ; SSE4-NEXT: retq ; @@ -3208,116 +3208,116 @@ define void @truncstore_v16i32_v16i8(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; AVX1-NEXT: vpmovmskb %xmm1, %eax ; AVX1-NEXT: xorl $65535, %eax # imm = 0xFFFF ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne .LBB10_1 -; AVX1-NEXT: # %bb.2: # %else +; AVX1-NEXT: jne .LBB10_17 +; AVX1-NEXT: # %bb.1: # %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne .LBB10_3 -; AVX1-NEXT: .LBB10_4: # %else2 +; AVX1-NEXT: jne .LBB10_18 +; AVX1-NEXT: .LBB10_2: # %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne .LBB10_5 -; AVX1-NEXT: .LBB10_6: # %else4 +; AVX1-NEXT: jne .LBB10_19 +; AVX1-NEXT: .LBB10_3: # %else4 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne .LBB10_7 -; AVX1-NEXT: .LBB10_8: # %else6 +; AVX1-NEXT: jne .LBB10_20 +; AVX1-NEXT: .LBB10_4: # %else6 ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: jne .LBB10_9 -; AVX1-NEXT: .LBB10_10: # %else8 +; AVX1-NEXT: jne .LBB10_21 +; AVX1-NEXT: .LBB10_5: # %else8 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: jne .LBB10_11 -; AVX1-NEXT: .LBB10_12: # %else10 +; AVX1-NEXT: jne .LBB10_22 +; AVX1-NEXT: .LBB10_6: # %else10 ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: jne .LBB10_13 -; AVX1-NEXT: .LBB10_14: # %else12 +; AVX1-NEXT: jne .LBB10_23 +; AVX1-NEXT: .LBB10_7: # %else12 ; AVX1-NEXT: testb %al, %al -; AVX1-NEXT: js .LBB10_15 -; AVX1-NEXT: .LBB10_16: # %else14 +; AVX1-NEXT: js .LBB10_24 +; AVX1-NEXT: .LBB10_8: # %else14 ; AVX1-NEXT: testl $256, %eax # imm = 0x100 -; AVX1-NEXT: jne .LBB10_17 -; AVX1-NEXT: .LBB10_18: # %else16 +; AVX1-NEXT: jne .LBB10_25 +; AVX1-NEXT: .LBB10_9: # %else16 ; AVX1-NEXT: testl $512, %eax # imm = 0x200 -; AVX1-NEXT: jne .LBB10_19 -; AVX1-NEXT: .LBB10_20: # %else18 +; AVX1-NEXT: jne .LBB10_26 +; AVX1-NEXT: .LBB10_10: # %else18 ; AVX1-NEXT: testl $1024, %eax # imm = 0x400 -; AVX1-NEXT: jne .LBB10_21 -; AVX1-NEXT: .LBB10_22: # %else20 +; AVX1-NEXT: jne .LBB10_27 +; AVX1-NEXT: .LBB10_11: # %else20 ; AVX1-NEXT: testl $2048, %eax # imm = 0x800 -; AVX1-NEXT: jne .LBB10_23 -; AVX1-NEXT: .LBB10_24: # %else22 +; AVX1-NEXT: jne .LBB10_28 +; AVX1-NEXT: .LBB10_12: # %else22 ; AVX1-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX1-NEXT: jne .LBB10_25 -; AVX1-NEXT: .LBB10_26: # %else24 +; AVX1-NEXT: jne .LBB10_29 +; AVX1-NEXT: .LBB10_13: # %else24 ; AVX1-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX1-NEXT: jne .LBB10_27 -; AVX1-NEXT: .LBB10_28: # %else26 +; AVX1-NEXT: jne .LBB10_30 +; AVX1-NEXT: .LBB10_14: # %else26 ; AVX1-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX1-NEXT: jne .LBB10_29 -; AVX1-NEXT: .LBB10_30: # %else28 -; AVX1-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX1-NEXT: jne .LBB10_31 -; AVX1-NEXT: .LBB10_32: # %else30 +; AVX1-NEXT: .LBB10_15: # %else28 +; AVX1-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX1-NEXT: jne .LBB10_32 +; AVX1-NEXT: .LBB10_16: # %else30 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB10_1: # %cond.store +; AVX1-NEXT: .LBB10_17: # %cond.store ; AVX1-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je .LBB10_4 -; AVX1-NEXT: .LBB10_3: # %cond.store1 +; AVX1-NEXT: je .LBB10_2 +; AVX1-NEXT: .LBB10_18: # %cond.store1 ; AVX1-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je .LBB10_6 -; AVX1-NEXT: .LBB10_5: # %cond.store3 +; AVX1-NEXT: je .LBB10_3 +; AVX1-NEXT: .LBB10_19: # %cond.store3 ; AVX1-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB10_8 -; AVX1-NEXT: .LBB10_7: # %cond.store5 +; AVX1-NEXT: je .LBB10_4 +; AVX1-NEXT: .LBB10_20: # %cond.store5 ; AVX1-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: je .LBB10_10 -; AVX1-NEXT: .LBB10_9: # %cond.store7 +; AVX1-NEXT: je .LBB10_5 +; AVX1-NEXT: .LBB10_21: # %cond.store7 ; AVX1-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je .LBB10_12 -; AVX1-NEXT: .LBB10_11: # %cond.store9 +; AVX1-NEXT: je .LBB10_6 +; AVX1-NEXT: .LBB10_22: # %cond.store9 ; AVX1-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: je .LBB10_14 -; AVX1-NEXT: .LBB10_13: # %cond.store11 +; AVX1-NEXT: je .LBB10_7 +; AVX1-NEXT: .LBB10_23: # %cond.store11 ; AVX1-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX1-NEXT: testb %al, %al -; AVX1-NEXT: jns .LBB10_16 -; AVX1-NEXT: .LBB10_15: # %cond.store13 +; AVX1-NEXT: jns .LBB10_8 +; AVX1-NEXT: .LBB10_24: # %cond.store13 ; AVX1-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX1-NEXT: testl $256, %eax # imm = 0x100 -; AVX1-NEXT: je .LBB10_18 -; AVX1-NEXT: .LBB10_17: # %cond.store15 +; AVX1-NEXT: je .LBB10_9 +; AVX1-NEXT: .LBB10_25: # %cond.store15 ; AVX1-NEXT: vpextrb $8, %xmm0, 8(%rdi) ; AVX1-NEXT: testl $512, %eax # imm = 0x200 -; AVX1-NEXT: je .LBB10_20 -; AVX1-NEXT: .LBB10_19: # %cond.store17 +; AVX1-NEXT: je .LBB10_10 +; AVX1-NEXT: .LBB10_26: # %cond.store17 ; AVX1-NEXT: vpextrb $9, %xmm0, 9(%rdi) ; AVX1-NEXT: testl $1024, %eax # imm = 0x400 -; AVX1-NEXT: je .LBB10_22 -; AVX1-NEXT: .LBB10_21: # %cond.store19 +; AVX1-NEXT: je .LBB10_11 +; AVX1-NEXT: .LBB10_27: # %cond.store19 ; AVX1-NEXT: vpextrb $10, %xmm0, 10(%rdi) ; AVX1-NEXT: testl $2048, %eax # imm = 0x800 -; AVX1-NEXT: je .LBB10_24 -; AVX1-NEXT: .LBB10_23: # %cond.store21 +; AVX1-NEXT: je .LBB10_12 +; AVX1-NEXT: .LBB10_28: # %cond.store21 ; AVX1-NEXT: vpextrb $11, %xmm0, 11(%rdi) ; AVX1-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX1-NEXT: je .LBB10_26 -; AVX1-NEXT: .LBB10_25: # %cond.store23 +; AVX1-NEXT: je .LBB10_13 +; AVX1-NEXT: .LBB10_29: # %cond.store23 ; AVX1-NEXT: vpextrb $12, %xmm0, 12(%rdi) ; AVX1-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX1-NEXT: je .LBB10_28 -; AVX1-NEXT: .LBB10_27: # %cond.store25 +; AVX1-NEXT: je .LBB10_14 +; AVX1-NEXT: .LBB10_30: # %cond.store25 ; AVX1-NEXT: vpextrb $13, %xmm0, 13(%rdi) ; AVX1-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX1-NEXT: je .LBB10_30 -; AVX1-NEXT: .LBB10_29: # %cond.store27 +; AVX1-NEXT: je .LBB10_15 +; AVX1-NEXT: .LBB10_31: # %cond.store27 ; AVX1-NEXT: vpextrb $14, %xmm0, 14(%rdi) ; AVX1-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX1-NEXT: je .LBB10_32 -; AVX1-NEXT: .LBB10_31: # %cond.store29 +; AVX1-NEXT: je .LBB10_16 +; AVX1-NEXT: .LBB10_32: # %cond.store29 ; AVX1-NEXT: vpextrb $15, %xmm0, 15(%rdi) ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq @@ -3342,116 +3342,116 @@ define void @truncstore_v16i32_v16i8(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,2,1,3] ; AVX2-NEXT: vpmovmskb %xmm1, %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne .LBB10_1 -; AVX2-NEXT: # %bb.2: # %else +; AVX2-NEXT: jne .LBB10_17 +; AVX2-NEXT: # %bb.1: # %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne .LBB10_3 -; AVX2-NEXT: .LBB10_4: # %else2 +; AVX2-NEXT: jne .LBB10_18 +; AVX2-NEXT: .LBB10_2: # %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne .LBB10_5 -; AVX2-NEXT: .LBB10_6: # %else4 +; AVX2-NEXT: jne .LBB10_19 +; AVX2-NEXT: .LBB10_3: # %else4 ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: jne .LBB10_7 -; AVX2-NEXT: .LBB10_8: # %else6 +; AVX2-NEXT: jne .LBB10_20 +; AVX2-NEXT: .LBB10_4: # %else6 ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: jne .LBB10_9 -; AVX2-NEXT: .LBB10_10: # %else8 +; AVX2-NEXT: jne .LBB10_21 +; AVX2-NEXT: .LBB10_5: # %else8 ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: jne .LBB10_11 -; AVX2-NEXT: .LBB10_12: # %else10 +; AVX2-NEXT: jne .LBB10_22 +; AVX2-NEXT: .LBB10_6: # %else10 ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: jne .LBB10_13 -; AVX2-NEXT: .LBB10_14: # %else12 +; AVX2-NEXT: jne .LBB10_23 +; AVX2-NEXT: .LBB10_7: # %else12 ; AVX2-NEXT: testb %al, %al -; AVX2-NEXT: js .LBB10_15 -; AVX2-NEXT: .LBB10_16: # %else14 +; AVX2-NEXT: js .LBB10_24 +; AVX2-NEXT: .LBB10_8: # %else14 ; AVX2-NEXT: testl $256, %eax # imm = 0x100 -; AVX2-NEXT: jne .LBB10_17 -; AVX2-NEXT: .LBB10_18: # %else16 +; AVX2-NEXT: jne .LBB10_25 +; AVX2-NEXT: .LBB10_9: # %else16 ; AVX2-NEXT: testl $512, %eax # imm = 0x200 -; AVX2-NEXT: jne .LBB10_19 -; AVX2-NEXT: .LBB10_20: # %else18 +; AVX2-NEXT: jne .LBB10_26 +; AVX2-NEXT: .LBB10_10: # %else18 ; AVX2-NEXT: testl $1024, %eax # imm = 0x400 -; AVX2-NEXT: jne .LBB10_21 -; AVX2-NEXT: .LBB10_22: # %else20 +; AVX2-NEXT: jne .LBB10_27 +; AVX2-NEXT: .LBB10_11: # %else20 ; AVX2-NEXT: testl $2048, %eax # imm = 0x800 -; AVX2-NEXT: jne .LBB10_23 -; AVX2-NEXT: .LBB10_24: # %else22 +; AVX2-NEXT: jne .LBB10_28 +; AVX2-NEXT: .LBB10_12: # %else22 ; AVX2-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX2-NEXT: jne .LBB10_25 -; AVX2-NEXT: .LBB10_26: # %else24 +; AVX2-NEXT: jne .LBB10_29 +; AVX2-NEXT: .LBB10_13: # %else24 ; AVX2-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX2-NEXT: jne .LBB10_27 -; AVX2-NEXT: .LBB10_28: # %else26 +; AVX2-NEXT: jne .LBB10_30 +; AVX2-NEXT: .LBB10_14: # %else26 ; AVX2-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX2-NEXT: jne .LBB10_29 -; AVX2-NEXT: .LBB10_30: # %else28 -; AVX2-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX2-NEXT: jne .LBB10_31 -; AVX2-NEXT: .LBB10_32: # %else30 +; AVX2-NEXT: .LBB10_15: # %else28 +; AVX2-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX2-NEXT: jne .LBB10_32 +; AVX2-NEXT: .LBB10_16: # %else30 ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; AVX2-NEXT: .LBB10_1: # %cond.store +; AVX2-NEXT: .LBB10_17: # %cond.store ; AVX2-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je .LBB10_4 -; AVX2-NEXT: .LBB10_3: # %cond.store1 +; AVX2-NEXT: je .LBB10_2 +; AVX2-NEXT: .LBB10_18: # %cond.store1 ; AVX2-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je .LBB10_6 -; AVX2-NEXT: .LBB10_5: # %cond.store3 +; AVX2-NEXT: je .LBB10_3 +; AVX2-NEXT: .LBB10_19: # %cond.store3 ; AVX2-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je .LBB10_8 -; AVX2-NEXT: .LBB10_7: # %cond.store5 +; AVX2-NEXT: je .LBB10_4 +; AVX2-NEXT: .LBB10_20: # %cond.store5 ; AVX2-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: je .LBB10_10 -; AVX2-NEXT: .LBB10_9: # %cond.store7 +; AVX2-NEXT: je .LBB10_5 +; AVX2-NEXT: .LBB10_21: # %cond.store7 ; AVX2-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: je .LBB10_12 -; AVX2-NEXT: .LBB10_11: # %cond.store9 +; AVX2-NEXT: je .LBB10_6 +; AVX2-NEXT: .LBB10_22: # %cond.store9 ; AVX2-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: je .LBB10_14 -; AVX2-NEXT: .LBB10_13: # %cond.store11 +; AVX2-NEXT: je .LBB10_7 +; AVX2-NEXT: .LBB10_23: # %cond.store11 ; AVX2-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX2-NEXT: testb %al, %al -; AVX2-NEXT: jns .LBB10_16 -; AVX2-NEXT: .LBB10_15: # %cond.store13 +; AVX2-NEXT: jns .LBB10_8 +; AVX2-NEXT: .LBB10_24: # %cond.store13 ; AVX2-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX2-NEXT: testl $256, %eax # imm = 0x100 -; AVX2-NEXT: je .LBB10_18 -; AVX2-NEXT: .LBB10_17: # %cond.store15 +; AVX2-NEXT: je .LBB10_9 +; AVX2-NEXT: .LBB10_25: # %cond.store15 ; AVX2-NEXT: vpextrb $8, %xmm0, 8(%rdi) ; AVX2-NEXT: testl $512, %eax # imm = 0x200 -; AVX2-NEXT: je .LBB10_20 -; AVX2-NEXT: .LBB10_19: # %cond.store17 +; AVX2-NEXT: je .LBB10_10 +; AVX2-NEXT: .LBB10_26: # %cond.store17 ; AVX2-NEXT: vpextrb $9, %xmm0, 9(%rdi) ; AVX2-NEXT: testl $1024, %eax # imm = 0x400 -; AVX2-NEXT: je .LBB10_22 -; AVX2-NEXT: .LBB10_21: # %cond.store19 +; AVX2-NEXT: je .LBB10_11 +; AVX2-NEXT: .LBB10_27: # %cond.store19 ; AVX2-NEXT: vpextrb $10, %xmm0, 10(%rdi) ; AVX2-NEXT: testl $2048, %eax # imm = 0x800 -; AVX2-NEXT: je .LBB10_24 -; AVX2-NEXT: .LBB10_23: # %cond.store21 +; AVX2-NEXT: je .LBB10_12 +; AVX2-NEXT: .LBB10_28: # %cond.store21 ; AVX2-NEXT: vpextrb $11, %xmm0, 11(%rdi) ; AVX2-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX2-NEXT: je .LBB10_26 -; AVX2-NEXT: .LBB10_25: # %cond.store23 +; AVX2-NEXT: je .LBB10_13 +; AVX2-NEXT: .LBB10_29: # %cond.store23 ; AVX2-NEXT: vpextrb $12, %xmm0, 12(%rdi) ; AVX2-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX2-NEXT: je .LBB10_28 -; AVX2-NEXT: .LBB10_27: # %cond.store25 +; AVX2-NEXT: je .LBB10_14 +; AVX2-NEXT: .LBB10_30: # %cond.store25 ; AVX2-NEXT: vpextrb $13, %xmm0, 13(%rdi) ; AVX2-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX2-NEXT: je .LBB10_30 -; AVX2-NEXT: .LBB10_29: # %cond.store27 +; AVX2-NEXT: je .LBB10_15 +; AVX2-NEXT: .LBB10_31: # %cond.store27 ; AVX2-NEXT: vpextrb $14, %xmm0, 14(%rdi) ; AVX2-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX2-NEXT: je .LBB10_32 -; AVX2-NEXT: .LBB10_31: # %cond.store29 +; AVX2-NEXT: je .LBB10_16 +; AVX2-NEXT: .LBB10_32: # %cond.store29 ; AVX2-NEXT: vpextrb $15, %xmm0, 15(%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq @@ -3462,116 +3462,116 @@ define void @truncstore_v16i32_v16i8(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; AVX512F-NEXT: vpmovdb %zmm0, %xmm0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB10_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB10_17 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB10_3 -; AVX512F-NEXT: .LBB10_4: # %else2 +; AVX512F-NEXT: jne .LBB10_18 +; AVX512F-NEXT: .LBB10_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB10_5 -; AVX512F-NEXT: .LBB10_6: # %else4 +; AVX512F-NEXT: jne .LBB10_19 +; AVX512F-NEXT: .LBB10_3: # %else4 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne .LBB10_7 -; AVX512F-NEXT: .LBB10_8: # %else6 +; AVX512F-NEXT: jne .LBB10_20 +; AVX512F-NEXT: .LBB10_4: # %else6 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne .LBB10_9 -; AVX512F-NEXT: .LBB10_10: # %else8 +; AVX512F-NEXT: jne .LBB10_21 +; AVX512F-NEXT: .LBB10_5: # %else8 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne .LBB10_11 -; AVX512F-NEXT: .LBB10_12: # %else10 +; AVX512F-NEXT: jne .LBB10_22 +; AVX512F-NEXT: .LBB10_6: # %else10 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne .LBB10_13 -; AVX512F-NEXT: .LBB10_14: # %else12 +; AVX512F-NEXT: jne .LBB10_23 +; AVX512F-NEXT: .LBB10_7: # %else12 ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: js .LBB10_15 -; AVX512F-NEXT: .LBB10_16: # %else14 +; AVX512F-NEXT: js .LBB10_24 +; AVX512F-NEXT: .LBB10_8: # %else14 ; AVX512F-NEXT: testl $256, %eax # imm = 0x100 -; AVX512F-NEXT: jne .LBB10_17 -; AVX512F-NEXT: .LBB10_18: # %else16 +; AVX512F-NEXT: jne .LBB10_25 +; AVX512F-NEXT: .LBB10_9: # %else16 ; AVX512F-NEXT: testl $512, %eax # imm = 0x200 -; AVX512F-NEXT: jne .LBB10_19 -; AVX512F-NEXT: .LBB10_20: # %else18 +; AVX512F-NEXT: jne .LBB10_26 +; AVX512F-NEXT: .LBB10_10: # %else18 ; AVX512F-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512F-NEXT: jne .LBB10_21 -; AVX512F-NEXT: .LBB10_22: # %else20 +; AVX512F-NEXT: jne .LBB10_27 +; AVX512F-NEXT: .LBB10_11: # %else20 ; AVX512F-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512F-NEXT: jne .LBB10_23 -; AVX512F-NEXT: .LBB10_24: # %else22 +; AVX512F-NEXT: jne .LBB10_28 +; AVX512F-NEXT: .LBB10_12: # %else22 ; AVX512F-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512F-NEXT: jne .LBB10_25 -; AVX512F-NEXT: .LBB10_26: # %else24 +; AVX512F-NEXT: jne .LBB10_29 +; AVX512F-NEXT: .LBB10_13: # %else24 ; AVX512F-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512F-NEXT: jne .LBB10_27 -; AVX512F-NEXT: .LBB10_28: # %else26 +; AVX512F-NEXT: jne .LBB10_30 +; AVX512F-NEXT: .LBB10_14: # %else26 ; AVX512F-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512F-NEXT: jne .LBB10_29 -; AVX512F-NEXT: .LBB10_30: # %else28 -; AVX512F-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX512F-NEXT: jne .LBB10_31 -; AVX512F-NEXT: .LBB10_32: # %else30 +; AVX512F-NEXT: .LBB10_15: # %else28 +; AVX512F-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX512F-NEXT: jne .LBB10_32 +; AVX512F-NEXT: .LBB10_16: # %else30 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB10_1: # %cond.store +; AVX512F-NEXT: .LBB10_17: # %cond.store ; AVX512F-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB10_4 -; AVX512F-NEXT: .LBB10_3: # %cond.store1 +; AVX512F-NEXT: je .LBB10_2 +; AVX512F-NEXT: .LBB10_18: # %cond.store1 ; AVX512F-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB10_6 -; AVX512F-NEXT: .LBB10_5: # %cond.store3 +; AVX512F-NEXT: je .LBB10_3 +; AVX512F-NEXT: .LBB10_19: # %cond.store3 ; AVX512F-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB10_8 -; AVX512F-NEXT: .LBB10_7: # %cond.store5 +; AVX512F-NEXT: je .LBB10_4 +; AVX512F-NEXT: .LBB10_20: # %cond.store5 ; AVX512F-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je .LBB10_10 -; AVX512F-NEXT: .LBB10_9: # %cond.store7 +; AVX512F-NEXT: je .LBB10_5 +; AVX512F-NEXT: .LBB10_21: # %cond.store7 ; AVX512F-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je .LBB10_12 -; AVX512F-NEXT: .LBB10_11: # %cond.store9 +; AVX512F-NEXT: je .LBB10_6 +; AVX512F-NEXT: .LBB10_22: # %cond.store9 ; AVX512F-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je .LBB10_14 -; AVX512F-NEXT: .LBB10_13: # %cond.store11 +; AVX512F-NEXT: je .LBB10_7 +; AVX512F-NEXT: .LBB10_23: # %cond.store11 ; AVX512F-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: jns .LBB10_16 -; AVX512F-NEXT: .LBB10_15: # %cond.store13 +; AVX512F-NEXT: jns .LBB10_8 +; AVX512F-NEXT: .LBB10_24: # %cond.store13 ; AVX512F-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX512F-NEXT: testl $256, %eax # imm = 0x100 -; AVX512F-NEXT: je .LBB10_18 -; AVX512F-NEXT: .LBB10_17: # %cond.store15 +; AVX512F-NEXT: je .LBB10_9 +; AVX512F-NEXT: .LBB10_25: # %cond.store15 ; AVX512F-NEXT: vpextrb $8, %xmm0, 8(%rdi) ; AVX512F-NEXT: testl $512, %eax # imm = 0x200 -; AVX512F-NEXT: je .LBB10_20 -; AVX512F-NEXT: .LBB10_19: # %cond.store17 +; AVX512F-NEXT: je .LBB10_10 +; AVX512F-NEXT: .LBB10_26: # %cond.store17 ; AVX512F-NEXT: vpextrb $9, %xmm0, 9(%rdi) ; AVX512F-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512F-NEXT: je .LBB10_22 -; AVX512F-NEXT: .LBB10_21: # %cond.store19 +; AVX512F-NEXT: je .LBB10_11 +; AVX512F-NEXT: .LBB10_27: # %cond.store19 ; AVX512F-NEXT: vpextrb $10, %xmm0, 10(%rdi) ; AVX512F-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512F-NEXT: je .LBB10_24 -; AVX512F-NEXT: .LBB10_23: # %cond.store21 +; AVX512F-NEXT: je .LBB10_12 +; AVX512F-NEXT: .LBB10_28: # %cond.store21 ; AVX512F-NEXT: vpextrb $11, %xmm0, 11(%rdi) ; AVX512F-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512F-NEXT: je .LBB10_26 -; AVX512F-NEXT: .LBB10_25: # %cond.store23 +; AVX512F-NEXT: je .LBB10_13 +; AVX512F-NEXT: .LBB10_29: # %cond.store23 ; AVX512F-NEXT: vpextrb $12, %xmm0, 12(%rdi) ; AVX512F-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512F-NEXT: je .LBB10_28 -; AVX512F-NEXT: .LBB10_27: # %cond.store25 +; AVX512F-NEXT: je .LBB10_14 +; AVX512F-NEXT: .LBB10_30: # %cond.store25 ; AVX512F-NEXT: vpextrb $13, %xmm0, 13(%rdi) ; AVX512F-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512F-NEXT: je .LBB10_30 -; AVX512F-NEXT: .LBB10_29: # %cond.store27 +; AVX512F-NEXT: je .LBB10_15 +; AVX512F-NEXT: .LBB10_31: # %cond.store27 ; AVX512F-NEXT: vpextrb $14, %xmm0, 14(%rdi) ; AVX512F-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX512F-NEXT: je .LBB10_32 -; AVX512F-NEXT: .LBB10_31: # %cond.store29 +; AVX512F-NEXT: je .LBB10_16 +; AVX512F-NEXT: .LBB10_32: # %cond.store29 ; AVX512F-NEXT: vpextrb $15, %xmm0, 15(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -3582,116 +3582,116 @@ define void @truncstore_v16i32_v16i8(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; AVX512FVL-NEXT: vpmovdb %zmm0, %xmm0 ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB10_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB10_17 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB10_3 -; AVX512FVL-NEXT: .LBB10_4: # %else2 +; AVX512FVL-NEXT: jne .LBB10_18 +; AVX512FVL-NEXT: .LBB10_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB10_5 -; AVX512FVL-NEXT: .LBB10_6: # %else4 +; AVX512FVL-NEXT: jne .LBB10_19 +; AVX512FVL-NEXT: .LBB10_3: # %else4 ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: jne .LBB10_7 -; AVX512FVL-NEXT: .LBB10_8: # %else6 +; AVX512FVL-NEXT: jne .LBB10_20 +; AVX512FVL-NEXT: .LBB10_4: # %else6 ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: jne .LBB10_9 -; AVX512FVL-NEXT: .LBB10_10: # %else8 +; AVX512FVL-NEXT: jne .LBB10_21 +; AVX512FVL-NEXT: .LBB10_5: # %else8 ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: jne .LBB10_11 -; AVX512FVL-NEXT: .LBB10_12: # %else10 +; AVX512FVL-NEXT: jne .LBB10_22 +; AVX512FVL-NEXT: .LBB10_6: # %else10 ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: jne .LBB10_13 -; AVX512FVL-NEXT: .LBB10_14: # %else12 +; AVX512FVL-NEXT: jne .LBB10_23 +; AVX512FVL-NEXT: .LBB10_7: # %else12 ; AVX512FVL-NEXT: testb %al, %al -; AVX512FVL-NEXT: js .LBB10_15 -; AVX512FVL-NEXT: .LBB10_16: # %else14 +; AVX512FVL-NEXT: js .LBB10_24 +; AVX512FVL-NEXT: .LBB10_8: # %else14 ; AVX512FVL-NEXT: testl $256, %eax # imm = 0x100 -; AVX512FVL-NEXT: jne .LBB10_17 -; AVX512FVL-NEXT: .LBB10_18: # %else16 +; AVX512FVL-NEXT: jne .LBB10_25 +; AVX512FVL-NEXT: .LBB10_9: # %else16 ; AVX512FVL-NEXT: testl $512, %eax # imm = 0x200 -; AVX512FVL-NEXT: jne .LBB10_19 -; AVX512FVL-NEXT: .LBB10_20: # %else18 +; AVX512FVL-NEXT: jne .LBB10_26 +; AVX512FVL-NEXT: .LBB10_10: # %else18 ; AVX512FVL-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512FVL-NEXT: jne .LBB10_21 -; AVX512FVL-NEXT: .LBB10_22: # %else20 +; AVX512FVL-NEXT: jne .LBB10_27 +; AVX512FVL-NEXT: .LBB10_11: # %else20 ; AVX512FVL-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512FVL-NEXT: jne .LBB10_23 -; AVX512FVL-NEXT: .LBB10_24: # %else22 +; AVX512FVL-NEXT: jne .LBB10_28 +; AVX512FVL-NEXT: .LBB10_12: # %else22 ; AVX512FVL-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512FVL-NEXT: jne .LBB10_25 -; AVX512FVL-NEXT: .LBB10_26: # %else24 +; AVX512FVL-NEXT: jne .LBB10_29 +; AVX512FVL-NEXT: .LBB10_13: # %else24 ; AVX512FVL-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512FVL-NEXT: jne .LBB10_27 -; AVX512FVL-NEXT: .LBB10_28: # %else26 +; AVX512FVL-NEXT: jne .LBB10_30 +; AVX512FVL-NEXT: .LBB10_14: # %else26 ; AVX512FVL-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512FVL-NEXT: jne .LBB10_29 -; AVX512FVL-NEXT: .LBB10_30: # %else28 -; AVX512FVL-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX512FVL-NEXT: jne .LBB10_31 -; AVX512FVL-NEXT: .LBB10_32: # %else30 +; AVX512FVL-NEXT: .LBB10_15: # %else28 +; AVX512FVL-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX512FVL-NEXT: jne .LBB10_32 +; AVX512FVL-NEXT: .LBB10_16: # %else30 ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB10_1: # %cond.store +; AVX512FVL-NEXT: .LBB10_17: # %cond.store ; AVX512FVL-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB10_4 -; AVX512FVL-NEXT: .LBB10_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB10_2 +; AVX512FVL-NEXT: .LBB10_18: # %cond.store1 ; AVX512FVL-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB10_6 -; AVX512FVL-NEXT: .LBB10_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB10_3 +; AVX512FVL-NEXT: .LBB10_19: # %cond.store3 ; AVX512FVL-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB10_8 -; AVX512FVL-NEXT: .LBB10_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB10_4 +; AVX512FVL-NEXT: .LBB10_20: # %cond.store5 ; AVX512FVL-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: je .LBB10_10 -; AVX512FVL-NEXT: .LBB10_9: # %cond.store7 +; AVX512FVL-NEXT: je .LBB10_5 +; AVX512FVL-NEXT: .LBB10_21: # %cond.store7 ; AVX512FVL-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: je .LBB10_12 -; AVX512FVL-NEXT: .LBB10_11: # %cond.store9 +; AVX512FVL-NEXT: je .LBB10_6 +; AVX512FVL-NEXT: .LBB10_22: # %cond.store9 ; AVX512FVL-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: je .LBB10_14 -; AVX512FVL-NEXT: .LBB10_13: # %cond.store11 +; AVX512FVL-NEXT: je .LBB10_7 +; AVX512FVL-NEXT: .LBB10_23: # %cond.store11 ; AVX512FVL-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX512FVL-NEXT: testb %al, %al -; AVX512FVL-NEXT: jns .LBB10_16 -; AVX512FVL-NEXT: .LBB10_15: # %cond.store13 +; AVX512FVL-NEXT: jns .LBB10_8 +; AVX512FVL-NEXT: .LBB10_24: # %cond.store13 ; AVX512FVL-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX512FVL-NEXT: testl $256, %eax # imm = 0x100 -; AVX512FVL-NEXT: je .LBB10_18 -; AVX512FVL-NEXT: .LBB10_17: # %cond.store15 +; AVX512FVL-NEXT: je .LBB10_9 +; AVX512FVL-NEXT: .LBB10_25: # %cond.store15 ; AVX512FVL-NEXT: vpextrb $8, %xmm0, 8(%rdi) ; AVX512FVL-NEXT: testl $512, %eax # imm = 0x200 -; AVX512FVL-NEXT: je .LBB10_20 -; AVX512FVL-NEXT: .LBB10_19: # %cond.store17 +; AVX512FVL-NEXT: je .LBB10_10 +; AVX512FVL-NEXT: .LBB10_26: # %cond.store17 ; AVX512FVL-NEXT: vpextrb $9, %xmm0, 9(%rdi) ; AVX512FVL-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512FVL-NEXT: je .LBB10_22 -; AVX512FVL-NEXT: .LBB10_21: # %cond.store19 +; AVX512FVL-NEXT: je .LBB10_11 +; AVX512FVL-NEXT: .LBB10_27: # %cond.store19 ; AVX512FVL-NEXT: vpextrb $10, %xmm0, 10(%rdi) ; AVX512FVL-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512FVL-NEXT: je .LBB10_24 -; AVX512FVL-NEXT: .LBB10_23: # %cond.store21 +; AVX512FVL-NEXT: je .LBB10_12 +; AVX512FVL-NEXT: .LBB10_28: # %cond.store21 ; AVX512FVL-NEXT: vpextrb $11, %xmm0, 11(%rdi) ; AVX512FVL-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512FVL-NEXT: je .LBB10_26 -; AVX512FVL-NEXT: .LBB10_25: # %cond.store23 +; AVX512FVL-NEXT: je .LBB10_13 +; AVX512FVL-NEXT: .LBB10_29: # %cond.store23 ; AVX512FVL-NEXT: vpextrb $12, %xmm0, 12(%rdi) ; AVX512FVL-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512FVL-NEXT: je .LBB10_28 -; AVX512FVL-NEXT: .LBB10_27: # %cond.store25 +; AVX512FVL-NEXT: je .LBB10_14 +; AVX512FVL-NEXT: .LBB10_30: # %cond.store25 ; AVX512FVL-NEXT: vpextrb $13, %xmm0, 13(%rdi) ; AVX512FVL-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512FVL-NEXT: je .LBB10_30 -; AVX512FVL-NEXT: .LBB10_29: # %cond.store27 +; AVX512FVL-NEXT: je .LBB10_15 +; AVX512FVL-NEXT: .LBB10_31: # %cond.store27 ; AVX512FVL-NEXT: vpextrb $14, %xmm0, 14(%rdi) ; AVX512FVL-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX512FVL-NEXT: je .LBB10_32 -; AVX512FVL-NEXT: .LBB10_31: # %cond.store29 +; AVX512FVL-NEXT: je .LBB10_16 +; AVX512FVL-NEXT: .LBB10_32: # %cond.store29 ; AVX512FVL-NEXT: vpextrb $15, %xmm0, 15(%rdi) ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq @@ -3731,66 +3731,66 @@ define void @truncstore_v8i32_v8i16(<8 x i32> %x, ptr %p, <8 x i32> %mask) { ; SSE2-NEXT: pmovmskb %xmm2, %eax ; SSE2-NEXT: notl %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne .LBB11_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB11_9 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne .LBB11_3 -; SSE2-NEXT: .LBB11_4: # %else2 +; SSE2-NEXT: jne .LBB11_10 +; SSE2-NEXT: .LBB11_2: # %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne .LBB11_5 -; SSE2-NEXT: .LBB11_6: # %else4 +; SSE2-NEXT: jne .LBB11_11 +; SSE2-NEXT: .LBB11_3: # %else4 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne .LBB11_7 -; SSE2-NEXT: .LBB11_8: # %else6 +; SSE2-NEXT: jne .LBB11_12 +; SSE2-NEXT: .LBB11_4: # %else6 ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: jne .LBB11_9 -; SSE2-NEXT: .LBB11_10: # %else8 +; SSE2-NEXT: jne .LBB11_13 +; SSE2-NEXT: .LBB11_5: # %else8 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: jne .LBB11_11 -; SSE2-NEXT: .LBB11_12: # %else10 +; SSE2-NEXT: jne .LBB11_14 +; SSE2-NEXT: .LBB11_6: # %else10 ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: jne .LBB11_13 -; SSE2-NEXT: .LBB11_14: # %else12 -; SSE2-NEXT: testb $-128, %al ; SSE2-NEXT: jne .LBB11_15 -; SSE2-NEXT: .LBB11_16: # %else14 +; SSE2-NEXT: .LBB11_7: # %else12 +; SSE2-NEXT: testb $-128, %al +; SSE2-NEXT: jne .LBB11_16 +; SSE2-NEXT: .LBB11_8: # %else14 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB11_1: # %cond.store +; SSE2-NEXT: .LBB11_9: # %cond.store ; SSE2-NEXT: movd %xmm0, %ecx ; SSE2-NEXT: movw %cx, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB11_4 -; SSE2-NEXT: .LBB11_3: # %cond.store1 +; SSE2-NEXT: je .LBB11_2 +; SSE2-NEXT: .LBB11_10: # %cond.store1 ; SSE2-NEXT: pextrw $1, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 2(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je .LBB11_6 -; SSE2-NEXT: .LBB11_5: # %cond.store3 +; SSE2-NEXT: je .LBB11_3 +; SSE2-NEXT: .LBB11_11: # %cond.store3 ; SSE2-NEXT: pextrw $2, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 4(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je .LBB11_8 -; SSE2-NEXT: .LBB11_7: # %cond.store5 +; SSE2-NEXT: je .LBB11_4 +; SSE2-NEXT: .LBB11_12: # %cond.store5 ; SSE2-NEXT: pextrw $3, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 6(%rdi) ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: je .LBB11_10 -; SSE2-NEXT: .LBB11_9: # %cond.store7 +; SSE2-NEXT: je .LBB11_5 +; SSE2-NEXT: .LBB11_13: # %cond.store7 ; SSE2-NEXT: pextrw $4, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 8(%rdi) ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je .LBB11_12 -; SSE2-NEXT: .LBB11_11: # %cond.store9 +; SSE2-NEXT: je .LBB11_6 +; SSE2-NEXT: .LBB11_14: # %cond.store9 ; SSE2-NEXT: pextrw $5, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 10(%rdi) ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: je .LBB11_14 -; SSE2-NEXT: .LBB11_13: # %cond.store11 +; SSE2-NEXT: je .LBB11_7 +; SSE2-NEXT: .LBB11_15: # %cond.store11 ; SSE2-NEXT: pextrw $6, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 12(%rdi) ; SSE2-NEXT: testb $-128, %al -; SSE2-NEXT: je .LBB11_16 -; SSE2-NEXT: .LBB11_15: # %cond.store13 +; SSE2-NEXT: je .LBB11_8 +; SSE2-NEXT: .LBB11_16: # %cond.store13 ; SSE2-NEXT: pextrw $7, %xmm0, %eax ; SSE2-NEXT: movw %ax, 14(%rdi) ; SSE2-NEXT: retq @@ -3808,59 +3808,59 @@ define void @truncstore_v8i32_v8i16(<8 x i32> %x, ptr %p, <8 x i32> %mask) { ; SSE4-NEXT: pmovmskb %xmm2, %eax ; SSE4-NEXT: notl %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB11_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB11_9 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB11_3 -; SSE4-NEXT: .LBB11_4: # %else2 +; SSE4-NEXT: jne .LBB11_10 +; SSE4-NEXT: .LBB11_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB11_5 -; SSE4-NEXT: .LBB11_6: # %else4 +; SSE4-NEXT: jne .LBB11_11 +; SSE4-NEXT: .LBB11_3: # %else4 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne .LBB11_7 -; SSE4-NEXT: .LBB11_8: # %else6 +; SSE4-NEXT: jne .LBB11_12 +; SSE4-NEXT: .LBB11_4: # %else6 ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: jne .LBB11_9 -; SSE4-NEXT: .LBB11_10: # %else8 +; SSE4-NEXT: jne .LBB11_13 +; SSE4-NEXT: .LBB11_5: # %else8 ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: jne .LBB11_11 -; SSE4-NEXT: .LBB11_12: # %else10 +; SSE4-NEXT: jne .LBB11_14 +; SSE4-NEXT: .LBB11_6: # %else10 ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: jne .LBB11_13 -; SSE4-NEXT: .LBB11_14: # %else12 -; SSE4-NEXT: testb $-128, %al ; SSE4-NEXT: jne .LBB11_15 -; SSE4-NEXT: .LBB11_16: # %else14 +; SSE4-NEXT: .LBB11_7: # %else12 +; SSE4-NEXT: testb $-128, %al +; SSE4-NEXT: jne .LBB11_16 +; SSE4-NEXT: .LBB11_8: # %else14 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB11_1: # %cond.store +; SSE4-NEXT: .LBB11_9: # %cond.store ; SSE4-NEXT: pextrw $0, %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB11_4 -; SSE4-NEXT: .LBB11_3: # %cond.store1 +; SSE4-NEXT: je .LBB11_2 +; SSE4-NEXT: .LBB11_10: # %cond.store1 ; SSE4-NEXT: pextrw $1, %xmm0, 2(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB11_6 -; SSE4-NEXT: .LBB11_5: # %cond.store3 +; SSE4-NEXT: je .LBB11_3 +; SSE4-NEXT: .LBB11_11: # %cond.store3 ; SSE4-NEXT: pextrw $2, %xmm0, 4(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB11_8 -; SSE4-NEXT: .LBB11_7: # %cond.store5 +; SSE4-NEXT: je .LBB11_4 +; SSE4-NEXT: .LBB11_12: # %cond.store5 ; SSE4-NEXT: pextrw $3, %xmm0, 6(%rdi) ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: je .LBB11_10 -; SSE4-NEXT: .LBB11_9: # %cond.store7 +; SSE4-NEXT: je .LBB11_5 +; SSE4-NEXT: .LBB11_13: # %cond.store7 ; SSE4-NEXT: pextrw $4, %xmm0, 8(%rdi) ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: je .LBB11_12 -; SSE4-NEXT: .LBB11_11: # %cond.store9 +; SSE4-NEXT: je .LBB11_6 +; SSE4-NEXT: .LBB11_14: # %cond.store9 ; SSE4-NEXT: pextrw $5, %xmm0, 10(%rdi) ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: je .LBB11_14 -; SSE4-NEXT: .LBB11_13: # %cond.store11 +; SSE4-NEXT: je .LBB11_7 +; SSE4-NEXT: .LBB11_15: # %cond.store11 ; SSE4-NEXT: pextrw $6, %xmm0, 12(%rdi) ; SSE4-NEXT: testb $-128, %al -; SSE4-NEXT: je .LBB11_16 -; SSE4-NEXT: .LBB11_15: # %cond.store13 +; SSE4-NEXT: je .LBB11_8 +; SSE4-NEXT: .LBB11_16: # %cond.store13 ; SSE4-NEXT: pextrw $7, %xmm0, 14(%rdi) ; SSE4-NEXT: retq ; @@ -3877,60 +3877,60 @@ define void @truncstore_v8i32_v8i16(<8 x i32> %x, ptr %p, <8 x i32> %mask) { ; AVX1-NEXT: vmovmskps %ymm1, %eax ; AVX1-NEXT: notl %eax ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne .LBB11_1 -; AVX1-NEXT: # %bb.2: # %else +; AVX1-NEXT: jne .LBB11_9 +; AVX1-NEXT: # %bb.1: # %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne .LBB11_3 -; AVX1-NEXT: .LBB11_4: # %else2 +; AVX1-NEXT: jne .LBB11_10 +; AVX1-NEXT: .LBB11_2: # %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne .LBB11_5 -; AVX1-NEXT: .LBB11_6: # %else4 +; AVX1-NEXT: jne .LBB11_11 +; AVX1-NEXT: .LBB11_3: # %else4 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne .LBB11_7 -; AVX1-NEXT: .LBB11_8: # %else6 +; AVX1-NEXT: jne .LBB11_12 +; AVX1-NEXT: .LBB11_4: # %else6 ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: jne .LBB11_9 -; AVX1-NEXT: .LBB11_10: # %else8 +; AVX1-NEXT: jne .LBB11_13 +; AVX1-NEXT: .LBB11_5: # %else8 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: jne .LBB11_11 -; AVX1-NEXT: .LBB11_12: # %else10 +; AVX1-NEXT: jne .LBB11_14 +; AVX1-NEXT: .LBB11_6: # %else10 ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: jne .LBB11_13 -; AVX1-NEXT: .LBB11_14: # %else12 -; AVX1-NEXT: testb $-128, %al ; AVX1-NEXT: jne .LBB11_15 -; AVX1-NEXT: .LBB11_16: # %else14 +; AVX1-NEXT: .LBB11_7: # %else12 +; AVX1-NEXT: testb $-128, %al +; AVX1-NEXT: jne .LBB11_16 +; AVX1-NEXT: .LBB11_8: # %else14 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB11_1: # %cond.store +; AVX1-NEXT: .LBB11_9: # %cond.store ; AVX1-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je .LBB11_4 -; AVX1-NEXT: .LBB11_3: # %cond.store1 +; AVX1-NEXT: je .LBB11_2 +; AVX1-NEXT: .LBB11_10: # %cond.store1 ; AVX1-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je .LBB11_6 -; AVX1-NEXT: .LBB11_5: # %cond.store3 +; AVX1-NEXT: je .LBB11_3 +; AVX1-NEXT: .LBB11_11: # %cond.store3 ; AVX1-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB11_8 -; AVX1-NEXT: .LBB11_7: # %cond.store5 +; AVX1-NEXT: je .LBB11_4 +; AVX1-NEXT: .LBB11_12: # %cond.store5 ; AVX1-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: je .LBB11_10 -; AVX1-NEXT: .LBB11_9: # %cond.store7 +; AVX1-NEXT: je .LBB11_5 +; AVX1-NEXT: .LBB11_13: # %cond.store7 ; AVX1-NEXT: vpextrw $4, %xmm0, 8(%rdi) ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je .LBB11_12 -; AVX1-NEXT: .LBB11_11: # %cond.store9 +; AVX1-NEXT: je .LBB11_6 +; AVX1-NEXT: .LBB11_14: # %cond.store9 ; AVX1-NEXT: vpextrw $5, %xmm0, 10(%rdi) ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: je .LBB11_14 -; AVX1-NEXT: .LBB11_13: # %cond.store11 +; AVX1-NEXT: je .LBB11_7 +; AVX1-NEXT: .LBB11_15: # %cond.store11 ; AVX1-NEXT: vpextrw $6, %xmm0, 12(%rdi) ; AVX1-NEXT: testb $-128, %al -; AVX1-NEXT: je .LBB11_16 -; AVX1-NEXT: .LBB11_15: # %cond.store13 +; AVX1-NEXT: je .LBB11_8 +; AVX1-NEXT: .LBB11_16: # %cond.store13 ; AVX1-NEXT: vpextrw $7, %xmm0, 14(%rdi) ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq @@ -3944,60 +3944,60 @@ define void @truncstore_v8i32_v8i16(<8 x i32> %x, ptr %p, <8 x i32> %mask) { ; AVX2-NEXT: vmovmskps %ymm1, %eax ; AVX2-NEXT: notl %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne .LBB11_1 -; AVX2-NEXT: # %bb.2: # %else +; AVX2-NEXT: jne .LBB11_9 +; AVX2-NEXT: # %bb.1: # %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne .LBB11_3 -; AVX2-NEXT: .LBB11_4: # %else2 +; AVX2-NEXT: jne .LBB11_10 +; AVX2-NEXT: .LBB11_2: # %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne .LBB11_5 -; AVX2-NEXT: .LBB11_6: # %else4 +; AVX2-NEXT: jne .LBB11_11 +; AVX2-NEXT: .LBB11_3: # %else4 ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: jne .LBB11_7 -; AVX2-NEXT: .LBB11_8: # %else6 +; AVX2-NEXT: jne .LBB11_12 +; AVX2-NEXT: .LBB11_4: # %else6 ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: jne .LBB11_9 -; AVX2-NEXT: .LBB11_10: # %else8 +; AVX2-NEXT: jne .LBB11_13 +; AVX2-NEXT: .LBB11_5: # %else8 ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: jne .LBB11_11 -; AVX2-NEXT: .LBB11_12: # %else10 +; AVX2-NEXT: jne .LBB11_14 +; AVX2-NEXT: .LBB11_6: # %else10 ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: jne .LBB11_13 -; AVX2-NEXT: .LBB11_14: # %else12 -; AVX2-NEXT: testb $-128, %al ; AVX2-NEXT: jne .LBB11_15 -; AVX2-NEXT: .LBB11_16: # %else14 +; AVX2-NEXT: .LBB11_7: # %else12 +; AVX2-NEXT: testb $-128, %al +; AVX2-NEXT: jne .LBB11_16 +; AVX2-NEXT: .LBB11_8: # %else14 ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; AVX2-NEXT: .LBB11_1: # %cond.store +; AVX2-NEXT: .LBB11_9: # %cond.store ; AVX2-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je .LBB11_4 -; AVX2-NEXT: .LBB11_3: # %cond.store1 +; AVX2-NEXT: je .LBB11_2 +; AVX2-NEXT: .LBB11_10: # %cond.store1 ; AVX2-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je .LBB11_6 -; AVX2-NEXT: .LBB11_5: # %cond.store3 +; AVX2-NEXT: je .LBB11_3 +; AVX2-NEXT: .LBB11_11: # %cond.store3 ; AVX2-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je .LBB11_8 -; AVX2-NEXT: .LBB11_7: # %cond.store5 +; AVX2-NEXT: je .LBB11_4 +; AVX2-NEXT: .LBB11_12: # %cond.store5 ; AVX2-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: je .LBB11_10 -; AVX2-NEXT: .LBB11_9: # %cond.store7 +; AVX2-NEXT: je .LBB11_5 +; AVX2-NEXT: .LBB11_13: # %cond.store7 ; AVX2-NEXT: vpextrw $4, %xmm0, 8(%rdi) ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: je .LBB11_12 -; AVX2-NEXT: .LBB11_11: # %cond.store9 +; AVX2-NEXT: je .LBB11_6 +; AVX2-NEXT: .LBB11_14: # %cond.store9 ; AVX2-NEXT: vpextrw $5, %xmm0, 10(%rdi) ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: je .LBB11_14 -; AVX2-NEXT: .LBB11_13: # %cond.store11 +; AVX2-NEXT: je .LBB11_7 +; AVX2-NEXT: .LBB11_15: # %cond.store11 ; AVX2-NEXT: vpextrw $6, %xmm0, 12(%rdi) ; AVX2-NEXT: testb $-128, %al -; AVX2-NEXT: je .LBB11_16 -; AVX2-NEXT: .LBB11_15: # %cond.store13 +; AVX2-NEXT: je .LBB11_8 +; AVX2-NEXT: .LBB11_16: # %cond.store13 ; AVX2-NEXT: vpextrw $7, %xmm0, 14(%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq @@ -4010,60 +4010,60 @@ define void @truncstore_v8i32_v8i16(<8 x i32> %x, ptr %p, <8 x i32> %mask) { ; AVX512F-NEXT: vpmovdw %zmm0, %ymm0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB11_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB11_9 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB11_3 -; AVX512F-NEXT: .LBB11_4: # %else2 +; AVX512F-NEXT: jne .LBB11_10 +; AVX512F-NEXT: .LBB11_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB11_5 -; AVX512F-NEXT: .LBB11_6: # %else4 +; AVX512F-NEXT: jne .LBB11_11 +; AVX512F-NEXT: .LBB11_3: # %else4 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne .LBB11_7 -; AVX512F-NEXT: .LBB11_8: # %else6 +; AVX512F-NEXT: jne .LBB11_12 +; AVX512F-NEXT: .LBB11_4: # %else6 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne .LBB11_9 -; AVX512F-NEXT: .LBB11_10: # %else8 +; AVX512F-NEXT: jne .LBB11_13 +; AVX512F-NEXT: .LBB11_5: # %else8 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne .LBB11_11 -; AVX512F-NEXT: .LBB11_12: # %else10 +; AVX512F-NEXT: jne .LBB11_14 +; AVX512F-NEXT: .LBB11_6: # %else10 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne .LBB11_13 -; AVX512F-NEXT: .LBB11_14: # %else12 -; AVX512F-NEXT: testb $-128, %al ; AVX512F-NEXT: jne .LBB11_15 -; AVX512F-NEXT: .LBB11_16: # %else14 +; AVX512F-NEXT: .LBB11_7: # %else12 +; AVX512F-NEXT: testb $-128, %al +; AVX512F-NEXT: jne .LBB11_16 +; AVX512F-NEXT: .LBB11_8: # %else14 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB11_1: # %cond.store +; AVX512F-NEXT: .LBB11_9: # %cond.store ; AVX512F-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB11_4 -; AVX512F-NEXT: .LBB11_3: # %cond.store1 +; AVX512F-NEXT: je .LBB11_2 +; AVX512F-NEXT: .LBB11_10: # %cond.store1 ; AVX512F-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB11_6 -; AVX512F-NEXT: .LBB11_5: # %cond.store3 +; AVX512F-NEXT: je .LBB11_3 +; AVX512F-NEXT: .LBB11_11: # %cond.store3 ; AVX512F-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB11_8 -; AVX512F-NEXT: .LBB11_7: # %cond.store5 +; AVX512F-NEXT: je .LBB11_4 +; AVX512F-NEXT: .LBB11_12: # %cond.store5 ; AVX512F-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je .LBB11_10 -; AVX512F-NEXT: .LBB11_9: # %cond.store7 +; AVX512F-NEXT: je .LBB11_5 +; AVX512F-NEXT: .LBB11_13: # %cond.store7 ; AVX512F-NEXT: vpextrw $4, %xmm0, 8(%rdi) ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je .LBB11_12 -; AVX512F-NEXT: .LBB11_11: # %cond.store9 +; AVX512F-NEXT: je .LBB11_6 +; AVX512F-NEXT: .LBB11_14: # %cond.store9 ; AVX512F-NEXT: vpextrw $5, %xmm0, 10(%rdi) ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je .LBB11_14 -; AVX512F-NEXT: .LBB11_13: # %cond.store11 +; AVX512F-NEXT: je .LBB11_7 +; AVX512F-NEXT: .LBB11_15: # %cond.store11 ; AVX512F-NEXT: vpextrw $6, %xmm0, 12(%rdi) ; AVX512F-NEXT: testb $-128, %al -; AVX512F-NEXT: je .LBB11_16 -; AVX512F-NEXT: .LBB11_15: # %cond.store13 +; AVX512F-NEXT: je .LBB11_8 +; AVX512F-NEXT: .LBB11_16: # %cond.store13 ; AVX512F-NEXT: vpextrw $7, %xmm0, 14(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -4074,60 +4074,60 @@ define void @truncstore_v8i32_v8i16(<8 x i32> %x, ptr %p, <8 x i32> %mask) { ; AVX512FVL-NEXT: vpmovdw %ymm0, %xmm0 ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB11_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB11_9 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB11_3 -; AVX512FVL-NEXT: .LBB11_4: # %else2 +; AVX512FVL-NEXT: jne .LBB11_10 +; AVX512FVL-NEXT: .LBB11_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB11_5 -; AVX512FVL-NEXT: .LBB11_6: # %else4 +; AVX512FVL-NEXT: jne .LBB11_11 +; AVX512FVL-NEXT: .LBB11_3: # %else4 ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: jne .LBB11_7 -; AVX512FVL-NEXT: .LBB11_8: # %else6 +; AVX512FVL-NEXT: jne .LBB11_12 +; AVX512FVL-NEXT: .LBB11_4: # %else6 ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: jne .LBB11_9 -; AVX512FVL-NEXT: .LBB11_10: # %else8 +; AVX512FVL-NEXT: jne .LBB11_13 +; AVX512FVL-NEXT: .LBB11_5: # %else8 ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: jne .LBB11_11 -; AVX512FVL-NEXT: .LBB11_12: # %else10 +; AVX512FVL-NEXT: jne .LBB11_14 +; AVX512FVL-NEXT: .LBB11_6: # %else10 ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: jne .LBB11_13 -; AVX512FVL-NEXT: .LBB11_14: # %else12 -; AVX512FVL-NEXT: testb $-128, %al ; AVX512FVL-NEXT: jne .LBB11_15 -; AVX512FVL-NEXT: .LBB11_16: # %else14 +; AVX512FVL-NEXT: .LBB11_7: # %else12 +; AVX512FVL-NEXT: testb $-128, %al +; AVX512FVL-NEXT: jne .LBB11_16 +; AVX512FVL-NEXT: .LBB11_8: # %else14 ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB11_1: # %cond.store +; AVX512FVL-NEXT: .LBB11_9: # %cond.store ; AVX512FVL-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB11_4 -; AVX512FVL-NEXT: .LBB11_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB11_2 +; AVX512FVL-NEXT: .LBB11_10: # %cond.store1 ; AVX512FVL-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB11_6 -; AVX512FVL-NEXT: .LBB11_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB11_3 +; AVX512FVL-NEXT: .LBB11_11: # %cond.store3 ; AVX512FVL-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB11_8 -; AVX512FVL-NEXT: .LBB11_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB11_4 +; AVX512FVL-NEXT: .LBB11_12: # %cond.store5 ; AVX512FVL-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: je .LBB11_10 -; AVX512FVL-NEXT: .LBB11_9: # %cond.store7 +; AVX512FVL-NEXT: je .LBB11_5 +; AVX512FVL-NEXT: .LBB11_13: # %cond.store7 ; AVX512FVL-NEXT: vpextrw $4, %xmm0, 8(%rdi) ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: je .LBB11_12 -; AVX512FVL-NEXT: .LBB11_11: # %cond.store9 +; AVX512FVL-NEXT: je .LBB11_6 +; AVX512FVL-NEXT: .LBB11_14: # %cond.store9 ; AVX512FVL-NEXT: vpextrw $5, %xmm0, 10(%rdi) ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: je .LBB11_14 -; AVX512FVL-NEXT: .LBB11_13: # %cond.store11 +; AVX512FVL-NEXT: je .LBB11_7 +; AVX512FVL-NEXT: .LBB11_15: # %cond.store11 ; AVX512FVL-NEXT: vpextrw $6, %xmm0, 12(%rdi) ; AVX512FVL-NEXT: testb $-128, %al -; AVX512FVL-NEXT: je .LBB11_16 -; AVX512FVL-NEXT: .LBB11_15: # %cond.store13 +; AVX512FVL-NEXT: je .LBB11_8 +; AVX512FVL-NEXT: .LBB11_16: # %cond.store13 ; AVX512FVL-NEXT: vpextrw $7, %xmm0, 14(%rdi) ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq @@ -4173,59 +4173,59 @@ define void @truncstore_v8i32_v8i8(<8 x i32> %x, ptr %p, <8 x i32> %mask) { ; SSE2-NEXT: notl %eax ; SSE2-NEXT: testb $1, %al ; SSE2-NEXT: movd %xmm0, %ecx -; SSE2-NEXT: jne .LBB12_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB12_12 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne .LBB12_3 -; SSE2-NEXT: .LBB12_4: # %else2 +; SSE2-NEXT: jne .LBB12_13 +; SSE2-NEXT: .LBB12_2: # %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne .LBB12_5 -; SSE2-NEXT: .LBB12_6: # %else4 +; SSE2-NEXT: jne .LBB12_14 +; SSE2-NEXT: .LBB12_3: # %else4 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je .LBB12_8 -; SSE2-NEXT: .LBB12_7: # %cond.store5 +; SSE2-NEXT: je .LBB12_5 +; SSE2-NEXT: .LBB12_4: # %cond.store5 ; SSE2-NEXT: shrl $24, %ecx ; SSE2-NEXT: movb %cl, 3(%rdi) -; SSE2-NEXT: .LBB12_8: # %else6 +; SSE2-NEXT: .LBB12_5: # %else6 ; SSE2-NEXT: testb $16, %al ; SSE2-NEXT: pextrw $2, %xmm0, %ecx -; SSE2-NEXT: je .LBB12_10 -; SSE2-NEXT: # %bb.9: # %cond.store7 +; SSE2-NEXT: je .LBB12_7 +; SSE2-NEXT: # %bb.6: # %cond.store7 ; SSE2-NEXT: movb %cl, 4(%rdi) -; SSE2-NEXT: .LBB12_10: # %else8 +; SSE2-NEXT: .LBB12_7: # %else8 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je .LBB12_12 -; SSE2-NEXT: # %bb.11: # %cond.store9 +; SSE2-NEXT: je .LBB12_9 +; SSE2-NEXT: # %bb.8: # %cond.store9 ; SSE2-NEXT: movb %ch, 5(%rdi) -; SSE2-NEXT: .LBB12_12: # %else10 +; SSE2-NEXT: .LBB12_9: # %else10 ; SSE2-NEXT: testb $64, %al ; SSE2-NEXT: pextrw $3, %xmm0, %ecx -; SSE2-NEXT: jne .LBB12_13 -; SSE2-NEXT: # %bb.14: # %else12 -; SSE2-NEXT: testb $-128, %al ; SSE2-NEXT: jne .LBB12_15 -; SSE2-NEXT: .LBB12_16: # %else14 +; SSE2-NEXT: # %bb.10: # %else12 +; SSE2-NEXT: testb $-128, %al +; SSE2-NEXT: jne .LBB12_16 +; SSE2-NEXT: .LBB12_11: # %else14 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB12_1: # %cond.store +; SSE2-NEXT: .LBB12_12: # %cond.store ; SSE2-NEXT: movb %cl, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB12_4 -; SSE2-NEXT: .LBB12_3: # %cond.store1 +; SSE2-NEXT: je .LBB12_2 +; SSE2-NEXT: .LBB12_13: # %cond.store1 ; SSE2-NEXT: movb %ch, 1(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je .LBB12_6 -; SSE2-NEXT: .LBB12_5: # %cond.store3 +; SSE2-NEXT: je .LBB12_3 +; SSE2-NEXT: .LBB12_14: # %cond.store3 ; SSE2-NEXT: movl %ecx, %edx ; SSE2-NEXT: shrl $16, %edx ; SSE2-NEXT: movb %dl, 2(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne .LBB12_7 -; SSE2-NEXT: jmp .LBB12_8 -; SSE2-NEXT: .LBB12_13: # %cond.store11 +; SSE2-NEXT: jne .LBB12_4 +; SSE2-NEXT: jmp .LBB12_5 +; SSE2-NEXT: .LBB12_15: # %cond.store11 ; SSE2-NEXT: movb %cl, 6(%rdi) ; SSE2-NEXT: testb $-128, %al -; SSE2-NEXT: je .LBB12_16 -; SSE2-NEXT: .LBB12_15: # %cond.store13 +; SSE2-NEXT: je .LBB12_11 +; SSE2-NEXT: .LBB12_16: # %cond.store13 ; SSE2-NEXT: movb %ch, 7(%rdi) ; SSE2-NEXT: retq ; @@ -4244,59 +4244,59 @@ define void @truncstore_v8i32_v8i8(<8 x i32> %x, ptr %p, <8 x i32> %mask) { ; SSE4-NEXT: pmovmskb %xmm2, %eax ; SSE4-NEXT: notl %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB12_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB12_9 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB12_3 -; SSE4-NEXT: .LBB12_4: # %else2 +; SSE4-NEXT: jne .LBB12_10 +; SSE4-NEXT: .LBB12_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB12_5 -; SSE4-NEXT: .LBB12_6: # %else4 +; SSE4-NEXT: jne .LBB12_11 +; SSE4-NEXT: .LBB12_3: # %else4 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne .LBB12_7 -; SSE4-NEXT: .LBB12_8: # %else6 +; SSE4-NEXT: jne .LBB12_12 +; SSE4-NEXT: .LBB12_4: # %else6 ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: jne .LBB12_9 -; SSE4-NEXT: .LBB12_10: # %else8 +; SSE4-NEXT: jne .LBB12_13 +; SSE4-NEXT: .LBB12_5: # %else8 ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: jne .LBB12_11 -; SSE4-NEXT: .LBB12_12: # %else10 +; SSE4-NEXT: jne .LBB12_14 +; SSE4-NEXT: .LBB12_6: # %else10 ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: jne .LBB12_13 -; SSE4-NEXT: .LBB12_14: # %else12 -; SSE4-NEXT: testb $-128, %al ; SSE4-NEXT: jne .LBB12_15 -; SSE4-NEXT: .LBB12_16: # %else14 +; SSE4-NEXT: .LBB12_7: # %else12 +; SSE4-NEXT: testb $-128, %al +; SSE4-NEXT: jne .LBB12_16 +; SSE4-NEXT: .LBB12_8: # %else14 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB12_1: # %cond.store +; SSE4-NEXT: .LBB12_9: # %cond.store ; SSE4-NEXT: pextrb $0, %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB12_4 -; SSE4-NEXT: .LBB12_3: # %cond.store1 +; SSE4-NEXT: je .LBB12_2 +; SSE4-NEXT: .LBB12_10: # %cond.store1 ; SSE4-NEXT: pextrb $1, %xmm0, 1(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB12_6 -; SSE4-NEXT: .LBB12_5: # %cond.store3 +; SSE4-NEXT: je .LBB12_3 +; SSE4-NEXT: .LBB12_11: # %cond.store3 ; SSE4-NEXT: pextrb $2, %xmm0, 2(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB12_8 -; SSE4-NEXT: .LBB12_7: # %cond.store5 +; SSE4-NEXT: je .LBB12_4 +; SSE4-NEXT: .LBB12_12: # %cond.store5 ; SSE4-NEXT: pextrb $3, %xmm0, 3(%rdi) ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: je .LBB12_10 -; SSE4-NEXT: .LBB12_9: # %cond.store7 +; SSE4-NEXT: je .LBB12_5 +; SSE4-NEXT: .LBB12_13: # %cond.store7 ; SSE4-NEXT: pextrb $4, %xmm0, 4(%rdi) ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: je .LBB12_12 -; SSE4-NEXT: .LBB12_11: # %cond.store9 +; SSE4-NEXT: je .LBB12_6 +; SSE4-NEXT: .LBB12_14: # %cond.store9 ; SSE4-NEXT: pextrb $5, %xmm0, 5(%rdi) ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: je .LBB12_14 -; SSE4-NEXT: .LBB12_13: # %cond.store11 +; SSE4-NEXT: je .LBB12_7 +; SSE4-NEXT: .LBB12_15: # %cond.store11 ; SSE4-NEXT: pextrb $6, %xmm0, 6(%rdi) ; SSE4-NEXT: testb $-128, %al -; SSE4-NEXT: je .LBB12_16 -; SSE4-NEXT: .LBB12_15: # %cond.store13 +; SSE4-NEXT: je .LBB12_8 +; SSE4-NEXT: .LBB12_16: # %cond.store13 ; SSE4-NEXT: pextrb $7, %xmm0, 7(%rdi) ; SSE4-NEXT: retq ; @@ -4315,60 +4315,60 @@ define void @truncstore_v8i32_v8i8(<8 x i32> %x, ptr %p, <8 x i32> %mask) { ; AVX1-NEXT: vmovmskps %ymm1, %eax ; AVX1-NEXT: notl %eax ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne .LBB12_1 -; AVX1-NEXT: # %bb.2: # %else +; AVX1-NEXT: jne .LBB12_9 +; AVX1-NEXT: # %bb.1: # %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne .LBB12_3 -; AVX1-NEXT: .LBB12_4: # %else2 +; AVX1-NEXT: jne .LBB12_10 +; AVX1-NEXT: .LBB12_2: # %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne .LBB12_5 -; AVX1-NEXT: .LBB12_6: # %else4 +; AVX1-NEXT: jne .LBB12_11 +; AVX1-NEXT: .LBB12_3: # %else4 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne .LBB12_7 -; AVX1-NEXT: .LBB12_8: # %else6 +; AVX1-NEXT: jne .LBB12_12 +; AVX1-NEXT: .LBB12_4: # %else6 ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: jne .LBB12_9 -; AVX1-NEXT: .LBB12_10: # %else8 +; AVX1-NEXT: jne .LBB12_13 +; AVX1-NEXT: .LBB12_5: # %else8 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: jne .LBB12_11 -; AVX1-NEXT: .LBB12_12: # %else10 +; AVX1-NEXT: jne .LBB12_14 +; AVX1-NEXT: .LBB12_6: # %else10 ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: jne .LBB12_13 -; AVX1-NEXT: .LBB12_14: # %else12 -; AVX1-NEXT: testb $-128, %al ; AVX1-NEXT: jne .LBB12_15 -; AVX1-NEXT: .LBB12_16: # %else14 +; AVX1-NEXT: .LBB12_7: # %else12 +; AVX1-NEXT: testb $-128, %al +; AVX1-NEXT: jne .LBB12_16 +; AVX1-NEXT: .LBB12_8: # %else14 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB12_1: # %cond.store +; AVX1-NEXT: .LBB12_9: # %cond.store ; AVX1-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je .LBB12_4 -; AVX1-NEXT: .LBB12_3: # %cond.store1 +; AVX1-NEXT: je .LBB12_2 +; AVX1-NEXT: .LBB12_10: # %cond.store1 ; AVX1-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je .LBB12_6 -; AVX1-NEXT: .LBB12_5: # %cond.store3 +; AVX1-NEXT: je .LBB12_3 +; AVX1-NEXT: .LBB12_11: # %cond.store3 ; AVX1-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB12_8 -; AVX1-NEXT: .LBB12_7: # %cond.store5 +; AVX1-NEXT: je .LBB12_4 +; AVX1-NEXT: .LBB12_12: # %cond.store5 ; AVX1-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: je .LBB12_10 -; AVX1-NEXT: .LBB12_9: # %cond.store7 +; AVX1-NEXT: je .LBB12_5 +; AVX1-NEXT: .LBB12_13: # %cond.store7 ; AVX1-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je .LBB12_12 -; AVX1-NEXT: .LBB12_11: # %cond.store9 +; AVX1-NEXT: je .LBB12_6 +; AVX1-NEXT: .LBB12_14: # %cond.store9 ; AVX1-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: je .LBB12_14 -; AVX1-NEXT: .LBB12_13: # %cond.store11 +; AVX1-NEXT: je .LBB12_7 +; AVX1-NEXT: .LBB12_15: # %cond.store11 ; AVX1-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX1-NEXT: testb $-128, %al -; AVX1-NEXT: je .LBB12_16 -; AVX1-NEXT: .LBB12_15: # %cond.store13 +; AVX1-NEXT: je .LBB12_8 +; AVX1-NEXT: .LBB12_16: # %cond.store13 ; AVX1-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq @@ -4385,60 +4385,60 @@ define void @truncstore_v8i32_v8i8(<8 x i32> %x, ptr %p, <8 x i32> %mask) { ; AVX2-NEXT: vmovmskps %ymm1, %eax ; AVX2-NEXT: notl %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne .LBB12_1 -; AVX2-NEXT: # %bb.2: # %else +; AVX2-NEXT: jne .LBB12_9 +; AVX2-NEXT: # %bb.1: # %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne .LBB12_3 -; AVX2-NEXT: .LBB12_4: # %else2 +; AVX2-NEXT: jne .LBB12_10 +; AVX2-NEXT: .LBB12_2: # %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne .LBB12_5 -; AVX2-NEXT: .LBB12_6: # %else4 +; AVX2-NEXT: jne .LBB12_11 +; AVX2-NEXT: .LBB12_3: # %else4 ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: jne .LBB12_7 -; AVX2-NEXT: .LBB12_8: # %else6 +; AVX2-NEXT: jne .LBB12_12 +; AVX2-NEXT: .LBB12_4: # %else6 ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: jne .LBB12_9 -; AVX2-NEXT: .LBB12_10: # %else8 +; AVX2-NEXT: jne .LBB12_13 +; AVX2-NEXT: .LBB12_5: # %else8 ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: jne .LBB12_11 -; AVX2-NEXT: .LBB12_12: # %else10 +; AVX2-NEXT: jne .LBB12_14 +; AVX2-NEXT: .LBB12_6: # %else10 ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: jne .LBB12_13 -; AVX2-NEXT: .LBB12_14: # %else12 -; AVX2-NEXT: testb $-128, %al ; AVX2-NEXT: jne .LBB12_15 -; AVX2-NEXT: .LBB12_16: # %else14 +; AVX2-NEXT: .LBB12_7: # %else12 +; AVX2-NEXT: testb $-128, %al +; AVX2-NEXT: jne .LBB12_16 +; AVX2-NEXT: .LBB12_8: # %else14 ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; AVX2-NEXT: .LBB12_1: # %cond.store +; AVX2-NEXT: .LBB12_9: # %cond.store ; AVX2-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je .LBB12_4 -; AVX2-NEXT: .LBB12_3: # %cond.store1 +; AVX2-NEXT: je .LBB12_2 +; AVX2-NEXT: .LBB12_10: # %cond.store1 ; AVX2-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je .LBB12_6 -; AVX2-NEXT: .LBB12_5: # %cond.store3 +; AVX2-NEXT: je .LBB12_3 +; AVX2-NEXT: .LBB12_11: # %cond.store3 ; AVX2-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je .LBB12_8 -; AVX2-NEXT: .LBB12_7: # %cond.store5 +; AVX2-NEXT: je .LBB12_4 +; AVX2-NEXT: .LBB12_12: # %cond.store5 ; AVX2-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: je .LBB12_10 -; AVX2-NEXT: .LBB12_9: # %cond.store7 +; AVX2-NEXT: je .LBB12_5 +; AVX2-NEXT: .LBB12_13: # %cond.store7 ; AVX2-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: je .LBB12_12 -; AVX2-NEXT: .LBB12_11: # %cond.store9 +; AVX2-NEXT: je .LBB12_6 +; AVX2-NEXT: .LBB12_14: # %cond.store9 ; AVX2-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: je .LBB12_14 -; AVX2-NEXT: .LBB12_13: # %cond.store11 +; AVX2-NEXT: je .LBB12_7 +; AVX2-NEXT: .LBB12_15: # %cond.store11 ; AVX2-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX2-NEXT: testb $-128, %al -; AVX2-NEXT: je .LBB12_16 -; AVX2-NEXT: .LBB12_15: # %cond.store13 +; AVX2-NEXT: je .LBB12_8 +; AVX2-NEXT: .LBB12_16: # %cond.store13 ; AVX2-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq @@ -4451,60 +4451,60 @@ define void @truncstore_v8i32_v8i8(<8 x i32> %x, ptr %p, <8 x i32> %mask) { ; AVX512F-NEXT: vpmovdb %zmm0, %xmm0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB12_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB12_9 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB12_3 -; AVX512F-NEXT: .LBB12_4: # %else2 +; AVX512F-NEXT: jne .LBB12_10 +; AVX512F-NEXT: .LBB12_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB12_5 -; AVX512F-NEXT: .LBB12_6: # %else4 +; AVX512F-NEXT: jne .LBB12_11 +; AVX512F-NEXT: .LBB12_3: # %else4 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne .LBB12_7 -; AVX512F-NEXT: .LBB12_8: # %else6 +; AVX512F-NEXT: jne .LBB12_12 +; AVX512F-NEXT: .LBB12_4: # %else6 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne .LBB12_9 -; AVX512F-NEXT: .LBB12_10: # %else8 +; AVX512F-NEXT: jne .LBB12_13 +; AVX512F-NEXT: .LBB12_5: # %else8 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne .LBB12_11 -; AVX512F-NEXT: .LBB12_12: # %else10 +; AVX512F-NEXT: jne .LBB12_14 +; AVX512F-NEXT: .LBB12_6: # %else10 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne .LBB12_13 -; AVX512F-NEXT: .LBB12_14: # %else12 -; AVX512F-NEXT: testb $-128, %al ; AVX512F-NEXT: jne .LBB12_15 -; AVX512F-NEXT: .LBB12_16: # %else14 +; AVX512F-NEXT: .LBB12_7: # %else12 +; AVX512F-NEXT: testb $-128, %al +; AVX512F-NEXT: jne .LBB12_16 +; AVX512F-NEXT: .LBB12_8: # %else14 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB12_1: # %cond.store +; AVX512F-NEXT: .LBB12_9: # %cond.store ; AVX512F-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB12_4 -; AVX512F-NEXT: .LBB12_3: # %cond.store1 +; AVX512F-NEXT: je .LBB12_2 +; AVX512F-NEXT: .LBB12_10: # %cond.store1 ; AVX512F-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB12_6 -; AVX512F-NEXT: .LBB12_5: # %cond.store3 +; AVX512F-NEXT: je .LBB12_3 +; AVX512F-NEXT: .LBB12_11: # %cond.store3 ; AVX512F-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB12_8 -; AVX512F-NEXT: .LBB12_7: # %cond.store5 +; AVX512F-NEXT: je .LBB12_4 +; AVX512F-NEXT: .LBB12_12: # %cond.store5 ; AVX512F-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je .LBB12_10 -; AVX512F-NEXT: .LBB12_9: # %cond.store7 +; AVX512F-NEXT: je .LBB12_5 +; AVX512F-NEXT: .LBB12_13: # %cond.store7 ; AVX512F-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je .LBB12_12 -; AVX512F-NEXT: .LBB12_11: # %cond.store9 +; AVX512F-NEXT: je .LBB12_6 +; AVX512F-NEXT: .LBB12_14: # %cond.store9 ; AVX512F-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je .LBB12_14 -; AVX512F-NEXT: .LBB12_13: # %cond.store11 +; AVX512F-NEXT: je .LBB12_7 +; AVX512F-NEXT: .LBB12_15: # %cond.store11 ; AVX512F-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX512F-NEXT: testb $-128, %al -; AVX512F-NEXT: je .LBB12_16 -; AVX512F-NEXT: .LBB12_15: # %cond.store13 +; AVX512F-NEXT: je .LBB12_8 +; AVX512F-NEXT: .LBB12_16: # %cond.store13 ; AVX512F-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -4515,60 +4515,60 @@ define void @truncstore_v8i32_v8i8(<8 x i32> %x, ptr %p, <8 x i32> %mask) { ; AVX512FVL-NEXT: vpmovdb %ymm0, %xmm0 ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB12_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB12_9 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB12_3 -; AVX512FVL-NEXT: .LBB12_4: # %else2 +; AVX512FVL-NEXT: jne .LBB12_10 +; AVX512FVL-NEXT: .LBB12_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB12_5 -; AVX512FVL-NEXT: .LBB12_6: # %else4 +; AVX512FVL-NEXT: jne .LBB12_11 +; AVX512FVL-NEXT: .LBB12_3: # %else4 ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: jne .LBB12_7 -; AVX512FVL-NEXT: .LBB12_8: # %else6 +; AVX512FVL-NEXT: jne .LBB12_12 +; AVX512FVL-NEXT: .LBB12_4: # %else6 ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: jne .LBB12_9 -; AVX512FVL-NEXT: .LBB12_10: # %else8 +; AVX512FVL-NEXT: jne .LBB12_13 +; AVX512FVL-NEXT: .LBB12_5: # %else8 ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: jne .LBB12_11 -; AVX512FVL-NEXT: .LBB12_12: # %else10 +; AVX512FVL-NEXT: jne .LBB12_14 +; AVX512FVL-NEXT: .LBB12_6: # %else10 ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: jne .LBB12_13 -; AVX512FVL-NEXT: .LBB12_14: # %else12 -; AVX512FVL-NEXT: testb $-128, %al ; AVX512FVL-NEXT: jne .LBB12_15 -; AVX512FVL-NEXT: .LBB12_16: # %else14 +; AVX512FVL-NEXT: .LBB12_7: # %else12 +; AVX512FVL-NEXT: testb $-128, %al +; AVX512FVL-NEXT: jne .LBB12_16 +; AVX512FVL-NEXT: .LBB12_8: # %else14 ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB12_1: # %cond.store +; AVX512FVL-NEXT: .LBB12_9: # %cond.store ; AVX512FVL-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB12_4 -; AVX512FVL-NEXT: .LBB12_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB12_2 +; AVX512FVL-NEXT: .LBB12_10: # %cond.store1 ; AVX512FVL-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB12_6 -; AVX512FVL-NEXT: .LBB12_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB12_3 +; AVX512FVL-NEXT: .LBB12_11: # %cond.store3 ; AVX512FVL-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB12_8 -; AVX512FVL-NEXT: .LBB12_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB12_4 +; AVX512FVL-NEXT: .LBB12_12: # %cond.store5 ; AVX512FVL-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: je .LBB12_10 -; AVX512FVL-NEXT: .LBB12_9: # %cond.store7 +; AVX512FVL-NEXT: je .LBB12_5 +; AVX512FVL-NEXT: .LBB12_13: # %cond.store7 ; AVX512FVL-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: je .LBB12_12 -; AVX512FVL-NEXT: .LBB12_11: # %cond.store9 +; AVX512FVL-NEXT: je .LBB12_6 +; AVX512FVL-NEXT: .LBB12_14: # %cond.store9 ; AVX512FVL-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: je .LBB12_14 -; AVX512FVL-NEXT: .LBB12_13: # %cond.store11 +; AVX512FVL-NEXT: je .LBB12_7 +; AVX512FVL-NEXT: .LBB12_15: # %cond.store11 ; AVX512FVL-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX512FVL-NEXT: testb $-128, %al -; AVX512FVL-NEXT: je .LBB12_16 -; AVX512FVL-NEXT: .LBB12_15: # %cond.store13 +; AVX512FVL-NEXT: je .LBB12_8 +; AVX512FVL-NEXT: .LBB12_16: # %cond.store13 ; AVX512FVL-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq @@ -4608,34 +4608,34 @@ define void @truncstore_v4i32_v4i16(<4 x i32> %x, ptr %p, <4 x i32> %mask) { ; SSE2-NEXT: movmskps %xmm2, %eax ; SSE2-NEXT: xorl $15, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne .LBB13_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB13_5 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne .LBB13_3 -; SSE2-NEXT: .LBB13_4: # %else2 +; SSE2-NEXT: jne .LBB13_6 +; SSE2-NEXT: .LBB13_2: # %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne .LBB13_5 -; SSE2-NEXT: .LBB13_6: # %else4 -; SSE2-NEXT: testb $8, %al ; SSE2-NEXT: jne .LBB13_7 -; SSE2-NEXT: .LBB13_8: # %else6 +; SSE2-NEXT: .LBB13_3: # %else4 +; SSE2-NEXT: testb $8, %al +; SSE2-NEXT: jne .LBB13_8 +; SSE2-NEXT: .LBB13_4: # %else6 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB13_1: # %cond.store +; SSE2-NEXT: .LBB13_5: # %cond.store ; SSE2-NEXT: movd %xmm0, %ecx ; SSE2-NEXT: movw %cx, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB13_4 -; SSE2-NEXT: .LBB13_3: # %cond.store1 +; SSE2-NEXT: je .LBB13_2 +; SSE2-NEXT: .LBB13_6: # %cond.store1 ; SSE2-NEXT: pextrw $1, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 2(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je .LBB13_6 -; SSE2-NEXT: .LBB13_5: # %cond.store3 +; SSE2-NEXT: je .LBB13_3 +; SSE2-NEXT: .LBB13_7: # %cond.store3 ; SSE2-NEXT: pextrw $2, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 4(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je .LBB13_8 -; SSE2-NEXT: .LBB13_7: # %cond.store5 +; SSE2-NEXT: je .LBB13_4 +; SSE2-NEXT: .LBB13_8: # %cond.store5 ; SSE2-NEXT: pextrw $3, %xmm0, %eax ; SSE2-NEXT: movw %ax, 6(%rdi) ; SSE2-NEXT: retq @@ -4648,31 +4648,31 @@ define void @truncstore_v4i32_v4i16(<4 x i32> %x, ptr %p, <4 x i32> %mask) { ; SSE4-NEXT: movmskps %xmm2, %eax ; SSE4-NEXT: xorl $15, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB13_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB13_5 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB13_3 -; SSE4-NEXT: .LBB13_4: # %else2 +; SSE4-NEXT: jne .LBB13_6 +; SSE4-NEXT: .LBB13_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB13_5 -; SSE4-NEXT: .LBB13_6: # %else4 -; SSE4-NEXT: testb $8, %al ; SSE4-NEXT: jne .LBB13_7 -; SSE4-NEXT: .LBB13_8: # %else6 +; SSE4-NEXT: .LBB13_3: # %else4 +; SSE4-NEXT: testb $8, %al +; SSE4-NEXT: jne .LBB13_8 +; SSE4-NEXT: .LBB13_4: # %else6 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB13_1: # %cond.store +; SSE4-NEXT: .LBB13_5: # %cond.store ; SSE4-NEXT: pextrw $0, %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB13_4 -; SSE4-NEXT: .LBB13_3: # %cond.store1 +; SSE4-NEXT: je .LBB13_2 +; SSE4-NEXT: .LBB13_6: # %cond.store1 ; SSE4-NEXT: pextrw $1, %xmm0, 2(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB13_6 -; SSE4-NEXT: .LBB13_5: # %cond.store3 +; SSE4-NEXT: je .LBB13_3 +; SSE4-NEXT: .LBB13_7: # %cond.store3 ; SSE4-NEXT: pextrw $2, %xmm0, 4(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB13_8 -; SSE4-NEXT: .LBB13_7: # %cond.store5 +; SSE4-NEXT: je .LBB13_4 +; SSE4-NEXT: .LBB13_8: # %cond.store5 ; SSE4-NEXT: pextrw $3, %xmm0, 6(%rdi) ; SSE4-NEXT: retq ; @@ -4684,31 +4684,31 @@ define void @truncstore_v4i32_v4i16(<4 x i32> %x, ptr %p, <4 x i32> %mask) { ; AVX-NEXT: vmovmskps %xmm1, %eax ; AVX-NEXT: xorl $15, %eax ; AVX-NEXT: testb $1, %al -; AVX-NEXT: jne .LBB13_1 -; AVX-NEXT: # %bb.2: # %else +; AVX-NEXT: jne .LBB13_5 +; AVX-NEXT: # %bb.1: # %else ; AVX-NEXT: testb $2, %al -; AVX-NEXT: jne .LBB13_3 -; AVX-NEXT: .LBB13_4: # %else2 +; AVX-NEXT: jne .LBB13_6 +; AVX-NEXT: .LBB13_2: # %else2 ; AVX-NEXT: testb $4, %al -; AVX-NEXT: jne .LBB13_5 -; AVX-NEXT: .LBB13_6: # %else4 -; AVX-NEXT: testb $8, %al ; AVX-NEXT: jne .LBB13_7 -; AVX-NEXT: .LBB13_8: # %else6 +; AVX-NEXT: .LBB13_3: # %else4 +; AVX-NEXT: testb $8, %al +; AVX-NEXT: jne .LBB13_8 +; AVX-NEXT: .LBB13_4: # %else6 ; AVX-NEXT: retq -; AVX-NEXT: .LBB13_1: # %cond.store +; AVX-NEXT: .LBB13_5: # %cond.store ; AVX-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX-NEXT: testb $2, %al -; AVX-NEXT: je .LBB13_4 -; AVX-NEXT: .LBB13_3: # %cond.store1 +; AVX-NEXT: je .LBB13_2 +; AVX-NEXT: .LBB13_6: # %cond.store1 ; AVX-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX-NEXT: testb $4, %al -; AVX-NEXT: je .LBB13_6 -; AVX-NEXT: .LBB13_5: # %cond.store3 +; AVX-NEXT: je .LBB13_3 +; AVX-NEXT: .LBB13_7: # %cond.store3 ; AVX-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX-NEXT: testb $8, %al -; AVX-NEXT: je .LBB13_8 -; AVX-NEXT: .LBB13_7: # %cond.store5 +; AVX-NEXT: je .LBB13_4 +; AVX-NEXT: .LBB13_8: # %cond.store5 ; AVX-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX-NEXT: retq ; @@ -4719,32 +4719,32 @@ define void @truncstore_v4i32_v4i16(<4 x i32> %x, ptr %p, <4 x i32> %mask) { ; AVX512F-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB13_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB13_5 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB13_3 -; AVX512F-NEXT: .LBB13_4: # %else2 +; AVX512F-NEXT: jne .LBB13_6 +; AVX512F-NEXT: .LBB13_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB13_5 -; AVX512F-NEXT: .LBB13_6: # %else4 -; AVX512F-NEXT: testb $8, %al ; AVX512F-NEXT: jne .LBB13_7 -; AVX512F-NEXT: .LBB13_8: # %else6 +; AVX512F-NEXT: .LBB13_3: # %else4 +; AVX512F-NEXT: testb $8, %al +; AVX512F-NEXT: jne .LBB13_8 +; AVX512F-NEXT: .LBB13_4: # %else6 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB13_1: # %cond.store +; AVX512F-NEXT: .LBB13_5: # %cond.store ; AVX512F-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB13_4 -; AVX512F-NEXT: .LBB13_3: # %cond.store1 +; AVX512F-NEXT: je .LBB13_2 +; AVX512F-NEXT: .LBB13_6: # %cond.store1 ; AVX512F-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB13_6 -; AVX512F-NEXT: .LBB13_5: # %cond.store3 +; AVX512F-NEXT: je .LBB13_3 +; AVX512F-NEXT: .LBB13_7: # %cond.store3 ; AVX512F-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB13_8 -; AVX512F-NEXT: .LBB13_7: # %cond.store5 +; AVX512F-NEXT: je .LBB13_4 +; AVX512F-NEXT: .LBB13_8: # %cond.store5 ; AVX512F-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -4755,31 +4755,31 @@ define void @truncstore_v4i32_v4i16(<4 x i32> %x, ptr %p, <4 x i32> %mask) { ; AVX512FVL-NEXT: vpmovdw %xmm0, %xmm0 ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB13_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB13_5 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB13_3 -; AVX512FVL-NEXT: .LBB13_4: # %else2 +; AVX512FVL-NEXT: jne .LBB13_6 +; AVX512FVL-NEXT: .LBB13_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB13_5 -; AVX512FVL-NEXT: .LBB13_6: # %else4 -; AVX512FVL-NEXT: testb $8, %al ; AVX512FVL-NEXT: jne .LBB13_7 -; AVX512FVL-NEXT: .LBB13_8: # %else6 +; AVX512FVL-NEXT: .LBB13_3: # %else4 +; AVX512FVL-NEXT: testb $8, %al +; AVX512FVL-NEXT: jne .LBB13_8 +; AVX512FVL-NEXT: .LBB13_4: # %else6 ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB13_1: # %cond.store +; AVX512FVL-NEXT: .LBB13_5: # %cond.store ; AVX512FVL-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB13_4 -; AVX512FVL-NEXT: .LBB13_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB13_2 +; AVX512FVL-NEXT: .LBB13_6: # %cond.store1 ; AVX512FVL-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB13_6 -; AVX512FVL-NEXT: .LBB13_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB13_3 +; AVX512FVL-NEXT: .LBB13_7: # %cond.store3 ; AVX512FVL-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB13_8 -; AVX512FVL-NEXT: .LBB13_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB13_4 +; AVX512FVL-NEXT: .LBB13_8: # %cond.store5 ; AVX512FVL-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX512FVL-NEXT: retq ; @@ -4817,33 +4817,33 @@ define void @truncstore_v4i32_v4i8(<4 x i32> %x, ptr %p, <4 x i32> %mask) { ; SSE2-NEXT: xorl $15, %ecx ; SSE2-NEXT: testb $1, %cl ; SSE2-NEXT: movd %xmm0, %eax -; SSE2-NEXT: jne .LBB14_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB14_5 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %cl -; SSE2-NEXT: jne .LBB14_3 -; SSE2-NEXT: .LBB14_4: # %else2 +; SSE2-NEXT: jne .LBB14_6 +; SSE2-NEXT: .LBB14_2: # %else2 ; SSE2-NEXT: testb $4, %cl -; SSE2-NEXT: jne .LBB14_5 -; SSE2-NEXT: .LBB14_6: # %else4 -; SSE2-NEXT: testb $8, %cl ; SSE2-NEXT: jne .LBB14_7 -; SSE2-NEXT: .LBB14_8: # %else6 +; SSE2-NEXT: .LBB14_3: # %else4 +; SSE2-NEXT: testb $8, %cl +; SSE2-NEXT: jne .LBB14_8 +; SSE2-NEXT: .LBB14_4: # %else6 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB14_1: # %cond.store +; SSE2-NEXT: .LBB14_5: # %cond.store ; SSE2-NEXT: movb %al, (%rdi) ; SSE2-NEXT: testb $2, %cl -; SSE2-NEXT: je .LBB14_4 -; SSE2-NEXT: .LBB14_3: # %cond.store1 +; SSE2-NEXT: je .LBB14_2 +; SSE2-NEXT: .LBB14_6: # %cond.store1 ; SSE2-NEXT: movb %ah, 1(%rdi) ; SSE2-NEXT: testb $4, %cl -; SSE2-NEXT: je .LBB14_6 -; SSE2-NEXT: .LBB14_5: # %cond.store3 +; SSE2-NEXT: je .LBB14_3 +; SSE2-NEXT: .LBB14_7: # %cond.store3 ; SSE2-NEXT: movl %eax, %edx ; SSE2-NEXT: shrl $16, %edx ; SSE2-NEXT: movb %dl, 2(%rdi) ; SSE2-NEXT: testb $8, %cl -; SSE2-NEXT: je .LBB14_8 -; SSE2-NEXT: .LBB14_7: # %cond.store5 +; SSE2-NEXT: je .LBB14_4 +; SSE2-NEXT: .LBB14_8: # %cond.store5 ; SSE2-NEXT: shrl $24, %eax ; SSE2-NEXT: movb %al, 3(%rdi) ; SSE2-NEXT: retq @@ -4856,31 +4856,31 @@ define void @truncstore_v4i32_v4i8(<4 x i32> %x, ptr %p, <4 x i32> %mask) { ; SSE4-NEXT: movmskps %xmm2, %eax ; SSE4-NEXT: xorl $15, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB14_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB14_5 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB14_3 -; SSE4-NEXT: .LBB14_4: # %else2 +; SSE4-NEXT: jne .LBB14_6 +; SSE4-NEXT: .LBB14_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB14_5 -; SSE4-NEXT: .LBB14_6: # %else4 -; SSE4-NEXT: testb $8, %al ; SSE4-NEXT: jne .LBB14_7 -; SSE4-NEXT: .LBB14_8: # %else6 +; SSE4-NEXT: .LBB14_3: # %else4 +; SSE4-NEXT: testb $8, %al +; SSE4-NEXT: jne .LBB14_8 +; SSE4-NEXT: .LBB14_4: # %else6 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB14_1: # %cond.store +; SSE4-NEXT: .LBB14_5: # %cond.store ; SSE4-NEXT: pextrb $0, %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB14_4 -; SSE4-NEXT: .LBB14_3: # %cond.store1 +; SSE4-NEXT: je .LBB14_2 +; SSE4-NEXT: .LBB14_6: # %cond.store1 ; SSE4-NEXT: pextrb $1, %xmm0, 1(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB14_6 -; SSE4-NEXT: .LBB14_5: # %cond.store3 +; SSE4-NEXT: je .LBB14_3 +; SSE4-NEXT: .LBB14_7: # %cond.store3 ; SSE4-NEXT: pextrb $2, %xmm0, 2(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB14_8 -; SSE4-NEXT: .LBB14_7: # %cond.store5 +; SSE4-NEXT: je .LBB14_4 +; SSE4-NEXT: .LBB14_8: # %cond.store5 ; SSE4-NEXT: pextrb $3, %xmm0, 3(%rdi) ; SSE4-NEXT: retq ; @@ -4892,31 +4892,31 @@ define void @truncstore_v4i32_v4i8(<4 x i32> %x, ptr %p, <4 x i32> %mask) { ; AVX-NEXT: vmovmskps %xmm1, %eax ; AVX-NEXT: xorl $15, %eax ; AVX-NEXT: testb $1, %al -; AVX-NEXT: jne .LBB14_1 -; AVX-NEXT: # %bb.2: # %else +; AVX-NEXT: jne .LBB14_5 +; AVX-NEXT: # %bb.1: # %else ; AVX-NEXT: testb $2, %al -; AVX-NEXT: jne .LBB14_3 -; AVX-NEXT: .LBB14_4: # %else2 +; AVX-NEXT: jne .LBB14_6 +; AVX-NEXT: .LBB14_2: # %else2 ; AVX-NEXT: testb $4, %al -; AVX-NEXT: jne .LBB14_5 -; AVX-NEXT: .LBB14_6: # %else4 -; AVX-NEXT: testb $8, %al ; AVX-NEXT: jne .LBB14_7 -; AVX-NEXT: .LBB14_8: # %else6 +; AVX-NEXT: .LBB14_3: # %else4 +; AVX-NEXT: testb $8, %al +; AVX-NEXT: jne .LBB14_8 +; AVX-NEXT: .LBB14_4: # %else6 ; AVX-NEXT: retq -; AVX-NEXT: .LBB14_1: # %cond.store +; AVX-NEXT: .LBB14_5: # %cond.store ; AVX-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX-NEXT: testb $2, %al -; AVX-NEXT: je .LBB14_4 -; AVX-NEXT: .LBB14_3: # %cond.store1 +; AVX-NEXT: je .LBB14_2 +; AVX-NEXT: .LBB14_6: # %cond.store1 ; AVX-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX-NEXT: testb $4, %al -; AVX-NEXT: je .LBB14_6 -; AVX-NEXT: .LBB14_5: # %cond.store3 +; AVX-NEXT: je .LBB14_3 +; AVX-NEXT: .LBB14_7: # %cond.store3 ; AVX-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX-NEXT: testb $8, %al -; AVX-NEXT: je .LBB14_8 -; AVX-NEXT: .LBB14_7: # %cond.store5 +; AVX-NEXT: je .LBB14_4 +; AVX-NEXT: .LBB14_8: # %cond.store5 ; AVX-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX-NEXT: retq ; @@ -4927,32 +4927,32 @@ define void @truncstore_v4i32_v4i8(<4 x i32> %x, ptr %p, <4 x i32> %mask) { ; AVX512F-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u] ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB14_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB14_5 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB14_3 -; AVX512F-NEXT: .LBB14_4: # %else2 +; AVX512F-NEXT: jne .LBB14_6 +; AVX512F-NEXT: .LBB14_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB14_5 -; AVX512F-NEXT: .LBB14_6: # %else4 -; AVX512F-NEXT: testb $8, %al ; AVX512F-NEXT: jne .LBB14_7 -; AVX512F-NEXT: .LBB14_8: # %else6 +; AVX512F-NEXT: .LBB14_3: # %else4 +; AVX512F-NEXT: testb $8, %al +; AVX512F-NEXT: jne .LBB14_8 +; AVX512F-NEXT: .LBB14_4: # %else6 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB14_1: # %cond.store +; AVX512F-NEXT: .LBB14_5: # %cond.store ; AVX512F-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB14_4 -; AVX512F-NEXT: .LBB14_3: # %cond.store1 +; AVX512F-NEXT: je .LBB14_2 +; AVX512F-NEXT: .LBB14_6: # %cond.store1 ; AVX512F-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB14_6 -; AVX512F-NEXT: .LBB14_5: # %cond.store3 +; AVX512F-NEXT: je .LBB14_3 +; AVX512F-NEXT: .LBB14_7: # %cond.store3 ; AVX512F-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB14_8 -; AVX512F-NEXT: .LBB14_7: # %cond.store5 +; AVX512F-NEXT: je .LBB14_4 +; AVX512F-NEXT: .LBB14_8: # %cond.store5 ; AVX512F-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -4963,31 +4963,31 @@ define void @truncstore_v4i32_v4i8(<4 x i32> %x, ptr %p, <4 x i32> %mask) { ; AVX512FVL-NEXT: vpmovdb %xmm0, %xmm0 ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB14_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB14_5 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB14_3 -; AVX512FVL-NEXT: .LBB14_4: # %else2 +; AVX512FVL-NEXT: jne .LBB14_6 +; AVX512FVL-NEXT: .LBB14_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB14_5 -; AVX512FVL-NEXT: .LBB14_6: # %else4 -; AVX512FVL-NEXT: testb $8, %al ; AVX512FVL-NEXT: jne .LBB14_7 -; AVX512FVL-NEXT: .LBB14_8: # %else6 +; AVX512FVL-NEXT: .LBB14_3: # %else4 +; AVX512FVL-NEXT: testb $8, %al +; AVX512FVL-NEXT: jne .LBB14_8 +; AVX512FVL-NEXT: .LBB14_4: # %else6 ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB14_1: # %cond.store +; AVX512FVL-NEXT: .LBB14_5: # %cond.store ; AVX512FVL-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB14_4 -; AVX512FVL-NEXT: .LBB14_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB14_2 +; AVX512FVL-NEXT: .LBB14_6: # %cond.store1 ; AVX512FVL-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB14_6 -; AVX512FVL-NEXT: .LBB14_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB14_3 +; AVX512FVL-NEXT: .LBB14_7: # %cond.store3 ; AVX512FVL-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB14_8 -; AVX512FVL-NEXT: .LBB14_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB14_4 +; AVX512FVL-NEXT: .LBB14_8: # %cond.store5 ; AVX512FVL-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512FVL-NEXT: retq ; @@ -5031,203 +5031,203 @@ define void @truncstore_v32i16_v32i8(<32 x i16> %x, ptr %p, <32 x i8> %mask) { ; SSE2-NEXT: orl %ecx, %eax ; SSE2-NEXT: testb $1, %al ; SSE2-NEXT: movd %xmm0, %ecx -; SSE2-NEXT: jne .LBB15_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB15_57 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne .LBB15_3 -; SSE2-NEXT: .LBB15_4: # %else2 +; SSE2-NEXT: jne .LBB15_58 +; SSE2-NEXT: .LBB15_2: # %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne .LBB15_5 -; SSE2-NEXT: .LBB15_6: # %else4 +; SSE2-NEXT: jne .LBB15_59 +; SSE2-NEXT: .LBB15_3: # %else4 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je .LBB15_8 -; SSE2-NEXT: .LBB15_7: # %cond.store5 +; SSE2-NEXT: je .LBB15_5 +; SSE2-NEXT: .LBB15_4: # %cond.store5 ; SSE2-NEXT: shrl $24, %ecx ; SSE2-NEXT: movb %cl, 3(%rdi) -; SSE2-NEXT: .LBB15_8: # %else6 +; SSE2-NEXT: .LBB15_5: # %else6 ; SSE2-NEXT: testb $16, %al ; SSE2-NEXT: pextrw $2, %xmm0, %ecx -; SSE2-NEXT: je .LBB15_10 -; SSE2-NEXT: # %bb.9: # %cond.store7 +; SSE2-NEXT: je .LBB15_7 +; SSE2-NEXT: # %bb.6: # %cond.store7 ; SSE2-NEXT: movb %cl, 4(%rdi) -; SSE2-NEXT: .LBB15_10: # %else8 +; SSE2-NEXT: .LBB15_7: # %else8 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je .LBB15_12 -; SSE2-NEXT: # %bb.11: # %cond.store9 +; SSE2-NEXT: je .LBB15_9 +; SSE2-NEXT: # %bb.8: # %cond.store9 ; SSE2-NEXT: movb %ch, 5(%rdi) -; SSE2-NEXT: .LBB15_12: # %else10 +; SSE2-NEXT: .LBB15_9: # %else10 ; SSE2-NEXT: testb $64, %al ; SSE2-NEXT: pextrw $3, %xmm0, %ecx -; SSE2-NEXT: je .LBB15_14 -; SSE2-NEXT: # %bb.13: # %cond.store11 +; SSE2-NEXT: je .LBB15_11 +; SSE2-NEXT: # %bb.10: # %cond.store11 ; SSE2-NEXT: movb %cl, 6(%rdi) -; SSE2-NEXT: .LBB15_14: # %else12 +; SSE2-NEXT: .LBB15_11: # %else12 ; SSE2-NEXT: testb %al, %al -; SSE2-NEXT: jns .LBB15_16 -; SSE2-NEXT: # %bb.15: # %cond.store13 +; SSE2-NEXT: jns .LBB15_13 +; SSE2-NEXT: # %bb.12: # %cond.store13 ; SSE2-NEXT: movb %ch, 7(%rdi) -; SSE2-NEXT: .LBB15_16: # %else14 +; SSE2-NEXT: .LBB15_13: # %else14 ; SSE2-NEXT: testl $256, %eax # imm = 0x100 ; SSE2-NEXT: pextrw $4, %xmm0, %ecx -; SSE2-NEXT: je .LBB15_18 -; SSE2-NEXT: # %bb.17: # %cond.store15 +; SSE2-NEXT: je .LBB15_15 +; SSE2-NEXT: # %bb.14: # %cond.store15 ; SSE2-NEXT: movb %cl, 8(%rdi) -; SSE2-NEXT: .LBB15_18: # %else16 +; SSE2-NEXT: .LBB15_15: # %else16 ; SSE2-NEXT: testl $512, %eax # imm = 0x200 -; SSE2-NEXT: je .LBB15_20 -; SSE2-NEXT: # %bb.19: # %cond.store17 +; SSE2-NEXT: je .LBB15_17 +; SSE2-NEXT: # %bb.16: # %cond.store17 ; SSE2-NEXT: movb %ch, 9(%rdi) -; SSE2-NEXT: .LBB15_20: # %else18 +; SSE2-NEXT: .LBB15_17: # %else18 ; SSE2-NEXT: testl $1024, %eax # imm = 0x400 ; SSE2-NEXT: pextrw $5, %xmm0, %ecx -; SSE2-NEXT: je .LBB15_22 -; SSE2-NEXT: # %bb.21: # %cond.store19 +; SSE2-NEXT: je .LBB15_19 +; SSE2-NEXT: # %bb.18: # %cond.store19 ; SSE2-NEXT: movb %cl, 10(%rdi) -; SSE2-NEXT: .LBB15_22: # %else20 +; SSE2-NEXT: .LBB15_19: # %else20 ; SSE2-NEXT: testl $2048, %eax # imm = 0x800 -; SSE2-NEXT: je .LBB15_24 -; SSE2-NEXT: # %bb.23: # %cond.store21 +; SSE2-NEXT: je .LBB15_21 +; SSE2-NEXT: # %bb.20: # %cond.store21 ; SSE2-NEXT: movb %ch, 11(%rdi) -; SSE2-NEXT: .LBB15_24: # %else22 +; SSE2-NEXT: .LBB15_21: # %else22 ; SSE2-NEXT: testl $4096, %eax # imm = 0x1000 ; SSE2-NEXT: pextrw $6, %xmm0, %ecx -; SSE2-NEXT: je .LBB15_26 -; SSE2-NEXT: # %bb.25: # %cond.store23 +; SSE2-NEXT: je .LBB15_23 +; SSE2-NEXT: # %bb.22: # %cond.store23 ; SSE2-NEXT: movb %cl, 12(%rdi) -; SSE2-NEXT: .LBB15_26: # %else24 +; SSE2-NEXT: .LBB15_23: # %else24 ; SSE2-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE2-NEXT: je .LBB15_28 -; SSE2-NEXT: # %bb.27: # %cond.store25 +; SSE2-NEXT: je .LBB15_25 +; SSE2-NEXT: # %bb.24: # %cond.store25 ; SSE2-NEXT: movb %ch, 13(%rdi) -; SSE2-NEXT: .LBB15_28: # %else26 +; SSE2-NEXT: .LBB15_25: # %else26 ; SSE2-NEXT: pand %xmm6, %xmm3 ; SSE2-NEXT: pand %xmm6, %xmm2 ; SSE2-NEXT: testl $16384, %eax # imm = 0x4000 ; SSE2-NEXT: pextrw $7, %xmm0, %ecx -; SSE2-NEXT: je .LBB15_30 -; SSE2-NEXT: # %bb.29: # %cond.store27 +; SSE2-NEXT: je .LBB15_27 +; SSE2-NEXT: # %bb.26: # %cond.store27 ; SSE2-NEXT: movb %cl, 14(%rdi) -; SSE2-NEXT: .LBB15_30: # %else28 +; SSE2-NEXT: .LBB15_27: # %else28 ; SSE2-NEXT: packuswb %xmm3, %xmm2 ; SSE2-NEXT: testw %ax, %ax -; SSE2-NEXT: jns .LBB15_32 -; SSE2-NEXT: # %bb.31: # %cond.store29 +; SSE2-NEXT: jns .LBB15_29 +; SSE2-NEXT: # %bb.28: # %cond.store29 ; SSE2-NEXT: movb %ch, 15(%rdi) -; SSE2-NEXT: .LBB15_32: # %else30 +; SSE2-NEXT: .LBB15_29: # %else30 ; SSE2-NEXT: testl $65536, %eax # imm = 0x10000 ; SSE2-NEXT: movd %xmm2, %ecx -; SSE2-NEXT: jne .LBB15_33 -; SSE2-NEXT: # %bb.34: # %else32 +; SSE2-NEXT: jne .LBB15_60 +; SSE2-NEXT: # %bb.30: # %else32 ; SSE2-NEXT: testl $131072, %eax # imm = 0x20000 -; SSE2-NEXT: jne .LBB15_35 -; SSE2-NEXT: .LBB15_36: # %else34 +; SSE2-NEXT: jne .LBB15_61 +; SSE2-NEXT: .LBB15_31: # %else34 ; SSE2-NEXT: testl $262144, %eax # imm = 0x40000 -; SSE2-NEXT: jne .LBB15_37 -; SSE2-NEXT: .LBB15_38: # %else36 +; SSE2-NEXT: jne .LBB15_62 +; SSE2-NEXT: .LBB15_32: # %else36 ; SSE2-NEXT: testl $524288, %eax # imm = 0x80000 -; SSE2-NEXT: je .LBB15_40 -; SSE2-NEXT: .LBB15_39: # %cond.store37 +; SSE2-NEXT: je .LBB15_34 +; SSE2-NEXT: .LBB15_33: # %cond.store37 ; SSE2-NEXT: shrl $24, %ecx ; SSE2-NEXT: movb %cl, 19(%rdi) -; SSE2-NEXT: .LBB15_40: # %else38 +; SSE2-NEXT: .LBB15_34: # %else38 ; SSE2-NEXT: testl $1048576, %eax # imm = 0x100000 ; SSE2-NEXT: pextrw $2, %xmm2, %ecx -; SSE2-NEXT: je .LBB15_42 -; SSE2-NEXT: # %bb.41: # %cond.store39 +; SSE2-NEXT: je .LBB15_36 +; SSE2-NEXT: # %bb.35: # %cond.store39 ; SSE2-NEXT: movb %cl, 20(%rdi) -; SSE2-NEXT: .LBB15_42: # %else40 +; SSE2-NEXT: .LBB15_36: # %else40 ; SSE2-NEXT: testl $2097152, %eax # imm = 0x200000 -; SSE2-NEXT: je .LBB15_44 -; SSE2-NEXT: # %bb.43: # %cond.store41 +; SSE2-NEXT: je .LBB15_38 +; SSE2-NEXT: # %bb.37: # %cond.store41 ; SSE2-NEXT: movb %ch, 21(%rdi) -; SSE2-NEXT: .LBB15_44: # %else42 +; SSE2-NEXT: .LBB15_38: # %else42 ; SSE2-NEXT: testl $4194304, %eax # imm = 0x400000 ; SSE2-NEXT: pextrw $3, %xmm2, %ecx -; SSE2-NEXT: je .LBB15_46 -; SSE2-NEXT: # %bb.45: # %cond.store43 +; SSE2-NEXT: je .LBB15_40 +; SSE2-NEXT: # %bb.39: # %cond.store43 ; SSE2-NEXT: movb %cl, 22(%rdi) -; SSE2-NEXT: .LBB15_46: # %else44 +; SSE2-NEXT: .LBB15_40: # %else44 ; SSE2-NEXT: testl $8388608, %eax # imm = 0x800000 -; SSE2-NEXT: je .LBB15_48 -; SSE2-NEXT: # %bb.47: # %cond.store45 +; SSE2-NEXT: je .LBB15_42 +; SSE2-NEXT: # %bb.41: # %cond.store45 ; SSE2-NEXT: movb %ch, 23(%rdi) -; SSE2-NEXT: .LBB15_48: # %else46 +; SSE2-NEXT: .LBB15_42: # %else46 ; SSE2-NEXT: testl $16777216, %eax # imm = 0x1000000 ; SSE2-NEXT: pextrw $4, %xmm2, %ecx -; SSE2-NEXT: je .LBB15_50 -; SSE2-NEXT: # %bb.49: # %cond.store47 +; SSE2-NEXT: je .LBB15_44 +; SSE2-NEXT: # %bb.43: # %cond.store47 ; SSE2-NEXT: movb %cl, 24(%rdi) -; SSE2-NEXT: .LBB15_50: # %else48 +; SSE2-NEXT: .LBB15_44: # %else48 ; SSE2-NEXT: testl $33554432, %eax # imm = 0x2000000 -; SSE2-NEXT: je .LBB15_52 -; SSE2-NEXT: # %bb.51: # %cond.store49 +; SSE2-NEXT: je .LBB15_46 +; SSE2-NEXT: # %bb.45: # %cond.store49 ; SSE2-NEXT: movb %ch, 25(%rdi) -; SSE2-NEXT: .LBB15_52: # %else50 +; SSE2-NEXT: .LBB15_46: # %else50 ; SSE2-NEXT: testl $67108864, %eax # imm = 0x4000000 ; SSE2-NEXT: pextrw $5, %xmm2, %ecx -; SSE2-NEXT: je .LBB15_54 -; SSE2-NEXT: # %bb.53: # %cond.store51 +; SSE2-NEXT: je .LBB15_48 +; SSE2-NEXT: # %bb.47: # %cond.store51 ; SSE2-NEXT: movb %cl, 26(%rdi) -; SSE2-NEXT: .LBB15_54: # %else52 +; SSE2-NEXT: .LBB15_48: # %else52 ; SSE2-NEXT: testl $134217728, %eax # imm = 0x8000000 -; SSE2-NEXT: je .LBB15_56 -; SSE2-NEXT: # %bb.55: # %cond.store53 +; SSE2-NEXT: je .LBB15_50 +; SSE2-NEXT: # %bb.49: # %cond.store53 ; SSE2-NEXT: movb %ch, 27(%rdi) -; SSE2-NEXT: .LBB15_56: # %else54 +; SSE2-NEXT: .LBB15_50: # %else54 ; SSE2-NEXT: testl $268435456, %eax # imm = 0x10000000 ; SSE2-NEXT: pextrw $6, %xmm2, %ecx -; SSE2-NEXT: je .LBB15_58 -; SSE2-NEXT: # %bb.57: # %cond.store55 +; SSE2-NEXT: je .LBB15_52 +; SSE2-NEXT: # %bb.51: # %cond.store55 ; SSE2-NEXT: movb %cl, 28(%rdi) -; SSE2-NEXT: .LBB15_58: # %else56 +; SSE2-NEXT: .LBB15_52: # %else56 ; SSE2-NEXT: testl $536870912, %eax # imm = 0x20000000 -; SSE2-NEXT: je .LBB15_60 -; SSE2-NEXT: # %bb.59: # %cond.store57 +; SSE2-NEXT: je .LBB15_54 +; SSE2-NEXT: # %bb.53: # %cond.store57 ; SSE2-NEXT: movb %ch, 29(%rdi) -; SSE2-NEXT: .LBB15_60: # %else58 +; SSE2-NEXT: .LBB15_54: # %else58 ; SSE2-NEXT: testl $1073741824, %eax # imm = 0x40000000 ; SSE2-NEXT: pextrw $7, %xmm2, %ecx -; SSE2-NEXT: jne .LBB15_61 -; SSE2-NEXT: # %bb.62: # %else60 -; SSE2-NEXT: testl $-2147483648, %eax # imm = 0x80000000 ; SSE2-NEXT: jne .LBB15_63 -; SSE2-NEXT: .LBB15_64: # %else62 +; SSE2-NEXT: # %bb.55: # %else60 +; SSE2-NEXT: testl $-2147483648, %eax # imm = 0x80000000 +; SSE2-NEXT: jne .LBB15_64 +; SSE2-NEXT: .LBB15_56: # %else62 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB15_1: # %cond.store +; SSE2-NEXT: .LBB15_57: # %cond.store ; SSE2-NEXT: movb %cl, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB15_4 -; SSE2-NEXT: .LBB15_3: # %cond.store1 +; SSE2-NEXT: je .LBB15_2 +; SSE2-NEXT: .LBB15_58: # %cond.store1 ; SSE2-NEXT: movb %ch, 1(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je .LBB15_6 -; SSE2-NEXT: .LBB15_5: # %cond.store3 +; SSE2-NEXT: je .LBB15_3 +; SSE2-NEXT: .LBB15_59: # %cond.store3 ; SSE2-NEXT: movl %ecx, %edx ; SSE2-NEXT: shrl $16, %edx ; SSE2-NEXT: movb %dl, 2(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne .LBB15_7 -; SSE2-NEXT: jmp .LBB15_8 -; SSE2-NEXT: .LBB15_33: # %cond.store31 +; SSE2-NEXT: jne .LBB15_4 +; SSE2-NEXT: jmp .LBB15_5 +; SSE2-NEXT: .LBB15_60: # %cond.store31 ; SSE2-NEXT: movb %cl, 16(%rdi) ; SSE2-NEXT: testl $131072, %eax # imm = 0x20000 -; SSE2-NEXT: je .LBB15_36 -; SSE2-NEXT: .LBB15_35: # %cond.store33 +; SSE2-NEXT: je .LBB15_31 +; SSE2-NEXT: .LBB15_61: # %cond.store33 ; SSE2-NEXT: movb %ch, 17(%rdi) ; SSE2-NEXT: testl $262144, %eax # imm = 0x40000 -; SSE2-NEXT: je .LBB15_38 -; SSE2-NEXT: .LBB15_37: # %cond.store35 +; SSE2-NEXT: je .LBB15_32 +; SSE2-NEXT: .LBB15_62: # %cond.store35 ; SSE2-NEXT: movl %ecx, %edx ; SSE2-NEXT: shrl $16, %edx ; SSE2-NEXT: movb %dl, 18(%rdi) ; SSE2-NEXT: testl $524288, %eax # imm = 0x80000 -; SSE2-NEXT: jne .LBB15_39 -; SSE2-NEXT: jmp .LBB15_40 -; SSE2-NEXT: .LBB15_61: # %cond.store59 +; SSE2-NEXT: jne .LBB15_33 +; SSE2-NEXT: jmp .LBB15_34 +; SSE2-NEXT: .LBB15_63: # %cond.store59 ; SSE2-NEXT: movb %cl, 30(%rdi) ; SSE2-NEXT: testl $-2147483648, %eax # imm = 0x80000000 -; SSE2-NEXT: je .LBB15_64 -; SSE2-NEXT: .LBB15_63: # %cond.store61 +; SSE2-NEXT: je .LBB15_56 +; SSE2-NEXT: .LBB15_64: # %cond.store61 ; SSE2-NEXT: movb %ch, 31(%rdi) ; SSE2-NEXT: retq ; @@ -5247,227 +5247,227 @@ define void @truncstore_v32i16_v32i8(<32 x i16> %x, ptr %p, <32 x i8> %mask) { ; SSE4-NEXT: shll $16, %eax ; SSE4-NEXT: orl %ecx, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB15_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB15_35 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB15_3 -; SSE4-NEXT: .LBB15_4: # %else2 +; SSE4-NEXT: jne .LBB15_36 +; SSE4-NEXT: .LBB15_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB15_5 -; SSE4-NEXT: .LBB15_6: # %else4 +; SSE4-NEXT: jne .LBB15_37 +; SSE4-NEXT: .LBB15_3: # %else4 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne .LBB15_7 -; SSE4-NEXT: .LBB15_8: # %else6 +; SSE4-NEXT: jne .LBB15_38 +; SSE4-NEXT: .LBB15_4: # %else6 ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: jne .LBB15_9 -; SSE4-NEXT: .LBB15_10: # %else8 +; SSE4-NEXT: jne .LBB15_39 +; SSE4-NEXT: .LBB15_5: # %else8 ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: jne .LBB15_11 -; SSE4-NEXT: .LBB15_12: # %else10 +; SSE4-NEXT: jne .LBB15_40 +; SSE4-NEXT: .LBB15_6: # %else10 ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: jne .LBB15_13 -; SSE4-NEXT: .LBB15_14: # %else12 +; SSE4-NEXT: jne .LBB15_41 +; SSE4-NEXT: .LBB15_7: # %else12 ; SSE4-NEXT: testb %al, %al -; SSE4-NEXT: js .LBB15_15 -; SSE4-NEXT: .LBB15_16: # %else14 +; SSE4-NEXT: js .LBB15_42 +; SSE4-NEXT: .LBB15_8: # %else14 ; SSE4-NEXT: testl $256, %eax # imm = 0x100 -; SSE4-NEXT: jne .LBB15_17 -; SSE4-NEXT: .LBB15_18: # %else16 +; SSE4-NEXT: jne .LBB15_43 +; SSE4-NEXT: .LBB15_9: # %else16 ; SSE4-NEXT: testl $512, %eax # imm = 0x200 -; SSE4-NEXT: jne .LBB15_19 -; SSE4-NEXT: .LBB15_20: # %else18 +; SSE4-NEXT: jne .LBB15_44 +; SSE4-NEXT: .LBB15_10: # %else18 ; SSE4-NEXT: testl $1024, %eax # imm = 0x400 -; SSE4-NEXT: jne .LBB15_21 -; SSE4-NEXT: .LBB15_22: # %else20 +; SSE4-NEXT: jne .LBB15_45 +; SSE4-NEXT: .LBB15_11: # %else20 ; SSE4-NEXT: testl $2048, %eax # imm = 0x800 -; SSE4-NEXT: jne .LBB15_23 -; SSE4-NEXT: .LBB15_24: # %else22 +; SSE4-NEXT: jne .LBB15_46 +; SSE4-NEXT: .LBB15_12: # %else22 ; SSE4-NEXT: testl $4096, %eax # imm = 0x1000 -; SSE4-NEXT: jne .LBB15_25 -; SSE4-NEXT: .LBB15_26: # %else24 +; SSE4-NEXT: jne .LBB15_47 +; SSE4-NEXT: .LBB15_13: # %else24 ; SSE4-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE4-NEXT: jne .LBB15_27 -; SSE4-NEXT: .LBB15_28: # %else26 +; SSE4-NEXT: jne .LBB15_48 +; SSE4-NEXT: .LBB15_14: # %else26 ; SSE4-NEXT: testl $16384, %eax # imm = 0x4000 -; SSE4-NEXT: je .LBB15_30 -; SSE4-NEXT: .LBB15_29: # %cond.store27 +; SSE4-NEXT: je .LBB15_16 +; SSE4-NEXT: .LBB15_15: # %cond.store27 ; SSE4-NEXT: pextrb $14, %xmm0, 14(%rdi) -; SSE4-NEXT: .LBB15_30: # %else28 +; SSE4-NEXT: .LBB15_16: # %else28 ; SSE4-NEXT: pand %xmm6, %xmm3 ; SSE4-NEXT: pand %xmm6, %xmm2 ; SSE4-NEXT: testw %ax, %ax -; SSE4-NEXT: jns .LBB15_32 -; SSE4-NEXT: # %bb.31: # %cond.store29 +; SSE4-NEXT: jns .LBB15_18 +; SSE4-NEXT: # %bb.17: # %cond.store29 ; SSE4-NEXT: pextrb $15, %xmm0, 15(%rdi) -; SSE4-NEXT: .LBB15_32: # %else30 +; SSE4-NEXT: .LBB15_18: # %else30 ; SSE4-NEXT: packuswb %xmm3, %xmm2 ; SSE4-NEXT: testl $65536, %eax # imm = 0x10000 -; SSE4-NEXT: jne .LBB15_33 -; SSE4-NEXT: # %bb.34: # %else32 +; SSE4-NEXT: jne .LBB15_49 +; SSE4-NEXT: # %bb.19: # %else32 ; SSE4-NEXT: testl $131072, %eax # imm = 0x20000 -; SSE4-NEXT: jne .LBB15_35 -; SSE4-NEXT: .LBB15_36: # %else34 +; SSE4-NEXT: jne .LBB15_50 +; SSE4-NEXT: .LBB15_20: # %else34 ; SSE4-NEXT: testl $262144, %eax # imm = 0x40000 -; SSE4-NEXT: jne .LBB15_37 -; SSE4-NEXT: .LBB15_38: # %else36 +; SSE4-NEXT: jne .LBB15_51 +; SSE4-NEXT: .LBB15_21: # %else36 ; SSE4-NEXT: testl $524288, %eax # imm = 0x80000 -; SSE4-NEXT: jne .LBB15_39 -; SSE4-NEXT: .LBB15_40: # %else38 +; SSE4-NEXT: jne .LBB15_52 +; SSE4-NEXT: .LBB15_22: # %else38 ; SSE4-NEXT: testl $1048576, %eax # imm = 0x100000 -; SSE4-NEXT: jne .LBB15_41 -; SSE4-NEXT: .LBB15_42: # %else40 +; SSE4-NEXT: jne .LBB15_53 +; SSE4-NEXT: .LBB15_23: # %else40 ; SSE4-NEXT: testl $2097152, %eax # imm = 0x200000 -; SSE4-NEXT: jne .LBB15_43 -; SSE4-NEXT: .LBB15_44: # %else42 +; SSE4-NEXT: jne .LBB15_54 +; SSE4-NEXT: .LBB15_24: # %else42 ; SSE4-NEXT: testl $4194304, %eax # imm = 0x400000 -; SSE4-NEXT: jne .LBB15_45 -; SSE4-NEXT: .LBB15_46: # %else44 +; SSE4-NEXT: jne .LBB15_55 +; SSE4-NEXT: .LBB15_25: # %else44 ; SSE4-NEXT: testl $8388608, %eax # imm = 0x800000 -; SSE4-NEXT: jne .LBB15_47 -; SSE4-NEXT: .LBB15_48: # %else46 +; SSE4-NEXT: jne .LBB15_56 +; SSE4-NEXT: .LBB15_26: # %else46 ; SSE4-NEXT: testl $16777216, %eax # imm = 0x1000000 -; SSE4-NEXT: jne .LBB15_49 -; SSE4-NEXT: .LBB15_50: # %else48 +; SSE4-NEXT: jne .LBB15_57 +; SSE4-NEXT: .LBB15_27: # %else48 ; SSE4-NEXT: testl $33554432, %eax # imm = 0x2000000 -; SSE4-NEXT: jne .LBB15_51 -; SSE4-NEXT: .LBB15_52: # %else50 +; SSE4-NEXT: jne .LBB15_58 +; SSE4-NEXT: .LBB15_28: # %else50 ; SSE4-NEXT: testl $67108864, %eax # imm = 0x4000000 -; SSE4-NEXT: jne .LBB15_53 -; SSE4-NEXT: .LBB15_54: # %else52 +; SSE4-NEXT: jne .LBB15_59 +; SSE4-NEXT: .LBB15_29: # %else52 ; SSE4-NEXT: testl $134217728, %eax # imm = 0x8000000 -; SSE4-NEXT: jne .LBB15_55 -; SSE4-NEXT: .LBB15_56: # %else54 +; SSE4-NEXT: jne .LBB15_60 +; SSE4-NEXT: .LBB15_30: # %else54 ; SSE4-NEXT: testl $268435456, %eax # imm = 0x10000000 -; SSE4-NEXT: jne .LBB15_57 -; SSE4-NEXT: .LBB15_58: # %else56 +; SSE4-NEXT: jne .LBB15_61 +; SSE4-NEXT: .LBB15_31: # %else56 ; SSE4-NEXT: testl $536870912, %eax # imm = 0x20000000 -; SSE4-NEXT: jne .LBB15_59 -; SSE4-NEXT: .LBB15_60: # %else58 +; SSE4-NEXT: jne .LBB15_62 +; SSE4-NEXT: .LBB15_32: # %else58 ; SSE4-NEXT: testl $1073741824, %eax # imm = 0x40000000 -; SSE4-NEXT: jne .LBB15_61 -; SSE4-NEXT: .LBB15_62: # %else60 -; SSE4-NEXT: testl $-2147483648, %eax # imm = 0x80000000 ; SSE4-NEXT: jne .LBB15_63 -; SSE4-NEXT: .LBB15_64: # %else62 +; SSE4-NEXT: .LBB15_33: # %else60 +; SSE4-NEXT: testl $-2147483648, %eax # imm = 0x80000000 +; SSE4-NEXT: jne .LBB15_64 +; SSE4-NEXT: .LBB15_34: # %else62 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB15_1: # %cond.store +; SSE4-NEXT: .LBB15_35: # %cond.store ; SSE4-NEXT: pextrb $0, %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB15_4 -; SSE4-NEXT: .LBB15_3: # %cond.store1 +; SSE4-NEXT: je .LBB15_2 +; SSE4-NEXT: .LBB15_36: # %cond.store1 ; SSE4-NEXT: pextrb $1, %xmm0, 1(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB15_6 -; SSE4-NEXT: .LBB15_5: # %cond.store3 +; SSE4-NEXT: je .LBB15_3 +; SSE4-NEXT: .LBB15_37: # %cond.store3 ; SSE4-NEXT: pextrb $2, %xmm0, 2(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB15_8 -; SSE4-NEXT: .LBB15_7: # %cond.store5 +; SSE4-NEXT: je .LBB15_4 +; SSE4-NEXT: .LBB15_38: # %cond.store5 ; SSE4-NEXT: pextrb $3, %xmm0, 3(%rdi) ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: je .LBB15_10 -; SSE4-NEXT: .LBB15_9: # %cond.store7 +; SSE4-NEXT: je .LBB15_5 +; SSE4-NEXT: .LBB15_39: # %cond.store7 ; SSE4-NEXT: pextrb $4, %xmm0, 4(%rdi) ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: je .LBB15_12 -; SSE4-NEXT: .LBB15_11: # %cond.store9 +; SSE4-NEXT: je .LBB15_6 +; SSE4-NEXT: .LBB15_40: # %cond.store9 ; SSE4-NEXT: pextrb $5, %xmm0, 5(%rdi) ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: je .LBB15_14 -; SSE4-NEXT: .LBB15_13: # %cond.store11 +; SSE4-NEXT: je .LBB15_7 +; SSE4-NEXT: .LBB15_41: # %cond.store11 ; SSE4-NEXT: pextrb $6, %xmm0, 6(%rdi) ; SSE4-NEXT: testb %al, %al -; SSE4-NEXT: jns .LBB15_16 -; SSE4-NEXT: .LBB15_15: # %cond.store13 +; SSE4-NEXT: jns .LBB15_8 +; SSE4-NEXT: .LBB15_42: # %cond.store13 ; SSE4-NEXT: pextrb $7, %xmm0, 7(%rdi) ; SSE4-NEXT: testl $256, %eax # imm = 0x100 -; SSE4-NEXT: je .LBB15_18 -; SSE4-NEXT: .LBB15_17: # %cond.store15 +; SSE4-NEXT: je .LBB15_9 +; SSE4-NEXT: .LBB15_43: # %cond.store15 ; SSE4-NEXT: pextrb $8, %xmm0, 8(%rdi) ; SSE4-NEXT: testl $512, %eax # imm = 0x200 -; SSE4-NEXT: je .LBB15_20 -; SSE4-NEXT: .LBB15_19: # %cond.store17 +; SSE4-NEXT: je .LBB15_10 +; SSE4-NEXT: .LBB15_44: # %cond.store17 ; SSE4-NEXT: pextrb $9, %xmm0, 9(%rdi) ; SSE4-NEXT: testl $1024, %eax # imm = 0x400 -; SSE4-NEXT: je .LBB15_22 -; SSE4-NEXT: .LBB15_21: # %cond.store19 +; SSE4-NEXT: je .LBB15_11 +; SSE4-NEXT: .LBB15_45: # %cond.store19 ; SSE4-NEXT: pextrb $10, %xmm0, 10(%rdi) ; SSE4-NEXT: testl $2048, %eax # imm = 0x800 -; SSE4-NEXT: je .LBB15_24 -; SSE4-NEXT: .LBB15_23: # %cond.store21 +; SSE4-NEXT: je .LBB15_12 +; SSE4-NEXT: .LBB15_46: # %cond.store21 ; SSE4-NEXT: pextrb $11, %xmm0, 11(%rdi) ; SSE4-NEXT: testl $4096, %eax # imm = 0x1000 -; SSE4-NEXT: je .LBB15_26 -; SSE4-NEXT: .LBB15_25: # %cond.store23 +; SSE4-NEXT: je .LBB15_13 +; SSE4-NEXT: .LBB15_47: # %cond.store23 ; SSE4-NEXT: pextrb $12, %xmm0, 12(%rdi) ; SSE4-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE4-NEXT: je .LBB15_28 -; SSE4-NEXT: .LBB15_27: # %cond.store25 +; SSE4-NEXT: je .LBB15_14 +; SSE4-NEXT: .LBB15_48: # %cond.store25 ; SSE4-NEXT: pextrb $13, %xmm0, 13(%rdi) ; SSE4-NEXT: testl $16384, %eax # imm = 0x4000 -; SSE4-NEXT: jne .LBB15_29 -; SSE4-NEXT: jmp .LBB15_30 -; SSE4-NEXT: .LBB15_33: # %cond.store31 +; SSE4-NEXT: jne .LBB15_15 +; SSE4-NEXT: jmp .LBB15_16 +; SSE4-NEXT: .LBB15_49: # %cond.store31 ; SSE4-NEXT: pextrb $0, %xmm2, 16(%rdi) ; SSE4-NEXT: testl $131072, %eax # imm = 0x20000 -; SSE4-NEXT: je .LBB15_36 -; SSE4-NEXT: .LBB15_35: # %cond.store33 +; SSE4-NEXT: je .LBB15_20 +; SSE4-NEXT: .LBB15_50: # %cond.store33 ; SSE4-NEXT: pextrb $1, %xmm2, 17(%rdi) ; SSE4-NEXT: testl $262144, %eax # imm = 0x40000 -; SSE4-NEXT: je .LBB15_38 -; SSE4-NEXT: .LBB15_37: # %cond.store35 +; SSE4-NEXT: je .LBB15_21 +; SSE4-NEXT: .LBB15_51: # %cond.store35 ; SSE4-NEXT: pextrb $2, %xmm2, 18(%rdi) ; SSE4-NEXT: testl $524288, %eax # imm = 0x80000 -; SSE4-NEXT: je .LBB15_40 -; SSE4-NEXT: .LBB15_39: # %cond.store37 +; SSE4-NEXT: je .LBB15_22 +; SSE4-NEXT: .LBB15_52: # %cond.store37 ; SSE4-NEXT: pextrb $3, %xmm2, 19(%rdi) ; SSE4-NEXT: testl $1048576, %eax # imm = 0x100000 -; SSE4-NEXT: je .LBB15_42 -; SSE4-NEXT: .LBB15_41: # %cond.store39 +; SSE4-NEXT: je .LBB15_23 +; SSE4-NEXT: .LBB15_53: # %cond.store39 ; SSE4-NEXT: pextrb $4, %xmm2, 20(%rdi) ; SSE4-NEXT: testl $2097152, %eax # imm = 0x200000 -; SSE4-NEXT: je .LBB15_44 -; SSE4-NEXT: .LBB15_43: # %cond.store41 +; SSE4-NEXT: je .LBB15_24 +; SSE4-NEXT: .LBB15_54: # %cond.store41 ; SSE4-NEXT: pextrb $5, %xmm2, 21(%rdi) ; SSE4-NEXT: testl $4194304, %eax # imm = 0x400000 -; SSE4-NEXT: je .LBB15_46 -; SSE4-NEXT: .LBB15_45: # %cond.store43 +; SSE4-NEXT: je .LBB15_25 +; SSE4-NEXT: .LBB15_55: # %cond.store43 ; SSE4-NEXT: pextrb $6, %xmm2, 22(%rdi) ; SSE4-NEXT: testl $8388608, %eax # imm = 0x800000 -; SSE4-NEXT: je .LBB15_48 -; SSE4-NEXT: .LBB15_47: # %cond.store45 +; SSE4-NEXT: je .LBB15_26 +; SSE4-NEXT: .LBB15_56: # %cond.store45 ; SSE4-NEXT: pextrb $7, %xmm2, 23(%rdi) ; SSE4-NEXT: testl $16777216, %eax # imm = 0x1000000 -; SSE4-NEXT: je .LBB15_50 -; SSE4-NEXT: .LBB15_49: # %cond.store47 +; SSE4-NEXT: je .LBB15_27 +; SSE4-NEXT: .LBB15_57: # %cond.store47 ; SSE4-NEXT: pextrb $8, %xmm2, 24(%rdi) ; SSE4-NEXT: testl $33554432, %eax # imm = 0x2000000 -; SSE4-NEXT: je .LBB15_52 -; SSE4-NEXT: .LBB15_51: # %cond.store49 +; SSE4-NEXT: je .LBB15_28 +; SSE4-NEXT: .LBB15_58: # %cond.store49 ; SSE4-NEXT: pextrb $9, %xmm2, 25(%rdi) ; SSE4-NEXT: testl $67108864, %eax # imm = 0x4000000 -; SSE4-NEXT: je .LBB15_54 -; SSE4-NEXT: .LBB15_53: # %cond.store51 +; SSE4-NEXT: je .LBB15_29 +; SSE4-NEXT: .LBB15_59: # %cond.store51 ; SSE4-NEXT: pextrb $10, %xmm2, 26(%rdi) ; SSE4-NEXT: testl $134217728, %eax # imm = 0x8000000 -; SSE4-NEXT: je .LBB15_56 -; SSE4-NEXT: .LBB15_55: # %cond.store53 +; SSE4-NEXT: je .LBB15_30 +; SSE4-NEXT: .LBB15_60: # %cond.store53 ; SSE4-NEXT: pextrb $11, %xmm2, 27(%rdi) ; SSE4-NEXT: testl $268435456, %eax # imm = 0x10000000 -; SSE4-NEXT: je .LBB15_58 -; SSE4-NEXT: .LBB15_57: # %cond.store55 +; SSE4-NEXT: je .LBB15_31 +; SSE4-NEXT: .LBB15_61: # %cond.store55 ; SSE4-NEXT: pextrb $12, %xmm2, 28(%rdi) ; SSE4-NEXT: testl $536870912, %eax # imm = 0x20000000 -; SSE4-NEXT: je .LBB15_60 -; SSE4-NEXT: .LBB15_59: # %cond.store57 +; SSE4-NEXT: je .LBB15_32 +; SSE4-NEXT: .LBB15_62: # %cond.store57 ; SSE4-NEXT: pextrb $13, %xmm2, 29(%rdi) ; SSE4-NEXT: testl $1073741824, %eax # imm = 0x40000000 -; SSE4-NEXT: je .LBB15_62 -; SSE4-NEXT: .LBB15_61: # %cond.store59 +; SSE4-NEXT: je .LBB15_33 +; SSE4-NEXT: .LBB15_63: # %cond.store59 ; SSE4-NEXT: pextrb $14, %xmm2, 30(%rdi) ; SSE4-NEXT: testl $-2147483648, %eax # imm = 0x80000000 -; SSE4-NEXT: je .LBB15_64 -; SSE4-NEXT: .LBB15_63: # %cond.store61 +; SSE4-NEXT: je .LBB15_34 +; SSE4-NEXT: .LBB15_64: # %cond.store61 ; SSE4-NEXT: pextrb $15, %xmm2, 31(%rdi) ; SSE4-NEXT: retq ; @@ -5492,228 +5492,228 @@ define void @truncstore_v32i16_v32i8(<32 x i16> %x, ptr %p, <32 x i8> %mask) { ; AVX1-NEXT: shll $16, %eax ; AVX1-NEXT: orl %ecx, %eax ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne .LBB15_1 -; AVX1-NEXT: # %bb.2: # %else +; AVX1-NEXT: jne .LBB15_34 +; AVX1-NEXT: # %bb.1: # %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne .LBB15_3 -; AVX1-NEXT: .LBB15_4: # %else2 +; AVX1-NEXT: jne .LBB15_35 +; AVX1-NEXT: .LBB15_2: # %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne .LBB15_5 -; AVX1-NEXT: .LBB15_6: # %else4 +; AVX1-NEXT: jne .LBB15_36 +; AVX1-NEXT: .LBB15_3: # %else4 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne .LBB15_7 -; AVX1-NEXT: .LBB15_8: # %else6 +; AVX1-NEXT: jne .LBB15_37 +; AVX1-NEXT: .LBB15_4: # %else6 ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: jne .LBB15_9 -; AVX1-NEXT: .LBB15_10: # %else8 +; AVX1-NEXT: jne .LBB15_38 +; AVX1-NEXT: .LBB15_5: # %else8 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: jne .LBB15_11 -; AVX1-NEXT: .LBB15_12: # %else10 +; AVX1-NEXT: jne .LBB15_39 +; AVX1-NEXT: .LBB15_6: # %else10 ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: jne .LBB15_13 -; AVX1-NEXT: .LBB15_14: # %else12 +; AVX1-NEXT: jne .LBB15_40 +; AVX1-NEXT: .LBB15_7: # %else12 ; AVX1-NEXT: testb %al, %al -; AVX1-NEXT: js .LBB15_15 -; AVX1-NEXT: .LBB15_16: # %else14 +; AVX1-NEXT: js .LBB15_41 +; AVX1-NEXT: .LBB15_8: # %else14 ; AVX1-NEXT: testl $256, %eax # imm = 0x100 -; AVX1-NEXT: jne .LBB15_17 -; AVX1-NEXT: .LBB15_18: # %else16 +; AVX1-NEXT: jne .LBB15_42 +; AVX1-NEXT: .LBB15_9: # %else16 ; AVX1-NEXT: testl $512, %eax # imm = 0x200 -; AVX1-NEXT: jne .LBB15_19 -; AVX1-NEXT: .LBB15_20: # %else18 +; AVX1-NEXT: jne .LBB15_43 +; AVX1-NEXT: .LBB15_10: # %else18 ; AVX1-NEXT: testl $1024, %eax # imm = 0x400 -; AVX1-NEXT: jne .LBB15_21 -; AVX1-NEXT: .LBB15_22: # %else20 +; AVX1-NEXT: jne .LBB15_44 +; AVX1-NEXT: .LBB15_11: # %else20 ; AVX1-NEXT: testl $2048, %eax # imm = 0x800 -; AVX1-NEXT: jne .LBB15_23 -; AVX1-NEXT: .LBB15_24: # %else22 +; AVX1-NEXT: jne .LBB15_45 +; AVX1-NEXT: .LBB15_12: # %else22 ; AVX1-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX1-NEXT: jne .LBB15_25 -; AVX1-NEXT: .LBB15_26: # %else24 +; AVX1-NEXT: jne .LBB15_46 +; AVX1-NEXT: .LBB15_13: # %else24 ; AVX1-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX1-NEXT: jne .LBB15_27 -; AVX1-NEXT: .LBB15_28: # %else26 +; AVX1-NEXT: jne .LBB15_47 +; AVX1-NEXT: .LBB15_14: # %else26 ; AVX1-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX1-NEXT: jne .LBB15_29 -; AVX1-NEXT: .LBB15_30: # %else28 +; AVX1-NEXT: jne .LBB15_48 +; AVX1-NEXT: .LBB15_15: # %else28 ; AVX1-NEXT: testw %ax, %ax -; AVX1-NEXT: jns .LBB15_32 -; AVX1-NEXT: .LBB15_31: # %cond.store29 +; AVX1-NEXT: jns .LBB15_17 +; AVX1-NEXT: .LBB15_16: # %cond.store29 ; AVX1-NEXT: vpextrb $15, %xmm0, 15(%rdi) -; AVX1-NEXT: .LBB15_32: # %else30 +; AVX1-NEXT: .LBB15_17: # %else30 ; AVX1-NEXT: testl $65536, %eax # imm = 0x10000 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 -; AVX1-NEXT: jne .LBB15_33 -; AVX1-NEXT: # %bb.34: # %else32 +; AVX1-NEXT: jne .LBB15_49 +; AVX1-NEXT: # %bb.18: # %else32 ; AVX1-NEXT: testl $131072, %eax # imm = 0x20000 -; AVX1-NEXT: jne .LBB15_35 -; AVX1-NEXT: .LBB15_36: # %else34 +; AVX1-NEXT: jne .LBB15_50 +; AVX1-NEXT: .LBB15_19: # %else34 ; AVX1-NEXT: testl $262144, %eax # imm = 0x40000 -; AVX1-NEXT: jne .LBB15_37 -; AVX1-NEXT: .LBB15_38: # %else36 +; AVX1-NEXT: jne .LBB15_51 +; AVX1-NEXT: .LBB15_20: # %else36 ; AVX1-NEXT: testl $524288, %eax # imm = 0x80000 -; AVX1-NEXT: jne .LBB15_39 -; AVX1-NEXT: .LBB15_40: # %else38 +; AVX1-NEXT: jne .LBB15_52 +; AVX1-NEXT: .LBB15_21: # %else38 ; AVX1-NEXT: testl $1048576, %eax # imm = 0x100000 -; AVX1-NEXT: jne .LBB15_41 -; AVX1-NEXT: .LBB15_42: # %else40 +; AVX1-NEXT: jne .LBB15_53 +; AVX1-NEXT: .LBB15_22: # %else40 ; AVX1-NEXT: testl $2097152, %eax # imm = 0x200000 -; AVX1-NEXT: jne .LBB15_43 -; AVX1-NEXT: .LBB15_44: # %else42 +; AVX1-NEXT: jne .LBB15_54 +; AVX1-NEXT: .LBB15_23: # %else42 ; AVX1-NEXT: testl $4194304, %eax # imm = 0x400000 -; AVX1-NEXT: jne .LBB15_45 -; AVX1-NEXT: .LBB15_46: # %else44 +; AVX1-NEXT: jne .LBB15_55 +; AVX1-NEXT: .LBB15_24: # %else44 ; AVX1-NEXT: testl $8388608, %eax # imm = 0x800000 -; AVX1-NEXT: jne .LBB15_47 -; AVX1-NEXT: .LBB15_48: # %else46 +; AVX1-NEXT: jne .LBB15_56 +; AVX1-NEXT: .LBB15_25: # %else46 ; AVX1-NEXT: testl $16777216, %eax # imm = 0x1000000 -; AVX1-NEXT: jne .LBB15_49 -; AVX1-NEXT: .LBB15_50: # %else48 +; AVX1-NEXT: jne .LBB15_57 +; AVX1-NEXT: .LBB15_26: # %else48 ; AVX1-NEXT: testl $33554432, %eax # imm = 0x2000000 -; AVX1-NEXT: jne .LBB15_51 -; AVX1-NEXT: .LBB15_52: # %else50 +; AVX1-NEXT: jne .LBB15_58 +; AVX1-NEXT: .LBB15_27: # %else50 ; AVX1-NEXT: testl $67108864, %eax # imm = 0x4000000 -; AVX1-NEXT: jne .LBB15_53 -; AVX1-NEXT: .LBB15_54: # %else52 +; AVX1-NEXT: jne .LBB15_59 +; AVX1-NEXT: .LBB15_28: # %else52 ; AVX1-NEXT: testl $134217728, %eax # imm = 0x8000000 -; AVX1-NEXT: jne .LBB15_55 -; AVX1-NEXT: .LBB15_56: # %else54 +; AVX1-NEXT: jne .LBB15_60 +; AVX1-NEXT: .LBB15_29: # %else54 ; AVX1-NEXT: testl $268435456, %eax # imm = 0x10000000 -; AVX1-NEXT: jne .LBB15_57 -; AVX1-NEXT: .LBB15_58: # %else56 +; AVX1-NEXT: jne .LBB15_61 +; AVX1-NEXT: .LBB15_30: # %else56 ; AVX1-NEXT: testl $536870912, %eax # imm = 0x20000000 -; AVX1-NEXT: jne .LBB15_59 -; AVX1-NEXT: .LBB15_60: # %else58 +; AVX1-NEXT: jne .LBB15_62 +; AVX1-NEXT: .LBB15_31: # %else58 ; AVX1-NEXT: testl $1073741824, %eax # imm = 0x40000000 -; AVX1-NEXT: jne .LBB15_61 -; AVX1-NEXT: .LBB15_62: # %else60 -; AVX1-NEXT: testl $-2147483648, %eax # imm = 0x80000000 ; AVX1-NEXT: jne .LBB15_63 -; AVX1-NEXT: .LBB15_64: # %else62 +; AVX1-NEXT: .LBB15_32: # %else60 +; AVX1-NEXT: testl $-2147483648, %eax # imm = 0x80000000 +; AVX1-NEXT: jne .LBB15_64 +; AVX1-NEXT: .LBB15_33: # %else62 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB15_1: # %cond.store +; AVX1-NEXT: .LBB15_34: # %cond.store ; AVX1-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je .LBB15_4 -; AVX1-NEXT: .LBB15_3: # %cond.store1 +; AVX1-NEXT: je .LBB15_2 +; AVX1-NEXT: .LBB15_35: # %cond.store1 ; AVX1-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je .LBB15_6 -; AVX1-NEXT: .LBB15_5: # %cond.store3 +; AVX1-NEXT: je .LBB15_3 +; AVX1-NEXT: .LBB15_36: # %cond.store3 ; AVX1-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB15_8 -; AVX1-NEXT: .LBB15_7: # %cond.store5 +; AVX1-NEXT: je .LBB15_4 +; AVX1-NEXT: .LBB15_37: # %cond.store5 ; AVX1-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: je .LBB15_10 -; AVX1-NEXT: .LBB15_9: # %cond.store7 +; AVX1-NEXT: je .LBB15_5 +; AVX1-NEXT: .LBB15_38: # %cond.store7 ; AVX1-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je .LBB15_12 -; AVX1-NEXT: .LBB15_11: # %cond.store9 +; AVX1-NEXT: je .LBB15_6 +; AVX1-NEXT: .LBB15_39: # %cond.store9 ; AVX1-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: je .LBB15_14 -; AVX1-NEXT: .LBB15_13: # %cond.store11 +; AVX1-NEXT: je .LBB15_7 +; AVX1-NEXT: .LBB15_40: # %cond.store11 ; AVX1-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX1-NEXT: testb %al, %al -; AVX1-NEXT: jns .LBB15_16 -; AVX1-NEXT: .LBB15_15: # %cond.store13 +; AVX1-NEXT: jns .LBB15_8 +; AVX1-NEXT: .LBB15_41: # %cond.store13 ; AVX1-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX1-NEXT: testl $256, %eax # imm = 0x100 -; AVX1-NEXT: je .LBB15_18 -; AVX1-NEXT: .LBB15_17: # %cond.store15 +; AVX1-NEXT: je .LBB15_9 +; AVX1-NEXT: .LBB15_42: # %cond.store15 ; AVX1-NEXT: vpextrb $8, %xmm0, 8(%rdi) ; AVX1-NEXT: testl $512, %eax # imm = 0x200 -; AVX1-NEXT: je .LBB15_20 -; AVX1-NEXT: .LBB15_19: # %cond.store17 +; AVX1-NEXT: je .LBB15_10 +; AVX1-NEXT: .LBB15_43: # %cond.store17 ; AVX1-NEXT: vpextrb $9, %xmm0, 9(%rdi) ; AVX1-NEXT: testl $1024, %eax # imm = 0x400 -; AVX1-NEXT: je .LBB15_22 -; AVX1-NEXT: .LBB15_21: # %cond.store19 +; AVX1-NEXT: je .LBB15_11 +; AVX1-NEXT: .LBB15_44: # %cond.store19 ; AVX1-NEXT: vpextrb $10, %xmm0, 10(%rdi) ; AVX1-NEXT: testl $2048, %eax # imm = 0x800 -; AVX1-NEXT: je .LBB15_24 -; AVX1-NEXT: .LBB15_23: # %cond.store21 +; AVX1-NEXT: je .LBB15_12 +; AVX1-NEXT: .LBB15_45: # %cond.store21 ; AVX1-NEXT: vpextrb $11, %xmm0, 11(%rdi) ; AVX1-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX1-NEXT: je .LBB15_26 -; AVX1-NEXT: .LBB15_25: # %cond.store23 +; AVX1-NEXT: je .LBB15_13 +; AVX1-NEXT: .LBB15_46: # %cond.store23 ; AVX1-NEXT: vpextrb $12, %xmm0, 12(%rdi) ; AVX1-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX1-NEXT: je .LBB15_28 -; AVX1-NEXT: .LBB15_27: # %cond.store25 +; AVX1-NEXT: je .LBB15_14 +; AVX1-NEXT: .LBB15_47: # %cond.store25 ; AVX1-NEXT: vpextrb $13, %xmm0, 13(%rdi) ; AVX1-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX1-NEXT: je .LBB15_30 -; AVX1-NEXT: .LBB15_29: # %cond.store27 +; AVX1-NEXT: je .LBB15_15 +; AVX1-NEXT: .LBB15_48: # %cond.store27 ; AVX1-NEXT: vpextrb $14, %xmm0, 14(%rdi) ; AVX1-NEXT: testw %ax, %ax -; AVX1-NEXT: js .LBB15_31 -; AVX1-NEXT: jmp .LBB15_32 -; AVX1-NEXT: .LBB15_33: # %cond.store31 +; AVX1-NEXT: js .LBB15_16 +; AVX1-NEXT: jmp .LBB15_17 +; AVX1-NEXT: .LBB15_49: # %cond.store31 ; AVX1-NEXT: vpextrb $0, %xmm0, 16(%rdi) ; AVX1-NEXT: testl $131072, %eax # imm = 0x20000 -; AVX1-NEXT: je .LBB15_36 -; AVX1-NEXT: .LBB15_35: # %cond.store33 +; AVX1-NEXT: je .LBB15_19 +; AVX1-NEXT: .LBB15_50: # %cond.store33 ; AVX1-NEXT: vpextrb $1, %xmm0, 17(%rdi) ; AVX1-NEXT: testl $262144, %eax # imm = 0x40000 -; AVX1-NEXT: je .LBB15_38 -; AVX1-NEXT: .LBB15_37: # %cond.store35 +; AVX1-NEXT: je .LBB15_20 +; AVX1-NEXT: .LBB15_51: # %cond.store35 ; AVX1-NEXT: vpextrb $2, %xmm0, 18(%rdi) ; AVX1-NEXT: testl $524288, %eax # imm = 0x80000 -; AVX1-NEXT: je .LBB15_40 -; AVX1-NEXT: .LBB15_39: # %cond.store37 +; AVX1-NEXT: je .LBB15_21 +; AVX1-NEXT: .LBB15_52: # %cond.store37 ; AVX1-NEXT: vpextrb $3, %xmm0, 19(%rdi) ; AVX1-NEXT: testl $1048576, %eax # imm = 0x100000 -; AVX1-NEXT: je .LBB15_42 -; AVX1-NEXT: .LBB15_41: # %cond.store39 +; AVX1-NEXT: je .LBB15_22 +; AVX1-NEXT: .LBB15_53: # %cond.store39 ; AVX1-NEXT: vpextrb $4, %xmm0, 20(%rdi) ; AVX1-NEXT: testl $2097152, %eax # imm = 0x200000 -; AVX1-NEXT: je .LBB15_44 -; AVX1-NEXT: .LBB15_43: # %cond.store41 +; AVX1-NEXT: je .LBB15_23 +; AVX1-NEXT: .LBB15_54: # %cond.store41 ; AVX1-NEXT: vpextrb $5, %xmm0, 21(%rdi) ; AVX1-NEXT: testl $4194304, %eax # imm = 0x400000 -; AVX1-NEXT: je .LBB15_46 -; AVX1-NEXT: .LBB15_45: # %cond.store43 +; AVX1-NEXT: je .LBB15_24 +; AVX1-NEXT: .LBB15_55: # %cond.store43 ; AVX1-NEXT: vpextrb $6, %xmm0, 22(%rdi) ; AVX1-NEXT: testl $8388608, %eax # imm = 0x800000 -; AVX1-NEXT: je .LBB15_48 -; AVX1-NEXT: .LBB15_47: # %cond.store45 +; AVX1-NEXT: je .LBB15_25 +; AVX1-NEXT: .LBB15_56: # %cond.store45 ; AVX1-NEXT: vpextrb $7, %xmm0, 23(%rdi) ; AVX1-NEXT: testl $16777216, %eax # imm = 0x1000000 -; AVX1-NEXT: je .LBB15_50 -; AVX1-NEXT: .LBB15_49: # %cond.store47 +; AVX1-NEXT: je .LBB15_26 +; AVX1-NEXT: .LBB15_57: # %cond.store47 ; AVX1-NEXT: vpextrb $8, %xmm0, 24(%rdi) ; AVX1-NEXT: testl $33554432, %eax # imm = 0x2000000 -; AVX1-NEXT: je .LBB15_52 -; AVX1-NEXT: .LBB15_51: # %cond.store49 +; AVX1-NEXT: je .LBB15_27 +; AVX1-NEXT: .LBB15_58: # %cond.store49 ; AVX1-NEXT: vpextrb $9, %xmm0, 25(%rdi) ; AVX1-NEXT: testl $67108864, %eax # imm = 0x4000000 -; AVX1-NEXT: je .LBB15_54 -; AVX1-NEXT: .LBB15_53: # %cond.store51 +; AVX1-NEXT: je .LBB15_28 +; AVX1-NEXT: .LBB15_59: # %cond.store51 ; AVX1-NEXT: vpextrb $10, %xmm0, 26(%rdi) ; AVX1-NEXT: testl $134217728, %eax # imm = 0x8000000 -; AVX1-NEXT: je .LBB15_56 -; AVX1-NEXT: .LBB15_55: # %cond.store53 +; AVX1-NEXT: je .LBB15_29 +; AVX1-NEXT: .LBB15_60: # %cond.store53 ; AVX1-NEXT: vpextrb $11, %xmm0, 27(%rdi) ; AVX1-NEXT: testl $268435456, %eax # imm = 0x10000000 -; AVX1-NEXT: je .LBB15_58 -; AVX1-NEXT: .LBB15_57: # %cond.store55 +; AVX1-NEXT: je .LBB15_30 +; AVX1-NEXT: .LBB15_61: # %cond.store55 ; AVX1-NEXT: vpextrb $12, %xmm0, 28(%rdi) ; AVX1-NEXT: testl $536870912, %eax # imm = 0x20000000 -; AVX1-NEXT: je .LBB15_60 -; AVX1-NEXT: .LBB15_59: # %cond.store57 +; AVX1-NEXT: je .LBB15_31 +; AVX1-NEXT: .LBB15_62: # %cond.store57 ; AVX1-NEXT: vpextrb $13, %xmm0, 29(%rdi) ; AVX1-NEXT: testl $1073741824, %eax # imm = 0x40000000 -; AVX1-NEXT: je .LBB15_62 -; AVX1-NEXT: .LBB15_61: # %cond.store59 +; AVX1-NEXT: je .LBB15_32 +; AVX1-NEXT: .LBB15_63: # %cond.store59 ; AVX1-NEXT: vpextrb $14, %xmm0, 30(%rdi) ; AVX1-NEXT: testl $-2147483648, %eax # imm = 0x80000000 -; AVX1-NEXT: je .LBB15_64 -; AVX1-NEXT: .LBB15_63: # %cond.store61 +; AVX1-NEXT: je .LBB15_33 +; AVX1-NEXT: .LBB15_64: # %cond.store61 ; AVX1-NEXT: vpextrb $15, %xmm0, 31(%rdi) ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq @@ -5730,228 +5730,228 @@ define void @truncstore_v32i16_v32i8(<32 x i16> %x, ptr %p, <32 x i8> %mask) { ; AVX2-NEXT: vpmovmskb %ymm1, %eax ; AVX2-NEXT: notl %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne .LBB15_1 -; AVX2-NEXT: # %bb.2: # %else +; AVX2-NEXT: jne .LBB15_34 +; AVX2-NEXT: # %bb.1: # %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne .LBB15_3 -; AVX2-NEXT: .LBB15_4: # %else2 +; AVX2-NEXT: jne .LBB15_35 +; AVX2-NEXT: .LBB15_2: # %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne .LBB15_5 -; AVX2-NEXT: .LBB15_6: # %else4 +; AVX2-NEXT: jne .LBB15_36 +; AVX2-NEXT: .LBB15_3: # %else4 ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: jne .LBB15_7 -; AVX2-NEXT: .LBB15_8: # %else6 +; AVX2-NEXT: jne .LBB15_37 +; AVX2-NEXT: .LBB15_4: # %else6 ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: jne .LBB15_9 -; AVX2-NEXT: .LBB15_10: # %else8 +; AVX2-NEXT: jne .LBB15_38 +; AVX2-NEXT: .LBB15_5: # %else8 ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: jne .LBB15_11 -; AVX2-NEXT: .LBB15_12: # %else10 +; AVX2-NEXT: jne .LBB15_39 +; AVX2-NEXT: .LBB15_6: # %else10 ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: jne .LBB15_13 -; AVX2-NEXT: .LBB15_14: # %else12 +; AVX2-NEXT: jne .LBB15_40 +; AVX2-NEXT: .LBB15_7: # %else12 ; AVX2-NEXT: testb %al, %al -; AVX2-NEXT: js .LBB15_15 -; AVX2-NEXT: .LBB15_16: # %else14 +; AVX2-NEXT: js .LBB15_41 +; AVX2-NEXT: .LBB15_8: # %else14 ; AVX2-NEXT: testl $256, %eax # imm = 0x100 -; AVX2-NEXT: jne .LBB15_17 -; AVX2-NEXT: .LBB15_18: # %else16 +; AVX2-NEXT: jne .LBB15_42 +; AVX2-NEXT: .LBB15_9: # %else16 ; AVX2-NEXT: testl $512, %eax # imm = 0x200 -; AVX2-NEXT: jne .LBB15_19 -; AVX2-NEXT: .LBB15_20: # %else18 +; AVX2-NEXT: jne .LBB15_43 +; AVX2-NEXT: .LBB15_10: # %else18 ; AVX2-NEXT: testl $1024, %eax # imm = 0x400 -; AVX2-NEXT: jne .LBB15_21 -; AVX2-NEXT: .LBB15_22: # %else20 +; AVX2-NEXT: jne .LBB15_44 +; AVX2-NEXT: .LBB15_11: # %else20 ; AVX2-NEXT: testl $2048, %eax # imm = 0x800 -; AVX2-NEXT: jne .LBB15_23 -; AVX2-NEXT: .LBB15_24: # %else22 +; AVX2-NEXT: jne .LBB15_45 +; AVX2-NEXT: .LBB15_12: # %else22 ; AVX2-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX2-NEXT: jne .LBB15_25 -; AVX2-NEXT: .LBB15_26: # %else24 +; AVX2-NEXT: jne .LBB15_46 +; AVX2-NEXT: .LBB15_13: # %else24 ; AVX2-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX2-NEXT: jne .LBB15_27 -; AVX2-NEXT: .LBB15_28: # %else26 +; AVX2-NEXT: jne .LBB15_47 +; AVX2-NEXT: .LBB15_14: # %else26 ; AVX2-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX2-NEXT: jne .LBB15_29 -; AVX2-NEXT: .LBB15_30: # %else28 +; AVX2-NEXT: jne .LBB15_48 +; AVX2-NEXT: .LBB15_15: # %else28 ; AVX2-NEXT: testw %ax, %ax -; AVX2-NEXT: jns .LBB15_32 -; AVX2-NEXT: .LBB15_31: # %cond.store29 +; AVX2-NEXT: jns .LBB15_17 +; AVX2-NEXT: .LBB15_16: # %cond.store29 ; AVX2-NEXT: vpextrb $15, %xmm0, 15(%rdi) -; AVX2-NEXT: .LBB15_32: # %else30 +; AVX2-NEXT: .LBB15_17: # %else30 ; AVX2-NEXT: testl $65536, %eax # imm = 0x10000 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0 -; AVX2-NEXT: jne .LBB15_33 -; AVX2-NEXT: # %bb.34: # %else32 +; AVX2-NEXT: jne .LBB15_49 +; AVX2-NEXT: # %bb.18: # %else32 ; AVX2-NEXT: testl $131072, %eax # imm = 0x20000 -; AVX2-NEXT: jne .LBB15_35 -; AVX2-NEXT: .LBB15_36: # %else34 +; AVX2-NEXT: jne .LBB15_50 +; AVX2-NEXT: .LBB15_19: # %else34 ; AVX2-NEXT: testl $262144, %eax # imm = 0x40000 -; AVX2-NEXT: jne .LBB15_37 -; AVX2-NEXT: .LBB15_38: # %else36 +; AVX2-NEXT: jne .LBB15_51 +; AVX2-NEXT: .LBB15_20: # %else36 ; AVX2-NEXT: testl $524288, %eax # imm = 0x80000 -; AVX2-NEXT: jne .LBB15_39 -; AVX2-NEXT: .LBB15_40: # %else38 +; AVX2-NEXT: jne .LBB15_52 +; AVX2-NEXT: .LBB15_21: # %else38 ; AVX2-NEXT: testl $1048576, %eax # imm = 0x100000 -; AVX2-NEXT: jne .LBB15_41 -; AVX2-NEXT: .LBB15_42: # %else40 +; AVX2-NEXT: jne .LBB15_53 +; AVX2-NEXT: .LBB15_22: # %else40 ; AVX2-NEXT: testl $2097152, %eax # imm = 0x200000 -; AVX2-NEXT: jne .LBB15_43 -; AVX2-NEXT: .LBB15_44: # %else42 +; AVX2-NEXT: jne .LBB15_54 +; AVX2-NEXT: .LBB15_23: # %else42 ; AVX2-NEXT: testl $4194304, %eax # imm = 0x400000 -; AVX2-NEXT: jne .LBB15_45 -; AVX2-NEXT: .LBB15_46: # %else44 +; AVX2-NEXT: jne .LBB15_55 +; AVX2-NEXT: .LBB15_24: # %else44 ; AVX2-NEXT: testl $8388608, %eax # imm = 0x800000 -; AVX2-NEXT: jne .LBB15_47 -; AVX2-NEXT: .LBB15_48: # %else46 +; AVX2-NEXT: jne .LBB15_56 +; AVX2-NEXT: .LBB15_25: # %else46 ; AVX2-NEXT: testl $16777216, %eax # imm = 0x1000000 -; AVX2-NEXT: jne .LBB15_49 -; AVX2-NEXT: .LBB15_50: # %else48 +; AVX2-NEXT: jne .LBB15_57 +; AVX2-NEXT: .LBB15_26: # %else48 ; AVX2-NEXT: testl $33554432, %eax # imm = 0x2000000 -; AVX2-NEXT: jne .LBB15_51 -; AVX2-NEXT: .LBB15_52: # %else50 +; AVX2-NEXT: jne .LBB15_58 +; AVX2-NEXT: .LBB15_27: # %else50 ; AVX2-NEXT: testl $67108864, %eax # imm = 0x4000000 -; AVX2-NEXT: jne .LBB15_53 -; AVX2-NEXT: .LBB15_54: # %else52 +; AVX2-NEXT: jne .LBB15_59 +; AVX2-NEXT: .LBB15_28: # %else52 ; AVX2-NEXT: testl $134217728, %eax # imm = 0x8000000 -; AVX2-NEXT: jne .LBB15_55 -; AVX2-NEXT: .LBB15_56: # %else54 +; AVX2-NEXT: jne .LBB15_60 +; AVX2-NEXT: .LBB15_29: # %else54 ; AVX2-NEXT: testl $268435456, %eax # imm = 0x10000000 -; AVX2-NEXT: jne .LBB15_57 -; AVX2-NEXT: .LBB15_58: # %else56 +; AVX2-NEXT: jne .LBB15_61 +; AVX2-NEXT: .LBB15_30: # %else56 ; AVX2-NEXT: testl $536870912, %eax # imm = 0x20000000 -; AVX2-NEXT: jne .LBB15_59 -; AVX2-NEXT: .LBB15_60: # %else58 +; AVX2-NEXT: jne .LBB15_62 +; AVX2-NEXT: .LBB15_31: # %else58 ; AVX2-NEXT: testl $1073741824, %eax # imm = 0x40000000 -; AVX2-NEXT: jne .LBB15_61 -; AVX2-NEXT: .LBB15_62: # %else60 -; AVX2-NEXT: testl $-2147483648, %eax # imm = 0x80000000 ; AVX2-NEXT: jne .LBB15_63 -; AVX2-NEXT: .LBB15_64: # %else62 +; AVX2-NEXT: .LBB15_32: # %else60 +; AVX2-NEXT: testl $-2147483648, %eax # imm = 0x80000000 +; AVX2-NEXT: jne .LBB15_64 +; AVX2-NEXT: .LBB15_33: # %else62 ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; AVX2-NEXT: .LBB15_1: # %cond.store +; AVX2-NEXT: .LBB15_34: # %cond.store ; AVX2-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je .LBB15_4 -; AVX2-NEXT: .LBB15_3: # %cond.store1 +; AVX2-NEXT: je .LBB15_2 +; AVX2-NEXT: .LBB15_35: # %cond.store1 ; AVX2-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je .LBB15_6 -; AVX2-NEXT: .LBB15_5: # %cond.store3 +; AVX2-NEXT: je .LBB15_3 +; AVX2-NEXT: .LBB15_36: # %cond.store3 ; AVX2-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je .LBB15_8 -; AVX2-NEXT: .LBB15_7: # %cond.store5 +; AVX2-NEXT: je .LBB15_4 +; AVX2-NEXT: .LBB15_37: # %cond.store5 ; AVX2-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: je .LBB15_10 -; AVX2-NEXT: .LBB15_9: # %cond.store7 +; AVX2-NEXT: je .LBB15_5 +; AVX2-NEXT: .LBB15_38: # %cond.store7 ; AVX2-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: je .LBB15_12 -; AVX2-NEXT: .LBB15_11: # %cond.store9 +; AVX2-NEXT: je .LBB15_6 +; AVX2-NEXT: .LBB15_39: # %cond.store9 ; AVX2-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: je .LBB15_14 -; AVX2-NEXT: .LBB15_13: # %cond.store11 +; AVX2-NEXT: je .LBB15_7 +; AVX2-NEXT: .LBB15_40: # %cond.store11 ; AVX2-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX2-NEXT: testb %al, %al -; AVX2-NEXT: jns .LBB15_16 -; AVX2-NEXT: .LBB15_15: # %cond.store13 +; AVX2-NEXT: jns .LBB15_8 +; AVX2-NEXT: .LBB15_41: # %cond.store13 ; AVX2-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX2-NEXT: testl $256, %eax # imm = 0x100 -; AVX2-NEXT: je .LBB15_18 -; AVX2-NEXT: .LBB15_17: # %cond.store15 +; AVX2-NEXT: je .LBB15_9 +; AVX2-NEXT: .LBB15_42: # %cond.store15 ; AVX2-NEXT: vpextrb $8, %xmm0, 8(%rdi) ; AVX2-NEXT: testl $512, %eax # imm = 0x200 -; AVX2-NEXT: je .LBB15_20 -; AVX2-NEXT: .LBB15_19: # %cond.store17 +; AVX2-NEXT: je .LBB15_10 +; AVX2-NEXT: .LBB15_43: # %cond.store17 ; AVX2-NEXT: vpextrb $9, %xmm0, 9(%rdi) ; AVX2-NEXT: testl $1024, %eax # imm = 0x400 -; AVX2-NEXT: je .LBB15_22 -; AVX2-NEXT: .LBB15_21: # %cond.store19 +; AVX2-NEXT: je .LBB15_11 +; AVX2-NEXT: .LBB15_44: # %cond.store19 ; AVX2-NEXT: vpextrb $10, %xmm0, 10(%rdi) ; AVX2-NEXT: testl $2048, %eax # imm = 0x800 -; AVX2-NEXT: je .LBB15_24 -; AVX2-NEXT: .LBB15_23: # %cond.store21 +; AVX2-NEXT: je .LBB15_12 +; AVX2-NEXT: .LBB15_45: # %cond.store21 ; AVX2-NEXT: vpextrb $11, %xmm0, 11(%rdi) ; AVX2-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX2-NEXT: je .LBB15_26 -; AVX2-NEXT: .LBB15_25: # %cond.store23 +; AVX2-NEXT: je .LBB15_13 +; AVX2-NEXT: .LBB15_46: # %cond.store23 ; AVX2-NEXT: vpextrb $12, %xmm0, 12(%rdi) ; AVX2-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX2-NEXT: je .LBB15_28 -; AVX2-NEXT: .LBB15_27: # %cond.store25 +; AVX2-NEXT: je .LBB15_14 +; AVX2-NEXT: .LBB15_47: # %cond.store25 ; AVX2-NEXT: vpextrb $13, %xmm0, 13(%rdi) ; AVX2-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX2-NEXT: je .LBB15_30 -; AVX2-NEXT: .LBB15_29: # %cond.store27 +; AVX2-NEXT: je .LBB15_15 +; AVX2-NEXT: .LBB15_48: # %cond.store27 ; AVX2-NEXT: vpextrb $14, %xmm0, 14(%rdi) ; AVX2-NEXT: testw %ax, %ax -; AVX2-NEXT: js .LBB15_31 -; AVX2-NEXT: jmp .LBB15_32 -; AVX2-NEXT: .LBB15_33: # %cond.store31 +; AVX2-NEXT: js .LBB15_16 +; AVX2-NEXT: jmp .LBB15_17 +; AVX2-NEXT: .LBB15_49: # %cond.store31 ; AVX2-NEXT: vpextrb $0, %xmm0, 16(%rdi) ; AVX2-NEXT: testl $131072, %eax # imm = 0x20000 -; AVX2-NEXT: je .LBB15_36 -; AVX2-NEXT: .LBB15_35: # %cond.store33 +; AVX2-NEXT: je .LBB15_19 +; AVX2-NEXT: .LBB15_50: # %cond.store33 ; AVX2-NEXT: vpextrb $1, %xmm0, 17(%rdi) ; AVX2-NEXT: testl $262144, %eax # imm = 0x40000 -; AVX2-NEXT: je .LBB15_38 -; AVX2-NEXT: .LBB15_37: # %cond.store35 +; AVX2-NEXT: je .LBB15_20 +; AVX2-NEXT: .LBB15_51: # %cond.store35 ; AVX2-NEXT: vpextrb $2, %xmm0, 18(%rdi) ; AVX2-NEXT: testl $524288, %eax # imm = 0x80000 -; AVX2-NEXT: je .LBB15_40 -; AVX2-NEXT: .LBB15_39: # %cond.store37 +; AVX2-NEXT: je .LBB15_21 +; AVX2-NEXT: .LBB15_52: # %cond.store37 ; AVX2-NEXT: vpextrb $3, %xmm0, 19(%rdi) ; AVX2-NEXT: testl $1048576, %eax # imm = 0x100000 -; AVX2-NEXT: je .LBB15_42 -; AVX2-NEXT: .LBB15_41: # %cond.store39 +; AVX2-NEXT: je .LBB15_22 +; AVX2-NEXT: .LBB15_53: # %cond.store39 ; AVX2-NEXT: vpextrb $4, %xmm0, 20(%rdi) ; AVX2-NEXT: testl $2097152, %eax # imm = 0x200000 -; AVX2-NEXT: je .LBB15_44 -; AVX2-NEXT: .LBB15_43: # %cond.store41 +; AVX2-NEXT: je .LBB15_23 +; AVX2-NEXT: .LBB15_54: # %cond.store41 ; AVX2-NEXT: vpextrb $5, %xmm0, 21(%rdi) ; AVX2-NEXT: testl $4194304, %eax # imm = 0x400000 -; AVX2-NEXT: je .LBB15_46 -; AVX2-NEXT: .LBB15_45: # %cond.store43 +; AVX2-NEXT: je .LBB15_24 +; AVX2-NEXT: .LBB15_55: # %cond.store43 ; AVX2-NEXT: vpextrb $6, %xmm0, 22(%rdi) ; AVX2-NEXT: testl $8388608, %eax # imm = 0x800000 -; AVX2-NEXT: je .LBB15_48 -; AVX2-NEXT: .LBB15_47: # %cond.store45 +; AVX2-NEXT: je .LBB15_25 +; AVX2-NEXT: .LBB15_56: # %cond.store45 ; AVX2-NEXT: vpextrb $7, %xmm0, 23(%rdi) ; AVX2-NEXT: testl $16777216, %eax # imm = 0x1000000 -; AVX2-NEXT: je .LBB15_50 -; AVX2-NEXT: .LBB15_49: # %cond.store47 +; AVX2-NEXT: je .LBB15_26 +; AVX2-NEXT: .LBB15_57: # %cond.store47 ; AVX2-NEXT: vpextrb $8, %xmm0, 24(%rdi) ; AVX2-NEXT: testl $33554432, %eax # imm = 0x2000000 -; AVX2-NEXT: je .LBB15_52 -; AVX2-NEXT: .LBB15_51: # %cond.store49 +; AVX2-NEXT: je .LBB15_27 +; AVX2-NEXT: .LBB15_58: # %cond.store49 ; AVX2-NEXT: vpextrb $9, %xmm0, 25(%rdi) ; AVX2-NEXT: testl $67108864, %eax # imm = 0x4000000 -; AVX2-NEXT: je .LBB15_54 -; AVX2-NEXT: .LBB15_53: # %cond.store51 +; AVX2-NEXT: je .LBB15_28 +; AVX2-NEXT: .LBB15_59: # %cond.store51 ; AVX2-NEXT: vpextrb $10, %xmm0, 26(%rdi) ; AVX2-NEXT: testl $134217728, %eax # imm = 0x8000000 -; AVX2-NEXT: je .LBB15_56 -; AVX2-NEXT: .LBB15_55: # %cond.store53 +; AVX2-NEXT: je .LBB15_29 +; AVX2-NEXT: .LBB15_60: # %cond.store53 ; AVX2-NEXT: vpextrb $11, %xmm0, 27(%rdi) ; AVX2-NEXT: testl $268435456, %eax # imm = 0x10000000 -; AVX2-NEXT: je .LBB15_58 -; AVX2-NEXT: .LBB15_57: # %cond.store55 +; AVX2-NEXT: je .LBB15_30 +; AVX2-NEXT: .LBB15_61: # %cond.store55 ; AVX2-NEXT: vpextrb $12, %xmm0, 28(%rdi) ; AVX2-NEXT: testl $536870912, %eax # imm = 0x20000000 -; AVX2-NEXT: je .LBB15_60 -; AVX2-NEXT: .LBB15_59: # %cond.store57 +; AVX2-NEXT: je .LBB15_31 +; AVX2-NEXT: .LBB15_62: # %cond.store57 ; AVX2-NEXT: vpextrb $13, %xmm0, 29(%rdi) ; AVX2-NEXT: testl $1073741824, %eax # imm = 0x40000000 -; AVX2-NEXT: je .LBB15_62 -; AVX2-NEXT: .LBB15_61: # %cond.store59 +; AVX2-NEXT: je .LBB15_32 +; AVX2-NEXT: .LBB15_63: # %cond.store59 ; AVX2-NEXT: vpextrb $14, %xmm0, 30(%rdi) ; AVX2-NEXT: testl $-2147483648, %eax # imm = 0x80000000 -; AVX2-NEXT: je .LBB15_64 -; AVX2-NEXT: .LBB15_63: # %cond.store61 +; AVX2-NEXT: je .LBB15_33 +; AVX2-NEXT: .LBB15_64: # %cond.store61 ; AVX2-NEXT: vpextrb $15, %xmm0, 31(%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq @@ -5969,228 +5969,228 @@ define void @truncstore_v32i16_v32i8(<32 x i16> %x, ptr %p, <32 x i8> %mask) { ; AVX512F-NEXT: vpmovmskb %ymm1, %eax ; AVX512F-NEXT: notl %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB15_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB15_34 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB15_3 -; AVX512F-NEXT: .LBB15_4: # %else2 +; AVX512F-NEXT: jne .LBB15_35 +; AVX512F-NEXT: .LBB15_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB15_5 -; AVX512F-NEXT: .LBB15_6: # %else4 +; AVX512F-NEXT: jne .LBB15_36 +; AVX512F-NEXT: .LBB15_3: # %else4 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne .LBB15_7 -; AVX512F-NEXT: .LBB15_8: # %else6 +; AVX512F-NEXT: jne .LBB15_37 +; AVX512F-NEXT: .LBB15_4: # %else6 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne .LBB15_9 -; AVX512F-NEXT: .LBB15_10: # %else8 +; AVX512F-NEXT: jne .LBB15_38 +; AVX512F-NEXT: .LBB15_5: # %else8 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne .LBB15_11 -; AVX512F-NEXT: .LBB15_12: # %else10 +; AVX512F-NEXT: jne .LBB15_39 +; AVX512F-NEXT: .LBB15_6: # %else10 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne .LBB15_13 -; AVX512F-NEXT: .LBB15_14: # %else12 +; AVX512F-NEXT: jne .LBB15_40 +; AVX512F-NEXT: .LBB15_7: # %else12 ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: js .LBB15_15 -; AVX512F-NEXT: .LBB15_16: # %else14 +; AVX512F-NEXT: js .LBB15_41 +; AVX512F-NEXT: .LBB15_8: # %else14 ; AVX512F-NEXT: testl $256, %eax # imm = 0x100 -; AVX512F-NEXT: jne .LBB15_17 -; AVX512F-NEXT: .LBB15_18: # %else16 +; AVX512F-NEXT: jne .LBB15_42 +; AVX512F-NEXT: .LBB15_9: # %else16 ; AVX512F-NEXT: testl $512, %eax # imm = 0x200 -; AVX512F-NEXT: jne .LBB15_19 -; AVX512F-NEXT: .LBB15_20: # %else18 +; AVX512F-NEXT: jne .LBB15_43 +; AVX512F-NEXT: .LBB15_10: # %else18 ; AVX512F-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512F-NEXT: jne .LBB15_21 -; AVX512F-NEXT: .LBB15_22: # %else20 +; AVX512F-NEXT: jne .LBB15_44 +; AVX512F-NEXT: .LBB15_11: # %else20 ; AVX512F-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512F-NEXT: jne .LBB15_23 -; AVX512F-NEXT: .LBB15_24: # %else22 +; AVX512F-NEXT: jne .LBB15_45 +; AVX512F-NEXT: .LBB15_12: # %else22 ; AVX512F-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512F-NEXT: jne .LBB15_25 -; AVX512F-NEXT: .LBB15_26: # %else24 +; AVX512F-NEXT: jne .LBB15_46 +; AVX512F-NEXT: .LBB15_13: # %else24 ; AVX512F-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512F-NEXT: jne .LBB15_27 -; AVX512F-NEXT: .LBB15_28: # %else26 +; AVX512F-NEXT: jne .LBB15_47 +; AVX512F-NEXT: .LBB15_14: # %else26 ; AVX512F-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512F-NEXT: jne .LBB15_29 -; AVX512F-NEXT: .LBB15_30: # %else28 +; AVX512F-NEXT: jne .LBB15_48 +; AVX512F-NEXT: .LBB15_15: # %else28 ; AVX512F-NEXT: testw %ax, %ax -; AVX512F-NEXT: jns .LBB15_32 -; AVX512F-NEXT: .LBB15_31: # %cond.store29 +; AVX512F-NEXT: jns .LBB15_17 +; AVX512F-NEXT: .LBB15_16: # %cond.store29 ; AVX512F-NEXT: vpextrb $15, %xmm0, 15(%rdi) -; AVX512F-NEXT: .LBB15_32: # %else30 +; AVX512F-NEXT: .LBB15_17: # %else30 ; AVX512F-NEXT: testl $65536, %eax # imm = 0x10000 ; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm0 -; AVX512F-NEXT: jne .LBB15_33 -; AVX512F-NEXT: # %bb.34: # %else32 +; AVX512F-NEXT: jne .LBB15_49 +; AVX512F-NEXT: # %bb.18: # %else32 ; AVX512F-NEXT: testl $131072, %eax # imm = 0x20000 -; AVX512F-NEXT: jne .LBB15_35 -; AVX512F-NEXT: .LBB15_36: # %else34 +; AVX512F-NEXT: jne .LBB15_50 +; AVX512F-NEXT: .LBB15_19: # %else34 ; AVX512F-NEXT: testl $262144, %eax # imm = 0x40000 -; AVX512F-NEXT: jne .LBB15_37 -; AVX512F-NEXT: .LBB15_38: # %else36 +; AVX512F-NEXT: jne .LBB15_51 +; AVX512F-NEXT: .LBB15_20: # %else36 ; AVX512F-NEXT: testl $524288, %eax # imm = 0x80000 -; AVX512F-NEXT: jne .LBB15_39 -; AVX512F-NEXT: .LBB15_40: # %else38 +; AVX512F-NEXT: jne .LBB15_52 +; AVX512F-NEXT: .LBB15_21: # %else38 ; AVX512F-NEXT: testl $1048576, %eax # imm = 0x100000 -; AVX512F-NEXT: jne .LBB15_41 -; AVX512F-NEXT: .LBB15_42: # %else40 +; AVX512F-NEXT: jne .LBB15_53 +; AVX512F-NEXT: .LBB15_22: # %else40 ; AVX512F-NEXT: testl $2097152, %eax # imm = 0x200000 -; AVX512F-NEXT: jne .LBB15_43 -; AVX512F-NEXT: .LBB15_44: # %else42 +; AVX512F-NEXT: jne .LBB15_54 +; AVX512F-NEXT: .LBB15_23: # %else42 ; AVX512F-NEXT: testl $4194304, %eax # imm = 0x400000 -; AVX512F-NEXT: jne .LBB15_45 -; AVX512F-NEXT: .LBB15_46: # %else44 +; AVX512F-NEXT: jne .LBB15_55 +; AVX512F-NEXT: .LBB15_24: # %else44 ; AVX512F-NEXT: testl $8388608, %eax # imm = 0x800000 -; AVX512F-NEXT: jne .LBB15_47 -; AVX512F-NEXT: .LBB15_48: # %else46 +; AVX512F-NEXT: jne .LBB15_56 +; AVX512F-NEXT: .LBB15_25: # %else46 ; AVX512F-NEXT: testl $16777216, %eax # imm = 0x1000000 -; AVX512F-NEXT: jne .LBB15_49 -; AVX512F-NEXT: .LBB15_50: # %else48 +; AVX512F-NEXT: jne .LBB15_57 +; AVX512F-NEXT: .LBB15_26: # %else48 ; AVX512F-NEXT: testl $33554432, %eax # imm = 0x2000000 -; AVX512F-NEXT: jne .LBB15_51 -; AVX512F-NEXT: .LBB15_52: # %else50 +; AVX512F-NEXT: jne .LBB15_58 +; AVX512F-NEXT: .LBB15_27: # %else50 ; AVX512F-NEXT: testl $67108864, %eax # imm = 0x4000000 -; AVX512F-NEXT: jne .LBB15_53 -; AVX512F-NEXT: .LBB15_54: # %else52 +; AVX512F-NEXT: jne .LBB15_59 +; AVX512F-NEXT: .LBB15_28: # %else52 ; AVX512F-NEXT: testl $134217728, %eax # imm = 0x8000000 -; AVX512F-NEXT: jne .LBB15_55 -; AVX512F-NEXT: .LBB15_56: # %else54 +; AVX512F-NEXT: jne .LBB15_60 +; AVX512F-NEXT: .LBB15_29: # %else54 ; AVX512F-NEXT: testl $268435456, %eax # imm = 0x10000000 -; AVX512F-NEXT: jne .LBB15_57 -; AVX512F-NEXT: .LBB15_58: # %else56 +; AVX512F-NEXT: jne .LBB15_61 +; AVX512F-NEXT: .LBB15_30: # %else56 ; AVX512F-NEXT: testl $536870912, %eax # imm = 0x20000000 -; AVX512F-NEXT: jne .LBB15_59 -; AVX512F-NEXT: .LBB15_60: # %else58 +; AVX512F-NEXT: jne .LBB15_62 +; AVX512F-NEXT: .LBB15_31: # %else58 ; AVX512F-NEXT: testl $1073741824, %eax # imm = 0x40000000 -; AVX512F-NEXT: jne .LBB15_61 -; AVX512F-NEXT: .LBB15_62: # %else60 -; AVX512F-NEXT: testl $-2147483648, %eax # imm = 0x80000000 ; AVX512F-NEXT: jne .LBB15_63 -; AVX512F-NEXT: .LBB15_64: # %else62 +; AVX512F-NEXT: .LBB15_32: # %else60 +; AVX512F-NEXT: testl $-2147483648, %eax # imm = 0x80000000 +; AVX512F-NEXT: jne .LBB15_64 +; AVX512F-NEXT: .LBB15_33: # %else62 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB15_1: # %cond.store +; AVX512F-NEXT: .LBB15_34: # %cond.store ; AVX512F-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB15_4 -; AVX512F-NEXT: .LBB15_3: # %cond.store1 +; AVX512F-NEXT: je .LBB15_2 +; AVX512F-NEXT: .LBB15_35: # %cond.store1 ; AVX512F-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB15_6 -; AVX512F-NEXT: .LBB15_5: # %cond.store3 +; AVX512F-NEXT: je .LBB15_3 +; AVX512F-NEXT: .LBB15_36: # %cond.store3 ; AVX512F-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB15_8 -; AVX512F-NEXT: .LBB15_7: # %cond.store5 +; AVX512F-NEXT: je .LBB15_4 +; AVX512F-NEXT: .LBB15_37: # %cond.store5 ; AVX512F-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je .LBB15_10 -; AVX512F-NEXT: .LBB15_9: # %cond.store7 +; AVX512F-NEXT: je .LBB15_5 +; AVX512F-NEXT: .LBB15_38: # %cond.store7 ; AVX512F-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je .LBB15_12 -; AVX512F-NEXT: .LBB15_11: # %cond.store9 +; AVX512F-NEXT: je .LBB15_6 +; AVX512F-NEXT: .LBB15_39: # %cond.store9 ; AVX512F-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je .LBB15_14 -; AVX512F-NEXT: .LBB15_13: # %cond.store11 +; AVX512F-NEXT: je .LBB15_7 +; AVX512F-NEXT: .LBB15_40: # %cond.store11 ; AVX512F-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: jns .LBB15_16 -; AVX512F-NEXT: .LBB15_15: # %cond.store13 +; AVX512F-NEXT: jns .LBB15_8 +; AVX512F-NEXT: .LBB15_41: # %cond.store13 ; AVX512F-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX512F-NEXT: testl $256, %eax # imm = 0x100 -; AVX512F-NEXT: je .LBB15_18 -; AVX512F-NEXT: .LBB15_17: # %cond.store15 +; AVX512F-NEXT: je .LBB15_9 +; AVX512F-NEXT: .LBB15_42: # %cond.store15 ; AVX512F-NEXT: vpextrb $8, %xmm0, 8(%rdi) ; AVX512F-NEXT: testl $512, %eax # imm = 0x200 -; AVX512F-NEXT: je .LBB15_20 -; AVX512F-NEXT: .LBB15_19: # %cond.store17 +; AVX512F-NEXT: je .LBB15_10 +; AVX512F-NEXT: .LBB15_43: # %cond.store17 ; AVX512F-NEXT: vpextrb $9, %xmm0, 9(%rdi) ; AVX512F-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512F-NEXT: je .LBB15_22 -; AVX512F-NEXT: .LBB15_21: # %cond.store19 +; AVX512F-NEXT: je .LBB15_11 +; AVX512F-NEXT: .LBB15_44: # %cond.store19 ; AVX512F-NEXT: vpextrb $10, %xmm0, 10(%rdi) ; AVX512F-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512F-NEXT: je .LBB15_24 -; AVX512F-NEXT: .LBB15_23: # %cond.store21 +; AVX512F-NEXT: je .LBB15_12 +; AVX512F-NEXT: .LBB15_45: # %cond.store21 ; AVX512F-NEXT: vpextrb $11, %xmm0, 11(%rdi) ; AVX512F-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512F-NEXT: je .LBB15_26 -; AVX512F-NEXT: .LBB15_25: # %cond.store23 +; AVX512F-NEXT: je .LBB15_13 +; AVX512F-NEXT: .LBB15_46: # %cond.store23 ; AVX512F-NEXT: vpextrb $12, %xmm0, 12(%rdi) ; AVX512F-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512F-NEXT: je .LBB15_28 -; AVX512F-NEXT: .LBB15_27: # %cond.store25 +; AVX512F-NEXT: je .LBB15_14 +; AVX512F-NEXT: .LBB15_47: # %cond.store25 ; AVX512F-NEXT: vpextrb $13, %xmm0, 13(%rdi) ; AVX512F-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512F-NEXT: je .LBB15_30 -; AVX512F-NEXT: .LBB15_29: # %cond.store27 +; AVX512F-NEXT: je .LBB15_15 +; AVX512F-NEXT: .LBB15_48: # %cond.store27 ; AVX512F-NEXT: vpextrb $14, %xmm0, 14(%rdi) ; AVX512F-NEXT: testw %ax, %ax -; AVX512F-NEXT: js .LBB15_31 -; AVX512F-NEXT: jmp .LBB15_32 -; AVX512F-NEXT: .LBB15_33: # %cond.store31 +; AVX512F-NEXT: js .LBB15_16 +; AVX512F-NEXT: jmp .LBB15_17 +; AVX512F-NEXT: .LBB15_49: # %cond.store31 ; AVX512F-NEXT: vpextrb $0, %xmm0, 16(%rdi) ; AVX512F-NEXT: testl $131072, %eax # imm = 0x20000 -; AVX512F-NEXT: je .LBB15_36 -; AVX512F-NEXT: .LBB15_35: # %cond.store33 +; AVX512F-NEXT: je .LBB15_19 +; AVX512F-NEXT: .LBB15_50: # %cond.store33 ; AVX512F-NEXT: vpextrb $1, %xmm0, 17(%rdi) ; AVX512F-NEXT: testl $262144, %eax # imm = 0x40000 -; AVX512F-NEXT: je .LBB15_38 -; AVX512F-NEXT: .LBB15_37: # %cond.store35 +; AVX512F-NEXT: je .LBB15_20 +; AVX512F-NEXT: .LBB15_51: # %cond.store35 ; AVX512F-NEXT: vpextrb $2, %xmm0, 18(%rdi) ; AVX512F-NEXT: testl $524288, %eax # imm = 0x80000 -; AVX512F-NEXT: je .LBB15_40 -; AVX512F-NEXT: .LBB15_39: # %cond.store37 +; AVX512F-NEXT: je .LBB15_21 +; AVX512F-NEXT: .LBB15_52: # %cond.store37 ; AVX512F-NEXT: vpextrb $3, %xmm0, 19(%rdi) ; AVX512F-NEXT: testl $1048576, %eax # imm = 0x100000 -; AVX512F-NEXT: je .LBB15_42 -; AVX512F-NEXT: .LBB15_41: # %cond.store39 +; AVX512F-NEXT: je .LBB15_22 +; AVX512F-NEXT: .LBB15_53: # %cond.store39 ; AVX512F-NEXT: vpextrb $4, %xmm0, 20(%rdi) ; AVX512F-NEXT: testl $2097152, %eax # imm = 0x200000 -; AVX512F-NEXT: je .LBB15_44 -; AVX512F-NEXT: .LBB15_43: # %cond.store41 +; AVX512F-NEXT: je .LBB15_23 +; AVX512F-NEXT: .LBB15_54: # %cond.store41 ; AVX512F-NEXT: vpextrb $5, %xmm0, 21(%rdi) ; AVX512F-NEXT: testl $4194304, %eax # imm = 0x400000 -; AVX512F-NEXT: je .LBB15_46 -; AVX512F-NEXT: .LBB15_45: # %cond.store43 +; AVX512F-NEXT: je .LBB15_24 +; AVX512F-NEXT: .LBB15_55: # %cond.store43 ; AVX512F-NEXT: vpextrb $6, %xmm0, 22(%rdi) ; AVX512F-NEXT: testl $8388608, %eax # imm = 0x800000 -; AVX512F-NEXT: je .LBB15_48 -; AVX512F-NEXT: .LBB15_47: # %cond.store45 +; AVX512F-NEXT: je .LBB15_25 +; AVX512F-NEXT: .LBB15_56: # %cond.store45 ; AVX512F-NEXT: vpextrb $7, %xmm0, 23(%rdi) ; AVX512F-NEXT: testl $16777216, %eax # imm = 0x1000000 -; AVX512F-NEXT: je .LBB15_50 -; AVX512F-NEXT: .LBB15_49: # %cond.store47 +; AVX512F-NEXT: je .LBB15_26 +; AVX512F-NEXT: .LBB15_57: # %cond.store47 ; AVX512F-NEXT: vpextrb $8, %xmm0, 24(%rdi) ; AVX512F-NEXT: testl $33554432, %eax # imm = 0x2000000 -; AVX512F-NEXT: je .LBB15_52 -; AVX512F-NEXT: .LBB15_51: # %cond.store49 +; AVX512F-NEXT: je .LBB15_27 +; AVX512F-NEXT: .LBB15_58: # %cond.store49 ; AVX512F-NEXT: vpextrb $9, %xmm0, 25(%rdi) ; AVX512F-NEXT: testl $67108864, %eax # imm = 0x4000000 -; AVX512F-NEXT: je .LBB15_54 -; AVX512F-NEXT: .LBB15_53: # %cond.store51 +; AVX512F-NEXT: je .LBB15_28 +; AVX512F-NEXT: .LBB15_59: # %cond.store51 ; AVX512F-NEXT: vpextrb $10, %xmm0, 26(%rdi) ; AVX512F-NEXT: testl $134217728, %eax # imm = 0x8000000 -; AVX512F-NEXT: je .LBB15_56 -; AVX512F-NEXT: .LBB15_55: # %cond.store53 +; AVX512F-NEXT: je .LBB15_29 +; AVX512F-NEXT: .LBB15_60: # %cond.store53 ; AVX512F-NEXT: vpextrb $11, %xmm0, 27(%rdi) ; AVX512F-NEXT: testl $268435456, %eax # imm = 0x10000000 -; AVX512F-NEXT: je .LBB15_58 -; AVX512F-NEXT: .LBB15_57: # %cond.store55 +; AVX512F-NEXT: je .LBB15_30 +; AVX512F-NEXT: .LBB15_61: # %cond.store55 ; AVX512F-NEXT: vpextrb $12, %xmm0, 28(%rdi) ; AVX512F-NEXT: testl $536870912, %eax # imm = 0x20000000 -; AVX512F-NEXT: je .LBB15_60 -; AVX512F-NEXT: .LBB15_59: # %cond.store57 +; AVX512F-NEXT: je .LBB15_31 +; AVX512F-NEXT: .LBB15_62: # %cond.store57 ; AVX512F-NEXT: vpextrb $13, %xmm0, 29(%rdi) ; AVX512F-NEXT: testl $1073741824, %eax # imm = 0x40000000 -; AVX512F-NEXT: je .LBB15_62 -; AVX512F-NEXT: .LBB15_61: # %cond.store59 +; AVX512F-NEXT: je .LBB15_32 +; AVX512F-NEXT: .LBB15_63: # %cond.store59 ; AVX512F-NEXT: vpextrb $14, %xmm0, 30(%rdi) ; AVX512F-NEXT: testl $-2147483648, %eax # imm = 0x80000000 -; AVX512F-NEXT: je .LBB15_64 -; AVX512F-NEXT: .LBB15_63: # %cond.store61 +; AVX512F-NEXT: je .LBB15_33 +; AVX512F-NEXT: .LBB15_64: # %cond.store61 ; AVX512F-NEXT: vpextrb $15, %xmm0, 31(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -6208,228 +6208,228 @@ define void @truncstore_v32i16_v32i8(<32 x i16> %x, ptr %p, <32 x i8> %mask) { ; AVX512FVL-NEXT: vpmovmskb %ymm1, %eax ; AVX512FVL-NEXT: notl %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB15_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB15_34 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB15_3 -; AVX512FVL-NEXT: .LBB15_4: # %else2 +; AVX512FVL-NEXT: jne .LBB15_35 +; AVX512FVL-NEXT: .LBB15_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB15_5 -; AVX512FVL-NEXT: .LBB15_6: # %else4 +; AVX512FVL-NEXT: jne .LBB15_36 +; AVX512FVL-NEXT: .LBB15_3: # %else4 ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: jne .LBB15_7 -; AVX512FVL-NEXT: .LBB15_8: # %else6 +; AVX512FVL-NEXT: jne .LBB15_37 +; AVX512FVL-NEXT: .LBB15_4: # %else6 ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: jne .LBB15_9 -; AVX512FVL-NEXT: .LBB15_10: # %else8 +; AVX512FVL-NEXT: jne .LBB15_38 +; AVX512FVL-NEXT: .LBB15_5: # %else8 ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: jne .LBB15_11 -; AVX512FVL-NEXT: .LBB15_12: # %else10 +; AVX512FVL-NEXT: jne .LBB15_39 +; AVX512FVL-NEXT: .LBB15_6: # %else10 ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: jne .LBB15_13 -; AVX512FVL-NEXT: .LBB15_14: # %else12 +; AVX512FVL-NEXT: jne .LBB15_40 +; AVX512FVL-NEXT: .LBB15_7: # %else12 ; AVX512FVL-NEXT: testb %al, %al -; AVX512FVL-NEXT: js .LBB15_15 -; AVX512FVL-NEXT: .LBB15_16: # %else14 +; AVX512FVL-NEXT: js .LBB15_41 +; AVX512FVL-NEXT: .LBB15_8: # %else14 ; AVX512FVL-NEXT: testl $256, %eax # imm = 0x100 -; AVX512FVL-NEXT: jne .LBB15_17 -; AVX512FVL-NEXT: .LBB15_18: # %else16 +; AVX512FVL-NEXT: jne .LBB15_42 +; AVX512FVL-NEXT: .LBB15_9: # %else16 ; AVX512FVL-NEXT: testl $512, %eax # imm = 0x200 -; AVX512FVL-NEXT: jne .LBB15_19 -; AVX512FVL-NEXT: .LBB15_20: # %else18 +; AVX512FVL-NEXT: jne .LBB15_43 +; AVX512FVL-NEXT: .LBB15_10: # %else18 ; AVX512FVL-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512FVL-NEXT: jne .LBB15_21 -; AVX512FVL-NEXT: .LBB15_22: # %else20 +; AVX512FVL-NEXT: jne .LBB15_44 +; AVX512FVL-NEXT: .LBB15_11: # %else20 ; AVX512FVL-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512FVL-NEXT: jne .LBB15_23 -; AVX512FVL-NEXT: .LBB15_24: # %else22 +; AVX512FVL-NEXT: jne .LBB15_45 +; AVX512FVL-NEXT: .LBB15_12: # %else22 ; AVX512FVL-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512FVL-NEXT: jne .LBB15_25 -; AVX512FVL-NEXT: .LBB15_26: # %else24 +; AVX512FVL-NEXT: jne .LBB15_46 +; AVX512FVL-NEXT: .LBB15_13: # %else24 ; AVX512FVL-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512FVL-NEXT: jne .LBB15_27 -; AVX512FVL-NEXT: .LBB15_28: # %else26 +; AVX512FVL-NEXT: jne .LBB15_47 +; AVX512FVL-NEXT: .LBB15_14: # %else26 ; AVX512FVL-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512FVL-NEXT: jne .LBB15_29 -; AVX512FVL-NEXT: .LBB15_30: # %else28 +; AVX512FVL-NEXT: jne .LBB15_48 +; AVX512FVL-NEXT: .LBB15_15: # %else28 ; AVX512FVL-NEXT: testw %ax, %ax -; AVX512FVL-NEXT: jns .LBB15_32 -; AVX512FVL-NEXT: .LBB15_31: # %cond.store29 +; AVX512FVL-NEXT: jns .LBB15_17 +; AVX512FVL-NEXT: .LBB15_16: # %cond.store29 ; AVX512FVL-NEXT: vpextrb $15, %xmm0, 15(%rdi) -; AVX512FVL-NEXT: .LBB15_32: # %else30 +; AVX512FVL-NEXT: .LBB15_17: # %else30 ; AVX512FVL-NEXT: testl $65536, %eax # imm = 0x10000 ; AVX512FVL-NEXT: vextracti128 $1, %ymm0, %xmm0 -; AVX512FVL-NEXT: jne .LBB15_33 -; AVX512FVL-NEXT: # %bb.34: # %else32 +; AVX512FVL-NEXT: jne .LBB15_49 +; AVX512FVL-NEXT: # %bb.18: # %else32 ; AVX512FVL-NEXT: testl $131072, %eax # imm = 0x20000 -; AVX512FVL-NEXT: jne .LBB15_35 -; AVX512FVL-NEXT: .LBB15_36: # %else34 +; AVX512FVL-NEXT: jne .LBB15_50 +; AVX512FVL-NEXT: .LBB15_19: # %else34 ; AVX512FVL-NEXT: testl $262144, %eax # imm = 0x40000 -; AVX512FVL-NEXT: jne .LBB15_37 -; AVX512FVL-NEXT: .LBB15_38: # %else36 +; AVX512FVL-NEXT: jne .LBB15_51 +; AVX512FVL-NEXT: .LBB15_20: # %else36 ; AVX512FVL-NEXT: testl $524288, %eax # imm = 0x80000 -; AVX512FVL-NEXT: jne .LBB15_39 -; AVX512FVL-NEXT: .LBB15_40: # %else38 +; AVX512FVL-NEXT: jne .LBB15_52 +; AVX512FVL-NEXT: .LBB15_21: # %else38 ; AVX512FVL-NEXT: testl $1048576, %eax # imm = 0x100000 -; AVX512FVL-NEXT: jne .LBB15_41 -; AVX512FVL-NEXT: .LBB15_42: # %else40 +; AVX512FVL-NEXT: jne .LBB15_53 +; AVX512FVL-NEXT: .LBB15_22: # %else40 ; AVX512FVL-NEXT: testl $2097152, %eax # imm = 0x200000 -; AVX512FVL-NEXT: jne .LBB15_43 -; AVX512FVL-NEXT: .LBB15_44: # %else42 +; AVX512FVL-NEXT: jne .LBB15_54 +; AVX512FVL-NEXT: .LBB15_23: # %else42 ; AVX512FVL-NEXT: testl $4194304, %eax # imm = 0x400000 -; AVX512FVL-NEXT: jne .LBB15_45 -; AVX512FVL-NEXT: .LBB15_46: # %else44 +; AVX512FVL-NEXT: jne .LBB15_55 +; AVX512FVL-NEXT: .LBB15_24: # %else44 ; AVX512FVL-NEXT: testl $8388608, %eax # imm = 0x800000 -; AVX512FVL-NEXT: jne .LBB15_47 -; AVX512FVL-NEXT: .LBB15_48: # %else46 +; AVX512FVL-NEXT: jne .LBB15_56 +; AVX512FVL-NEXT: .LBB15_25: # %else46 ; AVX512FVL-NEXT: testl $16777216, %eax # imm = 0x1000000 -; AVX512FVL-NEXT: jne .LBB15_49 -; AVX512FVL-NEXT: .LBB15_50: # %else48 +; AVX512FVL-NEXT: jne .LBB15_57 +; AVX512FVL-NEXT: .LBB15_26: # %else48 ; AVX512FVL-NEXT: testl $33554432, %eax # imm = 0x2000000 -; AVX512FVL-NEXT: jne .LBB15_51 -; AVX512FVL-NEXT: .LBB15_52: # %else50 +; AVX512FVL-NEXT: jne .LBB15_58 +; AVX512FVL-NEXT: .LBB15_27: # %else50 ; AVX512FVL-NEXT: testl $67108864, %eax # imm = 0x4000000 -; AVX512FVL-NEXT: jne .LBB15_53 -; AVX512FVL-NEXT: .LBB15_54: # %else52 +; AVX512FVL-NEXT: jne .LBB15_59 +; AVX512FVL-NEXT: .LBB15_28: # %else52 ; AVX512FVL-NEXT: testl $134217728, %eax # imm = 0x8000000 -; AVX512FVL-NEXT: jne .LBB15_55 -; AVX512FVL-NEXT: .LBB15_56: # %else54 +; AVX512FVL-NEXT: jne .LBB15_60 +; AVX512FVL-NEXT: .LBB15_29: # %else54 ; AVX512FVL-NEXT: testl $268435456, %eax # imm = 0x10000000 -; AVX512FVL-NEXT: jne .LBB15_57 -; AVX512FVL-NEXT: .LBB15_58: # %else56 +; AVX512FVL-NEXT: jne .LBB15_61 +; AVX512FVL-NEXT: .LBB15_30: # %else56 ; AVX512FVL-NEXT: testl $536870912, %eax # imm = 0x20000000 -; AVX512FVL-NEXT: jne .LBB15_59 -; AVX512FVL-NEXT: .LBB15_60: # %else58 +; AVX512FVL-NEXT: jne .LBB15_62 +; AVX512FVL-NEXT: .LBB15_31: # %else58 ; AVX512FVL-NEXT: testl $1073741824, %eax # imm = 0x40000000 -; AVX512FVL-NEXT: jne .LBB15_61 -; AVX512FVL-NEXT: .LBB15_62: # %else60 -; AVX512FVL-NEXT: testl $-2147483648, %eax # imm = 0x80000000 ; AVX512FVL-NEXT: jne .LBB15_63 -; AVX512FVL-NEXT: .LBB15_64: # %else62 +; AVX512FVL-NEXT: .LBB15_32: # %else60 +; AVX512FVL-NEXT: testl $-2147483648, %eax # imm = 0x80000000 +; AVX512FVL-NEXT: jne .LBB15_64 +; AVX512FVL-NEXT: .LBB15_33: # %else62 ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB15_1: # %cond.store +; AVX512FVL-NEXT: .LBB15_34: # %cond.store ; AVX512FVL-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB15_4 -; AVX512FVL-NEXT: .LBB15_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB15_2 +; AVX512FVL-NEXT: .LBB15_35: # %cond.store1 ; AVX512FVL-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB15_6 -; AVX512FVL-NEXT: .LBB15_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB15_3 +; AVX512FVL-NEXT: .LBB15_36: # %cond.store3 ; AVX512FVL-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB15_8 -; AVX512FVL-NEXT: .LBB15_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB15_4 +; AVX512FVL-NEXT: .LBB15_37: # %cond.store5 ; AVX512FVL-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: je .LBB15_10 -; AVX512FVL-NEXT: .LBB15_9: # %cond.store7 +; AVX512FVL-NEXT: je .LBB15_5 +; AVX512FVL-NEXT: .LBB15_38: # %cond.store7 ; AVX512FVL-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: je .LBB15_12 -; AVX512FVL-NEXT: .LBB15_11: # %cond.store9 +; AVX512FVL-NEXT: je .LBB15_6 +; AVX512FVL-NEXT: .LBB15_39: # %cond.store9 ; AVX512FVL-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: je .LBB15_14 -; AVX512FVL-NEXT: .LBB15_13: # %cond.store11 +; AVX512FVL-NEXT: je .LBB15_7 +; AVX512FVL-NEXT: .LBB15_40: # %cond.store11 ; AVX512FVL-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX512FVL-NEXT: testb %al, %al -; AVX512FVL-NEXT: jns .LBB15_16 -; AVX512FVL-NEXT: .LBB15_15: # %cond.store13 +; AVX512FVL-NEXT: jns .LBB15_8 +; AVX512FVL-NEXT: .LBB15_41: # %cond.store13 ; AVX512FVL-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX512FVL-NEXT: testl $256, %eax # imm = 0x100 -; AVX512FVL-NEXT: je .LBB15_18 -; AVX512FVL-NEXT: .LBB15_17: # %cond.store15 +; AVX512FVL-NEXT: je .LBB15_9 +; AVX512FVL-NEXT: .LBB15_42: # %cond.store15 ; AVX512FVL-NEXT: vpextrb $8, %xmm0, 8(%rdi) ; AVX512FVL-NEXT: testl $512, %eax # imm = 0x200 -; AVX512FVL-NEXT: je .LBB15_20 -; AVX512FVL-NEXT: .LBB15_19: # %cond.store17 +; AVX512FVL-NEXT: je .LBB15_10 +; AVX512FVL-NEXT: .LBB15_43: # %cond.store17 ; AVX512FVL-NEXT: vpextrb $9, %xmm0, 9(%rdi) ; AVX512FVL-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512FVL-NEXT: je .LBB15_22 -; AVX512FVL-NEXT: .LBB15_21: # %cond.store19 +; AVX512FVL-NEXT: je .LBB15_11 +; AVX512FVL-NEXT: .LBB15_44: # %cond.store19 ; AVX512FVL-NEXT: vpextrb $10, %xmm0, 10(%rdi) ; AVX512FVL-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512FVL-NEXT: je .LBB15_24 -; AVX512FVL-NEXT: .LBB15_23: # %cond.store21 +; AVX512FVL-NEXT: je .LBB15_12 +; AVX512FVL-NEXT: .LBB15_45: # %cond.store21 ; AVX512FVL-NEXT: vpextrb $11, %xmm0, 11(%rdi) ; AVX512FVL-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512FVL-NEXT: je .LBB15_26 -; AVX512FVL-NEXT: .LBB15_25: # %cond.store23 +; AVX512FVL-NEXT: je .LBB15_13 +; AVX512FVL-NEXT: .LBB15_46: # %cond.store23 ; AVX512FVL-NEXT: vpextrb $12, %xmm0, 12(%rdi) ; AVX512FVL-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512FVL-NEXT: je .LBB15_28 -; AVX512FVL-NEXT: .LBB15_27: # %cond.store25 +; AVX512FVL-NEXT: je .LBB15_14 +; AVX512FVL-NEXT: .LBB15_47: # %cond.store25 ; AVX512FVL-NEXT: vpextrb $13, %xmm0, 13(%rdi) ; AVX512FVL-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512FVL-NEXT: je .LBB15_30 -; AVX512FVL-NEXT: .LBB15_29: # %cond.store27 +; AVX512FVL-NEXT: je .LBB15_15 +; AVX512FVL-NEXT: .LBB15_48: # %cond.store27 ; AVX512FVL-NEXT: vpextrb $14, %xmm0, 14(%rdi) ; AVX512FVL-NEXT: testw %ax, %ax -; AVX512FVL-NEXT: js .LBB15_31 -; AVX512FVL-NEXT: jmp .LBB15_32 -; AVX512FVL-NEXT: .LBB15_33: # %cond.store31 +; AVX512FVL-NEXT: js .LBB15_16 +; AVX512FVL-NEXT: jmp .LBB15_17 +; AVX512FVL-NEXT: .LBB15_49: # %cond.store31 ; AVX512FVL-NEXT: vpextrb $0, %xmm0, 16(%rdi) ; AVX512FVL-NEXT: testl $131072, %eax # imm = 0x20000 -; AVX512FVL-NEXT: je .LBB15_36 -; AVX512FVL-NEXT: .LBB15_35: # %cond.store33 +; AVX512FVL-NEXT: je .LBB15_19 +; AVX512FVL-NEXT: .LBB15_50: # %cond.store33 ; AVX512FVL-NEXT: vpextrb $1, %xmm0, 17(%rdi) ; AVX512FVL-NEXT: testl $262144, %eax # imm = 0x40000 -; AVX512FVL-NEXT: je .LBB15_38 -; AVX512FVL-NEXT: .LBB15_37: # %cond.store35 +; AVX512FVL-NEXT: je .LBB15_20 +; AVX512FVL-NEXT: .LBB15_51: # %cond.store35 ; AVX512FVL-NEXT: vpextrb $2, %xmm0, 18(%rdi) ; AVX512FVL-NEXT: testl $524288, %eax # imm = 0x80000 -; AVX512FVL-NEXT: je .LBB15_40 -; AVX512FVL-NEXT: .LBB15_39: # %cond.store37 +; AVX512FVL-NEXT: je .LBB15_21 +; AVX512FVL-NEXT: .LBB15_52: # %cond.store37 ; AVX512FVL-NEXT: vpextrb $3, %xmm0, 19(%rdi) ; AVX512FVL-NEXT: testl $1048576, %eax # imm = 0x100000 -; AVX512FVL-NEXT: je .LBB15_42 -; AVX512FVL-NEXT: .LBB15_41: # %cond.store39 +; AVX512FVL-NEXT: je .LBB15_22 +; AVX512FVL-NEXT: .LBB15_53: # %cond.store39 ; AVX512FVL-NEXT: vpextrb $4, %xmm0, 20(%rdi) ; AVX512FVL-NEXT: testl $2097152, %eax # imm = 0x200000 -; AVX512FVL-NEXT: je .LBB15_44 -; AVX512FVL-NEXT: .LBB15_43: # %cond.store41 +; AVX512FVL-NEXT: je .LBB15_23 +; AVX512FVL-NEXT: .LBB15_54: # %cond.store41 ; AVX512FVL-NEXT: vpextrb $5, %xmm0, 21(%rdi) ; AVX512FVL-NEXT: testl $4194304, %eax # imm = 0x400000 -; AVX512FVL-NEXT: je .LBB15_46 -; AVX512FVL-NEXT: .LBB15_45: # %cond.store43 +; AVX512FVL-NEXT: je .LBB15_24 +; AVX512FVL-NEXT: .LBB15_55: # %cond.store43 ; AVX512FVL-NEXT: vpextrb $6, %xmm0, 22(%rdi) ; AVX512FVL-NEXT: testl $8388608, %eax # imm = 0x800000 -; AVX512FVL-NEXT: je .LBB15_48 -; AVX512FVL-NEXT: .LBB15_47: # %cond.store45 +; AVX512FVL-NEXT: je .LBB15_25 +; AVX512FVL-NEXT: .LBB15_56: # %cond.store45 ; AVX512FVL-NEXT: vpextrb $7, %xmm0, 23(%rdi) ; AVX512FVL-NEXT: testl $16777216, %eax # imm = 0x1000000 -; AVX512FVL-NEXT: je .LBB15_50 -; AVX512FVL-NEXT: .LBB15_49: # %cond.store47 +; AVX512FVL-NEXT: je .LBB15_26 +; AVX512FVL-NEXT: .LBB15_57: # %cond.store47 ; AVX512FVL-NEXT: vpextrb $8, %xmm0, 24(%rdi) ; AVX512FVL-NEXT: testl $33554432, %eax # imm = 0x2000000 -; AVX512FVL-NEXT: je .LBB15_52 -; AVX512FVL-NEXT: .LBB15_51: # %cond.store49 +; AVX512FVL-NEXT: je .LBB15_27 +; AVX512FVL-NEXT: .LBB15_58: # %cond.store49 ; AVX512FVL-NEXT: vpextrb $9, %xmm0, 25(%rdi) ; AVX512FVL-NEXT: testl $67108864, %eax # imm = 0x4000000 -; AVX512FVL-NEXT: je .LBB15_54 -; AVX512FVL-NEXT: .LBB15_53: # %cond.store51 +; AVX512FVL-NEXT: je .LBB15_28 +; AVX512FVL-NEXT: .LBB15_59: # %cond.store51 ; AVX512FVL-NEXT: vpextrb $10, %xmm0, 26(%rdi) ; AVX512FVL-NEXT: testl $134217728, %eax # imm = 0x8000000 -; AVX512FVL-NEXT: je .LBB15_56 -; AVX512FVL-NEXT: .LBB15_55: # %cond.store53 +; AVX512FVL-NEXT: je .LBB15_29 +; AVX512FVL-NEXT: .LBB15_60: # %cond.store53 ; AVX512FVL-NEXT: vpextrb $11, %xmm0, 27(%rdi) ; AVX512FVL-NEXT: testl $268435456, %eax # imm = 0x10000000 -; AVX512FVL-NEXT: je .LBB15_58 -; AVX512FVL-NEXT: .LBB15_57: # %cond.store55 +; AVX512FVL-NEXT: je .LBB15_30 +; AVX512FVL-NEXT: .LBB15_61: # %cond.store55 ; AVX512FVL-NEXT: vpextrb $12, %xmm0, 28(%rdi) ; AVX512FVL-NEXT: testl $536870912, %eax # imm = 0x20000000 -; AVX512FVL-NEXT: je .LBB15_60 -; AVX512FVL-NEXT: .LBB15_59: # %cond.store57 +; AVX512FVL-NEXT: je .LBB15_31 +; AVX512FVL-NEXT: .LBB15_62: # %cond.store57 ; AVX512FVL-NEXT: vpextrb $13, %xmm0, 29(%rdi) ; AVX512FVL-NEXT: testl $1073741824, %eax # imm = 0x40000000 -; AVX512FVL-NEXT: je .LBB15_62 -; AVX512FVL-NEXT: .LBB15_61: # %cond.store59 +; AVX512FVL-NEXT: je .LBB15_32 +; AVX512FVL-NEXT: .LBB15_63: # %cond.store59 ; AVX512FVL-NEXT: vpextrb $14, %xmm0, 30(%rdi) ; AVX512FVL-NEXT: testl $-2147483648, %eax # imm = 0x80000000 -; AVX512FVL-NEXT: je .LBB15_64 -; AVX512FVL-NEXT: .LBB15_63: # %cond.store61 +; AVX512FVL-NEXT: je .LBB15_33 +; AVX512FVL-NEXT: .LBB15_64: # %cond.store61 ; AVX512FVL-NEXT: vpextrb $15, %xmm0, 31(%rdi) ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq @@ -6467,103 +6467,103 @@ define void @truncstore_v16i16_v16i8(<16 x i16> %x, ptr %p, <16 x i8> %mask) { ; SSE2-NEXT: xorl $65535, %eax # imm = 0xFFFF ; SSE2-NEXT: testb $1, %al ; SSE2-NEXT: movd %xmm0, %ecx -; SSE2-NEXT: jne .LBB16_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB16_28 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne .LBB16_3 -; SSE2-NEXT: .LBB16_4: # %else2 +; SSE2-NEXT: jne .LBB16_29 +; SSE2-NEXT: .LBB16_2: # %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne .LBB16_5 -; SSE2-NEXT: .LBB16_6: # %else4 +; SSE2-NEXT: jne .LBB16_30 +; SSE2-NEXT: .LBB16_3: # %else4 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je .LBB16_8 -; SSE2-NEXT: .LBB16_7: # %cond.store5 +; SSE2-NEXT: je .LBB16_5 +; SSE2-NEXT: .LBB16_4: # %cond.store5 ; SSE2-NEXT: shrl $24, %ecx ; SSE2-NEXT: movb %cl, 3(%rdi) -; SSE2-NEXT: .LBB16_8: # %else6 +; SSE2-NEXT: .LBB16_5: # %else6 ; SSE2-NEXT: testb $16, %al ; SSE2-NEXT: pextrw $2, %xmm0, %ecx -; SSE2-NEXT: je .LBB16_10 -; SSE2-NEXT: # %bb.9: # %cond.store7 +; SSE2-NEXT: je .LBB16_7 +; SSE2-NEXT: # %bb.6: # %cond.store7 ; SSE2-NEXT: movb %cl, 4(%rdi) -; SSE2-NEXT: .LBB16_10: # %else8 +; SSE2-NEXT: .LBB16_7: # %else8 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je .LBB16_12 -; SSE2-NEXT: # %bb.11: # %cond.store9 +; SSE2-NEXT: je .LBB16_9 +; SSE2-NEXT: # %bb.8: # %cond.store9 ; SSE2-NEXT: movb %ch, 5(%rdi) -; SSE2-NEXT: .LBB16_12: # %else10 +; SSE2-NEXT: .LBB16_9: # %else10 ; SSE2-NEXT: testb $64, %al ; SSE2-NEXT: pextrw $3, %xmm0, %ecx -; SSE2-NEXT: je .LBB16_14 -; SSE2-NEXT: # %bb.13: # %cond.store11 +; SSE2-NEXT: je .LBB16_11 +; SSE2-NEXT: # %bb.10: # %cond.store11 ; SSE2-NEXT: movb %cl, 6(%rdi) -; SSE2-NEXT: .LBB16_14: # %else12 +; SSE2-NEXT: .LBB16_11: # %else12 ; SSE2-NEXT: testb %al, %al -; SSE2-NEXT: jns .LBB16_16 -; SSE2-NEXT: # %bb.15: # %cond.store13 +; SSE2-NEXT: jns .LBB16_13 +; SSE2-NEXT: # %bb.12: # %cond.store13 ; SSE2-NEXT: movb %ch, 7(%rdi) -; SSE2-NEXT: .LBB16_16: # %else14 +; SSE2-NEXT: .LBB16_13: # %else14 ; SSE2-NEXT: testl $256, %eax # imm = 0x100 ; SSE2-NEXT: pextrw $4, %xmm0, %ecx -; SSE2-NEXT: je .LBB16_18 -; SSE2-NEXT: # %bb.17: # %cond.store15 +; SSE2-NEXT: je .LBB16_15 +; SSE2-NEXT: # %bb.14: # %cond.store15 ; SSE2-NEXT: movb %cl, 8(%rdi) -; SSE2-NEXT: .LBB16_18: # %else16 +; SSE2-NEXT: .LBB16_15: # %else16 ; SSE2-NEXT: testl $512, %eax # imm = 0x200 -; SSE2-NEXT: je .LBB16_20 -; SSE2-NEXT: # %bb.19: # %cond.store17 +; SSE2-NEXT: je .LBB16_17 +; SSE2-NEXT: # %bb.16: # %cond.store17 ; SSE2-NEXT: movb %ch, 9(%rdi) -; SSE2-NEXT: .LBB16_20: # %else18 +; SSE2-NEXT: .LBB16_17: # %else18 ; SSE2-NEXT: testl $1024, %eax # imm = 0x400 ; SSE2-NEXT: pextrw $5, %xmm0, %ecx -; SSE2-NEXT: je .LBB16_22 -; SSE2-NEXT: # %bb.21: # %cond.store19 +; SSE2-NEXT: je .LBB16_19 +; SSE2-NEXT: # %bb.18: # %cond.store19 ; SSE2-NEXT: movb %cl, 10(%rdi) -; SSE2-NEXT: .LBB16_22: # %else20 +; SSE2-NEXT: .LBB16_19: # %else20 ; SSE2-NEXT: testl $2048, %eax # imm = 0x800 -; SSE2-NEXT: je .LBB16_24 -; SSE2-NEXT: # %bb.23: # %cond.store21 +; SSE2-NEXT: je .LBB16_21 +; SSE2-NEXT: # %bb.20: # %cond.store21 ; SSE2-NEXT: movb %ch, 11(%rdi) -; SSE2-NEXT: .LBB16_24: # %else22 +; SSE2-NEXT: .LBB16_21: # %else22 ; SSE2-NEXT: testl $4096, %eax # imm = 0x1000 ; SSE2-NEXT: pextrw $6, %xmm0, %ecx -; SSE2-NEXT: je .LBB16_26 -; SSE2-NEXT: # %bb.25: # %cond.store23 +; SSE2-NEXT: je .LBB16_23 +; SSE2-NEXT: # %bb.22: # %cond.store23 ; SSE2-NEXT: movb %cl, 12(%rdi) -; SSE2-NEXT: .LBB16_26: # %else24 +; SSE2-NEXT: .LBB16_23: # %else24 ; SSE2-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE2-NEXT: je .LBB16_28 -; SSE2-NEXT: # %bb.27: # %cond.store25 +; SSE2-NEXT: je .LBB16_25 +; SSE2-NEXT: # %bb.24: # %cond.store25 ; SSE2-NEXT: movb %ch, 13(%rdi) -; SSE2-NEXT: .LBB16_28: # %else26 +; SSE2-NEXT: .LBB16_25: # %else26 ; SSE2-NEXT: testl $16384, %eax # imm = 0x4000 ; SSE2-NEXT: pextrw $7, %xmm0, %ecx -; SSE2-NEXT: jne .LBB16_29 -; SSE2-NEXT: # %bb.30: # %else28 -; SSE2-NEXT: testl $32768, %eax # imm = 0x8000 ; SSE2-NEXT: jne .LBB16_31 -; SSE2-NEXT: .LBB16_32: # %else30 +; SSE2-NEXT: # %bb.26: # %else28 +; SSE2-NEXT: testl $32768, %eax # imm = 0x8000 +; SSE2-NEXT: jne .LBB16_32 +; SSE2-NEXT: .LBB16_27: # %else30 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB16_1: # %cond.store +; SSE2-NEXT: .LBB16_28: # %cond.store ; SSE2-NEXT: movb %cl, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB16_4 -; SSE2-NEXT: .LBB16_3: # %cond.store1 +; SSE2-NEXT: je .LBB16_2 +; SSE2-NEXT: .LBB16_29: # %cond.store1 ; SSE2-NEXT: movb %ch, 1(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je .LBB16_6 -; SSE2-NEXT: .LBB16_5: # %cond.store3 +; SSE2-NEXT: je .LBB16_3 +; SSE2-NEXT: .LBB16_30: # %cond.store3 ; SSE2-NEXT: movl %ecx, %edx ; SSE2-NEXT: shrl $16, %edx ; SSE2-NEXT: movb %dl, 2(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne .LBB16_7 -; SSE2-NEXT: jmp .LBB16_8 -; SSE2-NEXT: .LBB16_29: # %cond.store27 +; SSE2-NEXT: jne .LBB16_4 +; SSE2-NEXT: jmp .LBB16_5 +; SSE2-NEXT: .LBB16_31: # %cond.store27 ; SSE2-NEXT: movb %cl, 14(%rdi) ; SSE2-NEXT: testl $32768, %eax # imm = 0x8000 -; SSE2-NEXT: je .LBB16_32 -; SSE2-NEXT: .LBB16_31: # %cond.store29 +; SSE2-NEXT: je .LBB16_27 +; SSE2-NEXT: .LBB16_32: # %cond.store29 ; SSE2-NEXT: movb %ch, 15(%rdi) ; SSE2-NEXT: retq ; @@ -6578,115 +6578,115 @@ define void @truncstore_v16i16_v16i8(<16 x i16> %x, ptr %p, <16 x i8> %mask) { ; SSE4-NEXT: pmovmskb %xmm3, %eax ; SSE4-NEXT: xorl $65535, %eax # imm = 0xFFFF ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB16_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB16_17 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB16_3 -; SSE4-NEXT: .LBB16_4: # %else2 +; SSE4-NEXT: jne .LBB16_18 +; SSE4-NEXT: .LBB16_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB16_5 -; SSE4-NEXT: .LBB16_6: # %else4 +; SSE4-NEXT: jne .LBB16_19 +; SSE4-NEXT: .LBB16_3: # %else4 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne .LBB16_7 -; SSE4-NEXT: .LBB16_8: # %else6 +; SSE4-NEXT: jne .LBB16_20 +; SSE4-NEXT: .LBB16_4: # %else6 ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: jne .LBB16_9 -; SSE4-NEXT: .LBB16_10: # %else8 +; SSE4-NEXT: jne .LBB16_21 +; SSE4-NEXT: .LBB16_5: # %else8 ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: jne .LBB16_11 -; SSE4-NEXT: .LBB16_12: # %else10 +; SSE4-NEXT: jne .LBB16_22 +; SSE4-NEXT: .LBB16_6: # %else10 ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: jne .LBB16_13 -; SSE4-NEXT: .LBB16_14: # %else12 +; SSE4-NEXT: jne .LBB16_23 +; SSE4-NEXT: .LBB16_7: # %else12 ; SSE4-NEXT: testb %al, %al -; SSE4-NEXT: js .LBB16_15 -; SSE4-NEXT: .LBB16_16: # %else14 +; SSE4-NEXT: js .LBB16_24 +; SSE4-NEXT: .LBB16_8: # %else14 ; SSE4-NEXT: testl $256, %eax # imm = 0x100 -; SSE4-NEXT: jne .LBB16_17 -; SSE4-NEXT: .LBB16_18: # %else16 +; SSE4-NEXT: jne .LBB16_25 +; SSE4-NEXT: .LBB16_9: # %else16 ; SSE4-NEXT: testl $512, %eax # imm = 0x200 -; SSE4-NEXT: jne .LBB16_19 -; SSE4-NEXT: .LBB16_20: # %else18 +; SSE4-NEXT: jne .LBB16_26 +; SSE4-NEXT: .LBB16_10: # %else18 ; SSE4-NEXT: testl $1024, %eax # imm = 0x400 -; SSE4-NEXT: jne .LBB16_21 -; SSE4-NEXT: .LBB16_22: # %else20 +; SSE4-NEXT: jne .LBB16_27 +; SSE4-NEXT: .LBB16_11: # %else20 ; SSE4-NEXT: testl $2048, %eax # imm = 0x800 -; SSE4-NEXT: jne .LBB16_23 -; SSE4-NEXT: .LBB16_24: # %else22 +; SSE4-NEXT: jne .LBB16_28 +; SSE4-NEXT: .LBB16_12: # %else22 ; SSE4-NEXT: testl $4096, %eax # imm = 0x1000 -; SSE4-NEXT: jne .LBB16_25 -; SSE4-NEXT: .LBB16_26: # %else24 +; SSE4-NEXT: jne .LBB16_29 +; SSE4-NEXT: .LBB16_13: # %else24 ; SSE4-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE4-NEXT: jne .LBB16_27 -; SSE4-NEXT: .LBB16_28: # %else26 +; SSE4-NEXT: jne .LBB16_30 +; SSE4-NEXT: .LBB16_14: # %else26 ; SSE4-NEXT: testl $16384, %eax # imm = 0x4000 -; SSE4-NEXT: jne .LBB16_29 -; SSE4-NEXT: .LBB16_30: # %else28 -; SSE4-NEXT: testl $32768, %eax # imm = 0x8000 ; SSE4-NEXT: jne .LBB16_31 -; SSE4-NEXT: .LBB16_32: # %else30 +; SSE4-NEXT: .LBB16_15: # %else28 +; SSE4-NEXT: testl $32768, %eax # imm = 0x8000 +; SSE4-NEXT: jne .LBB16_32 +; SSE4-NEXT: .LBB16_16: # %else30 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB16_1: # %cond.store +; SSE4-NEXT: .LBB16_17: # %cond.store ; SSE4-NEXT: pextrb $0, %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB16_4 -; SSE4-NEXT: .LBB16_3: # %cond.store1 +; SSE4-NEXT: je .LBB16_2 +; SSE4-NEXT: .LBB16_18: # %cond.store1 ; SSE4-NEXT: pextrb $1, %xmm0, 1(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB16_6 -; SSE4-NEXT: .LBB16_5: # %cond.store3 +; SSE4-NEXT: je .LBB16_3 +; SSE4-NEXT: .LBB16_19: # %cond.store3 ; SSE4-NEXT: pextrb $2, %xmm0, 2(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB16_8 -; SSE4-NEXT: .LBB16_7: # %cond.store5 +; SSE4-NEXT: je .LBB16_4 +; SSE4-NEXT: .LBB16_20: # %cond.store5 ; SSE4-NEXT: pextrb $3, %xmm0, 3(%rdi) ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: je .LBB16_10 -; SSE4-NEXT: .LBB16_9: # %cond.store7 +; SSE4-NEXT: je .LBB16_5 +; SSE4-NEXT: .LBB16_21: # %cond.store7 ; SSE4-NEXT: pextrb $4, %xmm0, 4(%rdi) ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: je .LBB16_12 -; SSE4-NEXT: .LBB16_11: # %cond.store9 +; SSE4-NEXT: je .LBB16_6 +; SSE4-NEXT: .LBB16_22: # %cond.store9 ; SSE4-NEXT: pextrb $5, %xmm0, 5(%rdi) ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: je .LBB16_14 -; SSE4-NEXT: .LBB16_13: # %cond.store11 +; SSE4-NEXT: je .LBB16_7 +; SSE4-NEXT: .LBB16_23: # %cond.store11 ; SSE4-NEXT: pextrb $6, %xmm0, 6(%rdi) ; SSE4-NEXT: testb %al, %al -; SSE4-NEXT: jns .LBB16_16 -; SSE4-NEXT: .LBB16_15: # %cond.store13 +; SSE4-NEXT: jns .LBB16_8 +; SSE4-NEXT: .LBB16_24: # %cond.store13 ; SSE4-NEXT: pextrb $7, %xmm0, 7(%rdi) ; SSE4-NEXT: testl $256, %eax # imm = 0x100 -; SSE4-NEXT: je .LBB16_18 -; SSE4-NEXT: .LBB16_17: # %cond.store15 +; SSE4-NEXT: je .LBB16_9 +; SSE4-NEXT: .LBB16_25: # %cond.store15 ; SSE4-NEXT: pextrb $8, %xmm0, 8(%rdi) ; SSE4-NEXT: testl $512, %eax # imm = 0x200 -; SSE4-NEXT: je .LBB16_20 -; SSE4-NEXT: .LBB16_19: # %cond.store17 +; SSE4-NEXT: je .LBB16_10 +; SSE4-NEXT: .LBB16_26: # %cond.store17 ; SSE4-NEXT: pextrb $9, %xmm0, 9(%rdi) ; SSE4-NEXT: testl $1024, %eax # imm = 0x400 -; SSE4-NEXT: je .LBB16_22 -; SSE4-NEXT: .LBB16_21: # %cond.store19 +; SSE4-NEXT: je .LBB16_11 +; SSE4-NEXT: .LBB16_27: # %cond.store19 ; SSE4-NEXT: pextrb $10, %xmm0, 10(%rdi) ; SSE4-NEXT: testl $2048, %eax # imm = 0x800 -; SSE4-NEXT: je .LBB16_24 -; SSE4-NEXT: .LBB16_23: # %cond.store21 +; SSE4-NEXT: je .LBB16_12 +; SSE4-NEXT: .LBB16_28: # %cond.store21 ; SSE4-NEXT: pextrb $11, %xmm0, 11(%rdi) ; SSE4-NEXT: testl $4096, %eax # imm = 0x1000 -; SSE4-NEXT: je .LBB16_26 -; SSE4-NEXT: .LBB16_25: # %cond.store23 +; SSE4-NEXT: je .LBB16_13 +; SSE4-NEXT: .LBB16_29: # %cond.store23 ; SSE4-NEXT: pextrb $12, %xmm0, 12(%rdi) ; SSE4-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE4-NEXT: je .LBB16_28 -; SSE4-NEXT: .LBB16_27: # %cond.store25 +; SSE4-NEXT: je .LBB16_14 +; SSE4-NEXT: .LBB16_30: # %cond.store25 ; SSE4-NEXT: pextrb $13, %xmm0, 13(%rdi) ; SSE4-NEXT: testl $16384, %eax # imm = 0x4000 -; SSE4-NEXT: je .LBB16_30 -; SSE4-NEXT: .LBB16_29: # %cond.store27 +; SSE4-NEXT: je .LBB16_15 +; SSE4-NEXT: .LBB16_31: # %cond.store27 ; SSE4-NEXT: pextrb $14, %xmm0, 14(%rdi) ; SSE4-NEXT: testl $32768, %eax # imm = 0x8000 -; SSE4-NEXT: je .LBB16_32 -; SSE4-NEXT: .LBB16_31: # %cond.store29 +; SSE4-NEXT: je .LBB16_16 +; SSE4-NEXT: .LBB16_32: # %cond.store29 ; SSE4-NEXT: pextrb $15, %xmm0, 15(%rdi) ; SSE4-NEXT: retq ; @@ -6700,116 +6700,116 @@ define void @truncstore_v16i16_v16i8(<16 x i16> %x, ptr %p, <16 x i8> %mask) { ; AVX1-NEXT: vpmovmskb %xmm1, %eax ; AVX1-NEXT: xorl $65535, %eax # imm = 0xFFFF ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne .LBB16_1 -; AVX1-NEXT: # %bb.2: # %else +; AVX1-NEXT: jne .LBB16_17 +; AVX1-NEXT: # %bb.1: # %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne .LBB16_3 -; AVX1-NEXT: .LBB16_4: # %else2 +; AVX1-NEXT: jne .LBB16_18 +; AVX1-NEXT: .LBB16_2: # %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne .LBB16_5 -; AVX1-NEXT: .LBB16_6: # %else4 +; AVX1-NEXT: jne .LBB16_19 +; AVX1-NEXT: .LBB16_3: # %else4 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne .LBB16_7 -; AVX1-NEXT: .LBB16_8: # %else6 +; AVX1-NEXT: jne .LBB16_20 +; AVX1-NEXT: .LBB16_4: # %else6 ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: jne .LBB16_9 -; AVX1-NEXT: .LBB16_10: # %else8 +; AVX1-NEXT: jne .LBB16_21 +; AVX1-NEXT: .LBB16_5: # %else8 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: jne .LBB16_11 -; AVX1-NEXT: .LBB16_12: # %else10 +; AVX1-NEXT: jne .LBB16_22 +; AVX1-NEXT: .LBB16_6: # %else10 ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: jne .LBB16_13 -; AVX1-NEXT: .LBB16_14: # %else12 +; AVX1-NEXT: jne .LBB16_23 +; AVX1-NEXT: .LBB16_7: # %else12 ; AVX1-NEXT: testb %al, %al -; AVX1-NEXT: js .LBB16_15 -; AVX1-NEXT: .LBB16_16: # %else14 +; AVX1-NEXT: js .LBB16_24 +; AVX1-NEXT: .LBB16_8: # %else14 ; AVX1-NEXT: testl $256, %eax # imm = 0x100 -; AVX1-NEXT: jne .LBB16_17 -; AVX1-NEXT: .LBB16_18: # %else16 +; AVX1-NEXT: jne .LBB16_25 +; AVX1-NEXT: .LBB16_9: # %else16 ; AVX1-NEXT: testl $512, %eax # imm = 0x200 -; AVX1-NEXT: jne .LBB16_19 -; AVX1-NEXT: .LBB16_20: # %else18 +; AVX1-NEXT: jne .LBB16_26 +; AVX1-NEXT: .LBB16_10: # %else18 ; AVX1-NEXT: testl $1024, %eax # imm = 0x400 -; AVX1-NEXT: jne .LBB16_21 -; AVX1-NEXT: .LBB16_22: # %else20 +; AVX1-NEXT: jne .LBB16_27 +; AVX1-NEXT: .LBB16_11: # %else20 ; AVX1-NEXT: testl $2048, %eax # imm = 0x800 -; AVX1-NEXT: jne .LBB16_23 -; AVX1-NEXT: .LBB16_24: # %else22 +; AVX1-NEXT: jne .LBB16_28 +; AVX1-NEXT: .LBB16_12: # %else22 ; AVX1-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX1-NEXT: jne .LBB16_25 -; AVX1-NEXT: .LBB16_26: # %else24 +; AVX1-NEXT: jne .LBB16_29 +; AVX1-NEXT: .LBB16_13: # %else24 ; AVX1-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX1-NEXT: jne .LBB16_27 -; AVX1-NEXT: .LBB16_28: # %else26 +; AVX1-NEXT: jne .LBB16_30 +; AVX1-NEXT: .LBB16_14: # %else26 ; AVX1-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX1-NEXT: jne .LBB16_29 -; AVX1-NEXT: .LBB16_30: # %else28 -; AVX1-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX1-NEXT: jne .LBB16_31 -; AVX1-NEXT: .LBB16_32: # %else30 +; AVX1-NEXT: .LBB16_15: # %else28 +; AVX1-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX1-NEXT: jne .LBB16_32 +; AVX1-NEXT: .LBB16_16: # %else30 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB16_1: # %cond.store +; AVX1-NEXT: .LBB16_17: # %cond.store ; AVX1-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je .LBB16_4 -; AVX1-NEXT: .LBB16_3: # %cond.store1 +; AVX1-NEXT: je .LBB16_2 +; AVX1-NEXT: .LBB16_18: # %cond.store1 ; AVX1-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je .LBB16_6 -; AVX1-NEXT: .LBB16_5: # %cond.store3 +; AVX1-NEXT: je .LBB16_3 +; AVX1-NEXT: .LBB16_19: # %cond.store3 ; AVX1-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB16_8 -; AVX1-NEXT: .LBB16_7: # %cond.store5 +; AVX1-NEXT: je .LBB16_4 +; AVX1-NEXT: .LBB16_20: # %cond.store5 ; AVX1-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: je .LBB16_10 -; AVX1-NEXT: .LBB16_9: # %cond.store7 +; AVX1-NEXT: je .LBB16_5 +; AVX1-NEXT: .LBB16_21: # %cond.store7 ; AVX1-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je .LBB16_12 -; AVX1-NEXT: .LBB16_11: # %cond.store9 +; AVX1-NEXT: je .LBB16_6 +; AVX1-NEXT: .LBB16_22: # %cond.store9 ; AVX1-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: je .LBB16_14 -; AVX1-NEXT: .LBB16_13: # %cond.store11 +; AVX1-NEXT: je .LBB16_7 +; AVX1-NEXT: .LBB16_23: # %cond.store11 ; AVX1-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX1-NEXT: testb %al, %al -; AVX1-NEXT: jns .LBB16_16 -; AVX1-NEXT: .LBB16_15: # %cond.store13 +; AVX1-NEXT: jns .LBB16_8 +; AVX1-NEXT: .LBB16_24: # %cond.store13 ; AVX1-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX1-NEXT: testl $256, %eax # imm = 0x100 -; AVX1-NEXT: je .LBB16_18 -; AVX1-NEXT: .LBB16_17: # %cond.store15 +; AVX1-NEXT: je .LBB16_9 +; AVX1-NEXT: .LBB16_25: # %cond.store15 ; AVX1-NEXT: vpextrb $8, %xmm0, 8(%rdi) ; AVX1-NEXT: testl $512, %eax # imm = 0x200 -; AVX1-NEXT: je .LBB16_20 -; AVX1-NEXT: .LBB16_19: # %cond.store17 +; AVX1-NEXT: je .LBB16_10 +; AVX1-NEXT: .LBB16_26: # %cond.store17 ; AVX1-NEXT: vpextrb $9, %xmm0, 9(%rdi) ; AVX1-NEXT: testl $1024, %eax # imm = 0x400 -; AVX1-NEXT: je .LBB16_22 -; AVX1-NEXT: .LBB16_21: # %cond.store19 +; AVX1-NEXT: je .LBB16_11 +; AVX1-NEXT: .LBB16_27: # %cond.store19 ; AVX1-NEXT: vpextrb $10, %xmm0, 10(%rdi) ; AVX1-NEXT: testl $2048, %eax # imm = 0x800 -; AVX1-NEXT: je .LBB16_24 -; AVX1-NEXT: .LBB16_23: # %cond.store21 +; AVX1-NEXT: je .LBB16_12 +; AVX1-NEXT: .LBB16_28: # %cond.store21 ; AVX1-NEXT: vpextrb $11, %xmm0, 11(%rdi) ; AVX1-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX1-NEXT: je .LBB16_26 -; AVX1-NEXT: .LBB16_25: # %cond.store23 +; AVX1-NEXT: je .LBB16_13 +; AVX1-NEXT: .LBB16_29: # %cond.store23 ; AVX1-NEXT: vpextrb $12, %xmm0, 12(%rdi) ; AVX1-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX1-NEXT: je .LBB16_28 -; AVX1-NEXT: .LBB16_27: # %cond.store25 +; AVX1-NEXT: je .LBB16_14 +; AVX1-NEXT: .LBB16_30: # %cond.store25 ; AVX1-NEXT: vpextrb $13, %xmm0, 13(%rdi) ; AVX1-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX1-NEXT: je .LBB16_30 -; AVX1-NEXT: .LBB16_29: # %cond.store27 +; AVX1-NEXT: je .LBB16_15 +; AVX1-NEXT: .LBB16_31: # %cond.store27 ; AVX1-NEXT: vpextrb $14, %xmm0, 14(%rdi) ; AVX1-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX1-NEXT: je .LBB16_32 -; AVX1-NEXT: .LBB16_31: # %cond.store29 +; AVX1-NEXT: je .LBB16_16 +; AVX1-NEXT: .LBB16_32: # %cond.store29 ; AVX1-NEXT: vpextrb $15, %xmm0, 15(%rdi) ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq @@ -6824,116 +6824,116 @@ define void @truncstore_v16i16_v16i8(<16 x i16> %x, ptr %p, <16 x i8> %mask) { ; AVX2-NEXT: vpmovmskb %xmm1, %eax ; AVX2-NEXT: xorl $65535, %eax # imm = 0xFFFF ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne .LBB16_1 -; AVX2-NEXT: # %bb.2: # %else +; AVX2-NEXT: jne .LBB16_17 +; AVX2-NEXT: # %bb.1: # %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne .LBB16_3 -; AVX2-NEXT: .LBB16_4: # %else2 +; AVX2-NEXT: jne .LBB16_18 +; AVX2-NEXT: .LBB16_2: # %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne .LBB16_5 -; AVX2-NEXT: .LBB16_6: # %else4 +; AVX2-NEXT: jne .LBB16_19 +; AVX2-NEXT: .LBB16_3: # %else4 ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: jne .LBB16_7 -; AVX2-NEXT: .LBB16_8: # %else6 +; AVX2-NEXT: jne .LBB16_20 +; AVX2-NEXT: .LBB16_4: # %else6 ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: jne .LBB16_9 -; AVX2-NEXT: .LBB16_10: # %else8 +; AVX2-NEXT: jne .LBB16_21 +; AVX2-NEXT: .LBB16_5: # %else8 ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: jne .LBB16_11 -; AVX2-NEXT: .LBB16_12: # %else10 +; AVX2-NEXT: jne .LBB16_22 +; AVX2-NEXT: .LBB16_6: # %else10 ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: jne .LBB16_13 -; AVX2-NEXT: .LBB16_14: # %else12 +; AVX2-NEXT: jne .LBB16_23 +; AVX2-NEXT: .LBB16_7: # %else12 ; AVX2-NEXT: testb %al, %al -; AVX2-NEXT: js .LBB16_15 -; AVX2-NEXT: .LBB16_16: # %else14 +; AVX2-NEXT: js .LBB16_24 +; AVX2-NEXT: .LBB16_8: # %else14 ; AVX2-NEXT: testl $256, %eax # imm = 0x100 -; AVX2-NEXT: jne .LBB16_17 -; AVX2-NEXT: .LBB16_18: # %else16 +; AVX2-NEXT: jne .LBB16_25 +; AVX2-NEXT: .LBB16_9: # %else16 ; AVX2-NEXT: testl $512, %eax # imm = 0x200 -; AVX2-NEXT: jne .LBB16_19 -; AVX2-NEXT: .LBB16_20: # %else18 +; AVX2-NEXT: jne .LBB16_26 +; AVX2-NEXT: .LBB16_10: # %else18 ; AVX2-NEXT: testl $1024, %eax # imm = 0x400 -; AVX2-NEXT: jne .LBB16_21 -; AVX2-NEXT: .LBB16_22: # %else20 +; AVX2-NEXT: jne .LBB16_27 +; AVX2-NEXT: .LBB16_11: # %else20 ; AVX2-NEXT: testl $2048, %eax # imm = 0x800 -; AVX2-NEXT: jne .LBB16_23 -; AVX2-NEXT: .LBB16_24: # %else22 +; AVX2-NEXT: jne .LBB16_28 +; AVX2-NEXT: .LBB16_12: # %else22 ; AVX2-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX2-NEXT: jne .LBB16_25 -; AVX2-NEXT: .LBB16_26: # %else24 +; AVX2-NEXT: jne .LBB16_29 +; AVX2-NEXT: .LBB16_13: # %else24 ; AVX2-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX2-NEXT: jne .LBB16_27 -; AVX2-NEXT: .LBB16_28: # %else26 +; AVX2-NEXT: jne .LBB16_30 +; AVX2-NEXT: .LBB16_14: # %else26 ; AVX2-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX2-NEXT: jne .LBB16_29 -; AVX2-NEXT: .LBB16_30: # %else28 -; AVX2-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX2-NEXT: jne .LBB16_31 -; AVX2-NEXT: .LBB16_32: # %else30 +; AVX2-NEXT: .LBB16_15: # %else28 +; AVX2-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX2-NEXT: jne .LBB16_32 +; AVX2-NEXT: .LBB16_16: # %else30 ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; AVX2-NEXT: .LBB16_1: # %cond.store +; AVX2-NEXT: .LBB16_17: # %cond.store ; AVX2-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je .LBB16_4 -; AVX2-NEXT: .LBB16_3: # %cond.store1 +; AVX2-NEXT: je .LBB16_2 +; AVX2-NEXT: .LBB16_18: # %cond.store1 ; AVX2-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je .LBB16_6 -; AVX2-NEXT: .LBB16_5: # %cond.store3 +; AVX2-NEXT: je .LBB16_3 +; AVX2-NEXT: .LBB16_19: # %cond.store3 ; AVX2-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je .LBB16_8 -; AVX2-NEXT: .LBB16_7: # %cond.store5 +; AVX2-NEXT: je .LBB16_4 +; AVX2-NEXT: .LBB16_20: # %cond.store5 ; AVX2-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: je .LBB16_10 -; AVX2-NEXT: .LBB16_9: # %cond.store7 +; AVX2-NEXT: je .LBB16_5 +; AVX2-NEXT: .LBB16_21: # %cond.store7 ; AVX2-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: je .LBB16_12 -; AVX2-NEXT: .LBB16_11: # %cond.store9 +; AVX2-NEXT: je .LBB16_6 +; AVX2-NEXT: .LBB16_22: # %cond.store9 ; AVX2-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: je .LBB16_14 -; AVX2-NEXT: .LBB16_13: # %cond.store11 +; AVX2-NEXT: je .LBB16_7 +; AVX2-NEXT: .LBB16_23: # %cond.store11 ; AVX2-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX2-NEXT: testb %al, %al -; AVX2-NEXT: jns .LBB16_16 -; AVX2-NEXT: .LBB16_15: # %cond.store13 +; AVX2-NEXT: jns .LBB16_8 +; AVX2-NEXT: .LBB16_24: # %cond.store13 ; AVX2-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX2-NEXT: testl $256, %eax # imm = 0x100 -; AVX2-NEXT: je .LBB16_18 -; AVX2-NEXT: .LBB16_17: # %cond.store15 +; AVX2-NEXT: je .LBB16_9 +; AVX2-NEXT: .LBB16_25: # %cond.store15 ; AVX2-NEXT: vpextrb $8, %xmm0, 8(%rdi) ; AVX2-NEXT: testl $512, %eax # imm = 0x200 -; AVX2-NEXT: je .LBB16_20 -; AVX2-NEXT: .LBB16_19: # %cond.store17 +; AVX2-NEXT: je .LBB16_10 +; AVX2-NEXT: .LBB16_26: # %cond.store17 ; AVX2-NEXT: vpextrb $9, %xmm0, 9(%rdi) ; AVX2-NEXT: testl $1024, %eax # imm = 0x400 -; AVX2-NEXT: je .LBB16_22 -; AVX2-NEXT: .LBB16_21: # %cond.store19 +; AVX2-NEXT: je .LBB16_11 +; AVX2-NEXT: .LBB16_27: # %cond.store19 ; AVX2-NEXT: vpextrb $10, %xmm0, 10(%rdi) ; AVX2-NEXT: testl $2048, %eax # imm = 0x800 -; AVX2-NEXT: je .LBB16_24 -; AVX2-NEXT: .LBB16_23: # %cond.store21 +; AVX2-NEXT: je .LBB16_12 +; AVX2-NEXT: .LBB16_28: # %cond.store21 ; AVX2-NEXT: vpextrb $11, %xmm0, 11(%rdi) ; AVX2-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX2-NEXT: je .LBB16_26 -; AVX2-NEXT: .LBB16_25: # %cond.store23 +; AVX2-NEXT: je .LBB16_13 +; AVX2-NEXT: .LBB16_29: # %cond.store23 ; AVX2-NEXT: vpextrb $12, %xmm0, 12(%rdi) ; AVX2-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX2-NEXT: je .LBB16_28 -; AVX2-NEXT: .LBB16_27: # %cond.store25 +; AVX2-NEXT: je .LBB16_14 +; AVX2-NEXT: .LBB16_30: # %cond.store25 ; AVX2-NEXT: vpextrb $13, %xmm0, 13(%rdi) ; AVX2-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX2-NEXT: je .LBB16_30 -; AVX2-NEXT: .LBB16_29: # %cond.store27 +; AVX2-NEXT: je .LBB16_15 +; AVX2-NEXT: .LBB16_31: # %cond.store27 ; AVX2-NEXT: vpextrb $14, %xmm0, 14(%rdi) ; AVX2-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX2-NEXT: je .LBB16_32 -; AVX2-NEXT: .LBB16_31: # %cond.store29 +; AVX2-NEXT: je .LBB16_16 +; AVX2-NEXT: .LBB16_32: # %cond.store29 ; AVX2-NEXT: vpextrb $15, %xmm0, 15(%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq @@ -6947,116 +6947,116 @@ define void @truncstore_v16i16_v16i8(<16 x i16> %x, ptr %p, <16 x i8> %mask) { ; AVX512F-NEXT: vpmovmskb %xmm1, %eax ; AVX512F-NEXT: xorl $65535, %eax # imm = 0xFFFF ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB16_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB16_17 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB16_3 -; AVX512F-NEXT: .LBB16_4: # %else2 +; AVX512F-NEXT: jne .LBB16_18 +; AVX512F-NEXT: .LBB16_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB16_5 -; AVX512F-NEXT: .LBB16_6: # %else4 +; AVX512F-NEXT: jne .LBB16_19 +; AVX512F-NEXT: .LBB16_3: # %else4 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne .LBB16_7 -; AVX512F-NEXT: .LBB16_8: # %else6 +; AVX512F-NEXT: jne .LBB16_20 +; AVX512F-NEXT: .LBB16_4: # %else6 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne .LBB16_9 -; AVX512F-NEXT: .LBB16_10: # %else8 +; AVX512F-NEXT: jne .LBB16_21 +; AVX512F-NEXT: .LBB16_5: # %else8 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne .LBB16_11 -; AVX512F-NEXT: .LBB16_12: # %else10 +; AVX512F-NEXT: jne .LBB16_22 +; AVX512F-NEXT: .LBB16_6: # %else10 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne .LBB16_13 -; AVX512F-NEXT: .LBB16_14: # %else12 +; AVX512F-NEXT: jne .LBB16_23 +; AVX512F-NEXT: .LBB16_7: # %else12 ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: js .LBB16_15 -; AVX512F-NEXT: .LBB16_16: # %else14 +; AVX512F-NEXT: js .LBB16_24 +; AVX512F-NEXT: .LBB16_8: # %else14 ; AVX512F-NEXT: testl $256, %eax # imm = 0x100 -; AVX512F-NEXT: jne .LBB16_17 -; AVX512F-NEXT: .LBB16_18: # %else16 +; AVX512F-NEXT: jne .LBB16_25 +; AVX512F-NEXT: .LBB16_9: # %else16 ; AVX512F-NEXT: testl $512, %eax # imm = 0x200 -; AVX512F-NEXT: jne .LBB16_19 -; AVX512F-NEXT: .LBB16_20: # %else18 +; AVX512F-NEXT: jne .LBB16_26 +; AVX512F-NEXT: .LBB16_10: # %else18 ; AVX512F-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512F-NEXT: jne .LBB16_21 -; AVX512F-NEXT: .LBB16_22: # %else20 +; AVX512F-NEXT: jne .LBB16_27 +; AVX512F-NEXT: .LBB16_11: # %else20 ; AVX512F-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512F-NEXT: jne .LBB16_23 -; AVX512F-NEXT: .LBB16_24: # %else22 +; AVX512F-NEXT: jne .LBB16_28 +; AVX512F-NEXT: .LBB16_12: # %else22 ; AVX512F-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512F-NEXT: jne .LBB16_25 -; AVX512F-NEXT: .LBB16_26: # %else24 +; AVX512F-NEXT: jne .LBB16_29 +; AVX512F-NEXT: .LBB16_13: # %else24 ; AVX512F-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512F-NEXT: jne .LBB16_27 -; AVX512F-NEXT: .LBB16_28: # %else26 +; AVX512F-NEXT: jne .LBB16_30 +; AVX512F-NEXT: .LBB16_14: # %else26 ; AVX512F-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512F-NEXT: jne .LBB16_29 -; AVX512F-NEXT: .LBB16_30: # %else28 -; AVX512F-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX512F-NEXT: jne .LBB16_31 -; AVX512F-NEXT: .LBB16_32: # %else30 +; AVX512F-NEXT: .LBB16_15: # %else28 +; AVX512F-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX512F-NEXT: jne .LBB16_32 +; AVX512F-NEXT: .LBB16_16: # %else30 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB16_1: # %cond.store +; AVX512F-NEXT: .LBB16_17: # %cond.store ; AVX512F-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB16_4 -; AVX512F-NEXT: .LBB16_3: # %cond.store1 +; AVX512F-NEXT: je .LBB16_2 +; AVX512F-NEXT: .LBB16_18: # %cond.store1 ; AVX512F-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB16_6 -; AVX512F-NEXT: .LBB16_5: # %cond.store3 +; AVX512F-NEXT: je .LBB16_3 +; AVX512F-NEXT: .LBB16_19: # %cond.store3 ; AVX512F-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB16_8 -; AVX512F-NEXT: .LBB16_7: # %cond.store5 +; AVX512F-NEXT: je .LBB16_4 +; AVX512F-NEXT: .LBB16_20: # %cond.store5 ; AVX512F-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je .LBB16_10 -; AVX512F-NEXT: .LBB16_9: # %cond.store7 +; AVX512F-NEXT: je .LBB16_5 +; AVX512F-NEXT: .LBB16_21: # %cond.store7 ; AVX512F-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je .LBB16_12 -; AVX512F-NEXT: .LBB16_11: # %cond.store9 +; AVX512F-NEXT: je .LBB16_6 +; AVX512F-NEXT: .LBB16_22: # %cond.store9 ; AVX512F-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je .LBB16_14 -; AVX512F-NEXT: .LBB16_13: # %cond.store11 +; AVX512F-NEXT: je .LBB16_7 +; AVX512F-NEXT: .LBB16_23: # %cond.store11 ; AVX512F-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: jns .LBB16_16 -; AVX512F-NEXT: .LBB16_15: # %cond.store13 +; AVX512F-NEXT: jns .LBB16_8 +; AVX512F-NEXT: .LBB16_24: # %cond.store13 ; AVX512F-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX512F-NEXT: testl $256, %eax # imm = 0x100 -; AVX512F-NEXT: je .LBB16_18 -; AVX512F-NEXT: .LBB16_17: # %cond.store15 +; AVX512F-NEXT: je .LBB16_9 +; AVX512F-NEXT: .LBB16_25: # %cond.store15 ; AVX512F-NEXT: vpextrb $8, %xmm0, 8(%rdi) ; AVX512F-NEXT: testl $512, %eax # imm = 0x200 -; AVX512F-NEXT: je .LBB16_20 -; AVX512F-NEXT: .LBB16_19: # %cond.store17 +; AVX512F-NEXT: je .LBB16_10 +; AVX512F-NEXT: .LBB16_26: # %cond.store17 ; AVX512F-NEXT: vpextrb $9, %xmm0, 9(%rdi) ; AVX512F-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512F-NEXT: je .LBB16_22 -; AVX512F-NEXT: .LBB16_21: # %cond.store19 +; AVX512F-NEXT: je .LBB16_11 +; AVX512F-NEXT: .LBB16_27: # %cond.store19 ; AVX512F-NEXT: vpextrb $10, %xmm0, 10(%rdi) ; AVX512F-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512F-NEXT: je .LBB16_24 -; AVX512F-NEXT: .LBB16_23: # %cond.store21 +; AVX512F-NEXT: je .LBB16_12 +; AVX512F-NEXT: .LBB16_28: # %cond.store21 ; AVX512F-NEXT: vpextrb $11, %xmm0, 11(%rdi) ; AVX512F-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512F-NEXT: je .LBB16_26 -; AVX512F-NEXT: .LBB16_25: # %cond.store23 +; AVX512F-NEXT: je .LBB16_13 +; AVX512F-NEXT: .LBB16_29: # %cond.store23 ; AVX512F-NEXT: vpextrb $12, %xmm0, 12(%rdi) ; AVX512F-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512F-NEXT: je .LBB16_28 -; AVX512F-NEXT: .LBB16_27: # %cond.store25 +; AVX512F-NEXT: je .LBB16_14 +; AVX512F-NEXT: .LBB16_30: # %cond.store25 ; AVX512F-NEXT: vpextrb $13, %xmm0, 13(%rdi) ; AVX512F-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512F-NEXT: je .LBB16_30 -; AVX512F-NEXT: .LBB16_29: # %cond.store27 +; AVX512F-NEXT: je .LBB16_15 +; AVX512F-NEXT: .LBB16_31: # %cond.store27 ; AVX512F-NEXT: vpextrb $14, %xmm0, 14(%rdi) ; AVX512F-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX512F-NEXT: je .LBB16_32 -; AVX512F-NEXT: .LBB16_31: # %cond.store29 +; AVX512F-NEXT: je .LBB16_16 +; AVX512F-NEXT: .LBB16_32: # %cond.store29 ; AVX512F-NEXT: vpextrb $15, %xmm0, 15(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -7070,116 +7070,116 @@ define void @truncstore_v16i16_v16i8(<16 x i16> %x, ptr %p, <16 x i8> %mask) { ; AVX512FVL-NEXT: vpmovmskb %xmm1, %eax ; AVX512FVL-NEXT: xorl $65535, %eax # imm = 0xFFFF ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB16_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB16_17 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB16_3 -; AVX512FVL-NEXT: .LBB16_4: # %else2 +; AVX512FVL-NEXT: jne .LBB16_18 +; AVX512FVL-NEXT: .LBB16_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB16_5 -; AVX512FVL-NEXT: .LBB16_6: # %else4 +; AVX512FVL-NEXT: jne .LBB16_19 +; AVX512FVL-NEXT: .LBB16_3: # %else4 ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: jne .LBB16_7 -; AVX512FVL-NEXT: .LBB16_8: # %else6 +; AVX512FVL-NEXT: jne .LBB16_20 +; AVX512FVL-NEXT: .LBB16_4: # %else6 ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: jne .LBB16_9 -; AVX512FVL-NEXT: .LBB16_10: # %else8 +; AVX512FVL-NEXT: jne .LBB16_21 +; AVX512FVL-NEXT: .LBB16_5: # %else8 ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: jne .LBB16_11 -; AVX512FVL-NEXT: .LBB16_12: # %else10 +; AVX512FVL-NEXT: jne .LBB16_22 +; AVX512FVL-NEXT: .LBB16_6: # %else10 ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: jne .LBB16_13 -; AVX512FVL-NEXT: .LBB16_14: # %else12 +; AVX512FVL-NEXT: jne .LBB16_23 +; AVX512FVL-NEXT: .LBB16_7: # %else12 ; AVX512FVL-NEXT: testb %al, %al -; AVX512FVL-NEXT: js .LBB16_15 -; AVX512FVL-NEXT: .LBB16_16: # %else14 +; AVX512FVL-NEXT: js .LBB16_24 +; AVX512FVL-NEXT: .LBB16_8: # %else14 ; AVX512FVL-NEXT: testl $256, %eax # imm = 0x100 -; AVX512FVL-NEXT: jne .LBB16_17 -; AVX512FVL-NEXT: .LBB16_18: # %else16 +; AVX512FVL-NEXT: jne .LBB16_25 +; AVX512FVL-NEXT: .LBB16_9: # %else16 ; AVX512FVL-NEXT: testl $512, %eax # imm = 0x200 -; AVX512FVL-NEXT: jne .LBB16_19 -; AVX512FVL-NEXT: .LBB16_20: # %else18 +; AVX512FVL-NEXT: jne .LBB16_26 +; AVX512FVL-NEXT: .LBB16_10: # %else18 ; AVX512FVL-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512FVL-NEXT: jne .LBB16_21 -; AVX512FVL-NEXT: .LBB16_22: # %else20 +; AVX512FVL-NEXT: jne .LBB16_27 +; AVX512FVL-NEXT: .LBB16_11: # %else20 ; AVX512FVL-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512FVL-NEXT: jne .LBB16_23 -; AVX512FVL-NEXT: .LBB16_24: # %else22 +; AVX512FVL-NEXT: jne .LBB16_28 +; AVX512FVL-NEXT: .LBB16_12: # %else22 ; AVX512FVL-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512FVL-NEXT: jne .LBB16_25 -; AVX512FVL-NEXT: .LBB16_26: # %else24 +; AVX512FVL-NEXT: jne .LBB16_29 +; AVX512FVL-NEXT: .LBB16_13: # %else24 ; AVX512FVL-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512FVL-NEXT: jne .LBB16_27 -; AVX512FVL-NEXT: .LBB16_28: # %else26 +; AVX512FVL-NEXT: jne .LBB16_30 +; AVX512FVL-NEXT: .LBB16_14: # %else26 ; AVX512FVL-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512FVL-NEXT: jne .LBB16_29 -; AVX512FVL-NEXT: .LBB16_30: # %else28 -; AVX512FVL-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX512FVL-NEXT: jne .LBB16_31 -; AVX512FVL-NEXT: .LBB16_32: # %else30 +; AVX512FVL-NEXT: .LBB16_15: # %else28 +; AVX512FVL-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX512FVL-NEXT: jne .LBB16_32 +; AVX512FVL-NEXT: .LBB16_16: # %else30 ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB16_1: # %cond.store +; AVX512FVL-NEXT: .LBB16_17: # %cond.store ; AVX512FVL-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB16_4 -; AVX512FVL-NEXT: .LBB16_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB16_2 +; AVX512FVL-NEXT: .LBB16_18: # %cond.store1 ; AVX512FVL-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB16_6 -; AVX512FVL-NEXT: .LBB16_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB16_3 +; AVX512FVL-NEXT: .LBB16_19: # %cond.store3 ; AVX512FVL-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB16_8 -; AVX512FVL-NEXT: .LBB16_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB16_4 +; AVX512FVL-NEXT: .LBB16_20: # %cond.store5 ; AVX512FVL-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: je .LBB16_10 -; AVX512FVL-NEXT: .LBB16_9: # %cond.store7 +; AVX512FVL-NEXT: je .LBB16_5 +; AVX512FVL-NEXT: .LBB16_21: # %cond.store7 ; AVX512FVL-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: je .LBB16_12 -; AVX512FVL-NEXT: .LBB16_11: # %cond.store9 +; AVX512FVL-NEXT: je .LBB16_6 +; AVX512FVL-NEXT: .LBB16_22: # %cond.store9 ; AVX512FVL-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: je .LBB16_14 -; AVX512FVL-NEXT: .LBB16_13: # %cond.store11 +; AVX512FVL-NEXT: je .LBB16_7 +; AVX512FVL-NEXT: .LBB16_23: # %cond.store11 ; AVX512FVL-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX512FVL-NEXT: testb %al, %al -; AVX512FVL-NEXT: jns .LBB16_16 -; AVX512FVL-NEXT: .LBB16_15: # %cond.store13 +; AVX512FVL-NEXT: jns .LBB16_8 +; AVX512FVL-NEXT: .LBB16_24: # %cond.store13 ; AVX512FVL-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX512FVL-NEXT: testl $256, %eax # imm = 0x100 -; AVX512FVL-NEXT: je .LBB16_18 -; AVX512FVL-NEXT: .LBB16_17: # %cond.store15 +; AVX512FVL-NEXT: je .LBB16_9 +; AVX512FVL-NEXT: .LBB16_25: # %cond.store15 ; AVX512FVL-NEXT: vpextrb $8, %xmm0, 8(%rdi) ; AVX512FVL-NEXT: testl $512, %eax # imm = 0x200 -; AVX512FVL-NEXT: je .LBB16_20 -; AVX512FVL-NEXT: .LBB16_19: # %cond.store17 +; AVX512FVL-NEXT: je .LBB16_10 +; AVX512FVL-NEXT: .LBB16_26: # %cond.store17 ; AVX512FVL-NEXT: vpextrb $9, %xmm0, 9(%rdi) ; AVX512FVL-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512FVL-NEXT: je .LBB16_22 -; AVX512FVL-NEXT: .LBB16_21: # %cond.store19 +; AVX512FVL-NEXT: je .LBB16_11 +; AVX512FVL-NEXT: .LBB16_27: # %cond.store19 ; AVX512FVL-NEXT: vpextrb $10, %xmm0, 10(%rdi) ; AVX512FVL-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512FVL-NEXT: je .LBB16_24 -; AVX512FVL-NEXT: .LBB16_23: # %cond.store21 +; AVX512FVL-NEXT: je .LBB16_12 +; AVX512FVL-NEXT: .LBB16_28: # %cond.store21 ; AVX512FVL-NEXT: vpextrb $11, %xmm0, 11(%rdi) ; AVX512FVL-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512FVL-NEXT: je .LBB16_26 -; AVX512FVL-NEXT: .LBB16_25: # %cond.store23 +; AVX512FVL-NEXT: je .LBB16_13 +; AVX512FVL-NEXT: .LBB16_29: # %cond.store23 ; AVX512FVL-NEXT: vpextrb $12, %xmm0, 12(%rdi) ; AVX512FVL-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512FVL-NEXT: je .LBB16_28 -; AVX512FVL-NEXT: .LBB16_27: # %cond.store25 +; AVX512FVL-NEXT: je .LBB16_14 +; AVX512FVL-NEXT: .LBB16_30: # %cond.store25 ; AVX512FVL-NEXT: vpextrb $13, %xmm0, 13(%rdi) ; AVX512FVL-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512FVL-NEXT: je .LBB16_30 -; AVX512FVL-NEXT: .LBB16_29: # %cond.store27 +; AVX512FVL-NEXT: je .LBB16_15 +; AVX512FVL-NEXT: .LBB16_31: # %cond.store27 ; AVX512FVL-NEXT: vpextrb $14, %xmm0, 14(%rdi) ; AVX512FVL-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX512FVL-NEXT: je .LBB16_32 -; AVX512FVL-NEXT: .LBB16_31: # %cond.store29 +; AVX512FVL-NEXT: je .LBB16_16 +; AVX512FVL-NEXT: .LBB16_32: # %cond.store29 ; AVX512FVL-NEXT: vpextrb $15, %xmm0, 15(%rdi) ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq @@ -7219,59 +7219,59 @@ define void @truncstore_v8i16_v8i8(<8 x i16> %x, ptr %p, <8 x i16> %mask) { ; SSE2-NEXT: notl %eax ; SSE2-NEXT: testb $1, %al ; SSE2-NEXT: movd %xmm0, %ecx -; SSE2-NEXT: jne .LBB17_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB17_12 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne .LBB17_3 -; SSE2-NEXT: .LBB17_4: # %else2 +; SSE2-NEXT: jne .LBB17_13 +; SSE2-NEXT: .LBB17_2: # %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne .LBB17_5 -; SSE2-NEXT: .LBB17_6: # %else4 +; SSE2-NEXT: jne .LBB17_14 +; SSE2-NEXT: .LBB17_3: # %else4 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je .LBB17_8 -; SSE2-NEXT: .LBB17_7: # %cond.store5 +; SSE2-NEXT: je .LBB17_5 +; SSE2-NEXT: .LBB17_4: # %cond.store5 ; SSE2-NEXT: shrl $24, %ecx ; SSE2-NEXT: movb %cl, 3(%rdi) -; SSE2-NEXT: .LBB17_8: # %else6 +; SSE2-NEXT: .LBB17_5: # %else6 ; SSE2-NEXT: testb $16, %al ; SSE2-NEXT: pextrw $2, %xmm0, %ecx -; SSE2-NEXT: je .LBB17_10 -; SSE2-NEXT: # %bb.9: # %cond.store7 +; SSE2-NEXT: je .LBB17_7 +; SSE2-NEXT: # %bb.6: # %cond.store7 ; SSE2-NEXT: movb %cl, 4(%rdi) -; SSE2-NEXT: .LBB17_10: # %else8 +; SSE2-NEXT: .LBB17_7: # %else8 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je .LBB17_12 -; SSE2-NEXT: # %bb.11: # %cond.store9 +; SSE2-NEXT: je .LBB17_9 +; SSE2-NEXT: # %bb.8: # %cond.store9 ; SSE2-NEXT: movb %ch, 5(%rdi) -; SSE2-NEXT: .LBB17_12: # %else10 +; SSE2-NEXT: .LBB17_9: # %else10 ; SSE2-NEXT: testb $64, %al ; SSE2-NEXT: pextrw $3, %xmm0, %ecx -; SSE2-NEXT: jne .LBB17_13 -; SSE2-NEXT: # %bb.14: # %else12 -; SSE2-NEXT: testb $-128, %al ; SSE2-NEXT: jne .LBB17_15 -; SSE2-NEXT: .LBB17_16: # %else14 +; SSE2-NEXT: # %bb.10: # %else12 +; SSE2-NEXT: testb $-128, %al +; SSE2-NEXT: jne .LBB17_16 +; SSE2-NEXT: .LBB17_11: # %else14 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB17_1: # %cond.store +; SSE2-NEXT: .LBB17_12: # %cond.store ; SSE2-NEXT: movb %cl, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB17_4 -; SSE2-NEXT: .LBB17_3: # %cond.store1 +; SSE2-NEXT: je .LBB17_2 +; SSE2-NEXT: .LBB17_13: # %cond.store1 ; SSE2-NEXT: movb %ch, 1(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je .LBB17_6 -; SSE2-NEXT: .LBB17_5: # %cond.store3 +; SSE2-NEXT: je .LBB17_3 +; SSE2-NEXT: .LBB17_14: # %cond.store3 ; SSE2-NEXT: movl %ecx, %edx ; SSE2-NEXT: shrl $16, %edx ; SSE2-NEXT: movb %dl, 2(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne .LBB17_7 -; SSE2-NEXT: jmp .LBB17_8 -; SSE2-NEXT: .LBB17_13: # %cond.store11 +; SSE2-NEXT: jne .LBB17_4 +; SSE2-NEXT: jmp .LBB17_5 +; SSE2-NEXT: .LBB17_15: # %cond.store11 ; SSE2-NEXT: movb %cl, 6(%rdi) ; SSE2-NEXT: testb $-128, %al -; SSE2-NEXT: je .LBB17_16 -; SSE2-NEXT: .LBB17_15: # %cond.store13 +; SSE2-NEXT: je .LBB17_11 +; SSE2-NEXT: .LBB17_16: # %cond.store13 ; SSE2-NEXT: movb %ch, 7(%rdi) ; SSE2-NEXT: retq ; @@ -7284,59 +7284,59 @@ define void @truncstore_v8i16_v8i8(<8 x i16> %x, ptr %p, <8 x i16> %mask) { ; SSE4-NEXT: pmovmskb %xmm2, %eax ; SSE4-NEXT: notl %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB17_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB17_9 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB17_3 -; SSE4-NEXT: .LBB17_4: # %else2 +; SSE4-NEXT: jne .LBB17_10 +; SSE4-NEXT: .LBB17_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB17_5 -; SSE4-NEXT: .LBB17_6: # %else4 +; SSE4-NEXT: jne .LBB17_11 +; SSE4-NEXT: .LBB17_3: # %else4 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne .LBB17_7 -; SSE4-NEXT: .LBB17_8: # %else6 +; SSE4-NEXT: jne .LBB17_12 +; SSE4-NEXT: .LBB17_4: # %else6 ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: jne .LBB17_9 -; SSE4-NEXT: .LBB17_10: # %else8 +; SSE4-NEXT: jne .LBB17_13 +; SSE4-NEXT: .LBB17_5: # %else8 ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: jne .LBB17_11 -; SSE4-NEXT: .LBB17_12: # %else10 +; SSE4-NEXT: jne .LBB17_14 +; SSE4-NEXT: .LBB17_6: # %else10 ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: jne .LBB17_13 -; SSE4-NEXT: .LBB17_14: # %else12 -; SSE4-NEXT: testb $-128, %al ; SSE4-NEXT: jne .LBB17_15 -; SSE4-NEXT: .LBB17_16: # %else14 +; SSE4-NEXT: .LBB17_7: # %else12 +; SSE4-NEXT: testb $-128, %al +; SSE4-NEXT: jne .LBB17_16 +; SSE4-NEXT: .LBB17_8: # %else14 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB17_1: # %cond.store +; SSE4-NEXT: .LBB17_9: # %cond.store ; SSE4-NEXT: pextrb $0, %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB17_4 -; SSE4-NEXT: .LBB17_3: # %cond.store1 +; SSE4-NEXT: je .LBB17_2 +; SSE4-NEXT: .LBB17_10: # %cond.store1 ; SSE4-NEXT: pextrb $1, %xmm0, 1(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB17_6 -; SSE4-NEXT: .LBB17_5: # %cond.store3 +; SSE4-NEXT: je .LBB17_3 +; SSE4-NEXT: .LBB17_11: # %cond.store3 ; SSE4-NEXT: pextrb $2, %xmm0, 2(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB17_8 -; SSE4-NEXT: .LBB17_7: # %cond.store5 +; SSE4-NEXT: je .LBB17_4 +; SSE4-NEXT: .LBB17_12: # %cond.store5 ; SSE4-NEXT: pextrb $3, %xmm0, 3(%rdi) ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: je .LBB17_10 -; SSE4-NEXT: .LBB17_9: # %cond.store7 +; SSE4-NEXT: je .LBB17_5 +; SSE4-NEXT: .LBB17_13: # %cond.store7 ; SSE4-NEXT: pextrb $4, %xmm0, 4(%rdi) ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: je .LBB17_12 -; SSE4-NEXT: .LBB17_11: # %cond.store9 +; SSE4-NEXT: je .LBB17_6 +; SSE4-NEXT: .LBB17_14: # %cond.store9 ; SSE4-NEXT: pextrb $5, %xmm0, 5(%rdi) ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: je .LBB17_14 -; SSE4-NEXT: .LBB17_13: # %cond.store11 +; SSE4-NEXT: je .LBB17_7 +; SSE4-NEXT: .LBB17_15: # %cond.store11 ; SSE4-NEXT: pextrb $6, %xmm0, 6(%rdi) ; SSE4-NEXT: testb $-128, %al -; SSE4-NEXT: je .LBB17_16 -; SSE4-NEXT: .LBB17_15: # %cond.store13 +; SSE4-NEXT: je .LBB17_8 +; SSE4-NEXT: .LBB17_16: # %cond.store13 ; SSE4-NEXT: pextrb $7, %xmm0, 7(%rdi) ; SSE4-NEXT: retq ; @@ -7349,59 +7349,59 @@ define void @truncstore_v8i16_v8i8(<8 x i16> %x, ptr %p, <8 x i16> %mask) { ; AVX-NEXT: vpmovmskb %xmm1, %eax ; AVX-NEXT: notl %eax ; AVX-NEXT: testb $1, %al -; AVX-NEXT: jne .LBB17_1 -; AVX-NEXT: # %bb.2: # %else +; AVX-NEXT: jne .LBB17_9 +; AVX-NEXT: # %bb.1: # %else ; AVX-NEXT: testb $2, %al -; AVX-NEXT: jne .LBB17_3 -; AVX-NEXT: .LBB17_4: # %else2 +; AVX-NEXT: jne .LBB17_10 +; AVX-NEXT: .LBB17_2: # %else2 ; AVX-NEXT: testb $4, %al -; AVX-NEXT: jne .LBB17_5 -; AVX-NEXT: .LBB17_6: # %else4 +; AVX-NEXT: jne .LBB17_11 +; AVX-NEXT: .LBB17_3: # %else4 ; AVX-NEXT: testb $8, %al -; AVX-NEXT: jne .LBB17_7 -; AVX-NEXT: .LBB17_8: # %else6 +; AVX-NEXT: jne .LBB17_12 +; AVX-NEXT: .LBB17_4: # %else6 ; AVX-NEXT: testb $16, %al -; AVX-NEXT: jne .LBB17_9 -; AVX-NEXT: .LBB17_10: # %else8 +; AVX-NEXT: jne .LBB17_13 +; AVX-NEXT: .LBB17_5: # %else8 ; AVX-NEXT: testb $32, %al -; AVX-NEXT: jne .LBB17_11 -; AVX-NEXT: .LBB17_12: # %else10 +; AVX-NEXT: jne .LBB17_14 +; AVX-NEXT: .LBB17_6: # %else10 ; AVX-NEXT: testb $64, %al -; AVX-NEXT: jne .LBB17_13 -; AVX-NEXT: .LBB17_14: # %else12 -; AVX-NEXT: testb $-128, %al ; AVX-NEXT: jne .LBB17_15 -; AVX-NEXT: .LBB17_16: # %else14 +; AVX-NEXT: .LBB17_7: # %else12 +; AVX-NEXT: testb $-128, %al +; AVX-NEXT: jne .LBB17_16 +; AVX-NEXT: .LBB17_8: # %else14 ; AVX-NEXT: retq -; AVX-NEXT: .LBB17_1: # %cond.store +; AVX-NEXT: .LBB17_9: # %cond.store ; AVX-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX-NEXT: testb $2, %al -; AVX-NEXT: je .LBB17_4 -; AVX-NEXT: .LBB17_3: # %cond.store1 +; AVX-NEXT: je .LBB17_2 +; AVX-NEXT: .LBB17_10: # %cond.store1 ; AVX-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX-NEXT: testb $4, %al -; AVX-NEXT: je .LBB17_6 -; AVX-NEXT: .LBB17_5: # %cond.store3 +; AVX-NEXT: je .LBB17_3 +; AVX-NEXT: .LBB17_11: # %cond.store3 ; AVX-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX-NEXT: testb $8, %al -; AVX-NEXT: je .LBB17_8 -; AVX-NEXT: .LBB17_7: # %cond.store5 +; AVX-NEXT: je .LBB17_4 +; AVX-NEXT: .LBB17_12: # %cond.store5 ; AVX-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX-NEXT: testb $16, %al -; AVX-NEXT: je .LBB17_10 -; AVX-NEXT: .LBB17_9: # %cond.store7 +; AVX-NEXT: je .LBB17_5 +; AVX-NEXT: .LBB17_13: # %cond.store7 ; AVX-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX-NEXT: testb $32, %al -; AVX-NEXT: je .LBB17_12 -; AVX-NEXT: .LBB17_11: # %cond.store9 +; AVX-NEXT: je .LBB17_6 +; AVX-NEXT: .LBB17_14: # %cond.store9 ; AVX-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX-NEXT: testb $64, %al -; AVX-NEXT: je .LBB17_14 -; AVX-NEXT: .LBB17_13: # %cond.store11 +; AVX-NEXT: je .LBB17_7 +; AVX-NEXT: .LBB17_15: # %cond.store11 ; AVX-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX-NEXT: testb $-128, %al -; AVX-NEXT: je .LBB17_16 -; AVX-NEXT: .LBB17_15: # %cond.store13 +; AVX-NEXT: je .LBB17_8 +; AVX-NEXT: .LBB17_16: # %cond.store13 ; AVX-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX-NEXT: retq ; @@ -7415,60 +7415,60 @@ define void @truncstore_v8i16_v8i8(<8 x i16> %x, ptr %p, <8 x i16> %mask) { ; AVX512F-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u] ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB17_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB17_9 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB17_3 -; AVX512F-NEXT: .LBB17_4: # %else2 +; AVX512F-NEXT: jne .LBB17_10 +; AVX512F-NEXT: .LBB17_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB17_5 -; AVX512F-NEXT: .LBB17_6: # %else4 +; AVX512F-NEXT: jne .LBB17_11 +; AVX512F-NEXT: .LBB17_3: # %else4 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne .LBB17_7 -; AVX512F-NEXT: .LBB17_8: # %else6 +; AVX512F-NEXT: jne .LBB17_12 +; AVX512F-NEXT: .LBB17_4: # %else6 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne .LBB17_9 -; AVX512F-NEXT: .LBB17_10: # %else8 +; AVX512F-NEXT: jne .LBB17_13 +; AVX512F-NEXT: .LBB17_5: # %else8 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne .LBB17_11 -; AVX512F-NEXT: .LBB17_12: # %else10 +; AVX512F-NEXT: jne .LBB17_14 +; AVX512F-NEXT: .LBB17_6: # %else10 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne .LBB17_13 -; AVX512F-NEXT: .LBB17_14: # %else12 -; AVX512F-NEXT: testb $-128, %al ; AVX512F-NEXT: jne .LBB17_15 -; AVX512F-NEXT: .LBB17_16: # %else14 +; AVX512F-NEXT: .LBB17_7: # %else12 +; AVX512F-NEXT: testb $-128, %al +; AVX512F-NEXT: jne .LBB17_16 +; AVX512F-NEXT: .LBB17_8: # %else14 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB17_1: # %cond.store +; AVX512F-NEXT: .LBB17_9: # %cond.store ; AVX512F-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB17_4 -; AVX512F-NEXT: .LBB17_3: # %cond.store1 +; AVX512F-NEXT: je .LBB17_2 +; AVX512F-NEXT: .LBB17_10: # %cond.store1 ; AVX512F-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB17_6 -; AVX512F-NEXT: .LBB17_5: # %cond.store3 +; AVX512F-NEXT: je .LBB17_3 +; AVX512F-NEXT: .LBB17_11: # %cond.store3 ; AVX512F-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB17_8 -; AVX512F-NEXT: .LBB17_7: # %cond.store5 +; AVX512F-NEXT: je .LBB17_4 +; AVX512F-NEXT: .LBB17_12: # %cond.store5 ; AVX512F-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je .LBB17_10 -; AVX512F-NEXT: .LBB17_9: # %cond.store7 +; AVX512F-NEXT: je .LBB17_5 +; AVX512F-NEXT: .LBB17_13: # %cond.store7 ; AVX512F-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je .LBB17_12 -; AVX512F-NEXT: .LBB17_11: # %cond.store9 +; AVX512F-NEXT: je .LBB17_6 +; AVX512F-NEXT: .LBB17_14: # %cond.store9 ; AVX512F-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je .LBB17_14 -; AVX512F-NEXT: .LBB17_13: # %cond.store11 +; AVX512F-NEXT: je .LBB17_7 +; AVX512F-NEXT: .LBB17_15: # %cond.store11 ; AVX512F-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX512F-NEXT: testb $-128, %al -; AVX512F-NEXT: je .LBB17_16 -; AVX512F-NEXT: .LBB17_15: # %cond.store13 +; AVX512F-NEXT: je .LBB17_8 +; AVX512F-NEXT: .LBB17_16: # %cond.store13 ; AVX512F-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -7483,60 +7483,60 @@ define void @truncstore_v8i16_v8i8(<8 x i16> %x, ptr %p, <8 x i16> %mask) { ; AVX512FVL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u] ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB17_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB17_9 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB17_3 -; AVX512FVL-NEXT: .LBB17_4: # %else2 +; AVX512FVL-NEXT: jne .LBB17_10 +; AVX512FVL-NEXT: .LBB17_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB17_5 -; AVX512FVL-NEXT: .LBB17_6: # %else4 +; AVX512FVL-NEXT: jne .LBB17_11 +; AVX512FVL-NEXT: .LBB17_3: # %else4 ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: jne .LBB17_7 -; AVX512FVL-NEXT: .LBB17_8: # %else6 +; AVX512FVL-NEXT: jne .LBB17_12 +; AVX512FVL-NEXT: .LBB17_4: # %else6 ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: jne .LBB17_9 -; AVX512FVL-NEXT: .LBB17_10: # %else8 +; AVX512FVL-NEXT: jne .LBB17_13 +; AVX512FVL-NEXT: .LBB17_5: # %else8 ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: jne .LBB17_11 -; AVX512FVL-NEXT: .LBB17_12: # %else10 +; AVX512FVL-NEXT: jne .LBB17_14 +; AVX512FVL-NEXT: .LBB17_6: # %else10 ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: jne .LBB17_13 -; AVX512FVL-NEXT: .LBB17_14: # %else12 -; AVX512FVL-NEXT: testb $-128, %al ; AVX512FVL-NEXT: jne .LBB17_15 -; AVX512FVL-NEXT: .LBB17_16: # %else14 +; AVX512FVL-NEXT: .LBB17_7: # %else12 +; AVX512FVL-NEXT: testb $-128, %al +; AVX512FVL-NEXT: jne .LBB17_16 +; AVX512FVL-NEXT: .LBB17_8: # %else14 ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB17_1: # %cond.store +; AVX512FVL-NEXT: .LBB17_9: # %cond.store ; AVX512FVL-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB17_4 -; AVX512FVL-NEXT: .LBB17_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB17_2 +; AVX512FVL-NEXT: .LBB17_10: # %cond.store1 ; AVX512FVL-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB17_6 -; AVX512FVL-NEXT: .LBB17_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB17_3 +; AVX512FVL-NEXT: .LBB17_11: # %cond.store3 ; AVX512FVL-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB17_8 -; AVX512FVL-NEXT: .LBB17_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB17_4 +; AVX512FVL-NEXT: .LBB17_12: # %cond.store5 ; AVX512FVL-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: je .LBB17_10 -; AVX512FVL-NEXT: .LBB17_9: # %cond.store7 +; AVX512FVL-NEXT: je .LBB17_5 +; AVX512FVL-NEXT: .LBB17_13: # %cond.store7 ; AVX512FVL-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: je .LBB17_12 -; AVX512FVL-NEXT: .LBB17_11: # %cond.store9 +; AVX512FVL-NEXT: je .LBB17_6 +; AVX512FVL-NEXT: .LBB17_14: # %cond.store9 ; AVX512FVL-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: je .LBB17_14 -; AVX512FVL-NEXT: .LBB17_13: # %cond.store11 +; AVX512FVL-NEXT: je .LBB17_7 +; AVX512FVL-NEXT: .LBB17_15: # %cond.store11 ; AVX512FVL-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX512FVL-NEXT: testb $-128, %al -; AVX512FVL-NEXT: je .LBB17_16 -; AVX512FVL-NEXT: .LBB17_15: # %cond.store13 +; AVX512FVL-NEXT: je .LBB17_8 +; AVX512FVL-NEXT: .LBB17_16: # %cond.store13 ; AVX512FVL-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq diff --git a/llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll b/llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll index f56dabc99f595..6f855ddf649e7 100644 --- a/llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll +++ b/llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll @@ -148,33 +148,33 @@ define void @truncstore_v8i64_v8i32(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; SSE2-NEXT: .LBB0_8: # %else6 ; SSE2-NEXT: shufps {{.*#+}} xmm6 = xmm6[0,2],xmm2[0,2] ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: jne .LBB0_9 -; SSE2-NEXT: # %bb.10: # %else8 +; SSE2-NEXT: jne .LBB0_13 +; SSE2-NEXT: # %bb.9: # %else8 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: jne .LBB0_11 -; SSE2-NEXT: .LBB0_12: # %else10 +; SSE2-NEXT: jne .LBB0_14 +; SSE2-NEXT: .LBB0_10: # %else10 ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: jne .LBB0_13 -; SSE2-NEXT: .LBB0_14: # %else12 -; SSE2-NEXT: testb $-128, %al ; SSE2-NEXT: jne .LBB0_15 -; SSE2-NEXT: .LBB0_16: # %else14 +; SSE2-NEXT: .LBB0_11: # %else12 +; SSE2-NEXT: testb $-128, %al +; SSE2-NEXT: jne .LBB0_16 +; SSE2-NEXT: .LBB0_12: # %else14 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB0_9: # %cond.store7 +; SSE2-NEXT: .LBB0_13: # %cond.store7 ; SSE2-NEXT: movss %xmm6, 16(%rdi) ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je .LBB0_12 -; SSE2-NEXT: .LBB0_11: # %cond.store9 +; SSE2-NEXT: je .LBB0_10 +; SSE2-NEXT: .LBB0_14: # %cond.store9 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm6[1,1,1,1] ; SSE2-NEXT: movd %xmm0, 20(%rdi) ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: je .LBB0_14 -; SSE2-NEXT: .LBB0_13: # %cond.store11 +; SSE2-NEXT: je .LBB0_11 +; SSE2-NEXT: .LBB0_15: # %cond.store11 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm6[2,3,2,3] ; SSE2-NEXT: movd %xmm0, 24(%rdi) ; SSE2-NEXT: testb $-128, %al -; SSE2-NEXT: je .LBB0_16 -; SSE2-NEXT: .LBB0_15: # %cond.store13 +; SSE2-NEXT: je .LBB0_12 +; SSE2-NEXT: .LBB0_16: # %cond.store13 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm6[3,3,3,3] ; SSE2-NEXT: movd %xmm0, 28(%rdi) ; SSE2-NEXT: retq @@ -223,59 +223,59 @@ define void @truncstore_v8i64_v8i32(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; SSE4-NEXT: pmovmskb %xmm4, %eax ; SSE4-NEXT: notl %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB0_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB0_10 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB0_3 -; SSE4-NEXT: .LBB0_4: # %else2 +; SSE4-NEXT: jne .LBB0_11 +; SSE4-NEXT: .LBB0_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB0_5 -; SSE4-NEXT: .LBB0_6: # %else4 +; SSE4-NEXT: jne .LBB0_12 +; SSE4-NEXT: .LBB0_3: # %else4 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB0_8 -; SSE4-NEXT: .LBB0_7: # %cond.store5 +; SSE4-NEXT: je .LBB0_5 +; SSE4-NEXT: .LBB0_4: # %cond.store5 ; SSE4-NEXT: extractps $3, %xmm2, 12(%rdi) -; SSE4-NEXT: .LBB0_8: # %else6 +; SSE4-NEXT: .LBB0_5: # %else6 ; SSE4-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm3[0,2] ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: jne .LBB0_9 -; SSE4-NEXT: # %bb.10: # %else8 +; SSE4-NEXT: jne .LBB0_13 +; SSE4-NEXT: # %bb.6: # %else8 ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: jne .LBB0_11 -; SSE4-NEXT: .LBB0_12: # %else10 +; SSE4-NEXT: jne .LBB0_14 +; SSE4-NEXT: .LBB0_7: # %else10 ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: jne .LBB0_13 -; SSE4-NEXT: .LBB0_14: # %else12 -; SSE4-NEXT: testb $-128, %al ; SSE4-NEXT: jne .LBB0_15 -; SSE4-NEXT: .LBB0_16: # %else14 +; SSE4-NEXT: .LBB0_8: # %else12 +; SSE4-NEXT: testb $-128, %al +; SSE4-NEXT: jne .LBB0_16 +; SSE4-NEXT: .LBB0_9: # %else14 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB0_1: # %cond.store +; SSE4-NEXT: .LBB0_10: # %cond.store ; SSE4-NEXT: movss %xmm2, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB0_4 -; SSE4-NEXT: .LBB0_3: # %cond.store1 +; SSE4-NEXT: je .LBB0_2 +; SSE4-NEXT: .LBB0_11: # %cond.store1 ; SSE4-NEXT: extractps $1, %xmm2, 4(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB0_6 -; SSE4-NEXT: .LBB0_5: # %cond.store3 +; SSE4-NEXT: je .LBB0_3 +; SSE4-NEXT: .LBB0_12: # %cond.store3 ; SSE4-NEXT: extractps $2, %xmm2, 8(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne .LBB0_7 -; SSE4-NEXT: jmp .LBB0_8 -; SSE4-NEXT: .LBB0_9: # %cond.store7 +; SSE4-NEXT: jne .LBB0_4 +; SSE4-NEXT: jmp .LBB0_5 +; SSE4-NEXT: .LBB0_13: # %cond.store7 ; SSE4-NEXT: movss %xmm1, 16(%rdi) ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: je .LBB0_12 -; SSE4-NEXT: .LBB0_11: # %cond.store9 +; SSE4-NEXT: je .LBB0_7 +; SSE4-NEXT: .LBB0_14: # %cond.store9 ; SSE4-NEXT: extractps $1, %xmm1, 20(%rdi) ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: je .LBB0_14 -; SSE4-NEXT: .LBB0_13: # %cond.store11 +; SSE4-NEXT: je .LBB0_8 +; SSE4-NEXT: .LBB0_15: # %cond.store11 ; SSE4-NEXT: extractps $2, %xmm1, 24(%rdi) ; SSE4-NEXT: testb $-128, %al -; SSE4-NEXT: je .LBB0_16 -; SSE4-NEXT: .LBB0_15: # %cond.store13 +; SSE4-NEXT: je .LBB0_9 +; SSE4-NEXT: .LBB0_16: # %cond.store13 ; SSE4-NEXT: extractps $3, %xmm1, 28(%rdi) ; SSE4-NEXT: retq ; @@ -501,66 +501,66 @@ define void @truncstore_v8i64_v8i16(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; SSE2-NEXT: pmovmskb %xmm4, %eax ; SSE2-NEXT: notl %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne .LBB1_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB1_9 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne .LBB1_3 -; SSE2-NEXT: .LBB1_4: # %else2 +; SSE2-NEXT: jne .LBB1_10 +; SSE2-NEXT: .LBB1_2: # %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne .LBB1_5 -; SSE2-NEXT: .LBB1_6: # %else4 +; SSE2-NEXT: jne .LBB1_11 +; SSE2-NEXT: .LBB1_3: # %else4 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne .LBB1_7 -; SSE2-NEXT: .LBB1_8: # %else6 +; SSE2-NEXT: jne .LBB1_12 +; SSE2-NEXT: .LBB1_4: # %else6 ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: jne .LBB1_9 -; SSE2-NEXT: .LBB1_10: # %else8 +; SSE2-NEXT: jne .LBB1_13 +; SSE2-NEXT: .LBB1_5: # %else8 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: jne .LBB1_11 -; SSE2-NEXT: .LBB1_12: # %else10 +; SSE2-NEXT: jne .LBB1_14 +; SSE2-NEXT: .LBB1_6: # %else10 ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: jne .LBB1_13 -; SSE2-NEXT: .LBB1_14: # %else12 -; SSE2-NEXT: testb $-128, %al ; SSE2-NEXT: jne .LBB1_15 -; SSE2-NEXT: .LBB1_16: # %else14 +; SSE2-NEXT: .LBB1_7: # %else12 +; SSE2-NEXT: testb $-128, %al +; SSE2-NEXT: jne .LBB1_16 +; SSE2-NEXT: .LBB1_8: # %else14 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB1_1: # %cond.store +; SSE2-NEXT: .LBB1_9: # %cond.store ; SSE2-NEXT: movd %xmm0, %ecx ; SSE2-NEXT: movw %cx, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB1_4 -; SSE2-NEXT: .LBB1_3: # %cond.store1 +; SSE2-NEXT: je .LBB1_2 +; SSE2-NEXT: .LBB1_10: # %cond.store1 ; SSE2-NEXT: pextrw $1, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 2(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je .LBB1_6 -; SSE2-NEXT: .LBB1_5: # %cond.store3 +; SSE2-NEXT: je .LBB1_3 +; SSE2-NEXT: .LBB1_11: # %cond.store3 ; SSE2-NEXT: pextrw $2, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 4(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je .LBB1_8 -; SSE2-NEXT: .LBB1_7: # %cond.store5 +; SSE2-NEXT: je .LBB1_4 +; SSE2-NEXT: .LBB1_12: # %cond.store5 ; SSE2-NEXT: pextrw $3, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 6(%rdi) ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: je .LBB1_10 -; SSE2-NEXT: .LBB1_9: # %cond.store7 +; SSE2-NEXT: je .LBB1_5 +; SSE2-NEXT: .LBB1_13: # %cond.store7 ; SSE2-NEXT: pextrw $4, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 8(%rdi) ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je .LBB1_12 -; SSE2-NEXT: .LBB1_11: # %cond.store9 +; SSE2-NEXT: je .LBB1_6 +; SSE2-NEXT: .LBB1_14: # %cond.store9 ; SSE2-NEXT: pextrw $5, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 10(%rdi) ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: je .LBB1_14 -; SSE2-NEXT: .LBB1_13: # %cond.store11 +; SSE2-NEXT: je .LBB1_7 +; SSE2-NEXT: .LBB1_15: # %cond.store11 ; SSE2-NEXT: pextrw $6, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 12(%rdi) ; SSE2-NEXT: testb $-128, %al -; SSE2-NEXT: je .LBB1_16 -; SSE2-NEXT: .LBB1_15: # %cond.store13 +; SSE2-NEXT: je .LBB1_8 +; SSE2-NEXT: .LBB1_16: # %cond.store13 ; SSE2-NEXT: pextrw $7, %xmm0, %eax ; SSE2-NEXT: movw %ax, 14(%rdi) ; SSE2-NEXT: retq @@ -611,59 +611,59 @@ define void @truncstore_v8i64_v8i16(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; SSE4-NEXT: pmovmskb %xmm4, %eax ; SSE4-NEXT: notl %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB1_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB1_9 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB1_3 -; SSE4-NEXT: .LBB1_4: # %else2 +; SSE4-NEXT: jne .LBB1_10 +; SSE4-NEXT: .LBB1_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB1_5 -; SSE4-NEXT: .LBB1_6: # %else4 +; SSE4-NEXT: jne .LBB1_11 +; SSE4-NEXT: .LBB1_3: # %else4 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne .LBB1_7 -; SSE4-NEXT: .LBB1_8: # %else6 +; SSE4-NEXT: jne .LBB1_12 +; SSE4-NEXT: .LBB1_4: # %else6 ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: jne .LBB1_9 -; SSE4-NEXT: .LBB1_10: # %else8 +; SSE4-NEXT: jne .LBB1_13 +; SSE4-NEXT: .LBB1_5: # %else8 ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: jne .LBB1_11 -; SSE4-NEXT: .LBB1_12: # %else10 +; SSE4-NEXT: jne .LBB1_14 +; SSE4-NEXT: .LBB1_6: # %else10 ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: jne .LBB1_13 -; SSE4-NEXT: .LBB1_14: # %else12 -; SSE4-NEXT: testb $-128, %al ; SSE4-NEXT: jne .LBB1_15 -; SSE4-NEXT: .LBB1_16: # %else14 +; SSE4-NEXT: .LBB1_7: # %else12 +; SSE4-NEXT: testb $-128, %al +; SSE4-NEXT: jne .LBB1_16 +; SSE4-NEXT: .LBB1_8: # %else14 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB1_1: # %cond.store +; SSE4-NEXT: .LBB1_9: # %cond.store ; SSE4-NEXT: pextrw $0, %xmm1, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB1_4 -; SSE4-NEXT: .LBB1_3: # %cond.store1 +; SSE4-NEXT: je .LBB1_2 +; SSE4-NEXT: .LBB1_10: # %cond.store1 ; SSE4-NEXT: pextrw $1, %xmm1, 2(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB1_6 -; SSE4-NEXT: .LBB1_5: # %cond.store3 +; SSE4-NEXT: je .LBB1_3 +; SSE4-NEXT: .LBB1_11: # %cond.store3 ; SSE4-NEXT: pextrw $2, %xmm1, 4(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB1_8 -; SSE4-NEXT: .LBB1_7: # %cond.store5 +; SSE4-NEXT: je .LBB1_4 +; SSE4-NEXT: .LBB1_12: # %cond.store5 ; SSE4-NEXT: pextrw $3, %xmm1, 6(%rdi) ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: je .LBB1_10 -; SSE4-NEXT: .LBB1_9: # %cond.store7 +; SSE4-NEXT: je .LBB1_5 +; SSE4-NEXT: .LBB1_13: # %cond.store7 ; SSE4-NEXT: pextrw $4, %xmm1, 8(%rdi) ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: je .LBB1_12 -; SSE4-NEXT: .LBB1_11: # %cond.store9 +; SSE4-NEXT: je .LBB1_6 +; SSE4-NEXT: .LBB1_14: # %cond.store9 ; SSE4-NEXT: pextrw $5, %xmm1, 10(%rdi) ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: je .LBB1_14 -; SSE4-NEXT: .LBB1_13: # %cond.store11 +; SSE4-NEXT: je .LBB1_7 +; SSE4-NEXT: .LBB1_15: # %cond.store11 ; SSE4-NEXT: pextrw $6, %xmm1, 12(%rdi) ; SSE4-NEXT: testb $-128, %al -; SSE4-NEXT: je .LBB1_16 -; SSE4-NEXT: .LBB1_15: # %cond.store13 +; SSE4-NEXT: je .LBB1_8 +; SSE4-NEXT: .LBB1_16: # %cond.store13 ; SSE4-NEXT: pextrw $7, %xmm1, 14(%rdi) ; SSE4-NEXT: retq ; @@ -700,60 +700,60 @@ define void @truncstore_v8i64_v8i16(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; AVX1-NEXT: vmovmskps %ymm1, %eax ; AVX1-NEXT: notl %eax ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne .LBB1_1 -; AVX1-NEXT: # %bb.2: # %else +; AVX1-NEXT: jne .LBB1_9 +; AVX1-NEXT: # %bb.1: # %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne .LBB1_3 -; AVX1-NEXT: .LBB1_4: # %else2 +; AVX1-NEXT: jne .LBB1_10 +; AVX1-NEXT: .LBB1_2: # %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne .LBB1_5 -; AVX1-NEXT: .LBB1_6: # %else4 +; AVX1-NEXT: jne .LBB1_11 +; AVX1-NEXT: .LBB1_3: # %else4 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne .LBB1_7 -; AVX1-NEXT: .LBB1_8: # %else6 +; AVX1-NEXT: jne .LBB1_12 +; AVX1-NEXT: .LBB1_4: # %else6 ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: jne .LBB1_9 -; AVX1-NEXT: .LBB1_10: # %else8 +; AVX1-NEXT: jne .LBB1_13 +; AVX1-NEXT: .LBB1_5: # %else8 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: jne .LBB1_11 -; AVX1-NEXT: .LBB1_12: # %else10 +; AVX1-NEXT: jne .LBB1_14 +; AVX1-NEXT: .LBB1_6: # %else10 ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: jne .LBB1_13 -; AVX1-NEXT: .LBB1_14: # %else12 -; AVX1-NEXT: testb $-128, %al ; AVX1-NEXT: jne .LBB1_15 -; AVX1-NEXT: .LBB1_16: # %else14 +; AVX1-NEXT: .LBB1_7: # %else12 +; AVX1-NEXT: testb $-128, %al +; AVX1-NEXT: jne .LBB1_16 +; AVX1-NEXT: .LBB1_8: # %else14 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB1_1: # %cond.store +; AVX1-NEXT: .LBB1_9: # %cond.store ; AVX1-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je .LBB1_4 -; AVX1-NEXT: .LBB1_3: # %cond.store1 +; AVX1-NEXT: je .LBB1_2 +; AVX1-NEXT: .LBB1_10: # %cond.store1 ; AVX1-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je .LBB1_6 -; AVX1-NEXT: .LBB1_5: # %cond.store3 +; AVX1-NEXT: je .LBB1_3 +; AVX1-NEXT: .LBB1_11: # %cond.store3 ; AVX1-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB1_8 -; AVX1-NEXT: .LBB1_7: # %cond.store5 +; AVX1-NEXT: je .LBB1_4 +; AVX1-NEXT: .LBB1_12: # %cond.store5 ; AVX1-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: je .LBB1_10 -; AVX1-NEXT: .LBB1_9: # %cond.store7 +; AVX1-NEXT: je .LBB1_5 +; AVX1-NEXT: .LBB1_13: # %cond.store7 ; AVX1-NEXT: vpextrw $4, %xmm0, 8(%rdi) ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je .LBB1_12 -; AVX1-NEXT: .LBB1_11: # %cond.store9 +; AVX1-NEXT: je .LBB1_6 +; AVX1-NEXT: .LBB1_14: # %cond.store9 ; AVX1-NEXT: vpextrw $5, %xmm0, 10(%rdi) ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: je .LBB1_14 -; AVX1-NEXT: .LBB1_13: # %cond.store11 +; AVX1-NEXT: je .LBB1_7 +; AVX1-NEXT: .LBB1_15: # %cond.store11 ; AVX1-NEXT: vpextrw $6, %xmm0, 12(%rdi) ; AVX1-NEXT: testb $-128, %al -; AVX1-NEXT: je .LBB1_16 -; AVX1-NEXT: .LBB1_15: # %cond.store13 +; AVX1-NEXT: je .LBB1_8 +; AVX1-NEXT: .LBB1_16: # %cond.store13 ; AVX1-NEXT: vpextrw $7, %xmm0, 14(%rdi) ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq @@ -779,60 +779,60 @@ define void @truncstore_v8i64_v8i16(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; AVX2-NEXT: vmovmskps %ymm1, %eax ; AVX2-NEXT: notl %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne .LBB1_1 -; AVX2-NEXT: # %bb.2: # %else +; AVX2-NEXT: jne .LBB1_9 +; AVX2-NEXT: # %bb.1: # %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne .LBB1_3 -; AVX2-NEXT: .LBB1_4: # %else2 +; AVX2-NEXT: jne .LBB1_10 +; AVX2-NEXT: .LBB1_2: # %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne .LBB1_5 -; AVX2-NEXT: .LBB1_6: # %else4 +; AVX2-NEXT: jne .LBB1_11 +; AVX2-NEXT: .LBB1_3: # %else4 ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: jne .LBB1_7 -; AVX2-NEXT: .LBB1_8: # %else6 +; AVX2-NEXT: jne .LBB1_12 +; AVX2-NEXT: .LBB1_4: # %else6 ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: jne .LBB1_9 -; AVX2-NEXT: .LBB1_10: # %else8 +; AVX2-NEXT: jne .LBB1_13 +; AVX2-NEXT: .LBB1_5: # %else8 ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: jne .LBB1_11 -; AVX2-NEXT: .LBB1_12: # %else10 +; AVX2-NEXT: jne .LBB1_14 +; AVX2-NEXT: .LBB1_6: # %else10 ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: jne .LBB1_13 -; AVX2-NEXT: .LBB1_14: # %else12 -; AVX2-NEXT: testb $-128, %al ; AVX2-NEXT: jne .LBB1_15 -; AVX2-NEXT: .LBB1_16: # %else14 +; AVX2-NEXT: .LBB1_7: # %else12 +; AVX2-NEXT: testb $-128, %al +; AVX2-NEXT: jne .LBB1_16 +; AVX2-NEXT: .LBB1_8: # %else14 ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; AVX2-NEXT: .LBB1_1: # %cond.store +; AVX2-NEXT: .LBB1_9: # %cond.store ; AVX2-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je .LBB1_4 -; AVX2-NEXT: .LBB1_3: # %cond.store1 +; AVX2-NEXT: je .LBB1_2 +; AVX2-NEXT: .LBB1_10: # %cond.store1 ; AVX2-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je .LBB1_6 -; AVX2-NEXT: .LBB1_5: # %cond.store3 +; AVX2-NEXT: je .LBB1_3 +; AVX2-NEXT: .LBB1_11: # %cond.store3 ; AVX2-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je .LBB1_8 -; AVX2-NEXT: .LBB1_7: # %cond.store5 +; AVX2-NEXT: je .LBB1_4 +; AVX2-NEXT: .LBB1_12: # %cond.store5 ; AVX2-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: je .LBB1_10 -; AVX2-NEXT: .LBB1_9: # %cond.store7 +; AVX2-NEXT: je .LBB1_5 +; AVX2-NEXT: .LBB1_13: # %cond.store7 ; AVX2-NEXT: vpextrw $4, %xmm0, 8(%rdi) ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: je .LBB1_12 -; AVX2-NEXT: .LBB1_11: # %cond.store9 +; AVX2-NEXT: je .LBB1_6 +; AVX2-NEXT: .LBB1_14: # %cond.store9 ; AVX2-NEXT: vpextrw $5, %xmm0, 10(%rdi) ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: je .LBB1_14 -; AVX2-NEXT: .LBB1_13: # %cond.store11 +; AVX2-NEXT: je .LBB1_7 +; AVX2-NEXT: .LBB1_15: # %cond.store11 ; AVX2-NEXT: vpextrw $6, %xmm0, 12(%rdi) ; AVX2-NEXT: testb $-128, %al -; AVX2-NEXT: je .LBB1_16 -; AVX2-NEXT: .LBB1_15: # %cond.store13 +; AVX2-NEXT: je .LBB1_8 +; AVX2-NEXT: .LBB1_16: # %cond.store13 ; AVX2-NEXT: vpextrw $7, %xmm0, 14(%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq @@ -844,60 +844,60 @@ define void @truncstore_v8i64_v8i16(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; AVX512F-NEXT: vpmovsqw %zmm0, %xmm0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB1_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB1_9 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB1_3 -; AVX512F-NEXT: .LBB1_4: # %else2 +; AVX512F-NEXT: jne .LBB1_10 +; AVX512F-NEXT: .LBB1_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB1_5 -; AVX512F-NEXT: .LBB1_6: # %else4 +; AVX512F-NEXT: jne .LBB1_11 +; AVX512F-NEXT: .LBB1_3: # %else4 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne .LBB1_7 -; AVX512F-NEXT: .LBB1_8: # %else6 +; AVX512F-NEXT: jne .LBB1_12 +; AVX512F-NEXT: .LBB1_4: # %else6 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne .LBB1_9 -; AVX512F-NEXT: .LBB1_10: # %else8 +; AVX512F-NEXT: jne .LBB1_13 +; AVX512F-NEXT: .LBB1_5: # %else8 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne .LBB1_11 -; AVX512F-NEXT: .LBB1_12: # %else10 +; AVX512F-NEXT: jne .LBB1_14 +; AVX512F-NEXT: .LBB1_6: # %else10 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne .LBB1_13 -; AVX512F-NEXT: .LBB1_14: # %else12 -; AVX512F-NEXT: testb $-128, %al ; AVX512F-NEXT: jne .LBB1_15 -; AVX512F-NEXT: .LBB1_16: # %else14 +; AVX512F-NEXT: .LBB1_7: # %else12 +; AVX512F-NEXT: testb $-128, %al +; AVX512F-NEXT: jne .LBB1_16 +; AVX512F-NEXT: .LBB1_8: # %else14 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB1_1: # %cond.store +; AVX512F-NEXT: .LBB1_9: # %cond.store ; AVX512F-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB1_4 -; AVX512F-NEXT: .LBB1_3: # %cond.store1 +; AVX512F-NEXT: je .LBB1_2 +; AVX512F-NEXT: .LBB1_10: # %cond.store1 ; AVX512F-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB1_6 -; AVX512F-NEXT: .LBB1_5: # %cond.store3 +; AVX512F-NEXT: je .LBB1_3 +; AVX512F-NEXT: .LBB1_11: # %cond.store3 ; AVX512F-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB1_8 -; AVX512F-NEXT: .LBB1_7: # %cond.store5 +; AVX512F-NEXT: je .LBB1_4 +; AVX512F-NEXT: .LBB1_12: # %cond.store5 ; AVX512F-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je .LBB1_10 -; AVX512F-NEXT: .LBB1_9: # %cond.store7 +; AVX512F-NEXT: je .LBB1_5 +; AVX512F-NEXT: .LBB1_13: # %cond.store7 ; AVX512F-NEXT: vpextrw $4, %xmm0, 8(%rdi) ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je .LBB1_12 -; AVX512F-NEXT: .LBB1_11: # %cond.store9 +; AVX512F-NEXT: je .LBB1_6 +; AVX512F-NEXT: .LBB1_14: # %cond.store9 ; AVX512F-NEXT: vpextrw $5, %xmm0, 10(%rdi) ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je .LBB1_14 -; AVX512F-NEXT: .LBB1_13: # %cond.store11 +; AVX512F-NEXT: je .LBB1_7 +; AVX512F-NEXT: .LBB1_15: # %cond.store11 ; AVX512F-NEXT: vpextrw $6, %xmm0, 12(%rdi) ; AVX512F-NEXT: testb $-128, %al -; AVX512F-NEXT: je .LBB1_16 -; AVX512F-NEXT: .LBB1_15: # %cond.store13 +; AVX512F-NEXT: je .LBB1_8 +; AVX512F-NEXT: .LBB1_16: # %cond.store13 ; AVX512F-NEXT: vpextrw $7, %xmm0, 14(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -908,60 +908,60 @@ define void @truncstore_v8i64_v8i16(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; AVX512FVL-NEXT: vpmovsqw %zmm0, %xmm0 ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB1_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB1_9 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB1_3 -; AVX512FVL-NEXT: .LBB1_4: # %else2 +; AVX512FVL-NEXT: jne .LBB1_10 +; AVX512FVL-NEXT: .LBB1_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB1_5 -; AVX512FVL-NEXT: .LBB1_6: # %else4 +; AVX512FVL-NEXT: jne .LBB1_11 +; AVX512FVL-NEXT: .LBB1_3: # %else4 ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: jne .LBB1_7 -; AVX512FVL-NEXT: .LBB1_8: # %else6 +; AVX512FVL-NEXT: jne .LBB1_12 +; AVX512FVL-NEXT: .LBB1_4: # %else6 ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: jne .LBB1_9 -; AVX512FVL-NEXT: .LBB1_10: # %else8 +; AVX512FVL-NEXT: jne .LBB1_13 +; AVX512FVL-NEXT: .LBB1_5: # %else8 ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: jne .LBB1_11 -; AVX512FVL-NEXT: .LBB1_12: # %else10 +; AVX512FVL-NEXT: jne .LBB1_14 +; AVX512FVL-NEXT: .LBB1_6: # %else10 ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: jne .LBB1_13 -; AVX512FVL-NEXT: .LBB1_14: # %else12 -; AVX512FVL-NEXT: testb $-128, %al ; AVX512FVL-NEXT: jne .LBB1_15 -; AVX512FVL-NEXT: .LBB1_16: # %else14 +; AVX512FVL-NEXT: .LBB1_7: # %else12 +; AVX512FVL-NEXT: testb $-128, %al +; AVX512FVL-NEXT: jne .LBB1_16 +; AVX512FVL-NEXT: .LBB1_8: # %else14 ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB1_1: # %cond.store +; AVX512FVL-NEXT: .LBB1_9: # %cond.store ; AVX512FVL-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB1_4 -; AVX512FVL-NEXT: .LBB1_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB1_2 +; AVX512FVL-NEXT: .LBB1_10: # %cond.store1 ; AVX512FVL-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB1_6 -; AVX512FVL-NEXT: .LBB1_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB1_3 +; AVX512FVL-NEXT: .LBB1_11: # %cond.store3 ; AVX512FVL-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB1_8 -; AVX512FVL-NEXT: .LBB1_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB1_4 +; AVX512FVL-NEXT: .LBB1_12: # %cond.store5 ; AVX512FVL-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: je .LBB1_10 -; AVX512FVL-NEXT: .LBB1_9: # %cond.store7 +; AVX512FVL-NEXT: je .LBB1_5 +; AVX512FVL-NEXT: .LBB1_13: # %cond.store7 ; AVX512FVL-NEXT: vpextrw $4, %xmm0, 8(%rdi) ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: je .LBB1_12 -; AVX512FVL-NEXT: .LBB1_11: # %cond.store9 +; AVX512FVL-NEXT: je .LBB1_6 +; AVX512FVL-NEXT: .LBB1_14: # %cond.store9 ; AVX512FVL-NEXT: vpextrw $5, %xmm0, 10(%rdi) ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: je .LBB1_14 -; AVX512FVL-NEXT: .LBB1_13: # %cond.store11 +; AVX512FVL-NEXT: je .LBB1_7 +; AVX512FVL-NEXT: .LBB1_15: # %cond.store11 ; AVX512FVL-NEXT: vpextrw $6, %xmm0, 12(%rdi) ; AVX512FVL-NEXT: testb $-128, %al -; AVX512FVL-NEXT: je .LBB1_16 -; AVX512FVL-NEXT: .LBB1_15: # %cond.store13 +; AVX512FVL-NEXT: je .LBB1_8 +; AVX512FVL-NEXT: .LBB1_16: # %cond.store13 ; AVX512FVL-NEXT: vpextrw $7, %xmm0, 14(%rdi) ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq @@ -1110,59 +1110,59 @@ define void @truncstore_v8i64_v8i8(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; SSE2-NEXT: notl %eax ; SSE2-NEXT: testb $1, %al ; SSE2-NEXT: movd %xmm0, %ecx -; SSE2-NEXT: jne .LBB2_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB2_12 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne .LBB2_3 -; SSE2-NEXT: .LBB2_4: # %else2 +; SSE2-NEXT: jne .LBB2_13 +; SSE2-NEXT: .LBB2_2: # %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne .LBB2_5 -; SSE2-NEXT: .LBB2_6: # %else4 +; SSE2-NEXT: jne .LBB2_14 +; SSE2-NEXT: .LBB2_3: # %else4 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je .LBB2_8 -; SSE2-NEXT: .LBB2_7: # %cond.store5 +; SSE2-NEXT: je .LBB2_5 +; SSE2-NEXT: .LBB2_4: # %cond.store5 ; SSE2-NEXT: shrl $24, %ecx ; SSE2-NEXT: movb %cl, 3(%rdi) -; SSE2-NEXT: .LBB2_8: # %else6 +; SSE2-NEXT: .LBB2_5: # %else6 ; SSE2-NEXT: testb $16, %al ; SSE2-NEXT: pextrw $2, %xmm0, %ecx -; SSE2-NEXT: je .LBB2_10 -; SSE2-NEXT: # %bb.9: # %cond.store7 +; SSE2-NEXT: je .LBB2_7 +; SSE2-NEXT: # %bb.6: # %cond.store7 ; SSE2-NEXT: movb %cl, 4(%rdi) -; SSE2-NEXT: .LBB2_10: # %else8 +; SSE2-NEXT: .LBB2_7: # %else8 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je .LBB2_12 -; SSE2-NEXT: # %bb.11: # %cond.store9 +; SSE2-NEXT: je .LBB2_9 +; SSE2-NEXT: # %bb.8: # %cond.store9 ; SSE2-NEXT: movb %ch, 5(%rdi) -; SSE2-NEXT: .LBB2_12: # %else10 +; SSE2-NEXT: .LBB2_9: # %else10 ; SSE2-NEXT: testb $64, %al ; SSE2-NEXT: pextrw $3, %xmm0, %ecx -; SSE2-NEXT: jne .LBB2_13 -; SSE2-NEXT: # %bb.14: # %else12 -; SSE2-NEXT: testb $-128, %al ; SSE2-NEXT: jne .LBB2_15 -; SSE2-NEXT: .LBB2_16: # %else14 +; SSE2-NEXT: # %bb.10: # %else12 +; SSE2-NEXT: testb $-128, %al +; SSE2-NEXT: jne .LBB2_16 +; SSE2-NEXT: .LBB2_11: # %else14 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB2_1: # %cond.store +; SSE2-NEXT: .LBB2_12: # %cond.store ; SSE2-NEXT: movb %cl, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB2_4 -; SSE2-NEXT: .LBB2_3: # %cond.store1 +; SSE2-NEXT: je .LBB2_2 +; SSE2-NEXT: .LBB2_13: # %cond.store1 ; SSE2-NEXT: movb %ch, 1(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je .LBB2_6 -; SSE2-NEXT: .LBB2_5: # %cond.store3 +; SSE2-NEXT: je .LBB2_3 +; SSE2-NEXT: .LBB2_14: # %cond.store3 ; SSE2-NEXT: movl %ecx, %edx ; SSE2-NEXT: shrl $16, %edx ; SSE2-NEXT: movb %dl, 2(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne .LBB2_7 -; SSE2-NEXT: jmp .LBB2_8 -; SSE2-NEXT: .LBB2_13: # %cond.store11 +; SSE2-NEXT: jne .LBB2_4 +; SSE2-NEXT: jmp .LBB2_5 +; SSE2-NEXT: .LBB2_15: # %cond.store11 ; SSE2-NEXT: movb %cl, 6(%rdi) ; SSE2-NEXT: testb $-128, %al -; SSE2-NEXT: je .LBB2_16 -; SSE2-NEXT: .LBB2_15: # %cond.store13 +; SSE2-NEXT: je .LBB2_11 +; SSE2-NEXT: .LBB2_16: # %cond.store13 ; SSE2-NEXT: movb %ch, 7(%rdi) ; SSE2-NEXT: retq ; @@ -1213,59 +1213,59 @@ define void @truncstore_v8i64_v8i8(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; SSE4-NEXT: pmovmskb %xmm4, %eax ; SSE4-NEXT: notl %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB2_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB2_9 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB2_3 -; SSE4-NEXT: .LBB2_4: # %else2 +; SSE4-NEXT: jne .LBB2_10 +; SSE4-NEXT: .LBB2_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB2_5 -; SSE4-NEXT: .LBB2_6: # %else4 +; SSE4-NEXT: jne .LBB2_11 +; SSE4-NEXT: .LBB2_3: # %else4 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne .LBB2_7 -; SSE4-NEXT: .LBB2_8: # %else6 +; SSE4-NEXT: jne .LBB2_12 +; SSE4-NEXT: .LBB2_4: # %else6 ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: jne .LBB2_9 -; SSE4-NEXT: .LBB2_10: # %else8 +; SSE4-NEXT: jne .LBB2_13 +; SSE4-NEXT: .LBB2_5: # %else8 ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: jne .LBB2_11 -; SSE4-NEXT: .LBB2_12: # %else10 +; SSE4-NEXT: jne .LBB2_14 +; SSE4-NEXT: .LBB2_6: # %else10 ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: jne .LBB2_13 -; SSE4-NEXT: .LBB2_14: # %else12 -; SSE4-NEXT: testb $-128, %al ; SSE4-NEXT: jne .LBB2_15 -; SSE4-NEXT: .LBB2_16: # %else14 +; SSE4-NEXT: .LBB2_7: # %else12 +; SSE4-NEXT: testb $-128, %al +; SSE4-NEXT: jne .LBB2_16 +; SSE4-NEXT: .LBB2_8: # %else14 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB2_1: # %cond.store +; SSE4-NEXT: .LBB2_9: # %cond.store ; SSE4-NEXT: pextrb $0, %xmm1, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB2_4 -; SSE4-NEXT: .LBB2_3: # %cond.store1 +; SSE4-NEXT: je .LBB2_2 +; SSE4-NEXT: .LBB2_10: # %cond.store1 ; SSE4-NEXT: pextrb $1, %xmm1, 1(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB2_6 -; SSE4-NEXT: .LBB2_5: # %cond.store3 +; SSE4-NEXT: je .LBB2_3 +; SSE4-NEXT: .LBB2_11: # %cond.store3 ; SSE4-NEXT: pextrb $2, %xmm1, 2(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB2_8 -; SSE4-NEXT: .LBB2_7: # %cond.store5 +; SSE4-NEXT: je .LBB2_4 +; SSE4-NEXT: .LBB2_12: # %cond.store5 ; SSE4-NEXT: pextrb $3, %xmm1, 3(%rdi) ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: je .LBB2_10 -; SSE4-NEXT: .LBB2_9: # %cond.store7 +; SSE4-NEXT: je .LBB2_5 +; SSE4-NEXT: .LBB2_13: # %cond.store7 ; SSE4-NEXT: pextrb $4, %xmm1, 4(%rdi) ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: je .LBB2_12 -; SSE4-NEXT: .LBB2_11: # %cond.store9 +; SSE4-NEXT: je .LBB2_6 +; SSE4-NEXT: .LBB2_14: # %cond.store9 ; SSE4-NEXT: pextrb $5, %xmm1, 5(%rdi) ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: je .LBB2_14 -; SSE4-NEXT: .LBB2_13: # %cond.store11 +; SSE4-NEXT: je .LBB2_7 +; SSE4-NEXT: .LBB2_15: # %cond.store11 ; SSE4-NEXT: pextrb $6, %xmm1, 6(%rdi) ; SSE4-NEXT: testb $-128, %al -; SSE4-NEXT: je .LBB2_16 -; SSE4-NEXT: .LBB2_15: # %cond.store13 +; SSE4-NEXT: je .LBB2_8 +; SSE4-NEXT: .LBB2_16: # %cond.store13 ; SSE4-NEXT: pextrb $7, %xmm1, 7(%rdi) ; SSE4-NEXT: retq ; @@ -1303,60 +1303,60 @@ define void @truncstore_v8i64_v8i8(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; AVX1-NEXT: vmovmskps %ymm1, %eax ; AVX1-NEXT: notl %eax ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne .LBB2_1 -; AVX1-NEXT: # %bb.2: # %else +; AVX1-NEXT: jne .LBB2_9 +; AVX1-NEXT: # %bb.1: # %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne .LBB2_3 -; AVX1-NEXT: .LBB2_4: # %else2 +; AVX1-NEXT: jne .LBB2_10 +; AVX1-NEXT: .LBB2_2: # %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne .LBB2_5 -; AVX1-NEXT: .LBB2_6: # %else4 +; AVX1-NEXT: jne .LBB2_11 +; AVX1-NEXT: .LBB2_3: # %else4 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne .LBB2_7 -; AVX1-NEXT: .LBB2_8: # %else6 +; AVX1-NEXT: jne .LBB2_12 +; AVX1-NEXT: .LBB2_4: # %else6 ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: jne .LBB2_9 -; AVX1-NEXT: .LBB2_10: # %else8 +; AVX1-NEXT: jne .LBB2_13 +; AVX1-NEXT: .LBB2_5: # %else8 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: jne .LBB2_11 -; AVX1-NEXT: .LBB2_12: # %else10 +; AVX1-NEXT: jne .LBB2_14 +; AVX1-NEXT: .LBB2_6: # %else10 ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: jne .LBB2_13 -; AVX1-NEXT: .LBB2_14: # %else12 -; AVX1-NEXT: testb $-128, %al ; AVX1-NEXT: jne .LBB2_15 -; AVX1-NEXT: .LBB2_16: # %else14 +; AVX1-NEXT: .LBB2_7: # %else12 +; AVX1-NEXT: testb $-128, %al +; AVX1-NEXT: jne .LBB2_16 +; AVX1-NEXT: .LBB2_8: # %else14 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB2_1: # %cond.store +; AVX1-NEXT: .LBB2_9: # %cond.store ; AVX1-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je .LBB2_4 -; AVX1-NEXT: .LBB2_3: # %cond.store1 +; AVX1-NEXT: je .LBB2_2 +; AVX1-NEXT: .LBB2_10: # %cond.store1 ; AVX1-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je .LBB2_6 -; AVX1-NEXT: .LBB2_5: # %cond.store3 +; AVX1-NEXT: je .LBB2_3 +; AVX1-NEXT: .LBB2_11: # %cond.store3 ; AVX1-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB2_8 -; AVX1-NEXT: .LBB2_7: # %cond.store5 +; AVX1-NEXT: je .LBB2_4 +; AVX1-NEXT: .LBB2_12: # %cond.store5 ; AVX1-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: je .LBB2_10 -; AVX1-NEXT: .LBB2_9: # %cond.store7 +; AVX1-NEXT: je .LBB2_5 +; AVX1-NEXT: .LBB2_13: # %cond.store7 ; AVX1-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je .LBB2_12 -; AVX1-NEXT: .LBB2_11: # %cond.store9 +; AVX1-NEXT: je .LBB2_6 +; AVX1-NEXT: .LBB2_14: # %cond.store9 ; AVX1-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: je .LBB2_14 -; AVX1-NEXT: .LBB2_13: # %cond.store11 +; AVX1-NEXT: je .LBB2_7 +; AVX1-NEXT: .LBB2_15: # %cond.store11 ; AVX1-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX1-NEXT: testb $-128, %al -; AVX1-NEXT: je .LBB2_16 -; AVX1-NEXT: .LBB2_15: # %cond.store13 +; AVX1-NEXT: je .LBB2_8 +; AVX1-NEXT: .LBB2_16: # %cond.store13 ; AVX1-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq @@ -1383,60 +1383,60 @@ define void @truncstore_v8i64_v8i8(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; AVX2-NEXT: vmovmskps %ymm1, %eax ; AVX2-NEXT: notl %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne .LBB2_1 -; AVX2-NEXT: # %bb.2: # %else +; AVX2-NEXT: jne .LBB2_9 +; AVX2-NEXT: # %bb.1: # %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne .LBB2_3 -; AVX2-NEXT: .LBB2_4: # %else2 +; AVX2-NEXT: jne .LBB2_10 +; AVX2-NEXT: .LBB2_2: # %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne .LBB2_5 -; AVX2-NEXT: .LBB2_6: # %else4 +; AVX2-NEXT: jne .LBB2_11 +; AVX2-NEXT: .LBB2_3: # %else4 ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: jne .LBB2_7 -; AVX2-NEXT: .LBB2_8: # %else6 +; AVX2-NEXT: jne .LBB2_12 +; AVX2-NEXT: .LBB2_4: # %else6 ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: jne .LBB2_9 -; AVX2-NEXT: .LBB2_10: # %else8 +; AVX2-NEXT: jne .LBB2_13 +; AVX2-NEXT: .LBB2_5: # %else8 ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: jne .LBB2_11 -; AVX2-NEXT: .LBB2_12: # %else10 +; AVX2-NEXT: jne .LBB2_14 +; AVX2-NEXT: .LBB2_6: # %else10 ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: jne .LBB2_13 -; AVX2-NEXT: .LBB2_14: # %else12 -; AVX2-NEXT: testb $-128, %al ; AVX2-NEXT: jne .LBB2_15 -; AVX2-NEXT: .LBB2_16: # %else14 +; AVX2-NEXT: .LBB2_7: # %else12 +; AVX2-NEXT: testb $-128, %al +; AVX2-NEXT: jne .LBB2_16 +; AVX2-NEXT: .LBB2_8: # %else14 ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; AVX2-NEXT: .LBB2_1: # %cond.store +; AVX2-NEXT: .LBB2_9: # %cond.store ; AVX2-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je .LBB2_4 -; AVX2-NEXT: .LBB2_3: # %cond.store1 +; AVX2-NEXT: je .LBB2_2 +; AVX2-NEXT: .LBB2_10: # %cond.store1 ; AVX2-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je .LBB2_6 -; AVX2-NEXT: .LBB2_5: # %cond.store3 +; AVX2-NEXT: je .LBB2_3 +; AVX2-NEXT: .LBB2_11: # %cond.store3 ; AVX2-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je .LBB2_8 -; AVX2-NEXT: .LBB2_7: # %cond.store5 +; AVX2-NEXT: je .LBB2_4 +; AVX2-NEXT: .LBB2_12: # %cond.store5 ; AVX2-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: je .LBB2_10 -; AVX2-NEXT: .LBB2_9: # %cond.store7 +; AVX2-NEXT: je .LBB2_5 +; AVX2-NEXT: .LBB2_13: # %cond.store7 ; AVX2-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: je .LBB2_12 -; AVX2-NEXT: .LBB2_11: # %cond.store9 +; AVX2-NEXT: je .LBB2_6 +; AVX2-NEXT: .LBB2_14: # %cond.store9 ; AVX2-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: je .LBB2_14 -; AVX2-NEXT: .LBB2_13: # %cond.store11 +; AVX2-NEXT: je .LBB2_7 +; AVX2-NEXT: .LBB2_15: # %cond.store11 ; AVX2-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX2-NEXT: testb $-128, %al -; AVX2-NEXT: je .LBB2_16 -; AVX2-NEXT: .LBB2_15: # %cond.store13 +; AVX2-NEXT: je .LBB2_8 +; AVX2-NEXT: .LBB2_16: # %cond.store13 ; AVX2-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq @@ -1448,60 +1448,60 @@ define void @truncstore_v8i64_v8i8(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; AVX512F-NEXT: vpmovsqb %zmm0, %xmm0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB2_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB2_9 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB2_3 -; AVX512F-NEXT: .LBB2_4: # %else2 +; AVX512F-NEXT: jne .LBB2_10 +; AVX512F-NEXT: .LBB2_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB2_5 -; AVX512F-NEXT: .LBB2_6: # %else4 +; AVX512F-NEXT: jne .LBB2_11 +; AVX512F-NEXT: .LBB2_3: # %else4 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne .LBB2_7 -; AVX512F-NEXT: .LBB2_8: # %else6 +; AVX512F-NEXT: jne .LBB2_12 +; AVX512F-NEXT: .LBB2_4: # %else6 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne .LBB2_9 -; AVX512F-NEXT: .LBB2_10: # %else8 +; AVX512F-NEXT: jne .LBB2_13 +; AVX512F-NEXT: .LBB2_5: # %else8 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne .LBB2_11 -; AVX512F-NEXT: .LBB2_12: # %else10 +; AVX512F-NEXT: jne .LBB2_14 +; AVX512F-NEXT: .LBB2_6: # %else10 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne .LBB2_13 -; AVX512F-NEXT: .LBB2_14: # %else12 -; AVX512F-NEXT: testb $-128, %al ; AVX512F-NEXT: jne .LBB2_15 -; AVX512F-NEXT: .LBB2_16: # %else14 +; AVX512F-NEXT: .LBB2_7: # %else12 +; AVX512F-NEXT: testb $-128, %al +; AVX512F-NEXT: jne .LBB2_16 +; AVX512F-NEXT: .LBB2_8: # %else14 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB2_1: # %cond.store +; AVX512F-NEXT: .LBB2_9: # %cond.store ; AVX512F-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB2_4 -; AVX512F-NEXT: .LBB2_3: # %cond.store1 +; AVX512F-NEXT: je .LBB2_2 +; AVX512F-NEXT: .LBB2_10: # %cond.store1 ; AVX512F-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB2_6 -; AVX512F-NEXT: .LBB2_5: # %cond.store3 +; AVX512F-NEXT: je .LBB2_3 +; AVX512F-NEXT: .LBB2_11: # %cond.store3 ; AVX512F-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB2_8 -; AVX512F-NEXT: .LBB2_7: # %cond.store5 +; AVX512F-NEXT: je .LBB2_4 +; AVX512F-NEXT: .LBB2_12: # %cond.store5 ; AVX512F-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je .LBB2_10 -; AVX512F-NEXT: .LBB2_9: # %cond.store7 +; AVX512F-NEXT: je .LBB2_5 +; AVX512F-NEXT: .LBB2_13: # %cond.store7 ; AVX512F-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je .LBB2_12 -; AVX512F-NEXT: .LBB2_11: # %cond.store9 +; AVX512F-NEXT: je .LBB2_6 +; AVX512F-NEXT: .LBB2_14: # %cond.store9 ; AVX512F-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je .LBB2_14 -; AVX512F-NEXT: .LBB2_13: # %cond.store11 +; AVX512F-NEXT: je .LBB2_7 +; AVX512F-NEXT: .LBB2_15: # %cond.store11 ; AVX512F-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX512F-NEXT: testb $-128, %al -; AVX512F-NEXT: je .LBB2_16 -; AVX512F-NEXT: .LBB2_15: # %cond.store13 +; AVX512F-NEXT: je .LBB2_8 +; AVX512F-NEXT: .LBB2_16: # %cond.store13 ; AVX512F-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -1512,60 +1512,60 @@ define void @truncstore_v8i64_v8i8(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; AVX512FVL-NEXT: vpmovsqb %zmm0, %xmm0 ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB2_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB2_9 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB2_3 -; AVX512FVL-NEXT: .LBB2_4: # %else2 +; AVX512FVL-NEXT: jne .LBB2_10 +; AVX512FVL-NEXT: .LBB2_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB2_5 -; AVX512FVL-NEXT: .LBB2_6: # %else4 +; AVX512FVL-NEXT: jne .LBB2_11 +; AVX512FVL-NEXT: .LBB2_3: # %else4 ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: jne .LBB2_7 -; AVX512FVL-NEXT: .LBB2_8: # %else6 +; AVX512FVL-NEXT: jne .LBB2_12 +; AVX512FVL-NEXT: .LBB2_4: # %else6 ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: jne .LBB2_9 -; AVX512FVL-NEXT: .LBB2_10: # %else8 +; AVX512FVL-NEXT: jne .LBB2_13 +; AVX512FVL-NEXT: .LBB2_5: # %else8 ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: jne .LBB2_11 -; AVX512FVL-NEXT: .LBB2_12: # %else10 +; AVX512FVL-NEXT: jne .LBB2_14 +; AVX512FVL-NEXT: .LBB2_6: # %else10 ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: jne .LBB2_13 -; AVX512FVL-NEXT: .LBB2_14: # %else12 -; AVX512FVL-NEXT: testb $-128, %al ; AVX512FVL-NEXT: jne .LBB2_15 -; AVX512FVL-NEXT: .LBB2_16: # %else14 +; AVX512FVL-NEXT: .LBB2_7: # %else12 +; AVX512FVL-NEXT: testb $-128, %al +; AVX512FVL-NEXT: jne .LBB2_16 +; AVX512FVL-NEXT: .LBB2_8: # %else14 ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB2_1: # %cond.store +; AVX512FVL-NEXT: .LBB2_9: # %cond.store ; AVX512FVL-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB2_4 -; AVX512FVL-NEXT: .LBB2_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB2_2 +; AVX512FVL-NEXT: .LBB2_10: # %cond.store1 ; AVX512FVL-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB2_6 -; AVX512FVL-NEXT: .LBB2_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB2_3 +; AVX512FVL-NEXT: .LBB2_11: # %cond.store3 ; AVX512FVL-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB2_8 -; AVX512FVL-NEXT: .LBB2_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB2_4 +; AVX512FVL-NEXT: .LBB2_12: # %cond.store5 ; AVX512FVL-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: je .LBB2_10 -; AVX512FVL-NEXT: .LBB2_9: # %cond.store7 +; AVX512FVL-NEXT: je .LBB2_5 +; AVX512FVL-NEXT: .LBB2_13: # %cond.store7 ; AVX512FVL-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: je .LBB2_12 -; AVX512FVL-NEXT: .LBB2_11: # %cond.store9 +; AVX512FVL-NEXT: je .LBB2_6 +; AVX512FVL-NEXT: .LBB2_14: # %cond.store9 ; AVX512FVL-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: je .LBB2_14 -; AVX512FVL-NEXT: .LBB2_13: # %cond.store11 +; AVX512FVL-NEXT: je .LBB2_7 +; AVX512FVL-NEXT: .LBB2_15: # %cond.store11 ; AVX512FVL-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX512FVL-NEXT: testb $-128, %al -; AVX512FVL-NEXT: je .LBB2_16 -; AVX512FVL-NEXT: .LBB2_15: # %cond.store13 +; AVX512FVL-NEXT: je .LBB2_8 +; AVX512FVL-NEXT: .LBB2_16: # %cond.store13 ; AVX512FVL-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq @@ -1657,33 +1657,33 @@ define void @truncstore_v4i64_v4i32(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; SSE2-NEXT: movmskps %xmm2, %eax ; SSE2-NEXT: xorl $15, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne .LBB3_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB3_5 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne .LBB3_3 -; SSE2-NEXT: .LBB3_4: # %else2 +; SSE2-NEXT: jne .LBB3_6 +; SSE2-NEXT: .LBB3_2: # %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne .LBB3_5 -; SSE2-NEXT: .LBB3_6: # %else4 -; SSE2-NEXT: testb $8, %al ; SSE2-NEXT: jne .LBB3_7 -; SSE2-NEXT: .LBB3_8: # %else6 +; SSE2-NEXT: .LBB3_3: # %else4 +; SSE2-NEXT: testb $8, %al +; SSE2-NEXT: jne .LBB3_8 +; SSE2-NEXT: .LBB3_4: # %else6 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB3_1: # %cond.store +; SSE2-NEXT: .LBB3_5: # %cond.store ; SSE2-NEXT: movss %xmm0, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB3_4 -; SSE2-NEXT: .LBB3_3: # %cond.store1 +; SSE2-NEXT: je .LBB3_2 +; SSE2-NEXT: .LBB3_6: # %cond.store1 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1] ; SSE2-NEXT: movd %xmm1, 4(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je .LBB3_6 -; SSE2-NEXT: .LBB3_5: # %cond.store3 +; SSE2-NEXT: je .LBB3_3 +; SSE2-NEXT: .LBB3_7: # %cond.store3 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3] ; SSE2-NEXT: movd %xmm1, 8(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je .LBB3_8 -; SSE2-NEXT: .LBB3_7: # %cond.store5 +; SSE2-NEXT: je .LBB3_4 +; SSE2-NEXT: .LBB3_8: # %cond.store5 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE2-NEXT: movd %xmm0, 12(%rdi) ; SSE2-NEXT: retq @@ -1713,31 +1713,31 @@ define void @truncstore_v4i64_v4i32(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; SSE4-NEXT: movmskps %xmm4, %eax ; SSE4-NEXT: xorl $15, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB3_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB3_5 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB3_3 -; SSE4-NEXT: .LBB3_4: # %else2 +; SSE4-NEXT: jne .LBB3_6 +; SSE4-NEXT: .LBB3_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB3_5 -; SSE4-NEXT: .LBB3_6: # %else4 -; SSE4-NEXT: testb $8, %al ; SSE4-NEXT: jne .LBB3_7 -; SSE4-NEXT: .LBB3_8: # %else6 +; SSE4-NEXT: .LBB3_3: # %else4 +; SSE4-NEXT: testb $8, %al +; SSE4-NEXT: jne .LBB3_8 +; SSE4-NEXT: .LBB3_4: # %else6 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB3_1: # %cond.store +; SSE4-NEXT: .LBB3_5: # %cond.store ; SSE4-NEXT: movss %xmm1, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB3_4 -; SSE4-NEXT: .LBB3_3: # %cond.store1 +; SSE4-NEXT: je .LBB3_2 +; SSE4-NEXT: .LBB3_6: # %cond.store1 ; SSE4-NEXT: extractps $1, %xmm1, 4(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB3_6 -; SSE4-NEXT: .LBB3_5: # %cond.store3 +; SSE4-NEXT: je .LBB3_3 +; SSE4-NEXT: .LBB3_7: # %cond.store3 ; SSE4-NEXT: extractps $2, %xmm1, 8(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB3_8 -; SSE4-NEXT: .LBB3_7: # %cond.store5 +; SSE4-NEXT: je .LBB3_4 +; SSE4-NEXT: .LBB3_8: # %cond.store5 ; SSE4-NEXT: extractps $3, %xmm1, 12(%rdi) ; SSE4-NEXT: retq ; @@ -1884,34 +1884,34 @@ define void @truncstore_v4i64_v4i16(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; SSE2-NEXT: movmskps %xmm2, %eax ; SSE2-NEXT: xorl $15, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne .LBB4_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB4_5 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne .LBB4_3 -; SSE2-NEXT: .LBB4_4: # %else2 +; SSE2-NEXT: jne .LBB4_6 +; SSE2-NEXT: .LBB4_2: # %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne .LBB4_5 -; SSE2-NEXT: .LBB4_6: # %else4 -; SSE2-NEXT: testb $8, %al ; SSE2-NEXT: jne .LBB4_7 -; SSE2-NEXT: .LBB4_8: # %else6 +; SSE2-NEXT: .LBB4_3: # %else4 +; SSE2-NEXT: testb $8, %al +; SSE2-NEXT: jne .LBB4_8 +; SSE2-NEXT: .LBB4_4: # %else6 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB4_1: # %cond.store +; SSE2-NEXT: .LBB4_5: # %cond.store ; SSE2-NEXT: movd %xmm0, %ecx ; SSE2-NEXT: movw %cx, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB4_4 -; SSE2-NEXT: .LBB4_3: # %cond.store1 +; SSE2-NEXT: je .LBB4_2 +; SSE2-NEXT: .LBB4_6: # %cond.store1 ; SSE2-NEXT: pextrw $1, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 2(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je .LBB4_6 -; SSE2-NEXT: .LBB4_5: # %cond.store3 +; SSE2-NEXT: je .LBB4_3 +; SSE2-NEXT: .LBB4_7: # %cond.store3 ; SSE2-NEXT: pextrw $2, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 4(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je .LBB4_8 -; SSE2-NEXT: .LBB4_7: # %cond.store5 +; SSE2-NEXT: je .LBB4_4 +; SSE2-NEXT: .LBB4_8: # %cond.store5 ; SSE2-NEXT: pextrw $3, %xmm0, %eax ; SSE2-NEXT: movw %ax, 6(%rdi) ; SSE2-NEXT: retq @@ -1942,31 +1942,31 @@ define void @truncstore_v4i64_v4i16(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; SSE4-NEXT: movmskps %xmm4, %eax ; SSE4-NEXT: xorl $15, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB4_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB4_5 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB4_3 -; SSE4-NEXT: .LBB4_4: # %else2 +; SSE4-NEXT: jne .LBB4_6 +; SSE4-NEXT: .LBB4_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB4_5 -; SSE4-NEXT: .LBB4_6: # %else4 -; SSE4-NEXT: testb $8, %al ; SSE4-NEXT: jne .LBB4_7 -; SSE4-NEXT: .LBB4_8: # %else6 +; SSE4-NEXT: .LBB4_3: # %else4 +; SSE4-NEXT: testb $8, %al +; SSE4-NEXT: jne .LBB4_8 +; SSE4-NEXT: .LBB4_4: # %else6 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB4_1: # %cond.store +; SSE4-NEXT: .LBB4_5: # %cond.store ; SSE4-NEXT: pextrw $0, %xmm1, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB4_4 -; SSE4-NEXT: .LBB4_3: # %cond.store1 +; SSE4-NEXT: je .LBB4_2 +; SSE4-NEXT: .LBB4_6: # %cond.store1 ; SSE4-NEXT: pextrw $1, %xmm1, 2(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB4_6 -; SSE4-NEXT: .LBB4_5: # %cond.store3 +; SSE4-NEXT: je .LBB4_3 +; SSE4-NEXT: .LBB4_7: # %cond.store3 ; SSE4-NEXT: pextrw $2, %xmm1, 4(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB4_8 -; SSE4-NEXT: .LBB4_7: # %cond.store5 +; SSE4-NEXT: je .LBB4_4 +; SSE4-NEXT: .LBB4_8: # %cond.store5 ; SSE4-NEXT: pextrw $3, %xmm1, 6(%rdi) ; SSE4-NEXT: retq ; @@ -1990,32 +1990,32 @@ define void @truncstore_v4i64_v4i16(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; AVX1-NEXT: vmovmskps %xmm1, %eax ; AVX1-NEXT: xorl $15, %eax ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne .LBB4_1 -; AVX1-NEXT: # %bb.2: # %else +; AVX1-NEXT: jne .LBB4_5 +; AVX1-NEXT: # %bb.1: # %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne .LBB4_3 -; AVX1-NEXT: .LBB4_4: # %else2 +; AVX1-NEXT: jne .LBB4_6 +; AVX1-NEXT: .LBB4_2: # %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne .LBB4_5 -; AVX1-NEXT: .LBB4_6: # %else4 -; AVX1-NEXT: testb $8, %al ; AVX1-NEXT: jne .LBB4_7 -; AVX1-NEXT: .LBB4_8: # %else6 +; AVX1-NEXT: .LBB4_3: # %else4 +; AVX1-NEXT: testb $8, %al +; AVX1-NEXT: jne .LBB4_8 +; AVX1-NEXT: .LBB4_4: # %else6 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB4_1: # %cond.store +; AVX1-NEXT: .LBB4_5: # %cond.store ; AVX1-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je .LBB4_4 -; AVX1-NEXT: .LBB4_3: # %cond.store1 +; AVX1-NEXT: je .LBB4_2 +; AVX1-NEXT: .LBB4_6: # %cond.store1 ; AVX1-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je .LBB4_6 -; AVX1-NEXT: .LBB4_5: # %cond.store3 +; AVX1-NEXT: je .LBB4_3 +; AVX1-NEXT: .LBB4_7: # %cond.store3 ; AVX1-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB4_8 -; AVX1-NEXT: .LBB4_7: # %cond.store5 +; AVX1-NEXT: je .LBB4_4 +; AVX1-NEXT: .LBB4_8: # %cond.store5 ; AVX1-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq @@ -2036,32 +2036,32 @@ define void @truncstore_v4i64_v4i16(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; AVX2-NEXT: vmovmskps %xmm1, %eax ; AVX2-NEXT: xorl $15, %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne .LBB4_1 -; AVX2-NEXT: # %bb.2: # %else +; AVX2-NEXT: jne .LBB4_5 +; AVX2-NEXT: # %bb.1: # %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne .LBB4_3 -; AVX2-NEXT: .LBB4_4: # %else2 +; AVX2-NEXT: jne .LBB4_6 +; AVX2-NEXT: .LBB4_2: # %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne .LBB4_5 -; AVX2-NEXT: .LBB4_6: # %else4 -; AVX2-NEXT: testb $8, %al ; AVX2-NEXT: jne .LBB4_7 -; AVX2-NEXT: .LBB4_8: # %else6 +; AVX2-NEXT: .LBB4_3: # %else4 +; AVX2-NEXT: testb $8, %al +; AVX2-NEXT: jne .LBB4_8 +; AVX2-NEXT: .LBB4_4: # %else6 ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; AVX2-NEXT: .LBB4_1: # %cond.store +; AVX2-NEXT: .LBB4_5: # %cond.store ; AVX2-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je .LBB4_4 -; AVX2-NEXT: .LBB4_3: # %cond.store1 +; AVX2-NEXT: je .LBB4_2 +; AVX2-NEXT: .LBB4_6: # %cond.store1 ; AVX2-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je .LBB4_6 -; AVX2-NEXT: .LBB4_5: # %cond.store3 +; AVX2-NEXT: je .LBB4_3 +; AVX2-NEXT: .LBB4_7: # %cond.store3 ; AVX2-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je .LBB4_8 -; AVX2-NEXT: .LBB4_7: # %cond.store5 +; AVX2-NEXT: je .LBB4_4 +; AVX2-NEXT: .LBB4_8: # %cond.store5 ; AVX2-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq @@ -2074,32 +2074,32 @@ define void @truncstore_v4i64_v4i16(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; AVX512F-NEXT: vpmovsqw %zmm0, %xmm0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB4_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB4_5 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB4_3 -; AVX512F-NEXT: .LBB4_4: # %else2 +; AVX512F-NEXT: jne .LBB4_6 +; AVX512F-NEXT: .LBB4_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB4_5 -; AVX512F-NEXT: .LBB4_6: # %else4 -; AVX512F-NEXT: testb $8, %al ; AVX512F-NEXT: jne .LBB4_7 -; AVX512F-NEXT: .LBB4_8: # %else6 +; AVX512F-NEXT: .LBB4_3: # %else4 +; AVX512F-NEXT: testb $8, %al +; AVX512F-NEXT: jne .LBB4_8 +; AVX512F-NEXT: .LBB4_4: # %else6 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB4_1: # %cond.store +; AVX512F-NEXT: .LBB4_5: # %cond.store ; AVX512F-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB4_4 -; AVX512F-NEXT: .LBB4_3: # %cond.store1 +; AVX512F-NEXT: je .LBB4_2 +; AVX512F-NEXT: .LBB4_6: # %cond.store1 ; AVX512F-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB4_6 -; AVX512F-NEXT: .LBB4_5: # %cond.store3 +; AVX512F-NEXT: je .LBB4_3 +; AVX512F-NEXT: .LBB4_7: # %cond.store3 ; AVX512F-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB4_8 -; AVX512F-NEXT: .LBB4_7: # %cond.store5 +; AVX512F-NEXT: je .LBB4_4 +; AVX512F-NEXT: .LBB4_8: # %cond.store5 ; AVX512F-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -2110,32 +2110,32 @@ define void @truncstore_v4i64_v4i16(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; AVX512FVL-NEXT: vpmovsqw %ymm0, %xmm0 ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB4_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB4_5 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB4_3 -; AVX512FVL-NEXT: .LBB4_4: # %else2 +; AVX512FVL-NEXT: jne .LBB4_6 +; AVX512FVL-NEXT: .LBB4_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB4_5 -; AVX512FVL-NEXT: .LBB4_6: # %else4 -; AVX512FVL-NEXT: testb $8, %al ; AVX512FVL-NEXT: jne .LBB4_7 -; AVX512FVL-NEXT: .LBB4_8: # %else6 +; AVX512FVL-NEXT: .LBB4_3: # %else4 +; AVX512FVL-NEXT: testb $8, %al +; AVX512FVL-NEXT: jne .LBB4_8 +; AVX512FVL-NEXT: .LBB4_4: # %else6 ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB4_1: # %cond.store +; AVX512FVL-NEXT: .LBB4_5: # %cond.store ; AVX512FVL-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB4_4 -; AVX512FVL-NEXT: .LBB4_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB4_2 +; AVX512FVL-NEXT: .LBB4_6: # %cond.store1 ; AVX512FVL-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB4_6 -; AVX512FVL-NEXT: .LBB4_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB4_3 +; AVX512FVL-NEXT: .LBB4_7: # %cond.store3 ; AVX512FVL-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB4_8 -; AVX512FVL-NEXT: .LBB4_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB4_4 +; AVX512FVL-NEXT: .LBB4_8: # %cond.store5 ; AVX512FVL-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq @@ -2234,33 +2234,33 @@ define void @truncstore_v4i64_v4i8(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; SSE2-NEXT: xorl $15, %ecx ; SSE2-NEXT: testb $1, %cl ; SSE2-NEXT: movd %xmm4, %eax -; SSE2-NEXT: jne .LBB5_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB5_5 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %cl -; SSE2-NEXT: jne .LBB5_3 -; SSE2-NEXT: .LBB5_4: # %else2 +; SSE2-NEXT: jne .LBB5_6 +; SSE2-NEXT: .LBB5_2: # %else2 ; SSE2-NEXT: testb $4, %cl -; SSE2-NEXT: jne .LBB5_5 -; SSE2-NEXT: .LBB5_6: # %else4 -; SSE2-NEXT: testb $8, %cl ; SSE2-NEXT: jne .LBB5_7 -; SSE2-NEXT: .LBB5_8: # %else6 +; SSE2-NEXT: .LBB5_3: # %else4 +; SSE2-NEXT: testb $8, %cl +; SSE2-NEXT: jne .LBB5_8 +; SSE2-NEXT: .LBB5_4: # %else6 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB5_1: # %cond.store +; SSE2-NEXT: .LBB5_5: # %cond.store ; SSE2-NEXT: movb %al, (%rdi) ; SSE2-NEXT: testb $2, %cl -; SSE2-NEXT: je .LBB5_4 -; SSE2-NEXT: .LBB5_3: # %cond.store1 +; SSE2-NEXT: je .LBB5_2 +; SSE2-NEXT: .LBB5_6: # %cond.store1 ; SSE2-NEXT: movb %ah, 1(%rdi) ; SSE2-NEXT: testb $4, %cl -; SSE2-NEXT: je .LBB5_6 -; SSE2-NEXT: .LBB5_5: # %cond.store3 +; SSE2-NEXT: je .LBB5_3 +; SSE2-NEXT: .LBB5_7: # %cond.store3 ; SSE2-NEXT: movl %eax, %edx ; SSE2-NEXT: shrl $16, %edx ; SSE2-NEXT: movb %dl, 2(%rdi) ; SSE2-NEXT: testb $8, %cl -; SSE2-NEXT: je .LBB5_8 -; SSE2-NEXT: .LBB5_7: # %cond.store5 +; SSE2-NEXT: je .LBB5_4 +; SSE2-NEXT: .LBB5_8: # %cond.store5 ; SSE2-NEXT: shrl $24, %eax ; SSE2-NEXT: movb %al, 3(%rdi) ; SSE2-NEXT: retq @@ -2292,31 +2292,31 @@ define void @truncstore_v4i64_v4i8(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; SSE4-NEXT: movmskps %xmm4, %eax ; SSE4-NEXT: xorl $15, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB5_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB5_5 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB5_3 -; SSE4-NEXT: .LBB5_4: # %else2 +; SSE4-NEXT: jne .LBB5_6 +; SSE4-NEXT: .LBB5_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB5_5 -; SSE4-NEXT: .LBB5_6: # %else4 -; SSE4-NEXT: testb $8, %al ; SSE4-NEXT: jne .LBB5_7 -; SSE4-NEXT: .LBB5_8: # %else6 +; SSE4-NEXT: .LBB5_3: # %else4 +; SSE4-NEXT: testb $8, %al +; SSE4-NEXT: jne .LBB5_8 +; SSE4-NEXT: .LBB5_4: # %else6 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB5_1: # %cond.store +; SSE4-NEXT: .LBB5_5: # %cond.store ; SSE4-NEXT: pextrb $0, %xmm1, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB5_4 -; SSE4-NEXT: .LBB5_3: # %cond.store1 +; SSE4-NEXT: je .LBB5_2 +; SSE4-NEXT: .LBB5_6: # %cond.store1 ; SSE4-NEXT: pextrb $1, %xmm1, 1(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB5_6 -; SSE4-NEXT: .LBB5_5: # %cond.store3 +; SSE4-NEXT: je .LBB5_3 +; SSE4-NEXT: .LBB5_7: # %cond.store3 ; SSE4-NEXT: pextrb $2, %xmm1, 2(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB5_8 -; SSE4-NEXT: .LBB5_7: # %cond.store5 +; SSE4-NEXT: je .LBB5_4 +; SSE4-NEXT: .LBB5_8: # %cond.store5 ; SSE4-NEXT: pextrb $3, %xmm1, 3(%rdi) ; SSE4-NEXT: retq ; @@ -2341,32 +2341,32 @@ define void @truncstore_v4i64_v4i8(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; AVX1-NEXT: vmovmskps %xmm1, %eax ; AVX1-NEXT: xorl $15, %eax ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne .LBB5_1 -; AVX1-NEXT: # %bb.2: # %else +; AVX1-NEXT: jne .LBB5_5 +; AVX1-NEXT: # %bb.1: # %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne .LBB5_3 -; AVX1-NEXT: .LBB5_4: # %else2 +; AVX1-NEXT: jne .LBB5_6 +; AVX1-NEXT: .LBB5_2: # %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne .LBB5_5 -; AVX1-NEXT: .LBB5_6: # %else4 -; AVX1-NEXT: testb $8, %al ; AVX1-NEXT: jne .LBB5_7 -; AVX1-NEXT: .LBB5_8: # %else6 +; AVX1-NEXT: .LBB5_3: # %else4 +; AVX1-NEXT: testb $8, %al +; AVX1-NEXT: jne .LBB5_8 +; AVX1-NEXT: .LBB5_4: # %else6 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB5_1: # %cond.store +; AVX1-NEXT: .LBB5_5: # %cond.store ; AVX1-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je .LBB5_4 -; AVX1-NEXT: .LBB5_3: # %cond.store1 +; AVX1-NEXT: je .LBB5_2 +; AVX1-NEXT: .LBB5_6: # %cond.store1 ; AVX1-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je .LBB5_6 -; AVX1-NEXT: .LBB5_5: # %cond.store3 +; AVX1-NEXT: je .LBB5_3 +; AVX1-NEXT: .LBB5_7: # %cond.store3 ; AVX1-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB5_8 -; AVX1-NEXT: .LBB5_7: # %cond.store5 +; AVX1-NEXT: je .LBB5_4 +; AVX1-NEXT: .LBB5_8: # %cond.store5 ; AVX1-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq @@ -2388,32 +2388,32 @@ define void @truncstore_v4i64_v4i8(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; AVX2-NEXT: vmovmskps %xmm1, %eax ; AVX2-NEXT: xorl $15, %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne .LBB5_1 -; AVX2-NEXT: # %bb.2: # %else +; AVX2-NEXT: jne .LBB5_5 +; AVX2-NEXT: # %bb.1: # %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne .LBB5_3 -; AVX2-NEXT: .LBB5_4: # %else2 +; AVX2-NEXT: jne .LBB5_6 +; AVX2-NEXT: .LBB5_2: # %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne .LBB5_5 -; AVX2-NEXT: .LBB5_6: # %else4 -; AVX2-NEXT: testb $8, %al ; AVX2-NEXT: jne .LBB5_7 -; AVX2-NEXT: .LBB5_8: # %else6 +; AVX2-NEXT: .LBB5_3: # %else4 +; AVX2-NEXT: testb $8, %al +; AVX2-NEXT: jne .LBB5_8 +; AVX2-NEXT: .LBB5_4: # %else6 ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; AVX2-NEXT: .LBB5_1: # %cond.store +; AVX2-NEXT: .LBB5_5: # %cond.store ; AVX2-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je .LBB5_4 -; AVX2-NEXT: .LBB5_3: # %cond.store1 +; AVX2-NEXT: je .LBB5_2 +; AVX2-NEXT: .LBB5_6: # %cond.store1 ; AVX2-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je .LBB5_6 -; AVX2-NEXT: .LBB5_5: # %cond.store3 +; AVX2-NEXT: je .LBB5_3 +; AVX2-NEXT: .LBB5_7: # %cond.store3 ; AVX2-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je .LBB5_8 -; AVX2-NEXT: .LBB5_7: # %cond.store5 +; AVX2-NEXT: je .LBB5_4 +; AVX2-NEXT: .LBB5_8: # %cond.store5 ; AVX2-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq @@ -2426,32 +2426,32 @@ define void @truncstore_v4i64_v4i8(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; AVX512F-NEXT: vpmovsqb %zmm0, %xmm0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB5_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB5_5 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB5_3 -; AVX512F-NEXT: .LBB5_4: # %else2 +; AVX512F-NEXT: jne .LBB5_6 +; AVX512F-NEXT: .LBB5_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB5_5 -; AVX512F-NEXT: .LBB5_6: # %else4 -; AVX512F-NEXT: testb $8, %al ; AVX512F-NEXT: jne .LBB5_7 -; AVX512F-NEXT: .LBB5_8: # %else6 +; AVX512F-NEXT: .LBB5_3: # %else4 +; AVX512F-NEXT: testb $8, %al +; AVX512F-NEXT: jne .LBB5_8 +; AVX512F-NEXT: .LBB5_4: # %else6 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB5_1: # %cond.store +; AVX512F-NEXT: .LBB5_5: # %cond.store ; AVX512F-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB5_4 -; AVX512F-NEXT: .LBB5_3: # %cond.store1 +; AVX512F-NEXT: je .LBB5_2 +; AVX512F-NEXT: .LBB5_6: # %cond.store1 ; AVX512F-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB5_6 -; AVX512F-NEXT: .LBB5_5: # %cond.store3 +; AVX512F-NEXT: je .LBB5_3 +; AVX512F-NEXT: .LBB5_7: # %cond.store3 ; AVX512F-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB5_8 -; AVX512F-NEXT: .LBB5_7: # %cond.store5 +; AVX512F-NEXT: je .LBB5_4 +; AVX512F-NEXT: .LBB5_8: # %cond.store5 ; AVX512F-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -2462,32 +2462,32 @@ define void @truncstore_v4i64_v4i8(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; AVX512FVL-NEXT: vpmovsqb %ymm0, %xmm0 ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB5_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB5_5 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB5_3 -; AVX512FVL-NEXT: .LBB5_4: # %else2 +; AVX512FVL-NEXT: jne .LBB5_6 +; AVX512FVL-NEXT: .LBB5_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB5_5 -; AVX512FVL-NEXT: .LBB5_6: # %else4 -; AVX512FVL-NEXT: testb $8, %al ; AVX512FVL-NEXT: jne .LBB5_7 -; AVX512FVL-NEXT: .LBB5_8: # %else6 +; AVX512FVL-NEXT: .LBB5_3: # %else4 +; AVX512FVL-NEXT: testb $8, %al +; AVX512FVL-NEXT: jne .LBB5_8 +; AVX512FVL-NEXT: .LBB5_4: # %else6 ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB5_1: # %cond.store +; AVX512FVL-NEXT: .LBB5_5: # %cond.store ; AVX512FVL-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB5_4 -; AVX512FVL-NEXT: .LBB5_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB5_2 +; AVX512FVL-NEXT: .LBB5_6: # %cond.store1 ; AVX512FVL-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB5_6 -; AVX512FVL-NEXT: .LBB5_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB5_3 +; AVX512FVL-NEXT: .LBB5_7: # %cond.store3 ; AVX512FVL-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB5_8 -; AVX512FVL-NEXT: .LBB5_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB5_4 +; AVX512FVL-NEXT: .LBB5_8: # %cond.store5 ; AVX512FVL-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq @@ -2557,17 +2557,17 @@ define void @truncstore_v2i64_v2i32(<2 x i64> %x, ptr %p, <2 x i64> %mask) { ; SSE2-NEXT: movmskpd %xmm2, %eax ; SSE2-NEXT: xorl $3, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne .LBB6_1 -; SSE2-NEXT: # %bb.2: # %else -; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: jne .LBB6_3 -; SSE2-NEXT: .LBB6_4: # %else2 +; SSE2-NEXT: # %bb.1: # %else +; SSE2-NEXT: testb $2, %al +; SSE2-NEXT: jne .LBB6_4 +; SSE2-NEXT: .LBB6_2: # %else2 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB6_1: # %cond.store +; SSE2-NEXT: .LBB6_3: # %cond.store ; SSE2-NEXT: movd %xmm0, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB6_4 -; SSE2-NEXT: .LBB6_3: # %cond.store1 +; SSE2-NEXT: je .LBB6_2 +; SSE2-NEXT: .LBB6_4: # %cond.store1 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1] ; SSE2-NEXT: movd %xmm0, 4(%rdi) ; SSE2-NEXT: retq @@ -2589,17 +2589,17 @@ define void @truncstore_v2i64_v2i32(<2 x i64> %x, ptr %p, <2 x i64> %mask) { ; SSE4-NEXT: movmskpd %xmm3, %eax ; SSE4-NEXT: xorl $3, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB6_1 -; SSE4-NEXT: # %bb.2: # %else -; SSE4-NEXT: testb $2, %al ; SSE4-NEXT: jne .LBB6_3 -; SSE4-NEXT: .LBB6_4: # %else2 +; SSE4-NEXT: # %bb.1: # %else +; SSE4-NEXT: testb $2, %al +; SSE4-NEXT: jne .LBB6_4 +; SSE4-NEXT: .LBB6_2: # %else2 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB6_1: # %cond.store +; SSE4-NEXT: .LBB6_3: # %cond.store ; SSE4-NEXT: movd %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB6_4 -; SSE4-NEXT: .LBB6_3: # %cond.store1 +; SSE4-NEXT: je .LBB6_2 +; SSE4-NEXT: .LBB6_4: # %cond.store1 ; SSE4-NEXT: pextrd $1, %xmm0, 4(%rdi) ; SSE4-NEXT: retq ; @@ -2712,18 +2712,18 @@ define void @truncstore_v2i64_v2i16(<2 x i64> %x, ptr %p, <2 x i64> %mask) { ; SSE2-NEXT: movmskpd %xmm2, %eax ; SSE2-NEXT: xorl $3, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne .LBB7_1 -; SSE2-NEXT: # %bb.2: # %else -; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: jne .LBB7_3 -; SSE2-NEXT: .LBB7_4: # %else2 +; SSE2-NEXT: # %bb.1: # %else +; SSE2-NEXT: testb $2, %al +; SSE2-NEXT: jne .LBB7_4 +; SSE2-NEXT: .LBB7_2: # %else2 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB7_1: # %cond.store +; SSE2-NEXT: .LBB7_3: # %cond.store ; SSE2-NEXT: movd %xmm0, %ecx ; SSE2-NEXT: movw %cx, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB7_4 -; SSE2-NEXT: .LBB7_3: # %cond.store1 +; SSE2-NEXT: je .LBB7_2 +; SSE2-NEXT: .LBB7_4: # %cond.store1 ; SSE2-NEXT: pextrw $1, %xmm0, %eax ; SSE2-NEXT: movw %ax, 2(%rdi) ; SSE2-NEXT: retq @@ -2746,17 +2746,17 @@ define void @truncstore_v2i64_v2i16(<2 x i64> %x, ptr %p, <2 x i64> %mask) { ; SSE4-NEXT: movmskpd %xmm3, %eax ; SSE4-NEXT: xorl $3, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB7_1 -; SSE4-NEXT: # %bb.2: # %else -; SSE4-NEXT: testb $2, %al ; SSE4-NEXT: jne .LBB7_3 -; SSE4-NEXT: .LBB7_4: # %else2 +; SSE4-NEXT: # %bb.1: # %else +; SSE4-NEXT: testb $2, %al +; SSE4-NEXT: jne .LBB7_4 +; SSE4-NEXT: .LBB7_2: # %else2 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB7_1: # %cond.store +; SSE4-NEXT: .LBB7_3: # %cond.store ; SSE4-NEXT: pextrw $0, %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB7_4 -; SSE4-NEXT: .LBB7_3: # %cond.store1 +; SSE4-NEXT: je .LBB7_2 +; SSE4-NEXT: .LBB7_4: # %cond.store1 ; SSE4-NEXT: pextrw $1, %xmm0, 2(%rdi) ; SSE4-NEXT: retq ; @@ -2775,17 +2775,17 @@ define void @truncstore_v2i64_v2i16(<2 x i64> %x, ptr %p, <2 x i64> %mask) { ; AVX-NEXT: vmovmskpd %xmm1, %eax ; AVX-NEXT: xorl $3, %eax ; AVX-NEXT: testb $1, %al -; AVX-NEXT: jne .LBB7_1 -; AVX-NEXT: # %bb.2: # %else -; AVX-NEXT: testb $2, %al ; AVX-NEXT: jne .LBB7_3 -; AVX-NEXT: .LBB7_4: # %else2 +; AVX-NEXT: # %bb.1: # %else +; AVX-NEXT: testb $2, %al +; AVX-NEXT: jne .LBB7_4 +; AVX-NEXT: .LBB7_2: # %else2 ; AVX-NEXT: retq -; AVX-NEXT: .LBB7_1: # %cond.store +; AVX-NEXT: .LBB7_3: # %cond.store ; AVX-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX-NEXT: testb $2, %al -; AVX-NEXT: je .LBB7_4 -; AVX-NEXT: .LBB7_3: # %cond.store1 +; AVX-NEXT: je .LBB7_2 +; AVX-NEXT: .LBB7_4: # %cond.store1 ; AVX-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX-NEXT: retq ; @@ -2797,18 +2797,18 @@ define void @truncstore_v2i64_v2i16(<2 x i64> %x, ptr %p, <2 x i64> %mask) { ; AVX512F-NEXT: vpmovsqw %zmm0, %xmm0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB7_1 -; AVX512F-NEXT: # %bb.2: # %else -; AVX512F-NEXT: testb $2, %al ; AVX512F-NEXT: jne .LBB7_3 -; AVX512F-NEXT: .LBB7_4: # %else2 +; AVX512F-NEXT: # %bb.1: # %else +; AVX512F-NEXT: testb $2, %al +; AVX512F-NEXT: jne .LBB7_4 +; AVX512F-NEXT: .LBB7_2: # %else2 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB7_1: # %cond.store +; AVX512F-NEXT: .LBB7_3: # %cond.store ; AVX512F-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB7_4 -; AVX512F-NEXT: .LBB7_3: # %cond.store1 +; AVX512F-NEXT: je .LBB7_2 +; AVX512F-NEXT: .LBB7_4: # %cond.store1 ; AVX512F-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -2819,17 +2819,17 @@ define void @truncstore_v2i64_v2i16(<2 x i64> %x, ptr %p, <2 x i64> %mask) { ; AVX512FVL-NEXT: vpmovsqw %xmm0, %xmm0 ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB7_1 -; AVX512FVL-NEXT: # %bb.2: # %else -; AVX512FVL-NEXT: testb $2, %al ; AVX512FVL-NEXT: jne .LBB7_3 -; AVX512FVL-NEXT: .LBB7_4: # %else2 +; AVX512FVL-NEXT: # %bb.1: # %else +; AVX512FVL-NEXT: testb $2, %al +; AVX512FVL-NEXT: jne .LBB7_4 +; AVX512FVL-NEXT: .LBB7_2: # %else2 ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB7_1: # %cond.store +; AVX512FVL-NEXT: .LBB7_3: # %cond.store ; AVX512FVL-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB7_4 -; AVX512FVL-NEXT: .LBB7_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB7_2 +; AVX512FVL-NEXT: .LBB7_4: # %cond.store1 ; AVX512FVL-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: retq ; @@ -2900,17 +2900,17 @@ define void @truncstore_v2i64_v2i8(<2 x i64> %x, ptr %p, <2 x i64> %mask) { ; SSE2-NEXT: xorl $3, %eax ; SSE2-NEXT: testb $1, %al ; SSE2-NEXT: movd %xmm3, %ecx -; SSE2-NEXT: jne .LBB8_1 -; SSE2-NEXT: # %bb.2: # %else -; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: jne .LBB8_3 -; SSE2-NEXT: .LBB8_4: # %else2 +; SSE2-NEXT: # %bb.1: # %else +; SSE2-NEXT: testb $2, %al +; SSE2-NEXT: jne .LBB8_4 +; SSE2-NEXT: .LBB8_2: # %else2 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB8_1: # %cond.store +; SSE2-NEXT: .LBB8_3: # %cond.store ; SSE2-NEXT: movb %cl, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB8_4 -; SSE2-NEXT: .LBB8_3: # %cond.store1 +; SSE2-NEXT: je .LBB8_2 +; SSE2-NEXT: .LBB8_4: # %cond.store1 ; SSE2-NEXT: movb %ch, 1(%rdi) ; SSE2-NEXT: retq ; @@ -2931,17 +2931,17 @@ define void @truncstore_v2i64_v2i8(<2 x i64> %x, ptr %p, <2 x i64> %mask) { ; SSE4-NEXT: movmskpd %xmm3, %eax ; SSE4-NEXT: xorl $3, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB8_1 -; SSE4-NEXT: # %bb.2: # %else -; SSE4-NEXT: testb $2, %al ; SSE4-NEXT: jne .LBB8_3 -; SSE4-NEXT: .LBB8_4: # %else2 +; SSE4-NEXT: # %bb.1: # %else +; SSE4-NEXT: testb $2, %al +; SSE4-NEXT: jne .LBB8_4 +; SSE4-NEXT: .LBB8_2: # %else2 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB8_1: # %cond.store +; SSE4-NEXT: .LBB8_3: # %cond.store ; SSE4-NEXT: pextrb $0, %xmm2, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB8_4 -; SSE4-NEXT: .LBB8_3: # %cond.store1 +; SSE4-NEXT: je .LBB8_2 +; SSE4-NEXT: .LBB8_4: # %cond.store1 ; SSE4-NEXT: pextrb $1, %xmm2, 1(%rdi) ; SSE4-NEXT: retq ; @@ -2959,17 +2959,17 @@ define void @truncstore_v2i64_v2i8(<2 x i64> %x, ptr %p, <2 x i64> %mask) { ; AVX-NEXT: vmovmskpd %xmm1, %eax ; AVX-NEXT: xorl $3, %eax ; AVX-NEXT: testb $1, %al -; AVX-NEXT: jne .LBB8_1 -; AVX-NEXT: # %bb.2: # %else -; AVX-NEXT: testb $2, %al ; AVX-NEXT: jne .LBB8_3 -; AVX-NEXT: .LBB8_4: # %else2 +; AVX-NEXT: # %bb.1: # %else +; AVX-NEXT: testb $2, %al +; AVX-NEXT: jne .LBB8_4 +; AVX-NEXT: .LBB8_2: # %else2 ; AVX-NEXT: retq -; AVX-NEXT: .LBB8_1: # %cond.store +; AVX-NEXT: .LBB8_3: # %cond.store ; AVX-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX-NEXT: testb $2, %al -; AVX-NEXT: je .LBB8_4 -; AVX-NEXT: .LBB8_3: # %cond.store1 +; AVX-NEXT: je .LBB8_2 +; AVX-NEXT: .LBB8_4: # %cond.store1 ; AVX-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX-NEXT: retq ; @@ -2981,18 +2981,18 @@ define void @truncstore_v2i64_v2i8(<2 x i64> %x, ptr %p, <2 x i64> %mask) { ; AVX512F-NEXT: vpmovsqb %zmm0, %xmm0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB8_1 -; AVX512F-NEXT: # %bb.2: # %else -; AVX512F-NEXT: testb $2, %al ; AVX512F-NEXT: jne .LBB8_3 -; AVX512F-NEXT: .LBB8_4: # %else2 +; AVX512F-NEXT: # %bb.1: # %else +; AVX512F-NEXT: testb $2, %al +; AVX512F-NEXT: jne .LBB8_4 +; AVX512F-NEXT: .LBB8_2: # %else2 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB8_1: # %cond.store +; AVX512F-NEXT: .LBB8_3: # %cond.store ; AVX512F-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB8_4 -; AVX512F-NEXT: .LBB8_3: # %cond.store1 +; AVX512F-NEXT: je .LBB8_2 +; AVX512F-NEXT: .LBB8_4: # %cond.store1 ; AVX512F-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -3003,17 +3003,17 @@ define void @truncstore_v2i64_v2i8(<2 x i64> %x, ptr %p, <2 x i64> %mask) { ; AVX512FVL-NEXT: vpmovsqb %xmm0, %xmm0 ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB8_1 -; AVX512FVL-NEXT: # %bb.2: # %else -; AVX512FVL-NEXT: testb $2, %al ; AVX512FVL-NEXT: jne .LBB8_3 -; AVX512FVL-NEXT: .LBB8_4: # %else2 +; AVX512FVL-NEXT: # %bb.1: # %else +; AVX512FVL-NEXT: testb $2, %al +; AVX512FVL-NEXT: jne .LBB8_4 +; AVX512FVL-NEXT: .LBB8_2: # %else2 ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB8_1: # %cond.store +; AVX512FVL-NEXT: .LBB8_3: # %cond.store ; AVX512FVL-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB8_4 -; AVX512FVL-NEXT: .LBB8_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB8_2 +; AVX512FVL-NEXT: .LBB8_4: # %cond.store1 ; AVX512FVL-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512FVL-NEXT: retq ; @@ -3059,130 +3059,130 @@ define void @truncstore_v16i32_v16i16(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; SSE2-NEXT: pmovmskb %xmm4, %eax ; SSE2-NEXT: xorl $65535, %eax # imm = 0xFFFF ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne .LBB9_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB9_18 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne .LBB9_3 -; SSE2-NEXT: .LBB9_4: # %else2 +; SSE2-NEXT: jne .LBB9_19 +; SSE2-NEXT: .LBB9_2: # %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne .LBB9_5 -; SSE2-NEXT: .LBB9_6: # %else4 +; SSE2-NEXT: jne .LBB9_20 +; SSE2-NEXT: .LBB9_3: # %else4 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne .LBB9_7 -; SSE2-NEXT: .LBB9_8: # %else6 +; SSE2-NEXT: jne .LBB9_21 +; SSE2-NEXT: .LBB9_4: # %else6 ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: jne .LBB9_9 -; SSE2-NEXT: .LBB9_10: # %else8 +; SSE2-NEXT: jne .LBB9_22 +; SSE2-NEXT: .LBB9_5: # %else8 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: jne .LBB9_11 -; SSE2-NEXT: .LBB9_12: # %else10 +; SSE2-NEXT: jne .LBB9_23 +; SSE2-NEXT: .LBB9_6: # %else10 ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: jne .LBB9_13 -; SSE2-NEXT: .LBB9_14: # %else12 +; SSE2-NEXT: jne .LBB9_24 +; SSE2-NEXT: .LBB9_7: # %else12 ; SSE2-NEXT: testb %al, %al -; SSE2-NEXT: jns .LBB9_16 -; SSE2-NEXT: .LBB9_15: # %cond.store13 +; SSE2-NEXT: jns .LBB9_9 +; SSE2-NEXT: .LBB9_8: # %cond.store13 ; SSE2-NEXT: pextrw $7, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 14(%rdi) -; SSE2-NEXT: .LBB9_16: # %else14 +; SSE2-NEXT: .LBB9_9: # %else14 ; SSE2-NEXT: packssdw %xmm3, %xmm2 ; SSE2-NEXT: testl $256, %eax # imm = 0x100 -; SSE2-NEXT: jne .LBB9_17 -; SSE2-NEXT: # %bb.18: # %else16 +; SSE2-NEXT: jne .LBB9_25 +; SSE2-NEXT: # %bb.10: # %else16 ; SSE2-NEXT: testl $512, %eax # imm = 0x200 -; SSE2-NEXT: jne .LBB9_19 -; SSE2-NEXT: .LBB9_20: # %else18 +; SSE2-NEXT: jne .LBB9_26 +; SSE2-NEXT: .LBB9_11: # %else18 ; SSE2-NEXT: testl $1024, %eax # imm = 0x400 -; SSE2-NEXT: jne .LBB9_21 -; SSE2-NEXT: .LBB9_22: # %else20 +; SSE2-NEXT: jne .LBB9_27 +; SSE2-NEXT: .LBB9_12: # %else20 ; SSE2-NEXT: testl $2048, %eax # imm = 0x800 -; SSE2-NEXT: jne .LBB9_23 -; SSE2-NEXT: .LBB9_24: # %else22 +; SSE2-NEXT: jne .LBB9_28 +; SSE2-NEXT: .LBB9_13: # %else22 ; SSE2-NEXT: testl $4096, %eax # imm = 0x1000 -; SSE2-NEXT: jne .LBB9_25 -; SSE2-NEXT: .LBB9_26: # %else24 +; SSE2-NEXT: jne .LBB9_29 +; SSE2-NEXT: .LBB9_14: # %else24 ; SSE2-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE2-NEXT: jne .LBB9_27 -; SSE2-NEXT: .LBB9_28: # %else26 +; SSE2-NEXT: jne .LBB9_30 +; SSE2-NEXT: .LBB9_15: # %else26 ; SSE2-NEXT: testl $16384, %eax # imm = 0x4000 -; SSE2-NEXT: jne .LBB9_29 -; SSE2-NEXT: .LBB9_30: # %else28 -; SSE2-NEXT: testl $32768, %eax # imm = 0x8000 ; SSE2-NEXT: jne .LBB9_31 -; SSE2-NEXT: .LBB9_32: # %else30 +; SSE2-NEXT: .LBB9_16: # %else28 +; SSE2-NEXT: testl $32768, %eax # imm = 0x8000 +; SSE2-NEXT: jne .LBB9_32 +; SSE2-NEXT: .LBB9_17: # %else30 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB9_1: # %cond.store +; SSE2-NEXT: .LBB9_18: # %cond.store ; SSE2-NEXT: movd %xmm0, %ecx ; SSE2-NEXT: movw %cx, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB9_4 -; SSE2-NEXT: .LBB9_3: # %cond.store1 +; SSE2-NEXT: je .LBB9_2 +; SSE2-NEXT: .LBB9_19: # %cond.store1 ; SSE2-NEXT: pextrw $1, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 2(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je .LBB9_6 -; SSE2-NEXT: .LBB9_5: # %cond.store3 +; SSE2-NEXT: je .LBB9_3 +; SSE2-NEXT: .LBB9_20: # %cond.store3 ; SSE2-NEXT: pextrw $2, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 4(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je .LBB9_8 -; SSE2-NEXT: .LBB9_7: # %cond.store5 +; SSE2-NEXT: je .LBB9_4 +; SSE2-NEXT: .LBB9_21: # %cond.store5 ; SSE2-NEXT: pextrw $3, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 6(%rdi) ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: je .LBB9_10 -; SSE2-NEXT: .LBB9_9: # %cond.store7 +; SSE2-NEXT: je .LBB9_5 +; SSE2-NEXT: .LBB9_22: # %cond.store7 ; SSE2-NEXT: pextrw $4, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 8(%rdi) ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je .LBB9_12 -; SSE2-NEXT: .LBB9_11: # %cond.store9 +; SSE2-NEXT: je .LBB9_6 +; SSE2-NEXT: .LBB9_23: # %cond.store9 ; SSE2-NEXT: pextrw $5, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 10(%rdi) ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: je .LBB9_14 -; SSE2-NEXT: .LBB9_13: # %cond.store11 +; SSE2-NEXT: je .LBB9_7 +; SSE2-NEXT: .LBB9_24: # %cond.store11 ; SSE2-NEXT: pextrw $6, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 12(%rdi) ; SSE2-NEXT: testb %al, %al -; SSE2-NEXT: js .LBB9_15 -; SSE2-NEXT: jmp .LBB9_16 -; SSE2-NEXT: .LBB9_17: # %cond.store15 +; SSE2-NEXT: js .LBB9_8 +; SSE2-NEXT: jmp .LBB9_9 +; SSE2-NEXT: .LBB9_25: # %cond.store15 ; SSE2-NEXT: movd %xmm2, %ecx ; SSE2-NEXT: movw %cx, 16(%rdi) ; SSE2-NEXT: testl $512, %eax # imm = 0x200 -; SSE2-NEXT: je .LBB9_20 -; SSE2-NEXT: .LBB9_19: # %cond.store17 +; SSE2-NEXT: je .LBB9_11 +; SSE2-NEXT: .LBB9_26: # %cond.store17 ; SSE2-NEXT: pextrw $1, %xmm2, %ecx ; SSE2-NEXT: movw %cx, 18(%rdi) ; SSE2-NEXT: testl $1024, %eax # imm = 0x400 -; SSE2-NEXT: je .LBB9_22 -; SSE2-NEXT: .LBB9_21: # %cond.store19 +; SSE2-NEXT: je .LBB9_12 +; SSE2-NEXT: .LBB9_27: # %cond.store19 ; SSE2-NEXT: pextrw $2, %xmm2, %ecx ; SSE2-NEXT: movw %cx, 20(%rdi) ; SSE2-NEXT: testl $2048, %eax # imm = 0x800 -; SSE2-NEXT: je .LBB9_24 -; SSE2-NEXT: .LBB9_23: # %cond.store21 +; SSE2-NEXT: je .LBB9_13 +; SSE2-NEXT: .LBB9_28: # %cond.store21 ; SSE2-NEXT: pextrw $3, %xmm2, %ecx ; SSE2-NEXT: movw %cx, 22(%rdi) ; SSE2-NEXT: testl $4096, %eax # imm = 0x1000 -; SSE2-NEXT: je .LBB9_26 -; SSE2-NEXT: .LBB9_25: # %cond.store23 +; SSE2-NEXT: je .LBB9_14 +; SSE2-NEXT: .LBB9_29: # %cond.store23 ; SSE2-NEXT: pextrw $4, %xmm2, %ecx ; SSE2-NEXT: movw %cx, 24(%rdi) ; SSE2-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE2-NEXT: je .LBB9_28 -; SSE2-NEXT: .LBB9_27: # %cond.store25 +; SSE2-NEXT: je .LBB9_15 +; SSE2-NEXT: .LBB9_30: # %cond.store25 ; SSE2-NEXT: pextrw $5, %xmm2, %ecx ; SSE2-NEXT: movw %cx, 26(%rdi) ; SSE2-NEXT: testl $16384, %eax # imm = 0x4000 -; SSE2-NEXT: je .LBB9_30 -; SSE2-NEXT: .LBB9_29: # %cond.store27 +; SSE2-NEXT: je .LBB9_16 +; SSE2-NEXT: .LBB9_31: # %cond.store27 ; SSE2-NEXT: pextrw $6, %xmm2, %ecx ; SSE2-NEXT: movw %cx, 28(%rdi) ; SSE2-NEXT: testl $32768, %eax # imm = 0x8000 -; SSE2-NEXT: je .LBB9_32 -; SSE2-NEXT: .LBB9_31: # %cond.store29 +; SSE2-NEXT: je .LBB9_17 +; SSE2-NEXT: .LBB9_32: # %cond.store29 ; SSE2-NEXT: pextrw $7, %xmm2, %eax ; SSE2-NEXT: movw %ax, 30(%rdi) ; SSE2-NEXT: retq @@ -3201,115 +3201,115 @@ define void @truncstore_v16i32_v16i16(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; SSE4-NEXT: pmovmskb %xmm4, %eax ; SSE4-NEXT: xorl $65535, %eax # imm = 0xFFFF ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB9_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB9_18 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB9_3 -; SSE4-NEXT: .LBB9_4: # %else2 +; SSE4-NEXT: jne .LBB9_19 +; SSE4-NEXT: .LBB9_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB9_5 -; SSE4-NEXT: .LBB9_6: # %else4 +; SSE4-NEXT: jne .LBB9_20 +; SSE4-NEXT: .LBB9_3: # %else4 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne .LBB9_7 -; SSE4-NEXT: .LBB9_8: # %else6 +; SSE4-NEXT: jne .LBB9_21 +; SSE4-NEXT: .LBB9_4: # %else6 ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: jne .LBB9_9 -; SSE4-NEXT: .LBB9_10: # %else8 +; SSE4-NEXT: jne .LBB9_22 +; SSE4-NEXT: .LBB9_5: # %else8 ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: jne .LBB9_11 -; SSE4-NEXT: .LBB9_12: # %else10 +; SSE4-NEXT: jne .LBB9_23 +; SSE4-NEXT: .LBB9_6: # %else10 ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: jne .LBB9_13 -; SSE4-NEXT: .LBB9_14: # %else12 +; SSE4-NEXT: jne .LBB9_24 +; SSE4-NEXT: .LBB9_7: # %else12 ; SSE4-NEXT: testb %al, %al -; SSE4-NEXT: jns .LBB9_16 -; SSE4-NEXT: .LBB9_15: # %cond.store13 +; SSE4-NEXT: jns .LBB9_9 +; SSE4-NEXT: .LBB9_8: # %cond.store13 ; SSE4-NEXT: pextrw $7, %xmm0, 14(%rdi) -; SSE4-NEXT: .LBB9_16: # %else14 +; SSE4-NEXT: .LBB9_9: # %else14 ; SSE4-NEXT: packssdw %xmm3, %xmm2 ; SSE4-NEXT: testl $256, %eax # imm = 0x100 -; SSE4-NEXT: jne .LBB9_17 -; SSE4-NEXT: # %bb.18: # %else16 +; SSE4-NEXT: jne .LBB9_25 +; SSE4-NEXT: # %bb.10: # %else16 ; SSE4-NEXT: testl $512, %eax # imm = 0x200 -; SSE4-NEXT: jne .LBB9_19 -; SSE4-NEXT: .LBB9_20: # %else18 +; SSE4-NEXT: jne .LBB9_26 +; SSE4-NEXT: .LBB9_11: # %else18 ; SSE4-NEXT: testl $1024, %eax # imm = 0x400 -; SSE4-NEXT: jne .LBB9_21 -; SSE4-NEXT: .LBB9_22: # %else20 +; SSE4-NEXT: jne .LBB9_27 +; SSE4-NEXT: .LBB9_12: # %else20 ; SSE4-NEXT: testl $2048, %eax # imm = 0x800 -; SSE4-NEXT: jne .LBB9_23 -; SSE4-NEXT: .LBB9_24: # %else22 +; SSE4-NEXT: jne .LBB9_28 +; SSE4-NEXT: .LBB9_13: # %else22 ; SSE4-NEXT: testl $4096, %eax # imm = 0x1000 -; SSE4-NEXT: jne .LBB9_25 -; SSE4-NEXT: .LBB9_26: # %else24 +; SSE4-NEXT: jne .LBB9_29 +; SSE4-NEXT: .LBB9_14: # %else24 ; SSE4-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE4-NEXT: jne .LBB9_27 -; SSE4-NEXT: .LBB9_28: # %else26 +; SSE4-NEXT: jne .LBB9_30 +; SSE4-NEXT: .LBB9_15: # %else26 ; SSE4-NEXT: testl $16384, %eax # imm = 0x4000 -; SSE4-NEXT: jne .LBB9_29 -; SSE4-NEXT: .LBB9_30: # %else28 -; SSE4-NEXT: testl $32768, %eax # imm = 0x8000 ; SSE4-NEXT: jne .LBB9_31 -; SSE4-NEXT: .LBB9_32: # %else30 +; SSE4-NEXT: .LBB9_16: # %else28 +; SSE4-NEXT: testl $32768, %eax # imm = 0x8000 +; SSE4-NEXT: jne .LBB9_32 +; SSE4-NEXT: .LBB9_17: # %else30 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB9_1: # %cond.store +; SSE4-NEXT: .LBB9_18: # %cond.store ; SSE4-NEXT: pextrw $0, %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB9_4 -; SSE4-NEXT: .LBB9_3: # %cond.store1 +; SSE4-NEXT: je .LBB9_2 +; SSE4-NEXT: .LBB9_19: # %cond.store1 ; SSE4-NEXT: pextrw $1, %xmm0, 2(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB9_6 -; SSE4-NEXT: .LBB9_5: # %cond.store3 +; SSE4-NEXT: je .LBB9_3 +; SSE4-NEXT: .LBB9_20: # %cond.store3 ; SSE4-NEXT: pextrw $2, %xmm0, 4(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB9_8 -; SSE4-NEXT: .LBB9_7: # %cond.store5 +; SSE4-NEXT: je .LBB9_4 +; SSE4-NEXT: .LBB9_21: # %cond.store5 ; SSE4-NEXT: pextrw $3, %xmm0, 6(%rdi) ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: je .LBB9_10 -; SSE4-NEXT: .LBB9_9: # %cond.store7 +; SSE4-NEXT: je .LBB9_5 +; SSE4-NEXT: .LBB9_22: # %cond.store7 ; SSE4-NEXT: pextrw $4, %xmm0, 8(%rdi) ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: je .LBB9_12 -; SSE4-NEXT: .LBB9_11: # %cond.store9 +; SSE4-NEXT: je .LBB9_6 +; SSE4-NEXT: .LBB9_23: # %cond.store9 ; SSE4-NEXT: pextrw $5, %xmm0, 10(%rdi) ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: je .LBB9_14 -; SSE4-NEXT: .LBB9_13: # %cond.store11 +; SSE4-NEXT: je .LBB9_7 +; SSE4-NEXT: .LBB9_24: # %cond.store11 ; SSE4-NEXT: pextrw $6, %xmm0, 12(%rdi) ; SSE4-NEXT: testb %al, %al -; SSE4-NEXT: js .LBB9_15 -; SSE4-NEXT: jmp .LBB9_16 -; SSE4-NEXT: .LBB9_17: # %cond.store15 +; SSE4-NEXT: js .LBB9_8 +; SSE4-NEXT: jmp .LBB9_9 +; SSE4-NEXT: .LBB9_25: # %cond.store15 ; SSE4-NEXT: pextrw $0, %xmm2, 16(%rdi) ; SSE4-NEXT: testl $512, %eax # imm = 0x200 -; SSE4-NEXT: je .LBB9_20 -; SSE4-NEXT: .LBB9_19: # %cond.store17 +; SSE4-NEXT: je .LBB9_11 +; SSE4-NEXT: .LBB9_26: # %cond.store17 ; SSE4-NEXT: pextrw $1, %xmm2, 18(%rdi) ; SSE4-NEXT: testl $1024, %eax # imm = 0x400 -; SSE4-NEXT: je .LBB9_22 -; SSE4-NEXT: .LBB9_21: # %cond.store19 +; SSE4-NEXT: je .LBB9_12 +; SSE4-NEXT: .LBB9_27: # %cond.store19 ; SSE4-NEXT: pextrw $2, %xmm2, 20(%rdi) ; SSE4-NEXT: testl $2048, %eax # imm = 0x800 -; SSE4-NEXT: je .LBB9_24 -; SSE4-NEXT: .LBB9_23: # %cond.store21 +; SSE4-NEXT: je .LBB9_13 +; SSE4-NEXT: .LBB9_28: # %cond.store21 ; SSE4-NEXT: pextrw $3, %xmm2, 22(%rdi) ; SSE4-NEXT: testl $4096, %eax # imm = 0x1000 -; SSE4-NEXT: je .LBB9_26 -; SSE4-NEXT: .LBB9_25: # %cond.store23 +; SSE4-NEXT: je .LBB9_14 +; SSE4-NEXT: .LBB9_29: # %cond.store23 ; SSE4-NEXT: pextrw $4, %xmm2, 24(%rdi) ; SSE4-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE4-NEXT: je .LBB9_28 -; SSE4-NEXT: .LBB9_27: # %cond.store25 +; SSE4-NEXT: je .LBB9_15 +; SSE4-NEXT: .LBB9_30: # %cond.store25 ; SSE4-NEXT: pextrw $5, %xmm2, 26(%rdi) ; SSE4-NEXT: testl $16384, %eax # imm = 0x4000 -; SSE4-NEXT: je .LBB9_30 -; SSE4-NEXT: .LBB9_29: # %cond.store27 +; SSE4-NEXT: je .LBB9_16 +; SSE4-NEXT: .LBB9_31: # %cond.store27 ; SSE4-NEXT: pextrw $6, %xmm2, 28(%rdi) ; SSE4-NEXT: testl $32768, %eax # imm = 0x8000 -; SSE4-NEXT: je .LBB9_32 -; SSE4-NEXT: .LBB9_31: # %cond.store29 +; SSE4-NEXT: je .LBB9_17 +; SSE4-NEXT: .LBB9_32: # %cond.store29 ; SSE4-NEXT: pextrw $7, %xmm2, 30(%rdi) ; SSE4-NEXT: retq ; @@ -3333,116 +3333,116 @@ define void @truncstore_v16i32_v16i16(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; AVX1-NEXT: vpmovmskb %xmm1, %eax ; AVX1-NEXT: xorl $65535, %eax # imm = 0xFFFF ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne .LBB9_1 -; AVX1-NEXT: # %bb.2: # %else +; AVX1-NEXT: jne .LBB9_18 +; AVX1-NEXT: # %bb.1: # %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne .LBB9_3 -; AVX1-NEXT: .LBB9_4: # %else2 +; AVX1-NEXT: jne .LBB9_19 +; AVX1-NEXT: .LBB9_2: # %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne .LBB9_5 -; AVX1-NEXT: .LBB9_6: # %else4 +; AVX1-NEXT: jne .LBB9_20 +; AVX1-NEXT: .LBB9_3: # %else4 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne .LBB9_7 -; AVX1-NEXT: .LBB9_8: # %else6 +; AVX1-NEXT: jne .LBB9_21 +; AVX1-NEXT: .LBB9_4: # %else6 ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: jne .LBB9_9 -; AVX1-NEXT: .LBB9_10: # %else8 +; AVX1-NEXT: jne .LBB9_22 +; AVX1-NEXT: .LBB9_5: # %else8 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: jne .LBB9_11 -; AVX1-NEXT: .LBB9_12: # %else10 +; AVX1-NEXT: jne .LBB9_23 +; AVX1-NEXT: .LBB9_6: # %else10 ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: jne .LBB9_13 -; AVX1-NEXT: .LBB9_14: # %else12 +; AVX1-NEXT: jne .LBB9_24 +; AVX1-NEXT: .LBB9_7: # %else12 ; AVX1-NEXT: testb %al, %al -; AVX1-NEXT: jns .LBB9_16 -; AVX1-NEXT: .LBB9_15: # %cond.store13 +; AVX1-NEXT: jns .LBB9_9 +; AVX1-NEXT: .LBB9_8: # %cond.store13 ; AVX1-NEXT: vpextrw $7, %xmm0, 14(%rdi) -; AVX1-NEXT: .LBB9_16: # %else14 +; AVX1-NEXT: .LBB9_9: # %else14 ; AVX1-NEXT: testl $256, %eax # imm = 0x100 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 -; AVX1-NEXT: jne .LBB9_17 -; AVX1-NEXT: # %bb.18: # %else16 +; AVX1-NEXT: jne .LBB9_25 +; AVX1-NEXT: # %bb.10: # %else16 ; AVX1-NEXT: testl $512, %eax # imm = 0x200 -; AVX1-NEXT: jne .LBB9_19 -; AVX1-NEXT: .LBB9_20: # %else18 +; AVX1-NEXT: jne .LBB9_26 +; AVX1-NEXT: .LBB9_11: # %else18 ; AVX1-NEXT: testl $1024, %eax # imm = 0x400 -; AVX1-NEXT: jne .LBB9_21 -; AVX1-NEXT: .LBB9_22: # %else20 +; AVX1-NEXT: jne .LBB9_27 +; AVX1-NEXT: .LBB9_12: # %else20 ; AVX1-NEXT: testl $2048, %eax # imm = 0x800 -; AVX1-NEXT: jne .LBB9_23 -; AVX1-NEXT: .LBB9_24: # %else22 +; AVX1-NEXT: jne .LBB9_28 +; AVX1-NEXT: .LBB9_13: # %else22 ; AVX1-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX1-NEXT: jne .LBB9_25 -; AVX1-NEXT: .LBB9_26: # %else24 +; AVX1-NEXT: jne .LBB9_29 +; AVX1-NEXT: .LBB9_14: # %else24 ; AVX1-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX1-NEXT: jne .LBB9_27 -; AVX1-NEXT: .LBB9_28: # %else26 +; AVX1-NEXT: jne .LBB9_30 +; AVX1-NEXT: .LBB9_15: # %else26 ; AVX1-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX1-NEXT: jne .LBB9_29 -; AVX1-NEXT: .LBB9_30: # %else28 -; AVX1-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX1-NEXT: jne .LBB9_31 -; AVX1-NEXT: .LBB9_32: # %else30 +; AVX1-NEXT: .LBB9_16: # %else28 +; AVX1-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX1-NEXT: jne .LBB9_32 +; AVX1-NEXT: .LBB9_17: # %else30 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB9_1: # %cond.store +; AVX1-NEXT: .LBB9_18: # %cond.store ; AVX1-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je .LBB9_4 -; AVX1-NEXT: .LBB9_3: # %cond.store1 +; AVX1-NEXT: je .LBB9_2 +; AVX1-NEXT: .LBB9_19: # %cond.store1 ; AVX1-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je .LBB9_6 -; AVX1-NEXT: .LBB9_5: # %cond.store3 +; AVX1-NEXT: je .LBB9_3 +; AVX1-NEXT: .LBB9_20: # %cond.store3 ; AVX1-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB9_8 -; AVX1-NEXT: .LBB9_7: # %cond.store5 +; AVX1-NEXT: je .LBB9_4 +; AVX1-NEXT: .LBB9_21: # %cond.store5 ; AVX1-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: je .LBB9_10 -; AVX1-NEXT: .LBB9_9: # %cond.store7 +; AVX1-NEXT: je .LBB9_5 +; AVX1-NEXT: .LBB9_22: # %cond.store7 ; AVX1-NEXT: vpextrw $4, %xmm0, 8(%rdi) ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je .LBB9_12 -; AVX1-NEXT: .LBB9_11: # %cond.store9 +; AVX1-NEXT: je .LBB9_6 +; AVX1-NEXT: .LBB9_23: # %cond.store9 ; AVX1-NEXT: vpextrw $5, %xmm0, 10(%rdi) ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: je .LBB9_14 -; AVX1-NEXT: .LBB9_13: # %cond.store11 +; AVX1-NEXT: je .LBB9_7 +; AVX1-NEXT: .LBB9_24: # %cond.store11 ; AVX1-NEXT: vpextrw $6, %xmm0, 12(%rdi) ; AVX1-NEXT: testb %al, %al -; AVX1-NEXT: js .LBB9_15 -; AVX1-NEXT: jmp .LBB9_16 -; AVX1-NEXT: .LBB9_17: # %cond.store15 +; AVX1-NEXT: js .LBB9_8 +; AVX1-NEXT: jmp .LBB9_9 +; AVX1-NEXT: .LBB9_25: # %cond.store15 ; AVX1-NEXT: vpextrw $0, %xmm0, 16(%rdi) ; AVX1-NEXT: testl $512, %eax # imm = 0x200 -; AVX1-NEXT: je .LBB9_20 -; AVX1-NEXT: .LBB9_19: # %cond.store17 +; AVX1-NEXT: je .LBB9_11 +; AVX1-NEXT: .LBB9_26: # %cond.store17 ; AVX1-NEXT: vpextrw $1, %xmm0, 18(%rdi) ; AVX1-NEXT: testl $1024, %eax # imm = 0x400 -; AVX1-NEXT: je .LBB9_22 -; AVX1-NEXT: .LBB9_21: # %cond.store19 +; AVX1-NEXT: je .LBB9_12 +; AVX1-NEXT: .LBB9_27: # %cond.store19 ; AVX1-NEXT: vpextrw $2, %xmm0, 20(%rdi) ; AVX1-NEXT: testl $2048, %eax # imm = 0x800 -; AVX1-NEXT: je .LBB9_24 -; AVX1-NEXT: .LBB9_23: # %cond.store21 +; AVX1-NEXT: je .LBB9_13 +; AVX1-NEXT: .LBB9_28: # %cond.store21 ; AVX1-NEXT: vpextrw $3, %xmm0, 22(%rdi) ; AVX1-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX1-NEXT: je .LBB9_26 -; AVX1-NEXT: .LBB9_25: # %cond.store23 +; AVX1-NEXT: je .LBB9_14 +; AVX1-NEXT: .LBB9_29: # %cond.store23 ; AVX1-NEXT: vpextrw $4, %xmm0, 24(%rdi) ; AVX1-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX1-NEXT: je .LBB9_28 -; AVX1-NEXT: .LBB9_27: # %cond.store25 +; AVX1-NEXT: je .LBB9_15 +; AVX1-NEXT: .LBB9_30: # %cond.store25 ; AVX1-NEXT: vpextrw $5, %xmm0, 26(%rdi) ; AVX1-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX1-NEXT: je .LBB9_30 -; AVX1-NEXT: .LBB9_29: # %cond.store27 +; AVX1-NEXT: je .LBB9_16 +; AVX1-NEXT: .LBB9_31: # %cond.store27 ; AVX1-NEXT: vpextrw $6, %xmm0, 28(%rdi) ; AVX1-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX1-NEXT: je .LBB9_32 -; AVX1-NEXT: .LBB9_31: # %cond.store29 +; AVX1-NEXT: je .LBB9_17 +; AVX1-NEXT: .LBB9_32: # %cond.store29 ; AVX1-NEXT: vpextrw $7, %xmm0, 30(%rdi) ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq @@ -3462,116 +3462,116 @@ define void @truncstore_v16i32_v16i16(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,2,1,3] ; AVX2-NEXT: vpmovmskb %xmm1, %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne .LBB9_1 -; AVX2-NEXT: # %bb.2: # %else +; AVX2-NEXT: jne .LBB9_18 +; AVX2-NEXT: # %bb.1: # %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne .LBB9_3 -; AVX2-NEXT: .LBB9_4: # %else2 +; AVX2-NEXT: jne .LBB9_19 +; AVX2-NEXT: .LBB9_2: # %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne .LBB9_5 -; AVX2-NEXT: .LBB9_6: # %else4 +; AVX2-NEXT: jne .LBB9_20 +; AVX2-NEXT: .LBB9_3: # %else4 ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: jne .LBB9_7 -; AVX2-NEXT: .LBB9_8: # %else6 +; AVX2-NEXT: jne .LBB9_21 +; AVX2-NEXT: .LBB9_4: # %else6 ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: jne .LBB9_9 -; AVX2-NEXT: .LBB9_10: # %else8 +; AVX2-NEXT: jne .LBB9_22 +; AVX2-NEXT: .LBB9_5: # %else8 ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: jne .LBB9_11 -; AVX2-NEXT: .LBB9_12: # %else10 +; AVX2-NEXT: jne .LBB9_23 +; AVX2-NEXT: .LBB9_6: # %else10 ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: jne .LBB9_13 -; AVX2-NEXT: .LBB9_14: # %else12 +; AVX2-NEXT: jne .LBB9_24 +; AVX2-NEXT: .LBB9_7: # %else12 ; AVX2-NEXT: testb %al, %al -; AVX2-NEXT: jns .LBB9_16 -; AVX2-NEXT: .LBB9_15: # %cond.store13 +; AVX2-NEXT: jns .LBB9_9 +; AVX2-NEXT: .LBB9_8: # %cond.store13 ; AVX2-NEXT: vpextrw $7, %xmm0, 14(%rdi) -; AVX2-NEXT: .LBB9_16: # %else14 +; AVX2-NEXT: .LBB9_9: # %else14 ; AVX2-NEXT: testl $256, %eax # imm = 0x100 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0 -; AVX2-NEXT: jne .LBB9_17 -; AVX2-NEXT: # %bb.18: # %else16 +; AVX2-NEXT: jne .LBB9_25 +; AVX2-NEXT: # %bb.10: # %else16 ; AVX2-NEXT: testl $512, %eax # imm = 0x200 -; AVX2-NEXT: jne .LBB9_19 -; AVX2-NEXT: .LBB9_20: # %else18 +; AVX2-NEXT: jne .LBB9_26 +; AVX2-NEXT: .LBB9_11: # %else18 ; AVX2-NEXT: testl $1024, %eax # imm = 0x400 -; AVX2-NEXT: jne .LBB9_21 -; AVX2-NEXT: .LBB9_22: # %else20 +; AVX2-NEXT: jne .LBB9_27 +; AVX2-NEXT: .LBB9_12: # %else20 ; AVX2-NEXT: testl $2048, %eax # imm = 0x800 -; AVX2-NEXT: jne .LBB9_23 -; AVX2-NEXT: .LBB9_24: # %else22 +; AVX2-NEXT: jne .LBB9_28 +; AVX2-NEXT: .LBB9_13: # %else22 ; AVX2-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX2-NEXT: jne .LBB9_25 -; AVX2-NEXT: .LBB9_26: # %else24 +; AVX2-NEXT: jne .LBB9_29 +; AVX2-NEXT: .LBB9_14: # %else24 ; AVX2-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX2-NEXT: jne .LBB9_27 -; AVX2-NEXT: .LBB9_28: # %else26 +; AVX2-NEXT: jne .LBB9_30 +; AVX2-NEXT: .LBB9_15: # %else26 ; AVX2-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX2-NEXT: jne .LBB9_29 -; AVX2-NEXT: .LBB9_30: # %else28 -; AVX2-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX2-NEXT: jne .LBB9_31 -; AVX2-NEXT: .LBB9_32: # %else30 +; AVX2-NEXT: .LBB9_16: # %else28 +; AVX2-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX2-NEXT: jne .LBB9_32 +; AVX2-NEXT: .LBB9_17: # %else30 ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; AVX2-NEXT: .LBB9_1: # %cond.store +; AVX2-NEXT: .LBB9_18: # %cond.store ; AVX2-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je .LBB9_4 -; AVX2-NEXT: .LBB9_3: # %cond.store1 +; AVX2-NEXT: je .LBB9_2 +; AVX2-NEXT: .LBB9_19: # %cond.store1 ; AVX2-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je .LBB9_6 -; AVX2-NEXT: .LBB9_5: # %cond.store3 +; AVX2-NEXT: je .LBB9_3 +; AVX2-NEXT: .LBB9_20: # %cond.store3 ; AVX2-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je .LBB9_8 -; AVX2-NEXT: .LBB9_7: # %cond.store5 +; AVX2-NEXT: je .LBB9_4 +; AVX2-NEXT: .LBB9_21: # %cond.store5 ; AVX2-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: je .LBB9_10 -; AVX2-NEXT: .LBB9_9: # %cond.store7 +; AVX2-NEXT: je .LBB9_5 +; AVX2-NEXT: .LBB9_22: # %cond.store7 ; AVX2-NEXT: vpextrw $4, %xmm0, 8(%rdi) ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: je .LBB9_12 -; AVX2-NEXT: .LBB9_11: # %cond.store9 +; AVX2-NEXT: je .LBB9_6 +; AVX2-NEXT: .LBB9_23: # %cond.store9 ; AVX2-NEXT: vpextrw $5, %xmm0, 10(%rdi) ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: je .LBB9_14 -; AVX2-NEXT: .LBB9_13: # %cond.store11 +; AVX2-NEXT: je .LBB9_7 +; AVX2-NEXT: .LBB9_24: # %cond.store11 ; AVX2-NEXT: vpextrw $6, %xmm0, 12(%rdi) ; AVX2-NEXT: testb %al, %al -; AVX2-NEXT: js .LBB9_15 -; AVX2-NEXT: jmp .LBB9_16 -; AVX2-NEXT: .LBB9_17: # %cond.store15 +; AVX2-NEXT: js .LBB9_8 +; AVX2-NEXT: jmp .LBB9_9 +; AVX2-NEXT: .LBB9_25: # %cond.store15 ; AVX2-NEXT: vpextrw $0, %xmm0, 16(%rdi) ; AVX2-NEXT: testl $512, %eax # imm = 0x200 -; AVX2-NEXT: je .LBB9_20 -; AVX2-NEXT: .LBB9_19: # %cond.store17 +; AVX2-NEXT: je .LBB9_11 +; AVX2-NEXT: .LBB9_26: # %cond.store17 ; AVX2-NEXT: vpextrw $1, %xmm0, 18(%rdi) ; AVX2-NEXT: testl $1024, %eax # imm = 0x400 -; AVX2-NEXT: je .LBB9_22 -; AVX2-NEXT: .LBB9_21: # %cond.store19 +; AVX2-NEXT: je .LBB9_12 +; AVX2-NEXT: .LBB9_27: # %cond.store19 ; AVX2-NEXT: vpextrw $2, %xmm0, 20(%rdi) ; AVX2-NEXT: testl $2048, %eax # imm = 0x800 -; AVX2-NEXT: je .LBB9_24 -; AVX2-NEXT: .LBB9_23: # %cond.store21 +; AVX2-NEXT: je .LBB9_13 +; AVX2-NEXT: .LBB9_28: # %cond.store21 ; AVX2-NEXT: vpextrw $3, %xmm0, 22(%rdi) ; AVX2-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX2-NEXT: je .LBB9_26 -; AVX2-NEXT: .LBB9_25: # %cond.store23 +; AVX2-NEXT: je .LBB9_14 +; AVX2-NEXT: .LBB9_29: # %cond.store23 ; AVX2-NEXT: vpextrw $4, %xmm0, 24(%rdi) ; AVX2-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX2-NEXT: je .LBB9_28 -; AVX2-NEXT: .LBB9_27: # %cond.store25 +; AVX2-NEXT: je .LBB9_15 +; AVX2-NEXT: .LBB9_30: # %cond.store25 ; AVX2-NEXT: vpextrw $5, %xmm0, 26(%rdi) ; AVX2-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX2-NEXT: je .LBB9_30 -; AVX2-NEXT: .LBB9_29: # %cond.store27 +; AVX2-NEXT: je .LBB9_16 +; AVX2-NEXT: .LBB9_31: # %cond.store27 ; AVX2-NEXT: vpextrw $6, %xmm0, 28(%rdi) ; AVX2-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX2-NEXT: je .LBB9_32 -; AVX2-NEXT: .LBB9_31: # %cond.store29 +; AVX2-NEXT: je .LBB9_17 +; AVX2-NEXT: .LBB9_32: # %cond.store29 ; AVX2-NEXT: vpextrw $7, %xmm0, 30(%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq @@ -3582,116 +3582,116 @@ define void @truncstore_v16i32_v16i16(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; AVX512F-NEXT: vpmovsdw %zmm0, %ymm0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB9_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB9_18 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB9_3 -; AVX512F-NEXT: .LBB9_4: # %else2 +; AVX512F-NEXT: jne .LBB9_19 +; AVX512F-NEXT: .LBB9_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB9_5 -; AVX512F-NEXT: .LBB9_6: # %else4 +; AVX512F-NEXT: jne .LBB9_20 +; AVX512F-NEXT: .LBB9_3: # %else4 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne .LBB9_7 -; AVX512F-NEXT: .LBB9_8: # %else6 +; AVX512F-NEXT: jne .LBB9_21 +; AVX512F-NEXT: .LBB9_4: # %else6 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne .LBB9_9 -; AVX512F-NEXT: .LBB9_10: # %else8 +; AVX512F-NEXT: jne .LBB9_22 +; AVX512F-NEXT: .LBB9_5: # %else8 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne .LBB9_11 -; AVX512F-NEXT: .LBB9_12: # %else10 +; AVX512F-NEXT: jne .LBB9_23 +; AVX512F-NEXT: .LBB9_6: # %else10 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne .LBB9_13 -; AVX512F-NEXT: .LBB9_14: # %else12 +; AVX512F-NEXT: jne .LBB9_24 +; AVX512F-NEXT: .LBB9_7: # %else12 ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: jns .LBB9_16 -; AVX512F-NEXT: .LBB9_15: # %cond.store13 +; AVX512F-NEXT: jns .LBB9_9 +; AVX512F-NEXT: .LBB9_8: # %cond.store13 ; AVX512F-NEXT: vpextrw $7, %xmm0, 14(%rdi) -; AVX512F-NEXT: .LBB9_16: # %else14 +; AVX512F-NEXT: .LBB9_9: # %else14 ; AVX512F-NEXT: testl $256, %eax # imm = 0x100 ; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm0 -; AVX512F-NEXT: jne .LBB9_17 -; AVX512F-NEXT: # %bb.18: # %else16 +; AVX512F-NEXT: jne .LBB9_25 +; AVX512F-NEXT: # %bb.10: # %else16 ; AVX512F-NEXT: testl $512, %eax # imm = 0x200 -; AVX512F-NEXT: jne .LBB9_19 -; AVX512F-NEXT: .LBB9_20: # %else18 +; AVX512F-NEXT: jne .LBB9_26 +; AVX512F-NEXT: .LBB9_11: # %else18 ; AVX512F-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512F-NEXT: jne .LBB9_21 -; AVX512F-NEXT: .LBB9_22: # %else20 +; AVX512F-NEXT: jne .LBB9_27 +; AVX512F-NEXT: .LBB9_12: # %else20 ; AVX512F-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512F-NEXT: jne .LBB9_23 -; AVX512F-NEXT: .LBB9_24: # %else22 +; AVX512F-NEXT: jne .LBB9_28 +; AVX512F-NEXT: .LBB9_13: # %else22 ; AVX512F-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512F-NEXT: jne .LBB9_25 -; AVX512F-NEXT: .LBB9_26: # %else24 +; AVX512F-NEXT: jne .LBB9_29 +; AVX512F-NEXT: .LBB9_14: # %else24 ; AVX512F-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512F-NEXT: jne .LBB9_27 -; AVX512F-NEXT: .LBB9_28: # %else26 +; AVX512F-NEXT: jne .LBB9_30 +; AVX512F-NEXT: .LBB9_15: # %else26 ; AVX512F-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512F-NEXT: jne .LBB9_29 -; AVX512F-NEXT: .LBB9_30: # %else28 -; AVX512F-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX512F-NEXT: jne .LBB9_31 -; AVX512F-NEXT: .LBB9_32: # %else30 +; AVX512F-NEXT: .LBB9_16: # %else28 +; AVX512F-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX512F-NEXT: jne .LBB9_32 +; AVX512F-NEXT: .LBB9_17: # %else30 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB9_1: # %cond.store +; AVX512F-NEXT: .LBB9_18: # %cond.store ; AVX512F-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB9_4 -; AVX512F-NEXT: .LBB9_3: # %cond.store1 +; AVX512F-NEXT: je .LBB9_2 +; AVX512F-NEXT: .LBB9_19: # %cond.store1 ; AVX512F-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB9_6 -; AVX512F-NEXT: .LBB9_5: # %cond.store3 +; AVX512F-NEXT: je .LBB9_3 +; AVX512F-NEXT: .LBB9_20: # %cond.store3 ; AVX512F-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB9_8 -; AVX512F-NEXT: .LBB9_7: # %cond.store5 +; AVX512F-NEXT: je .LBB9_4 +; AVX512F-NEXT: .LBB9_21: # %cond.store5 ; AVX512F-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je .LBB9_10 -; AVX512F-NEXT: .LBB9_9: # %cond.store7 +; AVX512F-NEXT: je .LBB9_5 +; AVX512F-NEXT: .LBB9_22: # %cond.store7 ; AVX512F-NEXT: vpextrw $4, %xmm0, 8(%rdi) ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je .LBB9_12 -; AVX512F-NEXT: .LBB9_11: # %cond.store9 +; AVX512F-NEXT: je .LBB9_6 +; AVX512F-NEXT: .LBB9_23: # %cond.store9 ; AVX512F-NEXT: vpextrw $5, %xmm0, 10(%rdi) ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je .LBB9_14 -; AVX512F-NEXT: .LBB9_13: # %cond.store11 +; AVX512F-NEXT: je .LBB9_7 +; AVX512F-NEXT: .LBB9_24: # %cond.store11 ; AVX512F-NEXT: vpextrw $6, %xmm0, 12(%rdi) ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: js .LBB9_15 -; AVX512F-NEXT: jmp .LBB9_16 -; AVX512F-NEXT: .LBB9_17: # %cond.store15 +; AVX512F-NEXT: js .LBB9_8 +; AVX512F-NEXT: jmp .LBB9_9 +; AVX512F-NEXT: .LBB9_25: # %cond.store15 ; AVX512F-NEXT: vpextrw $0, %xmm0, 16(%rdi) ; AVX512F-NEXT: testl $512, %eax # imm = 0x200 -; AVX512F-NEXT: je .LBB9_20 -; AVX512F-NEXT: .LBB9_19: # %cond.store17 +; AVX512F-NEXT: je .LBB9_11 +; AVX512F-NEXT: .LBB9_26: # %cond.store17 ; AVX512F-NEXT: vpextrw $1, %xmm0, 18(%rdi) ; AVX512F-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512F-NEXT: je .LBB9_22 -; AVX512F-NEXT: .LBB9_21: # %cond.store19 +; AVX512F-NEXT: je .LBB9_12 +; AVX512F-NEXT: .LBB9_27: # %cond.store19 ; AVX512F-NEXT: vpextrw $2, %xmm0, 20(%rdi) ; AVX512F-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512F-NEXT: je .LBB9_24 -; AVX512F-NEXT: .LBB9_23: # %cond.store21 +; AVX512F-NEXT: je .LBB9_13 +; AVX512F-NEXT: .LBB9_28: # %cond.store21 ; AVX512F-NEXT: vpextrw $3, %xmm0, 22(%rdi) ; AVX512F-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512F-NEXT: je .LBB9_26 -; AVX512F-NEXT: .LBB9_25: # %cond.store23 +; AVX512F-NEXT: je .LBB9_14 +; AVX512F-NEXT: .LBB9_29: # %cond.store23 ; AVX512F-NEXT: vpextrw $4, %xmm0, 24(%rdi) ; AVX512F-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512F-NEXT: je .LBB9_28 -; AVX512F-NEXT: .LBB9_27: # %cond.store25 +; AVX512F-NEXT: je .LBB9_15 +; AVX512F-NEXT: .LBB9_30: # %cond.store25 ; AVX512F-NEXT: vpextrw $5, %xmm0, 26(%rdi) ; AVX512F-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512F-NEXT: je .LBB9_30 -; AVX512F-NEXT: .LBB9_29: # %cond.store27 +; AVX512F-NEXT: je .LBB9_16 +; AVX512F-NEXT: .LBB9_31: # %cond.store27 ; AVX512F-NEXT: vpextrw $6, %xmm0, 28(%rdi) ; AVX512F-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX512F-NEXT: je .LBB9_32 -; AVX512F-NEXT: .LBB9_31: # %cond.store29 +; AVX512F-NEXT: je .LBB9_17 +; AVX512F-NEXT: .LBB9_32: # %cond.store29 ; AVX512F-NEXT: vpextrw $7, %xmm0, 30(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -3702,116 +3702,116 @@ define void @truncstore_v16i32_v16i16(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; AVX512FVL-NEXT: vpmovsdw %zmm0, %ymm0 ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB9_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB9_18 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB9_3 -; AVX512FVL-NEXT: .LBB9_4: # %else2 +; AVX512FVL-NEXT: jne .LBB9_19 +; AVX512FVL-NEXT: .LBB9_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB9_5 -; AVX512FVL-NEXT: .LBB9_6: # %else4 +; AVX512FVL-NEXT: jne .LBB9_20 +; AVX512FVL-NEXT: .LBB9_3: # %else4 ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: jne .LBB9_7 -; AVX512FVL-NEXT: .LBB9_8: # %else6 +; AVX512FVL-NEXT: jne .LBB9_21 +; AVX512FVL-NEXT: .LBB9_4: # %else6 ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: jne .LBB9_9 -; AVX512FVL-NEXT: .LBB9_10: # %else8 +; AVX512FVL-NEXT: jne .LBB9_22 +; AVX512FVL-NEXT: .LBB9_5: # %else8 ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: jne .LBB9_11 -; AVX512FVL-NEXT: .LBB9_12: # %else10 +; AVX512FVL-NEXT: jne .LBB9_23 +; AVX512FVL-NEXT: .LBB9_6: # %else10 ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: jne .LBB9_13 -; AVX512FVL-NEXT: .LBB9_14: # %else12 +; AVX512FVL-NEXT: jne .LBB9_24 +; AVX512FVL-NEXT: .LBB9_7: # %else12 ; AVX512FVL-NEXT: testb %al, %al -; AVX512FVL-NEXT: jns .LBB9_16 -; AVX512FVL-NEXT: .LBB9_15: # %cond.store13 +; AVX512FVL-NEXT: jns .LBB9_9 +; AVX512FVL-NEXT: .LBB9_8: # %cond.store13 ; AVX512FVL-NEXT: vpextrw $7, %xmm0, 14(%rdi) -; AVX512FVL-NEXT: .LBB9_16: # %else14 +; AVX512FVL-NEXT: .LBB9_9: # %else14 ; AVX512FVL-NEXT: testl $256, %eax # imm = 0x100 ; AVX512FVL-NEXT: vextracti128 $1, %ymm0, %xmm0 -; AVX512FVL-NEXT: jne .LBB9_17 -; AVX512FVL-NEXT: # %bb.18: # %else16 +; AVX512FVL-NEXT: jne .LBB9_25 +; AVX512FVL-NEXT: # %bb.10: # %else16 ; AVX512FVL-NEXT: testl $512, %eax # imm = 0x200 -; AVX512FVL-NEXT: jne .LBB9_19 -; AVX512FVL-NEXT: .LBB9_20: # %else18 +; AVX512FVL-NEXT: jne .LBB9_26 +; AVX512FVL-NEXT: .LBB9_11: # %else18 ; AVX512FVL-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512FVL-NEXT: jne .LBB9_21 -; AVX512FVL-NEXT: .LBB9_22: # %else20 +; AVX512FVL-NEXT: jne .LBB9_27 +; AVX512FVL-NEXT: .LBB9_12: # %else20 ; AVX512FVL-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512FVL-NEXT: jne .LBB9_23 -; AVX512FVL-NEXT: .LBB9_24: # %else22 +; AVX512FVL-NEXT: jne .LBB9_28 +; AVX512FVL-NEXT: .LBB9_13: # %else22 ; AVX512FVL-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512FVL-NEXT: jne .LBB9_25 -; AVX512FVL-NEXT: .LBB9_26: # %else24 +; AVX512FVL-NEXT: jne .LBB9_29 +; AVX512FVL-NEXT: .LBB9_14: # %else24 ; AVX512FVL-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512FVL-NEXT: jne .LBB9_27 -; AVX512FVL-NEXT: .LBB9_28: # %else26 +; AVX512FVL-NEXT: jne .LBB9_30 +; AVX512FVL-NEXT: .LBB9_15: # %else26 ; AVX512FVL-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512FVL-NEXT: jne .LBB9_29 -; AVX512FVL-NEXT: .LBB9_30: # %else28 -; AVX512FVL-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX512FVL-NEXT: jne .LBB9_31 -; AVX512FVL-NEXT: .LBB9_32: # %else30 +; AVX512FVL-NEXT: .LBB9_16: # %else28 +; AVX512FVL-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX512FVL-NEXT: jne .LBB9_32 +; AVX512FVL-NEXT: .LBB9_17: # %else30 ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB9_1: # %cond.store +; AVX512FVL-NEXT: .LBB9_18: # %cond.store ; AVX512FVL-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB9_4 -; AVX512FVL-NEXT: .LBB9_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB9_2 +; AVX512FVL-NEXT: .LBB9_19: # %cond.store1 ; AVX512FVL-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB9_6 -; AVX512FVL-NEXT: .LBB9_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB9_3 +; AVX512FVL-NEXT: .LBB9_20: # %cond.store3 ; AVX512FVL-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB9_8 -; AVX512FVL-NEXT: .LBB9_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB9_4 +; AVX512FVL-NEXT: .LBB9_21: # %cond.store5 ; AVX512FVL-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: je .LBB9_10 -; AVX512FVL-NEXT: .LBB9_9: # %cond.store7 +; AVX512FVL-NEXT: je .LBB9_5 +; AVX512FVL-NEXT: .LBB9_22: # %cond.store7 ; AVX512FVL-NEXT: vpextrw $4, %xmm0, 8(%rdi) ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: je .LBB9_12 -; AVX512FVL-NEXT: .LBB9_11: # %cond.store9 +; AVX512FVL-NEXT: je .LBB9_6 +; AVX512FVL-NEXT: .LBB9_23: # %cond.store9 ; AVX512FVL-NEXT: vpextrw $5, %xmm0, 10(%rdi) ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: je .LBB9_14 -; AVX512FVL-NEXT: .LBB9_13: # %cond.store11 +; AVX512FVL-NEXT: je .LBB9_7 +; AVX512FVL-NEXT: .LBB9_24: # %cond.store11 ; AVX512FVL-NEXT: vpextrw $6, %xmm0, 12(%rdi) ; AVX512FVL-NEXT: testb %al, %al -; AVX512FVL-NEXT: js .LBB9_15 -; AVX512FVL-NEXT: jmp .LBB9_16 -; AVX512FVL-NEXT: .LBB9_17: # %cond.store15 +; AVX512FVL-NEXT: js .LBB9_8 +; AVX512FVL-NEXT: jmp .LBB9_9 +; AVX512FVL-NEXT: .LBB9_25: # %cond.store15 ; AVX512FVL-NEXT: vpextrw $0, %xmm0, 16(%rdi) ; AVX512FVL-NEXT: testl $512, %eax # imm = 0x200 -; AVX512FVL-NEXT: je .LBB9_20 -; AVX512FVL-NEXT: .LBB9_19: # %cond.store17 +; AVX512FVL-NEXT: je .LBB9_11 +; AVX512FVL-NEXT: .LBB9_26: # %cond.store17 ; AVX512FVL-NEXT: vpextrw $1, %xmm0, 18(%rdi) ; AVX512FVL-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512FVL-NEXT: je .LBB9_22 -; AVX512FVL-NEXT: .LBB9_21: # %cond.store19 +; AVX512FVL-NEXT: je .LBB9_12 +; AVX512FVL-NEXT: .LBB9_27: # %cond.store19 ; AVX512FVL-NEXT: vpextrw $2, %xmm0, 20(%rdi) ; AVX512FVL-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512FVL-NEXT: je .LBB9_24 -; AVX512FVL-NEXT: .LBB9_23: # %cond.store21 +; AVX512FVL-NEXT: je .LBB9_13 +; AVX512FVL-NEXT: .LBB9_28: # %cond.store21 ; AVX512FVL-NEXT: vpextrw $3, %xmm0, 22(%rdi) ; AVX512FVL-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512FVL-NEXT: je .LBB9_26 -; AVX512FVL-NEXT: .LBB9_25: # %cond.store23 +; AVX512FVL-NEXT: je .LBB9_14 +; AVX512FVL-NEXT: .LBB9_29: # %cond.store23 ; AVX512FVL-NEXT: vpextrw $4, %xmm0, 24(%rdi) ; AVX512FVL-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512FVL-NEXT: je .LBB9_28 -; AVX512FVL-NEXT: .LBB9_27: # %cond.store25 +; AVX512FVL-NEXT: je .LBB9_15 +; AVX512FVL-NEXT: .LBB9_30: # %cond.store25 ; AVX512FVL-NEXT: vpextrw $5, %xmm0, 26(%rdi) ; AVX512FVL-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512FVL-NEXT: je .LBB9_30 -; AVX512FVL-NEXT: .LBB9_29: # %cond.store27 +; AVX512FVL-NEXT: je .LBB9_16 +; AVX512FVL-NEXT: .LBB9_31: # %cond.store27 ; AVX512FVL-NEXT: vpextrw $6, %xmm0, 28(%rdi) ; AVX512FVL-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX512FVL-NEXT: je .LBB9_32 -; AVX512FVL-NEXT: .LBB9_31: # %cond.store29 +; AVX512FVL-NEXT: je .LBB9_17 +; AVX512FVL-NEXT: .LBB9_32: # %cond.store29 ; AVX512FVL-NEXT: vpextrw $7, %xmm0, 30(%rdi) ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq @@ -3857,103 +3857,103 @@ define void @truncstore_v16i32_v16i8(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; SSE2-NEXT: xorl $65535, %eax # imm = 0xFFFF ; SSE2-NEXT: testb $1, %al ; SSE2-NEXT: movd %xmm0, %ecx -; SSE2-NEXT: jne .LBB10_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB10_28 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne .LBB10_3 -; SSE2-NEXT: .LBB10_4: # %else2 +; SSE2-NEXT: jne .LBB10_29 +; SSE2-NEXT: .LBB10_2: # %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne .LBB10_5 -; SSE2-NEXT: .LBB10_6: # %else4 +; SSE2-NEXT: jne .LBB10_30 +; SSE2-NEXT: .LBB10_3: # %else4 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je .LBB10_8 -; SSE2-NEXT: .LBB10_7: # %cond.store5 +; SSE2-NEXT: je .LBB10_5 +; SSE2-NEXT: .LBB10_4: # %cond.store5 ; SSE2-NEXT: shrl $24, %ecx ; SSE2-NEXT: movb %cl, 3(%rdi) -; SSE2-NEXT: .LBB10_8: # %else6 +; SSE2-NEXT: .LBB10_5: # %else6 ; SSE2-NEXT: testb $16, %al ; SSE2-NEXT: pextrw $2, %xmm0, %ecx -; SSE2-NEXT: je .LBB10_10 -; SSE2-NEXT: # %bb.9: # %cond.store7 +; SSE2-NEXT: je .LBB10_7 +; SSE2-NEXT: # %bb.6: # %cond.store7 ; SSE2-NEXT: movb %cl, 4(%rdi) -; SSE2-NEXT: .LBB10_10: # %else8 +; SSE2-NEXT: .LBB10_7: # %else8 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je .LBB10_12 -; SSE2-NEXT: # %bb.11: # %cond.store9 +; SSE2-NEXT: je .LBB10_9 +; SSE2-NEXT: # %bb.8: # %cond.store9 ; SSE2-NEXT: movb %ch, 5(%rdi) -; SSE2-NEXT: .LBB10_12: # %else10 +; SSE2-NEXT: .LBB10_9: # %else10 ; SSE2-NEXT: testb $64, %al ; SSE2-NEXT: pextrw $3, %xmm0, %ecx -; SSE2-NEXT: je .LBB10_14 -; SSE2-NEXT: # %bb.13: # %cond.store11 +; SSE2-NEXT: je .LBB10_11 +; SSE2-NEXT: # %bb.10: # %cond.store11 ; SSE2-NEXT: movb %cl, 6(%rdi) -; SSE2-NEXT: .LBB10_14: # %else12 +; SSE2-NEXT: .LBB10_11: # %else12 ; SSE2-NEXT: testb %al, %al -; SSE2-NEXT: jns .LBB10_16 -; SSE2-NEXT: # %bb.15: # %cond.store13 +; SSE2-NEXT: jns .LBB10_13 +; SSE2-NEXT: # %bb.12: # %cond.store13 ; SSE2-NEXT: movb %ch, 7(%rdi) -; SSE2-NEXT: .LBB10_16: # %else14 +; SSE2-NEXT: .LBB10_13: # %else14 ; SSE2-NEXT: testl $256, %eax # imm = 0x100 ; SSE2-NEXT: pextrw $4, %xmm0, %ecx -; SSE2-NEXT: je .LBB10_18 -; SSE2-NEXT: # %bb.17: # %cond.store15 +; SSE2-NEXT: je .LBB10_15 +; SSE2-NEXT: # %bb.14: # %cond.store15 ; SSE2-NEXT: movb %cl, 8(%rdi) -; SSE2-NEXT: .LBB10_18: # %else16 +; SSE2-NEXT: .LBB10_15: # %else16 ; SSE2-NEXT: testl $512, %eax # imm = 0x200 -; SSE2-NEXT: je .LBB10_20 -; SSE2-NEXT: # %bb.19: # %cond.store17 +; SSE2-NEXT: je .LBB10_17 +; SSE2-NEXT: # %bb.16: # %cond.store17 ; SSE2-NEXT: movb %ch, 9(%rdi) -; SSE2-NEXT: .LBB10_20: # %else18 +; SSE2-NEXT: .LBB10_17: # %else18 ; SSE2-NEXT: testl $1024, %eax # imm = 0x400 ; SSE2-NEXT: pextrw $5, %xmm0, %ecx -; SSE2-NEXT: je .LBB10_22 -; SSE2-NEXT: # %bb.21: # %cond.store19 +; SSE2-NEXT: je .LBB10_19 +; SSE2-NEXT: # %bb.18: # %cond.store19 ; SSE2-NEXT: movb %cl, 10(%rdi) -; SSE2-NEXT: .LBB10_22: # %else20 +; SSE2-NEXT: .LBB10_19: # %else20 ; SSE2-NEXT: testl $2048, %eax # imm = 0x800 -; SSE2-NEXT: je .LBB10_24 -; SSE2-NEXT: # %bb.23: # %cond.store21 +; SSE2-NEXT: je .LBB10_21 +; SSE2-NEXT: # %bb.20: # %cond.store21 ; SSE2-NEXT: movb %ch, 11(%rdi) -; SSE2-NEXT: .LBB10_24: # %else22 +; SSE2-NEXT: .LBB10_21: # %else22 ; SSE2-NEXT: testl $4096, %eax # imm = 0x1000 ; SSE2-NEXT: pextrw $6, %xmm0, %ecx -; SSE2-NEXT: je .LBB10_26 -; SSE2-NEXT: # %bb.25: # %cond.store23 +; SSE2-NEXT: je .LBB10_23 +; SSE2-NEXT: # %bb.22: # %cond.store23 ; SSE2-NEXT: movb %cl, 12(%rdi) -; SSE2-NEXT: .LBB10_26: # %else24 +; SSE2-NEXT: .LBB10_23: # %else24 ; SSE2-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE2-NEXT: je .LBB10_28 -; SSE2-NEXT: # %bb.27: # %cond.store25 +; SSE2-NEXT: je .LBB10_25 +; SSE2-NEXT: # %bb.24: # %cond.store25 ; SSE2-NEXT: movb %ch, 13(%rdi) -; SSE2-NEXT: .LBB10_28: # %else26 +; SSE2-NEXT: .LBB10_25: # %else26 ; SSE2-NEXT: testl $16384, %eax # imm = 0x4000 ; SSE2-NEXT: pextrw $7, %xmm0, %ecx -; SSE2-NEXT: jne .LBB10_29 -; SSE2-NEXT: # %bb.30: # %else28 -; SSE2-NEXT: testl $32768, %eax # imm = 0x8000 ; SSE2-NEXT: jne .LBB10_31 -; SSE2-NEXT: .LBB10_32: # %else30 +; SSE2-NEXT: # %bb.26: # %else28 +; SSE2-NEXT: testl $32768, %eax # imm = 0x8000 +; SSE2-NEXT: jne .LBB10_32 +; SSE2-NEXT: .LBB10_27: # %else30 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB10_1: # %cond.store +; SSE2-NEXT: .LBB10_28: # %cond.store ; SSE2-NEXT: movb %cl, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB10_4 -; SSE2-NEXT: .LBB10_3: # %cond.store1 +; SSE2-NEXT: je .LBB10_2 +; SSE2-NEXT: .LBB10_29: # %cond.store1 ; SSE2-NEXT: movb %ch, 1(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je .LBB10_6 -; SSE2-NEXT: .LBB10_5: # %cond.store3 +; SSE2-NEXT: je .LBB10_3 +; SSE2-NEXT: .LBB10_30: # %cond.store3 ; SSE2-NEXT: movl %ecx, %edx ; SSE2-NEXT: shrl $16, %edx ; SSE2-NEXT: movb %dl, 2(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne .LBB10_7 -; SSE2-NEXT: jmp .LBB10_8 -; SSE2-NEXT: .LBB10_29: # %cond.store27 +; SSE2-NEXT: jne .LBB10_4 +; SSE2-NEXT: jmp .LBB10_5 +; SSE2-NEXT: .LBB10_31: # %cond.store27 ; SSE2-NEXT: movb %cl, 14(%rdi) ; SSE2-NEXT: testl $32768, %eax # imm = 0x8000 -; SSE2-NEXT: je .LBB10_32 -; SSE2-NEXT: .LBB10_31: # %cond.store29 +; SSE2-NEXT: je .LBB10_27 +; SSE2-NEXT: .LBB10_32: # %cond.store29 ; SSE2-NEXT: movb %ch, 15(%rdi) ; SSE2-NEXT: retq ; @@ -3973,115 +3973,115 @@ define void @truncstore_v16i32_v16i8(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; SSE4-NEXT: pmovmskb %xmm4, %eax ; SSE4-NEXT: xorl $65535, %eax # imm = 0xFFFF ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB10_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB10_17 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB10_3 -; SSE4-NEXT: .LBB10_4: # %else2 +; SSE4-NEXT: jne .LBB10_18 +; SSE4-NEXT: .LBB10_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB10_5 -; SSE4-NEXT: .LBB10_6: # %else4 +; SSE4-NEXT: jne .LBB10_19 +; SSE4-NEXT: .LBB10_3: # %else4 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne .LBB10_7 -; SSE4-NEXT: .LBB10_8: # %else6 +; SSE4-NEXT: jne .LBB10_20 +; SSE4-NEXT: .LBB10_4: # %else6 ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: jne .LBB10_9 -; SSE4-NEXT: .LBB10_10: # %else8 +; SSE4-NEXT: jne .LBB10_21 +; SSE4-NEXT: .LBB10_5: # %else8 ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: jne .LBB10_11 -; SSE4-NEXT: .LBB10_12: # %else10 +; SSE4-NEXT: jne .LBB10_22 +; SSE4-NEXT: .LBB10_6: # %else10 ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: jne .LBB10_13 -; SSE4-NEXT: .LBB10_14: # %else12 +; SSE4-NEXT: jne .LBB10_23 +; SSE4-NEXT: .LBB10_7: # %else12 ; SSE4-NEXT: testb %al, %al -; SSE4-NEXT: js .LBB10_15 -; SSE4-NEXT: .LBB10_16: # %else14 +; SSE4-NEXT: js .LBB10_24 +; SSE4-NEXT: .LBB10_8: # %else14 ; SSE4-NEXT: testl $256, %eax # imm = 0x100 -; SSE4-NEXT: jne .LBB10_17 -; SSE4-NEXT: .LBB10_18: # %else16 +; SSE4-NEXT: jne .LBB10_25 +; SSE4-NEXT: .LBB10_9: # %else16 ; SSE4-NEXT: testl $512, %eax # imm = 0x200 -; SSE4-NEXT: jne .LBB10_19 -; SSE4-NEXT: .LBB10_20: # %else18 +; SSE4-NEXT: jne .LBB10_26 +; SSE4-NEXT: .LBB10_10: # %else18 ; SSE4-NEXT: testl $1024, %eax # imm = 0x400 -; SSE4-NEXT: jne .LBB10_21 -; SSE4-NEXT: .LBB10_22: # %else20 +; SSE4-NEXT: jne .LBB10_27 +; SSE4-NEXT: .LBB10_11: # %else20 ; SSE4-NEXT: testl $2048, %eax # imm = 0x800 -; SSE4-NEXT: jne .LBB10_23 -; SSE4-NEXT: .LBB10_24: # %else22 +; SSE4-NEXT: jne .LBB10_28 +; SSE4-NEXT: .LBB10_12: # %else22 ; SSE4-NEXT: testl $4096, %eax # imm = 0x1000 -; SSE4-NEXT: jne .LBB10_25 -; SSE4-NEXT: .LBB10_26: # %else24 +; SSE4-NEXT: jne .LBB10_29 +; SSE4-NEXT: .LBB10_13: # %else24 ; SSE4-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE4-NEXT: jne .LBB10_27 -; SSE4-NEXT: .LBB10_28: # %else26 +; SSE4-NEXT: jne .LBB10_30 +; SSE4-NEXT: .LBB10_14: # %else26 ; SSE4-NEXT: testl $16384, %eax # imm = 0x4000 -; SSE4-NEXT: jne .LBB10_29 -; SSE4-NEXT: .LBB10_30: # %else28 -; SSE4-NEXT: testl $32768, %eax # imm = 0x8000 ; SSE4-NEXT: jne .LBB10_31 -; SSE4-NEXT: .LBB10_32: # %else30 +; SSE4-NEXT: .LBB10_15: # %else28 +; SSE4-NEXT: testl $32768, %eax # imm = 0x8000 +; SSE4-NEXT: jne .LBB10_32 +; SSE4-NEXT: .LBB10_16: # %else30 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB10_1: # %cond.store +; SSE4-NEXT: .LBB10_17: # %cond.store ; SSE4-NEXT: pextrb $0, %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB10_4 -; SSE4-NEXT: .LBB10_3: # %cond.store1 +; SSE4-NEXT: je .LBB10_2 +; SSE4-NEXT: .LBB10_18: # %cond.store1 ; SSE4-NEXT: pextrb $1, %xmm0, 1(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB10_6 -; SSE4-NEXT: .LBB10_5: # %cond.store3 +; SSE4-NEXT: je .LBB10_3 +; SSE4-NEXT: .LBB10_19: # %cond.store3 ; SSE4-NEXT: pextrb $2, %xmm0, 2(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB10_8 -; SSE4-NEXT: .LBB10_7: # %cond.store5 +; SSE4-NEXT: je .LBB10_4 +; SSE4-NEXT: .LBB10_20: # %cond.store5 ; SSE4-NEXT: pextrb $3, %xmm0, 3(%rdi) ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: je .LBB10_10 -; SSE4-NEXT: .LBB10_9: # %cond.store7 +; SSE4-NEXT: je .LBB10_5 +; SSE4-NEXT: .LBB10_21: # %cond.store7 ; SSE4-NEXT: pextrb $4, %xmm0, 4(%rdi) ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: je .LBB10_12 -; SSE4-NEXT: .LBB10_11: # %cond.store9 +; SSE4-NEXT: je .LBB10_6 +; SSE4-NEXT: .LBB10_22: # %cond.store9 ; SSE4-NEXT: pextrb $5, %xmm0, 5(%rdi) ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: je .LBB10_14 -; SSE4-NEXT: .LBB10_13: # %cond.store11 +; SSE4-NEXT: je .LBB10_7 +; SSE4-NEXT: .LBB10_23: # %cond.store11 ; SSE4-NEXT: pextrb $6, %xmm0, 6(%rdi) ; SSE4-NEXT: testb %al, %al -; SSE4-NEXT: jns .LBB10_16 -; SSE4-NEXT: .LBB10_15: # %cond.store13 +; SSE4-NEXT: jns .LBB10_8 +; SSE4-NEXT: .LBB10_24: # %cond.store13 ; SSE4-NEXT: pextrb $7, %xmm0, 7(%rdi) ; SSE4-NEXT: testl $256, %eax # imm = 0x100 -; SSE4-NEXT: je .LBB10_18 -; SSE4-NEXT: .LBB10_17: # %cond.store15 +; SSE4-NEXT: je .LBB10_9 +; SSE4-NEXT: .LBB10_25: # %cond.store15 ; SSE4-NEXT: pextrb $8, %xmm0, 8(%rdi) ; SSE4-NEXT: testl $512, %eax # imm = 0x200 -; SSE4-NEXT: je .LBB10_20 -; SSE4-NEXT: .LBB10_19: # %cond.store17 +; SSE4-NEXT: je .LBB10_10 +; SSE4-NEXT: .LBB10_26: # %cond.store17 ; SSE4-NEXT: pextrb $9, %xmm0, 9(%rdi) ; SSE4-NEXT: testl $1024, %eax # imm = 0x400 -; SSE4-NEXT: je .LBB10_22 -; SSE4-NEXT: .LBB10_21: # %cond.store19 +; SSE4-NEXT: je .LBB10_11 +; SSE4-NEXT: .LBB10_27: # %cond.store19 ; SSE4-NEXT: pextrb $10, %xmm0, 10(%rdi) ; SSE4-NEXT: testl $2048, %eax # imm = 0x800 -; SSE4-NEXT: je .LBB10_24 -; SSE4-NEXT: .LBB10_23: # %cond.store21 +; SSE4-NEXT: je .LBB10_12 +; SSE4-NEXT: .LBB10_28: # %cond.store21 ; SSE4-NEXT: pextrb $11, %xmm0, 11(%rdi) ; SSE4-NEXT: testl $4096, %eax # imm = 0x1000 -; SSE4-NEXT: je .LBB10_26 -; SSE4-NEXT: .LBB10_25: # %cond.store23 +; SSE4-NEXT: je .LBB10_13 +; SSE4-NEXT: .LBB10_29: # %cond.store23 ; SSE4-NEXT: pextrb $12, %xmm0, 12(%rdi) ; SSE4-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE4-NEXT: je .LBB10_28 -; SSE4-NEXT: .LBB10_27: # %cond.store25 +; SSE4-NEXT: je .LBB10_14 +; SSE4-NEXT: .LBB10_30: # %cond.store25 ; SSE4-NEXT: pextrb $13, %xmm0, 13(%rdi) ; SSE4-NEXT: testl $16384, %eax # imm = 0x4000 -; SSE4-NEXT: je .LBB10_30 -; SSE4-NEXT: .LBB10_29: # %cond.store27 +; SSE4-NEXT: je .LBB10_15 +; SSE4-NEXT: .LBB10_31: # %cond.store27 ; SSE4-NEXT: pextrb $14, %xmm0, 14(%rdi) ; SSE4-NEXT: testl $32768, %eax # imm = 0x8000 -; SSE4-NEXT: je .LBB10_32 -; SSE4-NEXT: .LBB10_31: # %cond.store29 +; SSE4-NEXT: je .LBB10_16 +; SSE4-NEXT: .LBB10_32: # %cond.store29 ; SSE4-NEXT: pextrb $15, %xmm0, 15(%rdi) ; SSE4-NEXT: retq ; @@ -4105,116 +4105,116 @@ define void @truncstore_v16i32_v16i8(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; AVX1-NEXT: vpmovmskb %xmm1, %eax ; AVX1-NEXT: xorl $65535, %eax # imm = 0xFFFF ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne .LBB10_1 -; AVX1-NEXT: # %bb.2: # %else +; AVX1-NEXT: jne .LBB10_17 +; AVX1-NEXT: # %bb.1: # %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne .LBB10_3 -; AVX1-NEXT: .LBB10_4: # %else2 +; AVX1-NEXT: jne .LBB10_18 +; AVX1-NEXT: .LBB10_2: # %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne .LBB10_5 -; AVX1-NEXT: .LBB10_6: # %else4 +; AVX1-NEXT: jne .LBB10_19 +; AVX1-NEXT: .LBB10_3: # %else4 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne .LBB10_7 -; AVX1-NEXT: .LBB10_8: # %else6 +; AVX1-NEXT: jne .LBB10_20 +; AVX1-NEXT: .LBB10_4: # %else6 ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: jne .LBB10_9 -; AVX1-NEXT: .LBB10_10: # %else8 +; AVX1-NEXT: jne .LBB10_21 +; AVX1-NEXT: .LBB10_5: # %else8 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: jne .LBB10_11 -; AVX1-NEXT: .LBB10_12: # %else10 +; AVX1-NEXT: jne .LBB10_22 +; AVX1-NEXT: .LBB10_6: # %else10 ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: jne .LBB10_13 -; AVX1-NEXT: .LBB10_14: # %else12 +; AVX1-NEXT: jne .LBB10_23 +; AVX1-NEXT: .LBB10_7: # %else12 ; AVX1-NEXT: testb %al, %al -; AVX1-NEXT: js .LBB10_15 -; AVX1-NEXT: .LBB10_16: # %else14 +; AVX1-NEXT: js .LBB10_24 +; AVX1-NEXT: .LBB10_8: # %else14 ; AVX1-NEXT: testl $256, %eax # imm = 0x100 -; AVX1-NEXT: jne .LBB10_17 -; AVX1-NEXT: .LBB10_18: # %else16 +; AVX1-NEXT: jne .LBB10_25 +; AVX1-NEXT: .LBB10_9: # %else16 ; AVX1-NEXT: testl $512, %eax # imm = 0x200 -; AVX1-NEXT: jne .LBB10_19 -; AVX1-NEXT: .LBB10_20: # %else18 +; AVX1-NEXT: jne .LBB10_26 +; AVX1-NEXT: .LBB10_10: # %else18 ; AVX1-NEXT: testl $1024, %eax # imm = 0x400 -; AVX1-NEXT: jne .LBB10_21 -; AVX1-NEXT: .LBB10_22: # %else20 +; AVX1-NEXT: jne .LBB10_27 +; AVX1-NEXT: .LBB10_11: # %else20 ; AVX1-NEXT: testl $2048, %eax # imm = 0x800 -; AVX1-NEXT: jne .LBB10_23 -; AVX1-NEXT: .LBB10_24: # %else22 +; AVX1-NEXT: jne .LBB10_28 +; AVX1-NEXT: .LBB10_12: # %else22 ; AVX1-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX1-NEXT: jne .LBB10_25 -; AVX1-NEXT: .LBB10_26: # %else24 +; AVX1-NEXT: jne .LBB10_29 +; AVX1-NEXT: .LBB10_13: # %else24 ; AVX1-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX1-NEXT: jne .LBB10_27 -; AVX1-NEXT: .LBB10_28: # %else26 +; AVX1-NEXT: jne .LBB10_30 +; AVX1-NEXT: .LBB10_14: # %else26 ; AVX1-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX1-NEXT: jne .LBB10_29 -; AVX1-NEXT: .LBB10_30: # %else28 -; AVX1-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX1-NEXT: jne .LBB10_31 -; AVX1-NEXT: .LBB10_32: # %else30 +; AVX1-NEXT: .LBB10_15: # %else28 +; AVX1-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX1-NEXT: jne .LBB10_32 +; AVX1-NEXT: .LBB10_16: # %else30 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB10_1: # %cond.store +; AVX1-NEXT: .LBB10_17: # %cond.store ; AVX1-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je .LBB10_4 -; AVX1-NEXT: .LBB10_3: # %cond.store1 +; AVX1-NEXT: je .LBB10_2 +; AVX1-NEXT: .LBB10_18: # %cond.store1 ; AVX1-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je .LBB10_6 -; AVX1-NEXT: .LBB10_5: # %cond.store3 +; AVX1-NEXT: je .LBB10_3 +; AVX1-NEXT: .LBB10_19: # %cond.store3 ; AVX1-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB10_8 -; AVX1-NEXT: .LBB10_7: # %cond.store5 +; AVX1-NEXT: je .LBB10_4 +; AVX1-NEXT: .LBB10_20: # %cond.store5 ; AVX1-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: je .LBB10_10 -; AVX1-NEXT: .LBB10_9: # %cond.store7 +; AVX1-NEXT: je .LBB10_5 +; AVX1-NEXT: .LBB10_21: # %cond.store7 ; AVX1-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je .LBB10_12 -; AVX1-NEXT: .LBB10_11: # %cond.store9 +; AVX1-NEXT: je .LBB10_6 +; AVX1-NEXT: .LBB10_22: # %cond.store9 ; AVX1-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: je .LBB10_14 -; AVX1-NEXT: .LBB10_13: # %cond.store11 +; AVX1-NEXT: je .LBB10_7 +; AVX1-NEXT: .LBB10_23: # %cond.store11 ; AVX1-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX1-NEXT: testb %al, %al -; AVX1-NEXT: jns .LBB10_16 -; AVX1-NEXT: .LBB10_15: # %cond.store13 +; AVX1-NEXT: jns .LBB10_8 +; AVX1-NEXT: .LBB10_24: # %cond.store13 ; AVX1-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX1-NEXT: testl $256, %eax # imm = 0x100 -; AVX1-NEXT: je .LBB10_18 -; AVX1-NEXT: .LBB10_17: # %cond.store15 +; AVX1-NEXT: je .LBB10_9 +; AVX1-NEXT: .LBB10_25: # %cond.store15 ; AVX1-NEXT: vpextrb $8, %xmm0, 8(%rdi) ; AVX1-NEXT: testl $512, %eax # imm = 0x200 -; AVX1-NEXT: je .LBB10_20 -; AVX1-NEXT: .LBB10_19: # %cond.store17 +; AVX1-NEXT: je .LBB10_10 +; AVX1-NEXT: .LBB10_26: # %cond.store17 ; AVX1-NEXT: vpextrb $9, %xmm0, 9(%rdi) ; AVX1-NEXT: testl $1024, %eax # imm = 0x400 -; AVX1-NEXT: je .LBB10_22 -; AVX1-NEXT: .LBB10_21: # %cond.store19 +; AVX1-NEXT: je .LBB10_11 +; AVX1-NEXT: .LBB10_27: # %cond.store19 ; AVX1-NEXT: vpextrb $10, %xmm0, 10(%rdi) ; AVX1-NEXT: testl $2048, %eax # imm = 0x800 -; AVX1-NEXT: je .LBB10_24 -; AVX1-NEXT: .LBB10_23: # %cond.store21 +; AVX1-NEXT: je .LBB10_12 +; AVX1-NEXT: .LBB10_28: # %cond.store21 ; AVX1-NEXT: vpextrb $11, %xmm0, 11(%rdi) ; AVX1-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX1-NEXT: je .LBB10_26 -; AVX1-NEXT: .LBB10_25: # %cond.store23 +; AVX1-NEXT: je .LBB10_13 +; AVX1-NEXT: .LBB10_29: # %cond.store23 ; AVX1-NEXT: vpextrb $12, %xmm0, 12(%rdi) ; AVX1-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX1-NEXT: je .LBB10_28 -; AVX1-NEXT: .LBB10_27: # %cond.store25 +; AVX1-NEXT: je .LBB10_14 +; AVX1-NEXT: .LBB10_30: # %cond.store25 ; AVX1-NEXT: vpextrb $13, %xmm0, 13(%rdi) ; AVX1-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX1-NEXT: je .LBB10_30 -; AVX1-NEXT: .LBB10_29: # %cond.store27 +; AVX1-NEXT: je .LBB10_15 +; AVX1-NEXT: .LBB10_31: # %cond.store27 ; AVX1-NEXT: vpextrb $14, %xmm0, 14(%rdi) ; AVX1-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX1-NEXT: je .LBB10_32 -; AVX1-NEXT: .LBB10_31: # %cond.store29 +; AVX1-NEXT: je .LBB10_16 +; AVX1-NEXT: .LBB10_32: # %cond.store29 ; AVX1-NEXT: vpextrb $15, %xmm0, 15(%rdi) ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq @@ -4236,116 +4236,116 @@ define void @truncstore_v16i32_v16i8(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,2,1,3] ; AVX2-NEXT: vpmovmskb %xmm1, %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne .LBB10_1 -; AVX2-NEXT: # %bb.2: # %else +; AVX2-NEXT: jne .LBB10_17 +; AVX2-NEXT: # %bb.1: # %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne .LBB10_3 -; AVX2-NEXT: .LBB10_4: # %else2 +; AVX2-NEXT: jne .LBB10_18 +; AVX2-NEXT: .LBB10_2: # %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne .LBB10_5 -; AVX2-NEXT: .LBB10_6: # %else4 +; AVX2-NEXT: jne .LBB10_19 +; AVX2-NEXT: .LBB10_3: # %else4 ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: jne .LBB10_7 -; AVX2-NEXT: .LBB10_8: # %else6 +; AVX2-NEXT: jne .LBB10_20 +; AVX2-NEXT: .LBB10_4: # %else6 ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: jne .LBB10_9 -; AVX2-NEXT: .LBB10_10: # %else8 +; AVX2-NEXT: jne .LBB10_21 +; AVX2-NEXT: .LBB10_5: # %else8 ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: jne .LBB10_11 -; AVX2-NEXT: .LBB10_12: # %else10 +; AVX2-NEXT: jne .LBB10_22 +; AVX2-NEXT: .LBB10_6: # %else10 ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: jne .LBB10_13 -; AVX2-NEXT: .LBB10_14: # %else12 +; AVX2-NEXT: jne .LBB10_23 +; AVX2-NEXT: .LBB10_7: # %else12 ; AVX2-NEXT: testb %al, %al -; AVX2-NEXT: js .LBB10_15 -; AVX2-NEXT: .LBB10_16: # %else14 +; AVX2-NEXT: js .LBB10_24 +; AVX2-NEXT: .LBB10_8: # %else14 ; AVX2-NEXT: testl $256, %eax # imm = 0x100 -; AVX2-NEXT: jne .LBB10_17 -; AVX2-NEXT: .LBB10_18: # %else16 +; AVX2-NEXT: jne .LBB10_25 +; AVX2-NEXT: .LBB10_9: # %else16 ; AVX2-NEXT: testl $512, %eax # imm = 0x200 -; AVX2-NEXT: jne .LBB10_19 -; AVX2-NEXT: .LBB10_20: # %else18 +; AVX2-NEXT: jne .LBB10_26 +; AVX2-NEXT: .LBB10_10: # %else18 ; AVX2-NEXT: testl $1024, %eax # imm = 0x400 -; AVX2-NEXT: jne .LBB10_21 -; AVX2-NEXT: .LBB10_22: # %else20 +; AVX2-NEXT: jne .LBB10_27 +; AVX2-NEXT: .LBB10_11: # %else20 ; AVX2-NEXT: testl $2048, %eax # imm = 0x800 -; AVX2-NEXT: jne .LBB10_23 -; AVX2-NEXT: .LBB10_24: # %else22 +; AVX2-NEXT: jne .LBB10_28 +; AVX2-NEXT: .LBB10_12: # %else22 ; AVX2-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX2-NEXT: jne .LBB10_25 -; AVX2-NEXT: .LBB10_26: # %else24 +; AVX2-NEXT: jne .LBB10_29 +; AVX2-NEXT: .LBB10_13: # %else24 ; AVX2-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX2-NEXT: jne .LBB10_27 -; AVX2-NEXT: .LBB10_28: # %else26 +; AVX2-NEXT: jne .LBB10_30 +; AVX2-NEXT: .LBB10_14: # %else26 ; AVX2-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX2-NEXT: jne .LBB10_29 -; AVX2-NEXT: .LBB10_30: # %else28 -; AVX2-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX2-NEXT: jne .LBB10_31 -; AVX2-NEXT: .LBB10_32: # %else30 +; AVX2-NEXT: .LBB10_15: # %else28 +; AVX2-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX2-NEXT: jne .LBB10_32 +; AVX2-NEXT: .LBB10_16: # %else30 ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; AVX2-NEXT: .LBB10_1: # %cond.store +; AVX2-NEXT: .LBB10_17: # %cond.store ; AVX2-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je .LBB10_4 -; AVX2-NEXT: .LBB10_3: # %cond.store1 +; AVX2-NEXT: je .LBB10_2 +; AVX2-NEXT: .LBB10_18: # %cond.store1 ; AVX2-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je .LBB10_6 -; AVX2-NEXT: .LBB10_5: # %cond.store3 +; AVX2-NEXT: je .LBB10_3 +; AVX2-NEXT: .LBB10_19: # %cond.store3 ; AVX2-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je .LBB10_8 -; AVX2-NEXT: .LBB10_7: # %cond.store5 +; AVX2-NEXT: je .LBB10_4 +; AVX2-NEXT: .LBB10_20: # %cond.store5 ; AVX2-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: je .LBB10_10 -; AVX2-NEXT: .LBB10_9: # %cond.store7 +; AVX2-NEXT: je .LBB10_5 +; AVX2-NEXT: .LBB10_21: # %cond.store7 ; AVX2-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: je .LBB10_12 -; AVX2-NEXT: .LBB10_11: # %cond.store9 +; AVX2-NEXT: je .LBB10_6 +; AVX2-NEXT: .LBB10_22: # %cond.store9 ; AVX2-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: je .LBB10_14 -; AVX2-NEXT: .LBB10_13: # %cond.store11 +; AVX2-NEXT: je .LBB10_7 +; AVX2-NEXT: .LBB10_23: # %cond.store11 ; AVX2-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX2-NEXT: testb %al, %al -; AVX2-NEXT: jns .LBB10_16 -; AVX2-NEXT: .LBB10_15: # %cond.store13 +; AVX2-NEXT: jns .LBB10_8 +; AVX2-NEXT: .LBB10_24: # %cond.store13 ; AVX2-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX2-NEXT: testl $256, %eax # imm = 0x100 -; AVX2-NEXT: je .LBB10_18 -; AVX2-NEXT: .LBB10_17: # %cond.store15 +; AVX2-NEXT: je .LBB10_9 +; AVX2-NEXT: .LBB10_25: # %cond.store15 ; AVX2-NEXT: vpextrb $8, %xmm0, 8(%rdi) ; AVX2-NEXT: testl $512, %eax # imm = 0x200 -; AVX2-NEXT: je .LBB10_20 -; AVX2-NEXT: .LBB10_19: # %cond.store17 +; AVX2-NEXT: je .LBB10_10 +; AVX2-NEXT: .LBB10_26: # %cond.store17 ; AVX2-NEXT: vpextrb $9, %xmm0, 9(%rdi) ; AVX2-NEXT: testl $1024, %eax # imm = 0x400 -; AVX2-NEXT: je .LBB10_22 -; AVX2-NEXT: .LBB10_21: # %cond.store19 +; AVX2-NEXT: je .LBB10_11 +; AVX2-NEXT: .LBB10_27: # %cond.store19 ; AVX2-NEXT: vpextrb $10, %xmm0, 10(%rdi) ; AVX2-NEXT: testl $2048, %eax # imm = 0x800 -; AVX2-NEXT: je .LBB10_24 -; AVX2-NEXT: .LBB10_23: # %cond.store21 +; AVX2-NEXT: je .LBB10_12 +; AVX2-NEXT: .LBB10_28: # %cond.store21 ; AVX2-NEXT: vpextrb $11, %xmm0, 11(%rdi) ; AVX2-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX2-NEXT: je .LBB10_26 -; AVX2-NEXT: .LBB10_25: # %cond.store23 +; AVX2-NEXT: je .LBB10_13 +; AVX2-NEXT: .LBB10_29: # %cond.store23 ; AVX2-NEXT: vpextrb $12, %xmm0, 12(%rdi) ; AVX2-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX2-NEXT: je .LBB10_28 -; AVX2-NEXT: .LBB10_27: # %cond.store25 +; AVX2-NEXT: je .LBB10_14 +; AVX2-NEXT: .LBB10_30: # %cond.store25 ; AVX2-NEXT: vpextrb $13, %xmm0, 13(%rdi) ; AVX2-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX2-NEXT: je .LBB10_30 -; AVX2-NEXT: .LBB10_29: # %cond.store27 +; AVX2-NEXT: je .LBB10_15 +; AVX2-NEXT: .LBB10_31: # %cond.store27 ; AVX2-NEXT: vpextrb $14, %xmm0, 14(%rdi) ; AVX2-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX2-NEXT: je .LBB10_32 -; AVX2-NEXT: .LBB10_31: # %cond.store29 +; AVX2-NEXT: je .LBB10_16 +; AVX2-NEXT: .LBB10_32: # %cond.store29 ; AVX2-NEXT: vpextrb $15, %xmm0, 15(%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq @@ -4356,116 +4356,116 @@ define void @truncstore_v16i32_v16i8(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; AVX512F-NEXT: vpmovsdb %zmm0, %xmm0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB10_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB10_17 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB10_3 -; AVX512F-NEXT: .LBB10_4: # %else2 +; AVX512F-NEXT: jne .LBB10_18 +; AVX512F-NEXT: .LBB10_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB10_5 -; AVX512F-NEXT: .LBB10_6: # %else4 +; AVX512F-NEXT: jne .LBB10_19 +; AVX512F-NEXT: .LBB10_3: # %else4 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne .LBB10_7 -; AVX512F-NEXT: .LBB10_8: # %else6 +; AVX512F-NEXT: jne .LBB10_20 +; AVX512F-NEXT: .LBB10_4: # %else6 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne .LBB10_9 -; AVX512F-NEXT: .LBB10_10: # %else8 +; AVX512F-NEXT: jne .LBB10_21 +; AVX512F-NEXT: .LBB10_5: # %else8 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne .LBB10_11 -; AVX512F-NEXT: .LBB10_12: # %else10 +; AVX512F-NEXT: jne .LBB10_22 +; AVX512F-NEXT: .LBB10_6: # %else10 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne .LBB10_13 -; AVX512F-NEXT: .LBB10_14: # %else12 +; AVX512F-NEXT: jne .LBB10_23 +; AVX512F-NEXT: .LBB10_7: # %else12 ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: js .LBB10_15 -; AVX512F-NEXT: .LBB10_16: # %else14 +; AVX512F-NEXT: js .LBB10_24 +; AVX512F-NEXT: .LBB10_8: # %else14 ; AVX512F-NEXT: testl $256, %eax # imm = 0x100 -; AVX512F-NEXT: jne .LBB10_17 -; AVX512F-NEXT: .LBB10_18: # %else16 +; AVX512F-NEXT: jne .LBB10_25 +; AVX512F-NEXT: .LBB10_9: # %else16 ; AVX512F-NEXT: testl $512, %eax # imm = 0x200 -; AVX512F-NEXT: jne .LBB10_19 -; AVX512F-NEXT: .LBB10_20: # %else18 +; AVX512F-NEXT: jne .LBB10_26 +; AVX512F-NEXT: .LBB10_10: # %else18 ; AVX512F-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512F-NEXT: jne .LBB10_21 -; AVX512F-NEXT: .LBB10_22: # %else20 +; AVX512F-NEXT: jne .LBB10_27 +; AVX512F-NEXT: .LBB10_11: # %else20 ; AVX512F-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512F-NEXT: jne .LBB10_23 -; AVX512F-NEXT: .LBB10_24: # %else22 +; AVX512F-NEXT: jne .LBB10_28 +; AVX512F-NEXT: .LBB10_12: # %else22 ; AVX512F-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512F-NEXT: jne .LBB10_25 -; AVX512F-NEXT: .LBB10_26: # %else24 +; AVX512F-NEXT: jne .LBB10_29 +; AVX512F-NEXT: .LBB10_13: # %else24 ; AVX512F-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512F-NEXT: jne .LBB10_27 -; AVX512F-NEXT: .LBB10_28: # %else26 +; AVX512F-NEXT: jne .LBB10_30 +; AVX512F-NEXT: .LBB10_14: # %else26 ; AVX512F-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512F-NEXT: jne .LBB10_29 -; AVX512F-NEXT: .LBB10_30: # %else28 -; AVX512F-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX512F-NEXT: jne .LBB10_31 -; AVX512F-NEXT: .LBB10_32: # %else30 +; AVX512F-NEXT: .LBB10_15: # %else28 +; AVX512F-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX512F-NEXT: jne .LBB10_32 +; AVX512F-NEXT: .LBB10_16: # %else30 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB10_1: # %cond.store +; AVX512F-NEXT: .LBB10_17: # %cond.store ; AVX512F-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB10_4 -; AVX512F-NEXT: .LBB10_3: # %cond.store1 +; AVX512F-NEXT: je .LBB10_2 +; AVX512F-NEXT: .LBB10_18: # %cond.store1 ; AVX512F-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB10_6 -; AVX512F-NEXT: .LBB10_5: # %cond.store3 +; AVX512F-NEXT: je .LBB10_3 +; AVX512F-NEXT: .LBB10_19: # %cond.store3 ; AVX512F-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB10_8 -; AVX512F-NEXT: .LBB10_7: # %cond.store5 +; AVX512F-NEXT: je .LBB10_4 +; AVX512F-NEXT: .LBB10_20: # %cond.store5 ; AVX512F-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je .LBB10_10 -; AVX512F-NEXT: .LBB10_9: # %cond.store7 +; AVX512F-NEXT: je .LBB10_5 +; AVX512F-NEXT: .LBB10_21: # %cond.store7 ; AVX512F-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je .LBB10_12 -; AVX512F-NEXT: .LBB10_11: # %cond.store9 +; AVX512F-NEXT: je .LBB10_6 +; AVX512F-NEXT: .LBB10_22: # %cond.store9 ; AVX512F-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je .LBB10_14 -; AVX512F-NEXT: .LBB10_13: # %cond.store11 +; AVX512F-NEXT: je .LBB10_7 +; AVX512F-NEXT: .LBB10_23: # %cond.store11 ; AVX512F-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: jns .LBB10_16 -; AVX512F-NEXT: .LBB10_15: # %cond.store13 +; AVX512F-NEXT: jns .LBB10_8 +; AVX512F-NEXT: .LBB10_24: # %cond.store13 ; AVX512F-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX512F-NEXT: testl $256, %eax # imm = 0x100 -; AVX512F-NEXT: je .LBB10_18 -; AVX512F-NEXT: .LBB10_17: # %cond.store15 +; AVX512F-NEXT: je .LBB10_9 +; AVX512F-NEXT: .LBB10_25: # %cond.store15 ; AVX512F-NEXT: vpextrb $8, %xmm0, 8(%rdi) ; AVX512F-NEXT: testl $512, %eax # imm = 0x200 -; AVX512F-NEXT: je .LBB10_20 -; AVX512F-NEXT: .LBB10_19: # %cond.store17 +; AVX512F-NEXT: je .LBB10_10 +; AVX512F-NEXT: .LBB10_26: # %cond.store17 ; AVX512F-NEXT: vpextrb $9, %xmm0, 9(%rdi) ; AVX512F-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512F-NEXT: je .LBB10_22 -; AVX512F-NEXT: .LBB10_21: # %cond.store19 +; AVX512F-NEXT: je .LBB10_11 +; AVX512F-NEXT: .LBB10_27: # %cond.store19 ; AVX512F-NEXT: vpextrb $10, %xmm0, 10(%rdi) ; AVX512F-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512F-NEXT: je .LBB10_24 -; AVX512F-NEXT: .LBB10_23: # %cond.store21 +; AVX512F-NEXT: je .LBB10_12 +; AVX512F-NEXT: .LBB10_28: # %cond.store21 ; AVX512F-NEXT: vpextrb $11, %xmm0, 11(%rdi) ; AVX512F-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512F-NEXT: je .LBB10_26 -; AVX512F-NEXT: .LBB10_25: # %cond.store23 +; AVX512F-NEXT: je .LBB10_13 +; AVX512F-NEXT: .LBB10_29: # %cond.store23 ; AVX512F-NEXT: vpextrb $12, %xmm0, 12(%rdi) ; AVX512F-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512F-NEXT: je .LBB10_28 -; AVX512F-NEXT: .LBB10_27: # %cond.store25 +; AVX512F-NEXT: je .LBB10_14 +; AVX512F-NEXT: .LBB10_30: # %cond.store25 ; AVX512F-NEXT: vpextrb $13, %xmm0, 13(%rdi) ; AVX512F-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512F-NEXT: je .LBB10_30 -; AVX512F-NEXT: .LBB10_29: # %cond.store27 +; AVX512F-NEXT: je .LBB10_15 +; AVX512F-NEXT: .LBB10_31: # %cond.store27 ; AVX512F-NEXT: vpextrb $14, %xmm0, 14(%rdi) ; AVX512F-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX512F-NEXT: je .LBB10_32 -; AVX512F-NEXT: .LBB10_31: # %cond.store29 +; AVX512F-NEXT: je .LBB10_16 +; AVX512F-NEXT: .LBB10_32: # %cond.store29 ; AVX512F-NEXT: vpextrb $15, %xmm0, 15(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -4476,116 +4476,116 @@ define void @truncstore_v16i32_v16i8(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; AVX512FVL-NEXT: vpmovsdb %zmm0, %xmm0 ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB10_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB10_17 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB10_3 -; AVX512FVL-NEXT: .LBB10_4: # %else2 +; AVX512FVL-NEXT: jne .LBB10_18 +; AVX512FVL-NEXT: .LBB10_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB10_5 -; AVX512FVL-NEXT: .LBB10_6: # %else4 +; AVX512FVL-NEXT: jne .LBB10_19 +; AVX512FVL-NEXT: .LBB10_3: # %else4 ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: jne .LBB10_7 -; AVX512FVL-NEXT: .LBB10_8: # %else6 +; AVX512FVL-NEXT: jne .LBB10_20 +; AVX512FVL-NEXT: .LBB10_4: # %else6 ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: jne .LBB10_9 -; AVX512FVL-NEXT: .LBB10_10: # %else8 +; AVX512FVL-NEXT: jne .LBB10_21 +; AVX512FVL-NEXT: .LBB10_5: # %else8 ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: jne .LBB10_11 -; AVX512FVL-NEXT: .LBB10_12: # %else10 +; AVX512FVL-NEXT: jne .LBB10_22 +; AVX512FVL-NEXT: .LBB10_6: # %else10 ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: jne .LBB10_13 -; AVX512FVL-NEXT: .LBB10_14: # %else12 +; AVX512FVL-NEXT: jne .LBB10_23 +; AVX512FVL-NEXT: .LBB10_7: # %else12 ; AVX512FVL-NEXT: testb %al, %al -; AVX512FVL-NEXT: js .LBB10_15 -; AVX512FVL-NEXT: .LBB10_16: # %else14 +; AVX512FVL-NEXT: js .LBB10_24 +; AVX512FVL-NEXT: .LBB10_8: # %else14 ; AVX512FVL-NEXT: testl $256, %eax # imm = 0x100 -; AVX512FVL-NEXT: jne .LBB10_17 -; AVX512FVL-NEXT: .LBB10_18: # %else16 +; AVX512FVL-NEXT: jne .LBB10_25 +; AVX512FVL-NEXT: .LBB10_9: # %else16 ; AVX512FVL-NEXT: testl $512, %eax # imm = 0x200 -; AVX512FVL-NEXT: jne .LBB10_19 -; AVX512FVL-NEXT: .LBB10_20: # %else18 +; AVX512FVL-NEXT: jne .LBB10_26 +; AVX512FVL-NEXT: .LBB10_10: # %else18 ; AVX512FVL-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512FVL-NEXT: jne .LBB10_21 -; AVX512FVL-NEXT: .LBB10_22: # %else20 +; AVX512FVL-NEXT: jne .LBB10_27 +; AVX512FVL-NEXT: .LBB10_11: # %else20 ; AVX512FVL-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512FVL-NEXT: jne .LBB10_23 -; AVX512FVL-NEXT: .LBB10_24: # %else22 +; AVX512FVL-NEXT: jne .LBB10_28 +; AVX512FVL-NEXT: .LBB10_12: # %else22 ; AVX512FVL-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512FVL-NEXT: jne .LBB10_25 -; AVX512FVL-NEXT: .LBB10_26: # %else24 +; AVX512FVL-NEXT: jne .LBB10_29 +; AVX512FVL-NEXT: .LBB10_13: # %else24 ; AVX512FVL-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512FVL-NEXT: jne .LBB10_27 -; AVX512FVL-NEXT: .LBB10_28: # %else26 +; AVX512FVL-NEXT: jne .LBB10_30 +; AVX512FVL-NEXT: .LBB10_14: # %else26 ; AVX512FVL-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512FVL-NEXT: jne .LBB10_29 -; AVX512FVL-NEXT: .LBB10_30: # %else28 -; AVX512FVL-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX512FVL-NEXT: jne .LBB10_31 -; AVX512FVL-NEXT: .LBB10_32: # %else30 +; AVX512FVL-NEXT: .LBB10_15: # %else28 +; AVX512FVL-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX512FVL-NEXT: jne .LBB10_32 +; AVX512FVL-NEXT: .LBB10_16: # %else30 ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB10_1: # %cond.store +; AVX512FVL-NEXT: .LBB10_17: # %cond.store ; AVX512FVL-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB10_4 -; AVX512FVL-NEXT: .LBB10_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB10_2 +; AVX512FVL-NEXT: .LBB10_18: # %cond.store1 ; AVX512FVL-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB10_6 -; AVX512FVL-NEXT: .LBB10_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB10_3 +; AVX512FVL-NEXT: .LBB10_19: # %cond.store3 ; AVX512FVL-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB10_8 -; AVX512FVL-NEXT: .LBB10_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB10_4 +; AVX512FVL-NEXT: .LBB10_20: # %cond.store5 ; AVX512FVL-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: je .LBB10_10 -; AVX512FVL-NEXT: .LBB10_9: # %cond.store7 +; AVX512FVL-NEXT: je .LBB10_5 +; AVX512FVL-NEXT: .LBB10_21: # %cond.store7 ; AVX512FVL-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: je .LBB10_12 -; AVX512FVL-NEXT: .LBB10_11: # %cond.store9 +; AVX512FVL-NEXT: je .LBB10_6 +; AVX512FVL-NEXT: .LBB10_22: # %cond.store9 ; AVX512FVL-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: je .LBB10_14 -; AVX512FVL-NEXT: .LBB10_13: # %cond.store11 +; AVX512FVL-NEXT: je .LBB10_7 +; AVX512FVL-NEXT: .LBB10_23: # %cond.store11 ; AVX512FVL-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX512FVL-NEXT: testb %al, %al -; AVX512FVL-NEXT: jns .LBB10_16 -; AVX512FVL-NEXT: .LBB10_15: # %cond.store13 +; AVX512FVL-NEXT: jns .LBB10_8 +; AVX512FVL-NEXT: .LBB10_24: # %cond.store13 ; AVX512FVL-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX512FVL-NEXT: testl $256, %eax # imm = 0x100 -; AVX512FVL-NEXT: je .LBB10_18 -; AVX512FVL-NEXT: .LBB10_17: # %cond.store15 +; AVX512FVL-NEXT: je .LBB10_9 +; AVX512FVL-NEXT: .LBB10_25: # %cond.store15 ; AVX512FVL-NEXT: vpextrb $8, %xmm0, 8(%rdi) ; AVX512FVL-NEXT: testl $512, %eax # imm = 0x200 -; AVX512FVL-NEXT: je .LBB10_20 -; AVX512FVL-NEXT: .LBB10_19: # %cond.store17 +; AVX512FVL-NEXT: je .LBB10_10 +; AVX512FVL-NEXT: .LBB10_26: # %cond.store17 ; AVX512FVL-NEXT: vpextrb $9, %xmm0, 9(%rdi) ; AVX512FVL-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512FVL-NEXT: je .LBB10_22 -; AVX512FVL-NEXT: .LBB10_21: # %cond.store19 +; AVX512FVL-NEXT: je .LBB10_11 +; AVX512FVL-NEXT: .LBB10_27: # %cond.store19 ; AVX512FVL-NEXT: vpextrb $10, %xmm0, 10(%rdi) ; AVX512FVL-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512FVL-NEXT: je .LBB10_24 -; AVX512FVL-NEXT: .LBB10_23: # %cond.store21 +; AVX512FVL-NEXT: je .LBB10_12 +; AVX512FVL-NEXT: .LBB10_28: # %cond.store21 ; AVX512FVL-NEXT: vpextrb $11, %xmm0, 11(%rdi) ; AVX512FVL-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512FVL-NEXT: je .LBB10_26 -; AVX512FVL-NEXT: .LBB10_25: # %cond.store23 +; AVX512FVL-NEXT: je .LBB10_13 +; AVX512FVL-NEXT: .LBB10_29: # %cond.store23 ; AVX512FVL-NEXT: vpextrb $12, %xmm0, 12(%rdi) ; AVX512FVL-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512FVL-NEXT: je .LBB10_28 -; AVX512FVL-NEXT: .LBB10_27: # %cond.store25 +; AVX512FVL-NEXT: je .LBB10_14 +; AVX512FVL-NEXT: .LBB10_30: # %cond.store25 ; AVX512FVL-NEXT: vpextrb $13, %xmm0, 13(%rdi) ; AVX512FVL-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512FVL-NEXT: je .LBB10_30 -; AVX512FVL-NEXT: .LBB10_29: # %cond.store27 +; AVX512FVL-NEXT: je .LBB10_15 +; AVX512FVL-NEXT: .LBB10_31: # %cond.store27 ; AVX512FVL-NEXT: vpextrb $14, %xmm0, 14(%rdi) ; AVX512FVL-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX512FVL-NEXT: je .LBB10_32 -; AVX512FVL-NEXT: .LBB10_31: # %cond.store29 +; AVX512FVL-NEXT: je .LBB10_16 +; AVX512FVL-NEXT: .LBB10_32: # %cond.store29 ; AVX512FVL-NEXT: vpextrb $15, %xmm0, 15(%rdi) ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq @@ -4625,66 +4625,66 @@ define void @truncstore_v8i32_v8i16(<8 x i32> %x, ptr %p, <8 x i32> %mask) { ; SSE2-NEXT: pmovmskb %xmm2, %eax ; SSE2-NEXT: notl %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne .LBB11_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB11_9 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne .LBB11_3 -; SSE2-NEXT: .LBB11_4: # %else2 +; SSE2-NEXT: jne .LBB11_10 +; SSE2-NEXT: .LBB11_2: # %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne .LBB11_5 -; SSE2-NEXT: .LBB11_6: # %else4 +; SSE2-NEXT: jne .LBB11_11 +; SSE2-NEXT: .LBB11_3: # %else4 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne .LBB11_7 -; SSE2-NEXT: .LBB11_8: # %else6 +; SSE2-NEXT: jne .LBB11_12 +; SSE2-NEXT: .LBB11_4: # %else6 ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: jne .LBB11_9 -; SSE2-NEXT: .LBB11_10: # %else8 +; SSE2-NEXT: jne .LBB11_13 +; SSE2-NEXT: .LBB11_5: # %else8 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: jne .LBB11_11 -; SSE2-NEXT: .LBB11_12: # %else10 +; SSE2-NEXT: jne .LBB11_14 +; SSE2-NEXT: .LBB11_6: # %else10 ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: jne .LBB11_13 -; SSE2-NEXT: .LBB11_14: # %else12 -; SSE2-NEXT: testb $-128, %al ; SSE2-NEXT: jne .LBB11_15 -; SSE2-NEXT: .LBB11_16: # %else14 +; SSE2-NEXT: .LBB11_7: # %else12 +; SSE2-NEXT: testb $-128, %al +; SSE2-NEXT: jne .LBB11_16 +; SSE2-NEXT: .LBB11_8: # %else14 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB11_1: # %cond.store +; SSE2-NEXT: .LBB11_9: # %cond.store ; SSE2-NEXT: movd %xmm0, %ecx ; SSE2-NEXT: movw %cx, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB11_4 -; SSE2-NEXT: .LBB11_3: # %cond.store1 +; SSE2-NEXT: je .LBB11_2 +; SSE2-NEXT: .LBB11_10: # %cond.store1 ; SSE2-NEXT: pextrw $1, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 2(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je .LBB11_6 -; SSE2-NEXT: .LBB11_5: # %cond.store3 +; SSE2-NEXT: je .LBB11_3 +; SSE2-NEXT: .LBB11_11: # %cond.store3 ; SSE2-NEXT: pextrw $2, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 4(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je .LBB11_8 -; SSE2-NEXT: .LBB11_7: # %cond.store5 +; SSE2-NEXT: je .LBB11_4 +; SSE2-NEXT: .LBB11_12: # %cond.store5 ; SSE2-NEXT: pextrw $3, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 6(%rdi) ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: je .LBB11_10 -; SSE2-NEXT: .LBB11_9: # %cond.store7 +; SSE2-NEXT: je .LBB11_5 +; SSE2-NEXT: .LBB11_13: # %cond.store7 ; SSE2-NEXT: pextrw $4, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 8(%rdi) ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je .LBB11_12 -; SSE2-NEXT: .LBB11_11: # %cond.store9 +; SSE2-NEXT: je .LBB11_6 +; SSE2-NEXT: .LBB11_14: # %cond.store9 ; SSE2-NEXT: pextrw $5, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 10(%rdi) ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: je .LBB11_14 -; SSE2-NEXT: .LBB11_13: # %cond.store11 +; SSE2-NEXT: je .LBB11_7 +; SSE2-NEXT: .LBB11_15: # %cond.store11 ; SSE2-NEXT: pextrw $6, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 12(%rdi) ; SSE2-NEXT: testb $-128, %al -; SSE2-NEXT: je .LBB11_16 -; SSE2-NEXT: .LBB11_15: # %cond.store13 +; SSE2-NEXT: je .LBB11_8 +; SSE2-NEXT: .LBB11_16: # %cond.store13 ; SSE2-NEXT: pextrw $7, %xmm0, %eax ; SSE2-NEXT: movw %ax, 14(%rdi) ; SSE2-NEXT: retq @@ -4700,59 +4700,59 @@ define void @truncstore_v8i32_v8i16(<8 x i32> %x, ptr %p, <8 x i32> %mask) { ; SSE4-NEXT: pmovmskb %xmm2, %eax ; SSE4-NEXT: notl %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB11_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB11_9 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB11_3 -; SSE4-NEXT: .LBB11_4: # %else2 +; SSE4-NEXT: jne .LBB11_10 +; SSE4-NEXT: .LBB11_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB11_5 -; SSE4-NEXT: .LBB11_6: # %else4 +; SSE4-NEXT: jne .LBB11_11 +; SSE4-NEXT: .LBB11_3: # %else4 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne .LBB11_7 -; SSE4-NEXT: .LBB11_8: # %else6 +; SSE4-NEXT: jne .LBB11_12 +; SSE4-NEXT: .LBB11_4: # %else6 ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: jne .LBB11_9 -; SSE4-NEXT: .LBB11_10: # %else8 +; SSE4-NEXT: jne .LBB11_13 +; SSE4-NEXT: .LBB11_5: # %else8 ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: jne .LBB11_11 -; SSE4-NEXT: .LBB11_12: # %else10 +; SSE4-NEXT: jne .LBB11_14 +; SSE4-NEXT: .LBB11_6: # %else10 ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: jne .LBB11_13 -; SSE4-NEXT: .LBB11_14: # %else12 -; SSE4-NEXT: testb $-128, %al ; SSE4-NEXT: jne .LBB11_15 -; SSE4-NEXT: .LBB11_16: # %else14 +; SSE4-NEXT: .LBB11_7: # %else12 +; SSE4-NEXT: testb $-128, %al +; SSE4-NEXT: jne .LBB11_16 +; SSE4-NEXT: .LBB11_8: # %else14 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB11_1: # %cond.store +; SSE4-NEXT: .LBB11_9: # %cond.store ; SSE4-NEXT: pextrw $0, %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB11_4 -; SSE4-NEXT: .LBB11_3: # %cond.store1 +; SSE4-NEXT: je .LBB11_2 +; SSE4-NEXT: .LBB11_10: # %cond.store1 ; SSE4-NEXT: pextrw $1, %xmm0, 2(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB11_6 -; SSE4-NEXT: .LBB11_5: # %cond.store3 +; SSE4-NEXT: je .LBB11_3 +; SSE4-NEXT: .LBB11_11: # %cond.store3 ; SSE4-NEXT: pextrw $2, %xmm0, 4(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB11_8 -; SSE4-NEXT: .LBB11_7: # %cond.store5 +; SSE4-NEXT: je .LBB11_4 +; SSE4-NEXT: .LBB11_12: # %cond.store5 ; SSE4-NEXT: pextrw $3, %xmm0, 6(%rdi) ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: je .LBB11_10 -; SSE4-NEXT: .LBB11_9: # %cond.store7 +; SSE4-NEXT: je .LBB11_5 +; SSE4-NEXT: .LBB11_13: # %cond.store7 ; SSE4-NEXT: pextrw $4, %xmm0, 8(%rdi) ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: je .LBB11_12 -; SSE4-NEXT: .LBB11_11: # %cond.store9 +; SSE4-NEXT: je .LBB11_6 +; SSE4-NEXT: .LBB11_14: # %cond.store9 ; SSE4-NEXT: pextrw $5, %xmm0, 10(%rdi) ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: je .LBB11_14 -; SSE4-NEXT: .LBB11_13: # %cond.store11 +; SSE4-NEXT: je .LBB11_7 +; SSE4-NEXT: .LBB11_15: # %cond.store11 ; SSE4-NEXT: pextrw $6, %xmm0, 12(%rdi) ; SSE4-NEXT: testb $-128, %al -; SSE4-NEXT: je .LBB11_16 -; SSE4-NEXT: .LBB11_15: # %cond.store13 +; SSE4-NEXT: je .LBB11_8 +; SSE4-NEXT: .LBB11_16: # %cond.store13 ; SSE4-NEXT: pextrw $7, %xmm0, 14(%rdi) ; SSE4-NEXT: retq ; @@ -4768,60 +4768,60 @@ define void @truncstore_v8i32_v8i16(<8 x i32> %x, ptr %p, <8 x i32> %mask) { ; AVX1-NEXT: vmovmskps %ymm1, %eax ; AVX1-NEXT: notl %eax ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne .LBB11_1 -; AVX1-NEXT: # %bb.2: # %else +; AVX1-NEXT: jne .LBB11_9 +; AVX1-NEXT: # %bb.1: # %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne .LBB11_3 -; AVX1-NEXT: .LBB11_4: # %else2 +; AVX1-NEXT: jne .LBB11_10 +; AVX1-NEXT: .LBB11_2: # %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne .LBB11_5 -; AVX1-NEXT: .LBB11_6: # %else4 +; AVX1-NEXT: jne .LBB11_11 +; AVX1-NEXT: .LBB11_3: # %else4 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne .LBB11_7 -; AVX1-NEXT: .LBB11_8: # %else6 +; AVX1-NEXT: jne .LBB11_12 +; AVX1-NEXT: .LBB11_4: # %else6 ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: jne .LBB11_9 -; AVX1-NEXT: .LBB11_10: # %else8 +; AVX1-NEXT: jne .LBB11_13 +; AVX1-NEXT: .LBB11_5: # %else8 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: jne .LBB11_11 -; AVX1-NEXT: .LBB11_12: # %else10 +; AVX1-NEXT: jne .LBB11_14 +; AVX1-NEXT: .LBB11_6: # %else10 ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: jne .LBB11_13 -; AVX1-NEXT: .LBB11_14: # %else12 -; AVX1-NEXT: testb $-128, %al ; AVX1-NEXT: jne .LBB11_15 -; AVX1-NEXT: .LBB11_16: # %else14 +; AVX1-NEXT: .LBB11_7: # %else12 +; AVX1-NEXT: testb $-128, %al +; AVX1-NEXT: jne .LBB11_16 +; AVX1-NEXT: .LBB11_8: # %else14 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB11_1: # %cond.store +; AVX1-NEXT: .LBB11_9: # %cond.store ; AVX1-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je .LBB11_4 -; AVX1-NEXT: .LBB11_3: # %cond.store1 +; AVX1-NEXT: je .LBB11_2 +; AVX1-NEXT: .LBB11_10: # %cond.store1 ; AVX1-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je .LBB11_6 -; AVX1-NEXT: .LBB11_5: # %cond.store3 +; AVX1-NEXT: je .LBB11_3 +; AVX1-NEXT: .LBB11_11: # %cond.store3 ; AVX1-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB11_8 -; AVX1-NEXT: .LBB11_7: # %cond.store5 +; AVX1-NEXT: je .LBB11_4 +; AVX1-NEXT: .LBB11_12: # %cond.store5 ; AVX1-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: je .LBB11_10 -; AVX1-NEXT: .LBB11_9: # %cond.store7 +; AVX1-NEXT: je .LBB11_5 +; AVX1-NEXT: .LBB11_13: # %cond.store7 ; AVX1-NEXT: vpextrw $4, %xmm0, 8(%rdi) ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je .LBB11_12 -; AVX1-NEXT: .LBB11_11: # %cond.store9 +; AVX1-NEXT: je .LBB11_6 +; AVX1-NEXT: .LBB11_14: # %cond.store9 ; AVX1-NEXT: vpextrw $5, %xmm0, 10(%rdi) ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: je .LBB11_14 -; AVX1-NEXT: .LBB11_13: # %cond.store11 +; AVX1-NEXT: je .LBB11_7 +; AVX1-NEXT: .LBB11_15: # %cond.store11 ; AVX1-NEXT: vpextrw $6, %xmm0, 12(%rdi) ; AVX1-NEXT: testb $-128, %al -; AVX1-NEXT: je .LBB11_16 -; AVX1-NEXT: .LBB11_15: # %cond.store13 +; AVX1-NEXT: je .LBB11_8 +; AVX1-NEXT: .LBB11_16: # %cond.store13 ; AVX1-NEXT: vpextrw $7, %xmm0, 14(%rdi) ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq @@ -4835,60 +4835,60 @@ define void @truncstore_v8i32_v8i16(<8 x i32> %x, ptr %p, <8 x i32> %mask) { ; AVX2-NEXT: vmovmskps %ymm1, %eax ; AVX2-NEXT: notl %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne .LBB11_1 -; AVX2-NEXT: # %bb.2: # %else +; AVX2-NEXT: jne .LBB11_9 +; AVX2-NEXT: # %bb.1: # %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne .LBB11_3 -; AVX2-NEXT: .LBB11_4: # %else2 +; AVX2-NEXT: jne .LBB11_10 +; AVX2-NEXT: .LBB11_2: # %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne .LBB11_5 -; AVX2-NEXT: .LBB11_6: # %else4 +; AVX2-NEXT: jne .LBB11_11 +; AVX2-NEXT: .LBB11_3: # %else4 ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: jne .LBB11_7 -; AVX2-NEXT: .LBB11_8: # %else6 +; AVX2-NEXT: jne .LBB11_12 +; AVX2-NEXT: .LBB11_4: # %else6 ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: jne .LBB11_9 -; AVX2-NEXT: .LBB11_10: # %else8 +; AVX2-NEXT: jne .LBB11_13 +; AVX2-NEXT: .LBB11_5: # %else8 ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: jne .LBB11_11 -; AVX2-NEXT: .LBB11_12: # %else10 +; AVX2-NEXT: jne .LBB11_14 +; AVX2-NEXT: .LBB11_6: # %else10 ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: jne .LBB11_13 -; AVX2-NEXT: .LBB11_14: # %else12 -; AVX2-NEXT: testb $-128, %al ; AVX2-NEXT: jne .LBB11_15 -; AVX2-NEXT: .LBB11_16: # %else14 +; AVX2-NEXT: .LBB11_7: # %else12 +; AVX2-NEXT: testb $-128, %al +; AVX2-NEXT: jne .LBB11_16 +; AVX2-NEXT: .LBB11_8: # %else14 ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; AVX2-NEXT: .LBB11_1: # %cond.store +; AVX2-NEXT: .LBB11_9: # %cond.store ; AVX2-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je .LBB11_4 -; AVX2-NEXT: .LBB11_3: # %cond.store1 +; AVX2-NEXT: je .LBB11_2 +; AVX2-NEXT: .LBB11_10: # %cond.store1 ; AVX2-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je .LBB11_6 -; AVX2-NEXT: .LBB11_5: # %cond.store3 +; AVX2-NEXT: je .LBB11_3 +; AVX2-NEXT: .LBB11_11: # %cond.store3 ; AVX2-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je .LBB11_8 -; AVX2-NEXT: .LBB11_7: # %cond.store5 +; AVX2-NEXT: je .LBB11_4 +; AVX2-NEXT: .LBB11_12: # %cond.store5 ; AVX2-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: je .LBB11_10 -; AVX2-NEXT: .LBB11_9: # %cond.store7 +; AVX2-NEXT: je .LBB11_5 +; AVX2-NEXT: .LBB11_13: # %cond.store7 ; AVX2-NEXT: vpextrw $4, %xmm0, 8(%rdi) ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: je .LBB11_12 -; AVX2-NEXT: .LBB11_11: # %cond.store9 +; AVX2-NEXT: je .LBB11_6 +; AVX2-NEXT: .LBB11_14: # %cond.store9 ; AVX2-NEXT: vpextrw $5, %xmm0, 10(%rdi) ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: je .LBB11_14 -; AVX2-NEXT: .LBB11_13: # %cond.store11 +; AVX2-NEXT: je .LBB11_7 +; AVX2-NEXT: .LBB11_15: # %cond.store11 ; AVX2-NEXT: vpextrw $6, %xmm0, 12(%rdi) ; AVX2-NEXT: testb $-128, %al -; AVX2-NEXT: je .LBB11_16 -; AVX2-NEXT: .LBB11_15: # %cond.store13 +; AVX2-NEXT: je .LBB11_8 +; AVX2-NEXT: .LBB11_16: # %cond.store13 ; AVX2-NEXT: vpextrw $7, %xmm0, 14(%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq @@ -4901,60 +4901,60 @@ define void @truncstore_v8i32_v8i16(<8 x i32> %x, ptr %p, <8 x i32> %mask) { ; AVX512F-NEXT: vpackssdw %xmm1, %xmm0, %xmm0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB11_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB11_9 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB11_3 -; AVX512F-NEXT: .LBB11_4: # %else2 +; AVX512F-NEXT: jne .LBB11_10 +; AVX512F-NEXT: .LBB11_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB11_5 -; AVX512F-NEXT: .LBB11_6: # %else4 +; AVX512F-NEXT: jne .LBB11_11 +; AVX512F-NEXT: .LBB11_3: # %else4 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne .LBB11_7 -; AVX512F-NEXT: .LBB11_8: # %else6 +; AVX512F-NEXT: jne .LBB11_12 +; AVX512F-NEXT: .LBB11_4: # %else6 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne .LBB11_9 -; AVX512F-NEXT: .LBB11_10: # %else8 +; AVX512F-NEXT: jne .LBB11_13 +; AVX512F-NEXT: .LBB11_5: # %else8 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne .LBB11_11 -; AVX512F-NEXT: .LBB11_12: # %else10 +; AVX512F-NEXT: jne .LBB11_14 +; AVX512F-NEXT: .LBB11_6: # %else10 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne .LBB11_13 -; AVX512F-NEXT: .LBB11_14: # %else12 -; AVX512F-NEXT: testb $-128, %al ; AVX512F-NEXT: jne .LBB11_15 -; AVX512F-NEXT: .LBB11_16: # %else14 +; AVX512F-NEXT: .LBB11_7: # %else12 +; AVX512F-NEXT: testb $-128, %al +; AVX512F-NEXT: jne .LBB11_16 +; AVX512F-NEXT: .LBB11_8: # %else14 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB11_1: # %cond.store +; AVX512F-NEXT: .LBB11_9: # %cond.store ; AVX512F-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB11_4 -; AVX512F-NEXT: .LBB11_3: # %cond.store1 +; AVX512F-NEXT: je .LBB11_2 +; AVX512F-NEXT: .LBB11_10: # %cond.store1 ; AVX512F-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB11_6 -; AVX512F-NEXT: .LBB11_5: # %cond.store3 +; AVX512F-NEXT: je .LBB11_3 +; AVX512F-NEXT: .LBB11_11: # %cond.store3 ; AVX512F-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB11_8 -; AVX512F-NEXT: .LBB11_7: # %cond.store5 +; AVX512F-NEXT: je .LBB11_4 +; AVX512F-NEXT: .LBB11_12: # %cond.store5 ; AVX512F-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je .LBB11_10 -; AVX512F-NEXT: .LBB11_9: # %cond.store7 +; AVX512F-NEXT: je .LBB11_5 +; AVX512F-NEXT: .LBB11_13: # %cond.store7 ; AVX512F-NEXT: vpextrw $4, %xmm0, 8(%rdi) ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je .LBB11_12 -; AVX512F-NEXT: .LBB11_11: # %cond.store9 +; AVX512F-NEXT: je .LBB11_6 +; AVX512F-NEXT: .LBB11_14: # %cond.store9 ; AVX512F-NEXT: vpextrw $5, %xmm0, 10(%rdi) ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je .LBB11_14 -; AVX512F-NEXT: .LBB11_13: # %cond.store11 +; AVX512F-NEXT: je .LBB11_7 +; AVX512F-NEXT: .LBB11_15: # %cond.store11 ; AVX512F-NEXT: vpextrw $6, %xmm0, 12(%rdi) ; AVX512F-NEXT: testb $-128, %al -; AVX512F-NEXT: je .LBB11_16 -; AVX512F-NEXT: .LBB11_15: # %cond.store13 +; AVX512F-NEXT: je .LBB11_8 +; AVX512F-NEXT: .LBB11_16: # %cond.store13 ; AVX512F-NEXT: vpextrw $7, %xmm0, 14(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -4965,60 +4965,60 @@ define void @truncstore_v8i32_v8i16(<8 x i32> %x, ptr %p, <8 x i32> %mask) { ; AVX512FVL-NEXT: vpmovsdw %ymm0, %xmm0 ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB11_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB11_9 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB11_3 -; AVX512FVL-NEXT: .LBB11_4: # %else2 +; AVX512FVL-NEXT: jne .LBB11_10 +; AVX512FVL-NEXT: .LBB11_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB11_5 -; AVX512FVL-NEXT: .LBB11_6: # %else4 +; AVX512FVL-NEXT: jne .LBB11_11 +; AVX512FVL-NEXT: .LBB11_3: # %else4 ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: jne .LBB11_7 -; AVX512FVL-NEXT: .LBB11_8: # %else6 +; AVX512FVL-NEXT: jne .LBB11_12 +; AVX512FVL-NEXT: .LBB11_4: # %else6 ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: jne .LBB11_9 -; AVX512FVL-NEXT: .LBB11_10: # %else8 +; AVX512FVL-NEXT: jne .LBB11_13 +; AVX512FVL-NEXT: .LBB11_5: # %else8 ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: jne .LBB11_11 -; AVX512FVL-NEXT: .LBB11_12: # %else10 +; AVX512FVL-NEXT: jne .LBB11_14 +; AVX512FVL-NEXT: .LBB11_6: # %else10 ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: jne .LBB11_13 -; AVX512FVL-NEXT: .LBB11_14: # %else12 -; AVX512FVL-NEXT: testb $-128, %al ; AVX512FVL-NEXT: jne .LBB11_15 -; AVX512FVL-NEXT: .LBB11_16: # %else14 +; AVX512FVL-NEXT: .LBB11_7: # %else12 +; AVX512FVL-NEXT: testb $-128, %al +; AVX512FVL-NEXT: jne .LBB11_16 +; AVX512FVL-NEXT: .LBB11_8: # %else14 ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB11_1: # %cond.store +; AVX512FVL-NEXT: .LBB11_9: # %cond.store ; AVX512FVL-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB11_4 -; AVX512FVL-NEXT: .LBB11_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB11_2 +; AVX512FVL-NEXT: .LBB11_10: # %cond.store1 ; AVX512FVL-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB11_6 -; AVX512FVL-NEXT: .LBB11_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB11_3 +; AVX512FVL-NEXT: .LBB11_11: # %cond.store3 ; AVX512FVL-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB11_8 -; AVX512FVL-NEXT: .LBB11_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB11_4 +; AVX512FVL-NEXT: .LBB11_12: # %cond.store5 ; AVX512FVL-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: je .LBB11_10 -; AVX512FVL-NEXT: .LBB11_9: # %cond.store7 +; AVX512FVL-NEXT: je .LBB11_5 +; AVX512FVL-NEXT: .LBB11_13: # %cond.store7 ; AVX512FVL-NEXT: vpextrw $4, %xmm0, 8(%rdi) ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: je .LBB11_12 -; AVX512FVL-NEXT: .LBB11_11: # %cond.store9 +; AVX512FVL-NEXT: je .LBB11_6 +; AVX512FVL-NEXT: .LBB11_14: # %cond.store9 ; AVX512FVL-NEXT: vpextrw $5, %xmm0, 10(%rdi) ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: je .LBB11_14 -; AVX512FVL-NEXT: .LBB11_13: # %cond.store11 +; AVX512FVL-NEXT: je .LBB11_7 +; AVX512FVL-NEXT: .LBB11_15: # %cond.store11 ; AVX512FVL-NEXT: vpextrw $6, %xmm0, 12(%rdi) ; AVX512FVL-NEXT: testb $-128, %al -; AVX512FVL-NEXT: je .LBB11_16 -; AVX512FVL-NEXT: .LBB11_15: # %cond.store13 +; AVX512FVL-NEXT: je .LBB11_8 +; AVX512FVL-NEXT: .LBB11_16: # %cond.store13 ; AVX512FVL-NEXT: vpextrw $7, %xmm0, 14(%rdi) ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq @@ -5065,59 +5065,59 @@ define void @truncstore_v8i32_v8i8(<8 x i32> %x, ptr %p, <8 x i32> %mask) { ; SSE2-NEXT: notl %eax ; SSE2-NEXT: testb $1, %al ; SSE2-NEXT: movd %xmm0, %ecx -; SSE2-NEXT: jne .LBB12_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB12_12 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne .LBB12_3 -; SSE2-NEXT: .LBB12_4: # %else2 +; SSE2-NEXT: jne .LBB12_13 +; SSE2-NEXT: .LBB12_2: # %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne .LBB12_5 -; SSE2-NEXT: .LBB12_6: # %else4 +; SSE2-NEXT: jne .LBB12_14 +; SSE2-NEXT: .LBB12_3: # %else4 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je .LBB12_8 -; SSE2-NEXT: .LBB12_7: # %cond.store5 +; SSE2-NEXT: je .LBB12_5 +; SSE2-NEXT: .LBB12_4: # %cond.store5 ; SSE2-NEXT: shrl $24, %ecx ; SSE2-NEXT: movb %cl, 3(%rdi) -; SSE2-NEXT: .LBB12_8: # %else6 +; SSE2-NEXT: .LBB12_5: # %else6 ; SSE2-NEXT: testb $16, %al ; SSE2-NEXT: pextrw $2, %xmm0, %ecx -; SSE2-NEXT: je .LBB12_10 -; SSE2-NEXT: # %bb.9: # %cond.store7 +; SSE2-NEXT: je .LBB12_7 +; SSE2-NEXT: # %bb.6: # %cond.store7 ; SSE2-NEXT: movb %cl, 4(%rdi) -; SSE2-NEXT: .LBB12_10: # %else8 +; SSE2-NEXT: .LBB12_7: # %else8 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je .LBB12_12 -; SSE2-NEXT: # %bb.11: # %cond.store9 +; SSE2-NEXT: je .LBB12_9 +; SSE2-NEXT: # %bb.8: # %cond.store9 ; SSE2-NEXT: movb %ch, 5(%rdi) -; SSE2-NEXT: .LBB12_12: # %else10 +; SSE2-NEXT: .LBB12_9: # %else10 ; SSE2-NEXT: testb $64, %al ; SSE2-NEXT: pextrw $3, %xmm0, %ecx -; SSE2-NEXT: jne .LBB12_13 -; SSE2-NEXT: # %bb.14: # %else12 -; SSE2-NEXT: testb $-128, %al ; SSE2-NEXT: jne .LBB12_15 -; SSE2-NEXT: .LBB12_16: # %else14 +; SSE2-NEXT: # %bb.10: # %else12 +; SSE2-NEXT: testb $-128, %al +; SSE2-NEXT: jne .LBB12_16 +; SSE2-NEXT: .LBB12_11: # %else14 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB12_1: # %cond.store +; SSE2-NEXT: .LBB12_12: # %cond.store ; SSE2-NEXT: movb %cl, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB12_4 -; SSE2-NEXT: .LBB12_3: # %cond.store1 +; SSE2-NEXT: je .LBB12_2 +; SSE2-NEXT: .LBB12_13: # %cond.store1 ; SSE2-NEXT: movb %ch, 1(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je .LBB12_6 -; SSE2-NEXT: .LBB12_5: # %cond.store3 +; SSE2-NEXT: je .LBB12_3 +; SSE2-NEXT: .LBB12_14: # %cond.store3 ; SSE2-NEXT: movl %ecx, %edx ; SSE2-NEXT: shrl $16, %edx ; SSE2-NEXT: movb %dl, 2(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne .LBB12_7 -; SSE2-NEXT: jmp .LBB12_8 -; SSE2-NEXT: .LBB12_13: # %cond.store11 +; SSE2-NEXT: jne .LBB12_4 +; SSE2-NEXT: jmp .LBB12_5 +; SSE2-NEXT: .LBB12_15: # %cond.store11 ; SSE2-NEXT: movb %cl, 6(%rdi) ; SSE2-NEXT: testb $-128, %al -; SSE2-NEXT: je .LBB12_16 -; SSE2-NEXT: .LBB12_15: # %cond.store13 +; SSE2-NEXT: je .LBB12_11 +; SSE2-NEXT: .LBB12_16: # %cond.store13 ; SSE2-NEXT: movb %ch, 7(%rdi) ; SSE2-NEXT: retq ; @@ -5133,59 +5133,59 @@ define void @truncstore_v8i32_v8i8(<8 x i32> %x, ptr %p, <8 x i32> %mask) { ; SSE4-NEXT: pmovmskb %xmm2, %eax ; SSE4-NEXT: notl %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB12_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB12_9 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB12_3 -; SSE4-NEXT: .LBB12_4: # %else2 +; SSE4-NEXT: jne .LBB12_10 +; SSE4-NEXT: .LBB12_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB12_5 -; SSE4-NEXT: .LBB12_6: # %else4 +; SSE4-NEXT: jne .LBB12_11 +; SSE4-NEXT: .LBB12_3: # %else4 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne .LBB12_7 -; SSE4-NEXT: .LBB12_8: # %else6 +; SSE4-NEXT: jne .LBB12_12 +; SSE4-NEXT: .LBB12_4: # %else6 ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: jne .LBB12_9 -; SSE4-NEXT: .LBB12_10: # %else8 +; SSE4-NEXT: jne .LBB12_13 +; SSE4-NEXT: .LBB12_5: # %else8 ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: jne .LBB12_11 -; SSE4-NEXT: .LBB12_12: # %else10 +; SSE4-NEXT: jne .LBB12_14 +; SSE4-NEXT: .LBB12_6: # %else10 ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: jne .LBB12_13 -; SSE4-NEXT: .LBB12_14: # %else12 -; SSE4-NEXT: testb $-128, %al ; SSE4-NEXT: jne .LBB12_15 -; SSE4-NEXT: .LBB12_16: # %else14 +; SSE4-NEXT: .LBB12_7: # %else12 +; SSE4-NEXT: testb $-128, %al +; SSE4-NEXT: jne .LBB12_16 +; SSE4-NEXT: .LBB12_8: # %else14 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB12_1: # %cond.store +; SSE4-NEXT: .LBB12_9: # %cond.store ; SSE4-NEXT: pextrb $0, %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB12_4 -; SSE4-NEXT: .LBB12_3: # %cond.store1 +; SSE4-NEXT: je .LBB12_2 +; SSE4-NEXT: .LBB12_10: # %cond.store1 ; SSE4-NEXT: pextrb $1, %xmm0, 1(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB12_6 -; SSE4-NEXT: .LBB12_5: # %cond.store3 +; SSE4-NEXT: je .LBB12_3 +; SSE4-NEXT: .LBB12_11: # %cond.store3 ; SSE4-NEXT: pextrb $2, %xmm0, 2(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB12_8 -; SSE4-NEXT: .LBB12_7: # %cond.store5 +; SSE4-NEXT: je .LBB12_4 +; SSE4-NEXT: .LBB12_12: # %cond.store5 ; SSE4-NEXT: pextrb $3, %xmm0, 3(%rdi) ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: je .LBB12_10 -; SSE4-NEXT: .LBB12_9: # %cond.store7 +; SSE4-NEXT: je .LBB12_5 +; SSE4-NEXT: .LBB12_13: # %cond.store7 ; SSE4-NEXT: pextrb $4, %xmm0, 4(%rdi) ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: je .LBB12_12 -; SSE4-NEXT: .LBB12_11: # %cond.store9 +; SSE4-NEXT: je .LBB12_6 +; SSE4-NEXT: .LBB12_14: # %cond.store9 ; SSE4-NEXT: pextrb $5, %xmm0, 5(%rdi) ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: je .LBB12_14 -; SSE4-NEXT: .LBB12_13: # %cond.store11 +; SSE4-NEXT: je .LBB12_7 +; SSE4-NEXT: .LBB12_15: # %cond.store11 ; SSE4-NEXT: pextrb $6, %xmm0, 6(%rdi) ; SSE4-NEXT: testb $-128, %al -; SSE4-NEXT: je .LBB12_16 -; SSE4-NEXT: .LBB12_15: # %cond.store13 +; SSE4-NEXT: je .LBB12_8 +; SSE4-NEXT: .LBB12_16: # %cond.store13 ; SSE4-NEXT: pextrb $7, %xmm0, 7(%rdi) ; SSE4-NEXT: retq ; @@ -5202,60 +5202,60 @@ define void @truncstore_v8i32_v8i8(<8 x i32> %x, ptr %p, <8 x i32> %mask) { ; AVX1-NEXT: vmovmskps %ymm1, %eax ; AVX1-NEXT: notl %eax ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne .LBB12_1 -; AVX1-NEXT: # %bb.2: # %else +; AVX1-NEXT: jne .LBB12_9 +; AVX1-NEXT: # %bb.1: # %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne .LBB12_3 -; AVX1-NEXT: .LBB12_4: # %else2 +; AVX1-NEXT: jne .LBB12_10 +; AVX1-NEXT: .LBB12_2: # %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne .LBB12_5 -; AVX1-NEXT: .LBB12_6: # %else4 +; AVX1-NEXT: jne .LBB12_11 +; AVX1-NEXT: .LBB12_3: # %else4 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne .LBB12_7 -; AVX1-NEXT: .LBB12_8: # %else6 +; AVX1-NEXT: jne .LBB12_12 +; AVX1-NEXT: .LBB12_4: # %else6 ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: jne .LBB12_9 -; AVX1-NEXT: .LBB12_10: # %else8 +; AVX1-NEXT: jne .LBB12_13 +; AVX1-NEXT: .LBB12_5: # %else8 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: jne .LBB12_11 -; AVX1-NEXT: .LBB12_12: # %else10 +; AVX1-NEXT: jne .LBB12_14 +; AVX1-NEXT: .LBB12_6: # %else10 ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: jne .LBB12_13 -; AVX1-NEXT: .LBB12_14: # %else12 -; AVX1-NEXT: testb $-128, %al ; AVX1-NEXT: jne .LBB12_15 -; AVX1-NEXT: .LBB12_16: # %else14 +; AVX1-NEXT: .LBB12_7: # %else12 +; AVX1-NEXT: testb $-128, %al +; AVX1-NEXT: jne .LBB12_16 +; AVX1-NEXT: .LBB12_8: # %else14 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB12_1: # %cond.store +; AVX1-NEXT: .LBB12_9: # %cond.store ; AVX1-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je .LBB12_4 -; AVX1-NEXT: .LBB12_3: # %cond.store1 +; AVX1-NEXT: je .LBB12_2 +; AVX1-NEXT: .LBB12_10: # %cond.store1 ; AVX1-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je .LBB12_6 -; AVX1-NEXT: .LBB12_5: # %cond.store3 +; AVX1-NEXT: je .LBB12_3 +; AVX1-NEXT: .LBB12_11: # %cond.store3 ; AVX1-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB12_8 -; AVX1-NEXT: .LBB12_7: # %cond.store5 +; AVX1-NEXT: je .LBB12_4 +; AVX1-NEXT: .LBB12_12: # %cond.store5 ; AVX1-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: je .LBB12_10 -; AVX1-NEXT: .LBB12_9: # %cond.store7 +; AVX1-NEXT: je .LBB12_5 +; AVX1-NEXT: .LBB12_13: # %cond.store7 ; AVX1-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je .LBB12_12 -; AVX1-NEXT: .LBB12_11: # %cond.store9 +; AVX1-NEXT: je .LBB12_6 +; AVX1-NEXT: .LBB12_14: # %cond.store9 ; AVX1-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: je .LBB12_14 -; AVX1-NEXT: .LBB12_13: # %cond.store11 +; AVX1-NEXT: je .LBB12_7 +; AVX1-NEXT: .LBB12_15: # %cond.store11 ; AVX1-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX1-NEXT: testb $-128, %al -; AVX1-NEXT: je .LBB12_16 -; AVX1-NEXT: .LBB12_15: # %cond.store13 +; AVX1-NEXT: je .LBB12_8 +; AVX1-NEXT: .LBB12_16: # %cond.store13 ; AVX1-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq @@ -5270,60 +5270,60 @@ define void @truncstore_v8i32_v8i8(<8 x i32> %x, ptr %p, <8 x i32> %mask) { ; AVX2-NEXT: vmovmskps %ymm1, %eax ; AVX2-NEXT: notl %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne .LBB12_1 -; AVX2-NEXT: # %bb.2: # %else +; AVX2-NEXT: jne .LBB12_9 +; AVX2-NEXT: # %bb.1: # %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne .LBB12_3 -; AVX2-NEXT: .LBB12_4: # %else2 +; AVX2-NEXT: jne .LBB12_10 +; AVX2-NEXT: .LBB12_2: # %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne .LBB12_5 -; AVX2-NEXT: .LBB12_6: # %else4 +; AVX2-NEXT: jne .LBB12_11 +; AVX2-NEXT: .LBB12_3: # %else4 ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: jne .LBB12_7 -; AVX2-NEXT: .LBB12_8: # %else6 +; AVX2-NEXT: jne .LBB12_12 +; AVX2-NEXT: .LBB12_4: # %else6 ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: jne .LBB12_9 -; AVX2-NEXT: .LBB12_10: # %else8 +; AVX2-NEXT: jne .LBB12_13 +; AVX2-NEXT: .LBB12_5: # %else8 ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: jne .LBB12_11 -; AVX2-NEXT: .LBB12_12: # %else10 +; AVX2-NEXT: jne .LBB12_14 +; AVX2-NEXT: .LBB12_6: # %else10 ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: jne .LBB12_13 -; AVX2-NEXT: .LBB12_14: # %else12 -; AVX2-NEXT: testb $-128, %al ; AVX2-NEXT: jne .LBB12_15 -; AVX2-NEXT: .LBB12_16: # %else14 +; AVX2-NEXT: .LBB12_7: # %else12 +; AVX2-NEXT: testb $-128, %al +; AVX2-NEXT: jne .LBB12_16 +; AVX2-NEXT: .LBB12_8: # %else14 ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; AVX2-NEXT: .LBB12_1: # %cond.store +; AVX2-NEXT: .LBB12_9: # %cond.store ; AVX2-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je .LBB12_4 -; AVX2-NEXT: .LBB12_3: # %cond.store1 +; AVX2-NEXT: je .LBB12_2 +; AVX2-NEXT: .LBB12_10: # %cond.store1 ; AVX2-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je .LBB12_6 -; AVX2-NEXT: .LBB12_5: # %cond.store3 +; AVX2-NEXT: je .LBB12_3 +; AVX2-NEXT: .LBB12_11: # %cond.store3 ; AVX2-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je .LBB12_8 -; AVX2-NEXT: .LBB12_7: # %cond.store5 +; AVX2-NEXT: je .LBB12_4 +; AVX2-NEXT: .LBB12_12: # %cond.store5 ; AVX2-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: je .LBB12_10 -; AVX2-NEXT: .LBB12_9: # %cond.store7 +; AVX2-NEXT: je .LBB12_5 +; AVX2-NEXT: .LBB12_13: # %cond.store7 ; AVX2-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: je .LBB12_12 -; AVX2-NEXT: .LBB12_11: # %cond.store9 +; AVX2-NEXT: je .LBB12_6 +; AVX2-NEXT: .LBB12_14: # %cond.store9 ; AVX2-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: je .LBB12_14 -; AVX2-NEXT: .LBB12_13: # %cond.store11 +; AVX2-NEXT: je .LBB12_7 +; AVX2-NEXT: .LBB12_15: # %cond.store11 ; AVX2-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX2-NEXT: testb $-128, %al -; AVX2-NEXT: je .LBB12_16 -; AVX2-NEXT: .LBB12_15: # %cond.store13 +; AVX2-NEXT: je .LBB12_8 +; AVX2-NEXT: .LBB12_16: # %cond.store13 ; AVX2-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq @@ -5337,60 +5337,60 @@ define void @truncstore_v8i32_v8i8(<8 x i32> %x, ptr %p, <8 x i32> %mask) { ; AVX512F-NEXT: vpacksswb %xmm0, %xmm0, %xmm0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB12_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB12_9 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB12_3 -; AVX512F-NEXT: .LBB12_4: # %else2 +; AVX512F-NEXT: jne .LBB12_10 +; AVX512F-NEXT: .LBB12_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB12_5 -; AVX512F-NEXT: .LBB12_6: # %else4 +; AVX512F-NEXT: jne .LBB12_11 +; AVX512F-NEXT: .LBB12_3: # %else4 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne .LBB12_7 -; AVX512F-NEXT: .LBB12_8: # %else6 +; AVX512F-NEXT: jne .LBB12_12 +; AVX512F-NEXT: .LBB12_4: # %else6 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne .LBB12_9 -; AVX512F-NEXT: .LBB12_10: # %else8 +; AVX512F-NEXT: jne .LBB12_13 +; AVX512F-NEXT: .LBB12_5: # %else8 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne .LBB12_11 -; AVX512F-NEXT: .LBB12_12: # %else10 +; AVX512F-NEXT: jne .LBB12_14 +; AVX512F-NEXT: .LBB12_6: # %else10 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne .LBB12_13 -; AVX512F-NEXT: .LBB12_14: # %else12 -; AVX512F-NEXT: testb $-128, %al ; AVX512F-NEXT: jne .LBB12_15 -; AVX512F-NEXT: .LBB12_16: # %else14 +; AVX512F-NEXT: .LBB12_7: # %else12 +; AVX512F-NEXT: testb $-128, %al +; AVX512F-NEXT: jne .LBB12_16 +; AVX512F-NEXT: .LBB12_8: # %else14 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB12_1: # %cond.store +; AVX512F-NEXT: .LBB12_9: # %cond.store ; AVX512F-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB12_4 -; AVX512F-NEXT: .LBB12_3: # %cond.store1 +; AVX512F-NEXT: je .LBB12_2 +; AVX512F-NEXT: .LBB12_10: # %cond.store1 ; AVX512F-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB12_6 -; AVX512F-NEXT: .LBB12_5: # %cond.store3 +; AVX512F-NEXT: je .LBB12_3 +; AVX512F-NEXT: .LBB12_11: # %cond.store3 ; AVX512F-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB12_8 -; AVX512F-NEXT: .LBB12_7: # %cond.store5 +; AVX512F-NEXT: je .LBB12_4 +; AVX512F-NEXT: .LBB12_12: # %cond.store5 ; AVX512F-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je .LBB12_10 -; AVX512F-NEXT: .LBB12_9: # %cond.store7 +; AVX512F-NEXT: je .LBB12_5 +; AVX512F-NEXT: .LBB12_13: # %cond.store7 ; AVX512F-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je .LBB12_12 -; AVX512F-NEXT: .LBB12_11: # %cond.store9 +; AVX512F-NEXT: je .LBB12_6 +; AVX512F-NEXT: .LBB12_14: # %cond.store9 ; AVX512F-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je .LBB12_14 -; AVX512F-NEXT: .LBB12_13: # %cond.store11 +; AVX512F-NEXT: je .LBB12_7 +; AVX512F-NEXT: .LBB12_15: # %cond.store11 ; AVX512F-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX512F-NEXT: testb $-128, %al -; AVX512F-NEXT: je .LBB12_16 -; AVX512F-NEXT: .LBB12_15: # %cond.store13 +; AVX512F-NEXT: je .LBB12_8 +; AVX512F-NEXT: .LBB12_16: # %cond.store13 ; AVX512F-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -5401,60 +5401,60 @@ define void @truncstore_v8i32_v8i8(<8 x i32> %x, ptr %p, <8 x i32> %mask) { ; AVX512FVL-NEXT: vpmovsdb %ymm0, %xmm0 ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB12_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB12_9 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB12_3 -; AVX512FVL-NEXT: .LBB12_4: # %else2 +; AVX512FVL-NEXT: jne .LBB12_10 +; AVX512FVL-NEXT: .LBB12_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB12_5 -; AVX512FVL-NEXT: .LBB12_6: # %else4 +; AVX512FVL-NEXT: jne .LBB12_11 +; AVX512FVL-NEXT: .LBB12_3: # %else4 ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: jne .LBB12_7 -; AVX512FVL-NEXT: .LBB12_8: # %else6 +; AVX512FVL-NEXT: jne .LBB12_12 +; AVX512FVL-NEXT: .LBB12_4: # %else6 ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: jne .LBB12_9 -; AVX512FVL-NEXT: .LBB12_10: # %else8 +; AVX512FVL-NEXT: jne .LBB12_13 +; AVX512FVL-NEXT: .LBB12_5: # %else8 ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: jne .LBB12_11 -; AVX512FVL-NEXT: .LBB12_12: # %else10 +; AVX512FVL-NEXT: jne .LBB12_14 +; AVX512FVL-NEXT: .LBB12_6: # %else10 ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: jne .LBB12_13 -; AVX512FVL-NEXT: .LBB12_14: # %else12 -; AVX512FVL-NEXT: testb $-128, %al ; AVX512FVL-NEXT: jne .LBB12_15 -; AVX512FVL-NEXT: .LBB12_16: # %else14 +; AVX512FVL-NEXT: .LBB12_7: # %else12 +; AVX512FVL-NEXT: testb $-128, %al +; AVX512FVL-NEXT: jne .LBB12_16 +; AVX512FVL-NEXT: .LBB12_8: # %else14 ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB12_1: # %cond.store +; AVX512FVL-NEXT: .LBB12_9: # %cond.store ; AVX512FVL-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB12_4 -; AVX512FVL-NEXT: .LBB12_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB12_2 +; AVX512FVL-NEXT: .LBB12_10: # %cond.store1 ; AVX512FVL-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB12_6 -; AVX512FVL-NEXT: .LBB12_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB12_3 +; AVX512FVL-NEXT: .LBB12_11: # %cond.store3 ; AVX512FVL-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB12_8 -; AVX512FVL-NEXT: .LBB12_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB12_4 +; AVX512FVL-NEXT: .LBB12_12: # %cond.store5 ; AVX512FVL-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: je .LBB12_10 -; AVX512FVL-NEXT: .LBB12_9: # %cond.store7 +; AVX512FVL-NEXT: je .LBB12_5 +; AVX512FVL-NEXT: .LBB12_13: # %cond.store7 ; AVX512FVL-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: je .LBB12_12 -; AVX512FVL-NEXT: .LBB12_11: # %cond.store9 +; AVX512FVL-NEXT: je .LBB12_6 +; AVX512FVL-NEXT: .LBB12_14: # %cond.store9 ; AVX512FVL-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: je .LBB12_14 -; AVX512FVL-NEXT: .LBB12_13: # %cond.store11 +; AVX512FVL-NEXT: je .LBB12_7 +; AVX512FVL-NEXT: .LBB12_15: # %cond.store11 ; AVX512FVL-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX512FVL-NEXT: testb $-128, %al -; AVX512FVL-NEXT: je .LBB12_16 -; AVX512FVL-NEXT: .LBB12_15: # %cond.store13 +; AVX512FVL-NEXT: je .LBB12_8 +; AVX512FVL-NEXT: .LBB12_16: # %cond.store13 ; AVX512FVL-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq @@ -5497,34 +5497,34 @@ define void @truncstore_v4i32_v4i16(<4 x i32> %x, ptr %p, <4 x i32> %mask) { ; SSE2-NEXT: movmskps %xmm2, %eax ; SSE2-NEXT: xorl $15, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne .LBB13_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB13_5 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne .LBB13_3 -; SSE2-NEXT: .LBB13_4: # %else2 +; SSE2-NEXT: jne .LBB13_6 +; SSE2-NEXT: .LBB13_2: # %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne .LBB13_5 -; SSE2-NEXT: .LBB13_6: # %else4 -; SSE2-NEXT: testb $8, %al ; SSE2-NEXT: jne .LBB13_7 -; SSE2-NEXT: .LBB13_8: # %else6 +; SSE2-NEXT: .LBB13_3: # %else4 +; SSE2-NEXT: testb $8, %al +; SSE2-NEXT: jne .LBB13_8 +; SSE2-NEXT: .LBB13_4: # %else6 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB13_1: # %cond.store +; SSE2-NEXT: .LBB13_5: # %cond.store ; SSE2-NEXT: movd %xmm0, %ecx ; SSE2-NEXT: movw %cx, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB13_4 -; SSE2-NEXT: .LBB13_3: # %cond.store1 +; SSE2-NEXT: je .LBB13_2 +; SSE2-NEXT: .LBB13_6: # %cond.store1 ; SSE2-NEXT: pextrw $1, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 2(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je .LBB13_6 -; SSE2-NEXT: .LBB13_5: # %cond.store3 +; SSE2-NEXT: je .LBB13_3 +; SSE2-NEXT: .LBB13_7: # %cond.store3 ; SSE2-NEXT: pextrw $2, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 4(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je .LBB13_8 -; SSE2-NEXT: .LBB13_7: # %cond.store5 +; SSE2-NEXT: je .LBB13_4 +; SSE2-NEXT: .LBB13_8: # %cond.store5 ; SSE2-NEXT: pextrw $3, %xmm0, %eax ; SSE2-NEXT: movw %ax, 6(%rdi) ; SSE2-NEXT: retq @@ -5537,31 +5537,31 @@ define void @truncstore_v4i32_v4i16(<4 x i32> %x, ptr %p, <4 x i32> %mask) { ; SSE4-NEXT: movmskps %xmm2, %eax ; SSE4-NEXT: xorl $15, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB13_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB13_5 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB13_3 -; SSE4-NEXT: .LBB13_4: # %else2 +; SSE4-NEXT: jne .LBB13_6 +; SSE4-NEXT: .LBB13_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB13_5 -; SSE4-NEXT: .LBB13_6: # %else4 -; SSE4-NEXT: testb $8, %al ; SSE4-NEXT: jne .LBB13_7 -; SSE4-NEXT: .LBB13_8: # %else6 +; SSE4-NEXT: .LBB13_3: # %else4 +; SSE4-NEXT: testb $8, %al +; SSE4-NEXT: jne .LBB13_8 +; SSE4-NEXT: .LBB13_4: # %else6 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB13_1: # %cond.store +; SSE4-NEXT: .LBB13_5: # %cond.store ; SSE4-NEXT: pextrw $0, %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB13_4 -; SSE4-NEXT: .LBB13_3: # %cond.store1 +; SSE4-NEXT: je .LBB13_2 +; SSE4-NEXT: .LBB13_6: # %cond.store1 ; SSE4-NEXT: pextrw $1, %xmm0, 2(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB13_6 -; SSE4-NEXT: .LBB13_5: # %cond.store3 +; SSE4-NEXT: je .LBB13_3 +; SSE4-NEXT: .LBB13_7: # %cond.store3 ; SSE4-NEXT: pextrw $2, %xmm0, 4(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB13_8 -; SSE4-NEXT: .LBB13_7: # %cond.store5 +; SSE4-NEXT: je .LBB13_4 +; SSE4-NEXT: .LBB13_8: # %cond.store5 ; SSE4-NEXT: pextrw $3, %xmm0, 6(%rdi) ; SSE4-NEXT: retq ; @@ -5573,31 +5573,31 @@ define void @truncstore_v4i32_v4i16(<4 x i32> %x, ptr %p, <4 x i32> %mask) { ; AVX-NEXT: vmovmskps %xmm1, %eax ; AVX-NEXT: xorl $15, %eax ; AVX-NEXT: testb $1, %al -; AVX-NEXT: jne .LBB13_1 -; AVX-NEXT: # %bb.2: # %else +; AVX-NEXT: jne .LBB13_5 +; AVX-NEXT: # %bb.1: # %else ; AVX-NEXT: testb $2, %al -; AVX-NEXT: jne .LBB13_3 -; AVX-NEXT: .LBB13_4: # %else2 +; AVX-NEXT: jne .LBB13_6 +; AVX-NEXT: .LBB13_2: # %else2 ; AVX-NEXT: testb $4, %al -; AVX-NEXT: jne .LBB13_5 -; AVX-NEXT: .LBB13_6: # %else4 -; AVX-NEXT: testb $8, %al ; AVX-NEXT: jne .LBB13_7 -; AVX-NEXT: .LBB13_8: # %else6 +; AVX-NEXT: .LBB13_3: # %else4 +; AVX-NEXT: testb $8, %al +; AVX-NEXT: jne .LBB13_8 +; AVX-NEXT: .LBB13_4: # %else6 ; AVX-NEXT: retq -; AVX-NEXT: .LBB13_1: # %cond.store +; AVX-NEXT: .LBB13_5: # %cond.store ; AVX-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX-NEXT: testb $2, %al -; AVX-NEXT: je .LBB13_4 -; AVX-NEXT: .LBB13_3: # %cond.store1 +; AVX-NEXT: je .LBB13_2 +; AVX-NEXT: .LBB13_6: # %cond.store1 ; AVX-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX-NEXT: testb $4, %al -; AVX-NEXT: je .LBB13_6 -; AVX-NEXT: .LBB13_5: # %cond.store3 +; AVX-NEXT: je .LBB13_3 +; AVX-NEXT: .LBB13_7: # %cond.store3 ; AVX-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX-NEXT: testb $8, %al -; AVX-NEXT: je .LBB13_8 -; AVX-NEXT: .LBB13_7: # %cond.store5 +; AVX-NEXT: je .LBB13_4 +; AVX-NEXT: .LBB13_8: # %cond.store5 ; AVX-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX-NEXT: retq ; @@ -5608,32 +5608,32 @@ define void @truncstore_v4i32_v4i16(<4 x i32> %x, ptr %p, <4 x i32> %mask) { ; AVX512F-NEXT: vpackssdw %xmm0, %xmm0, %xmm0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB13_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB13_5 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB13_3 -; AVX512F-NEXT: .LBB13_4: # %else2 +; AVX512F-NEXT: jne .LBB13_6 +; AVX512F-NEXT: .LBB13_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB13_5 -; AVX512F-NEXT: .LBB13_6: # %else4 -; AVX512F-NEXT: testb $8, %al ; AVX512F-NEXT: jne .LBB13_7 -; AVX512F-NEXT: .LBB13_8: # %else6 +; AVX512F-NEXT: .LBB13_3: # %else4 +; AVX512F-NEXT: testb $8, %al +; AVX512F-NEXT: jne .LBB13_8 +; AVX512F-NEXT: .LBB13_4: # %else6 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB13_1: # %cond.store +; AVX512F-NEXT: .LBB13_5: # %cond.store ; AVX512F-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB13_4 -; AVX512F-NEXT: .LBB13_3: # %cond.store1 +; AVX512F-NEXT: je .LBB13_2 +; AVX512F-NEXT: .LBB13_6: # %cond.store1 ; AVX512F-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB13_6 -; AVX512F-NEXT: .LBB13_5: # %cond.store3 +; AVX512F-NEXT: je .LBB13_3 +; AVX512F-NEXT: .LBB13_7: # %cond.store3 ; AVX512F-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB13_8 -; AVX512F-NEXT: .LBB13_7: # %cond.store5 +; AVX512F-NEXT: je .LBB13_4 +; AVX512F-NEXT: .LBB13_8: # %cond.store5 ; AVX512F-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -5644,31 +5644,31 @@ define void @truncstore_v4i32_v4i16(<4 x i32> %x, ptr %p, <4 x i32> %mask) { ; AVX512FVL-NEXT: vpackssdw %xmm0, %xmm0, %xmm0 ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB13_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB13_5 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB13_3 -; AVX512FVL-NEXT: .LBB13_4: # %else2 +; AVX512FVL-NEXT: jne .LBB13_6 +; AVX512FVL-NEXT: .LBB13_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB13_5 -; AVX512FVL-NEXT: .LBB13_6: # %else4 -; AVX512FVL-NEXT: testb $8, %al ; AVX512FVL-NEXT: jne .LBB13_7 -; AVX512FVL-NEXT: .LBB13_8: # %else6 +; AVX512FVL-NEXT: .LBB13_3: # %else4 +; AVX512FVL-NEXT: testb $8, %al +; AVX512FVL-NEXT: jne .LBB13_8 +; AVX512FVL-NEXT: .LBB13_4: # %else6 ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB13_1: # %cond.store +; AVX512FVL-NEXT: .LBB13_5: # %cond.store ; AVX512FVL-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB13_4 -; AVX512FVL-NEXT: .LBB13_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB13_2 +; AVX512FVL-NEXT: .LBB13_6: # %cond.store1 ; AVX512FVL-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB13_6 -; AVX512FVL-NEXT: .LBB13_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB13_3 +; AVX512FVL-NEXT: .LBB13_7: # %cond.store3 ; AVX512FVL-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB13_8 -; AVX512FVL-NEXT: .LBB13_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB13_4 +; AVX512FVL-NEXT: .LBB13_8: # %cond.store5 ; AVX512FVL-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX512FVL-NEXT: retq ; @@ -5709,33 +5709,33 @@ define void @truncstore_v4i32_v4i8(<4 x i32> %x, ptr %p, <4 x i32> %mask) { ; SSE2-NEXT: xorl $15, %ecx ; SSE2-NEXT: testb $1, %cl ; SSE2-NEXT: movd %xmm0, %eax -; SSE2-NEXT: jne .LBB14_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB14_5 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %cl -; SSE2-NEXT: jne .LBB14_3 -; SSE2-NEXT: .LBB14_4: # %else2 +; SSE2-NEXT: jne .LBB14_6 +; SSE2-NEXT: .LBB14_2: # %else2 ; SSE2-NEXT: testb $4, %cl -; SSE2-NEXT: jne .LBB14_5 -; SSE2-NEXT: .LBB14_6: # %else4 -; SSE2-NEXT: testb $8, %cl ; SSE2-NEXT: jne .LBB14_7 -; SSE2-NEXT: .LBB14_8: # %else6 +; SSE2-NEXT: .LBB14_3: # %else4 +; SSE2-NEXT: testb $8, %cl +; SSE2-NEXT: jne .LBB14_8 +; SSE2-NEXT: .LBB14_4: # %else6 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB14_1: # %cond.store +; SSE2-NEXT: .LBB14_5: # %cond.store ; SSE2-NEXT: movb %al, (%rdi) ; SSE2-NEXT: testb $2, %cl -; SSE2-NEXT: je .LBB14_4 -; SSE2-NEXT: .LBB14_3: # %cond.store1 +; SSE2-NEXT: je .LBB14_2 +; SSE2-NEXT: .LBB14_6: # %cond.store1 ; SSE2-NEXT: movb %ah, 1(%rdi) ; SSE2-NEXT: testb $4, %cl -; SSE2-NEXT: je .LBB14_6 -; SSE2-NEXT: .LBB14_5: # %cond.store3 +; SSE2-NEXT: je .LBB14_3 +; SSE2-NEXT: .LBB14_7: # %cond.store3 ; SSE2-NEXT: movl %eax, %edx ; SSE2-NEXT: shrl $16, %edx ; SSE2-NEXT: movb %dl, 2(%rdi) ; SSE2-NEXT: testb $8, %cl -; SSE2-NEXT: je .LBB14_8 -; SSE2-NEXT: .LBB14_7: # %cond.store5 +; SSE2-NEXT: je .LBB14_4 +; SSE2-NEXT: .LBB14_8: # %cond.store5 ; SSE2-NEXT: shrl $24, %eax ; SSE2-NEXT: movb %al, 3(%rdi) ; SSE2-NEXT: retq @@ -5749,31 +5749,31 @@ define void @truncstore_v4i32_v4i8(<4 x i32> %x, ptr %p, <4 x i32> %mask) { ; SSE4-NEXT: movmskps %xmm2, %eax ; SSE4-NEXT: xorl $15, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB14_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB14_5 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB14_3 -; SSE4-NEXT: .LBB14_4: # %else2 +; SSE4-NEXT: jne .LBB14_6 +; SSE4-NEXT: .LBB14_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB14_5 -; SSE4-NEXT: .LBB14_6: # %else4 -; SSE4-NEXT: testb $8, %al ; SSE4-NEXT: jne .LBB14_7 -; SSE4-NEXT: .LBB14_8: # %else6 +; SSE4-NEXT: .LBB14_3: # %else4 +; SSE4-NEXT: testb $8, %al +; SSE4-NEXT: jne .LBB14_8 +; SSE4-NEXT: .LBB14_4: # %else6 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB14_1: # %cond.store +; SSE4-NEXT: .LBB14_5: # %cond.store ; SSE4-NEXT: pextrb $0, %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB14_4 -; SSE4-NEXT: .LBB14_3: # %cond.store1 +; SSE4-NEXT: je .LBB14_2 +; SSE4-NEXT: .LBB14_6: # %cond.store1 ; SSE4-NEXT: pextrb $1, %xmm0, 1(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB14_6 -; SSE4-NEXT: .LBB14_5: # %cond.store3 +; SSE4-NEXT: je .LBB14_3 +; SSE4-NEXT: .LBB14_7: # %cond.store3 ; SSE4-NEXT: pextrb $2, %xmm0, 2(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB14_8 -; SSE4-NEXT: .LBB14_7: # %cond.store5 +; SSE4-NEXT: je .LBB14_4 +; SSE4-NEXT: .LBB14_8: # %cond.store5 ; SSE4-NEXT: pextrb $3, %xmm0, 3(%rdi) ; SSE4-NEXT: retq ; @@ -5786,31 +5786,31 @@ define void @truncstore_v4i32_v4i8(<4 x i32> %x, ptr %p, <4 x i32> %mask) { ; AVX-NEXT: vmovmskps %xmm1, %eax ; AVX-NEXT: xorl $15, %eax ; AVX-NEXT: testb $1, %al -; AVX-NEXT: jne .LBB14_1 -; AVX-NEXT: # %bb.2: # %else +; AVX-NEXT: jne .LBB14_5 +; AVX-NEXT: # %bb.1: # %else ; AVX-NEXT: testb $2, %al -; AVX-NEXT: jne .LBB14_3 -; AVX-NEXT: .LBB14_4: # %else2 +; AVX-NEXT: jne .LBB14_6 +; AVX-NEXT: .LBB14_2: # %else2 ; AVX-NEXT: testb $4, %al -; AVX-NEXT: jne .LBB14_5 -; AVX-NEXT: .LBB14_6: # %else4 -; AVX-NEXT: testb $8, %al ; AVX-NEXT: jne .LBB14_7 -; AVX-NEXT: .LBB14_8: # %else6 +; AVX-NEXT: .LBB14_3: # %else4 +; AVX-NEXT: testb $8, %al +; AVX-NEXT: jne .LBB14_8 +; AVX-NEXT: .LBB14_4: # %else6 ; AVX-NEXT: retq -; AVX-NEXT: .LBB14_1: # %cond.store +; AVX-NEXT: .LBB14_5: # %cond.store ; AVX-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX-NEXT: testb $2, %al -; AVX-NEXT: je .LBB14_4 -; AVX-NEXT: .LBB14_3: # %cond.store1 +; AVX-NEXT: je .LBB14_2 +; AVX-NEXT: .LBB14_6: # %cond.store1 ; AVX-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX-NEXT: testb $4, %al -; AVX-NEXT: je .LBB14_6 -; AVX-NEXT: .LBB14_5: # %cond.store3 +; AVX-NEXT: je .LBB14_3 +; AVX-NEXT: .LBB14_7: # %cond.store3 ; AVX-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX-NEXT: testb $8, %al -; AVX-NEXT: je .LBB14_8 -; AVX-NEXT: .LBB14_7: # %cond.store5 +; AVX-NEXT: je .LBB14_4 +; AVX-NEXT: .LBB14_8: # %cond.store5 ; AVX-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX-NEXT: retq ; @@ -5822,32 +5822,32 @@ define void @truncstore_v4i32_v4i8(<4 x i32> %x, ptr %p, <4 x i32> %mask) { ; AVX512F-NEXT: vpacksswb %xmm0, %xmm0, %xmm0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB14_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB14_5 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB14_3 -; AVX512F-NEXT: .LBB14_4: # %else2 +; AVX512F-NEXT: jne .LBB14_6 +; AVX512F-NEXT: .LBB14_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB14_5 -; AVX512F-NEXT: .LBB14_6: # %else4 -; AVX512F-NEXT: testb $8, %al ; AVX512F-NEXT: jne .LBB14_7 -; AVX512F-NEXT: .LBB14_8: # %else6 +; AVX512F-NEXT: .LBB14_3: # %else4 +; AVX512F-NEXT: testb $8, %al +; AVX512F-NEXT: jne .LBB14_8 +; AVX512F-NEXT: .LBB14_4: # %else6 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB14_1: # %cond.store +; AVX512F-NEXT: .LBB14_5: # %cond.store ; AVX512F-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB14_4 -; AVX512F-NEXT: .LBB14_3: # %cond.store1 +; AVX512F-NEXT: je .LBB14_2 +; AVX512F-NEXT: .LBB14_6: # %cond.store1 ; AVX512F-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB14_6 -; AVX512F-NEXT: .LBB14_5: # %cond.store3 +; AVX512F-NEXT: je .LBB14_3 +; AVX512F-NEXT: .LBB14_7: # %cond.store3 ; AVX512F-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB14_8 -; AVX512F-NEXT: .LBB14_7: # %cond.store5 +; AVX512F-NEXT: je .LBB14_4 +; AVX512F-NEXT: .LBB14_8: # %cond.store5 ; AVX512F-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -5859,31 +5859,31 @@ define void @truncstore_v4i32_v4i8(<4 x i32> %x, ptr %p, <4 x i32> %mask) { ; AVX512FVL-NEXT: vpacksswb %xmm0, %xmm0, %xmm0 ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB14_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB14_5 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB14_3 -; AVX512FVL-NEXT: .LBB14_4: # %else2 +; AVX512FVL-NEXT: jne .LBB14_6 +; AVX512FVL-NEXT: .LBB14_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB14_5 -; AVX512FVL-NEXT: .LBB14_6: # %else4 -; AVX512FVL-NEXT: testb $8, %al ; AVX512FVL-NEXT: jne .LBB14_7 -; AVX512FVL-NEXT: .LBB14_8: # %else6 +; AVX512FVL-NEXT: .LBB14_3: # %else4 +; AVX512FVL-NEXT: testb $8, %al +; AVX512FVL-NEXT: jne .LBB14_8 +; AVX512FVL-NEXT: .LBB14_4: # %else6 ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB14_1: # %cond.store +; AVX512FVL-NEXT: .LBB14_5: # %cond.store ; AVX512FVL-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB14_4 -; AVX512FVL-NEXT: .LBB14_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB14_2 +; AVX512FVL-NEXT: .LBB14_6: # %cond.store1 ; AVX512FVL-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB14_6 -; AVX512FVL-NEXT: .LBB14_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB14_3 +; AVX512FVL-NEXT: .LBB14_7: # %cond.store3 ; AVX512FVL-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB14_8 -; AVX512FVL-NEXT: .LBB14_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB14_4 +; AVX512FVL-NEXT: .LBB14_8: # %cond.store5 ; AVX512FVL-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512FVL-NEXT: retq ; @@ -5929,201 +5929,201 @@ define void @truncstore_v32i16_v32i8(<32 x i16> %x, ptr %p, <32 x i8> %mask) { ; SSE2-NEXT: orl %ecx, %eax ; SSE2-NEXT: testb $1, %al ; SSE2-NEXT: movd %xmm0, %ecx -; SSE2-NEXT: jne .LBB15_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB15_57 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne .LBB15_3 -; SSE2-NEXT: .LBB15_4: # %else2 +; SSE2-NEXT: jne .LBB15_58 +; SSE2-NEXT: .LBB15_2: # %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne .LBB15_5 -; SSE2-NEXT: .LBB15_6: # %else4 +; SSE2-NEXT: jne .LBB15_59 +; SSE2-NEXT: .LBB15_3: # %else4 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je .LBB15_8 -; SSE2-NEXT: .LBB15_7: # %cond.store5 +; SSE2-NEXT: je .LBB15_5 +; SSE2-NEXT: .LBB15_4: # %cond.store5 ; SSE2-NEXT: shrl $24, %ecx ; SSE2-NEXT: movb %cl, 3(%rdi) -; SSE2-NEXT: .LBB15_8: # %else6 +; SSE2-NEXT: .LBB15_5: # %else6 ; SSE2-NEXT: testb $16, %al ; SSE2-NEXT: pextrw $2, %xmm0, %ecx -; SSE2-NEXT: je .LBB15_10 -; SSE2-NEXT: # %bb.9: # %cond.store7 +; SSE2-NEXT: je .LBB15_7 +; SSE2-NEXT: # %bb.6: # %cond.store7 ; SSE2-NEXT: movb %cl, 4(%rdi) -; SSE2-NEXT: .LBB15_10: # %else8 +; SSE2-NEXT: .LBB15_7: # %else8 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je .LBB15_12 -; SSE2-NEXT: # %bb.11: # %cond.store9 +; SSE2-NEXT: je .LBB15_9 +; SSE2-NEXT: # %bb.8: # %cond.store9 ; SSE2-NEXT: movb %ch, 5(%rdi) -; SSE2-NEXT: .LBB15_12: # %else10 +; SSE2-NEXT: .LBB15_9: # %else10 ; SSE2-NEXT: testb $64, %al ; SSE2-NEXT: pextrw $3, %xmm0, %ecx -; SSE2-NEXT: je .LBB15_14 -; SSE2-NEXT: # %bb.13: # %cond.store11 +; SSE2-NEXT: je .LBB15_11 +; SSE2-NEXT: # %bb.10: # %cond.store11 ; SSE2-NEXT: movb %cl, 6(%rdi) -; SSE2-NEXT: .LBB15_14: # %else12 +; SSE2-NEXT: .LBB15_11: # %else12 ; SSE2-NEXT: testb %al, %al -; SSE2-NEXT: jns .LBB15_16 -; SSE2-NEXT: # %bb.15: # %cond.store13 +; SSE2-NEXT: jns .LBB15_13 +; SSE2-NEXT: # %bb.12: # %cond.store13 ; SSE2-NEXT: movb %ch, 7(%rdi) -; SSE2-NEXT: .LBB15_16: # %else14 +; SSE2-NEXT: .LBB15_13: # %else14 ; SSE2-NEXT: testl $256, %eax # imm = 0x100 ; SSE2-NEXT: pextrw $4, %xmm0, %ecx -; SSE2-NEXT: je .LBB15_18 -; SSE2-NEXT: # %bb.17: # %cond.store15 +; SSE2-NEXT: je .LBB15_15 +; SSE2-NEXT: # %bb.14: # %cond.store15 ; SSE2-NEXT: movb %cl, 8(%rdi) -; SSE2-NEXT: .LBB15_18: # %else16 +; SSE2-NEXT: .LBB15_15: # %else16 ; SSE2-NEXT: testl $512, %eax # imm = 0x200 -; SSE2-NEXT: je .LBB15_20 -; SSE2-NEXT: # %bb.19: # %cond.store17 +; SSE2-NEXT: je .LBB15_17 +; SSE2-NEXT: # %bb.16: # %cond.store17 ; SSE2-NEXT: movb %ch, 9(%rdi) -; SSE2-NEXT: .LBB15_20: # %else18 +; SSE2-NEXT: .LBB15_17: # %else18 ; SSE2-NEXT: testl $1024, %eax # imm = 0x400 ; SSE2-NEXT: pextrw $5, %xmm0, %ecx -; SSE2-NEXT: je .LBB15_22 -; SSE2-NEXT: # %bb.21: # %cond.store19 +; SSE2-NEXT: je .LBB15_19 +; SSE2-NEXT: # %bb.18: # %cond.store19 ; SSE2-NEXT: movb %cl, 10(%rdi) -; SSE2-NEXT: .LBB15_22: # %else20 +; SSE2-NEXT: .LBB15_19: # %else20 ; SSE2-NEXT: testl $2048, %eax # imm = 0x800 -; SSE2-NEXT: je .LBB15_24 -; SSE2-NEXT: # %bb.23: # %cond.store21 +; SSE2-NEXT: je .LBB15_21 +; SSE2-NEXT: # %bb.20: # %cond.store21 ; SSE2-NEXT: movb %ch, 11(%rdi) -; SSE2-NEXT: .LBB15_24: # %else22 +; SSE2-NEXT: .LBB15_21: # %else22 ; SSE2-NEXT: testl $4096, %eax # imm = 0x1000 ; SSE2-NEXT: pextrw $6, %xmm0, %ecx -; SSE2-NEXT: je .LBB15_26 -; SSE2-NEXT: # %bb.25: # %cond.store23 +; SSE2-NEXT: je .LBB15_23 +; SSE2-NEXT: # %bb.22: # %cond.store23 ; SSE2-NEXT: movb %cl, 12(%rdi) -; SSE2-NEXT: .LBB15_26: # %else24 +; SSE2-NEXT: .LBB15_23: # %else24 ; SSE2-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE2-NEXT: je .LBB15_28 -; SSE2-NEXT: # %bb.27: # %cond.store25 +; SSE2-NEXT: je .LBB15_25 +; SSE2-NEXT: # %bb.24: # %cond.store25 ; SSE2-NEXT: movb %ch, 13(%rdi) -; SSE2-NEXT: .LBB15_28: # %else26 +; SSE2-NEXT: .LBB15_25: # %else26 ; SSE2-NEXT: testl $16384, %eax # imm = 0x4000 ; SSE2-NEXT: pextrw $7, %xmm0, %ecx -; SSE2-NEXT: je .LBB15_30 -; SSE2-NEXT: # %bb.29: # %cond.store27 +; SSE2-NEXT: je .LBB15_27 +; SSE2-NEXT: # %bb.26: # %cond.store27 ; SSE2-NEXT: movb %cl, 14(%rdi) -; SSE2-NEXT: .LBB15_30: # %else28 +; SSE2-NEXT: .LBB15_27: # %else28 ; SSE2-NEXT: packsswb %xmm3, %xmm2 ; SSE2-NEXT: testw %ax, %ax -; SSE2-NEXT: jns .LBB15_32 -; SSE2-NEXT: # %bb.31: # %cond.store29 +; SSE2-NEXT: jns .LBB15_29 +; SSE2-NEXT: # %bb.28: # %cond.store29 ; SSE2-NEXT: movb %ch, 15(%rdi) -; SSE2-NEXT: .LBB15_32: # %else30 +; SSE2-NEXT: .LBB15_29: # %else30 ; SSE2-NEXT: testl $65536, %eax # imm = 0x10000 ; SSE2-NEXT: movd %xmm2, %ecx -; SSE2-NEXT: jne .LBB15_33 -; SSE2-NEXT: # %bb.34: # %else32 +; SSE2-NEXT: jne .LBB15_60 +; SSE2-NEXT: # %bb.30: # %else32 ; SSE2-NEXT: testl $131072, %eax # imm = 0x20000 -; SSE2-NEXT: jne .LBB15_35 -; SSE2-NEXT: .LBB15_36: # %else34 +; SSE2-NEXT: jne .LBB15_61 +; SSE2-NEXT: .LBB15_31: # %else34 ; SSE2-NEXT: testl $262144, %eax # imm = 0x40000 -; SSE2-NEXT: jne .LBB15_37 -; SSE2-NEXT: .LBB15_38: # %else36 +; SSE2-NEXT: jne .LBB15_62 +; SSE2-NEXT: .LBB15_32: # %else36 ; SSE2-NEXT: testl $524288, %eax # imm = 0x80000 -; SSE2-NEXT: je .LBB15_40 -; SSE2-NEXT: .LBB15_39: # %cond.store37 +; SSE2-NEXT: je .LBB15_34 +; SSE2-NEXT: .LBB15_33: # %cond.store37 ; SSE2-NEXT: shrl $24, %ecx ; SSE2-NEXT: movb %cl, 19(%rdi) -; SSE2-NEXT: .LBB15_40: # %else38 +; SSE2-NEXT: .LBB15_34: # %else38 ; SSE2-NEXT: testl $1048576, %eax # imm = 0x100000 ; SSE2-NEXT: pextrw $2, %xmm2, %ecx -; SSE2-NEXT: je .LBB15_42 -; SSE2-NEXT: # %bb.41: # %cond.store39 +; SSE2-NEXT: je .LBB15_36 +; SSE2-NEXT: # %bb.35: # %cond.store39 ; SSE2-NEXT: movb %cl, 20(%rdi) -; SSE2-NEXT: .LBB15_42: # %else40 +; SSE2-NEXT: .LBB15_36: # %else40 ; SSE2-NEXT: testl $2097152, %eax # imm = 0x200000 -; SSE2-NEXT: je .LBB15_44 -; SSE2-NEXT: # %bb.43: # %cond.store41 +; SSE2-NEXT: je .LBB15_38 +; SSE2-NEXT: # %bb.37: # %cond.store41 ; SSE2-NEXT: movb %ch, 21(%rdi) -; SSE2-NEXT: .LBB15_44: # %else42 +; SSE2-NEXT: .LBB15_38: # %else42 ; SSE2-NEXT: testl $4194304, %eax # imm = 0x400000 ; SSE2-NEXT: pextrw $3, %xmm2, %ecx -; SSE2-NEXT: je .LBB15_46 -; SSE2-NEXT: # %bb.45: # %cond.store43 +; SSE2-NEXT: je .LBB15_40 +; SSE2-NEXT: # %bb.39: # %cond.store43 ; SSE2-NEXT: movb %cl, 22(%rdi) -; SSE2-NEXT: .LBB15_46: # %else44 +; SSE2-NEXT: .LBB15_40: # %else44 ; SSE2-NEXT: testl $8388608, %eax # imm = 0x800000 -; SSE2-NEXT: je .LBB15_48 -; SSE2-NEXT: # %bb.47: # %cond.store45 +; SSE2-NEXT: je .LBB15_42 +; SSE2-NEXT: # %bb.41: # %cond.store45 ; SSE2-NEXT: movb %ch, 23(%rdi) -; SSE2-NEXT: .LBB15_48: # %else46 +; SSE2-NEXT: .LBB15_42: # %else46 ; SSE2-NEXT: testl $16777216, %eax # imm = 0x1000000 ; SSE2-NEXT: pextrw $4, %xmm2, %ecx -; SSE2-NEXT: je .LBB15_50 -; SSE2-NEXT: # %bb.49: # %cond.store47 +; SSE2-NEXT: je .LBB15_44 +; SSE2-NEXT: # %bb.43: # %cond.store47 ; SSE2-NEXT: movb %cl, 24(%rdi) -; SSE2-NEXT: .LBB15_50: # %else48 +; SSE2-NEXT: .LBB15_44: # %else48 ; SSE2-NEXT: testl $33554432, %eax # imm = 0x2000000 -; SSE2-NEXT: je .LBB15_52 -; SSE2-NEXT: # %bb.51: # %cond.store49 +; SSE2-NEXT: je .LBB15_46 +; SSE2-NEXT: # %bb.45: # %cond.store49 ; SSE2-NEXT: movb %ch, 25(%rdi) -; SSE2-NEXT: .LBB15_52: # %else50 +; SSE2-NEXT: .LBB15_46: # %else50 ; SSE2-NEXT: testl $67108864, %eax # imm = 0x4000000 ; SSE2-NEXT: pextrw $5, %xmm2, %ecx -; SSE2-NEXT: je .LBB15_54 -; SSE2-NEXT: # %bb.53: # %cond.store51 +; SSE2-NEXT: je .LBB15_48 +; SSE2-NEXT: # %bb.47: # %cond.store51 ; SSE2-NEXT: movb %cl, 26(%rdi) -; SSE2-NEXT: .LBB15_54: # %else52 +; SSE2-NEXT: .LBB15_48: # %else52 ; SSE2-NEXT: testl $134217728, %eax # imm = 0x8000000 -; SSE2-NEXT: je .LBB15_56 -; SSE2-NEXT: # %bb.55: # %cond.store53 +; SSE2-NEXT: je .LBB15_50 +; SSE2-NEXT: # %bb.49: # %cond.store53 ; SSE2-NEXT: movb %ch, 27(%rdi) -; SSE2-NEXT: .LBB15_56: # %else54 +; SSE2-NEXT: .LBB15_50: # %else54 ; SSE2-NEXT: testl $268435456, %eax # imm = 0x10000000 ; SSE2-NEXT: pextrw $6, %xmm2, %ecx -; SSE2-NEXT: je .LBB15_58 -; SSE2-NEXT: # %bb.57: # %cond.store55 +; SSE2-NEXT: je .LBB15_52 +; SSE2-NEXT: # %bb.51: # %cond.store55 ; SSE2-NEXT: movb %cl, 28(%rdi) -; SSE2-NEXT: .LBB15_58: # %else56 +; SSE2-NEXT: .LBB15_52: # %else56 ; SSE2-NEXT: testl $536870912, %eax # imm = 0x20000000 -; SSE2-NEXT: je .LBB15_60 -; SSE2-NEXT: # %bb.59: # %cond.store57 +; SSE2-NEXT: je .LBB15_54 +; SSE2-NEXT: # %bb.53: # %cond.store57 ; SSE2-NEXT: movb %ch, 29(%rdi) -; SSE2-NEXT: .LBB15_60: # %else58 +; SSE2-NEXT: .LBB15_54: # %else58 ; SSE2-NEXT: testl $1073741824, %eax # imm = 0x40000000 ; SSE2-NEXT: pextrw $7, %xmm2, %ecx -; SSE2-NEXT: jne .LBB15_61 -; SSE2-NEXT: # %bb.62: # %else60 -; SSE2-NEXT: testl $-2147483648, %eax # imm = 0x80000000 ; SSE2-NEXT: jne .LBB15_63 -; SSE2-NEXT: .LBB15_64: # %else62 +; SSE2-NEXT: # %bb.55: # %else60 +; SSE2-NEXT: testl $-2147483648, %eax # imm = 0x80000000 +; SSE2-NEXT: jne .LBB15_64 +; SSE2-NEXT: .LBB15_56: # %else62 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB15_1: # %cond.store +; SSE2-NEXT: .LBB15_57: # %cond.store ; SSE2-NEXT: movb %cl, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB15_4 -; SSE2-NEXT: .LBB15_3: # %cond.store1 +; SSE2-NEXT: je .LBB15_2 +; SSE2-NEXT: .LBB15_58: # %cond.store1 ; SSE2-NEXT: movb %ch, 1(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je .LBB15_6 -; SSE2-NEXT: .LBB15_5: # %cond.store3 +; SSE2-NEXT: je .LBB15_3 +; SSE2-NEXT: .LBB15_59: # %cond.store3 ; SSE2-NEXT: movl %ecx, %edx ; SSE2-NEXT: shrl $16, %edx ; SSE2-NEXT: movb %dl, 2(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne .LBB15_7 -; SSE2-NEXT: jmp .LBB15_8 -; SSE2-NEXT: .LBB15_33: # %cond.store31 +; SSE2-NEXT: jne .LBB15_4 +; SSE2-NEXT: jmp .LBB15_5 +; SSE2-NEXT: .LBB15_60: # %cond.store31 ; SSE2-NEXT: movb %cl, 16(%rdi) ; SSE2-NEXT: testl $131072, %eax # imm = 0x20000 -; SSE2-NEXT: je .LBB15_36 -; SSE2-NEXT: .LBB15_35: # %cond.store33 +; SSE2-NEXT: je .LBB15_31 +; SSE2-NEXT: .LBB15_61: # %cond.store33 ; SSE2-NEXT: movb %ch, 17(%rdi) ; SSE2-NEXT: testl $262144, %eax # imm = 0x40000 -; SSE2-NEXT: je .LBB15_38 -; SSE2-NEXT: .LBB15_37: # %cond.store35 +; SSE2-NEXT: je .LBB15_32 +; SSE2-NEXT: .LBB15_62: # %cond.store35 ; SSE2-NEXT: movl %ecx, %edx ; SSE2-NEXT: shrl $16, %edx ; SSE2-NEXT: movb %dl, 18(%rdi) ; SSE2-NEXT: testl $524288, %eax # imm = 0x80000 -; SSE2-NEXT: jne .LBB15_39 -; SSE2-NEXT: jmp .LBB15_40 -; SSE2-NEXT: .LBB15_61: # %cond.store59 +; SSE2-NEXT: jne .LBB15_33 +; SSE2-NEXT: jmp .LBB15_34 +; SSE2-NEXT: .LBB15_63: # %cond.store59 ; SSE2-NEXT: movb %cl, 30(%rdi) ; SSE2-NEXT: testl $-2147483648, %eax # imm = 0x80000000 -; SSE2-NEXT: je .LBB15_64 -; SSE2-NEXT: .LBB15_63: # %cond.store61 +; SSE2-NEXT: je .LBB15_56 +; SSE2-NEXT: .LBB15_64: # %cond.store61 ; SSE2-NEXT: movb %ch, 31(%rdi) ; SSE2-NEXT: retq ; @@ -6140,227 +6140,227 @@ define void @truncstore_v32i16_v32i8(<32 x i16> %x, ptr %p, <32 x i8> %mask) { ; SSE4-NEXT: shll $16, %eax ; SSE4-NEXT: orl %ecx, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB15_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB15_34 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB15_3 -; SSE4-NEXT: .LBB15_4: # %else2 +; SSE4-NEXT: jne .LBB15_35 +; SSE4-NEXT: .LBB15_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB15_5 -; SSE4-NEXT: .LBB15_6: # %else4 +; SSE4-NEXT: jne .LBB15_36 +; SSE4-NEXT: .LBB15_3: # %else4 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne .LBB15_7 -; SSE4-NEXT: .LBB15_8: # %else6 +; SSE4-NEXT: jne .LBB15_37 +; SSE4-NEXT: .LBB15_4: # %else6 ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: jne .LBB15_9 -; SSE4-NEXT: .LBB15_10: # %else8 +; SSE4-NEXT: jne .LBB15_38 +; SSE4-NEXT: .LBB15_5: # %else8 ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: jne .LBB15_11 -; SSE4-NEXT: .LBB15_12: # %else10 +; SSE4-NEXT: jne .LBB15_39 +; SSE4-NEXT: .LBB15_6: # %else10 ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: jne .LBB15_13 -; SSE4-NEXT: .LBB15_14: # %else12 +; SSE4-NEXT: jne .LBB15_40 +; SSE4-NEXT: .LBB15_7: # %else12 ; SSE4-NEXT: testb %al, %al -; SSE4-NEXT: js .LBB15_15 -; SSE4-NEXT: .LBB15_16: # %else14 +; SSE4-NEXT: js .LBB15_41 +; SSE4-NEXT: .LBB15_8: # %else14 ; SSE4-NEXT: testl $256, %eax # imm = 0x100 -; SSE4-NEXT: jne .LBB15_17 -; SSE4-NEXT: .LBB15_18: # %else16 +; SSE4-NEXT: jne .LBB15_42 +; SSE4-NEXT: .LBB15_9: # %else16 ; SSE4-NEXT: testl $512, %eax # imm = 0x200 -; SSE4-NEXT: jne .LBB15_19 -; SSE4-NEXT: .LBB15_20: # %else18 +; SSE4-NEXT: jne .LBB15_43 +; SSE4-NEXT: .LBB15_10: # %else18 ; SSE4-NEXT: testl $1024, %eax # imm = 0x400 -; SSE4-NEXT: jne .LBB15_21 -; SSE4-NEXT: .LBB15_22: # %else20 +; SSE4-NEXT: jne .LBB15_44 +; SSE4-NEXT: .LBB15_11: # %else20 ; SSE4-NEXT: testl $2048, %eax # imm = 0x800 -; SSE4-NEXT: jne .LBB15_23 -; SSE4-NEXT: .LBB15_24: # %else22 +; SSE4-NEXT: jne .LBB15_45 +; SSE4-NEXT: .LBB15_12: # %else22 ; SSE4-NEXT: testl $4096, %eax # imm = 0x1000 -; SSE4-NEXT: jne .LBB15_25 -; SSE4-NEXT: .LBB15_26: # %else24 +; SSE4-NEXT: jne .LBB15_46 +; SSE4-NEXT: .LBB15_13: # %else24 ; SSE4-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE4-NEXT: jne .LBB15_27 -; SSE4-NEXT: .LBB15_28: # %else26 +; SSE4-NEXT: jne .LBB15_47 +; SSE4-NEXT: .LBB15_14: # %else26 ; SSE4-NEXT: testl $16384, %eax # imm = 0x4000 -; SSE4-NEXT: jne .LBB15_29 -; SSE4-NEXT: .LBB15_30: # %else28 +; SSE4-NEXT: jne .LBB15_48 +; SSE4-NEXT: .LBB15_15: # %else28 ; SSE4-NEXT: testw %ax, %ax -; SSE4-NEXT: jns .LBB15_32 -; SSE4-NEXT: .LBB15_31: # %cond.store29 +; SSE4-NEXT: jns .LBB15_17 +; SSE4-NEXT: .LBB15_16: # %cond.store29 ; SSE4-NEXT: pextrb $15, %xmm0, 15(%rdi) -; SSE4-NEXT: .LBB15_32: # %else30 +; SSE4-NEXT: .LBB15_17: # %else30 ; SSE4-NEXT: packsswb %xmm3, %xmm2 ; SSE4-NEXT: testl $65536, %eax # imm = 0x10000 -; SSE4-NEXT: jne .LBB15_33 -; SSE4-NEXT: # %bb.34: # %else32 +; SSE4-NEXT: jne .LBB15_49 +; SSE4-NEXT: # %bb.18: # %else32 ; SSE4-NEXT: testl $131072, %eax # imm = 0x20000 -; SSE4-NEXT: jne .LBB15_35 -; SSE4-NEXT: .LBB15_36: # %else34 +; SSE4-NEXT: jne .LBB15_50 +; SSE4-NEXT: .LBB15_19: # %else34 ; SSE4-NEXT: testl $262144, %eax # imm = 0x40000 -; SSE4-NEXT: jne .LBB15_37 -; SSE4-NEXT: .LBB15_38: # %else36 +; SSE4-NEXT: jne .LBB15_51 +; SSE4-NEXT: .LBB15_20: # %else36 ; SSE4-NEXT: testl $524288, %eax # imm = 0x80000 -; SSE4-NEXT: jne .LBB15_39 -; SSE4-NEXT: .LBB15_40: # %else38 +; SSE4-NEXT: jne .LBB15_52 +; SSE4-NEXT: .LBB15_21: # %else38 ; SSE4-NEXT: testl $1048576, %eax # imm = 0x100000 -; SSE4-NEXT: jne .LBB15_41 -; SSE4-NEXT: .LBB15_42: # %else40 +; SSE4-NEXT: jne .LBB15_53 +; SSE4-NEXT: .LBB15_22: # %else40 ; SSE4-NEXT: testl $2097152, %eax # imm = 0x200000 -; SSE4-NEXT: jne .LBB15_43 -; SSE4-NEXT: .LBB15_44: # %else42 +; SSE4-NEXT: jne .LBB15_54 +; SSE4-NEXT: .LBB15_23: # %else42 ; SSE4-NEXT: testl $4194304, %eax # imm = 0x400000 -; SSE4-NEXT: jne .LBB15_45 -; SSE4-NEXT: .LBB15_46: # %else44 +; SSE4-NEXT: jne .LBB15_55 +; SSE4-NEXT: .LBB15_24: # %else44 ; SSE4-NEXT: testl $8388608, %eax # imm = 0x800000 -; SSE4-NEXT: jne .LBB15_47 -; SSE4-NEXT: .LBB15_48: # %else46 +; SSE4-NEXT: jne .LBB15_56 +; SSE4-NEXT: .LBB15_25: # %else46 ; SSE4-NEXT: testl $16777216, %eax # imm = 0x1000000 -; SSE4-NEXT: jne .LBB15_49 -; SSE4-NEXT: .LBB15_50: # %else48 +; SSE4-NEXT: jne .LBB15_57 +; SSE4-NEXT: .LBB15_26: # %else48 ; SSE4-NEXT: testl $33554432, %eax # imm = 0x2000000 -; SSE4-NEXT: jne .LBB15_51 -; SSE4-NEXT: .LBB15_52: # %else50 +; SSE4-NEXT: jne .LBB15_58 +; SSE4-NEXT: .LBB15_27: # %else50 ; SSE4-NEXT: testl $67108864, %eax # imm = 0x4000000 -; SSE4-NEXT: jne .LBB15_53 -; SSE4-NEXT: .LBB15_54: # %else52 +; SSE4-NEXT: jne .LBB15_59 +; SSE4-NEXT: .LBB15_28: # %else52 ; SSE4-NEXT: testl $134217728, %eax # imm = 0x8000000 -; SSE4-NEXT: jne .LBB15_55 -; SSE4-NEXT: .LBB15_56: # %else54 +; SSE4-NEXT: jne .LBB15_60 +; SSE4-NEXT: .LBB15_29: # %else54 ; SSE4-NEXT: testl $268435456, %eax # imm = 0x10000000 -; SSE4-NEXT: jne .LBB15_57 -; SSE4-NEXT: .LBB15_58: # %else56 +; SSE4-NEXT: jne .LBB15_61 +; SSE4-NEXT: .LBB15_30: # %else56 ; SSE4-NEXT: testl $536870912, %eax # imm = 0x20000000 -; SSE4-NEXT: jne .LBB15_59 -; SSE4-NEXT: .LBB15_60: # %else58 +; SSE4-NEXT: jne .LBB15_62 +; SSE4-NEXT: .LBB15_31: # %else58 ; SSE4-NEXT: testl $1073741824, %eax # imm = 0x40000000 -; SSE4-NEXT: jne .LBB15_61 -; SSE4-NEXT: .LBB15_62: # %else60 -; SSE4-NEXT: testl $-2147483648, %eax # imm = 0x80000000 ; SSE4-NEXT: jne .LBB15_63 -; SSE4-NEXT: .LBB15_64: # %else62 +; SSE4-NEXT: .LBB15_32: # %else60 +; SSE4-NEXT: testl $-2147483648, %eax # imm = 0x80000000 +; SSE4-NEXT: jne .LBB15_64 +; SSE4-NEXT: .LBB15_33: # %else62 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB15_1: # %cond.store +; SSE4-NEXT: .LBB15_34: # %cond.store ; SSE4-NEXT: pextrb $0, %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB15_4 -; SSE4-NEXT: .LBB15_3: # %cond.store1 +; SSE4-NEXT: je .LBB15_2 +; SSE4-NEXT: .LBB15_35: # %cond.store1 ; SSE4-NEXT: pextrb $1, %xmm0, 1(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB15_6 -; SSE4-NEXT: .LBB15_5: # %cond.store3 +; SSE4-NEXT: je .LBB15_3 +; SSE4-NEXT: .LBB15_36: # %cond.store3 ; SSE4-NEXT: pextrb $2, %xmm0, 2(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB15_8 -; SSE4-NEXT: .LBB15_7: # %cond.store5 +; SSE4-NEXT: je .LBB15_4 +; SSE4-NEXT: .LBB15_37: # %cond.store5 ; SSE4-NEXT: pextrb $3, %xmm0, 3(%rdi) ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: je .LBB15_10 -; SSE4-NEXT: .LBB15_9: # %cond.store7 +; SSE4-NEXT: je .LBB15_5 +; SSE4-NEXT: .LBB15_38: # %cond.store7 ; SSE4-NEXT: pextrb $4, %xmm0, 4(%rdi) ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: je .LBB15_12 -; SSE4-NEXT: .LBB15_11: # %cond.store9 +; SSE4-NEXT: je .LBB15_6 +; SSE4-NEXT: .LBB15_39: # %cond.store9 ; SSE4-NEXT: pextrb $5, %xmm0, 5(%rdi) ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: je .LBB15_14 -; SSE4-NEXT: .LBB15_13: # %cond.store11 +; SSE4-NEXT: je .LBB15_7 +; SSE4-NEXT: .LBB15_40: # %cond.store11 ; SSE4-NEXT: pextrb $6, %xmm0, 6(%rdi) ; SSE4-NEXT: testb %al, %al -; SSE4-NEXT: jns .LBB15_16 -; SSE4-NEXT: .LBB15_15: # %cond.store13 +; SSE4-NEXT: jns .LBB15_8 +; SSE4-NEXT: .LBB15_41: # %cond.store13 ; SSE4-NEXT: pextrb $7, %xmm0, 7(%rdi) ; SSE4-NEXT: testl $256, %eax # imm = 0x100 -; SSE4-NEXT: je .LBB15_18 -; SSE4-NEXT: .LBB15_17: # %cond.store15 +; SSE4-NEXT: je .LBB15_9 +; SSE4-NEXT: .LBB15_42: # %cond.store15 ; SSE4-NEXT: pextrb $8, %xmm0, 8(%rdi) ; SSE4-NEXT: testl $512, %eax # imm = 0x200 -; SSE4-NEXT: je .LBB15_20 -; SSE4-NEXT: .LBB15_19: # %cond.store17 +; SSE4-NEXT: je .LBB15_10 +; SSE4-NEXT: .LBB15_43: # %cond.store17 ; SSE4-NEXT: pextrb $9, %xmm0, 9(%rdi) ; SSE4-NEXT: testl $1024, %eax # imm = 0x400 -; SSE4-NEXT: je .LBB15_22 -; SSE4-NEXT: .LBB15_21: # %cond.store19 +; SSE4-NEXT: je .LBB15_11 +; SSE4-NEXT: .LBB15_44: # %cond.store19 ; SSE4-NEXT: pextrb $10, %xmm0, 10(%rdi) ; SSE4-NEXT: testl $2048, %eax # imm = 0x800 -; SSE4-NEXT: je .LBB15_24 -; SSE4-NEXT: .LBB15_23: # %cond.store21 +; SSE4-NEXT: je .LBB15_12 +; SSE4-NEXT: .LBB15_45: # %cond.store21 ; SSE4-NEXT: pextrb $11, %xmm0, 11(%rdi) ; SSE4-NEXT: testl $4096, %eax # imm = 0x1000 -; SSE4-NEXT: je .LBB15_26 -; SSE4-NEXT: .LBB15_25: # %cond.store23 +; SSE4-NEXT: je .LBB15_13 +; SSE4-NEXT: .LBB15_46: # %cond.store23 ; SSE4-NEXT: pextrb $12, %xmm0, 12(%rdi) ; SSE4-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE4-NEXT: je .LBB15_28 -; SSE4-NEXT: .LBB15_27: # %cond.store25 +; SSE4-NEXT: je .LBB15_14 +; SSE4-NEXT: .LBB15_47: # %cond.store25 ; SSE4-NEXT: pextrb $13, %xmm0, 13(%rdi) ; SSE4-NEXT: testl $16384, %eax # imm = 0x4000 -; SSE4-NEXT: je .LBB15_30 -; SSE4-NEXT: .LBB15_29: # %cond.store27 +; SSE4-NEXT: je .LBB15_15 +; SSE4-NEXT: .LBB15_48: # %cond.store27 ; SSE4-NEXT: pextrb $14, %xmm0, 14(%rdi) ; SSE4-NEXT: testw %ax, %ax -; SSE4-NEXT: js .LBB15_31 -; SSE4-NEXT: jmp .LBB15_32 -; SSE4-NEXT: .LBB15_33: # %cond.store31 +; SSE4-NEXT: js .LBB15_16 +; SSE4-NEXT: jmp .LBB15_17 +; SSE4-NEXT: .LBB15_49: # %cond.store31 ; SSE4-NEXT: pextrb $0, %xmm2, 16(%rdi) ; SSE4-NEXT: testl $131072, %eax # imm = 0x20000 -; SSE4-NEXT: je .LBB15_36 -; SSE4-NEXT: .LBB15_35: # %cond.store33 +; SSE4-NEXT: je .LBB15_19 +; SSE4-NEXT: .LBB15_50: # %cond.store33 ; SSE4-NEXT: pextrb $1, %xmm2, 17(%rdi) ; SSE4-NEXT: testl $262144, %eax # imm = 0x40000 -; SSE4-NEXT: je .LBB15_38 -; SSE4-NEXT: .LBB15_37: # %cond.store35 +; SSE4-NEXT: je .LBB15_20 +; SSE4-NEXT: .LBB15_51: # %cond.store35 ; SSE4-NEXT: pextrb $2, %xmm2, 18(%rdi) ; SSE4-NEXT: testl $524288, %eax # imm = 0x80000 -; SSE4-NEXT: je .LBB15_40 -; SSE4-NEXT: .LBB15_39: # %cond.store37 +; SSE4-NEXT: je .LBB15_21 +; SSE4-NEXT: .LBB15_52: # %cond.store37 ; SSE4-NEXT: pextrb $3, %xmm2, 19(%rdi) ; SSE4-NEXT: testl $1048576, %eax # imm = 0x100000 -; SSE4-NEXT: je .LBB15_42 -; SSE4-NEXT: .LBB15_41: # %cond.store39 +; SSE4-NEXT: je .LBB15_22 +; SSE4-NEXT: .LBB15_53: # %cond.store39 ; SSE4-NEXT: pextrb $4, %xmm2, 20(%rdi) ; SSE4-NEXT: testl $2097152, %eax # imm = 0x200000 -; SSE4-NEXT: je .LBB15_44 -; SSE4-NEXT: .LBB15_43: # %cond.store41 +; SSE4-NEXT: je .LBB15_23 +; SSE4-NEXT: .LBB15_54: # %cond.store41 ; SSE4-NEXT: pextrb $5, %xmm2, 21(%rdi) ; SSE4-NEXT: testl $4194304, %eax # imm = 0x400000 -; SSE4-NEXT: je .LBB15_46 -; SSE4-NEXT: .LBB15_45: # %cond.store43 +; SSE4-NEXT: je .LBB15_24 +; SSE4-NEXT: .LBB15_55: # %cond.store43 ; SSE4-NEXT: pextrb $6, %xmm2, 22(%rdi) ; SSE4-NEXT: testl $8388608, %eax # imm = 0x800000 -; SSE4-NEXT: je .LBB15_48 -; SSE4-NEXT: .LBB15_47: # %cond.store45 +; SSE4-NEXT: je .LBB15_25 +; SSE4-NEXT: .LBB15_56: # %cond.store45 ; SSE4-NEXT: pextrb $7, %xmm2, 23(%rdi) ; SSE4-NEXT: testl $16777216, %eax # imm = 0x1000000 -; SSE4-NEXT: je .LBB15_50 -; SSE4-NEXT: .LBB15_49: # %cond.store47 +; SSE4-NEXT: je .LBB15_26 +; SSE4-NEXT: .LBB15_57: # %cond.store47 ; SSE4-NEXT: pextrb $8, %xmm2, 24(%rdi) ; SSE4-NEXT: testl $33554432, %eax # imm = 0x2000000 -; SSE4-NEXT: je .LBB15_52 -; SSE4-NEXT: .LBB15_51: # %cond.store49 +; SSE4-NEXT: je .LBB15_27 +; SSE4-NEXT: .LBB15_58: # %cond.store49 ; SSE4-NEXT: pextrb $9, %xmm2, 25(%rdi) ; SSE4-NEXT: testl $67108864, %eax # imm = 0x4000000 -; SSE4-NEXT: je .LBB15_54 -; SSE4-NEXT: .LBB15_53: # %cond.store51 +; SSE4-NEXT: je .LBB15_28 +; SSE4-NEXT: .LBB15_59: # %cond.store51 ; SSE4-NEXT: pextrb $10, %xmm2, 26(%rdi) ; SSE4-NEXT: testl $134217728, %eax # imm = 0x8000000 -; SSE4-NEXT: je .LBB15_56 -; SSE4-NEXT: .LBB15_55: # %cond.store53 +; SSE4-NEXT: je .LBB15_29 +; SSE4-NEXT: .LBB15_60: # %cond.store53 ; SSE4-NEXT: pextrb $11, %xmm2, 27(%rdi) ; SSE4-NEXT: testl $268435456, %eax # imm = 0x10000000 -; SSE4-NEXT: je .LBB15_58 -; SSE4-NEXT: .LBB15_57: # %cond.store55 +; SSE4-NEXT: je .LBB15_30 +; SSE4-NEXT: .LBB15_61: # %cond.store55 ; SSE4-NEXT: pextrb $12, %xmm2, 28(%rdi) ; SSE4-NEXT: testl $536870912, %eax # imm = 0x20000000 -; SSE4-NEXT: je .LBB15_60 -; SSE4-NEXT: .LBB15_59: # %cond.store57 +; SSE4-NEXT: je .LBB15_31 +; SSE4-NEXT: .LBB15_62: # %cond.store57 ; SSE4-NEXT: pextrb $13, %xmm2, 29(%rdi) ; SSE4-NEXT: testl $1073741824, %eax # imm = 0x40000000 -; SSE4-NEXT: je .LBB15_62 -; SSE4-NEXT: .LBB15_61: # %cond.store59 +; SSE4-NEXT: je .LBB15_32 +; SSE4-NEXT: .LBB15_63: # %cond.store59 ; SSE4-NEXT: pextrb $14, %xmm2, 30(%rdi) ; SSE4-NEXT: testl $-2147483648, %eax # imm = 0x80000000 -; SSE4-NEXT: je .LBB15_64 -; SSE4-NEXT: .LBB15_63: # %cond.store61 +; SSE4-NEXT: je .LBB15_33 +; SSE4-NEXT: .LBB15_64: # %cond.store61 ; SSE4-NEXT: pextrb $15, %xmm2, 31(%rdi) ; SSE4-NEXT: retq ; @@ -6382,228 +6382,228 @@ define void @truncstore_v32i16_v32i8(<32 x i16> %x, ptr %p, <32 x i8> %mask) { ; AVX1-NEXT: shll $16, %eax ; AVX1-NEXT: orl %ecx, %eax ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne .LBB15_1 -; AVX1-NEXT: # %bb.2: # %else +; AVX1-NEXT: jne .LBB15_34 +; AVX1-NEXT: # %bb.1: # %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne .LBB15_3 -; AVX1-NEXT: .LBB15_4: # %else2 +; AVX1-NEXT: jne .LBB15_35 +; AVX1-NEXT: .LBB15_2: # %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne .LBB15_5 -; AVX1-NEXT: .LBB15_6: # %else4 +; AVX1-NEXT: jne .LBB15_36 +; AVX1-NEXT: .LBB15_3: # %else4 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne .LBB15_7 -; AVX1-NEXT: .LBB15_8: # %else6 +; AVX1-NEXT: jne .LBB15_37 +; AVX1-NEXT: .LBB15_4: # %else6 ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: jne .LBB15_9 -; AVX1-NEXT: .LBB15_10: # %else8 +; AVX1-NEXT: jne .LBB15_38 +; AVX1-NEXT: .LBB15_5: # %else8 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: jne .LBB15_11 -; AVX1-NEXT: .LBB15_12: # %else10 +; AVX1-NEXT: jne .LBB15_39 +; AVX1-NEXT: .LBB15_6: # %else10 ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: jne .LBB15_13 -; AVX1-NEXT: .LBB15_14: # %else12 +; AVX1-NEXT: jne .LBB15_40 +; AVX1-NEXT: .LBB15_7: # %else12 ; AVX1-NEXT: testb %al, %al -; AVX1-NEXT: js .LBB15_15 -; AVX1-NEXT: .LBB15_16: # %else14 +; AVX1-NEXT: js .LBB15_41 +; AVX1-NEXT: .LBB15_8: # %else14 ; AVX1-NEXT: testl $256, %eax # imm = 0x100 -; AVX1-NEXT: jne .LBB15_17 -; AVX1-NEXT: .LBB15_18: # %else16 +; AVX1-NEXT: jne .LBB15_42 +; AVX1-NEXT: .LBB15_9: # %else16 ; AVX1-NEXT: testl $512, %eax # imm = 0x200 -; AVX1-NEXT: jne .LBB15_19 -; AVX1-NEXT: .LBB15_20: # %else18 +; AVX1-NEXT: jne .LBB15_43 +; AVX1-NEXT: .LBB15_10: # %else18 ; AVX1-NEXT: testl $1024, %eax # imm = 0x400 -; AVX1-NEXT: jne .LBB15_21 -; AVX1-NEXT: .LBB15_22: # %else20 +; AVX1-NEXT: jne .LBB15_44 +; AVX1-NEXT: .LBB15_11: # %else20 ; AVX1-NEXT: testl $2048, %eax # imm = 0x800 -; AVX1-NEXT: jne .LBB15_23 -; AVX1-NEXT: .LBB15_24: # %else22 +; AVX1-NEXT: jne .LBB15_45 +; AVX1-NEXT: .LBB15_12: # %else22 ; AVX1-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX1-NEXT: jne .LBB15_25 -; AVX1-NEXT: .LBB15_26: # %else24 +; AVX1-NEXT: jne .LBB15_46 +; AVX1-NEXT: .LBB15_13: # %else24 ; AVX1-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX1-NEXT: jne .LBB15_27 -; AVX1-NEXT: .LBB15_28: # %else26 +; AVX1-NEXT: jne .LBB15_47 +; AVX1-NEXT: .LBB15_14: # %else26 ; AVX1-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX1-NEXT: jne .LBB15_29 -; AVX1-NEXT: .LBB15_30: # %else28 +; AVX1-NEXT: jne .LBB15_48 +; AVX1-NEXT: .LBB15_15: # %else28 ; AVX1-NEXT: testw %ax, %ax -; AVX1-NEXT: jns .LBB15_32 -; AVX1-NEXT: .LBB15_31: # %cond.store29 +; AVX1-NEXT: jns .LBB15_17 +; AVX1-NEXT: .LBB15_16: # %cond.store29 ; AVX1-NEXT: vpextrb $15, %xmm0, 15(%rdi) -; AVX1-NEXT: .LBB15_32: # %else30 +; AVX1-NEXT: .LBB15_17: # %else30 ; AVX1-NEXT: testl $65536, %eax # imm = 0x10000 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 -; AVX1-NEXT: jne .LBB15_33 -; AVX1-NEXT: # %bb.34: # %else32 +; AVX1-NEXT: jne .LBB15_49 +; AVX1-NEXT: # %bb.18: # %else32 ; AVX1-NEXT: testl $131072, %eax # imm = 0x20000 -; AVX1-NEXT: jne .LBB15_35 -; AVX1-NEXT: .LBB15_36: # %else34 +; AVX1-NEXT: jne .LBB15_50 +; AVX1-NEXT: .LBB15_19: # %else34 ; AVX1-NEXT: testl $262144, %eax # imm = 0x40000 -; AVX1-NEXT: jne .LBB15_37 -; AVX1-NEXT: .LBB15_38: # %else36 +; AVX1-NEXT: jne .LBB15_51 +; AVX1-NEXT: .LBB15_20: # %else36 ; AVX1-NEXT: testl $524288, %eax # imm = 0x80000 -; AVX1-NEXT: jne .LBB15_39 -; AVX1-NEXT: .LBB15_40: # %else38 +; AVX1-NEXT: jne .LBB15_52 +; AVX1-NEXT: .LBB15_21: # %else38 ; AVX1-NEXT: testl $1048576, %eax # imm = 0x100000 -; AVX1-NEXT: jne .LBB15_41 -; AVX1-NEXT: .LBB15_42: # %else40 +; AVX1-NEXT: jne .LBB15_53 +; AVX1-NEXT: .LBB15_22: # %else40 ; AVX1-NEXT: testl $2097152, %eax # imm = 0x200000 -; AVX1-NEXT: jne .LBB15_43 -; AVX1-NEXT: .LBB15_44: # %else42 +; AVX1-NEXT: jne .LBB15_54 +; AVX1-NEXT: .LBB15_23: # %else42 ; AVX1-NEXT: testl $4194304, %eax # imm = 0x400000 -; AVX1-NEXT: jne .LBB15_45 -; AVX1-NEXT: .LBB15_46: # %else44 +; AVX1-NEXT: jne .LBB15_55 +; AVX1-NEXT: .LBB15_24: # %else44 ; AVX1-NEXT: testl $8388608, %eax # imm = 0x800000 -; AVX1-NEXT: jne .LBB15_47 -; AVX1-NEXT: .LBB15_48: # %else46 +; AVX1-NEXT: jne .LBB15_56 +; AVX1-NEXT: .LBB15_25: # %else46 ; AVX1-NEXT: testl $16777216, %eax # imm = 0x1000000 -; AVX1-NEXT: jne .LBB15_49 -; AVX1-NEXT: .LBB15_50: # %else48 +; AVX1-NEXT: jne .LBB15_57 +; AVX1-NEXT: .LBB15_26: # %else48 ; AVX1-NEXT: testl $33554432, %eax # imm = 0x2000000 -; AVX1-NEXT: jne .LBB15_51 -; AVX1-NEXT: .LBB15_52: # %else50 +; AVX1-NEXT: jne .LBB15_58 +; AVX1-NEXT: .LBB15_27: # %else50 ; AVX1-NEXT: testl $67108864, %eax # imm = 0x4000000 -; AVX1-NEXT: jne .LBB15_53 -; AVX1-NEXT: .LBB15_54: # %else52 +; AVX1-NEXT: jne .LBB15_59 +; AVX1-NEXT: .LBB15_28: # %else52 ; AVX1-NEXT: testl $134217728, %eax # imm = 0x8000000 -; AVX1-NEXT: jne .LBB15_55 -; AVX1-NEXT: .LBB15_56: # %else54 +; AVX1-NEXT: jne .LBB15_60 +; AVX1-NEXT: .LBB15_29: # %else54 ; AVX1-NEXT: testl $268435456, %eax # imm = 0x10000000 -; AVX1-NEXT: jne .LBB15_57 -; AVX1-NEXT: .LBB15_58: # %else56 +; AVX1-NEXT: jne .LBB15_61 +; AVX1-NEXT: .LBB15_30: # %else56 ; AVX1-NEXT: testl $536870912, %eax # imm = 0x20000000 -; AVX1-NEXT: jne .LBB15_59 -; AVX1-NEXT: .LBB15_60: # %else58 +; AVX1-NEXT: jne .LBB15_62 +; AVX1-NEXT: .LBB15_31: # %else58 ; AVX1-NEXT: testl $1073741824, %eax # imm = 0x40000000 -; AVX1-NEXT: jne .LBB15_61 -; AVX1-NEXT: .LBB15_62: # %else60 -; AVX1-NEXT: testl $-2147483648, %eax # imm = 0x80000000 ; AVX1-NEXT: jne .LBB15_63 -; AVX1-NEXT: .LBB15_64: # %else62 +; AVX1-NEXT: .LBB15_32: # %else60 +; AVX1-NEXT: testl $-2147483648, %eax # imm = 0x80000000 +; AVX1-NEXT: jne .LBB15_64 +; AVX1-NEXT: .LBB15_33: # %else62 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB15_1: # %cond.store +; AVX1-NEXT: .LBB15_34: # %cond.store ; AVX1-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je .LBB15_4 -; AVX1-NEXT: .LBB15_3: # %cond.store1 +; AVX1-NEXT: je .LBB15_2 +; AVX1-NEXT: .LBB15_35: # %cond.store1 ; AVX1-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je .LBB15_6 -; AVX1-NEXT: .LBB15_5: # %cond.store3 +; AVX1-NEXT: je .LBB15_3 +; AVX1-NEXT: .LBB15_36: # %cond.store3 ; AVX1-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB15_8 -; AVX1-NEXT: .LBB15_7: # %cond.store5 +; AVX1-NEXT: je .LBB15_4 +; AVX1-NEXT: .LBB15_37: # %cond.store5 ; AVX1-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: je .LBB15_10 -; AVX1-NEXT: .LBB15_9: # %cond.store7 +; AVX1-NEXT: je .LBB15_5 +; AVX1-NEXT: .LBB15_38: # %cond.store7 ; AVX1-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je .LBB15_12 -; AVX1-NEXT: .LBB15_11: # %cond.store9 +; AVX1-NEXT: je .LBB15_6 +; AVX1-NEXT: .LBB15_39: # %cond.store9 ; AVX1-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: je .LBB15_14 -; AVX1-NEXT: .LBB15_13: # %cond.store11 +; AVX1-NEXT: je .LBB15_7 +; AVX1-NEXT: .LBB15_40: # %cond.store11 ; AVX1-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX1-NEXT: testb %al, %al -; AVX1-NEXT: jns .LBB15_16 -; AVX1-NEXT: .LBB15_15: # %cond.store13 +; AVX1-NEXT: jns .LBB15_8 +; AVX1-NEXT: .LBB15_41: # %cond.store13 ; AVX1-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX1-NEXT: testl $256, %eax # imm = 0x100 -; AVX1-NEXT: je .LBB15_18 -; AVX1-NEXT: .LBB15_17: # %cond.store15 +; AVX1-NEXT: je .LBB15_9 +; AVX1-NEXT: .LBB15_42: # %cond.store15 ; AVX1-NEXT: vpextrb $8, %xmm0, 8(%rdi) ; AVX1-NEXT: testl $512, %eax # imm = 0x200 -; AVX1-NEXT: je .LBB15_20 -; AVX1-NEXT: .LBB15_19: # %cond.store17 +; AVX1-NEXT: je .LBB15_10 +; AVX1-NEXT: .LBB15_43: # %cond.store17 ; AVX1-NEXT: vpextrb $9, %xmm0, 9(%rdi) ; AVX1-NEXT: testl $1024, %eax # imm = 0x400 -; AVX1-NEXT: je .LBB15_22 -; AVX1-NEXT: .LBB15_21: # %cond.store19 +; AVX1-NEXT: je .LBB15_11 +; AVX1-NEXT: .LBB15_44: # %cond.store19 ; AVX1-NEXT: vpextrb $10, %xmm0, 10(%rdi) ; AVX1-NEXT: testl $2048, %eax # imm = 0x800 -; AVX1-NEXT: je .LBB15_24 -; AVX1-NEXT: .LBB15_23: # %cond.store21 +; AVX1-NEXT: je .LBB15_12 +; AVX1-NEXT: .LBB15_45: # %cond.store21 ; AVX1-NEXT: vpextrb $11, %xmm0, 11(%rdi) ; AVX1-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX1-NEXT: je .LBB15_26 -; AVX1-NEXT: .LBB15_25: # %cond.store23 +; AVX1-NEXT: je .LBB15_13 +; AVX1-NEXT: .LBB15_46: # %cond.store23 ; AVX1-NEXT: vpextrb $12, %xmm0, 12(%rdi) ; AVX1-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX1-NEXT: je .LBB15_28 -; AVX1-NEXT: .LBB15_27: # %cond.store25 +; AVX1-NEXT: je .LBB15_14 +; AVX1-NEXT: .LBB15_47: # %cond.store25 ; AVX1-NEXT: vpextrb $13, %xmm0, 13(%rdi) ; AVX1-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX1-NEXT: je .LBB15_30 -; AVX1-NEXT: .LBB15_29: # %cond.store27 +; AVX1-NEXT: je .LBB15_15 +; AVX1-NEXT: .LBB15_48: # %cond.store27 ; AVX1-NEXT: vpextrb $14, %xmm0, 14(%rdi) ; AVX1-NEXT: testw %ax, %ax -; AVX1-NEXT: js .LBB15_31 -; AVX1-NEXT: jmp .LBB15_32 -; AVX1-NEXT: .LBB15_33: # %cond.store31 +; AVX1-NEXT: js .LBB15_16 +; AVX1-NEXT: jmp .LBB15_17 +; AVX1-NEXT: .LBB15_49: # %cond.store31 ; AVX1-NEXT: vpextrb $0, %xmm0, 16(%rdi) ; AVX1-NEXT: testl $131072, %eax # imm = 0x20000 -; AVX1-NEXT: je .LBB15_36 -; AVX1-NEXT: .LBB15_35: # %cond.store33 +; AVX1-NEXT: je .LBB15_19 +; AVX1-NEXT: .LBB15_50: # %cond.store33 ; AVX1-NEXT: vpextrb $1, %xmm0, 17(%rdi) ; AVX1-NEXT: testl $262144, %eax # imm = 0x40000 -; AVX1-NEXT: je .LBB15_38 -; AVX1-NEXT: .LBB15_37: # %cond.store35 +; AVX1-NEXT: je .LBB15_20 +; AVX1-NEXT: .LBB15_51: # %cond.store35 ; AVX1-NEXT: vpextrb $2, %xmm0, 18(%rdi) ; AVX1-NEXT: testl $524288, %eax # imm = 0x80000 -; AVX1-NEXT: je .LBB15_40 -; AVX1-NEXT: .LBB15_39: # %cond.store37 +; AVX1-NEXT: je .LBB15_21 +; AVX1-NEXT: .LBB15_52: # %cond.store37 ; AVX1-NEXT: vpextrb $3, %xmm0, 19(%rdi) ; AVX1-NEXT: testl $1048576, %eax # imm = 0x100000 -; AVX1-NEXT: je .LBB15_42 -; AVX1-NEXT: .LBB15_41: # %cond.store39 +; AVX1-NEXT: je .LBB15_22 +; AVX1-NEXT: .LBB15_53: # %cond.store39 ; AVX1-NEXT: vpextrb $4, %xmm0, 20(%rdi) ; AVX1-NEXT: testl $2097152, %eax # imm = 0x200000 -; AVX1-NEXT: je .LBB15_44 -; AVX1-NEXT: .LBB15_43: # %cond.store41 +; AVX1-NEXT: je .LBB15_23 +; AVX1-NEXT: .LBB15_54: # %cond.store41 ; AVX1-NEXT: vpextrb $5, %xmm0, 21(%rdi) ; AVX1-NEXT: testl $4194304, %eax # imm = 0x400000 -; AVX1-NEXT: je .LBB15_46 -; AVX1-NEXT: .LBB15_45: # %cond.store43 +; AVX1-NEXT: je .LBB15_24 +; AVX1-NEXT: .LBB15_55: # %cond.store43 ; AVX1-NEXT: vpextrb $6, %xmm0, 22(%rdi) ; AVX1-NEXT: testl $8388608, %eax # imm = 0x800000 -; AVX1-NEXT: je .LBB15_48 -; AVX1-NEXT: .LBB15_47: # %cond.store45 +; AVX1-NEXT: je .LBB15_25 +; AVX1-NEXT: .LBB15_56: # %cond.store45 ; AVX1-NEXT: vpextrb $7, %xmm0, 23(%rdi) ; AVX1-NEXT: testl $16777216, %eax # imm = 0x1000000 -; AVX1-NEXT: je .LBB15_50 -; AVX1-NEXT: .LBB15_49: # %cond.store47 +; AVX1-NEXT: je .LBB15_26 +; AVX1-NEXT: .LBB15_57: # %cond.store47 ; AVX1-NEXT: vpextrb $8, %xmm0, 24(%rdi) ; AVX1-NEXT: testl $33554432, %eax # imm = 0x2000000 -; AVX1-NEXT: je .LBB15_52 -; AVX1-NEXT: .LBB15_51: # %cond.store49 +; AVX1-NEXT: je .LBB15_27 +; AVX1-NEXT: .LBB15_58: # %cond.store49 ; AVX1-NEXT: vpextrb $9, %xmm0, 25(%rdi) ; AVX1-NEXT: testl $67108864, %eax # imm = 0x4000000 -; AVX1-NEXT: je .LBB15_54 -; AVX1-NEXT: .LBB15_53: # %cond.store51 +; AVX1-NEXT: je .LBB15_28 +; AVX1-NEXT: .LBB15_59: # %cond.store51 ; AVX1-NEXT: vpextrb $10, %xmm0, 26(%rdi) ; AVX1-NEXT: testl $134217728, %eax # imm = 0x8000000 -; AVX1-NEXT: je .LBB15_56 -; AVX1-NEXT: .LBB15_55: # %cond.store53 +; AVX1-NEXT: je .LBB15_29 +; AVX1-NEXT: .LBB15_60: # %cond.store53 ; AVX1-NEXT: vpextrb $11, %xmm0, 27(%rdi) ; AVX1-NEXT: testl $268435456, %eax # imm = 0x10000000 -; AVX1-NEXT: je .LBB15_58 -; AVX1-NEXT: .LBB15_57: # %cond.store55 +; AVX1-NEXT: je .LBB15_30 +; AVX1-NEXT: .LBB15_61: # %cond.store55 ; AVX1-NEXT: vpextrb $12, %xmm0, 28(%rdi) ; AVX1-NEXT: testl $536870912, %eax # imm = 0x20000000 -; AVX1-NEXT: je .LBB15_60 -; AVX1-NEXT: .LBB15_59: # %cond.store57 +; AVX1-NEXT: je .LBB15_31 +; AVX1-NEXT: .LBB15_62: # %cond.store57 ; AVX1-NEXT: vpextrb $13, %xmm0, 29(%rdi) ; AVX1-NEXT: testl $1073741824, %eax # imm = 0x40000000 -; AVX1-NEXT: je .LBB15_62 -; AVX1-NEXT: .LBB15_61: # %cond.store59 +; AVX1-NEXT: je .LBB15_32 +; AVX1-NEXT: .LBB15_63: # %cond.store59 ; AVX1-NEXT: vpextrb $14, %xmm0, 30(%rdi) ; AVX1-NEXT: testl $-2147483648, %eax # imm = 0x80000000 -; AVX1-NEXT: je .LBB15_64 -; AVX1-NEXT: .LBB15_63: # %cond.store61 +; AVX1-NEXT: je .LBB15_33 +; AVX1-NEXT: .LBB15_64: # %cond.store61 ; AVX1-NEXT: vpextrb $15, %xmm0, 31(%rdi) ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq @@ -6617,228 +6617,228 @@ define void @truncstore_v32i16_v32i8(<32 x i16> %x, ptr %p, <32 x i8> %mask) { ; AVX2-NEXT: vpmovmskb %ymm1, %eax ; AVX2-NEXT: notl %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne .LBB15_1 -; AVX2-NEXT: # %bb.2: # %else +; AVX2-NEXT: jne .LBB15_34 +; AVX2-NEXT: # %bb.1: # %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne .LBB15_3 -; AVX2-NEXT: .LBB15_4: # %else2 +; AVX2-NEXT: jne .LBB15_35 +; AVX2-NEXT: .LBB15_2: # %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne .LBB15_5 -; AVX2-NEXT: .LBB15_6: # %else4 +; AVX2-NEXT: jne .LBB15_36 +; AVX2-NEXT: .LBB15_3: # %else4 ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: jne .LBB15_7 -; AVX2-NEXT: .LBB15_8: # %else6 +; AVX2-NEXT: jne .LBB15_37 +; AVX2-NEXT: .LBB15_4: # %else6 ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: jne .LBB15_9 -; AVX2-NEXT: .LBB15_10: # %else8 +; AVX2-NEXT: jne .LBB15_38 +; AVX2-NEXT: .LBB15_5: # %else8 ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: jne .LBB15_11 -; AVX2-NEXT: .LBB15_12: # %else10 +; AVX2-NEXT: jne .LBB15_39 +; AVX2-NEXT: .LBB15_6: # %else10 ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: jne .LBB15_13 -; AVX2-NEXT: .LBB15_14: # %else12 +; AVX2-NEXT: jne .LBB15_40 +; AVX2-NEXT: .LBB15_7: # %else12 ; AVX2-NEXT: testb %al, %al -; AVX2-NEXT: js .LBB15_15 -; AVX2-NEXT: .LBB15_16: # %else14 +; AVX2-NEXT: js .LBB15_41 +; AVX2-NEXT: .LBB15_8: # %else14 ; AVX2-NEXT: testl $256, %eax # imm = 0x100 -; AVX2-NEXT: jne .LBB15_17 -; AVX2-NEXT: .LBB15_18: # %else16 +; AVX2-NEXT: jne .LBB15_42 +; AVX2-NEXT: .LBB15_9: # %else16 ; AVX2-NEXT: testl $512, %eax # imm = 0x200 -; AVX2-NEXT: jne .LBB15_19 -; AVX2-NEXT: .LBB15_20: # %else18 +; AVX2-NEXT: jne .LBB15_43 +; AVX2-NEXT: .LBB15_10: # %else18 ; AVX2-NEXT: testl $1024, %eax # imm = 0x400 -; AVX2-NEXT: jne .LBB15_21 -; AVX2-NEXT: .LBB15_22: # %else20 +; AVX2-NEXT: jne .LBB15_44 +; AVX2-NEXT: .LBB15_11: # %else20 ; AVX2-NEXT: testl $2048, %eax # imm = 0x800 -; AVX2-NEXT: jne .LBB15_23 -; AVX2-NEXT: .LBB15_24: # %else22 +; AVX2-NEXT: jne .LBB15_45 +; AVX2-NEXT: .LBB15_12: # %else22 ; AVX2-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX2-NEXT: jne .LBB15_25 -; AVX2-NEXT: .LBB15_26: # %else24 +; AVX2-NEXT: jne .LBB15_46 +; AVX2-NEXT: .LBB15_13: # %else24 ; AVX2-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX2-NEXT: jne .LBB15_27 -; AVX2-NEXT: .LBB15_28: # %else26 +; AVX2-NEXT: jne .LBB15_47 +; AVX2-NEXT: .LBB15_14: # %else26 ; AVX2-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX2-NEXT: jne .LBB15_29 -; AVX2-NEXT: .LBB15_30: # %else28 +; AVX2-NEXT: jne .LBB15_48 +; AVX2-NEXT: .LBB15_15: # %else28 ; AVX2-NEXT: testw %ax, %ax -; AVX2-NEXT: jns .LBB15_32 -; AVX2-NEXT: .LBB15_31: # %cond.store29 +; AVX2-NEXT: jns .LBB15_17 +; AVX2-NEXT: .LBB15_16: # %cond.store29 ; AVX2-NEXT: vpextrb $15, %xmm0, 15(%rdi) -; AVX2-NEXT: .LBB15_32: # %else30 +; AVX2-NEXT: .LBB15_17: # %else30 ; AVX2-NEXT: testl $65536, %eax # imm = 0x10000 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0 -; AVX2-NEXT: jne .LBB15_33 -; AVX2-NEXT: # %bb.34: # %else32 +; AVX2-NEXT: jne .LBB15_49 +; AVX2-NEXT: # %bb.18: # %else32 ; AVX2-NEXT: testl $131072, %eax # imm = 0x20000 -; AVX2-NEXT: jne .LBB15_35 -; AVX2-NEXT: .LBB15_36: # %else34 +; AVX2-NEXT: jne .LBB15_50 +; AVX2-NEXT: .LBB15_19: # %else34 ; AVX2-NEXT: testl $262144, %eax # imm = 0x40000 -; AVX2-NEXT: jne .LBB15_37 -; AVX2-NEXT: .LBB15_38: # %else36 +; AVX2-NEXT: jne .LBB15_51 +; AVX2-NEXT: .LBB15_20: # %else36 ; AVX2-NEXT: testl $524288, %eax # imm = 0x80000 -; AVX2-NEXT: jne .LBB15_39 -; AVX2-NEXT: .LBB15_40: # %else38 +; AVX2-NEXT: jne .LBB15_52 +; AVX2-NEXT: .LBB15_21: # %else38 ; AVX2-NEXT: testl $1048576, %eax # imm = 0x100000 -; AVX2-NEXT: jne .LBB15_41 -; AVX2-NEXT: .LBB15_42: # %else40 +; AVX2-NEXT: jne .LBB15_53 +; AVX2-NEXT: .LBB15_22: # %else40 ; AVX2-NEXT: testl $2097152, %eax # imm = 0x200000 -; AVX2-NEXT: jne .LBB15_43 -; AVX2-NEXT: .LBB15_44: # %else42 +; AVX2-NEXT: jne .LBB15_54 +; AVX2-NEXT: .LBB15_23: # %else42 ; AVX2-NEXT: testl $4194304, %eax # imm = 0x400000 -; AVX2-NEXT: jne .LBB15_45 -; AVX2-NEXT: .LBB15_46: # %else44 +; AVX2-NEXT: jne .LBB15_55 +; AVX2-NEXT: .LBB15_24: # %else44 ; AVX2-NEXT: testl $8388608, %eax # imm = 0x800000 -; AVX2-NEXT: jne .LBB15_47 -; AVX2-NEXT: .LBB15_48: # %else46 +; AVX2-NEXT: jne .LBB15_56 +; AVX2-NEXT: .LBB15_25: # %else46 ; AVX2-NEXT: testl $16777216, %eax # imm = 0x1000000 -; AVX2-NEXT: jne .LBB15_49 -; AVX2-NEXT: .LBB15_50: # %else48 +; AVX2-NEXT: jne .LBB15_57 +; AVX2-NEXT: .LBB15_26: # %else48 ; AVX2-NEXT: testl $33554432, %eax # imm = 0x2000000 -; AVX2-NEXT: jne .LBB15_51 -; AVX2-NEXT: .LBB15_52: # %else50 +; AVX2-NEXT: jne .LBB15_58 +; AVX2-NEXT: .LBB15_27: # %else50 ; AVX2-NEXT: testl $67108864, %eax # imm = 0x4000000 -; AVX2-NEXT: jne .LBB15_53 -; AVX2-NEXT: .LBB15_54: # %else52 +; AVX2-NEXT: jne .LBB15_59 +; AVX2-NEXT: .LBB15_28: # %else52 ; AVX2-NEXT: testl $134217728, %eax # imm = 0x8000000 -; AVX2-NEXT: jne .LBB15_55 -; AVX2-NEXT: .LBB15_56: # %else54 +; AVX2-NEXT: jne .LBB15_60 +; AVX2-NEXT: .LBB15_29: # %else54 ; AVX2-NEXT: testl $268435456, %eax # imm = 0x10000000 -; AVX2-NEXT: jne .LBB15_57 -; AVX2-NEXT: .LBB15_58: # %else56 +; AVX2-NEXT: jne .LBB15_61 +; AVX2-NEXT: .LBB15_30: # %else56 ; AVX2-NEXT: testl $536870912, %eax # imm = 0x20000000 -; AVX2-NEXT: jne .LBB15_59 -; AVX2-NEXT: .LBB15_60: # %else58 +; AVX2-NEXT: jne .LBB15_62 +; AVX2-NEXT: .LBB15_31: # %else58 ; AVX2-NEXT: testl $1073741824, %eax # imm = 0x40000000 -; AVX2-NEXT: jne .LBB15_61 -; AVX2-NEXT: .LBB15_62: # %else60 -; AVX2-NEXT: testl $-2147483648, %eax # imm = 0x80000000 ; AVX2-NEXT: jne .LBB15_63 -; AVX2-NEXT: .LBB15_64: # %else62 +; AVX2-NEXT: .LBB15_32: # %else60 +; AVX2-NEXT: testl $-2147483648, %eax # imm = 0x80000000 +; AVX2-NEXT: jne .LBB15_64 +; AVX2-NEXT: .LBB15_33: # %else62 ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; AVX2-NEXT: .LBB15_1: # %cond.store +; AVX2-NEXT: .LBB15_34: # %cond.store ; AVX2-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je .LBB15_4 -; AVX2-NEXT: .LBB15_3: # %cond.store1 +; AVX2-NEXT: je .LBB15_2 +; AVX2-NEXT: .LBB15_35: # %cond.store1 ; AVX2-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je .LBB15_6 -; AVX2-NEXT: .LBB15_5: # %cond.store3 +; AVX2-NEXT: je .LBB15_3 +; AVX2-NEXT: .LBB15_36: # %cond.store3 ; AVX2-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je .LBB15_8 -; AVX2-NEXT: .LBB15_7: # %cond.store5 +; AVX2-NEXT: je .LBB15_4 +; AVX2-NEXT: .LBB15_37: # %cond.store5 ; AVX2-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: je .LBB15_10 -; AVX2-NEXT: .LBB15_9: # %cond.store7 +; AVX2-NEXT: je .LBB15_5 +; AVX2-NEXT: .LBB15_38: # %cond.store7 ; AVX2-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: je .LBB15_12 -; AVX2-NEXT: .LBB15_11: # %cond.store9 +; AVX2-NEXT: je .LBB15_6 +; AVX2-NEXT: .LBB15_39: # %cond.store9 ; AVX2-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: je .LBB15_14 -; AVX2-NEXT: .LBB15_13: # %cond.store11 +; AVX2-NEXT: je .LBB15_7 +; AVX2-NEXT: .LBB15_40: # %cond.store11 ; AVX2-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX2-NEXT: testb %al, %al -; AVX2-NEXT: jns .LBB15_16 -; AVX2-NEXT: .LBB15_15: # %cond.store13 +; AVX2-NEXT: jns .LBB15_8 +; AVX2-NEXT: .LBB15_41: # %cond.store13 ; AVX2-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX2-NEXT: testl $256, %eax # imm = 0x100 -; AVX2-NEXT: je .LBB15_18 -; AVX2-NEXT: .LBB15_17: # %cond.store15 +; AVX2-NEXT: je .LBB15_9 +; AVX2-NEXT: .LBB15_42: # %cond.store15 ; AVX2-NEXT: vpextrb $8, %xmm0, 8(%rdi) ; AVX2-NEXT: testl $512, %eax # imm = 0x200 -; AVX2-NEXT: je .LBB15_20 -; AVX2-NEXT: .LBB15_19: # %cond.store17 +; AVX2-NEXT: je .LBB15_10 +; AVX2-NEXT: .LBB15_43: # %cond.store17 ; AVX2-NEXT: vpextrb $9, %xmm0, 9(%rdi) ; AVX2-NEXT: testl $1024, %eax # imm = 0x400 -; AVX2-NEXT: je .LBB15_22 -; AVX2-NEXT: .LBB15_21: # %cond.store19 +; AVX2-NEXT: je .LBB15_11 +; AVX2-NEXT: .LBB15_44: # %cond.store19 ; AVX2-NEXT: vpextrb $10, %xmm0, 10(%rdi) ; AVX2-NEXT: testl $2048, %eax # imm = 0x800 -; AVX2-NEXT: je .LBB15_24 -; AVX2-NEXT: .LBB15_23: # %cond.store21 +; AVX2-NEXT: je .LBB15_12 +; AVX2-NEXT: .LBB15_45: # %cond.store21 ; AVX2-NEXT: vpextrb $11, %xmm0, 11(%rdi) ; AVX2-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX2-NEXT: je .LBB15_26 -; AVX2-NEXT: .LBB15_25: # %cond.store23 +; AVX2-NEXT: je .LBB15_13 +; AVX2-NEXT: .LBB15_46: # %cond.store23 ; AVX2-NEXT: vpextrb $12, %xmm0, 12(%rdi) ; AVX2-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX2-NEXT: je .LBB15_28 -; AVX2-NEXT: .LBB15_27: # %cond.store25 +; AVX2-NEXT: je .LBB15_14 +; AVX2-NEXT: .LBB15_47: # %cond.store25 ; AVX2-NEXT: vpextrb $13, %xmm0, 13(%rdi) ; AVX2-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX2-NEXT: je .LBB15_30 -; AVX2-NEXT: .LBB15_29: # %cond.store27 +; AVX2-NEXT: je .LBB15_15 +; AVX2-NEXT: .LBB15_48: # %cond.store27 ; AVX2-NEXT: vpextrb $14, %xmm0, 14(%rdi) ; AVX2-NEXT: testw %ax, %ax -; AVX2-NEXT: js .LBB15_31 -; AVX2-NEXT: jmp .LBB15_32 -; AVX2-NEXT: .LBB15_33: # %cond.store31 +; AVX2-NEXT: js .LBB15_16 +; AVX2-NEXT: jmp .LBB15_17 +; AVX2-NEXT: .LBB15_49: # %cond.store31 ; AVX2-NEXT: vpextrb $0, %xmm0, 16(%rdi) ; AVX2-NEXT: testl $131072, %eax # imm = 0x20000 -; AVX2-NEXT: je .LBB15_36 -; AVX2-NEXT: .LBB15_35: # %cond.store33 +; AVX2-NEXT: je .LBB15_19 +; AVX2-NEXT: .LBB15_50: # %cond.store33 ; AVX2-NEXT: vpextrb $1, %xmm0, 17(%rdi) ; AVX2-NEXT: testl $262144, %eax # imm = 0x40000 -; AVX2-NEXT: je .LBB15_38 -; AVX2-NEXT: .LBB15_37: # %cond.store35 +; AVX2-NEXT: je .LBB15_20 +; AVX2-NEXT: .LBB15_51: # %cond.store35 ; AVX2-NEXT: vpextrb $2, %xmm0, 18(%rdi) ; AVX2-NEXT: testl $524288, %eax # imm = 0x80000 -; AVX2-NEXT: je .LBB15_40 -; AVX2-NEXT: .LBB15_39: # %cond.store37 +; AVX2-NEXT: je .LBB15_21 +; AVX2-NEXT: .LBB15_52: # %cond.store37 ; AVX2-NEXT: vpextrb $3, %xmm0, 19(%rdi) ; AVX2-NEXT: testl $1048576, %eax # imm = 0x100000 -; AVX2-NEXT: je .LBB15_42 -; AVX2-NEXT: .LBB15_41: # %cond.store39 +; AVX2-NEXT: je .LBB15_22 +; AVX2-NEXT: .LBB15_53: # %cond.store39 ; AVX2-NEXT: vpextrb $4, %xmm0, 20(%rdi) ; AVX2-NEXT: testl $2097152, %eax # imm = 0x200000 -; AVX2-NEXT: je .LBB15_44 -; AVX2-NEXT: .LBB15_43: # %cond.store41 +; AVX2-NEXT: je .LBB15_23 +; AVX2-NEXT: .LBB15_54: # %cond.store41 ; AVX2-NEXT: vpextrb $5, %xmm0, 21(%rdi) ; AVX2-NEXT: testl $4194304, %eax # imm = 0x400000 -; AVX2-NEXT: je .LBB15_46 -; AVX2-NEXT: .LBB15_45: # %cond.store43 +; AVX2-NEXT: je .LBB15_24 +; AVX2-NEXT: .LBB15_55: # %cond.store43 ; AVX2-NEXT: vpextrb $6, %xmm0, 22(%rdi) ; AVX2-NEXT: testl $8388608, %eax # imm = 0x800000 -; AVX2-NEXT: je .LBB15_48 -; AVX2-NEXT: .LBB15_47: # %cond.store45 +; AVX2-NEXT: je .LBB15_25 +; AVX2-NEXT: .LBB15_56: # %cond.store45 ; AVX2-NEXT: vpextrb $7, %xmm0, 23(%rdi) ; AVX2-NEXT: testl $16777216, %eax # imm = 0x1000000 -; AVX2-NEXT: je .LBB15_50 -; AVX2-NEXT: .LBB15_49: # %cond.store47 +; AVX2-NEXT: je .LBB15_26 +; AVX2-NEXT: .LBB15_57: # %cond.store47 ; AVX2-NEXT: vpextrb $8, %xmm0, 24(%rdi) ; AVX2-NEXT: testl $33554432, %eax # imm = 0x2000000 -; AVX2-NEXT: je .LBB15_52 -; AVX2-NEXT: .LBB15_51: # %cond.store49 +; AVX2-NEXT: je .LBB15_27 +; AVX2-NEXT: .LBB15_58: # %cond.store49 ; AVX2-NEXT: vpextrb $9, %xmm0, 25(%rdi) ; AVX2-NEXT: testl $67108864, %eax # imm = 0x4000000 -; AVX2-NEXT: je .LBB15_54 -; AVX2-NEXT: .LBB15_53: # %cond.store51 +; AVX2-NEXT: je .LBB15_28 +; AVX2-NEXT: .LBB15_59: # %cond.store51 ; AVX2-NEXT: vpextrb $10, %xmm0, 26(%rdi) ; AVX2-NEXT: testl $134217728, %eax # imm = 0x8000000 -; AVX2-NEXT: je .LBB15_56 -; AVX2-NEXT: .LBB15_55: # %cond.store53 +; AVX2-NEXT: je .LBB15_29 +; AVX2-NEXT: .LBB15_60: # %cond.store53 ; AVX2-NEXT: vpextrb $11, %xmm0, 27(%rdi) ; AVX2-NEXT: testl $268435456, %eax # imm = 0x10000000 -; AVX2-NEXT: je .LBB15_58 -; AVX2-NEXT: .LBB15_57: # %cond.store55 +; AVX2-NEXT: je .LBB15_30 +; AVX2-NEXT: .LBB15_61: # %cond.store55 ; AVX2-NEXT: vpextrb $12, %xmm0, 28(%rdi) ; AVX2-NEXT: testl $536870912, %eax # imm = 0x20000000 -; AVX2-NEXT: je .LBB15_60 -; AVX2-NEXT: .LBB15_59: # %cond.store57 +; AVX2-NEXT: je .LBB15_31 +; AVX2-NEXT: .LBB15_62: # %cond.store57 ; AVX2-NEXT: vpextrb $13, %xmm0, 29(%rdi) ; AVX2-NEXT: testl $1073741824, %eax # imm = 0x40000000 -; AVX2-NEXT: je .LBB15_62 -; AVX2-NEXT: .LBB15_61: # %cond.store59 +; AVX2-NEXT: je .LBB15_32 +; AVX2-NEXT: .LBB15_63: # %cond.store59 ; AVX2-NEXT: vpextrb $14, %xmm0, 30(%rdi) ; AVX2-NEXT: testl $-2147483648, %eax # imm = 0x80000000 -; AVX2-NEXT: je .LBB15_64 -; AVX2-NEXT: .LBB15_63: # %cond.store61 +; AVX2-NEXT: je .LBB15_33 +; AVX2-NEXT: .LBB15_64: # %cond.store61 ; AVX2-NEXT: vpextrb $15, %xmm0, 31(%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq @@ -6853,228 +6853,228 @@ define void @truncstore_v32i16_v32i8(<32 x i16> %x, ptr %p, <32 x i8> %mask) { ; AVX512F-NEXT: vpmovmskb %ymm1, %eax ; AVX512F-NEXT: notl %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB15_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB15_34 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB15_3 -; AVX512F-NEXT: .LBB15_4: # %else2 +; AVX512F-NEXT: jne .LBB15_35 +; AVX512F-NEXT: .LBB15_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB15_5 -; AVX512F-NEXT: .LBB15_6: # %else4 +; AVX512F-NEXT: jne .LBB15_36 +; AVX512F-NEXT: .LBB15_3: # %else4 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne .LBB15_7 -; AVX512F-NEXT: .LBB15_8: # %else6 +; AVX512F-NEXT: jne .LBB15_37 +; AVX512F-NEXT: .LBB15_4: # %else6 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne .LBB15_9 -; AVX512F-NEXT: .LBB15_10: # %else8 +; AVX512F-NEXT: jne .LBB15_38 +; AVX512F-NEXT: .LBB15_5: # %else8 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne .LBB15_11 -; AVX512F-NEXT: .LBB15_12: # %else10 +; AVX512F-NEXT: jne .LBB15_39 +; AVX512F-NEXT: .LBB15_6: # %else10 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne .LBB15_13 -; AVX512F-NEXT: .LBB15_14: # %else12 +; AVX512F-NEXT: jne .LBB15_40 +; AVX512F-NEXT: .LBB15_7: # %else12 ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: js .LBB15_15 -; AVX512F-NEXT: .LBB15_16: # %else14 +; AVX512F-NEXT: js .LBB15_41 +; AVX512F-NEXT: .LBB15_8: # %else14 ; AVX512F-NEXT: testl $256, %eax # imm = 0x100 -; AVX512F-NEXT: jne .LBB15_17 -; AVX512F-NEXT: .LBB15_18: # %else16 +; AVX512F-NEXT: jne .LBB15_42 +; AVX512F-NEXT: .LBB15_9: # %else16 ; AVX512F-NEXT: testl $512, %eax # imm = 0x200 -; AVX512F-NEXT: jne .LBB15_19 -; AVX512F-NEXT: .LBB15_20: # %else18 +; AVX512F-NEXT: jne .LBB15_43 +; AVX512F-NEXT: .LBB15_10: # %else18 ; AVX512F-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512F-NEXT: jne .LBB15_21 -; AVX512F-NEXT: .LBB15_22: # %else20 +; AVX512F-NEXT: jne .LBB15_44 +; AVX512F-NEXT: .LBB15_11: # %else20 ; AVX512F-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512F-NEXT: jne .LBB15_23 -; AVX512F-NEXT: .LBB15_24: # %else22 +; AVX512F-NEXT: jne .LBB15_45 +; AVX512F-NEXT: .LBB15_12: # %else22 ; AVX512F-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512F-NEXT: jne .LBB15_25 -; AVX512F-NEXT: .LBB15_26: # %else24 +; AVX512F-NEXT: jne .LBB15_46 +; AVX512F-NEXT: .LBB15_13: # %else24 ; AVX512F-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512F-NEXT: jne .LBB15_27 -; AVX512F-NEXT: .LBB15_28: # %else26 +; AVX512F-NEXT: jne .LBB15_47 +; AVX512F-NEXT: .LBB15_14: # %else26 ; AVX512F-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512F-NEXT: jne .LBB15_29 -; AVX512F-NEXT: .LBB15_30: # %else28 +; AVX512F-NEXT: jne .LBB15_48 +; AVX512F-NEXT: .LBB15_15: # %else28 ; AVX512F-NEXT: testw %ax, %ax -; AVX512F-NEXT: jns .LBB15_32 -; AVX512F-NEXT: .LBB15_31: # %cond.store29 +; AVX512F-NEXT: jns .LBB15_17 +; AVX512F-NEXT: .LBB15_16: # %cond.store29 ; AVX512F-NEXT: vpextrb $15, %xmm0, 15(%rdi) -; AVX512F-NEXT: .LBB15_32: # %else30 +; AVX512F-NEXT: .LBB15_17: # %else30 ; AVX512F-NEXT: testl $65536, %eax # imm = 0x10000 ; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm0 -; AVX512F-NEXT: jne .LBB15_33 -; AVX512F-NEXT: # %bb.34: # %else32 +; AVX512F-NEXT: jne .LBB15_49 +; AVX512F-NEXT: # %bb.18: # %else32 ; AVX512F-NEXT: testl $131072, %eax # imm = 0x20000 -; AVX512F-NEXT: jne .LBB15_35 -; AVX512F-NEXT: .LBB15_36: # %else34 +; AVX512F-NEXT: jne .LBB15_50 +; AVX512F-NEXT: .LBB15_19: # %else34 ; AVX512F-NEXT: testl $262144, %eax # imm = 0x40000 -; AVX512F-NEXT: jne .LBB15_37 -; AVX512F-NEXT: .LBB15_38: # %else36 +; AVX512F-NEXT: jne .LBB15_51 +; AVX512F-NEXT: .LBB15_20: # %else36 ; AVX512F-NEXT: testl $524288, %eax # imm = 0x80000 -; AVX512F-NEXT: jne .LBB15_39 -; AVX512F-NEXT: .LBB15_40: # %else38 +; AVX512F-NEXT: jne .LBB15_52 +; AVX512F-NEXT: .LBB15_21: # %else38 ; AVX512F-NEXT: testl $1048576, %eax # imm = 0x100000 -; AVX512F-NEXT: jne .LBB15_41 -; AVX512F-NEXT: .LBB15_42: # %else40 +; AVX512F-NEXT: jne .LBB15_53 +; AVX512F-NEXT: .LBB15_22: # %else40 ; AVX512F-NEXT: testl $2097152, %eax # imm = 0x200000 -; AVX512F-NEXT: jne .LBB15_43 -; AVX512F-NEXT: .LBB15_44: # %else42 +; AVX512F-NEXT: jne .LBB15_54 +; AVX512F-NEXT: .LBB15_23: # %else42 ; AVX512F-NEXT: testl $4194304, %eax # imm = 0x400000 -; AVX512F-NEXT: jne .LBB15_45 -; AVX512F-NEXT: .LBB15_46: # %else44 +; AVX512F-NEXT: jne .LBB15_55 +; AVX512F-NEXT: .LBB15_24: # %else44 ; AVX512F-NEXT: testl $8388608, %eax # imm = 0x800000 -; AVX512F-NEXT: jne .LBB15_47 -; AVX512F-NEXT: .LBB15_48: # %else46 +; AVX512F-NEXT: jne .LBB15_56 +; AVX512F-NEXT: .LBB15_25: # %else46 ; AVX512F-NEXT: testl $16777216, %eax # imm = 0x1000000 -; AVX512F-NEXT: jne .LBB15_49 -; AVX512F-NEXT: .LBB15_50: # %else48 +; AVX512F-NEXT: jne .LBB15_57 +; AVX512F-NEXT: .LBB15_26: # %else48 ; AVX512F-NEXT: testl $33554432, %eax # imm = 0x2000000 -; AVX512F-NEXT: jne .LBB15_51 -; AVX512F-NEXT: .LBB15_52: # %else50 +; AVX512F-NEXT: jne .LBB15_58 +; AVX512F-NEXT: .LBB15_27: # %else50 ; AVX512F-NEXT: testl $67108864, %eax # imm = 0x4000000 -; AVX512F-NEXT: jne .LBB15_53 -; AVX512F-NEXT: .LBB15_54: # %else52 +; AVX512F-NEXT: jne .LBB15_59 +; AVX512F-NEXT: .LBB15_28: # %else52 ; AVX512F-NEXT: testl $134217728, %eax # imm = 0x8000000 -; AVX512F-NEXT: jne .LBB15_55 -; AVX512F-NEXT: .LBB15_56: # %else54 +; AVX512F-NEXT: jne .LBB15_60 +; AVX512F-NEXT: .LBB15_29: # %else54 ; AVX512F-NEXT: testl $268435456, %eax # imm = 0x10000000 -; AVX512F-NEXT: jne .LBB15_57 -; AVX512F-NEXT: .LBB15_58: # %else56 +; AVX512F-NEXT: jne .LBB15_61 +; AVX512F-NEXT: .LBB15_30: # %else56 ; AVX512F-NEXT: testl $536870912, %eax # imm = 0x20000000 -; AVX512F-NEXT: jne .LBB15_59 -; AVX512F-NEXT: .LBB15_60: # %else58 +; AVX512F-NEXT: jne .LBB15_62 +; AVX512F-NEXT: .LBB15_31: # %else58 ; AVX512F-NEXT: testl $1073741824, %eax # imm = 0x40000000 -; AVX512F-NEXT: jne .LBB15_61 -; AVX512F-NEXT: .LBB15_62: # %else60 -; AVX512F-NEXT: testl $-2147483648, %eax # imm = 0x80000000 ; AVX512F-NEXT: jne .LBB15_63 -; AVX512F-NEXT: .LBB15_64: # %else62 +; AVX512F-NEXT: .LBB15_32: # %else60 +; AVX512F-NEXT: testl $-2147483648, %eax # imm = 0x80000000 +; AVX512F-NEXT: jne .LBB15_64 +; AVX512F-NEXT: .LBB15_33: # %else62 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB15_1: # %cond.store +; AVX512F-NEXT: .LBB15_34: # %cond.store ; AVX512F-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB15_4 -; AVX512F-NEXT: .LBB15_3: # %cond.store1 +; AVX512F-NEXT: je .LBB15_2 +; AVX512F-NEXT: .LBB15_35: # %cond.store1 ; AVX512F-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB15_6 -; AVX512F-NEXT: .LBB15_5: # %cond.store3 +; AVX512F-NEXT: je .LBB15_3 +; AVX512F-NEXT: .LBB15_36: # %cond.store3 ; AVX512F-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB15_8 -; AVX512F-NEXT: .LBB15_7: # %cond.store5 +; AVX512F-NEXT: je .LBB15_4 +; AVX512F-NEXT: .LBB15_37: # %cond.store5 ; AVX512F-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je .LBB15_10 -; AVX512F-NEXT: .LBB15_9: # %cond.store7 +; AVX512F-NEXT: je .LBB15_5 +; AVX512F-NEXT: .LBB15_38: # %cond.store7 ; AVX512F-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je .LBB15_12 -; AVX512F-NEXT: .LBB15_11: # %cond.store9 +; AVX512F-NEXT: je .LBB15_6 +; AVX512F-NEXT: .LBB15_39: # %cond.store9 ; AVX512F-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je .LBB15_14 -; AVX512F-NEXT: .LBB15_13: # %cond.store11 +; AVX512F-NEXT: je .LBB15_7 +; AVX512F-NEXT: .LBB15_40: # %cond.store11 ; AVX512F-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: jns .LBB15_16 -; AVX512F-NEXT: .LBB15_15: # %cond.store13 +; AVX512F-NEXT: jns .LBB15_8 +; AVX512F-NEXT: .LBB15_41: # %cond.store13 ; AVX512F-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX512F-NEXT: testl $256, %eax # imm = 0x100 -; AVX512F-NEXT: je .LBB15_18 -; AVX512F-NEXT: .LBB15_17: # %cond.store15 +; AVX512F-NEXT: je .LBB15_9 +; AVX512F-NEXT: .LBB15_42: # %cond.store15 ; AVX512F-NEXT: vpextrb $8, %xmm0, 8(%rdi) ; AVX512F-NEXT: testl $512, %eax # imm = 0x200 -; AVX512F-NEXT: je .LBB15_20 -; AVX512F-NEXT: .LBB15_19: # %cond.store17 +; AVX512F-NEXT: je .LBB15_10 +; AVX512F-NEXT: .LBB15_43: # %cond.store17 ; AVX512F-NEXT: vpextrb $9, %xmm0, 9(%rdi) ; AVX512F-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512F-NEXT: je .LBB15_22 -; AVX512F-NEXT: .LBB15_21: # %cond.store19 +; AVX512F-NEXT: je .LBB15_11 +; AVX512F-NEXT: .LBB15_44: # %cond.store19 ; AVX512F-NEXT: vpextrb $10, %xmm0, 10(%rdi) ; AVX512F-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512F-NEXT: je .LBB15_24 -; AVX512F-NEXT: .LBB15_23: # %cond.store21 +; AVX512F-NEXT: je .LBB15_12 +; AVX512F-NEXT: .LBB15_45: # %cond.store21 ; AVX512F-NEXT: vpextrb $11, %xmm0, 11(%rdi) ; AVX512F-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512F-NEXT: je .LBB15_26 -; AVX512F-NEXT: .LBB15_25: # %cond.store23 +; AVX512F-NEXT: je .LBB15_13 +; AVX512F-NEXT: .LBB15_46: # %cond.store23 ; AVX512F-NEXT: vpextrb $12, %xmm0, 12(%rdi) ; AVX512F-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512F-NEXT: je .LBB15_28 -; AVX512F-NEXT: .LBB15_27: # %cond.store25 +; AVX512F-NEXT: je .LBB15_14 +; AVX512F-NEXT: .LBB15_47: # %cond.store25 ; AVX512F-NEXT: vpextrb $13, %xmm0, 13(%rdi) ; AVX512F-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512F-NEXT: je .LBB15_30 -; AVX512F-NEXT: .LBB15_29: # %cond.store27 +; AVX512F-NEXT: je .LBB15_15 +; AVX512F-NEXT: .LBB15_48: # %cond.store27 ; AVX512F-NEXT: vpextrb $14, %xmm0, 14(%rdi) ; AVX512F-NEXT: testw %ax, %ax -; AVX512F-NEXT: js .LBB15_31 -; AVX512F-NEXT: jmp .LBB15_32 -; AVX512F-NEXT: .LBB15_33: # %cond.store31 +; AVX512F-NEXT: js .LBB15_16 +; AVX512F-NEXT: jmp .LBB15_17 +; AVX512F-NEXT: .LBB15_49: # %cond.store31 ; AVX512F-NEXT: vpextrb $0, %xmm0, 16(%rdi) ; AVX512F-NEXT: testl $131072, %eax # imm = 0x20000 -; AVX512F-NEXT: je .LBB15_36 -; AVX512F-NEXT: .LBB15_35: # %cond.store33 +; AVX512F-NEXT: je .LBB15_19 +; AVX512F-NEXT: .LBB15_50: # %cond.store33 ; AVX512F-NEXT: vpextrb $1, %xmm0, 17(%rdi) ; AVX512F-NEXT: testl $262144, %eax # imm = 0x40000 -; AVX512F-NEXT: je .LBB15_38 -; AVX512F-NEXT: .LBB15_37: # %cond.store35 +; AVX512F-NEXT: je .LBB15_20 +; AVX512F-NEXT: .LBB15_51: # %cond.store35 ; AVX512F-NEXT: vpextrb $2, %xmm0, 18(%rdi) ; AVX512F-NEXT: testl $524288, %eax # imm = 0x80000 -; AVX512F-NEXT: je .LBB15_40 -; AVX512F-NEXT: .LBB15_39: # %cond.store37 +; AVX512F-NEXT: je .LBB15_21 +; AVX512F-NEXT: .LBB15_52: # %cond.store37 ; AVX512F-NEXT: vpextrb $3, %xmm0, 19(%rdi) ; AVX512F-NEXT: testl $1048576, %eax # imm = 0x100000 -; AVX512F-NEXT: je .LBB15_42 -; AVX512F-NEXT: .LBB15_41: # %cond.store39 +; AVX512F-NEXT: je .LBB15_22 +; AVX512F-NEXT: .LBB15_53: # %cond.store39 ; AVX512F-NEXT: vpextrb $4, %xmm0, 20(%rdi) ; AVX512F-NEXT: testl $2097152, %eax # imm = 0x200000 -; AVX512F-NEXT: je .LBB15_44 -; AVX512F-NEXT: .LBB15_43: # %cond.store41 +; AVX512F-NEXT: je .LBB15_23 +; AVX512F-NEXT: .LBB15_54: # %cond.store41 ; AVX512F-NEXT: vpextrb $5, %xmm0, 21(%rdi) ; AVX512F-NEXT: testl $4194304, %eax # imm = 0x400000 -; AVX512F-NEXT: je .LBB15_46 -; AVX512F-NEXT: .LBB15_45: # %cond.store43 +; AVX512F-NEXT: je .LBB15_24 +; AVX512F-NEXT: .LBB15_55: # %cond.store43 ; AVX512F-NEXT: vpextrb $6, %xmm0, 22(%rdi) ; AVX512F-NEXT: testl $8388608, %eax # imm = 0x800000 -; AVX512F-NEXT: je .LBB15_48 -; AVX512F-NEXT: .LBB15_47: # %cond.store45 +; AVX512F-NEXT: je .LBB15_25 +; AVX512F-NEXT: .LBB15_56: # %cond.store45 ; AVX512F-NEXT: vpextrb $7, %xmm0, 23(%rdi) ; AVX512F-NEXT: testl $16777216, %eax # imm = 0x1000000 -; AVX512F-NEXT: je .LBB15_50 -; AVX512F-NEXT: .LBB15_49: # %cond.store47 +; AVX512F-NEXT: je .LBB15_26 +; AVX512F-NEXT: .LBB15_57: # %cond.store47 ; AVX512F-NEXT: vpextrb $8, %xmm0, 24(%rdi) ; AVX512F-NEXT: testl $33554432, %eax # imm = 0x2000000 -; AVX512F-NEXT: je .LBB15_52 -; AVX512F-NEXT: .LBB15_51: # %cond.store49 +; AVX512F-NEXT: je .LBB15_27 +; AVX512F-NEXT: .LBB15_58: # %cond.store49 ; AVX512F-NEXT: vpextrb $9, %xmm0, 25(%rdi) ; AVX512F-NEXT: testl $67108864, %eax # imm = 0x4000000 -; AVX512F-NEXT: je .LBB15_54 -; AVX512F-NEXT: .LBB15_53: # %cond.store51 +; AVX512F-NEXT: je .LBB15_28 +; AVX512F-NEXT: .LBB15_59: # %cond.store51 ; AVX512F-NEXT: vpextrb $10, %xmm0, 26(%rdi) ; AVX512F-NEXT: testl $134217728, %eax # imm = 0x8000000 -; AVX512F-NEXT: je .LBB15_56 -; AVX512F-NEXT: .LBB15_55: # %cond.store53 +; AVX512F-NEXT: je .LBB15_29 +; AVX512F-NEXT: .LBB15_60: # %cond.store53 ; AVX512F-NEXT: vpextrb $11, %xmm0, 27(%rdi) ; AVX512F-NEXT: testl $268435456, %eax # imm = 0x10000000 -; AVX512F-NEXT: je .LBB15_58 -; AVX512F-NEXT: .LBB15_57: # %cond.store55 +; AVX512F-NEXT: je .LBB15_30 +; AVX512F-NEXT: .LBB15_61: # %cond.store55 ; AVX512F-NEXT: vpextrb $12, %xmm0, 28(%rdi) ; AVX512F-NEXT: testl $536870912, %eax # imm = 0x20000000 -; AVX512F-NEXT: je .LBB15_60 -; AVX512F-NEXT: .LBB15_59: # %cond.store57 +; AVX512F-NEXT: je .LBB15_31 +; AVX512F-NEXT: .LBB15_62: # %cond.store57 ; AVX512F-NEXT: vpextrb $13, %xmm0, 29(%rdi) ; AVX512F-NEXT: testl $1073741824, %eax # imm = 0x40000000 -; AVX512F-NEXT: je .LBB15_62 -; AVX512F-NEXT: .LBB15_61: # %cond.store59 +; AVX512F-NEXT: je .LBB15_32 +; AVX512F-NEXT: .LBB15_63: # %cond.store59 ; AVX512F-NEXT: vpextrb $14, %xmm0, 30(%rdi) ; AVX512F-NEXT: testl $-2147483648, %eax # imm = 0x80000000 -; AVX512F-NEXT: je .LBB15_64 -; AVX512F-NEXT: .LBB15_63: # %cond.store61 +; AVX512F-NEXT: je .LBB15_33 +; AVX512F-NEXT: .LBB15_64: # %cond.store61 ; AVX512F-NEXT: vpextrb $15, %xmm0, 31(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -7089,228 +7089,228 @@ define void @truncstore_v32i16_v32i8(<32 x i16> %x, ptr %p, <32 x i8> %mask) { ; AVX512FVL-NEXT: vpmovmskb %ymm1, %eax ; AVX512FVL-NEXT: notl %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB15_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB15_34 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB15_3 -; AVX512FVL-NEXT: .LBB15_4: # %else2 +; AVX512FVL-NEXT: jne .LBB15_35 +; AVX512FVL-NEXT: .LBB15_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB15_5 -; AVX512FVL-NEXT: .LBB15_6: # %else4 +; AVX512FVL-NEXT: jne .LBB15_36 +; AVX512FVL-NEXT: .LBB15_3: # %else4 ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: jne .LBB15_7 -; AVX512FVL-NEXT: .LBB15_8: # %else6 +; AVX512FVL-NEXT: jne .LBB15_37 +; AVX512FVL-NEXT: .LBB15_4: # %else6 ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: jne .LBB15_9 -; AVX512FVL-NEXT: .LBB15_10: # %else8 +; AVX512FVL-NEXT: jne .LBB15_38 +; AVX512FVL-NEXT: .LBB15_5: # %else8 ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: jne .LBB15_11 -; AVX512FVL-NEXT: .LBB15_12: # %else10 +; AVX512FVL-NEXT: jne .LBB15_39 +; AVX512FVL-NEXT: .LBB15_6: # %else10 ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: jne .LBB15_13 -; AVX512FVL-NEXT: .LBB15_14: # %else12 +; AVX512FVL-NEXT: jne .LBB15_40 +; AVX512FVL-NEXT: .LBB15_7: # %else12 ; AVX512FVL-NEXT: testb %al, %al -; AVX512FVL-NEXT: js .LBB15_15 -; AVX512FVL-NEXT: .LBB15_16: # %else14 +; AVX512FVL-NEXT: js .LBB15_41 +; AVX512FVL-NEXT: .LBB15_8: # %else14 ; AVX512FVL-NEXT: testl $256, %eax # imm = 0x100 -; AVX512FVL-NEXT: jne .LBB15_17 -; AVX512FVL-NEXT: .LBB15_18: # %else16 +; AVX512FVL-NEXT: jne .LBB15_42 +; AVX512FVL-NEXT: .LBB15_9: # %else16 ; AVX512FVL-NEXT: testl $512, %eax # imm = 0x200 -; AVX512FVL-NEXT: jne .LBB15_19 -; AVX512FVL-NEXT: .LBB15_20: # %else18 +; AVX512FVL-NEXT: jne .LBB15_43 +; AVX512FVL-NEXT: .LBB15_10: # %else18 ; AVX512FVL-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512FVL-NEXT: jne .LBB15_21 -; AVX512FVL-NEXT: .LBB15_22: # %else20 +; AVX512FVL-NEXT: jne .LBB15_44 +; AVX512FVL-NEXT: .LBB15_11: # %else20 ; AVX512FVL-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512FVL-NEXT: jne .LBB15_23 -; AVX512FVL-NEXT: .LBB15_24: # %else22 +; AVX512FVL-NEXT: jne .LBB15_45 +; AVX512FVL-NEXT: .LBB15_12: # %else22 ; AVX512FVL-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512FVL-NEXT: jne .LBB15_25 -; AVX512FVL-NEXT: .LBB15_26: # %else24 +; AVX512FVL-NEXT: jne .LBB15_46 +; AVX512FVL-NEXT: .LBB15_13: # %else24 ; AVX512FVL-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512FVL-NEXT: jne .LBB15_27 -; AVX512FVL-NEXT: .LBB15_28: # %else26 +; AVX512FVL-NEXT: jne .LBB15_47 +; AVX512FVL-NEXT: .LBB15_14: # %else26 ; AVX512FVL-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512FVL-NEXT: jne .LBB15_29 -; AVX512FVL-NEXT: .LBB15_30: # %else28 +; AVX512FVL-NEXT: jne .LBB15_48 +; AVX512FVL-NEXT: .LBB15_15: # %else28 ; AVX512FVL-NEXT: testw %ax, %ax -; AVX512FVL-NEXT: jns .LBB15_32 -; AVX512FVL-NEXT: .LBB15_31: # %cond.store29 +; AVX512FVL-NEXT: jns .LBB15_17 +; AVX512FVL-NEXT: .LBB15_16: # %cond.store29 ; AVX512FVL-NEXT: vpextrb $15, %xmm0, 15(%rdi) -; AVX512FVL-NEXT: .LBB15_32: # %else30 +; AVX512FVL-NEXT: .LBB15_17: # %else30 ; AVX512FVL-NEXT: testl $65536, %eax # imm = 0x10000 ; AVX512FVL-NEXT: vextracti128 $1, %ymm0, %xmm0 -; AVX512FVL-NEXT: jne .LBB15_33 -; AVX512FVL-NEXT: # %bb.34: # %else32 +; AVX512FVL-NEXT: jne .LBB15_49 +; AVX512FVL-NEXT: # %bb.18: # %else32 ; AVX512FVL-NEXT: testl $131072, %eax # imm = 0x20000 -; AVX512FVL-NEXT: jne .LBB15_35 -; AVX512FVL-NEXT: .LBB15_36: # %else34 +; AVX512FVL-NEXT: jne .LBB15_50 +; AVX512FVL-NEXT: .LBB15_19: # %else34 ; AVX512FVL-NEXT: testl $262144, %eax # imm = 0x40000 -; AVX512FVL-NEXT: jne .LBB15_37 -; AVX512FVL-NEXT: .LBB15_38: # %else36 +; AVX512FVL-NEXT: jne .LBB15_51 +; AVX512FVL-NEXT: .LBB15_20: # %else36 ; AVX512FVL-NEXT: testl $524288, %eax # imm = 0x80000 -; AVX512FVL-NEXT: jne .LBB15_39 -; AVX512FVL-NEXT: .LBB15_40: # %else38 +; AVX512FVL-NEXT: jne .LBB15_52 +; AVX512FVL-NEXT: .LBB15_21: # %else38 ; AVX512FVL-NEXT: testl $1048576, %eax # imm = 0x100000 -; AVX512FVL-NEXT: jne .LBB15_41 -; AVX512FVL-NEXT: .LBB15_42: # %else40 +; AVX512FVL-NEXT: jne .LBB15_53 +; AVX512FVL-NEXT: .LBB15_22: # %else40 ; AVX512FVL-NEXT: testl $2097152, %eax # imm = 0x200000 -; AVX512FVL-NEXT: jne .LBB15_43 -; AVX512FVL-NEXT: .LBB15_44: # %else42 +; AVX512FVL-NEXT: jne .LBB15_54 +; AVX512FVL-NEXT: .LBB15_23: # %else42 ; AVX512FVL-NEXT: testl $4194304, %eax # imm = 0x400000 -; AVX512FVL-NEXT: jne .LBB15_45 -; AVX512FVL-NEXT: .LBB15_46: # %else44 +; AVX512FVL-NEXT: jne .LBB15_55 +; AVX512FVL-NEXT: .LBB15_24: # %else44 ; AVX512FVL-NEXT: testl $8388608, %eax # imm = 0x800000 -; AVX512FVL-NEXT: jne .LBB15_47 -; AVX512FVL-NEXT: .LBB15_48: # %else46 +; AVX512FVL-NEXT: jne .LBB15_56 +; AVX512FVL-NEXT: .LBB15_25: # %else46 ; AVX512FVL-NEXT: testl $16777216, %eax # imm = 0x1000000 -; AVX512FVL-NEXT: jne .LBB15_49 -; AVX512FVL-NEXT: .LBB15_50: # %else48 +; AVX512FVL-NEXT: jne .LBB15_57 +; AVX512FVL-NEXT: .LBB15_26: # %else48 ; AVX512FVL-NEXT: testl $33554432, %eax # imm = 0x2000000 -; AVX512FVL-NEXT: jne .LBB15_51 -; AVX512FVL-NEXT: .LBB15_52: # %else50 +; AVX512FVL-NEXT: jne .LBB15_58 +; AVX512FVL-NEXT: .LBB15_27: # %else50 ; AVX512FVL-NEXT: testl $67108864, %eax # imm = 0x4000000 -; AVX512FVL-NEXT: jne .LBB15_53 -; AVX512FVL-NEXT: .LBB15_54: # %else52 +; AVX512FVL-NEXT: jne .LBB15_59 +; AVX512FVL-NEXT: .LBB15_28: # %else52 ; AVX512FVL-NEXT: testl $134217728, %eax # imm = 0x8000000 -; AVX512FVL-NEXT: jne .LBB15_55 -; AVX512FVL-NEXT: .LBB15_56: # %else54 +; AVX512FVL-NEXT: jne .LBB15_60 +; AVX512FVL-NEXT: .LBB15_29: # %else54 ; AVX512FVL-NEXT: testl $268435456, %eax # imm = 0x10000000 -; AVX512FVL-NEXT: jne .LBB15_57 -; AVX512FVL-NEXT: .LBB15_58: # %else56 +; AVX512FVL-NEXT: jne .LBB15_61 +; AVX512FVL-NEXT: .LBB15_30: # %else56 ; AVX512FVL-NEXT: testl $536870912, %eax # imm = 0x20000000 -; AVX512FVL-NEXT: jne .LBB15_59 -; AVX512FVL-NEXT: .LBB15_60: # %else58 +; AVX512FVL-NEXT: jne .LBB15_62 +; AVX512FVL-NEXT: .LBB15_31: # %else58 ; AVX512FVL-NEXT: testl $1073741824, %eax # imm = 0x40000000 -; AVX512FVL-NEXT: jne .LBB15_61 -; AVX512FVL-NEXT: .LBB15_62: # %else60 -; AVX512FVL-NEXT: testl $-2147483648, %eax # imm = 0x80000000 ; AVX512FVL-NEXT: jne .LBB15_63 -; AVX512FVL-NEXT: .LBB15_64: # %else62 +; AVX512FVL-NEXT: .LBB15_32: # %else60 +; AVX512FVL-NEXT: testl $-2147483648, %eax # imm = 0x80000000 +; AVX512FVL-NEXT: jne .LBB15_64 +; AVX512FVL-NEXT: .LBB15_33: # %else62 ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB15_1: # %cond.store +; AVX512FVL-NEXT: .LBB15_34: # %cond.store ; AVX512FVL-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB15_4 -; AVX512FVL-NEXT: .LBB15_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB15_2 +; AVX512FVL-NEXT: .LBB15_35: # %cond.store1 ; AVX512FVL-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB15_6 -; AVX512FVL-NEXT: .LBB15_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB15_3 +; AVX512FVL-NEXT: .LBB15_36: # %cond.store3 ; AVX512FVL-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB15_8 -; AVX512FVL-NEXT: .LBB15_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB15_4 +; AVX512FVL-NEXT: .LBB15_37: # %cond.store5 ; AVX512FVL-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: je .LBB15_10 -; AVX512FVL-NEXT: .LBB15_9: # %cond.store7 +; AVX512FVL-NEXT: je .LBB15_5 +; AVX512FVL-NEXT: .LBB15_38: # %cond.store7 ; AVX512FVL-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: je .LBB15_12 -; AVX512FVL-NEXT: .LBB15_11: # %cond.store9 +; AVX512FVL-NEXT: je .LBB15_6 +; AVX512FVL-NEXT: .LBB15_39: # %cond.store9 ; AVX512FVL-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: je .LBB15_14 -; AVX512FVL-NEXT: .LBB15_13: # %cond.store11 +; AVX512FVL-NEXT: je .LBB15_7 +; AVX512FVL-NEXT: .LBB15_40: # %cond.store11 ; AVX512FVL-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX512FVL-NEXT: testb %al, %al -; AVX512FVL-NEXT: jns .LBB15_16 -; AVX512FVL-NEXT: .LBB15_15: # %cond.store13 +; AVX512FVL-NEXT: jns .LBB15_8 +; AVX512FVL-NEXT: .LBB15_41: # %cond.store13 ; AVX512FVL-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX512FVL-NEXT: testl $256, %eax # imm = 0x100 -; AVX512FVL-NEXT: je .LBB15_18 -; AVX512FVL-NEXT: .LBB15_17: # %cond.store15 +; AVX512FVL-NEXT: je .LBB15_9 +; AVX512FVL-NEXT: .LBB15_42: # %cond.store15 ; AVX512FVL-NEXT: vpextrb $8, %xmm0, 8(%rdi) ; AVX512FVL-NEXT: testl $512, %eax # imm = 0x200 -; AVX512FVL-NEXT: je .LBB15_20 -; AVX512FVL-NEXT: .LBB15_19: # %cond.store17 +; AVX512FVL-NEXT: je .LBB15_10 +; AVX512FVL-NEXT: .LBB15_43: # %cond.store17 ; AVX512FVL-NEXT: vpextrb $9, %xmm0, 9(%rdi) ; AVX512FVL-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512FVL-NEXT: je .LBB15_22 -; AVX512FVL-NEXT: .LBB15_21: # %cond.store19 +; AVX512FVL-NEXT: je .LBB15_11 +; AVX512FVL-NEXT: .LBB15_44: # %cond.store19 ; AVX512FVL-NEXT: vpextrb $10, %xmm0, 10(%rdi) ; AVX512FVL-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512FVL-NEXT: je .LBB15_24 -; AVX512FVL-NEXT: .LBB15_23: # %cond.store21 +; AVX512FVL-NEXT: je .LBB15_12 +; AVX512FVL-NEXT: .LBB15_45: # %cond.store21 ; AVX512FVL-NEXT: vpextrb $11, %xmm0, 11(%rdi) ; AVX512FVL-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512FVL-NEXT: je .LBB15_26 -; AVX512FVL-NEXT: .LBB15_25: # %cond.store23 +; AVX512FVL-NEXT: je .LBB15_13 +; AVX512FVL-NEXT: .LBB15_46: # %cond.store23 ; AVX512FVL-NEXT: vpextrb $12, %xmm0, 12(%rdi) ; AVX512FVL-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512FVL-NEXT: je .LBB15_28 -; AVX512FVL-NEXT: .LBB15_27: # %cond.store25 +; AVX512FVL-NEXT: je .LBB15_14 +; AVX512FVL-NEXT: .LBB15_47: # %cond.store25 ; AVX512FVL-NEXT: vpextrb $13, %xmm0, 13(%rdi) ; AVX512FVL-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512FVL-NEXT: je .LBB15_30 -; AVX512FVL-NEXT: .LBB15_29: # %cond.store27 +; AVX512FVL-NEXT: je .LBB15_15 +; AVX512FVL-NEXT: .LBB15_48: # %cond.store27 ; AVX512FVL-NEXT: vpextrb $14, %xmm0, 14(%rdi) ; AVX512FVL-NEXT: testw %ax, %ax -; AVX512FVL-NEXT: js .LBB15_31 -; AVX512FVL-NEXT: jmp .LBB15_32 -; AVX512FVL-NEXT: .LBB15_33: # %cond.store31 +; AVX512FVL-NEXT: js .LBB15_16 +; AVX512FVL-NEXT: jmp .LBB15_17 +; AVX512FVL-NEXT: .LBB15_49: # %cond.store31 ; AVX512FVL-NEXT: vpextrb $0, %xmm0, 16(%rdi) ; AVX512FVL-NEXT: testl $131072, %eax # imm = 0x20000 -; AVX512FVL-NEXT: je .LBB15_36 -; AVX512FVL-NEXT: .LBB15_35: # %cond.store33 +; AVX512FVL-NEXT: je .LBB15_19 +; AVX512FVL-NEXT: .LBB15_50: # %cond.store33 ; AVX512FVL-NEXT: vpextrb $1, %xmm0, 17(%rdi) ; AVX512FVL-NEXT: testl $262144, %eax # imm = 0x40000 -; AVX512FVL-NEXT: je .LBB15_38 -; AVX512FVL-NEXT: .LBB15_37: # %cond.store35 +; AVX512FVL-NEXT: je .LBB15_20 +; AVX512FVL-NEXT: .LBB15_51: # %cond.store35 ; AVX512FVL-NEXT: vpextrb $2, %xmm0, 18(%rdi) ; AVX512FVL-NEXT: testl $524288, %eax # imm = 0x80000 -; AVX512FVL-NEXT: je .LBB15_40 -; AVX512FVL-NEXT: .LBB15_39: # %cond.store37 +; AVX512FVL-NEXT: je .LBB15_21 +; AVX512FVL-NEXT: .LBB15_52: # %cond.store37 ; AVX512FVL-NEXT: vpextrb $3, %xmm0, 19(%rdi) ; AVX512FVL-NEXT: testl $1048576, %eax # imm = 0x100000 -; AVX512FVL-NEXT: je .LBB15_42 -; AVX512FVL-NEXT: .LBB15_41: # %cond.store39 +; AVX512FVL-NEXT: je .LBB15_22 +; AVX512FVL-NEXT: .LBB15_53: # %cond.store39 ; AVX512FVL-NEXT: vpextrb $4, %xmm0, 20(%rdi) ; AVX512FVL-NEXT: testl $2097152, %eax # imm = 0x200000 -; AVX512FVL-NEXT: je .LBB15_44 -; AVX512FVL-NEXT: .LBB15_43: # %cond.store41 +; AVX512FVL-NEXT: je .LBB15_23 +; AVX512FVL-NEXT: .LBB15_54: # %cond.store41 ; AVX512FVL-NEXT: vpextrb $5, %xmm0, 21(%rdi) ; AVX512FVL-NEXT: testl $4194304, %eax # imm = 0x400000 -; AVX512FVL-NEXT: je .LBB15_46 -; AVX512FVL-NEXT: .LBB15_45: # %cond.store43 +; AVX512FVL-NEXT: je .LBB15_24 +; AVX512FVL-NEXT: .LBB15_55: # %cond.store43 ; AVX512FVL-NEXT: vpextrb $6, %xmm0, 22(%rdi) ; AVX512FVL-NEXT: testl $8388608, %eax # imm = 0x800000 -; AVX512FVL-NEXT: je .LBB15_48 -; AVX512FVL-NEXT: .LBB15_47: # %cond.store45 +; AVX512FVL-NEXT: je .LBB15_25 +; AVX512FVL-NEXT: .LBB15_56: # %cond.store45 ; AVX512FVL-NEXT: vpextrb $7, %xmm0, 23(%rdi) ; AVX512FVL-NEXT: testl $16777216, %eax # imm = 0x1000000 -; AVX512FVL-NEXT: je .LBB15_50 -; AVX512FVL-NEXT: .LBB15_49: # %cond.store47 +; AVX512FVL-NEXT: je .LBB15_26 +; AVX512FVL-NEXT: .LBB15_57: # %cond.store47 ; AVX512FVL-NEXT: vpextrb $8, %xmm0, 24(%rdi) ; AVX512FVL-NEXT: testl $33554432, %eax # imm = 0x2000000 -; AVX512FVL-NEXT: je .LBB15_52 -; AVX512FVL-NEXT: .LBB15_51: # %cond.store49 +; AVX512FVL-NEXT: je .LBB15_27 +; AVX512FVL-NEXT: .LBB15_58: # %cond.store49 ; AVX512FVL-NEXT: vpextrb $9, %xmm0, 25(%rdi) ; AVX512FVL-NEXT: testl $67108864, %eax # imm = 0x4000000 -; AVX512FVL-NEXT: je .LBB15_54 -; AVX512FVL-NEXT: .LBB15_53: # %cond.store51 +; AVX512FVL-NEXT: je .LBB15_28 +; AVX512FVL-NEXT: .LBB15_59: # %cond.store51 ; AVX512FVL-NEXT: vpextrb $10, %xmm0, 26(%rdi) ; AVX512FVL-NEXT: testl $134217728, %eax # imm = 0x8000000 -; AVX512FVL-NEXT: je .LBB15_56 -; AVX512FVL-NEXT: .LBB15_55: # %cond.store53 +; AVX512FVL-NEXT: je .LBB15_29 +; AVX512FVL-NEXT: .LBB15_60: # %cond.store53 ; AVX512FVL-NEXT: vpextrb $11, %xmm0, 27(%rdi) ; AVX512FVL-NEXT: testl $268435456, %eax # imm = 0x10000000 -; AVX512FVL-NEXT: je .LBB15_58 -; AVX512FVL-NEXT: .LBB15_57: # %cond.store55 +; AVX512FVL-NEXT: je .LBB15_30 +; AVX512FVL-NEXT: .LBB15_61: # %cond.store55 ; AVX512FVL-NEXT: vpextrb $12, %xmm0, 28(%rdi) ; AVX512FVL-NEXT: testl $536870912, %eax # imm = 0x20000000 -; AVX512FVL-NEXT: je .LBB15_60 -; AVX512FVL-NEXT: .LBB15_59: # %cond.store57 +; AVX512FVL-NEXT: je .LBB15_31 +; AVX512FVL-NEXT: .LBB15_62: # %cond.store57 ; AVX512FVL-NEXT: vpextrb $13, %xmm0, 29(%rdi) ; AVX512FVL-NEXT: testl $1073741824, %eax # imm = 0x40000000 -; AVX512FVL-NEXT: je .LBB15_62 -; AVX512FVL-NEXT: .LBB15_61: # %cond.store59 +; AVX512FVL-NEXT: je .LBB15_32 +; AVX512FVL-NEXT: .LBB15_63: # %cond.store59 ; AVX512FVL-NEXT: vpextrb $14, %xmm0, 30(%rdi) ; AVX512FVL-NEXT: testl $-2147483648, %eax # imm = 0x80000000 -; AVX512FVL-NEXT: je .LBB15_64 -; AVX512FVL-NEXT: .LBB15_63: # %cond.store61 +; AVX512FVL-NEXT: je .LBB15_33 +; AVX512FVL-NEXT: .LBB15_64: # %cond.store61 ; AVX512FVL-NEXT: vpextrb $15, %xmm0, 31(%rdi) ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq @@ -7349,103 +7349,103 @@ define void @truncstore_v16i16_v16i8(<16 x i16> %x, ptr %p, <16 x i8> %mask) { ; SSE2-NEXT: xorl $65535, %eax # imm = 0xFFFF ; SSE2-NEXT: testb $1, %al ; SSE2-NEXT: movd %xmm0, %ecx -; SSE2-NEXT: jne .LBB16_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB16_28 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne .LBB16_3 -; SSE2-NEXT: .LBB16_4: # %else2 +; SSE2-NEXT: jne .LBB16_29 +; SSE2-NEXT: .LBB16_2: # %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne .LBB16_5 -; SSE2-NEXT: .LBB16_6: # %else4 +; SSE2-NEXT: jne .LBB16_30 +; SSE2-NEXT: .LBB16_3: # %else4 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je .LBB16_8 -; SSE2-NEXT: .LBB16_7: # %cond.store5 +; SSE2-NEXT: je .LBB16_5 +; SSE2-NEXT: .LBB16_4: # %cond.store5 ; SSE2-NEXT: shrl $24, %ecx ; SSE2-NEXT: movb %cl, 3(%rdi) -; SSE2-NEXT: .LBB16_8: # %else6 +; SSE2-NEXT: .LBB16_5: # %else6 ; SSE2-NEXT: testb $16, %al ; SSE2-NEXT: pextrw $2, %xmm0, %ecx -; SSE2-NEXT: je .LBB16_10 -; SSE2-NEXT: # %bb.9: # %cond.store7 +; SSE2-NEXT: je .LBB16_7 +; SSE2-NEXT: # %bb.6: # %cond.store7 ; SSE2-NEXT: movb %cl, 4(%rdi) -; SSE2-NEXT: .LBB16_10: # %else8 +; SSE2-NEXT: .LBB16_7: # %else8 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je .LBB16_12 -; SSE2-NEXT: # %bb.11: # %cond.store9 +; SSE2-NEXT: je .LBB16_9 +; SSE2-NEXT: # %bb.8: # %cond.store9 ; SSE2-NEXT: movb %ch, 5(%rdi) -; SSE2-NEXT: .LBB16_12: # %else10 +; SSE2-NEXT: .LBB16_9: # %else10 ; SSE2-NEXT: testb $64, %al ; SSE2-NEXT: pextrw $3, %xmm0, %ecx -; SSE2-NEXT: je .LBB16_14 -; SSE2-NEXT: # %bb.13: # %cond.store11 +; SSE2-NEXT: je .LBB16_11 +; SSE2-NEXT: # %bb.10: # %cond.store11 ; SSE2-NEXT: movb %cl, 6(%rdi) -; SSE2-NEXT: .LBB16_14: # %else12 +; SSE2-NEXT: .LBB16_11: # %else12 ; SSE2-NEXT: testb %al, %al -; SSE2-NEXT: jns .LBB16_16 -; SSE2-NEXT: # %bb.15: # %cond.store13 +; SSE2-NEXT: jns .LBB16_13 +; SSE2-NEXT: # %bb.12: # %cond.store13 ; SSE2-NEXT: movb %ch, 7(%rdi) -; SSE2-NEXT: .LBB16_16: # %else14 +; SSE2-NEXT: .LBB16_13: # %else14 ; SSE2-NEXT: testl $256, %eax # imm = 0x100 ; SSE2-NEXT: pextrw $4, %xmm0, %ecx -; SSE2-NEXT: je .LBB16_18 -; SSE2-NEXT: # %bb.17: # %cond.store15 +; SSE2-NEXT: je .LBB16_15 +; SSE2-NEXT: # %bb.14: # %cond.store15 ; SSE2-NEXT: movb %cl, 8(%rdi) -; SSE2-NEXT: .LBB16_18: # %else16 +; SSE2-NEXT: .LBB16_15: # %else16 ; SSE2-NEXT: testl $512, %eax # imm = 0x200 -; SSE2-NEXT: je .LBB16_20 -; SSE2-NEXT: # %bb.19: # %cond.store17 +; SSE2-NEXT: je .LBB16_17 +; SSE2-NEXT: # %bb.16: # %cond.store17 ; SSE2-NEXT: movb %ch, 9(%rdi) -; SSE2-NEXT: .LBB16_20: # %else18 +; SSE2-NEXT: .LBB16_17: # %else18 ; SSE2-NEXT: testl $1024, %eax # imm = 0x400 ; SSE2-NEXT: pextrw $5, %xmm0, %ecx -; SSE2-NEXT: je .LBB16_22 -; SSE2-NEXT: # %bb.21: # %cond.store19 +; SSE2-NEXT: je .LBB16_19 +; SSE2-NEXT: # %bb.18: # %cond.store19 ; SSE2-NEXT: movb %cl, 10(%rdi) -; SSE2-NEXT: .LBB16_22: # %else20 +; SSE2-NEXT: .LBB16_19: # %else20 ; SSE2-NEXT: testl $2048, %eax # imm = 0x800 -; SSE2-NEXT: je .LBB16_24 -; SSE2-NEXT: # %bb.23: # %cond.store21 +; SSE2-NEXT: je .LBB16_21 +; SSE2-NEXT: # %bb.20: # %cond.store21 ; SSE2-NEXT: movb %ch, 11(%rdi) -; SSE2-NEXT: .LBB16_24: # %else22 +; SSE2-NEXT: .LBB16_21: # %else22 ; SSE2-NEXT: testl $4096, %eax # imm = 0x1000 ; SSE2-NEXT: pextrw $6, %xmm0, %ecx -; SSE2-NEXT: je .LBB16_26 -; SSE2-NEXT: # %bb.25: # %cond.store23 +; SSE2-NEXT: je .LBB16_23 +; SSE2-NEXT: # %bb.22: # %cond.store23 ; SSE2-NEXT: movb %cl, 12(%rdi) -; SSE2-NEXT: .LBB16_26: # %else24 +; SSE2-NEXT: .LBB16_23: # %else24 ; SSE2-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE2-NEXT: je .LBB16_28 -; SSE2-NEXT: # %bb.27: # %cond.store25 +; SSE2-NEXT: je .LBB16_25 +; SSE2-NEXT: # %bb.24: # %cond.store25 ; SSE2-NEXT: movb %ch, 13(%rdi) -; SSE2-NEXT: .LBB16_28: # %else26 +; SSE2-NEXT: .LBB16_25: # %else26 ; SSE2-NEXT: testl $16384, %eax # imm = 0x4000 ; SSE2-NEXT: pextrw $7, %xmm0, %ecx -; SSE2-NEXT: jne .LBB16_29 -; SSE2-NEXT: # %bb.30: # %else28 -; SSE2-NEXT: testl $32768, %eax # imm = 0x8000 ; SSE2-NEXT: jne .LBB16_31 -; SSE2-NEXT: .LBB16_32: # %else30 +; SSE2-NEXT: # %bb.26: # %else28 +; SSE2-NEXT: testl $32768, %eax # imm = 0x8000 +; SSE2-NEXT: jne .LBB16_32 +; SSE2-NEXT: .LBB16_27: # %else30 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB16_1: # %cond.store +; SSE2-NEXT: .LBB16_28: # %cond.store ; SSE2-NEXT: movb %cl, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB16_4 -; SSE2-NEXT: .LBB16_3: # %cond.store1 +; SSE2-NEXT: je .LBB16_2 +; SSE2-NEXT: .LBB16_29: # %cond.store1 ; SSE2-NEXT: movb %ch, 1(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je .LBB16_6 -; SSE2-NEXT: .LBB16_5: # %cond.store3 +; SSE2-NEXT: je .LBB16_3 +; SSE2-NEXT: .LBB16_30: # %cond.store3 ; SSE2-NEXT: movl %ecx, %edx ; SSE2-NEXT: shrl $16, %edx ; SSE2-NEXT: movb %dl, 2(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne .LBB16_7 -; SSE2-NEXT: jmp .LBB16_8 -; SSE2-NEXT: .LBB16_29: # %cond.store27 +; SSE2-NEXT: jne .LBB16_4 +; SSE2-NEXT: jmp .LBB16_5 +; SSE2-NEXT: .LBB16_31: # %cond.store27 ; SSE2-NEXT: movb %cl, 14(%rdi) ; SSE2-NEXT: testl $32768, %eax # imm = 0x8000 -; SSE2-NEXT: je .LBB16_32 -; SSE2-NEXT: .LBB16_31: # %cond.store29 +; SSE2-NEXT: je .LBB16_27 +; SSE2-NEXT: .LBB16_32: # %cond.store29 ; SSE2-NEXT: movb %ch, 15(%rdi) ; SSE2-NEXT: retq ; @@ -7457,115 +7457,115 @@ define void @truncstore_v16i16_v16i8(<16 x i16> %x, ptr %p, <16 x i8> %mask) { ; SSE4-NEXT: pmovmskb %xmm3, %eax ; SSE4-NEXT: xorl $65535, %eax # imm = 0xFFFF ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB16_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB16_17 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB16_3 -; SSE4-NEXT: .LBB16_4: # %else2 +; SSE4-NEXT: jne .LBB16_18 +; SSE4-NEXT: .LBB16_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB16_5 -; SSE4-NEXT: .LBB16_6: # %else4 +; SSE4-NEXT: jne .LBB16_19 +; SSE4-NEXT: .LBB16_3: # %else4 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne .LBB16_7 -; SSE4-NEXT: .LBB16_8: # %else6 +; SSE4-NEXT: jne .LBB16_20 +; SSE4-NEXT: .LBB16_4: # %else6 ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: jne .LBB16_9 -; SSE4-NEXT: .LBB16_10: # %else8 +; SSE4-NEXT: jne .LBB16_21 +; SSE4-NEXT: .LBB16_5: # %else8 ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: jne .LBB16_11 -; SSE4-NEXT: .LBB16_12: # %else10 +; SSE4-NEXT: jne .LBB16_22 +; SSE4-NEXT: .LBB16_6: # %else10 ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: jne .LBB16_13 -; SSE4-NEXT: .LBB16_14: # %else12 +; SSE4-NEXT: jne .LBB16_23 +; SSE4-NEXT: .LBB16_7: # %else12 ; SSE4-NEXT: testb %al, %al -; SSE4-NEXT: js .LBB16_15 -; SSE4-NEXT: .LBB16_16: # %else14 +; SSE4-NEXT: js .LBB16_24 +; SSE4-NEXT: .LBB16_8: # %else14 ; SSE4-NEXT: testl $256, %eax # imm = 0x100 -; SSE4-NEXT: jne .LBB16_17 -; SSE4-NEXT: .LBB16_18: # %else16 +; SSE4-NEXT: jne .LBB16_25 +; SSE4-NEXT: .LBB16_9: # %else16 ; SSE4-NEXT: testl $512, %eax # imm = 0x200 -; SSE4-NEXT: jne .LBB16_19 -; SSE4-NEXT: .LBB16_20: # %else18 +; SSE4-NEXT: jne .LBB16_26 +; SSE4-NEXT: .LBB16_10: # %else18 ; SSE4-NEXT: testl $1024, %eax # imm = 0x400 -; SSE4-NEXT: jne .LBB16_21 -; SSE4-NEXT: .LBB16_22: # %else20 +; SSE4-NEXT: jne .LBB16_27 +; SSE4-NEXT: .LBB16_11: # %else20 ; SSE4-NEXT: testl $2048, %eax # imm = 0x800 -; SSE4-NEXT: jne .LBB16_23 -; SSE4-NEXT: .LBB16_24: # %else22 +; SSE4-NEXT: jne .LBB16_28 +; SSE4-NEXT: .LBB16_12: # %else22 ; SSE4-NEXT: testl $4096, %eax # imm = 0x1000 -; SSE4-NEXT: jne .LBB16_25 -; SSE4-NEXT: .LBB16_26: # %else24 +; SSE4-NEXT: jne .LBB16_29 +; SSE4-NEXT: .LBB16_13: # %else24 ; SSE4-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE4-NEXT: jne .LBB16_27 -; SSE4-NEXT: .LBB16_28: # %else26 +; SSE4-NEXT: jne .LBB16_30 +; SSE4-NEXT: .LBB16_14: # %else26 ; SSE4-NEXT: testl $16384, %eax # imm = 0x4000 -; SSE4-NEXT: jne .LBB16_29 -; SSE4-NEXT: .LBB16_30: # %else28 -; SSE4-NEXT: testl $32768, %eax # imm = 0x8000 ; SSE4-NEXT: jne .LBB16_31 -; SSE4-NEXT: .LBB16_32: # %else30 +; SSE4-NEXT: .LBB16_15: # %else28 +; SSE4-NEXT: testl $32768, %eax # imm = 0x8000 +; SSE4-NEXT: jne .LBB16_32 +; SSE4-NEXT: .LBB16_16: # %else30 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB16_1: # %cond.store +; SSE4-NEXT: .LBB16_17: # %cond.store ; SSE4-NEXT: pextrb $0, %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB16_4 -; SSE4-NEXT: .LBB16_3: # %cond.store1 +; SSE4-NEXT: je .LBB16_2 +; SSE4-NEXT: .LBB16_18: # %cond.store1 ; SSE4-NEXT: pextrb $1, %xmm0, 1(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB16_6 -; SSE4-NEXT: .LBB16_5: # %cond.store3 +; SSE4-NEXT: je .LBB16_3 +; SSE4-NEXT: .LBB16_19: # %cond.store3 ; SSE4-NEXT: pextrb $2, %xmm0, 2(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB16_8 -; SSE4-NEXT: .LBB16_7: # %cond.store5 +; SSE4-NEXT: je .LBB16_4 +; SSE4-NEXT: .LBB16_20: # %cond.store5 ; SSE4-NEXT: pextrb $3, %xmm0, 3(%rdi) ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: je .LBB16_10 -; SSE4-NEXT: .LBB16_9: # %cond.store7 +; SSE4-NEXT: je .LBB16_5 +; SSE4-NEXT: .LBB16_21: # %cond.store7 ; SSE4-NEXT: pextrb $4, %xmm0, 4(%rdi) ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: je .LBB16_12 -; SSE4-NEXT: .LBB16_11: # %cond.store9 +; SSE4-NEXT: je .LBB16_6 +; SSE4-NEXT: .LBB16_22: # %cond.store9 ; SSE4-NEXT: pextrb $5, %xmm0, 5(%rdi) ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: je .LBB16_14 -; SSE4-NEXT: .LBB16_13: # %cond.store11 +; SSE4-NEXT: je .LBB16_7 +; SSE4-NEXT: .LBB16_23: # %cond.store11 ; SSE4-NEXT: pextrb $6, %xmm0, 6(%rdi) ; SSE4-NEXT: testb %al, %al -; SSE4-NEXT: jns .LBB16_16 -; SSE4-NEXT: .LBB16_15: # %cond.store13 +; SSE4-NEXT: jns .LBB16_8 +; SSE4-NEXT: .LBB16_24: # %cond.store13 ; SSE4-NEXT: pextrb $7, %xmm0, 7(%rdi) ; SSE4-NEXT: testl $256, %eax # imm = 0x100 -; SSE4-NEXT: je .LBB16_18 -; SSE4-NEXT: .LBB16_17: # %cond.store15 +; SSE4-NEXT: je .LBB16_9 +; SSE4-NEXT: .LBB16_25: # %cond.store15 ; SSE4-NEXT: pextrb $8, %xmm0, 8(%rdi) ; SSE4-NEXT: testl $512, %eax # imm = 0x200 -; SSE4-NEXT: je .LBB16_20 -; SSE4-NEXT: .LBB16_19: # %cond.store17 +; SSE4-NEXT: je .LBB16_10 +; SSE4-NEXT: .LBB16_26: # %cond.store17 ; SSE4-NEXT: pextrb $9, %xmm0, 9(%rdi) ; SSE4-NEXT: testl $1024, %eax # imm = 0x400 -; SSE4-NEXT: je .LBB16_22 -; SSE4-NEXT: .LBB16_21: # %cond.store19 +; SSE4-NEXT: je .LBB16_11 +; SSE4-NEXT: .LBB16_27: # %cond.store19 ; SSE4-NEXT: pextrb $10, %xmm0, 10(%rdi) ; SSE4-NEXT: testl $2048, %eax # imm = 0x800 -; SSE4-NEXT: je .LBB16_24 -; SSE4-NEXT: .LBB16_23: # %cond.store21 +; SSE4-NEXT: je .LBB16_12 +; SSE4-NEXT: .LBB16_28: # %cond.store21 ; SSE4-NEXT: pextrb $11, %xmm0, 11(%rdi) ; SSE4-NEXT: testl $4096, %eax # imm = 0x1000 -; SSE4-NEXT: je .LBB16_26 -; SSE4-NEXT: .LBB16_25: # %cond.store23 +; SSE4-NEXT: je .LBB16_13 +; SSE4-NEXT: .LBB16_29: # %cond.store23 ; SSE4-NEXT: pextrb $12, %xmm0, 12(%rdi) ; SSE4-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE4-NEXT: je .LBB16_28 -; SSE4-NEXT: .LBB16_27: # %cond.store25 +; SSE4-NEXT: je .LBB16_14 +; SSE4-NEXT: .LBB16_30: # %cond.store25 ; SSE4-NEXT: pextrb $13, %xmm0, 13(%rdi) ; SSE4-NEXT: testl $16384, %eax # imm = 0x4000 -; SSE4-NEXT: je .LBB16_30 -; SSE4-NEXT: .LBB16_29: # %cond.store27 +; SSE4-NEXT: je .LBB16_15 +; SSE4-NEXT: .LBB16_31: # %cond.store27 ; SSE4-NEXT: pextrb $14, %xmm0, 14(%rdi) ; SSE4-NEXT: testl $32768, %eax # imm = 0x8000 -; SSE4-NEXT: je .LBB16_32 -; SSE4-NEXT: .LBB16_31: # %cond.store29 +; SSE4-NEXT: je .LBB16_16 +; SSE4-NEXT: .LBB16_32: # %cond.store29 ; SSE4-NEXT: pextrb $15, %xmm0, 15(%rdi) ; SSE4-NEXT: retq ; @@ -7578,116 +7578,116 @@ define void @truncstore_v16i16_v16i8(<16 x i16> %x, ptr %p, <16 x i8> %mask) { ; AVX1-NEXT: vpmovmskb %xmm1, %eax ; AVX1-NEXT: xorl $65535, %eax # imm = 0xFFFF ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne .LBB16_1 -; AVX1-NEXT: # %bb.2: # %else +; AVX1-NEXT: jne .LBB16_17 +; AVX1-NEXT: # %bb.1: # %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne .LBB16_3 -; AVX1-NEXT: .LBB16_4: # %else2 +; AVX1-NEXT: jne .LBB16_18 +; AVX1-NEXT: .LBB16_2: # %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne .LBB16_5 -; AVX1-NEXT: .LBB16_6: # %else4 +; AVX1-NEXT: jne .LBB16_19 +; AVX1-NEXT: .LBB16_3: # %else4 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne .LBB16_7 -; AVX1-NEXT: .LBB16_8: # %else6 +; AVX1-NEXT: jne .LBB16_20 +; AVX1-NEXT: .LBB16_4: # %else6 ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: jne .LBB16_9 -; AVX1-NEXT: .LBB16_10: # %else8 +; AVX1-NEXT: jne .LBB16_21 +; AVX1-NEXT: .LBB16_5: # %else8 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: jne .LBB16_11 -; AVX1-NEXT: .LBB16_12: # %else10 +; AVX1-NEXT: jne .LBB16_22 +; AVX1-NEXT: .LBB16_6: # %else10 ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: jne .LBB16_13 -; AVX1-NEXT: .LBB16_14: # %else12 +; AVX1-NEXT: jne .LBB16_23 +; AVX1-NEXT: .LBB16_7: # %else12 ; AVX1-NEXT: testb %al, %al -; AVX1-NEXT: js .LBB16_15 -; AVX1-NEXT: .LBB16_16: # %else14 +; AVX1-NEXT: js .LBB16_24 +; AVX1-NEXT: .LBB16_8: # %else14 ; AVX1-NEXT: testl $256, %eax # imm = 0x100 -; AVX1-NEXT: jne .LBB16_17 -; AVX1-NEXT: .LBB16_18: # %else16 +; AVX1-NEXT: jne .LBB16_25 +; AVX1-NEXT: .LBB16_9: # %else16 ; AVX1-NEXT: testl $512, %eax # imm = 0x200 -; AVX1-NEXT: jne .LBB16_19 -; AVX1-NEXT: .LBB16_20: # %else18 +; AVX1-NEXT: jne .LBB16_26 +; AVX1-NEXT: .LBB16_10: # %else18 ; AVX1-NEXT: testl $1024, %eax # imm = 0x400 -; AVX1-NEXT: jne .LBB16_21 -; AVX1-NEXT: .LBB16_22: # %else20 +; AVX1-NEXT: jne .LBB16_27 +; AVX1-NEXT: .LBB16_11: # %else20 ; AVX1-NEXT: testl $2048, %eax # imm = 0x800 -; AVX1-NEXT: jne .LBB16_23 -; AVX1-NEXT: .LBB16_24: # %else22 +; AVX1-NEXT: jne .LBB16_28 +; AVX1-NEXT: .LBB16_12: # %else22 ; AVX1-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX1-NEXT: jne .LBB16_25 -; AVX1-NEXT: .LBB16_26: # %else24 +; AVX1-NEXT: jne .LBB16_29 +; AVX1-NEXT: .LBB16_13: # %else24 ; AVX1-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX1-NEXT: jne .LBB16_27 -; AVX1-NEXT: .LBB16_28: # %else26 +; AVX1-NEXT: jne .LBB16_30 +; AVX1-NEXT: .LBB16_14: # %else26 ; AVX1-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX1-NEXT: jne .LBB16_29 -; AVX1-NEXT: .LBB16_30: # %else28 -; AVX1-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX1-NEXT: jne .LBB16_31 -; AVX1-NEXT: .LBB16_32: # %else30 +; AVX1-NEXT: .LBB16_15: # %else28 +; AVX1-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX1-NEXT: jne .LBB16_32 +; AVX1-NEXT: .LBB16_16: # %else30 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB16_1: # %cond.store +; AVX1-NEXT: .LBB16_17: # %cond.store ; AVX1-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je .LBB16_4 -; AVX1-NEXT: .LBB16_3: # %cond.store1 +; AVX1-NEXT: je .LBB16_2 +; AVX1-NEXT: .LBB16_18: # %cond.store1 ; AVX1-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je .LBB16_6 -; AVX1-NEXT: .LBB16_5: # %cond.store3 +; AVX1-NEXT: je .LBB16_3 +; AVX1-NEXT: .LBB16_19: # %cond.store3 ; AVX1-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB16_8 -; AVX1-NEXT: .LBB16_7: # %cond.store5 +; AVX1-NEXT: je .LBB16_4 +; AVX1-NEXT: .LBB16_20: # %cond.store5 ; AVX1-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: je .LBB16_10 -; AVX1-NEXT: .LBB16_9: # %cond.store7 +; AVX1-NEXT: je .LBB16_5 +; AVX1-NEXT: .LBB16_21: # %cond.store7 ; AVX1-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je .LBB16_12 -; AVX1-NEXT: .LBB16_11: # %cond.store9 +; AVX1-NEXT: je .LBB16_6 +; AVX1-NEXT: .LBB16_22: # %cond.store9 ; AVX1-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: je .LBB16_14 -; AVX1-NEXT: .LBB16_13: # %cond.store11 +; AVX1-NEXT: je .LBB16_7 +; AVX1-NEXT: .LBB16_23: # %cond.store11 ; AVX1-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX1-NEXT: testb %al, %al -; AVX1-NEXT: jns .LBB16_16 -; AVX1-NEXT: .LBB16_15: # %cond.store13 +; AVX1-NEXT: jns .LBB16_8 +; AVX1-NEXT: .LBB16_24: # %cond.store13 ; AVX1-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX1-NEXT: testl $256, %eax # imm = 0x100 -; AVX1-NEXT: je .LBB16_18 -; AVX1-NEXT: .LBB16_17: # %cond.store15 +; AVX1-NEXT: je .LBB16_9 +; AVX1-NEXT: .LBB16_25: # %cond.store15 ; AVX1-NEXT: vpextrb $8, %xmm0, 8(%rdi) ; AVX1-NEXT: testl $512, %eax # imm = 0x200 -; AVX1-NEXT: je .LBB16_20 -; AVX1-NEXT: .LBB16_19: # %cond.store17 +; AVX1-NEXT: je .LBB16_10 +; AVX1-NEXT: .LBB16_26: # %cond.store17 ; AVX1-NEXT: vpextrb $9, %xmm0, 9(%rdi) ; AVX1-NEXT: testl $1024, %eax # imm = 0x400 -; AVX1-NEXT: je .LBB16_22 -; AVX1-NEXT: .LBB16_21: # %cond.store19 +; AVX1-NEXT: je .LBB16_11 +; AVX1-NEXT: .LBB16_27: # %cond.store19 ; AVX1-NEXT: vpextrb $10, %xmm0, 10(%rdi) ; AVX1-NEXT: testl $2048, %eax # imm = 0x800 -; AVX1-NEXT: je .LBB16_24 -; AVX1-NEXT: .LBB16_23: # %cond.store21 +; AVX1-NEXT: je .LBB16_12 +; AVX1-NEXT: .LBB16_28: # %cond.store21 ; AVX1-NEXT: vpextrb $11, %xmm0, 11(%rdi) ; AVX1-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX1-NEXT: je .LBB16_26 -; AVX1-NEXT: .LBB16_25: # %cond.store23 +; AVX1-NEXT: je .LBB16_13 +; AVX1-NEXT: .LBB16_29: # %cond.store23 ; AVX1-NEXT: vpextrb $12, %xmm0, 12(%rdi) ; AVX1-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX1-NEXT: je .LBB16_28 -; AVX1-NEXT: .LBB16_27: # %cond.store25 +; AVX1-NEXT: je .LBB16_14 +; AVX1-NEXT: .LBB16_30: # %cond.store25 ; AVX1-NEXT: vpextrb $13, %xmm0, 13(%rdi) ; AVX1-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX1-NEXT: je .LBB16_30 -; AVX1-NEXT: .LBB16_29: # %cond.store27 +; AVX1-NEXT: je .LBB16_15 +; AVX1-NEXT: .LBB16_31: # %cond.store27 ; AVX1-NEXT: vpextrb $14, %xmm0, 14(%rdi) ; AVX1-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX1-NEXT: je .LBB16_32 -; AVX1-NEXT: .LBB16_31: # %cond.store29 +; AVX1-NEXT: je .LBB16_16 +; AVX1-NEXT: .LBB16_32: # %cond.store29 ; AVX1-NEXT: vpextrb $15, %xmm0, 15(%rdi) ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq @@ -7701,116 +7701,116 @@ define void @truncstore_v16i16_v16i8(<16 x i16> %x, ptr %p, <16 x i8> %mask) { ; AVX2-NEXT: vpmovmskb %xmm1, %eax ; AVX2-NEXT: xorl $65535, %eax # imm = 0xFFFF ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne .LBB16_1 -; AVX2-NEXT: # %bb.2: # %else +; AVX2-NEXT: jne .LBB16_17 +; AVX2-NEXT: # %bb.1: # %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne .LBB16_3 -; AVX2-NEXT: .LBB16_4: # %else2 +; AVX2-NEXT: jne .LBB16_18 +; AVX2-NEXT: .LBB16_2: # %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne .LBB16_5 -; AVX2-NEXT: .LBB16_6: # %else4 +; AVX2-NEXT: jne .LBB16_19 +; AVX2-NEXT: .LBB16_3: # %else4 ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: jne .LBB16_7 -; AVX2-NEXT: .LBB16_8: # %else6 +; AVX2-NEXT: jne .LBB16_20 +; AVX2-NEXT: .LBB16_4: # %else6 ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: jne .LBB16_9 -; AVX2-NEXT: .LBB16_10: # %else8 +; AVX2-NEXT: jne .LBB16_21 +; AVX2-NEXT: .LBB16_5: # %else8 ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: jne .LBB16_11 -; AVX2-NEXT: .LBB16_12: # %else10 +; AVX2-NEXT: jne .LBB16_22 +; AVX2-NEXT: .LBB16_6: # %else10 ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: jne .LBB16_13 -; AVX2-NEXT: .LBB16_14: # %else12 +; AVX2-NEXT: jne .LBB16_23 +; AVX2-NEXT: .LBB16_7: # %else12 ; AVX2-NEXT: testb %al, %al -; AVX2-NEXT: js .LBB16_15 -; AVX2-NEXT: .LBB16_16: # %else14 +; AVX2-NEXT: js .LBB16_24 +; AVX2-NEXT: .LBB16_8: # %else14 ; AVX2-NEXT: testl $256, %eax # imm = 0x100 -; AVX2-NEXT: jne .LBB16_17 -; AVX2-NEXT: .LBB16_18: # %else16 +; AVX2-NEXT: jne .LBB16_25 +; AVX2-NEXT: .LBB16_9: # %else16 ; AVX2-NEXT: testl $512, %eax # imm = 0x200 -; AVX2-NEXT: jne .LBB16_19 -; AVX2-NEXT: .LBB16_20: # %else18 +; AVX2-NEXT: jne .LBB16_26 +; AVX2-NEXT: .LBB16_10: # %else18 ; AVX2-NEXT: testl $1024, %eax # imm = 0x400 -; AVX2-NEXT: jne .LBB16_21 -; AVX2-NEXT: .LBB16_22: # %else20 +; AVX2-NEXT: jne .LBB16_27 +; AVX2-NEXT: .LBB16_11: # %else20 ; AVX2-NEXT: testl $2048, %eax # imm = 0x800 -; AVX2-NEXT: jne .LBB16_23 -; AVX2-NEXT: .LBB16_24: # %else22 +; AVX2-NEXT: jne .LBB16_28 +; AVX2-NEXT: .LBB16_12: # %else22 ; AVX2-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX2-NEXT: jne .LBB16_25 -; AVX2-NEXT: .LBB16_26: # %else24 +; AVX2-NEXT: jne .LBB16_29 +; AVX2-NEXT: .LBB16_13: # %else24 ; AVX2-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX2-NEXT: jne .LBB16_27 -; AVX2-NEXT: .LBB16_28: # %else26 +; AVX2-NEXT: jne .LBB16_30 +; AVX2-NEXT: .LBB16_14: # %else26 ; AVX2-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX2-NEXT: jne .LBB16_29 -; AVX2-NEXT: .LBB16_30: # %else28 -; AVX2-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX2-NEXT: jne .LBB16_31 -; AVX2-NEXT: .LBB16_32: # %else30 +; AVX2-NEXT: .LBB16_15: # %else28 +; AVX2-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX2-NEXT: jne .LBB16_32 +; AVX2-NEXT: .LBB16_16: # %else30 ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; AVX2-NEXT: .LBB16_1: # %cond.store +; AVX2-NEXT: .LBB16_17: # %cond.store ; AVX2-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je .LBB16_4 -; AVX2-NEXT: .LBB16_3: # %cond.store1 +; AVX2-NEXT: je .LBB16_2 +; AVX2-NEXT: .LBB16_18: # %cond.store1 ; AVX2-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je .LBB16_6 -; AVX2-NEXT: .LBB16_5: # %cond.store3 +; AVX2-NEXT: je .LBB16_3 +; AVX2-NEXT: .LBB16_19: # %cond.store3 ; AVX2-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je .LBB16_8 -; AVX2-NEXT: .LBB16_7: # %cond.store5 +; AVX2-NEXT: je .LBB16_4 +; AVX2-NEXT: .LBB16_20: # %cond.store5 ; AVX2-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: je .LBB16_10 -; AVX2-NEXT: .LBB16_9: # %cond.store7 +; AVX2-NEXT: je .LBB16_5 +; AVX2-NEXT: .LBB16_21: # %cond.store7 ; AVX2-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: je .LBB16_12 -; AVX2-NEXT: .LBB16_11: # %cond.store9 +; AVX2-NEXT: je .LBB16_6 +; AVX2-NEXT: .LBB16_22: # %cond.store9 ; AVX2-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: je .LBB16_14 -; AVX2-NEXT: .LBB16_13: # %cond.store11 +; AVX2-NEXT: je .LBB16_7 +; AVX2-NEXT: .LBB16_23: # %cond.store11 ; AVX2-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX2-NEXT: testb %al, %al -; AVX2-NEXT: jns .LBB16_16 -; AVX2-NEXT: .LBB16_15: # %cond.store13 +; AVX2-NEXT: jns .LBB16_8 +; AVX2-NEXT: .LBB16_24: # %cond.store13 ; AVX2-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX2-NEXT: testl $256, %eax # imm = 0x100 -; AVX2-NEXT: je .LBB16_18 -; AVX2-NEXT: .LBB16_17: # %cond.store15 +; AVX2-NEXT: je .LBB16_9 +; AVX2-NEXT: .LBB16_25: # %cond.store15 ; AVX2-NEXT: vpextrb $8, %xmm0, 8(%rdi) ; AVX2-NEXT: testl $512, %eax # imm = 0x200 -; AVX2-NEXT: je .LBB16_20 -; AVX2-NEXT: .LBB16_19: # %cond.store17 +; AVX2-NEXT: je .LBB16_10 +; AVX2-NEXT: .LBB16_26: # %cond.store17 ; AVX2-NEXT: vpextrb $9, %xmm0, 9(%rdi) ; AVX2-NEXT: testl $1024, %eax # imm = 0x400 -; AVX2-NEXT: je .LBB16_22 -; AVX2-NEXT: .LBB16_21: # %cond.store19 +; AVX2-NEXT: je .LBB16_11 +; AVX2-NEXT: .LBB16_27: # %cond.store19 ; AVX2-NEXT: vpextrb $10, %xmm0, 10(%rdi) ; AVX2-NEXT: testl $2048, %eax # imm = 0x800 -; AVX2-NEXT: je .LBB16_24 -; AVX2-NEXT: .LBB16_23: # %cond.store21 +; AVX2-NEXT: je .LBB16_12 +; AVX2-NEXT: .LBB16_28: # %cond.store21 ; AVX2-NEXT: vpextrb $11, %xmm0, 11(%rdi) ; AVX2-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX2-NEXT: je .LBB16_26 -; AVX2-NEXT: .LBB16_25: # %cond.store23 +; AVX2-NEXT: je .LBB16_13 +; AVX2-NEXT: .LBB16_29: # %cond.store23 ; AVX2-NEXT: vpextrb $12, %xmm0, 12(%rdi) ; AVX2-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX2-NEXT: je .LBB16_28 -; AVX2-NEXT: .LBB16_27: # %cond.store25 +; AVX2-NEXT: je .LBB16_14 +; AVX2-NEXT: .LBB16_30: # %cond.store25 ; AVX2-NEXT: vpextrb $13, %xmm0, 13(%rdi) ; AVX2-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX2-NEXT: je .LBB16_30 -; AVX2-NEXT: .LBB16_29: # %cond.store27 +; AVX2-NEXT: je .LBB16_15 +; AVX2-NEXT: .LBB16_31: # %cond.store27 ; AVX2-NEXT: vpextrb $14, %xmm0, 14(%rdi) ; AVX2-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX2-NEXT: je .LBB16_32 -; AVX2-NEXT: .LBB16_31: # %cond.store29 +; AVX2-NEXT: je .LBB16_16 +; AVX2-NEXT: .LBB16_32: # %cond.store29 ; AVX2-NEXT: vpextrb $15, %xmm0, 15(%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq @@ -7824,116 +7824,116 @@ define void @truncstore_v16i16_v16i8(<16 x i16> %x, ptr %p, <16 x i8> %mask) { ; AVX512F-NEXT: vpmovmskb %xmm1, %eax ; AVX512F-NEXT: xorl $65535, %eax # imm = 0xFFFF ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB16_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB16_17 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB16_3 -; AVX512F-NEXT: .LBB16_4: # %else2 +; AVX512F-NEXT: jne .LBB16_18 +; AVX512F-NEXT: .LBB16_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB16_5 -; AVX512F-NEXT: .LBB16_6: # %else4 +; AVX512F-NEXT: jne .LBB16_19 +; AVX512F-NEXT: .LBB16_3: # %else4 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne .LBB16_7 -; AVX512F-NEXT: .LBB16_8: # %else6 +; AVX512F-NEXT: jne .LBB16_20 +; AVX512F-NEXT: .LBB16_4: # %else6 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne .LBB16_9 -; AVX512F-NEXT: .LBB16_10: # %else8 +; AVX512F-NEXT: jne .LBB16_21 +; AVX512F-NEXT: .LBB16_5: # %else8 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne .LBB16_11 -; AVX512F-NEXT: .LBB16_12: # %else10 +; AVX512F-NEXT: jne .LBB16_22 +; AVX512F-NEXT: .LBB16_6: # %else10 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne .LBB16_13 -; AVX512F-NEXT: .LBB16_14: # %else12 +; AVX512F-NEXT: jne .LBB16_23 +; AVX512F-NEXT: .LBB16_7: # %else12 ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: js .LBB16_15 -; AVX512F-NEXT: .LBB16_16: # %else14 +; AVX512F-NEXT: js .LBB16_24 +; AVX512F-NEXT: .LBB16_8: # %else14 ; AVX512F-NEXT: testl $256, %eax # imm = 0x100 -; AVX512F-NEXT: jne .LBB16_17 -; AVX512F-NEXT: .LBB16_18: # %else16 +; AVX512F-NEXT: jne .LBB16_25 +; AVX512F-NEXT: .LBB16_9: # %else16 ; AVX512F-NEXT: testl $512, %eax # imm = 0x200 -; AVX512F-NEXT: jne .LBB16_19 -; AVX512F-NEXT: .LBB16_20: # %else18 +; AVX512F-NEXT: jne .LBB16_26 +; AVX512F-NEXT: .LBB16_10: # %else18 ; AVX512F-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512F-NEXT: jne .LBB16_21 -; AVX512F-NEXT: .LBB16_22: # %else20 +; AVX512F-NEXT: jne .LBB16_27 +; AVX512F-NEXT: .LBB16_11: # %else20 ; AVX512F-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512F-NEXT: jne .LBB16_23 -; AVX512F-NEXT: .LBB16_24: # %else22 +; AVX512F-NEXT: jne .LBB16_28 +; AVX512F-NEXT: .LBB16_12: # %else22 ; AVX512F-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512F-NEXT: jne .LBB16_25 -; AVX512F-NEXT: .LBB16_26: # %else24 +; AVX512F-NEXT: jne .LBB16_29 +; AVX512F-NEXT: .LBB16_13: # %else24 ; AVX512F-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512F-NEXT: jne .LBB16_27 -; AVX512F-NEXT: .LBB16_28: # %else26 +; AVX512F-NEXT: jne .LBB16_30 +; AVX512F-NEXT: .LBB16_14: # %else26 ; AVX512F-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512F-NEXT: jne .LBB16_29 -; AVX512F-NEXT: .LBB16_30: # %else28 -; AVX512F-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX512F-NEXT: jne .LBB16_31 -; AVX512F-NEXT: .LBB16_32: # %else30 +; AVX512F-NEXT: .LBB16_15: # %else28 +; AVX512F-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX512F-NEXT: jne .LBB16_32 +; AVX512F-NEXT: .LBB16_16: # %else30 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB16_1: # %cond.store +; AVX512F-NEXT: .LBB16_17: # %cond.store ; AVX512F-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB16_4 -; AVX512F-NEXT: .LBB16_3: # %cond.store1 +; AVX512F-NEXT: je .LBB16_2 +; AVX512F-NEXT: .LBB16_18: # %cond.store1 ; AVX512F-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB16_6 -; AVX512F-NEXT: .LBB16_5: # %cond.store3 +; AVX512F-NEXT: je .LBB16_3 +; AVX512F-NEXT: .LBB16_19: # %cond.store3 ; AVX512F-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB16_8 -; AVX512F-NEXT: .LBB16_7: # %cond.store5 +; AVX512F-NEXT: je .LBB16_4 +; AVX512F-NEXT: .LBB16_20: # %cond.store5 ; AVX512F-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je .LBB16_10 -; AVX512F-NEXT: .LBB16_9: # %cond.store7 +; AVX512F-NEXT: je .LBB16_5 +; AVX512F-NEXT: .LBB16_21: # %cond.store7 ; AVX512F-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je .LBB16_12 -; AVX512F-NEXT: .LBB16_11: # %cond.store9 +; AVX512F-NEXT: je .LBB16_6 +; AVX512F-NEXT: .LBB16_22: # %cond.store9 ; AVX512F-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je .LBB16_14 -; AVX512F-NEXT: .LBB16_13: # %cond.store11 +; AVX512F-NEXT: je .LBB16_7 +; AVX512F-NEXT: .LBB16_23: # %cond.store11 ; AVX512F-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: jns .LBB16_16 -; AVX512F-NEXT: .LBB16_15: # %cond.store13 +; AVX512F-NEXT: jns .LBB16_8 +; AVX512F-NEXT: .LBB16_24: # %cond.store13 ; AVX512F-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX512F-NEXT: testl $256, %eax # imm = 0x100 -; AVX512F-NEXT: je .LBB16_18 -; AVX512F-NEXT: .LBB16_17: # %cond.store15 +; AVX512F-NEXT: je .LBB16_9 +; AVX512F-NEXT: .LBB16_25: # %cond.store15 ; AVX512F-NEXT: vpextrb $8, %xmm0, 8(%rdi) ; AVX512F-NEXT: testl $512, %eax # imm = 0x200 -; AVX512F-NEXT: je .LBB16_20 -; AVX512F-NEXT: .LBB16_19: # %cond.store17 +; AVX512F-NEXT: je .LBB16_10 +; AVX512F-NEXT: .LBB16_26: # %cond.store17 ; AVX512F-NEXT: vpextrb $9, %xmm0, 9(%rdi) ; AVX512F-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512F-NEXT: je .LBB16_22 -; AVX512F-NEXT: .LBB16_21: # %cond.store19 +; AVX512F-NEXT: je .LBB16_11 +; AVX512F-NEXT: .LBB16_27: # %cond.store19 ; AVX512F-NEXT: vpextrb $10, %xmm0, 10(%rdi) ; AVX512F-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512F-NEXT: je .LBB16_24 -; AVX512F-NEXT: .LBB16_23: # %cond.store21 +; AVX512F-NEXT: je .LBB16_12 +; AVX512F-NEXT: .LBB16_28: # %cond.store21 ; AVX512F-NEXT: vpextrb $11, %xmm0, 11(%rdi) ; AVX512F-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512F-NEXT: je .LBB16_26 -; AVX512F-NEXT: .LBB16_25: # %cond.store23 +; AVX512F-NEXT: je .LBB16_13 +; AVX512F-NEXT: .LBB16_29: # %cond.store23 ; AVX512F-NEXT: vpextrb $12, %xmm0, 12(%rdi) ; AVX512F-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512F-NEXT: je .LBB16_28 -; AVX512F-NEXT: .LBB16_27: # %cond.store25 +; AVX512F-NEXT: je .LBB16_14 +; AVX512F-NEXT: .LBB16_30: # %cond.store25 ; AVX512F-NEXT: vpextrb $13, %xmm0, 13(%rdi) ; AVX512F-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512F-NEXT: je .LBB16_30 -; AVX512F-NEXT: .LBB16_29: # %cond.store27 +; AVX512F-NEXT: je .LBB16_15 +; AVX512F-NEXT: .LBB16_31: # %cond.store27 ; AVX512F-NEXT: vpextrb $14, %xmm0, 14(%rdi) ; AVX512F-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX512F-NEXT: je .LBB16_32 -; AVX512F-NEXT: .LBB16_31: # %cond.store29 +; AVX512F-NEXT: je .LBB16_16 +; AVX512F-NEXT: .LBB16_32: # %cond.store29 ; AVX512F-NEXT: vpextrb $15, %xmm0, 15(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -7947,116 +7947,116 @@ define void @truncstore_v16i16_v16i8(<16 x i16> %x, ptr %p, <16 x i8> %mask) { ; AVX512FVL-NEXT: vpmovmskb %xmm1, %eax ; AVX512FVL-NEXT: xorl $65535, %eax # imm = 0xFFFF ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB16_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB16_17 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB16_3 -; AVX512FVL-NEXT: .LBB16_4: # %else2 +; AVX512FVL-NEXT: jne .LBB16_18 +; AVX512FVL-NEXT: .LBB16_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB16_5 -; AVX512FVL-NEXT: .LBB16_6: # %else4 +; AVX512FVL-NEXT: jne .LBB16_19 +; AVX512FVL-NEXT: .LBB16_3: # %else4 ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: jne .LBB16_7 -; AVX512FVL-NEXT: .LBB16_8: # %else6 +; AVX512FVL-NEXT: jne .LBB16_20 +; AVX512FVL-NEXT: .LBB16_4: # %else6 ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: jne .LBB16_9 -; AVX512FVL-NEXT: .LBB16_10: # %else8 +; AVX512FVL-NEXT: jne .LBB16_21 +; AVX512FVL-NEXT: .LBB16_5: # %else8 ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: jne .LBB16_11 -; AVX512FVL-NEXT: .LBB16_12: # %else10 +; AVX512FVL-NEXT: jne .LBB16_22 +; AVX512FVL-NEXT: .LBB16_6: # %else10 ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: jne .LBB16_13 -; AVX512FVL-NEXT: .LBB16_14: # %else12 +; AVX512FVL-NEXT: jne .LBB16_23 +; AVX512FVL-NEXT: .LBB16_7: # %else12 ; AVX512FVL-NEXT: testb %al, %al -; AVX512FVL-NEXT: js .LBB16_15 -; AVX512FVL-NEXT: .LBB16_16: # %else14 +; AVX512FVL-NEXT: js .LBB16_24 +; AVX512FVL-NEXT: .LBB16_8: # %else14 ; AVX512FVL-NEXT: testl $256, %eax # imm = 0x100 -; AVX512FVL-NEXT: jne .LBB16_17 -; AVX512FVL-NEXT: .LBB16_18: # %else16 +; AVX512FVL-NEXT: jne .LBB16_25 +; AVX512FVL-NEXT: .LBB16_9: # %else16 ; AVX512FVL-NEXT: testl $512, %eax # imm = 0x200 -; AVX512FVL-NEXT: jne .LBB16_19 -; AVX512FVL-NEXT: .LBB16_20: # %else18 +; AVX512FVL-NEXT: jne .LBB16_26 +; AVX512FVL-NEXT: .LBB16_10: # %else18 ; AVX512FVL-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512FVL-NEXT: jne .LBB16_21 -; AVX512FVL-NEXT: .LBB16_22: # %else20 +; AVX512FVL-NEXT: jne .LBB16_27 +; AVX512FVL-NEXT: .LBB16_11: # %else20 ; AVX512FVL-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512FVL-NEXT: jne .LBB16_23 -; AVX512FVL-NEXT: .LBB16_24: # %else22 +; AVX512FVL-NEXT: jne .LBB16_28 +; AVX512FVL-NEXT: .LBB16_12: # %else22 ; AVX512FVL-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512FVL-NEXT: jne .LBB16_25 -; AVX512FVL-NEXT: .LBB16_26: # %else24 +; AVX512FVL-NEXT: jne .LBB16_29 +; AVX512FVL-NEXT: .LBB16_13: # %else24 ; AVX512FVL-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512FVL-NEXT: jne .LBB16_27 -; AVX512FVL-NEXT: .LBB16_28: # %else26 +; AVX512FVL-NEXT: jne .LBB16_30 +; AVX512FVL-NEXT: .LBB16_14: # %else26 ; AVX512FVL-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512FVL-NEXT: jne .LBB16_29 -; AVX512FVL-NEXT: .LBB16_30: # %else28 -; AVX512FVL-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX512FVL-NEXT: jne .LBB16_31 -; AVX512FVL-NEXT: .LBB16_32: # %else30 +; AVX512FVL-NEXT: .LBB16_15: # %else28 +; AVX512FVL-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX512FVL-NEXT: jne .LBB16_32 +; AVX512FVL-NEXT: .LBB16_16: # %else30 ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB16_1: # %cond.store +; AVX512FVL-NEXT: .LBB16_17: # %cond.store ; AVX512FVL-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB16_4 -; AVX512FVL-NEXT: .LBB16_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB16_2 +; AVX512FVL-NEXT: .LBB16_18: # %cond.store1 ; AVX512FVL-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB16_6 -; AVX512FVL-NEXT: .LBB16_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB16_3 +; AVX512FVL-NEXT: .LBB16_19: # %cond.store3 ; AVX512FVL-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB16_8 -; AVX512FVL-NEXT: .LBB16_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB16_4 +; AVX512FVL-NEXT: .LBB16_20: # %cond.store5 ; AVX512FVL-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: je .LBB16_10 -; AVX512FVL-NEXT: .LBB16_9: # %cond.store7 +; AVX512FVL-NEXT: je .LBB16_5 +; AVX512FVL-NEXT: .LBB16_21: # %cond.store7 ; AVX512FVL-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: je .LBB16_12 -; AVX512FVL-NEXT: .LBB16_11: # %cond.store9 +; AVX512FVL-NEXT: je .LBB16_6 +; AVX512FVL-NEXT: .LBB16_22: # %cond.store9 ; AVX512FVL-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: je .LBB16_14 -; AVX512FVL-NEXT: .LBB16_13: # %cond.store11 +; AVX512FVL-NEXT: je .LBB16_7 +; AVX512FVL-NEXT: .LBB16_23: # %cond.store11 ; AVX512FVL-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX512FVL-NEXT: testb %al, %al -; AVX512FVL-NEXT: jns .LBB16_16 -; AVX512FVL-NEXT: .LBB16_15: # %cond.store13 +; AVX512FVL-NEXT: jns .LBB16_8 +; AVX512FVL-NEXT: .LBB16_24: # %cond.store13 ; AVX512FVL-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX512FVL-NEXT: testl $256, %eax # imm = 0x100 -; AVX512FVL-NEXT: je .LBB16_18 -; AVX512FVL-NEXT: .LBB16_17: # %cond.store15 +; AVX512FVL-NEXT: je .LBB16_9 +; AVX512FVL-NEXT: .LBB16_25: # %cond.store15 ; AVX512FVL-NEXT: vpextrb $8, %xmm0, 8(%rdi) ; AVX512FVL-NEXT: testl $512, %eax # imm = 0x200 -; AVX512FVL-NEXT: je .LBB16_20 -; AVX512FVL-NEXT: .LBB16_19: # %cond.store17 +; AVX512FVL-NEXT: je .LBB16_10 +; AVX512FVL-NEXT: .LBB16_26: # %cond.store17 ; AVX512FVL-NEXT: vpextrb $9, %xmm0, 9(%rdi) ; AVX512FVL-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512FVL-NEXT: je .LBB16_22 -; AVX512FVL-NEXT: .LBB16_21: # %cond.store19 +; AVX512FVL-NEXT: je .LBB16_11 +; AVX512FVL-NEXT: .LBB16_27: # %cond.store19 ; AVX512FVL-NEXT: vpextrb $10, %xmm0, 10(%rdi) ; AVX512FVL-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512FVL-NEXT: je .LBB16_24 -; AVX512FVL-NEXT: .LBB16_23: # %cond.store21 +; AVX512FVL-NEXT: je .LBB16_12 +; AVX512FVL-NEXT: .LBB16_28: # %cond.store21 ; AVX512FVL-NEXT: vpextrb $11, %xmm0, 11(%rdi) ; AVX512FVL-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512FVL-NEXT: je .LBB16_26 -; AVX512FVL-NEXT: .LBB16_25: # %cond.store23 +; AVX512FVL-NEXT: je .LBB16_13 +; AVX512FVL-NEXT: .LBB16_29: # %cond.store23 ; AVX512FVL-NEXT: vpextrb $12, %xmm0, 12(%rdi) ; AVX512FVL-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512FVL-NEXT: je .LBB16_28 -; AVX512FVL-NEXT: .LBB16_27: # %cond.store25 +; AVX512FVL-NEXT: je .LBB16_14 +; AVX512FVL-NEXT: .LBB16_30: # %cond.store25 ; AVX512FVL-NEXT: vpextrb $13, %xmm0, 13(%rdi) ; AVX512FVL-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512FVL-NEXT: je .LBB16_30 -; AVX512FVL-NEXT: .LBB16_29: # %cond.store27 +; AVX512FVL-NEXT: je .LBB16_15 +; AVX512FVL-NEXT: .LBB16_31: # %cond.store27 ; AVX512FVL-NEXT: vpextrb $14, %xmm0, 14(%rdi) ; AVX512FVL-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX512FVL-NEXT: je .LBB16_32 -; AVX512FVL-NEXT: .LBB16_31: # %cond.store29 +; AVX512FVL-NEXT: je .LBB16_16 +; AVX512FVL-NEXT: .LBB16_32: # %cond.store29 ; AVX512FVL-NEXT: vpextrb $15, %xmm0, 15(%rdi) ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq @@ -8099,59 +8099,59 @@ define void @truncstore_v8i16_v8i8(<8 x i16> %x, ptr %p, <8 x i16> %mask) { ; SSE2-NEXT: notl %eax ; SSE2-NEXT: testb $1, %al ; SSE2-NEXT: movd %xmm0, %ecx -; SSE2-NEXT: jne .LBB17_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB17_12 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne .LBB17_3 -; SSE2-NEXT: .LBB17_4: # %else2 +; SSE2-NEXT: jne .LBB17_13 +; SSE2-NEXT: .LBB17_2: # %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne .LBB17_5 -; SSE2-NEXT: .LBB17_6: # %else4 +; SSE2-NEXT: jne .LBB17_14 +; SSE2-NEXT: .LBB17_3: # %else4 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je .LBB17_8 -; SSE2-NEXT: .LBB17_7: # %cond.store5 +; SSE2-NEXT: je .LBB17_5 +; SSE2-NEXT: .LBB17_4: # %cond.store5 ; SSE2-NEXT: shrl $24, %ecx ; SSE2-NEXT: movb %cl, 3(%rdi) -; SSE2-NEXT: .LBB17_8: # %else6 +; SSE2-NEXT: .LBB17_5: # %else6 ; SSE2-NEXT: testb $16, %al ; SSE2-NEXT: pextrw $2, %xmm0, %ecx -; SSE2-NEXT: je .LBB17_10 -; SSE2-NEXT: # %bb.9: # %cond.store7 +; SSE2-NEXT: je .LBB17_7 +; SSE2-NEXT: # %bb.6: # %cond.store7 ; SSE2-NEXT: movb %cl, 4(%rdi) -; SSE2-NEXT: .LBB17_10: # %else8 +; SSE2-NEXT: .LBB17_7: # %else8 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je .LBB17_12 -; SSE2-NEXT: # %bb.11: # %cond.store9 +; SSE2-NEXT: je .LBB17_9 +; SSE2-NEXT: # %bb.8: # %cond.store9 ; SSE2-NEXT: movb %ch, 5(%rdi) -; SSE2-NEXT: .LBB17_12: # %else10 +; SSE2-NEXT: .LBB17_9: # %else10 ; SSE2-NEXT: testb $64, %al ; SSE2-NEXT: pextrw $3, %xmm0, %ecx -; SSE2-NEXT: jne .LBB17_13 -; SSE2-NEXT: # %bb.14: # %else12 -; SSE2-NEXT: testb $-128, %al ; SSE2-NEXT: jne .LBB17_15 -; SSE2-NEXT: .LBB17_16: # %else14 +; SSE2-NEXT: # %bb.10: # %else12 +; SSE2-NEXT: testb $-128, %al +; SSE2-NEXT: jne .LBB17_16 +; SSE2-NEXT: .LBB17_11: # %else14 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB17_1: # %cond.store +; SSE2-NEXT: .LBB17_12: # %cond.store ; SSE2-NEXT: movb %cl, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB17_4 -; SSE2-NEXT: .LBB17_3: # %cond.store1 +; SSE2-NEXT: je .LBB17_2 +; SSE2-NEXT: .LBB17_13: # %cond.store1 ; SSE2-NEXT: movb %ch, 1(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je .LBB17_6 -; SSE2-NEXT: .LBB17_5: # %cond.store3 +; SSE2-NEXT: je .LBB17_3 +; SSE2-NEXT: .LBB17_14: # %cond.store3 ; SSE2-NEXT: movl %ecx, %edx ; SSE2-NEXT: shrl $16, %edx ; SSE2-NEXT: movb %dl, 2(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne .LBB17_7 -; SSE2-NEXT: jmp .LBB17_8 -; SSE2-NEXT: .LBB17_13: # %cond.store11 +; SSE2-NEXT: jne .LBB17_4 +; SSE2-NEXT: jmp .LBB17_5 +; SSE2-NEXT: .LBB17_15: # %cond.store11 ; SSE2-NEXT: movb %cl, 6(%rdi) ; SSE2-NEXT: testb $-128, %al -; SSE2-NEXT: je .LBB17_16 -; SSE2-NEXT: .LBB17_15: # %cond.store13 +; SSE2-NEXT: je .LBB17_11 +; SSE2-NEXT: .LBB17_16: # %cond.store13 ; SSE2-NEXT: movb %ch, 7(%rdi) ; SSE2-NEXT: retq ; @@ -8164,59 +8164,59 @@ define void @truncstore_v8i16_v8i8(<8 x i16> %x, ptr %p, <8 x i16> %mask) { ; SSE4-NEXT: pmovmskb %xmm2, %eax ; SSE4-NEXT: notl %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB17_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB17_9 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB17_3 -; SSE4-NEXT: .LBB17_4: # %else2 +; SSE4-NEXT: jne .LBB17_10 +; SSE4-NEXT: .LBB17_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB17_5 -; SSE4-NEXT: .LBB17_6: # %else4 +; SSE4-NEXT: jne .LBB17_11 +; SSE4-NEXT: .LBB17_3: # %else4 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne .LBB17_7 -; SSE4-NEXT: .LBB17_8: # %else6 +; SSE4-NEXT: jne .LBB17_12 +; SSE4-NEXT: .LBB17_4: # %else6 ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: jne .LBB17_9 -; SSE4-NEXT: .LBB17_10: # %else8 +; SSE4-NEXT: jne .LBB17_13 +; SSE4-NEXT: .LBB17_5: # %else8 ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: jne .LBB17_11 -; SSE4-NEXT: .LBB17_12: # %else10 +; SSE4-NEXT: jne .LBB17_14 +; SSE4-NEXT: .LBB17_6: # %else10 ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: jne .LBB17_13 -; SSE4-NEXT: .LBB17_14: # %else12 -; SSE4-NEXT: testb $-128, %al ; SSE4-NEXT: jne .LBB17_15 -; SSE4-NEXT: .LBB17_16: # %else14 +; SSE4-NEXT: .LBB17_7: # %else12 +; SSE4-NEXT: testb $-128, %al +; SSE4-NEXT: jne .LBB17_16 +; SSE4-NEXT: .LBB17_8: # %else14 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB17_1: # %cond.store +; SSE4-NEXT: .LBB17_9: # %cond.store ; SSE4-NEXT: pextrb $0, %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB17_4 -; SSE4-NEXT: .LBB17_3: # %cond.store1 +; SSE4-NEXT: je .LBB17_2 +; SSE4-NEXT: .LBB17_10: # %cond.store1 ; SSE4-NEXT: pextrb $1, %xmm0, 1(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB17_6 -; SSE4-NEXT: .LBB17_5: # %cond.store3 +; SSE4-NEXT: je .LBB17_3 +; SSE4-NEXT: .LBB17_11: # %cond.store3 ; SSE4-NEXT: pextrb $2, %xmm0, 2(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB17_8 -; SSE4-NEXT: .LBB17_7: # %cond.store5 +; SSE4-NEXT: je .LBB17_4 +; SSE4-NEXT: .LBB17_12: # %cond.store5 ; SSE4-NEXT: pextrb $3, %xmm0, 3(%rdi) ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: je .LBB17_10 -; SSE4-NEXT: .LBB17_9: # %cond.store7 +; SSE4-NEXT: je .LBB17_5 +; SSE4-NEXT: .LBB17_13: # %cond.store7 ; SSE4-NEXT: pextrb $4, %xmm0, 4(%rdi) ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: je .LBB17_12 -; SSE4-NEXT: .LBB17_11: # %cond.store9 +; SSE4-NEXT: je .LBB17_6 +; SSE4-NEXT: .LBB17_14: # %cond.store9 ; SSE4-NEXT: pextrb $5, %xmm0, 5(%rdi) ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: je .LBB17_14 -; SSE4-NEXT: .LBB17_13: # %cond.store11 +; SSE4-NEXT: je .LBB17_7 +; SSE4-NEXT: .LBB17_15: # %cond.store11 ; SSE4-NEXT: pextrb $6, %xmm0, 6(%rdi) ; SSE4-NEXT: testb $-128, %al -; SSE4-NEXT: je .LBB17_16 -; SSE4-NEXT: .LBB17_15: # %cond.store13 +; SSE4-NEXT: je .LBB17_8 +; SSE4-NEXT: .LBB17_16: # %cond.store13 ; SSE4-NEXT: pextrb $7, %xmm0, 7(%rdi) ; SSE4-NEXT: retq ; @@ -8229,59 +8229,59 @@ define void @truncstore_v8i16_v8i8(<8 x i16> %x, ptr %p, <8 x i16> %mask) { ; AVX-NEXT: vpmovmskb %xmm1, %eax ; AVX-NEXT: notl %eax ; AVX-NEXT: testb $1, %al -; AVX-NEXT: jne .LBB17_1 -; AVX-NEXT: # %bb.2: # %else +; AVX-NEXT: jne .LBB17_9 +; AVX-NEXT: # %bb.1: # %else ; AVX-NEXT: testb $2, %al -; AVX-NEXT: jne .LBB17_3 -; AVX-NEXT: .LBB17_4: # %else2 +; AVX-NEXT: jne .LBB17_10 +; AVX-NEXT: .LBB17_2: # %else2 ; AVX-NEXT: testb $4, %al -; AVX-NEXT: jne .LBB17_5 -; AVX-NEXT: .LBB17_6: # %else4 +; AVX-NEXT: jne .LBB17_11 +; AVX-NEXT: .LBB17_3: # %else4 ; AVX-NEXT: testb $8, %al -; AVX-NEXT: jne .LBB17_7 -; AVX-NEXT: .LBB17_8: # %else6 +; AVX-NEXT: jne .LBB17_12 +; AVX-NEXT: .LBB17_4: # %else6 ; AVX-NEXT: testb $16, %al -; AVX-NEXT: jne .LBB17_9 -; AVX-NEXT: .LBB17_10: # %else8 +; AVX-NEXT: jne .LBB17_13 +; AVX-NEXT: .LBB17_5: # %else8 ; AVX-NEXT: testb $32, %al -; AVX-NEXT: jne .LBB17_11 -; AVX-NEXT: .LBB17_12: # %else10 +; AVX-NEXT: jne .LBB17_14 +; AVX-NEXT: .LBB17_6: # %else10 ; AVX-NEXT: testb $64, %al -; AVX-NEXT: jne .LBB17_13 -; AVX-NEXT: .LBB17_14: # %else12 -; AVX-NEXT: testb $-128, %al ; AVX-NEXT: jne .LBB17_15 -; AVX-NEXT: .LBB17_16: # %else14 +; AVX-NEXT: .LBB17_7: # %else12 +; AVX-NEXT: testb $-128, %al +; AVX-NEXT: jne .LBB17_16 +; AVX-NEXT: .LBB17_8: # %else14 ; AVX-NEXT: retq -; AVX-NEXT: .LBB17_1: # %cond.store +; AVX-NEXT: .LBB17_9: # %cond.store ; AVX-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX-NEXT: testb $2, %al -; AVX-NEXT: je .LBB17_4 -; AVX-NEXT: .LBB17_3: # %cond.store1 +; AVX-NEXT: je .LBB17_2 +; AVX-NEXT: .LBB17_10: # %cond.store1 ; AVX-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX-NEXT: testb $4, %al -; AVX-NEXT: je .LBB17_6 -; AVX-NEXT: .LBB17_5: # %cond.store3 +; AVX-NEXT: je .LBB17_3 +; AVX-NEXT: .LBB17_11: # %cond.store3 ; AVX-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX-NEXT: testb $8, %al -; AVX-NEXT: je .LBB17_8 -; AVX-NEXT: .LBB17_7: # %cond.store5 +; AVX-NEXT: je .LBB17_4 +; AVX-NEXT: .LBB17_12: # %cond.store5 ; AVX-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX-NEXT: testb $16, %al -; AVX-NEXT: je .LBB17_10 -; AVX-NEXT: .LBB17_9: # %cond.store7 +; AVX-NEXT: je .LBB17_5 +; AVX-NEXT: .LBB17_13: # %cond.store7 ; AVX-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX-NEXT: testb $32, %al -; AVX-NEXT: je .LBB17_12 -; AVX-NEXT: .LBB17_11: # %cond.store9 +; AVX-NEXT: je .LBB17_6 +; AVX-NEXT: .LBB17_14: # %cond.store9 ; AVX-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX-NEXT: testb $64, %al -; AVX-NEXT: je .LBB17_14 -; AVX-NEXT: .LBB17_13: # %cond.store11 +; AVX-NEXT: je .LBB17_7 +; AVX-NEXT: .LBB17_15: # %cond.store11 ; AVX-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX-NEXT: testb $-128, %al -; AVX-NEXT: je .LBB17_16 -; AVX-NEXT: .LBB17_15: # %cond.store13 +; AVX-NEXT: je .LBB17_8 +; AVX-NEXT: .LBB17_16: # %cond.store13 ; AVX-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX-NEXT: retq ; @@ -8295,60 +8295,60 @@ define void @truncstore_v8i16_v8i8(<8 x i16> %x, ptr %p, <8 x i16> %mask) { ; AVX512F-NEXT: vpacksswb %xmm0, %xmm0, %xmm0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB17_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB17_9 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB17_3 -; AVX512F-NEXT: .LBB17_4: # %else2 +; AVX512F-NEXT: jne .LBB17_10 +; AVX512F-NEXT: .LBB17_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB17_5 -; AVX512F-NEXT: .LBB17_6: # %else4 +; AVX512F-NEXT: jne .LBB17_11 +; AVX512F-NEXT: .LBB17_3: # %else4 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne .LBB17_7 -; AVX512F-NEXT: .LBB17_8: # %else6 +; AVX512F-NEXT: jne .LBB17_12 +; AVX512F-NEXT: .LBB17_4: # %else6 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne .LBB17_9 -; AVX512F-NEXT: .LBB17_10: # %else8 +; AVX512F-NEXT: jne .LBB17_13 +; AVX512F-NEXT: .LBB17_5: # %else8 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne .LBB17_11 -; AVX512F-NEXT: .LBB17_12: # %else10 +; AVX512F-NEXT: jne .LBB17_14 +; AVX512F-NEXT: .LBB17_6: # %else10 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne .LBB17_13 -; AVX512F-NEXT: .LBB17_14: # %else12 -; AVX512F-NEXT: testb $-128, %al ; AVX512F-NEXT: jne .LBB17_15 -; AVX512F-NEXT: .LBB17_16: # %else14 +; AVX512F-NEXT: .LBB17_7: # %else12 +; AVX512F-NEXT: testb $-128, %al +; AVX512F-NEXT: jne .LBB17_16 +; AVX512F-NEXT: .LBB17_8: # %else14 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB17_1: # %cond.store +; AVX512F-NEXT: .LBB17_9: # %cond.store ; AVX512F-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB17_4 -; AVX512F-NEXT: .LBB17_3: # %cond.store1 +; AVX512F-NEXT: je .LBB17_2 +; AVX512F-NEXT: .LBB17_10: # %cond.store1 ; AVX512F-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB17_6 -; AVX512F-NEXT: .LBB17_5: # %cond.store3 +; AVX512F-NEXT: je .LBB17_3 +; AVX512F-NEXT: .LBB17_11: # %cond.store3 ; AVX512F-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB17_8 -; AVX512F-NEXT: .LBB17_7: # %cond.store5 +; AVX512F-NEXT: je .LBB17_4 +; AVX512F-NEXT: .LBB17_12: # %cond.store5 ; AVX512F-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je .LBB17_10 -; AVX512F-NEXT: .LBB17_9: # %cond.store7 +; AVX512F-NEXT: je .LBB17_5 +; AVX512F-NEXT: .LBB17_13: # %cond.store7 ; AVX512F-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je .LBB17_12 -; AVX512F-NEXT: .LBB17_11: # %cond.store9 +; AVX512F-NEXT: je .LBB17_6 +; AVX512F-NEXT: .LBB17_14: # %cond.store9 ; AVX512F-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je .LBB17_14 -; AVX512F-NEXT: .LBB17_13: # %cond.store11 +; AVX512F-NEXT: je .LBB17_7 +; AVX512F-NEXT: .LBB17_15: # %cond.store11 ; AVX512F-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX512F-NEXT: testb $-128, %al -; AVX512F-NEXT: je .LBB17_16 -; AVX512F-NEXT: .LBB17_15: # %cond.store13 +; AVX512F-NEXT: je .LBB17_8 +; AVX512F-NEXT: .LBB17_16: # %cond.store13 ; AVX512F-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -8363,60 +8363,60 @@ define void @truncstore_v8i16_v8i8(<8 x i16> %x, ptr %p, <8 x i16> %mask) { ; AVX512FVL-NEXT: vpacksswb %xmm0, %xmm0, %xmm0 ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB17_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB17_9 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB17_3 -; AVX512FVL-NEXT: .LBB17_4: # %else2 +; AVX512FVL-NEXT: jne .LBB17_10 +; AVX512FVL-NEXT: .LBB17_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB17_5 -; AVX512FVL-NEXT: .LBB17_6: # %else4 +; AVX512FVL-NEXT: jne .LBB17_11 +; AVX512FVL-NEXT: .LBB17_3: # %else4 ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: jne .LBB17_7 -; AVX512FVL-NEXT: .LBB17_8: # %else6 +; AVX512FVL-NEXT: jne .LBB17_12 +; AVX512FVL-NEXT: .LBB17_4: # %else6 ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: jne .LBB17_9 -; AVX512FVL-NEXT: .LBB17_10: # %else8 +; AVX512FVL-NEXT: jne .LBB17_13 +; AVX512FVL-NEXT: .LBB17_5: # %else8 ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: jne .LBB17_11 -; AVX512FVL-NEXT: .LBB17_12: # %else10 +; AVX512FVL-NEXT: jne .LBB17_14 +; AVX512FVL-NEXT: .LBB17_6: # %else10 ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: jne .LBB17_13 -; AVX512FVL-NEXT: .LBB17_14: # %else12 -; AVX512FVL-NEXT: testb $-128, %al ; AVX512FVL-NEXT: jne .LBB17_15 -; AVX512FVL-NEXT: .LBB17_16: # %else14 +; AVX512FVL-NEXT: .LBB17_7: # %else12 +; AVX512FVL-NEXT: testb $-128, %al +; AVX512FVL-NEXT: jne .LBB17_16 +; AVX512FVL-NEXT: .LBB17_8: # %else14 ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB17_1: # %cond.store +; AVX512FVL-NEXT: .LBB17_9: # %cond.store ; AVX512FVL-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB17_4 -; AVX512FVL-NEXT: .LBB17_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB17_2 +; AVX512FVL-NEXT: .LBB17_10: # %cond.store1 ; AVX512FVL-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB17_6 -; AVX512FVL-NEXT: .LBB17_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB17_3 +; AVX512FVL-NEXT: .LBB17_11: # %cond.store3 ; AVX512FVL-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB17_8 -; AVX512FVL-NEXT: .LBB17_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB17_4 +; AVX512FVL-NEXT: .LBB17_12: # %cond.store5 ; AVX512FVL-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: je .LBB17_10 -; AVX512FVL-NEXT: .LBB17_9: # %cond.store7 +; AVX512FVL-NEXT: je .LBB17_5 +; AVX512FVL-NEXT: .LBB17_13: # %cond.store7 ; AVX512FVL-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: je .LBB17_12 -; AVX512FVL-NEXT: .LBB17_11: # %cond.store9 +; AVX512FVL-NEXT: je .LBB17_6 +; AVX512FVL-NEXT: .LBB17_14: # %cond.store9 ; AVX512FVL-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: je .LBB17_14 -; AVX512FVL-NEXT: .LBB17_13: # %cond.store11 +; AVX512FVL-NEXT: je .LBB17_7 +; AVX512FVL-NEXT: .LBB17_15: # %cond.store11 ; AVX512FVL-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX512FVL-NEXT: testb $-128, %al -; AVX512FVL-NEXT: je .LBB17_16 -; AVX512FVL-NEXT: .LBB17_15: # %cond.store13 +; AVX512FVL-NEXT: je .LBB17_8 +; AVX512FVL-NEXT: .LBB17_16: # %cond.store13 ; AVX512FVL-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq diff --git a/llvm/test/CodeGen/X86/masked_store_trunc_usat.ll b/llvm/test/CodeGen/X86/masked_store_trunc_usat.ll index d214fb694252f..53aefd8475673 100644 --- a/llvm/test/CodeGen/X86/masked_store_trunc_usat.ll +++ b/llvm/test/CodeGen/X86/masked_store_trunc_usat.ll @@ -90,33 +90,33 @@ define void @truncstore_v8i64_v8i32(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; SSE2-NEXT: .LBB0_8: # %else6 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm3[0,2] ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: jne .LBB0_9 -; SSE2-NEXT: # %bb.10: # %else8 +; SSE2-NEXT: jne .LBB0_13 +; SSE2-NEXT: # %bb.9: # %else8 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: jne .LBB0_11 -; SSE2-NEXT: .LBB0_12: # %else10 +; SSE2-NEXT: jne .LBB0_14 +; SSE2-NEXT: .LBB0_10: # %else10 ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: jne .LBB0_13 -; SSE2-NEXT: .LBB0_14: # %else12 -; SSE2-NEXT: testb $-128, %al ; SSE2-NEXT: jne .LBB0_15 -; SSE2-NEXT: .LBB0_16: # %else14 +; SSE2-NEXT: .LBB0_11: # %else12 +; SSE2-NEXT: testb $-128, %al +; SSE2-NEXT: jne .LBB0_16 +; SSE2-NEXT: .LBB0_12: # %else14 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB0_9: # %cond.store7 +; SSE2-NEXT: .LBB0_13: # %cond.store7 ; SSE2-NEXT: movss %xmm2, 16(%rdi) ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je .LBB0_12 -; SSE2-NEXT: .LBB0_11: # %cond.store9 +; SSE2-NEXT: je .LBB0_10 +; SSE2-NEXT: .LBB0_14: # %cond.store9 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,1,1] ; SSE2-NEXT: movd %xmm0, 20(%rdi) ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: je .LBB0_14 -; SSE2-NEXT: .LBB0_13: # %cond.store11 +; SSE2-NEXT: je .LBB0_11 +; SSE2-NEXT: .LBB0_15: # %cond.store11 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[2,3,2,3] ; SSE2-NEXT: movd %xmm0, 24(%rdi) ; SSE2-NEXT: testb $-128, %al -; SSE2-NEXT: je .LBB0_16 -; SSE2-NEXT: .LBB0_15: # %cond.store13 +; SSE2-NEXT: je .LBB0_12 +; SSE2-NEXT: .LBB0_16: # %cond.store13 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[3,3,3,3] ; SSE2-NEXT: movd %xmm0, 28(%rdi) ; SSE2-NEXT: retq @@ -158,59 +158,59 @@ define void @truncstore_v8i64_v8i32(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; SSE4-NEXT: pmovmskb %xmm4, %eax ; SSE4-NEXT: notl %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB0_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB0_10 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB0_3 -; SSE4-NEXT: .LBB0_4: # %else2 +; SSE4-NEXT: jne .LBB0_11 +; SSE4-NEXT: .LBB0_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB0_5 -; SSE4-NEXT: .LBB0_6: # %else4 +; SSE4-NEXT: jne .LBB0_12 +; SSE4-NEXT: .LBB0_3: # %else4 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB0_8 -; SSE4-NEXT: .LBB0_7: # %cond.store5 +; SSE4-NEXT: je .LBB0_5 +; SSE4-NEXT: .LBB0_4: # %cond.store5 ; SSE4-NEXT: extractps $3, %xmm1, 12(%rdi) -; SSE4-NEXT: .LBB0_8: # %else6 +; SSE4-NEXT: .LBB0_5: # %else6 ; SSE4-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,2],xmm6[0,2] ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: jne .LBB0_9 -; SSE4-NEXT: # %bb.10: # %else8 +; SSE4-NEXT: jne .LBB0_13 +; SSE4-NEXT: # %bb.6: # %else8 ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: jne .LBB0_11 -; SSE4-NEXT: .LBB0_12: # %else10 +; SSE4-NEXT: jne .LBB0_14 +; SSE4-NEXT: .LBB0_7: # %else10 ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: jne .LBB0_13 -; SSE4-NEXT: .LBB0_14: # %else12 -; SSE4-NEXT: testb $-128, %al ; SSE4-NEXT: jne .LBB0_15 -; SSE4-NEXT: .LBB0_16: # %else14 +; SSE4-NEXT: .LBB0_8: # %else12 +; SSE4-NEXT: testb $-128, %al +; SSE4-NEXT: jne .LBB0_16 +; SSE4-NEXT: .LBB0_9: # %else14 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB0_1: # %cond.store +; SSE4-NEXT: .LBB0_10: # %cond.store ; SSE4-NEXT: movss %xmm1, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB0_4 -; SSE4-NEXT: .LBB0_3: # %cond.store1 +; SSE4-NEXT: je .LBB0_2 +; SSE4-NEXT: .LBB0_11: # %cond.store1 ; SSE4-NEXT: extractps $1, %xmm1, 4(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB0_6 -; SSE4-NEXT: .LBB0_5: # %cond.store3 +; SSE4-NEXT: je .LBB0_3 +; SSE4-NEXT: .LBB0_12: # %cond.store3 ; SSE4-NEXT: extractps $2, %xmm1, 8(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne .LBB0_7 -; SSE4-NEXT: jmp .LBB0_8 -; SSE4-NEXT: .LBB0_9: # %cond.store7 +; SSE4-NEXT: jne .LBB0_4 +; SSE4-NEXT: jmp .LBB0_5 +; SSE4-NEXT: .LBB0_13: # %cond.store7 ; SSE4-NEXT: movss %xmm8, 16(%rdi) ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: je .LBB0_12 -; SSE4-NEXT: .LBB0_11: # %cond.store9 +; SSE4-NEXT: je .LBB0_7 +; SSE4-NEXT: .LBB0_14: # %cond.store9 ; SSE4-NEXT: extractps $1, %xmm8, 20(%rdi) ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: je .LBB0_14 -; SSE4-NEXT: .LBB0_13: # %cond.store11 +; SSE4-NEXT: je .LBB0_8 +; SSE4-NEXT: .LBB0_15: # %cond.store11 ; SSE4-NEXT: extractps $2, %xmm8, 24(%rdi) ; SSE4-NEXT: testb $-128, %al -; SSE4-NEXT: je .LBB0_16 -; SSE4-NEXT: .LBB0_15: # %cond.store13 +; SSE4-NEXT: je .LBB0_9 +; SSE4-NEXT: .LBB0_16: # %cond.store13 ; SSE4-NEXT: extractps $3, %xmm8, 28(%rdi) ; SSE4-NEXT: retq ; @@ -375,66 +375,66 @@ define void @truncstore_v8i64_v8i16(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; SSE2-NEXT: pmovmskb %xmm4, %eax ; SSE2-NEXT: notl %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne .LBB1_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB1_9 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne .LBB1_3 -; SSE2-NEXT: .LBB1_4: # %else2 +; SSE2-NEXT: jne .LBB1_10 +; SSE2-NEXT: .LBB1_2: # %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne .LBB1_5 -; SSE2-NEXT: .LBB1_6: # %else4 +; SSE2-NEXT: jne .LBB1_11 +; SSE2-NEXT: .LBB1_3: # %else4 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne .LBB1_7 -; SSE2-NEXT: .LBB1_8: # %else6 +; SSE2-NEXT: jne .LBB1_12 +; SSE2-NEXT: .LBB1_4: # %else6 ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: jne .LBB1_9 -; SSE2-NEXT: .LBB1_10: # %else8 +; SSE2-NEXT: jne .LBB1_13 +; SSE2-NEXT: .LBB1_5: # %else8 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: jne .LBB1_11 -; SSE2-NEXT: .LBB1_12: # %else10 +; SSE2-NEXT: jne .LBB1_14 +; SSE2-NEXT: .LBB1_6: # %else10 ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: jne .LBB1_13 -; SSE2-NEXT: .LBB1_14: # %else12 -; SSE2-NEXT: testb $-128, %al ; SSE2-NEXT: jne .LBB1_15 -; SSE2-NEXT: .LBB1_16: # %else14 +; SSE2-NEXT: .LBB1_7: # %else12 +; SSE2-NEXT: testb $-128, %al +; SSE2-NEXT: jne .LBB1_16 +; SSE2-NEXT: .LBB1_8: # %else14 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB1_1: # %cond.store +; SSE2-NEXT: .LBB1_9: # %cond.store ; SSE2-NEXT: movd %xmm1, %ecx ; SSE2-NEXT: movw %cx, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB1_4 -; SSE2-NEXT: .LBB1_3: # %cond.store1 +; SSE2-NEXT: je .LBB1_2 +; SSE2-NEXT: .LBB1_10: # %cond.store1 ; SSE2-NEXT: pextrw $1, %xmm1, %ecx ; SSE2-NEXT: movw %cx, 2(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je .LBB1_6 -; SSE2-NEXT: .LBB1_5: # %cond.store3 +; SSE2-NEXT: je .LBB1_3 +; SSE2-NEXT: .LBB1_11: # %cond.store3 ; SSE2-NEXT: pextrw $2, %xmm1, %ecx ; SSE2-NEXT: movw %cx, 4(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je .LBB1_8 -; SSE2-NEXT: .LBB1_7: # %cond.store5 +; SSE2-NEXT: je .LBB1_4 +; SSE2-NEXT: .LBB1_12: # %cond.store5 ; SSE2-NEXT: pextrw $3, %xmm1, %ecx ; SSE2-NEXT: movw %cx, 6(%rdi) ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: je .LBB1_10 -; SSE2-NEXT: .LBB1_9: # %cond.store7 +; SSE2-NEXT: je .LBB1_5 +; SSE2-NEXT: .LBB1_13: # %cond.store7 ; SSE2-NEXT: pextrw $4, %xmm1, %ecx ; SSE2-NEXT: movw %cx, 8(%rdi) ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je .LBB1_12 -; SSE2-NEXT: .LBB1_11: # %cond.store9 +; SSE2-NEXT: je .LBB1_6 +; SSE2-NEXT: .LBB1_14: # %cond.store9 ; SSE2-NEXT: pextrw $5, %xmm1, %ecx ; SSE2-NEXT: movw %cx, 10(%rdi) ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: je .LBB1_14 -; SSE2-NEXT: .LBB1_13: # %cond.store11 +; SSE2-NEXT: je .LBB1_7 +; SSE2-NEXT: .LBB1_15: # %cond.store11 ; SSE2-NEXT: pextrw $6, %xmm1, %ecx ; SSE2-NEXT: movw %cx, 12(%rdi) ; SSE2-NEXT: testb $-128, %al -; SSE2-NEXT: je .LBB1_16 -; SSE2-NEXT: .LBB1_15: # %cond.store13 +; SSE2-NEXT: je .LBB1_8 +; SSE2-NEXT: .LBB1_16: # %cond.store13 ; SSE2-NEXT: pextrw $7, %xmm1, %eax ; SSE2-NEXT: movw %ax, 14(%rdi) ; SSE2-NEXT: retq @@ -478,59 +478,59 @@ define void @truncstore_v8i64_v8i16(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; SSE4-NEXT: pmovmskb %xmm4, %eax ; SSE4-NEXT: notl %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB1_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB1_9 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB1_3 -; SSE4-NEXT: .LBB1_4: # %else2 +; SSE4-NEXT: jne .LBB1_10 +; SSE4-NEXT: .LBB1_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB1_5 -; SSE4-NEXT: .LBB1_6: # %else4 +; SSE4-NEXT: jne .LBB1_11 +; SSE4-NEXT: .LBB1_3: # %else4 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne .LBB1_7 -; SSE4-NEXT: .LBB1_8: # %else6 +; SSE4-NEXT: jne .LBB1_12 +; SSE4-NEXT: .LBB1_4: # %else6 ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: jne .LBB1_9 -; SSE4-NEXT: .LBB1_10: # %else8 +; SSE4-NEXT: jne .LBB1_13 +; SSE4-NEXT: .LBB1_5: # %else8 ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: jne .LBB1_11 -; SSE4-NEXT: .LBB1_12: # %else10 +; SSE4-NEXT: jne .LBB1_14 +; SSE4-NEXT: .LBB1_6: # %else10 ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: jne .LBB1_13 -; SSE4-NEXT: .LBB1_14: # %else12 -; SSE4-NEXT: testb $-128, %al ; SSE4-NEXT: jne .LBB1_15 -; SSE4-NEXT: .LBB1_16: # %else14 +; SSE4-NEXT: .LBB1_7: # %else12 +; SSE4-NEXT: testb $-128, %al +; SSE4-NEXT: jne .LBB1_16 +; SSE4-NEXT: .LBB1_8: # %else14 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB1_1: # %cond.store +; SSE4-NEXT: .LBB1_9: # %cond.store ; SSE4-NEXT: pextrw $0, %xmm1, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB1_4 -; SSE4-NEXT: .LBB1_3: # %cond.store1 +; SSE4-NEXT: je .LBB1_2 +; SSE4-NEXT: .LBB1_10: # %cond.store1 ; SSE4-NEXT: pextrw $1, %xmm1, 2(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB1_6 -; SSE4-NEXT: .LBB1_5: # %cond.store3 +; SSE4-NEXT: je .LBB1_3 +; SSE4-NEXT: .LBB1_11: # %cond.store3 ; SSE4-NEXT: pextrw $2, %xmm1, 4(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB1_8 -; SSE4-NEXT: .LBB1_7: # %cond.store5 +; SSE4-NEXT: je .LBB1_4 +; SSE4-NEXT: .LBB1_12: # %cond.store5 ; SSE4-NEXT: pextrw $3, %xmm1, 6(%rdi) ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: je .LBB1_10 -; SSE4-NEXT: .LBB1_9: # %cond.store7 +; SSE4-NEXT: je .LBB1_5 +; SSE4-NEXT: .LBB1_13: # %cond.store7 ; SSE4-NEXT: pextrw $4, %xmm1, 8(%rdi) ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: je .LBB1_12 -; SSE4-NEXT: .LBB1_11: # %cond.store9 +; SSE4-NEXT: je .LBB1_6 +; SSE4-NEXT: .LBB1_14: # %cond.store9 ; SSE4-NEXT: pextrw $5, %xmm1, 10(%rdi) ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: je .LBB1_14 -; SSE4-NEXT: .LBB1_13: # %cond.store11 +; SSE4-NEXT: je .LBB1_7 +; SSE4-NEXT: .LBB1_15: # %cond.store11 ; SSE4-NEXT: pextrw $6, %xmm1, 12(%rdi) ; SSE4-NEXT: testb $-128, %al -; SSE4-NEXT: je .LBB1_16 -; SSE4-NEXT: .LBB1_15: # %cond.store13 +; SSE4-NEXT: je .LBB1_8 +; SSE4-NEXT: .LBB1_16: # %cond.store13 ; SSE4-NEXT: pextrw $7, %xmm1, 14(%rdi) ; SSE4-NEXT: retq ; @@ -567,60 +567,60 @@ define void @truncstore_v8i64_v8i16(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; AVX1-NEXT: vmovmskps %ymm1, %eax ; AVX1-NEXT: notl %eax ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne .LBB1_1 -; AVX1-NEXT: # %bb.2: # %else +; AVX1-NEXT: jne .LBB1_9 +; AVX1-NEXT: # %bb.1: # %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne .LBB1_3 -; AVX1-NEXT: .LBB1_4: # %else2 +; AVX1-NEXT: jne .LBB1_10 +; AVX1-NEXT: .LBB1_2: # %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne .LBB1_5 -; AVX1-NEXT: .LBB1_6: # %else4 +; AVX1-NEXT: jne .LBB1_11 +; AVX1-NEXT: .LBB1_3: # %else4 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne .LBB1_7 -; AVX1-NEXT: .LBB1_8: # %else6 +; AVX1-NEXT: jne .LBB1_12 +; AVX1-NEXT: .LBB1_4: # %else6 ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: jne .LBB1_9 -; AVX1-NEXT: .LBB1_10: # %else8 +; AVX1-NEXT: jne .LBB1_13 +; AVX1-NEXT: .LBB1_5: # %else8 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: jne .LBB1_11 -; AVX1-NEXT: .LBB1_12: # %else10 +; AVX1-NEXT: jne .LBB1_14 +; AVX1-NEXT: .LBB1_6: # %else10 ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: jne .LBB1_13 -; AVX1-NEXT: .LBB1_14: # %else12 -; AVX1-NEXT: testb $-128, %al ; AVX1-NEXT: jne .LBB1_15 -; AVX1-NEXT: .LBB1_16: # %else14 +; AVX1-NEXT: .LBB1_7: # %else12 +; AVX1-NEXT: testb $-128, %al +; AVX1-NEXT: jne .LBB1_16 +; AVX1-NEXT: .LBB1_8: # %else14 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB1_1: # %cond.store +; AVX1-NEXT: .LBB1_9: # %cond.store ; AVX1-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je .LBB1_4 -; AVX1-NEXT: .LBB1_3: # %cond.store1 +; AVX1-NEXT: je .LBB1_2 +; AVX1-NEXT: .LBB1_10: # %cond.store1 ; AVX1-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je .LBB1_6 -; AVX1-NEXT: .LBB1_5: # %cond.store3 +; AVX1-NEXT: je .LBB1_3 +; AVX1-NEXT: .LBB1_11: # %cond.store3 ; AVX1-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB1_8 -; AVX1-NEXT: .LBB1_7: # %cond.store5 +; AVX1-NEXT: je .LBB1_4 +; AVX1-NEXT: .LBB1_12: # %cond.store5 ; AVX1-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: je .LBB1_10 -; AVX1-NEXT: .LBB1_9: # %cond.store7 +; AVX1-NEXT: je .LBB1_5 +; AVX1-NEXT: .LBB1_13: # %cond.store7 ; AVX1-NEXT: vpextrw $4, %xmm0, 8(%rdi) ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je .LBB1_12 -; AVX1-NEXT: .LBB1_11: # %cond.store9 +; AVX1-NEXT: je .LBB1_6 +; AVX1-NEXT: .LBB1_14: # %cond.store9 ; AVX1-NEXT: vpextrw $5, %xmm0, 10(%rdi) ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: je .LBB1_14 -; AVX1-NEXT: .LBB1_13: # %cond.store11 +; AVX1-NEXT: je .LBB1_7 +; AVX1-NEXT: .LBB1_15: # %cond.store11 ; AVX1-NEXT: vpextrw $6, %xmm0, 12(%rdi) ; AVX1-NEXT: testb $-128, %al -; AVX1-NEXT: je .LBB1_16 -; AVX1-NEXT: .LBB1_15: # %cond.store13 +; AVX1-NEXT: je .LBB1_8 +; AVX1-NEXT: .LBB1_16: # %cond.store13 ; AVX1-NEXT: vpextrw $7, %xmm0, 14(%rdi) ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq @@ -645,60 +645,60 @@ define void @truncstore_v8i64_v8i16(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; AVX2-NEXT: vmovmskps %ymm1, %eax ; AVX2-NEXT: notl %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne .LBB1_1 -; AVX2-NEXT: # %bb.2: # %else +; AVX2-NEXT: jne .LBB1_9 +; AVX2-NEXT: # %bb.1: # %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne .LBB1_3 -; AVX2-NEXT: .LBB1_4: # %else2 +; AVX2-NEXT: jne .LBB1_10 +; AVX2-NEXT: .LBB1_2: # %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne .LBB1_5 -; AVX2-NEXT: .LBB1_6: # %else4 +; AVX2-NEXT: jne .LBB1_11 +; AVX2-NEXT: .LBB1_3: # %else4 ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: jne .LBB1_7 -; AVX2-NEXT: .LBB1_8: # %else6 +; AVX2-NEXT: jne .LBB1_12 +; AVX2-NEXT: .LBB1_4: # %else6 ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: jne .LBB1_9 -; AVX2-NEXT: .LBB1_10: # %else8 +; AVX2-NEXT: jne .LBB1_13 +; AVX2-NEXT: .LBB1_5: # %else8 ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: jne .LBB1_11 -; AVX2-NEXT: .LBB1_12: # %else10 +; AVX2-NEXT: jne .LBB1_14 +; AVX2-NEXT: .LBB1_6: # %else10 ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: jne .LBB1_13 -; AVX2-NEXT: .LBB1_14: # %else12 -; AVX2-NEXT: testb $-128, %al ; AVX2-NEXT: jne .LBB1_15 -; AVX2-NEXT: .LBB1_16: # %else14 +; AVX2-NEXT: .LBB1_7: # %else12 +; AVX2-NEXT: testb $-128, %al +; AVX2-NEXT: jne .LBB1_16 +; AVX2-NEXT: .LBB1_8: # %else14 ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; AVX2-NEXT: .LBB1_1: # %cond.store +; AVX2-NEXT: .LBB1_9: # %cond.store ; AVX2-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je .LBB1_4 -; AVX2-NEXT: .LBB1_3: # %cond.store1 +; AVX2-NEXT: je .LBB1_2 +; AVX2-NEXT: .LBB1_10: # %cond.store1 ; AVX2-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je .LBB1_6 -; AVX2-NEXT: .LBB1_5: # %cond.store3 +; AVX2-NEXT: je .LBB1_3 +; AVX2-NEXT: .LBB1_11: # %cond.store3 ; AVX2-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je .LBB1_8 -; AVX2-NEXT: .LBB1_7: # %cond.store5 +; AVX2-NEXT: je .LBB1_4 +; AVX2-NEXT: .LBB1_12: # %cond.store5 ; AVX2-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: je .LBB1_10 -; AVX2-NEXT: .LBB1_9: # %cond.store7 +; AVX2-NEXT: je .LBB1_5 +; AVX2-NEXT: .LBB1_13: # %cond.store7 ; AVX2-NEXT: vpextrw $4, %xmm0, 8(%rdi) ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: je .LBB1_12 -; AVX2-NEXT: .LBB1_11: # %cond.store9 +; AVX2-NEXT: je .LBB1_6 +; AVX2-NEXT: .LBB1_14: # %cond.store9 ; AVX2-NEXT: vpextrw $5, %xmm0, 10(%rdi) ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: je .LBB1_14 -; AVX2-NEXT: .LBB1_13: # %cond.store11 +; AVX2-NEXT: je .LBB1_7 +; AVX2-NEXT: .LBB1_15: # %cond.store11 ; AVX2-NEXT: vpextrw $6, %xmm0, 12(%rdi) ; AVX2-NEXT: testb $-128, %al -; AVX2-NEXT: je .LBB1_16 -; AVX2-NEXT: .LBB1_15: # %cond.store13 +; AVX2-NEXT: je .LBB1_8 +; AVX2-NEXT: .LBB1_16: # %cond.store13 ; AVX2-NEXT: vpextrw $7, %xmm0, 14(%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq @@ -710,60 +710,60 @@ define void @truncstore_v8i64_v8i16(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; AVX512F-NEXT: vpmovusqw %zmm0, %xmm0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB1_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB1_9 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB1_3 -; AVX512F-NEXT: .LBB1_4: # %else2 +; AVX512F-NEXT: jne .LBB1_10 +; AVX512F-NEXT: .LBB1_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB1_5 -; AVX512F-NEXT: .LBB1_6: # %else4 +; AVX512F-NEXT: jne .LBB1_11 +; AVX512F-NEXT: .LBB1_3: # %else4 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne .LBB1_7 -; AVX512F-NEXT: .LBB1_8: # %else6 +; AVX512F-NEXT: jne .LBB1_12 +; AVX512F-NEXT: .LBB1_4: # %else6 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne .LBB1_9 -; AVX512F-NEXT: .LBB1_10: # %else8 +; AVX512F-NEXT: jne .LBB1_13 +; AVX512F-NEXT: .LBB1_5: # %else8 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne .LBB1_11 -; AVX512F-NEXT: .LBB1_12: # %else10 +; AVX512F-NEXT: jne .LBB1_14 +; AVX512F-NEXT: .LBB1_6: # %else10 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne .LBB1_13 -; AVX512F-NEXT: .LBB1_14: # %else12 -; AVX512F-NEXT: testb $-128, %al ; AVX512F-NEXT: jne .LBB1_15 -; AVX512F-NEXT: .LBB1_16: # %else14 +; AVX512F-NEXT: .LBB1_7: # %else12 +; AVX512F-NEXT: testb $-128, %al +; AVX512F-NEXT: jne .LBB1_16 +; AVX512F-NEXT: .LBB1_8: # %else14 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB1_1: # %cond.store +; AVX512F-NEXT: .LBB1_9: # %cond.store ; AVX512F-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB1_4 -; AVX512F-NEXT: .LBB1_3: # %cond.store1 +; AVX512F-NEXT: je .LBB1_2 +; AVX512F-NEXT: .LBB1_10: # %cond.store1 ; AVX512F-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB1_6 -; AVX512F-NEXT: .LBB1_5: # %cond.store3 +; AVX512F-NEXT: je .LBB1_3 +; AVX512F-NEXT: .LBB1_11: # %cond.store3 ; AVX512F-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB1_8 -; AVX512F-NEXT: .LBB1_7: # %cond.store5 +; AVX512F-NEXT: je .LBB1_4 +; AVX512F-NEXT: .LBB1_12: # %cond.store5 ; AVX512F-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je .LBB1_10 -; AVX512F-NEXT: .LBB1_9: # %cond.store7 +; AVX512F-NEXT: je .LBB1_5 +; AVX512F-NEXT: .LBB1_13: # %cond.store7 ; AVX512F-NEXT: vpextrw $4, %xmm0, 8(%rdi) ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je .LBB1_12 -; AVX512F-NEXT: .LBB1_11: # %cond.store9 +; AVX512F-NEXT: je .LBB1_6 +; AVX512F-NEXT: .LBB1_14: # %cond.store9 ; AVX512F-NEXT: vpextrw $5, %xmm0, 10(%rdi) ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je .LBB1_14 -; AVX512F-NEXT: .LBB1_13: # %cond.store11 +; AVX512F-NEXT: je .LBB1_7 +; AVX512F-NEXT: .LBB1_15: # %cond.store11 ; AVX512F-NEXT: vpextrw $6, %xmm0, 12(%rdi) ; AVX512F-NEXT: testb $-128, %al -; AVX512F-NEXT: je .LBB1_16 -; AVX512F-NEXT: .LBB1_15: # %cond.store13 +; AVX512F-NEXT: je .LBB1_8 +; AVX512F-NEXT: .LBB1_16: # %cond.store13 ; AVX512F-NEXT: vpextrw $7, %xmm0, 14(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -774,60 +774,60 @@ define void @truncstore_v8i64_v8i16(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; AVX512FVL-NEXT: vpmovusqw %zmm0, %xmm0 ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB1_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB1_9 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB1_3 -; AVX512FVL-NEXT: .LBB1_4: # %else2 +; AVX512FVL-NEXT: jne .LBB1_10 +; AVX512FVL-NEXT: .LBB1_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB1_5 -; AVX512FVL-NEXT: .LBB1_6: # %else4 +; AVX512FVL-NEXT: jne .LBB1_11 +; AVX512FVL-NEXT: .LBB1_3: # %else4 ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: jne .LBB1_7 -; AVX512FVL-NEXT: .LBB1_8: # %else6 +; AVX512FVL-NEXT: jne .LBB1_12 +; AVX512FVL-NEXT: .LBB1_4: # %else6 ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: jne .LBB1_9 -; AVX512FVL-NEXT: .LBB1_10: # %else8 +; AVX512FVL-NEXT: jne .LBB1_13 +; AVX512FVL-NEXT: .LBB1_5: # %else8 ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: jne .LBB1_11 -; AVX512FVL-NEXT: .LBB1_12: # %else10 +; AVX512FVL-NEXT: jne .LBB1_14 +; AVX512FVL-NEXT: .LBB1_6: # %else10 ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: jne .LBB1_13 -; AVX512FVL-NEXT: .LBB1_14: # %else12 -; AVX512FVL-NEXT: testb $-128, %al ; AVX512FVL-NEXT: jne .LBB1_15 -; AVX512FVL-NEXT: .LBB1_16: # %else14 +; AVX512FVL-NEXT: .LBB1_7: # %else12 +; AVX512FVL-NEXT: testb $-128, %al +; AVX512FVL-NEXT: jne .LBB1_16 +; AVX512FVL-NEXT: .LBB1_8: # %else14 ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB1_1: # %cond.store +; AVX512FVL-NEXT: .LBB1_9: # %cond.store ; AVX512FVL-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB1_4 -; AVX512FVL-NEXT: .LBB1_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB1_2 +; AVX512FVL-NEXT: .LBB1_10: # %cond.store1 ; AVX512FVL-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB1_6 -; AVX512FVL-NEXT: .LBB1_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB1_3 +; AVX512FVL-NEXT: .LBB1_11: # %cond.store3 ; AVX512FVL-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB1_8 -; AVX512FVL-NEXT: .LBB1_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB1_4 +; AVX512FVL-NEXT: .LBB1_12: # %cond.store5 ; AVX512FVL-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: je .LBB1_10 -; AVX512FVL-NEXT: .LBB1_9: # %cond.store7 +; AVX512FVL-NEXT: je .LBB1_5 +; AVX512FVL-NEXT: .LBB1_13: # %cond.store7 ; AVX512FVL-NEXT: vpextrw $4, %xmm0, 8(%rdi) ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: je .LBB1_12 -; AVX512FVL-NEXT: .LBB1_11: # %cond.store9 +; AVX512FVL-NEXT: je .LBB1_6 +; AVX512FVL-NEXT: .LBB1_14: # %cond.store9 ; AVX512FVL-NEXT: vpextrw $5, %xmm0, 10(%rdi) ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: je .LBB1_14 -; AVX512FVL-NEXT: .LBB1_13: # %cond.store11 +; AVX512FVL-NEXT: je .LBB1_7 +; AVX512FVL-NEXT: .LBB1_15: # %cond.store11 ; AVX512FVL-NEXT: vpextrw $6, %xmm0, 12(%rdi) ; AVX512FVL-NEXT: testb $-128, %al -; AVX512FVL-NEXT: je .LBB1_16 -; AVX512FVL-NEXT: .LBB1_15: # %cond.store13 +; AVX512FVL-NEXT: je .LBB1_8 +; AVX512FVL-NEXT: .LBB1_16: # %cond.store13 ; AVX512FVL-NEXT: vpextrw $7, %xmm0, 14(%rdi) ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq @@ -916,59 +916,59 @@ define void @truncstore_v8i64_v8i8(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; SSE2-NEXT: notl %eax ; SSE2-NEXT: testb $1, %al ; SSE2-NEXT: movd %xmm1, %ecx -; SSE2-NEXT: jne .LBB2_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB2_12 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne .LBB2_3 -; SSE2-NEXT: .LBB2_4: # %else2 +; SSE2-NEXT: jne .LBB2_13 +; SSE2-NEXT: .LBB2_2: # %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne .LBB2_5 -; SSE2-NEXT: .LBB2_6: # %else4 +; SSE2-NEXT: jne .LBB2_14 +; SSE2-NEXT: .LBB2_3: # %else4 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je .LBB2_8 -; SSE2-NEXT: .LBB2_7: # %cond.store5 +; SSE2-NEXT: je .LBB2_5 +; SSE2-NEXT: .LBB2_4: # %cond.store5 ; SSE2-NEXT: shrl $24, %ecx ; SSE2-NEXT: movb %cl, 3(%rdi) -; SSE2-NEXT: .LBB2_8: # %else6 +; SSE2-NEXT: .LBB2_5: # %else6 ; SSE2-NEXT: testb $16, %al ; SSE2-NEXT: pextrw $2, %xmm1, %ecx -; SSE2-NEXT: je .LBB2_10 -; SSE2-NEXT: # %bb.9: # %cond.store7 +; SSE2-NEXT: je .LBB2_7 +; SSE2-NEXT: # %bb.6: # %cond.store7 ; SSE2-NEXT: movb %cl, 4(%rdi) -; SSE2-NEXT: .LBB2_10: # %else8 +; SSE2-NEXT: .LBB2_7: # %else8 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je .LBB2_12 -; SSE2-NEXT: # %bb.11: # %cond.store9 +; SSE2-NEXT: je .LBB2_9 +; SSE2-NEXT: # %bb.8: # %cond.store9 ; SSE2-NEXT: movb %ch, 5(%rdi) -; SSE2-NEXT: .LBB2_12: # %else10 +; SSE2-NEXT: .LBB2_9: # %else10 ; SSE2-NEXT: testb $64, %al ; SSE2-NEXT: pextrw $3, %xmm1, %ecx -; SSE2-NEXT: jne .LBB2_13 -; SSE2-NEXT: # %bb.14: # %else12 -; SSE2-NEXT: testb $-128, %al ; SSE2-NEXT: jne .LBB2_15 -; SSE2-NEXT: .LBB2_16: # %else14 +; SSE2-NEXT: # %bb.10: # %else12 +; SSE2-NEXT: testb $-128, %al +; SSE2-NEXT: jne .LBB2_16 +; SSE2-NEXT: .LBB2_11: # %else14 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB2_1: # %cond.store +; SSE2-NEXT: .LBB2_12: # %cond.store ; SSE2-NEXT: movb %cl, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB2_4 -; SSE2-NEXT: .LBB2_3: # %cond.store1 +; SSE2-NEXT: je .LBB2_2 +; SSE2-NEXT: .LBB2_13: # %cond.store1 ; SSE2-NEXT: movb %ch, 1(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je .LBB2_6 -; SSE2-NEXT: .LBB2_5: # %cond.store3 +; SSE2-NEXT: je .LBB2_3 +; SSE2-NEXT: .LBB2_14: # %cond.store3 ; SSE2-NEXT: movl %ecx, %edx ; SSE2-NEXT: shrl $16, %edx ; SSE2-NEXT: movb %dl, 2(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne .LBB2_7 -; SSE2-NEXT: jmp .LBB2_8 -; SSE2-NEXT: .LBB2_13: # %cond.store11 +; SSE2-NEXT: jne .LBB2_4 +; SSE2-NEXT: jmp .LBB2_5 +; SSE2-NEXT: .LBB2_15: # %cond.store11 ; SSE2-NEXT: movb %cl, 6(%rdi) ; SSE2-NEXT: testb $-128, %al -; SSE2-NEXT: je .LBB2_16 -; SSE2-NEXT: .LBB2_15: # %cond.store13 +; SSE2-NEXT: je .LBB2_11 +; SSE2-NEXT: .LBB2_16: # %cond.store13 ; SSE2-NEXT: movb %ch, 7(%rdi) ; SSE2-NEXT: retq ; @@ -1012,59 +1012,59 @@ define void @truncstore_v8i64_v8i8(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; SSE4-NEXT: pmovmskb %xmm4, %eax ; SSE4-NEXT: notl %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB2_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB2_9 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB2_3 -; SSE4-NEXT: .LBB2_4: # %else2 +; SSE4-NEXT: jne .LBB2_10 +; SSE4-NEXT: .LBB2_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB2_5 -; SSE4-NEXT: .LBB2_6: # %else4 +; SSE4-NEXT: jne .LBB2_11 +; SSE4-NEXT: .LBB2_3: # %else4 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne .LBB2_7 -; SSE4-NEXT: .LBB2_8: # %else6 +; SSE4-NEXT: jne .LBB2_12 +; SSE4-NEXT: .LBB2_4: # %else6 ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: jne .LBB2_9 -; SSE4-NEXT: .LBB2_10: # %else8 +; SSE4-NEXT: jne .LBB2_13 +; SSE4-NEXT: .LBB2_5: # %else8 ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: jne .LBB2_11 -; SSE4-NEXT: .LBB2_12: # %else10 +; SSE4-NEXT: jne .LBB2_14 +; SSE4-NEXT: .LBB2_6: # %else10 ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: jne .LBB2_13 -; SSE4-NEXT: .LBB2_14: # %else12 -; SSE4-NEXT: testb $-128, %al ; SSE4-NEXT: jne .LBB2_15 -; SSE4-NEXT: .LBB2_16: # %else14 +; SSE4-NEXT: .LBB2_7: # %else12 +; SSE4-NEXT: testb $-128, %al +; SSE4-NEXT: jne .LBB2_16 +; SSE4-NEXT: .LBB2_8: # %else14 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB2_1: # %cond.store +; SSE4-NEXT: .LBB2_9: # %cond.store ; SSE4-NEXT: pextrb $0, %xmm1, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB2_4 -; SSE4-NEXT: .LBB2_3: # %cond.store1 +; SSE4-NEXT: je .LBB2_2 +; SSE4-NEXT: .LBB2_10: # %cond.store1 ; SSE4-NEXT: pextrb $1, %xmm1, 1(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB2_6 -; SSE4-NEXT: .LBB2_5: # %cond.store3 +; SSE4-NEXT: je .LBB2_3 +; SSE4-NEXT: .LBB2_11: # %cond.store3 ; SSE4-NEXT: pextrb $2, %xmm1, 2(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB2_8 -; SSE4-NEXT: .LBB2_7: # %cond.store5 +; SSE4-NEXT: je .LBB2_4 +; SSE4-NEXT: .LBB2_12: # %cond.store5 ; SSE4-NEXT: pextrb $3, %xmm1, 3(%rdi) ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: je .LBB2_10 -; SSE4-NEXT: .LBB2_9: # %cond.store7 +; SSE4-NEXT: je .LBB2_5 +; SSE4-NEXT: .LBB2_13: # %cond.store7 ; SSE4-NEXT: pextrb $4, %xmm1, 4(%rdi) ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: je .LBB2_12 -; SSE4-NEXT: .LBB2_11: # %cond.store9 +; SSE4-NEXT: je .LBB2_6 +; SSE4-NEXT: .LBB2_14: # %cond.store9 ; SSE4-NEXT: pextrb $5, %xmm1, 5(%rdi) ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: je .LBB2_14 -; SSE4-NEXT: .LBB2_13: # %cond.store11 +; SSE4-NEXT: je .LBB2_7 +; SSE4-NEXT: .LBB2_15: # %cond.store11 ; SSE4-NEXT: pextrb $6, %xmm1, 6(%rdi) ; SSE4-NEXT: testb $-128, %al -; SSE4-NEXT: je .LBB2_16 -; SSE4-NEXT: .LBB2_15: # %cond.store13 +; SSE4-NEXT: je .LBB2_8 +; SSE4-NEXT: .LBB2_16: # %cond.store13 ; SSE4-NEXT: pextrb $7, %xmm1, 7(%rdi) ; SSE4-NEXT: retq ; @@ -1102,60 +1102,60 @@ define void @truncstore_v8i64_v8i8(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; AVX1-NEXT: vmovmskps %ymm1, %eax ; AVX1-NEXT: notl %eax ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne .LBB2_1 -; AVX1-NEXT: # %bb.2: # %else +; AVX1-NEXT: jne .LBB2_9 +; AVX1-NEXT: # %bb.1: # %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne .LBB2_3 -; AVX1-NEXT: .LBB2_4: # %else2 +; AVX1-NEXT: jne .LBB2_10 +; AVX1-NEXT: .LBB2_2: # %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne .LBB2_5 -; AVX1-NEXT: .LBB2_6: # %else4 +; AVX1-NEXT: jne .LBB2_11 +; AVX1-NEXT: .LBB2_3: # %else4 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne .LBB2_7 -; AVX1-NEXT: .LBB2_8: # %else6 +; AVX1-NEXT: jne .LBB2_12 +; AVX1-NEXT: .LBB2_4: # %else6 ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: jne .LBB2_9 -; AVX1-NEXT: .LBB2_10: # %else8 +; AVX1-NEXT: jne .LBB2_13 +; AVX1-NEXT: .LBB2_5: # %else8 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: jne .LBB2_11 -; AVX1-NEXT: .LBB2_12: # %else10 +; AVX1-NEXT: jne .LBB2_14 +; AVX1-NEXT: .LBB2_6: # %else10 ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: jne .LBB2_13 -; AVX1-NEXT: .LBB2_14: # %else12 -; AVX1-NEXT: testb $-128, %al ; AVX1-NEXT: jne .LBB2_15 -; AVX1-NEXT: .LBB2_16: # %else14 +; AVX1-NEXT: .LBB2_7: # %else12 +; AVX1-NEXT: testb $-128, %al +; AVX1-NEXT: jne .LBB2_16 +; AVX1-NEXT: .LBB2_8: # %else14 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB2_1: # %cond.store +; AVX1-NEXT: .LBB2_9: # %cond.store ; AVX1-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je .LBB2_4 -; AVX1-NEXT: .LBB2_3: # %cond.store1 +; AVX1-NEXT: je .LBB2_2 +; AVX1-NEXT: .LBB2_10: # %cond.store1 ; AVX1-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je .LBB2_6 -; AVX1-NEXT: .LBB2_5: # %cond.store3 +; AVX1-NEXT: je .LBB2_3 +; AVX1-NEXT: .LBB2_11: # %cond.store3 ; AVX1-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB2_8 -; AVX1-NEXT: .LBB2_7: # %cond.store5 +; AVX1-NEXT: je .LBB2_4 +; AVX1-NEXT: .LBB2_12: # %cond.store5 ; AVX1-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: je .LBB2_10 -; AVX1-NEXT: .LBB2_9: # %cond.store7 +; AVX1-NEXT: je .LBB2_5 +; AVX1-NEXT: .LBB2_13: # %cond.store7 ; AVX1-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je .LBB2_12 -; AVX1-NEXT: .LBB2_11: # %cond.store9 +; AVX1-NEXT: je .LBB2_6 +; AVX1-NEXT: .LBB2_14: # %cond.store9 ; AVX1-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: je .LBB2_14 -; AVX1-NEXT: .LBB2_13: # %cond.store11 +; AVX1-NEXT: je .LBB2_7 +; AVX1-NEXT: .LBB2_15: # %cond.store11 ; AVX1-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX1-NEXT: testb $-128, %al -; AVX1-NEXT: je .LBB2_16 -; AVX1-NEXT: .LBB2_15: # %cond.store13 +; AVX1-NEXT: je .LBB2_8 +; AVX1-NEXT: .LBB2_16: # %cond.store13 ; AVX1-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq @@ -1181,60 +1181,60 @@ define void @truncstore_v8i64_v8i8(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; AVX2-NEXT: vmovmskps %ymm1, %eax ; AVX2-NEXT: notl %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne .LBB2_1 -; AVX2-NEXT: # %bb.2: # %else +; AVX2-NEXT: jne .LBB2_9 +; AVX2-NEXT: # %bb.1: # %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne .LBB2_3 -; AVX2-NEXT: .LBB2_4: # %else2 +; AVX2-NEXT: jne .LBB2_10 +; AVX2-NEXT: .LBB2_2: # %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne .LBB2_5 -; AVX2-NEXT: .LBB2_6: # %else4 +; AVX2-NEXT: jne .LBB2_11 +; AVX2-NEXT: .LBB2_3: # %else4 ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: jne .LBB2_7 -; AVX2-NEXT: .LBB2_8: # %else6 +; AVX2-NEXT: jne .LBB2_12 +; AVX2-NEXT: .LBB2_4: # %else6 ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: jne .LBB2_9 -; AVX2-NEXT: .LBB2_10: # %else8 +; AVX2-NEXT: jne .LBB2_13 +; AVX2-NEXT: .LBB2_5: # %else8 ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: jne .LBB2_11 -; AVX2-NEXT: .LBB2_12: # %else10 +; AVX2-NEXT: jne .LBB2_14 +; AVX2-NEXT: .LBB2_6: # %else10 ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: jne .LBB2_13 -; AVX2-NEXT: .LBB2_14: # %else12 -; AVX2-NEXT: testb $-128, %al ; AVX2-NEXT: jne .LBB2_15 -; AVX2-NEXT: .LBB2_16: # %else14 +; AVX2-NEXT: .LBB2_7: # %else12 +; AVX2-NEXT: testb $-128, %al +; AVX2-NEXT: jne .LBB2_16 +; AVX2-NEXT: .LBB2_8: # %else14 ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; AVX2-NEXT: .LBB2_1: # %cond.store +; AVX2-NEXT: .LBB2_9: # %cond.store ; AVX2-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je .LBB2_4 -; AVX2-NEXT: .LBB2_3: # %cond.store1 +; AVX2-NEXT: je .LBB2_2 +; AVX2-NEXT: .LBB2_10: # %cond.store1 ; AVX2-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je .LBB2_6 -; AVX2-NEXT: .LBB2_5: # %cond.store3 +; AVX2-NEXT: je .LBB2_3 +; AVX2-NEXT: .LBB2_11: # %cond.store3 ; AVX2-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je .LBB2_8 -; AVX2-NEXT: .LBB2_7: # %cond.store5 +; AVX2-NEXT: je .LBB2_4 +; AVX2-NEXT: .LBB2_12: # %cond.store5 ; AVX2-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: je .LBB2_10 -; AVX2-NEXT: .LBB2_9: # %cond.store7 +; AVX2-NEXT: je .LBB2_5 +; AVX2-NEXT: .LBB2_13: # %cond.store7 ; AVX2-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: je .LBB2_12 -; AVX2-NEXT: .LBB2_11: # %cond.store9 +; AVX2-NEXT: je .LBB2_6 +; AVX2-NEXT: .LBB2_14: # %cond.store9 ; AVX2-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: je .LBB2_14 -; AVX2-NEXT: .LBB2_13: # %cond.store11 +; AVX2-NEXT: je .LBB2_7 +; AVX2-NEXT: .LBB2_15: # %cond.store11 ; AVX2-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX2-NEXT: testb $-128, %al -; AVX2-NEXT: je .LBB2_16 -; AVX2-NEXT: .LBB2_15: # %cond.store13 +; AVX2-NEXT: je .LBB2_8 +; AVX2-NEXT: .LBB2_16: # %cond.store13 ; AVX2-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq @@ -1246,60 +1246,60 @@ define void @truncstore_v8i64_v8i8(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; AVX512F-NEXT: vpmovusqb %zmm0, %xmm0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB2_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB2_9 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB2_3 -; AVX512F-NEXT: .LBB2_4: # %else2 +; AVX512F-NEXT: jne .LBB2_10 +; AVX512F-NEXT: .LBB2_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB2_5 -; AVX512F-NEXT: .LBB2_6: # %else4 +; AVX512F-NEXT: jne .LBB2_11 +; AVX512F-NEXT: .LBB2_3: # %else4 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne .LBB2_7 -; AVX512F-NEXT: .LBB2_8: # %else6 +; AVX512F-NEXT: jne .LBB2_12 +; AVX512F-NEXT: .LBB2_4: # %else6 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne .LBB2_9 -; AVX512F-NEXT: .LBB2_10: # %else8 +; AVX512F-NEXT: jne .LBB2_13 +; AVX512F-NEXT: .LBB2_5: # %else8 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne .LBB2_11 -; AVX512F-NEXT: .LBB2_12: # %else10 +; AVX512F-NEXT: jne .LBB2_14 +; AVX512F-NEXT: .LBB2_6: # %else10 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne .LBB2_13 -; AVX512F-NEXT: .LBB2_14: # %else12 -; AVX512F-NEXT: testb $-128, %al ; AVX512F-NEXT: jne .LBB2_15 -; AVX512F-NEXT: .LBB2_16: # %else14 +; AVX512F-NEXT: .LBB2_7: # %else12 +; AVX512F-NEXT: testb $-128, %al +; AVX512F-NEXT: jne .LBB2_16 +; AVX512F-NEXT: .LBB2_8: # %else14 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB2_1: # %cond.store +; AVX512F-NEXT: .LBB2_9: # %cond.store ; AVX512F-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB2_4 -; AVX512F-NEXT: .LBB2_3: # %cond.store1 +; AVX512F-NEXT: je .LBB2_2 +; AVX512F-NEXT: .LBB2_10: # %cond.store1 ; AVX512F-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB2_6 -; AVX512F-NEXT: .LBB2_5: # %cond.store3 +; AVX512F-NEXT: je .LBB2_3 +; AVX512F-NEXT: .LBB2_11: # %cond.store3 ; AVX512F-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB2_8 -; AVX512F-NEXT: .LBB2_7: # %cond.store5 +; AVX512F-NEXT: je .LBB2_4 +; AVX512F-NEXT: .LBB2_12: # %cond.store5 ; AVX512F-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je .LBB2_10 -; AVX512F-NEXT: .LBB2_9: # %cond.store7 +; AVX512F-NEXT: je .LBB2_5 +; AVX512F-NEXT: .LBB2_13: # %cond.store7 ; AVX512F-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je .LBB2_12 -; AVX512F-NEXT: .LBB2_11: # %cond.store9 +; AVX512F-NEXT: je .LBB2_6 +; AVX512F-NEXT: .LBB2_14: # %cond.store9 ; AVX512F-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je .LBB2_14 -; AVX512F-NEXT: .LBB2_13: # %cond.store11 +; AVX512F-NEXT: je .LBB2_7 +; AVX512F-NEXT: .LBB2_15: # %cond.store11 ; AVX512F-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX512F-NEXT: testb $-128, %al -; AVX512F-NEXT: je .LBB2_16 -; AVX512F-NEXT: .LBB2_15: # %cond.store13 +; AVX512F-NEXT: je .LBB2_8 +; AVX512F-NEXT: .LBB2_16: # %cond.store13 ; AVX512F-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -1310,60 +1310,60 @@ define void @truncstore_v8i64_v8i8(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; AVX512FVL-NEXT: vpmovusqb %zmm0, %xmm0 ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB2_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB2_9 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB2_3 -; AVX512FVL-NEXT: .LBB2_4: # %else2 +; AVX512FVL-NEXT: jne .LBB2_10 +; AVX512FVL-NEXT: .LBB2_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB2_5 -; AVX512FVL-NEXT: .LBB2_6: # %else4 +; AVX512FVL-NEXT: jne .LBB2_11 +; AVX512FVL-NEXT: .LBB2_3: # %else4 ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: jne .LBB2_7 -; AVX512FVL-NEXT: .LBB2_8: # %else6 +; AVX512FVL-NEXT: jne .LBB2_12 +; AVX512FVL-NEXT: .LBB2_4: # %else6 ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: jne .LBB2_9 -; AVX512FVL-NEXT: .LBB2_10: # %else8 +; AVX512FVL-NEXT: jne .LBB2_13 +; AVX512FVL-NEXT: .LBB2_5: # %else8 ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: jne .LBB2_11 -; AVX512FVL-NEXT: .LBB2_12: # %else10 +; AVX512FVL-NEXT: jne .LBB2_14 +; AVX512FVL-NEXT: .LBB2_6: # %else10 ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: jne .LBB2_13 -; AVX512FVL-NEXT: .LBB2_14: # %else12 -; AVX512FVL-NEXT: testb $-128, %al ; AVX512FVL-NEXT: jne .LBB2_15 -; AVX512FVL-NEXT: .LBB2_16: # %else14 +; AVX512FVL-NEXT: .LBB2_7: # %else12 +; AVX512FVL-NEXT: testb $-128, %al +; AVX512FVL-NEXT: jne .LBB2_16 +; AVX512FVL-NEXT: .LBB2_8: # %else14 ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB2_1: # %cond.store +; AVX512FVL-NEXT: .LBB2_9: # %cond.store ; AVX512FVL-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB2_4 -; AVX512FVL-NEXT: .LBB2_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB2_2 +; AVX512FVL-NEXT: .LBB2_10: # %cond.store1 ; AVX512FVL-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB2_6 -; AVX512FVL-NEXT: .LBB2_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB2_3 +; AVX512FVL-NEXT: .LBB2_11: # %cond.store3 ; AVX512FVL-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB2_8 -; AVX512FVL-NEXT: .LBB2_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB2_4 +; AVX512FVL-NEXT: .LBB2_12: # %cond.store5 ; AVX512FVL-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: je .LBB2_10 -; AVX512FVL-NEXT: .LBB2_9: # %cond.store7 +; AVX512FVL-NEXT: je .LBB2_5 +; AVX512FVL-NEXT: .LBB2_13: # %cond.store7 ; AVX512FVL-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: je .LBB2_12 -; AVX512FVL-NEXT: .LBB2_11: # %cond.store9 +; AVX512FVL-NEXT: je .LBB2_6 +; AVX512FVL-NEXT: .LBB2_14: # %cond.store9 ; AVX512FVL-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: je .LBB2_14 -; AVX512FVL-NEXT: .LBB2_13: # %cond.store11 +; AVX512FVL-NEXT: je .LBB2_7 +; AVX512FVL-NEXT: .LBB2_15: # %cond.store11 ; AVX512FVL-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX512FVL-NEXT: testb $-128, %al -; AVX512FVL-NEXT: je .LBB2_16 -; AVX512FVL-NEXT: .LBB2_15: # %cond.store13 +; AVX512FVL-NEXT: je .LBB2_8 +; AVX512FVL-NEXT: .LBB2_16: # %cond.store13 ; AVX512FVL-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq @@ -1423,33 +1423,33 @@ define void @truncstore_v4i64_v4i32(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; SSE2-NEXT: movmskps %xmm3, %eax ; SSE2-NEXT: xorl $15, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne .LBB3_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB3_5 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne .LBB3_3 -; SSE2-NEXT: .LBB3_4: # %else2 +; SSE2-NEXT: jne .LBB3_6 +; SSE2-NEXT: .LBB3_2: # %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne .LBB3_5 -; SSE2-NEXT: .LBB3_6: # %else4 -; SSE2-NEXT: testb $8, %al ; SSE2-NEXT: jne .LBB3_7 -; SSE2-NEXT: .LBB3_8: # %else6 +; SSE2-NEXT: .LBB3_3: # %else4 +; SSE2-NEXT: testb $8, %al +; SSE2-NEXT: jne .LBB3_8 +; SSE2-NEXT: .LBB3_4: # %else6 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB3_1: # %cond.store +; SSE2-NEXT: .LBB3_5: # %cond.store ; SSE2-NEXT: movss %xmm1, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB3_4 -; SSE2-NEXT: .LBB3_3: # %cond.store1 +; SSE2-NEXT: je .LBB3_2 +; SSE2-NEXT: .LBB3_6: # %cond.store1 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1] ; SSE2-NEXT: movd %xmm0, 4(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je .LBB3_6 -; SSE2-NEXT: .LBB3_5: # %cond.store3 +; SSE2-NEXT: je .LBB3_3 +; SSE2-NEXT: .LBB3_7: # %cond.store3 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3] ; SSE2-NEXT: movd %xmm0, 8(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je .LBB3_8 -; SSE2-NEXT: .LBB3_7: # %cond.store5 +; SSE2-NEXT: je .LBB3_4 +; SSE2-NEXT: .LBB3_8: # %cond.store5 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[3,3,3,3] ; SSE2-NEXT: movd %xmm0, 12(%rdi) ; SSE2-NEXT: retq @@ -1476,31 +1476,31 @@ define void @truncstore_v4i64_v4i32(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; SSE4-NEXT: movmskps %xmm6, %eax ; SSE4-NEXT: xorl $15, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB3_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB3_5 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB3_3 -; SSE4-NEXT: .LBB3_4: # %else2 +; SSE4-NEXT: jne .LBB3_6 +; SSE4-NEXT: .LBB3_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB3_5 -; SSE4-NEXT: .LBB3_6: # %else4 -; SSE4-NEXT: testb $8, %al ; SSE4-NEXT: jne .LBB3_7 -; SSE4-NEXT: .LBB3_8: # %else6 +; SSE4-NEXT: .LBB3_3: # %else4 +; SSE4-NEXT: testb $8, %al +; SSE4-NEXT: jne .LBB3_8 +; SSE4-NEXT: .LBB3_4: # %else6 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB3_1: # %cond.store +; SSE4-NEXT: .LBB3_5: # %cond.store ; SSE4-NEXT: movss %xmm5, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB3_4 -; SSE4-NEXT: .LBB3_3: # %cond.store1 +; SSE4-NEXT: je .LBB3_2 +; SSE4-NEXT: .LBB3_6: # %cond.store1 ; SSE4-NEXT: extractps $1, %xmm5, 4(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB3_6 -; SSE4-NEXT: .LBB3_5: # %cond.store3 +; SSE4-NEXT: je .LBB3_3 +; SSE4-NEXT: .LBB3_7: # %cond.store3 ; SSE4-NEXT: extractps $2, %xmm5, 8(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB3_8 -; SSE4-NEXT: .LBB3_7: # %cond.store5 +; SSE4-NEXT: je .LBB3_4 +; SSE4-NEXT: .LBB3_8: # %cond.store5 ; SSE4-NEXT: extractps $3, %xmm5, 12(%rdi) ; SSE4-NEXT: retq ; @@ -1616,34 +1616,34 @@ define void @truncstore_v4i64_v4i16(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; SSE2-NEXT: movmskps %xmm2, %eax ; SSE2-NEXT: xorl $15, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne .LBB4_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB4_5 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne .LBB4_3 -; SSE2-NEXT: .LBB4_4: # %else2 +; SSE2-NEXT: jne .LBB4_6 +; SSE2-NEXT: .LBB4_2: # %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne .LBB4_5 -; SSE2-NEXT: .LBB4_6: # %else4 -; SSE2-NEXT: testb $8, %al ; SSE2-NEXT: jne .LBB4_7 -; SSE2-NEXT: .LBB4_8: # %else6 +; SSE2-NEXT: .LBB4_3: # %else4 +; SSE2-NEXT: testb $8, %al +; SSE2-NEXT: jne .LBB4_8 +; SSE2-NEXT: .LBB4_4: # %else6 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB4_1: # %cond.store +; SSE2-NEXT: .LBB4_5: # %cond.store ; SSE2-NEXT: movd %xmm1, %ecx ; SSE2-NEXT: movw %cx, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB4_4 -; SSE2-NEXT: .LBB4_3: # %cond.store1 +; SSE2-NEXT: je .LBB4_2 +; SSE2-NEXT: .LBB4_6: # %cond.store1 ; SSE2-NEXT: pextrw $1, %xmm1, %ecx ; SSE2-NEXT: movw %cx, 2(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je .LBB4_6 -; SSE2-NEXT: .LBB4_5: # %cond.store3 +; SSE2-NEXT: je .LBB4_3 +; SSE2-NEXT: .LBB4_7: # %cond.store3 ; SSE2-NEXT: pextrw $2, %xmm1, %ecx ; SSE2-NEXT: movw %cx, 4(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je .LBB4_8 -; SSE2-NEXT: .LBB4_7: # %cond.store5 +; SSE2-NEXT: je .LBB4_4 +; SSE2-NEXT: .LBB4_8: # %cond.store5 ; SSE2-NEXT: pextrw $3, %xmm1, %eax ; SSE2-NEXT: movw %ax, 6(%rdi) ; SSE2-NEXT: retq @@ -1671,31 +1671,31 @@ define void @truncstore_v4i64_v4i16(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; SSE4-NEXT: movmskps %xmm6, %eax ; SSE4-NEXT: xorl $15, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB4_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB4_5 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB4_3 -; SSE4-NEXT: .LBB4_4: # %else2 +; SSE4-NEXT: jne .LBB4_6 +; SSE4-NEXT: .LBB4_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB4_5 -; SSE4-NEXT: .LBB4_6: # %else4 -; SSE4-NEXT: testb $8, %al ; SSE4-NEXT: jne .LBB4_7 -; SSE4-NEXT: .LBB4_8: # %else6 +; SSE4-NEXT: .LBB4_3: # %else4 +; SSE4-NEXT: testb $8, %al +; SSE4-NEXT: jne .LBB4_8 +; SSE4-NEXT: .LBB4_4: # %else6 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB4_1: # %cond.store +; SSE4-NEXT: .LBB4_5: # %cond.store ; SSE4-NEXT: pextrw $0, %xmm5, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB4_4 -; SSE4-NEXT: .LBB4_3: # %cond.store1 +; SSE4-NEXT: je .LBB4_2 +; SSE4-NEXT: .LBB4_6: # %cond.store1 ; SSE4-NEXT: pextrw $1, %xmm5, 2(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB4_6 -; SSE4-NEXT: .LBB4_5: # %cond.store3 +; SSE4-NEXT: je .LBB4_3 +; SSE4-NEXT: .LBB4_7: # %cond.store3 ; SSE4-NEXT: pextrw $2, %xmm5, 4(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB4_8 -; SSE4-NEXT: .LBB4_7: # %cond.store5 +; SSE4-NEXT: je .LBB4_4 +; SSE4-NEXT: .LBB4_8: # %cond.store5 ; SSE4-NEXT: pextrw $3, %xmm5, 6(%rdi) ; SSE4-NEXT: retq ; @@ -1721,32 +1721,32 @@ define void @truncstore_v4i64_v4i16(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; AVX1-NEXT: vmovmskps %xmm1, %eax ; AVX1-NEXT: xorl $15, %eax ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne .LBB4_1 -; AVX1-NEXT: # %bb.2: # %else +; AVX1-NEXT: jne .LBB4_5 +; AVX1-NEXT: # %bb.1: # %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne .LBB4_3 -; AVX1-NEXT: .LBB4_4: # %else2 +; AVX1-NEXT: jne .LBB4_6 +; AVX1-NEXT: .LBB4_2: # %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne .LBB4_5 -; AVX1-NEXT: .LBB4_6: # %else4 -; AVX1-NEXT: testb $8, %al ; AVX1-NEXT: jne .LBB4_7 -; AVX1-NEXT: .LBB4_8: # %else6 +; AVX1-NEXT: .LBB4_3: # %else4 +; AVX1-NEXT: testb $8, %al +; AVX1-NEXT: jne .LBB4_8 +; AVX1-NEXT: .LBB4_4: # %else6 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB4_1: # %cond.store +; AVX1-NEXT: .LBB4_5: # %cond.store ; AVX1-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je .LBB4_4 -; AVX1-NEXT: .LBB4_3: # %cond.store1 +; AVX1-NEXT: je .LBB4_2 +; AVX1-NEXT: .LBB4_6: # %cond.store1 ; AVX1-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je .LBB4_6 -; AVX1-NEXT: .LBB4_5: # %cond.store3 +; AVX1-NEXT: je .LBB4_3 +; AVX1-NEXT: .LBB4_7: # %cond.store3 ; AVX1-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB4_8 -; AVX1-NEXT: .LBB4_7: # %cond.store5 +; AVX1-NEXT: je .LBB4_4 +; AVX1-NEXT: .LBB4_8: # %cond.store5 ; AVX1-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq @@ -1767,32 +1767,32 @@ define void @truncstore_v4i64_v4i16(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; AVX2-NEXT: vmovmskps %xmm1, %eax ; AVX2-NEXT: xorl $15, %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne .LBB4_1 -; AVX2-NEXT: # %bb.2: # %else +; AVX2-NEXT: jne .LBB4_5 +; AVX2-NEXT: # %bb.1: # %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne .LBB4_3 -; AVX2-NEXT: .LBB4_4: # %else2 +; AVX2-NEXT: jne .LBB4_6 +; AVX2-NEXT: .LBB4_2: # %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne .LBB4_5 -; AVX2-NEXT: .LBB4_6: # %else4 -; AVX2-NEXT: testb $8, %al ; AVX2-NEXT: jne .LBB4_7 -; AVX2-NEXT: .LBB4_8: # %else6 +; AVX2-NEXT: .LBB4_3: # %else4 +; AVX2-NEXT: testb $8, %al +; AVX2-NEXT: jne .LBB4_8 +; AVX2-NEXT: .LBB4_4: # %else6 ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; AVX2-NEXT: .LBB4_1: # %cond.store +; AVX2-NEXT: .LBB4_5: # %cond.store ; AVX2-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je .LBB4_4 -; AVX2-NEXT: .LBB4_3: # %cond.store1 +; AVX2-NEXT: je .LBB4_2 +; AVX2-NEXT: .LBB4_6: # %cond.store1 ; AVX2-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je .LBB4_6 -; AVX2-NEXT: .LBB4_5: # %cond.store3 +; AVX2-NEXT: je .LBB4_3 +; AVX2-NEXT: .LBB4_7: # %cond.store3 ; AVX2-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je .LBB4_8 -; AVX2-NEXT: .LBB4_7: # %cond.store5 +; AVX2-NEXT: je .LBB4_4 +; AVX2-NEXT: .LBB4_8: # %cond.store5 ; AVX2-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq @@ -1805,32 +1805,32 @@ define void @truncstore_v4i64_v4i16(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; AVX512F-NEXT: vpmovusqw %zmm0, %xmm0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB4_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB4_5 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB4_3 -; AVX512F-NEXT: .LBB4_4: # %else2 +; AVX512F-NEXT: jne .LBB4_6 +; AVX512F-NEXT: .LBB4_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB4_5 -; AVX512F-NEXT: .LBB4_6: # %else4 -; AVX512F-NEXT: testb $8, %al ; AVX512F-NEXT: jne .LBB4_7 -; AVX512F-NEXT: .LBB4_8: # %else6 +; AVX512F-NEXT: .LBB4_3: # %else4 +; AVX512F-NEXT: testb $8, %al +; AVX512F-NEXT: jne .LBB4_8 +; AVX512F-NEXT: .LBB4_4: # %else6 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB4_1: # %cond.store +; AVX512F-NEXT: .LBB4_5: # %cond.store ; AVX512F-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB4_4 -; AVX512F-NEXT: .LBB4_3: # %cond.store1 +; AVX512F-NEXT: je .LBB4_2 +; AVX512F-NEXT: .LBB4_6: # %cond.store1 ; AVX512F-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB4_6 -; AVX512F-NEXT: .LBB4_5: # %cond.store3 +; AVX512F-NEXT: je .LBB4_3 +; AVX512F-NEXT: .LBB4_7: # %cond.store3 ; AVX512F-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB4_8 -; AVX512F-NEXT: .LBB4_7: # %cond.store5 +; AVX512F-NEXT: je .LBB4_4 +; AVX512F-NEXT: .LBB4_8: # %cond.store5 ; AVX512F-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -1841,32 +1841,32 @@ define void @truncstore_v4i64_v4i16(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; AVX512FVL-NEXT: vpmovusqw %ymm0, %xmm0 ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB4_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB4_5 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB4_3 -; AVX512FVL-NEXT: .LBB4_4: # %else2 +; AVX512FVL-NEXT: jne .LBB4_6 +; AVX512FVL-NEXT: .LBB4_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB4_5 -; AVX512FVL-NEXT: .LBB4_6: # %else4 -; AVX512FVL-NEXT: testb $8, %al ; AVX512FVL-NEXT: jne .LBB4_7 -; AVX512FVL-NEXT: .LBB4_8: # %else6 +; AVX512FVL-NEXT: .LBB4_3: # %else4 +; AVX512FVL-NEXT: testb $8, %al +; AVX512FVL-NEXT: jne .LBB4_8 +; AVX512FVL-NEXT: .LBB4_4: # %else6 ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB4_1: # %cond.store +; AVX512FVL-NEXT: .LBB4_5: # %cond.store ; AVX512FVL-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB4_4 -; AVX512FVL-NEXT: .LBB4_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB4_2 +; AVX512FVL-NEXT: .LBB4_6: # %cond.store1 ; AVX512FVL-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB4_6 -; AVX512FVL-NEXT: .LBB4_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB4_3 +; AVX512FVL-NEXT: .LBB4_7: # %cond.store3 ; AVX512FVL-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB4_8 -; AVX512FVL-NEXT: .LBB4_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB4_4 +; AVX512FVL-NEXT: .LBB4_8: # %cond.store5 ; AVX512FVL-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq @@ -1933,33 +1933,33 @@ define void @truncstore_v4i64_v4i8(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; SSE2-NEXT: xorl $15, %ecx ; SSE2-NEXT: testb $1, %cl ; SSE2-NEXT: movd %xmm1, %eax -; SSE2-NEXT: jne .LBB5_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB5_5 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %cl -; SSE2-NEXT: jne .LBB5_3 -; SSE2-NEXT: .LBB5_4: # %else2 +; SSE2-NEXT: jne .LBB5_6 +; SSE2-NEXT: .LBB5_2: # %else2 ; SSE2-NEXT: testb $4, %cl -; SSE2-NEXT: jne .LBB5_5 -; SSE2-NEXT: .LBB5_6: # %else4 -; SSE2-NEXT: testb $8, %cl ; SSE2-NEXT: jne .LBB5_7 -; SSE2-NEXT: .LBB5_8: # %else6 +; SSE2-NEXT: .LBB5_3: # %else4 +; SSE2-NEXT: testb $8, %cl +; SSE2-NEXT: jne .LBB5_8 +; SSE2-NEXT: .LBB5_4: # %else6 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB5_1: # %cond.store +; SSE2-NEXT: .LBB5_5: # %cond.store ; SSE2-NEXT: movb %al, (%rdi) ; SSE2-NEXT: testb $2, %cl -; SSE2-NEXT: je .LBB5_4 -; SSE2-NEXT: .LBB5_3: # %cond.store1 +; SSE2-NEXT: je .LBB5_2 +; SSE2-NEXT: .LBB5_6: # %cond.store1 ; SSE2-NEXT: movb %ah, 1(%rdi) ; SSE2-NEXT: testb $4, %cl -; SSE2-NEXT: je .LBB5_6 -; SSE2-NEXT: .LBB5_5: # %cond.store3 +; SSE2-NEXT: je .LBB5_3 +; SSE2-NEXT: .LBB5_7: # %cond.store3 ; SSE2-NEXT: movl %eax, %edx ; SSE2-NEXT: shrl $16, %edx ; SSE2-NEXT: movb %dl, 2(%rdi) ; SSE2-NEXT: testb $8, %cl -; SSE2-NEXT: je .LBB5_8 -; SSE2-NEXT: .LBB5_7: # %cond.store5 +; SSE2-NEXT: je .LBB5_4 +; SSE2-NEXT: .LBB5_8: # %cond.store5 ; SSE2-NEXT: shrl $24, %eax ; SSE2-NEXT: movb %al, 3(%rdi) ; SSE2-NEXT: retq @@ -1988,31 +1988,31 @@ define void @truncstore_v4i64_v4i8(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; SSE4-NEXT: movmskps %xmm6, %eax ; SSE4-NEXT: xorl $15, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB5_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB5_5 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB5_3 -; SSE4-NEXT: .LBB5_4: # %else2 +; SSE4-NEXT: jne .LBB5_6 +; SSE4-NEXT: .LBB5_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB5_5 -; SSE4-NEXT: .LBB5_6: # %else4 -; SSE4-NEXT: testb $8, %al ; SSE4-NEXT: jne .LBB5_7 -; SSE4-NEXT: .LBB5_8: # %else6 +; SSE4-NEXT: .LBB5_3: # %else4 +; SSE4-NEXT: testb $8, %al +; SSE4-NEXT: jne .LBB5_8 +; SSE4-NEXT: .LBB5_4: # %else6 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB5_1: # %cond.store +; SSE4-NEXT: .LBB5_5: # %cond.store ; SSE4-NEXT: pextrb $0, %xmm5, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB5_4 -; SSE4-NEXT: .LBB5_3: # %cond.store1 +; SSE4-NEXT: je .LBB5_2 +; SSE4-NEXT: .LBB5_6: # %cond.store1 ; SSE4-NEXT: pextrb $1, %xmm5, 1(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB5_6 -; SSE4-NEXT: .LBB5_5: # %cond.store3 +; SSE4-NEXT: je .LBB5_3 +; SSE4-NEXT: .LBB5_7: # %cond.store3 ; SSE4-NEXT: pextrb $2, %xmm5, 2(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB5_8 -; SSE4-NEXT: .LBB5_7: # %cond.store5 +; SSE4-NEXT: je .LBB5_4 +; SSE4-NEXT: .LBB5_8: # %cond.store5 ; SSE4-NEXT: pextrb $3, %xmm5, 3(%rdi) ; SSE4-NEXT: retq ; @@ -2039,32 +2039,32 @@ define void @truncstore_v4i64_v4i8(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; AVX1-NEXT: vmovmskps %xmm1, %eax ; AVX1-NEXT: xorl $15, %eax ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne .LBB5_1 -; AVX1-NEXT: # %bb.2: # %else +; AVX1-NEXT: jne .LBB5_5 +; AVX1-NEXT: # %bb.1: # %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne .LBB5_3 -; AVX1-NEXT: .LBB5_4: # %else2 +; AVX1-NEXT: jne .LBB5_6 +; AVX1-NEXT: .LBB5_2: # %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne .LBB5_5 -; AVX1-NEXT: .LBB5_6: # %else4 -; AVX1-NEXT: testb $8, %al ; AVX1-NEXT: jne .LBB5_7 -; AVX1-NEXT: .LBB5_8: # %else6 +; AVX1-NEXT: .LBB5_3: # %else4 +; AVX1-NEXT: testb $8, %al +; AVX1-NEXT: jne .LBB5_8 +; AVX1-NEXT: .LBB5_4: # %else6 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB5_1: # %cond.store +; AVX1-NEXT: .LBB5_5: # %cond.store ; AVX1-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je .LBB5_4 -; AVX1-NEXT: .LBB5_3: # %cond.store1 +; AVX1-NEXT: je .LBB5_2 +; AVX1-NEXT: .LBB5_6: # %cond.store1 ; AVX1-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je .LBB5_6 -; AVX1-NEXT: .LBB5_5: # %cond.store3 +; AVX1-NEXT: je .LBB5_3 +; AVX1-NEXT: .LBB5_7: # %cond.store3 ; AVX1-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB5_8 -; AVX1-NEXT: .LBB5_7: # %cond.store5 +; AVX1-NEXT: je .LBB5_4 +; AVX1-NEXT: .LBB5_8: # %cond.store5 ; AVX1-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq @@ -2086,32 +2086,32 @@ define void @truncstore_v4i64_v4i8(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; AVX2-NEXT: vmovmskps %xmm1, %eax ; AVX2-NEXT: xorl $15, %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne .LBB5_1 -; AVX2-NEXT: # %bb.2: # %else +; AVX2-NEXT: jne .LBB5_5 +; AVX2-NEXT: # %bb.1: # %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne .LBB5_3 -; AVX2-NEXT: .LBB5_4: # %else2 +; AVX2-NEXT: jne .LBB5_6 +; AVX2-NEXT: .LBB5_2: # %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne .LBB5_5 -; AVX2-NEXT: .LBB5_6: # %else4 -; AVX2-NEXT: testb $8, %al ; AVX2-NEXT: jne .LBB5_7 -; AVX2-NEXT: .LBB5_8: # %else6 +; AVX2-NEXT: .LBB5_3: # %else4 +; AVX2-NEXT: testb $8, %al +; AVX2-NEXT: jne .LBB5_8 +; AVX2-NEXT: .LBB5_4: # %else6 ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; AVX2-NEXT: .LBB5_1: # %cond.store +; AVX2-NEXT: .LBB5_5: # %cond.store ; AVX2-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je .LBB5_4 -; AVX2-NEXT: .LBB5_3: # %cond.store1 +; AVX2-NEXT: je .LBB5_2 +; AVX2-NEXT: .LBB5_6: # %cond.store1 ; AVX2-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je .LBB5_6 -; AVX2-NEXT: .LBB5_5: # %cond.store3 +; AVX2-NEXT: je .LBB5_3 +; AVX2-NEXT: .LBB5_7: # %cond.store3 ; AVX2-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je .LBB5_8 -; AVX2-NEXT: .LBB5_7: # %cond.store5 +; AVX2-NEXT: je .LBB5_4 +; AVX2-NEXT: .LBB5_8: # %cond.store5 ; AVX2-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq @@ -2124,32 +2124,32 @@ define void @truncstore_v4i64_v4i8(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; AVX512F-NEXT: vpmovusqb %zmm0, %xmm0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB5_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB5_5 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB5_3 -; AVX512F-NEXT: .LBB5_4: # %else2 +; AVX512F-NEXT: jne .LBB5_6 +; AVX512F-NEXT: .LBB5_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB5_5 -; AVX512F-NEXT: .LBB5_6: # %else4 -; AVX512F-NEXT: testb $8, %al ; AVX512F-NEXT: jne .LBB5_7 -; AVX512F-NEXT: .LBB5_8: # %else6 +; AVX512F-NEXT: .LBB5_3: # %else4 +; AVX512F-NEXT: testb $8, %al +; AVX512F-NEXT: jne .LBB5_8 +; AVX512F-NEXT: .LBB5_4: # %else6 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB5_1: # %cond.store +; AVX512F-NEXT: .LBB5_5: # %cond.store ; AVX512F-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB5_4 -; AVX512F-NEXT: .LBB5_3: # %cond.store1 +; AVX512F-NEXT: je .LBB5_2 +; AVX512F-NEXT: .LBB5_6: # %cond.store1 ; AVX512F-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB5_6 -; AVX512F-NEXT: .LBB5_5: # %cond.store3 +; AVX512F-NEXT: je .LBB5_3 +; AVX512F-NEXT: .LBB5_7: # %cond.store3 ; AVX512F-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB5_8 -; AVX512F-NEXT: .LBB5_7: # %cond.store5 +; AVX512F-NEXT: je .LBB5_4 +; AVX512F-NEXT: .LBB5_8: # %cond.store5 ; AVX512F-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -2160,32 +2160,32 @@ define void @truncstore_v4i64_v4i8(<4 x i64> %x, ptr %p, <4 x i32> %mask) { ; AVX512FVL-NEXT: vpmovusqb %ymm0, %xmm0 ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB5_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB5_5 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB5_3 -; AVX512FVL-NEXT: .LBB5_4: # %else2 +; AVX512FVL-NEXT: jne .LBB5_6 +; AVX512FVL-NEXT: .LBB5_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB5_5 -; AVX512FVL-NEXT: .LBB5_6: # %else4 -; AVX512FVL-NEXT: testb $8, %al ; AVX512FVL-NEXT: jne .LBB5_7 -; AVX512FVL-NEXT: .LBB5_8: # %else6 +; AVX512FVL-NEXT: .LBB5_3: # %else4 +; AVX512FVL-NEXT: testb $8, %al +; AVX512FVL-NEXT: jne .LBB5_8 +; AVX512FVL-NEXT: .LBB5_4: # %else6 ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB5_1: # %cond.store +; AVX512FVL-NEXT: .LBB5_5: # %cond.store ; AVX512FVL-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB5_4 -; AVX512FVL-NEXT: .LBB5_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB5_2 +; AVX512FVL-NEXT: .LBB5_6: # %cond.store1 ; AVX512FVL-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB5_6 -; AVX512FVL-NEXT: .LBB5_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB5_3 +; AVX512FVL-NEXT: .LBB5_7: # %cond.store3 ; AVX512FVL-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB5_8 -; AVX512FVL-NEXT: .LBB5_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB5_4 +; AVX512FVL-NEXT: .LBB5_8: # %cond.store5 ; AVX512FVL-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq @@ -2238,17 +2238,17 @@ define void @truncstore_v2i64_v2i32(<2 x i64> %x, ptr %p, <2 x i64> %mask) { ; SSE2-NEXT: movmskpd %xmm1, %eax ; SSE2-NEXT: xorl $3, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne .LBB6_1 -; SSE2-NEXT: # %bb.2: # %else -; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: jne .LBB6_3 -; SSE2-NEXT: .LBB6_4: # %else2 +; SSE2-NEXT: # %bb.1: # %else +; SSE2-NEXT: testb $2, %al +; SSE2-NEXT: jne .LBB6_4 +; SSE2-NEXT: .LBB6_2: # %else2 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB6_1: # %cond.store +; SSE2-NEXT: .LBB6_3: # %cond.store ; SSE2-NEXT: movd %xmm0, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB6_4 -; SSE2-NEXT: .LBB6_3: # %cond.store1 +; SSE2-NEXT: je .LBB6_2 +; SSE2-NEXT: .LBB6_4: # %cond.store1 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1] ; SSE2-NEXT: movd %xmm0, 4(%rdi) ; SSE2-NEXT: retq @@ -2266,17 +2266,17 @@ define void @truncstore_v2i64_v2i32(<2 x i64> %x, ptr %p, <2 x i64> %mask) { ; SSE4-NEXT: movmskpd %xmm3, %eax ; SSE4-NEXT: xorl $3, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB6_1 -; SSE4-NEXT: # %bb.2: # %else -; SSE4-NEXT: testb $2, %al ; SSE4-NEXT: jne .LBB6_3 -; SSE4-NEXT: .LBB6_4: # %else2 +; SSE4-NEXT: # %bb.1: # %else +; SSE4-NEXT: testb $2, %al +; SSE4-NEXT: jne .LBB6_4 +; SSE4-NEXT: .LBB6_2: # %else2 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB6_1: # %cond.store +; SSE4-NEXT: .LBB6_3: # %cond.store ; SSE4-NEXT: movd %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB6_4 -; SSE4-NEXT: .LBB6_3: # %cond.store1 +; SSE4-NEXT: je .LBB6_2 +; SSE4-NEXT: .LBB6_4: # %cond.store1 ; SSE4-NEXT: pextrd $1, %xmm0, 4(%rdi) ; SSE4-NEXT: retq ; @@ -2363,18 +2363,18 @@ define void @truncstore_v2i64_v2i16(<2 x i64> %x, ptr %p, <2 x i64> %mask) { ; SSE2-NEXT: movmskpd %xmm1, %eax ; SSE2-NEXT: xorl $3, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne .LBB7_1 -; SSE2-NEXT: # %bb.2: # %else -; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: jne .LBB7_3 -; SSE2-NEXT: .LBB7_4: # %else2 +; SSE2-NEXT: # %bb.1: # %else +; SSE2-NEXT: testb $2, %al +; SSE2-NEXT: jne .LBB7_4 +; SSE2-NEXT: .LBB7_2: # %else2 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB7_1: # %cond.store +; SSE2-NEXT: .LBB7_3: # %cond.store ; SSE2-NEXT: movd %xmm0, %ecx ; SSE2-NEXT: movw %cx, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB7_4 -; SSE2-NEXT: .LBB7_3: # %cond.store1 +; SSE2-NEXT: je .LBB7_2 +; SSE2-NEXT: .LBB7_4: # %cond.store1 ; SSE2-NEXT: pextrw $1, %xmm0, %eax ; SSE2-NEXT: movw %ax, 2(%rdi) ; SSE2-NEXT: retq @@ -2393,17 +2393,17 @@ define void @truncstore_v2i64_v2i16(<2 x i64> %x, ptr %p, <2 x i64> %mask) { ; SSE4-NEXT: movmskpd %xmm3, %eax ; SSE4-NEXT: xorl $3, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB7_1 -; SSE4-NEXT: # %bb.2: # %else -; SSE4-NEXT: testb $2, %al ; SSE4-NEXT: jne .LBB7_3 -; SSE4-NEXT: .LBB7_4: # %else2 +; SSE4-NEXT: # %bb.1: # %else +; SSE4-NEXT: testb $2, %al +; SSE4-NEXT: jne .LBB7_4 +; SSE4-NEXT: .LBB7_2: # %else2 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB7_1: # %cond.store +; SSE4-NEXT: .LBB7_3: # %cond.store ; SSE4-NEXT: pextrw $0, %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB7_4 -; SSE4-NEXT: .LBB7_3: # %cond.store1 +; SSE4-NEXT: je .LBB7_2 +; SSE4-NEXT: .LBB7_4: # %cond.store1 ; SSE4-NEXT: pextrw $1, %xmm0, 2(%rdi) ; SSE4-NEXT: retq ; @@ -2419,17 +2419,17 @@ define void @truncstore_v2i64_v2i16(<2 x i64> %x, ptr %p, <2 x i64> %mask) { ; AVX-NEXT: vmovmskpd %xmm1, %eax ; AVX-NEXT: xorl $3, %eax ; AVX-NEXT: testb $1, %al -; AVX-NEXT: jne .LBB7_1 -; AVX-NEXT: # %bb.2: # %else -; AVX-NEXT: testb $2, %al ; AVX-NEXT: jne .LBB7_3 -; AVX-NEXT: .LBB7_4: # %else2 +; AVX-NEXT: # %bb.1: # %else +; AVX-NEXT: testb $2, %al +; AVX-NEXT: jne .LBB7_4 +; AVX-NEXT: .LBB7_2: # %else2 ; AVX-NEXT: retq -; AVX-NEXT: .LBB7_1: # %cond.store +; AVX-NEXT: .LBB7_3: # %cond.store ; AVX-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX-NEXT: testb $2, %al -; AVX-NEXT: je .LBB7_4 -; AVX-NEXT: .LBB7_3: # %cond.store1 +; AVX-NEXT: je .LBB7_2 +; AVX-NEXT: .LBB7_4: # %cond.store1 ; AVX-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX-NEXT: retq ; @@ -2441,18 +2441,18 @@ define void @truncstore_v2i64_v2i16(<2 x i64> %x, ptr %p, <2 x i64> %mask) { ; AVX512F-NEXT: vpmovusqw %zmm0, %xmm0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB7_1 -; AVX512F-NEXT: # %bb.2: # %else -; AVX512F-NEXT: testb $2, %al ; AVX512F-NEXT: jne .LBB7_3 -; AVX512F-NEXT: .LBB7_4: # %else2 +; AVX512F-NEXT: # %bb.1: # %else +; AVX512F-NEXT: testb $2, %al +; AVX512F-NEXT: jne .LBB7_4 +; AVX512F-NEXT: .LBB7_2: # %else2 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB7_1: # %cond.store +; AVX512F-NEXT: .LBB7_3: # %cond.store ; AVX512F-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB7_4 -; AVX512F-NEXT: .LBB7_3: # %cond.store1 +; AVX512F-NEXT: je .LBB7_2 +; AVX512F-NEXT: .LBB7_4: # %cond.store1 ; AVX512F-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -2463,17 +2463,17 @@ define void @truncstore_v2i64_v2i16(<2 x i64> %x, ptr %p, <2 x i64> %mask) { ; AVX512FVL-NEXT: vpmovusqw %xmm0, %xmm0 ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB7_1 -; AVX512FVL-NEXT: # %bb.2: # %else -; AVX512FVL-NEXT: testb $2, %al ; AVX512FVL-NEXT: jne .LBB7_3 -; AVX512FVL-NEXT: .LBB7_4: # %else2 +; AVX512FVL-NEXT: # %bb.1: # %else +; AVX512FVL-NEXT: testb $2, %al +; AVX512FVL-NEXT: jne .LBB7_4 +; AVX512FVL-NEXT: .LBB7_2: # %else2 ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB7_1: # %cond.store +; AVX512FVL-NEXT: .LBB7_3: # %cond.store ; AVX512FVL-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB7_4 -; AVX512FVL-NEXT: .LBB7_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB7_2 +; AVX512FVL-NEXT: .LBB7_4: # %cond.store1 ; AVX512FVL-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: retq ; @@ -2526,17 +2526,17 @@ define void @truncstore_v2i64_v2i8(<2 x i64> %x, ptr %p, <2 x i64> %mask) { ; SSE2-NEXT: xorl $3, %eax ; SSE2-NEXT: testb $1, %al ; SSE2-NEXT: movd %xmm3, %ecx -; SSE2-NEXT: jne .LBB8_1 -; SSE2-NEXT: # %bb.2: # %else -; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: jne .LBB8_3 -; SSE2-NEXT: .LBB8_4: # %else2 +; SSE2-NEXT: # %bb.1: # %else +; SSE2-NEXT: testb $2, %al +; SSE2-NEXT: jne .LBB8_4 +; SSE2-NEXT: .LBB8_2: # %else2 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB8_1: # %cond.store +; SSE2-NEXT: .LBB8_3: # %cond.store ; SSE2-NEXT: movb %cl, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB8_4 -; SSE2-NEXT: .LBB8_3: # %cond.store1 +; SSE2-NEXT: je .LBB8_2 +; SSE2-NEXT: .LBB8_4: # %cond.store1 ; SSE2-NEXT: movb %ch, 1(%rdi) ; SSE2-NEXT: retq ; @@ -2553,17 +2553,17 @@ define void @truncstore_v2i64_v2i8(<2 x i64> %x, ptr %p, <2 x i64> %mask) { ; SSE4-NEXT: movmskpd %xmm3, %eax ; SSE4-NEXT: xorl $3, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB8_1 -; SSE4-NEXT: # %bb.2: # %else -; SSE4-NEXT: testb $2, %al ; SSE4-NEXT: jne .LBB8_3 -; SSE4-NEXT: .LBB8_4: # %else2 +; SSE4-NEXT: # %bb.1: # %else +; SSE4-NEXT: testb $2, %al +; SSE4-NEXT: jne .LBB8_4 +; SSE4-NEXT: .LBB8_2: # %else2 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB8_1: # %cond.store +; SSE4-NEXT: .LBB8_3: # %cond.store ; SSE4-NEXT: pextrb $0, %xmm2, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB8_4 -; SSE4-NEXT: .LBB8_3: # %cond.store1 +; SSE4-NEXT: je .LBB8_2 +; SSE4-NEXT: .LBB8_4: # %cond.store1 ; SSE4-NEXT: pextrb $1, %xmm2, 1(%rdi) ; SSE4-NEXT: retq ; @@ -2578,17 +2578,17 @@ define void @truncstore_v2i64_v2i8(<2 x i64> %x, ptr %p, <2 x i64> %mask) { ; AVX-NEXT: vmovmskpd %xmm1, %eax ; AVX-NEXT: xorl $3, %eax ; AVX-NEXT: testb $1, %al -; AVX-NEXT: jne .LBB8_1 -; AVX-NEXT: # %bb.2: # %else -; AVX-NEXT: testb $2, %al ; AVX-NEXT: jne .LBB8_3 -; AVX-NEXT: .LBB8_4: # %else2 +; AVX-NEXT: # %bb.1: # %else +; AVX-NEXT: testb $2, %al +; AVX-NEXT: jne .LBB8_4 +; AVX-NEXT: .LBB8_2: # %else2 ; AVX-NEXT: retq -; AVX-NEXT: .LBB8_1: # %cond.store +; AVX-NEXT: .LBB8_3: # %cond.store ; AVX-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX-NEXT: testb $2, %al -; AVX-NEXT: je .LBB8_4 -; AVX-NEXT: .LBB8_3: # %cond.store1 +; AVX-NEXT: je .LBB8_2 +; AVX-NEXT: .LBB8_4: # %cond.store1 ; AVX-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX-NEXT: retq ; @@ -2600,18 +2600,18 @@ define void @truncstore_v2i64_v2i8(<2 x i64> %x, ptr %p, <2 x i64> %mask) { ; AVX512F-NEXT: vpmovusqb %zmm0, %xmm0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB8_1 -; AVX512F-NEXT: # %bb.2: # %else -; AVX512F-NEXT: testb $2, %al ; AVX512F-NEXT: jne .LBB8_3 -; AVX512F-NEXT: .LBB8_4: # %else2 +; AVX512F-NEXT: # %bb.1: # %else +; AVX512F-NEXT: testb $2, %al +; AVX512F-NEXT: jne .LBB8_4 +; AVX512F-NEXT: .LBB8_2: # %else2 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB8_1: # %cond.store +; AVX512F-NEXT: .LBB8_3: # %cond.store ; AVX512F-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB8_4 -; AVX512F-NEXT: .LBB8_3: # %cond.store1 +; AVX512F-NEXT: je .LBB8_2 +; AVX512F-NEXT: .LBB8_4: # %cond.store1 ; AVX512F-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -2622,17 +2622,17 @@ define void @truncstore_v2i64_v2i8(<2 x i64> %x, ptr %p, <2 x i64> %mask) { ; AVX512FVL-NEXT: vpmovusqb %xmm0, %xmm0 ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB8_1 -; AVX512FVL-NEXT: # %bb.2: # %else -; AVX512FVL-NEXT: testb $2, %al ; AVX512FVL-NEXT: jne .LBB8_3 -; AVX512FVL-NEXT: .LBB8_4: # %else2 +; AVX512FVL-NEXT: # %bb.1: # %else +; AVX512FVL-NEXT: testb $2, %al +; AVX512FVL-NEXT: jne .LBB8_4 +; AVX512FVL-NEXT: .LBB8_2: # %else2 ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB8_1: # %cond.store +; AVX512FVL-NEXT: .LBB8_3: # %cond.store ; AVX512FVL-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB8_4 -; AVX512FVL-NEXT: .LBB8_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB8_2 +; AVX512FVL-NEXT: .LBB8_4: # %cond.store1 ; AVX512FVL-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512FVL-NEXT: retq ; @@ -2762,66 +2762,66 @@ define void @truncstore_v16i32_v16i16(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; SSE2-NEXT: .LBB9_16: # %else14 ; SSE2-NEXT: packssdw %xmm3, %xmm2 ; SSE2-NEXT: testl $256, %eax # imm = 0x100 -; SSE2-NEXT: jne .LBB9_17 -; SSE2-NEXT: # %bb.18: # %else16 +; SSE2-NEXT: jne .LBB9_25 +; SSE2-NEXT: # %bb.17: # %else16 ; SSE2-NEXT: testl $512, %eax # imm = 0x200 -; SSE2-NEXT: jne .LBB9_19 -; SSE2-NEXT: .LBB9_20: # %else18 +; SSE2-NEXT: jne .LBB9_26 +; SSE2-NEXT: .LBB9_18: # %else18 ; SSE2-NEXT: testl $1024, %eax # imm = 0x400 -; SSE2-NEXT: jne .LBB9_21 -; SSE2-NEXT: .LBB9_22: # %else20 +; SSE2-NEXT: jne .LBB9_27 +; SSE2-NEXT: .LBB9_19: # %else20 ; SSE2-NEXT: testl $2048, %eax # imm = 0x800 -; SSE2-NEXT: jne .LBB9_23 -; SSE2-NEXT: .LBB9_24: # %else22 +; SSE2-NEXT: jne .LBB9_28 +; SSE2-NEXT: .LBB9_20: # %else22 ; SSE2-NEXT: testl $4096, %eax # imm = 0x1000 -; SSE2-NEXT: jne .LBB9_25 -; SSE2-NEXT: .LBB9_26: # %else24 +; SSE2-NEXT: jne .LBB9_29 +; SSE2-NEXT: .LBB9_21: # %else24 ; SSE2-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE2-NEXT: jne .LBB9_27 -; SSE2-NEXT: .LBB9_28: # %else26 +; SSE2-NEXT: jne .LBB9_30 +; SSE2-NEXT: .LBB9_22: # %else26 ; SSE2-NEXT: testl $16384, %eax # imm = 0x4000 -; SSE2-NEXT: jne .LBB9_29 -; SSE2-NEXT: .LBB9_30: # %else28 -; SSE2-NEXT: testl $32768, %eax # imm = 0x8000 ; SSE2-NEXT: jne .LBB9_31 -; SSE2-NEXT: .LBB9_32: # %else30 +; SSE2-NEXT: .LBB9_23: # %else28 +; SSE2-NEXT: testl $32768, %eax # imm = 0x8000 +; SSE2-NEXT: jne .LBB9_32 +; SSE2-NEXT: .LBB9_24: # %else30 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB9_17: # %cond.store15 +; SSE2-NEXT: .LBB9_25: # %cond.store15 ; SSE2-NEXT: movd %xmm2, %ecx ; SSE2-NEXT: movw %cx, 16(%rdi) ; SSE2-NEXT: testl $512, %eax # imm = 0x200 -; SSE2-NEXT: je .LBB9_20 -; SSE2-NEXT: .LBB9_19: # %cond.store17 +; SSE2-NEXT: je .LBB9_18 +; SSE2-NEXT: .LBB9_26: # %cond.store17 ; SSE2-NEXT: pextrw $1, %xmm2, %ecx ; SSE2-NEXT: movw %cx, 18(%rdi) ; SSE2-NEXT: testl $1024, %eax # imm = 0x400 -; SSE2-NEXT: je .LBB9_22 -; SSE2-NEXT: .LBB9_21: # %cond.store19 +; SSE2-NEXT: je .LBB9_19 +; SSE2-NEXT: .LBB9_27: # %cond.store19 ; SSE2-NEXT: pextrw $2, %xmm2, %ecx ; SSE2-NEXT: movw %cx, 20(%rdi) ; SSE2-NEXT: testl $2048, %eax # imm = 0x800 -; SSE2-NEXT: je .LBB9_24 -; SSE2-NEXT: .LBB9_23: # %cond.store21 +; SSE2-NEXT: je .LBB9_20 +; SSE2-NEXT: .LBB9_28: # %cond.store21 ; SSE2-NEXT: pextrw $3, %xmm2, %ecx ; SSE2-NEXT: movw %cx, 22(%rdi) ; SSE2-NEXT: testl $4096, %eax # imm = 0x1000 -; SSE2-NEXT: je .LBB9_26 -; SSE2-NEXT: .LBB9_25: # %cond.store23 +; SSE2-NEXT: je .LBB9_21 +; SSE2-NEXT: .LBB9_29: # %cond.store23 ; SSE2-NEXT: pextrw $4, %xmm2, %ecx ; SSE2-NEXT: movw %cx, 24(%rdi) ; SSE2-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE2-NEXT: je .LBB9_28 -; SSE2-NEXT: .LBB9_27: # %cond.store25 +; SSE2-NEXT: je .LBB9_22 +; SSE2-NEXT: .LBB9_30: # %cond.store25 ; SSE2-NEXT: pextrw $5, %xmm2, %ecx ; SSE2-NEXT: movw %cx, 26(%rdi) ; SSE2-NEXT: testl $16384, %eax # imm = 0x4000 -; SSE2-NEXT: je .LBB9_30 -; SSE2-NEXT: .LBB9_29: # %cond.store27 +; SSE2-NEXT: je .LBB9_23 +; SSE2-NEXT: .LBB9_31: # %cond.store27 ; SSE2-NEXT: pextrw $6, %xmm2, %ecx ; SSE2-NEXT: movw %cx, 28(%rdi) ; SSE2-NEXT: testl $32768, %eax # imm = 0x8000 -; SSE2-NEXT: je .LBB9_32 -; SSE2-NEXT: .LBB9_31: # %cond.store29 +; SSE2-NEXT: je .LBB9_24 +; SSE2-NEXT: .LBB9_32: # %cond.store29 ; SSE2-NEXT: pextrw $7, %xmm2, %eax ; SSE2-NEXT: movw %ax, 30(%rdi) ; SSE2-NEXT: retq @@ -2843,115 +2843,115 @@ define void @truncstore_v16i32_v16i16(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; SSE4-NEXT: pmovmskb %xmm4, %eax ; SSE4-NEXT: xorl $65535, %eax # imm = 0xFFFF ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB9_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB9_19 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB9_3 -; SSE4-NEXT: .LBB9_4: # %else2 +; SSE4-NEXT: jne .LBB9_20 +; SSE4-NEXT: .LBB9_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB9_5 -; SSE4-NEXT: .LBB9_6: # %else4 +; SSE4-NEXT: jne .LBB9_21 +; SSE4-NEXT: .LBB9_3: # %else4 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne .LBB9_7 -; SSE4-NEXT: .LBB9_8: # %else6 +; SSE4-NEXT: jne .LBB9_22 +; SSE4-NEXT: .LBB9_4: # %else6 ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: jne .LBB9_9 -; SSE4-NEXT: .LBB9_10: # %else8 +; SSE4-NEXT: jne .LBB9_23 +; SSE4-NEXT: .LBB9_5: # %else8 ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: jne .LBB9_11 -; SSE4-NEXT: .LBB9_12: # %else10 +; SSE4-NEXT: jne .LBB9_24 +; SSE4-NEXT: .LBB9_6: # %else10 ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: je .LBB9_14 -; SSE4-NEXT: .LBB9_13: # %cond.store11 +; SSE4-NEXT: je .LBB9_8 +; SSE4-NEXT: .LBB9_7: # %cond.store11 ; SSE4-NEXT: pextrw $6, %xmm0, 12(%rdi) -; SSE4-NEXT: .LBB9_14: # %else12 +; SSE4-NEXT: .LBB9_8: # %else12 ; SSE4-NEXT: pminud %xmm8, %xmm3 ; SSE4-NEXT: pminud %xmm8, %xmm2 ; SSE4-NEXT: testb %al, %al -; SSE4-NEXT: jns .LBB9_16 -; SSE4-NEXT: # %bb.15: # %cond.store13 +; SSE4-NEXT: jns .LBB9_10 +; SSE4-NEXT: # %bb.9: # %cond.store13 ; SSE4-NEXT: pextrw $7, %xmm0, 14(%rdi) -; SSE4-NEXT: .LBB9_16: # %else14 +; SSE4-NEXT: .LBB9_10: # %else14 ; SSE4-NEXT: packusdw %xmm3, %xmm2 ; SSE4-NEXT: testl $256, %eax # imm = 0x100 -; SSE4-NEXT: jne .LBB9_17 -; SSE4-NEXT: # %bb.18: # %else16 +; SSE4-NEXT: jne .LBB9_25 +; SSE4-NEXT: # %bb.11: # %else16 ; SSE4-NEXT: testl $512, %eax # imm = 0x200 -; SSE4-NEXT: jne .LBB9_19 -; SSE4-NEXT: .LBB9_20: # %else18 +; SSE4-NEXT: jne .LBB9_26 +; SSE4-NEXT: .LBB9_12: # %else18 ; SSE4-NEXT: testl $1024, %eax # imm = 0x400 -; SSE4-NEXT: jne .LBB9_21 -; SSE4-NEXT: .LBB9_22: # %else20 +; SSE4-NEXT: jne .LBB9_27 +; SSE4-NEXT: .LBB9_13: # %else20 ; SSE4-NEXT: testl $2048, %eax # imm = 0x800 -; SSE4-NEXT: jne .LBB9_23 -; SSE4-NEXT: .LBB9_24: # %else22 +; SSE4-NEXT: jne .LBB9_28 +; SSE4-NEXT: .LBB9_14: # %else22 ; SSE4-NEXT: testl $4096, %eax # imm = 0x1000 -; SSE4-NEXT: jne .LBB9_25 -; SSE4-NEXT: .LBB9_26: # %else24 +; SSE4-NEXT: jne .LBB9_29 +; SSE4-NEXT: .LBB9_15: # %else24 ; SSE4-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE4-NEXT: jne .LBB9_27 -; SSE4-NEXT: .LBB9_28: # %else26 +; SSE4-NEXT: jne .LBB9_30 +; SSE4-NEXT: .LBB9_16: # %else26 ; SSE4-NEXT: testl $16384, %eax # imm = 0x4000 -; SSE4-NEXT: jne .LBB9_29 -; SSE4-NEXT: .LBB9_30: # %else28 -; SSE4-NEXT: testl $32768, %eax # imm = 0x8000 ; SSE4-NEXT: jne .LBB9_31 -; SSE4-NEXT: .LBB9_32: # %else30 +; SSE4-NEXT: .LBB9_17: # %else28 +; SSE4-NEXT: testl $32768, %eax # imm = 0x8000 +; SSE4-NEXT: jne .LBB9_32 +; SSE4-NEXT: .LBB9_18: # %else30 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB9_1: # %cond.store +; SSE4-NEXT: .LBB9_19: # %cond.store ; SSE4-NEXT: pextrw $0, %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB9_4 -; SSE4-NEXT: .LBB9_3: # %cond.store1 +; SSE4-NEXT: je .LBB9_2 +; SSE4-NEXT: .LBB9_20: # %cond.store1 ; SSE4-NEXT: pextrw $1, %xmm0, 2(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB9_6 -; SSE4-NEXT: .LBB9_5: # %cond.store3 +; SSE4-NEXT: je .LBB9_3 +; SSE4-NEXT: .LBB9_21: # %cond.store3 ; SSE4-NEXT: pextrw $2, %xmm0, 4(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB9_8 -; SSE4-NEXT: .LBB9_7: # %cond.store5 +; SSE4-NEXT: je .LBB9_4 +; SSE4-NEXT: .LBB9_22: # %cond.store5 ; SSE4-NEXT: pextrw $3, %xmm0, 6(%rdi) ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: je .LBB9_10 -; SSE4-NEXT: .LBB9_9: # %cond.store7 +; SSE4-NEXT: je .LBB9_5 +; SSE4-NEXT: .LBB9_23: # %cond.store7 ; SSE4-NEXT: pextrw $4, %xmm0, 8(%rdi) ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: je .LBB9_12 -; SSE4-NEXT: .LBB9_11: # %cond.store9 +; SSE4-NEXT: je .LBB9_6 +; SSE4-NEXT: .LBB9_24: # %cond.store9 ; SSE4-NEXT: pextrw $5, %xmm0, 10(%rdi) ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: jne .LBB9_13 -; SSE4-NEXT: jmp .LBB9_14 -; SSE4-NEXT: .LBB9_17: # %cond.store15 +; SSE4-NEXT: jne .LBB9_7 +; SSE4-NEXT: jmp .LBB9_8 +; SSE4-NEXT: .LBB9_25: # %cond.store15 ; SSE4-NEXT: pextrw $0, %xmm2, 16(%rdi) ; SSE4-NEXT: testl $512, %eax # imm = 0x200 -; SSE4-NEXT: je .LBB9_20 -; SSE4-NEXT: .LBB9_19: # %cond.store17 +; SSE4-NEXT: je .LBB9_12 +; SSE4-NEXT: .LBB9_26: # %cond.store17 ; SSE4-NEXT: pextrw $1, %xmm2, 18(%rdi) ; SSE4-NEXT: testl $1024, %eax # imm = 0x400 -; SSE4-NEXT: je .LBB9_22 -; SSE4-NEXT: .LBB9_21: # %cond.store19 +; SSE4-NEXT: je .LBB9_13 +; SSE4-NEXT: .LBB9_27: # %cond.store19 ; SSE4-NEXT: pextrw $2, %xmm2, 20(%rdi) ; SSE4-NEXT: testl $2048, %eax # imm = 0x800 -; SSE4-NEXT: je .LBB9_24 -; SSE4-NEXT: .LBB9_23: # %cond.store21 +; SSE4-NEXT: je .LBB9_14 +; SSE4-NEXT: .LBB9_28: # %cond.store21 ; SSE4-NEXT: pextrw $3, %xmm2, 22(%rdi) ; SSE4-NEXT: testl $4096, %eax # imm = 0x1000 -; SSE4-NEXT: je .LBB9_26 -; SSE4-NEXT: .LBB9_25: # %cond.store23 +; SSE4-NEXT: je .LBB9_15 +; SSE4-NEXT: .LBB9_29: # %cond.store23 ; SSE4-NEXT: pextrw $4, %xmm2, 24(%rdi) ; SSE4-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE4-NEXT: je .LBB9_28 -; SSE4-NEXT: .LBB9_27: # %cond.store25 +; SSE4-NEXT: je .LBB9_16 +; SSE4-NEXT: .LBB9_30: # %cond.store25 ; SSE4-NEXT: pextrw $5, %xmm2, 26(%rdi) ; SSE4-NEXT: testl $16384, %eax # imm = 0x4000 -; SSE4-NEXT: je .LBB9_30 -; SSE4-NEXT: .LBB9_29: # %cond.store27 +; SSE4-NEXT: je .LBB9_17 +; SSE4-NEXT: .LBB9_31: # %cond.store27 ; SSE4-NEXT: pextrw $6, %xmm2, 28(%rdi) ; SSE4-NEXT: testl $32768, %eax # imm = 0x8000 -; SSE4-NEXT: je .LBB9_32 -; SSE4-NEXT: .LBB9_31: # %cond.store29 +; SSE4-NEXT: je .LBB9_18 +; SSE4-NEXT: .LBB9_32: # %cond.store29 ; SSE4-NEXT: pextrw $7, %xmm2, 30(%rdi) ; SSE4-NEXT: retq ; @@ -2980,116 +2980,116 @@ define void @truncstore_v16i32_v16i16(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; AVX1-NEXT: vpmovmskb %xmm1, %eax ; AVX1-NEXT: xorl $65535, %eax # imm = 0xFFFF ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne .LBB9_1 -; AVX1-NEXT: # %bb.2: # %else +; AVX1-NEXT: jne .LBB9_18 +; AVX1-NEXT: # %bb.1: # %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne .LBB9_3 -; AVX1-NEXT: .LBB9_4: # %else2 +; AVX1-NEXT: jne .LBB9_19 +; AVX1-NEXT: .LBB9_2: # %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne .LBB9_5 -; AVX1-NEXT: .LBB9_6: # %else4 +; AVX1-NEXT: jne .LBB9_20 +; AVX1-NEXT: .LBB9_3: # %else4 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne .LBB9_7 -; AVX1-NEXT: .LBB9_8: # %else6 +; AVX1-NEXT: jne .LBB9_21 +; AVX1-NEXT: .LBB9_4: # %else6 ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: jne .LBB9_9 -; AVX1-NEXT: .LBB9_10: # %else8 +; AVX1-NEXT: jne .LBB9_22 +; AVX1-NEXT: .LBB9_5: # %else8 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: jne .LBB9_11 -; AVX1-NEXT: .LBB9_12: # %else10 +; AVX1-NEXT: jne .LBB9_23 +; AVX1-NEXT: .LBB9_6: # %else10 ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: jne .LBB9_13 -; AVX1-NEXT: .LBB9_14: # %else12 +; AVX1-NEXT: jne .LBB9_24 +; AVX1-NEXT: .LBB9_7: # %else12 ; AVX1-NEXT: testb %al, %al -; AVX1-NEXT: jns .LBB9_16 -; AVX1-NEXT: .LBB9_15: # %cond.store13 +; AVX1-NEXT: jns .LBB9_9 +; AVX1-NEXT: .LBB9_8: # %cond.store13 ; AVX1-NEXT: vpextrw $7, %xmm0, 14(%rdi) -; AVX1-NEXT: .LBB9_16: # %else14 +; AVX1-NEXT: .LBB9_9: # %else14 ; AVX1-NEXT: testl $256, %eax # imm = 0x100 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 -; AVX1-NEXT: jne .LBB9_17 -; AVX1-NEXT: # %bb.18: # %else16 +; AVX1-NEXT: jne .LBB9_25 +; AVX1-NEXT: # %bb.10: # %else16 ; AVX1-NEXT: testl $512, %eax # imm = 0x200 -; AVX1-NEXT: jne .LBB9_19 -; AVX1-NEXT: .LBB9_20: # %else18 +; AVX1-NEXT: jne .LBB9_26 +; AVX1-NEXT: .LBB9_11: # %else18 ; AVX1-NEXT: testl $1024, %eax # imm = 0x400 -; AVX1-NEXT: jne .LBB9_21 -; AVX1-NEXT: .LBB9_22: # %else20 +; AVX1-NEXT: jne .LBB9_27 +; AVX1-NEXT: .LBB9_12: # %else20 ; AVX1-NEXT: testl $2048, %eax # imm = 0x800 -; AVX1-NEXT: jne .LBB9_23 -; AVX1-NEXT: .LBB9_24: # %else22 +; AVX1-NEXT: jne .LBB9_28 +; AVX1-NEXT: .LBB9_13: # %else22 ; AVX1-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX1-NEXT: jne .LBB9_25 -; AVX1-NEXT: .LBB9_26: # %else24 +; AVX1-NEXT: jne .LBB9_29 +; AVX1-NEXT: .LBB9_14: # %else24 ; AVX1-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX1-NEXT: jne .LBB9_27 -; AVX1-NEXT: .LBB9_28: # %else26 +; AVX1-NEXT: jne .LBB9_30 +; AVX1-NEXT: .LBB9_15: # %else26 ; AVX1-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX1-NEXT: jne .LBB9_29 -; AVX1-NEXT: .LBB9_30: # %else28 -; AVX1-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX1-NEXT: jne .LBB9_31 -; AVX1-NEXT: .LBB9_32: # %else30 +; AVX1-NEXT: .LBB9_16: # %else28 +; AVX1-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX1-NEXT: jne .LBB9_32 +; AVX1-NEXT: .LBB9_17: # %else30 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB9_1: # %cond.store +; AVX1-NEXT: .LBB9_18: # %cond.store ; AVX1-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je .LBB9_4 -; AVX1-NEXT: .LBB9_3: # %cond.store1 +; AVX1-NEXT: je .LBB9_2 +; AVX1-NEXT: .LBB9_19: # %cond.store1 ; AVX1-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je .LBB9_6 -; AVX1-NEXT: .LBB9_5: # %cond.store3 +; AVX1-NEXT: je .LBB9_3 +; AVX1-NEXT: .LBB9_20: # %cond.store3 ; AVX1-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB9_8 -; AVX1-NEXT: .LBB9_7: # %cond.store5 +; AVX1-NEXT: je .LBB9_4 +; AVX1-NEXT: .LBB9_21: # %cond.store5 ; AVX1-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: je .LBB9_10 -; AVX1-NEXT: .LBB9_9: # %cond.store7 +; AVX1-NEXT: je .LBB9_5 +; AVX1-NEXT: .LBB9_22: # %cond.store7 ; AVX1-NEXT: vpextrw $4, %xmm0, 8(%rdi) ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je .LBB9_12 -; AVX1-NEXT: .LBB9_11: # %cond.store9 +; AVX1-NEXT: je .LBB9_6 +; AVX1-NEXT: .LBB9_23: # %cond.store9 ; AVX1-NEXT: vpextrw $5, %xmm0, 10(%rdi) ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: je .LBB9_14 -; AVX1-NEXT: .LBB9_13: # %cond.store11 +; AVX1-NEXT: je .LBB9_7 +; AVX1-NEXT: .LBB9_24: # %cond.store11 ; AVX1-NEXT: vpextrw $6, %xmm0, 12(%rdi) ; AVX1-NEXT: testb %al, %al -; AVX1-NEXT: js .LBB9_15 -; AVX1-NEXT: jmp .LBB9_16 -; AVX1-NEXT: .LBB9_17: # %cond.store15 +; AVX1-NEXT: js .LBB9_8 +; AVX1-NEXT: jmp .LBB9_9 +; AVX1-NEXT: .LBB9_25: # %cond.store15 ; AVX1-NEXT: vpextrw $0, %xmm0, 16(%rdi) ; AVX1-NEXT: testl $512, %eax # imm = 0x200 -; AVX1-NEXT: je .LBB9_20 -; AVX1-NEXT: .LBB9_19: # %cond.store17 +; AVX1-NEXT: je .LBB9_11 +; AVX1-NEXT: .LBB9_26: # %cond.store17 ; AVX1-NEXT: vpextrw $1, %xmm0, 18(%rdi) ; AVX1-NEXT: testl $1024, %eax # imm = 0x400 -; AVX1-NEXT: je .LBB9_22 -; AVX1-NEXT: .LBB9_21: # %cond.store19 +; AVX1-NEXT: je .LBB9_12 +; AVX1-NEXT: .LBB9_27: # %cond.store19 ; AVX1-NEXT: vpextrw $2, %xmm0, 20(%rdi) ; AVX1-NEXT: testl $2048, %eax # imm = 0x800 -; AVX1-NEXT: je .LBB9_24 -; AVX1-NEXT: .LBB9_23: # %cond.store21 +; AVX1-NEXT: je .LBB9_13 +; AVX1-NEXT: .LBB9_28: # %cond.store21 ; AVX1-NEXT: vpextrw $3, %xmm0, 22(%rdi) ; AVX1-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX1-NEXT: je .LBB9_26 -; AVX1-NEXT: .LBB9_25: # %cond.store23 +; AVX1-NEXT: je .LBB9_14 +; AVX1-NEXT: .LBB9_29: # %cond.store23 ; AVX1-NEXT: vpextrw $4, %xmm0, 24(%rdi) ; AVX1-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX1-NEXT: je .LBB9_28 -; AVX1-NEXT: .LBB9_27: # %cond.store25 +; AVX1-NEXT: je .LBB9_15 +; AVX1-NEXT: .LBB9_30: # %cond.store25 ; AVX1-NEXT: vpextrw $5, %xmm0, 26(%rdi) ; AVX1-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX1-NEXT: je .LBB9_30 -; AVX1-NEXT: .LBB9_29: # %cond.store27 +; AVX1-NEXT: je .LBB9_16 +; AVX1-NEXT: .LBB9_31: # %cond.store27 ; AVX1-NEXT: vpextrw $6, %xmm0, 28(%rdi) ; AVX1-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX1-NEXT: je .LBB9_32 -; AVX1-NEXT: .LBB9_31: # %cond.store29 +; AVX1-NEXT: je .LBB9_17 +; AVX1-NEXT: .LBB9_32: # %cond.store29 ; AVX1-NEXT: vpextrw $7, %xmm0, 30(%rdi) ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq @@ -3112,116 +3112,116 @@ define void @truncstore_v16i32_v16i16(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,2,1,3] ; AVX2-NEXT: vpmovmskb %xmm1, %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne .LBB9_1 -; AVX2-NEXT: # %bb.2: # %else +; AVX2-NEXT: jne .LBB9_18 +; AVX2-NEXT: # %bb.1: # %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne .LBB9_3 -; AVX2-NEXT: .LBB9_4: # %else2 +; AVX2-NEXT: jne .LBB9_19 +; AVX2-NEXT: .LBB9_2: # %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne .LBB9_5 -; AVX2-NEXT: .LBB9_6: # %else4 +; AVX2-NEXT: jne .LBB9_20 +; AVX2-NEXT: .LBB9_3: # %else4 ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: jne .LBB9_7 -; AVX2-NEXT: .LBB9_8: # %else6 +; AVX2-NEXT: jne .LBB9_21 +; AVX2-NEXT: .LBB9_4: # %else6 ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: jne .LBB9_9 -; AVX2-NEXT: .LBB9_10: # %else8 +; AVX2-NEXT: jne .LBB9_22 +; AVX2-NEXT: .LBB9_5: # %else8 ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: jne .LBB9_11 -; AVX2-NEXT: .LBB9_12: # %else10 +; AVX2-NEXT: jne .LBB9_23 +; AVX2-NEXT: .LBB9_6: # %else10 ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: jne .LBB9_13 -; AVX2-NEXT: .LBB9_14: # %else12 +; AVX2-NEXT: jne .LBB9_24 +; AVX2-NEXT: .LBB9_7: # %else12 ; AVX2-NEXT: testb %al, %al -; AVX2-NEXT: jns .LBB9_16 -; AVX2-NEXT: .LBB9_15: # %cond.store13 +; AVX2-NEXT: jns .LBB9_9 +; AVX2-NEXT: .LBB9_8: # %cond.store13 ; AVX2-NEXT: vpextrw $7, %xmm0, 14(%rdi) -; AVX2-NEXT: .LBB9_16: # %else14 +; AVX2-NEXT: .LBB9_9: # %else14 ; AVX2-NEXT: testl $256, %eax # imm = 0x100 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0 -; AVX2-NEXT: jne .LBB9_17 -; AVX2-NEXT: # %bb.18: # %else16 +; AVX2-NEXT: jne .LBB9_25 +; AVX2-NEXT: # %bb.10: # %else16 ; AVX2-NEXT: testl $512, %eax # imm = 0x200 -; AVX2-NEXT: jne .LBB9_19 -; AVX2-NEXT: .LBB9_20: # %else18 +; AVX2-NEXT: jne .LBB9_26 +; AVX2-NEXT: .LBB9_11: # %else18 ; AVX2-NEXT: testl $1024, %eax # imm = 0x400 -; AVX2-NEXT: jne .LBB9_21 -; AVX2-NEXT: .LBB9_22: # %else20 +; AVX2-NEXT: jne .LBB9_27 +; AVX2-NEXT: .LBB9_12: # %else20 ; AVX2-NEXT: testl $2048, %eax # imm = 0x800 -; AVX2-NEXT: jne .LBB9_23 -; AVX2-NEXT: .LBB9_24: # %else22 +; AVX2-NEXT: jne .LBB9_28 +; AVX2-NEXT: .LBB9_13: # %else22 ; AVX2-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX2-NEXT: jne .LBB9_25 -; AVX2-NEXT: .LBB9_26: # %else24 +; AVX2-NEXT: jne .LBB9_29 +; AVX2-NEXT: .LBB9_14: # %else24 ; AVX2-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX2-NEXT: jne .LBB9_27 -; AVX2-NEXT: .LBB9_28: # %else26 +; AVX2-NEXT: jne .LBB9_30 +; AVX2-NEXT: .LBB9_15: # %else26 ; AVX2-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX2-NEXT: jne .LBB9_29 -; AVX2-NEXT: .LBB9_30: # %else28 -; AVX2-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX2-NEXT: jne .LBB9_31 -; AVX2-NEXT: .LBB9_32: # %else30 +; AVX2-NEXT: .LBB9_16: # %else28 +; AVX2-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX2-NEXT: jne .LBB9_32 +; AVX2-NEXT: .LBB9_17: # %else30 ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; AVX2-NEXT: .LBB9_1: # %cond.store +; AVX2-NEXT: .LBB9_18: # %cond.store ; AVX2-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je .LBB9_4 -; AVX2-NEXT: .LBB9_3: # %cond.store1 +; AVX2-NEXT: je .LBB9_2 +; AVX2-NEXT: .LBB9_19: # %cond.store1 ; AVX2-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je .LBB9_6 -; AVX2-NEXT: .LBB9_5: # %cond.store3 +; AVX2-NEXT: je .LBB9_3 +; AVX2-NEXT: .LBB9_20: # %cond.store3 ; AVX2-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je .LBB9_8 -; AVX2-NEXT: .LBB9_7: # %cond.store5 +; AVX2-NEXT: je .LBB9_4 +; AVX2-NEXT: .LBB9_21: # %cond.store5 ; AVX2-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: je .LBB9_10 -; AVX2-NEXT: .LBB9_9: # %cond.store7 +; AVX2-NEXT: je .LBB9_5 +; AVX2-NEXT: .LBB9_22: # %cond.store7 ; AVX2-NEXT: vpextrw $4, %xmm0, 8(%rdi) ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: je .LBB9_12 -; AVX2-NEXT: .LBB9_11: # %cond.store9 +; AVX2-NEXT: je .LBB9_6 +; AVX2-NEXT: .LBB9_23: # %cond.store9 ; AVX2-NEXT: vpextrw $5, %xmm0, 10(%rdi) ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: je .LBB9_14 -; AVX2-NEXT: .LBB9_13: # %cond.store11 +; AVX2-NEXT: je .LBB9_7 +; AVX2-NEXT: .LBB9_24: # %cond.store11 ; AVX2-NEXT: vpextrw $6, %xmm0, 12(%rdi) ; AVX2-NEXT: testb %al, %al -; AVX2-NEXT: js .LBB9_15 -; AVX2-NEXT: jmp .LBB9_16 -; AVX2-NEXT: .LBB9_17: # %cond.store15 +; AVX2-NEXT: js .LBB9_8 +; AVX2-NEXT: jmp .LBB9_9 +; AVX2-NEXT: .LBB9_25: # %cond.store15 ; AVX2-NEXT: vpextrw $0, %xmm0, 16(%rdi) ; AVX2-NEXT: testl $512, %eax # imm = 0x200 -; AVX2-NEXT: je .LBB9_20 -; AVX2-NEXT: .LBB9_19: # %cond.store17 +; AVX2-NEXT: je .LBB9_11 +; AVX2-NEXT: .LBB9_26: # %cond.store17 ; AVX2-NEXT: vpextrw $1, %xmm0, 18(%rdi) ; AVX2-NEXT: testl $1024, %eax # imm = 0x400 -; AVX2-NEXT: je .LBB9_22 -; AVX2-NEXT: .LBB9_21: # %cond.store19 +; AVX2-NEXT: je .LBB9_12 +; AVX2-NEXT: .LBB9_27: # %cond.store19 ; AVX2-NEXT: vpextrw $2, %xmm0, 20(%rdi) ; AVX2-NEXT: testl $2048, %eax # imm = 0x800 -; AVX2-NEXT: je .LBB9_24 -; AVX2-NEXT: .LBB9_23: # %cond.store21 +; AVX2-NEXT: je .LBB9_13 +; AVX2-NEXT: .LBB9_28: # %cond.store21 ; AVX2-NEXT: vpextrw $3, %xmm0, 22(%rdi) ; AVX2-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX2-NEXT: je .LBB9_26 -; AVX2-NEXT: .LBB9_25: # %cond.store23 +; AVX2-NEXT: je .LBB9_14 +; AVX2-NEXT: .LBB9_29: # %cond.store23 ; AVX2-NEXT: vpextrw $4, %xmm0, 24(%rdi) ; AVX2-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX2-NEXT: je .LBB9_28 -; AVX2-NEXT: .LBB9_27: # %cond.store25 +; AVX2-NEXT: je .LBB9_15 +; AVX2-NEXT: .LBB9_30: # %cond.store25 ; AVX2-NEXT: vpextrw $5, %xmm0, 26(%rdi) ; AVX2-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX2-NEXT: je .LBB9_30 -; AVX2-NEXT: .LBB9_29: # %cond.store27 +; AVX2-NEXT: je .LBB9_16 +; AVX2-NEXT: .LBB9_31: # %cond.store27 ; AVX2-NEXT: vpextrw $6, %xmm0, 28(%rdi) ; AVX2-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX2-NEXT: je .LBB9_32 -; AVX2-NEXT: .LBB9_31: # %cond.store29 +; AVX2-NEXT: je .LBB9_17 +; AVX2-NEXT: .LBB9_32: # %cond.store29 ; AVX2-NEXT: vpextrw $7, %xmm0, 30(%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq @@ -3232,116 +3232,116 @@ define void @truncstore_v16i32_v16i16(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; AVX512F-NEXT: vpmovusdw %zmm0, %ymm0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB9_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB9_18 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB9_3 -; AVX512F-NEXT: .LBB9_4: # %else2 +; AVX512F-NEXT: jne .LBB9_19 +; AVX512F-NEXT: .LBB9_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB9_5 -; AVX512F-NEXT: .LBB9_6: # %else4 +; AVX512F-NEXT: jne .LBB9_20 +; AVX512F-NEXT: .LBB9_3: # %else4 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne .LBB9_7 -; AVX512F-NEXT: .LBB9_8: # %else6 +; AVX512F-NEXT: jne .LBB9_21 +; AVX512F-NEXT: .LBB9_4: # %else6 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne .LBB9_9 -; AVX512F-NEXT: .LBB9_10: # %else8 +; AVX512F-NEXT: jne .LBB9_22 +; AVX512F-NEXT: .LBB9_5: # %else8 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne .LBB9_11 -; AVX512F-NEXT: .LBB9_12: # %else10 +; AVX512F-NEXT: jne .LBB9_23 +; AVX512F-NEXT: .LBB9_6: # %else10 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne .LBB9_13 -; AVX512F-NEXT: .LBB9_14: # %else12 +; AVX512F-NEXT: jne .LBB9_24 +; AVX512F-NEXT: .LBB9_7: # %else12 ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: jns .LBB9_16 -; AVX512F-NEXT: .LBB9_15: # %cond.store13 +; AVX512F-NEXT: jns .LBB9_9 +; AVX512F-NEXT: .LBB9_8: # %cond.store13 ; AVX512F-NEXT: vpextrw $7, %xmm0, 14(%rdi) -; AVX512F-NEXT: .LBB9_16: # %else14 +; AVX512F-NEXT: .LBB9_9: # %else14 ; AVX512F-NEXT: testl $256, %eax # imm = 0x100 ; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm0 -; AVX512F-NEXT: jne .LBB9_17 -; AVX512F-NEXT: # %bb.18: # %else16 +; AVX512F-NEXT: jne .LBB9_25 +; AVX512F-NEXT: # %bb.10: # %else16 ; AVX512F-NEXT: testl $512, %eax # imm = 0x200 -; AVX512F-NEXT: jne .LBB9_19 -; AVX512F-NEXT: .LBB9_20: # %else18 +; AVX512F-NEXT: jne .LBB9_26 +; AVX512F-NEXT: .LBB9_11: # %else18 ; AVX512F-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512F-NEXT: jne .LBB9_21 -; AVX512F-NEXT: .LBB9_22: # %else20 +; AVX512F-NEXT: jne .LBB9_27 +; AVX512F-NEXT: .LBB9_12: # %else20 ; AVX512F-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512F-NEXT: jne .LBB9_23 -; AVX512F-NEXT: .LBB9_24: # %else22 +; AVX512F-NEXT: jne .LBB9_28 +; AVX512F-NEXT: .LBB9_13: # %else22 ; AVX512F-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512F-NEXT: jne .LBB9_25 -; AVX512F-NEXT: .LBB9_26: # %else24 +; AVX512F-NEXT: jne .LBB9_29 +; AVX512F-NEXT: .LBB9_14: # %else24 ; AVX512F-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512F-NEXT: jne .LBB9_27 -; AVX512F-NEXT: .LBB9_28: # %else26 +; AVX512F-NEXT: jne .LBB9_30 +; AVX512F-NEXT: .LBB9_15: # %else26 ; AVX512F-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512F-NEXT: jne .LBB9_29 -; AVX512F-NEXT: .LBB9_30: # %else28 -; AVX512F-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX512F-NEXT: jne .LBB9_31 -; AVX512F-NEXT: .LBB9_32: # %else30 +; AVX512F-NEXT: .LBB9_16: # %else28 +; AVX512F-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX512F-NEXT: jne .LBB9_32 +; AVX512F-NEXT: .LBB9_17: # %else30 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB9_1: # %cond.store +; AVX512F-NEXT: .LBB9_18: # %cond.store ; AVX512F-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB9_4 -; AVX512F-NEXT: .LBB9_3: # %cond.store1 +; AVX512F-NEXT: je .LBB9_2 +; AVX512F-NEXT: .LBB9_19: # %cond.store1 ; AVX512F-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB9_6 -; AVX512F-NEXT: .LBB9_5: # %cond.store3 +; AVX512F-NEXT: je .LBB9_3 +; AVX512F-NEXT: .LBB9_20: # %cond.store3 ; AVX512F-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB9_8 -; AVX512F-NEXT: .LBB9_7: # %cond.store5 +; AVX512F-NEXT: je .LBB9_4 +; AVX512F-NEXT: .LBB9_21: # %cond.store5 ; AVX512F-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je .LBB9_10 -; AVX512F-NEXT: .LBB9_9: # %cond.store7 +; AVX512F-NEXT: je .LBB9_5 +; AVX512F-NEXT: .LBB9_22: # %cond.store7 ; AVX512F-NEXT: vpextrw $4, %xmm0, 8(%rdi) ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je .LBB9_12 -; AVX512F-NEXT: .LBB9_11: # %cond.store9 +; AVX512F-NEXT: je .LBB9_6 +; AVX512F-NEXT: .LBB9_23: # %cond.store9 ; AVX512F-NEXT: vpextrw $5, %xmm0, 10(%rdi) ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je .LBB9_14 -; AVX512F-NEXT: .LBB9_13: # %cond.store11 +; AVX512F-NEXT: je .LBB9_7 +; AVX512F-NEXT: .LBB9_24: # %cond.store11 ; AVX512F-NEXT: vpextrw $6, %xmm0, 12(%rdi) ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: js .LBB9_15 -; AVX512F-NEXT: jmp .LBB9_16 -; AVX512F-NEXT: .LBB9_17: # %cond.store15 +; AVX512F-NEXT: js .LBB9_8 +; AVX512F-NEXT: jmp .LBB9_9 +; AVX512F-NEXT: .LBB9_25: # %cond.store15 ; AVX512F-NEXT: vpextrw $0, %xmm0, 16(%rdi) ; AVX512F-NEXT: testl $512, %eax # imm = 0x200 -; AVX512F-NEXT: je .LBB9_20 -; AVX512F-NEXT: .LBB9_19: # %cond.store17 +; AVX512F-NEXT: je .LBB9_11 +; AVX512F-NEXT: .LBB9_26: # %cond.store17 ; AVX512F-NEXT: vpextrw $1, %xmm0, 18(%rdi) ; AVX512F-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512F-NEXT: je .LBB9_22 -; AVX512F-NEXT: .LBB9_21: # %cond.store19 +; AVX512F-NEXT: je .LBB9_12 +; AVX512F-NEXT: .LBB9_27: # %cond.store19 ; AVX512F-NEXT: vpextrw $2, %xmm0, 20(%rdi) ; AVX512F-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512F-NEXT: je .LBB9_24 -; AVX512F-NEXT: .LBB9_23: # %cond.store21 +; AVX512F-NEXT: je .LBB9_13 +; AVX512F-NEXT: .LBB9_28: # %cond.store21 ; AVX512F-NEXT: vpextrw $3, %xmm0, 22(%rdi) ; AVX512F-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512F-NEXT: je .LBB9_26 -; AVX512F-NEXT: .LBB9_25: # %cond.store23 +; AVX512F-NEXT: je .LBB9_14 +; AVX512F-NEXT: .LBB9_29: # %cond.store23 ; AVX512F-NEXT: vpextrw $4, %xmm0, 24(%rdi) ; AVX512F-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512F-NEXT: je .LBB9_28 -; AVX512F-NEXT: .LBB9_27: # %cond.store25 +; AVX512F-NEXT: je .LBB9_15 +; AVX512F-NEXT: .LBB9_30: # %cond.store25 ; AVX512F-NEXT: vpextrw $5, %xmm0, 26(%rdi) ; AVX512F-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512F-NEXT: je .LBB9_30 -; AVX512F-NEXT: .LBB9_29: # %cond.store27 +; AVX512F-NEXT: je .LBB9_16 +; AVX512F-NEXT: .LBB9_31: # %cond.store27 ; AVX512F-NEXT: vpextrw $6, %xmm0, 28(%rdi) ; AVX512F-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX512F-NEXT: je .LBB9_32 -; AVX512F-NEXT: .LBB9_31: # %cond.store29 +; AVX512F-NEXT: je .LBB9_17 +; AVX512F-NEXT: .LBB9_32: # %cond.store29 ; AVX512F-NEXT: vpextrw $7, %xmm0, 30(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -3352,116 +3352,116 @@ define void @truncstore_v16i32_v16i16(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; AVX512FVL-NEXT: vpmovusdw %zmm0, %ymm0 ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB9_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB9_18 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB9_3 -; AVX512FVL-NEXT: .LBB9_4: # %else2 +; AVX512FVL-NEXT: jne .LBB9_19 +; AVX512FVL-NEXT: .LBB9_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB9_5 -; AVX512FVL-NEXT: .LBB9_6: # %else4 +; AVX512FVL-NEXT: jne .LBB9_20 +; AVX512FVL-NEXT: .LBB9_3: # %else4 ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: jne .LBB9_7 -; AVX512FVL-NEXT: .LBB9_8: # %else6 +; AVX512FVL-NEXT: jne .LBB9_21 +; AVX512FVL-NEXT: .LBB9_4: # %else6 ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: jne .LBB9_9 -; AVX512FVL-NEXT: .LBB9_10: # %else8 +; AVX512FVL-NEXT: jne .LBB9_22 +; AVX512FVL-NEXT: .LBB9_5: # %else8 ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: jne .LBB9_11 -; AVX512FVL-NEXT: .LBB9_12: # %else10 +; AVX512FVL-NEXT: jne .LBB9_23 +; AVX512FVL-NEXT: .LBB9_6: # %else10 ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: jne .LBB9_13 -; AVX512FVL-NEXT: .LBB9_14: # %else12 +; AVX512FVL-NEXT: jne .LBB9_24 +; AVX512FVL-NEXT: .LBB9_7: # %else12 ; AVX512FVL-NEXT: testb %al, %al -; AVX512FVL-NEXT: jns .LBB9_16 -; AVX512FVL-NEXT: .LBB9_15: # %cond.store13 +; AVX512FVL-NEXT: jns .LBB9_9 +; AVX512FVL-NEXT: .LBB9_8: # %cond.store13 ; AVX512FVL-NEXT: vpextrw $7, %xmm0, 14(%rdi) -; AVX512FVL-NEXT: .LBB9_16: # %else14 +; AVX512FVL-NEXT: .LBB9_9: # %else14 ; AVX512FVL-NEXT: testl $256, %eax # imm = 0x100 ; AVX512FVL-NEXT: vextracti128 $1, %ymm0, %xmm0 -; AVX512FVL-NEXT: jne .LBB9_17 -; AVX512FVL-NEXT: # %bb.18: # %else16 +; AVX512FVL-NEXT: jne .LBB9_25 +; AVX512FVL-NEXT: # %bb.10: # %else16 ; AVX512FVL-NEXT: testl $512, %eax # imm = 0x200 -; AVX512FVL-NEXT: jne .LBB9_19 -; AVX512FVL-NEXT: .LBB9_20: # %else18 +; AVX512FVL-NEXT: jne .LBB9_26 +; AVX512FVL-NEXT: .LBB9_11: # %else18 ; AVX512FVL-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512FVL-NEXT: jne .LBB9_21 -; AVX512FVL-NEXT: .LBB9_22: # %else20 +; AVX512FVL-NEXT: jne .LBB9_27 +; AVX512FVL-NEXT: .LBB9_12: # %else20 ; AVX512FVL-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512FVL-NEXT: jne .LBB9_23 -; AVX512FVL-NEXT: .LBB9_24: # %else22 +; AVX512FVL-NEXT: jne .LBB9_28 +; AVX512FVL-NEXT: .LBB9_13: # %else22 ; AVX512FVL-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512FVL-NEXT: jne .LBB9_25 -; AVX512FVL-NEXT: .LBB9_26: # %else24 +; AVX512FVL-NEXT: jne .LBB9_29 +; AVX512FVL-NEXT: .LBB9_14: # %else24 ; AVX512FVL-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512FVL-NEXT: jne .LBB9_27 -; AVX512FVL-NEXT: .LBB9_28: # %else26 +; AVX512FVL-NEXT: jne .LBB9_30 +; AVX512FVL-NEXT: .LBB9_15: # %else26 ; AVX512FVL-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512FVL-NEXT: jne .LBB9_29 -; AVX512FVL-NEXT: .LBB9_30: # %else28 -; AVX512FVL-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX512FVL-NEXT: jne .LBB9_31 -; AVX512FVL-NEXT: .LBB9_32: # %else30 +; AVX512FVL-NEXT: .LBB9_16: # %else28 +; AVX512FVL-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX512FVL-NEXT: jne .LBB9_32 +; AVX512FVL-NEXT: .LBB9_17: # %else30 ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB9_1: # %cond.store +; AVX512FVL-NEXT: .LBB9_18: # %cond.store ; AVX512FVL-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB9_4 -; AVX512FVL-NEXT: .LBB9_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB9_2 +; AVX512FVL-NEXT: .LBB9_19: # %cond.store1 ; AVX512FVL-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB9_6 -; AVX512FVL-NEXT: .LBB9_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB9_3 +; AVX512FVL-NEXT: .LBB9_20: # %cond.store3 ; AVX512FVL-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB9_8 -; AVX512FVL-NEXT: .LBB9_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB9_4 +; AVX512FVL-NEXT: .LBB9_21: # %cond.store5 ; AVX512FVL-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: je .LBB9_10 -; AVX512FVL-NEXT: .LBB9_9: # %cond.store7 +; AVX512FVL-NEXT: je .LBB9_5 +; AVX512FVL-NEXT: .LBB9_22: # %cond.store7 ; AVX512FVL-NEXT: vpextrw $4, %xmm0, 8(%rdi) ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: je .LBB9_12 -; AVX512FVL-NEXT: .LBB9_11: # %cond.store9 +; AVX512FVL-NEXT: je .LBB9_6 +; AVX512FVL-NEXT: .LBB9_23: # %cond.store9 ; AVX512FVL-NEXT: vpextrw $5, %xmm0, 10(%rdi) ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: je .LBB9_14 -; AVX512FVL-NEXT: .LBB9_13: # %cond.store11 +; AVX512FVL-NEXT: je .LBB9_7 +; AVX512FVL-NEXT: .LBB9_24: # %cond.store11 ; AVX512FVL-NEXT: vpextrw $6, %xmm0, 12(%rdi) ; AVX512FVL-NEXT: testb %al, %al -; AVX512FVL-NEXT: js .LBB9_15 -; AVX512FVL-NEXT: jmp .LBB9_16 -; AVX512FVL-NEXT: .LBB9_17: # %cond.store15 +; AVX512FVL-NEXT: js .LBB9_8 +; AVX512FVL-NEXT: jmp .LBB9_9 +; AVX512FVL-NEXT: .LBB9_25: # %cond.store15 ; AVX512FVL-NEXT: vpextrw $0, %xmm0, 16(%rdi) ; AVX512FVL-NEXT: testl $512, %eax # imm = 0x200 -; AVX512FVL-NEXT: je .LBB9_20 -; AVX512FVL-NEXT: .LBB9_19: # %cond.store17 +; AVX512FVL-NEXT: je .LBB9_11 +; AVX512FVL-NEXT: .LBB9_26: # %cond.store17 ; AVX512FVL-NEXT: vpextrw $1, %xmm0, 18(%rdi) ; AVX512FVL-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512FVL-NEXT: je .LBB9_22 -; AVX512FVL-NEXT: .LBB9_21: # %cond.store19 +; AVX512FVL-NEXT: je .LBB9_12 +; AVX512FVL-NEXT: .LBB9_27: # %cond.store19 ; AVX512FVL-NEXT: vpextrw $2, %xmm0, 20(%rdi) ; AVX512FVL-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512FVL-NEXT: je .LBB9_24 -; AVX512FVL-NEXT: .LBB9_23: # %cond.store21 +; AVX512FVL-NEXT: je .LBB9_13 +; AVX512FVL-NEXT: .LBB9_28: # %cond.store21 ; AVX512FVL-NEXT: vpextrw $3, %xmm0, 22(%rdi) ; AVX512FVL-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512FVL-NEXT: je .LBB9_26 -; AVX512FVL-NEXT: .LBB9_25: # %cond.store23 +; AVX512FVL-NEXT: je .LBB9_14 +; AVX512FVL-NEXT: .LBB9_29: # %cond.store23 ; AVX512FVL-NEXT: vpextrw $4, %xmm0, 24(%rdi) ; AVX512FVL-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512FVL-NEXT: je .LBB9_28 -; AVX512FVL-NEXT: .LBB9_27: # %cond.store25 +; AVX512FVL-NEXT: je .LBB9_15 +; AVX512FVL-NEXT: .LBB9_30: # %cond.store25 ; AVX512FVL-NEXT: vpextrw $5, %xmm0, 26(%rdi) ; AVX512FVL-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512FVL-NEXT: je .LBB9_30 -; AVX512FVL-NEXT: .LBB9_29: # %cond.store27 +; AVX512FVL-NEXT: je .LBB9_16 +; AVX512FVL-NEXT: .LBB9_31: # %cond.store27 ; AVX512FVL-NEXT: vpextrw $6, %xmm0, 28(%rdi) ; AVX512FVL-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX512FVL-NEXT: je .LBB9_32 -; AVX512FVL-NEXT: .LBB9_31: # %cond.store29 +; AVX512FVL-NEXT: je .LBB9_17 +; AVX512FVL-NEXT: .LBB9_32: # %cond.store29 ; AVX512FVL-NEXT: vpextrw $7, %xmm0, 30(%rdi) ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq @@ -3534,103 +3534,103 @@ define void @truncstore_v16i32_v16i8(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; SSE2-NEXT: xorl $65535, %eax # imm = 0xFFFF ; SSE2-NEXT: testb $1, %al ; SSE2-NEXT: movd %xmm1, %ecx -; SSE2-NEXT: jne .LBB10_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB10_28 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne .LBB10_3 -; SSE2-NEXT: .LBB10_4: # %else2 +; SSE2-NEXT: jne .LBB10_29 +; SSE2-NEXT: .LBB10_2: # %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne .LBB10_5 -; SSE2-NEXT: .LBB10_6: # %else4 +; SSE2-NEXT: jne .LBB10_30 +; SSE2-NEXT: .LBB10_3: # %else4 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je .LBB10_8 -; SSE2-NEXT: .LBB10_7: # %cond.store5 +; SSE2-NEXT: je .LBB10_5 +; SSE2-NEXT: .LBB10_4: # %cond.store5 ; SSE2-NEXT: shrl $24, %ecx ; SSE2-NEXT: movb %cl, 3(%rdi) -; SSE2-NEXT: .LBB10_8: # %else6 +; SSE2-NEXT: .LBB10_5: # %else6 ; SSE2-NEXT: testb $16, %al ; SSE2-NEXT: pextrw $2, %xmm1, %ecx -; SSE2-NEXT: je .LBB10_10 -; SSE2-NEXT: # %bb.9: # %cond.store7 +; SSE2-NEXT: je .LBB10_7 +; SSE2-NEXT: # %bb.6: # %cond.store7 ; SSE2-NEXT: movb %cl, 4(%rdi) -; SSE2-NEXT: .LBB10_10: # %else8 +; SSE2-NEXT: .LBB10_7: # %else8 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je .LBB10_12 -; SSE2-NEXT: # %bb.11: # %cond.store9 +; SSE2-NEXT: je .LBB10_9 +; SSE2-NEXT: # %bb.8: # %cond.store9 ; SSE2-NEXT: movb %ch, 5(%rdi) -; SSE2-NEXT: .LBB10_12: # %else10 +; SSE2-NEXT: .LBB10_9: # %else10 ; SSE2-NEXT: testb $64, %al ; SSE2-NEXT: pextrw $3, %xmm1, %ecx -; SSE2-NEXT: je .LBB10_14 -; SSE2-NEXT: # %bb.13: # %cond.store11 +; SSE2-NEXT: je .LBB10_11 +; SSE2-NEXT: # %bb.10: # %cond.store11 ; SSE2-NEXT: movb %cl, 6(%rdi) -; SSE2-NEXT: .LBB10_14: # %else12 +; SSE2-NEXT: .LBB10_11: # %else12 ; SSE2-NEXT: testb %al, %al -; SSE2-NEXT: jns .LBB10_16 -; SSE2-NEXT: # %bb.15: # %cond.store13 +; SSE2-NEXT: jns .LBB10_13 +; SSE2-NEXT: # %bb.12: # %cond.store13 ; SSE2-NEXT: movb %ch, 7(%rdi) -; SSE2-NEXT: .LBB10_16: # %else14 +; SSE2-NEXT: .LBB10_13: # %else14 ; SSE2-NEXT: testl $256, %eax # imm = 0x100 ; SSE2-NEXT: pextrw $4, %xmm1, %ecx -; SSE2-NEXT: je .LBB10_18 -; SSE2-NEXT: # %bb.17: # %cond.store15 +; SSE2-NEXT: je .LBB10_15 +; SSE2-NEXT: # %bb.14: # %cond.store15 ; SSE2-NEXT: movb %cl, 8(%rdi) -; SSE2-NEXT: .LBB10_18: # %else16 +; SSE2-NEXT: .LBB10_15: # %else16 ; SSE2-NEXT: testl $512, %eax # imm = 0x200 -; SSE2-NEXT: je .LBB10_20 -; SSE2-NEXT: # %bb.19: # %cond.store17 +; SSE2-NEXT: je .LBB10_17 +; SSE2-NEXT: # %bb.16: # %cond.store17 ; SSE2-NEXT: movb %ch, 9(%rdi) -; SSE2-NEXT: .LBB10_20: # %else18 +; SSE2-NEXT: .LBB10_17: # %else18 ; SSE2-NEXT: testl $1024, %eax # imm = 0x400 ; SSE2-NEXT: pextrw $5, %xmm1, %ecx -; SSE2-NEXT: je .LBB10_22 -; SSE2-NEXT: # %bb.21: # %cond.store19 +; SSE2-NEXT: je .LBB10_19 +; SSE2-NEXT: # %bb.18: # %cond.store19 ; SSE2-NEXT: movb %cl, 10(%rdi) -; SSE2-NEXT: .LBB10_22: # %else20 +; SSE2-NEXT: .LBB10_19: # %else20 ; SSE2-NEXT: testl $2048, %eax # imm = 0x800 -; SSE2-NEXT: je .LBB10_24 -; SSE2-NEXT: # %bb.23: # %cond.store21 +; SSE2-NEXT: je .LBB10_21 +; SSE2-NEXT: # %bb.20: # %cond.store21 ; SSE2-NEXT: movb %ch, 11(%rdi) -; SSE2-NEXT: .LBB10_24: # %else22 +; SSE2-NEXT: .LBB10_21: # %else22 ; SSE2-NEXT: testl $4096, %eax # imm = 0x1000 ; SSE2-NEXT: pextrw $6, %xmm1, %ecx -; SSE2-NEXT: je .LBB10_26 -; SSE2-NEXT: # %bb.25: # %cond.store23 +; SSE2-NEXT: je .LBB10_23 +; SSE2-NEXT: # %bb.22: # %cond.store23 ; SSE2-NEXT: movb %cl, 12(%rdi) -; SSE2-NEXT: .LBB10_26: # %else24 +; SSE2-NEXT: .LBB10_23: # %else24 ; SSE2-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE2-NEXT: je .LBB10_28 -; SSE2-NEXT: # %bb.27: # %cond.store25 +; SSE2-NEXT: je .LBB10_25 +; SSE2-NEXT: # %bb.24: # %cond.store25 ; SSE2-NEXT: movb %ch, 13(%rdi) -; SSE2-NEXT: .LBB10_28: # %else26 +; SSE2-NEXT: .LBB10_25: # %else26 ; SSE2-NEXT: testl $16384, %eax # imm = 0x4000 ; SSE2-NEXT: pextrw $7, %xmm1, %ecx -; SSE2-NEXT: jne .LBB10_29 -; SSE2-NEXT: # %bb.30: # %else28 -; SSE2-NEXT: testl $32768, %eax # imm = 0x8000 ; SSE2-NEXT: jne .LBB10_31 -; SSE2-NEXT: .LBB10_32: # %else30 +; SSE2-NEXT: # %bb.26: # %else28 +; SSE2-NEXT: testl $32768, %eax # imm = 0x8000 +; SSE2-NEXT: jne .LBB10_32 +; SSE2-NEXT: .LBB10_27: # %else30 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB10_1: # %cond.store +; SSE2-NEXT: .LBB10_28: # %cond.store ; SSE2-NEXT: movb %cl, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB10_4 -; SSE2-NEXT: .LBB10_3: # %cond.store1 +; SSE2-NEXT: je .LBB10_2 +; SSE2-NEXT: .LBB10_29: # %cond.store1 ; SSE2-NEXT: movb %ch, 1(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je .LBB10_6 -; SSE2-NEXT: .LBB10_5: # %cond.store3 +; SSE2-NEXT: je .LBB10_3 +; SSE2-NEXT: .LBB10_30: # %cond.store3 ; SSE2-NEXT: movl %ecx, %edx ; SSE2-NEXT: shrl $16, %edx ; SSE2-NEXT: movb %dl, 2(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne .LBB10_7 -; SSE2-NEXT: jmp .LBB10_8 -; SSE2-NEXT: .LBB10_29: # %cond.store27 +; SSE2-NEXT: jne .LBB10_4 +; SSE2-NEXT: jmp .LBB10_5 +; SSE2-NEXT: .LBB10_31: # %cond.store27 ; SSE2-NEXT: movb %cl, 14(%rdi) ; SSE2-NEXT: testl $32768, %eax # imm = 0x8000 -; SSE2-NEXT: je .LBB10_32 -; SSE2-NEXT: .LBB10_31: # %cond.store29 +; SSE2-NEXT: je .LBB10_27 +; SSE2-NEXT: .LBB10_32: # %cond.store29 ; SSE2-NEXT: movb %ch, 15(%rdi) ; SSE2-NEXT: retq ; @@ -3655,115 +3655,115 @@ define void @truncstore_v16i32_v16i8(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; SSE4-NEXT: pmovmskb %xmm4, %eax ; SSE4-NEXT: xorl $65535, %eax # imm = 0xFFFF ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB10_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB10_17 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB10_3 -; SSE4-NEXT: .LBB10_4: # %else2 +; SSE4-NEXT: jne .LBB10_18 +; SSE4-NEXT: .LBB10_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB10_5 -; SSE4-NEXT: .LBB10_6: # %else4 +; SSE4-NEXT: jne .LBB10_19 +; SSE4-NEXT: .LBB10_3: # %else4 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne .LBB10_7 -; SSE4-NEXT: .LBB10_8: # %else6 +; SSE4-NEXT: jne .LBB10_20 +; SSE4-NEXT: .LBB10_4: # %else6 ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: jne .LBB10_9 -; SSE4-NEXT: .LBB10_10: # %else8 +; SSE4-NEXT: jne .LBB10_21 +; SSE4-NEXT: .LBB10_5: # %else8 ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: jne .LBB10_11 -; SSE4-NEXT: .LBB10_12: # %else10 +; SSE4-NEXT: jne .LBB10_22 +; SSE4-NEXT: .LBB10_6: # %else10 ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: jne .LBB10_13 -; SSE4-NEXT: .LBB10_14: # %else12 +; SSE4-NEXT: jne .LBB10_23 +; SSE4-NEXT: .LBB10_7: # %else12 ; SSE4-NEXT: testb %al, %al -; SSE4-NEXT: js .LBB10_15 -; SSE4-NEXT: .LBB10_16: # %else14 +; SSE4-NEXT: js .LBB10_24 +; SSE4-NEXT: .LBB10_8: # %else14 ; SSE4-NEXT: testl $256, %eax # imm = 0x100 -; SSE4-NEXT: jne .LBB10_17 -; SSE4-NEXT: .LBB10_18: # %else16 +; SSE4-NEXT: jne .LBB10_25 +; SSE4-NEXT: .LBB10_9: # %else16 ; SSE4-NEXT: testl $512, %eax # imm = 0x200 -; SSE4-NEXT: jne .LBB10_19 -; SSE4-NEXT: .LBB10_20: # %else18 +; SSE4-NEXT: jne .LBB10_26 +; SSE4-NEXT: .LBB10_10: # %else18 ; SSE4-NEXT: testl $1024, %eax # imm = 0x400 -; SSE4-NEXT: jne .LBB10_21 -; SSE4-NEXT: .LBB10_22: # %else20 +; SSE4-NEXT: jne .LBB10_27 +; SSE4-NEXT: .LBB10_11: # %else20 ; SSE4-NEXT: testl $2048, %eax # imm = 0x800 -; SSE4-NEXT: jne .LBB10_23 -; SSE4-NEXT: .LBB10_24: # %else22 +; SSE4-NEXT: jne .LBB10_28 +; SSE4-NEXT: .LBB10_12: # %else22 ; SSE4-NEXT: testl $4096, %eax # imm = 0x1000 -; SSE4-NEXT: jne .LBB10_25 -; SSE4-NEXT: .LBB10_26: # %else24 +; SSE4-NEXT: jne .LBB10_29 +; SSE4-NEXT: .LBB10_13: # %else24 ; SSE4-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE4-NEXT: jne .LBB10_27 -; SSE4-NEXT: .LBB10_28: # %else26 +; SSE4-NEXT: jne .LBB10_30 +; SSE4-NEXT: .LBB10_14: # %else26 ; SSE4-NEXT: testl $16384, %eax # imm = 0x4000 -; SSE4-NEXT: jne .LBB10_29 -; SSE4-NEXT: .LBB10_30: # %else28 -; SSE4-NEXT: testl $32768, %eax # imm = 0x8000 ; SSE4-NEXT: jne .LBB10_31 -; SSE4-NEXT: .LBB10_32: # %else30 +; SSE4-NEXT: .LBB10_15: # %else28 +; SSE4-NEXT: testl $32768, %eax # imm = 0x8000 +; SSE4-NEXT: jne .LBB10_32 +; SSE4-NEXT: .LBB10_16: # %else30 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB10_1: # %cond.store +; SSE4-NEXT: .LBB10_17: # %cond.store ; SSE4-NEXT: pextrb $0, %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB10_4 -; SSE4-NEXT: .LBB10_3: # %cond.store1 +; SSE4-NEXT: je .LBB10_2 +; SSE4-NEXT: .LBB10_18: # %cond.store1 ; SSE4-NEXT: pextrb $1, %xmm0, 1(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB10_6 -; SSE4-NEXT: .LBB10_5: # %cond.store3 +; SSE4-NEXT: je .LBB10_3 +; SSE4-NEXT: .LBB10_19: # %cond.store3 ; SSE4-NEXT: pextrb $2, %xmm0, 2(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB10_8 -; SSE4-NEXT: .LBB10_7: # %cond.store5 +; SSE4-NEXT: je .LBB10_4 +; SSE4-NEXT: .LBB10_20: # %cond.store5 ; SSE4-NEXT: pextrb $3, %xmm0, 3(%rdi) ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: je .LBB10_10 -; SSE4-NEXT: .LBB10_9: # %cond.store7 +; SSE4-NEXT: je .LBB10_5 +; SSE4-NEXT: .LBB10_21: # %cond.store7 ; SSE4-NEXT: pextrb $4, %xmm0, 4(%rdi) ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: je .LBB10_12 -; SSE4-NEXT: .LBB10_11: # %cond.store9 +; SSE4-NEXT: je .LBB10_6 +; SSE4-NEXT: .LBB10_22: # %cond.store9 ; SSE4-NEXT: pextrb $5, %xmm0, 5(%rdi) ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: je .LBB10_14 -; SSE4-NEXT: .LBB10_13: # %cond.store11 +; SSE4-NEXT: je .LBB10_7 +; SSE4-NEXT: .LBB10_23: # %cond.store11 ; SSE4-NEXT: pextrb $6, %xmm0, 6(%rdi) ; SSE4-NEXT: testb %al, %al -; SSE4-NEXT: jns .LBB10_16 -; SSE4-NEXT: .LBB10_15: # %cond.store13 +; SSE4-NEXT: jns .LBB10_8 +; SSE4-NEXT: .LBB10_24: # %cond.store13 ; SSE4-NEXT: pextrb $7, %xmm0, 7(%rdi) ; SSE4-NEXT: testl $256, %eax # imm = 0x100 -; SSE4-NEXT: je .LBB10_18 -; SSE4-NEXT: .LBB10_17: # %cond.store15 +; SSE4-NEXT: je .LBB10_9 +; SSE4-NEXT: .LBB10_25: # %cond.store15 ; SSE4-NEXT: pextrb $8, %xmm0, 8(%rdi) ; SSE4-NEXT: testl $512, %eax # imm = 0x200 -; SSE4-NEXT: je .LBB10_20 -; SSE4-NEXT: .LBB10_19: # %cond.store17 +; SSE4-NEXT: je .LBB10_10 +; SSE4-NEXT: .LBB10_26: # %cond.store17 ; SSE4-NEXT: pextrb $9, %xmm0, 9(%rdi) ; SSE4-NEXT: testl $1024, %eax # imm = 0x400 -; SSE4-NEXT: je .LBB10_22 -; SSE4-NEXT: .LBB10_21: # %cond.store19 +; SSE4-NEXT: je .LBB10_11 +; SSE4-NEXT: .LBB10_27: # %cond.store19 ; SSE4-NEXT: pextrb $10, %xmm0, 10(%rdi) ; SSE4-NEXT: testl $2048, %eax # imm = 0x800 -; SSE4-NEXT: je .LBB10_24 -; SSE4-NEXT: .LBB10_23: # %cond.store21 +; SSE4-NEXT: je .LBB10_12 +; SSE4-NEXT: .LBB10_28: # %cond.store21 ; SSE4-NEXT: pextrb $11, %xmm0, 11(%rdi) ; SSE4-NEXT: testl $4096, %eax # imm = 0x1000 -; SSE4-NEXT: je .LBB10_26 -; SSE4-NEXT: .LBB10_25: # %cond.store23 +; SSE4-NEXT: je .LBB10_13 +; SSE4-NEXT: .LBB10_29: # %cond.store23 ; SSE4-NEXT: pextrb $12, %xmm0, 12(%rdi) ; SSE4-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE4-NEXT: je .LBB10_28 -; SSE4-NEXT: .LBB10_27: # %cond.store25 +; SSE4-NEXT: je .LBB10_14 +; SSE4-NEXT: .LBB10_30: # %cond.store25 ; SSE4-NEXT: pextrb $13, %xmm0, 13(%rdi) ; SSE4-NEXT: testl $16384, %eax # imm = 0x4000 -; SSE4-NEXT: je .LBB10_30 -; SSE4-NEXT: .LBB10_29: # %cond.store27 +; SSE4-NEXT: je .LBB10_15 +; SSE4-NEXT: .LBB10_31: # %cond.store27 ; SSE4-NEXT: pextrb $14, %xmm0, 14(%rdi) ; SSE4-NEXT: testl $32768, %eax # imm = 0x8000 -; SSE4-NEXT: je .LBB10_32 -; SSE4-NEXT: .LBB10_31: # %cond.store29 +; SSE4-NEXT: je .LBB10_16 +; SSE4-NEXT: .LBB10_32: # %cond.store29 ; SSE4-NEXT: pextrb $15, %xmm0, 15(%rdi) ; SSE4-NEXT: retq ; @@ -3792,116 +3792,116 @@ define void @truncstore_v16i32_v16i8(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; AVX1-NEXT: vpmovmskb %xmm1, %eax ; AVX1-NEXT: xorl $65535, %eax # imm = 0xFFFF ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne .LBB10_1 -; AVX1-NEXT: # %bb.2: # %else +; AVX1-NEXT: jne .LBB10_17 +; AVX1-NEXT: # %bb.1: # %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne .LBB10_3 -; AVX1-NEXT: .LBB10_4: # %else2 +; AVX1-NEXT: jne .LBB10_18 +; AVX1-NEXT: .LBB10_2: # %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne .LBB10_5 -; AVX1-NEXT: .LBB10_6: # %else4 +; AVX1-NEXT: jne .LBB10_19 +; AVX1-NEXT: .LBB10_3: # %else4 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne .LBB10_7 -; AVX1-NEXT: .LBB10_8: # %else6 +; AVX1-NEXT: jne .LBB10_20 +; AVX1-NEXT: .LBB10_4: # %else6 ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: jne .LBB10_9 -; AVX1-NEXT: .LBB10_10: # %else8 +; AVX1-NEXT: jne .LBB10_21 +; AVX1-NEXT: .LBB10_5: # %else8 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: jne .LBB10_11 -; AVX1-NEXT: .LBB10_12: # %else10 +; AVX1-NEXT: jne .LBB10_22 +; AVX1-NEXT: .LBB10_6: # %else10 ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: jne .LBB10_13 -; AVX1-NEXT: .LBB10_14: # %else12 +; AVX1-NEXT: jne .LBB10_23 +; AVX1-NEXT: .LBB10_7: # %else12 ; AVX1-NEXT: testb %al, %al -; AVX1-NEXT: js .LBB10_15 -; AVX1-NEXT: .LBB10_16: # %else14 +; AVX1-NEXT: js .LBB10_24 +; AVX1-NEXT: .LBB10_8: # %else14 ; AVX1-NEXT: testl $256, %eax # imm = 0x100 -; AVX1-NEXT: jne .LBB10_17 -; AVX1-NEXT: .LBB10_18: # %else16 +; AVX1-NEXT: jne .LBB10_25 +; AVX1-NEXT: .LBB10_9: # %else16 ; AVX1-NEXT: testl $512, %eax # imm = 0x200 -; AVX1-NEXT: jne .LBB10_19 -; AVX1-NEXT: .LBB10_20: # %else18 +; AVX1-NEXT: jne .LBB10_26 +; AVX1-NEXT: .LBB10_10: # %else18 ; AVX1-NEXT: testl $1024, %eax # imm = 0x400 -; AVX1-NEXT: jne .LBB10_21 -; AVX1-NEXT: .LBB10_22: # %else20 +; AVX1-NEXT: jne .LBB10_27 +; AVX1-NEXT: .LBB10_11: # %else20 ; AVX1-NEXT: testl $2048, %eax # imm = 0x800 -; AVX1-NEXT: jne .LBB10_23 -; AVX1-NEXT: .LBB10_24: # %else22 +; AVX1-NEXT: jne .LBB10_28 +; AVX1-NEXT: .LBB10_12: # %else22 ; AVX1-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX1-NEXT: jne .LBB10_25 -; AVX1-NEXT: .LBB10_26: # %else24 +; AVX1-NEXT: jne .LBB10_29 +; AVX1-NEXT: .LBB10_13: # %else24 ; AVX1-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX1-NEXT: jne .LBB10_27 -; AVX1-NEXT: .LBB10_28: # %else26 +; AVX1-NEXT: jne .LBB10_30 +; AVX1-NEXT: .LBB10_14: # %else26 ; AVX1-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX1-NEXT: jne .LBB10_29 -; AVX1-NEXT: .LBB10_30: # %else28 -; AVX1-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX1-NEXT: jne .LBB10_31 -; AVX1-NEXT: .LBB10_32: # %else30 +; AVX1-NEXT: .LBB10_15: # %else28 +; AVX1-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX1-NEXT: jne .LBB10_32 +; AVX1-NEXT: .LBB10_16: # %else30 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB10_1: # %cond.store +; AVX1-NEXT: .LBB10_17: # %cond.store ; AVX1-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je .LBB10_4 -; AVX1-NEXT: .LBB10_3: # %cond.store1 +; AVX1-NEXT: je .LBB10_2 +; AVX1-NEXT: .LBB10_18: # %cond.store1 ; AVX1-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je .LBB10_6 -; AVX1-NEXT: .LBB10_5: # %cond.store3 +; AVX1-NEXT: je .LBB10_3 +; AVX1-NEXT: .LBB10_19: # %cond.store3 ; AVX1-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB10_8 -; AVX1-NEXT: .LBB10_7: # %cond.store5 +; AVX1-NEXT: je .LBB10_4 +; AVX1-NEXT: .LBB10_20: # %cond.store5 ; AVX1-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: je .LBB10_10 -; AVX1-NEXT: .LBB10_9: # %cond.store7 +; AVX1-NEXT: je .LBB10_5 +; AVX1-NEXT: .LBB10_21: # %cond.store7 ; AVX1-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je .LBB10_12 -; AVX1-NEXT: .LBB10_11: # %cond.store9 +; AVX1-NEXT: je .LBB10_6 +; AVX1-NEXT: .LBB10_22: # %cond.store9 ; AVX1-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: je .LBB10_14 -; AVX1-NEXT: .LBB10_13: # %cond.store11 +; AVX1-NEXT: je .LBB10_7 +; AVX1-NEXT: .LBB10_23: # %cond.store11 ; AVX1-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX1-NEXT: testb %al, %al -; AVX1-NEXT: jns .LBB10_16 -; AVX1-NEXT: .LBB10_15: # %cond.store13 +; AVX1-NEXT: jns .LBB10_8 +; AVX1-NEXT: .LBB10_24: # %cond.store13 ; AVX1-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX1-NEXT: testl $256, %eax # imm = 0x100 -; AVX1-NEXT: je .LBB10_18 -; AVX1-NEXT: .LBB10_17: # %cond.store15 +; AVX1-NEXT: je .LBB10_9 +; AVX1-NEXT: .LBB10_25: # %cond.store15 ; AVX1-NEXT: vpextrb $8, %xmm0, 8(%rdi) ; AVX1-NEXT: testl $512, %eax # imm = 0x200 -; AVX1-NEXT: je .LBB10_20 -; AVX1-NEXT: .LBB10_19: # %cond.store17 +; AVX1-NEXT: je .LBB10_10 +; AVX1-NEXT: .LBB10_26: # %cond.store17 ; AVX1-NEXT: vpextrb $9, %xmm0, 9(%rdi) ; AVX1-NEXT: testl $1024, %eax # imm = 0x400 -; AVX1-NEXT: je .LBB10_22 -; AVX1-NEXT: .LBB10_21: # %cond.store19 +; AVX1-NEXT: je .LBB10_11 +; AVX1-NEXT: .LBB10_27: # %cond.store19 ; AVX1-NEXT: vpextrb $10, %xmm0, 10(%rdi) ; AVX1-NEXT: testl $2048, %eax # imm = 0x800 -; AVX1-NEXT: je .LBB10_24 -; AVX1-NEXT: .LBB10_23: # %cond.store21 +; AVX1-NEXT: je .LBB10_12 +; AVX1-NEXT: .LBB10_28: # %cond.store21 ; AVX1-NEXT: vpextrb $11, %xmm0, 11(%rdi) ; AVX1-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX1-NEXT: je .LBB10_26 -; AVX1-NEXT: .LBB10_25: # %cond.store23 +; AVX1-NEXT: je .LBB10_13 +; AVX1-NEXT: .LBB10_29: # %cond.store23 ; AVX1-NEXT: vpextrb $12, %xmm0, 12(%rdi) ; AVX1-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX1-NEXT: je .LBB10_28 -; AVX1-NEXT: .LBB10_27: # %cond.store25 +; AVX1-NEXT: je .LBB10_14 +; AVX1-NEXT: .LBB10_30: # %cond.store25 ; AVX1-NEXT: vpextrb $13, %xmm0, 13(%rdi) ; AVX1-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX1-NEXT: je .LBB10_30 -; AVX1-NEXT: .LBB10_29: # %cond.store27 +; AVX1-NEXT: je .LBB10_15 +; AVX1-NEXT: .LBB10_31: # %cond.store27 ; AVX1-NEXT: vpextrb $14, %xmm0, 14(%rdi) ; AVX1-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX1-NEXT: je .LBB10_32 -; AVX1-NEXT: .LBB10_31: # %cond.store29 +; AVX1-NEXT: je .LBB10_16 +; AVX1-NEXT: .LBB10_32: # %cond.store29 ; AVX1-NEXT: vpextrb $15, %xmm0, 15(%rdi) ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq @@ -3926,116 +3926,116 @@ define void @truncstore_v16i32_v16i8(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,2,1,3] ; AVX2-NEXT: vpmovmskb %xmm1, %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne .LBB10_1 -; AVX2-NEXT: # %bb.2: # %else +; AVX2-NEXT: jne .LBB10_17 +; AVX2-NEXT: # %bb.1: # %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne .LBB10_3 -; AVX2-NEXT: .LBB10_4: # %else2 +; AVX2-NEXT: jne .LBB10_18 +; AVX2-NEXT: .LBB10_2: # %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne .LBB10_5 -; AVX2-NEXT: .LBB10_6: # %else4 +; AVX2-NEXT: jne .LBB10_19 +; AVX2-NEXT: .LBB10_3: # %else4 ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: jne .LBB10_7 -; AVX2-NEXT: .LBB10_8: # %else6 +; AVX2-NEXT: jne .LBB10_20 +; AVX2-NEXT: .LBB10_4: # %else6 ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: jne .LBB10_9 -; AVX2-NEXT: .LBB10_10: # %else8 +; AVX2-NEXT: jne .LBB10_21 +; AVX2-NEXT: .LBB10_5: # %else8 ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: jne .LBB10_11 -; AVX2-NEXT: .LBB10_12: # %else10 +; AVX2-NEXT: jne .LBB10_22 +; AVX2-NEXT: .LBB10_6: # %else10 ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: jne .LBB10_13 -; AVX2-NEXT: .LBB10_14: # %else12 +; AVX2-NEXT: jne .LBB10_23 +; AVX2-NEXT: .LBB10_7: # %else12 ; AVX2-NEXT: testb %al, %al -; AVX2-NEXT: js .LBB10_15 -; AVX2-NEXT: .LBB10_16: # %else14 +; AVX2-NEXT: js .LBB10_24 +; AVX2-NEXT: .LBB10_8: # %else14 ; AVX2-NEXT: testl $256, %eax # imm = 0x100 -; AVX2-NEXT: jne .LBB10_17 -; AVX2-NEXT: .LBB10_18: # %else16 +; AVX2-NEXT: jne .LBB10_25 +; AVX2-NEXT: .LBB10_9: # %else16 ; AVX2-NEXT: testl $512, %eax # imm = 0x200 -; AVX2-NEXT: jne .LBB10_19 -; AVX2-NEXT: .LBB10_20: # %else18 +; AVX2-NEXT: jne .LBB10_26 +; AVX2-NEXT: .LBB10_10: # %else18 ; AVX2-NEXT: testl $1024, %eax # imm = 0x400 -; AVX2-NEXT: jne .LBB10_21 -; AVX2-NEXT: .LBB10_22: # %else20 +; AVX2-NEXT: jne .LBB10_27 +; AVX2-NEXT: .LBB10_11: # %else20 ; AVX2-NEXT: testl $2048, %eax # imm = 0x800 -; AVX2-NEXT: jne .LBB10_23 -; AVX2-NEXT: .LBB10_24: # %else22 +; AVX2-NEXT: jne .LBB10_28 +; AVX2-NEXT: .LBB10_12: # %else22 ; AVX2-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX2-NEXT: jne .LBB10_25 -; AVX2-NEXT: .LBB10_26: # %else24 +; AVX2-NEXT: jne .LBB10_29 +; AVX2-NEXT: .LBB10_13: # %else24 ; AVX2-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX2-NEXT: jne .LBB10_27 -; AVX2-NEXT: .LBB10_28: # %else26 +; AVX2-NEXT: jne .LBB10_30 +; AVX2-NEXT: .LBB10_14: # %else26 ; AVX2-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX2-NEXT: jne .LBB10_29 -; AVX2-NEXT: .LBB10_30: # %else28 -; AVX2-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX2-NEXT: jne .LBB10_31 -; AVX2-NEXT: .LBB10_32: # %else30 +; AVX2-NEXT: .LBB10_15: # %else28 +; AVX2-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX2-NEXT: jne .LBB10_32 +; AVX2-NEXT: .LBB10_16: # %else30 ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; AVX2-NEXT: .LBB10_1: # %cond.store +; AVX2-NEXT: .LBB10_17: # %cond.store ; AVX2-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je .LBB10_4 -; AVX2-NEXT: .LBB10_3: # %cond.store1 +; AVX2-NEXT: je .LBB10_2 +; AVX2-NEXT: .LBB10_18: # %cond.store1 ; AVX2-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je .LBB10_6 -; AVX2-NEXT: .LBB10_5: # %cond.store3 +; AVX2-NEXT: je .LBB10_3 +; AVX2-NEXT: .LBB10_19: # %cond.store3 ; AVX2-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je .LBB10_8 -; AVX2-NEXT: .LBB10_7: # %cond.store5 +; AVX2-NEXT: je .LBB10_4 +; AVX2-NEXT: .LBB10_20: # %cond.store5 ; AVX2-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: je .LBB10_10 -; AVX2-NEXT: .LBB10_9: # %cond.store7 +; AVX2-NEXT: je .LBB10_5 +; AVX2-NEXT: .LBB10_21: # %cond.store7 ; AVX2-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: je .LBB10_12 -; AVX2-NEXT: .LBB10_11: # %cond.store9 +; AVX2-NEXT: je .LBB10_6 +; AVX2-NEXT: .LBB10_22: # %cond.store9 ; AVX2-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: je .LBB10_14 -; AVX2-NEXT: .LBB10_13: # %cond.store11 +; AVX2-NEXT: je .LBB10_7 +; AVX2-NEXT: .LBB10_23: # %cond.store11 ; AVX2-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX2-NEXT: testb %al, %al -; AVX2-NEXT: jns .LBB10_16 -; AVX2-NEXT: .LBB10_15: # %cond.store13 +; AVX2-NEXT: jns .LBB10_8 +; AVX2-NEXT: .LBB10_24: # %cond.store13 ; AVX2-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX2-NEXT: testl $256, %eax # imm = 0x100 -; AVX2-NEXT: je .LBB10_18 -; AVX2-NEXT: .LBB10_17: # %cond.store15 +; AVX2-NEXT: je .LBB10_9 +; AVX2-NEXT: .LBB10_25: # %cond.store15 ; AVX2-NEXT: vpextrb $8, %xmm0, 8(%rdi) ; AVX2-NEXT: testl $512, %eax # imm = 0x200 -; AVX2-NEXT: je .LBB10_20 -; AVX2-NEXT: .LBB10_19: # %cond.store17 +; AVX2-NEXT: je .LBB10_10 +; AVX2-NEXT: .LBB10_26: # %cond.store17 ; AVX2-NEXT: vpextrb $9, %xmm0, 9(%rdi) ; AVX2-NEXT: testl $1024, %eax # imm = 0x400 -; AVX2-NEXT: je .LBB10_22 -; AVX2-NEXT: .LBB10_21: # %cond.store19 +; AVX2-NEXT: je .LBB10_11 +; AVX2-NEXT: .LBB10_27: # %cond.store19 ; AVX2-NEXT: vpextrb $10, %xmm0, 10(%rdi) ; AVX2-NEXT: testl $2048, %eax # imm = 0x800 -; AVX2-NEXT: je .LBB10_24 -; AVX2-NEXT: .LBB10_23: # %cond.store21 +; AVX2-NEXT: je .LBB10_12 +; AVX2-NEXT: .LBB10_28: # %cond.store21 ; AVX2-NEXT: vpextrb $11, %xmm0, 11(%rdi) ; AVX2-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX2-NEXT: je .LBB10_26 -; AVX2-NEXT: .LBB10_25: # %cond.store23 +; AVX2-NEXT: je .LBB10_13 +; AVX2-NEXT: .LBB10_29: # %cond.store23 ; AVX2-NEXT: vpextrb $12, %xmm0, 12(%rdi) ; AVX2-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX2-NEXT: je .LBB10_28 -; AVX2-NEXT: .LBB10_27: # %cond.store25 +; AVX2-NEXT: je .LBB10_14 +; AVX2-NEXT: .LBB10_30: # %cond.store25 ; AVX2-NEXT: vpextrb $13, %xmm0, 13(%rdi) ; AVX2-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX2-NEXT: je .LBB10_30 -; AVX2-NEXT: .LBB10_29: # %cond.store27 +; AVX2-NEXT: je .LBB10_15 +; AVX2-NEXT: .LBB10_31: # %cond.store27 ; AVX2-NEXT: vpextrb $14, %xmm0, 14(%rdi) ; AVX2-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX2-NEXT: je .LBB10_32 -; AVX2-NEXT: .LBB10_31: # %cond.store29 +; AVX2-NEXT: je .LBB10_16 +; AVX2-NEXT: .LBB10_32: # %cond.store29 ; AVX2-NEXT: vpextrb $15, %xmm0, 15(%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq @@ -4046,116 +4046,116 @@ define void @truncstore_v16i32_v16i8(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; AVX512F-NEXT: vpmovusdb %zmm0, %xmm0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB10_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB10_17 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB10_3 -; AVX512F-NEXT: .LBB10_4: # %else2 +; AVX512F-NEXT: jne .LBB10_18 +; AVX512F-NEXT: .LBB10_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB10_5 -; AVX512F-NEXT: .LBB10_6: # %else4 +; AVX512F-NEXT: jne .LBB10_19 +; AVX512F-NEXT: .LBB10_3: # %else4 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne .LBB10_7 -; AVX512F-NEXT: .LBB10_8: # %else6 +; AVX512F-NEXT: jne .LBB10_20 +; AVX512F-NEXT: .LBB10_4: # %else6 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne .LBB10_9 -; AVX512F-NEXT: .LBB10_10: # %else8 +; AVX512F-NEXT: jne .LBB10_21 +; AVX512F-NEXT: .LBB10_5: # %else8 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne .LBB10_11 -; AVX512F-NEXT: .LBB10_12: # %else10 +; AVX512F-NEXT: jne .LBB10_22 +; AVX512F-NEXT: .LBB10_6: # %else10 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne .LBB10_13 -; AVX512F-NEXT: .LBB10_14: # %else12 +; AVX512F-NEXT: jne .LBB10_23 +; AVX512F-NEXT: .LBB10_7: # %else12 ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: js .LBB10_15 -; AVX512F-NEXT: .LBB10_16: # %else14 +; AVX512F-NEXT: js .LBB10_24 +; AVX512F-NEXT: .LBB10_8: # %else14 ; AVX512F-NEXT: testl $256, %eax # imm = 0x100 -; AVX512F-NEXT: jne .LBB10_17 -; AVX512F-NEXT: .LBB10_18: # %else16 +; AVX512F-NEXT: jne .LBB10_25 +; AVX512F-NEXT: .LBB10_9: # %else16 ; AVX512F-NEXT: testl $512, %eax # imm = 0x200 -; AVX512F-NEXT: jne .LBB10_19 -; AVX512F-NEXT: .LBB10_20: # %else18 +; AVX512F-NEXT: jne .LBB10_26 +; AVX512F-NEXT: .LBB10_10: # %else18 ; AVX512F-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512F-NEXT: jne .LBB10_21 -; AVX512F-NEXT: .LBB10_22: # %else20 +; AVX512F-NEXT: jne .LBB10_27 +; AVX512F-NEXT: .LBB10_11: # %else20 ; AVX512F-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512F-NEXT: jne .LBB10_23 -; AVX512F-NEXT: .LBB10_24: # %else22 +; AVX512F-NEXT: jne .LBB10_28 +; AVX512F-NEXT: .LBB10_12: # %else22 ; AVX512F-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512F-NEXT: jne .LBB10_25 -; AVX512F-NEXT: .LBB10_26: # %else24 +; AVX512F-NEXT: jne .LBB10_29 +; AVX512F-NEXT: .LBB10_13: # %else24 ; AVX512F-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512F-NEXT: jne .LBB10_27 -; AVX512F-NEXT: .LBB10_28: # %else26 +; AVX512F-NEXT: jne .LBB10_30 +; AVX512F-NEXT: .LBB10_14: # %else26 ; AVX512F-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512F-NEXT: jne .LBB10_29 -; AVX512F-NEXT: .LBB10_30: # %else28 -; AVX512F-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX512F-NEXT: jne .LBB10_31 -; AVX512F-NEXT: .LBB10_32: # %else30 +; AVX512F-NEXT: .LBB10_15: # %else28 +; AVX512F-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX512F-NEXT: jne .LBB10_32 +; AVX512F-NEXT: .LBB10_16: # %else30 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB10_1: # %cond.store +; AVX512F-NEXT: .LBB10_17: # %cond.store ; AVX512F-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB10_4 -; AVX512F-NEXT: .LBB10_3: # %cond.store1 +; AVX512F-NEXT: je .LBB10_2 +; AVX512F-NEXT: .LBB10_18: # %cond.store1 ; AVX512F-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB10_6 -; AVX512F-NEXT: .LBB10_5: # %cond.store3 +; AVX512F-NEXT: je .LBB10_3 +; AVX512F-NEXT: .LBB10_19: # %cond.store3 ; AVX512F-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB10_8 -; AVX512F-NEXT: .LBB10_7: # %cond.store5 +; AVX512F-NEXT: je .LBB10_4 +; AVX512F-NEXT: .LBB10_20: # %cond.store5 ; AVX512F-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je .LBB10_10 -; AVX512F-NEXT: .LBB10_9: # %cond.store7 +; AVX512F-NEXT: je .LBB10_5 +; AVX512F-NEXT: .LBB10_21: # %cond.store7 ; AVX512F-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je .LBB10_12 -; AVX512F-NEXT: .LBB10_11: # %cond.store9 +; AVX512F-NEXT: je .LBB10_6 +; AVX512F-NEXT: .LBB10_22: # %cond.store9 ; AVX512F-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je .LBB10_14 -; AVX512F-NEXT: .LBB10_13: # %cond.store11 +; AVX512F-NEXT: je .LBB10_7 +; AVX512F-NEXT: .LBB10_23: # %cond.store11 ; AVX512F-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: jns .LBB10_16 -; AVX512F-NEXT: .LBB10_15: # %cond.store13 +; AVX512F-NEXT: jns .LBB10_8 +; AVX512F-NEXT: .LBB10_24: # %cond.store13 ; AVX512F-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX512F-NEXT: testl $256, %eax # imm = 0x100 -; AVX512F-NEXT: je .LBB10_18 -; AVX512F-NEXT: .LBB10_17: # %cond.store15 +; AVX512F-NEXT: je .LBB10_9 +; AVX512F-NEXT: .LBB10_25: # %cond.store15 ; AVX512F-NEXT: vpextrb $8, %xmm0, 8(%rdi) ; AVX512F-NEXT: testl $512, %eax # imm = 0x200 -; AVX512F-NEXT: je .LBB10_20 -; AVX512F-NEXT: .LBB10_19: # %cond.store17 +; AVX512F-NEXT: je .LBB10_10 +; AVX512F-NEXT: .LBB10_26: # %cond.store17 ; AVX512F-NEXT: vpextrb $9, %xmm0, 9(%rdi) ; AVX512F-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512F-NEXT: je .LBB10_22 -; AVX512F-NEXT: .LBB10_21: # %cond.store19 +; AVX512F-NEXT: je .LBB10_11 +; AVX512F-NEXT: .LBB10_27: # %cond.store19 ; AVX512F-NEXT: vpextrb $10, %xmm0, 10(%rdi) ; AVX512F-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512F-NEXT: je .LBB10_24 -; AVX512F-NEXT: .LBB10_23: # %cond.store21 +; AVX512F-NEXT: je .LBB10_12 +; AVX512F-NEXT: .LBB10_28: # %cond.store21 ; AVX512F-NEXT: vpextrb $11, %xmm0, 11(%rdi) ; AVX512F-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512F-NEXT: je .LBB10_26 -; AVX512F-NEXT: .LBB10_25: # %cond.store23 +; AVX512F-NEXT: je .LBB10_13 +; AVX512F-NEXT: .LBB10_29: # %cond.store23 ; AVX512F-NEXT: vpextrb $12, %xmm0, 12(%rdi) ; AVX512F-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512F-NEXT: je .LBB10_28 -; AVX512F-NEXT: .LBB10_27: # %cond.store25 +; AVX512F-NEXT: je .LBB10_14 +; AVX512F-NEXT: .LBB10_30: # %cond.store25 ; AVX512F-NEXT: vpextrb $13, %xmm0, 13(%rdi) ; AVX512F-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512F-NEXT: je .LBB10_30 -; AVX512F-NEXT: .LBB10_29: # %cond.store27 +; AVX512F-NEXT: je .LBB10_15 +; AVX512F-NEXT: .LBB10_31: # %cond.store27 ; AVX512F-NEXT: vpextrb $14, %xmm0, 14(%rdi) ; AVX512F-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX512F-NEXT: je .LBB10_32 -; AVX512F-NEXT: .LBB10_31: # %cond.store29 +; AVX512F-NEXT: je .LBB10_16 +; AVX512F-NEXT: .LBB10_32: # %cond.store29 ; AVX512F-NEXT: vpextrb $15, %xmm0, 15(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -4166,116 +4166,116 @@ define void @truncstore_v16i32_v16i8(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; AVX512FVL-NEXT: vpmovusdb %zmm0, %xmm0 ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB10_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB10_17 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB10_3 -; AVX512FVL-NEXT: .LBB10_4: # %else2 +; AVX512FVL-NEXT: jne .LBB10_18 +; AVX512FVL-NEXT: .LBB10_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB10_5 -; AVX512FVL-NEXT: .LBB10_6: # %else4 +; AVX512FVL-NEXT: jne .LBB10_19 +; AVX512FVL-NEXT: .LBB10_3: # %else4 ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: jne .LBB10_7 -; AVX512FVL-NEXT: .LBB10_8: # %else6 +; AVX512FVL-NEXT: jne .LBB10_20 +; AVX512FVL-NEXT: .LBB10_4: # %else6 ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: jne .LBB10_9 -; AVX512FVL-NEXT: .LBB10_10: # %else8 +; AVX512FVL-NEXT: jne .LBB10_21 +; AVX512FVL-NEXT: .LBB10_5: # %else8 ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: jne .LBB10_11 -; AVX512FVL-NEXT: .LBB10_12: # %else10 +; AVX512FVL-NEXT: jne .LBB10_22 +; AVX512FVL-NEXT: .LBB10_6: # %else10 ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: jne .LBB10_13 -; AVX512FVL-NEXT: .LBB10_14: # %else12 +; AVX512FVL-NEXT: jne .LBB10_23 +; AVX512FVL-NEXT: .LBB10_7: # %else12 ; AVX512FVL-NEXT: testb %al, %al -; AVX512FVL-NEXT: js .LBB10_15 -; AVX512FVL-NEXT: .LBB10_16: # %else14 +; AVX512FVL-NEXT: js .LBB10_24 +; AVX512FVL-NEXT: .LBB10_8: # %else14 ; AVX512FVL-NEXT: testl $256, %eax # imm = 0x100 -; AVX512FVL-NEXT: jne .LBB10_17 -; AVX512FVL-NEXT: .LBB10_18: # %else16 +; AVX512FVL-NEXT: jne .LBB10_25 +; AVX512FVL-NEXT: .LBB10_9: # %else16 ; AVX512FVL-NEXT: testl $512, %eax # imm = 0x200 -; AVX512FVL-NEXT: jne .LBB10_19 -; AVX512FVL-NEXT: .LBB10_20: # %else18 +; AVX512FVL-NEXT: jne .LBB10_26 +; AVX512FVL-NEXT: .LBB10_10: # %else18 ; AVX512FVL-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512FVL-NEXT: jne .LBB10_21 -; AVX512FVL-NEXT: .LBB10_22: # %else20 +; AVX512FVL-NEXT: jne .LBB10_27 +; AVX512FVL-NEXT: .LBB10_11: # %else20 ; AVX512FVL-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512FVL-NEXT: jne .LBB10_23 -; AVX512FVL-NEXT: .LBB10_24: # %else22 +; AVX512FVL-NEXT: jne .LBB10_28 +; AVX512FVL-NEXT: .LBB10_12: # %else22 ; AVX512FVL-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512FVL-NEXT: jne .LBB10_25 -; AVX512FVL-NEXT: .LBB10_26: # %else24 +; AVX512FVL-NEXT: jne .LBB10_29 +; AVX512FVL-NEXT: .LBB10_13: # %else24 ; AVX512FVL-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512FVL-NEXT: jne .LBB10_27 -; AVX512FVL-NEXT: .LBB10_28: # %else26 +; AVX512FVL-NEXT: jne .LBB10_30 +; AVX512FVL-NEXT: .LBB10_14: # %else26 ; AVX512FVL-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512FVL-NEXT: jne .LBB10_29 -; AVX512FVL-NEXT: .LBB10_30: # %else28 -; AVX512FVL-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX512FVL-NEXT: jne .LBB10_31 -; AVX512FVL-NEXT: .LBB10_32: # %else30 +; AVX512FVL-NEXT: .LBB10_15: # %else28 +; AVX512FVL-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX512FVL-NEXT: jne .LBB10_32 +; AVX512FVL-NEXT: .LBB10_16: # %else30 ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB10_1: # %cond.store +; AVX512FVL-NEXT: .LBB10_17: # %cond.store ; AVX512FVL-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB10_4 -; AVX512FVL-NEXT: .LBB10_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB10_2 +; AVX512FVL-NEXT: .LBB10_18: # %cond.store1 ; AVX512FVL-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB10_6 -; AVX512FVL-NEXT: .LBB10_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB10_3 +; AVX512FVL-NEXT: .LBB10_19: # %cond.store3 ; AVX512FVL-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB10_8 -; AVX512FVL-NEXT: .LBB10_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB10_4 +; AVX512FVL-NEXT: .LBB10_20: # %cond.store5 ; AVX512FVL-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: je .LBB10_10 -; AVX512FVL-NEXT: .LBB10_9: # %cond.store7 +; AVX512FVL-NEXT: je .LBB10_5 +; AVX512FVL-NEXT: .LBB10_21: # %cond.store7 ; AVX512FVL-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: je .LBB10_12 -; AVX512FVL-NEXT: .LBB10_11: # %cond.store9 +; AVX512FVL-NEXT: je .LBB10_6 +; AVX512FVL-NEXT: .LBB10_22: # %cond.store9 ; AVX512FVL-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: je .LBB10_14 -; AVX512FVL-NEXT: .LBB10_13: # %cond.store11 +; AVX512FVL-NEXT: je .LBB10_7 +; AVX512FVL-NEXT: .LBB10_23: # %cond.store11 ; AVX512FVL-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX512FVL-NEXT: testb %al, %al -; AVX512FVL-NEXT: jns .LBB10_16 -; AVX512FVL-NEXT: .LBB10_15: # %cond.store13 +; AVX512FVL-NEXT: jns .LBB10_8 +; AVX512FVL-NEXT: .LBB10_24: # %cond.store13 ; AVX512FVL-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX512FVL-NEXT: testl $256, %eax # imm = 0x100 -; AVX512FVL-NEXT: je .LBB10_18 -; AVX512FVL-NEXT: .LBB10_17: # %cond.store15 +; AVX512FVL-NEXT: je .LBB10_9 +; AVX512FVL-NEXT: .LBB10_25: # %cond.store15 ; AVX512FVL-NEXT: vpextrb $8, %xmm0, 8(%rdi) ; AVX512FVL-NEXT: testl $512, %eax # imm = 0x200 -; AVX512FVL-NEXT: je .LBB10_20 -; AVX512FVL-NEXT: .LBB10_19: # %cond.store17 +; AVX512FVL-NEXT: je .LBB10_10 +; AVX512FVL-NEXT: .LBB10_26: # %cond.store17 ; AVX512FVL-NEXT: vpextrb $9, %xmm0, 9(%rdi) ; AVX512FVL-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512FVL-NEXT: je .LBB10_22 -; AVX512FVL-NEXT: .LBB10_21: # %cond.store19 +; AVX512FVL-NEXT: je .LBB10_11 +; AVX512FVL-NEXT: .LBB10_27: # %cond.store19 ; AVX512FVL-NEXT: vpextrb $10, %xmm0, 10(%rdi) ; AVX512FVL-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512FVL-NEXT: je .LBB10_24 -; AVX512FVL-NEXT: .LBB10_23: # %cond.store21 +; AVX512FVL-NEXT: je .LBB10_12 +; AVX512FVL-NEXT: .LBB10_28: # %cond.store21 ; AVX512FVL-NEXT: vpextrb $11, %xmm0, 11(%rdi) ; AVX512FVL-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512FVL-NEXT: je .LBB10_26 -; AVX512FVL-NEXT: .LBB10_25: # %cond.store23 +; AVX512FVL-NEXT: je .LBB10_13 +; AVX512FVL-NEXT: .LBB10_29: # %cond.store23 ; AVX512FVL-NEXT: vpextrb $12, %xmm0, 12(%rdi) ; AVX512FVL-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512FVL-NEXT: je .LBB10_28 -; AVX512FVL-NEXT: .LBB10_27: # %cond.store25 +; AVX512FVL-NEXT: je .LBB10_14 +; AVX512FVL-NEXT: .LBB10_30: # %cond.store25 ; AVX512FVL-NEXT: vpextrb $13, %xmm0, 13(%rdi) ; AVX512FVL-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512FVL-NEXT: je .LBB10_30 -; AVX512FVL-NEXT: .LBB10_29: # %cond.store27 +; AVX512FVL-NEXT: je .LBB10_15 +; AVX512FVL-NEXT: .LBB10_31: # %cond.store27 ; AVX512FVL-NEXT: vpextrb $14, %xmm0, 14(%rdi) ; AVX512FVL-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX512FVL-NEXT: je .LBB10_32 -; AVX512FVL-NEXT: .LBB10_31: # %cond.store29 +; AVX512FVL-NEXT: je .LBB10_16 +; AVX512FVL-NEXT: .LBB10_32: # %cond.store29 ; AVX512FVL-NEXT: vpextrb $15, %xmm0, 15(%rdi) ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq @@ -4332,66 +4332,66 @@ define void @truncstore_v8i32_v8i16(<8 x i32> %x, ptr %p, <8 x i32> %mask) { ; SSE2-NEXT: pmovmskb %xmm2, %eax ; SSE2-NEXT: notl %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne .LBB11_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB11_9 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne .LBB11_3 -; SSE2-NEXT: .LBB11_4: # %else2 +; SSE2-NEXT: jne .LBB11_10 +; SSE2-NEXT: .LBB11_2: # %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne .LBB11_5 -; SSE2-NEXT: .LBB11_6: # %else4 +; SSE2-NEXT: jne .LBB11_11 +; SSE2-NEXT: .LBB11_3: # %else4 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne .LBB11_7 -; SSE2-NEXT: .LBB11_8: # %else6 +; SSE2-NEXT: jne .LBB11_12 +; SSE2-NEXT: .LBB11_4: # %else6 ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: jne .LBB11_9 -; SSE2-NEXT: .LBB11_10: # %else8 +; SSE2-NEXT: jne .LBB11_13 +; SSE2-NEXT: .LBB11_5: # %else8 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: jne .LBB11_11 -; SSE2-NEXT: .LBB11_12: # %else10 +; SSE2-NEXT: jne .LBB11_14 +; SSE2-NEXT: .LBB11_6: # %else10 ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: jne .LBB11_13 -; SSE2-NEXT: .LBB11_14: # %else12 -; SSE2-NEXT: testb $-128, %al ; SSE2-NEXT: jne .LBB11_15 -; SSE2-NEXT: .LBB11_16: # %else14 +; SSE2-NEXT: .LBB11_7: # %else12 +; SSE2-NEXT: testb $-128, %al +; SSE2-NEXT: jne .LBB11_16 +; SSE2-NEXT: .LBB11_8: # %else14 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB11_1: # %cond.store +; SSE2-NEXT: .LBB11_9: # %cond.store ; SSE2-NEXT: movd %xmm4, %ecx ; SSE2-NEXT: movw %cx, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB11_4 -; SSE2-NEXT: .LBB11_3: # %cond.store1 +; SSE2-NEXT: je .LBB11_2 +; SSE2-NEXT: .LBB11_10: # %cond.store1 ; SSE2-NEXT: pextrw $1, %xmm4, %ecx ; SSE2-NEXT: movw %cx, 2(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je .LBB11_6 -; SSE2-NEXT: .LBB11_5: # %cond.store3 +; SSE2-NEXT: je .LBB11_3 +; SSE2-NEXT: .LBB11_11: # %cond.store3 ; SSE2-NEXT: pextrw $2, %xmm4, %ecx ; SSE2-NEXT: movw %cx, 4(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je .LBB11_8 -; SSE2-NEXT: .LBB11_7: # %cond.store5 +; SSE2-NEXT: je .LBB11_4 +; SSE2-NEXT: .LBB11_12: # %cond.store5 ; SSE2-NEXT: pextrw $3, %xmm4, %ecx ; SSE2-NEXT: movw %cx, 6(%rdi) ; SSE2-NEXT: testb $16, %al -; SSE2-NEXT: je .LBB11_10 -; SSE2-NEXT: .LBB11_9: # %cond.store7 +; SSE2-NEXT: je .LBB11_5 +; SSE2-NEXT: .LBB11_13: # %cond.store7 ; SSE2-NEXT: pextrw $4, %xmm4, %ecx ; SSE2-NEXT: movw %cx, 8(%rdi) ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je .LBB11_12 -; SSE2-NEXT: .LBB11_11: # %cond.store9 +; SSE2-NEXT: je .LBB11_6 +; SSE2-NEXT: .LBB11_14: # %cond.store9 ; SSE2-NEXT: pextrw $5, %xmm4, %ecx ; SSE2-NEXT: movw %cx, 10(%rdi) ; SSE2-NEXT: testb $64, %al -; SSE2-NEXT: je .LBB11_14 -; SSE2-NEXT: .LBB11_13: # %cond.store11 +; SSE2-NEXT: je .LBB11_7 +; SSE2-NEXT: .LBB11_15: # %cond.store11 ; SSE2-NEXT: pextrw $6, %xmm4, %ecx ; SSE2-NEXT: movw %cx, 12(%rdi) ; SSE2-NEXT: testb $-128, %al -; SSE2-NEXT: je .LBB11_16 -; SSE2-NEXT: .LBB11_15: # %cond.store13 +; SSE2-NEXT: je .LBB11_8 +; SSE2-NEXT: .LBB11_16: # %cond.store13 ; SSE2-NEXT: pextrw $7, %xmm4, %eax ; SSE2-NEXT: movw %ax, 14(%rdi) ; SSE2-NEXT: retq @@ -4410,59 +4410,59 @@ define void @truncstore_v8i32_v8i16(<8 x i32> %x, ptr %p, <8 x i32> %mask) { ; SSE4-NEXT: pmovmskb %xmm2, %eax ; SSE4-NEXT: notl %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB11_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB11_9 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB11_3 -; SSE4-NEXT: .LBB11_4: # %else2 +; SSE4-NEXT: jne .LBB11_10 +; SSE4-NEXT: .LBB11_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB11_5 -; SSE4-NEXT: .LBB11_6: # %else4 +; SSE4-NEXT: jne .LBB11_11 +; SSE4-NEXT: .LBB11_3: # %else4 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne .LBB11_7 -; SSE4-NEXT: .LBB11_8: # %else6 +; SSE4-NEXT: jne .LBB11_12 +; SSE4-NEXT: .LBB11_4: # %else6 ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: jne .LBB11_9 -; SSE4-NEXT: .LBB11_10: # %else8 +; SSE4-NEXT: jne .LBB11_13 +; SSE4-NEXT: .LBB11_5: # %else8 ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: jne .LBB11_11 -; SSE4-NEXT: .LBB11_12: # %else10 +; SSE4-NEXT: jne .LBB11_14 +; SSE4-NEXT: .LBB11_6: # %else10 ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: jne .LBB11_13 -; SSE4-NEXT: .LBB11_14: # %else12 -; SSE4-NEXT: testb $-128, %al ; SSE4-NEXT: jne .LBB11_15 -; SSE4-NEXT: .LBB11_16: # %else14 +; SSE4-NEXT: .LBB11_7: # %else12 +; SSE4-NEXT: testb $-128, %al +; SSE4-NEXT: jne .LBB11_16 +; SSE4-NEXT: .LBB11_8: # %else14 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB11_1: # %cond.store +; SSE4-NEXT: .LBB11_9: # %cond.store ; SSE4-NEXT: pextrw $0, %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB11_4 -; SSE4-NEXT: .LBB11_3: # %cond.store1 +; SSE4-NEXT: je .LBB11_2 +; SSE4-NEXT: .LBB11_10: # %cond.store1 ; SSE4-NEXT: pextrw $1, %xmm0, 2(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB11_6 -; SSE4-NEXT: .LBB11_5: # %cond.store3 +; SSE4-NEXT: je .LBB11_3 +; SSE4-NEXT: .LBB11_11: # %cond.store3 ; SSE4-NEXT: pextrw $2, %xmm0, 4(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB11_8 -; SSE4-NEXT: .LBB11_7: # %cond.store5 +; SSE4-NEXT: je .LBB11_4 +; SSE4-NEXT: .LBB11_12: # %cond.store5 ; SSE4-NEXT: pextrw $3, %xmm0, 6(%rdi) ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: je .LBB11_10 -; SSE4-NEXT: .LBB11_9: # %cond.store7 +; SSE4-NEXT: je .LBB11_5 +; SSE4-NEXT: .LBB11_13: # %cond.store7 ; SSE4-NEXT: pextrw $4, %xmm0, 8(%rdi) ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: je .LBB11_12 -; SSE4-NEXT: .LBB11_11: # %cond.store9 +; SSE4-NEXT: je .LBB11_6 +; SSE4-NEXT: .LBB11_14: # %cond.store9 ; SSE4-NEXT: pextrw $5, %xmm0, 10(%rdi) ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: je .LBB11_14 -; SSE4-NEXT: .LBB11_13: # %cond.store11 +; SSE4-NEXT: je .LBB11_7 +; SSE4-NEXT: .LBB11_15: # %cond.store11 ; SSE4-NEXT: pextrw $6, %xmm0, 12(%rdi) ; SSE4-NEXT: testb $-128, %al -; SSE4-NEXT: je .LBB11_16 -; SSE4-NEXT: .LBB11_15: # %cond.store13 +; SSE4-NEXT: je .LBB11_8 +; SSE4-NEXT: .LBB11_16: # %cond.store13 ; SSE4-NEXT: pextrw $7, %xmm0, 14(%rdi) ; SSE4-NEXT: retq ; @@ -4481,60 +4481,60 @@ define void @truncstore_v8i32_v8i16(<8 x i32> %x, ptr %p, <8 x i32> %mask) { ; AVX1-NEXT: vmovmskps %ymm1, %eax ; AVX1-NEXT: notl %eax ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne .LBB11_1 -; AVX1-NEXT: # %bb.2: # %else +; AVX1-NEXT: jne .LBB11_9 +; AVX1-NEXT: # %bb.1: # %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne .LBB11_3 -; AVX1-NEXT: .LBB11_4: # %else2 +; AVX1-NEXT: jne .LBB11_10 +; AVX1-NEXT: .LBB11_2: # %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne .LBB11_5 -; AVX1-NEXT: .LBB11_6: # %else4 +; AVX1-NEXT: jne .LBB11_11 +; AVX1-NEXT: .LBB11_3: # %else4 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne .LBB11_7 -; AVX1-NEXT: .LBB11_8: # %else6 +; AVX1-NEXT: jne .LBB11_12 +; AVX1-NEXT: .LBB11_4: # %else6 ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: jne .LBB11_9 -; AVX1-NEXT: .LBB11_10: # %else8 +; AVX1-NEXT: jne .LBB11_13 +; AVX1-NEXT: .LBB11_5: # %else8 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: jne .LBB11_11 -; AVX1-NEXT: .LBB11_12: # %else10 +; AVX1-NEXT: jne .LBB11_14 +; AVX1-NEXT: .LBB11_6: # %else10 ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: jne .LBB11_13 -; AVX1-NEXT: .LBB11_14: # %else12 -; AVX1-NEXT: testb $-128, %al ; AVX1-NEXT: jne .LBB11_15 -; AVX1-NEXT: .LBB11_16: # %else14 +; AVX1-NEXT: .LBB11_7: # %else12 +; AVX1-NEXT: testb $-128, %al +; AVX1-NEXT: jne .LBB11_16 +; AVX1-NEXT: .LBB11_8: # %else14 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB11_1: # %cond.store +; AVX1-NEXT: .LBB11_9: # %cond.store ; AVX1-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je .LBB11_4 -; AVX1-NEXT: .LBB11_3: # %cond.store1 +; AVX1-NEXT: je .LBB11_2 +; AVX1-NEXT: .LBB11_10: # %cond.store1 ; AVX1-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je .LBB11_6 -; AVX1-NEXT: .LBB11_5: # %cond.store3 +; AVX1-NEXT: je .LBB11_3 +; AVX1-NEXT: .LBB11_11: # %cond.store3 ; AVX1-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB11_8 -; AVX1-NEXT: .LBB11_7: # %cond.store5 +; AVX1-NEXT: je .LBB11_4 +; AVX1-NEXT: .LBB11_12: # %cond.store5 ; AVX1-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: je .LBB11_10 -; AVX1-NEXT: .LBB11_9: # %cond.store7 +; AVX1-NEXT: je .LBB11_5 +; AVX1-NEXT: .LBB11_13: # %cond.store7 ; AVX1-NEXT: vpextrw $4, %xmm0, 8(%rdi) ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je .LBB11_12 -; AVX1-NEXT: .LBB11_11: # %cond.store9 +; AVX1-NEXT: je .LBB11_6 +; AVX1-NEXT: .LBB11_14: # %cond.store9 ; AVX1-NEXT: vpextrw $5, %xmm0, 10(%rdi) ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: je .LBB11_14 -; AVX1-NEXT: .LBB11_13: # %cond.store11 +; AVX1-NEXT: je .LBB11_7 +; AVX1-NEXT: .LBB11_15: # %cond.store11 ; AVX1-NEXT: vpextrw $6, %xmm0, 12(%rdi) ; AVX1-NEXT: testb $-128, %al -; AVX1-NEXT: je .LBB11_16 -; AVX1-NEXT: .LBB11_15: # %cond.store13 +; AVX1-NEXT: je .LBB11_8 +; AVX1-NEXT: .LBB11_16: # %cond.store13 ; AVX1-NEXT: vpextrw $7, %xmm0, 14(%rdi) ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq @@ -4550,60 +4550,60 @@ define void @truncstore_v8i32_v8i16(<8 x i32> %x, ptr %p, <8 x i32> %mask) { ; AVX2-NEXT: vmovmskps %ymm1, %eax ; AVX2-NEXT: notl %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne .LBB11_1 -; AVX2-NEXT: # %bb.2: # %else +; AVX2-NEXT: jne .LBB11_9 +; AVX2-NEXT: # %bb.1: # %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne .LBB11_3 -; AVX2-NEXT: .LBB11_4: # %else2 +; AVX2-NEXT: jne .LBB11_10 +; AVX2-NEXT: .LBB11_2: # %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne .LBB11_5 -; AVX2-NEXT: .LBB11_6: # %else4 +; AVX2-NEXT: jne .LBB11_11 +; AVX2-NEXT: .LBB11_3: # %else4 ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: jne .LBB11_7 -; AVX2-NEXT: .LBB11_8: # %else6 +; AVX2-NEXT: jne .LBB11_12 +; AVX2-NEXT: .LBB11_4: # %else6 ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: jne .LBB11_9 -; AVX2-NEXT: .LBB11_10: # %else8 +; AVX2-NEXT: jne .LBB11_13 +; AVX2-NEXT: .LBB11_5: # %else8 ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: jne .LBB11_11 -; AVX2-NEXT: .LBB11_12: # %else10 +; AVX2-NEXT: jne .LBB11_14 +; AVX2-NEXT: .LBB11_6: # %else10 ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: jne .LBB11_13 -; AVX2-NEXT: .LBB11_14: # %else12 -; AVX2-NEXT: testb $-128, %al ; AVX2-NEXT: jne .LBB11_15 -; AVX2-NEXT: .LBB11_16: # %else14 +; AVX2-NEXT: .LBB11_7: # %else12 +; AVX2-NEXT: testb $-128, %al +; AVX2-NEXT: jne .LBB11_16 +; AVX2-NEXT: .LBB11_8: # %else14 ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; AVX2-NEXT: .LBB11_1: # %cond.store +; AVX2-NEXT: .LBB11_9: # %cond.store ; AVX2-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je .LBB11_4 -; AVX2-NEXT: .LBB11_3: # %cond.store1 +; AVX2-NEXT: je .LBB11_2 +; AVX2-NEXT: .LBB11_10: # %cond.store1 ; AVX2-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je .LBB11_6 -; AVX2-NEXT: .LBB11_5: # %cond.store3 +; AVX2-NEXT: je .LBB11_3 +; AVX2-NEXT: .LBB11_11: # %cond.store3 ; AVX2-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je .LBB11_8 -; AVX2-NEXT: .LBB11_7: # %cond.store5 +; AVX2-NEXT: je .LBB11_4 +; AVX2-NEXT: .LBB11_12: # %cond.store5 ; AVX2-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: je .LBB11_10 -; AVX2-NEXT: .LBB11_9: # %cond.store7 +; AVX2-NEXT: je .LBB11_5 +; AVX2-NEXT: .LBB11_13: # %cond.store7 ; AVX2-NEXT: vpextrw $4, %xmm0, 8(%rdi) ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: je .LBB11_12 -; AVX2-NEXT: .LBB11_11: # %cond.store9 +; AVX2-NEXT: je .LBB11_6 +; AVX2-NEXT: .LBB11_14: # %cond.store9 ; AVX2-NEXT: vpextrw $5, %xmm0, 10(%rdi) ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: je .LBB11_14 -; AVX2-NEXT: .LBB11_13: # %cond.store11 +; AVX2-NEXT: je .LBB11_7 +; AVX2-NEXT: .LBB11_15: # %cond.store11 ; AVX2-NEXT: vpextrw $6, %xmm0, 12(%rdi) ; AVX2-NEXT: testb $-128, %al -; AVX2-NEXT: je .LBB11_16 -; AVX2-NEXT: .LBB11_15: # %cond.store13 +; AVX2-NEXT: je .LBB11_8 +; AVX2-NEXT: .LBB11_16: # %cond.store13 ; AVX2-NEXT: vpextrw $7, %xmm0, 14(%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq @@ -4616,60 +4616,60 @@ define void @truncstore_v8i32_v8i16(<8 x i32> %x, ptr %p, <8 x i32> %mask) { ; AVX512F-NEXT: vpmovusdw %zmm0, %ymm0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB11_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB11_9 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB11_3 -; AVX512F-NEXT: .LBB11_4: # %else2 +; AVX512F-NEXT: jne .LBB11_10 +; AVX512F-NEXT: .LBB11_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB11_5 -; AVX512F-NEXT: .LBB11_6: # %else4 +; AVX512F-NEXT: jne .LBB11_11 +; AVX512F-NEXT: .LBB11_3: # %else4 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne .LBB11_7 -; AVX512F-NEXT: .LBB11_8: # %else6 +; AVX512F-NEXT: jne .LBB11_12 +; AVX512F-NEXT: .LBB11_4: # %else6 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne .LBB11_9 -; AVX512F-NEXT: .LBB11_10: # %else8 +; AVX512F-NEXT: jne .LBB11_13 +; AVX512F-NEXT: .LBB11_5: # %else8 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne .LBB11_11 -; AVX512F-NEXT: .LBB11_12: # %else10 +; AVX512F-NEXT: jne .LBB11_14 +; AVX512F-NEXT: .LBB11_6: # %else10 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne .LBB11_13 -; AVX512F-NEXT: .LBB11_14: # %else12 -; AVX512F-NEXT: testb $-128, %al ; AVX512F-NEXT: jne .LBB11_15 -; AVX512F-NEXT: .LBB11_16: # %else14 +; AVX512F-NEXT: .LBB11_7: # %else12 +; AVX512F-NEXT: testb $-128, %al +; AVX512F-NEXT: jne .LBB11_16 +; AVX512F-NEXT: .LBB11_8: # %else14 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB11_1: # %cond.store +; AVX512F-NEXT: .LBB11_9: # %cond.store ; AVX512F-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB11_4 -; AVX512F-NEXT: .LBB11_3: # %cond.store1 +; AVX512F-NEXT: je .LBB11_2 +; AVX512F-NEXT: .LBB11_10: # %cond.store1 ; AVX512F-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB11_6 -; AVX512F-NEXT: .LBB11_5: # %cond.store3 +; AVX512F-NEXT: je .LBB11_3 +; AVX512F-NEXT: .LBB11_11: # %cond.store3 ; AVX512F-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB11_8 -; AVX512F-NEXT: .LBB11_7: # %cond.store5 +; AVX512F-NEXT: je .LBB11_4 +; AVX512F-NEXT: .LBB11_12: # %cond.store5 ; AVX512F-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je .LBB11_10 -; AVX512F-NEXT: .LBB11_9: # %cond.store7 +; AVX512F-NEXT: je .LBB11_5 +; AVX512F-NEXT: .LBB11_13: # %cond.store7 ; AVX512F-NEXT: vpextrw $4, %xmm0, 8(%rdi) ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je .LBB11_12 -; AVX512F-NEXT: .LBB11_11: # %cond.store9 +; AVX512F-NEXT: je .LBB11_6 +; AVX512F-NEXT: .LBB11_14: # %cond.store9 ; AVX512F-NEXT: vpextrw $5, %xmm0, 10(%rdi) ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je .LBB11_14 -; AVX512F-NEXT: .LBB11_13: # %cond.store11 +; AVX512F-NEXT: je .LBB11_7 +; AVX512F-NEXT: .LBB11_15: # %cond.store11 ; AVX512F-NEXT: vpextrw $6, %xmm0, 12(%rdi) ; AVX512F-NEXT: testb $-128, %al -; AVX512F-NEXT: je .LBB11_16 -; AVX512F-NEXT: .LBB11_15: # %cond.store13 +; AVX512F-NEXT: je .LBB11_8 +; AVX512F-NEXT: .LBB11_16: # %cond.store13 ; AVX512F-NEXT: vpextrw $7, %xmm0, 14(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -4680,60 +4680,60 @@ define void @truncstore_v8i32_v8i16(<8 x i32> %x, ptr %p, <8 x i32> %mask) { ; AVX512FVL-NEXT: vpmovusdw %ymm0, %xmm0 ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB11_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB11_9 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB11_3 -; AVX512FVL-NEXT: .LBB11_4: # %else2 +; AVX512FVL-NEXT: jne .LBB11_10 +; AVX512FVL-NEXT: .LBB11_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB11_5 -; AVX512FVL-NEXT: .LBB11_6: # %else4 +; AVX512FVL-NEXT: jne .LBB11_11 +; AVX512FVL-NEXT: .LBB11_3: # %else4 ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: jne .LBB11_7 -; AVX512FVL-NEXT: .LBB11_8: # %else6 +; AVX512FVL-NEXT: jne .LBB11_12 +; AVX512FVL-NEXT: .LBB11_4: # %else6 ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: jne .LBB11_9 -; AVX512FVL-NEXT: .LBB11_10: # %else8 +; AVX512FVL-NEXT: jne .LBB11_13 +; AVX512FVL-NEXT: .LBB11_5: # %else8 ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: jne .LBB11_11 -; AVX512FVL-NEXT: .LBB11_12: # %else10 +; AVX512FVL-NEXT: jne .LBB11_14 +; AVX512FVL-NEXT: .LBB11_6: # %else10 ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: jne .LBB11_13 -; AVX512FVL-NEXT: .LBB11_14: # %else12 -; AVX512FVL-NEXT: testb $-128, %al ; AVX512FVL-NEXT: jne .LBB11_15 -; AVX512FVL-NEXT: .LBB11_16: # %else14 +; AVX512FVL-NEXT: .LBB11_7: # %else12 +; AVX512FVL-NEXT: testb $-128, %al +; AVX512FVL-NEXT: jne .LBB11_16 +; AVX512FVL-NEXT: .LBB11_8: # %else14 ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB11_1: # %cond.store +; AVX512FVL-NEXT: .LBB11_9: # %cond.store ; AVX512FVL-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB11_4 -; AVX512FVL-NEXT: .LBB11_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB11_2 +; AVX512FVL-NEXT: .LBB11_10: # %cond.store1 ; AVX512FVL-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB11_6 -; AVX512FVL-NEXT: .LBB11_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB11_3 +; AVX512FVL-NEXT: .LBB11_11: # %cond.store3 ; AVX512FVL-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB11_8 -; AVX512FVL-NEXT: .LBB11_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB11_4 +; AVX512FVL-NEXT: .LBB11_12: # %cond.store5 ; AVX512FVL-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: je .LBB11_10 -; AVX512FVL-NEXT: .LBB11_9: # %cond.store7 +; AVX512FVL-NEXT: je .LBB11_5 +; AVX512FVL-NEXT: .LBB11_13: # %cond.store7 ; AVX512FVL-NEXT: vpextrw $4, %xmm0, 8(%rdi) ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: je .LBB11_12 -; AVX512FVL-NEXT: .LBB11_11: # %cond.store9 +; AVX512FVL-NEXT: je .LBB11_6 +; AVX512FVL-NEXT: .LBB11_14: # %cond.store9 ; AVX512FVL-NEXT: vpextrw $5, %xmm0, 10(%rdi) ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: je .LBB11_14 -; AVX512FVL-NEXT: .LBB11_13: # %cond.store11 +; AVX512FVL-NEXT: je .LBB11_7 +; AVX512FVL-NEXT: .LBB11_15: # %cond.store11 ; AVX512FVL-NEXT: vpextrw $6, %xmm0, 12(%rdi) ; AVX512FVL-NEXT: testb $-128, %al -; AVX512FVL-NEXT: je .LBB11_16 -; AVX512FVL-NEXT: .LBB11_15: # %cond.store13 +; AVX512FVL-NEXT: je .LBB11_8 +; AVX512FVL-NEXT: .LBB11_16: # %cond.store13 ; AVX512FVL-NEXT: vpextrw $7, %xmm0, 14(%rdi) ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq @@ -4793,59 +4793,59 @@ define void @truncstore_v8i32_v8i8(<8 x i32> %x, ptr %p, <8 x i32> %mask) { ; SSE2-NEXT: notl %eax ; SSE2-NEXT: testb $1, %al ; SSE2-NEXT: movd %xmm4, %ecx -; SSE2-NEXT: jne .LBB12_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB12_12 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne .LBB12_3 -; SSE2-NEXT: .LBB12_4: # %else2 +; SSE2-NEXT: jne .LBB12_13 +; SSE2-NEXT: .LBB12_2: # %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne .LBB12_5 -; SSE2-NEXT: .LBB12_6: # %else4 +; SSE2-NEXT: jne .LBB12_14 +; SSE2-NEXT: .LBB12_3: # %else4 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je .LBB12_8 -; SSE2-NEXT: .LBB12_7: # %cond.store5 +; SSE2-NEXT: je .LBB12_5 +; SSE2-NEXT: .LBB12_4: # %cond.store5 ; SSE2-NEXT: shrl $24, %ecx ; SSE2-NEXT: movb %cl, 3(%rdi) -; SSE2-NEXT: .LBB12_8: # %else6 +; SSE2-NEXT: .LBB12_5: # %else6 ; SSE2-NEXT: testb $16, %al ; SSE2-NEXT: pextrw $2, %xmm4, %ecx -; SSE2-NEXT: je .LBB12_10 -; SSE2-NEXT: # %bb.9: # %cond.store7 +; SSE2-NEXT: je .LBB12_7 +; SSE2-NEXT: # %bb.6: # %cond.store7 ; SSE2-NEXT: movb %cl, 4(%rdi) -; SSE2-NEXT: .LBB12_10: # %else8 +; SSE2-NEXT: .LBB12_7: # %else8 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je .LBB12_12 -; SSE2-NEXT: # %bb.11: # %cond.store9 +; SSE2-NEXT: je .LBB12_9 +; SSE2-NEXT: # %bb.8: # %cond.store9 ; SSE2-NEXT: movb %ch, 5(%rdi) -; SSE2-NEXT: .LBB12_12: # %else10 +; SSE2-NEXT: .LBB12_9: # %else10 ; SSE2-NEXT: testb $64, %al ; SSE2-NEXT: pextrw $3, %xmm4, %ecx -; SSE2-NEXT: jne .LBB12_13 -; SSE2-NEXT: # %bb.14: # %else12 -; SSE2-NEXT: testb $-128, %al ; SSE2-NEXT: jne .LBB12_15 -; SSE2-NEXT: .LBB12_16: # %else14 +; SSE2-NEXT: # %bb.10: # %else12 +; SSE2-NEXT: testb $-128, %al +; SSE2-NEXT: jne .LBB12_16 +; SSE2-NEXT: .LBB12_11: # %else14 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB12_1: # %cond.store +; SSE2-NEXT: .LBB12_12: # %cond.store ; SSE2-NEXT: movb %cl, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB12_4 -; SSE2-NEXT: .LBB12_3: # %cond.store1 +; SSE2-NEXT: je .LBB12_2 +; SSE2-NEXT: .LBB12_13: # %cond.store1 ; SSE2-NEXT: movb %ch, 1(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je .LBB12_6 -; SSE2-NEXT: .LBB12_5: # %cond.store3 +; SSE2-NEXT: je .LBB12_3 +; SSE2-NEXT: .LBB12_14: # %cond.store3 ; SSE2-NEXT: movl %ecx, %edx ; SSE2-NEXT: shrl $16, %edx ; SSE2-NEXT: movb %dl, 2(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne .LBB12_7 -; SSE2-NEXT: jmp .LBB12_8 -; SSE2-NEXT: .LBB12_13: # %cond.store11 +; SSE2-NEXT: jne .LBB12_4 +; SSE2-NEXT: jmp .LBB12_5 +; SSE2-NEXT: .LBB12_15: # %cond.store11 ; SSE2-NEXT: movb %cl, 6(%rdi) ; SSE2-NEXT: testb $-128, %al -; SSE2-NEXT: je .LBB12_16 -; SSE2-NEXT: .LBB12_15: # %cond.store13 +; SSE2-NEXT: je .LBB12_11 +; SSE2-NEXT: .LBB12_16: # %cond.store13 ; SSE2-NEXT: movb %ch, 7(%rdi) ; SSE2-NEXT: retq ; @@ -4864,59 +4864,59 @@ define void @truncstore_v8i32_v8i8(<8 x i32> %x, ptr %p, <8 x i32> %mask) { ; SSE4-NEXT: pmovmskb %xmm2, %eax ; SSE4-NEXT: notl %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB12_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB12_9 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB12_3 -; SSE4-NEXT: .LBB12_4: # %else2 +; SSE4-NEXT: jne .LBB12_10 +; SSE4-NEXT: .LBB12_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB12_5 -; SSE4-NEXT: .LBB12_6: # %else4 +; SSE4-NEXT: jne .LBB12_11 +; SSE4-NEXT: .LBB12_3: # %else4 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne .LBB12_7 -; SSE4-NEXT: .LBB12_8: # %else6 +; SSE4-NEXT: jne .LBB12_12 +; SSE4-NEXT: .LBB12_4: # %else6 ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: jne .LBB12_9 -; SSE4-NEXT: .LBB12_10: # %else8 +; SSE4-NEXT: jne .LBB12_13 +; SSE4-NEXT: .LBB12_5: # %else8 ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: jne .LBB12_11 -; SSE4-NEXT: .LBB12_12: # %else10 +; SSE4-NEXT: jne .LBB12_14 +; SSE4-NEXT: .LBB12_6: # %else10 ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: jne .LBB12_13 -; SSE4-NEXT: .LBB12_14: # %else12 -; SSE4-NEXT: testb $-128, %al ; SSE4-NEXT: jne .LBB12_15 -; SSE4-NEXT: .LBB12_16: # %else14 +; SSE4-NEXT: .LBB12_7: # %else12 +; SSE4-NEXT: testb $-128, %al +; SSE4-NEXT: jne .LBB12_16 +; SSE4-NEXT: .LBB12_8: # %else14 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB12_1: # %cond.store +; SSE4-NEXT: .LBB12_9: # %cond.store ; SSE4-NEXT: pextrb $0, %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB12_4 -; SSE4-NEXT: .LBB12_3: # %cond.store1 +; SSE4-NEXT: je .LBB12_2 +; SSE4-NEXT: .LBB12_10: # %cond.store1 ; SSE4-NEXT: pextrb $1, %xmm0, 1(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB12_6 -; SSE4-NEXT: .LBB12_5: # %cond.store3 +; SSE4-NEXT: je .LBB12_3 +; SSE4-NEXT: .LBB12_11: # %cond.store3 ; SSE4-NEXT: pextrb $2, %xmm0, 2(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB12_8 -; SSE4-NEXT: .LBB12_7: # %cond.store5 +; SSE4-NEXT: je .LBB12_4 +; SSE4-NEXT: .LBB12_12: # %cond.store5 ; SSE4-NEXT: pextrb $3, %xmm0, 3(%rdi) ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: je .LBB12_10 -; SSE4-NEXT: .LBB12_9: # %cond.store7 +; SSE4-NEXT: je .LBB12_5 +; SSE4-NEXT: .LBB12_13: # %cond.store7 ; SSE4-NEXT: pextrb $4, %xmm0, 4(%rdi) ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: je .LBB12_12 -; SSE4-NEXT: .LBB12_11: # %cond.store9 +; SSE4-NEXT: je .LBB12_6 +; SSE4-NEXT: .LBB12_14: # %cond.store9 ; SSE4-NEXT: pextrb $5, %xmm0, 5(%rdi) ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: je .LBB12_14 -; SSE4-NEXT: .LBB12_13: # %cond.store11 +; SSE4-NEXT: je .LBB12_7 +; SSE4-NEXT: .LBB12_15: # %cond.store11 ; SSE4-NEXT: pextrb $6, %xmm0, 6(%rdi) ; SSE4-NEXT: testb $-128, %al -; SSE4-NEXT: je .LBB12_16 -; SSE4-NEXT: .LBB12_15: # %cond.store13 +; SSE4-NEXT: je .LBB12_8 +; SSE4-NEXT: .LBB12_16: # %cond.store13 ; SSE4-NEXT: pextrb $7, %xmm0, 7(%rdi) ; SSE4-NEXT: retq ; @@ -4936,60 +4936,60 @@ define void @truncstore_v8i32_v8i8(<8 x i32> %x, ptr %p, <8 x i32> %mask) { ; AVX1-NEXT: vmovmskps %ymm1, %eax ; AVX1-NEXT: notl %eax ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne .LBB12_1 -; AVX1-NEXT: # %bb.2: # %else +; AVX1-NEXT: jne .LBB12_9 +; AVX1-NEXT: # %bb.1: # %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne .LBB12_3 -; AVX1-NEXT: .LBB12_4: # %else2 +; AVX1-NEXT: jne .LBB12_10 +; AVX1-NEXT: .LBB12_2: # %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne .LBB12_5 -; AVX1-NEXT: .LBB12_6: # %else4 +; AVX1-NEXT: jne .LBB12_11 +; AVX1-NEXT: .LBB12_3: # %else4 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne .LBB12_7 -; AVX1-NEXT: .LBB12_8: # %else6 +; AVX1-NEXT: jne .LBB12_12 +; AVX1-NEXT: .LBB12_4: # %else6 ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: jne .LBB12_9 -; AVX1-NEXT: .LBB12_10: # %else8 +; AVX1-NEXT: jne .LBB12_13 +; AVX1-NEXT: .LBB12_5: # %else8 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: jne .LBB12_11 -; AVX1-NEXT: .LBB12_12: # %else10 +; AVX1-NEXT: jne .LBB12_14 +; AVX1-NEXT: .LBB12_6: # %else10 ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: jne .LBB12_13 -; AVX1-NEXT: .LBB12_14: # %else12 -; AVX1-NEXT: testb $-128, %al ; AVX1-NEXT: jne .LBB12_15 -; AVX1-NEXT: .LBB12_16: # %else14 +; AVX1-NEXT: .LBB12_7: # %else12 +; AVX1-NEXT: testb $-128, %al +; AVX1-NEXT: jne .LBB12_16 +; AVX1-NEXT: .LBB12_8: # %else14 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB12_1: # %cond.store +; AVX1-NEXT: .LBB12_9: # %cond.store ; AVX1-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je .LBB12_4 -; AVX1-NEXT: .LBB12_3: # %cond.store1 +; AVX1-NEXT: je .LBB12_2 +; AVX1-NEXT: .LBB12_10: # %cond.store1 ; AVX1-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je .LBB12_6 -; AVX1-NEXT: .LBB12_5: # %cond.store3 +; AVX1-NEXT: je .LBB12_3 +; AVX1-NEXT: .LBB12_11: # %cond.store3 ; AVX1-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB12_8 -; AVX1-NEXT: .LBB12_7: # %cond.store5 +; AVX1-NEXT: je .LBB12_4 +; AVX1-NEXT: .LBB12_12: # %cond.store5 ; AVX1-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: je .LBB12_10 -; AVX1-NEXT: .LBB12_9: # %cond.store7 +; AVX1-NEXT: je .LBB12_5 +; AVX1-NEXT: .LBB12_13: # %cond.store7 ; AVX1-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je .LBB12_12 -; AVX1-NEXT: .LBB12_11: # %cond.store9 +; AVX1-NEXT: je .LBB12_6 +; AVX1-NEXT: .LBB12_14: # %cond.store9 ; AVX1-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: je .LBB12_14 -; AVX1-NEXT: .LBB12_13: # %cond.store11 +; AVX1-NEXT: je .LBB12_7 +; AVX1-NEXT: .LBB12_15: # %cond.store11 ; AVX1-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX1-NEXT: testb $-128, %al -; AVX1-NEXT: je .LBB12_16 -; AVX1-NEXT: .LBB12_15: # %cond.store13 +; AVX1-NEXT: je .LBB12_8 +; AVX1-NEXT: .LBB12_16: # %cond.store13 ; AVX1-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq @@ -5006,60 +5006,60 @@ define void @truncstore_v8i32_v8i8(<8 x i32> %x, ptr %p, <8 x i32> %mask) { ; AVX2-NEXT: vmovmskps %ymm1, %eax ; AVX2-NEXT: notl %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne .LBB12_1 -; AVX2-NEXT: # %bb.2: # %else +; AVX2-NEXT: jne .LBB12_9 +; AVX2-NEXT: # %bb.1: # %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne .LBB12_3 -; AVX2-NEXT: .LBB12_4: # %else2 +; AVX2-NEXT: jne .LBB12_10 +; AVX2-NEXT: .LBB12_2: # %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne .LBB12_5 -; AVX2-NEXT: .LBB12_6: # %else4 +; AVX2-NEXT: jne .LBB12_11 +; AVX2-NEXT: .LBB12_3: # %else4 ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: jne .LBB12_7 -; AVX2-NEXT: .LBB12_8: # %else6 +; AVX2-NEXT: jne .LBB12_12 +; AVX2-NEXT: .LBB12_4: # %else6 ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: jne .LBB12_9 -; AVX2-NEXT: .LBB12_10: # %else8 +; AVX2-NEXT: jne .LBB12_13 +; AVX2-NEXT: .LBB12_5: # %else8 ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: jne .LBB12_11 -; AVX2-NEXT: .LBB12_12: # %else10 +; AVX2-NEXT: jne .LBB12_14 +; AVX2-NEXT: .LBB12_6: # %else10 ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: jne .LBB12_13 -; AVX2-NEXT: .LBB12_14: # %else12 -; AVX2-NEXT: testb $-128, %al ; AVX2-NEXT: jne .LBB12_15 -; AVX2-NEXT: .LBB12_16: # %else14 +; AVX2-NEXT: .LBB12_7: # %else12 +; AVX2-NEXT: testb $-128, %al +; AVX2-NEXT: jne .LBB12_16 +; AVX2-NEXT: .LBB12_8: # %else14 ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; AVX2-NEXT: .LBB12_1: # %cond.store +; AVX2-NEXT: .LBB12_9: # %cond.store ; AVX2-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je .LBB12_4 -; AVX2-NEXT: .LBB12_3: # %cond.store1 +; AVX2-NEXT: je .LBB12_2 +; AVX2-NEXT: .LBB12_10: # %cond.store1 ; AVX2-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je .LBB12_6 -; AVX2-NEXT: .LBB12_5: # %cond.store3 +; AVX2-NEXT: je .LBB12_3 +; AVX2-NEXT: .LBB12_11: # %cond.store3 ; AVX2-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je .LBB12_8 -; AVX2-NEXT: .LBB12_7: # %cond.store5 +; AVX2-NEXT: je .LBB12_4 +; AVX2-NEXT: .LBB12_12: # %cond.store5 ; AVX2-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: je .LBB12_10 -; AVX2-NEXT: .LBB12_9: # %cond.store7 +; AVX2-NEXT: je .LBB12_5 +; AVX2-NEXT: .LBB12_13: # %cond.store7 ; AVX2-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: je .LBB12_12 -; AVX2-NEXT: .LBB12_11: # %cond.store9 +; AVX2-NEXT: je .LBB12_6 +; AVX2-NEXT: .LBB12_14: # %cond.store9 ; AVX2-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: je .LBB12_14 -; AVX2-NEXT: .LBB12_13: # %cond.store11 +; AVX2-NEXT: je .LBB12_7 +; AVX2-NEXT: .LBB12_15: # %cond.store11 ; AVX2-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX2-NEXT: testb $-128, %al -; AVX2-NEXT: je .LBB12_16 -; AVX2-NEXT: .LBB12_15: # %cond.store13 +; AVX2-NEXT: je .LBB12_8 +; AVX2-NEXT: .LBB12_16: # %cond.store13 ; AVX2-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq @@ -5072,60 +5072,60 @@ define void @truncstore_v8i32_v8i8(<8 x i32> %x, ptr %p, <8 x i32> %mask) { ; AVX512F-NEXT: vpmovusdb %zmm0, %xmm0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB12_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB12_9 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB12_3 -; AVX512F-NEXT: .LBB12_4: # %else2 +; AVX512F-NEXT: jne .LBB12_10 +; AVX512F-NEXT: .LBB12_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB12_5 -; AVX512F-NEXT: .LBB12_6: # %else4 +; AVX512F-NEXT: jne .LBB12_11 +; AVX512F-NEXT: .LBB12_3: # %else4 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne .LBB12_7 -; AVX512F-NEXT: .LBB12_8: # %else6 +; AVX512F-NEXT: jne .LBB12_12 +; AVX512F-NEXT: .LBB12_4: # %else6 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne .LBB12_9 -; AVX512F-NEXT: .LBB12_10: # %else8 +; AVX512F-NEXT: jne .LBB12_13 +; AVX512F-NEXT: .LBB12_5: # %else8 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne .LBB12_11 -; AVX512F-NEXT: .LBB12_12: # %else10 +; AVX512F-NEXT: jne .LBB12_14 +; AVX512F-NEXT: .LBB12_6: # %else10 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne .LBB12_13 -; AVX512F-NEXT: .LBB12_14: # %else12 -; AVX512F-NEXT: testb $-128, %al ; AVX512F-NEXT: jne .LBB12_15 -; AVX512F-NEXT: .LBB12_16: # %else14 +; AVX512F-NEXT: .LBB12_7: # %else12 +; AVX512F-NEXT: testb $-128, %al +; AVX512F-NEXT: jne .LBB12_16 +; AVX512F-NEXT: .LBB12_8: # %else14 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB12_1: # %cond.store +; AVX512F-NEXT: .LBB12_9: # %cond.store ; AVX512F-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB12_4 -; AVX512F-NEXT: .LBB12_3: # %cond.store1 +; AVX512F-NEXT: je .LBB12_2 +; AVX512F-NEXT: .LBB12_10: # %cond.store1 ; AVX512F-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB12_6 -; AVX512F-NEXT: .LBB12_5: # %cond.store3 +; AVX512F-NEXT: je .LBB12_3 +; AVX512F-NEXT: .LBB12_11: # %cond.store3 ; AVX512F-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB12_8 -; AVX512F-NEXT: .LBB12_7: # %cond.store5 +; AVX512F-NEXT: je .LBB12_4 +; AVX512F-NEXT: .LBB12_12: # %cond.store5 ; AVX512F-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je .LBB12_10 -; AVX512F-NEXT: .LBB12_9: # %cond.store7 +; AVX512F-NEXT: je .LBB12_5 +; AVX512F-NEXT: .LBB12_13: # %cond.store7 ; AVX512F-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je .LBB12_12 -; AVX512F-NEXT: .LBB12_11: # %cond.store9 +; AVX512F-NEXT: je .LBB12_6 +; AVX512F-NEXT: .LBB12_14: # %cond.store9 ; AVX512F-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je .LBB12_14 -; AVX512F-NEXT: .LBB12_13: # %cond.store11 +; AVX512F-NEXT: je .LBB12_7 +; AVX512F-NEXT: .LBB12_15: # %cond.store11 ; AVX512F-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX512F-NEXT: testb $-128, %al -; AVX512F-NEXT: je .LBB12_16 -; AVX512F-NEXT: .LBB12_15: # %cond.store13 +; AVX512F-NEXT: je .LBB12_8 +; AVX512F-NEXT: .LBB12_16: # %cond.store13 ; AVX512F-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -5136,60 +5136,60 @@ define void @truncstore_v8i32_v8i8(<8 x i32> %x, ptr %p, <8 x i32> %mask) { ; AVX512FVL-NEXT: vpmovusdb %ymm0, %xmm0 ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB12_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB12_9 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB12_3 -; AVX512FVL-NEXT: .LBB12_4: # %else2 +; AVX512FVL-NEXT: jne .LBB12_10 +; AVX512FVL-NEXT: .LBB12_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB12_5 -; AVX512FVL-NEXT: .LBB12_6: # %else4 +; AVX512FVL-NEXT: jne .LBB12_11 +; AVX512FVL-NEXT: .LBB12_3: # %else4 ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: jne .LBB12_7 -; AVX512FVL-NEXT: .LBB12_8: # %else6 +; AVX512FVL-NEXT: jne .LBB12_12 +; AVX512FVL-NEXT: .LBB12_4: # %else6 ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: jne .LBB12_9 -; AVX512FVL-NEXT: .LBB12_10: # %else8 +; AVX512FVL-NEXT: jne .LBB12_13 +; AVX512FVL-NEXT: .LBB12_5: # %else8 ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: jne .LBB12_11 -; AVX512FVL-NEXT: .LBB12_12: # %else10 +; AVX512FVL-NEXT: jne .LBB12_14 +; AVX512FVL-NEXT: .LBB12_6: # %else10 ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: jne .LBB12_13 -; AVX512FVL-NEXT: .LBB12_14: # %else12 -; AVX512FVL-NEXT: testb $-128, %al ; AVX512FVL-NEXT: jne .LBB12_15 -; AVX512FVL-NEXT: .LBB12_16: # %else14 +; AVX512FVL-NEXT: .LBB12_7: # %else12 +; AVX512FVL-NEXT: testb $-128, %al +; AVX512FVL-NEXT: jne .LBB12_16 +; AVX512FVL-NEXT: .LBB12_8: # %else14 ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB12_1: # %cond.store +; AVX512FVL-NEXT: .LBB12_9: # %cond.store ; AVX512FVL-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB12_4 -; AVX512FVL-NEXT: .LBB12_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB12_2 +; AVX512FVL-NEXT: .LBB12_10: # %cond.store1 ; AVX512FVL-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB12_6 -; AVX512FVL-NEXT: .LBB12_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB12_3 +; AVX512FVL-NEXT: .LBB12_11: # %cond.store3 ; AVX512FVL-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB12_8 -; AVX512FVL-NEXT: .LBB12_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB12_4 +; AVX512FVL-NEXT: .LBB12_12: # %cond.store5 ; AVX512FVL-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: je .LBB12_10 -; AVX512FVL-NEXT: .LBB12_9: # %cond.store7 +; AVX512FVL-NEXT: je .LBB12_5 +; AVX512FVL-NEXT: .LBB12_13: # %cond.store7 ; AVX512FVL-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: je .LBB12_12 -; AVX512FVL-NEXT: .LBB12_11: # %cond.store9 +; AVX512FVL-NEXT: je .LBB12_6 +; AVX512FVL-NEXT: .LBB12_14: # %cond.store9 ; AVX512FVL-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: je .LBB12_14 -; AVX512FVL-NEXT: .LBB12_13: # %cond.store11 +; AVX512FVL-NEXT: je .LBB12_7 +; AVX512FVL-NEXT: .LBB12_15: # %cond.store11 ; AVX512FVL-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX512FVL-NEXT: testb $-128, %al -; AVX512FVL-NEXT: je .LBB12_16 -; AVX512FVL-NEXT: .LBB12_15: # %cond.store13 +; AVX512FVL-NEXT: je .LBB12_8 +; AVX512FVL-NEXT: .LBB12_16: # %cond.store13 ; AVX512FVL-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq @@ -5238,34 +5238,34 @@ define void @truncstore_v4i32_v4i16(<4 x i32> %x, ptr %p, <4 x i32> %mask) { ; SSE2-NEXT: movmskps %xmm2, %eax ; SSE2-NEXT: xorl $15, %eax ; SSE2-NEXT: testb $1, %al -; SSE2-NEXT: jne .LBB13_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB13_5 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne .LBB13_3 -; SSE2-NEXT: .LBB13_4: # %else2 +; SSE2-NEXT: jne .LBB13_6 +; SSE2-NEXT: .LBB13_2: # %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne .LBB13_5 -; SSE2-NEXT: .LBB13_6: # %else4 -; SSE2-NEXT: testb $8, %al ; SSE2-NEXT: jne .LBB13_7 -; SSE2-NEXT: .LBB13_8: # %else6 +; SSE2-NEXT: .LBB13_3: # %else4 +; SSE2-NEXT: testb $8, %al +; SSE2-NEXT: jne .LBB13_8 +; SSE2-NEXT: .LBB13_4: # %else6 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB13_1: # %cond.store +; SSE2-NEXT: .LBB13_5: # %cond.store ; SSE2-NEXT: movd %xmm0, %ecx ; SSE2-NEXT: movw %cx, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB13_4 -; SSE2-NEXT: .LBB13_3: # %cond.store1 +; SSE2-NEXT: je .LBB13_2 +; SSE2-NEXT: .LBB13_6: # %cond.store1 ; SSE2-NEXT: pextrw $1, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 2(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je .LBB13_6 -; SSE2-NEXT: .LBB13_5: # %cond.store3 +; SSE2-NEXT: je .LBB13_3 +; SSE2-NEXT: .LBB13_7: # %cond.store3 ; SSE2-NEXT: pextrw $2, %xmm0, %ecx ; SSE2-NEXT: movw %cx, 4(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je .LBB13_8 -; SSE2-NEXT: .LBB13_7: # %cond.store5 +; SSE2-NEXT: je .LBB13_4 +; SSE2-NEXT: .LBB13_8: # %cond.store5 ; SSE2-NEXT: pextrw $3, %xmm0, %eax ; SSE2-NEXT: movw %ax, 6(%rdi) ; SSE2-NEXT: retq @@ -5279,31 +5279,31 @@ define void @truncstore_v4i32_v4i16(<4 x i32> %x, ptr %p, <4 x i32> %mask) { ; SSE4-NEXT: movmskps %xmm2, %eax ; SSE4-NEXT: xorl $15, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB13_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB13_5 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB13_3 -; SSE4-NEXT: .LBB13_4: # %else2 +; SSE4-NEXT: jne .LBB13_6 +; SSE4-NEXT: .LBB13_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB13_5 -; SSE4-NEXT: .LBB13_6: # %else4 -; SSE4-NEXT: testb $8, %al ; SSE4-NEXT: jne .LBB13_7 -; SSE4-NEXT: .LBB13_8: # %else6 +; SSE4-NEXT: .LBB13_3: # %else4 +; SSE4-NEXT: testb $8, %al +; SSE4-NEXT: jne .LBB13_8 +; SSE4-NEXT: .LBB13_4: # %else6 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB13_1: # %cond.store +; SSE4-NEXT: .LBB13_5: # %cond.store ; SSE4-NEXT: pextrw $0, %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB13_4 -; SSE4-NEXT: .LBB13_3: # %cond.store1 +; SSE4-NEXT: je .LBB13_2 +; SSE4-NEXT: .LBB13_6: # %cond.store1 ; SSE4-NEXT: pextrw $1, %xmm0, 2(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB13_6 -; SSE4-NEXT: .LBB13_5: # %cond.store3 +; SSE4-NEXT: je .LBB13_3 +; SSE4-NEXT: .LBB13_7: # %cond.store3 ; SSE4-NEXT: pextrw $2, %xmm0, 4(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB13_8 -; SSE4-NEXT: .LBB13_7: # %cond.store5 +; SSE4-NEXT: je .LBB13_4 +; SSE4-NEXT: .LBB13_8: # %cond.store5 ; SSE4-NEXT: pextrw $3, %xmm0, 6(%rdi) ; SSE4-NEXT: retq ; @@ -5316,31 +5316,31 @@ define void @truncstore_v4i32_v4i16(<4 x i32> %x, ptr %p, <4 x i32> %mask) { ; AVX1-NEXT: vmovmskps %xmm1, %eax ; AVX1-NEXT: xorl $15, %eax ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne .LBB13_1 -; AVX1-NEXT: # %bb.2: # %else +; AVX1-NEXT: jne .LBB13_5 +; AVX1-NEXT: # %bb.1: # %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne .LBB13_3 -; AVX1-NEXT: .LBB13_4: # %else2 +; AVX1-NEXT: jne .LBB13_6 +; AVX1-NEXT: .LBB13_2: # %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne .LBB13_5 -; AVX1-NEXT: .LBB13_6: # %else4 -; AVX1-NEXT: testb $8, %al ; AVX1-NEXT: jne .LBB13_7 -; AVX1-NEXT: .LBB13_8: # %else6 +; AVX1-NEXT: .LBB13_3: # %else4 +; AVX1-NEXT: testb $8, %al +; AVX1-NEXT: jne .LBB13_8 +; AVX1-NEXT: .LBB13_4: # %else6 ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB13_1: # %cond.store +; AVX1-NEXT: .LBB13_5: # %cond.store ; AVX1-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je .LBB13_4 -; AVX1-NEXT: .LBB13_3: # %cond.store1 +; AVX1-NEXT: je .LBB13_2 +; AVX1-NEXT: .LBB13_6: # %cond.store1 ; AVX1-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je .LBB13_6 -; AVX1-NEXT: .LBB13_5: # %cond.store3 +; AVX1-NEXT: je .LBB13_3 +; AVX1-NEXT: .LBB13_7: # %cond.store3 ; AVX1-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB13_8 -; AVX1-NEXT: .LBB13_7: # %cond.store5 +; AVX1-NEXT: je .LBB13_4 +; AVX1-NEXT: .LBB13_8: # %cond.store5 ; AVX1-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX1-NEXT: retq ; @@ -5354,31 +5354,31 @@ define void @truncstore_v4i32_v4i16(<4 x i32> %x, ptr %p, <4 x i32> %mask) { ; AVX2-NEXT: vmovmskps %xmm1, %eax ; AVX2-NEXT: xorl $15, %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne .LBB13_1 -; AVX2-NEXT: # %bb.2: # %else +; AVX2-NEXT: jne .LBB13_5 +; AVX2-NEXT: # %bb.1: # %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne .LBB13_3 -; AVX2-NEXT: .LBB13_4: # %else2 +; AVX2-NEXT: jne .LBB13_6 +; AVX2-NEXT: .LBB13_2: # %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne .LBB13_5 -; AVX2-NEXT: .LBB13_6: # %else4 -; AVX2-NEXT: testb $8, %al ; AVX2-NEXT: jne .LBB13_7 -; AVX2-NEXT: .LBB13_8: # %else6 +; AVX2-NEXT: .LBB13_3: # %else4 +; AVX2-NEXT: testb $8, %al +; AVX2-NEXT: jne .LBB13_8 +; AVX2-NEXT: .LBB13_4: # %else6 ; AVX2-NEXT: retq -; AVX2-NEXT: .LBB13_1: # %cond.store +; AVX2-NEXT: .LBB13_5: # %cond.store ; AVX2-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je .LBB13_4 -; AVX2-NEXT: .LBB13_3: # %cond.store1 +; AVX2-NEXT: je .LBB13_2 +; AVX2-NEXT: .LBB13_6: # %cond.store1 ; AVX2-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je .LBB13_6 -; AVX2-NEXT: .LBB13_5: # %cond.store3 +; AVX2-NEXT: je .LBB13_3 +; AVX2-NEXT: .LBB13_7: # %cond.store3 ; AVX2-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je .LBB13_8 -; AVX2-NEXT: .LBB13_7: # %cond.store5 +; AVX2-NEXT: je .LBB13_4 +; AVX2-NEXT: .LBB13_8: # %cond.store5 ; AVX2-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX2-NEXT: retq ; @@ -5390,32 +5390,32 @@ define void @truncstore_v4i32_v4i16(<4 x i32> %x, ptr %p, <4 x i32> %mask) { ; AVX512F-NEXT: vpmovusdw %zmm0, %ymm0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB13_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB13_5 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB13_3 -; AVX512F-NEXT: .LBB13_4: # %else2 +; AVX512F-NEXT: jne .LBB13_6 +; AVX512F-NEXT: .LBB13_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB13_5 -; AVX512F-NEXT: .LBB13_6: # %else4 -; AVX512F-NEXT: testb $8, %al ; AVX512F-NEXT: jne .LBB13_7 -; AVX512F-NEXT: .LBB13_8: # %else6 +; AVX512F-NEXT: .LBB13_3: # %else4 +; AVX512F-NEXT: testb $8, %al +; AVX512F-NEXT: jne .LBB13_8 +; AVX512F-NEXT: .LBB13_4: # %else6 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB13_1: # %cond.store +; AVX512F-NEXT: .LBB13_5: # %cond.store ; AVX512F-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB13_4 -; AVX512F-NEXT: .LBB13_3: # %cond.store1 +; AVX512F-NEXT: je .LBB13_2 +; AVX512F-NEXT: .LBB13_6: # %cond.store1 ; AVX512F-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB13_6 -; AVX512F-NEXT: .LBB13_5: # %cond.store3 +; AVX512F-NEXT: je .LBB13_3 +; AVX512F-NEXT: .LBB13_7: # %cond.store3 ; AVX512F-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB13_8 -; AVX512F-NEXT: .LBB13_7: # %cond.store5 +; AVX512F-NEXT: je .LBB13_4 +; AVX512F-NEXT: .LBB13_8: # %cond.store5 ; AVX512F-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -5426,31 +5426,31 @@ define void @truncstore_v4i32_v4i16(<4 x i32> %x, ptr %p, <4 x i32> %mask) { ; AVX512FVL-NEXT: vpmovusdw %xmm0, %xmm0 ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB13_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB13_5 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB13_3 -; AVX512FVL-NEXT: .LBB13_4: # %else2 +; AVX512FVL-NEXT: jne .LBB13_6 +; AVX512FVL-NEXT: .LBB13_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB13_5 -; AVX512FVL-NEXT: .LBB13_6: # %else4 -; AVX512FVL-NEXT: testb $8, %al ; AVX512FVL-NEXT: jne .LBB13_7 -; AVX512FVL-NEXT: .LBB13_8: # %else6 +; AVX512FVL-NEXT: .LBB13_3: # %else4 +; AVX512FVL-NEXT: testb $8, %al +; AVX512FVL-NEXT: jne .LBB13_8 +; AVX512FVL-NEXT: .LBB13_4: # %else6 ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB13_1: # %cond.store +; AVX512FVL-NEXT: .LBB13_5: # %cond.store ; AVX512FVL-NEXT: vpextrw $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB13_4 -; AVX512FVL-NEXT: .LBB13_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB13_2 +; AVX512FVL-NEXT: .LBB13_6: # %cond.store1 ; AVX512FVL-NEXT: vpextrw $1, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB13_6 -; AVX512FVL-NEXT: .LBB13_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB13_3 +; AVX512FVL-NEXT: .LBB13_7: # %cond.store3 ; AVX512FVL-NEXT: vpextrw $2, %xmm0, 4(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB13_8 -; AVX512FVL-NEXT: .LBB13_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB13_4 +; AVX512FVL-NEXT: .LBB13_8: # %cond.store5 ; AVX512FVL-NEXT: vpextrw $3, %xmm0, 6(%rdi) ; AVX512FVL-NEXT: retq ; @@ -5497,33 +5497,33 @@ define void @truncstore_v4i32_v4i8(<4 x i32> %x, ptr %p, <4 x i32> %mask) { ; SSE2-NEXT: xorl $15, %ecx ; SSE2-NEXT: testb $1, %cl ; SSE2-NEXT: movd %xmm3, %eax -; SSE2-NEXT: jne .LBB14_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB14_5 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %cl -; SSE2-NEXT: jne .LBB14_3 -; SSE2-NEXT: .LBB14_4: # %else2 +; SSE2-NEXT: jne .LBB14_6 +; SSE2-NEXT: .LBB14_2: # %else2 ; SSE2-NEXT: testb $4, %cl -; SSE2-NEXT: jne .LBB14_5 -; SSE2-NEXT: .LBB14_6: # %else4 -; SSE2-NEXT: testb $8, %cl ; SSE2-NEXT: jne .LBB14_7 -; SSE2-NEXT: .LBB14_8: # %else6 +; SSE2-NEXT: .LBB14_3: # %else4 +; SSE2-NEXT: testb $8, %cl +; SSE2-NEXT: jne .LBB14_8 +; SSE2-NEXT: .LBB14_4: # %else6 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB14_1: # %cond.store +; SSE2-NEXT: .LBB14_5: # %cond.store ; SSE2-NEXT: movb %al, (%rdi) ; SSE2-NEXT: testb $2, %cl -; SSE2-NEXT: je .LBB14_4 -; SSE2-NEXT: .LBB14_3: # %cond.store1 +; SSE2-NEXT: je .LBB14_2 +; SSE2-NEXT: .LBB14_6: # %cond.store1 ; SSE2-NEXT: movb %ah, 1(%rdi) ; SSE2-NEXT: testb $4, %cl -; SSE2-NEXT: je .LBB14_6 -; SSE2-NEXT: .LBB14_5: # %cond.store3 +; SSE2-NEXT: je .LBB14_3 +; SSE2-NEXT: .LBB14_7: # %cond.store3 ; SSE2-NEXT: movl %eax, %edx ; SSE2-NEXT: shrl $16, %edx ; SSE2-NEXT: movb %dl, 2(%rdi) ; SSE2-NEXT: testb $8, %cl -; SSE2-NEXT: je .LBB14_8 -; SSE2-NEXT: .LBB14_7: # %cond.store5 +; SSE2-NEXT: je .LBB14_4 +; SSE2-NEXT: .LBB14_8: # %cond.store5 ; SSE2-NEXT: shrl $24, %eax ; SSE2-NEXT: movb %al, 3(%rdi) ; SSE2-NEXT: retq @@ -5538,31 +5538,31 @@ define void @truncstore_v4i32_v4i8(<4 x i32> %x, ptr %p, <4 x i32> %mask) { ; SSE4-NEXT: movmskps %xmm2, %eax ; SSE4-NEXT: xorl $15, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB14_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB14_5 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB14_3 -; SSE4-NEXT: .LBB14_4: # %else2 +; SSE4-NEXT: jne .LBB14_6 +; SSE4-NEXT: .LBB14_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB14_5 -; SSE4-NEXT: .LBB14_6: # %else4 -; SSE4-NEXT: testb $8, %al ; SSE4-NEXT: jne .LBB14_7 -; SSE4-NEXT: .LBB14_8: # %else6 +; SSE4-NEXT: .LBB14_3: # %else4 +; SSE4-NEXT: testb $8, %al +; SSE4-NEXT: jne .LBB14_8 +; SSE4-NEXT: .LBB14_4: # %else6 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB14_1: # %cond.store +; SSE4-NEXT: .LBB14_5: # %cond.store ; SSE4-NEXT: pextrb $0, %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB14_4 -; SSE4-NEXT: .LBB14_3: # %cond.store1 +; SSE4-NEXT: je .LBB14_2 +; SSE4-NEXT: .LBB14_6: # %cond.store1 ; SSE4-NEXT: pextrb $1, %xmm0, 1(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB14_6 -; SSE4-NEXT: .LBB14_5: # %cond.store3 +; SSE4-NEXT: je .LBB14_3 +; SSE4-NEXT: .LBB14_7: # %cond.store3 ; SSE4-NEXT: pextrb $2, %xmm0, 2(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB14_8 -; SSE4-NEXT: .LBB14_7: # %cond.store5 +; SSE4-NEXT: je .LBB14_4 +; SSE4-NEXT: .LBB14_8: # %cond.store5 ; SSE4-NEXT: pextrb $3, %xmm0, 3(%rdi) ; SSE4-NEXT: retq ; @@ -5576,31 +5576,31 @@ define void @truncstore_v4i32_v4i8(<4 x i32> %x, ptr %p, <4 x i32> %mask) { ; AVX1-NEXT: vmovmskps %xmm1, %eax ; AVX1-NEXT: xorl $15, %eax ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne .LBB14_1 -; AVX1-NEXT: # %bb.2: # %else +; AVX1-NEXT: jne .LBB14_5 +; AVX1-NEXT: # %bb.1: # %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne .LBB14_3 -; AVX1-NEXT: .LBB14_4: # %else2 +; AVX1-NEXT: jne .LBB14_6 +; AVX1-NEXT: .LBB14_2: # %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne .LBB14_5 -; AVX1-NEXT: .LBB14_6: # %else4 -; AVX1-NEXT: testb $8, %al ; AVX1-NEXT: jne .LBB14_7 -; AVX1-NEXT: .LBB14_8: # %else6 +; AVX1-NEXT: .LBB14_3: # %else4 +; AVX1-NEXT: testb $8, %al +; AVX1-NEXT: jne .LBB14_8 +; AVX1-NEXT: .LBB14_4: # %else6 ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB14_1: # %cond.store +; AVX1-NEXT: .LBB14_5: # %cond.store ; AVX1-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je .LBB14_4 -; AVX1-NEXT: .LBB14_3: # %cond.store1 +; AVX1-NEXT: je .LBB14_2 +; AVX1-NEXT: .LBB14_6: # %cond.store1 ; AVX1-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je .LBB14_6 -; AVX1-NEXT: .LBB14_5: # %cond.store3 +; AVX1-NEXT: je .LBB14_3 +; AVX1-NEXT: .LBB14_7: # %cond.store3 ; AVX1-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB14_8 -; AVX1-NEXT: .LBB14_7: # %cond.store5 +; AVX1-NEXT: je .LBB14_4 +; AVX1-NEXT: .LBB14_8: # %cond.store5 ; AVX1-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX1-NEXT: retq ; @@ -5615,31 +5615,31 @@ define void @truncstore_v4i32_v4i8(<4 x i32> %x, ptr %p, <4 x i32> %mask) { ; AVX2-NEXT: vmovmskps %xmm1, %eax ; AVX2-NEXT: xorl $15, %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne .LBB14_1 -; AVX2-NEXT: # %bb.2: # %else +; AVX2-NEXT: jne .LBB14_5 +; AVX2-NEXT: # %bb.1: # %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne .LBB14_3 -; AVX2-NEXT: .LBB14_4: # %else2 +; AVX2-NEXT: jne .LBB14_6 +; AVX2-NEXT: .LBB14_2: # %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne .LBB14_5 -; AVX2-NEXT: .LBB14_6: # %else4 -; AVX2-NEXT: testb $8, %al ; AVX2-NEXT: jne .LBB14_7 -; AVX2-NEXT: .LBB14_8: # %else6 +; AVX2-NEXT: .LBB14_3: # %else4 +; AVX2-NEXT: testb $8, %al +; AVX2-NEXT: jne .LBB14_8 +; AVX2-NEXT: .LBB14_4: # %else6 ; AVX2-NEXT: retq -; AVX2-NEXT: .LBB14_1: # %cond.store +; AVX2-NEXT: .LBB14_5: # %cond.store ; AVX2-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je .LBB14_4 -; AVX2-NEXT: .LBB14_3: # %cond.store1 +; AVX2-NEXT: je .LBB14_2 +; AVX2-NEXT: .LBB14_6: # %cond.store1 ; AVX2-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je .LBB14_6 -; AVX2-NEXT: .LBB14_5: # %cond.store3 +; AVX2-NEXT: je .LBB14_3 +; AVX2-NEXT: .LBB14_7: # %cond.store3 ; AVX2-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je .LBB14_8 -; AVX2-NEXT: .LBB14_7: # %cond.store5 +; AVX2-NEXT: je .LBB14_4 +; AVX2-NEXT: .LBB14_8: # %cond.store5 ; AVX2-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX2-NEXT: retq ; @@ -5651,32 +5651,32 @@ define void @truncstore_v4i32_v4i8(<4 x i32> %x, ptr %p, <4 x i32> %mask) { ; AVX512F-NEXT: vpmovusdb %zmm0, %xmm0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB14_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB14_5 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB14_3 -; AVX512F-NEXT: .LBB14_4: # %else2 +; AVX512F-NEXT: jne .LBB14_6 +; AVX512F-NEXT: .LBB14_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB14_5 -; AVX512F-NEXT: .LBB14_6: # %else4 -; AVX512F-NEXT: testb $8, %al ; AVX512F-NEXT: jne .LBB14_7 -; AVX512F-NEXT: .LBB14_8: # %else6 +; AVX512F-NEXT: .LBB14_3: # %else4 +; AVX512F-NEXT: testb $8, %al +; AVX512F-NEXT: jne .LBB14_8 +; AVX512F-NEXT: .LBB14_4: # %else6 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB14_1: # %cond.store +; AVX512F-NEXT: .LBB14_5: # %cond.store ; AVX512F-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB14_4 -; AVX512F-NEXT: .LBB14_3: # %cond.store1 +; AVX512F-NEXT: je .LBB14_2 +; AVX512F-NEXT: .LBB14_6: # %cond.store1 ; AVX512F-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB14_6 -; AVX512F-NEXT: .LBB14_5: # %cond.store3 +; AVX512F-NEXT: je .LBB14_3 +; AVX512F-NEXT: .LBB14_7: # %cond.store3 ; AVX512F-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB14_8 -; AVX512F-NEXT: .LBB14_7: # %cond.store5 +; AVX512F-NEXT: je .LBB14_4 +; AVX512F-NEXT: .LBB14_8: # %cond.store5 ; AVX512F-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -5687,31 +5687,31 @@ define void @truncstore_v4i32_v4i8(<4 x i32> %x, ptr %p, <4 x i32> %mask) { ; AVX512FVL-NEXT: vpmovusdb %xmm0, %xmm0 ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB14_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB14_5 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB14_3 -; AVX512FVL-NEXT: .LBB14_4: # %else2 +; AVX512FVL-NEXT: jne .LBB14_6 +; AVX512FVL-NEXT: .LBB14_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB14_5 -; AVX512FVL-NEXT: .LBB14_6: # %else4 -; AVX512FVL-NEXT: testb $8, %al ; AVX512FVL-NEXT: jne .LBB14_7 -; AVX512FVL-NEXT: .LBB14_8: # %else6 +; AVX512FVL-NEXT: .LBB14_3: # %else4 +; AVX512FVL-NEXT: testb $8, %al +; AVX512FVL-NEXT: jne .LBB14_8 +; AVX512FVL-NEXT: .LBB14_4: # %else6 ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB14_1: # %cond.store +; AVX512FVL-NEXT: .LBB14_5: # %cond.store ; AVX512FVL-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB14_4 -; AVX512FVL-NEXT: .LBB14_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB14_2 +; AVX512FVL-NEXT: .LBB14_6: # %cond.store1 ; AVX512FVL-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB14_6 -; AVX512FVL-NEXT: .LBB14_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB14_3 +; AVX512FVL-NEXT: .LBB14_7: # %cond.store3 ; AVX512FVL-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB14_8 -; AVX512FVL-NEXT: .LBB14_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB14_4 +; AVX512FVL-NEXT: .LBB14_8: # %cond.store5 ; AVX512FVL-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512FVL-NEXT: retq ; @@ -5762,207 +5762,207 @@ define void @truncstore_v32i16_v32i8(<32 x i16> %x, ptr %p, <32 x i8> %mask) { ; SSE2-NEXT: orl %ecx, %eax ; SSE2-NEXT: testb $1, %al ; SSE2-NEXT: movd %xmm0, %ecx -; SSE2-NEXT: jne .LBB15_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB15_57 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne .LBB15_3 -; SSE2-NEXT: .LBB15_4: # %else2 +; SSE2-NEXT: jne .LBB15_58 +; SSE2-NEXT: .LBB15_2: # %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne .LBB15_5 -; SSE2-NEXT: .LBB15_6: # %else4 +; SSE2-NEXT: jne .LBB15_59 +; SSE2-NEXT: .LBB15_3: # %else4 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je .LBB15_8 -; SSE2-NEXT: .LBB15_7: # %cond.store5 +; SSE2-NEXT: je .LBB15_5 +; SSE2-NEXT: .LBB15_4: # %cond.store5 ; SSE2-NEXT: shrl $24, %ecx ; SSE2-NEXT: movb %cl, 3(%rdi) -; SSE2-NEXT: .LBB15_8: # %else6 +; SSE2-NEXT: .LBB15_5: # %else6 ; SSE2-NEXT: testb $16, %al ; SSE2-NEXT: pextrw $2, %xmm0, %ecx -; SSE2-NEXT: je .LBB15_10 -; SSE2-NEXT: # %bb.9: # %cond.store7 +; SSE2-NEXT: je .LBB15_7 +; SSE2-NEXT: # %bb.6: # %cond.store7 ; SSE2-NEXT: movb %cl, 4(%rdi) -; SSE2-NEXT: .LBB15_10: # %else8 +; SSE2-NEXT: .LBB15_7: # %else8 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je .LBB15_12 -; SSE2-NEXT: # %bb.11: # %cond.store9 +; SSE2-NEXT: je .LBB15_9 +; SSE2-NEXT: # %bb.8: # %cond.store9 ; SSE2-NEXT: movb %ch, 5(%rdi) -; SSE2-NEXT: .LBB15_12: # %else10 +; SSE2-NEXT: .LBB15_9: # %else10 ; SSE2-NEXT: testb $64, %al ; SSE2-NEXT: pextrw $3, %xmm0, %ecx -; SSE2-NEXT: je .LBB15_14 -; SSE2-NEXT: # %bb.13: # %cond.store11 +; SSE2-NEXT: je .LBB15_11 +; SSE2-NEXT: # %bb.10: # %cond.store11 ; SSE2-NEXT: movb %cl, 6(%rdi) -; SSE2-NEXT: .LBB15_14: # %else12 +; SSE2-NEXT: .LBB15_11: # %else12 ; SSE2-NEXT: testb %al, %al -; SSE2-NEXT: jns .LBB15_16 -; SSE2-NEXT: # %bb.15: # %cond.store13 +; SSE2-NEXT: jns .LBB15_13 +; SSE2-NEXT: # %bb.12: # %cond.store13 ; SSE2-NEXT: movb %ch, 7(%rdi) -; SSE2-NEXT: .LBB15_16: # %else14 +; SSE2-NEXT: .LBB15_13: # %else14 ; SSE2-NEXT: testl $256, %eax # imm = 0x100 ; SSE2-NEXT: pextrw $4, %xmm0, %ecx -; SSE2-NEXT: je .LBB15_18 -; SSE2-NEXT: # %bb.17: # %cond.store15 +; SSE2-NEXT: je .LBB15_15 +; SSE2-NEXT: # %bb.14: # %cond.store15 ; SSE2-NEXT: movb %cl, 8(%rdi) -; SSE2-NEXT: .LBB15_18: # %else16 +; SSE2-NEXT: .LBB15_15: # %else16 ; SSE2-NEXT: testl $512, %eax # imm = 0x200 -; SSE2-NEXT: je .LBB15_20 -; SSE2-NEXT: # %bb.19: # %cond.store17 +; SSE2-NEXT: je .LBB15_17 +; SSE2-NEXT: # %bb.16: # %cond.store17 ; SSE2-NEXT: movb %ch, 9(%rdi) -; SSE2-NEXT: .LBB15_20: # %else18 +; SSE2-NEXT: .LBB15_17: # %else18 ; SSE2-NEXT: testl $1024, %eax # imm = 0x400 ; SSE2-NEXT: pextrw $5, %xmm0, %ecx -; SSE2-NEXT: je .LBB15_22 -; SSE2-NEXT: # %bb.21: # %cond.store19 +; SSE2-NEXT: je .LBB15_19 +; SSE2-NEXT: # %bb.18: # %cond.store19 ; SSE2-NEXT: movb %cl, 10(%rdi) -; SSE2-NEXT: .LBB15_22: # %else20 +; SSE2-NEXT: .LBB15_19: # %else20 ; SSE2-NEXT: testl $2048, %eax # imm = 0x800 -; SSE2-NEXT: je .LBB15_24 -; SSE2-NEXT: # %bb.23: # %cond.store21 +; SSE2-NEXT: je .LBB15_21 +; SSE2-NEXT: # %bb.20: # %cond.store21 ; SSE2-NEXT: movb %ch, 11(%rdi) -; SSE2-NEXT: .LBB15_24: # %else22 +; SSE2-NEXT: .LBB15_21: # %else22 ; SSE2-NEXT: testl $4096, %eax # imm = 0x1000 ; SSE2-NEXT: pextrw $6, %xmm0, %ecx -; SSE2-NEXT: je .LBB15_26 -; SSE2-NEXT: # %bb.25: # %cond.store23 +; SSE2-NEXT: je .LBB15_23 +; SSE2-NEXT: # %bb.22: # %cond.store23 ; SSE2-NEXT: movb %cl, 12(%rdi) -; SSE2-NEXT: .LBB15_26: # %else24 +; SSE2-NEXT: .LBB15_23: # %else24 ; SSE2-NEXT: movdqa %xmm3, %xmm1 ; SSE2-NEXT: psubusw %xmm6, %xmm1 ; SSE2-NEXT: movdqa %xmm2, %xmm4 ; SSE2-NEXT: psubusw %xmm6, %xmm4 ; SSE2-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE2-NEXT: je .LBB15_28 -; SSE2-NEXT: # %bb.27: # %cond.store25 +; SSE2-NEXT: je .LBB15_25 +; SSE2-NEXT: # %bb.24: # %cond.store25 ; SSE2-NEXT: movb %ch, 13(%rdi) -; SSE2-NEXT: .LBB15_28: # %else26 +; SSE2-NEXT: .LBB15_25: # %else26 ; SSE2-NEXT: psubw %xmm1, %xmm3 ; SSE2-NEXT: psubw %xmm4, %xmm2 ; SSE2-NEXT: testl $16384, %eax # imm = 0x4000 ; SSE2-NEXT: pextrw $7, %xmm0, %ecx -; SSE2-NEXT: je .LBB15_30 -; SSE2-NEXT: # %bb.29: # %cond.store27 +; SSE2-NEXT: je .LBB15_27 +; SSE2-NEXT: # %bb.26: # %cond.store27 ; SSE2-NEXT: movb %cl, 14(%rdi) -; SSE2-NEXT: .LBB15_30: # %else28 +; SSE2-NEXT: .LBB15_27: # %else28 ; SSE2-NEXT: packuswb %xmm3, %xmm2 ; SSE2-NEXT: testw %ax, %ax -; SSE2-NEXT: jns .LBB15_32 -; SSE2-NEXT: # %bb.31: # %cond.store29 +; SSE2-NEXT: jns .LBB15_29 +; SSE2-NEXT: # %bb.28: # %cond.store29 ; SSE2-NEXT: movb %ch, 15(%rdi) -; SSE2-NEXT: .LBB15_32: # %else30 +; SSE2-NEXT: .LBB15_29: # %else30 ; SSE2-NEXT: testl $65536, %eax # imm = 0x10000 ; SSE2-NEXT: movd %xmm2, %ecx -; SSE2-NEXT: jne .LBB15_33 -; SSE2-NEXT: # %bb.34: # %else32 +; SSE2-NEXT: jne .LBB15_60 +; SSE2-NEXT: # %bb.30: # %else32 ; SSE2-NEXT: testl $131072, %eax # imm = 0x20000 -; SSE2-NEXT: jne .LBB15_35 -; SSE2-NEXT: .LBB15_36: # %else34 +; SSE2-NEXT: jne .LBB15_61 +; SSE2-NEXT: .LBB15_31: # %else34 ; SSE2-NEXT: testl $262144, %eax # imm = 0x40000 -; SSE2-NEXT: jne .LBB15_37 -; SSE2-NEXT: .LBB15_38: # %else36 +; SSE2-NEXT: jne .LBB15_62 +; SSE2-NEXT: .LBB15_32: # %else36 ; SSE2-NEXT: testl $524288, %eax # imm = 0x80000 -; SSE2-NEXT: je .LBB15_40 -; SSE2-NEXT: .LBB15_39: # %cond.store37 +; SSE2-NEXT: je .LBB15_34 +; SSE2-NEXT: .LBB15_33: # %cond.store37 ; SSE2-NEXT: shrl $24, %ecx ; SSE2-NEXT: movb %cl, 19(%rdi) -; SSE2-NEXT: .LBB15_40: # %else38 +; SSE2-NEXT: .LBB15_34: # %else38 ; SSE2-NEXT: testl $1048576, %eax # imm = 0x100000 ; SSE2-NEXT: pextrw $2, %xmm2, %ecx -; SSE2-NEXT: je .LBB15_42 -; SSE2-NEXT: # %bb.41: # %cond.store39 +; SSE2-NEXT: je .LBB15_36 +; SSE2-NEXT: # %bb.35: # %cond.store39 ; SSE2-NEXT: movb %cl, 20(%rdi) -; SSE2-NEXT: .LBB15_42: # %else40 +; SSE2-NEXT: .LBB15_36: # %else40 ; SSE2-NEXT: testl $2097152, %eax # imm = 0x200000 -; SSE2-NEXT: je .LBB15_44 -; SSE2-NEXT: # %bb.43: # %cond.store41 +; SSE2-NEXT: je .LBB15_38 +; SSE2-NEXT: # %bb.37: # %cond.store41 ; SSE2-NEXT: movb %ch, 21(%rdi) -; SSE2-NEXT: .LBB15_44: # %else42 +; SSE2-NEXT: .LBB15_38: # %else42 ; SSE2-NEXT: testl $4194304, %eax # imm = 0x400000 ; SSE2-NEXT: pextrw $3, %xmm2, %ecx -; SSE2-NEXT: je .LBB15_46 -; SSE2-NEXT: # %bb.45: # %cond.store43 +; SSE2-NEXT: je .LBB15_40 +; SSE2-NEXT: # %bb.39: # %cond.store43 ; SSE2-NEXT: movb %cl, 22(%rdi) -; SSE2-NEXT: .LBB15_46: # %else44 +; SSE2-NEXT: .LBB15_40: # %else44 ; SSE2-NEXT: testl $8388608, %eax # imm = 0x800000 -; SSE2-NEXT: je .LBB15_48 -; SSE2-NEXT: # %bb.47: # %cond.store45 +; SSE2-NEXT: je .LBB15_42 +; SSE2-NEXT: # %bb.41: # %cond.store45 ; SSE2-NEXT: movb %ch, 23(%rdi) -; SSE2-NEXT: .LBB15_48: # %else46 +; SSE2-NEXT: .LBB15_42: # %else46 ; SSE2-NEXT: testl $16777216, %eax # imm = 0x1000000 ; SSE2-NEXT: pextrw $4, %xmm2, %ecx -; SSE2-NEXT: je .LBB15_50 -; SSE2-NEXT: # %bb.49: # %cond.store47 +; SSE2-NEXT: je .LBB15_44 +; SSE2-NEXT: # %bb.43: # %cond.store47 ; SSE2-NEXT: movb %cl, 24(%rdi) -; SSE2-NEXT: .LBB15_50: # %else48 +; SSE2-NEXT: .LBB15_44: # %else48 ; SSE2-NEXT: testl $33554432, %eax # imm = 0x2000000 -; SSE2-NEXT: je .LBB15_52 -; SSE2-NEXT: # %bb.51: # %cond.store49 +; SSE2-NEXT: je .LBB15_46 +; SSE2-NEXT: # %bb.45: # %cond.store49 ; SSE2-NEXT: movb %ch, 25(%rdi) -; SSE2-NEXT: .LBB15_52: # %else50 +; SSE2-NEXT: .LBB15_46: # %else50 ; SSE2-NEXT: testl $67108864, %eax # imm = 0x4000000 ; SSE2-NEXT: pextrw $5, %xmm2, %ecx -; SSE2-NEXT: je .LBB15_54 -; SSE2-NEXT: # %bb.53: # %cond.store51 +; SSE2-NEXT: je .LBB15_48 +; SSE2-NEXT: # %bb.47: # %cond.store51 ; SSE2-NEXT: movb %cl, 26(%rdi) -; SSE2-NEXT: .LBB15_54: # %else52 +; SSE2-NEXT: .LBB15_48: # %else52 ; SSE2-NEXT: testl $134217728, %eax # imm = 0x8000000 -; SSE2-NEXT: je .LBB15_56 -; SSE2-NEXT: # %bb.55: # %cond.store53 +; SSE2-NEXT: je .LBB15_50 +; SSE2-NEXT: # %bb.49: # %cond.store53 ; SSE2-NEXT: movb %ch, 27(%rdi) -; SSE2-NEXT: .LBB15_56: # %else54 +; SSE2-NEXT: .LBB15_50: # %else54 ; SSE2-NEXT: testl $268435456, %eax # imm = 0x10000000 ; SSE2-NEXT: pextrw $6, %xmm2, %ecx -; SSE2-NEXT: je .LBB15_58 -; SSE2-NEXT: # %bb.57: # %cond.store55 +; SSE2-NEXT: je .LBB15_52 +; SSE2-NEXT: # %bb.51: # %cond.store55 ; SSE2-NEXT: movb %cl, 28(%rdi) -; SSE2-NEXT: .LBB15_58: # %else56 +; SSE2-NEXT: .LBB15_52: # %else56 ; SSE2-NEXT: testl $536870912, %eax # imm = 0x20000000 -; SSE2-NEXT: je .LBB15_60 -; SSE2-NEXT: # %bb.59: # %cond.store57 +; SSE2-NEXT: je .LBB15_54 +; SSE2-NEXT: # %bb.53: # %cond.store57 ; SSE2-NEXT: movb %ch, 29(%rdi) -; SSE2-NEXT: .LBB15_60: # %else58 +; SSE2-NEXT: .LBB15_54: # %else58 ; SSE2-NEXT: testl $1073741824, %eax # imm = 0x40000000 ; SSE2-NEXT: pextrw $7, %xmm2, %ecx -; SSE2-NEXT: jne .LBB15_61 -; SSE2-NEXT: # %bb.62: # %else60 -; SSE2-NEXT: testl $-2147483648, %eax # imm = 0x80000000 ; SSE2-NEXT: jne .LBB15_63 -; SSE2-NEXT: .LBB15_64: # %else62 +; SSE2-NEXT: # %bb.55: # %else60 +; SSE2-NEXT: testl $-2147483648, %eax # imm = 0x80000000 +; SSE2-NEXT: jne .LBB15_64 +; SSE2-NEXT: .LBB15_56: # %else62 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB15_1: # %cond.store +; SSE2-NEXT: .LBB15_57: # %cond.store ; SSE2-NEXT: movb %cl, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB15_4 -; SSE2-NEXT: .LBB15_3: # %cond.store1 +; SSE2-NEXT: je .LBB15_2 +; SSE2-NEXT: .LBB15_58: # %cond.store1 ; SSE2-NEXT: movb %ch, 1(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je .LBB15_6 -; SSE2-NEXT: .LBB15_5: # %cond.store3 +; SSE2-NEXT: je .LBB15_3 +; SSE2-NEXT: .LBB15_59: # %cond.store3 ; SSE2-NEXT: movl %ecx, %edx ; SSE2-NEXT: shrl $16, %edx ; SSE2-NEXT: movb %dl, 2(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne .LBB15_7 -; SSE2-NEXT: jmp .LBB15_8 -; SSE2-NEXT: .LBB15_33: # %cond.store31 +; SSE2-NEXT: jne .LBB15_4 +; SSE2-NEXT: jmp .LBB15_5 +; SSE2-NEXT: .LBB15_60: # %cond.store31 ; SSE2-NEXT: movb %cl, 16(%rdi) ; SSE2-NEXT: testl $131072, %eax # imm = 0x20000 -; SSE2-NEXT: je .LBB15_36 -; SSE2-NEXT: .LBB15_35: # %cond.store33 +; SSE2-NEXT: je .LBB15_31 +; SSE2-NEXT: .LBB15_61: # %cond.store33 ; SSE2-NEXT: movb %ch, 17(%rdi) ; SSE2-NEXT: testl $262144, %eax # imm = 0x40000 -; SSE2-NEXT: je .LBB15_38 -; SSE2-NEXT: .LBB15_37: # %cond.store35 +; SSE2-NEXT: je .LBB15_32 +; SSE2-NEXT: .LBB15_62: # %cond.store35 ; SSE2-NEXT: movl %ecx, %edx ; SSE2-NEXT: shrl $16, %edx ; SSE2-NEXT: movb %dl, 18(%rdi) ; SSE2-NEXT: testl $524288, %eax # imm = 0x80000 -; SSE2-NEXT: jne .LBB15_39 -; SSE2-NEXT: jmp .LBB15_40 -; SSE2-NEXT: .LBB15_61: # %cond.store59 +; SSE2-NEXT: jne .LBB15_33 +; SSE2-NEXT: jmp .LBB15_34 +; SSE2-NEXT: .LBB15_63: # %cond.store59 ; SSE2-NEXT: movb %cl, 30(%rdi) ; SSE2-NEXT: testl $-2147483648, %eax # imm = 0x80000000 -; SSE2-NEXT: je .LBB15_64 -; SSE2-NEXT: .LBB15_63: # %cond.store61 +; SSE2-NEXT: je .LBB15_56 +; SSE2-NEXT: .LBB15_64: # %cond.store61 ; SSE2-NEXT: movb %ch, 31(%rdi) ; SSE2-NEXT: retq ; @@ -5982,227 +5982,227 @@ define void @truncstore_v32i16_v32i8(<32 x i16> %x, ptr %p, <32 x i8> %mask) { ; SSE4-NEXT: shll $16, %eax ; SSE4-NEXT: orl %ecx, %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB15_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB15_35 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB15_3 -; SSE4-NEXT: .LBB15_4: # %else2 +; SSE4-NEXT: jne .LBB15_36 +; SSE4-NEXT: .LBB15_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB15_5 -; SSE4-NEXT: .LBB15_6: # %else4 +; SSE4-NEXT: jne .LBB15_37 +; SSE4-NEXT: .LBB15_3: # %else4 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne .LBB15_7 -; SSE4-NEXT: .LBB15_8: # %else6 +; SSE4-NEXT: jne .LBB15_38 +; SSE4-NEXT: .LBB15_4: # %else6 ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: jne .LBB15_9 -; SSE4-NEXT: .LBB15_10: # %else8 +; SSE4-NEXT: jne .LBB15_39 +; SSE4-NEXT: .LBB15_5: # %else8 ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: jne .LBB15_11 -; SSE4-NEXT: .LBB15_12: # %else10 +; SSE4-NEXT: jne .LBB15_40 +; SSE4-NEXT: .LBB15_6: # %else10 ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: jne .LBB15_13 -; SSE4-NEXT: .LBB15_14: # %else12 +; SSE4-NEXT: jne .LBB15_41 +; SSE4-NEXT: .LBB15_7: # %else12 ; SSE4-NEXT: testb %al, %al -; SSE4-NEXT: js .LBB15_15 -; SSE4-NEXT: .LBB15_16: # %else14 +; SSE4-NEXT: js .LBB15_42 +; SSE4-NEXT: .LBB15_8: # %else14 ; SSE4-NEXT: testl $256, %eax # imm = 0x100 -; SSE4-NEXT: jne .LBB15_17 -; SSE4-NEXT: .LBB15_18: # %else16 +; SSE4-NEXT: jne .LBB15_43 +; SSE4-NEXT: .LBB15_9: # %else16 ; SSE4-NEXT: testl $512, %eax # imm = 0x200 -; SSE4-NEXT: jne .LBB15_19 -; SSE4-NEXT: .LBB15_20: # %else18 +; SSE4-NEXT: jne .LBB15_44 +; SSE4-NEXT: .LBB15_10: # %else18 ; SSE4-NEXT: testl $1024, %eax # imm = 0x400 -; SSE4-NEXT: jne .LBB15_21 -; SSE4-NEXT: .LBB15_22: # %else20 +; SSE4-NEXT: jne .LBB15_45 +; SSE4-NEXT: .LBB15_11: # %else20 ; SSE4-NEXT: testl $2048, %eax # imm = 0x800 -; SSE4-NEXT: jne .LBB15_23 -; SSE4-NEXT: .LBB15_24: # %else22 +; SSE4-NEXT: jne .LBB15_46 +; SSE4-NEXT: .LBB15_12: # %else22 ; SSE4-NEXT: testl $4096, %eax # imm = 0x1000 -; SSE4-NEXT: jne .LBB15_25 -; SSE4-NEXT: .LBB15_26: # %else24 +; SSE4-NEXT: jne .LBB15_47 +; SSE4-NEXT: .LBB15_13: # %else24 ; SSE4-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE4-NEXT: jne .LBB15_27 -; SSE4-NEXT: .LBB15_28: # %else26 +; SSE4-NEXT: jne .LBB15_48 +; SSE4-NEXT: .LBB15_14: # %else26 ; SSE4-NEXT: testl $16384, %eax # imm = 0x4000 -; SSE4-NEXT: je .LBB15_30 -; SSE4-NEXT: .LBB15_29: # %cond.store27 +; SSE4-NEXT: je .LBB15_16 +; SSE4-NEXT: .LBB15_15: # %cond.store27 ; SSE4-NEXT: pextrb $14, %xmm0, 14(%rdi) -; SSE4-NEXT: .LBB15_30: # %else28 +; SSE4-NEXT: .LBB15_16: # %else28 ; SSE4-NEXT: pminuw %xmm6, %xmm3 ; SSE4-NEXT: pminuw %xmm6, %xmm2 ; SSE4-NEXT: testw %ax, %ax -; SSE4-NEXT: jns .LBB15_32 -; SSE4-NEXT: # %bb.31: # %cond.store29 +; SSE4-NEXT: jns .LBB15_18 +; SSE4-NEXT: # %bb.17: # %cond.store29 ; SSE4-NEXT: pextrb $15, %xmm0, 15(%rdi) -; SSE4-NEXT: .LBB15_32: # %else30 +; SSE4-NEXT: .LBB15_18: # %else30 ; SSE4-NEXT: packuswb %xmm3, %xmm2 ; SSE4-NEXT: testl $65536, %eax # imm = 0x10000 -; SSE4-NEXT: jne .LBB15_33 -; SSE4-NEXT: # %bb.34: # %else32 +; SSE4-NEXT: jne .LBB15_49 +; SSE4-NEXT: # %bb.19: # %else32 ; SSE4-NEXT: testl $131072, %eax # imm = 0x20000 -; SSE4-NEXT: jne .LBB15_35 -; SSE4-NEXT: .LBB15_36: # %else34 +; SSE4-NEXT: jne .LBB15_50 +; SSE4-NEXT: .LBB15_20: # %else34 ; SSE4-NEXT: testl $262144, %eax # imm = 0x40000 -; SSE4-NEXT: jne .LBB15_37 -; SSE4-NEXT: .LBB15_38: # %else36 +; SSE4-NEXT: jne .LBB15_51 +; SSE4-NEXT: .LBB15_21: # %else36 ; SSE4-NEXT: testl $524288, %eax # imm = 0x80000 -; SSE4-NEXT: jne .LBB15_39 -; SSE4-NEXT: .LBB15_40: # %else38 +; SSE4-NEXT: jne .LBB15_52 +; SSE4-NEXT: .LBB15_22: # %else38 ; SSE4-NEXT: testl $1048576, %eax # imm = 0x100000 -; SSE4-NEXT: jne .LBB15_41 -; SSE4-NEXT: .LBB15_42: # %else40 +; SSE4-NEXT: jne .LBB15_53 +; SSE4-NEXT: .LBB15_23: # %else40 ; SSE4-NEXT: testl $2097152, %eax # imm = 0x200000 -; SSE4-NEXT: jne .LBB15_43 -; SSE4-NEXT: .LBB15_44: # %else42 +; SSE4-NEXT: jne .LBB15_54 +; SSE4-NEXT: .LBB15_24: # %else42 ; SSE4-NEXT: testl $4194304, %eax # imm = 0x400000 -; SSE4-NEXT: jne .LBB15_45 -; SSE4-NEXT: .LBB15_46: # %else44 +; SSE4-NEXT: jne .LBB15_55 +; SSE4-NEXT: .LBB15_25: # %else44 ; SSE4-NEXT: testl $8388608, %eax # imm = 0x800000 -; SSE4-NEXT: jne .LBB15_47 -; SSE4-NEXT: .LBB15_48: # %else46 +; SSE4-NEXT: jne .LBB15_56 +; SSE4-NEXT: .LBB15_26: # %else46 ; SSE4-NEXT: testl $16777216, %eax # imm = 0x1000000 -; SSE4-NEXT: jne .LBB15_49 -; SSE4-NEXT: .LBB15_50: # %else48 +; SSE4-NEXT: jne .LBB15_57 +; SSE4-NEXT: .LBB15_27: # %else48 ; SSE4-NEXT: testl $33554432, %eax # imm = 0x2000000 -; SSE4-NEXT: jne .LBB15_51 -; SSE4-NEXT: .LBB15_52: # %else50 +; SSE4-NEXT: jne .LBB15_58 +; SSE4-NEXT: .LBB15_28: # %else50 ; SSE4-NEXT: testl $67108864, %eax # imm = 0x4000000 -; SSE4-NEXT: jne .LBB15_53 -; SSE4-NEXT: .LBB15_54: # %else52 +; SSE4-NEXT: jne .LBB15_59 +; SSE4-NEXT: .LBB15_29: # %else52 ; SSE4-NEXT: testl $134217728, %eax # imm = 0x8000000 -; SSE4-NEXT: jne .LBB15_55 -; SSE4-NEXT: .LBB15_56: # %else54 +; SSE4-NEXT: jne .LBB15_60 +; SSE4-NEXT: .LBB15_30: # %else54 ; SSE4-NEXT: testl $268435456, %eax # imm = 0x10000000 -; SSE4-NEXT: jne .LBB15_57 -; SSE4-NEXT: .LBB15_58: # %else56 +; SSE4-NEXT: jne .LBB15_61 +; SSE4-NEXT: .LBB15_31: # %else56 ; SSE4-NEXT: testl $536870912, %eax # imm = 0x20000000 -; SSE4-NEXT: jne .LBB15_59 -; SSE4-NEXT: .LBB15_60: # %else58 +; SSE4-NEXT: jne .LBB15_62 +; SSE4-NEXT: .LBB15_32: # %else58 ; SSE4-NEXT: testl $1073741824, %eax # imm = 0x40000000 -; SSE4-NEXT: jne .LBB15_61 -; SSE4-NEXT: .LBB15_62: # %else60 -; SSE4-NEXT: testl $-2147483648, %eax # imm = 0x80000000 ; SSE4-NEXT: jne .LBB15_63 -; SSE4-NEXT: .LBB15_64: # %else62 +; SSE4-NEXT: .LBB15_33: # %else60 +; SSE4-NEXT: testl $-2147483648, %eax # imm = 0x80000000 +; SSE4-NEXT: jne .LBB15_64 +; SSE4-NEXT: .LBB15_34: # %else62 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB15_1: # %cond.store +; SSE4-NEXT: .LBB15_35: # %cond.store ; SSE4-NEXT: pextrb $0, %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB15_4 -; SSE4-NEXT: .LBB15_3: # %cond.store1 +; SSE4-NEXT: je .LBB15_2 +; SSE4-NEXT: .LBB15_36: # %cond.store1 ; SSE4-NEXT: pextrb $1, %xmm0, 1(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB15_6 -; SSE4-NEXT: .LBB15_5: # %cond.store3 +; SSE4-NEXT: je .LBB15_3 +; SSE4-NEXT: .LBB15_37: # %cond.store3 ; SSE4-NEXT: pextrb $2, %xmm0, 2(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB15_8 -; SSE4-NEXT: .LBB15_7: # %cond.store5 +; SSE4-NEXT: je .LBB15_4 +; SSE4-NEXT: .LBB15_38: # %cond.store5 ; SSE4-NEXT: pextrb $3, %xmm0, 3(%rdi) ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: je .LBB15_10 -; SSE4-NEXT: .LBB15_9: # %cond.store7 +; SSE4-NEXT: je .LBB15_5 +; SSE4-NEXT: .LBB15_39: # %cond.store7 ; SSE4-NEXT: pextrb $4, %xmm0, 4(%rdi) ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: je .LBB15_12 -; SSE4-NEXT: .LBB15_11: # %cond.store9 +; SSE4-NEXT: je .LBB15_6 +; SSE4-NEXT: .LBB15_40: # %cond.store9 ; SSE4-NEXT: pextrb $5, %xmm0, 5(%rdi) ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: je .LBB15_14 -; SSE4-NEXT: .LBB15_13: # %cond.store11 +; SSE4-NEXT: je .LBB15_7 +; SSE4-NEXT: .LBB15_41: # %cond.store11 ; SSE4-NEXT: pextrb $6, %xmm0, 6(%rdi) ; SSE4-NEXT: testb %al, %al -; SSE4-NEXT: jns .LBB15_16 -; SSE4-NEXT: .LBB15_15: # %cond.store13 +; SSE4-NEXT: jns .LBB15_8 +; SSE4-NEXT: .LBB15_42: # %cond.store13 ; SSE4-NEXT: pextrb $7, %xmm0, 7(%rdi) ; SSE4-NEXT: testl $256, %eax # imm = 0x100 -; SSE4-NEXT: je .LBB15_18 -; SSE4-NEXT: .LBB15_17: # %cond.store15 +; SSE4-NEXT: je .LBB15_9 +; SSE4-NEXT: .LBB15_43: # %cond.store15 ; SSE4-NEXT: pextrb $8, %xmm0, 8(%rdi) ; SSE4-NEXT: testl $512, %eax # imm = 0x200 -; SSE4-NEXT: je .LBB15_20 -; SSE4-NEXT: .LBB15_19: # %cond.store17 +; SSE4-NEXT: je .LBB15_10 +; SSE4-NEXT: .LBB15_44: # %cond.store17 ; SSE4-NEXT: pextrb $9, %xmm0, 9(%rdi) ; SSE4-NEXT: testl $1024, %eax # imm = 0x400 -; SSE4-NEXT: je .LBB15_22 -; SSE4-NEXT: .LBB15_21: # %cond.store19 +; SSE4-NEXT: je .LBB15_11 +; SSE4-NEXT: .LBB15_45: # %cond.store19 ; SSE4-NEXT: pextrb $10, %xmm0, 10(%rdi) ; SSE4-NEXT: testl $2048, %eax # imm = 0x800 -; SSE4-NEXT: je .LBB15_24 -; SSE4-NEXT: .LBB15_23: # %cond.store21 +; SSE4-NEXT: je .LBB15_12 +; SSE4-NEXT: .LBB15_46: # %cond.store21 ; SSE4-NEXT: pextrb $11, %xmm0, 11(%rdi) ; SSE4-NEXT: testl $4096, %eax # imm = 0x1000 -; SSE4-NEXT: je .LBB15_26 -; SSE4-NEXT: .LBB15_25: # %cond.store23 +; SSE4-NEXT: je .LBB15_13 +; SSE4-NEXT: .LBB15_47: # %cond.store23 ; SSE4-NEXT: pextrb $12, %xmm0, 12(%rdi) ; SSE4-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE4-NEXT: je .LBB15_28 -; SSE4-NEXT: .LBB15_27: # %cond.store25 +; SSE4-NEXT: je .LBB15_14 +; SSE4-NEXT: .LBB15_48: # %cond.store25 ; SSE4-NEXT: pextrb $13, %xmm0, 13(%rdi) ; SSE4-NEXT: testl $16384, %eax # imm = 0x4000 -; SSE4-NEXT: jne .LBB15_29 -; SSE4-NEXT: jmp .LBB15_30 -; SSE4-NEXT: .LBB15_33: # %cond.store31 +; SSE4-NEXT: jne .LBB15_15 +; SSE4-NEXT: jmp .LBB15_16 +; SSE4-NEXT: .LBB15_49: # %cond.store31 ; SSE4-NEXT: pextrb $0, %xmm2, 16(%rdi) ; SSE4-NEXT: testl $131072, %eax # imm = 0x20000 -; SSE4-NEXT: je .LBB15_36 -; SSE4-NEXT: .LBB15_35: # %cond.store33 +; SSE4-NEXT: je .LBB15_20 +; SSE4-NEXT: .LBB15_50: # %cond.store33 ; SSE4-NEXT: pextrb $1, %xmm2, 17(%rdi) ; SSE4-NEXT: testl $262144, %eax # imm = 0x40000 -; SSE4-NEXT: je .LBB15_38 -; SSE4-NEXT: .LBB15_37: # %cond.store35 +; SSE4-NEXT: je .LBB15_21 +; SSE4-NEXT: .LBB15_51: # %cond.store35 ; SSE4-NEXT: pextrb $2, %xmm2, 18(%rdi) ; SSE4-NEXT: testl $524288, %eax # imm = 0x80000 -; SSE4-NEXT: je .LBB15_40 -; SSE4-NEXT: .LBB15_39: # %cond.store37 +; SSE4-NEXT: je .LBB15_22 +; SSE4-NEXT: .LBB15_52: # %cond.store37 ; SSE4-NEXT: pextrb $3, %xmm2, 19(%rdi) ; SSE4-NEXT: testl $1048576, %eax # imm = 0x100000 -; SSE4-NEXT: je .LBB15_42 -; SSE4-NEXT: .LBB15_41: # %cond.store39 +; SSE4-NEXT: je .LBB15_23 +; SSE4-NEXT: .LBB15_53: # %cond.store39 ; SSE4-NEXT: pextrb $4, %xmm2, 20(%rdi) ; SSE4-NEXT: testl $2097152, %eax # imm = 0x200000 -; SSE4-NEXT: je .LBB15_44 -; SSE4-NEXT: .LBB15_43: # %cond.store41 +; SSE4-NEXT: je .LBB15_24 +; SSE4-NEXT: .LBB15_54: # %cond.store41 ; SSE4-NEXT: pextrb $5, %xmm2, 21(%rdi) ; SSE4-NEXT: testl $4194304, %eax # imm = 0x400000 -; SSE4-NEXT: je .LBB15_46 -; SSE4-NEXT: .LBB15_45: # %cond.store43 +; SSE4-NEXT: je .LBB15_25 +; SSE4-NEXT: .LBB15_55: # %cond.store43 ; SSE4-NEXT: pextrb $6, %xmm2, 22(%rdi) ; SSE4-NEXT: testl $8388608, %eax # imm = 0x800000 -; SSE4-NEXT: je .LBB15_48 -; SSE4-NEXT: .LBB15_47: # %cond.store45 +; SSE4-NEXT: je .LBB15_26 +; SSE4-NEXT: .LBB15_56: # %cond.store45 ; SSE4-NEXT: pextrb $7, %xmm2, 23(%rdi) ; SSE4-NEXT: testl $16777216, %eax # imm = 0x1000000 -; SSE4-NEXT: je .LBB15_50 -; SSE4-NEXT: .LBB15_49: # %cond.store47 +; SSE4-NEXT: je .LBB15_27 +; SSE4-NEXT: .LBB15_57: # %cond.store47 ; SSE4-NEXT: pextrb $8, %xmm2, 24(%rdi) ; SSE4-NEXT: testl $33554432, %eax # imm = 0x2000000 -; SSE4-NEXT: je .LBB15_52 -; SSE4-NEXT: .LBB15_51: # %cond.store49 +; SSE4-NEXT: je .LBB15_28 +; SSE4-NEXT: .LBB15_58: # %cond.store49 ; SSE4-NEXT: pextrb $9, %xmm2, 25(%rdi) ; SSE4-NEXT: testl $67108864, %eax # imm = 0x4000000 -; SSE4-NEXT: je .LBB15_54 -; SSE4-NEXT: .LBB15_53: # %cond.store51 +; SSE4-NEXT: je .LBB15_29 +; SSE4-NEXT: .LBB15_59: # %cond.store51 ; SSE4-NEXT: pextrb $10, %xmm2, 26(%rdi) ; SSE4-NEXT: testl $134217728, %eax # imm = 0x8000000 -; SSE4-NEXT: je .LBB15_56 -; SSE4-NEXT: .LBB15_55: # %cond.store53 +; SSE4-NEXT: je .LBB15_30 +; SSE4-NEXT: .LBB15_60: # %cond.store53 ; SSE4-NEXT: pextrb $11, %xmm2, 27(%rdi) ; SSE4-NEXT: testl $268435456, %eax # imm = 0x10000000 -; SSE4-NEXT: je .LBB15_58 -; SSE4-NEXT: .LBB15_57: # %cond.store55 +; SSE4-NEXT: je .LBB15_31 +; SSE4-NEXT: .LBB15_61: # %cond.store55 ; SSE4-NEXT: pextrb $12, %xmm2, 28(%rdi) ; SSE4-NEXT: testl $536870912, %eax # imm = 0x20000000 -; SSE4-NEXT: je .LBB15_60 -; SSE4-NEXT: .LBB15_59: # %cond.store57 +; SSE4-NEXT: je .LBB15_32 +; SSE4-NEXT: .LBB15_62: # %cond.store57 ; SSE4-NEXT: pextrb $13, %xmm2, 29(%rdi) ; SSE4-NEXT: testl $1073741824, %eax # imm = 0x40000000 -; SSE4-NEXT: je .LBB15_62 -; SSE4-NEXT: .LBB15_61: # %cond.store59 +; SSE4-NEXT: je .LBB15_33 +; SSE4-NEXT: .LBB15_63: # %cond.store59 ; SSE4-NEXT: pextrb $14, %xmm2, 30(%rdi) ; SSE4-NEXT: testl $-2147483648, %eax # imm = 0x80000000 -; SSE4-NEXT: je .LBB15_64 -; SSE4-NEXT: .LBB15_63: # %cond.store61 +; SSE4-NEXT: je .LBB15_34 +; SSE4-NEXT: .LBB15_64: # %cond.store61 ; SSE4-NEXT: pextrb $15, %xmm2, 31(%rdi) ; SSE4-NEXT: retq ; @@ -6229,228 +6229,228 @@ define void @truncstore_v32i16_v32i8(<32 x i16> %x, ptr %p, <32 x i8> %mask) { ; AVX1-NEXT: shll $16, %eax ; AVX1-NEXT: orl %ecx, %eax ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne .LBB15_1 -; AVX1-NEXT: # %bb.2: # %else +; AVX1-NEXT: jne .LBB15_34 +; AVX1-NEXT: # %bb.1: # %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne .LBB15_3 -; AVX1-NEXT: .LBB15_4: # %else2 +; AVX1-NEXT: jne .LBB15_35 +; AVX1-NEXT: .LBB15_2: # %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne .LBB15_5 -; AVX1-NEXT: .LBB15_6: # %else4 +; AVX1-NEXT: jne .LBB15_36 +; AVX1-NEXT: .LBB15_3: # %else4 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne .LBB15_7 -; AVX1-NEXT: .LBB15_8: # %else6 +; AVX1-NEXT: jne .LBB15_37 +; AVX1-NEXT: .LBB15_4: # %else6 ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: jne .LBB15_9 -; AVX1-NEXT: .LBB15_10: # %else8 +; AVX1-NEXT: jne .LBB15_38 +; AVX1-NEXT: .LBB15_5: # %else8 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: jne .LBB15_11 -; AVX1-NEXT: .LBB15_12: # %else10 +; AVX1-NEXT: jne .LBB15_39 +; AVX1-NEXT: .LBB15_6: # %else10 ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: jne .LBB15_13 -; AVX1-NEXT: .LBB15_14: # %else12 +; AVX1-NEXT: jne .LBB15_40 +; AVX1-NEXT: .LBB15_7: # %else12 ; AVX1-NEXT: testb %al, %al -; AVX1-NEXT: js .LBB15_15 -; AVX1-NEXT: .LBB15_16: # %else14 +; AVX1-NEXT: js .LBB15_41 +; AVX1-NEXT: .LBB15_8: # %else14 ; AVX1-NEXT: testl $256, %eax # imm = 0x100 -; AVX1-NEXT: jne .LBB15_17 -; AVX1-NEXT: .LBB15_18: # %else16 +; AVX1-NEXT: jne .LBB15_42 +; AVX1-NEXT: .LBB15_9: # %else16 ; AVX1-NEXT: testl $512, %eax # imm = 0x200 -; AVX1-NEXT: jne .LBB15_19 -; AVX1-NEXT: .LBB15_20: # %else18 +; AVX1-NEXT: jne .LBB15_43 +; AVX1-NEXT: .LBB15_10: # %else18 ; AVX1-NEXT: testl $1024, %eax # imm = 0x400 -; AVX1-NEXT: jne .LBB15_21 -; AVX1-NEXT: .LBB15_22: # %else20 +; AVX1-NEXT: jne .LBB15_44 +; AVX1-NEXT: .LBB15_11: # %else20 ; AVX1-NEXT: testl $2048, %eax # imm = 0x800 -; AVX1-NEXT: jne .LBB15_23 -; AVX1-NEXT: .LBB15_24: # %else22 +; AVX1-NEXT: jne .LBB15_45 +; AVX1-NEXT: .LBB15_12: # %else22 ; AVX1-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX1-NEXT: jne .LBB15_25 -; AVX1-NEXT: .LBB15_26: # %else24 +; AVX1-NEXT: jne .LBB15_46 +; AVX1-NEXT: .LBB15_13: # %else24 ; AVX1-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX1-NEXT: jne .LBB15_27 -; AVX1-NEXT: .LBB15_28: # %else26 +; AVX1-NEXT: jne .LBB15_47 +; AVX1-NEXT: .LBB15_14: # %else26 ; AVX1-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX1-NEXT: jne .LBB15_29 -; AVX1-NEXT: .LBB15_30: # %else28 +; AVX1-NEXT: jne .LBB15_48 +; AVX1-NEXT: .LBB15_15: # %else28 ; AVX1-NEXT: testw %ax, %ax -; AVX1-NEXT: jns .LBB15_32 -; AVX1-NEXT: .LBB15_31: # %cond.store29 +; AVX1-NEXT: jns .LBB15_17 +; AVX1-NEXT: .LBB15_16: # %cond.store29 ; AVX1-NEXT: vpextrb $15, %xmm0, 15(%rdi) -; AVX1-NEXT: .LBB15_32: # %else30 +; AVX1-NEXT: .LBB15_17: # %else30 ; AVX1-NEXT: testl $65536, %eax # imm = 0x10000 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 -; AVX1-NEXT: jne .LBB15_33 -; AVX1-NEXT: # %bb.34: # %else32 +; AVX1-NEXT: jne .LBB15_49 +; AVX1-NEXT: # %bb.18: # %else32 ; AVX1-NEXT: testl $131072, %eax # imm = 0x20000 -; AVX1-NEXT: jne .LBB15_35 -; AVX1-NEXT: .LBB15_36: # %else34 +; AVX1-NEXT: jne .LBB15_50 +; AVX1-NEXT: .LBB15_19: # %else34 ; AVX1-NEXT: testl $262144, %eax # imm = 0x40000 -; AVX1-NEXT: jne .LBB15_37 -; AVX1-NEXT: .LBB15_38: # %else36 +; AVX1-NEXT: jne .LBB15_51 +; AVX1-NEXT: .LBB15_20: # %else36 ; AVX1-NEXT: testl $524288, %eax # imm = 0x80000 -; AVX1-NEXT: jne .LBB15_39 -; AVX1-NEXT: .LBB15_40: # %else38 +; AVX1-NEXT: jne .LBB15_52 +; AVX1-NEXT: .LBB15_21: # %else38 ; AVX1-NEXT: testl $1048576, %eax # imm = 0x100000 -; AVX1-NEXT: jne .LBB15_41 -; AVX1-NEXT: .LBB15_42: # %else40 +; AVX1-NEXT: jne .LBB15_53 +; AVX1-NEXT: .LBB15_22: # %else40 ; AVX1-NEXT: testl $2097152, %eax # imm = 0x200000 -; AVX1-NEXT: jne .LBB15_43 -; AVX1-NEXT: .LBB15_44: # %else42 +; AVX1-NEXT: jne .LBB15_54 +; AVX1-NEXT: .LBB15_23: # %else42 ; AVX1-NEXT: testl $4194304, %eax # imm = 0x400000 -; AVX1-NEXT: jne .LBB15_45 -; AVX1-NEXT: .LBB15_46: # %else44 +; AVX1-NEXT: jne .LBB15_55 +; AVX1-NEXT: .LBB15_24: # %else44 ; AVX1-NEXT: testl $8388608, %eax # imm = 0x800000 -; AVX1-NEXT: jne .LBB15_47 -; AVX1-NEXT: .LBB15_48: # %else46 +; AVX1-NEXT: jne .LBB15_56 +; AVX1-NEXT: .LBB15_25: # %else46 ; AVX1-NEXT: testl $16777216, %eax # imm = 0x1000000 -; AVX1-NEXT: jne .LBB15_49 -; AVX1-NEXT: .LBB15_50: # %else48 +; AVX1-NEXT: jne .LBB15_57 +; AVX1-NEXT: .LBB15_26: # %else48 ; AVX1-NEXT: testl $33554432, %eax # imm = 0x2000000 -; AVX1-NEXT: jne .LBB15_51 -; AVX1-NEXT: .LBB15_52: # %else50 +; AVX1-NEXT: jne .LBB15_58 +; AVX1-NEXT: .LBB15_27: # %else50 ; AVX1-NEXT: testl $67108864, %eax # imm = 0x4000000 -; AVX1-NEXT: jne .LBB15_53 -; AVX1-NEXT: .LBB15_54: # %else52 +; AVX1-NEXT: jne .LBB15_59 +; AVX1-NEXT: .LBB15_28: # %else52 ; AVX1-NEXT: testl $134217728, %eax # imm = 0x8000000 -; AVX1-NEXT: jne .LBB15_55 -; AVX1-NEXT: .LBB15_56: # %else54 +; AVX1-NEXT: jne .LBB15_60 +; AVX1-NEXT: .LBB15_29: # %else54 ; AVX1-NEXT: testl $268435456, %eax # imm = 0x10000000 -; AVX1-NEXT: jne .LBB15_57 -; AVX1-NEXT: .LBB15_58: # %else56 +; AVX1-NEXT: jne .LBB15_61 +; AVX1-NEXT: .LBB15_30: # %else56 ; AVX1-NEXT: testl $536870912, %eax # imm = 0x20000000 -; AVX1-NEXT: jne .LBB15_59 -; AVX1-NEXT: .LBB15_60: # %else58 +; AVX1-NEXT: jne .LBB15_62 +; AVX1-NEXT: .LBB15_31: # %else58 ; AVX1-NEXT: testl $1073741824, %eax # imm = 0x40000000 -; AVX1-NEXT: jne .LBB15_61 -; AVX1-NEXT: .LBB15_62: # %else60 -; AVX1-NEXT: testl $-2147483648, %eax # imm = 0x80000000 ; AVX1-NEXT: jne .LBB15_63 -; AVX1-NEXT: .LBB15_64: # %else62 +; AVX1-NEXT: .LBB15_32: # %else60 +; AVX1-NEXT: testl $-2147483648, %eax # imm = 0x80000000 +; AVX1-NEXT: jne .LBB15_64 +; AVX1-NEXT: .LBB15_33: # %else62 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB15_1: # %cond.store +; AVX1-NEXT: .LBB15_34: # %cond.store ; AVX1-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je .LBB15_4 -; AVX1-NEXT: .LBB15_3: # %cond.store1 +; AVX1-NEXT: je .LBB15_2 +; AVX1-NEXT: .LBB15_35: # %cond.store1 ; AVX1-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je .LBB15_6 -; AVX1-NEXT: .LBB15_5: # %cond.store3 +; AVX1-NEXT: je .LBB15_3 +; AVX1-NEXT: .LBB15_36: # %cond.store3 ; AVX1-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB15_8 -; AVX1-NEXT: .LBB15_7: # %cond.store5 +; AVX1-NEXT: je .LBB15_4 +; AVX1-NEXT: .LBB15_37: # %cond.store5 ; AVX1-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: je .LBB15_10 -; AVX1-NEXT: .LBB15_9: # %cond.store7 +; AVX1-NEXT: je .LBB15_5 +; AVX1-NEXT: .LBB15_38: # %cond.store7 ; AVX1-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je .LBB15_12 -; AVX1-NEXT: .LBB15_11: # %cond.store9 +; AVX1-NEXT: je .LBB15_6 +; AVX1-NEXT: .LBB15_39: # %cond.store9 ; AVX1-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: je .LBB15_14 -; AVX1-NEXT: .LBB15_13: # %cond.store11 +; AVX1-NEXT: je .LBB15_7 +; AVX1-NEXT: .LBB15_40: # %cond.store11 ; AVX1-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX1-NEXT: testb %al, %al -; AVX1-NEXT: jns .LBB15_16 -; AVX1-NEXT: .LBB15_15: # %cond.store13 +; AVX1-NEXT: jns .LBB15_8 +; AVX1-NEXT: .LBB15_41: # %cond.store13 ; AVX1-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX1-NEXT: testl $256, %eax # imm = 0x100 -; AVX1-NEXT: je .LBB15_18 -; AVX1-NEXT: .LBB15_17: # %cond.store15 +; AVX1-NEXT: je .LBB15_9 +; AVX1-NEXT: .LBB15_42: # %cond.store15 ; AVX1-NEXT: vpextrb $8, %xmm0, 8(%rdi) ; AVX1-NEXT: testl $512, %eax # imm = 0x200 -; AVX1-NEXT: je .LBB15_20 -; AVX1-NEXT: .LBB15_19: # %cond.store17 +; AVX1-NEXT: je .LBB15_10 +; AVX1-NEXT: .LBB15_43: # %cond.store17 ; AVX1-NEXT: vpextrb $9, %xmm0, 9(%rdi) ; AVX1-NEXT: testl $1024, %eax # imm = 0x400 -; AVX1-NEXT: je .LBB15_22 -; AVX1-NEXT: .LBB15_21: # %cond.store19 +; AVX1-NEXT: je .LBB15_11 +; AVX1-NEXT: .LBB15_44: # %cond.store19 ; AVX1-NEXT: vpextrb $10, %xmm0, 10(%rdi) ; AVX1-NEXT: testl $2048, %eax # imm = 0x800 -; AVX1-NEXT: je .LBB15_24 -; AVX1-NEXT: .LBB15_23: # %cond.store21 +; AVX1-NEXT: je .LBB15_12 +; AVX1-NEXT: .LBB15_45: # %cond.store21 ; AVX1-NEXT: vpextrb $11, %xmm0, 11(%rdi) ; AVX1-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX1-NEXT: je .LBB15_26 -; AVX1-NEXT: .LBB15_25: # %cond.store23 +; AVX1-NEXT: je .LBB15_13 +; AVX1-NEXT: .LBB15_46: # %cond.store23 ; AVX1-NEXT: vpextrb $12, %xmm0, 12(%rdi) ; AVX1-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX1-NEXT: je .LBB15_28 -; AVX1-NEXT: .LBB15_27: # %cond.store25 +; AVX1-NEXT: je .LBB15_14 +; AVX1-NEXT: .LBB15_47: # %cond.store25 ; AVX1-NEXT: vpextrb $13, %xmm0, 13(%rdi) ; AVX1-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX1-NEXT: je .LBB15_30 -; AVX1-NEXT: .LBB15_29: # %cond.store27 +; AVX1-NEXT: je .LBB15_15 +; AVX1-NEXT: .LBB15_48: # %cond.store27 ; AVX1-NEXT: vpextrb $14, %xmm0, 14(%rdi) ; AVX1-NEXT: testw %ax, %ax -; AVX1-NEXT: js .LBB15_31 -; AVX1-NEXT: jmp .LBB15_32 -; AVX1-NEXT: .LBB15_33: # %cond.store31 +; AVX1-NEXT: js .LBB15_16 +; AVX1-NEXT: jmp .LBB15_17 +; AVX1-NEXT: .LBB15_49: # %cond.store31 ; AVX1-NEXT: vpextrb $0, %xmm0, 16(%rdi) ; AVX1-NEXT: testl $131072, %eax # imm = 0x20000 -; AVX1-NEXT: je .LBB15_36 -; AVX1-NEXT: .LBB15_35: # %cond.store33 +; AVX1-NEXT: je .LBB15_19 +; AVX1-NEXT: .LBB15_50: # %cond.store33 ; AVX1-NEXT: vpextrb $1, %xmm0, 17(%rdi) ; AVX1-NEXT: testl $262144, %eax # imm = 0x40000 -; AVX1-NEXT: je .LBB15_38 -; AVX1-NEXT: .LBB15_37: # %cond.store35 +; AVX1-NEXT: je .LBB15_20 +; AVX1-NEXT: .LBB15_51: # %cond.store35 ; AVX1-NEXT: vpextrb $2, %xmm0, 18(%rdi) ; AVX1-NEXT: testl $524288, %eax # imm = 0x80000 -; AVX1-NEXT: je .LBB15_40 -; AVX1-NEXT: .LBB15_39: # %cond.store37 +; AVX1-NEXT: je .LBB15_21 +; AVX1-NEXT: .LBB15_52: # %cond.store37 ; AVX1-NEXT: vpextrb $3, %xmm0, 19(%rdi) ; AVX1-NEXT: testl $1048576, %eax # imm = 0x100000 -; AVX1-NEXT: je .LBB15_42 -; AVX1-NEXT: .LBB15_41: # %cond.store39 +; AVX1-NEXT: je .LBB15_22 +; AVX1-NEXT: .LBB15_53: # %cond.store39 ; AVX1-NEXT: vpextrb $4, %xmm0, 20(%rdi) ; AVX1-NEXT: testl $2097152, %eax # imm = 0x200000 -; AVX1-NEXT: je .LBB15_44 -; AVX1-NEXT: .LBB15_43: # %cond.store41 +; AVX1-NEXT: je .LBB15_23 +; AVX1-NEXT: .LBB15_54: # %cond.store41 ; AVX1-NEXT: vpextrb $5, %xmm0, 21(%rdi) ; AVX1-NEXT: testl $4194304, %eax # imm = 0x400000 -; AVX1-NEXT: je .LBB15_46 -; AVX1-NEXT: .LBB15_45: # %cond.store43 +; AVX1-NEXT: je .LBB15_24 +; AVX1-NEXT: .LBB15_55: # %cond.store43 ; AVX1-NEXT: vpextrb $6, %xmm0, 22(%rdi) ; AVX1-NEXT: testl $8388608, %eax # imm = 0x800000 -; AVX1-NEXT: je .LBB15_48 -; AVX1-NEXT: .LBB15_47: # %cond.store45 +; AVX1-NEXT: je .LBB15_25 +; AVX1-NEXT: .LBB15_56: # %cond.store45 ; AVX1-NEXT: vpextrb $7, %xmm0, 23(%rdi) ; AVX1-NEXT: testl $16777216, %eax # imm = 0x1000000 -; AVX1-NEXT: je .LBB15_50 -; AVX1-NEXT: .LBB15_49: # %cond.store47 +; AVX1-NEXT: je .LBB15_26 +; AVX1-NEXT: .LBB15_57: # %cond.store47 ; AVX1-NEXT: vpextrb $8, %xmm0, 24(%rdi) ; AVX1-NEXT: testl $33554432, %eax # imm = 0x2000000 -; AVX1-NEXT: je .LBB15_52 -; AVX1-NEXT: .LBB15_51: # %cond.store49 +; AVX1-NEXT: je .LBB15_27 +; AVX1-NEXT: .LBB15_58: # %cond.store49 ; AVX1-NEXT: vpextrb $9, %xmm0, 25(%rdi) ; AVX1-NEXT: testl $67108864, %eax # imm = 0x4000000 -; AVX1-NEXT: je .LBB15_54 -; AVX1-NEXT: .LBB15_53: # %cond.store51 +; AVX1-NEXT: je .LBB15_28 +; AVX1-NEXT: .LBB15_59: # %cond.store51 ; AVX1-NEXT: vpextrb $10, %xmm0, 26(%rdi) ; AVX1-NEXT: testl $134217728, %eax # imm = 0x8000000 -; AVX1-NEXT: je .LBB15_56 -; AVX1-NEXT: .LBB15_55: # %cond.store53 +; AVX1-NEXT: je .LBB15_29 +; AVX1-NEXT: .LBB15_60: # %cond.store53 ; AVX1-NEXT: vpextrb $11, %xmm0, 27(%rdi) ; AVX1-NEXT: testl $268435456, %eax # imm = 0x10000000 -; AVX1-NEXT: je .LBB15_58 -; AVX1-NEXT: .LBB15_57: # %cond.store55 +; AVX1-NEXT: je .LBB15_30 +; AVX1-NEXT: .LBB15_61: # %cond.store55 ; AVX1-NEXT: vpextrb $12, %xmm0, 28(%rdi) ; AVX1-NEXT: testl $536870912, %eax # imm = 0x20000000 -; AVX1-NEXT: je .LBB15_60 -; AVX1-NEXT: .LBB15_59: # %cond.store57 +; AVX1-NEXT: je .LBB15_31 +; AVX1-NEXT: .LBB15_62: # %cond.store57 ; AVX1-NEXT: vpextrb $13, %xmm0, 29(%rdi) ; AVX1-NEXT: testl $1073741824, %eax # imm = 0x40000000 -; AVX1-NEXT: je .LBB15_62 -; AVX1-NEXT: .LBB15_61: # %cond.store59 +; AVX1-NEXT: je .LBB15_32 +; AVX1-NEXT: .LBB15_63: # %cond.store59 ; AVX1-NEXT: vpextrb $14, %xmm0, 30(%rdi) ; AVX1-NEXT: testl $-2147483648, %eax # imm = 0x80000000 -; AVX1-NEXT: je .LBB15_64 -; AVX1-NEXT: .LBB15_63: # %cond.store61 +; AVX1-NEXT: je .LBB15_33 +; AVX1-NEXT: .LBB15_64: # %cond.store61 ; AVX1-NEXT: vpextrb $15, %xmm0, 31(%rdi) ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq @@ -6467,228 +6467,228 @@ define void @truncstore_v32i16_v32i8(<32 x i16> %x, ptr %p, <32 x i8> %mask) { ; AVX2-NEXT: vpmovmskb %ymm1, %eax ; AVX2-NEXT: notl %eax ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne .LBB15_1 -; AVX2-NEXT: # %bb.2: # %else +; AVX2-NEXT: jne .LBB15_34 +; AVX2-NEXT: # %bb.1: # %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne .LBB15_3 -; AVX2-NEXT: .LBB15_4: # %else2 +; AVX2-NEXT: jne .LBB15_35 +; AVX2-NEXT: .LBB15_2: # %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne .LBB15_5 -; AVX2-NEXT: .LBB15_6: # %else4 +; AVX2-NEXT: jne .LBB15_36 +; AVX2-NEXT: .LBB15_3: # %else4 ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: jne .LBB15_7 -; AVX2-NEXT: .LBB15_8: # %else6 +; AVX2-NEXT: jne .LBB15_37 +; AVX2-NEXT: .LBB15_4: # %else6 ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: jne .LBB15_9 -; AVX2-NEXT: .LBB15_10: # %else8 +; AVX2-NEXT: jne .LBB15_38 +; AVX2-NEXT: .LBB15_5: # %else8 ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: jne .LBB15_11 -; AVX2-NEXT: .LBB15_12: # %else10 +; AVX2-NEXT: jne .LBB15_39 +; AVX2-NEXT: .LBB15_6: # %else10 ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: jne .LBB15_13 -; AVX2-NEXT: .LBB15_14: # %else12 +; AVX2-NEXT: jne .LBB15_40 +; AVX2-NEXT: .LBB15_7: # %else12 ; AVX2-NEXT: testb %al, %al -; AVX2-NEXT: js .LBB15_15 -; AVX2-NEXT: .LBB15_16: # %else14 +; AVX2-NEXT: js .LBB15_41 +; AVX2-NEXT: .LBB15_8: # %else14 ; AVX2-NEXT: testl $256, %eax # imm = 0x100 -; AVX2-NEXT: jne .LBB15_17 -; AVX2-NEXT: .LBB15_18: # %else16 +; AVX2-NEXT: jne .LBB15_42 +; AVX2-NEXT: .LBB15_9: # %else16 ; AVX2-NEXT: testl $512, %eax # imm = 0x200 -; AVX2-NEXT: jne .LBB15_19 -; AVX2-NEXT: .LBB15_20: # %else18 +; AVX2-NEXT: jne .LBB15_43 +; AVX2-NEXT: .LBB15_10: # %else18 ; AVX2-NEXT: testl $1024, %eax # imm = 0x400 -; AVX2-NEXT: jne .LBB15_21 -; AVX2-NEXT: .LBB15_22: # %else20 +; AVX2-NEXT: jne .LBB15_44 +; AVX2-NEXT: .LBB15_11: # %else20 ; AVX2-NEXT: testl $2048, %eax # imm = 0x800 -; AVX2-NEXT: jne .LBB15_23 -; AVX2-NEXT: .LBB15_24: # %else22 +; AVX2-NEXT: jne .LBB15_45 +; AVX2-NEXT: .LBB15_12: # %else22 ; AVX2-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX2-NEXT: jne .LBB15_25 -; AVX2-NEXT: .LBB15_26: # %else24 +; AVX2-NEXT: jne .LBB15_46 +; AVX2-NEXT: .LBB15_13: # %else24 ; AVX2-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX2-NEXT: jne .LBB15_27 -; AVX2-NEXT: .LBB15_28: # %else26 +; AVX2-NEXT: jne .LBB15_47 +; AVX2-NEXT: .LBB15_14: # %else26 ; AVX2-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX2-NEXT: jne .LBB15_29 -; AVX2-NEXT: .LBB15_30: # %else28 +; AVX2-NEXT: jne .LBB15_48 +; AVX2-NEXT: .LBB15_15: # %else28 ; AVX2-NEXT: testw %ax, %ax -; AVX2-NEXT: jns .LBB15_32 -; AVX2-NEXT: .LBB15_31: # %cond.store29 +; AVX2-NEXT: jns .LBB15_17 +; AVX2-NEXT: .LBB15_16: # %cond.store29 ; AVX2-NEXT: vpextrb $15, %xmm0, 15(%rdi) -; AVX2-NEXT: .LBB15_32: # %else30 +; AVX2-NEXT: .LBB15_17: # %else30 ; AVX2-NEXT: testl $65536, %eax # imm = 0x10000 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0 -; AVX2-NEXT: jne .LBB15_33 -; AVX2-NEXT: # %bb.34: # %else32 +; AVX2-NEXT: jne .LBB15_49 +; AVX2-NEXT: # %bb.18: # %else32 ; AVX2-NEXT: testl $131072, %eax # imm = 0x20000 -; AVX2-NEXT: jne .LBB15_35 -; AVX2-NEXT: .LBB15_36: # %else34 +; AVX2-NEXT: jne .LBB15_50 +; AVX2-NEXT: .LBB15_19: # %else34 ; AVX2-NEXT: testl $262144, %eax # imm = 0x40000 -; AVX2-NEXT: jne .LBB15_37 -; AVX2-NEXT: .LBB15_38: # %else36 +; AVX2-NEXT: jne .LBB15_51 +; AVX2-NEXT: .LBB15_20: # %else36 ; AVX2-NEXT: testl $524288, %eax # imm = 0x80000 -; AVX2-NEXT: jne .LBB15_39 -; AVX2-NEXT: .LBB15_40: # %else38 +; AVX2-NEXT: jne .LBB15_52 +; AVX2-NEXT: .LBB15_21: # %else38 ; AVX2-NEXT: testl $1048576, %eax # imm = 0x100000 -; AVX2-NEXT: jne .LBB15_41 -; AVX2-NEXT: .LBB15_42: # %else40 +; AVX2-NEXT: jne .LBB15_53 +; AVX2-NEXT: .LBB15_22: # %else40 ; AVX2-NEXT: testl $2097152, %eax # imm = 0x200000 -; AVX2-NEXT: jne .LBB15_43 -; AVX2-NEXT: .LBB15_44: # %else42 +; AVX2-NEXT: jne .LBB15_54 +; AVX2-NEXT: .LBB15_23: # %else42 ; AVX2-NEXT: testl $4194304, %eax # imm = 0x400000 -; AVX2-NEXT: jne .LBB15_45 -; AVX2-NEXT: .LBB15_46: # %else44 +; AVX2-NEXT: jne .LBB15_55 +; AVX2-NEXT: .LBB15_24: # %else44 ; AVX2-NEXT: testl $8388608, %eax # imm = 0x800000 -; AVX2-NEXT: jne .LBB15_47 -; AVX2-NEXT: .LBB15_48: # %else46 +; AVX2-NEXT: jne .LBB15_56 +; AVX2-NEXT: .LBB15_25: # %else46 ; AVX2-NEXT: testl $16777216, %eax # imm = 0x1000000 -; AVX2-NEXT: jne .LBB15_49 -; AVX2-NEXT: .LBB15_50: # %else48 +; AVX2-NEXT: jne .LBB15_57 +; AVX2-NEXT: .LBB15_26: # %else48 ; AVX2-NEXT: testl $33554432, %eax # imm = 0x2000000 -; AVX2-NEXT: jne .LBB15_51 -; AVX2-NEXT: .LBB15_52: # %else50 +; AVX2-NEXT: jne .LBB15_58 +; AVX2-NEXT: .LBB15_27: # %else50 ; AVX2-NEXT: testl $67108864, %eax # imm = 0x4000000 -; AVX2-NEXT: jne .LBB15_53 -; AVX2-NEXT: .LBB15_54: # %else52 +; AVX2-NEXT: jne .LBB15_59 +; AVX2-NEXT: .LBB15_28: # %else52 ; AVX2-NEXT: testl $134217728, %eax # imm = 0x8000000 -; AVX2-NEXT: jne .LBB15_55 -; AVX2-NEXT: .LBB15_56: # %else54 +; AVX2-NEXT: jne .LBB15_60 +; AVX2-NEXT: .LBB15_29: # %else54 ; AVX2-NEXT: testl $268435456, %eax # imm = 0x10000000 -; AVX2-NEXT: jne .LBB15_57 -; AVX2-NEXT: .LBB15_58: # %else56 +; AVX2-NEXT: jne .LBB15_61 +; AVX2-NEXT: .LBB15_30: # %else56 ; AVX2-NEXT: testl $536870912, %eax # imm = 0x20000000 -; AVX2-NEXT: jne .LBB15_59 -; AVX2-NEXT: .LBB15_60: # %else58 +; AVX2-NEXT: jne .LBB15_62 +; AVX2-NEXT: .LBB15_31: # %else58 ; AVX2-NEXT: testl $1073741824, %eax # imm = 0x40000000 -; AVX2-NEXT: jne .LBB15_61 -; AVX2-NEXT: .LBB15_62: # %else60 -; AVX2-NEXT: testl $-2147483648, %eax # imm = 0x80000000 ; AVX2-NEXT: jne .LBB15_63 -; AVX2-NEXT: .LBB15_64: # %else62 +; AVX2-NEXT: .LBB15_32: # %else60 +; AVX2-NEXT: testl $-2147483648, %eax # imm = 0x80000000 +; AVX2-NEXT: jne .LBB15_64 +; AVX2-NEXT: .LBB15_33: # %else62 ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; AVX2-NEXT: .LBB15_1: # %cond.store +; AVX2-NEXT: .LBB15_34: # %cond.store ; AVX2-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je .LBB15_4 -; AVX2-NEXT: .LBB15_3: # %cond.store1 +; AVX2-NEXT: je .LBB15_2 +; AVX2-NEXT: .LBB15_35: # %cond.store1 ; AVX2-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je .LBB15_6 -; AVX2-NEXT: .LBB15_5: # %cond.store3 +; AVX2-NEXT: je .LBB15_3 +; AVX2-NEXT: .LBB15_36: # %cond.store3 ; AVX2-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je .LBB15_8 -; AVX2-NEXT: .LBB15_7: # %cond.store5 +; AVX2-NEXT: je .LBB15_4 +; AVX2-NEXT: .LBB15_37: # %cond.store5 ; AVX2-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: je .LBB15_10 -; AVX2-NEXT: .LBB15_9: # %cond.store7 +; AVX2-NEXT: je .LBB15_5 +; AVX2-NEXT: .LBB15_38: # %cond.store7 ; AVX2-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: je .LBB15_12 -; AVX2-NEXT: .LBB15_11: # %cond.store9 +; AVX2-NEXT: je .LBB15_6 +; AVX2-NEXT: .LBB15_39: # %cond.store9 ; AVX2-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: je .LBB15_14 -; AVX2-NEXT: .LBB15_13: # %cond.store11 +; AVX2-NEXT: je .LBB15_7 +; AVX2-NEXT: .LBB15_40: # %cond.store11 ; AVX2-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX2-NEXT: testb %al, %al -; AVX2-NEXT: jns .LBB15_16 -; AVX2-NEXT: .LBB15_15: # %cond.store13 +; AVX2-NEXT: jns .LBB15_8 +; AVX2-NEXT: .LBB15_41: # %cond.store13 ; AVX2-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX2-NEXT: testl $256, %eax # imm = 0x100 -; AVX2-NEXT: je .LBB15_18 -; AVX2-NEXT: .LBB15_17: # %cond.store15 +; AVX2-NEXT: je .LBB15_9 +; AVX2-NEXT: .LBB15_42: # %cond.store15 ; AVX2-NEXT: vpextrb $8, %xmm0, 8(%rdi) ; AVX2-NEXT: testl $512, %eax # imm = 0x200 -; AVX2-NEXT: je .LBB15_20 -; AVX2-NEXT: .LBB15_19: # %cond.store17 +; AVX2-NEXT: je .LBB15_10 +; AVX2-NEXT: .LBB15_43: # %cond.store17 ; AVX2-NEXT: vpextrb $9, %xmm0, 9(%rdi) ; AVX2-NEXT: testl $1024, %eax # imm = 0x400 -; AVX2-NEXT: je .LBB15_22 -; AVX2-NEXT: .LBB15_21: # %cond.store19 +; AVX2-NEXT: je .LBB15_11 +; AVX2-NEXT: .LBB15_44: # %cond.store19 ; AVX2-NEXT: vpextrb $10, %xmm0, 10(%rdi) ; AVX2-NEXT: testl $2048, %eax # imm = 0x800 -; AVX2-NEXT: je .LBB15_24 -; AVX2-NEXT: .LBB15_23: # %cond.store21 +; AVX2-NEXT: je .LBB15_12 +; AVX2-NEXT: .LBB15_45: # %cond.store21 ; AVX2-NEXT: vpextrb $11, %xmm0, 11(%rdi) ; AVX2-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX2-NEXT: je .LBB15_26 -; AVX2-NEXT: .LBB15_25: # %cond.store23 +; AVX2-NEXT: je .LBB15_13 +; AVX2-NEXT: .LBB15_46: # %cond.store23 ; AVX2-NEXT: vpextrb $12, %xmm0, 12(%rdi) ; AVX2-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX2-NEXT: je .LBB15_28 -; AVX2-NEXT: .LBB15_27: # %cond.store25 +; AVX2-NEXT: je .LBB15_14 +; AVX2-NEXT: .LBB15_47: # %cond.store25 ; AVX2-NEXT: vpextrb $13, %xmm0, 13(%rdi) ; AVX2-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX2-NEXT: je .LBB15_30 -; AVX2-NEXT: .LBB15_29: # %cond.store27 +; AVX2-NEXT: je .LBB15_15 +; AVX2-NEXT: .LBB15_48: # %cond.store27 ; AVX2-NEXT: vpextrb $14, %xmm0, 14(%rdi) ; AVX2-NEXT: testw %ax, %ax -; AVX2-NEXT: js .LBB15_31 -; AVX2-NEXT: jmp .LBB15_32 -; AVX2-NEXT: .LBB15_33: # %cond.store31 +; AVX2-NEXT: js .LBB15_16 +; AVX2-NEXT: jmp .LBB15_17 +; AVX2-NEXT: .LBB15_49: # %cond.store31 ; AVX2-NEXT: vpextrb $0, %xmm0, 16(%rdi) ; AVX2-NEXT: testl $131072, %eax # imm = 0x20000 -; AVX2-NEXT: je .LBB15_36 -; AVX2-NEXT: .LBB15_35: # %cond.store33 +; AVX2-NEXT: je .LBB15_19 +; AVX2-NEXT: .LBB15_50: # %cond.store33 ; AVX2-NEXT: vpextrb $1, %xmm0, 17(%rdi) ; AVX2-NEXT: testl $262144, %eax # imm = 0x40000 -; AVX2-NEXT: je .LBB15_38 -; AVX2-NEXT: .LBB15_37: # %cond.store35 +; AVX2-NEXT: je .LBB15_20 +; AVX2-NEXT: .LBB15_51: # %cond.store35 ; AVX2-NEXT: vpextrb $2, %xmm0, 18(%rdi) ; AVX2-NEXT: testl $524288, %eax # imm = 0x80000 -; AVX2-NEXT: je .LBB15_40 -; AVX2-NEXT: .LBB15_39: # %cond.store37 +; AVX2-NEXT: je .LBB15_21 +; AVX2-NEXT: .LBB15_52: # %cond.store37 ; AVX2-NEXT: vpextrb $3, %xmm0, 19(%rdi) ; AVX2-NEXT: testl $1048576, %eax # imm = 0x100000 -; AVX2-NEXT: je .LBB15_42 -; AVX2-NEXT: .LBB15_41: # %cond.store39 +; AVX2-NEXT: je .LBB15_22 +; AVX2-NEXT: .LBB15_53: # %cond.store39 ; AVX2-NEXT: vpextrb $4, %xmm0, 20(%rdi) ; AVX2-NEXT: testl $2097152, %eax # imm = 0x200000 -; AVX2-NEXT: je .LBB15_44 -; AVX2-NEXT: .LBB15_43: # %cond.store41 +; AVX2-NEXT: je .LBB15_23 +; AVX2-NEXT: .LBB15_54: # %cond.store41 ; AVX2-NEXT: vpextrb $5, %xmm0, 21(%rdi) ; AVX2-NEXT: testl $4194304, %eax # imm = 0x400000 -; AVX2-NEXT: je .LBB15_46 -; AVX2-NEXT: .LBB15_45: # %cond.store43 +; AVX2-NEXT: je .LBB15_24 +; AVX2-NEXT: .LBB15_55: # %cond.store43 ; AVX2-NEXT: vpextrb $6, %xmm0, 22(%rdi) ; AVX2-NEXT: testl $8388608, %eax # imm = 0x800000 -; AVX2-NEXT: je .LBB15_48 -; AVX2-NEXT: .LBB15_47: # %cond.store45 +; AVX2-NEXT: je .LBB15_25 +; AVX2-NEXT: .LBB15_56: # %cond.store45 ; AVX2-NEXT: vpextrb $7, %xmm0, 23(%rdi) ; AVX2-NEXT: testl $16777216, %eax # imm = 0x1000000 -; AVX2-NEXT: je .LBB15_50 -; AVX2-NEXT: .LBB15_49: # %cond.store47 +; AVX2-NEXT: je .LBB15_26 +; AVX2-NEXT: .LBB15_57: # %cond.store47 ; AVX2-NEXT: vpextrb $8, %xmm0, 24(%rdi) ; AVX2-NEXT: testl $33554432, %eax # imm = 0x2000000 -; AVX2-NEXT: je .LBB15_52 -; AVX2-NEXT: .LBB15_51: # %cond.store49 +; AVX2-NEXT: je .LBB15_27 +; AVX2-NEXT: .LBB15_58: # %cond.store49 ; AVX2-NEXT: vpextrb $9, %xmm0, 25(%rdi) ; AVX2-NEXT: testl $67108864, %eax # imm = 0x4000000 -; AVX2-NEXT: je .LBB15_54 -; AVX2-NEXT: .LBB15_53: # %cond.store51 +; AVX2-NEXT: je .LBB15_28 +; AVX2-NEXT: .LBB15_59: # %cond.store51 ; AVX2-NEXT: vpextrb $10, %xmm0, 26(%rdi) ; AVX2-NEXT: testl $134217728, %eax # imm = 0x8000000 -; AVX2-NEXT: je .LBB15_56 -; AVX2-NEXT: .LBB15_55: # %cond.store53 +; AVX2-NEXT: je .LBB15_29 +; AVX2-NEXT: .LBB15_60: # %cond.store53 ; AVX2-NEXT: vpextrb $11, %xmm0, 27(%rdi) ; AVX2-NEXT: testl $268435456, %eax # imm = 0x10000000 -; AVX2-NEXT: je .LBB15_58 -; AVX2-NEXT: .LBB15_57: # %cond.store55 +; AVX2-NEXT: je .LBB15_30 +; AVX2-NEXT: .LBB15_61: # %cond.store55 ; AVX2-NEXT: vpextrb $12, %xmm0, 28(%rdi) ; AVX2-NEXT: testl $536870912, %eax # imm = 0x20000000 -; AVX2-NEXT: je .LBB15_60 -; AVX2-NEXT: .LBB15_59: # %cond.store57 +; AVX2-NEXT: je .LBB15_31 +; AVX2-NEXT: .LBB15_62: # %cond.store57 ; AVX2-NEXT: vpextrb $13, %xmm0, 29(%rdi) ; AVX2-NEXT: testl $1073741824, %eax # imm = 0x40000000 -; AVX2-NEXT: je .LBB15_62 -; AVX2-NEXT: .LBB15_61: # %cond.store59 +; AVX2-NEXT: je .LBB15_32 +; AVX2-NEXT: .LBB15_63: # %cond.store59 ; AVX2-NEXT: vpextrb $14, %xmm0, 30(%rdi) ; AVX2-NEXT: testl $-2147483648, %eax # imm = 0x80000000 -; AVX2-NEXT: je .LBB15_64 -; AVX2-NEXT: .LBB15_63: # %cond.store61 +; AVX2-NEXT: je .LBB15_33 +; AVX2-NEXT: .LBB15_64: # %cond.store61 ; AVX2-NEXT: vpextrb $15, %xmm0, 31(%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq @@ -6706,228 +6706,228 @@ define void @truncstore_v32i16_v32i8(<32 x i16> %x, ptr %p, <32 x i8> %mask) { ; AVX512F-NEXT: vpmovmskb %ymm1, %eax ; AVX512F-NEXT: notl %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB15_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB15_34 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB15_3 -; AVX512F-NEXT: .LBB15_4: # %else2 +; AVX512F-NEXT: jne .LBB15_35 +; AVX512F-NEXT: .LBB15_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB15_5 -; AVX512F-NEXT: .LBB15_6: # %else4 +; AVX512F-NEXT: jne .LBB15_36 +; AVX512F-NEXT: .LBB15_3: # %else4 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne .LBB15_7 -; AVX512F-NEXT: .LBB15_8: # %else6 +; AVX512F-NEXT: jne .LBB15_37 +; AVX512F-NEXT: .LBB15_4: # %else6 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne .LBB15_9 -; AVX512F-NEXT: .LBB15_10: # %else8 +; AVX512F-NEXT: jne .LBB15_38 +; AVX512F-NEXT: .LBB15_5: # %else8 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne .LBB15_11 -; AVX512F-NEXT: .LBB15_12: # %else10 +; AVX512F-NEXT: jne .LBB15_39 +; AVX512F-NEXT: .LBB15_6: # %else10 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne .LBB15_13 -; AVX512F-NEXT: .LBB15_14: # %else12 +; AVX512F-NEXT: jne .LBB15_40 +; AVX512F-NEXT: .LBB15_7: # %else12 ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: js .LBB15_15 -; AVX512F-NEXT: .LBB15_16: # %else14 +; AVX512F-NEXT: js .LBB15_41 +; AVX512F-NEXT: .LBB15_8: # %else14 ; AVX512F-NEXT: testl $256, %eax # imm = 0x100 -; AVX512F-NEXT: jne .LBB15_17 -; AVX512F-NEXT: .LBB15_18: # %else16 +; AVX512F-NEXT: jne .LBB15_42 +; AVX512F-NEXT: .LBB15_9: # %else16 ; AVX512F-NEXT: testl $512, %eax # imm = 0x200 -; AVX512F-NEXT: jne .LBB15_19 -; AVX512F-NEXT: .LBB15_20: # %else18 +; AVX512F-NEXT: jne .LBB15_43 +; AVX512F-NEXT: .LBB15_10: # %else18 ; AVX512F-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512F-NEXT: jne .LBB15_21 -; AVX512F-NEXT: .LBB15_22: # %else20 +; AVX512F-NEXT: jne .LBB15_44 +; AVX512F-NEXT: .LBB15_11: # %else20 ; AVX512F-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512F-NEXT: jne .LBB15_23 -; AVX512F-NEXT: .LBB15_24: # %else22 +; AVX512F-NEXT: jne .LBB15_45 +; AVX512F-NEXT: .LBB15_12: # %else22 ; AVX512F-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512F-NEXT: jne .LBB15_25 -; AVX512F-NEXT: .LBB15_26: # %else24 +; AVX512F-NEXT: jne .LBB15_46 +; AVX512F-NEXT: .LBB15_13: # %else24 ; AVX512F-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512F-NEXT: jne .LBB15_27 -; AVX512F-NEXT: .LBB15_28: # %else26 +; AVX512F-NEXT: jne .LBB15_47 +; AVX512F-NEXT: .LBB15_14: # %else26 ; AVX512F-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512F-NEXT: jne .LBB15_29 -; AVX512F-NEXT: .LBB15_30: # %else28 +; AVX512F-NEXT: jne .LBB15_48 +; AVX512F-NEXT: .LBB15_15: # %else28 ; AVX512F-NEXT: testw %ax, %ax -; AVX512F-NEXT: jns .LBB15_32 -; AVX512F-NEXT: .LBB15_31: # %cond.store29 +; AVX512F-NEXT: jns .LBB15_17 +; AVX512F-NEXT: .LBB15_16: # %cond.store29 ; AVX512F-NEXT: vpextrb $15, %xmm0, 15(%rdi) -; AVX512F-NEXT: .LBB15_32: # %else30 +; AVX512F-NEXT: .LBB15_17: # %else30 ; AVX512F-NEXT: testl $65536, %eax # imm = 0x10000 ; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm0 -; AVX512F-NEXT: jne .LBB15_33 -; AVX512F-NEXT: # %bb.34: # %else32 +; AVX512F-NEXT: jne .LBB15_49 +; AVX512F-NEXT: # %bb.18: # %else32 ; AVX512F-NEXT: testl $131072, %eax # imm = 0x20000 -; AVX512F-NEXT: jne .LBB15_35 -; AVX512F-NEXT: .LBB15_36: # %else34 +; AVX512F-NEXT: jne .LBB15_50 +; AVX512F-NEXT: .LBB15_19: # %else34 ; AVX512F-NEXT: testl $262144, %eax # imm = 0x40000 -; AVX512F-NEXT: jne .LBB15_37 -; AVX512F-NEXT: .LBB15_38: # %else36 +; AVX512F-NEXT: jne .LBB15_51 +; AVX512F-NEXT: .LBB15_20: # %else36 ; AVX512F-NEXT: testl $524288, %eax # imm = 0x80000 -; AVX512F-NEXT: jne .LBB15_39 -; AVX512F-NEXT: .LBB15_40: # %else38 +; AVX512F-NEXT: jne .LBB15_52 +; AVX512F-NEXT: .LBB15_21: # %else38 ; AVX512F-NEXT: testl $1048576, %eax # imm = 0x100000 -; AVX512F-NEXT: jne .LBB15_41 -; AVX512F-NEXT: .LBB15_42: # %else40 +; AVX512F-NEXT: jne .LBB15_53 +; AVX512F-NEXT: .LBB15_22: # %else40 ; AVX512F-NEXT: testl $2097152, %eax # imm = 0x200000 -; AVX512F-NEXT: jne .LBB15_43 -; AVX512F-NEXT: .LBB15_44: # %else42 +; AVX512F-NEXT: jne .LBB15_54 +; AVX512F-NEXT: .LBB15_23: # %else42 ; AVX512F-NEXT: testl $4194304, %eax # imm = 0x400000 -; AVX512F-NEXT: jne .LBB15_45 -; AVX512F-NEXT: .LBB15_46: # %else44 +; AVX512F-NEXT: jne .LBB15_55 +; AVX512F-NEXT: .LBB15_24: # %else44 ; AVX512F-NEXT: testl $8388608, %eax # imm = 0x800000 -; AVX512F-NEXT: jne .LBB15_47 -; AVX512F-NEXT: .LBB15_48: # %else46 +; AVX512F-NEXT: jne .LBB15_56 +; AVX512F-NEXT: .LBB15_25: # %else46 ; AVX512F-NEXT: testl $16777216, %eax # imm = 0x1000000 -; AVX512F-NEXT: jne .LBB15_49 -; AVX512F-NEXT: .LBB15_50: # %else48 +; AVX512F-NEXT: jne .LBB15_57 +; AVX512F-NEXT: .LBB15_26: # %else48 ; AVX512F-NEXT: testl $33554432, %eax # imm = 0x2000000 -; AVX512F-NEXT: jne .LBB15_51 -; AVX512F-NEXT: .LBB15_52: # %else50 +; AVX512F-NEXT: jne .LBB15_58 +; AVX512F-NEXT: .LBB15_27: # %else50 ; AVX512F-NEXT: testl $67108864, %eax # imm = 0x4000000 -; AVX512F-NEXT: jne .LBB15_53 -; AVX512F-NEXT: .LBB15_54: # %else52 +; AVX512F-NEXT: jne .LBB15_59 +; AVX512F-NEXT: .LBB15_28: # %else52 ; AVX512F-NEXT: testl $134217728, %eax # imm = 0x8000000 -; AVX512F-NEXT: jne .LBB15_55 -; AVX512F-NEXT: .LBB15_56: # %else54 +; AVX512F-NEXT: jne .LBB15_60 +; AVX512F-NEXT: .LBB15_29: # %else54 ; AVX512F-NEXT: testl $268435456, %eax # imm = 0x10000000 -; AVX512F-NEXT: jne .LBB15_57 -; AVX512F-NEXT: .LBB15_58: # %else56 +; AVX512F-NEXT: jne .LBB15_61 +; AVX512F-NEXT: .LBB15_30: # %else56 ; AVX512F-NEXT: testl $536870912, %eax # imm = 0x20000000 -; AVX512F-NEXT: jne .LBB15_59 -; AVX512F-NEXT: .LBB15_60: # %else58 +; AVX512F-NEXT: jne .LBB15_62 +; AVX512F-NEXT: .LBB15_31: # %else58 ; AVX512F-NEXT: testl $1073741824, %eax # imm = 0x40000000 -; AVX512F-NEXT: jne .LBB15_61 -; AVX512F-NEXT: .LBB15_62: # %else60 -; AVX512F-NEXT: testl $-2147483648, %eax # imm = 0x80000000 ; AVX512F-NEXT: jne .LBB15_63 -; AVX512F-NEXT: .LBB15_64: # %else62 +; AVX512F-NEXT: .LBB15_32: # %else60 +; AVX512F-NEXT: testl $-2147483648, %eax # imm = 0x80000000 +; AVX512F-NEXT: jne .LBB15_64 +; AVX512F-NEXT: .LBB15_33: # %else62 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB15_1: # %cond.store +; AVX512F-NEXT: .LBB15_34: # %cond.store ; AVX512F-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB15_4 -; AVX512F-NEXT: .LBB15_3: # %cond.store1 +; AVX512F-NEXT: je .LBB15_2 +; AVX512F-NEXT: .LBB15_35: # %cond.store1 ; AVX512F-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB15_6 -; AVX512F-NEXT: .LBB15_5: # %cond.store3 +; AVX512F-NEXT: je .LBB15_3 +; AVX512F-NEXT: .LBB15_36: # %cond.store3 ; AVX512F-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB15_8 -; AVX512F-NEXT: .LBB15_7: # %cond.store5 +; AVX512F-NEXT: je .LBB15_4 +; AVX512F-NEXT: .LBB15_37: # %cond.store5 ; AVX512F-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je .LBB15_10 -; AVX512F-NEXT: .LBB15_9: # %cond.store7 +; AVX512F-NEXT: je .LBB15_5 +; AVX512F-NEXT: .LBB15_38: # %cond.store7 ; AVX512F-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je .LBB15_12 -; AVX512F-NEXT: .LBB15_11: # %cond.store9 +; AVX512F-NEXT: je .LBB15_6 +; AVX512F-NEXT: .LBB15_39: # %cond.store9 ; AVX512F-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je .LBB15_14 -; AVX512F-NEXT: .LBB15_13: # %cond.store11 +; AVX512F-NEXT: je .LBB15_7 +; AVX512F-NEXT: .LBB15_40: # %cond.store11 ; AVX512F-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: jns .LBB15_16 -; AVX512F-NEXT: .LBB15_15: # %cond.store13 +; AVX512F-NEXT: jns .LBB15_8 +; AVX512F-NEXT: .LBB15_41: # %cond.store13 ; AVX512F-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX512F-NEXT: testl $256, %eax # imm = 0x100 -; AVX512F-NEXT: je .LBB15_18 -; AVX512F-NEXT: .LBB15_17: # %cond.store15 +; AVX512F-NEXT: je .LBB15_9 +; AVX512F-NEXT: .LBB15_42: # %cond.store15 ; AVX512F-NEXT: vpextrb $8, %xmm0, 8(%rdi) ; AVX512F-NEXT: testl $512, %eax # imm = 0x200 -; AVX512F-NEXT: je .LBB15_20 -; AVX512F-NEXT: .LBB15_19: # %cond.store17 +; AVX512F-NEXT: je .LBB15_10 +; AVX512F-NEXT: .LBB15_43: # %cond.store17 ; AVX512F-NEXT: vpextrb $9, %xmm0, 9(%rdi) ; AVX512F-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512F-NEXT: je .LBB15_22 -; AVX512F-NEXT: .LBB15_21: # %cond.store19 +; AVX512F-NEXT: je .LBB15_11 +; AVX512F-NEXT: .LBB15_44: # %cond.store19 ; AVX512F-NEXT: vpextrb $10, %xmm0, 10(%rdi) ; AVX512F-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512F-NEXT: je .LBB15_24 -; AVX512F-NEXT: .LBB15_23: # %cond.store21 +; AVX512F-NEXT: je .LBB15_12 +; AVX512F-NEXT: .LBB15_45: # %cond.store21 ; AVX512F-NEXT: vpextrb $11, %xmm0, 11(%rdi) ; AVX512F-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512F-NEXT: je .LBB15_26 -; AVX512F-NEXT: .LBB15_25: # %cond.store23 +; AVX512F-NEXT: je .LBB15_13 +; AVX512F-NEXT: .LBB15_46: # %cond.store23 ; AVX512F-NEXT: vpextrb $12, %xmm0, 12(%rdi) ; AVX512F-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512F-NEXT: je .LBB15_28 -; AVX512F-NEXT: .LBB15_27: # %cond.store25 +; AVX512F-NEXT: je .LBB15_14 +; AVX512F-NEXT: .LBB15_47: # %cond.store25 ; AVX512F-NEXT: vpextrb $13, %xmm0, 13(%rdi) ; AVX512F-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512F-NEXT: je .LBB15_30 -; AVX512F-NEXT: .LBB15_29: # %cond.store27 +; AVX512F-NEXT: je .LBB15_15 +; AVX512F-NEXT: .LBB15_48: # %cond.store27 ; AVX512F-NEXT: vpextrb $14, %xmm0, 14(%rdi) ; AVX512F-NEXT: testw %ax, %ax -; AVX512F-NEXT: js .LBB15_31 -; AVX512F-NEXT: jmp .LBB15_32 -; AVX512F-NEXT: .LBB15_33: # %cond.store31 +; AVX512F-NEXT: js .LBB15_16 +; AVX512F-NEXT: jmp .LBB15_17 +; AVX512F-NEXT: .LBB15_49: # %cond.store31 ; AVX512F-NEXT: vpextrb $0, %xmm0, 16(%rdi) ; AVX512F-NEXT: testl $131072, %eax # imm = 0x20000 -; AVX512F-NEXT: je .LBB15_36 -; AVX512F-NEXT: .LBB15_35: # %cond.store33 +; AVX512F-NEXT: je .LBB15_19 +; AVX512F-NEXT: .LBB15_50: # %cond.store33 ; AVX512F-NEXT: vpextrb $1, %xmm0, 17(%rdi) ; AVX512F-NEXT: testl $262144, %eax # imm = 0x40000 -; AVX512F-NEXT: je .LBB15_38 -; AVX512F-NEXT: .LBB15_37: # %cond.store35 +; AVX512F-NEXT: je .LBB15_20 +; AVX512F-NEXT: .LBB15_51: # %cond.store35 ; AVX512F-NEXT: vpextrb $2, %xmm0, 18(%rdi) ; AVX512F-NEXT: testl $524288, %eax # imm = 0x80000 -; AVX512F-NEXT: je .LBB15_40 -; AVX512F-NEXT: .LBB15_39: # %cond.store37 +; AVX512F-NEXT: je .LBB15_21 +; AVX512F-NEXT: .LBB15_52: # %cond.store37 ; AVX512F-NEXT: vpextrb $3, %xmm0, 19(%rdi) ; AVX512F-NEXT: testl $1048576, %eax # imm = 0x100000 -; AVX512F-NEXT: je .LBB15_42 -; AVX512F-NEXT: .LBB15_41: # %cond.store39 +; AVX512F-NEXT: je .LBB15_22 +; AVX512F-NEXT: .LBB15_53: # %cond.store39 ; AVX512F-NEXT: vpextrb $4, %xmm0, 20(%rdi) ; AVX512F-NEXT: testl $2097152, %eax # imm = 0x200000 -; AVX512F-NEXT: je .LBB15_44 -; AVX512F-NEXT: .LBB15_43: # %cond.store41 +; AVX512F-NEXT: je .LBB15_23 +; AVX512F-NEXT: .LBB15_54: # %cond.store41 ; AVX512F-NEXT: vpextrb $5, %xmm0, 21(%rdi) ; AVX512F-NEXT: testl $4194304, %eax # imm = 0x400000 -; AVX512F-NEXT: je .LBB15_46 -; AVX512F-NEXT: .LBB15_45: # %cond.store43 +; AVX512F-NEXT: je .LBB15_24 +; AVX512F-NEXT: .LBB15_55: # %cond.store43 ; AVX512F-NEXT: vpextrb $6, %xmm0, 22(%rdi) ; AVX512F-NEXT: testl $8388608, %eax # imm = 0x800000 -; AVX512F-NEXT: je .LBB15_48 -; AVX512F-NEXT: .LBB15_47: # %cond.store45 +; AVX512F-NEXT: je .LBB15_25 +; AVX512F-NEXT: .LBB15_56: # %cond.store45 ; AVX512F-NEXT: vpextrb $7, %xmm0, 23(%rdi) ; AVX512F-NEXT: testl $16777216, %eax # imm = 0x1000000 -; AVX512F-NEXT: je .LBB15_50 -; AVX512F-NEXT: .LBB15_49: # %cond.store47 +; AVX512F-NEXT: je .LBB15_26 +; AVX512F-NEXT: .LBB15_57: # %cond.store47 ; AVX512F-NEXT: vpextrb $8, %xmm0, 24(%rdi) ; AVX512F-NEXT: testl $33554432, %eax # imm = 0x2000000 -; AVX512F-NEXT: je .LBB15_52 -; AVX512F-NEXT: .LBB15_51: # %cond.store49 +; AVX512F-NEXT: je .LBB15_27 +; AVX512F-NEXT: .LBB15_58: # %cond.store49 ; AVX512F-NEXT: vpextrb $9, %xmm0, 25(%rdi) ; AVX512F-NEXT: testl $67108864, %eax # imm = 0x4000000 -; AVX512F-NEXT: je .LBB15_54 -; AVX512F-NEXT: .LBB15_53: # %cond.store51 +; AVX512F-NEXT: je .LBB15_28 +; AVX512F-NEXT: .LBB15_59: # %cond.store51 ; AVX512F-NEXT: vpextrb $10, %xmm0, 26(%rdi) ; AVX512F-NEXT: testl $134217728, %eax # imm = 0x8000000 -; AVX512F-NEXT: je .LBB15_56 -; AVX512F-NEXT: .LBB15_55: # %cond.store53 +; AVX512F-NEXT: je .LBB15_29 +; AVX512F-NEXT: .LBB15_60: # %cond.store53 ; AVX512F-NEXT: vpextrb $11, %xmm0, 27(%rdi) ; AVX512F-NEXT: testl $268435456, %eax # imm = 0x10000000 -; AVX512F-NEXT: je .LBB15_58 -; AVX512F-NEXT: .LBB15_57: # %cond.store55 +; AVX512F-NEXT: je .LBB15_30 +; AVX512F-NEXT: .LBB15_61: # %cond.store55 ; AVX512F-NEXT: vpextrb $12, %xmm0, 28(%rdi) ; AVX512F-NEXT: testl $536870912, %eax # imm = 0x20000000 -; AVX512F-NEXT: je .LBB15_60 -; AVX512F-NEXT: .LBB15_59: # %cond.store57 +; AVX512F-NEXT: je .LBB15_31 +; AVX512F-NEXT: .LBB15_62: # %cond.store57 ; AVX512F-NEXT: vpextrb $13, %xmm0, 29(%rdi) ; AVX512F-NEXT: testl $1073741824, %eax # imm = 0x40000000 -; AVX512F-NEXT: je .LBB15_62 -; AVX512F-NEXT: .LBB15_61: # %cond.store59 +; AVX512F-NEXT: je .LBB15_32 +; AVX512F-NEXT: .LBB15_63: # %cond.store59 ; AVX512F-NEXT: vpextrb $14, %xmm0, 30(%rdi) ; AVX512F-NEXT: testl $-2147483648, %eax # imm = 0x80000000 -; AVX512F-NEXT: je .LBB15_64 -; AVX512F-NEXT: .LBB15_63: # %cond.store61 +; AVX512F-NEXT: je .LBB15_33 +; AVX512F-NEXT: .LBB15_64: # %cond.store61 ; AVX512F-NEXT: vpextrb $15, %xmm0, 31(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -6945,228 +6945,228 @@ define void @truncstore_v32i16_v32i8(<32 x i16> %x, ptr %p, <32 x i8> %mask) { ; AVX512FVL-NEXT: vpmovmskb %ymm1, %eax ; AVX512FVL-NEXT: notl %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB15_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB15_34 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB15_3 -; AVX512FVL-NEXT: .LBB15_4: # %else2 +; AVX512FVL-NEXT: jne .LBB15_35 +; AVX512FVL-NEXT: .LBB15_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB15_5 -; AVX512FVL-NEXT: .LBB15_6: # %else4 +; AVX512FVL-NEXT: jne .LBB15_36 +; AVX512FVL-NEXT: .LBB15_3: # %else4 ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: jne .LBB15_7 -; AVX512FVL-NEXT: .LBB15_8: # %else6 +; AVX512FVL-NEXT: jne .LBB15_37 +; AVX512FVL-NEXT: .LBB15_4: # %else6 ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: jne .LBB15_9 -; AVX512FVL-NEXT: .LBB15_10: # %else8 +; AVX512FVL-NEXT: jne .LBB15_38 +; AVX512FVL-NEXT: .LBB15_5: # %else8 ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: jne .LBB15_11 -; AVX512FVL-NEXT: .LBB15_12: # %else10 +; AVX512FVL-NEXT: jne .LBB15_39 +; AVX512FVL-NEXT: .LBB15_6: # %else10 ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: jne .LBB15_13 -; AVX512FVL-NEXT: .LBB15_14: # %else12 +; AVX512FVL-NEXT: jne .LBB15_40 +; AVX512FVL-NEXT: .LBB15_7: # %else12 ; AVX512FVL-NEXT: testb %al, %al -; AVX512FVL-NEXT: js .LBB15_15 -; AVX512FVL-NEXT: .LBB15_16: # %else14 +; AVX512FVL-NEXT: js .LBB15_41 +; AVX512FVL-NEXT: .LBB15_8: # %else14 ; AVX512FVL-NEXT: testl $256, %eax # imm = 0x100 -; AVX512FVL-NEXT: jne .LBB15_17 -; AVX512FVL-NEXT: .LBB15_18: # %else16 +; AVX512FVL-NEXT: jne .LBB15_42 +; AVX512FVL-NEXT: .LBB15_9: # %else16 ; AVX512FVL-NEXT: testl $512, %eax # imm = 0x200 -; AVX512FVL-NEXT: jne .LBB15_19 -; AVX512FVL-NEXT: .LBB15_20: # %else18 +; AVX512FVL-NEXT: jne .LBB15_43 +; AVX512FVL-NEXT: .LBB15_10: # %else18 ; AVX512FVL-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512FVL-NEXT: jne .LBB15_21 -; AVX512FVL-NEXT: .LBB15_22: # %else20 +; AVX512FVL-NEXT: jne .LBB15_44 +; AVX512FVL-NEXT: .LBB15_11: # %else20 ; AVX512FVL-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512FVL-NEXT: jne .LBB15_23 -; AVX512FVL-NEXT: .LBB15_24: # %else22 +; AVX512FVL-NEXT: jne .LBB15_45 +; AVX512FVL-NEXT: .LBB15_12: # %else22 ; AVX512FVL-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512FVL-NEXT: jne .LBB15_25 -; AVX512FVL-NEXT: .LBB15_26: # %else24 +; AVX512FVL-NEXT: jne .LBB15_46 +; AVX512FVL-NEXT: .LBB15_13: # %else24 ; AVX512FVL-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512FVL-NEXT: jne .LBB15_27 -; AVX512FVL-NEXT: .LBB15_28: # %else26 +; AVX512FVL-NEXT: jne .LBB15_47 +; AVX512FVL-NEXT: .LBB15_14: # %else26 ; AVX512FVL-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512FVL-NEXT: jne .LBB15_29 -; AVX512FVL-NEXT: .LBB15_30: # %else28 +; AVX512FVL-NEXT: jne .LBB15_48 +; AVX512FVL-NEXT: .LBB15_15: # %else28 ; AVX512FVL-NEXT: testw %ax, %ax -; AVX512FVL-NEXT: jns .LBB15_32 -; AVX512FVL-NEXT: .LBB15_31: # %cond.store29 +; AVX512FVL-NEXT: jns .LBB15_17 +; AVX512FVL-NEXT: .LBB15_16: # %cond.store29 ; AVX512FVL-NEXT: vpextrb $15, %xmm0, 15(%rdi) -; AVX512FVL-NEXT: .LBB15_32: # %else30 +; AVX512FVL-NEXT: .LBB15_17: # %else30 ; AVX512FVL-NEXT: testl $65536, %eax # imm = 0x10000 ; AVX512FVL-NEXT: vextracti128 $1, %ymm0, %xmm0 -; AVX512FVL-NEXT: jne .LBB15_33 -; AVX512FVL-NEXT: # %bb.34: # %else32 +; AVX512FVL-NEXT: jne .LBB15_49 +; AVX512FVL-NEXT: # %bb.18: # %else32 ; AVX512FVL-NEXT: testl $131072, %eax # imm = 0x20000 -; AVX512FVL-NEXT: jne .LBB15_35 -; AVX512FVL-NEXT: .LBB15_36: # %else34 +; AVX512FVL-NEXT: jne .LBB15_50 +; AVX512FVL-NEXT: .LBB15_19: # %else34 ; AVX512FVL-NEXT: testl $262144, %eax # imm = 0x40000 -; AVX512FVL-NEXT: jne .LBB15_37 -; AVX512FVL-NEXT: .LBB15_38: # %else36 +; AVX512FVL-NEXT: jne .LBB15_51 +; AVX512FVL-NEXT: .LBB15_20: # %else36 ; AVX512FVL-NEXT: testl $524288, %eax # imm = 0x80000 -; AVX512FVL-NEXT: jne .LBB15_39 -; AVX512FVL-NEXT: .LBB15_40: # %else38 +; AVX512FVL-NEXT: jne .LBB15_52 +; AVX512FVL-NEXT: .LBB15_21: # %else38 ; AVX512FVL-NEXT: testl $1048576, %eax # imm = 0x100000 -; AVX512FVL-NEXT: jne .LBB15_41 -; AVX512FVL-NEXT: .LBB15_42: # %else40 +; AVX512FVL-NEXT: jne .LBB15_53 +; AVX512FVL-NEXT: .LBB15_22: # %else40 ; AVX512FVL-NEXT: testl $2097152, %eax # imm = 0x200000 -; AVX512FVL-NEXT: jne .LBB15_43 -; AVX512FVL-NEXT: .LBB15_44: # %else42 +; AVX512FVL-NEXT: jne .LBB15_54 +; AVX512FVL-NEXT: .LBB15_23: # %else42 ; AVX512FVL-NEXT: testl $4194304, %eax # imm = 0x400000 -; AVX512FVL-NEXT: jne .LBB15_45 -; AVX512FVL-NEXT: .LBB15_46: # %else44 +; AVX512FVL-NEXT: jne .LBB15_55 +; AVX512FVL-NEXT: .LBB15_24: # %else44 ; AVX512FVL-NEXT: testl $8388608, %eax # imm = 0x800000 -; AVX512FVL-NEXT: jne .LBB15_47 -; AVX512FVL-NEXT: .LBB15_48: # %else46 +; AVX512FVL-NEXT: jne .LBB15_56 +; AVX512FVL-NEXT: .LBB15_25: # %else46 ; AVX512FVL-NEXT: testl $16777216, %eax # imm = 0x1000000 -; AVX512FVL-NEXT: jne .LBB15_49 -; AVX512FVL-NEXT: .LBB15_50: # %else48 +; AVX512FVL-NEXT: jne .LBB15_57 +; AVX512FVL-NEXT: .LBB15_26: # %else48 ; AVX512FVL-NEXT: testl $33554432, %eax # imm = 0x2000000 -; AVX512FVL-NEXT: jne .LBB15_51 -; AVX512FVL-NEXT: .LBB15_52: # %else50 +; AVX512FVL-NEXT: jne .LBB15_58 +; AVX512FVL-NEXT: .LBB15_27: # %else50 ; AVX512FVL-NEXT: testl $67108864, %eax # imm = 0x4000000 -; AVX512FVL-NEXT: jne .LBB15_53 -; AVX512FVL-NEXT: .LBB15_54: # %else52 +; AVX512FVL-NEXT: jne .LBB15_59 +; AVX512FVL-NEXT: .LBB15_28: # %else52 ; AVX512FVL-NEXT: testl $134217728, %eax # imm = 0x8000000 -; AVX512FVL-NEXT: jne .LBB15_55 -; AVX512FVL-NEXT: .LBB15_56: # %else54 +; AVX512FVL-NEXT: jne .LBB15_60 +; AVX512FVL-NEXT: .LBB15_29: # %else54 ; AVX512FVL-NEXT: testl $268435456, %eax # imm = 0x10000000 -; AVX512FVL-NEXT: jne .LBB15_57 -; AVX512FVL-NEXT: .LBB15_58: # %else56 +; AVX512FVL-NEXT: jne .LBB15_61 +; AVX512FVL-NEXT: .LBB15_30: # %else56 ; AVX512FVL-NEXT: testl $536870912, %eax # imm = 0x20000000 -; AVX512FVL-NEXT: jne .LBB15_59 -; AVX512FVL-NEXT: .LBB15_60: # %else58 +; AVX512FVL-NEXT: jne .LBB15_62 +; AVX512FVL-NEXT: .LBB15_31: # %else58 ; AVX512FVL-NEXT: testl $1073741824, %eax # imm = 0x40000000 -; AVX512FVL-NEXT: jne .LBB15_61 -; AVX512FVL-NEXT: .LBB15_62: # %else60 -; AVX512FVL-NEXT: testl $-2147483648, %eax # imm = 0x80000000 ; AVX512FVL-NEXT: jne .LBB15_63 -; AVX512FVL-NEXT: .LBB15_64: # %else62 +; AVX512FVL-NEXT: .LBB15_32: # %else60 +; AVX512FVL-NEXT: testl $-2147483648, %eax # imm = 0x80000000 +; AVX512FVL-NEXT: jne .LBB15_64 +; AVX512FVL-NEXT: .LBB15_33: # %else62 ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB15_1: # %cond.store +; AVX512FVL-NEXT: .LBB15_34: # %cond.store ; AVX512FVL-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB15_4 -; AVX512FVL-NEXT: .LBB15_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB15_2 +; AVX512FVL-NEXT: .LBB15_35: # %cond.store1 ; AVX512FVL-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB15_6 -; AVX512FVL-NEXT: .LBB15_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB15_3 +; AVX512FVL-NEXT: .LBB15_36: # %cond.store3 ; AVX512FVL-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB15_8 -; AVX512FVL-NEXT: .LBB15_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB15_4 +; AVX512FVL-NEXT: .LBB15_37: # %cond.store5 ; AVX512FVL-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: je .LBB15_10 -; AVX512FVL-NEXT: .LBB15_9: # %cond.store7 +; AVX512FVL-NEXT: je .LBB15_5 +; AVX512FVL-NEXT: .LBB15_38: # %cond.store7 ; AVX512FVL-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: je .LBB15_12 -; AVX512FVL-NEXT: .LBB15_11: # %cond.store9 +; AVX512FVL-NEXT: je .LBB15_6 +; AVX512FVL-NEXT: .LBB15_39: # %cond.store9 ; AVX512FVL-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: je .LBB15_14 -; AVX512FVL-NEXT: .LBB15_13: # %cond.store11 +; AVX512FVL-NEXT: je .LBB15_7 +; AVX512FVL-NEXT: .LBB15_40: # %cond.store11 ; AVX512FVL-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX512FVL-NEXT: testb %al, %al -; AVX512FVL-NEXT: jns .LBB15_16 -; AVX512FVL-NEXT: .LBB15_15: # %cond.store13 +; AVX512FVL-NEXT: jns .LBB15_8 +; AVX512FVL-NEXT: .LBB15_41: # %cond.store13 ; AVX512FVL-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX512FVL-NEXT: testl $256, %eax # imm = 0x100 -; AVX512FVL-NEXT: je .LBB15_18 -; AVX512FVL-NEXT: .LBB15_17: # %cond.store15 +; AVX512FVL-NEXT: je .LBB15_9 +; AVX512FVL-NEXT: .LBB15_42: # %cond.store15 ; AVX512FVL-NEXT: vpextrb $8, %xmm0, 8(%rdi) ; AVX512FVL-NEXT: testl $512, %eax # imm = 0x200 -; AVX512FVL-NEXT: je .LBB15_20 -; AVX512FVL-NEXT: .LBB15_19: # %cond.store17 +; AVX512FVL-NEXT: je .LBB15_10 +; AVX512FVL-NEXT: .LBB15_43: # %cond.store17 ; AVX512FVL-NEXT: vpextrb $9, %xmm0, 9(%rdi) ; AVX512FVL-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512FVL-NEXT: je .LBB15_22 -; AVX512FVL-NEXT: .LBB15_21: # %cond.store19 +; AVX512FVL-NEXT: je .LBB15_11 +; AVX512FVL-NEXT: .LBB15_44: # %cond.store19 ; AVX512FVL-NEXT: vpextrb $10, %xmm0, 10(%rdi) ; AVX512FVL-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512FVL-NEXT: je .LBB15_24 -; AVX512FVL-NEXT: .LBB15_23: # %cond.store21 +; AVX512FVL-NEXT: je .LBB15_12 +; AVX512FVL-NEXT: .LBB15_45: # %cond.store21 ; AVX512FVL-NEXT: vpextrb $11, %xmm0, 11(%rdi) ; AVX512FVL-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512FVL-NEXT: je .LBB15_26 -; AVX512FVL-NEXT: .LBB15_25: # %cond.store23 +; AVX512FVL-NEXT: je .LBB15_13 +; AVX512FVL-NEXT: .LBB15_46: # %cond.store23 ; AVX512FVL-NEXT: vpextrb $12, %xmm0, 12(%rdi) ; AVX512FVL-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512FVL-NEXT: je .LBB15_28 -; AVX512FVL-NEXT: .LBB15_27: # %cond.store25 +; AVX512FVL-NEXT: je .LBB15_14 +; AVX512FVL-NEXT: .LBB15_47: # %cond.store25 ; AVX512FVL-NEXT: vpextrb $13, %xmm0, 13(%rdi) ; AVX512FVL-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512FVL-NEXT: je .LBB15_30 -; AVX512FVL-NEXT: .LBB15_29: # %cond.store27 +; AVX512FVL-NEXT: je .LBB15_15 +; AVX512FVL-NEXT: .LBB15_48: # %cond.store27 ; AVX512FVL-NEXT: vpextrb $14, %xmm0, 14(%rdi) ; AVX512FVL-NEXT: testw %ax, %ax -; AVX512FVL-NEXT: js .LBB15_31 -; AVX512FVL-NEXT: jmp .LBB15_32 -; AVX512FVL-NEXT: .LBB15_33: # %cond.store31 +; AVX512FVL-NEXT: js .LBB15_16 +; AVX512FVL-NEXT: jmp .LBB15_17 +; AVX512FVL-NEXT: .LBB15_49: # %cond.store31 ; AVX512FVL-NEXT: vpextrb $0, %xmm0, 16(%rdi) ; AVX512FVL-NEXT: testl $131072, %eax # imm = 0x20000 -; AVX512FVL-NEXT: je .LBB15_36 -; AVX512FVL-NEXT: .LBB15_35: # %cond.store33 +; AVX512FVL-NEXT: je .LBB15_19 +; AVX512FVL-NEXT: .LBB15_50: # %cond.store33 ; AVX512FVL-NEXT: vpextrb $1, %xmm0, 17(%rdi) ; AVX512FVL-NEXT: testl $262144, %eax # imm = 0x40000 -; AVX512FVL-NEXT: je .LBB15_38 -; AVX512FVL-NEXT: .LBB15_37: # %cond.store35 +; AVX512FVL-NEXT: je .LBB15_20 +; AVX512FVL-NEXT: .LBB15_51: # %cond.store35 ; AVX512FVL-NEXT: vpextrb $2, %xmm0, 18(%rdi) ; AVX512FVL-NEXT: testl $524288, %eax # imm = 0x80000 -; AVX512FVL-NEXT: je .LBB15_40 -; AVX512FVL-NEXT: .LBB15_39: # %cond.store37 +; AVX512FVL-NEXT: je .LBB15_21 +; AVX512FVL-NEXT: .LBB15_52: # %cond.store37 ; AVX512FVL-NEXT: vpextrb $3, %xmm0, 19(%rdi) ; AVX512FVL-NEXT: testl $1048576, %eax # imm = 0x100000 -; AVX512FVL-NEXT: je .LBB15_42 -; AVX512FVL-NEXT: .LBB15_41: # %cond.store39 +; AVX512FVL-NEXT: je .LBB15_22 +; AVX512FVL-NEXT: .LBB15_53: # %cond.store39 ; AVX512FVL-NEXT: vpextrb $4, %xmm0, 20(%rdi) ; AVX512FVL-NEXT: testl $2097152, %eax # imm = 0x200000 -; AVX512FVL-NEXT: je .LBB15_44 -; AVX512FVL-NEXT: .LBB15_43: # %cond.store41 +; AVX512FVL-NEXT: je .LBB15_23 +; AVX512FVL-NEXT: .LBB15_54: # %cond.store41 ; AVX512FVL-NEXT: vpextrb $5, %xmm0, 21(%rdi) ; AVX512FVL-NEXT: testl $4194304, %eax # imm = 0x400000 -; AVX512FVL-NEXT: je .LBB15_46 -; AVX512FVL-NEXT: .LBB15_45: # %cond.store43 +; AVX512FVL-NEXT: je .LBB15_24 +; AVX512FVL-NEXT: .LBB15_55: # %cond.store43 ; AVX512FVL-NEXT: vpextrb $6, %xmm0, 22(%rdi) ; AVX512FVL-NEXT: testl $8388608, %eax # imm = 0x800000 -; AVX512FVL-NEXT: je .LBB15_48 -; AVX512FVL-NEXT: .LBB15_47: # %cond.store45 +; AVX512FVL-NEXT: je .LBB15_25 +; AVX512FVL-NEXT: .LBB15_56: # %cond.store45 ; AVX512FVL-NEXT: vpextrb $7, %xmm0, 23(%rdi) ; AVX512FVL-NEXT: testl $16777216, %eax # imm = 0x1000000 -; AVX512FVL-NEXT: je .LBB15_50 -; AVX512FVL-NEXT: .LBB15_49: # %cond.store47 +; AVX512FVL-NEXT: je .LBB15_26 +; AVX512FVL-NEXT: .LBB15_57: # %cond.store47 ; AVX512FVL-NEXT: vpextrb $8, %xmm0, 24(%rdi) ; AVX512FVL-NEXT: testl $33554432, %eax # imm = 0x2000000 -; AVX512FVL-NEXT: je .LBB15_52 -; AVX512FVL-NEXT: .LBB15_51: # %cond.store49 +; AVX512FVL-NEXT: je .LBB15_27 +; AVX512FVL-NEXT: .LBB15_58: # %cond.store49 ; AVX512FVL-NEXT: vpextrb $9, %xmm0, 25(%rdi) ; AVX512FVL-NEXT: testl $67108864, %eax # imm = 0x4000000 -; AVX512FVL-NEXT: je .LBB15_54 -; AVX512FVL-NEXT: .LBB15_53: # %cond.store51 +; AVX512FVL-NEXT: je .LBB15_28 +; AVX512FVL-NEXT: .LBB15_59: # %cond.store51 ; AVX512FVL-NEXT: vpextrb $10, %xmm0, 26(%rdi) ; AVX512FVL-NEXT: testl $134217728, %eax # imm = 0x8000000 -; AVX512FVL-NEXT: je .LBB15_56 -; AVX512FVL-NEXT: .LBB15_55: # %cond.store53 +; AVX512FVL-NEXT: je .LBB15_29 +; AVX512FVL-NEXT: .LBB15_60: # %cond.store53 ; AVX512FVL-NEXT: vpextrb $11, %xmm0, 27(%rdi) ; AVX512FVL-NEXT: testl $268435456, %eax # imm = 0x10000000 -; AVX512FVL-NEXT: je .LBB15_58 -; AVX512FVL-NEXT: .LBB15_57: # %cond.store55 +; AVX512FVL-NEXT: je .LBB15_30 +; AVX512FVL-NEXT: .LBB15_61: # %cond.store55 ; AVX512FVL-NEXT: vpextrb $12, %xmm0, 28(%rdi) ; AVX512FVL-NEXT: testl $536870912, %eax # imm = 0x20000000 -; AVX512FVL-NEXT: je .LBB15_60 -; AVX512FVL-NEXT: .LBB15_59: # %cond.store57 +; AVX512FVL-NEXT: je .LBB15_31 +; AVX512FVL-NEXT: .LBB15_62: # %cond.store57 ; AVX512FVL-NEXT: vpextrb $13, %xmm0, 29(%rdi) ; AVX512FVL-NEXT: testl $1073741824, %eax # imm = 0x40000000 -; AVX512FVL-NEXT: je .LBB15_62 -; AVX512FVL-NEXT: .LBB15_61: # %cond.store59 +; AVX512FVL-NEXT: je .LBB15_32 +; AVX512FVL-NEXT: .LBB15_63: # %cond.store59 ; AVX512FVL-NEXT: vpextrb $14, %xmm0, 30(%rdi) ; AVX512FVL-NEXT: testl $-2147483648, %eax # imm = 0x80000000 -; AVX512FVL-NEXT: je .LBB15_64 -; AVX512FVL-NEXT: .LBB15_63: # %cond.store61 +; AVX512FVL-NEXT: je .LBB15_33 +; AVX512FVL-NEXT: .LBB15_64: # %cond.store61 ; AVX512FVL-NEXT: vpextrb $15, %xmm0, 31(%rdi) ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq @@ -7210,103 +7210,103 @@ define void @truncstore_v16i16_v16i8(<16 x i16> %x, ptr %p, <16 x i8> %mask) { ; SSE2-NEXT: xorl $65535, %eax # imm = 0xFFFF ; SSE2-NEXT: testb $1, %al ; SSE2-NEXT: movd %xmm0, %ecx -; SSE2-NEXT: jne .LBB16_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB16_28 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne .LBB16_3 -; SSE2-NEXT: .LBB16_4: # %else2 +; SSE2-NEXT: jne .LBB16_29 +; SSE2-NEXT: .LBB16_2: # %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne .LBB16_5 -; SSE2-NEXT: .LBB16_6: # %else4 +; SSE2-NEXT: jne .LBB16_30 +; SSE2-NEXT: .LBB16_3: # %else4 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je .LBB16_8 -; SSE2-NEXT: .LBB16_7: # %cond.store5 +; SSE2-NEXT: je .LBB16_5 +; SSE2-NEXT: .LBB16_4: # %cond.store5 ; SSE2-NEXT: shrl $24, %ecx ; SSE2-NEXT: movb %cl, 3(%rdi) -; SSE2-NEXT: .LBB16_8: # %else6 +; SSE2-NEXT: .LBB16_5: # %else6 ; SSE2-NEXT: testb $16, %al ; SSE2-NEXT: pextrw $2, %xmm0, %ecx -; SSE2-NEXT: je .LBB16_10 -; SSE2-NEXT: # %bb.9: # %cond.store7 +; SSE2-NEXT: je .LBB16_7 +; SSE2-NEXT: # %bb.6: # %cond.store7 ; SSE2-NEXT: movb %cl, 4(%rdi) -; SSE2-NEXT: .LBB16_10: # %else8 +; SSE2-NEXT: .LBB16_7: # %else8 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je .LBB16_12 -; SSE2-NEXT: # %bb.11: # %cond.store9 +; SSE2-NEXT: je .LBB16_9 +; SSE2-NEXT: # %bb.8: # %cond.store9 ; SSE2-NEXT: movb %ch, 5(%rdi) -; SSE2-NEXT: .LBB16_12: # %else10 +; SSE2-NEXT: .LBB16_9: # %else10 ; SSE2-NEXT: testb $64, %al ; SSE2-NEXT: pextrw $3, %xmm0, %ecx -; SSE2-NEXT: je .LBB16_14 -; SSE2-NEXT: # %bb.13: # %cond.store11 +; SSE2-NEXT: je .LBB16_11 +; SSE2-NEXT: # %bb.10: # %cond.store11 ; SSE2-NEXT: movb %cl, 6(%rdi) -; SSE2-NEXT: .LBB16_14: # %else12 +; SSE2-NEXT: .LBB16_11: # %else12 ; SSE2-NEXT: testb %al, %al -; SSE2-NEXT: jns .LBB16_16 -; SSE2-NEXT: # %bb.15: # %cond.store13 +; SSE2-NEXT: jns .LBB16_13 +; SSE2-NEXT: # %bb.12: # %cond.store13 ; SSE2-NEXT: movb %ch, 7(%rdi) -; SSE2-NEXT: .LBB16_16: # %else14 +; SSE2-NEXT: .LBB16_13: # %else14 ; SSE2-NEXT: testl $256, %eax # imm = 0x100 ; SSE2-NEXT: pextrw $4, %xmm0, %ecx -; SSE2-NEXT: je .LBB16_18 -; SSE2-NEXT: # %bb.17: # %cond.store15 +; SSE2-NEXT: je .LBB16_15 +; SSE2-NEXT: # %bb.14: # %cond.store15 ; SSE2-NEXT: movb %cl, 8(%rdi) -; SSE2-NEXT: .LBB16_18: # %else16 +; SSE2-NEXT: .LBB16_15: # %else16 ; SSE2-NEXT: testl $512, %eax # imm = 0x200 -; SSE2-NEXT: je .LBB16_20 -; SSE2-NEXT: # %bb.19: # %cond.store17 +; SSE2-NEXT: je .LBB16_17 +; SSE2-NEXT: # %bb.16: # %cond.store17 ; SSE2-NEXT: movb %ch, 9(%rdi) -; SSE2-NEXT: .LBB16_20: # %else18 +; SSE2-NEXT: .LBB16_17: # %else18 ; SSE2-NEXT: testl $1024, %eax # imm = 0x400 ; SSE2-NEXT: pextrw $5, %xmm0, %ecx -; SSE2-NEXT: je .LBB16_22 -; SSE2-NEXT: # %bb.21: # %cond.store19 +; SSE2-NEXT: je .LBB16_19 +; SSE2-NEXT: # %bb.18: # %cond.store19 ; SSE2-NEXT: movb %cl, 10(%rdi) -; SSE2-NEXT: .LBB16_22: # %else20 +; SSE2-NEXT: .LBB16_19: # %else20 ; SSE2-NEXT: testl $2048, %eax # imm = 0x800 -; SSE2-NEXT: je .LBB16_24 -; SSE2-NEXT: # %bb.23: # %cond.store21 +; SSE2-NEXT: je .LBB16_21 +; SSE2-NEXT: # %bb.20: # %cond.store21 ; SSE2-NEXT: movb %ch, 11(%rdi) -; SSE2-NEXT: .LBB16_24: # %else22 +; SSE2-NEXT: .LBB16_21: # %else22 ; SSE2-NEXT: testl $4096, %eax # imm = 0x1000 ; SSE2-NEXT: pextrw $6, %xmm0, %ecx -; SSE2-NEXT: je .LBB16_26 -; SSE2-NEXT: # %bb.25: # %cond.store23 +; SSE2-NEXT: je .LBB16_23 +; SSE2-NEXT: # %bb.22: # %cond.store23 ; SSE2-NEXT: movb %cl, 12(%rdi) -; SSE2-NEXT: .LBB16_26: # %else24 +; SSE2-NEXT: .LBB16_23: # %else24 ; SSE2-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE2-NEXT: je .LBB16_28 -; SSE2-NEXT: # %bb.27: # %cond.store25 +; SSE2-NEXT: je .LBB16_25 +; SSE2-NEXT: # %bb.24: # %cond.store25 ; SSE2-NEXT: movb %ch, 13(%rdi) -; SSE2-NEXT: .LBB16_28: # %else26 +; SSE2-NEXT: .LBB16_25: # %else26 ; SSE2-NEXT: testl $16384, %eax # imm = 0x4000 ; SSE2-NEXT: pextrw $7, %xmm0, %ecx -; SSE2-NEXT: jne .LBB16_29 -; SSE2-NEXT: # %bb.30: # %else28 -; SSE2-NEXT: testl $32768, %eax # imm = 0x8000 ; SSE2-NEXT: jne .LBB16_31 -; SSE2-NEXT: .LBB16_32: # %else30 +; SSE2-NEXT: # %bb.26: # %else28 +; SSE2-NEXT: testl $32768, %eax # imm = 0x8000 +; SSE2-NEXT: jne .LBB16_32 +; SSE2-NEXT: .LBB16_27: # %else30 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB16_1: # %cond.store +; SSE2-NEXT: .LBB16_28: # %cond.store ; SSE2-NEXT: movb %cl, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB16_4 -; SSE2-NEXT: .LBB16_3: # %cond.store1 +; SSE2-NEXT: je .LBB16_2 +; SSE2-NEXT: .LBB16_29: # %cond.store1 ; SSE2-NEXT: movb %ch, 1(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je .LBB16_6 -; SSE2-NEXT: .LBB16_5: # %cond.store3 +; SSE2-NEXT: je .LBB16_3 +; SSE2-NEXT: .LBB16_30: # %cond.store3 ; SSE2-NEXT: movl %ecx, %edx ; SSE2-NEXT: shrl $16, %edx ; SSE2-NEXT: movb %dl, 2(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne .LBB16_7 -; SSE2-NEXT: jmp .LBB16_8 -; SSE2-NEXT: .LBB16_29: # %cond.store27 +; SSE2-NEXT: jne .LBB16_4 +; SSE2-NEXT: jmp .LBB16_5 +; SSE2-NEXT: .LBB16_31: # %cond.store27 ; SSE2-NEXT: movb %cl, 14(%rdi) ; SSE2-NEXT: testl $32768, %eax # imm = 0x8000 -; SSE2-NEXT: je .LBB16_32 -; SSE2-NEXT: .LBB16_31: # %cond.store29 +; SSE2-NEXT: je .LBB16_27 +; SSE2-NEXT: .LBB16_32: # %cond.store29 ; SSE2-NEXT: movb %ch, 15(%rdi) ; SSE2-NEXT: retq ; @@ -7321,115 +7321,115 @@ define void @truncstore_v16i16_v16i8(<16 x i16> %x, ptr %p, <16 x i8> %mask) { ; SSE4-NEXT: pmovmskb %xmm3, %eax ; SSE4-NEXT: xorl $65535, %eax # imm = 0xFFFF ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB16_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB16_17 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB16_3 -; SSE4-NEXT: .LBB16_4: # %else2 +; SSE4-NEXT: jne .LBB16_18 +; SSE4-NEXT: .LBB16_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB16_5 -; SSE4-NEXT: .LBB16_6: # %else4 +; SSE4-NEXT: jne .LBB16_19 +; SSE4-NEXT: .LBB16_3: # %else4 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne .LBB16_7 -; SSE4-NEXT: .LBB16_8: # %else6 +; SSE4-NEXT: jne .LBB16_20 +; SSE4-NEXT: .LBB16_4: # %else6 ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: jne .LBB16_9 -; SSE4-NEXT: .LBB16_10: # %else8 +; SSE4-NEXT: jne .LBB16_21 +; SSE4-NEXT: .LBB16_5: # %else8 ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: jne .LBB16_11 -; SSE4-NEXT: .LBB16_12: # %else10 +; SSE4-NEXT: jne .LBB16_22 +; SSE4-NEXT: .LBB16_6: # %else10 ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: jne .LBB16_13 -; SSE4-NEXT: .LBB16_14: # %else12 +; SSE4-NEXT: jne .LBB16_23 +; SSE4-NEXT: .LBB16_7: # %else12 ; SSE4-NEXT: testb %al, %al -; SSE4-NEXT: js .LBB16_15 -; SSE4-NEXT: .LBB16_16: # %else14 +; SSE4-NEXT: js .LBB16_24 +; SSE4-NEXT: .LBB16_8: # %else14 ; SSE4-NEXT: testl $256, %eax # imm = 0x100 -; SSE4-NEXT: jne .LBB16_17 -; SSE4-NEXT: .LBB16_18: # %else16 +; SSE4-NEXT: jne .LBB16_25 +; SSE4-NEXT: .LBB16_9: # %else16 ; SSE4-NEXT: testl $512, %eax # imm = 0x200 -; SSE4-NEXT: jne .LBB16_19 -; SSE4-NEXT: .LBB16_20: # %else18 +; SSE4-NEXT: jne .LBB16_26 +; SSE4-NEXT: .LBB16_10: # %else18 ; SSE4-NEXT: testl $1024, %eax # imm = 0x400 -; SSE4-NEXT: jne .LBB16_21 -; SSE4-NEXT: .LBB16_22: # %else20 +; SSE4-NEXT: jne .LBB16_27 +; SSE4-NEXT: .LBB16_11: # %else20 ; SSE4-NEXT: testl $2048, %eax # imm = 0x800 -; SSE4-NEXT: jne .LBB16_23 -; SSE4-NEXT: .LBB16_24: # %else22 +; SSE4-NEXT: jne .LBB16_28 +; SSE4-NEXT: .LBB16_12: # %else22 ; SSE4-NEXT: testl $4096, %eax # imm = 0x1000 -; SSE4-NEXT: jne .LBB16_25 -; SSE4-NEXT: .LBB16_26: # %else24 +; SSE4-NEXT: jne .LBB16_29 +; SSE4-NEXT: .LBB16_13: # %else24 ; SSE4-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE4-NEXT: jne .LBB16_27 -; SSE4-NEXT: .LBB16_28: # %else26 +; SSE4-NEXT: jne .LBB16_30 +; SSE4-NEXT: .LBB16_14: # %else26 ; SSE4-NEXT: testl $16384, %eax # imm = 0x4000 -; SSE4-NEXT: jne .LBB16_29 -; SSE4-NEXT: .LBB16_30: # %else28 -; SSE4-NEXT: testl $32768, %eax # imm = 0x8000 ; SSE4-NEXT: jne .LBB16_31 -; SSE4-NEXT: .LBB16_32: # %else30 +; SSE4-NEXT: .LBB16_15: # %else28 +; SSE4-NEXT: testl $32768, %eax # imm = 0x8000 +; SSE4-NEXT: jne .LBB16_32 +; SSE4-NEXT: .LBB16_16: # %else30 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB16_1: # %cond.store +; SSE4-NEXT: .LBB16_17: # %cond.store ; SSE4-NEXT: pextrb $0, %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB16_4 -; SSE4-NEXT: .LBB16_3: # %cond.store1 +; SSE4-NEXT: je .LBB16_2 +; SSE4-NEXT: .LBB16_18: # %cond.store1 ; SSE4-NEXT: pextrb $1, %xmm0, 1(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB16_6 -; SSE4-NEXT: .LBB16_5: # %cond.store3 +; SSE4-NEXT: je .LBB16_3 +; SSE4-NEXT: .LBB16_19: # %cond.store3 ; SSE4-NEXT: pextrb $2, %xmm0, 2(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB16_8 -; SSE4-NEXT: .LBB16_7: # %cond.store5 +; SSE4-NEXT: je .LBB16_4 +; SSE4-NEXT: .LBB16_20: # %cond.store5 ; SSE4-NEXT: pextrb $3, %xmm0, 3(%rdi) ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: je .LBB16_10 -; SSE4-NEXT: .LBB16_9: # %cond.store7 +; SSE4-NEXT: je .LBB16_5 +; SSE4-NEXT: .LBB16_21: # %cond.store7 ; SSE4-NEXT: pextrb $4, %xmm0, 4(%rdi) ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: je .LBB16_12 -; SSE4-NEXT: .LBB16_11: # %cond.store9 +; SSE4-NEXT: je .LBB16_6 +; SSE4-NEXT: .LBB16_22: # %cond.store9 ; SSE4-NEXT: pextrb $5, %xmm0, 5(%rdi) ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: je .LBB16_14 -; SSE4-NEXT: .LBB16_13: # %cond.store11 +; SSE4-NEXT: je .LBB16_7 +; SSE4-NEXT: .LBB16_23: # %cond.store11 ; SSE4-NEXT: pextrb $6, %xmm0, 6(%rdi) ; SSE4-NEXT: testb %al, %al -; SSE4-NEXT: jns .LBB16_16 -; SSE4-NEXT: .LBB16_15: # %cond.store13 +; SSE4-NEXT: jns .LBB16_8 +; SSE4-NEXT: .LBB16_24: # %cond.store13 ; SSE4-NEXT: pextrb $7, %xmm0, 7(%rdi) ; SSE4-NEXT: testl $256, %eax # imm = 0x100 -; SSE4-NEXT: je .LBB16_18 -; SSE4-NEXT: .LBB16_17: # %cond.store15 +; SSE4-NEXT: je .LBB16_9 +; SSE4-NEXT: .LBB16_25: # %cond.store15 ; SSE4-NEXT: pextrb $8, %xmm0, 8(%rdi) ; SSE4-NEXT: testl $512, %eax # imm = 0x200 -; SSE4-NEXT: je .LBB16_20 -; SSE4-NEXT: .LBB16_19: # %cond.store17 +; SSE4-NEXT: je .LBB16_10 +; SSE4-NEXT: .LBB16_26: # %cond.store17 ; SSE4-NEXT: pextrb $9, %xmm0, 9(%rdi) ; SSE4-NEXT: testl $1024, %eax # imm = 0x400 -; SSE4-NEXT: je .LBB16_22 -; SSE4-NEXT: .LBB16_21: # %cond.store19 +; SSE4-NEXT: je .LBB16_11 +; SSE4-NEXT: .LBB16_27: # %cond.store19 ; SSE4-NEXT: pextrb $10, %xmm0, 10(%rdi) ; SSE4-NEXT: testl $2048, %eax # imm = 0x800 -; SSE4-NEXT: je .LBB16_24 -; SSE4-NEXT: .LBB16_23: # %cond.store21 +; SSE4-NEXT: je .LBB16_12 +; SSE4-NEXT: .LBB16_28: # %cond.store21 ; SSE4-NEXT: pextrb $11, %xmm0, 11(%rdi) ; SSE4-NEXT: testl $4096, %eax # imm = 0x1000 -; SSE4-NEXT: je .LBB16_26 -; SSE4-NEXT: .LBB16_25: # %cond.store23 +; SSE4-NEXT: je .LBB16_13 +; SSE4-NEXT: .LBB16_29: # %cond.store23 ; SSE4-NEXT: pextrb $12, %xmm0, 12(%rdi) ; SSE4-NEXT: testl $8192, %eax # imm = 0x2000 -; SSE4-NEXT: je .LBB16_28 -; SSE4-NEXT: .LBB16_27: # %cond.store25 +; SSE4-NEXT: je .LBB16_14 +; SSE4-NEXT: .LBB16_30: # %cond.store25 ; SSE4-NEXT: pextrb $13, %xmm0, 13(%rdi) ; SSE4-NEXT: testl $16384, %eax # imm = 0x4000 -; SSE4-NEXT: je .LBB16_30 -; SSE4-NEXT: .LBB16_29: # %cond.store27 +; SSE4-NEXT: je .LBB16_15 +; SSE4-NEXT: .LBB16_31: # %cond.store27 ; SSE4-NEXT: pextrb $14, %xmm0, 14(%rdi) ; SSE4-NEXT: testl $32768, %eax # imm = 0x8000 -; SSE4-NEXT: je .LBB16_32 -; SSE4-NEXT: .LBB16_31: # %cond.store29 +; SSE4-NEXT: je .LBB16_16 +; SSE4-NEXT: .LBB16_32: # %cond.store29 ; SSE4-NEXT: pextrb $15, %xmm0, 15(%rdi) ; SSE4-NEXT: retq ; @@ -7445,116 +7445,116 @@ define void @truncstore_v16i16_v16i8(<16 x i16> %x, ptr %p, <16 x i8> %mask) { ; AVX1-NEXT: vpmovmskb %xmm1, %eax ; AVX1-NEXT: xorl $65535, %eax # imm = 0xFFFF ; AVX1-NEXT: testb $1, %al -; AVX1-NEXT: jne .LBB16_1 -; AVX1-NEXT: # %bb.2: # %else +; AVX1-NEXT: jne .LBB16_17 +; AVX1-NEXT: # %bb.1: # %else ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: jne .LBB16_3 -; AVX1-NEXT: .LBB16_4: # %else2 +; AVX1-NEXT: jne .LBB16_18 +; AVX1-NEXT: .LBB16_2: # %else2 ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: jne .LBB16_5 -; AVX1-NEXT: .LBB16_6: # %else4 +; AVX1-NEXT: jne .LBB16_19 +; AVX1-NEXT: .LBB16_3: # %else4 ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: jne .LBB16_7 -; AVX1-NEXT: .LBB16_8: # %else6 +; AVX1-NEXT: jne .LBB16_20 +; AVX1-NEXT: .LBB16_4: # %else6 ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: jne .LBB16_9 -; AVX1-NEXT: .LBB16_10: # %else8 +; AVX1-NEXT: jne .LBB16_21 +; AVX1-NEXT: .LBB16_5: # %else8 ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: jne .LBB16_11 -; AVX1-NEXT: .LBB16_12: # %else10 +; AVX1-NEXT: jne .LBB16_22 +; AVX1-NEXT: .LBB16_6: # %else10 ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: jne .LBB16_13 -; AVX1-NEXT: .LBB16_14: # %else12 +; AVX1-NEXT: jne .LBB16_23 +; AVX1-NEXT: .LBB16_7: # %else12 ; AVX1-NEXT: testb %al, %al -; AVX1-NEXT: js .LBB16_15 -; AVX1-NEXT: .LBB16_16: # %else14 +; AVX1-NEXT: js .LBB16_24 +; AVX1-NEXT: .LBB16_8: # %else14 ; AVX1-NEXT: testl $256, %eax # imm = 0x100 -; AVX1-NEXT: jne .LBB16_17 -; AVX1-NEXT: .LBB16_18: # %else16 +; AVX1-NEXT: jne .LBB16_25 +; AVX1-NEXT: .LBB16_9: # %else16 ; AVX1-NEXT: testl $512, %eax # imm = 0x200 -; AVX1-NEXT: jne .LBB16_19 -; AVX1-NEXT: .LBB16_20: # %else18 +; AVX1-NEXT: jne .LBB16_26 +; AVX1-NEXT: .LBB16_10: # %else18 ; AVX1-NEXT: testl $1024, %eax # imm = 0x400 -; AVX1-NEXT: jne .LBB16_21 -; AVX1-NEXT: .LBB16_22: # %else20 +; AVX1-NEXT: jne .LBB16_27 +; AVX1-NEXT: .LBB16_11: # %else20 ; AVX1-NEXT: testl $2048, %eax # imm = 0x800 -; AVX1-NEXT: jne .LBB16_23 -; AVX1-NEXT: .LBB16_24: # %else22 +; AVX1-NEXT: jne .LBB16_28 +; AVX1-NEXT: .LBB16_12: # %else22 ; AVX1-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX1-NEXT: jne .LBB16_25 -; AVX1-NEXT: .LBB16_26: # %else24 +; AVX1-NEXT: jne .LBB16_29 +; AVX1-NEXT: .LBB16_13: # %else24 ; AVX1-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX1-NEXT: jne .LBB16_27 -; AVX1-NEXT: .LBB16_28: # %else26 +; AVX1-NEXT: jne .LBB16_30 +; AVX1-NEXT: .LBB16_14: # %else26 ; AVX1-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX1-NEXT: jne .LBB16_29 -; AVX1-NEXT: .LBB16_30: # %else28 -; AVX1-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX1-NEXT: jne .LBB16_31 -; AVX1-NEXT: .LBB16_32: # %else30 +; AVX1-NEXT: .LBB16_15: # %else28 +; AVX1-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX1-NEXT: jne .LBB16_32 +; AVX1-NEXT: .LBB16_16: # %else30 ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq -; AVX1-NEXT: .LBB16_1: # %cond.store +; AVX1-NEXT: .LBB16_17: # %cond.store ; AVX1-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX1-NEXT: testb $2, %al -; AVX1-NEXT: je .LBB16_4 -; AVX1-NEXT: .LBB16_3: # %cond.store1 +; AVX1-NEXT: je .LBB16_2 +; AVX1-NEXT: .LBB16_18: # %cond.store1 ; AVX1-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX1-NEXT: testb $4, %al -; AVX1-NEXT: je .LBB16_6 -; AVX1-NEXT: .LBB16_5: # %cond.store3 +; AVX1-NEXT: je .LBB16_3 +; AVX1-NEXT: .LBB16_19: # %cond.store3 ; AVX1-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX1-NEXT: testb $8, %al -; AVX1-NEXT: je .LBB16_8 -; AVX1-NEXT: .LBB16_7: # %cond.store5 +; AVX1-NEXT: je .LBB16_4 +; AVX1-NEXT: .LBB16_20: # %cond.store5 ; AVX1-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX1-NEXT: testb $16, %al -; AVX1-NEXT: je .LBB16_10 -; AVX1-NEXT: .LBB16_9: # %cond.store7 +; AVX1-NEXT: je .LBB16_5 +; AVX1-NEXT: .LBB16_21: # %cond.store7 ; AVX1-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX1-NEXT: testb $32, %al -; AVX1-NEXT: je .LBB16_12 -; AVX1-NEXT: .LBB16_11: # %cond.store9 +; AVX1-NEXT: je .LBB16_6 +; AVX1-NEXT: .LBB16_22: # %cond.store9 ; AVX1-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX1-NEXT: testb $64, %al -; AVX1-NEXT: je .LBB16_14 -; AVX1-NEXT: .LBB16_13: # %cond.store11 +; AVX1-NEXT: je .LBB16_7 +; AVX1-NEXT: .LBB16_23: # %cond.store11 ; AVX1-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX1-NEXT: testb %al, %al -; AVX1-NEXT: jns .LBB16_16 -; AVX1-NEXT: .LBB16_15: # %cond.store13 +; AVX1-NEXT: jns .LBB16_8 +; AVX1-NEXT: .LBB16_24: # %cond.store13 ; AVX1-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX1-NEXT: testl $256, %eax # imm = 0x100 -; AVX1-NEXT: je .LBB16_18 -; AVX1-NEXT: .LBB16_17: # %cond.store15 +; AVX1-NEXT: je .LBB16_9 +; AVX1-NEXT: .LBB16_25: # %cond.store15 ; AVX1-NEXT: vpextrb $8, %xmm0, 8(%rdi) ; AVX1-NEXT: testl $512, %eax # imm = 0x200 -; AVX1-NEXT: je .LBB16_20 -; AVX1-NEXT: .LBB16_19: # %cond.store17 +; AVX1-NEXT: je .LBB16_10 +; AVX1-NEXT: .LBB16_26: # %cond.store17 ; AVX1-NEXT: vpextrb $9, %xmm0, 9(%rdi) ; AVX1-NEXT: testl $1024, %eax # imm = 0x400 -; AVX1-NEXT: je .LBB16_22 -; AVX1-NEXT: .LBB16_21: # %cond.store19 +; AVX1-NEXT: je .LBB16_11 +; AVX1-NEXT: .LBB16_27: # %cond.store19 ; AVX1-NEXT: vpextrb $10, %xmm0, 10(%rdi) ; AVX1-NEXT: testl $2048, %eax # imm = 0x800 -; AVX1-NEXT: je .LBB16_24 -; AVX1-NEXT: .LBB16_23: # %cond.store21 +; AVX1-NEXT: je .LBB16_12 +; AVX1-NEXT: .LBB16_28: # %cond.store21 ; AVX1-NEXT: vpextrb $11, %xmm0, 11(%rdi) ; AVX1-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX1-NEXT: je .LBB16_26 -; AVX1-NEXT: .LBB16_25: # %cond.store23 +; AVX1-NEXT: je .LBB16_13 +; AVX1-NEXT: .LBB16_29: # %cond.store23 ; AVX1-NEXT: vpextrb $12, %xmm0, 12(%rdi) ; AVX1-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX1-NEXT: je .LBB16_28 -; AVX1-NEXT: .LBB16_27: # %cond.store25 +; AVX1-NEXT: je .LBB16_14 +; AVX1-NEXT: .LBB16_30: # %cond.store25 ; AVX1-NEXT: vpextrb $13, %xmm0, 13(%rdi) ; AVX1-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX1-NEXT: je .LBB16_30 -; AVX1-NEXT: .LBB16_29: # %cond.store27 +; AVX1-NEXT: je .LBB16_15 +; AVX1-NEXT: .LBB16_31: # %cond.store27 ; AVX1-NEXT: vpextrb $14, %xmm0, 14(%rdi) ; AVX1-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX1-NEXT: je .LBB16_32 -; AVX1-NEXT: .LBB16_31: # %cond.store29 +; AVX1-NEXT: je .LBB16_16 +; AVX1-NEXT: .LBB16_32: # %cond.store29 ; AVX1-NEXT: vpextrb $15, %xmm0, 15(%rdi) ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq @@ -7569,116 +7569,116 @@ define void @truncstore_v16i16_v16i8(<16 x i16> %x, ptr %p, <16 x i8> %mask) { ; AVX2-NEXT: vpmovmskb %xmm1, %eax ; AVX2-NEXT: xorl $65535, %eax # imm = 0xFFFF ; AVX2-NEXT: testb $1, %al -; AVX2-NEXT: jne .LBB16_1 -; AVX2-NEXT: # %bb.2: # %else +; AVX2-NEXT: jne .LBB16_17 +; AVX2-NEXT: # %bb.1: # %else ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: jne .LBB16_3 -; AVX2-NEXT: .LBB16_4: # %else2 +; AVX2-NEXT: jne .LBB16_18 +; AVX2-NEXT: .LBB16_2: # %else2 ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: jne .LBB16_5 -; AVX2-NEXT: .LBB16_6: # %else4 +; AVX2-NEXT: jne .LBB16_19 +; AVX2-NEXT: .LBB16_3: # %else4 ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: jne .LBB16_7 -; AVX2-NEXT: .LBB16_8: # %else6 +; AVX2-NEXT: jne .LBB16_20 +; AVX2-NEXT: .LBB16_4: # %else6 ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: jne .LBB16_9 -; AVX2-NEXT: .LBB16_10: # %else8 +; AVX2-NEXT: jne .LBB16_21 +; AVX2-NEXT: .LBB16_5: # %else8 ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: jne .LBB16_11 -; AVX2-NEXT: .LBB16_12: # %else10 +; AVX2-NEXT: jne .LBB16_22 +; AVX2-NEXT: .LBB16_6: # %else10 ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: jne .LBB16_13 -; AVX2-NEXT: .LBB16_14: # %else12 +; AVX2-NEXT: jne .LBB16_23 +; AVX2-NEXT: .LBB16_7: # %else12 ; AVX2-NEXT: testb %al, %al -; AVX2-NEXT: js .LBB16_15 -; AVX2-NEXT: .LBB16_16: # %else14 +; AVX2-NEXT: js .LBB16_24 +; AVX2-NEXT: .LBB16_8: # %else14 ; AVX2-NEXT: testl $256, %eax # imm = 0x100 -; AVX2-NEXT: jne .LBB16_17 -; AVX2-NEXT: .LBB16_18: # %else16 +; AVX2-NEXT: jne .LBB16_25 +; AVX2-NEXT: .LBB16_9: # %else16 ; AVX2-NEXT: testl $512, %eax # imm = 0x200 -; AVX2-NEXT: jne .LBB16_19 -; AVX2-NEXT: .LBB16_20: # %else18 +; AVX2-NEXT: jne .LBB16_26 +; AVX2-NEXT: .LBB16_10: # %else18 ; AVX2-NEXT: testl $1024, %eax # imm = 0x400 -; AVX2-NEXT: jne .LBB16_21 -; AVX2-NEXT: .LBB16_22: # %else20 +; AVX2-NEXT: jne .LBB16_27 +; AVX2-NEXT: .LBB16_11: # %else20 ; AVX2-NEXT: testl $2048, %eax # imm = 0x800 -; AVX2-NEXT: jne .LBB16_23 -; AVX2-NEXT: .LBB16_24: # %else22 +; AVX2-NEXT: jne .LBB16_28 +; AVX2-NEXT: .LBB16_12: # %else22 ; AVX2-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX2-NEXT: jne .LBB16_25 -; AVX2-NEXT: .LBB16_26: # %else24 +; AVX2-NEXT: jne .LBB16_29 +; AVX2-NEXT: .LBB16_13: # %else24 ; AVX2-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX2-NEXT: jne .LBB16_27 -; AVX2-NEXT: .LBB16_28: # %else26 +; AVX2-NEXT: jne .LBB16_30 +; AVX2-NEXT: .LBB16_14: # %else26 ; AVX2-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX2-NEXT: jne .LBB16_29 -; AVX2-NEXT: .LBB16_30: # %else28 -; AVX2-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX2-NEXT: jne .LBB16_31 -; AVX2-NEXT: .LBB16_32: # %else30 +; AVX2-NEXT: .LBB16_15: # %else28 +; AVX2-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX2-NEXT: jne .LBB16_32 +; AVX2-NEXT: .LBB16_16: # %else30 ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; AVX2-NEXT: .LBB16_1: # %cond.store +; AVX2-NEXT: .LBB16_17: # %cond.store ; AVX2-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX2-NEXT: testb $2, %al -; AVX2-NEXT: je .LBB16_4 -; AVX2-NEXT: .LBB16_3: # %cond.store1 +; AVX2-NEXT: je .LBB16_2 +; AVX2-NEXT: .LBB16_18: # %cond.store1 ; AVX2-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX2-NEXT: testb $4, %al -; AVX2-NEXT: je .LBB16_6 -; AVX2-NEXT: .LBB16_5: # %cond.store3 +; AVX2-NEXT: je .LBB16_3 +; AVX2-NEXT: .LBB16_19: # %cond.store3 ; AVX2-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX2-NEXT: testb $8, %al -; AVX2-NEXT: je .LBB16_8 -; AVX2-NEXT: .LBB16_7: # %cond.store5 +; AVX2-NEXT: je .LBB16_4 +; AVX2-NEXT: .LBB16_20: # %cond.store5 ; AVX2-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX2-NEXT: testb $16, %al -; AVX2-NEXT: je .LBB16_10 -; AVX2-NEXT: .LBB16_9: # %cond.store7 +; AVX2-NEXT: je .LBB16_5 +; AVX2-NEXT: .LBB16_21: # %cond.store7 ; AVX2-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX2-NEXT: testb $32, %al -; AVX2-NEXT: je .LBB16_12 -; AVX2-NEXT: .LBB16_11: # %cond.store9 +; AVX2-NEXT: je .LBB16_6 +; AVX2-NEXT: .LBB16_22: # %cond.store9 ; AVX2-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX2-NEXT: testb $64, %al -; AVX2-NEXT: je .LBB16_14 -; AVX2-NEXT: .LBB16_13: # %cond.store11 +; AVX2-NEXT: je .LBB16_7 +; AVX2-NEXT: .LBB16_23: # %cond.store11 ; AVX2-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX2-NEXT: testb %al, %al -; AVX2-NEXT: jns .LBB16_16 -; AVX2-NEXT: .LBB16_15: # %cond.store13 +; AVX2-NEXT: jns .LBB16_8 +; AVX2-NEXT: .LBB16_24: # %cond.store13 ; AVX2-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX2-NEXT: testl $256, %eax # imm = 0x100 -; AVX2-NEXT: je .LBB16_18 -; AVX2-NEXT: .LBB16_17: # %cond.store15 +; AVX2-NEXT: je .LBB16_9 +; AVX2-NEXT: .LBB16_25: # %cond.store15 ; AVX2-NEXT: vpextrb $8, %xmm0, 8(%rdi) ; AVX2-NEXT: testl $512, %eax # imm = 0x200 -; AVX2-NEXT: je .LBB16_20 -; AVX2-NEXT: .LBB16_19: # %cond.store17 +; AVX2-NEXT: je .LBB16_10 +; AVX2-NEXT: .LBB16_26: # %cond.store17 ; AVX2-NEXT: vpextrb $9, %xmm0, 9(%rdi) ; AVX2-NEXT: testl $1024, %eax # imm = 0x400 -; AVX2-NEXT: je .LBB16_22 -; AVX2-NEXT: .LBB16_21: # %cond.store19 +; AVX2-NEXT: je .LBB16_11 +; AVX2-NEXT: .LBB16_27: # %cond.store19 ; AVX2-NEXT: vpextrb $10, %xmm0, 10(%rdi) ; AVX2-NEXT: testl $2048, %eax # imm = 0x800 -; AVX2-NEXT: je .LBB16_24 -; AVX2-NEXT: .LBB16_23: # %cond.store21 +; AVX2-NEXT: je .LBB16_12 +; AVX2-NEXT: .LBB16_28: # %cond.store21 ; AVX2-NEXT: vpextrb $11, %xmm0, 11(%rdi) ; AVX2-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX2-NEXT: je .LBB16_26 -; AVX2-NEXT: .LBB16_25: # %cond.store23 +; AVX2-NEXT: je .LBB16_13 +; AVX2-NEXT: .LBB16_29: # %cond.store23 ; AVX2-NEXT: vpextrb $12, %xmm0, 12(%rdi) ; AVX2-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX2-NEXT: je .LBB16_28 -; AVX2-NEXT: .LBB16_27: # %cond.store25 +; AVX2-NEXT: je .LBB16_14 +; AVX2-NEXT: .LBB16_30: # %cond.store25 ; AVX2-NEXT: vpextrb $13, %xmm0, 13(%rdi) ; AVX2-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX2-NEXT: je .LBB16_30 -; AVX2-NEXT: .LBB16_29: # %cond.store27 +; AVX2-NEXT: je .LBB16_15 +; AVX2-NEXT: .LBB16_31: # %cond.store27 ; AVX2-NEXT: vpextrb $14, %xmm0, 14(%rdi) ; AVX2-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX2-NEXT: je .LBB16_32 -; AVX2-NEXT: .LBB16_31: # %cond.store29 +; AVX2-NEXT: je .LBB16_16 +; AVX2-NEXT: .LBB16_32: # %cond.store29 ; AVX2-NEXT: vpextrb $15, %xmm0, 15(%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq @@ -7693,116 +7693,116 @@ define void @truncstore_v16i16_v16i8(<16 x i16> %x, ptr %p, <16 x i8> %mask) { ; AVX512F-NEXT: vpmovmskb %xmm1, %eax ; AVX512F-NEXT: xorl $65535, %eax # imm = 0xFFFF ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB16_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB16_17 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB16_3 -; AVX512F-NEXT: .LBB16_4: # %else2 +; AVX512F-NEXT: jne .LBB16_18 +; AVX512F-NEXT: .LBB16_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB16_5 -; AVX512F-NEXT: .LBB16_6: # %else4 +; AVX512F-NEXT: jne .LBB16_19 +; AVX512F-NEXT: .LBB16_3: # %else4 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne .LBB16_7 -; AVX512F-NEXT: .LBB16_8: # %else6 +; AVX512F-NEXT: jne .LBB16_20 +; AVX512F-NEXT: .LBB16_4: # %else6 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne .LBB16_9 -; AVX512F-NEXT: .LBB16_10: # %else8 +; AVX512F-NEXT: jne .LBB16_21 +; AVX512F-NEXT: .LBB16_5: # %else8 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne .LBB16_11 -; AVX512F-NEXT: .LBB16_12: # %else10 +; AVX512F-NEXT: jne .LBB16_22 +; AVX512F-NEXT: .LBB16_6: # %else10 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne .LBB16_13 -; AVX512F-NEXT: .LBB16_14: # %else12 +; AVX512F-NEXT: jne .LBB16_23 +; AVX512F-NEXT: .LBB16_7: # %else12 ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: js .LBB16_15 -; AVX512F-NEXT: .LBB16_16: # %else14 +; AVX512F-NEXT: js .LBB16_24 +; AVX512F-NEXT: .LBB16_8: # %else14 ; AVX512F-NEXT: testl $256, %eax # imm = 0x100 -; AVX512F-NEXT: jne .LBB16_17 -; AVX512F-NEXT: .LBB16_18: # %else16 +; AVX512F-NEXT: jne .LBB16_25 +; AVX512F-NEXT: .LBB16_9: # %else16 ; AVX512F-NEXT: testl $512, %eax # imm = 0x200 -; AVX512F-NEXT: jne .LBB16_19 -; AVX512F-NEXT: .LBB16_20: # %else18 +; AVX512F-NEXT: jne .LBB16_26 +; AVX512F-NEXT: .LBB16_10: # %else18 ; AVX512F-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512F-NEXT: jne .LBB16_21 -; AVX512F-NEXT: .LBB16_22: # %else20 +; AVX512F-NEXT: jne .LBB16_27 +; AVX512F-NEXT: .LBB16_11: # %else20 ; AVX512F-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512F-NEXT: jne .LBB16_23 -; AVX512F-NEXT: .LBB16_24: # %else22 +; AVX512F-NEXT: jne .LBB16_28 +; AVX512F-NEXT: .LBB16_12: # %else22 ; AVX512F-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512F-NEXT: jne .LBB16_25 -; AVX512F-NEXT: .LBB16_26: # %else24 +; AVX512F-NEXT: jne .LBB16_29 +; AVX512F-NEXT: .LBB16_13: # %else24 ; AVX512F-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512F-NEXT: jne .LBB16_27 -; AVX512F-NEXT: .LBB16_28: # %else26 +; AVX512F-NEXT: jne .LBB16_30 +; AVX512F-NEXT: .LBB16_14: # %else26 ; AVX512F-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512F-NEXT: jne .LBB16_29 -; AVX512F-NEXT: .LBB16_30: # %else28 -; AVX512F-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX512F-NEXT: jne .LBB16_31 -; AVX512F-NEXT: .LBB16_32: # %else30 +; AVX512F-NEXT: .LBB16_15: # %else28 +; AVX512F-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX512F-NEXT: jne .LBB16_32 +; AVX512F-NEXT: .LBB16_16: # %else30 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB16_1: # %cond.store +; AVX512F-NEXT: .LBB16_17: # %cond.store ; AVX512F-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB16_4 -; AVX512F-NEXT: .LBB16_3: # %cond.store1 +; AVX512F-NEXT: je .LBB16_2 +; AVX512F-NEXT: .LBB16_18: # %cond.store1 ; AVX512F-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB16_6 -; AVX512F-NEXT: .LBB16_5: # %cond.store3 +; AVX512F-NEXT: je .LBB16_3 +; AVX512F-NEXT: .LBB16_19: # %cond.store3 ; AVX512F-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB16_8 -; AVX512F-NEXT: .LBB16_7: # %cond.store5 +; AVX512F-NEXT: je .LBB16_4 +; AVX512F-NEXT: .LBB16_20: # %cond.store5 ; AVX512F-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je .LBB16_10 -; AVX512F-NEXT: .LBB16_9: # %cond.store7 +; AVX512F-NEXT: je .LBB16_5 +; AVX512F-NEXT: .LBB16_21: # %cond.store7 ; AVX512F-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je .LBB16_12 -; AVX512F-NEXT: .LBB16_11: # %cond.store9 +; AVX512F-NEXT: je .LBB16_6 +; AVX512F-NEXT: .LBB16_22: # %cond.store9 ; AVX512F-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je .LBB16_14 -; AVX512F-NEXT: .LBB16_13: # %cond.store11 +; AVX512F-NEXT: je .LBB16_7 +; AVX512F-NEXT: .LBB16_23: # %cond.store11 ; AVX512F-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX512F-NEXT: testb %al, %al -; AVX512F-NEXT: jns .LBB16_16 -; AVX512F-NEXT: .LBB16_15: # %cond.store13 +; AVX512F-NEXT: jns .LBB16_8 +; AVX512F-NEXT: .LBB16_24: # %cond.store13 ; AVX512F-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX512F-NEXT: testl $256, %eax # imm = 0x100 -; AVX512F-NEXT: je .LBB16_18 -; AVX512F-NEXT: .LBB16_17: # %cond.store15 +; AVX512F-NEXT: je .LBB16_9 +; AVX512F-NEXT: .LBB16_25: # %cond.store15 ; AVX512F-NEXT: vpextrb $8, %xmm0, 8(%rdi) ; AVX512F-NEXT: testl $512, %eax # imm = 0x200 -; AVX512F-NEXT: je .LBB16_20 -; AVX512F-NEXT: .LBB16_19: # %cond.store17 +; AVX512F-NEXT: je .LBB16_10 +; AVX512F-NEXT: .LBB16_26: # %cond.store17 ; AVX512F-NEXT: vpextrb $9, %xmm0, 9(%rdi) ; AVX512F-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512F-NEXT: je .LBB16_22 -; AVX512F-NEXT: .LBB16_21: # %cond.store19 +; AVX512F-NEXT: je .LBB16_11 +; AVX512F-NEXT: .LBB16_27: # %cond.store19 ; AVX512F-NEXT: vpextrb $10, %xmm0, 10(%rdi) ; AVX512F-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512F-NEXT: je .LBB16_24 -; AVX512F-NEXT: .LBB16_23: # %cond.store21 +; AVX512F-NEXT: je .LBB16_12 +; AVX512F-NEXT: .LBB16_28: # %cond.store21 ; AVX512F-NEXT: vpextrb $11, %xmm0, 11(%rdi) ; AVX512F-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512F-NEXT: je .LBB16_26 -; AVX512F-NEXT: .LBB16_25: # %cond.store23 +; AVX512F-NEXT: je .LBB16_13 +; AVX512F-NEXT: .LBB16_29: # %cond.store23 ; AVX512F-NEXT: vpextrb $12, %xmm0, 12(%rdi) ; AVX512F-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512F-NEXT: je .LBB16_28 -; AVX512F-NEXT: .LBB16_27: # %cond.store25 +; AVX512F-NEXT: je .LBB16_14 +; AVX512F-NEXT: .LBB16_30: # %cond.store25 ; AVX512F-NEXT: vpextrb $13, %xmm0, 13(%rdi) ; AVX512F-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512F-NEXT: je .LBB16_30 -; AVX512F-NEXT: .LBB16_29: # %cond.store27 +; AVX512F-NEXT: je .LBB16_15 +; AVX512F-NEXT: .LBB16_31: # %cond.store27 ; AVX512F-NEXT: vpextrb $14, %xmm0, 14(%rdi) ; AVX512F-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX512F-NEXT: je .LBB16_32 -; AVX512F-NEXT: .LBB16_31: # %cond.store29 +; AVX512F-NEXT: je .LBB16_16 +; AVX512F-NEXT: .LBB16_32: # %cond.store29 ; AVX512F-NEXT: vpextrb $15, %xmm0, 15(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -7817,116 +7817,116 @@ define void @truncstore_v16i16_v16i8(<16 x i16> %x, ptr %p, <16 x i8> %mask) { ; AVX512FVL-NEXT: vpmovmskb %xmm1, %eax ; AVX512FVL-NEXT: xorl $65535, %eax # imm = 0xFFFF ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB16_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB16_17 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB16_3 -; AVX512FVL-NEXT: .LBB16_4: # %else2 +; AVX512FVL-NEXT: jne .LBB16_18 +; AVX512FVL-NEXT: .LBB16_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB16_5 -; AVX512FVL-NEXT: .LBB16_6: # %else4 +; AVX512FVL-NEXT: jne .LBB16_19 +; AVX512FVL-NEXT: .LBB16_3: # %else4 ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: jne .LBB16_7 -; AVX512FVL-NEXT: .LBB16_8: # %else6 +; AVX512FVL-NEXT: jne .LBB16_20 +; AVX512FVL-NEXT: .LBB16_4: # %else6 ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: jne .LBB16_9 -; AVX512FVL-NEXT: .LBB16_10: # %else8 +; AVX512FVL-NEXT: jne .LBB16_21 +; AVX512FVL-NEXT: .LBB16_5: # %else8 ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: jne .LBB16_11 -; AVX512FVL-NEXT: .LBB16_12: # %else10 +; AVX512FVL-NEXT: jne .LBB16_22 +; AVX512FVL-NEXT: .LBB16_6: # %else10 ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: jne .LBB16_13 -; AVX512FVL-NEXT: .LBB16_14: # %else12 +; AVX512FVL-NEXT: jne .LBB16_23 +; AVX512FVL-NEXT: .LBB16_7: # %else12 ; AVX512FVL-NEXT: testb %al, %al -; AVX512FVL-NEXT: js .LBB16_15 -; AVX512FVL-NEXT: .LBB16_16: # %else14 +; AVX512FVL-NEXT: js .LBB16_24 +; AVX512FVL-NEXT: .LBB16_8: # %else14 ; AVX512FVL-NEXT: testl $256, %eax # imm = 0x100 -; AVX512FVL-NEXT: jne .LBB16_17 -; AVX512FVL-NEXT: .LBB16_18: # %else16 +; AVX512FVL-NEXT: jne .LBB16_25 +; AVX512FVL-NEXT: .LBB16_9: # %else16 ; AVX512FVL-NEXT: testl $512, %eax # imm = 0x200 -; AVX512FVL-NEXT: jne .LBB16_19 -; AVX512FVL-NEXT: .LBB16_20: # %else18 +; AVX512FVL-NEXT: jne .LBB16_26 +; AVX512FVL-NEXT: .LBB16_10: # %else18 ; AVX512FVL-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512FVL-NEXT: jne .LBB16_21 -; AVX512FVL-NEXT: .LBB16_22: # %else20 +; AVX512FVL-NEXT: jne .LBB16_27 +; AVX512FVL-NEXT: .LBB16_11: # %else20 ; AVX512FVL-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512FVL-NEXT: jne .LBB16_23 -; AVX512FVL-NEXT: .LBB16_24: # %else22 +; AVX512FVL-NEXT: jne .LBB16_28 +; AVX512FVL-NEXT: .LBB16_12: # %else22 ; AVX512FVL-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512FVL-NEXT: jne .LBB16_25 -; AVX512FVL-NEXT: .LBB16_26: # %else24 +; AVX512FVL-NEXT: jne .LBB16_29 +; AVX512FVL-NEXT: .LBB16_13: # %else24 ; AVX512FVL-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512FVL-NEXT: jne .LBB16_27 -; AVX512FVL-NEXT: .LBB16_28: # %else26 +; AVX512FVL-NEXT: jne .LBB16_30 +; AVX512FVL-NEXT: .LBB16_14: # %else26 ; AVX512FVL-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512FVL-NEXT: jne .LBB16_29 -; AVX512FVL-NEXT: .LBB16_30: # %else28 -; AVX512FVL-NEXT: testl $32768, %eax # imm = 0x8000 ; AVX512FVL-NEXT: jne .LBB16_31 -; AVX512FVL-NEXT: .LBB16_32: # %else30 +; AVX512FVL-NEXT: .LBB16_15: # %else28 +; AVX512FVL-NEXT: testl $32768, %eax # imm = 0x8000 +; AVX512FVL-NEXT: jne .LBB16_32 +; AVX512FVL-NEXT: .LBB16_16: # %else30 ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB16_1: # %cond.store +; AVX512FVL-NEXT: .LBB16_17: # %cond.store ; AVX512FVL-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB16_4 -; AVX512FVL-NEXT: .LBB16_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB16_2 +; AVX512FVL-NEXT: .LBB16_18: # %cond.store1 ; AVX512FVL-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB16_6 -; AVX512FVL-NEXT: .LBB16_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB16_3 +; AVX512FVL-NEXT: .LBB16_19: # %cond.store3 ; AVX512FVL-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB16_8 -; AVX512FVL-NEXT: .LBB16_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB16_4 +; AVX512FVL-NEXT: .LBB16_20: # %cond.store5 ; AVX512FVL-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: je .LBB16_10 -; AVX512FVL-NEXT: .LBB16_9: # %cond.store7 +; AVX512FVL-NEXT: je .LBB16_5 +; AVX512FVL-NEXT: .LBB16_21: # %cond.store7 ; AVX512FVL-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: je .LBB16_12 -; AVX512FVL-NEXT: .LBB16_11: # %cond.store9 +; AVX512FVL-NEXT: je .LBB16_6 +; AVX512FVL-NEXT: .LBB16_22: # %cond.store9 ; AVX512FVL-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: je .LBB16_14 -; AVX512FVL-NEXT: .LBB16_13: # %cond.store11 +; AVX512FVL-NEXT: je .LBB16_7 +; AVX512FVL-NEXT: .LBB16_23: # %cond.store11 ; AVX512FVL-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX512FVL-NEXT: testb %al, %al -; AVX512FVL-NEXT: jns .LBB16_16 -; AVX512FVL-NEXT: .LBB16_15: # %cond.store13 +; AVX512FVL-NEXT: jns .LBB16_8 +; AVX512FVL-NEXT: .LBB16_24: # %cond.store13 ; AVX512FVL-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX512FVL-NEXT: testl $256, %eax # imm = 0x100 -; AVX512FVL-NEXT: je .LBB16_18 -; AVX512FVL-NEXT: .LBB16_17: # %cond.store15 +; AVX512FVL-NEXT: je .LBB16_9 +; AVX512FVL-NEXT: .LBB16_25: # %cond.store15 ; AVX512FVL-NEXT: vpextrb $8, %xmm0, 8(%rdi) ; AVX512FVL-NEXT: testl $512, %eax # imm = 0x200 -; AVX512FVL-NEXT: je .LBB16_20 -; AVX512FVL-NEXT: .LBB16_19: # %cond.store17 +; AVX512FVL-NEXT: je .LBB16_10 +; AVX512FVL-NEXT: .LBB16_26: # %cond.store17 ; AVX512FVL-NEXT: vpextrb $9, %xmm0, 9(%rdi) ; AVX512FVL-NEXT: testl $1024, %eax # imm = 0x400 -; AVX512FVL-NEXT: je .LBB16_22 -; AVX512FVL-NEXT: .LBB16_21: # %cond.store19 +; AVX512FVL-NEXT: je .LBB16_11 +; AVX512FVL-NEXT: .LBB16_27: # %cond.store19 ; AVX512FVL-NEXT: vpextrb $10, %xmm0, 10(%rdi) ; AVX512FVL-NEXT: testl $2048, %eax # imm = 0x800 -; AVX512FVL-NEXT: je .LBB16_24 -; AVX512FVL-NEXT: .LBB16_23: # %cond.store21 +; AVX512FVL-NEXT: je .LBB16_12 +; AVX512FVL-NEXT: .LBB16_28: # %cond.store21 ; AVX512FVL-NEXT: vpextrb $11, %xmm0, 11(%rdi) ; AVX512FVL-NEXT: testl $4096, %eax # imm = 0x1000 -; AVX512FVL-NEXT: je .LBB16_26 -; AVX512FVL-NEXT: .LBB16_25: # %cond.store23 +; AVX512FVL-NEXT: je .LBB16_13 +; AVX512FVL-NEXT: .LBB16_29: # %cond.store23 ; AVX512FVL-NEXT: vpextrb $12, %xmm0, 12(%rdi) ; AVX512FVL-NEXT: testl $8192, %eax # imm = 0x2000 -; AVX512FVL-NEXT: je .LBB16_28 -; AVX512FVL-NEXT: .LBB16_27: # %cond.store25 +; AVX512FVL-NEXT: je .LBB16_14 +; AVX512FVL-NEXT: .LBB16_30: # %cond.store25 ; AVX512FVL-NEXT: vpextrb $13, %xmm0, 13(%rdi) ; AVX512FVL-NEXT: testl $16384, %eax # imm = 0x4000 -; AVX512FVL-NEXT: je .LBB16_30 -; AVX512FVL-NEXT: .LBB16_29: # %cond.store27 +; AVX512FVL-NEXT: je .LBB16_15 +; AVX512FVL-NEXT: .LBB16_31: # %cond.store27 ; AVX512FVL-NEXT: vpextrb $14, %xmm0, 14(%rdi) ; AVX512FVL-NEXT: testl $32768, %eax # imm = 0x8000 -; AVX512FVL-NEXT: je .LBB16_32 -; AVX512FVL-NEXT: .LBB16_31: # %cond.store29 +; AVX512FVL-NEXT: je .LBB16_16 +; AVX512FVL-NEXT: .LBB16_32: # %cond.store29 ; AVX512FVL-NEXT: vpextrb $15, %xmm0, 15(%rdi) ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq @@ -7970,59 +7970,59 @@ define void @truncstore_v8i16_v8i8(<8 x i16> %x, ptr %p, <8 x i16> %mask) { ; SSE2-NEXT: notl %eax ; SSE2-NEXT: testb $1, %al ; SSE2-NEXT: movd %xmm0, %ecx -; SSE2-NEXT: jne .LBB17_1 -; SSE2-NEXT: # %bb.2: # %else +; SSE2-NEXT: jne .LBB17_12 +; SSE2-NEXT: # %bb.1: # %else ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: jne .LBB17_3 -; SSE2-NEXT: .LBB17_4: # %else2 +; SSE2-NEXT: jne .LBB17_13 +; SSE2-NEXT: .LBB17_2: # %else2 ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: jne .LBB17_5 -; SSE2-NEXT: .LBB17_6: # %else4 +; SSE2-NEXT: jne .LBB17_14 +; SSE2-NEXT: .LBB17_3: # %else4 ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: je .LBB17_8 -; SSE2-NEXT: .LBB17_7: # %cond.store5 +; SSE2-NEXT: je .LBB17_5 +; SSE2-NEXT: .LBB17_4: # %cond.store5 ; SSE2-NEXT: shrl $24, %ecx ; SSE2-NEXT: movb %cl, 3(%rdi) -; SSE2-NEXT: .LBB17_8: # %else6 +; SSE2-NEXT: .LBB17_5: # %else6 ; SSE2-NEXT: testb $16, %al ; SSE2-NEXT: pextrw $2, %xmm0, %ecx -; SSE2-NEXT: je .LBB17_10 -; SSE2-NEXT: # %bb.9: # %cond.store7 +; SSE2-NEXT: je .LBB17_7 +; SSE2-NEXT: # %bb.6: # %cond.store7 ; SSE2-NEXT: movb %cl, 4(%rdi) -; SSE2-NEXT: .LBB17_10: # %else8 +; SSE2-NEXT: .LBB17_7: # %else8 ; SSE2-NEXT: testb $32, %al -; SSE2-NEXT: je .LBB17_12 -; SSE2-NEXT: # %bb.11: # %cond.store9 +; SSE2-NEXT: je .LBB17_9 +; SSE2-NEXT: # %bb.8: # %cond.store9 ; SSE2-NEXT: movb %ch, 5(%rdi) -; SSE2-NEXT: .LBB17_12: # %else10 +; SSE2-NEXT: .LBB17_9: # %else10 ; SSE2-NEXT: testb $64, %al ; SSE2-NEXT: pextrw $3, %xmm0, %ecx -; SSE2-NEXT: jne .LBB17_13 -; SSE2-NEXT: # %bb.14: # %else12 -; SSE2-NEXT: testb $-128, %al ; SSE2-NEXT: jne .LBB17_15 -; SSE2-NEXT: .LBB17_16: # %else14 +; SSE2-NEXT: # %bb.10: # %else12 +; SSE2-NEXT: testb $-128, %al +; SSE2-NEXT: jne .LBB17_16 +; SSE2-NEXT: .LBB17_11: # %else14 ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB17_1: # %cond.store +; SSE2-NEXT: .LBB17_12: # %cond.store ; SSE2-NEXT: movb %cl, (%rdi) ; SSE2-NEXT: testb $2, %al -; SSE2-NEXT: je .LBB17_4 -; SSE2-NEXT: .LBB17_3: # %cond.store1 +; SSE2-NEXT: je .LBB17_2 +; SSE2-NEXT: .LBB17_13: # %cond.store1 ; SSE2-NEXT: movb %ch, 1(%rdi) ; SSE2-NEXT: testb $4, %al -; SSE2-NEXT: je .LBB17_6 -; SSE2-NEXT: .LBB17_5: # %cond.store3 +; SSE2-NEXT: je .LBB17_3 +; SSE2-NEXT: .LBB17_14: # %cond.store3 ; SSE2-NEXT: movl %ecx, %edx ; SSE2-NEXT: shrl $16, %edx ; SSE2-NEXT: movb %dl, 2(%rdi) ; SSE2-NEXT: testb $8, %al -; SSE2-NEXT: jne .LBB17_7 -; SSE2-NEXT: jmp .LBB17_8 -; SSE2-NEXT: .LBB17_13: # %cond.store11 +; SSE2-NEXT: jne .LBB17_4 +; SSE2-NEXT: jmp .LBB17_5 +; SSE2-NEXT: .LBB17_15: # %cond.store11 ; SSE2-NEXT: movb %cl, 6(%rdi) ; SSE2-NEXT: testb $-128, %al -; SSE2-NEXT: je .LBB17_16 -; SSE2-NEXT: .LBB17_15: # %cond.store13 +; SSE2-NEXT: je .LBB17_11 +; SSE2-NEXT: .LBB17_16: # %cond.store13 ; SSE2-NEXT: movb %ch, 7(%rdi) ; SSE2-NEXT: retq ; @@ -8036,59 +8036,59 @@ define void @truncstore_v8i16_v8i8(<8 x i16> %x, ptr %p, <8 x i16> %mask) { ; SSE4-NEXT: pmovmskb %xmm2, %eax ; SSE4-NEXT: notl %eax ; SSE4-NEXT: testb $1, %al -; SSE4-NEXT: jne .LBB17_1 -; SSE4-NEXT: # %bb.2: # %else +; SSE4-NEXT: jne .LBB17_9 +; SSE4-NEXT: # %bb.1: # %else ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: jne .LBB17_3 -; SSE4-NEXT: .LBB17_4: # %else2 +; SSE4-NEXT: jne .LBB17_10 +; SSE4-NEXT: .LBB17_2: # %else2 ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: jne .LBB17_5 -; SSE4-NEXT: .LBB17_6: # %else4 +; SSE4-NEXT: jne .LBB17_11 +; SSE4-NEXT: .LBB17_3: # %else4 ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: jne .LBB17_7 -; SSE4-NEXT: .LBB17_8: # %else6 +; SSE4-NEXT: jne .LBB17_12 +; SSE4-NEXT: .LBB17_4: # %else6 ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: jne .LBB17_9 -; SSE4-NEXT: .LBB17_10: # %else8 +; SSE4-NEXT: jne .LBB17_13 +; SSE4-NEXT: .LBB17_5: # %else8 ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: jne .LBB17_11 -; SSE4-NEXT: .LBB17_12: # %else10 +; SSE4-NEXT: jne .LBB17_14 +; SSE4-NEXT: .LBB17_6: # %else10 ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: jne .LBB17_13 -; SSE4-NEXT: .LBB17_14: # %else12 -; SSE4-NEXT: testb $-128, %al ; SSE4-NEXT: jne .LBB17_15 -; SSE4-NEXT: .LBB17_16: # %else14 +; SSE4-NEXT: .LBB17_7: # %else12 +; SSE4-NEXT: testb $-128, %al +; SSE4-NEXT: jne .LBB17_16 +; SSE4-NEXT: .LBB17_8: # %else14 ; SSE4-NEXT: retq -; SSE4-NEXT: .LBB17_1: # %cond.store +; SSE4-NEXT: .LBB17_9: # %cond.store ; SSE4-NEXT: pextrb $0, %xmm0, (%rdi) ; SSE4-NEXT: testb $2, %al -; SSE4-NEXT: je .LBB17_4 -; SSE4-NEXT: .LBB17_3: # %cond.store1 +; SSE4-NEXT: je .LBB17_2 +; SSE4-NEXT: .LBB17_10: # %cond.store1 ; SSE4-NEXT: pextrb $1, %xmm0, 1(%rdi) ; SSE4-NEXT: testb $4, %al -; SSE4-NEXT: je .LBB17_6 -; SSE4-NEXT: .LBB17_5: # %cond.store3 +; SSE4-NEXT: je .LBB17_3 +; SSE4-NEXT: .LBB17_11: # %cond.store3 ; SSE4-NEXT: pextrb $2, %xmm0, 2(%rdi) ; SSE4-NEXT: testb $8, %al -; SSE4-NEXT: je .LBB17_8 -; SSE4-NEXT: .LBB17_7: # %cond.store5 +; SSE4-NEXT: je .LBB17_4 +; SSE4-NEXT: .LBB17_12: # %cond.store5 ; SSE4-NEXT: pextrb $3, %xmm0, 3(%rdi) ; SSE4-NEXT: testb $16, %al -; SSE4-NEXT: je .LBB17_10 -; SSE4-NEXT: .LBB17_9: # %cond.store7 +; SSE4-NEXT: je .LBB17_5 +; SSE4-NEXT: .LBB17_13: # %cond.store7 ; SSE4-NEXT: pextrb $4, %xmm0, 4(%rdi) ; SSE4-NEXT: testb $32, %al -; SSE4-NEXT: je .LBB17_12 -; SSE4-NEXT: .LBB17_11: # %cond.store9 +; SSE4-NEXT: je .LBB17_6 +; SSE4-NEXT: .LBB17_14: # %cond.store9 ; SSE4-NEXT: pextrb $5, %xmm0, 5(%rdi) ; SSE4-NEXT: testb $64, %al -; SSE4-NEXT: je .LBB17_14 -; SSE4-NEXT: .LBB17_13: # %cond.store11 +; SSE4-NEXT: je .LBB17_7 +; SSE4-NEXT: .LBB17_15: # %cond.store11 ; SSE4-NEXT: pextrb $6, %xmm0, 6(%rdi) ; SSE4-NEXT: testb $-128, %al -; SSE4-NEXT: je .LBB17_16 -; SSE4-NEXT: .LBB17_15: # %cond.store13 +; SSE4-NEXT: je .LBB17_8 +; SSE4-NEXT: .LBB17_16: # %cond.store13 ; SSE4-NEXT: pextrb $7, %xmm0, 7(%rdi) ; SSE4-NEXT: retq ; @@ -8102,59 +8102,59 @@ define void @truncstore_v8i16_v8i8(<8 x i16> %x, ptr %p, <8 x i16> %mask) { ; AVX-NEXT: vpmovmskb %xmm1, %eax ; AVX-NEXT: notl %eax ; AVX-NEXT: testb $1, %al -; AVX-NEXT: jne .LBB17_1 -; AVX-NEXT: # %bb.2: # %else +; AVX-NEXT: jne .LBB17_9 +; AVX-NEXT: # %bb.1: # %else ; AVX-NEXT: testb $2, %al -; AVX-NEXT: jne .LBB17_3 -; AVX-NEXT: .LBB17_4: # %else2 +; AVX-NEXT: jne .LBB17_10 +; AVX-NEXT: .LBB17_2: # %else2 ; AVX-NEXT: testb $4, %al -; AVX-NEXT: jne .LBB17_5 -; AVX-NEXT: .LBB17_6: # %else4 +; AVX-NEXT: jne .LBB17_11 +; AVX-NEXT: .LBB17_3: # %else4 ; AVX-NEXT: testb $8, %al -; AVX-NEXT: jne .LBB17_7 -; AVX-NEXT: .LBB17_8: # %else6 +; AVX-NEXT: jne .LBB17_12 +; AVX-NEXT: .LBB17_4: # %else6 ; AVX-NEXT: testb $16, %al -; AVX-NEXT: jne .LBB17_9 -; AVX-NEXT: .LBB17_10: # %else8 +; AVX-NEXT: jne .LBB17_13 +; AVX-NEXT: .LBB17_5: # %else8 ; AVX-NEXT: testb $32, %al -; AVX-NEXT: jne .LBB17_11 -; AVX-NEXT: .LBB17_12: # %else10 +; AVX-NEXT: jne .LBB17_14 +; AVX-NEXT: .LBB17_6: # %else10 ; AVX-NEXT: testb $64, %al -; AVX-NEXT: jne .LBB17_13 -; AVX-NEXT: .LBB17_14: # %else12 -; AVX-NEXT: testb $-128, %al ; AVX-NEXT: jne .LBB17_15 -; AVX-NEXT: .LBB17_16: # %else14 +; AVX-NEXT: .LBB17_7: # %else12 +; AVX-NEXT: testb $-128, %al +; AVX-NEXT: jne .LBB17_16 +; AVX-NEXT: .LBB17_8: # %else14 ; AVX-NEXT: retq -; AVX-NEXT: .LBB17_1: # %cond.store +; AVX-NEXT: .LBB17_9: # %cond.store ; AVX-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX-NEXT: testb $2, %al -; AVX-NEXT: je .LBB17_4 -; AVX-NEXT: .LBB17_3: # %cond.store1 +; AVX-NEXT: je .LBB17_2 +; AVX-NEXT: .LBB17_10: # %cond.store1 ; AVX-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX-NEXT: testb $4, %al -; AVX-NEXT: je .LBB17_6 -; AVX-NEXT: .LBB17_5: # %cond.store3 +; AVX-NEXT: je .LBB17_3 +; AVX-NEXT: .LBB17_11: # %cond.store3 ; AVX-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX-NEXT: testb $8, %al -; AVX-NEXT: je .LBB17_8 -; AVX-NEXT: .LBB17_7: # %cond.store5 +; AVX-NEXT: je .LBB17_4 +; AVX-NEXT: .LBB17_12: # %cond.store5 ; AVX-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX-NEXT: testb $16, %al -; AVX-NEXT: je .LBB17_10 -; AVX-NEXT: .LBB17_9: # %cond.store7 +; AVX-NEXT: je .LBB17_5 +; AVX-NEXT: .LBB17_13: # %cond.store7 ; AVX-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX-NEXT: testb $32, %al -; AVX-NEXT: je .LBB17_12 -; AVX-NEXT: .LBB17_11: # %cond.store9 +; AVX-NEXT: je .LBB17_6 +; AVX-NEXT: .LBB17_14: # %cond.store9 ; AVX-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX-NEXT: testb $64, %al -; AVX-NEXT: je .LBB17_14 -; AVX-NEXT: .LBB17_13: # %cond.store11 +; AVX-NEXT: je .LBB17_7 +; AVX-NEXT: .LBB17_15: # %cond.store11 ; AVX-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX-NEXT: testb $-128, %al -; AVX-NEXT: je .LBB17_16 -; AVX-NEXT: .LBB17_15: # %cond.store13 +; AVX-NEXT: je .LBB17_8 +; AVX-NEXT: .LBB17_16: # %cond.store13 ; AVX-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX-NEXT: retq ; @@ -8169,60 +8169,60 @@ define void @truncstore_v8i16_v8i8(<8 x i16> %x, ptr %p, <8 x i16> %mask) { ; AVX512F-NEXT: vpackuswb %xmm0, %xmm0, %xmm0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: testb $1, %al -; AVX512F-NEXT: jne .LBB17_1 -; AVX512F-NEXT: # %bb.2: # %else +; AVX512F-NEXT: jne .LBB17_9 +; AVX512F-NEXT: # %bb.1: # %else ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: jne .LBB17_3 -; AVX512F-NEXT: .LBB17_4: # %else2 +; AVX512F-NEXT: jne .LBB17_10 +; AVX512F-NEXT: .LBB17_2: # %else2 ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: jne .LBB17_5 -; AVX512F-NEXT: .LBB17_6: # %else4 +; AVX512F-NEXT: jne .LBB17_11 +; AVX512F-NEXT: .LBB17_3: # %else4 ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: jne .LBB17_7 -; AVX512F-NEXT: .LBB17_8: # %else6 +; AVX512F-NEXT: jne .LBB17_12 +; AVX512F-NEXT: .LBB17_4: # %else6 ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: jne .LBB17_9 -; AVX512F-NEXT: .LBB17_10: # %else8 +; AVX512F-NEXT: jne .LBB17_13 +; AVX512F-NEXT: .LBB17_5: # %else8 ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: jne .LBB17_11 -; AVX512F-NEXT: .LBB17_12: # %else10 +; AVX512F-NEXT: jne .LBB17_14 +; AVX512F-NEXT: .LBB17_6: # %else10 ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: jne .LBB17_13 -; AVX512F-NEXT: .LBB17_14: # %else12 -; AVX512F-NEXT: testb $-128, %al ; AVX512F-NEXT: jne .LBB17_15 -; AVX512F-NEXT: .LBB17_16: # %else14 +; AVX512F-NEXT: .LBB17_7: # %else12 +; AVX512F-NEXT: testb $-128, %al +; AVX512F-NEXT: jne .LBB17_16 +; AVX512F-NEXT: .LBB17_8: # %else14 ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq -; AVX512F-NEXT: .LBB17_1: # %cond.store +; AVX512F-NEXT: .LBB17_9: # %cond.store ; AVX512F-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512F-NEXT: testb $2, %al -; AVX512F-NEXT: je .LBB17_4 -; AVX512F-NEXT: .LBB17_3: # %cond.store1 +; AVX512F-NEXT: je .LBB17_2 +; AVX512F-NEXT: .LBB17_10: # %cond.store1 ; AVX512F-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512F-NEXT: testb $4, %al -; AVX512F-NEXT: je .LBB17_6 -; AVX512F-NEXT: .LBB17_5: # %cond.store3 +; AVX512F-NEXT: je .LBB17_3 +; AVX512F-NEXT: .LBB17_11: # %cond.store3 ; AVX512F-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512F-NEXT: testb $8, %al -; AVX512F-NEXT: je .LBB17_8 -; AVX512F-NEXT: .LBB17_7: # %cond.store5 +; AVX512F-NEXT: je .LBB17_4 +; AVX512F-NEXT: .LBB17_12: # %cond.store5 ; AVX512F-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512F-NEXT: testb $16, %al -; AVX512F-NEXT: je .LBB17_10 -; AVX512F-NEXT: .LBB17_9: # %cond.store7 +; AVX512F-NEXT: je .LBB17_5 +; AVX512F-NEXT: .LBB17_13: # %cond.store7 ; AVX512F-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX512F-NEXT: testb $32, %al -; AVX512F-NEXT: je .LBB17_12 -; AVX512F-NEXT: .LBB17_11: # %cond.store9 +; AVX512F-NEXT: je .LBB17_6 +; AVX512F-NEXT: .LBB17_14: # %cond.store9 ; AVX512F-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX512F-NEXT: testb $64, %al -; AVX512F-NEXT: je .LBB17_14 -; AVX512F-NEXT: .LBB17_13: # %cond.store11 +; AVX512F-NEXT: je .LBB17_7 +; AVX512F-NEXT: .LBB17_15: # %cond.store11 ; AVX512F-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX512F-NEXT: testb $-128, %al -; AVX512F-NEXT: je .LBB17_16 -; AVX512F-NEXT: .LBB17_15: # %cond.store13 +; AVX512F-NEXT: je .LBB17_8 +; AVX512F-NEXT: .LBB17_16: # %cond.store13 ; AVX512F-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: retq @@ -8238,60 +8238,60 @@ define void @truncstore_v8i16_v8i8(<8 x i16> %x, ptr %p, <8 x i16> %mask) { ; AVX512FVL-NEXT: vpackuswb %xmm0, %xmm0, %xmm0 ; AVX512FVL-NEXT: kmovw %k0, %eax ; AVX512FVL-NEXT: testb $1, %al -; AVX512FVL-NEXT: jne .LBB17_1 -; AVX512FVL-NEXT: # %bb.2: # %else +; AVX512FVL-NEXT: jne .LBB17_9 +; AVX512FVL-NEXT: # %bb.1: # %else ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: jne .LBB17_3 -; AVX512FVL-NEXT: .LBB17_4: # %else2 +; AVX512FVL-NEXT: jne .LBB17_10 +; AVX512FVL-NEXT: .LBB17_2: # %else2 ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: jne .LBB17_5 -; AVX512FVL-NEXT: .LBB17_6: # %else4 +; AVX512FVL-NEXT: jne .LBB17_11 +; AVX512FVL-NEXT: .LBB17_3: # %else4 ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: jne .LBB17_7 -; AVX512FVL-NEXT: .LBB17_8: # %else6 +; AVX512FVL-NEXT: jne .LBB17_12 +; AVX512FVL-NEXT: .LBB17_4: # %else6 ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: jne .LBB17_9 -; AVX512FVL-NEXT: .LBB17_10: # %else8 +; AVX512FVL-NEXT: jne .LBB17_13 +; AVX512FVL-NEXT: .LBB17_5: # %else8 ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: jne .LBB17_11 -; AVX512FVL-NEXT: .LBB17_12: # %else10 +; AVX512FVL-NEXT: jne .LBB17_14 +; AVX512FVL-NEXT: .LBB17_6: # %else10 ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: jne .LBB17_13 -; AVX512FVL-NEXT: .LBB17_14: # %else12 -; AVX512FVL-NEXT: testb $-128, %al ; AVX512FVL-NEXT: jne .LBB17_15 -; AVX512FVL-NEXT: .LBB17_16: # %else14 +; AVX512FVL-NEXT: .LBB17_7: # %else12 +; AVX512FVL-NEXT: testb $-128, %al +; AVX512FVL-NEXT: jne .LBB17_16 +; AVX512FVL-NEXT: .LBB17_8: # %else14 ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq -; AVX512FVL-NEXT: .LBB17_1: # %cond.store +; AVX512FVL-NEXT: .LBB17_9: # %cond.store ; AVX512FVL-NEXT: vpextrb $0, %xmm0, (%rdi) ; AVX512FVL-NEXT: testb $2, %al -; AVX512FVL-NEXT: je .LBB17_4 -; AVX512FVL-NEXT: .LBB17_3: # %cond.store1 +; AVX512FVL-NEXT: je .LBB17_2 +; AVX512FVL-NEXT: .LBB17_10: # %cond.store1 ; AVX512FVL-NEXT: vpextrb $1, %xmm0, 1(%rdi) ; AVX512FVL-NEXT: testb $4, %al -; AVX512FVL-NEXT: je .LBB17_6 -; AVX512FVL-NEXT: .LBB17_5: # %cond.store3 +; AVX512FVL-NEXT: je .LBB17_3 +; AVX512FVL-NEXT: .LBB17_11: # %cond.store3 ; AVX512FVL-NEXT: vpextrb $2, %xmm0, 2(%rdi) ; AVX512FVL-NEXT: testb $8, %al -; AVX512FVL-NEXT: je .LBB17_8 -; AVX512FVL-NEXT: .LBB17_7: # %cond.store5 +; AVX512FVL-NEXT: je .LBB17_4 +; AVX512FVL-NEXT: .LBB17_12: # %cond.store5 ; AVX512FVL-NEXT: vpextrb $3, %xmm0, 3(%rdi) ; AVX512FVL-NEXT: testb $16, %al -; AVX512FVL-NEXT: je .LBB17_10 -; AVX512FVL-NEXT: .LBB17_9: # %cond.store7 +; AVX512FVL-NEXT: je .LBB17_5 +; AVX512FVL-NEXT: .LBB17_13: # %cond.store7 ; AVX512FVL-NEXT: vpextrb $4, %xmm0, 4(%rdi) ; AVX512FVL-NEXT: testb $32, %al -; AVX512FVL-NEXT: je .LBB17_12 -; AVX512FVL-NEXT: .LBB17_11: # %cond.store9 +; AVX512FVL-NEXT: je .LBB17_6 +; AVX512FVL-NEXT: .LBB17_14: # %cond.store9 ; AVX512FVL-NEXT: vpextrb $5, %xmm0, 5(%rdi) ; AVX512FVL-NEXT: testb $64, %al -; AVX512FVL-NEXT: je .LBB17_14 -; AVX512FVL-NEXT: .LBB17_13: # %cond.store11 +; AVX512FVL-NEXT: je .LBB17_7 +; AVX512FVL-NEXT: .LBB17_15: # %cond.store11 ; AVX512FVL-NEXT: vpextrb $6, %xmm0, 6(%rdi) ; AVX512FVL-NEXT: testb $-128, %al -; AVX512FVL-NEXT: je .LBB17_16 -; AVX512FVL-NEXT: .LBB17_15: # %cond.store13 +; AVX512FVL-NEXT: je .LBB17_8 +; AVX512FVL-NEXT: .LBB17_16: # %cond.store13 ; AVX512FVL-NEXT: vpextrb $7, %xmm0, 7(%rdi) ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq diff --git a/llvm/test/CodeGen/X86/memcmp-more-load-pairs-x32.ll b/llvm/test/CodeGen/X86/memcmp-more-load-pairs-x32.ll index 7d1422d3c961e..5520a45acd83c 100644 --- a/llvm/test/CodeGen/X86/memcmp-more-load-pairs-x32.ll +++ b/llvm/test/CodeGen/X86/memcmp-more-load-pairs-x32.ll @@ -151,14 +151,14 @@ define i32 @length3(ptr %X, ptr %Y) nounwind { ; X86-NEXT: rolw $8, %dx ; X86-NEXT: rolw $8, %si ; X86-NEXT: cmpw %si, %dx -; X86-NEXT: jne .LBB9_3 +; X86-NEXT: jne .LBB9_2 ; X86-NEXT: # %bb.1: # %loadbb1 ; X86-NEXT: movzbl 2(%eax), %eax ; X86-NEXT: movzbl 2(%ecx), %ecx ; X86-NEXT: subl %ecx, %eax ; X86-NEXT: popl %esi ; X86-NEXT: retl -; X86-NEXT: .LBB9_3: # %res_block +; X86-NEXT: .LBB9_2: # %res_block ; X86-NEXT: setae %al ; X86-NEXT: movzbl %al, %eax ; X86-NEXT: leal -1(%eax,%eax), %eax @@ -275,14 +275,14 @@ define i32 @length5(ptr %X, ptr %Y) nounwind { ; X86-NEXT: bswapl %edx ; X86-NEXT: bswapl %esi ; X86-NEXT: cmpl %esi, %edx -; X86-NEXT: jne .LBB16_3 +; X86-NEXT: jne .LBB16_2 ; X86-NEXT: # %bb.1: # %loadbb1 ; X86-NEXT: movzbl 4(%eax), %eax ; X86-NEXT: movzbl 4(%ecx), %ecx ; X86-NEXT: subl %ecx, %eax ; X86-NEXT: popl %esi ; X86-NEXT: retl -; X86-NEXT: .LBB16_3: # %res_block +; X86-NEXT: .LBB16_2: # %res_block ; X86-NEXT: setae %al ; X86-NEXT: movzbl %al, %eax ; X86-NEXT: leal -1(%eax,%eax), %eax @@ -321,17 +321,17 @@ define i1 @length5_lt(ptr %X, ptr %Y) nounwind { ; X86-NEXT: bswapl %edx ; X86-NEXT: bswapl %esi ; X86-NEXT: cmpl %esi, %edx -; X86-NEXT: jne .LBB18_3 +; X86-NEXT: jne .LBB18_2 ; X86-NEXT: # %bb.1: # %loadbb1 ; X86-NEXT: movzbl 4(%eax), %eax ; X86-NEXT: movzbl 4(%ecx), %ecx ; X86-NEXT: subl %ecx, %eax -; X86-NEXT: jmp .LBB18_2 -; X86-NEXT: .LBB18_3: # %res_block +; X86-NEXT: jmp .LBB18_3 +; X86-NEXT: .LBB18_2: # %res_block ; X86-NEXT: setae %al ; X86-NEXT: movzbl %al, %eax ; X86-NEXT: leal -1(%eax,%eax), %eax -; X86-NEXT: .LBB18_2: # %endblock +; X86-NEXT: .LBB18_3: # %endblock ; X86-NEXT: shrl $31, %eax ; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: popl %esi diff --git a/llvm/test/CodeGen/X86/memcmp-more-load-pairs.ll b/llvm/test/CodeGen/X86/memcmp-more-load-pairs.ll index 3a3824a4ffe83..d3f48efca4cb7 100644 --- a/llvm/test/CodeGen/X86/memcmp-more-load-pairs.ll +++ b/llvm/test/CodeGen/X86/memcmp-more-load-pairs.ll @@ -144,13 +144,13 @@ define i32 @length3(ptr %X, ptr %Y) nounwind { ; X64-NEXT: rolw $8, %ax ; X64-NEXT: rolw $8, %cx ; X64-NEXT: cmpw %cx, %ax -; X64-NEXT: jne .LBB9_3 +; X64-NEXT: jne .LBB9_2 ; X64-NEXT: # %bb.1: # %loadbb1 ; X64-NEXT: movzbl 2(%rdi), %eax ; X64-NEXT: movzbl 2(%rsi), %ecx ; X64-NEXT: subl %ecx, %eax ; X64-NEXT: retq -; X64-NEXT: .LBB9_3: # %res_block +; X64-NEXT: .LBB9_2: # %res_block ; X64-NEXT: setae %al ; X64-NEXT: movzbl %al, %eax ; X64-NEXT: leal -1(%rax,%rax), %eax @@ -252,13 +252,13 @@ define i32 @length5(ptr %X, ptr %Y) nounwind { ; X64-NEXT: bswapl %eax ; X64-NEXT: bswapl %ecx ; X64-NEXT: cmpl %ecx, %eax -; X64-NEXT: jne .LBB16_3 +; X64-NEXT: jne .LBB16_2 ; X64-NEXT: # %bb.1: # %loadbb1 ; X64-NEXT: movzbl 4(%rdi), %eax ; X64-NEXT: movzbl 4(%rsi), %ecx ; X64-NEXT: subl %ecx, %eax ; X64-NEXT: retq -; X64-NEXT: .LBB16_3: # %res_block +; X64-NEXT: .LBB16_2: # %res_block ; X64-NEXT: setae %al ; X64-NEXT: movzbl %al, %eax ; X64-NEXT: leal -1(%rax,%rax), %eax @@ -291,7 +291,7 @@ define i1 @length5_lt(ptr %X, ptr %Y) nounwind { ; X64-NEXT: bswapl %eax ; X64-NEXT: bswapl %ecx ; X64-NEXT: cmpl %ecx, %eax -; X64-NEXT: jne .LBB18_3 +; X64-NEXT: jne .LBB18_2 ; X64-NEXT: # %bb.1: # %loadbb1 ; X64-NEXT: movzbl 4(%rdi), %eax ; X64-NEXT: movzbl 4(%rsi), %ecx @@ -299,7 +299,7 @@ define i1 @length5_lt(ptr %X, ptr %Y) nounwind { ; X64-NEXT: shrl $31, %eax ; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq -; X64-NEXT: .LBB18_3: # %res_block +; X64-NEXT: .LBB18_2: # %res_block ; X64-NEXT: setae %al ; X64-NEXT: movzbl %al, %eax ; X64-NEXT: leal -1(%rax,%rax), %eax diff --git a/llvm/test/CodeGen/X86/memcmp-optsize-x32.ll b/llvm/test/CodeGen/X86/memcmp-optsize-x32.ll index 09f02c3f56346..e0f4ef047b722 100644 --- a/llvm/test/CodeGen/X86/memcmp-optsize-x32.ll +++ b/llvm/test/CodeGen/X86/memcmp-optsize-x32.ll @@ -80,17 +80,17 @@ define i32 @length3(ptr %X, ptr %Y) nounwind optsize { ; X86-NEXT: rolw $8, %dx ; X86-NEXT: rolw $8, %si ; X86-NEXT: cmpw %si, %dx -; X86-NEXT: jne .LBB4_3 +; X86-NEXT: jne .LBB4_2 ; X86-NEXT: # %bb.1: # %loadbb1 ; X86-NEXT: movzbl 2(%eax), %eax ; X86-NEXT: movzbl 2(%ecx), %ecx ; X86-NEXT: subl %ecx, %eax -; X86-NEXT: jmp .LBB4_2 -; X86-NEXT: .LBB4_3: # %res_block +; X86-NEXT: jmp .LBB4_3 +; X86-NEXT: .LBB4_2: # %res_block ; X86-NEXT: setae %al ; X86-NEXT: movzbl %al, %eax ; X86-NEXT: leal -1(%eax,%eax), %eax -; X86-NEXT: .LBB4_2: # %endblock +; X86-NEXT: .LBB4_3: # %endblock ; X86-NEXT: popl %esi ; X86-NEXT: retl %m = tail call i32 @memcmp(ptr %X, ptr %Y, i32 3) nounwind @@ -170,17 +170,17 @@ define i32 @length5(ptr %X, ptr %Y) nounwind optsize { ; X86-NEXT: bswapl %edx ; X86-NEXT: bswapl %esi ; X86-NEXT: cmpl %esi, %edx -; X86-NEXT: jne .LBB9_3 +; X86-NEXT: jne .LBB9_2 ; X86-NEXT: # %bb.1: # %loadbb1 ; X86-NEXT: movzbl 4(%eax), %eax ; X86-NEXT: movzbl 4(%ecx), %ecx ; X86-NEXT: subl %ecx, %eax -; X86-NEXT: jmp .LBB9_2 -; X86-NEXT: .LBB9_3: # %res_block +; X86-NEXT: jmp .LBB9_3 +; X86-NEXT: .LBB9_2: # %res_block ; X86-NEXT: setae %al ; X86-NEXT: movzbl %al, %eax ; X86-NEXT: leal -1(%eax,%eax), %eax -; X86-NEXT: .LBB9_2: # %endblock +; X86-NEXT: .LBB9_3: # %endblock ; X86-NEXT: popl %esi ; X86-NEXT: retl %m = tail call i32 @memcmp(ptr %X, ptr %Y, i32 5) nounwind diff --git a/llvm/test/CodeGen/X86/memcmp-optsize.ll b/llvm/test/CodeGen/X86/memcmp-optsize.ll index 4fe67fa0883de..d95f99d492794 100644 --- a/llvm/test/CodeGen/X86/memcmp-optsize.ll +++ b/llvm/test/CodeGen/X86/memcmp-optsize.ll @@ -72,13 +72,13 @@ define i32 @length3(ptr %X, ptr %Y) nounwind optsize { ; X64-NEXT: rolw $8, %ax ; X64-NEXT: rolw $8, %cx ; X64-NEXT: cmpw %cx, %ax -; X64-NEXT: jne .LBB4_3 +; X64-NEXT: jne .LBB4_2 ; X64-NEXT: # %bb.1: # %loadbb1 ; X64-NEXT: movzbl 2(%rdi), %eax ; X64-NEXT: movzbl 2(%rsi), %ecx ; X64-NEXT: subl %ecx, %eax ; X64-NEXT: retq -; X64-NEXT: .LBB4_3: # %res_block +; X64-NEXT: .LBB4_2: # %res_block ; X64-NEXT: setae %al ; X64-NEXT: movzbl %al, %eax ; X64-NEXT: leal -1(%rax,%rax), %eax @@ -150,13 +150,13 @@ define i32 @length5(ptr %X, ptr %Y) nounwind optsize { ; X64-NEXT: bswapl %eax ; X64-NEXT: bswapl %ecx ; X64-NEXT: cmpl %ecx, %eax -; X64-NEXT: jne .LBB9_3 +; X64-NEXT: jne .LBB9_2 ; X64-NEXT: # %bb.1: # %loadbb1 ; X64-NEXT: movzbl 4(%rdi), %eax ; X64-NEXT: movzbl 4(%rsi), %ecx ; X64-NEXT: subl %ecx, %eax ; X64-NEXT: retq -; X64-NEXT: .LBB9_3: # %res_block +; X64-NEXT: .LBB9_2: # %res_block ; X64-NEXT: setae %al ; X64-NEXT: movzbl %al, %eax ; X64-NEXT: leal -1(%rax,%rax), %eax diff --git a/llvm/test/CodeGen/X86/memcmp-pgso-x32.ll b/llvm/test/CodeGen/X86/memcmp-pgso-x32.ll index 1b3fd6d4ddd3b..1808b91f7be1e 100644 --- a/llvm/test/CodeGen/X86/memcmp-pgso-x32.ll +++ b/llvm/test/CodeGen/X86/memcmp-pgso-x32.ll @@ -80,17 +80,17 @@ define i32 @length3(ptr %X, ptr %Y) nounwind !prof !14 { ; X86-NEXT: rolw $8, %dx ; X86-NEXT: rolw $8, %si ; X86-NEXT: cmpw %si, %dx -; X86-NEXT: jne .LBB4_3 +; X86-NEXT: jne .LBB4_2 ; X86-NEXT: # %bb.1: # %loadbb1 ; X86-NEXT: movzbl 2(%eax), %eax ; X86-NEXT: movzbl 2(%ecx), %ecx ; X86-NEXT: subl %ecx, %eax -; X86-NEXT: jmp .LBB4_2 -; X86-NEXT: .LBB4_3: # %res_block +; X86-NEXT: jmp .LBB4_3 +; X86-NEXT: .LBB4_2: # %res_block ; X86-NEXT: setae %al ; X86-NEXT: movzbl %al, %eax ; X86-NEXT: leal -1(%eax,%eax), %eax -; X86-NEXT: .LBB4_2: # %endblock +; X86-NEXT: .LBB4_3: # %endblock ; X86-NEXT: popl %esi ; X86-NEXT: retl %m = tail call i32 @memcmp(ptr %X, ptr %Y, i32 3) nounwind @@ -170,17 +170,17 @@ define i32 @length5(ptr %X, ptr %Y) nounwind !prof !14 { ; X86-NEXT: bswapl %edx ; X86-NEXT: bswapl %esi ; X86-NEXT: cmpl %esi, %edx -; X86-NEXT: jne .LBB9_3 +; X86-NEXT: jne .LBB9_2 ; X86-NEXT: # %bb.1: # %loadbb1 ; X86-NEXT: movzbl 4(%eax), %eax ; X86-NEXT: movzbl 4(%ecx), %ecx ; X86-NEXT: subl %ecx, %eax -; X86-NEXT: jmp .LBB9_2 -; X86-NEXT: .LBB9_3: # %res_block +; X86-NEXT: jmp .LBB9_3 +; X86-NEXT: .LBB9_2: # %res_block ; X86-NEXT: setae %al ; X86-NEXT: movzbl %al, %eax ; X86-NEXT: leal -1(%eax,%eax), %eax -; X86-NEXT: .LBB9_2: # %endblock +; X86-NEXT: .LBB9_3: # %endblock ; X86-NEXT: popl %esi ; X86-NEXT: retl %m = tail call i32 @memcmp(ptr %X, ptr %Y, i32 5) nounwind diff --git a/llvm/test/CodeGen/X86/memcmp-pgso.ll b/llvm/test/CodeGen/X86/memcmp-pgso.ll index 26ee94afbce88..790620cfd47ac 100644 --- a/llvm/test/CodeGen/X86/memcmp-pgso.ll +++ b/llvm/test/CodeGen/X86/memcmp-pgso.ll @@ -72,13 +72,13 @@ define i32 @length3(ptr %X, ptr %Y) nounwind !prof !14 { ; X64-NEXT: rolw $8, %ax ; X64-NEXT: rolw $8, %cx ; X64-NEXT: cmpw %cx, %ax -; X64-NEXT: jne .LBB4_3 +; X64-NEXT: jne .LBB4_2 ; X64-NEXT: # %bb.1: # %loadbb1 ; X64-NEXT: movzbl 2(%rdi), %eax ; X64-NEXT: movzbl 2(%rsi), %ecx ; X64-NEXT: subl %ecx, %eax ; X64-NEXT: retq -; X64-NEXT: .LBB4_3: # %res_block +; X64-NEXT: .LBB4_2: # %res_block ; X64-NEXT: setae %al ; X64-NEXT: movzbl %al, %eax ; X64-NEXT: leal -1(%rax,%rax), %eax @@ -150,13 +150,13 @@ define i32 @length5(ptr %X, ptr %Y) nounwind !prof !14 { ; X64-NEXT: bswapl %eax ; X64-NEXT: bswapl %ecx ; X64-NEXT: cmpl %ecx, %eax -; X64-NEXT: jne .LBB9_3 +; X64-NEXT: jne .LBB9_2 ; X64-NEXT: # %bb.1: # %loadbb1 ; X64-NEXT: movzbl 4(%rdi), %eax ; X64-NEXT: movzbl 4(%rsi), %ecx ; X64-NEXT: subl %ecx, %eax ; X64-NEXT: retq -; X64-NEXT: .LBB9_3: # %res_block +; X64-NEXT: .LBB9_2: # %res_block ; X64-NEXT: setae %al ; X64-NEXT: movzbl %al, %eax ; X64-NEXT: leal -1(%rax,%rax), %eax diff --git a/llvm/test/CodeGen/X86/memcmp-x32.ll b/llvm/test/CodeGen/X86/memcmp-x32.ll index 28e732be9191d..e4a2bbd11dc0b 100644 --- a/llvm/test/CodeGen/X86/memcmp-x32.ll +++ b/llvm/test/CodeGen/X86/memcmp-x32.ll @@ -179,14 +179,14 @@ define i32 @length3(ptr %X, ptr %Y) nounwind { ; X86-NEXT: rolw $8, %dx ; X86-NEXT: rolw $8, %si ; X86-NEXT: cmpw %si, %dx -; X86-NEXT: jne .LBB11_3 +; X86-NEXT: jne .LBB11_2 ; X86-NEXT: # %bb.1: # %loadbb1 ; X86-NEXT: movzbl 2(%eax), %eax ; X86-NEXT: movzbl 2(%ecx), %ecx ; X86-NEXT: subl %ecx, %eax ; X86-NEXT: popl %esi ; X86-NEXT: retl -; X86-NEXT: .LBB11_3: # %res_block +; X86-NEXT: .LBB11_2: # %res_block ; X86-NEXT: setae %al ; X86-NEXT: movzbl %al, %eax ; X86-NEXT: leal -1(%eax,%eax), %eax @@ -303,14 +303,14 @@ define i32 @length5(ptr %X, ptr %Y) nounwind { ; X86-NEXT: bswapl %edx ; X86-NEXT: bswapl %esi ; X86-NEXT: cmpl %esi, %edx -; X86-NEXT: jne .LBB18_3 +; X86-NEXT: jne .LBB18_2 ; X86-NEXT: # %bb.1: # %loadbb1 ; X86-NEXT: movzbl 4(%eax), %eax ; X86-NEXT: movzbl 4(%ecx), %ecx ; X86-NEXT: subl %ecx, %eax ; X86-NEXT: popl %esi ; X86-NEXT: retl -; X86-NEXT: .LBB18_3: # %res_block +; X86-NEXT: .LBB18_2: # %res_block ; X86-NEXT: setae %al ; X86-NEXT: movzbl %al, %eax ; X86-NEXT: leal -1(%eax,%eax), %eax @@ -349,17 +349,17 @@ define i1 @length5_lt(ptr %X, ptr %Y) nounwind { ; X86-NEXT: bswapl %edx ; X86-NEXT: bswapl %esi ; X86-NEXT: cmpl %esi, %edx -; X86-NEXT: jne .LBB20_3 +; X86-NEXT: jne .LBB20_2 ; X86-NEXT: # %bb.1: # %loadbb1 ; X86-NEXT: movzbl 4(%eax), %eax ; X86-NEXT: movzbl 4(%ecx), %ecx ; X86-NEXT: subl %ecx, %eax -; X86-NEXT: jmp .LBB20_2 -; X86-NEXT: .LBB20_3: # %res_block +; X86-NEXT: jmp .LBB20_3 +; X86-NEXT: .LBB20_2: # %res_block ; X86-NEXT: setae %al ; X86-NEXT: movzbl %al, %eax ; X86-NEXT: leal -1(%eax,%eax), %eax -; X86-NEXT: .LBB20_2: # %endblock +; X86-NEXT: .LBB20_3: # %endblock ; X86-NEXT: shrl $31, %eax ; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: popl %esi diff --git a/llvm/test/CodeGen/X86/memcmp.ll b/llvm/test/CodeGen/X86/memcmp.ll index 9e713bfa6c392..6a7d4324082b4 100644 --- a/llvm/test/CodeGen/X86/memcmp.ll +++ b/llvm/test/CodeGen/X86/memcmp.ll @@ -170,13 +170,13 @@ define i32 @length3(ptr %X, ptr %Y) nounwind { ; X64-NEXT: rolw $8, %ax ; X64-NEXT: rolw $8, %cx ; X64-NEXT: cmpw %cx, %ax -; X64-NEXT: jne .LBB11_3 +; X64-NEXT: jne .LBB11_2 ; X64-NEXT: # %bb.1: # %loadbb1 ; X64-NEXT: movzbl 2(%rdi), %eax ; X64-NEXT: movzbl 2(%rsi), %ecx ; X64-NEXT: subl %ecx, %eax ; X64-NEXT: retq -; X64-NEXT: .LBB11_3: # %res_block +; X64-NEXT: .LBB11_2: # %res_block ; X64-NEXT: setae %al ; X64-NEXT: movzbl %al, %eax ; X64-NEXT: leal -1(%rax,%rax), %eax @@ -308,13 +308,13 @@ define i32 @length5(ptr %X, ptr %Y) nounwind { ; X64-NEXT: bswapl %eax ; X64-NEXT: bswapl %ecx ; X64-NEXT: cmpl %ecx, %eax -; X64-NEXT: jne .LBB20_3 +; X64-NEXT: jne .LBB20_2 ; X64-NEXT: # %bb.1: # %loadbb1 ; X64-NEXT: movzbl 4(%rdi), %eax ; X64-NEXT: movzbl 4(%rsi), %ecx ; X64-NEXT: subl %ecx, %eax ; X64-NEXT: retq -; X64-NEXT: .LBB20_3: # %res_block +; X64-NEXT: .LBB20_2: # %res_block ; X64-NEXT: setae %al ; X64-NEXT: movzbl %al, %eax ; X64-NEXT: leal -1(%rax,%rax), %eax @@ -347,7 +347,7 @@ define i1 @length5_lt(ptr %X, ptr %Y) nounwind { ; X64-NEXT: bswapl %eax ; X64-NEXT: bswapl %ecx ; X64-NEXT: cmpl %ecx, %eax -; X64-NEXT: jne .LBB22_3 +; X64-NEXT: jne .LBB22_2 ; X64-NEXT: # %bb.1: # %loadbb1 ; X64-NEXT: movzbl 4(%rdi), %eax ; X64-NEXT: movzbl 4(%rsi), %ecx @@ -355,7 +355,7 @@ define i1 @length5_lt(ptr %X, ptr %Y) nounwind { ; X64-NEXT: shrl $31, %eax ; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq -; X64-NEXT: .LBB22_3: # %res_block +; X64-NEXT: .LBB22_2: # %res_block ; X64-NEXT: setae %al ; X64-NEXT: movzbl %al, %eax ; X64-NEXT: leal -1(%rax,%rax), %eax diff --git a/llvm/test/CodeGen/X86/mmx-arith.ll b/llvm/test/CodeGen/X86/mmx-arith.ll index 8f97d2652bc53..56817b5048acd 100644 --- a/llvm/test/CodeGen/X86/mmx-arith.ll +++ b/llvm/test/CodeGen/X86/mmx-arith.ll @@ -405,12 +405,12 @@ define <1 x i64> @test3(ptr %a, ptr %b, i32 %count) nounwind { ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: xorl %eax, %eax ; X86-NEXT: testl %ecx, %ecx -; X86-NEXT: je .LBB3_1 -; X86-NEXT: # %bb.2: # %bb26.preheader +; X86-NEXT: je .LBB3_3 +; X86-NEXT: # %bb.1: # %bb26.preheader ; X86-NEXT: xorl %ebx, %ebx ; X86-NEXT: xorl %edx, %edx ; X86-NEXT: .p2align 4 -; X86-NEXT: .LBB3_3: # %bb26 +; X86-NEXT: .LBB3_2: # %bb26 ; X86-NEXT: # =>This Inner Loop Header: Depth=1 ; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-NEXT: movl (%edi,%ebx,8), %ebp @@ -424,9 +424,9 @@ define <1 x i64> @test3(ptr %a, ptr %b, i32 %count) nounwind { ; X86-NEXT: movl %esi, %ecx ; X86-NEXT: incl %ebx ; X86-NEXT: cmpl %esi, %ebx -; X86-NEXT: jb .LBB3_3 +; X86-NEXT: jb .LBB3_2 ; X86-NEXT: jmp .LBB3_4 -; X86-NEXT: .LBB3_1: +; X86-NEXT: .LBB3_3: ; X86-NEXT: xorl %edx, %edx ; X86-NEXT: .LBB3_4: # %bb31 ; X86-NEXT: popl %esi diff --git a/llvm/test/CodeGen/X86/mmx-coalescing.ll b/llvm/test/CodeGen/X86/mmx-coalescing.ll index 589f5af4bb4d6..e5eac5b339499 100644 --- a/llvm/test/CodeGen/X86/mmx-coalescing.ll +++ b/llvm/test/CodeGen/X86/mmx-coalescing.ll @@ -12,12 +12,12 @@ define i32 @test(ptr %pSA, ptr %A, i32 %B, i32 %C, i32 %D, ptr %E) { ; CHECK-NEXT: pshufw $238, (%rdi), %mm0 # mm0 = mem[2,3,2,3] ; CHECK-NEXT: movd %mm0, %eax ; CHECK-NEXT: testl %eax, %eax -; CHECK-NEXT: je .LBB0_1 -; CHECK-NEXT: # %bb.2: # %if.B +; CHECK-NEXT: je .LBB0_2 +; CHECK-NEXT: # %bb.1: # %if.B ; CHECK-NEXT: pshufw $238, %mm0, %mm0 # mm0 = mm0[2,3,2,3] ; CHECK-NEXT: movq %mm0, %rax ; CHECK-NEXT: jmp .LBB0_3 -; CHECK-NEXT: .LBB0_1: # %if.A +; CHECK-NEXT: .LBB0_2: # %if.A ; CHECK-NEXT: movd %edx, %mm1 ; CHECK-NEXT: psllq %mm1, %mm0 ; CHECK-NEXT: movq %mm0, %rax @@ -25,7 +25,7 @@ define i32 @test(ptr %pSA, ptr %A, i32 %B, i32 %C, i32 %D, ptr %E) { ; CHECK-NEXT: jne .LBB0_4 ; CHECK-NEXT: .LBB0_3: # %if.C ; CHECK-NEXT: testl %eax, %eax -; CHECK-NEXT: je .LBB0_1 +; CHECK-NEXT: je .LBB0_2 ; CHECK-NEXT: .LBB0_4: # %merge ; CHECK-NEXT: pshufw $238, %mm0, %mm0 # mm0 = mm0[2,3,2,3] ; CHECK-NEXT: movd %mm0, %eax diff --git a/llvm/test/CodeGen/X86/mul-constant-result.ll b/llvm/test/CodeGen/X86/mul-constant-result.ll index 1f9e7a93ad0b9..e8a2e062d7ac8 100644 --- a/llvm/test/CodeGen/X86/mul-constant-result.ll +++ b/llvm/test/CodeGen/X86/mul-constant-result.ll @@ -28,7 +28,7 @@ define i32 @mult(i32, i32) local_unnamed_addr #0 { ; X86-NEXT: .LBB0_4: ; X86-NEXT: decl %ecx ; X86-NEXT: cmpl $31, %ecx -; X86-NEXT: ja .LBB0_35 +; X86-NEXT: ja .LBB0_31 ; X86-NEXT: # %bb.5: ; X86-NEXT: jmpl *.LJTI0_0(,%ecx,4) ; X86-NEXT: .LBB0_6: @@ -40,149 +40,149 @@ define i32 @mult(i32, i32) local_unnamed_addr #0 { ; X86-NEXT: .cfi_def_cfa_offset 8 ; X86-NEXT: leal (%eax,%eax,8), %ecx ; X86-NEXT: leal (%ecx,%ecx,2), %ecx -; X86-NEXT: jmp .LBB0_9 +; X86-NEXT: jmp .LBB0_39 ; X86-NEXT: .LBB0_8: ; X86-NEXT: movl %eax, %ecx ; X86-NEXT: shll $4, %ecx -; X86-NEXT: jmp .LBB0_9 -; X86-NEXT: .LBB0_10: +; X86-NEXT: jmp .LBB0_39 +; X86-NEXT: .LBB0_9: ; X86-NEXT: leal (%eax,%eax,4), %eax -; X86-NEXT: jmp .LBB0_18 -; X86-NEXT: .LBB0_11: +; X86-NEXT: jmp .LBB0_43 +; X86-NEXT: .LBB0_10: ; X86-NEXT: shll $2, %eax -; X86-NEXT: jmp .LBB0_18 -; X86-NEXT: .LBB0_13: +; X86-NEXT: jmp .LBB0_43 +; X86-NEXT: .LBB0_11: ; X86-NEXT: leal (%eax,%eax,2), %ecx -; X86-NEXT: jmp .LBB0_14 -; X86-NEXT: .LBB0_15: +; X86-NEXT: jmp .LBB0_22 +; X86-NEXT: .LBB0_12: ; X86-NEXT: addl %eax, %eax -; X86-NEXT: jmp .LBB0_12 -; X86-NEXT: .LBB0_16: +; X86-NEXT: jmp .LBB0_36 +; X86-NEXT: .LBB0_13: ; X86-NEXT: leal (%eax,%eax,4), %ecx ; X86-NEXT: leal (%ecx,%ecx,4), %ecx -; X86-NEXT: jmp .LBB0_9 -; X86-NEXT: .LBB0_17: +; X86-NEXT: jmp .LBB0_39 +; X86-NEXT: .LBB0_14: ; X86-NEXT: leal (%eax,%eax,4), %eax -; X86-NEXT: jmp .LBB0_12 -; X86-NEXT: .LBB0_19: +; X86-NEXT: jmp .LBB0_36 +; X86-NEXT: .LBB0_15: ; X86-NEXT: shll $4, %eax ; X86-NEXT: popl %esi ; X86-NEXT: .cfi_def_cfa_offset 4 ; X86-NEXT: retl -; X86-NEXT: .LBB0_20: +; X86-NEXT: .LBB0_16: ; X86-NEXT: .cfi_def_cfa_offset 8 ; X86-NEXT: shll $2, %eax ; X86-NEXT: popl %esi ; X86-NEXT: .cfi_def_cfa_offset 4 ; X86-NEXT: retl -; X86-NEXT: .LBB0_21: +; X86-NEXT: .LBB0_17: ; X86-NEXT: .cfi_def_cfa_offset 8 ; X86-NEXT: shll $3, %eax ; X86-NEXT: popl %esi ; X86-NEXT: .cfi_def_cfa_offset 4 ; X86-NEXT: retl -; X86-NEXT: .LBB0_22: +; X86-NEXT: .LBB0_18: ; X86-NEXT: .cfi_def_cfa_offset 8 ; X86-NEXT: shll $5, %eax ; X86-NEXT: popl %esi ; X86-NEXT: .cfi_def_cfa_offset 4 ; X86-NEXT: retl -; X86-NEXT: .LBB0_23: +; X86-NEXT: .LBB0_19: ; X86-NEXT: .cfi_def_cfa_offset 8 ; X86-NEXT: addl %eax, %eax -; X86-NEXT: .LBB0_33: +; X86-NEXT: .LBB0_20: ; X86-NEXT: leal (%eax,%eax,8), %eax ; X86-NEXT: popl %esi ; X86-NEXT: .cfi_def_cfa_offset 4 ; X86-NEXT: retl -; X86-NEXT: .LBB0_24: +; X86-NEXT: .LBB0_21: ; X86-NEXT: .cfi_def_cfa_offset 8 ; X86-NEXT: leal (%eax,%eax,4), %ecx -; X86-NEXT: .LBB0_14: +; X86-NEXT: .LBB0_22: ; X86-NEXT: leal (%eax,%ecx,4), %eax ; X86-NEXT: popl %esi ; X86-NEXT: .cfi_def_cfa_offset 4 ; X86-NEXT: retl -; X86-NEXT: .LBB0_25: +; X86-NEXT: .LBB0_23: ; X86-NEXT: .cfi_def_cfa_offset 8 ; X86-NEXT: addl %eax, %eax -; X86-NEXT: jmp .LBB0_18 -; X86-NEXT: .LBB0_26: +; X86-NEXT: jmp .LBB0_43 +; X86-NEXT: .LBB0_24: ; X86-NEXT: leal (%eax,%eax,4), %ecx ; X86-NEXT: leal (%eax,%ecx,4), %ecx -; X86-NEXT: jmp .LBB0_9 -; X86-NEXT: .LBB0_27: +; X86-NEXT: jmp .LBB0_39 +; X86-NEXT: .LBB0_25: ; X86-NEXT: leal (%eax,%eax), %ecx ; X86-NEXT: shll $4, %eax -; X86-NEXT: jmp .LBB0_28 -; X86-NEXT: .LBB0_29: +; X86-NEXT: jmp .LBB0_41 +; X86-NEXT: .LBB0_26: ; X86-NEXT: leal (,%eax,8), %ecx -; X86-NEXT: jmp .LBB0_38 -; X86-NEXT: .LBB0_30: +; X86-NEXT: jmp .LBB0_34 +; X86-NEXT: .LBB0_27: ; X86-NEXT: leal (%eax,%eax,8), %ecx -; X86-NEXT: jmp .LBB0_32 -; X86-NEXT: .LBB0_31: +; X86-NEXT: jmp .LBB0_29 +; X86-NEXT: .LBB0_28: ; X86-NEXT: leal (%eax,%eax,4), %ecx -; X86-NEXT: .LBB0_32: +; X86-NEXT: .LBB0_29: ; X86-NEXT: leal (%eax,%ecx,2), %eax ; X86-NEXT: popl %esi ; X86-NEXT: .cfi_def_cfa_offset 4 ; X86-NEXT: retl -; X86-NEXT: .LBB0_34: +; X86-NEXT: .LBB0_30: ; X86-NEXT: .cfi_def_cfa_offset 8 ; X86-NEXT: movl %eax, %ecx ; X86-NEXT: shll $5, %ecx -; X86-NEXT: jmp .LBB0_38 -; X86-NEXT: .LBB0_35: +; X86-NEXT: jmp .LBB0_34 +; X86-NEXT: .LBB0_31: ; X86-NEXT: xorl %eax, %eax -; X86-NEXT: .LBB0_36: +; X86-NEXT: .LBB0_32: ; X86-NEXT: popl %esi ; X86-NEXT: .cfi_def_cfa_offset 4 ; X86-NEXT: retl -; X86-NEXT: .LBB0_37: +; X86-NEXT: .LBB0_33: ; X86-NEXT: .cfi_def_cfa_offset 8 ; X86-NEXT: leal (%eax,%eax,2), %ecx ; X86-NEXT: shll $3, %ecx -; X86-NEXT: .LBB0_38: +; X86-NEXT: .LBB0_34: ; X86-NEXT: subl %eax, %ecx ; X86-NEXT: movl %ecx, %eax ; X86-NEXT: popl %esi ; X86-NEXT: .cfi_def_cfa_offset 4 ; X86-NEXT: retl -; X86-NEXT: .LBB0_39: +; X86-NEXT: .LBB0_35: ; X86-NEXT: .cfi_def_cfa_offset 8 ; X86-NEXT: shll $2, %eax -; X86-NEXT: .LBB0_12: +; X86-NEXT: .LBB0_36: ; X86-NEXT: leal (%eax,%eax,4), %eax ; X86-NEXT: popl %esi ; X86-NEXT: .cfi_def_cfa_offset 4 ; X86-NEXT: retl -; X86-NEXT: .LBB0_40: +; X86-NEXT: .LBB0_37: ; X86-NEXT: .cfi_def_cfa_offset 8 ; X86-NEXT: shll $3, %eax -; X86-NEXT: jmp .LBB0_18 -; X86-NEXT: .LBB0_41: +; X86-NEXT: jmp .LBB0_43 +; X86-NEXT: .LBB0_38: ; X86-NEXT: leal (%eax,%eax,8), %ecx ; X86-NEXT: leal (%ecx,%ecx,2), %ecx ; X86-NEXT: addl %eax, %eax -; X86-NEXT: .LBB0_9: +; X86-NEXT: .LBB0_39: ; X86-NEXT: addl %ecx, %eax ; X86-NEXT: popl %esi ; X86-NEXT: .cfi_def_cfa_offset 4 ; X86-NEXT: retl -; X86-NEXT: .LBB0_42: +; X86-NEXT: .LBB0_40: ; X86-NEXT: .cfi_def_cfa_offset 8 ; X86-NEXT: leal (%eax,%eax), %ecx ; X86-NEXT: shll $5, %eax -; X86-NEXT: .LBB0_28: +; X86-NEXT: .LBB0_41: ; X86-NEXT: subl %ecx, %eax ; X86-NEXT: popl %esi ; X86-NEXT: .cfi_def_cfa_offset 4 ; X86-NEXT: retl -; X86-NEXT: .LBB0_43: +; X86-NEXT: .LBB0_42: ; X86-NEXT: .cfi_def_cfa_offset 8 ; X86-NEXT: leal (%eax,%eax,8), %eax -; X86-NEXT: .LBB0_18: +; X86-NEXT: .LBB0_43: ; X86-NEXT: leal (%eax,%eax,2), %eax ; X86-NEXT: popl %esi ; X86-NEXT: .cfi_def_cfa_offset 4 @@ -199,7 +199,7 @@ define i32 @mult(i32, i32) local_unnamed_addr #0 { ; X64-HSW-NEXT: cmovel %ecx, %eax ; X64-HSW-NEXT: decl %edi ; X64-HSW-NEXT: cmpl $31, %edi -; X64-HSW-NEXT: ja .LBB0_31 +; X64-HSW-NEXT: ja .LBB0_28 ; X64-HSW-NEXT: # %bb.1: ; X64-HSW-NEXT: jmpq *.LJTI0_0(,%rdi,8) ; X64-HSW-NEXT: .LBB0_2: @@ -216,11 +216,11 @@ define i32 @mult(i32, i32) local_unnamed_addr #0 { ; X64-HSW-NEXT: jmp .LBB0_22 ; X64-HSW-NEXT: .LBB0_5: ; X64-HSW-NEXT: leal (%rax,%rax,4), %eax -; X64-HSW-NEXT: .LBB0_13: +; X64-HSW-NEXT: .LBB0_6: ; X64-HSW-NEXT: leal (%rax,%rax,2), %eax ; X64-HSW-NEXT: # kill: def $eax killed $eax killed $rax ; X64-HSW-NEXT: retq -; X64-HSW-NEXT: .LBB0_6: +; X64-HSW-NEXT: .LBB0_7: ; X64-HSW-NEXT: shll $2, %eax ; X64-HSW-NEXT: leal (%rax,%rax,2), %eax ; X64-HSW-NEXT: # kill: def $eax killed $eax killed $rax @@ -230,9 +230,9 @@ define i32 @mult(i32, i32) local_unnamed_addr #0 { ; X64-HSW-NEXT: leal (%rax,%rcx,4), %eax ; X64-HSW-NEXT: # kill: def $eax killed $eax killed $rax ; X64-HSW-NEXT: retq -; X64-HSW-NEXT: .LBB0_10: +; X64-HSW-NEXT: .LBB0_9: ; X64-HSW-NEXT: addl %eax, %eax -; X64-HSW-NEXT: .LBB0_7: +; X64-HSW-NEXT: .LBB0_10: ; X64-HSW-NEXT: leal (%rax,%rax,4), %eax ; X64-HSW-NEXT: # kill: def $eax killed $eax killed $rax ; X64-HSW-NEXT: retq @@ -245,25 +245,25 @@ define i32 @mult(i32, i32) local_unnamed_addr #0 { ; X64-HSW-NEXT: leal (%rax,%rax,4), %eax ; X64-HSW-NEXT: # kill: def $eax killed $eax killed $rax ; X64-HSW-NEXT: retq -; X64-HSW-NEXT: .LBB0_14: +; X64-HSW-NEXT: .LBB0_13: ; X64-HSW-NEXT: shll $4, %eax ; X64-HSW-NEXT: # kill: def $eax killed $eax killed $rax ; X64-HSW-NEXT: retq -; X64-HSW-NEXT: .LBB0_15: +; X64-HSW-NEXT: .LBB0_14: ; X64-HSW-NEXT: shll $2, %eax ; X64-HSW-NEXT: # kill: def $eax killed $eax killed $rax ; X64-HSW-NEXT: retq -; X64-HSW-NEXT: .LBB0_16: +; X64-HSW-NEXT: .LBB0_15: ; X64-HSW-NEXT: shll $3, %eax ; X64-HSW-NEXT: # kill: def $eax killed $eax killed $rax ; X64-HSW-NEXT: retq -; X64-HSW-NEXT: .LBB0_17: +; X64-HSW-NEXT: .LBB0_16: ; X64-HSW-NEXT: shll $5, %eax ; X64-HSW-NEXT: # kill: def $eax killed $eax killed $rax ; X64-HSW-NEXT: retq -; X64-HSW-NEXT: .LBB0_18: +; X64-HSW-NEXT: .LBB0_17: ; X64-HSW-NEXT: addl %eax, %eax -; X64-HSW-NEXT: .LBB0_29: +; X64-HSW-NEXT: .LBB0_18: ; X64-HSW-NEXT: leal (%rax,%rax,8), %eax ; X64-HSW-NEXT: # kill: def $eax killed $eax killed $rax ; X64-HSW-NEXT: retq @@ -291,60 +291,60 @@ define i32 @mult(i32, i32) local_unnamed_addr #0 { ; X64-HSW-NEXT: subl %ecx, %eax ; X64-HSW-NEXT: # kill: def $eax killed $eax killed $rax ; X64-HSW-NEXT: retq -; X64-HSW-NEXT: .LBB0_25: +; X64-HSW-NEXT: .LBB0_24: ; X64-HSW-NEXT: leal (,%rax,8), %ecx -; X64-HSW-NEXT: jmp .LBB0_34 -; X64-HSW-NEXT: .LBB0_26: +; X64-HSW-NEXT: jmp .LBB0_31 +; X64-HSW-NEXT: .LBB0_25: ; X64-HSW-NEXT: leal (%rax,%rax,8), %ecx ; X64-HSW-NEXT: leal (%rax,%rcx,2), %eax ; X64-HSW-NEXT: # kill: def $eax killed $eax killed $rax ; X64-HSW-NEXT: retq -; X64-HSW-NEXT: .LBB0_27: +; X64-HSW-NEXT: .LBB0_26: ; X64-HSW-NEXT: leal (%rax,%rax,4), %ecx ; X64-HSW-NEXT: leal (%rax,%rcx,2), %eax ; X64-HSW-NEXT: # kill: def $eax killed $eax killed $rax ; X64-HSW-NEXT: retq -; X64-HSW-NEXT: .LBB0_30: +; X64-HSW-NEXT: .LBB0_27: ; X64-HSW-NEXT: movl %eax, %ecx ; X64-HSW-NEXT: shll $5, %ecx -; X64-HSW-NEXT: jmp .LBB0_34 -; X64-HSW-NEXT: .LBB0_31: +; X64-HSW-NEXT: jmp .LBB0_31 +; X64-HSW-NEXT: .LBB0_28: ; X64-HSW-NEXT: xorl %eax, %eax -; X64-HSW-NEXT: .LBB0_32: +; X64-HSW-NEXT: .LBB0_29: ; X64-HSW-NEXT: # kill: def $eax killed $eax killed $rax ; X64-HSW-NEXT: retq -; X64-HSW-NEXT: .LBB0_33: +; X64-HSW-NEXT: .LBB0_30: ; X64-HSW-NEXT: leal (%rax,%rax,2), %ecx ; X64-HSW-NEXT: shll $3, %ecx -; X64-HSW-NEXT: .LBB0_34: +; X64-HSW-NEXT: .LBB0_31: ; X64-HSW-NEXT: subl %eax, %ecx ; X64-HSW-NEXT: movl %ecx, %eax ; X64-HSW-NEXT: # kill: def $eax killed $eax killed $rax ; X64-HSW-NEXT: retq -; X64-HSW-NEXT: .LBB0_36: +; X64-HSW-NEXT: .LBB0_32: ; X64-HSW-NEXT: shll $2, %eax ; X64-HSW-NEXT: leal (%rax,%rax,4), %eax ; X64-HSW-NEXT: # kill: def $eax killed $eax killed $rax ; X64-HSW-NEXT: retq -; X64-HSW-NEXT: .LBB0_37: +; X64-HSW-NEXT: .LBB0_33: ; X64-HSW-NEXT: shll $3, %eax ; X64-HSW-NEXT: leal (%rax,%rax,2), %eax ; X64-HSW-NEXT: # kill: def $eax killed $eax killed $rax ; X64-HSW-NEXT: retq -; X64-HSW-NEXT: .LBB0_38: +; X64-HSW-NEXT: .LBB0_34: ; X64-HSW-NEXT: leal (%rax,%rax,8), %ecx ; X64-HSW-NEXT: leal (%rcx,%rcx,2), %ecx ; X64-HSW-NEXT: addl %eax, %eax ; X64-HSW-NEXT: addl %ecx, %eax ; X64-HSW-NEXT: # kill: def $eax killed $eax killed $rax ; X64-HSW-NEXT: retq -; X64-HSW-NEXT: .LBB0_39: +; X64-HSW-NEXT: .LBB0_35: ; X64-HSW-NEXT: leal (%rax,%rax), %ecx ; X64-HSW-NEXT: shll $5, %eax ; X64-HSW-NEXT: subl %ecx, %eax ; X64-HSW-NEXT: # kill: def $eax killed $eax killed $rax ; X64-HSW-NEXT: retq -; X64-HSW-NEXT: .LBB0_40: +; X64-HSW-NEXT: .LBB0_36: ; X64-HSW-NEXT: leal (%rax,%rax,8), %eax ; X64-HSW-NEXT: leal (%rax,%rax,2), %eax ; X64-HSW-NEXT: # kill: def $eax killed $eax killed $rax diff --git a/llvm/test/CodeGen/X86/muloti.ll b/llvm/test/CodeGen/X86/muloti.ll index e101c702e6409..e09288354bb49 100644 --- a/llvm/test/CodeGen/X86/muloti.ll +++ b/llvm/test/CodeGen/X86/muloti.ll @@ -52,14 +52,14 @@ define %0 @x(i64 %a.coerce0, i64 %a.coerce1, i64 %b.coerce0, i64 %b.coerce1) nou ; CHECK-NEXT: xorq %rcx, %rdx ; CHECK-NEXT: xorq %rax, %rcx ; CHECK-NEXT: orq %rdx, %rcx -; CHECK-NEXT: jne LBB0_1 -; CHECK-NEXT: ## %bb.2: ## %nooverflow +; CHECK-NEXT: jne LBB0_2 +; CHECK-NEXT: ## %bb.1: ## %nooverflow ; CHECK-NEXT: movq %rsi, %rax ; CHECK-NEXT: movq %rdi, %rdx ; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %r14 ; CHECK-NEXT: retq -; CHECK-NEXT: LBB0_1: ## %overflow +; CHECK-NEXT: LBB0_2: ## %overflow ; CHECK-NEXT: ud2 entry: %tmp16 = zext i64 %a.coerce0 to i128 diff --git a/llvm/test/CodeGen/X86/negative-stride-fptosi-user.ll b/llvm/test/CodeGen/X86/negative-stride-fptosi-user.ll index 96080d2d87cdf..c5e37ac5c8132 100644 --- a/llvm/test/CodeGen/X86/negative-stride-fptosi-user.ll +++ b/llvm/test/CodeGen/X86/negative-stride-fptosi-user.ll @@ -10,25 +10,25 @@ define void @foo(i32 %N) nounwind { ; CHECK-LABEL: foo: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: testl %edi, %edi -; CHECK-NEXT: js .LBB0_1 -; CHECK-NEXT: # %bb.4: # %return +; CHECK-NEXT: js .LBB0_2 +; CHECK-NEXT: # %bb.1: # %return ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB0_1: # %bb.preheader +; CHECK-NEXT: .LBB0_2: # %bb.preheader ; CHECK-NEXT: pushq %rbp ; CHECK-NEXT: pushq %rbx ; CHECK-NEXT: pushq %rax ; CHECK-NEXT: movl %edi, %ebx ; CHECK-NEXT: xorl %ebp, %ebp ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_2: # %bb +; CHECK-NEXT: .LBB0_3: # %bb ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: xorps %xmm0, %xmm0 ; CHECK-NEXT: cvtsi2sd %ebp, %xmm0 ; CHECK-NEXT: callq bar@PLT ; CHECK-NEXT: decl %ebp ; CHECK-NEXT: cmpl %ebp, %ebx -; CHECK-NEXT: jne .LBB0_2 -; CHECK-NEXT: # %bb.3: +; CHECK-NEXT: jne .LBB0_3 +; CHECK-NEXT: # %bb.4: ; CHECK-NEXT: addq $8, %rsp ; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %rbp diff --git a/llvm/test/CodeGen/X86/no-split-size.ll b/llvm/test/CodeGen/X86/no-split-size.ll index c1f93acd77dee..aa4528cf88edb 100644 --- a/llvm/test/CodeGen/X86/no-split-size.ll +++ b/llvm/test/CodeGen/X86/no-split-size.ll @@ -28,12 +28,12 @@ define i64 @foo(ptr %ptr, i64 %p2, i64 %p3, i64 %p4, i64 %p5, i64 %p6) optsize { ; CHECK-NEXT: movq %rdx, %r15 ; CHECK-NEXT: movq %rsi, %r13 ; CHECK-NEXT: testq %rdi, %rdi -; CHECK-NEXT: je .LBB0_1 -; CHECK-NEXT: # %bb.2: # %if.else +; CHECK-NEXT: je .LBB0_3 +; CHECK-NEXT: # %bb.1: # %if.else ; CHECK-NEXT: testq %r13, %r13 ; CHECK-NEXT: movq %r15, %rax -; CHECK-NEXT: je .LBB0_3 -; CHECK-NEXT: .LBB0_4: # %if.end +; CHECK-NEXT: je .LBB0_4 +; CHECK-NEXT: .LBB0_2: # %if.end ; CHECK-NEXT: addq %r13, %rax ; CHECK-NEXT: addq %r12, %r15 ; CHECK-NEXT: addq %rax, %r15 @@ -51,13 +51,13 @@ define i64 @foo(ptr %ptr, i64 %p2, i64 %p3, i64 %p4, i64 %p5, i64 %p6) optsize { ; CHECK-NEXT: popq %r15 ; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB0_1: # %if.then +; CHECK-NEXT: .LBB0_3: # %if.then ; CHECK-NEXT: .cfi_def_cfa_offset 48 ; CHECK-NEXT: callq bar1@PLT -; CHECK-NEXT: jmp .LBB0_4 -; CHECK-NEXT: .LBB0_3: # %if.then2 +; CHECK-NEXT: jmp .LBB0_2 +; CHECK-NEXT: .LBB0_4: # %if.then2 ; CHECK-NEXT: callq bar2@PLT -; CHECK-NEXT: jmp .LBB0_4 +; CHECK-NEXT: jmp .LBB0_2 entry: %tobool.not = icmp eq ptr %ptr, null br i1 %tobool.not, label %if.then, label %if.else, !prof !5 diff --git a/llvm/test/CodeGen/X86/optimize-max-0.ll b/llvm/test/CodeGen/X86/optimize-max-0.ll index b6af7e1641a9c..2429e88fd6b48 100644 --- a/llvm/test/CodeGen/X86/optimize-max-0.ll +++ b/llvm/test/CodeGen/X86/optimize-max-0.ll @@ -31,10 +31,10 @@ define void @foo(ptr %r, i32 %s, i32 %w, i32 %x, ptr %j, i32 %d) nounwind { ; CHECK-NEXT: addl %eax, %ebp ; CHECK-NEXT: sarl $2, %ebp ; CHECK-NEXT: testl %edx, %edx -; CHECK-NEXT: jle LBB0_12 +; CHECK-NEXT: jle LBB0_7 ; CHECK-NEXT: ## %bb.2: ## %bb.nph9 ; CHECK-NEXT: testl %esi, %esi -; CHECK-NEXT: jle LBB0_12 +; CHECK-NEXT: jle LBB0_7 ; CHECK-NEXT: ## %bb.3: ## %bb.nph9.split ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: incl %eax @@ -55,22 +55,22 @@ define void @foo(ptr %r, i32 %s, i32 %w, i32 %x, ptr %j, i32 %d) nounwind { ; CHECK-NEXT: addl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: addl %esi, %edx ; CHECK-NEXT: cmpl {{[0-9]+}}(%esp), %ecx -; CHECK-NEXT: je LBB0_12 +; CHECK-NEXT: je LBB0_7 ; CHECK-NEXT: ## %bb.6: ## %bb7.preheader ; CHECK-NEXT: ## in Loop: Header=BB0_4 Depth=1 ; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: jmp LBB0_4 -; CHECK-NEXT: LBB0_12: ## %bb18.loopexit +; CHECK-NEXT: LBB0_7: ## %bb18.loopexit ; CHECK-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill ; CHECK-NEXT: movl (%esp), %eax ## 4-byte Reload ; CHECK-NEXT: addl %ebp, %eax ; CHECK-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill ; CHECK-NEXT: cmpl $1, {{[0-9]+}}(%esp) ; CHECK-NEXT: jle LBB0_13 -; CHECK-NEXT: ## %bb.7: ## %bb.nph5 +; CHECK-NEXT: ## %bb.8: ## %bb.nph5 ; CHECK-NEXT: cmpl $2, %esi ; CHECK-NEXT: jl LBB0_13 -; CHECK-NEXT: ## %bb.8: ## %bb.nph5.split +; CHECK-NEXT: ## %bb.9: ## %bb.nph5.split ; CHECK-NEXT: movl %esi, %ebp ; CHECK-NEXT: shrl $31, %ebp ; CHECK-NEXT: addl %esi, %ebp @@ -92,9 +92,9 @@ define void @foo(ptr %r, i32 %s, i32 %w, i32 %x, ptr %j, i32 %d) nounwind { ; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: LBB0_9: ## %bb13 +; CHECK-NEXT: LBB0_10: ## %bb13 ; CHECK-NEXT: ## =>This Loop Header: Depth=1 -; CHECK-NEXT: ## Child Loop BB0_10 Depth 2 +; CHECK-NEXT: ## Child Loop BB0_11 Depth 2 ; CHECK-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill ; CHECK-NEXT: andl $1, %edi ; CHECK-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill @@ -103,8 +103,8 @@ define void @foo(ptr %r, i32 %s, i32 %w, i32 %x, ptr %j, i32 %d) nounwind { ; CHECK-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %edi ## 4-byte Folded Reload ; CHECK-NEXT: xorl %ebx, %ebx ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: LBB0_10: ## %bb14 -; CHECK-NEXT: ## Parent Loop BB0_9 Depth=1 +; CHECK-NEXT: LBB0_11: ## %bb14 +; CHECK-NEXT: ## Parent Loop BB0_10 Depth=1 ; CHECK-NEXT: ## => This Inner Loop Header: Depth=2 ; CHECK-NEXT: movzbl -2(%edi,%ebx,4), %edx ; CHECK-NEXT: movb %dl, (%ecx,%ebx) @@ -112,9 +112,9 @@ define void @foo(ptr %r, i32 %s, i32 %w, i32 %x, ptr %j, i32 %d) nounwind { ; CHECK-NEXT: movb %dl, (%eax,%ebx) ; CHECK-NEXT: incl %ebx ; CHECK-NEXT: cmpl %ebp, %ebx -; CHECK-NEXT: jl LBB0_10 -; CHECK-NEXT: ## %bb.11: ## %bb17 -; CHECK-NEXT: ## in Loop: Header=BB0_9 Depth=1 +; CHECK-NEXT: jl LBB0_11 +; CHECK-NEXT: ## %bb.12: ## %bb17 +; CHECK-NEXT: ## in Loop: Header=BB0_10 Depth=1 ; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi ## 4-byte Reload ; CHECK-NEXT: incl %edi ; CHECK-NEXT: addl %ebp, %eax @@ -122,7 +122,7 @@ define void @foo(ptr %r, i32 %s, i32 %w, i32 %x, ptr %j, i32 %d) nounwind { ; CHECK-NEXT: addl $2, %edx ; CHECK-NEXT: addl %ebp, %ecx ; CHECK-NEXT: cmpl {{[-0-9]+}}(%e{{[sb]}}p), %edi ## 4-byte Folded Reload -; CHECK-NEXT: jl LBB0_9 +; CHECK-NEXT: jl LBB0_10 ; CHECK-NEXT: LBB0_13: ## %bb20 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: cmpl $1, %ecx @@ -131,7 +131,7 @@ define void @foo(ptr %r, i32 %s, i32 %w, i32 %x, ptr %j, i32 %d) nounwind { ; CHECK-NEXT: je LBB0_19 ; CHECK-NEXT: ## %bb.14: ## %bb20 ; CHECK-NEXT: cmpl $3, %ecx -; CHECK-NEXT: jne LBB0_24 +; CHECK-NEXT: jne LBB0_25 ; CHECK-NEXT: ## %bb.15: ## %bb22 ; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebp ## 4-byte Reload ; CHECK-NEXT: addl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Folded Spill @@ -216,15 +216,15 @@ define void @foo(ptr %r, i32 %s, i32 %w, i32 %x, ptr %j, i32 %d) nounwind { ; CHECK-NEXT: pushl %edx ; CHECK-NEXT: calll _memset ; CHECK-NEXT: addl $44, %esp -; CHECK-NEXT: LBB0_25: ## %return +; CHECK-NEXT: LBB0_24: ## %return ; CHECK-NEXT: popl %esi ; CHECK-NEXT: popl %edi ; CHECK-NEXT: popl %ebx ; CHECK-NEXT: popl %ebp ; CHECK-NEXT: retl -; CHECK-NEXT: LBB0_24: ## %return +; CHECK-NEXT: LBB0_25: ## %return ; CHECK-NEXT: addl $28, %esp -; CHECK-NEXT: jmp LBB0_25 +; CHECK-NEXT: jmp LBB0_24 entry: %0 = mul i32 %x, %w %1 = mul i32 %x, %w @@ -472,10 +472,10 @@ define void @bar(ptr %r, i32 %s, i32 %w, i32 %x, ptr %j, i32 %d) nounwind { ; CHECK-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill ; CHECK-NEXT: testl %ebp, %ebp ; CHECK-NEXT: movl %eax, %edi -; CHECK-NEXT: je LBB1_12 +; CHECK-NEXT: je LBB1_7 ; CHECK-NEXT: ## %bb.2: ## %bb.nph9 ; CHECK-NEXT: testl %eax, %eax -; CHECK-NEXT: je LBB1_12 +; CHECK-NEXT: je LBB1_7 ; CHECK-NEXT: ## %bb.3: ## %bb.nph9.split ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: incl %eax @@ -496,22 +496,22 @@ define void @bar(ptr %r, i32 %s, i32 %w, i32 %x, ptr %j, i32 %d) nounwind { ; CHECK-NEXT: addl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: addl %edi, %edx ; CHECK-NEXT: cmpl %ebp, %ecx -; CHECK-NEXT: je LBB1_12 +; CHECK-NEXT: je LBB1_7 ; CHECK-NEXT: ## %bb.6: ## %bb7.preheader ; CHECK-NEXT: ## in Loop: Header=BB1_4 Depth=1 ; CHECK-NEXT: xorl %esi, %esi ; CHECK-NEXT: jmp LBB1_4 -; CHECK-NEXT: LBB1_12: ## %bb18.loopexit +; CHECK-NEXT: LBB1_7: ## %bb18.loopexit ; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax ## 4-byte Reload ; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx ## 4-byte Reload ; CHECK-NEXT: addl %ecx, %eax ; CHECK-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill ; CHECK-NEXT: cmpl $1, %ebp ; CHECK-NEXT: jbe LBB1_13 -; CHECK-NEXT: ## %bb.7: ## %bb.nph5 +; CHECK-NEXT: ## %bb.8: ## %bb.nph5 ; CHECK-NEXT: cmpl $2, %edi ; CHECK-NEXT: jb LBB1_13 -; CHECK-NEXT: ## %bb.8: ## %bb.nph5.split +; CHECK-NEXT: ## %bb.9: ## %bb.nph5.split ; CHECK-NEXT: movl %edi, %ebp ; CHECK-NEXT: shrl %ebp ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax @@ -528,9 +528,9 @@ define void @bar(ptr %r, i32 %s, i32 %w, i32 %x, ptr %j, i32 %d) nounwind { ; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: xorl %esi, %esi ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: LBB1_9: ## %bb13 +; CHECK-NEXT: LBB1_10: ## %bb13 ; CHECK-NEXT: ## =>This Loop Header: Depth=1 -; CHECK-NEXT: ## Child Loop BB1_10 Depth 2 +; CHECK-NEXT: ## Child Loop BB1_11 Depth 2 ; CHECK-NEXT: movl %edx, (%esp) ## 4-byte Spill ; CHECK-NEXT: andl $1, %edx ; CHECK-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill @@ -539,8 +539,8 @@ define void @bar(ptr %r, i32 %s, i32 %w, i32 %x, ptr %j, i32 %d) nounwind { ; CHECK-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %edx ## 4-byte Folded Reload ; CHECK-NEXT: xorl %esi, %esi ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: LBB1_10: ## %bb14 -; CHECK-NEXT: ## Parent Loop BB1_9 Depth=1 +; CHECK-NEXT: LBB1_11: ## %bb14 +; CHECK-NEXT: ## Parent Loop BB1_10 Depth=1 ; CHECK-NEXT: ## => This Inner Loop Header: Depth=2 ; CHECK-NEXT: movzbl -2(%edx,%esi,4), %ebx ; CHECK-NEXT: movb %bl, (%eax,%esi) @@ -548,9 +548,9 @@ define void @bar(ptr %r, i32 %s, i32 %w, i32 %x, ptr %j, i32 %d) nounwind { ; CHECK-NEXT: movb %bl, (%ecx,%esi) ; CHECK-NEXT: incl %esi ; CHECK-NEXT: cmpl %ebp, %esi -; CHECK-NEXT: jb LBB1_10 -; CHECK-NEXT: ## %bb.11: ## %bb17 -; CHECK-NEXT: ## in Loop: Header=BB1_9 Depth=1 +; CHECK-NEXT: jb LBB1_11 +; CHECK-NEXT: ## %bb.12: ## %bb17 +; CHECK-NEXT: ## in Loop: Header=BB1_10 Depth=1 ; CHECK-NEXT: movl (%esp), %edx ## 4-byte Reload ; CHECK-NEXT: incl %edx ; CHECK-NEXT: addl %ebp, %ecx @@ -558,7 +558,7 @@ define void @bar(ptr %r, i32 %s, i32 %w, i32 %x, ptr %j, i32 %d) nounwind { ; CHECK-NEXT: addl $2, %esi ; CHECK-NEXT: addl %ebp, %eax ; CHECK-NEXT: cmpl {{[-0-9]+}}(%e{{[sb]}}p), %edx ## 4-byte Folded Reload -; CHECK-NEXT: jb LBB1_9 +; CHECK-NEXT: jb LBB1_10 ; CHECK-NEXT: LBB1_13: ## %bb20 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi ; CHECK-NEXT: cmpl $1, %esi @@ -568,7 +568,7 @@ define void @bar(ptr %r, i32 %s, i32 %w, i32 %x, ptr %j, i32 %d) nounwind { ; CHECK-NEXT: je LBB1_19 ; CHECK-NEXT: ## %bb.14: ## %bb20 ; CHECK-NEXT: cmpl $3, %esi -; CHECK-NEXT: jne LBB1_24 +; CHECK-NEXT: jne LBB1_25 ; CHECK-NEXT: ## %bb.15: ## %bb22 ; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx ## 4-byte Reload ; CHECK-NEXT: addl %edx, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Folded Spill @@ -652,15 +652,15 @@ define void @bar(ptr %r, i32 %s, i32 %w, i32 %x, ptr %j, i32 %d) nounwind { ; CHECK-NEXT: LBB1_23: ## %bb33 ; CHECK-NEXT: calll _memset ; CHECK-NEXT: addl $44, %esp -; CHECK-NEXT: LBB1_25: ## %return +; CHECK-NEXT: LBB1_24: ## %return ; CHECK-NEXT: popl %esi ; CHECK-NEXT: popl %edi ; CHECK-NEXT: popl %ebx ; CHECK-NEXT: popl %ebp ; CHECK-NEXT: retl -; CHECK-NEXT: LBB1_24: ## %return +; CHECK-NEXT: LBB1_25: ## %return ; CHECK-NEXT: addl $28, %esp -; CHECK-NEXT: jmp LBB1_25 +; CHECK-NEXT: jmp LBB1_24 entry: %0 = mul i32 %x, %w %1 = mul i32 %x, %w diff --git a/llvm/test/CodeGen/X86/partial-tail-dup.ll b/llvm/test/CodeGen/X86/partial-tail-dup.ll index 691f3e70c286c..ecd5748071deb 100644 --- a/llvm/test/CodeGen/X86/partial-tail-dup.ll +++ b/llvm/test/CodeGen/X86/partial-tail-dup.ll @@ -8,9 +8,9 @@ ; ; CHECK-LABEL: test1 ; CHECK: %p1 -; CHECK: .LBB0_4: # %dupbb +; CHECK: .LBB0_3: # %dupbb ; CHECK: %p2 -; CHECK: jmp .LBB0_4 +; CHECK: jmp .LBB0_3 define void @test1(ptr %p) !prof !1 { entry: @@ -47,7 +47,7 @@ end: ; ; CHECK-LABEL: test2 ; CHECK: %p1 -; CHECK: .LBB1_8: # %dupbb +; CHECK: .LBB1_4: # %dupbb ; ; CHECK: %p2 ; CHECK: callq c @@ -56,9 +56,9 @@ end: ; CHECK-NEXT: jmp ; ; CHECK: %p3 -; CHECK: jmp .LBB1_8 +; CHECK: jmp .LBB1_4 ; CHECK: %p4 -; CHECK: jmp .LBB1_8 +; CHECK: jmp .LBB1_4 define void @test2(ptr %p) !prof !1 { entry: @@ -119,7 +119,7 @@ end: ; ; CHECK-LABEL: test3 ; CHECK: %p1 -; CHECK: .LBB2_6: # %dupbb +; CHECK: .LBB2_4: # %dupbb ; ; CHECK: %p2 ; CHECK: callq c @@ -128,7 +128,7 @@ end: ; CHECK-NEXT: jmp ; ; CHECK: %p3 -; CHECK: jne .LBB2_6 +; CHECK: jne .LBB2_4 define void @test3(ptr %p) !prof !1 { entry: diff --git a/llvm/test/CodeGen/X86/peep-test-5.ll b/llvm/test/CodeGen/X86/peep-test-5.ll index a4af93b810233..e172da4280ef3 100644 --- a/llvm/test/CodeGen/X86/peep-test-5.ll +++ b/llvm/test/CodeGen/X86/peep-test-5.ll @@ -14,18 +14,18 @@ define void @decref(ptr %p) { ; CHECK: # %bb.0: ; CHECK-NEXT: movl (%rdi), %eax ; CHECK-NEXT: cmpl $1, %eax -; CHECK-NEXT: jne .LBB0_2 +; CHECK-NEXT: jne .LBB0_3 ; CHECK-NEXT: # %bb.1: # %bb_free ; CHECK-NEXT: pushq %rax ; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: callq free_object@PLT ; CHECK-NEXT: addq $8, %rsp ; CHECK-NEXT: .cfi_def_cfa_offset 8 -; CHECK-NEXT: .LBB0_4: # %end +; CHECK-NEXT: .LBB0_2: # %end ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB0_2: # %bb2 -; CHECK-NEXT: jle .LBB0_4 -; CHECK-NEXT: # %bb.3: # %bb_dec +; CHECK-NEXT: .LBB0_3: # %bb2 +; CHECK-NEXT: jle .LBB0_2 +; CHECK-NEXT: # %bb.4: # %bb_dec ; CHECK-NEXT: decl %eax ; CHECK-NEXT: movl %eax, (%rdi) ; CHECK-NEXT: retq diff --git a/llvm/test/CodeGen/X86/peephole-na-phys-copy-folding.ll b/llvm/test/CodeGen/X86/peephole-na-phys-copy-folding.ll index f3741dc202dc5..b47f65ed09461 100644 --- a/llvm/test/CodeGen/X86/peephole-na-phys-copy-folding.ll +++ b/llvm/test/CodeGen/X86/peephole-na-phys-copy-folding.ll @@ -16,14 +16,14 @@ define i1 @plus_one() nounwind { ; CHECK32: # %bb.0: # %entry ; CHECK32-NEXT: movzbl M, %eax ; CHECK32-NEXT: incl L -; CHECK32-NEXT: jne .LBB0_2 +; CHECK32-NEXT: jne .LBB0_3 ; CHECK32-NEXT: # %bb.1: # %entry ; CHECK32-NEXT: andb $8, %al -; CHECK32-NEXT: je .LBB0_2 -; CHECK32-NEXT: # %bb.3: # %exit2 +; CHECK32-NEXT: je .LBB0_3 +; CHECK32-NEXT: # %bb.2: # %exit2 ; CHECK32-NEXT: xorl %eax, %eax ; CHECK32-NEXT: retl -; CHECK32-NEXT: .LBB0_2: # %exit +; CHECK32-NEXT: .LBB0_3: # %exit ; CHECK32-NEXT: movb $1, %al ; CHECK32-NEXT: retl ; @@ -31,14 +31,14 @@ define i1 @plus_one() nounwind { ; CHECK64: # %bb.0: # %entry ; CHECK64-NEXT: movzbl M(%rip), %eax ; CHECK64-NEXT: incl L(%rip) -; CHECK64-NEXT: jne .LBB0_2 +; CHECK64-NEXT: jne .LBB0_3 ; CHECK64-NEXT: # %bb.1: # %entry ; CHECK64-NEXT: andb $8, %al -; CHECK64-NEXT: je .LBB0_2 -; CHECK64-NEXT: # %bb.3: # %exit2 +; CHECK64-NEXT: je .LBB0_3 +; CHECK64-NEXT: # %bb.2: # %exit2 ; CHECK64-NEXT: xorl %eax, %eax ; CHECK64-NEXT: retq -; CHECK64-NEXT: .LBB0_2: # %exit +; CHECK64-NEXT: .LBB0_3: # %exit ; CHECK64-NEXT: movb $1, %al ; CHECK64-NEXT: retq entry: @@ -64,14 +64,14 @@ define i1 @plus_forty_two() nounwind { ; CHECK32: # %bb.0: # %entry ; CHECK32-NEXT: movzbl M, %eax ; CHECK32-NEXT: addl $42, L -; CHECK32-NEXT: jne .LBB1_2 +; CHECK32-NEXT: jne .LBB1_3 ; CHECK32-NEXT: # %bb.1: # %entry ; CHECK32-NEXT: andb $8, %al -; CHECK32-NEXT: je .LBB1_2 -; CHECK32-NEXT: # %bb.3: # %exit2 +; CHECK32-NEXT: je .LBB1_3 +; CHECK32-NEXT: # %bb.2: # %exit2 ; CHECK32-NEXT: xorl %eax, %eax ; CHECK32-NEXT: retl -; CHECK32-NEXT: .LBB1_2: # %exit +; CHECK32-NEXT: .LBB1_3: # %exit ; CHECK32-NEXT: movb $1, %al ; CHECK32-NEXT: retl ; @@ -79,14 +79,14 @@ define i1 @plus_forty_two() nounwind { ; CHECK64: # %bb.0: # %entry ; CHECK64-NEXT: movzbl M(%rip), %eax ; CHECK64-NEXT: addl $42, L(%rip) -; CHECK64-NEXT: jne .LBB1_2 +; CHECK64-NEXT: jne .LBB1_3 ; CHECK64-NEXT: # %bb.1: # %entry ; CHECK64-NEXT: andb $8, %al -; CHECK64-NEXT: je .LBB1_2 -; CHECK64-NEXT: # %bb.3: # %exit2 +; CHECK64-NEXT: je .LBB1_3 +; CHECK64-NEXT: # %bb.2: # %exit2 ; CHECK64-NEXT: xorl %eax, %eax ; CHECK64-NEXT: retq -; CHECK64-NEXT: .LBB1_2: # %exit +; CHECK64-NEXT: .LBB1_3: # %exit ; CHECK64-NEXT: movb $1, %al ; CHECK64-NEXT: retq entry: @@ -112,14 +112,14 @@ define i1 @minus_one() nounwind { ; CHECK32: # %bb.0: # %entry ; CHECK32-NEXT: movzbl M, %eax ; CHECK32-NEXT: decl L -; CHECK32-NEXT: jne .LBB2_2 +; CHECK32-NEXT: jne .LBB2_3 ; CHECK32-NEXT: # %bb.1: # %entry ; CHECK32-NEXT: andb $8, %al -; CHECK32-NEXT: je .LBB2_2 -; CHECK32-NEXT: # %bb.3: # %exit2 +; CHECK32-NEXT: je .LBB2_3 +; CHECK32-NEXT: # %bb.2: # %exit2 ; CHECK32-NEXT: xorl %eax, %eax ; CHECK32-NEXT: retl -; CHECK32-NEXT: .LBB2_2: # %exit +; CHECK32-NEXT: .LBB2_3: # %exit ; CHECK32-NEXT: movb $1, %al ; CHECK32-NEXT: retl ; @@ -127,14 +127,14 @@ define i1 @minus_one() nounwind { ; CHECK64: # %bb.0: # %entry ; CHECK64-NEXT: movzbl M(%rip), %eax ; CHECK64-NEXT: decl L(%rip) -; CHECK64-NEXT: jne .LBB2_2 +; CHECK64-NEXT: jne .LBB2_3 ; CHECK64-NEXT: # %bb.1: # %entry ; CHECK64-NEXT: andb $8, %al -; CHECK64-NEXT: je .LBB2_2 -; CHECK64-NEXT: # %bb.3: # %exit2 +; CHECK64-NEXT: je .LBB2_3 +; CHECK64-NEXT: # %bb.2: # %exit2 ; CHECK64-NEXT: xorl %eax, %eax ; CHECK64-NEXT: retq -; CHECK64-NEXT: .LBB2_2: # %exit +; CHECK64-NEXT: .LBB2_3: # %exit ; CHECK64-NEXT: movb $1, %al ; CHECK64-NEXT: retq entry: @@ -160,14 +160,14 @@ define i1 @minus_forty_two() nounwind { ; CHECK32: # %bb.0: # %entry ; CHECK32-NEXT: movzbl M, %eax ; CHECK32-NEXT: addl $-42, L -; CHECK32-NEXT: jne .LBB3_2 +; CHECK32-NEXT: jne .LBB3_3 ; CHECK32-NEXT: # %bb.1: # %entry ; CHECK32-NEXT: andb $8, %al -; CHECK32-NEXT: je .LBB3_2 -; CHECK32-NEXT: # %bb.3: # %exit2 +; CHECK32-NEXT: je .LBB3_3 +; CHECK32-NEXT: # %bb.2: # %exit2 ; CHECK32-NEXT: xorl %eax, %eax ; CHECK32-NEXT: retl -; CHECK32-NEXT: .LBB3_2: # %exit +; CHECK32-NEXT: .LBB3_3: # %exit ; CHECK32-NEXT: movb $1, %al ; CHECK32-NEXT: retl ; @@ -175,14 +175,14 @@ define i1 @minus_forty_two() nounwind { ; CHECK64: # %bb.0: # %entry ; CHECK64-NEXT: movzbl M(%rip), %eax ; CHECK64-NEXT: addl $-42, L(%rip) -; CHECK64-NEXT: jne .LBB3_2 +; CHECK64-NEXT: jne .LBB3_3 ; CHECK64-NEXT: # %bb.1: # %entry ; CHECK64-NEXT: andb $8, %al -; CHECK64-NEXT: je .LBB3_2 -; CHECK64-NEXT: # %bb.3: # %exit2 +; CHECK64-NEXT: je .LBB3_3 +; CHECK64-NEXT: # %bb.2: # %exit2 ; CHECK64-NEXT: xorl %eax, %eax ; CHECK64-NEXT: retq -; CHECK64-NEXT: .LBB3_2: # %exit +; CHECK64-NEXT: .LBB3_3: # %exit ; CHECK64-NEXT: movb $1, %al ; CHECK64-NEXT: retq entry: @@ -222,13 +222,13 @@ define i64 @test_intervening_call(ptr %foo, i64 %bar, i64 %baz) nounwind { ; CHECK32-NEXT: calll bar@PLT ; CHECK32-NEXT: addl $16, %esp ; CHECK32-NEXT: testb %bl, %bl -; CHECK32-NEXT: jne .LBB4_3 +; CHECK32-NEXT: jne .LBB4_2 ; CHECK32-NEXT: # %bb.1: # %t ; CHECK32-NEXT: movl $42, %eax -; CHECK32-NEXT: jmp .LBB4_2 -; CHECK32-NEXT: .LBB4_3: # %f +; CHECK32-NEXT: jmp .LBB4_3 +; CHECK32-NEXT: .LBB4_2: # %f ; CHECK32-NEXT: xorl %eax, %eax -; CHECK32-NEXT: .LBB4_2: # %t +; CHECK32-NEXT: .LBB4_3: # %t ; CHECK32-NEXT: xorl %edx, %edx ; CHECK32-NEXT: addl $4, %esp ; CHECK32-NEXT: popl %esi @@ -294,13 +294,13 @@ define i64 @test_two_live_flags(ptr %foo0, i64 %bar0, i64 %baz0, ptr %foo1, i64 ; CHECK32-NEXT: sete %al ; CHECK32-NEXT: andb {{[-0-9]+}}(%e{{[sb]}}p), %al # 1-byte Folded Reload ; CHECK32-NEXT: cmpb $1, %al -; CHECK32-NEXT: jne .LBB5_3 +; CHECK32-NEXT: jne .LBB5_2 ; CHECK32-NEXT: # %bb.1: # %t ; CHECK32-NEXT: movl $42, %eax -; CHECK32-NEXT: jmp .LBB5_2 -; CHECK32-NEXT: .LBB5_3: # %f +; CHECK32-NEXT: jmp .LBB5_3 +; CHECK32-NEXT: .LBB5_2: # %f ; CHECK32-NEXT: xorl %eax, %eax -; CHECK32-NEXT: .LBB5_2: # %t +; CHECK32-NEXT: .LBB5_3: # %t ; CHECK32-NEXT: xorl %edx, %edx ; CHECK32-NEXT: addl $4, %esp ; CHECK32-NEXT: popl %esi diff --git a/llvm/test/CodeGen/X86/pic.ll b/llvm/test/CodeGen/X86/pic.ll index ef2849ca0cde6..2991cac21d01d 100644 --- a/llvm/test/CodeGen/X86/pic.ll +++ b/llvm/test/CodeGen/X86/pic.ll @@ -224,26 +224,26 @@ bb12: ; CHECK: .p2align 2 ; CHECK-NEXT: .LJTI7_0: -; CHECK-I686: .long .LBB7_2@GOTOFF -; CHECK-I686: .long .LBB7_8@GOTOFF -; CHECK-I686: .long .LBB7_4@GOTOFF -; CHECK-I686: .long .LBB7_6@GOTOFF -; CHECK-I686: .long .LBB7_5@GOTOFF -; CHECK-I686: .long .LBB7_8@GOTOFF -; CHECK-I686: .long .LBB7_7@GOTOFF -; CHECK-X32: .long .LBB7_2-.LJTI7_0 -; CHECK-X32: .long .LBB7_2-.LJTI7_0 -; CHECK-X32: .long .LBB7_12-.LJTI7_0 -; CHECK-X32: .long .LBB7_5-.LJTI7_0 -; CHECK-X32: .long .LBB7_12-.LJTI7_0 -; CHECK-X32: .long .LBB7_9-.LJTI7_0 -; CHECK-X32: .long .LBB7_5-.LJTI7_0 -; CHECK-X32: .long .LBB7_8-.LJTI7_0 -; CHECK-X32: .long .LBB7_9-.LJTI7_0 -; CHECK-X32: .long .LBB7_8-.LJTI7_0 -; CHECK-X32: .long .LBB7_12-.LJTI7_0 -; CHECK-X32: .long .LBB7_3-.LJTI7_0 -; CHECK-X32: .long .LBB7_3-.LJTI7_0 +; CHECK-I686: .long .LBB7_{{[0-9]+}}@GOTOFF +; CHECK-I686: .long .LBB7_{{[0-9]+}}@GOTOFF +; CHECK-I686: .long .LBB7_{{[0-9]+}}@GOTOFF +; CHECK-I686: .long .LBB7_{{[0-9]+}}@GOTOFF +; CHECK-I686: .long .LBB7_{{[0-9]+}}@GOTOFF +; CHECK-I686: .long .LBB7_{{[0-9]+}}@GOTOFF +; CHECK-I686: .long .LBB7_{{[0-9]+}}@GOTOFF +; CHECK-X32: .long .LBB7_{{[0-9]+}}-.LJTI7_0 +; CHECK-X32: .long .LBB7_{{[0-9]+}}-.LJTI7_0 +; CHECK-X32: .long .LBB7_{{[0-9]+}}-.LJTI7_0 +; CHECK-X32: .long .LBB7_{{[0-9]+}}-.LJTI7_0 +; CHECK-X32: .long .LBB7_{{[0-9]+}}-.LJTI7_0 +; CHECK-X32: .long .LBB7_{{[0-9]+}}-.LJTI7_0 +; CHECK-X32: .long .LBB7_{{[0-9]+}}-.LJTI7_0 +; CHECK-X32: .long .LBB7_{{[0-9]+}}-.LJTI7_0 +; CHECK-X32: .long .LBB7_{{[0-9]+}}-.LJTI7_0 +; CHECK-X32: .long .LBB7_{{[0-9]+}}-.LJTI7_0 +; CHECK-X32: .long .LBB7_{{[0-9]+}}-.LJTI7_0 +; CHECK-X32: .long .LBB7_{{[0-9]+}}-.LJTI7_0 +; CHECK-X32: .long .LBB7_{{[0-9]+}}-.LJTI7_0 } declare void @foo1(...) diff --git a/llvm/test/CodeGen/X86/postalloc-coalescing.ll b/llvm/test/CodeGen/X86/postalloc-coalescing.ll index 7430d7a9baf26..e576b0b9f2114 100644 --- a/llvm/test/CodeGen/X86/postalloc-coalescing.ll +++ b/llvm/test/CodeGen/X86/postalloc-coalescing.ll @@ -6,14 +6,14 @@ define fastcc i32 @_Z18yy_get_next_bufferv() nounwind { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movl $42, %eax ; CHECK-NEXT: cmpl $-1, %eax -; CHECK-NEXT: je .LBB0_3 +; CHECK-NEXT: je .LBB0_2 ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .LBB0_1: # %bb116 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: movb %al, 0 ; CHECK-NEXT: cmpl $-1, %eax ; CHECK-NEXT: jne .LBB0_1 -; CHECK-NEXT: .LBB0_3: # %bb158 +; CHECK-NEXT: .LBB0_2: # %bb158 ; CHECK-NEXT: movb %al, 0 ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: retl diff --git a/llvm/test/CodeGen/X86/pr142513.ll b/llvm/test/CodeGen/X86/pr142513.ll index fe969104fcf5e..23f9fd574d460 100644 --- a/llvm/test/CodeGen/X86/pr142513.ll +++ b/llvm/test/CodeGen/X86/pr142513.ll @@ -8,22 +8,22 @@ define i64 @foo(i64 %x) { ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: shrl $15, %eax ; X86-NEXT: cmpl $65509, %eax # imm = 0xFFE5 -; X86-NEXT: je .LBB0_1 -; X86-NEXT: # %bb.2: # %if.end +; X86-NEXT: je .LBB0_2 +; X86-NEXT: # %bb.1: # %if.end ; X86-NEXT: movl $3, %eax ; X86-NEXT: movl $2146598912, %edx # imm = 0x7FF28000 ; X86-NEXT: retl -; X86-NEXT: .LBB0_1: # %if.then +; X86-NEXT: .LBB0_2: # %if.then ; ; X64-LABEL: foo: ; X64: # %bb.0: # %entry ; X64-NEXT: shrq $47, %rdi ; X64-NEXT: cmpl $65509, %edi # imm = 0xFFE5 -; X64-NEXT: je .LBB0_1 -; X64-NEXT: # %bb.2: # %if.end +; X64-NEXT: je .LBB0_2 +; X64-NEXT: # %bb.1: # %if.end ; X64-NEXT: movabsq $9219572124669181955, %rax # imm = 0x7FF2800000000003 ; X64-NEXT: retq -; X64-NEXT: .LBB0_1: # %if.then +; X64-NEXT: .LBB0_2: # %if.then entry: %shr.mask = and i64 %x, -140737488355328 %cmp = icmp eq i64 %shr.mask, 9219572124669181952 diff --git a/llvm/test/CodeGen/X86/pr174871.ll b/llvm/test/CodeGen/X86/pr174871.ll index 9d671a9a1b8d2..e82ec6d18a395 100644 --- a/llvm/test/CodeGen/X86/pr174871.ll +++ b/llvm/test/CodeGen/X86/pr174871.ll @@ -8,8 +8,8 @@ define <16 x i32> @pr174871(<16 x i32> %a, <16 x i1> %__mask) local_unnamed_addr ; CHECK-NEXT: vpmovb2m %xmm1, %k0 ; CHECK-NEXT: kmovd %k0, %eax ; CHECK-NEXT: andl $65534, %eax # imm = 0xFFFE -; CHECK-NEXT: je .LBB0_1 -; CHECK-NEXT: # %bb.2: # %for_loop.lr.ph +; CHECK-NEXT: je .LBB0_8 +; CHECK-NEXT: # %bb.1: # %for_loop.lr.ph ; CHECK-NEXT: vpternlogd {{.*#+}} zmm2 = -1 ; CHECK-NEXT: vpaddd %zmm2, %zmm0, %zmm3 ; CHECK-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm4 @@ -26,14 +26,14 @@ define <16 x i32> @pr174871(<16 x i32> %a, <16 x i1> %__mask) local_unnamed_addr ; CHECK-NEXT: vpxor %xmm12, %xmm12, %xmm12 ; CHECK-NEXT: jmp .LBB0_3 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_4: # %switch_done +; CHECK-NEXT: .LBB0_2: # %switch_done ; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1 ; CHECK-NEXT: vpsubd %zmm2, %zmm12, %zmm12 ; CHECK-NEXT: vpcmpltud %zmm10, %zmm12, %k1 {%k1} ; CHECK-NEXT: kandw %k1, %k0, %k2 ; CHECK-NEXT: kmovd %k2, %eax ; CHECK-NEXT: ktestw %k1, %k0 -; CHECK-NEXT: je .LBB0_5 +; CHECK-NEXT: je .LBB0_7 ; CHECK-NEXT: .LBB0_3: # %for_loop ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vpcmpltud %zmm9, %zmm3, %k2 {%k1} @@ -41,8 +41,8 @@ define <16 x i32> @pr174871(<16 x i32> %a, <16 x i1> %__mask) local_unnamed_addr ; CHECK-NEXT: kandw %k2, %k0, %k3 ; CHECK-NEXT: kmovd %k3, %ecx ; CHECK-NEXT: cmpw %cx, %ax -; CHECK-NEXT: je .LBB0_4 -; CHECK-NEXT: # %bb.6: # %not_all_continued_or_breaked +; CHECK-NEXT: je .LBB0_2 +; CHECK-NEXT: # %bb.4: # %not_all_continued_or_breaked ; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1 ; CHECK-NEXT: vpcmpltud %zmm11, %zmm4, %k3 {%k1} ; CHECK-NEXT: vpaddd %zmm0, %zmm1, %zmm1 {%k3} @@ -50,8 +50,8 @@ define <16 x i32> @pr174871(<16 x i32> %a, <16 x i1> %__mask) local_unnamed_addr ; CHECK-NEXT: kandw %k2, %k0, %k3 ; CHECK-NEXT: kmovd %k3, %ecx ; CHECK-NEXT: cmpw %cx, %ax -; CHECK-NEXT: je .LBB0_4 -; CHECK-NEXT: # %bb.7: # %not_all_continued_or_breaked95 +; CHECK-NEXT: je .LBB0_2 +; CHECK-NEXT: # %bb.5: # %not_all_continued_or_breaked95 ; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1 ; CHECK-NEXT: vpcmpltud %zmm9, %zmm5, %k3 {%k1} ; CHECK-NEXT: vpaddd %zmm6, %zmm1, %zmm1 {%k3} @@ -59,16 +59,16 @@ define <16 x i32> @pr174871(<16 x i32> %a, <16 x i1> %__mask) local_unnamed_addr ; CHECK-NEXT: kandw %k2, %k0, %k2 ; CHECK-NEXT: kmovd %k2, %ecx ; CHECK-NEXT: cmpw %cx, %ax -; CHECK-NEXT: je .LBB0_4 -; CHECK-NEXT: # %bb.8: # %not_all_continued_or_breaked135 +; CHECK-NEXT: je .LBB0_2 +; CHECK-NEXT: # %bb.6: # %not_all_continued_or_breaked135 ; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1 ; CHECK-NEXT: vpcmpltud %zmm9, %zmm7, %k2 {%k1} ; CHECK-NEXT: vpaddd %zmm8, %zmm1, %zmm1 {%k2} -; CHECK-NEXT: jmp .LBB0_4 -; CHECK-NEXT: .LBB0_5: # %for_exit +; CHECK-NEXT: jmp .LBB0_2 +; CHECK-NEXT: .LBB0_7: # %for_exit ; CHECK-NEXT: vmovdqa64 %zmm1, %zmm0 ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB0_1: +; CHECK-NEXT: .LBB0_8: ; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; CHECK-NEXT: retq allocas: diff --git a/llvm/test/CodeGen/X86/pr31271.ll b/llvm/test/CodeGen/X86/pr31271.ll index 0ac1943a428ef..cdcfca888acc8 100644 --- a/llvm/test/CodeGen/X86/pr31271.ll +++ b/llvm/test/CodeGen/X86/pr31271.ll @@ -14,10 +14,10 @@ define void @fn1(i32 %k, ptr %p) { ; CHECK-NEXT: setne %dl ; CHECK-NEXT: addl $c, %eax ; CHECK-NEXT: movl %edx, (%eax) -; CHECK-NEXT: je .LBB0_1 -; CHECK-NEXT: # %bb.2: # %r +; CHECK-NEXT: je .LBB0_2 +; CHECK-NEXT: # %bb.1: # %r ; CHECK-NEXT: retl -; CHECK-NEXT: .LBB0_1: # %u +; CHECK-NEXT: .LBB0_2: # %u %g = getelementptr inbounds [1 x i32], ptr @c, i32 0, i32 %k %cmp = icmp ne ptr %p, %g %z = zext i1 %cmp to i32 diff --git a/llvm/test/CodeGen/X86/pr32282.ll b/llvm/test/CodeGen/X86/pr32282.ll index a5bb7316a9673..6aab7f729024d 100644 --- a/llvm/test/CodeGen/X86/pr32282.ll +++ b/llvm/test/CodeGen/X86/pr32282.ll @@ -44,12 +44,12 @@ define dso_local void @foo(i64 %x) nounwind { ; X64-NEXT: movq %rdi, %rdx ; X64-NEXT: orq %rcx, %rdx ; X64-NEXT: shrq $32, %rdx -; X64-NEXT: je .LBB0_1 -; X64-NEXT: # %bb.2: +; X64-NEXT: je .LBB0_2 +; X64-NEXT: # %bb.1: ; X64-NEXT: cqto ; X64-NEXT: idivq %rcx ; X64-NEXT: jmp .LBB0_3 -; X64-NEXT: .LBB0_1: +; X64-NEXT: .LBB0_2: ; X64-NEXT: # kill: def $eax killed $eax killed $rax ; X64-NEXT: xorl %edx, %edx ; X64-NEXT: divl %ecx diff --git a/llvm/test/CodeGen/X86/pr33828.ll b/llvm/test/CodeGen/X86/pr33828.ll index a96543ee6ef7a..1e8334a915473 100644 --- a/llvm/test/CodeGen/X86/pr33828.ll +++ b/llvm/test/CodeGen/X86/pr33828.ll @@ -9,19 +9,19 @@ define void @foo(i8 %a0) { ; X86: # %bb.0: # %entry ; X86-NEXT: movsbl var_580, %eax ; X86-NEXT: testl $-536870913, %eax # imm = 0xDFFFFFFF -; X86-NEXT: jne .LBB0_1 -; X86-NEXT: # %bb.2: # %if.end13 +; X86-NEXT: jne .LBB0_2 +; X86-NEXT: # %bb.1: # %if.end13 ; X86-NEXT: retl -; X86-NEXT: .LBB0_1: # %if.then11 +; X86-NEXT: .LBB0_2: # %if.then11 ; ; X64-LABEL: foo: ; X64: # %bb.0: # %entry ; X64-NEXT: movsbl var_580(%rip), %eax ; X64-NEXT: testl $-536870913, %eax # imm = 0xDFFFFFFF -; X64-NEXT: jne .LBB0_1 -; X64-NEXT: # %bb.2: # %if.end13 +; X64-NEXT: jne .LBB0_2 +; X64-NEXT: # %bb.1: # %if.end13 ; X64-NEXT: retq -; X64-NEXT: .LBB0_1: # %if.then11 +; X64-NEXT: .LBB0_2: # %if.then11 entry: %tmp = icmp ugt i8 %a0, 60 %phitmp = zext i1 %tmp to i16 diff --git a/llvm/test/CodeGen/X86/pr38539.ll b/llvm/test/CodeGen/X86/pr38539.ll index eecd15dd2afe9..7798c49149ee1 100644 --- a/llvm/test/CodeGen/X86/pr38539.ll +++ b/llvm/test/CodeGen/X86/pr38539.ll @@ -49,33 +49,33 @@ define void @f() nounwind { ; X86-NEXT: shrdl $2, %ebx, %edx ; X86-NEXT: testl %ecx, %ecx ; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: jne .LBB0_1 -; X86-NEXT: # %bb.2: # %BB_udiv-special-cases +; X86-NEXT: jne .LBB0_2 +; X86-NEXT: # %bb.1: # %BB_udiv-special-cases ; X86-NEXT: bsrl %edx, %eax ; X86-NEXT: xorl $31, %eax ; X86-NEXT: orl $32, %eax ; X86-NEXT: jmp .LBB0_3 -; X86-NEXT: .LBB0_1: +; X86-NEXT: .LBB0_2: ; X86-NEXT: bsrl %ecx, %eax ; X86-NEXT: xorl $31, %eax ; X86-NEXT: .LBB0_3: # %BB_udiv-special-cases ; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: shll $30, %esi -; X86-NEXT: jne .LBB0_4 -; X86-NEXT: # %bb.5: # %BB_udiv-special-cases +; X86-NEXT: jne .LBB0_5 +; X86-NEXT: # %bb.4: # %BB_udiv-special-cases ; X86-NEXT: movl $64, %esi ; X86-NEXT: orl %ecx, %edx -; X86-NEXT: je .LBB0_7 -; X86-NEXT: jmp .LBB0_8 -; X86-NEXT: .LBB0_4: +; X86-NEXT: je .LBB0_6 +; X86-NEXT: jmp .LBB0_7 +; X86-NEXT: .LBB0_5: ; X86-NEXT: bsrl %esi, %esi ; X86-NEXT: xorl $31, %esi ; X86-NEXT: orl %ecx, %edx -; X86-NEXT: jne .LBB0_8 -; X86-NEXT: .LBB0_7: # %BB_udiv-special-cases +; X86-NEXT: jne .LBB0_7 +; X86-NEXT: .LBB0_6: # %BB_udiv-special-cases ; X86-NEXT: addl $64, %esi ; X86-NEXT: movl %esi, %eax -; X86-NEXT: .LBB0_8: # %BB_udiv-special-cases +; X86-NEXT: .LBB0_7: # %BB_udiv-special-cases ; X86-NEXT: addl $-66, %eax ; X86-NEXT: movl $0, %ebx ; X86-NEXT: adcl $-1, %ebx @@ -84,8 +84,8 @@ define void @f() nounwind { ; X86-NEXT: andl $3, %esi ; X86-NEXT: movb $1, %cl ; X86-NEXT: testb %cl, %cl -; X86-NEXT: jne .LBB0_10 -; X86-NEXT: # %bb.9: # %select.false.sink +; X86-NEXT: jne .LBB0_9 +; X86-NEXT: # %bb.8: # %select.false.sink ; X86-NEXT: xorl %ecx, %ecx ; X86-NEXT: movl $65, %edx ; X86-NEXT: cmpl %eax, %edx @@ -95,17 +95,17 @@ define void @f() nounwind { ; X86-NEXT: sbbl %esi, %edx ; X86-NEXT: sbbl %ecx, %ecx ; X86-NEXT: setb %cl -; X86-NEXT: .LBB0_10: # %select.end +; X86-NEXT: .LBB0_9: # %select.end ; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: testb %cl, %cl -; X86-NEXT: jne .LBB0_15 -; X86-NEXT: # %bb.11: # %select.end +; X86-NEXT: jne .LBB0_14 +; X86-NEXT: # %bb.10: # %select.end ; X86-NEXT: movl %eax, %ecx ; X86-NEXT: xorl $65, %ecx ; X86-NEXT: orl %esi, %ecx ; X86-NEXT: orl %ebx, %ecx -; X86-NEXT: je .LBB0_15 -; X86-NEXT: # %bb.12: # %udiv-bb1 +; X86-NEXT: je .LBB0_14 +; X86-NEXT: # %bb.11: # %udiv-bb1 ; X86-NEXT: movl %eax, %ecx ; X86-NEXT: addl $1, %ecx ; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill @@ -142,8 +142,8 @@ define void @f() nounwind { ; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: orl %ebx, %eax ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload -; X86-NEXT: je .LBB0_15 -; X86-NEXT: # %bb.13: # %udiv-preheader +; X86-NEXT: je .LBB0_14 +; X86-NEXT: # %bb.12: # %udiv-preheader ; X86-NEXT: andl $3, %esi ; X86-NEXT: andl $3, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; X86-NEXT: movl $0, {{[0-9]+}}(%esp) @@ -181,7 +181,7 @@ define void @f() nounwind { ; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; X86-NEXT: xorl %ecx, %ecx ; X86-NEXT: .p2align 4 -; X86-NEXT: .LBB0_14: # %udiv-do-while +; X86-NEXT: .LBB0_13: # %udiv-do-while ; X86-NEXT: # =>This Inner Loop Header: Depth=1 ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload ; X86-NEXT: shldl $1, %edx, %ecx @@ -239,8 +239,8 @@ define void @f() nounwind { ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload ; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: orl %esi, %eax -; X86-NEXT: jne .LBB0_14 -; X86-NEXT: .LBB0_15: # %udiv-end +; X86-NEXT: jne .LBB0_13 +; X86-NEXT: .LBB0_14: # %udiv-end ; X86-NEXT: cmpb $0, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload ; X86-NEXT: setne (%eax) ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax diff --git a/llvm/test/CodeGen/X86/pr38743.ll b/llvm/test/CodeGen/X86/pr38743.ll index c05310090660d..597ea0dfd1940 100644 --- a/llvm/test/CodeGen/X86/pr38743.ll +++ b/llvm/test/CodeGen/X86/pr38743.ll @@ -22,12 +22,12 @@ define void @pr38743(i32 %a0) #1 align 2 { ; CHECK-NEXT: # kill: def $edi killed $edi def $rdi ; CHECK-NEXT: decl %edi ; CHECK-NEXT: jmpq *.LJTI0_0(,%rdi,8) -; CHECK-NEXT: .LBB0_2: # %bb5 +; CHECK-NEXT: .LBB0_1: # %bb5 ; CHECK-NEXT: movzwl .str.17+8(%rip), %eax ; CHECK-NEXT: movw %ax, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movq .str.17(%rip), %rax ; CHECK-NEXT: jmp .LBB0_4 -; CHECK-NEXT: .LBB0_1: # %bb2 +; CHECK-NEXT: .LBB0_2: # %bb2 ; CHECK-NEXT: movq .str.16+7(%rip), %rax ; CHECK-NEXT: movq %rax, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movq .str.16(%rip), %rax diff --git a/llvm/test/CodeGen/X86/pr38795.ll b/llvm/test/CodeGen/X86/pr38795.ll index 6a0c13526ac18..e9ac3742c64e8 100644 --- a/llvm/test/CodeGen/X86/pr38795.ll +++ b/llvm/test/CodeGen/X86/pr38795.ll @@ -29,29 +29,29 @@ define dso_local void @fn() { ; CHECK-NEXT: # implicit-def: $al ; CHECK-NEXT: # kill: killed $al ; CHECK-NEXT: # implicit-def: $ebp -; CHECK-NEXT: jmp .LBB0_1 +; CHECK-NEXT: jmp .LBB0_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_15: # %for.inc -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: .LBB0_1: # %for.inc +; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: movb %dl, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill -; CHECK-NEXT: .LBB0_1: # %for.cond +; CHECK-NEXT: .LBB0_2: # %for.cond ; CHECK-NEXT: # =>This Loop Header: Depth=1 -; CHECK-NEXT: # Child Loop BB0_19 Depth 2 +; CHECK-NEXT: # Child Loop BB0_13 Depth 2 ; CHECK-NEXT: testb %bl, %bl -; CHECK-NEXT: jne .LBB0_3 -; CHECK-NEXT: # %bb.2: # %if.then -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: jne .LBB0_4 +; CHECK-NEXT: # %bb.3: # %if.then +; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: movb %dh, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill ; CHECK-NEXT: movl $.str, (%esp) ; CHECK-NEXT: calll printf ; CHECK-NEXT: # implicit-def: $eax ; CHECK-NEXT: movzbl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 1-byte Folded Reload ; CHECK-NEXT: testl %edi, %edi -; CHECK-NEXT: jne .LBB0_10 -; CHECK-NEXT: jmp .LBB0_6 +; CHECK-NEXT: jne .LBB0_7 +; CHECK-NEXT: jmp .LBB0_12 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_3: # %if.end -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: .LBB0_4: # %if.end +; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: movl %ecx, %eax ; CHECK-NEXT: cltd ; CHECK-NEXT: idivl a @@ -59,9 +59,9 @@ define dso_local void @fn() { ; CHECK-NEXT: movl $0, h ; CHECK-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %dh # 1-byte Reload ; CHECK-NEXT: cmpb $8, %dh -; CHECK-NEXT: jg .LBB0_7 -; CHECK-NEXT: # %bb.4: # %if.then13 -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: jg .LBB0_11 +; CHECK-NEXT: # %bb.5: # %if.then13 +; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: movl %eax, %esi ; CHECK-NEXT: movl $.str, (%esp) ; CHECK-NEXT: movb %dl, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill @@ -72,79 +72,79 @@ define dso_local void @fn() { ; CHECK-NEXT: movl %esi, %ecx ; CHECK-NEXT: # implicit-def: $eax ; CHECK-NEXT: movb %dh, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill -; CHECK-NEXT: jne .LBB0_15 +; CHECK-NEXT: jne .LBB0_1 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: # %bb.5: # %for.cond35 -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: # %bb.6: # %for.cond35 +; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: testl %edi, %edi -; CHECK-NEXT: je .LBB0_6 -; CHECK-NEXT: .LBB0_10: # %af -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: je .LBB0_12 +; CHECK-NEXT: .LBB0_7: # %af +; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: testb %bl, %bl -; CHECK-NEXT: jne .LBB0_11 -; CHECK-NEXT: .LBB0_16: # %if.end39 -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: jne .LBB0_19 +; CHECK-NEXT: .LBB0_8: # %if.end39 +; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: testl %eax, %eax -; CHECK-NEXT: je .LBB0_18 -; CHECK-NEXT: # %bb.17: # %if.then41 -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: je .LBB0_10 +; CHECK-NEXT: # %bb.9: # %if.then41 +; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: movl $0, {{[0-9]+}}(%esp) ; CHECK-NEXT: movl $fn, {{[0-9]+}}(%esp) ; CHECK-NEXT: movl $.str, (%esp) ; CHECK-NEXT: calll printf -; CHECK-NEXT: .LBB0_18: # %for.end46 -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: .LBB0_10: # %for.end46 +; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: # implicit-def: $dh ; CHECK-NEXT: # implicit-def: $dl ; CHECK-NEXT: # implicit-def: $ebp -; CHECK-NEXT: jmp .LBB0_19 +; CHECK-NEXT: jmp .LBB0_13 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_7: # %if.end21 -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: .LBB0_11: # %if.end21 +; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: # implicit-def: $ebp -; CHECK-NEXT: jmp .LBB0_8 +; CHECK-NEXT: jmp .LBB0_14 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_6: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: .LBB0_12: # in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %dh # 1-byte Reload ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_19: # %for.cond47 -; CHECK-NEXT: # Parent Loop BB0_1 Depth=1 +; CHECK-NEXT: .LBB0_13: # %for.cond47 +; CHECK-NEXT: # Parent Loop BB0_2 Depth=1 ; CHECK-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-NEXT: testb %bl, %bl -; CHECK-NEXT: jne .LBB0_19 -; CHECK-NEXT: .LBB0_8: # %ae -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: jne .LBB0_13 +; CHECK-NEXT: .LBB0_14: # %ae +; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: testb %bl, %bl -; CHECK-NEXT: jne .LBB0_9 -; CHECK-NEXT: # %bb.12: # %if.end26 -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: jne .LBB0_18 +; CHECK-NEXT: # %bb.15: # %if.end26 +; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: testb %dh, %dh -; CHECK-NEXT: je .LBB0_15 -; CHECK-NEXT: # %bb.13: # %if.end26 -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: je .LBB0_1 +; CHECK-NEXT: # %bb.16: # %if.end26 +; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: testl %ebp, %ebp -; CHECK-NEXT: jne .LBB0_15 -; CHECK-NEXT: # %bb.14: # %if.then31 -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: jne .LBB0_1 +; CHECK-NEXT: # %bb.17: # %if.then31 +; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: xorl %ebp, %ebp -; CHECK-NEXT: jmp .LBB0_15 +; CHECK-NEXT: jmp .LBB0_1 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_9: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: .LBB0_18: # in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: # implicit-def: $eax ; CHECK-NEXT: testb %bl, %bl -; CHECK-NEXT: je .LBB0_16 -; CHECK-NEXT: .LBB0_11: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: je .LBB0_8 +; CHECK-NEXT: .LBB0_19: # in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: # implicit-def: $edi ; CHECK-NEXT: # implicit-def: $cl ; CHECK-NEXT: # kill: killed $cl ; CHECK-NEXT: # implicit-def: $dl ; CHECK-NEXT: # implicit-def: $ebp ; CHECK-NEXT: testl %edi, %edi -; CHECK-NEXT: jne .LBB0_10 -; CHECK-NEXT: jmp .LBB0_6 +; CHECK-NEXT: jne .LBB0_7 +; CHECK-NEXT: jmp .LBB0_12 entry: br label %for.cond @@ -262,46 +262,46 @@ define void @verifier_error_reduced_issue38788(i1 %cmp11) { ; CHECK-NEXT: .cfi_offset %ebx, -8 ; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: xorl %ebx, %ebx -; CHECK-NEXT: jmp .LBB1_1 +; CHECK-NEXT: jmp .LBB1_3 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB1_7: # %if.end26 -; CHECK-NEXT: # in Loop: Header=BB1_1 Depth=1 +; CHECK-NEXT: .LBB1_1: # %if.end26 +; CHECK-NEXT: # in Loop: Header=BB1_3 Depth=1 ; CHECK-NEXT: movl %ecx, %edx -; CHECK-NEXT: .LBB1_8: # %for.inc -; CHECK-NEXT: # in Loop: Header=BB1_1 Depth=1 +; CHECK-NEXT: .LBB1_2: # %for.inc +; CHECK-NEXT: # in Loop: Header=BB1_3 Depth=1 ; CHECK-NEXT: movl %eax, %ecx ; CHECK-NEXT: movl %edx, %ebx -; CHECK-NEXT: .LBB1_1: # %for.cond +; CHECK-NEXT: .LBB1_3: # %for.cond ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: testb $1, {{[0-9]+}}(%esp) -; CHECK-NEXT: je .LBB1_3 -; CHECK-NEXT: # %bb.2: # in Loop: Header=BB1_1 Depth=1 +; CHECK-NEXT: je .LBB1_5 +; CHECK-NEXT: # %bb.4: # in Loop: Header=BB1_3 Depth=1 ; CHECK-NEXT: xorl %eax, %eax -; CHECK-NEXT: jmp .LBB1_5 +; CHECK-NEXT: jmp .LBB1_8 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB1_3: # %if.end -; CHECK-NEXT: # in Loop: Header=BB1_1 Depth=1 -; CHECK-NEXT: je .LBB1_4 -; CHECK-NEXT: # %bb.9: # %if.then13 -; CHECK-NEXT: # in Loop: Header=BB1_1 Depth=1 +; CHECK-NEXT: .LBB1_5: # %if.end +; CHECK-NEXT: # in Loop: Header=BB1_3 Depth=1 +; CHECK-NEXT: je .LBB1_7 +; CHECK-NEXT: # %bb.6: # %if.then13 +; CHECK-NEXT: # in Loop: Header=BB1_3 Depth=1 ; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: testb $1, {{[0-9]+}}(%esp) ; CHECK-NEXT: movl %ebx, %eax ; CHECK-NEXT: movl $0, %ebx -; CHECK-NEXT: jne .LBB1_8 -; CHECK-NEXT: jmp .LBB1_5 +; CHECK-NEXT: jne .LBB1_2 +; CHECK-NEXT: jmp .LBB1_8 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB1_4: # in Loop: Header=BB1_1 Depth=1 +; CHECK-NEXT: .LBB1_7: # in Loop: Header=BB1_3 Depth=1 ; CHECK-NEXT: movl %ebx, %eax ; CHECK-NEXT: xorl %ebx, %ebx -; CHECK-NEXT: .LBB1_5: # %if.end26 -; CHECK-NEXT: # in Loop: Header=BB1_1 Depth=1 +; CHECK-NEXT: .LBB1_8: # %if.end26 +; CHECK-NEXT: # in Loop: Header=BB1_3 Depth=1 ; CHECK-NEXT: testb %cl, %cl -; CHECK-NEXT: je .LBB1_7 -; CHECK-NEXT: # %bb.6: # %if.end26 -; CHECK-NEXT: # in Loop: Header=BB1_1 Depth=1 +; CHECK-NEXT: je .LBB1_1 +; CHECK-NEXT: # %bb.9: # %if.end26 +; CHECK-NEXT: # in Loop: Header=BB1_3 Depth=1 ; CHECK-NEXT: movl %ebx, %ecx -; CHECK-NEXT: jmp .LBB1_7 +; CHECK-NEXT: jmp .LBB1_1 entry: br label %for.cond diff --git a/llvm/test/CodeGen/X86/pr39666.ll b/llvm/test/CodeGen/X86/pr39666.ll index 093805fab4304..13a2f5bd5e272 100644 --- a/llvm/test/CodeGen/X86/pr39666.ll +++ b/llvm/test/CodeGen/X86/pr39666.ll @@ -17,18 +17,18 @@ define void @test11(ptr %base, <2 x i64> %V, <2 x i1> %mask) { ; CHECK-NEXT: vpsllq $63, %xmm1, %xmm1 ; CHECK-NEXT: vmovmskpd %xmm1, %eax ; CHECK-NEXT: testb $1, %al -; CHECK-NEXT: jne .LBB1_1 -; CHECK-NEXT: # %bb.2: # %else -; CHECK-NEXT: testb $2, %al ; CHECK-NEXT: jne .LBB1_3 -; CHECK-NEXT: .LBB1_4: # %else2 +; CHECK-NEXT: # %bb.1: # %else +; CHECK-NEXT: testb $2, %al +; CHECK-NEXT: jne .LBB1_4 +; CHECK-NEXT: .LBB1_2: # %else2 ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB1_1: # %cond.store +; CHECK-NEXT: .LBB1_3: # %cond.store ; CHECK-NEXT: vmovq %xmm0, (%rdi) ; CHECK-NEXT: addq $8, %rdi ; CHECK-NEXT: testb $2, %al -; CHECK-NEXT: je .LBB1_4 -; CHECK-NEXT: .LBB1_3: # %cond.store1 +; CHECK-NEXT: je .LBB1_2 +; CHECK-NEXT: .LBB1_4: # %cond.store1 ; CHECK-NEXT: vpextrq $1, %xmm0, (%rdi) ; CHECK-NEXT: retq call void @llvm.masked.compressstore.v2i64(<2 x i64> %V, ptr %base, <2 x i1> %mask) diff --git a/llvm/test/CodeGen/X86/pr49451.ll b/llvm/test/CodeGen/X86/pr49451.ll index 1a7551f6117e8..6e52db69010e2 100644 --- a/llvm/test/CodeGen/X86/pr49451.ll +++ b/llvm/test/CodeGen/X86/pr49451.ll @@ -19,8 +19,8 @@ define void @func_6(i8 %uc_8, i64 %uli_10) nounwind { ; X86-NEXT: .LBB0_1: # %for.body612 ; X86-NEXT: # =>This Inner Loop Header: Depth=1 ; X86-NEXT: testb %bl, %bl -; X86-NEXT: je .LBB0_2 -; X86-NEXT: # %bb.3: # %if.end1401 +; X86-NEXT: je .LBB0_4 +; X86-NEXT: # %bb.2: # %if.end1401 ; X86-NEXT: # in Loop: Header=BB0_1 Depth=1 ; X86-NEXT: addl %eax, %esi ; X86-NEXT: movw %si, s_2 @@ -29,8 +29,8 @@ define void @func_6(i8 %uc_8, i64 %uli_10) nounwind { ; X86-NEXT: incl %edx ; X86-NEXT: cmpw $73, %cx ; X86-NEXT: jl .LBB0_1 -; X86-NEXT: # %bb.4: # %for.body1703 -; X86-NEXT: .LBB0_2: # %if.then671 +; X86-NEXT: # %bb.3: # %for.body1703 +; X86-NEXT: .LBB0_4: # %if.then671 ; ; X64-LABEL: func_6: ; X64: # %bb.0: # %entry @@ -41,8 +41,8 @@ define void @func_6(i8 %uc_8, i64 %uli_10) nounwind { ; X64-NEXT: .LBB0_1: # %for.body612 ; X64-NEXT: # =>This Inner Loop Header: Depth=1 ; X64-NEXT: testb %cl, %cl -; X64-NEXT: je .LBB0_2 -; X64-NEXT: # %bb.3: # %if.end1401 +; X64-NEXT: je .LBB0_4 +; X64-NEXT: # %bb.2: # %if.end1401 ; X64-NEXT: # in Loop: Header=BB0_1 Depth=1 ; X64-NEXT: addl %esi, %edx ; X64-NEXT: movw %dx, s_2(%rip) @@ -52,8 +52,8 @@ define void @func_6(i8 %uc_8, i64 %uli_10) nounwind { ; X64-NEXT: leal -23091(%rax), %edi ; X64-NEXT: cmpw $73, %di ; X64-NEXT: jl .LBB0_1 -; X64-NEXT: # %bb.4: # %for.body1703 -; X64-NEXT: .LBB0_2: # %if.then671 +; X64-NEXT: # %bb.3: # %for.body1703 +; X64-NEXT: .LBB0_4: # %if.then671 entry: %conv649 = zext i8 %uc_8 to i64 %xor650 = xor i64 %conv649, 296357731680175678 diff --git a/llvm/test/CodeGen/X86/pr50431.ll b/llvm/test/CodeGen/X86/pr50431.ll index e19aafdca0c1b..e6bacb1b6d9b7 100644 --- a/llvm/test/CodeGen/X86/pr50431.ll +++ b/llvm/test/CodeGen/X86/pr50431.ll @@ -14,11 +14,11 @@ define dso_local i32 @main() #0 { ; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx ; CHECK-NEXT: shlq %cl, %rax ; CHECK-NEXT: testl %eax, %eax -; CHECK-NEXT: je .LBB0_1 -; CHECK-NEXT: # %bb.2: # %lor.end +; CHECK-NEXT: je .LBB0_2 +; CHECK-NEXT: # %bb.1: # %lor.end ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB0_1: # %lor.rhs +; CHECK-NEXT: .LBB0_2: # %lor.rhs ; CHECK-NEXT: movl a(%rip), %eax ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: retq diff --git a/llvm/test/CodeGen/X86/pr50782.ll b/llvm/test/CodeGen/X86/pr50782.ll index 591a33446d4e3..92af6566356b1 100644 --- a/llvm/test/CodeGen/X86/pr50782.ll +++ b/llvm/test/CodeGen/X86/pr50782.ll @@ -51,14 +51,14 @@ define void @h(float %i) { ; CHECK-NEXT: movl %ecx, 12(%esi) ; CHECK-NEXT: fildl 12(%esi) ; CHECK-NEXT: movl _c, %edx -; CHECK-NEXT: jmp LBB0_3 +; CHECK-NEXT: jmp LBB0_4 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: LBB0_5: # %for.inc -; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1 +; CHECK-NEXT: LBB0_3: # %for.inc +; CHECK-NEXT: # in Loop: Header=BB0_4 Depth=1 ; CHECK-NEXT: fxch %st(5) ; CHECK-NEXT: fadd %st(4), %st ; CHECK-NEXT: fxch %st(5) -; CHECK-NEXT: LBB0_3: # %for.cond1 +; CHECK-NEXT: LBB0_4: # %for.cond1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: fld %st(5) ; CHECK-NEXT: fmul %st(4), %st @@ -71,12 +71,12 @@ define void @h(float %i) { ; CHECK-NEXT: fnstsw %ax ; CHECK-NEXT: # kill: def $ah killed $ah killed $ax ; CHECK-NEXT: sahf -; CHECK-NEXT: jbe LBB0_5 -; CHECK-NEXT: # %bb.4: # %if.then -; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1 +; CHECK-NEXT: jbe LBB0_3 +; CHECK-NEXT: # %bb.5: # %if.then +; CHECK-NEXT: # in Loop: Header=BB0_4 Depth=1 ; CHECK-NEXT: flds 8(%esi) # 4-byte Folded Reload ; CHECK-NEXT: fstps (%edx,%ecx,4) -; CHECK-NEXT: jmp LBB0_5 +; CHECK-NEXT: jmp LBB0_3 entry: %0 = load i32, ptr @a, align 4 %1 = alloca i8, i32 %0, align 16 diff --git a/llvm/test/CodeGen/X86/pr53990-incorrect-machine-sink.ll b/llvm/test/CodeGen/X86/pr53990-incorrect-machine-sink.ll index f2f6e6934abeb..c7da733ee589e 100644 --- a/llvm/test/CodeGen/X86/pr53990-incorrect-machine-sink.ll +++ b/llvm/test/CodeGen/X86/pr53990-incorrect-machine-sink.ll @@ -15,23 +15,23 @@ define void @test(i1 %c, ptr %p, ptr noalias %p2) nounwind { ; CHECK-NEXT: movl %edi, %ebp ; CHECK-NEXT: movq (%rsi), %r14 ; CHECK-NEXT: movb $1, %r15b -; CHECK-NEXT: jmp .LBB0_1 +; CHECK-NEXT: jmp .LBB0_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_4: # %sink -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: .LBB0_1: # %sink +; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: movq %r14, (%rbx) -; CHECK-NEXT: .LBB0_1: # %loop +; CHECK-NEXT: .LBB0_2: # %loop ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: testb %r15b, %r15b -; CHECK-NEXT: jne .LBB0_1 -; CHECK-NEXT: # %bb.2: # %split.3 -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: jne .LBB0_2 +; CHECK-NEXT: # %bb.3: # %split.3 +; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: testb $1, %bpl -; CHECK-NEXT: je .LBB0_4 -; CHECK-NEXT: # %bb.3: # %clobber -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: je .LBB0_1 +; CHECK-NEXT: # %bb.4: # %clobber +; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: callq clobber@PLT -; CHECK-NEXT: jmp .LBB0_4 +; CHECK-NEXT: jmp .LBB0_1 entry: %val = load i64, ptr %p, align 8 br label %loop diff --git a/llvm/test/CodeGen/X86/pr57402.ll b/llvm/test/CodeGen/X86/pr57402.ll index 338229f51cf6e..c889dc9159d4b 100644 --- a/llvm/test/CodeGen/X86/pr57402.ll +++ b/llvm/test/CodeGen/X86/pr57402.ll @@ -13,20 +13,20 @@ define void @PR57402() { ; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: divq %rsi ; CHECK-NEXT: testb %dil, %dil -; CHECK-NEXT: jne .LBB0_4 +; CHECK-NEXT: jne .LBB0_3 ; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB0_4 +; CHECK-NEXT: jne .LBB0_3 ; CHECK-NEXT: # %bb.2: # %entry ; CHECK-NEXT: andl %ecx, %edx ; CHECK-NEXT: movswl %dx, %eax ; CHECK-NEXT: imull %eax, %eax ; CHECK-NEXT: testq %rax, %rax -; CHECK-NEXT: jne .LBB0_3 -; CHECK-NEXT: .LBB0_4: # %if.end +; CHECK-NEXT: jne .LBB0_4 +; CHECK-NEXT: .LBB0_3: # %if.end ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB0_3: # %if.then +; CHECK-NEXT: .LBB0_4: # %if.then entry: %.fr = freeze i64 undef %0 = trunc i64 %.fr to i16 diff --git a/llvm/test/CodeGen/X86/pr61524.ll b/llvm/test/CodeGen/X86/pr61524.ll index 0f4ccd6498fef..6a5570e449f35 100644 --- a/llvm/test/CodeGen/X86/pr61524.ll +++ b/llvm/test/CodeGen/X86/pr61524.ll @@ -5,11 +5,11 @@ define <3 x i1> @repro(i1 %cond) { ; CHECK-LABEL: repro: ; CHECK: # %bb.0: ; CHECK-NEXT: testb $1, %dil -; CHECK-NEXT: jne .LBB0_1 -; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: jne .LBB0_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: kxorw %k0, %k0, %k0 ; CHECK-NEXT: jmp .LBB0_3 -; CHECK-NEXT: .LBB0_1: +; CHECK-NEXT: .LBB0_2: ; CHECK-NEXT: kxnorw %k0, %k0, %k0 ; CHECK-NEXT: .LBB0_3: ; CHECK-NEXT: kshiftrb $1, %k0, %k1 diff --git a/llvm/test/CodeGen/X86/pr62145.ll b/llvm/test/CodeGen/X86/pr62145.ll index 38208422be6b4..1c596ffcbfdcf 100644 --- a/llvm/test/CodeGen/X86/pr62145.ll +++ b/llvm/test/CodeGen/X86/pr62145.ll @@ -18,12 +18,12 @@ define void @f(i64 %a, i64 %b) nounwind { ; X86-NEXT: calll ext2@PLT ; X86-NEXT: andl %edi, %esi ; X86-NEXT: cmpl $-589824, %esi # imm = 0xFFF70000 -; X86-NEXT: jne .LBB0_3 -; X86-NEXT: # %bb.4: # %if.then2 +; X86-NEXT: jne .LBB0_4 +; X86-NEXT: # %bb.3: # %if.then2 ; X86-NEXT: popl %esi ; X86-NEXT: popl %edi ; X86-NEXT: jmp ext1@PLT # TAILCALL -; X86-NEXT: .LBB0_3: # %if.end3 +; X86-NEXT: .LBB0_4: # %if.end3 ; X86-NEXT: popl %esi ; X86-NEXT: popl %edi ; X86-NEXT: retl @@ -46,12 +46,12 @@ define void @f(i64 %a, i64 %b) nounwind { ; X64-NEXT: movabsq $-2533274790395904, %rax # imm = 0xFFF7000000000000 ; X64-NEXT: addq $8, %rsp ; X64-NEXT: cmpq %rax, %rbx -; X64-NEXT: jne .LBB0_3 -; X64-NEXT: # %bb.4: # %if.then2 +; X64-NEXT: jne .LBB0_4 +; X64-NEXT: # %bb.3: # %if.then2 ; X64-NEXT: popq %rbx ; X64-NEXT: popq %r14 ; X64-NEXT: jmp ext1@PLT # TAILCALL -; X64-NEXT: .LBB0_3: # %if.end3 +; X64-NEXT: .LBB0_4: # %if.end3 ; X64-NEXT: popq %rbx ; X64-NEXT: popq %r14 ; X64-NEXT: retq diff --git a/llvm/test/CodeGen/X86/pr63692.ll b/llvm/test/CodeGen/X86/pr63692.ll index 8cbd24240e1d8..22618f178f79b 100644 --- a/llvm/test/CodeGen/X86/pr63692.ll +++ b/llvm/test/CodeGen/X86/pr63692.ll @@ -5,7 +5,7 @@ define void @prefault(ptr noundef %range_start, ptr noundef readnone %range_end) ; CHECK-LABEL: prefault: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cmpq %rsi, %rdi -; CHECK-NEXT: jae .LBB0_3 +; CHECK-NEXT: jae .LBB0_2 ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .LBB0_1: # %while.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 @@ -13,7 +13,7 @@ define void @prefault(ptr noundef %range_start, ptr noundef readnone %range_end) ; CHECK-NEXT: addq $4096, %rdi # imm = 0x1000 ; CHECK-NEXT: cmpq %rsi, %rdi ; CHECK-NEXT: jb .LBB0_1 -; CHECK-NEXT: .LBB0_3: # %while.end +; CHECK-NEXT: .LBB0_2: # %while.end ; CHECK-NEXT: retq entry: %cmp3 = icmp ult ptr %range_start, %range_end diff --git a/llvm/test/CodeGen/X86/pr94829.ll b/llvm/test/CodeGen/X86/pr94829.ll index b858c636cebd8..0ec4bad2abd05 100644 --- a/llvm/test/CodeGen/X86/pr94829.ll +++ b/llvm/test/CodeGen/X86/pr94829.ll @@ -5,15 +5,15 @@ define i64 @test(i64 %x, i64 %y, i64 %a, i64 %b) { ; CHECK-LABEL: test: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: testq %rsi, %rsi -; CHECK-NEXT: jg .LBB0_2 +; CHECK-NEXT: jg .LBB0_3 ; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: movq %rcx, %rax ; CHECK-NEXT: leaq -1(%rdi), %rcx ; CHECK-NEXT: andq %rdi, %rcx -; CHECK-NEXT: jne .LBB0_2 -; CHECK-NEXT: # %bb.3: # %if.end +; CHECK-NEXT: jne .LBB0_3 +; CHECK-NEXT: # %bb.2: # %if.end ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB0_2: # %if.then +; CHECK-NEXT: .LBB0_3: # %if.then ; CHECK-NEXT: movq %rdx, %rax ; CHECK-NEXT: retq entry: diff --git a/llvm/test/CodeGen/X86/probe-stack-eflags.ll b/llvm/test/CodeGen/X86/probe-stack-eflags.ll index cc1839bba7e89..8d02c48d19ff8 100644 --- a/llvm/test/CodeGen/X86/probe-stack-eflags.ll +++ b/llvm/test/CodeGen/X86/probe-stack-eflags.ll @@ -15,8 +15,8 @@ define i32 @f(i32 %a, i32 %b) #0 { ; CHECK-NEXT: pushq %rbx ; CHECK-NEXT: pushq %rax ; CHECK-NEXT: testl %edi, %edi -; CHECK-NEXT: je .LBB0_1 -; CHECK-NEXT: # %bb.2: # %bb16.i +; CHECK-NEXT: je .LBB0_2 +; CHECK-NEXT: # %bb.1: # %bb16.i ; CHECK-NEXT: sets %bl ; CHECK-NEXT: testl %esi, %esi ; CHECK-NEXT: sets %bpl @@ -29,7 +29,7 @@ define i32 @f(i32 %a, i32 %b) #0 { ; CHECK-NEXT: xorb $1, %bl ; CHECK-NEXT: movzbl %bl, %eax ; CHECK-NEXT: jmp .LBB0_3 -; CHECK-NEXT: .LBB0_1: +; CHECK-NEXT: .LBB0_2: ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: .LBB0_3: # %exit2 ; CHECK-NEXT: addq $8, %rsp diff --git a/llvm/test/CodeGen/X86/pseudo_cmov_lower2.ll b/llvm/test/CodeGen/X86/pseudo_cmov_lower2.ll index 6091e2bf5bc56..026087498839e 100644 --- a/llvm/test/CodeGen/X86/pseudo_cmov_lower2.ll +++ b/llvm/test/CodeGen/X86/pseudo_cmov_lower2.ll @@ -30,13 +30,13 @@ define double @foo2(float %p1, double %p2, double %p3) nounwind { ; CHECK-NEXT: xorps %xmm3, %xmm3 ; CHECK-NEXT: ucomiss %xmm3, %xmm0 ; CHECK-NEXT: movsd {{.*#+}} xmm0 = [1.25E+0,0.0E+0] -; CHECK-NEXT: jae .LBB1_1 -; CHECK-NEXT: # %bb.2: # %entry +; CHECK-NEXT: jae .LBB1_2 +; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: addsd %xmm0, %xmm2 ; CHECK-NEXT: movapd %xmm2, %xmm0 ; CHECK-NEXT: movapd %xmm2, %xmm1 ; CHECK-NEXT: jmp .LBB1_3 -; CHECK-NEXT: .LBB1_1: +; CHECK-NEXT: .LBB1_2: ; CHECK-NEXT: addsd %xmm1, %xmm0 ; CHECK-NEXT: .LBB1_3: # %entry ; CHECK-NEXT: subsd %xmm1, %xmm0 @@ -123,18 +123,18 @@ define double @foo5(float %p1, double %p2, double %p3) nounwind { ; CHECK-NEXT: xorps %xmm3, %xmm3 ; CHECK-NEXT: ucomiss %xmm3, %xmm0 ; CHECK-NEXT: movsd {{.*#+}} xmm0 = [1.25E+0,0.0E+0] -; CHECK-NEXT: jae .LBB4_1 -; CHECK-NEXT: # %bb.2: # %select.false +; CHECK-NEXT: jae .LBB4_3 +; CHECK-NEXT: # %bb.1: # %select.false ; CHECK-NEXT: addsd %xmm2, %xmm0 -; CHECK-NEXT: .LBB4_3: # %select.end +; CHECK-NEXT: .LBB4_2: # %select.end ; CHECK-NEXT: subsd %xmm1, %xmm0 ; CHECK-NEXT: addsd %xmm2, %xmm0 ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB4_1: +; CHECK-NEXT: .LBB4_3: ; CHECK-NEXT: addsd %xmm0, %xmm1 ; CHECK-NEXT: movapd %xmm1, %xmm0 ; CHECK-NEXT: movapd %xmm1, %xmm2 -; CHECK-NEXT: jmp .LBB4_3 +; CHECK-NEXT: jmp .LBB4_2 entry: %c1 = fcmp oge float %p1, 0.000000e+00 %d0 = fadd double %p2, 1.25e0 @@ -157,28 +157,28 @@ define double @foo6(float %p1, double %p2, double %p3) nounwind { ; CHECK-NEXT: xorps %xmm0, %xmm0 ; CHECK-NEXT: ucomiss %xmm0, %xmm3 ; CHECK-NEXT: movsd {{.*#+}} xmm0 = [1.25E+0,0.0E+0] -; CHECK-NEXT: jae .LBB5_1 -; CHECK-NEXT: # %bb.2: # %select.false +; CHECK-NEXT: jae .LBB5_7 +; CHECK-NEXT: # %bb.1: # %select.false ; CHECK-NEXT: addsd %xmm2, %xmm0 -; CHECK-NEXT: .LBB5_3: # %select.end +; CHECK-NEXT: .LBB5_2: # %select.end ; CHECK-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3 ; CHECK-NEXT: movapd %xmm0, %xmm4 -; CHECK-NEXT: jae .LBB5_5 -; CHECK-NEXT: # %bb.4: # %select.false2 +; CHECK-NEXT: jae .LBB5_4 +; CHECK-NEXT: # %bb.3: # %select.false2 ; CHECK-NEXT: movapd %xmm1, %xmm4 -; CHECK-NEXT: .LBB5_5: # %select.end1 +; CHECK-NEXT: .LBB5_4: # %select.end1 ; CHECK-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3 ; CHECK-NEXT: movapd %xmm4, %xmm1 -; CHECK-NEXT: jae .LBB5_7 -; CHECK-NEXT: # %bb.6: # %select.false4 +; CHECK-NEXT: jae .LBB5_6 +; CHECK-NEXT: # %bb.5: # %select.false4 ; CHECK-NEXT: movapd %xmm2, %xmm1 -; CHECK-NEXT: .LBB5_7: # %select.end3 +; CHECK-NEXT: .LBB5_6: # %select.end3 ; CHECK-NEXT: subsd %xmm4, %xmm0 ; CHECK-NEXT: addsd %xmm1, %xmm0 ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB5_1: +; CHECK-NEXT: .LBB5_7: ; CHECK-NEXT: addsd %xmm1, %xmm0 -; CHECK-NEXT: jmp .LBB5_3 +; CHECK-NEXT: jmp .LBB5_2 entry: %c1 = fcmp oge float %p1, 0.000000e+00 %c2 = fcmp oge float %p1, 1.000000e+00 @@ -201,16 +201,16 @@ declare void @llvm.dbg.value(metadata, metadata, metadata) define double @foo1_g(float %p1, double %p2, double %p3) nounwind !dbg !4 { ; CHECK-LABEL: foo1_g: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: .file 1 "." "test.c" -; CHECK-NEXT: .loc 1 3 0 prologue_end +; CHECK-NEXT: .file 1 "." "test.c" +; CHECK-NEXT: .loc 1 3 0 prologue_end # test.c:3:0 ; CHECK-NEXT: xorps %xmm3, %xmm3 ; CHECK-NEXT: ucomiss %xmm3, %xmm0 ; CHECK-NEXT: movsd {{.*#+}} xmm0 = [1.25E+0,0.0E+0] -; CHECK-NEXT: jae .LBB6_1 -; CHECK-NEXT: # %bb.2: # %entry +; CHECK-NEXT: jae .LBB6_2 +; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: addsd %xmm2, %xmm0 ; CHECK-NEXT: jmp .LBB6_3 -; CHECK-NEXT: .LBB6_1: +; CHECK-NEXT: .LBB6_2: ; CHECK-NEXT: addsd %xmm0, %xmm1 ; CHECK-NEXT: movapd %xmm1, %xmm0 ; CHECK-NEXT: movapd %xmm1, %xmm2 diff --git a/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll b/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll index c24823538aa14..3ea2044013f46 100644 --- a/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll +++ b/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll @@ -45,10 +45,10 @@ define ptr @SyFgets(ptr %line, i64 %length, i64 %fid) { ; CHECK-NEXT: jne LBB0_5 ; CHECK-NEXT: ## %bb.2: ## %if.then4 ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: je LBB0_54 +; CHECK-NEXT: je LBB0_56 ; CHECK-NEXT: ## %bb.3: ## %SyTime.exit ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: je LBB0_54 +; CHECK-NEXT: je LBB0_56 ; CHECK-NEXT: LBB0_4: ## %cleanup ; CHECK-NEXT: addq $552, %rsp ## imm = 0x228 ; CHECK-NEXT: popq %rbx @@ -60,7 +60,7 @@ define ptr @SyFgets(ptr %line, i64 %length, i64 %fid) { ; CHECK-NEXT: retq ; CHECK-NEXT: LBB0_5: ## %if.end25 ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: je LBB0_54 +; CHECK-NEXT: je LBB0_56 ; CHECK-NEXT: ## %bb.6: ## %SyTime.exit2720 ; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rax ; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rcx @@ -92,221 +92,221 @@ define ptr @SyFgets(ptr %line, i64 %length, i64 %fid) { ; CHECK-NEXT: movq %rdi, {{[-0-9]+}}(%r{{[sb]}}p) ## 8-byte Spill ; CHECK-NEXT: xorl %ebp, %ebp ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne LBB0_11 -; CHECK-NEXT: ## %bb.12: ## %while.body200.preheader +; CHECK-NEXT: jne LBB0_41 +; CHECK-NEXT: ## %bb.11: ## %while.body200.preheader ; CHECK-NEXT: xorl %r12d, %r12d ; CHECK-NEXT: leaq LJTI0_0(%rip), %rdx ; CHECK-NEXT: leaq LJTI0_1(%rip), %r14 ; CHECK-NEXT: movb $1, %sil ; CHECK-NEXT: movl $0, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Folded Spill ; CHECK-NEXT: xorl %r15d, %r15d -; CHECK-NEXT: jmp LBB0_13 -; CHECK-NEXT: LBB0_43: ## %while.cond1037.preheader -; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1 +; CHECK-NEXT: jmp LBB0_14 +; CHECK-NEXT: LBB0_12: ## %while.cond1037.preheader +; CHECK-NEXT: ## in Loop: Header=BB0_14 Depth=1 ; CHECK-NEXT: testb %r12b, %r12b -; CHECK-NEXT: je LBB0_54 +; CHECK-NEXT: je LBB0_56 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: LBB0_20: ## %while.cond197.backedge -; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1 +; CHECK-NEXT: LBB0_13: ## %while.cond197.backedge +; CHECK-NEXT: ## in Loop: Header=BB0_14 Depth=1 ; CHECK-NEXT: decl %r13d ; CHECK-NEXT: testl %r13d, %r13d ; CHECK-NEXT: movl %ebp, %r15d -; CHECK-NEXT: jle LBB0_21 -; CHECK-NEXT: LBB0_13: ## %while.body200 +; CHECK-NEXT: jle LBB0_42 +; CHECK-NEXT: LBB0_14: ## %while.body200 ; CHECK-NEXT: ## =>This Loop Header: Depth=1 -; CHECK-NEXT: ## Child Loop BB0_28 Depth 2 -; CHECK-NEXT: ## Child Loop BB0_37 Depth 2 +; CHECK-NEXT: ## Child Loop BB0_20 Depth 2 +; CHECK-NEXT: ## Child Loop BB0_36 Depth 2 ; CHECK-NEXT: leal -268(%rbp), %eax ; CHECK-NEXT: cmpl $105, %eax -; CHECK-NEXT: ja LBB0_14 -; CHECK-NEXT: ## %bb.55: ## %while.body200 -; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1 +; CHECK-NEXT: ja LBB0_23 +; CHECK-NEXT: ## %bb.15: ## %while.body200 +; CHECK-NEXT: ## in Loop: Header=BB0_14 Depth=1 ; CHECK-NEXT: movslq (%r14,%rax,4), %rax ; CHECK-NEXT: addq %r14, %rax ; CHECK-NEXT: jmpq *%rax -; CHECK-NEXT: LBB0_25: ## %sw.bb474 -; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1 +; CHECK-NEXT: LBB0_16: ## %sw.bb474 +; CHECK-NEXT: ## in Loop: Header=BB0_14 Depth=1 ; CHECK-NEXT: testb %r12b, %r12b ; CHECK-NEXT: ## implicit-def: $rbx -; CHECK-NEXT: jne LBB0_33 -; CHECK-NEXT: ## %bb.26: ## %do.body479.preheader -; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1 +; CHECK-NEXT: jne LBB0_31 +; CHECK-NEXT: ## %bb.17: ## %do.body479.preheader +; CHECK-NEXT: ## in Loop: Header=BB0_14 Depth=1 ; CHECK-NEXT: testb %r12b, %r12b ; CHECK-NEXT: ## implicit-def: $rbx -; CHECK-NEXT: jne LBB0_33 -; CHECK-NEXT: ## %bb.27: ## %land.rhs485.preheader -; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1 +; CHECK-NEXT: jne LBB0_31 +; CHECK-NEXT: ## %bb.18: ## %land.rhs485.preheader +; CHECK-NEXT: ## in Loop: Header=BB0_14 Depth=1 ; CHECK-NEXT: ## implicit-def: $rax -; CHECK-NEXT: jmp LBB0_28 +; CHECK-NEXT: jmp LBB0_20 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: LBB0_31: ## %do.body479.backedge -; CHECK-NEXT: ## in Loop: Header=BB0_28 Depth=2 +; CHECK-NEXT: LBB0_19: ## %do.body479.backedge +; CHECK-NEXT: ## in Loop: Header=BB0_20 Depth=2 ; CHECK-NEXT: leaq 1(%rbx), %rax ; CHECK-NEXT: testb %r12b, %r12b -; CHECK-NEXT: je LBB0_32 -; CHECK-NEXT: LBB0_28: ## %land.rhs485 -; CHECK-NEXT: ## Parent Loop BB0_13 Depth=1 +; CHECK-NEXT: je LBB0_30 +; CHECK-NEXT: LBB0_20: ## %land.rhs485 +; CHECK-NEXT: ## Parent Loop BB0_14 Depth=1 ; CHECK-NEXT: ## => This Inner Loop Header: Depth=2 ; CHECK-NEXT: testb %sil, %sil -; CHECK-NEXT: jne LBB0_54 -; CHECK-NEXT: ## %bb.29: ## %cond.true.i.i2780 -; CHECK-NEXT: ## in Loop: Header=BB0_28 Depth=2 +; CHECK-NEXT: jne LBB0_56 +; CHECK-NEXT: ## %bb.21: ## %cond.true.i.i2780 +; CHECK-NEXT: ## in Loop: Header=BB0_20 Depth=2 ; CHECK-NEXT: movq %rax, %rbx ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne LBB0_31 -; CHECK-NEXT: ## %bb.30: ## %lor.rhs500 -; CHECK-NEXT: ## in Loop: Header=BB0_28 Depth=2 +; CHECK-NEXT: jne LBB0_19 +; CHECK-NEXT: ## %bb.22: ## %lor.rhs500 +; CHECK-NEXT: ## in Loop: Header=BB0_20 Depth=2 ; CHECK-NEXT: movl $256, %esi ## imm = 0x100 ; CHECK-NEXT: callq ___maskrune ; CHECK-NEXT: movb $1, %sil ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne LBB0_31 -; CHECK-NEXT: jmp LBB0_33 +; CHECK-NEXT: jne LBB0_19 +; CHECK-NEXT: jmp LBB0_31 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: LBB0_14: ## %while.body200 -; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1 +; CHECK-NEXT: LBB0_23: ## %while.body200 +; CHECK-NEXT: ## in Loop: Header=BB0_14 Depth=1 ; CHECK-NEXT: leal 1(%rbp), %eax ; CHECK-NEXT: cmpl $21, %eax -; CHECK-NEXT: ja LBB0_20 -; CHECK-NEXT: ## %bb.15: ## %while.body200 -; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1 +; CHECK-NEXT: ja LBB0_13 +; CHECK-NEXT: ## %bb.24: ## %while.body200 +; CHECK-NEXT: ## in Loop: Header=BB0_14 Depth=1 ; CHECK-NEXT: movslq (%rdx,%rax,4), %rax ; CHECK-NEXT: addq %rdx, %rax ; CHECK-NEXT: jmpq *%rax -; CHECK-NEXT: LBB0_18: ## %while.cond201.preheader -; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1 +; CHECK-NEXT: LBB0_25: ## %while.cond201.preheader +; CHECK-NEXT: ## in Loop: Header=BB0_14 Depth=1 ; CHECK-NEXT: movl $1, %ebp -; CHECK-NEXT: jmp LBB0_20 -; CHECK-NEXT: LBB0_44: ## %sw.bb1134 -; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1 +; CHECK-NEXT: jmp LBB0_13 +; CHECK-NEXT: LBB0_26: ## %sw.bb1134 +; CHECK-NEXT: ## in Loop: Header=BB0_14 Depth=1 ; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rax ; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rcx ; CHECK-NEXT: cmpq %rax, %rcx -; CHECK-NEXT: jb LBB0_54 -; CHECK-NEXT: ## %bb.45: ## in Loop: Header=BB0_13 Depth=1 +; CHECK-NEXT: jb LBB0_56 +; CHECK-NEXT: ## %bb.27: ## in Loop: Header=BB0_14 Depth=1 ; CHECK-NEXT: movl $0, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Folded Spill ; CHECK-NEXT: movl $268, %ebp ## imm = 0x10C -; CHECK-NEXT: jmp LBB0_20 -; CHECK-NEXT: LBB0_39: ## %sw.bb566 -; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1 +; CHECK-NEXT: jmp LBB0_13 +; CHECK-NEXT: LBB0_28: ## %sw.bb566 +; CHECK-NEXT: ## in Loop: Header=BB0_14 Depth=1 ; CHECK-NEXT: movl $20, %ebp -; CHECK-NEXT: jmp LBB0_20 -; CHECK-NEXT: LBB0_19: ## %sw.bb243 -; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1 +; CHECK-NEXT: jmp LBB0_13 +; CHECK-NEXT: LBB0_29: ## %sw.bb243 +; CHECK-NEXT: ## in Loop: Header=BB0_14 Depth=1 ; CHECK-NEXT: movl $2, %ebp -; CHECK-NEXT: jmp LBB0_20 -; CHECK-NEXT: LBB0_32: ## %if.end517.loopexitsplit -; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1 +; CHECK-NEXT: jmp LBB0_13 +; CHECK-NEXT: LBB0_30: ## %if.end517.loopexitsplit +; CHECK-NEXT: ## in Loop: Header=BB0_14 Depth=1 ; CHECK-NEXT: incq %rbx -; CHECK-NEXT: LBB0_33: ## %if.end517 -; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1 +; CHECK-NEXT: LBB0_31: ## %if.end517 +; CHECK-NEXT: ## in Loop: Header=BB0_14 Depth=1 ; CHECK-NEXT: leal -324(%r15), %eax ; CHECK-NEXT: cmpl $59, %eax -; CHECK-NEXT: ja LBB0_34 -; CHECK-NEXT: ## %bb.56: ## %if.end517 -; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1 +; CHECK-NEXT: ja LBB0_33 +; CHECK-NEXT: ## %bb.32: ## %if.end517 +; CHECK-NEXT: ## in Loop: Header=BB0_14 Depth=1 ; CHECK-NEXT: movabsq $576460756598390785, %rcx ## imm = 0x800000100000001 ; CHECK-NEXT: btq %rax, %rcx -; CHECK-NEXT: jb LBB0_37 -; CHECK-NEXT: LBB0_34: ## %if.end517 -; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1 +; CHECK-NEXT: jb LBB0_36 +; CHECK-NEXT: LBB0_33: ## %if.end517 +; CHECK-NEXT: ## in Loop: Header=BB0_14 Depth=1 ; CHECK-NEXT: cmpl $11, %r15d -; CHECK-NEXT: je LBB0_37 -; CHECK-NEXT: ## %bb.35: ## %if.end517 -; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1 +; CHECK-NEXT: je LBB0_36 +; CHECK-NEXT: ## %bb.34: ## %if.end517 +; CHECK-NEXT: ## in Loop: Header=BB0_14 Depth=1 ; CHECK-NEXT: cmpl $24, %r15d -; CHECK-NEXT: je LBB0_37 -; CHECK-NEXT: ## %bb.36: ## %if.then532 -; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1 +; CHECK-NEXT: je LBB0_36 +; CHECK-NEXT: ## %bb.35: ## %if.then532 +; CHECK-NEXT: ## in Loop: Header=BB0_14 Depth=1 ; CHECK-NEXT: movq _SyFgets.yank@GOTPCREL(%rip), %rax ; CHECK-NEXT: movb $0, (%rax) ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: LBB0_37: ## %for.cond534 -; CHECK-NEXT: ## Parent Loop BB0_13 Depth=1 +; CHECK-NEXT: LBB0_36: ## %for.cond534 +; CHECK-NEXT: ## Parent Loop BB0_14 Depth=1 ; CHECK-NEXT: ## => This Inner Loop Header: Depth=2 ; CHECK-NEXT: testb %r12b, %r12b -; CHECK-NEXT: jne LBB0_37 -; CHECK-NEXT: ## %bb.38: ## %for.cond542.preheader -; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=1 +; CHECK-NEXT: jne LBB0_36 +; CHECK-NEXT: ## %bb.37: ## %for.cond542.preheader +; CHECK-NEXT: ## in Loop: Header=BB0_14 Depth=1 ; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: movb $0, (%rbx) ; CHECK-NEXT: leaq LJTI0_0(%rip), %rdx -; CHECK-NEXT: jmp LBB0_20 +; CHECK-NEXT: jmp LBB0_13 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: LBB0_41: ## %while.cond864 +; CHECK-NEXT: LBB0_38: ## %while.cond864 ; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: jmp LBB0_41 +; CHECK-NEXT: jmp LBB0_38 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: LBB0_42: ## %while.cond962 +; CHECK-NEXT: LBB0_39: ## %while.cond962 ; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: jmp LBB0_42 +; CHECK-NEXT: jmp LBB0_39 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: LBB0_24: ## %for.cond357 +; CHECK-NEXT: LBB0_40: ## %for.cond357 ; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: jmp LBB0_24 -; CHECK-NEXT: LBB0_11: +; CHECK-NEXT: jmp LBB0_40 +; CHECK-NEXT: LBB0_41: ; CHECK-NEXT: movl $0, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Folded Spill -; CHECK-NEXT: LBB0_21: ## %while.end1465 +; CHECK-NEXT: LBB0_42: ## %while.end1465 ; CHECK-NEXT: incl %ebp ; CHECK-NEXT: cmpl $16, %ebp -; CHECK-NEXT: ja LBB0_49 -; CHECK-NEXT: ## %bb.22: ## %while.end1465 +; CHECK-NEXT: ja LBB0_51 +; CHECK-NEXT: ## %bb.43: ## %while.end1465 ; CHECK-NEXT: movl $83969, %eax ## imm = 0x14801 ; CHECK-NEXT: btl %ebp, %eax -; CHECK-NEXT: jae LBB0_49 -; CHECK-NEXT: ## %bb.23: +; CHECK-NEXT: jae LBB0_51 +; CHECK-NEXT: ## %bb.44: ; CHECK-NEXT: xorl %ebx, %ebx ; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r14 ## 8-byte Reload -; CHECK-NEXT: LBB0_47: ## %if.then1477 +; CHECK-NEXT: LBB0_45: ## %if.then1477 ; CHECK-NEXT: movl $1, %edx ; CHECK-NEXT: callq _write ; CHECK-NEXT: subq %rbx, %r14 ; CHECK-NEXT: movq _syHistory@GOTPCREL(%rip), %rax ; CHECK-NEXT: leaq 8189(%r14,%rax), %rax ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: LBB0_48: ## %for.body1723 +; CHECK-NEXT: LBB0_46: ## %for.body1723 ; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: decq %rax -; CHECK-NEXT: jmp LBB0_48 -; CHECK-NEXT: LBB0_46: ## %if.then1477.loopexit +; CHECK-NEXT: jmp LBB0_46 +; CHECK-NEXT: LBB0_47: ## %if.then1477.loopexit ; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r14 ## 8-byte Reload ; CHECK-NEXT: movq %r14, %rbx -; CHECK-NEXT: jmp LBB0_47 -; CHECK-NEXT: LBB0_16: ## %while.cond635.preheader +; CHECK-NEXT: jmp LBB0_45 +; CHECK-NEXT: LBB0_48: ## %while.cond635.preheader ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: je LBB0_40 +; CHECK-NEXT: je LBB0_50 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: LBB0_17: ## %for.body643.us +; CHECK-NEXT: LBB0_49: ## %for.body643.us ; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: jmp LBB0_17 +; CHECK-NEXT: jmp LBB0_49 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: LBB0_40: ## %while.cond661 +; CHECK-NEXT: LBB0_50: ## %while.cond661 ; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: jmp LBB0_40 -; CHECK-NEXT: LBB0_49: ## %for.cond1480.preheader +; CHECK-NEXT: jmp LBB0_50 +; CHECK-NEXT: LBB0_51: ## %for.cond1480.preheader ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: je LBB0_54 -; CHECK-NEXT: ## %bb.50: ## %for.body1664.lr.ph +; CHECK-NEXT: je LBB0_56 +; CHECK-NEXT: ## %bb.52: ## %for.body1664.lr.ph ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %r14 ## 8-byte Reload ; CHECK-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ebp ## 4-byte Reload -; CHECK-NEXT: jne LBB0_53 -; CHECK-NEXT: ## %bb.51: ## %while.body1679.preheader +; CHECK-NEXT: jne LBB0_55 +; CHECK-NEXT: ## %bb.53: ## %while.body1679.preheader ; CHECK-NEXT: incl %ebp ; CHECK-NEXT: xorl %ebx, %ebx ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: LBB0_52: ## %while.body1679 +; CHECK-NEXT: LBB0_54: ## %while.body1679 ; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: movq (%r14), %rdi ; CHECK-NEXT: callq _fileno ; CHECK-NEXT: incl %ebp ; CHECK-NEXT: testb %bl, %bl -; CHECK-NEXT: jne LBB0_52 -; CHECK-NEXT: LBB0_53: ## %while.cond1683.preheader +; CHECK-NEXT: jne LBB0_54 +; CHECK-NEXT: LBB0_55: ## %while.cond1683.preheader ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: LBB0_54: ## %if.then.i +; CHECK-NEXT: LBB0_56: ## %if.then.i ; CHECK-NEXT: ud2 entry: %sub.ptr.rhs.cast646 = ptrtoint ptr %line to i64 diff --git a/llvm/test/CodeGen/X86/reverse_branches.ll b/llvm/test/CodeGen/X86/reverse_branches.ll index 93c82a4524ef9..08f5fc112b4f2 100644 --- a/llvm/test/CodeGen/X86/reverse_branches.ll +++ b/llvm/test/CodeGen/X86/reverse_branches.ll @@ -36,30 +36,30 @@ define i32 @test_branches_order() uwtable ssp { ; CHECK-NEXT: xorl %ebx, %ebx ; CHECK-NEXT: leaq -{{[0-9]+}}(%rsp), %r14 ; CHECK-NEXT: movq %rsp, %r15 -; CHECK-NEXT: jmp LBB0_1 +; CHECK-NEXT: jmp LBB0_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: LBB0_6: ## %for.inc9 -; CHECK-NEXT: ## in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: LBB0_1: ## %for.inc9 +; CHECK-NEXT: ## in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: incl %ebx -; CHECK-NEXT: LBB0_1: ## %for.cond +; CHECK-NEXT: LBB0_2: ## %for.cond ; CHECK-NEXT: ## =>This Loop Header: Depth=1 -; CHECK-NEXT: ## Child Loop BB0_3 Depth 2 +; CHECK-NEXT: ## Child Loop BB0_4 Depth 2 ; CHECK-NEXT: cmpl $999, %ebx ## imm = 0x3E7 -; CHECK-NEXT: jg LBB0_7 -; CHECK-NEXT: ## %bb.2: ## %for.cond1.preheader -; CHECK-NEXT: ## in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: jg LBB0_6 +; CHECK-NEXT: ## %bb.3: ## %for.cond1.preheader +; CHECK-NEXT: ## in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: movl $-1, %ebp ; CHECK-NEXT: movq %r15, %rdi ; CHECK-NEXT: movq %r14, %r12 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: LBB0_3: ## %for.cond1 -; CHECK-NEXT: ## Parent Loop BB0_1 Depth=1 +; CHECK-NEXT: LBB0_4: ## %for.cond1 +; CHECK-NEXT: ## Parent Loop BB0_2 Depth=1 ; CHECK-NEXT: ## => This Inner Loop Header: Depth=2 ; CHECK-NEXT: incl %ebp ; CHECK-NEXT: cmpl $999, %ebp ## imm = 0x3E7 -; CHECK-NEXT: jg LBB0_6 -; CHECK-NEXT: ## %bb.4: ## %for.body3 -; CHECK-NEXT: ## in Loop: Header=BB0_3 Depth=2 +; CHECK-NEXT: jg LBB0_1 +; CHECK-NEXT: ## %bb.5: ## %for.body3 +; CHECK-NEXT: ## in Loop: Header=BB0_4 Depth=2 ; CHECK-NEXT: addq $1002, %r12 ## imm = 0x3EA ; CHECK-NEXT: leaq 1001(%rdi), %r13 ; CHECK-NEXT: movl $1000, %edx ## imm = 0x3E8 @@ -67,22 +67,22 @@ define i32 @test_branches_order() uwtable ssp { ; CHECK-NEXT: callq _memchr ; CHECK-NEXT: cmpq %rax, %r12 ; CHECK-NEXT: movq %r13, %rdi -; CHECK-NEXT: je LBB0_3 -; CHECK-NEXT: jmp LBB0_5 -; CHECK-NEXT: LBB0_7: ## %for.end11 +; CHECK-NEXT: je LBB0_4 +; CHECK-NEXT: jmp LBB0_15 +; CHECK-NEXT: LBB0_6: ## %for.end11 ; CHECK-NEXT: leaq L_.str2(%rip), %rdi ; CHECK-NEXT: callq _puts ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: movq %rsp, %rcx ; CHECK-NEXT: jmp LBB0_8 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: LBB0_15: ## %for.inc38 +; CHECK-NEXT: LBB0_7: ## %for.inc38 ; CHECK-NEXT: ## in Loop: Header=BB0_8 Depth=1 ; CHECK-NEXT: incl %eax ; CHECK-NEXT: LBB0_8: ## %for.cond14 ; CHECK-NEXT: ## =>This Loop Header: Depth=1 -; CHECK-NEXT: ## Child Loop BB0_10 Depth 2 -; CHECK-NEXT: ## Child Loop BB0_12 Depth 3 +; CHECK-NEXT: ## Child Loop BB0_11 Depth 2 +; CHECK-NEXT: ## Child Loop BB0_13 Depth 3 ; CHECK-NEXT: cmpl $999, %eax ## imm = 0x3E7 ; CHECK-NEXT: jg LBB0_16 ; CHECK-NEXT: ## %bb.9: ## %for.cond18.preheader @@ -90,37 +90,37 @@ define i32 @test_branches_order() uwtable ssp { ; CHECK-NEXT: movq %rcx, %rdx ; CHECK-NEXT: xorl %esi, %esi ; CHECK-NEXT: xorl %edi, %edi -; CHECK-NEXT: jmp LBB0_10 +; CHECK-NEXT: jmp LBB0_11 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: LBB0_14: ## %exit -; CHECK-NEXT: ## in Loop: Header=BB0_10 Depth=2 +; CHECK-NEXT: LBB0_10: ## %exit +; CHECK-NEXT: ## in Loop: Header=BB0_11 Depth=2 ; CHECK-NEXT: addq %rsi, %r8 ; CHECK-NEXT: incq %rdi ; CHECK-NEXT: decq %rsi ; CHECK-NEXT: addq $1001, %rdx ## imm = 0x3E9 ; CHECK-NEXT: cmpq $-1000, %r8 ## imm = 0xFC18 -; CHECK-NEXT: jne LBB0_5 -; CHECK-NEXT: LBB0_10: ## %for.cond18 +; CHECK-NEXT: jne LBB0_15 +; CHECK-NEXT: LBB0_11: ## %for.cond18 ; CHECK-NEXT: ## Parent Loop BB0_8 Depth=1 ; CHECK-NEXT: ## => This Loop Header: Depth=2 -; CHECK-NEXT: ## Child Loop BB0_12 Depth 3 +; CHECK-NEXT: ## Child Loop BB0_13 Depth 3 ; CHECK-NEXT: cmpl $999, %edi ## imm = 0x3E7 -; CHECK-NEXT: jg LBB0_15 -; CHECK-NEXT: ## %bb.11: ## %for.body20 -; CHECK-NEXT: ## in Loop: Header=BB0_10 Depth=2 +; CHECK-NEXT: jg LBB0_7 +; CHECK-NEXT: ## %bb.12: ## %for.body20 +; CHECK-NEXT: ## in Loop: Header=BB0_11 Depth=2 ; CHECK-NEXT: movq $-1000, %r8 ## imm = 0xFC18 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: LBB0_12: ## %do.body.i +; CHECK-NEXT: LBB0_13: ## %do.body.i ; CHECK-NEXT: ## Parent Loop BB0_8 Depth=1 -; CHECK-NEXT: ## Parent Loop BB0_10 Depth=2 +; CHECK-NEXT: ## Parent Loop BB0_11 Depth=2 ; CHECK-NEXT: ## => This Inner Loop Header: Depth=3 ; CHECK-NEXT: cmpb $120, 1000(%rdx,%r8) -; CHECK-NEXT: je LBB0_14 -; CHECK-NEXT: ## %bb.13: ## %do.cond.i -; CHECK-NEXT: ## in Loop: Header=BB0_12 Depth=3 +; CHECK-NEXT: je LBB0_10 +; CHECK-NEXT: ## %bb.14: ## %do.cond.i +; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=3 ; CHECK-NEXT: incq %r8 -; CHECK-NEXT: jne LBB0_12 -; CHECK-NEXT: LBB0_5: ## %if.then +; CHECK-NEXT: jne LBB0_13 +; CHECK-NEXT: LBB0_15: ## %if.then ; CHECK-NEXT: leaq L_str4(%rip), %rdi ; CHECK-NEXT: callq _puts ; CHECK-NEXT: movl $1, %edi diff --git a/llvm/test/CodeGen/X86/scalar-int-to-fp.ll b/llvm/test/CodeGen/X86/scalar-int-to-fp.ll index 43c1a84f7cd6c..f484767ecf5ac 100644 --- a/llvm/test/CodeGen/X86/scalar-int-to-fp.ll +++ b/llvm/test/CodeGen/X86/scalar-int-to-fp.ll @@ -365,11 +365,11 @@ define float @u64_to_f(i64 %a) nounwind { ; SSE2_64-LABEL: u64_to_f: ; SSE2_64: # %bb.0: ; SSE2_64-NEXT: testq %rdi, %rdi -; SSE2_64-NEXT: js .LBB6_1 -; SSE2_64-NEXT: # %bb.2: +; SSE2_64-NEXT: js .LBB6_2 +; SSE2_64-NEXT: # %bb.1: ; SSE2_64-NEXT: cvtsi2ss %rdi, %xmm0 ; SSE2_64-NEXT: retq -; SSE2_64-NEXT: .LBB6_1: +; SSE2_64-NEXT: .LBB6_2: ; SSE2_64-NEXT: movq %rdi, %rax ; SSE2_64-NEXT: shrq %rax ; SSE2_64-NEXT: andl $1, %edi diff --git a/llvm/test/CodeGen/X86/scheduler-backtracking.ll b/llvm/test/CodeGen/X86/scheduler-backtracking.ll index 28029793211f0..767ff4b7cc0a7 100644 --- a/llvm/test/CodeGen/X86/scheduler-backtracking.ll +++ b/llvm/test/CodeGen/X86/scheduler-backtracking.ll @@ -735,8 +735,8 @@ define i256 @PR25498(i256 %a) nounwind { ; ILP-NEXT: orq %r8, %rdx ; ILP-NEXT: orq %rcx, %rsi ; ILP-NEXT: orq %rdx, %rsi -; ILP-NEXT: je .LBB4_1 -; ILP-NEXT: # %bb.2: # %cond.false +; ILP-NEXT: je .LBB4_2 +; ILP-NEXT: # %bb.1: # %cond.false ; ILP-NEXT: bsrq %r10, %rdx ; ILP-NEXT: bsrq %rdi, %rcx ; ILP-NEXT: xorq $63, %rcx @@ -755,7 +755,7 @@ define i256 @PR25498(i256 %a) nounwind { ; ILP-NEXT: orq %rdi, %r9 ; ILP-NEXT: cmovneq %rsi, %rcx ; ILP-NEXT: jmp .LBB4_3 -; ILP-NEXT: .LBB4_1: +; ILP-NEXT: .LBB4_2: ; ILP-NEXT: movl $256, %ecx # imm = 0x100 ; ILP-NEXT: .LBB4_3: # %cond.end ; ILP-NEXT: xorps %xmm0, %xmm0 @@ -778,8 +778,8 @@ define i256 @PR25498(i256 %a) nounwind { ; HYBRID-NEXT: orq %r8, %rdx ; HYBRID-NEXT: orq %rcx, %rsi ; HYBRID-NEXT: orq %rdx, %rsi -; HYBRID-NEXT: je .LBB4_1 -; HYBRID-NEXT: # %bb.2: # %cond.false +; HYBRID-NEXT: je .LBB4_2 +; HYBRID-NEXT: # %bb.1: # %cond.false ; HYBRID-NEXT: bsrq %rdi, %rcx ; HYBRID-NEXT: xorq $63, %rcx ; HYBRID-NEXT: bsrq %r9, %rdx @@ -798,7 +798,7 @@ define i256 @PR25498(i256 %a) nounwind { ; HYBRID-NEXT: orq %rdi, %r9 ; HYBRID-NEXT: cmovneq %rdx, %rcx ; HYBRID-NEXT: jmp .LBB4_3 -; HYBRID-NEXT: .LBB4_1: +; HYBRID-NEXT: .LBB4_2: ; HYBRID-NEXT: movl $256, %ecx # imm = 0x100 ; HYBRID-NEXT: .LBB4_3: # %cond.end ; HYBRID-NEXT: xorps %xmm0, %xmm0 @@ -821,8 +821,8 @@ define i256 @PR25498(i256 %a) nounwind { ; BURR-NEXT: orq %r8, %rdx ; BURR-NEXT: orq %rcx, %rsi ; BURR-NEXT: orq %rdx, %rsi -; BURR-NEXT: je .LBB4_1 -; BURR-NEXT: # %bb.2: # %cond.false +; BURR-NEXT: je .LBB4_2 +; BURR-NEXT: # %bb.1: # %cond.false ; BURR-NEXT: bsrq %rdi, %rcx ; BURR-NEXT: xorq $63, %rcx ; BURR-NEXT: bsrq %r9, %rdx @@ -841,7 +841,7 @@ define i256 @PR25498(i256 %a) nounwind { ; BURR-NEXT: orq %rdi, %r9 ; BURR-NEXT: cmovneq %rdx, %rcx ; BURR-NEXT: jmp .LBB4_3 -; BURR-NEXT: .LBB4_1: +; BURR-NEXT: .LBB4_2: ; BURR-NEXT: movl $256, %ecx # imm = 0x100 ; BURR-NEXT: .LBB4_3: # %cond.end ; BURR-NEXT: movq %rcx, (%rax) @@ -864,8 +864,8 @@ define i256 @PR25498(i256 %a) nounwind { ; SRC-NEXT: orq %r8, %rdx ; SRC-NEXT: orq %rcx, %rsi ; SRC-NEXT: orq %rdx, %rsi -; SRC-NEXT: je .LBB4_1 -; SRC-NEXT: # %bb.2: # %cond.false +; SRC-NEXT: je .LBB4_2 +; SRC-NEXT: # %bb.1: # %cond.false ; SRC-NEXT: bsrq %rdi, %rcx ; SRC-NEXT: xorq $63, %rcx ; SRC-NEXT: bsrq %r9, %rdx @@ -884,7 +884,7 @@ define i256 @PR25498(i256 %a) nounwind { ; SRC-NEXT: orq %rdi, %r9 ; SRC-NEXT: cmovneq %rdx, %rcx ; SRC-NEXT: jmp .LBB4_3 -; SRC-NEXT: .LBB4_1: +; SRC-NEXT: .LBB4_2: ; SRC-NEXT: movl $256, %ecx # imm = 0x100 ; SRC-NEXT: .LBB4_3: # %cond.end ; SRC-NEXT: movq %rcx, (%rax) @@ -907,8 +907,8 @@ define i256 @PR25498(i256 %a) nounwind { ; LIN-NEXT: orq %rcx, %rsi ; LIN-NEXT: orq %r8, %rdx ; LIN-NEXT: orq %rsi, %rdx -; LIN-NEXT: je .LBB4_1 -; LIN-NEXT: # %bb.2: # %cond.false +; LIN-NEXT: je .LBB4_2 +; LIN-NEXT: # %bb.1: # %cond.false ; LIN-NEXT: bsrq %r11, %rcx ; LIN-NEXT: xorq $63, %rcx ; LIN-NEXT: orq $64, %rcx @@ -927,7 +927,7 @@ define i256 @PR25498(i256 %a) nounwind { ; LIN-NEXT: orq %rdi, %r9 ; LIN-NEXT: cmoveq %rdx, %rcx ; LIN-NEXT: jmp .LBB4_3 -; LIN-NEXT: .LBB4_1: +; LIN-NEXT: .LBB4_2: ; LIN-NEXT: movl $256, %ecx # imm = 0x100 ; LIN-NEXT: .LBB4_3: # %cond.end ; LIN-NEXT: xorps %xmm0, %xmm0 diff --git a/llvm/test/CodeGen/X86/segmented-stacks-dynamic.ll b/llvm/test/CodeGen/X86/segmented-stacks-dynamic.ll index e8359cb088dc3..0c3ee356bdf2c 100644 --- a/llvm/test/CodeGen/X86/segmented-stacks-dynamic.ll +++ b/llvm/test/CodeGen/X86/segmented-stacks-dynamic.ll @@ -13,8 +13,8 @@ define i32 @test_basic(i32 %l) #0 { ; X86-LABEL: test_basic: ; X86: # %bb.0: ; X86-NEXT: cmpl %gs:48, %esp -; X86-NEXT: jbe .LBB0_1 -; X86-NEXT: .LBB0_2: +; X86-NEXT: jbe .LBB0_8 +; X86-NEXT: .LBB0_1: ; X86-NEXT: pushl %ebp ; X86-NEXT: .cfi_def_cfa_offset 8 ; X86-NEXT: .cfi_offset %ebp, -8 @@ -29,16 +29,16 @@ define i32 @test_basic(i32 %l) #0 { ; X86-NEXT: andl $-16, %ecx ; X86-NEXT: subl %ecx, %eax ; X86-NEXT: cmpl %eax, %gs:48 -; X86-NEXT: jg .LBB0_4 -; X86-NEXT: # %bb.3: +; X86-NEXT: jg .LBB0_3 +; X86-NEXT: # %bb.2: ; X86-NEXT: movl %eax, %esp -; X86-NEXT: jmp .LBB0_5 -; X86-NEXT: .LBB0_4: +; X86-NEXT: jmp .LBB0_4 +; X86-NEXT: .LBB0_3: ; X86-NEXT: subl $12, %esp ; X86-NEXT: pushl %ecx ; X86-NEXT: calll __morestack_allocate_stack_space ; X86-NEXT: addl $16, %esp -; X86-NEXT: .LBB0_5: +; X86-NEXT: .LBB0_4: ; X86-NEXT: subl $16, %esp ; X86-NEXT: movl %esi, {{[0-9]+}}(%esp) ; X86-NEXT: movl %eax, (%esp) @@ -46,7 +46,7 @@ define i32 @test_basic(i32 %l) #0 { ; X86-NEXT: addl $16, %esp ; X86-NEXT: testl %esi, %esi ; X86-NEXT: je .LBB0_6 -; X86-NEXT: # %bb.8: # %false +; X86-NEXT: # %bb.5: # %false ; X86-NEXT: decl %esi ; X86-NEXT: subl $16, %esp ; X86-NEXT: movl %esi, (%esp) @@ -60,20 +60,20 @@ define i32 @test_basic(i32 %l) #0 { ; X86-NEXT: popl %ebp ; X86-NEXT: .cfi_def_cfa %esp, 4 ; X86-NEXT: retl -; X86-NEXT: .LBB0_1: +; X86-NEXT: .LBB0_8: ; X86-NEXT: .cfi_restore %ebp ; X86-NEXT: .cfi_restore %esi ; X86-NEXT: pushl $4 ; X86-NEXT: pushl $12 ; X86-NEXT: calll __morestack ; X86-NEXT: retl -; X86-NEXT: jmp .LBB0_2 +; X86-NEXT: jmp .LBB0_1 ; ; X64-LABEL: test_basic: ; X64: # %bb.0: ; X64-NEXT: cmpq %fs:112, %rsp -; X64-NEXT: jbe .LBB0_1 -; X64-NEXT: .LBB0_2: +; X64-NEXT: jbe .LBB0_8 +; X64-NEXT: .LBB0_1: ; X64-NEXT: pushq %rbp ; X64-NEXT: .cfi_def_cfa_offset 16 ; X64-NEXT: .cfi_offset %rbp, -16 @@ -89,20 +89,20 @@ define i32 @test_basic(i32 %l) #0 { ; X64-NEXT: andq $-16, %rax ; X64-NEXT: subq %rax, %rdi ; X64-NEXT: cmpq %rdi, %fs:112 -; X64-NEXT: jg .LBB0_4 -; X64-NEXT: # %bb.3: +; X64-NEXT: jg .LBB0_3 +; X64-NEXT: # %bb.2: ; X64-NEXT: movq %rdi, %rsp -; X64-NEXT: jmp .LBB0_5 -; X64-NEXT: .LBB0_4: +; X64-NEXT: jmp .LBB0_4 +; X64-NEXT: .LBB0_3: ; X64-NEXT: movq %rax, %rdi ; X64-NEXT: callq __morestack_allocate_stack_space ; X64-NEXT: movq %rax, %rdi -; X64-NEXT: .LBB0_5: +; X64-NEXT: .LBB0_4: ; X64-NEXT: movl %ebx, %esi ; X64-NEXT: callq dummy_use@PLT ; X64-NEXT: testl %ebx, %ebx ; X64-NEXT: je .LBB0_6 -; X64-NEXT: # %bb.8: # %false +; X64-NEXT: # %bb.5: # %false ; X64-NEXT: decl %ebx ; X64-NEXT: movl %ebx, %edi ; X64-NEXT: callq test_basic@PLT @@ -115,20 +115,20 @@ define i32 @test_basic(i32 %l) #0 { ; X64-NEXT: popq %rbp ; X64-NEXT: .cfi_def_cfa %rsp, 8 ; X64-NEXT: retq -; X64-NEXT: .LBB0_1: +; X64-NEXT: .LBB0_8: ; X64-NEXT: .cfi_restore %rbx ; X64-NEXT: .cfi_restore %rbp ; X64-NEXT: movl $24, %r10d ; X64-NEXT: movl $0, %r11d ; X64-NEXT: callq __morestack ; X64-NEXT: retq -; X64-NEXT: jmp .LBB0_2 +; X64-NEXT: jmp .LBB0_1 ; ; X32ABI-LABEL: test_basic: ; X32ABI: # %bb.0: ; X32ABI-NEXT: cmpl %fs:64, %esp -; X32ABI-NEXT: jbe .LBB0_1 -; X32ABI-NEXT: .LBB0_2: +; X32ABI-NEXT: jbe .LBB0_8 +; X32ABI-NEXT: .LBB0_1: ; X32ABI-NEXT: pushq %rbp ; X32ABI-NEXT: .cfi_def_cfa_offset 16 ; X32ABI-NEXT: .cfi_offset %rbp, -16 @@ -143,20 +143,20 @@ define i32 @test_basic(i32 %l) #0 { ; X32ABI-NEXT: movl %esp, %edi ; X32ABI-NEXT: subl %eax, %edi ; X32ABI-NEXT: cmpl %edi, %fs:64 -; X32ABI-NEXT: jg .LBB0_4 -; X32ABI-NEXT: # %bb.3: +; X32ABI-NEXT: jg .LBB0_3 +; X32ABI-NEXT: # %bb.2: ; X32ABI-NEXT: movl %edi, %esp -; X32ABI-NEXT: jmp .LBB0_5 -; X32ABI-NEXT: .LBB0_4: +; X32ABI-NEXT: jmp .LBB0_4 +; X32ABI-NEXT: .LBB0_3: ; X32ABI-NEXT: movl %eax, %edi ; X32ABI-NEXT: callq __morestack_allocate_stack_space ; X32ABI-NEXT: movl %eax, %edi -; X32ABI-NEXT: .LBB0_5: +; X32ABI-NEXT: .LBB0_4: ; X32ABI-NEXT: movl %ebx, %esi ; X32ABI-NEXT: callq dummy_use@PLT ; X32ABI-NEXT: testl %ebx, %ebx ; X32ABI-NEXT: je .LBB0_6 -; X32ABI-NEXT: # %bb.8: # %false +; X32ABI-NEXT: # %bb.5: # %false ; X32ABI-NEXT: decl %ebx ; X32ABI-NEXT: movl %ebx, %edi ; X32ABI-NEXT: callq test_basic@PLT @@ -169,7 +169,7 @@ define i32 @test_basic(i32 %l) #0 { ; X32ABI-NEXT: popq %rbp ; X32ABI-NEXT: .cfi_def_cfa %rsp, 8 ; X32ABI-NEXT: retq -; X32ABI-NEXT: .LBB0_1: +; X32ABI-NEXT: .LBB0_8: ; X32ABI-NEXT: .cfi_def_cfa_register 4294967294 ; X32ABI-NEXT: .cfi_restore %rbx ; X32ABI-NEXT: .cfi_restore %rbp @@ -177,7 +177,7 @@ define i32 @test_basic(i32 %l) #0 { ; X32ABI-NEXT: movl $0, %r11d ; X32ABI-NEXT: callq __morestack ; X32ABI-NEXT: retq -; X32ABI-NEXT: jmp .LBB0_2 +; X32ABI-NEXT: jmp .LBB0_1 %mem = alloca i32, i32 %l call void @dummy_use (ptr %mem, i32 %l) %terminate = icmp eq i32 %l, 0 diff --git a/llvm/test/CodeGen/X86/segmented-stacks.ll b/llvm/test/CodeGen/X86/segmented-stacks.ll index f8627ff56a1f9..6d9d0dabb59ef 100644 --- a/llvm/test/CodeGen/X86/segmented-stacks.ll +++ b/llvm/test/CodeGen/X86/segmented-stacks.ll @@ -38,8 +38,8 @@ define void @test_basic() #0 { ; X86-Linux-LABEL: test_basic: ; X86-Linux: # %bb.0: ; X86-Linux-NEXT: cmpl %gs:48, %esp -; X86-Linux-NEXT: jbe .LBB0_1 -; X86-Linux-NEXT: .LBB0_2: +; X86-Linux-NEXT: jbe .LBB0_2 +; X86-Linux-NEXT: .LBB0_1: ; X86-Linux-NEXT: subl $52, %esp ; X86-Linux-NEXT: .cfi_adjust_cfa_offset 52 ; X86-Linux-NEXT: leal {{[0-9]+}}(%esp), %eax @@ -51,18 +51,18 @@ define void @test_basic() #0 { ; X86-Linux-NEXT: addl $60, %esp ; X86-Linux-NEXT: .cfi_adjust_cfa_offset -60 ; X86-Linux-NEXT: retl -; X86-Linux-NEXT: .LBB0_1: +; X86-Linux-NEXT: .LBB0_2: ; X86-Linux-NEXT: pushl $0 ; X86-Linux-NEXT: pushl $44 ; X86-Linux-NEXT: calll __morestack ; X86-Linux-NEXT: retl -; X86-Linux-NEXT: jmp .LBB0_2 +; X86-Linux-NEXT: jmp .LBB0_1 ; ; X64-Linux-LABEL: test_basic: ; X64-Linux: # %bb.0: ; X64-Linux-NEXT: cmpq %fs:112, %rsp -; X64-Linux-NEXT: jbe .LBB0_1 -; X64-Linux-NEXT: .LBB0_2: +; X64-Linux-NEXT: jbe .LBB0_2 +; X64-Linux-NEXT: .LBB0_1: ; X64-Linux-NEXT: subq $40, %rsp ; X64-Linux-NEXT: .cfi_def_cfa_offset 48 ; X64-Linux-NEXT: movq %rsp, %rdi @@ -71,18 +71,18 @@ define void @test_basic() #0 { ; X64-Linux-NEXT: addq $40, %rsp ; X64-Linux-NEXT: .cfi_def_cfa_offset 8 ; X64-Linux-NEXT: retq -; X64-Linux-NEXT: .LBB0_1: +; X64-Linux-NEXT: .LBB0_2: ; X64-Linux-NEXT: movl $40, %r10d ; X64-Linux-NEXT: movl $0, %r11d ; X64-Linux-NEXT: callq __morestack ; X64-Linux-NEXT: retq -; X64-Linux-NEXT: jmp .LBB0_2 +; X64-Linux-NEXT: jmp .LBB0_1 ; ; X64-Linux-Large-LABEL: test_basic: ; X64-Linux-Large: # %bb.0: ; X64-Linux-Large-NEXT: cmpq %fs:112, %rsp -; X64-Linux-Large-NEXT: jbe .LBB0_1 -; X64-Linux-Large-NEXT: .LBB0_2: +; X64-Linux-Large-NEXT: jbe .LBB0_2 +; X64-Linux-Large-NEXT: .LBB0_1: ; X64-Linux-Large-NEXT: subq $40, %rsp ; X64-Linux-Large-NEXT: .cfi_def_cfa_offset 48 ; X64-Linux-Large-NEXT: movabsq $dummy_use, %rax @@ -92,18 +92,18 @@ define void @test_basic() #0 { ; X64-Linux-Large-NEXT: addq $40, %rsp ; X64-Linux-Large-NEXT: .cfi_def_cfa_offset 8 ; X64-Linux-Large-NEXT: retq -; X64-Linux-Large-NEXT: .LBB0_1: +; X64-Linux-Large-NEXT: .LBB0_2: ; X64-Linux-Large-NEXT: movl $40, %r10d ; X64-Linux-Large-NEXT: movl $0, %r11d ; X64-Linux-Large-NEXT: callq *__morestack_addr(%rip) ; X64-Linux-Large-NEXT: retq -; X64-Linux-Large-NEXT: jmp .LBB0_2 +; X64-Linux-Large-NEXT: jmp .LBB0_1 ; ; X32ABI-LABEL: test_basic: ; X32ABI: # %bb.0: ; X32ABI-NEXT: cmpl %fs:64, %esp -; X32ABI-NEXT: jbe .LBB0_1 -; X32ABI-NEXT: .LBB0_2: +; X32ABI-NEXT: jbe .LBB0_2 +; X32ABI-NEXT: .LBB0_1: ; X32ABI-NEXT: subl $40, %esp ; X32ABI-NEXT: .cfi_def_cfa_offset 48 ; X32ABI-NEXT: movl %esp, %edi @@ -112,19 +112,19 @@ define void @test_basic() #0 { ; X32ABI-NEXT: addl $40, %esp ; X32ABI-NEXT: .cfi_def_cfa_offset 8 ; X32ABI-NEXT: retq -; X32ABI-NEXT: .LBB0_1: +; X32ABI-NEXT: .LBB0_2: ; X32ABI-NEXT: movl $40, %r10d ; X32ABI-NEXT: movl $0, %r11d ; X32ABI-NEXT: callq __morestack ; X32ABI-NEXT: retq -; X32ABI-NEXT: jmp .LBB0_2 +; X32ABI-NEXT: jmp .LBB0_1 ; ; X86-Darwin-LABEL: test_basic: ; X86-Darwin: ## %bb.0: ; X86-Darwin-NEXT: movl $432, %ecx ## imm = 0x1B0 ; X86-Darwin-NEXT: cmpl %gs:(%ecx), %esp -; X86-Darwin-NEXT: jbe LBB0_1 -; X86-Darwin-NEXT: LBB0_2: +; X86-Darwin-NEXT: jbe LBB0_2 +; X86-Darwin-NEXT: LBB0_1: ; X86-Darwin-NEXT: subl $60, %esp ; X86-Darwin-NEXT: .cfi_def_cfa_offset 64 ; X86-Darwin-NEXT: leal {{[0-9]+}}(%esp), %eax @@ -133,18 +133,18 @@ define void @test_basic() #0 { ; X86-Darwin-NEXT: calll _dummy_use ; X86-Darwin-NEXT: addl $60, %esp ; X86-Darwin-NEXT: retl -; X86-Darwin-NEXT: LBB0_1: +; X86-Darwin-NEXT: LBB0_2: ; X86-Darwin-NEXT: pushl $0 ; X86-Darwin-NEXT: pushl $60 ; X86-Darwin-NEXT: calll ___morestack ; X86-Darwin-NEXT: retl -; X86-Darwin-NEXT: jmp LBB0_2 +; X86-Darwin-NEXT: jmp LBB0_1 ; ; X64-Darwin-LABEL: test_basic: ; X64-Darwin: ## %bb.0: ; X64-Darwin-NEXT: cmpq %gs:816, %rsp -; X64-Darwin-NEXT: jbe LBB0_1 -; X64-Darwin-NEXT: LBB0_2: +; X64-Darwin-NEXT: jbe LBB0_2 +; X64-Darwin-NEXT: LBB0_1: ; X64-Darwin-NEXT: subq $40, %rsp ; X64-Darwin-NEXT: .cfi_def_cfa_offset 48 ; X64-Darwin-NEXT: movq %rsp, %rdi @@ -152,18 +152,18 @@ define void @test_basic() #0 { ; X64-Darwin-NEXT: callq _dummy_use ; X64-Darwin-NEXT: addq $40, %rsp ; X64-Darwin-NEXT: retq -; X64-Darwin-NEXT: LBB0_1: +; X64-Darwin-NEXT: LBB0_2: ; X64-Darwin-NEXT: movl $40, %r10d ; X64-Darwin-NEXT: movl $0, %r11d ; X64-Darwin-NEXT: callq ___morestack ; X64-Darwin-NEXT: retq -; X64-Darwin-NEXT: jmp LBB0_2 +; X64-Darwin-NEXT: jmp LBB0_1 ; ; X86-MinGW-LABEL: test_basic: ; X86-MinGW: # %bb.0: ; X86-MinGW-NEXT: cmpl %fs:20, %esp -; X86-MinGW-NEXT: jbe LBB0_1 -; X86-MinGW-NEXT: LBB0_2: +; X86-MinGW-NEXT: jbe LBB0_2 +; X86-MinGW-NEXT: LBB0_1: ; X86-MinGW-NEXT: subl $40, %esp ; X86-MinGW-NEXT: .cfi_def_cfa_offset 44 ; X86-MinGW-NEXT: movl %esp, %eax @@ -175,18 +175,18 @@ define void @test_basic() #0 { ; X86-MinGW-NEXT: addl $48, %esp ; X86-MinGW-NEXT: .cfi_adjust_cfa_offset -48 ; X86-MinGW-NEXT: retl -; X86-MinGW-NEXT: LBB0_1: +; X86-MinGW-NEXT: LBB0_2: ; X86-MinGW-NEXT: pushl $0 ; X86-MinGW-NEXT: pushl $40 ; X86-MinGW-NEXT: calll ___morestack ; X86-MinGW-NEXT: retl -; X86-MinGW-NEXT: jmp LBB0_2 +; X86-MinGW-NEXT: jmp LBB0_1 ; ; X64-FreeBSD-LABEL: test_basic: ; X64-FreeBSD: # %bb.0: ; X64-FreeBSD-NEXT: cmpq %fs:24, %rsp -; X64-FreeBSD-NEXT: jbe .LBB0_1 -; X64-FreeBSD-NEXT: .LBB0_2: +; X64-FreeBSD-NEXT: jbe .LBB0_2 +; X64-FreeBSD-NEXT: .LBB0_1: ; X64-FreeBSD-NEXT: subq $40, %rsp ; X64-FreeBSD-NEXT: .cfi_def_cfa_offset 48 ; X64-FreeBSD-NEXT: movq %rsp, %rdi @@ -195,18 +195,18 @@ define void @test_basic() #0 { ; X64-FreeBSD-NEXT: addq $40, %rsp ; X64-FreeBSD-NEXT: .cfi_def_cfa_offset 8 ; X64-FreeBSD-NEXT: retq -; X64-FreeBSD-NEXT: .LBB0_1: +; X64-FreeBSD-NEXT: .LBB0_2: ; X64-FreeBSD-NEXT: movl $40, %r10d ; X64-FreeBSD-NEXT: movl $0, %r11d ; X64-FreeBSD-NEXT: callq __morestack ; X64-FreeBSD-NEXT: retq -; X64-FreeBSD-NEXT: jmp .LBB0_2 +; X64-FreeBSD-NEXT: jmp .LBB0_1 ; ; X86-DFlyBSD-LABEL: test_basic: ; X86-DFlyBSD: # %bb.0: ; X86-DFlyBSD-NEXT: cmpl %fs:16, %esp -; X86-DFlyBSD-NEXT: jbe .LBB0_1 -; X86-DFlyBSD-NEXT: .LBB0_2: +; X86-DFlyBSD-NEXT: jbe .LBB0_2 +; X86-DFlyBSD-NEXT: .LBB0_1: ; X86-DFlyBSD-NEXT: subl $40, %esp ; X86-DFlyBSD-NEXT: .cfi_def_cfa_offset 44 ; X86-DFlyBSD-NEXT: movl %esp, %eax @@ -218,18 +218,18 @@ define void @test_basic() #0 { ; X86-DFlyBSD-NEXT: addl $48, %esp ; X86-DFlyBSD-NEXT: .cfi_adjust_cfa_offset -48 ; X86-DFlyBSD-NEXT: retl -; X86-DFlyBSD-NEXT: .LBB0_1: +; X86-DFlyBSD-NEXT: .LBB0_2: ; X86-DFlyBSD-NEXT: pushl $0 ; X86-DFlyBSD-NEXT: pushl $40 ; X86-DFlyBSD-NEXT: calll __morestack ; X86-DFlyBSD-NEXT: retl -; X86-DFlyBSD-NEXT: jmp .LBB0_2 +; X86-DFlyBSD-NEXT: jmp .LBB0_1 ; ; X64-DFlyBSD-LABEL: test_basic: ; X64-DFlyBSD: # %bb.0: ; X64-DFlyBSD-NEXT: cmpq %fs:32, %rsp -; X64-DFlyBSD-NEXT: jbe .LBB0_1 -; X64-DFlyBSD-NEXT: .LBB0_2: +; X64-DFlyBSD-NEXT: jbe .LBB0_2 +; X64-DFlyBSD-NEXT: .LBB0_1: ; X64-DFlyBSD-NEXT: subq $40, %rsp ; X64-DFlyBSD-NEXT: .cfi_def_cfa_offset 48 ; X64-DFlyBSD-NEXT: movq %rsp, %rdi @@ -238,18 +238,18 @@ define void @test_basic() #0 { ; X64-DFlyBSD-NEXT: addq $40, %rsp ; X64-DFlyBSD-NEXT: .cfi_def_cfa_offset 8 ; X64-DFlyBSD-NEXT: retq -; X64-DFlyBSD-NEXT: .LBB0_1: +; X64-DFlyBSD-NEXT: .LBB0_2: ; X64-DFlyBSD-NEXT: movl $40, %r10d ; X64-DFlyBSD-NEXT: movl $0, %r11d ; X64-DFlyBSD-NEXT: callq __morestack ; X64-DFlyBSD-NEXT: retq -; X64-DFlyBSD-NEXT: jmp .LBB0_2 +; X64-DFlyBSD-NEXT: jmp .LBB0_1 ; ; X64-MinGW-LABEL: test_basic: ; X64-MinGW: # %bb.0: ; X64-MinGW-NEXT: cmpq %gs:40, %rsp -; X64-MinGW-NEXT: jbe .LBB0_1 -; X64-MinGW-NEXT: .LBB0_2: +; X64-MinGW-NEXT: jbe .LBB0_2 +; X64-MinGW-NEXT: .LBB0_1: ; X64-MinGW-NEXT: subq $72, %rsp ; X64-MinGW-NEXT: .seh_stackalloc 72 ; X64-MinGW-NEXT: .seh_endprologue @@ -261,12 +261,12 @@ define void @test_basic() #0 { ; X64-MinGW-NEXT: addq $72, %rsp ; X64-MinGW-NEXT: .seh_endepilogue ; X64-MinGW-NEXT: retq -; X64-MinGW-NEXT: .LBB0_1: +; X64-MinGW-NEXT: .LBB0_2: ; X64-MinGW-NEXT: movl $72, %r10d ; X64-MinGW-NEXT: movl $32, %r11d ; X64-MinGW-NEXT: callq __morestack ; X64-MinGW-NEXT: retq -; X64-MinGW-NEXT: jmp .LBB0_2 +; X64-MinGW-NEXT: jmp .LBB0_1 ; X64-MinGW-NEXT: .seh_endproc %mem = alloca i32, i32 10 call void @dummy_use (ptr %mem, i32 10) @@ -277,8 +277,8 @@ define i32 @test_nested(ptr nest %closure, i32 %other) #0 { ; X86-Linux-LABEL: test_nested: ; X86-Linux: # %bb.0: ; X86-Linux-NEXT: cmpl %gs:48, %esp -; X86-Linux-NEXT: jbe .LBB1_1 -; X86-Linux-NEXT: .LBB1_2: +; X86-Linux-NEXT: jbe .LBB1_2 +; X86-Linux-NEXT: .LBB1_1: ; X86-Linux-NEXT: pushl %esi ; X86-Linux-NEXT: .cfi_def_cfa_offset 8 ; X86-Linux-NEXT: subl $40, %esp @@ -302,19 +302,19 @@ define i32 @test_nested(ptr nest %closure, i32 %other) #0 { ; X86-Linux-NEXT: popl %esi ; X86-Linux-NEXT: .cfi_def_cfa_offset 4 ; X86-Linux-NEXT: retl -; X86-Linux-NEXT: .LBB1_1: +; X86-Linux-NEXT: .LBB1_2: ; X86-Linux-NEXT: .cfi_restore %esi ; X86-Linux-NEXT: pushl $4 ; X86-Linux-NEXT: pushl $44 ; X86-Linux-NEXT: calll __morestack ; X86-Linux-NEXT: retl -; X86-Linux-NEXT: jmp .LBB1_2 +; X86-Linux-NEXT: jmp .LBB1_1 ; ; X64-Linux-LABEL: test_nested: ; X64-Linux: # %bb.0: ; X64-Linux-NEXT: cmpq %fs:112, %rsp -; X64-Linux-NEXT: jbe .LBB1_1 -; X64-Linux-NEXT: .LBB1_2: +; X64-Linux-NEXT: jbe .LBB1_2 +; X64-Linux-NEXT: .LBB1_1: ; X64-Linux-NEXT: pushq %rbx ; X64-Linux-NEXT: .cfi_def_cfa_offset 16 ; X64-Linux-NEXT: subq $48, %rsp @@ -331,7 +331,7 @@ define i32 @test_nested(ptr nest %closure, i32 %other) #0 { ; X64-Linux-NEXT: popq %rbx ; X64-Linux-NEXT: .cfi_def_cfa_offset 8 ; X64-Linux-NEXT: retq -; X64-Linux-NEXT: .LBB1_1: +; X64-Linux-NEXT: .LBB1_2: ; X64-Linux-NEXT: .cfi_restore %rbx ; X64-Linux-NEXT: movq %r10, %rax ; X64-Linux-NEXT: movl $56, %r10d @@ -339,13 +339,13 @@ define i32 @test_nested(ptr nest %closure, i32 %other) #0 { ; X64-Linux-NEXT: callq __morestack ; X64-Linux-NEXT: retq ; X64-Linux-NEXT: movq %rax, %r10 -; X64-Linux-NEXT: jmp .LBB1_2 +; X64-Linux-NEXT: jmp .LBB1_1 ; ; X64-Linux-Large-LABEL: test_nested: ; X64-Linux-Large: # %bb.0: ; X64-Linux-Large-NEXT: cmpq %fs:112, %rsp -; X64-Linux-Large-NEXT: jbe .LBB1_1 -; X64-Linux-Large-NEXT: .LBB1_2: +; X64-Linux-Large-NEXT: jbe .LBB1_2 +; X64-Linux-Large-NEXT: .LBB1_1: ; X64-Linux-Large-NEXT: pushq %rbx ; X64-Linux-Large-NEXT: .cfi_def_cfa_offset 16 ; X64-Linux-Large-NEXT: subq $48, %rsp @@ -363,7 +363,7 @@ define i32 @test_nested(ptr nest %closure, i32 %other) #0 { ; X64-Linux-Large-NEXT: popq %rbx ; X64-Linux-Large-NEXT: .cfi_def_cfa_offset 8 ; X64-Linux-Large-NEXT: retq -; X64-Linux-Large-NEXT: .LBB1_1: +; X64-Linux-Large-NEXT: .LBB1_2: ; X64-Linux-Large-NEXT: .cfi_restore %rbx ; X64-Linux-Large-NEXT: movq %r10, %rax ; X64-Linux-Large-NEXT: movl $56, %r10d @@ -371,13 +371,13 @@ define i32 @test_nested(ptr nest %closure, i32 %other) #0 { ; X64-Linux-Large-NEXT: callq *__morestack_addr(%rip) ; X64-Linux-Large-NEXT: retq ; X64-Linux-Large-NEXT: movq %rax, %r10 -; X64-Linux-Large-NEXT: jmp .LBB1_2 +; X64-Linux-Large-NEXT: jmp .LBB1_1 ; ; X32ABI-LABEL: test_nested: ; X32ABI: # %bb.0: ; X32ABI-NEXT: cmpl %fs:64, %esp -; X32ABI-NEXT: jbe .LBB1_1 -; X32ABI-NEXT: .LBB1_2: +; X32ABI-NEXT: jbe .LBB1_2 +; X32ABI-NEXT: .LBB1_1: ; X32ABI-NEXT: pushq %rbx ; X32ABI-NEXT: .cfi_def_cfa_offset 16 ; X32ABI-NEXT: subl $48, %esp @@ -394,7 +394,7 @@ define i32 @test_nested(ptr nest %closure, i32 %other) #0 { ; X32ABI-NEXT: popq %rbx ; X32ABI-NEXT: .cfi_def_cfa_offset 8 ; X32ABI-NEXT: retq -; X32ABI-NEXT: .LBB1_1: +; X32ABI-NEXT: .LBB1_2: ; X32ABI-NEXT: .cfi_restore %rbx ; X32ABI-NEXT: movl %r10d, %eax ; X32ABI-NEXT: movl $56, %r10d @@ -402,14 +402,14 @@ define i32 @test_nested(ptr nest %closure, i32 %other) #0 { ; X32ABI-NEXT: callq __morestack ; X32ABI-NEXT: retq ; X32ABI-NEXT: movq %rax, %r10 -; X32ABI-NEXT: jmp .LBB1_2 +; X32ABI-NEXT: jmp .LBB1_1 ; ; X86-Darwin-LABEL: test_nested: ; X86-Darwin: ## %bb.0: ; X86-Darwin-NEXT: movl $432, %edx ## imm = 0x1B0 ; X86-Darwin-NEXT: cmpl %gs:(%edx), %esp -; X86-Darwin-NEXT: jbe LBB1_1 -; X86-Darwin-NEXT: LBB1_2: +; X86-Darwin-NEXT: jbe LBB1_2 +; X86-Darwin-NEXT: LBB1_1: ; X86-Darwin-NEXT: pushl %esi ; X86-Darwin-NEXT: .cfi_def_cfa_offset 8 ; X86-Darwin-NEXT: subl $56, %esp @@ -425,18 +425,18 @@ define i32 @test_nested(ptr nest %closure, i32 %other) #0 { ; X86-Darwin-NEXT: addl $56, %esp ; X86-Darwin-NEXT: popl %esi ; X86-Darwin-NEXT: retl -; X86-Darwin-NEXT: LBB1_1: +; X86-Darwin-NEXT: LBB1_2: ; X86-Darwin-NEXT: pushl $4 ; X86-Darwin-NEXT: pushl $60 ; X86-Darwin-NEXT: calll ___morestack ; X86-Darwin-NEXT: retl -; X86-Darwin-NEXT: jmp LBB1_2 +; X86-Darwin-NEXT: jmp LBB1_1 ; ; X64-Darwin-LABEL: test_nested: ; X64-Darwin: ## %bb.0: ; X64-Darwin-NEXT: cmpq %gs:816, %rsp -; X64-Darwin-NEXT: jbe LBB1_1 -; X64-Darwin-NEXT: LBB1_2: +; X64-Darwin-NEXT: jbe LBB1_2 +; X64-Darwin-NEXT: LBB1_1: ; X64-Darwin-NEXT: pushq %rbx ; X64-Darwin-NEXT: .cfi_def_cfa_offset 16 ; X64-Darwin-NEXT: subq $48, %rsp @@ -451,20 +451,20 @@ define i32 @test_nested(ptr nest %closure, i32 %other) #0 { ; X64-Darwin-NEXT: addq $48, %rsp ; X64-Darwin-NEXT: popq %rbx ; X64-Darwin-NEXT: retq -; X64-Darwin-NEXT: LBB1_1: +; X64-Darwin-NEXT: LBB1_2: ; X64-Darwin-NEXT: movq %r10, %rax ; X64-Darwin-NEXT: movl $56, %r10d ; X64-Darwin-NEXT: movl $0, %r11d ; X64-Darwin-NEXT: callq ___morestack ; X64-Darwin-NEXT: retq ; X64-Darwin-NEXT: movq %rax, %r10 -; X64-Darwin-NEXT: jmp LBB1_2 +; X64-Darwin-NEXT: jmp LBB1_1 ; ; X86-MinGW-LABEL: test_nested: ; X86-MinGW: # %bb.0: ; X86-MinGW-NEXT: cmpl %fs:20, %esp -; X86-MinGW-NEXT: jbe LBB1_1 -; X86-MinGW-NEXT: LBB1_2: +; X86-MinGW-NEXT: jbe LBB1_2 +; X86-MinGW-NEXT: LBB1_1: ; X86-MinGW-NEXT: pushl %esi ; X86-MinGW-NEXT: .cfi_def_cfa_offset 8 ; X86-MinGW-NEXT: subl $40, %esp @@ -484,20 +484,20 @@ define i32 @test_nested(ptr nest %closure, i32 %other) #0 { ; X86-MinGW-NEXT: addl $40, %esp ; X86-MinGW-NEXT: popl %esi ; X86-MinGW-NEXT: retl -; X86-MinGW-NEXT: LBB1_1: +; X86-MinGW-NEXT: LBB1_2: ; X86-MinGW-NEXT: .cfi_def_cfa_offset 4 ; X86-MinGW-NEXT: .cfi_restore %esi ; X86-MinGW-NEXT: pushl $4 ; X86-MinGW-NEXT: pushl $44 ; X86-MinGW-NEXT: calll ___morestack ; X86-MinGW-NEXT: retl -; X86-MinGW-NEXT: jmp LBB1_2 +; X86-MinGW-NEXT: jmp LBB1_1 ; ; X64-FreeBSD-LABEL: test_nested: ; X64-FreeBSD: # %bb.0: ; X64-FreeBSD-NEXT: cmpq %fs:24, %rsp -; X64-FreeBSD-NEXT: jbe .LBB1_1 -; X64-FreeBSD-NEXT: .LBB1_2: +; X64-FreeBSD-NEXT: jbe .LBB1_2 +; X64-FreeBSD-NEXT: .LBB1_1: ; X64-FreeBSD-NEXT: pushq %rbx ; X64-FreeBSD-NEXT: .cfi_def_cfa_offset 16 ; X64-FreeBSD-NEXT: subq $48, %rsp @@ -514,7 +514,7 @@ define i32 @test_nested(ptr nest %closure, i32 %other) #0 { ; X64-FreeBSD-NEXT: popq %rbx ; X64-FreeBSD-NEXT: .cfi_def_cfa_offset 8 ; X64-FreeBSD-NEXT: retq -; X64-FreeBSD-NEXT: .LBB1_1: +; X64-FreeBSD-NEXT: .LBB1_2: ; X64-FreeBSD-NEXT: .cfi_restore %rbx ; X64-FreeBSD-NEXT: movq %r10, %rax ; X64-FreeBSD-NEXT: movl $56, %r10d @@ -522,13 +522,13 @@ define i32 @test_nested(ptr nest %closure, i32 %other) #0 { ; X64-FreeBSD-NEXT: callq __morestack ; X64-FreeBSD-NEXT: retq ; X64-FreeBSD-NEXT: movq %rax, %r10 -; X64-FreeBSD-NEXT: jmp .LBB1_2 +; X64-FreeBSD-NEXT: jmp .LBB1_1 ; ; X86-DFlyBSD-LABEL: test_nested: ; X86-DFlyBSD: # %bb.0: ; X86-DFlyBSD-NEXT: cmpl %fs:16, %esp -; X86-DFlyBSD-NEXT: jbe .LBB1_1 -; X86-DFlyBSD-NEXT: .LBB1_2: +; X86-DFlyBSD-NEXT: jbe .LBB1_2 +; X86-DFlyBSD-NEXT: .LBB1_1: ; X86-DFlyBSD-NEXT: pushl %esi ; X86-DFlyBSD-NEXT: .cfi_def_cfa_offset 8 ; X86-DFlyBSD-NEXT: subl $40, %esp @@ -550,19 +550,19 @@ define i32 @test_nested(ptr nest %closure, i32 %other) #0 { ; X86-DFlyBSD-NEXT: popl %esi ; X86-DFlyBSD-NEXT: .cfi_def_cfa_offset 4 ; X86-DFlyBSD-NEXT: retl -; X86-DFlyBSD-NEXT: .LBB1_1: +; X86-DFlyBSD-NEXT: .LBB1_2: ; X86-DFlyBSD-NEXT: .cfi_restore %esi ; X86-DFlyBSD-NEXT: pushl $4 ; X86-DFlyBSD-NEXT: pushl $44 ; X86-DFlyBSD-NEXT: calll __morestack ; X86-DFlyBSD-NEXT: retl -; X86-DFlyBSD-NEXT: jmp .LBB1_2 +; X86-DFlyBSD-NEXT: jmp .LBB1_1 ; ; X64-DFlyBSD-LABEL: test_nested: ; X64-DFlyBSD: # %bb.0: ; X64-DFlyBSD-NEXT: cmpq %fs:32, %rsp -; X64-DFlyBSD-NEXT: jbe .LBB1_1 -; X64-DFlyBSD-NEXT: .LBB1_2: +; X64-DFlyBSD-NEXT: jbe .LBB1_2 +; X64-DFlyBSD-NEXT: .LBB1_1: ; X64-DFlyBSD-NEXT: pushq %rbx ; X64-DFlyBSD-NEXT: .cfi_def_cfa_offset 16 ; X64-DFlyBSD-NEXT: subq $48, %rsp @@ -579,7 +579,7 @@ define i32 @test_nested(ptr nest %closure, i32 %other) #0 { ; X64-DFlyBSD-NEXT: popq %rbx ; X64-DFlyBSD-NEXT: .cfi_def_cfa_offset 8 ; X64-DFlyBSD-NEXT: retq -; X64-DFlyBSD-NEXT: .LBB1_1: +; X64-DFlyBSD-NEXT: .LBB1_2: ; X64-DFlyBSD-NEXT: .cfi_restore %rbx ; X64-DFlyBSD-NEXT: movq %r10, %rax ; X64-DFlyBSD-NEXT: movl $56, %r10d @@ -587,13 +587,13 @@ define i32 @test_nested(ptr nest %closure, i32 %other) #0 { ; X64-DFlyBSD-NEXT: callq __morestack ; X64-DFlyBSD-NEXT: retq ; X64-DFlyBSD-NEXT: movq %rax, %r10 -; X64-DFlyBSD-NEXT: jmp .LBB1_2 +; X64-DFlyBSD-NEXT: jmp .LBB1_1 ; ; X64-MinGW-LABEL: test_nested: ; X64-MinGW: # %bb.0: ; X64-MinGW-NEXT: cmpq %gs:40, %rsp -; X64-MinGW-NEXT: jbe .LBB1_1 -; X64-MinGW-NEXT: .LBB1_2: +; X64-MinGW-NEXT: jbe .LBB1_2 +; X64-MinGW-NEXT: .LBB1_1: ; X64-MinGW-NEXT: pushq %rsi ; X64-MinGW-NEXT: .seh_pushreg %rsi ; X64-MinGW-NEXT: subq $80, %rsp @@ -610,14 +610,14 @@ define i32 @test_nested(ptr nest %closure, i32 %other) #0 { ; X64-MinGW-NEXT: popq %rsi ; X64-MinGW-NEXT: .seh_endepilogue ; X64-MinGW-NEXT: retq -; X64-MinGW-NEXT: .LBB1_1: +; X64-MinGW-NEXT: .LBB1_2: ; X64-MinGW-NEXT: movq %r10, %rax ; X64-MinGW-NEXT: movl $88, %r10d ; X64-MinGW-NEXT: movl $32, %r11d ; X64-MinGW-NEXT: callq __morestack ; X64-MinGW-NEXT: retq ; X64-MinGW-NEXT: movq %rax, %r10 -; X64-MinGW-NEXT: jmp .LBB1_2 +; X64-MinGW-NEXT: jmp .LBB1_1 ; X64-MinGW-NEXT: .seh_endproc %addend = load i32 , ptr %closure %result = add i32 %other, %addend @@ -631,8 +631,8 @@ define void @test_large() #0 { ; X86-Linux: # %bb.0: ; X86-Linux-NEXT: leal -{{[0-9]+}}(%esp), %ecx ; X86-Linux-NEXT: cmpl %gs:48, %ecx -; X86-Linux-NEXT: jbe .LBB2_1 -; X86-Linux-NEXT: .LBB2_2: +; X86-Linux-NEXT: jbe .LBB2_2 +; X86-Linux-NEXT: .LBB2_1: ; X86-Linux-NEXT: subl $40020, %esp # imm = 0x9C54 ; X86-Linux-NEXT: .cfi_adjust_cfa_offset 40020 ; X86-Linux-NEXT: leal {{[0-9]+}}(%esp), %eax @@ -644,19 +644,19 @@ define void @test_large() #0 { ; X86-Linux-NEXT: addl $40028, %esp # imm = 0x9C5C ; X86-Linux-NEXT: .cfi_adjust_cfa_offset -40028 ; X86-Linux-NEXT: retl -; X86-Linux-NEXT: .LBB2_1: +; X86-Linux-NEXT: .LBB2_2: ; X86-Linux-NEXT: pushl $0 ; X86-Linux-NEXT: pushl $40012 # imm = 0x9C4C ; X86-Linux-NEXT: calll __morestack ; X86-Linux-NEXT: retl -; X86-Linux-NEXT: jmp .LBB2_2 +; X86-Linux-NEXT: jmp .LBB2_1 ; ; X64-Linux-LABEL: test_large: ; X64-Linux: # %bb.0: ; X64-Linux-NEXT: leaq -{{[0-9]+}}(%rsp), %r11 ; X64-Linux-NEXT: cmpq %fs:112, %r11 -; X64-Linux-NEXT: jbe .LBB2_1 -; X64-Linux-NEXT: .LBB2_2: +; X64-Linux-NEXT: jbe .LBB2_2 +; X64-Linux-NEXT: .LBB2_1: ; X64-Linux-NEXT: subq $40008, %rsp # imm = 0x9C48 ; X64-Linux-NEXT: .cfi_def_cfa_offset 40016 ; X64-Linux-NEXT: leaq {{[0-9]+}}(%rsp), %rdi @@ -665,19 +665,19 @@ define void @test_large() #0 { ; X64-Linux-NEXT: addq $40008, %rsp # imm = 0x9C48 ; X64-Linux-NEXT: .cfi_def_cfa_offset 8 ; X64-Linux-NEXT: retq -; X64-Linux-NEXT: .LBB2_1: +; X64-Linux-NEXT: .LBB2_2: ; X64-Linux-NEXT: movl $40008, %r10d # imm = 0x9C48 ; X64-Linux-NEXT: movl $0, %r11d ; X64-Linux-NEXT: callq __morestack ; X64-Linux-NEXT: retq -; X64-Linux-NEXT: jmp .LBB2_2 +; X64-Linux-NEXT: jmp .LBB2_1 ; ; X64-Linux-Large-LABEL: test_large: ; X64-Linux-Large: # %bb.0: ; X64-Linux-Large-NEXT: leaq -{{[0-9]+}}(%rsp), %r11 ; X64-Linux-Large-NEXT: cmpq %fs:112, %r11 -; X64-Linux-Large-NEXT: jbe .LBB2_1 -; X64-Linux-Large-NEXT: .LBB2_2: +; X64-Linux-Large-NEXT: jbe .LBB2_2 +; X64-Linux-Large-NEXT: .LBB2_1: ; X64-Linux-Large-NEXT: subq $40008, %rsp # imm = 0x9C48 ; X64-Linux-Large-NEXT: .cfi_def_cfa_offset 40016 ; X64-Linux-Large-NEXT: movabsq $dummy_use, %rax @@ -687,19 +687,19 @@ define void @test_large() #0 { ; X64-Linux-Large-NEXT: addq $40008, %rsp # imm = 0x9C48 ; X64-Linux-Large-NEXT: .cfi_def_cfa_offset 8 ; X64-Linux-Large-NEXT: retq -; X64-Linux-Large-NEXT: .LBB2_1: +; X64-Linux-Large-NEXT: .LBB2_2: ; X64-Linux-Large-NEXT: movl $40008, %r10d # imm = 0x9C48 ; X64-Linux-Large-NEXT: movl $0, %r11d ; X64-Linux-Large-NEXT: callq *__morestack_addr(%rip) ; X64-Linux-Large-NEXT: retq -; X64-Linux-Large-NEXT: jmp .LBB2_2 +; X64-Linux-Large-NEXT: jmp .LBB2_1 ; ; X32ABI-LABEL: test_large: ; X32ABI: # %bb.0: ; X32ABI-NEXT: leal -{{[0-9]+}}(%rsp), %r11d ; X32ABI-NEXT: cmpl %fs:64, %r11d -; X32ABI-NEXT: jbe .LBB2_1 -; X32ABI-NEXT: .LBB2_2: +; X32ABI-NEXT: jbe .LBB2_2 +; X32ABI-NEXT: .LBB2_1: ; X32ABI-NEXT: subl $40008, %esp # imm = 0x9C48 ; X32ABI-NEXT: .cfi_def_cfa_offset 40016 ; X32ABI-NEXT: leal {{[0-9]+}}(%rsp), %edi @@ -708,20 +708,20 @@ define void @test_large() #0 { ; X32ABI-NEXT: addl $40008, %esp # imm = 0x9C48 ; X32ABI-NEXT: .cfi_def_cfa_offset 8 ; X32ABI-NEXT: retq -; X32ABI-NEXT: .LBB2_1: +; X32ABI-NEXT: .LBB2_2: ; X32ABI-NEXT: movl $40008, %r10d # imm = 0x9C48 ; X32ABI-NEXT: movl $0, %r11d ; X32ABI-NEXT: callq __morestack ; X32ABI-NEXT: retq -; X32ABI-NEXT: jmp .LBB2_2 +; X32ABI-NEXT: jmp .LBB2_1 ; ; X86-Darwin-LABEL: test_large: ; X86-Darwin: ## %bb.0: ; X86-Darwin-NEXT: leal -{{[0-9]+}}(%esp), %ecx ; X86-Darwin-NEXT: movl $432, %eax ## imm = 0x1B0 ; X86-Darwin-NEXT: cmpl %gs:(%eax), %ecx -; X86-Darwin-NEXT: jbe LBB2_1 -; X86-Darwin-NEXT: LBB2_2: +; X86-Darwin-NEXT: jbe LBB2_2 +; X86-Darwin-NEXT: LBB2_1: ; X86-Darwin-NEXT: subl $40012, %esp ## imm = 0x9C4C ; X86-Darwin-NEXT: .cfi_def_cfa_offset 40016 ; X86-Darwin-NEXT: leal {{[0-9]+}}(%esp), %eax @@ -730,19 +730,19 @@ define void @test_large() #0 { ; X86-Darwin-NEXT: calll _dummy_use ; X86-Darwin-NEXT: addl $40012, %esp ## imm = 0x9C4C ; X86-Darwin-NEXT: retl -; X86-Darwin-NEXT: LBB2_1: +; X86-Darwin-NEXT: LBB2_2: ; X86-Darwin-NEXT: pushl $0 ; X86-Darwin-NEXT: pushl $40012 ## imm = 0x9C4C ; X86-Darwin-NEXT: calll ___morestack ; X86-Darwin-NEXT: retl -; X86-Darwin-NEXT: jmp LBB2_2 +; X86-Darwin-NEXT: jmp LBB2_1 ; ; X64-Darwin-LABEL: test_large: ; X64-Darwin: ## %bb.0: ; X64-Darwin-NEXT: leaq -{{[0-9]+}}(%rsp), %r11 ; X64-Darwin-NEXT: cmpq %gs:816, %r11 -; X64-Darwin-NEXT: jbe LBB2_1 -; X64-Darwin-NEXT: LBB2_2: +; X64-Darwin-NEXT: jbe LBB2_2 +; X64-Darwin-NEXT: LBB2_1: ; X64-Darwin-NEXT: subq $40008, %rsp ## imm = 0x9C48 ; X64-Darwin-NEXT: .cfi_def_cfa_offset 40016 ; X64-Darwin-NEXT: leaq {{[0-9]+}}(%rsp), %rdi @@ -750,19 +750,19 @@ define void @test_large() #0 { ; X64-Darwin-NEXT: callq _dummy_use ; X64-Darwin-NEXT: addq $40008, %rsp ## imm = 0x9C48 ; X64-Darwin-NEXT: retq -; X64-Darwin-NEXT: LBB2_1: +; X64-Darwin-NEXT: LBB2_2: ; X64-Darwin-NEXT: movl $40008, %r10d ## imm = 0x9C48 ; X64-Darwin-NEXT: movl $0, %r11d ; X64-Darwin-NEXT: callq ___morestack ; X64-Darwin-NEXT: retq -; X64-Darwin-NEXT: jmp LBB2_2 +; X64-Darwin-NEXT: jmp LBB2_1 ; ; X86-MinGW-LABEL: test_large: ; X86-MinGW: # %bb.0: ; X86-MinGW-NEXT: leal -{{[0-9]+}}(%esp), %ecx ; X86-MinGW-NEXT: cmpl %fs:20, %ecx -; X86-MinGW-NEXT: jbe LBB2_1 -; X86-MinGW-NEXT: LBB2_2: +; X86-MinGW-NEXT: jbe LBB2_2 +; X86-MinGW-NEXT: LBB2_1: ; X86-MinGW-NEXT: movl $40000, %eax # imm = 0x9C40 ; X86-MinGW-NEXT: calll __alloca ; X86-MinGW-NEXT: .cfi_def_cfa_offset 40004 @@ -775,19 +775,19 @@ define void @test_large() #0 { ; X86-MinGW-NEXT: addl $40008, %esp # imm = 0x9C48 ; X86-MinGW-NEXT: .cfi_adjust_cfa_offset -40008 ; X86-MinGW-NEXT: retl -; X86-MinGW-NEXT: LBB2_1: +; X86-MinGW-NEXT: LBB2_2: ; X86-MinGW-NEXT: pushl $0 ; X86-MinGW-NEXT: pushl $40000 # imm = 0x9C40 ; X86-MinGW-NEXT: calll ___morestack ; X86-MinGW-NEXT: retl -; X86-MinGW-NEXT: jmp LBB2_2 +; X86-MinGW-NEXT: jmp LBB2_1 ; ; X64-FreeBSD-LABEL: test_large: ; X64-FreeBSD: # %bb.0: ; X64-FreeBSD-NEXT: leaq -{{[0-9]+}}(%rsp), %r11 ; X64-FreeBSD-NEXT: cmpq %fs:24, %r11 -; X64-FreeBSD-NEXT: jbe .LBB2_1 -; X64-FreeBSD-NEXT: .LBB2_2: +; X64-FreeBSD-NEXT: jbe .LBB2_2 +; X64-FreeBSD-NEXT: .LBB2_1: ; X64-FreeBSD-NEXT: subq $40008, %rsp # imm = 0x9C48 ; X64-FreeBSD-NEXT: .cfi_def_cfa_offset 40016 ; X64-FreeBSD-NEXT: leaq {{[0-9]+}}(%rsp), %rdi @@ -796,19 +796,19 @@ define void @test_large() #0 { ; X64-FreeBSD-NEXT: addq $40008, %rsp # imm = 0x9C48 ; X64-FreeBSD-NEXT: .cfi_def_cfa_offset 8 ; X64-FreeBSD-NEXT: retq -; X64-FreeBSD-NEXT: .LBB2_1: +; X64-FreeBSD-NEXT: .LBB2_2: ; X64-FreeBSD-NEXT: movl $40008, %r10d # imm = 0x9C48 ; X64-FreeBSD-NEXT: movl $0, %r11d ; X64-FreeBSD-NEXT: callq __morestack ; X64-FreeBSD-NEXT: retq -; X64-FreeBSD-NEXT: jmp .LBB2_2 +; X64-FreeBSD-NEXT: jmp .LBB2_1 ; ; X86-DFlyBSD-LABEL: test_large: ; X86-DFlyBSD: # %bb.0: ; X86-DFlyBSD-NEXT: leal -{{[0-9]+}}(%esp), %ecx ; X86-DFlyBSD-NEXT: cmpl %fs:16, %ecx -; X86-DFlyBSD-NEXT: jbe .LBB2_1 -; X86-DFlyBSD-NEXT: .LBB2_2: +; X86-DFlyBSD-NEXT: jbe .LBB2_2 +; X86-DFlyBSD-NEXT: .LBB2_1: ; X86-DFlyBSD-NEXT: subl $40000, %esp # imm = 0x9C40 ; X86-DFlyBSD-NEXT: .cfi_def_cfa_offset 40004 ; X86-DFlyBSD-NEXT: movl %esp, %eax @@ -820,19 +820,19 @@ define void @test_large() #0 { ; X86-DFlyBSD-NEXT: addl $40008, %esp # imm = 0x9C48 ; X86-DFlyBSD-NEXT: .cfi_adjust_cfa_offset -40008 ; X86-DFlyBSD-NEXT: retl -; X86-DFlyBSD-NEXT: .LBB2_1: +; X86-DFlyBSD-NEXT: .LBB2_2: ; X86-DFlyBSD-NEXT: pushl $0 ; X86-DFlyBSD-NEXT: pushl $40000 # imm = 0x9C40 ; X86-DFlyBSD-NEXT: calll __morestack ; X86-DFlyBSD-NEXT: retl -; X86-DFlyBSD-NEXT: jmp .LBB2_2 +; X86-DFlyBSD-NEXT: jmp .LBB2_1 ; ; X64-DFlyBSD-LABEL: test_large: ; X64-DFlyBSD: # %bb.0: ; X64-DFlyBSD-NEXT: leaq -{{[0-9]+}}(%rsp), %r11 ; X64-DFlyBSD-NEXT: cmpq %fs:32, %r11 -; X64-DFlyBSD-NEXT: jbe .LBB2_1 -; X64-DFlyBSD-NEXT: .LBB2_2: +; X64-DFlyBSD-NEXT: jbe .LBB2_2 +; X64-DFlyBSD-NEXT: .LBB2_1: ; X64-DFlyBSD-NEXT: subq $40008, %rsp # imm = 0x9C48 ; X64-DFlyBSD-NEXT: .cfi_def_cfa_offset 40016 ; X64-DFlyBSD-NEXT: leaq {{[0-9]+}}(%rsp), %rdi @@ -841,19 +841,19 @@ define void @test_large() #0 { ; X64-DFlyBSD-NEXT: addq $40008, %rsp # imm = 0x9C48 ; X64-DFlyBSD-NEXT: .cfi_def_cfa_offset 8 ; X64-DFlyBSD-NEXT: retq -; X64-DFlyBSD-NEXT: .LBB2_1: +; X64-DFlyBSD-NEXT: .LBB2_2: ; X64-DFlyBSD-NEXT: movl $40008, %r10d # imm = 0x9C48 ; X64-DFlyBSD-NEXT: movl $0, %r11d ; X64-DFlyBSD-NEXT: callq __morestack ; X64-DFlyBSD-NEXT: retq -; X64-DFlyBSD-NEXT: jmp .LBB2_2 +; X64-DFlyBSD-NEXT: jmp .LBB2_1 ; ; X64-MinGW-LABEL: test_large: ; X64-MinGW: # %bb.0: ; X64-MinGW-NEXT: leaq -{{[0-9]+}}(%rsp), %r11 ; X64-MinGW-NEXT: cmpq %gs:40, %r11 -; X64-MinGW-NEXT: jbe .LBB2_1 -; X64-MinGW-NEXT: .LBB2_2: +; X64-MinGW-NEXT: jbe .LBB2_2 +; X64-MinGW-NEXT: .LBB2_1: ; X64-MinGW-NEXT: movl $40040, %eax # imm = 0x9C68 ; X64-MinGW-NEXT: callq ___chkstk_ms ; X64-MinGW-NEXT: subq %rax, %rsp @@ -867,12 +867,12 @@ define void @test_large() #0 { ; X64-MinGW-NEXT: addq $40040, %rsp # imm = 0x9C68 ; X64-MinGW-NEXT: .seh_endepilogue ; X64-MinGW-NEXT: retq -; X64-MinGW-NEXT: .LBB2_1: +; X64-MinGW-NEXT: .LBB2_2: ; X64-MinGW-NEXT: movl $40040, %r10d # imm = 0x9C68 ; X64-MinGW-NEXT: movl $32, %r11d ; X64-MinGW-NEXT: callq __morestack ; X64-MinGW-NEXT: retq -; X64-MinGW-NEXT: jmp .LBB2_2 +; X64-MinGW-NEXT: jmp .LBB2_1 ; X64-MinGW-NEXT: .seh_endproc %mem = alloca i32, i32 10000 call void @dummy_use (ptr %mem, i32 3) @@ -883,8 +883,8 @@ define fastcc void @test_fastcc() #0 { ; X86-Linux-LABEL: test_fastcc: ; X86-Linux: # %bb.0: ; X86-Linux-NEXT: cmpl %gs:48, %esp -; X86-Linux-NEXT: jbe .LBB3_1 -; X86-Linux-NEXT: .LBB3_2: +; X86-Linux-NEXT: jbe .LBB3_2 +; X86-Linux-NEXT: .LBB3_1: ; X86-Linux-NEXT: subl $52, %esp ; X86-Linux-NEXT: .cfi_adjust_cfa_offset 52 ; X86-Linux-NEXT: leal {{[0-9]+}}(%esp), %eax @@ -896,18 +896,18 @@ define fastcc void @test_fastcc() #0 { ; X86-Linux-NEXT: addl $60, %esp ; X86-Linux-NEXT: .cfi_adjust_cfa_offset -60 ; X86-Linux-NEXT: retl -; X86-Linux-NEXT: .LBB3_1: +; X86-Linux-NEXT: .LBB3_2: ; X86-Linux-NEXT: pushl $0 ; X86-Linux-NEXT: pushl $44 ; X86-Linux-NEXT: calll __morestack ; X86-Linux-NEXT: retl -; X86-Linux-NEXT: jmp .LBB3_2 +; X86-Linux-NEXT: jmp .LBB3_1 ; ; X64-Linux-LABEL: test_fastcc: ; X64-Linux: # %bb.0: ; X64-Linux-NEXT: cmpq %fs:112, %rsp -; X64-Linux-NEXT: jbe .LBB3_1 -; X64-Linux-NEXT: .LBB3_2: +; X64-Linux-NEXT: jbe .LBB3_2 +; X64-Linux-NEXT: .LBB3_1: ; X64-Linux-NEXT: subq $40, %rsp ; X64-Linux-NEXT: .cfi_def_cfa_offset 48 ; X64-Linux-NEXT: movq %rsp, %rdi @@ -916,18 +916,18 @@ define fastcc void @test_fastcc() #0 { ; X64-Linux-NEXT: addq $40, %rsp ; X64-Linux-NEXT: .cfi_def_cfa_offset 8 ; X64-Linux-NEXT: retq -; X64-Linux-NEXT: .LBB3_1: +; X64-Linux-NEXT: .LBB3_2: ; X64-Linux-NEXT: movl $40, %r10d ; X64-Linux-NEXT: movl $0, %r11d ; X64-Linux-NEXT: callq __morestack ; X64-Linux-NEXT: retq -; X64-Linux-NEXT: jmp .LBB3_2 +; X64-Linux-NEXT: jmp .LBB3_1 ; ; X64-Linux-Large-LABEL: test_fastcc: ; X64-Linux-Large: # %bb.0: ; X64-Linux-Large-NEXT: cmpq %fs:112, %rsp -; X64-Linux-Large-NEXT: jbe .LBB3_1 -; X64-Linux-Large-NEXT: .LBB3_2: +; X64-Linux-Large-NEXT: jbe .LBB3_2 +; X64-Linux-Large-NEXT: .LBB3_1: ; X64-Linux-Large-NEXT: subq $40, %rsp ; X64-Linux-Large-NEXT: .cfi_def_cfa_offset 48 ; X64-Linux-Large-NEXT: movabsq $dummy_use, %rax @@ -937,18 +937,18 @@ define fastcc void @test_fastcc() #0 { ; X64-Linux-Large-NEXT: addq $40, %rsp ; X64-Linux-Large-NEXT: .cfi_def_cfa_offset 8 ; X64-Linux-Large-NEXT: retq -; X64-Linux-Large-NEXT: .LBB3_1: +; X64-Linux-Large-NEXT: .LBB3_2: ; X64-Linux-Large-NEXT: movl $40, %r10d ; X64-Linux-Large-NEXT: movl $0, %r11d ; X64-Linux-Large-NEXT: callq *__morestack_addr(%rip) ; X64-Linux-Large-NEXT: retq -; X64-Linux-Large-NEXT: jmp .LBB3_2 +; X64-Linux-Large-NEXT: jmp .LBB3_1 ; ; X32ABI-LABEL: test_fastcc: ; X32ABI: # %bb.0: ; X32ABI-NEXT: cmpl %fs:64, %esp -; X32ABI-NEXT: jbe .LBB3_1 -; X32ABI-NEXT: .LBB3_2: +; X32ABI-NEXT: jbe .LBB3_2 +; X32ABI-NEXT: .LBB3_1: ; X32ABI-NEXT: subl $40, %esp ; X32ABI-NEXT: .cfi_def_cfa_offset 48 ; X32ABI-NEXT: movl %esp, %edi @@ -957,19 +957,19 @@ define fastcc void @test_fastcc() #0 { ; X32ABI-NEXT: addl $40, %esp ; X32ABI-NEXT: .cfi_def_cfa_offset 8 ; X32ABI-NEXT: retq -; X32ABI-NEXT: .LBB3_1: +; X32ABI-NEXT: .LBB3_2: ; X32ABI-NEXT: movl $40, %r10d ; X32ABI-NEXT: movl $0, %r11d ; X32ABI-NEXT: callq __morestack ; X32ABI-NEXT: retq -; X32ABI-NEXT: jmp .LBB3_2 +; X32ABI-NEXT: jmp .LBB3_1 ; ; X86-Darwin-LABEL: test_fastcc: ; X86-Darwin: ## %bb.0: ; X86-Darwin-NEXT: movl $432, %eax ## imm = 0x1B0 ; X86-Darwin-NEXT: cmpl %gs:(%eax), %esp -; X86-Darwin-NEXT: jbe LBB3_1 -; X86-Darwin-NEXT: LBB3_2: +; X86-Darwin-NEXT: jbe LBB3_2 +; X86-Darwin-NEXT: LBB3_1: ; X86-Darwin-NEXT: subl $60, %esp ; X86-Darwin-NEXT: .cfi_def_cfa_offset 64 ; X86-Darwin-NEXT: leal {{[0-9]+}}(%esp), %eax @@ -978,18 +978,18 @@ define fastcc void @test_fastcc() #0 { ; X86-Darwin-NEXT: calll _dummy_use ; X86-Darwin-NEXT: addl $60, %esp ; X86-Darwin-NEXT: retl -; X86-Darwin-NEXT: LBB3_1: +; X86-Darwin-NEXT: LBB3_2: ; X86-Darwin-NEXT: pushl $0 ; X86-Darwin-NEXT: pushl $60 ; X86-Darwin-NEXT: calll ___morestack ; X86-Darwin-NEXT: retl -; X86-Darwin-NEXT: jmp LBB3_2 +; X86-Darwin-NEXT: jmp LBB3_1 ; ; X64-Darwin-LABEL: test_fastcc: ; X64-Darwin: ## %bb.0: ; X64-Darwin-NEXT: cmpq %gs:816, %rsp -; X64-Darwin-NEXT: jbe LBB3_1 -; X64-Darwin-NEXT: LBB3_2: +; X64-Darwin-NEXT: jbe LBB3_2 +; X64-Darwin-NEXT: LBB3_1: ; X64-Darwin-NEXT: subq $40, %rsp ; X64-Darwin-NEXT: .cfi_def_cfa_offset 48 ; X64-Darwin-NEXT: movq %rsp, %rdi @@ -997,18 +997,18 @@ define fastcc void @test_fastcc() #0 { ; X64-Darwin-NEXT: callq _dummy_use ; X64-Darwin-NEXT: addq $40, %rsp ; X64-Darwin-NEXT: retq -; X64-Darwin-NEXT: LBB3_1: +; X64-Darwin-NEXT: LBB3_2: ; X64-Darwin-NEXT: movl $40, %r10d ; X64-Darwin-NEXT: movl $0, %r11d ; X64-Darwin-NEXT: callq ___morestack ; X64-Darwin-NEXT: retq -; X64-Darwin-NEXT: jmp LBB3_2 +; X64-Darwin-NEXT: jmp LBB3_1 ; ; X86-MinGW-LABEL: test_fastcc: ; X86-MinGW: # %bb.0: ; X86-MinGW-NEXT: cmpl %fs:20, %esp -; X86-MinGW-NEXT: jbe LBB3_1 -; X86-MinGW-NEXT: LBB3_2: +; X86-MinGW-NEXT: jbe LBB3_2 +; X86-MinGW-NEXT: LBB3_1: ; X86-MinGW-NEXT: subl $40, %esp ; X86-MinGW-NEXT: .cfi_def_cfa_offset 44 ; X86-MinGW-NEXT: movl %esp, %eax @@ -1020,18 +1020,18 @@ define fastcc void @test_fastcc() #0 { ; X86-MinGW-NEXT: addl $48, %esp ; X86-MinGW-NEXT: .cfi_adjust_cfa_offset -48 ; X86-MinGW-NEXT: retl -; X86-MinGW-NEXT: LBB3_1: +; X86-MinGW-NEXT: LBB3_2: ; X86-MinGW-NEXT: pushl $0 ; X86-MinGW-NEXT: pushl $40 ; X86-MinGW-NEXT: calll ___morestack ; X86-MinGW-NEXT: retl -; X86-MinGW-NEXT: jmp LBB3_2 +; X86-MinGW-NEXT: jmp LBB3_1 ; ; X64-FreeBSD-LABEL: test_fastcc: ; X64-FreeBSD: # %bb.0: ; X64-FreeBSD-NEXT: cmpq %fs:24, %rsp -; X64-FreeBSD-NEXT: jbe .LBB3_1 -; X64-FreeBSD-NEXT: .LBB3_2: +; X64-FreeBSD-NEXT: jbe .LBB3_2 +; X64-FreeBSD-NEXT: .LBB3_1: ; X64-FreeBSD-NEXT: subq $40, %rsp ; X64-FreeBSD-NEXT: .cfi_def_cfa_offset 48 ; X64-FreeBSD-NEXT: movq %rsp, %rdi @@ -1040,18 +1040,18 @@ define fastcc void @test_fastcc() #0 { ; X64-FreeBSD-NEXT: addq $40, %rsp ; X64-FreeBSD-NEXT: .cfi_def_cfa_offset 8 ; X64-FreeBSD-NEXT: retq -; X64-FreeBSD-NEXT: .LBB3_1: +; X64-FreeBSD-NEXT: .LBB3_2: ; X64-FreeBSD-NEXT: movl $40, %r10d ; X64-FreeBSD-NEXT: movl $0, %r11d ; X64-FreeBSD-NEXT: callq __morestack ; X64-FreeBSD-NEXT: retq -; X64-FreeBSD-NEXT: jmp .LBB3_2 +; X64-FreeBSD-NEXT: jmp .LBB3_1 ; ; X86-DFlyBSD-LABEL: test_fastcc: ; X86-DFlyBSD: # %bb.0: ; X86-DFlyBSD-NEXT: cmpl %fs:16, %esp -; X86-DFlyBSD-NEXT: jbe .LBB3_1 -; X86-DFlyBSD-NEXT: .LBB3_2: +; X86-DFlyBSD-NEXT: jbe .LBB3_2 +; X86-DFlyBSD-NEXT: .LBB3_1: ; X86-DFlyBSD-NEXT: subl $40, %esp ; X86-DFlyBSD-NEXT: .cfi_def_cfa_offset 44 ; X86-DFlyBSD-NEXT: movl %esp, %eax @@ -1063,18 +1063,18 @@ define fastcc void @test_fastcc() #0 { ; X86-DFlyBSD-NEXT: addl $48, %esp ; X86-DFlyBSD-NEXT: .cfi_adjust_cfa_offset -48 ; X86-DFlyBSD-NEXT: retl -; X86-DFlyBSD-NEXT: .LBB3_1: +; X86-DFlyBSD-NEXT: .LBB3_2: ; X86-DFlyBSD-NEXT: pushl $0 ; X86-DFlyBSD-NEXT: pushl $40 ; X86-DFlyBSD-NEXT: calll __morestack ; X86-DFlyBSD-NEXT: retl -; X86-DFlyBSD-NEXT: jmp .LBB3_2 +; X86-DFlyBSD-NEXT: jmp .LBB3_1 ; ; X64-DFlyBSD-LABEL: test_fastcc: ; X64-DFlyBSD: # %bb.0: ; X64-DFlyBSD-NEXT: cmpq %fs:32, %rsp -; X64-DFlyBSD-NEXT: jbe .LBB3_1 -; X64-DFlyBSD-NEXT: .LBB3_2: +; X64-DFlyBSD-NEXT: jbe .LBB3_2 +; X64-DFlyBSD-NEXT: .LBB3_1: ; X64-DFlyBSD-NEXT: subq $40, %rsp ; X64-DFlyBSD-NEXT: .cfi_def_cfa_offset 48 ; X64-DFlyBSD-NEXT: movq %rsp, %rdi @@ -1083,18 +1083,18 @@ define fastcc void @test_fastcc() #0 { ; X64-DFlyBSD-NEXT: addq $40, %rsp ; X64-DFlyBSD-NEXT: .cfi_def_cfa_offset 8 ; X64-DFlyBSD-NEXT: retq -; X64-DFlyBSD-NEXT: .LBB3_1: +; X64-DFlyBSD-NEXT: .LBB3_2: ; X64-DFlyBSD-NEXT: movl $40, %r10d ; X64-DFlyBSD-NEXT: movl $0, %r11d ; X64-DFlyBSD-NEXT: callq __morestack ; X64-DFlyBSD-NEXT: retq -; X64-DFlyBSD-NEXT: jmp .LBB3_2 +; X64-DFlyBSD-NEXT: jmp .LBB3_1 ; ; X64-MinGW-LABEL: test_fastcc: ; X64-MinGW: # %bb.0: ; X64-MinGW-NEXT: cmpq %gs:40, %rsp -; X64-MinGW-NEXT: jbe .LBB3_1 -; X64-MinGW-NEXT: .LBB3_2: +; X64-MinGW-NEXT: jbe .LBB3_2 +; X64-MinGW-NEXT: .LBB3_1: ; X64-MinGW-NEXT: subq $72, %rsp ; X64-MinGW-NEXT: .seh_stackalloc 72 ; X64-MinGW-NEXT: .seh_endprologue @@ -1106,12 +1106,12 @@ define fastcc void @test_fastcc() #0 { ; X64-MinGW-NEXT: addq $72, %rsp ; X64-MinGW-NEXT: .seh_endepilogue ; X64-MinGW-NEXT: retq -; X64-MinGW-NEXT: .LBB3_1: +; X64-MinGW-NEXT: .LBB3_2: ; X64-MinGW-NEXT: movl $72, %r10d ; X64-MinGW-NEXT: movl $32, %r11d ; X64-MinGW-NEXT: callq __morestack ; X64-MinGW-NEXT: retq -; X64-MinGW-NEXT: jmp .LBB3_2 +; X64-MinGW-NEXT: jmp .LBB3_1 ; X64-MinGW-NEXT: .seh_endproc %mem = alloca i32, i32 10 call void @dummy_use (ptr %mem, i32 10) @@ -1123,8 +1123,8 @@ define fastcc void @test_fastcc_large() #0 { ; X86-Linux: # %bb.0: ; X86-Linux-NEXT: leal -{{[0-9]+}}(%esp), %eax ; X86-Linux-NEXT: cmpl %gs:48, %eax -; X86-Linux-NEXT: jbe .LBB4_1 -; X86-Linux-NEXT: .LBB4_2: +; X86-Linux-NEXT: jbe .LBB4_2 +; X86-Linux-NEXT: .LBB4_1: ; X86-Linux-NEXT: subl $40020, %esp # imm = 0x9C54 ; X86-Linux-NEXT: .cfi_adjust_cfa_offset 40020 ; X86-Linux-NEXT: leal {{[0-9]+}}(%esp), %eax @@ -1136,19 +1136,19 @@ define fastcc void @test_fastcc_large() #0 { ; X86-Linux-NEXT: addl $40028, %esp # imm = 0x9C5C ; X86-Linux-NEXT: .cfi_adjust_cfa_offset -40028 ; X86-Linux-NEXT: retl -; X86-Linux-NEXT: .LBB4_1: +; X86-Linux-NEXT: .LBB4_2: ; X86-Linux-NEXT: pushl $0 ; X86-Linux-NEXT: pushl $40012 # imm = 0x9C4C ; X86-Linux-NEXT: calll __morestack ; X86-Linux-NEXT: retl -; X86-Linux-NEXT: jmp .LBB4_2 +; X86-Linux-NEXT: jmp .LBB4_1 ; ; X64-Linux-LABEL: test_fastcc_large: ; X64-Linux: # %bb.0: ; X64-Linux-NEXT: leaq -{{[0-9]+}}(%rsp), %r11 ; X64-Linux-NEXT: cmpq %fs:112, %r11 -; X64-Linux-NEXT: jbe .LBB4_1 -; X64-Linux-NEXT: .LBB4_2: +; X64-Linux-NEXT: jbe .LBB4_2 +; X64-Linux-NEXT: .LBB4_1: ; X64-Linux-NEXT: subq $40008, %rsp # imm = 0x9C48 ; X64-Linux-NEXT: .cfi_def_cfa_offset 40016 ; X64-Linux-NEXT: leaq {{[0-9]+}}(%rsp), %rdi @@ -1157,19 +1157,19 @@ define fastcc void @test_fastcc_large() #0 { ; X64-Linux-NEXT: addq $40008, %rsp # imm = 0x9C48 ; X64-Linux-NEXT: .cfi_def_cfa_offset 8 ; X64-Linux-NEXT: retq -; X64-Linux-NEXT: .LBB4_1: +; X64-Linux-NEXT: .LBB4_2: ; X64-Linux-NEXT: movl $40008, %r10d # imm = 0x9C48 ; X64-Linux-NEXT: movl $0, %r11d ; X64-Linux-NEXT: callq __morestack ; X64-Linux-NEXT: retq -; X64-Linux-NEXT: jmp .LBB4_2 +; X64-Linux-NEXT: jmp .LBB4_1 ; ; X64-Linux-Large-LABEL: test_fastcc_large: ; X64-Linux-Large: # %bb.0: ; X64-Linux-Large-NEXT: leaq -{{[0-9]+}}(%rsp), %r11 ; X64-Linux-Large-NEXT: cmpq %fs:112, %r11 -; X64-Linux-Large-NEXT: jbe .LBB4_1 -; X64-Linux-Large-NEXT: .LBB4_2: +; X64-Linux-Large-NEXT: jbe .LBB4_2 +; X64-Linux-Large-NEXT: .LBB4_1: ; X64-Linux-Large-NEXT: subq $40008, %rsp # imm = 0x9C48 ; X64-Linux-Large-NEXT: .cfi_def_cfa_offset 40016 ; X64-Linux-Large-NEXT: movabsq $dummy_use, %rax @@ -1179,19 +1179,19 @@ define fastcc void @test_fastcc_large() #0 { ; X64-Linux-Large-NEXT: addq $40008, %rsp # imm = 0x9C48 ; X64-Linux-Large-NEXT: .cfi_def_cfa_offset 8 ; X64-Linux-Large-NEXT: retq -; X64-Linux-Large-NEXT: .LBB4_1: +; X64-Linux-Large-NEXT: .LBB4_2: ; X64-Linux-Large-NEXT: movl $40008, %r10d # imm = 0x9C48 ; X64-Linux-Large-NEXT: movl $0, %r11d ; X64-Linux-Large-NEXT: callq *__morestack_addr(%rip) ; X64-Linux-Large-NEXT: retq -; X64-Linux-Large-NEXT: jmp .LBB4_2 +; X64-Linux-Large-NEXT: jmp .LBB4_1 ; ; X32ABI-LABEL: test_fastcc_large: ; X32ABI: # %bb.0: ; X32ABI-NEXT: leal -{{[0-9]+}}(%rsp), %r11d ; X32ABI-NEXT: cmpl %fs:64, %r11d -; X32ABI-NEXT: jbe .LBB4_1 -; X32ABI-NEXT: .LBB4_2: +; X32ABI-NEXT: jbe .LBB4_2 +; X32ABI-NEXT: .LBB4_1: ; X32ABI-NEXT: subl $40008, %esp # imm = 0x9C48 ; X32ABI-NEXT: .cfi_def_cfa_offset 40016 ; X32ABI-NEXT: leal {{[0-9]+}}(%rsp), %edi @@ -1200,20 +1200,20 @@ define fastcc void @test_fastcc_large() #0 { ; X32ABI-NEXT: addl $40008, %esp # imm = 0x9C48 ; X32ABI-NEXT: .cfi_def_cfa_offset 8 ; X32ABI-NEXT: retq -; X32ABI-NEXT: .LBB4_1: +; X32ABI-NEXT: .LBB4_2: ; X32ABI-NEXT: movl $40008, %r10d # imm = 0x9C48 ; X32ABI-NEXT: movl $0, %r11d ; X32ABI-NEXT: callq __morestack ; X32ABI-NEXT: retq -; X32ABI-NEXT: jmp .LBB4_2 +; X32ABI-NEXT: jmp .LBB4_1 ; ; X86-Darwin-LABEL: test_fastcc_large: ; X86-Darwin: ## %bb.0: ; X86-Darwin-NEXT: leal -{{[0-9]+}}(%esp), %eax ; X86-Darwin-NEXT: movl $432, %ecx ## imm = 0x1B0 ; X86-Darwin-NEXT: cmpl %gs:(%ecx), %eax -; X86-Darwin-NEXT: jbe LBB4_1 -; X86-Darwin-NEXT: LBB4_2: +; X86-Darwin-NEXT: jbe LBB4_2 +; X86-Darwin-NEXT: LBB4_1: ; X86-Darwin-NEXT: subl $40012, %esp ## imm = 0x9C4C ; X86-Darwin-NEXT: .cfi_def_cfa_offset 40016 ; X86-Darwin-NEXT: leal {{[0-9]+}}(%esp), %eax @@ -1222,19 +1222,19 @@ define fastcc void @test_fastcc_large() #0 { ; X86-Darwin-NEXT: calll _dummy_use ; X86-Darwin-NEXT: addl $40012, %esp ## imm = 0x9C4C ; X86-Darwin-NEXT: retl -; X86-Darwin-NEXT: LBB4_1: +; X86-Darwin-NEXT: LBB4_2: ; X86-Darwin-NEXT: pushl $0 ; X86-Darwin-NEXT: pushl $40012 ## imm = 0x9C4C ; X86-Darwin-NEXT: calll ___morestack ; X86-Darwin-NEXT: retl -; X86-Darwin-NEXT: jmp LBB4_2 +; X86-Darwin-NEXT: jmp LBB4_1 ; ; X64-Darwin-LABEL: test_fastcc_large: ; X64-Darwin: ## %bb.0: ; X64-Darwin-NEXT: leaq -{{[0-9]+}}(%rsp), %r11 ; X64-Darwin-NEXT: cmpq %gs:816, %r11 -; X64-Darwin-NEXT: jbe LBB4_1 -; X64-Darwin-NEXT: LBB4_2: +; X64-Darwin-NEXT: jbe LBB4_2 +; X64-Darwin-NEXT: LBB4_1: ; X64-Darwin-NEXT: subq $40008, %rsp ## imm = 0x9C48 ; X64-Darwin-NEXT: .cfi_def_cfa_offset 40016 ; X64-Darwin-NEXT: leaq {{[0-9]+}}(%rsp), %rdi @@ -1242,19 +1242,19 @@ define fastcc void @test_fastcc_large() #0 { ; X64-Darwin-NEXT: callq _dummy_use ; X64-Darwin-NEXT: addq $40008, %rsp ## imm = 0x9C48 ; X64-Darwin-NEXT: retq -; X64-Darwin-NEXT: LBB4_1: +; X64-Darwin-NEXT: LBB4_2: ; X64-Darwin-NEXT: movl $40008, %r10d ## imm = 0x9C48 ; X64-Darwin-NEXT: movl $0, %r11d ; X64-Darwin-NEXT: callq ___morestack ; X64-Darwin-NEXT: retq -; X64-Darwin-NEXT: jmp LBB4_2 +; X64-Darwin-NEXT: jmp LBB4_1 ; ; X86-MinGW-LABEL: test_fastcc_large: ; X86-MinGW: # %bb.0: ; X86-MinGW-NEXT: leal -{{[0-9]+}}(%esp), %eax ; X86-MinGW-NEXT: cmpl %fs:20, %eax -; X86-MinGW-NEXT: jbe LBB4_1 -; X86-MinGW-NEXT: LBB4_2: +; X86-MinGW-NEXT: jbe LBB4_2 +; X86-MinGW-NEXT: LBB4_1: ; X86-MinGW-NEXT: movl $40000, %eax # imm = 0x9C40 ; X86-MinGW-NEXT: calll __alloca ; X86-MinGW-NEXT: .cfi_def_cfa_offset 40004 @@ -1267,19 +1267,19 @@ define fastcc void @test_fastcc_large() #0 { ; X86-MinGW-NEXT: addl $40008, %esp # imm = 0x9C48 ; X86-MinGW-NEXT: .cfi_adjust_cfa_offset -40008 ; X86-MinGW-NEXT: retl -; X86-MinGW-NEXT: LBB4_1: +; X86-MinGW-NEXT: LBB4_2: ; X86-MinGW-NEXT: pushl $0 ; X86-MinGW-NEXT: pushl $40000 # imm = 0x9C40 ; X86-MinGW-NEXT: calll ___morestack ; X86-MinGW-NEXT: retl -; X86-MinGW-NEXT: jmp LBB4_2 +; X86-MinGW-NEXT: jmp LBB4_1 ; ; X64-FreeBSD-LABEL: test_fastcc_large: ; X64-FreeBSD: # %bb.0: ; X64-FreeBSD-NEXT: leaq -{{[0-9]+}}(%rsp), %r11 ; X64-FreeBSD-NEXT: cmpq %fs:24, %r11 -; X64-FreeBSD-NEXT: jbe .LBB4_1 -; X64-FreeBSD-NEXT: .LBB4_2: +; X64-FreeBSD-NEXT: jbe .LBB4_2 +; X64-FreeBSD-NEXT: .LBB4_1: ; X64-FreeBSD-NEXT: subq $40008, %rsp # imm = 0x9C48 ; X64-FreeBSD-NEXT: .cfi_def_cfa_offset 40016 ; X64-FreeBSD-NEXT: leaq {{[0-9]+}}(%rsp), %rdi @@ -1288,19 +1288,19 @@ define fastcc void @test_fastcc_large() #0 { ; X64-FreeBSD-NEXT: addq $40008, %rsp # imm = 0x9C48 ; X64-FreeBSD-NEXT: .cfi_def_cfa_offset 8 ; X64-FreeBSD-NEXT: retq -; X64-FreeBSD-NEXT: .LBB4_1: +; X64-FreeBSD-NEXT: .LBB4_2: ; X64-FreeBSD-NEXT: movl $40008, %r10d # imm = 0x9C48 ; X64-FreeBSD-NEXT: movl $0, %r11d ; X64-FreeBSD-NEXT: callq __morestack ; X64-FreeBSD-NEXT: retq -; X64-FreeBSD-NEXT: jmp .LBB4_2 +; X64-FreeBSD-NEXT: jmp .LBB4_1 ; ; X86-DFlyBSD-LABEL: test_fastcc_large: ; X86-DFlyBSD: # %bb.0: ; X86-DFlyBSD-NEXT: leal -{{[0-9]+}}(%esp), %eax ; X86-DFlyBSD-NEXT: cmpl %fs:16, %eax -; X86-DFlyBSD-NEXT: jbe .LBB4_1 -; X86-DFlyBSD-NEXT: .LBB4_2: +; X86-DFlyBSD-NEXT: jbe .LBB4_2 +; X86-DFlyBSD-NEXT: .LBB4_1: ; X86-DFlyBSD-NEXT: subl $40000, %esp # imm = 0x9C40 ; X86-DFlyBSD-NEXT: .cfi_def_cfa_offset 40004 ; X86-DFlyBSD-NEXT: movl %esp, %eax @@ -1312,19 +1312,19 @@ define fastcc void @test_fastcc_large() #0 { ; X86-DFlyBSD-NEXT: addl $40008, %esp # imm = 0x9C48 ; X86-DFlyBSD-NEXT: .cfi_adjust_cfa_offset -40008 ; X86-DFlyBSD-NEXT: retl -; X86-DFlyBSD-NEXT: .LBB4_1: +; X86-DFlyBSD-NEXT: .LBB4_2: ; X86-DFlyBSD-NEXT: pushl $0 ; X86-DFlyBSD-NEXT: pushl $40000 # imm = 0x9C40 ; X86-DFlyBSD-NEXT: calll __morestack ; X86-DFlyBSD-NEXT: retl -; X86-DFlyBSD-NEXT: jmp .LBB4_2 +; X86-DFlyBSD-NEXT: jmp .LBB4_1 ; ; X64-DFlyBSD-LABEL: test_fastcc_large: ; X64-DFlyBSD: # %bb.0: ; X64-DFlyBSD-NEXT: leaq -{{[0-9]+}}(%rsp), %r11 ; X64-DFlyBSD-NEXT: cmpq %fs:32, %r11 -; X64-DFlyBSD-NEXT: jbe .LBB4_1 -; X64-DFlyBSD-NEXT: .LBB4_2: +; X64-DFlyBSD-NEXT: jbe .LBB4_2 +; X64-DFlyBSD-NEXT: .LBB4_1: ; X64-DFlyBSD-NEXT: subq $40008, %rsp # imm = 0x9C48 ; X64-DFlyBSD-NEXT: .cfi_def_cfa_offset 40016 ; X64-DFlyBSD-NEXT: leaq {{[0-9]+}}(%rsp), %rdi @@ -1333,19 +1333,19 @@ define fastcc void @test_fastcc_large() #0 { ; X64-DFlyBSD-NEXT: addq $40008, %rsp # imm = 0x9C48 ; X64-DFlyBSD-NEXT: .cfi_def_cfa_offset 8 ; X64-DFlyBSD-NEXT: retq -; X64-DFlyBSD-NEXT: .LBB4_1: +; X64-DFlyBSD-NEXT: .LBB4_2: ; X64-DFlyBSD-NEXT: movl $40008, %r10d # imm = 0x9C48 ; X64-DFlyBSD-NEXT: movl $0, %r11d ; X64-DFlyBSD-NEXT: callq __morestack ; X64-DFlyBSD-NEXT: retq -; X64-DFlyBSD-NEXT: jmp .LBB4_2 +; X64-DFlyBSD-NEXT: jmp .LBB4_1 ; ; X64-MinGW-LABEL: test_fastcc_large: ; X64-MinGW: # %bb.0: ; X64-MinGW-NEXT: leaq -{{[0-9]+}}(%rsp), %r11 ; X64-MinGW-NEXT: cmpq %gs:40, %r11 -; X64-MinGW-NEXT: jbe .LBB4_1 -; X64-MinGW-NEXT: .LBB4_2: +; X64-MinGW-NEXT: jbe .LBB4_2 +; X64-MinGW-NEXT: .LBB4_1: ; X64-MinGW-NEXT: movl $40040, %eax # imm = 0x9C68 ; X64-MinGW-NEXT: callq ___chkstk_ms ; X64-MinGW-NEXT: subq %rax, %rsp @@ -1359,12 +1359,12 @@ define fastcc void @test_fastcc_large() #0 { ; X64-MinGW-NEXT: addq $40040, %rsp # imm = 0x9C68 ; X64-MinGW-NEXT: .seh_endepilogue ; X64-MinGW-NEXT: retq -; X64-MinGW-NEXT: .LBB4_1: +; X64-MinGW-NEXT: .LBB4_2: ; X64-MinGW-NEXT: movl $40040, %r10d # imm = 0x9C68 ; X64-MinGW-NEXT: movl $32, %r11d ; X64-MinGW-NEXT: callq __morestack ; X64-MinGW-NEXT: retq -; X64-MinGW-NEXT: jmp .LBB4_2 +; X64-MinGW-NEXT: jmp .LBB4_1 ; X64-MinGW-NEXT: .seh_endproc %mem = alloca i32, i32 10000 call void @dummy_use (ptr %mem, i32 3) @@ -1378,8 +1378,8 @@ define fastcc void @test_fastcc_large_with_ecx_arg(i32 %a) #0 { ; X86-Linux: # %bb.0: ; X86-Linux-NEXT: leal -{{[0-9]+}}(%esp), %eax ; X86-Linux-NEXT: cmpl %gs:48, %eax -; X86-Linux-NEXT: jbe .LBB5_1 -; X86-Linux-NEXT: .LBB5_2: +; X86-Linux-NEXT: jbe .LBB5_2 +; X86-Linux-NEXT: .LBB5_1: ; X86-Linux-NEXT: subl $40020, %esp # imm = 0x9C54 ; X86-Linux-NEXT: .cfi_adjust_cfa_offset 40020 ; X86-Linux-NEXT: leal {{[0-9]+}}(%esp), %eax @@ -1391,19 +1391,19 @@ define fastcc void @test_fastcc_large_with_ecx_arg(i32 %a) #0 { ; X86-Linux-NEXT: addl $40028, %esp # imm = 0x9C5C ; X86-Linux-NEXT: .cfi_adjust_cfa_offset -40028 ; X86-Linux-NEXT: retl -; X86-Linux-NEXT: .LBB5_1: +; X86-Linux-NEXT: .LBB5_2: ; X86-Linux-NEXT: pushl $0 ; X86-Linux-NEXT: pushl $40012 # imm = 0x9C4C ; X86-Linux-NEXT: calll __morestack ; X86-Linux-NEXT: retl -; X86-Linux-NEXT: jmp .LBB5_2 +; X86-Linux-NEXT: jmp .LBB5_1 ; ; X64-Linux-LABEL: test_fastcc_large_with_ecx_arg: ; X64-Linux: # %bb.0: ; X64-Linux-NEXT: leaq -{{[0-9]+}}(%rsp), %r11 ; X64-Linux-NEXT: cmpq %fs:112, %r11 -; X64-Linux-NEXT: jbe .LBB5_1 -; X64-Linux-NEXT: .LBB5_2: +; X64-Linux-NEXT: jbe .LBB5_2 +; X64-Linux-NEXT: .LBB5_1: ; X64-Linux-NEXT: subq $40008, %rsp # imm = 0x9C48 ; X64-Linux-NEXT: .cfi_def_cfa_offset 40016 ; X64-Linux-NEXT: movl %edi, %esi @@ -1412,19 +1412,19 @@ define fastcc void @test_fastcc_large_with_ecx_arg(i32 %a) #0 { ; X64-Linux-NEXT: addq $40008, %rsp # imm = 0x9C48 ; X64-Linux-NEXT: .cfi_def_cfa_offset 8 ; X64-Linux-NEXT: retq -; X64-Linux-NEXT: .LBB5_1: +; X64-Linux-NEXT: .LBB5_2: ; X64-Linux-NEXT: movl $40008, %r10d # imm = 0x9C48 ; X64-Linux-NEXT: movl $0, %r11d ; X64-Linux-NEXT: callq __morestack ; X64-Linux-NEXT: retq -; X64-Linux-NEXT: jmp .LBB5_2 +; X64-Linux-NEXT: jmp .LBB5_1 ; ; X64-Linux-Large-LABEL: test_fastcc_large_with_ecx_arg: ; X64-Linux-Large: # %bb.0: ; X64-Linux-Large-NEXT: leaq -{{[0-9]+}}(%rsp), %r11 ; X64-Linux-Large-NEXT: cmpq %fs:112, %r11 -; X64-Linux-Large-NEXT: jbe .LBB5_1 -; X64-Linux-Large-NEXT: .LBB5_2: +; X64-Linux-Large-NEXT: jbe .LBB5_2 +; X64-Linux-Large-NEXT: .LBB5_1: ; X64-Linux-Large-NEXT: subq $40008, %rsp # imm = 0x9C48 ; X64-Linux-Large-NEXT: .cfi_def_cfa_offset 40016 ; X64-Linux-Large-NEXT: movl %edi, %esi @@ -1434,19 +1434,19 @@ define fastcc void @test_fastcc_large_with_ecx_arg(i32 %a) #0 { ; X64-Linux-Large-NEXT: addq $40008, %rsp # imm = 0x9C48 ; X64-Linux-Large-NEXT: .cfi_def_cfa_offset 8 ; X64-Linux-Large-NEXT: retq -; X64-Linux-Large-NEXT: .LBB5_1: +; X64-Linux-Large-NEXT: .LBB5_2: ; X64-Linux-Large-NEXT: movl $40008, %r10d # imm = 0x9C48 ; X64-Linux-Large-NEXT: movl $0, %r11d ; X64-Linux-Large-NEXT: callq *__morestack_addr(%rip) ; X64-Linux-Large-NEXT: retq -; X64-Linux-Large-NEXT: jmp .LBB5_2 +; X64-Linux-Large-NEXT: jmp .LBB5_1 ; ; X32ABI-LABEL: test_fastcc_large_with_ecx_arg: ; X32ABI: # %bb.0: ; X32ABI-NEXT: leal -{{[0-9]+}}(%rsp), %r11d ; X32ABI-NEXT: cmpl %fs:64, %r11d -; X32ABI-NEXT: jbe .LBB5_1 -; X32ABI-NEXT: .LBB5_2: +; X32ABI-NEXT: jbe .LBB5_2 +; X32ABI-NEXT: .LBB5_1: ; X32ABI-NEXT: subl $40008, %esp # imm = 0x9C48 ; X32ABI-NEXT: .cfi_def_cfa_offset 40016 ; X32ABI-NEXT: movl %edi, %esi @@ -1455,12 +1455,12 @@ define fastcc void @test_fastcc_large_with_ecx_arg(i32 %a) #0 { ; X32ABI-NEXT: addl $40008, %esp # imm = 0x9C48 ; X32ABI-NEXT: .cfi_def_cfa_offset 8 ; X32ABI-NEXT: retq -; X32ABI-NEXT: .LBB5_1: +; X32ABI-NEXT: .LBB5_2: ; X32ABI-NEXT: movl $40008, %r10d # imm = 0x9C48 ; X32ABI-NEXT: movl $0, %r11d ; X32ABI-NEXT: callq __morestack ; X32ABI-NEXT: retq -; X32ABI-NEXT: jmp .LBB5_2 +; X32ABI-NEXT: jmp .LBB5_1 ; ; X86-Darwin-LABEL: test_fastcc_large_with_ecx_arg: ; X86-Darwin: ## %bb.0: @@ -1469,8 +1469,8 @@ define fastcc void @test_fastcc_large_with_ecx_arg(i32 %a) #0 { ; X86-Darwin-NEXT: movl $432, %ecx ## imm = 0x1B0 ; X86-Darwin-NEXT: cmpl %gs:(%ecx), %eax ; X86-Darwin-NEXT: popl %ecx -; X86-Darwin-NEXT: jbe LBB5_1 -; X86-Darwin-NEXT: LBB5_2: +; X86-Darwin-NEXT: jbe LBB5_2 +; X86-Darwin-NEXT: LBB5_1: ; X86-Darwin-NEXT: subl $40012, %esp ## imm = 0x9C4C ; X86-Darwin-NEXT: .cfi_def_cfa_offset 40016 ; X86-Darwin-NEXT: movl %ecx, {{[0-9]+}}(%esp) @@ -1479,19 +1479,19 @@ define fastcc void @test_fastcc_large_with_ecx_arg(i32 %a) #0 { ; X86-Darwin-NEXT: calll _dummy_use ; X86-Darwin-NEXT: addl $40012, %esp ## imm = 0x9C4C ; X86-Darwin-NEXT: retl -; X86-Darwin-NEXT: LBB5_1: +; X86-Darwin-NEXT: LBB5_2: ; X86-Darwin-NEXT: pushl $0 ; X86-Darwin-NEXT: pushl $40012 ## imm = 0x9C4C ; X86-Darwin-NEXT: calll ___morestack ; X86-Darwin-NEXT: retl -; X86-Darwin-NEXT: jmp LBB5_2 +; X86-Darwin-NEXT: jmp LBB5_1 ; ; X64-Darwin-LABEL: test_fastcc_large_with_ecx_arg: ; X64-Darwin: ## %bb.0: ; X64-Darwin-NEXT: leaq -{{[0-9]+}}(%rsp), %r11 ; X64-Darwin-NEXT: cmpq %gs:816, %r11 -; X64-Darwin-NEXT: jbe LBB5_1 -; X64-Darwin-NEXT: LBB5_2: +; X64-Darwin-NEXT: jbe LBB5_2 +; X64-Darwin-NEXT: LBB5_1: ; X64-Darwin-NEXT: subq $40008, %rsp ## imm = 0x9C48 ; X64-Darwin-NEXT: .cfi_def_cfa_offset 40016 ; X64-Darwin-NEXT: movl %edi, %esi @@ -1499,19 +1499,19 @@ define fastcc void @test_fastcc_large_with_ecx_arg(i32 %a) #0 { ; X64-Darwin-NEXT: callq _dummy_use ; X64-Darwin-NEXT: addq $40008, %rsp ## imm = 0x9C48 ; X64-Darwin-NEXT: retq -; X64-Darwin-NEXT: LBB5_1: +; X64-Darwin-NEXT: LBB5_2: ; X64-Darwin-NEXT: movl $40008, %r10d ## imm = 0x9C48 ; X64-Darwin-NEXT: movl $0, %r11d ; X64-Darwin-NEXT: callq ___morestack ; X64-Darwin-NEXT: retq -; X64-Darwin-NEXT: jmp LBB5_2 +; X64-Darwin-NEXT: jmp LBB5_1 ; ; X86-MinGW-LABEL: test_fastcc_large_with_ecx_arg: ; X86-MinGW: # %bb.0: ; X86-MinGW-NEXT: leal -{{[0-9]+}}(%esp), %eax ; X86-MinGW-NEXT: cmpl %fs:20, %eax -; X86-MinGW-NEXT: jbe LBB5_1 -; X86-MinGW-NEXT: LBB5_2: +; X86-MinGW-NEXT: jbe LBB5_2 +; X86-MinGW-NEXT: LBB5_1: ; X86-MinGW-NEXT: movl $40000, %eax # imm = 0x9C40 ; X86-MinGW-NEXT: calll __alloca ; X86-MinGW-NEXT: .cfi_def_cfa_offset 40004 @@ -1524,19 +1524,19 @@ define fastcc void @test_fastcc_large_with_ecx_arg(i32 %a) #0 { ; X86-MinGW-NEXT: addl $40008, %esp # imm = 0x9C48 ; X86-MinGW-NEXT: .cfi_adjust_cfa_offset -40008 ; X86-MinGW-NEXT: retl -; X86-MinGW-NEXT: LBB5_1: +; X86-MinGW-NEXT: LBB5_2: ; X86-MinGW-NEXT: pushl $0 ; X86-MinGW-NEXT: pushl $40000 # imm = 0x9C40 ; X86-MinGW-NEXT: calll ___morestack ; X86-MinGW-NEXT: retl -; X86-MinGW-NEXT: jmp LBB5_2 +; X86-MinGW-NEXT: jmp LBB5_1 ; ; X64-FreeBSD-LABEL: test_fastcc_large_with_ecx_arg: ; X64-FreeBSD: # %bb.0: ; X64-FreeBSD-NEXT: leaq -{{[0-9]+}}(%rsp), %r11 ; X64-FreeBSD-NEXT: cmpq %fs:24, %r11 -; X64-FreeBSD-NEXT: jbe .LBB5_1 -; X64-FreeBSD-NEXT: .LBB5_2: +; X64-FreeBSD-NEXT: jbe .LBB5_2 +; X64-FreeBSD-NEXT: .LBB5_1: ; X64-FreeBSD-NEXT: subq $40008, %rsp # imm = 0x9C48 ; X64-FreeBSD-NEXT: .cfi_def_cfa_offset 40016 ; X64-FreeBSD-NEXT: movl %edi, %esi @@ -1545,19 +1545,19 @@ define fastcc void @test_fastcc_large_with_ecx_arg(i32 %a) #0 { ; X64-FreeBSD-NEXT: addq $40008, %rsp # imm = 0x9C48 ; X64-FreeBSD-NEXT: .cfi_def_cfa_offset 8 ; X64-FreeBSD-NEXT: retq -; X64-FreeBSD-NEXT: .LBB5_1: +; X64-FreeBSD-NEXT: .LBB5_2: ; X64-FreeBSD-NEXT: movl $40008, %r10d # imm = 0x9C48 ; X64-FreeBSD-NEXT: movl $0, %r11d ; X64-FreeBSD-NEXT: callq __morestack ; X64-FreeBSD-NEXT: retq -; X64-FreeBSD-NEXT: jmp .LBB5_2 +; X64-FreeBSD-NEXT: jmp .LBB5_1 ; ; X86-DFlyBSD-LABEL: test_fastcc_large_with_ecx_arg: ; X86-DFlyBSD: # %bb.0: ; X86-DFlyBSD-NEXT: leal -{{[0-9]+}}(%esp), %eax ; X86-DFlyBSD-NEXT: cmpl %fs:16, %eax -; X86-DFlyBSD-NEXT: jbe .LBB5_1 -; X86-DFlyBSD-NEXT: .LBB5_2: +; X86-DFlyBSD-NEXT: jbe .LBB5_2 +; X86-DFlyBSD-NEXT: .LBB5_1: ; X86-DFlyBSD-NEXT: subl $40000, %esp # imm = 0x9C40 ; X86-DFlyBSD-NEXT: .cfi_def_cfa_offset 40004 ; X86-DFlyBSD-NEXT: movl %esp, %eax @@ -1569,19 +1569,19 @@ define fastcc void @test_fastcc_large_with_ecx_arg(i32 %a) #0 { ; X86-DFlyBSD-NEXT: addl $40008, %esp # imm = 0x9C48 ; X86-DFlyBSD-NEXT: .cfi_adjust_cfa_offset -40008 ; X86-DFlyBSD-NEXT: retl -; X86-DFlyBSD-NEXT: .LBB5_1: +; X86-DFlyBSD-NEXT: .LBB5_2: ; X86-DFlyBSD-NEXT: pushl $0 ; X86-DFlyBSD-NEXT: pushl $40000 # imm = 0x9C40 ; X86-DFlyBSD-NEXT: calll __morestack ; X86-DFlyBSD-NEXT: retl -; X86-DFlyBSD-NEXT: jmp .LBB5_2 +; X86-DFlyBSD-NEXT: jmp .LBB5_1 ; ; X64-DFlyBSD-LABEL: test_fastcc_large_with_ecx_arg: ; X64-DFlyBSD: # %bb.0: ; X64-DFlyBSD-NEXT: leaq -{{[0-9]+}}(%rsp), %r11 ; X64-DFlyBSD-NEXT: cmpq %fs:32, %r11 -; X64-DFlyBSD-NEXT: jbe .LBB5_1 -; X64-DFlyBSD-NEXT: .LBB5_2: +; X64-DFlyBSD-NEXT: jbe .LBB5_2 +; X64-DFlyBSD-NEXT: .LBB5_1: ; X64-DFlyBSD-NEXT: subq $40008, %rsp # imm = 0x9C48 ; X64-DFlyBSD-NEXT: .cfi_def_cfa_offset 40016 ; X64-DFlyBSD-NEXT: movl %edi, %esi @@ -1590,19 +1590,19 @@ define fastcc void @test_fastcc_large_with_ecx_arg(i32 %a) #0 { ; X64-DFlyBSD-NEXT: addq $40008, %rsp # imm = 0x9C48 ; X64-DFlyBSD-NEXT: .cfi_def_cfa_offset 8 ; X64-DFlyBSD-NEXT: retq -; X64-DFlyBSD-NEXT: .LBB5_1: +; X64-DFlyBSD-NEXT: .LBB5_2: ; X64-DFlyBSD-NEXT: movl $40008, %r10d # imm = 0x9C48 ; X64-DFlyBSD-NEXT: movl $0, %r11d ; X64-DFlyBSD-NEXT: callq __morestack ; X64-DFlyBSD-NEXT: retq -; X64-DFlyBSD-NEXT: jmp .LBB5_2 +; X64-DFlyBSD-NEXT: jmp .LBB5_1 ; ; X64-MinGW-LABEL: test_fastcc_large_with_ecx_arg: ; X64-MinGW: # %bb.0: ; X64-MinGW-NEXT: leaq -{{[0-9]+}}(%rsp), %r11 ; X64-MinGW-NEXT: cmpq %gs:40, %r11 -; X64-MinGW-NEXT: jbe .LBB5_1 -; X64-MinGW-NEXT: .LBB5_2: +; X64-MinGW-NEXT: jbe .LBB5_2 +; X64-MinGW-NEXT: .LBB5_1: ; X64-MinGW-NEXT: movl $40040, %eax # imm = 0x9C68 ; X64-MinGW-NEXT: callq ___chkstk_ms ; X64-MinGW-NEXT: subq %rax, %rsp @@ -1616,12 +1616,12 @@ define fastcc void @test_fastcc_large_with_ecx_arg(i32 %a) #0 { ; X64-MinGW-NEXT: addq $40040, %rsp # imm = 0x9C68 ; X64-MinGW-NEXT: .seh_endepilogue ; X64-MinGW-NEXT: retq -; X64-MinGW-NEXT: .LBB5_1: +; X64-MinGW-NEXT: .LBB5_2: ; X64-MinGW-NEXT: movl $40040, %r10d # imm = 0x9C68 ; X64-MinGW-NEXT: movl $32, %r11d ; X64-MinGW-NEXT: callq __morestack ; X64-MinGW-NEXT: retq -; X64-MinGW-NEXT: jmp .LBB5_2 +; X64-MinGW-NEXT: jmp .LBB5_1 ; X64-MinGW-NEXT: .seh_endproc %mem = alloca i32, i32 10000 call void @dummy_use (ptr %mem, i32 %a) @@ -1754,11 +1754,11 @@ define i32 @test_sibling_call_empty_frame(i32 %x) #0 { ; X64-Linux-Large-LABEL: test_sibling_call_empty_frame: ; X64-Linux-Large: # %bb.0: ; X64-Linux-Large-NEXT: cmpq %fs:112, %rsp -; X64-Linux-Large-NEXT: jbe .LBB8_1 -; X64-Linux-Large-NEXT: # %bb.2: +; X64-Linux-Large-NEXT: jbe .LBB8_2 +; X64-Linux-Large-NEXT: # %bb.1: ; X64-Linux-Large-NEXT: movabsq $callee, %rax ; X64-Linux-Large-NEXT: jmpq *%rax # TAILCALL -; X64-Linux-Large-NEXT: .LBB8_1: +; X64-Linux-Large-NEXT: .LBB8_2: ; X64-Linux-Large-NEXT: movl $0, %r10d ; X64-Linux-Large-NEXT: movl $0, %r11d ; X64-Linux-Large-NEXT: callq *__morestack_addr(%rip) @@ -1864,8 +1864,8 @@ define i32 @test_nested_unused(ptr nest %unused) #0 { ; X86-Linux-LABEL: test_nested_unused: ; X86-Linux: # %bb.0: ; X86-Linux-NEXT: cmpl %gs:48, %esp -; X86-Linux-NEXT: jbe .LBB9_1 -; X86-Linux-NEXT: .LBB9_2: +; X86-Linux-NEXT: jbe .LBB9_2 +; X86-Linux-NEXT: .LBB9_1: ; X86-Linux-NEXT: subl $52, %esp ; X86-Linux-NEXT: .cfi_adjust_cfa_offset 52 ; X86-Linux-NEXT: leal {{[0-9]+}}(%esp), %eax @@ -1880,18 +1880,18 @@ define i32 @test_nested_unused(ptr nest %unused) #0 { ; X86-Linux-NEXT: addl $44, %esp ; X86-Linux-NEXT: .cfi_def_cfa_offset 4 ; X86-Linux-NEXT: retl -; X86-Linux-NEXT: .LBB9_1: +; X86-Linux-NEXT: .LBB9_2: ; X86-Linux-NEXT: pushl $0 ; X86-Linux-NEXT: pushl $44 ; X86-Linux-NEXT: calll __morestack ; X86-Linux-NEXT: retl -; X86-Linux-NEXT: jmp .LBB9_2 +; X86-Linux-NEXT: jmp .LBB9_1 ; ; X64-Linux-LABEL: test_nested_unused: ; X64-Linux: # %bb.0: ; X64-Linux-NEXT: cmpq %fs:112, %rsp -; X64-Linux-NEXT: jbe .LBB9_1 -; X64-Linux-NEXT: .LBB9_2: +; X64-Linux-NEXT: jbe .LBB9_2 +; X64-Linux-NEXT: .LBB9_1: ; X64-Linux-NEXT: subq $40, %rsp ; X64-Linux-NEXT: .cfi_def_cfa_offset 48 ; X64-Linux-NEXT: movq %rsp, %rdi @@ -1901,18 +1901,18 @@ define i32 @test_nested_unused(ptr nest %unused) #0 { ; X64-Linux-NEXT: addq $40, %rsp ; X64-Linux-NEXT: .cfi_def_cfa_offset 8 ; X64-Linux-NEXT: retq -; X64-Linux-NEXT: .LBB9_1: +; X64-Linux-NEXT: .LBB9_2: ; X64-Linux-NEXT: movl $40, %r10d ; X64-Linux-NEXT: movl $0, %r11d ; X64-Linux-NEXT: callq __morestack ; X64-Linux-NEXT: retq -; X64-Linux-NEXT: jmp .LBB9_2 +; X64-Linux-NEXT: jmp .LBB9_1 ; ; X64-Linux-Large-LABEL: test_nested_unused: ; X64-Linux-Large: # %bb.0: ; X64-Linux-Large-NEXT: cmpq %fs:112, %rsp -; X64-Linux-Large-NEXT: jbe .LBB9_1 -; X64-Linux-Large-NEXT: .LBB9_2: +; X64-Linux-Large-NEXT: jbe .LBB9_2 +; X64-Linux-Large-NEXT: .LBB9_1: ; X64-Linux-Large-NEXT: subq $40, %rsp ; X64-Linux-Large-NEXT: .cfi_def_cfa_offset 48 ; X64-Linux-Large-NEXT: movabsq $dummy_use, %rax @@ -1923,18 +1923,18 @@ define i32 @test_nested_unused(ptr nest %unused) #0 { ; X64-Linux-Large-NEXT: addq $40, %rsp ; X64-Linux-Large-NEXT: .cfi_def_cfa_offset 8 ; X64-Linux-Large-NEXT: retq -; X64-Linux-Large-NEXT: .LBB9_1: +; X64-Linux-Large-NEXT: .LBB9_2: ; X64-Linux-Large-NEXT: movl $40, %r10d ; X64-Linux-Large-NEXT: movl $0, %r11d ; X64-Linux-Large-NEXT: callq *__morestack_addr(%rip) ; X64-Linux-Large-NEXT: retq -; X64-Linux-Large-NEXT: jmp .LBB9_2 +; X64-Linux-Large-NEXT: jmp .LBB9_1 ; ; X32ABI-LABEL: test_nested_unused: ; X32ABI: # %bb.0: ; X32ABI-NEXT: cmpl %fs:64, %esp -; X32ABI-NEXT: jbe .LBB9_1 -; X32ABI-NEXT: .LBB9_2: +; X32ABI-NEXT: jbe .LBB9_2 +; X32ABI-NEXT: .LBB9_1: ; X32ABI-NEXT: subl $40, %esp ; X32ABI-NEXT: .cfi_def_cfa_offset 48 ; X32ABI-NEXT: movl %esp, %edi @@ -1944,19 +1944,19 @@ define i32 @test_nested_unused(ptr nest %unused) #0 { ; X32ABI-NEXT: addl $40, %esp ; X32ABI-NEXT: .cfi_def_cfa_offset 8 ; X32ABI-NEXT: retq -; X32ABI-NEXT: .LBB9_1: +; X32ABI-NEXT: .LBB9_2: ; X32ABI-NEXT: movl $40, %r10d ; X32ABI-NEXT: movl $0, %r11d ; X32ABI-NEXT: callq __morestack ; X32ABI-NEXT: retq -; X32ABI-NEXT: jmp .LBB9_2 +; X32ABI-NEXT: jmp .LBB9_1 ; ; X86-Darwin-LABEL: test_nested_unused: ; X86-Darwin: ## %bb.0: ; X86-Darwin-NEXT: movl $432, %ecx ## imm = 0x1B0 ; X86-Darwin-NEXT: cmpl %gs:(%ecx), %esp -; X86-Darwin-NEXT: jbe LBB9_1 -; X86-Darwin-NEXT: LBB9_2: +; X86-Darwin-NEXT: jbe LBB9_2 +; X86-Darwin-NEXT: LBB9_1: ; X86-Darwin-NEXT: subl $60, %esp ; X86-Darwin-NEXT: .cfi_def_cfa_offset 64 ; X86-Darwin-NEXT: leal {{[0-9]+}}(%esp), %eax @@ -1966,18 +1966,18 @@ define i32 @test_nested_unused(ptr nest %unused) #0 { ; X86-Darwin-NEXT: movl $123, %eax ; X86-Darwin-NEXT: addl $60, %esp ; X86-Darwin-NEXT: retl -; X86-Darwin-NEXT: LBB9_1: +; X86-Darwin-NEXT: LBB9_2: ; X86-Darwin-NEXT: pushl $0 ; X86-Darwin-NEXT: pushl $60 ; X86-Darwin-NEXT: calll ___morestack ; X86-Darwin-NEXT: retl -; X86-Darwin-NEXT: jmp LBB9_2 +; X86-Darwin-NEXT: jmp LBB9_1 ; ; X64-Darwin-LABEL: test_nested_unused: ; X64-Darwin: ## %bb.0: ; X64-Darwin-NEXT: cmpq %gs:816, %rsp -; X64-Darwin-NEXT: jbe LBB9_1 -; X64-Darwin-NEXT: LBB9_2: +; X64-Darwin-NEXT: jbe LBB9_2 +; X64-Darwin-NEXT: LBB9_1: ; X64-Darwin-NEXT: subq $40, %rsp ; X64-Darwin-NEXT: .cfi_def_cfa_offset 48 ; X64-Darwin-NEXT: movq %rsp, %rdi @@ -1986,18 +1986,18 @@ define i32 @test_nested_unused(ptr nest %unused) #0 { ; X64-Darwin-NEXT: movl $123, %eax ; X64-Darwin-NEXT: addq $40, %rsp ; X64-Darwin-NEXT: retq -; X64-Darwin-NEXT: LBB9_1: +; X64-Darwin-NEXT: LBB9_2: ; X64-Darwin-NEXT: movl $40, %r10d ; X64-Darwin-NEXT: movl $0, %r11d ; X64-Darwin-NEXT: callq ___morestack ; X64-Darwin-NEXT: retq -; X64-Darwin-NEXT: jmp LBB9_2 +; X64-Darwin-NEXT: jmp LBB9_1 ; ; X86-MinGW-LABEL: test_nested_unused: ; X86-MinGW: # %bb.0: ; X86-MinGW-NEXT: cmpl %fs:20, %esp -; X86-MinGW-NEXT: jbe LBB9_1 -; X86-MinGW-NEXT: LBB9_2: +; X86-MinGW-NEXT: jbe LBB9_2 +; X86-MinGW-NEXT: LBB9_1: ; X86-MinGW-NEXT: subl $40, %esp ; X86-MinGW-NEXT: .cfi_def_cfa_offset 44 ; X86-MinGW-NEXT: movl %esp, %eax @@ -2011,19 +2011,19 @@ define i32 @test_nested_unused(ptr nest %unused) #0 { ; X86-MinGW-NEXT: movl $123, %eax ; X86-MinGW-NEXT: addl $40, %esp ; X86-MinGW-NEXT: retl -; X86-MinGW-NEXT: LBB9_1: +; X86-MinGW-NEXT: LBB9_2: ; X86-MinGW-NEXT: .cfi_def_cfa_offset 4 ; X86-MinGW-NEXT: pushl $0 ; X86-MinGW-NEXT: pushl $40 ; X86-MinGW-NEXT: calll ___morestack ; X86-MinGW-NEXT: retl -; X86-MinGW-NEXT: jmp LBB9_2 +; X86-MinGW-NEXT: jmp LBB9_1 ; ; X64-FreeBSD-LABEL: test_nested_unused: ; X64-FreeBSD: # %bb.0: ; X64-FreeBSD-NEXT: cmpq %fs:24, %rsp -; X64-FreeBSD-NEXT: jbe .LBB9_1 -; X64-FreeBSD-NEXT: .LBB9_2: +; X64-FreeBSD-NEXT: jbe .LBB9_2 +; X64-FreeBSD-NEXT: .LBB9_1: ; X64-FreeBSD-NEXT: subq $40, %rsp ; X64-FreeBSD-NEXT: .cfi_def_cfa_offset 48 ; X64-FreeBSD-NEXT: movq %rsp, %rdi @@ -2033,18 +2033,18 @@ define i32 @test_nested_unused(ptr nest %unused) #0 { ; X64-FreeBSD-NEXT: addq $40, %rsp ; X64-FreeBSD-NEXT: .cfi_def_cfa_offset 8 ; X64-FreeBSD-NEXT: retq -; X64-FreeBSD-NEXT: .LBB9_1: +; X64-FreeBSD-NEXT: .LBB9_2: ; X64-FreeBSD-NEXT: movl $40, %r10d ; X64-FreeBSD-NEXT: movl $0, %r11d ; X64-FreeBSD-NEXT: callq __morestack ; X64-FreeBSD-NEXT: retq -; X64-FreeBSD-NEXT: jmp .LBB9_2 +; X64-FreeBSD-NEXT: jmp .LBB9_1 ; ; X86-DFlyBSD-LABEL: test_nested_unused: ; X86-DFlyBSD: # %bb.0: ; X86-DFlyBSD-NEXT: cmpl %fs:16, %esp -; X86-DFlyBSD-NEXT: jbe .LBB9_1 -; X86-DFlyBSD-NEXT: .LBB9_2: +; X86-DFlyBSD-NEXT: jbe .LBB9_2 +; X86-DFlyBSD-NEXT: .LBB9_1: ; X86-DFlyBSD-NEXT: subl $40, %esp ; X86-DFlyBSD-NEXT: .cfi_def_cfa_offset 44 ; X86-DFlyBSD-NEXT: movl %esp, %eax @@ -2059,18 +2059,18 @@ define i32 @test_nested_unused(ptr nest %unused) #0 { ; X86-DFlyBSD-NEXT: addl $40, %esp ; X86-DFlyBSD-NEXT: .cfi_def_cfa_offset 4 ; X86-DFlyBSD-NEXT: retl -; X86-DFlyBSD-NEXT: .LBB9_1: +; X86-DFlyBSD-NEXT: .LBB9_2: ; X86-DFlyBSD-NEXT: pushl $0 ; X86-DFlyBSD-NEXT: pushl $40 ; X86-DFlyBSD-NEXT: calll __morestack ; X86-DFlyBSD-NEXT: retl -; X86-DFlyBSD-NEXT: jmp .LBB9_2 +; X86-DFlyBSD-NEXT: jmp .LBB9_1 ; ; X64-DFlyBSD-LABEL: test_nested_unused: ; X64-DFlyBSD: # %bb.0: ; X64-DFlyBSD-NEXT: cmpq %fs:32, %rsp -; X64-DFlyBSD-NEXT: jbe .LBB9_1 -; X64-DFlyBSD-NEXT: .LBB9_2: +; X64-DFlyBSD-NEXT: jbe .LBB9_2 +; X64-DFlyBSD-NEXT: .LBB9_1: ; X64-DFlyBSD-NEXT: subq $40, %rsp ; X64-DFlyBSD-NEXT: .cfi_def_cfa_offset 48 ; X64-DFlyBSD-NEXT: movq %rsp, %rdi @@ -2080,18 +2080,18 @@ define i32 @test_nested_unused(ptr nest %unused) #0 { ; X64-DFlyBSD-NEXT: addq $40, %rsp ; X64-DFlyBSD-NEXT: .cfi_def_cfa_offset 8 ; X64-DFlyBSD-NEXT: retq -; X64-DFlyBSD-NEXT: .LBB9_1: +; X64-DFlyBSD-NEXT: .LBB9_2: ; X64-DFlyBSD-NEXT: movl $40, %r10d ; X64-DFlyBSD-NEXT: movl $0, %r11d ; X64-DFlyBSD-NEXT: callq __morestack ; X64-DFlyBSD-NEXT: retq -; X64-DFlyBSD-NEXT: jmp .LBB9_2 +; X64-DFlyBSD-NEXT: jmp .LBB9_1 ; ; X64-MinGW-LABEL: test_nested_unused: ; X64-MinGW: # %bb.0: ; X64-MinGW-NEXT: cmpq %gs:40, %rsp -; X64-MinGW-NEXT: jbe .LBB9_1 -; X64-MinGW-NEXT: .LBB9_2: +; X64-MinGW-NEXT: jbe .LBB9_2 +; X64-MinGW-NEXT: .LBB9_1: ; X64-MinGW-NEXT: subq $72, %rsp ; X64-MinGW-NEXT: .seh_stackalloc 72 ; X64-MinGW-NEXT: .seh_endprologue @@ -2103,12 +2103,12 @@ define i32 @test_nested_unused(ptr nest %unused) #0 { ; X64-MinGW-NEXT: addq $72, %rsp ; X64-MinGW-NEXT: .seh_endepilogue ; X64-MinGW-NEXT: retq -; X64-MinGW-NEXT: .LBB9_1: +; X64-MinGW-NEXT: .LBB9_2: ; X64-MinGW-NEXT: movl $72, %r10d ; X64-MinGW-NEXT: movl $32, %r11d ; X64-MinGW-NEXT: callq __morestack ; X64-MinGW-NEXT: retq -; X64-MinGW-NEXT: jmp .LBB9_2 +; X64-MinGW-NEXT: jmp .LBB9_1 ; X64-MinGW-NEXT: .seh_endproc %mem = alloca i32, i32 10 call void @dummy_use (ptr %mem, i32 10) diff --git a/llvm/test/CodeGen/X86/seh-catchpad.ll b/llvm/test/CodeGen/X86/seh-catchpad.ll index 85e465b822e1f..db2b929be315b 100644 --- a/llvm/test/CodeGen/X86/seh-catchpad.ll +++ b/llvm/test/CodeGen/X86/seh-catchpad.ll @@ -137,11 +137,11 @@ __except.ret: ; preds = %catch.dispatch.7 ; CHECK-NEXT: .long .Ltmp2@IMGREL ; CHECK-NEXT: .long .Ltmp3@IMGREL ; CHECK-NEXT: .long "?filt$0@0@main@@"@IMGREL -; CHECK-NEXT: .long .LBB1_3@IMGREL +; CHECK-NEXT: .long .LBB1_4@IMGREL ; CHECK-NEXT: .long .Ltmp6@IMGREL ; CHECK-NEXT: .long .Ltmp7@IMGREL ; CHECK-NEXT: .long "?filt$0@0@main@@"@IMGREL -; CHECK-NEXT: .long .LBB1_3@IMGREL +; CHECK-NEXT: .long .LBB1_4@IMGREL ; CHECK-NEXT: .Llsda_end0: ; CHECK: .text diff --git a/llvm/test/CodeGen/X86/seh-except-finally.ll b/llvm/test/CodeGen/X86/seh-except-finally.ll index fedb0c46d1ba1..7e674d3614eb0 100644 --- a/llvm/test/CodeGen/X86/seh-except-finally.ll +++ b/llvm/test/CodeGen/X86/seh-except-finally.ll @@ -84,7 +84,7 @@ __try.cont: ; preds = %__except, %invoke.c ; CHECK-NEXT: .Llsda_begin0: ; CHECK-NEXT: .long .Ltmp0@IMGREL ; CHECK-NEXT: .long .Ltmp1@IMGREL -; CHECK-NEXT: .long "?dtor$2@?0?use_both@4HA"@IMGREL +; CHECK-NEXT: .long "?dtor$4@?0?use_both@4HA"@IMGREL ; CHECK-NEXT: .long 0 ; CHECK-NEXT: .long .Ltmp0@IMGREL ; CHECK-NEXT: .long .Ltmp1@IMGREL diff --git a/llvm/test/CodeGen/X86/seh-except-restore.ll b/llvm/test/CodeGen/X86/seh-except-restore.ll index f428a83cc2aef..c0e4c6c0216c9 100644 --- a/llvm/test/CodeGen/X86/seh-except-restore.ll +++ b/llvm/test/CodeGen/X86/seh-except-restore.ll @@ -45,10 +45,10 @@ return: ; preds = %entry, %__except ; CHECK-LABEL: _invokewrapper: # @invokewrapper ; CHECK: calll *8(%ebp) -; CHECK: LBB0_2: # %return +; CHECK: LBB0_1: # %return -; CHECK: LBB0_1: # %__except.ret -; CHECK-NEXT: $ehgcr_0_1: +; CHECK: LBB0_2: # %__except.ret +; CHECK-NEXT: $ehgcr_0_2: ; CHECK-NEXT: movl -24(%ebp), %esp ; CHECK-NEXT: addl $12, %ebp diff --git a/llvm/test/CodeGen/X86/select-constant-xor.ll b/llvm/test/CodeGen/X86/select-constant-xor.ll index efc367d204cf1..70d91e8c92ef1 100644 --- a/llvm/test/CodeGen/X86/select-constant-xor.ll +++ b/llvm/test/CodeGen/X86/select-constant-xor.ll @@ -173,12 +173,12 @@ define i32 @icmpasreq(i32 %input, i32 %a, i32 %b) { ; X86-LABEL: icmpasreq: ; X86: # %bb.0: ; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp) -; X86-NEXT: js .LBB8_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: js .LBB8_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB8_1: +; X86-NEXT: .LBB8_2: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl @@ -199,12 +199,12 @@ define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) { ; X86-LABEL: icmpasrne: ; X86: # %bb.0: ; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp) -; X86-NEXT: jns .LBB9_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: jns .LBB9_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB9_1: +; X86-NEXT: .LBB9_2: ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: retl @@ -229,12 +229,12 @@ define i32 @oneusecmp(i32 %a, i32 %b, i32 %d) { ; X86-NEXT: sarl $31, %eax ; X86-NEXT: xorl $127, %eax ; X86-NEXT: testl %ecx, %ecx -; X86-NEXT: js .LBB10_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: js .LBB10_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: leal {{[0-9]+}}(%esp), %ecx ; X86-NEXT: addl (%ecx), %eax ; X86-NEXT: retl -; X86-NEXT: .LBB10_1: +; X86-NEXT: .LBB10_2: ; X86-NEXT: leal {{[0-9]+}}(%esp), %ecx ; X86-NEXT: addl (%ecx), %eax ; X86-NEXT: retl diff --git a/llvm/test/CodeGen/X86/select-mmx.ll b/llvm/test/CodeGen/X86/select-mmx.ll index 8a4308a5af64b..e32d3d366d12e 100644 --- a/llvm/test/CodeGen/X86/select-mmx.ll +++ b/llvm/test/CodeGen/X86/select-mmx.ll @@ -87,11 +87,11 @@ define i64 @test49(i64 %arg, i64 %x, i64 %y) { ; X86-NEXT: subl $8, %esp ; X86-NEXT: movl 8(%ebp), %eax ; X86-NEXT: orl 12(%ebp), %eax -; X86-NEXT: je .LBB1_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: je .LBB1_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: leal 24(%ebp), %eax ; X86-NEXT: jmp .LBB1_3 -; X86-NEXT: .LBB1_1: +; X86-NEXT: .LBB1_2: ; X86-NEXT: leal 16(%ebp), %eax ; X86-NEXT: .LBB1_3: ; X86-NEXT: movq (%eax), %mm0 diff --git a/llvm/test/CodeGen/X86/select-smin-smax.ll b/llvm/test/CodeGen/X86/select-smin-smax.ll index 3c2ec52f2c261..0deb4fceaa876 100644 --- a/llvm/test/CodeGen/X86/select-smin-smax.ll +++ b/llvm/test/CodeGen/X86/select-smin-smax.ll @@ -203,15 +203,15 @@ define i64 @test_i64_smax(i64 %a) nounwind { ; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NOBMI-NEXT: testl %edx, %edx ; X86-NOBMI-NEXT: movl $0, %eax -; X86-NOBMI-NEXT: jns .LBB6_1 -; X86-NOBMI-NEXT: # %bb.2: -; X86-NOBMI-NEXT: jle .LBB6_3 -; X86-NOBMI-NEXT: .LBB6_4: +; X86-NOBMI-NEXT: jns .LBB6_3 +; X86-NOBMI-NEXT: # %bb.1: +; X86-NOBMI-NEXT: jle .LBB6_4 +; X86-NOBMI-NEXT: .LBB6_2: ; X86-NOBMI-NEXT: retl -; X86-NOBMI-NEXT: .LBB6_1: -; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax -; X86-NOBMI-NEXT: jg .LBB6_4 ; X86-NOBMI-NEXT: .LBB6_3: +; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NOBMI-NEXT: jg .LBB6_2 +; X86-NOBMI-NEXT: .LBB6_4: ; X86-NOBMI-NEXT: xorl %edx, %edx ; X86-NOBMI-NEXT: retl %r = call i64 @llvm.smax.i64(i64 %a, i64 0) diff --git a/llvm/test/CodeGen/X86/select-testb-volatile-load.ll b/llvm/test/CodeGen/X86/select-testb-volatile-load.ll index 2490fbdaf614c..b5953dfda3190 100644 --- a/llvm/test/CodeGen/X86/select-testb-volatile-load.ll +++ b/llvm/test/CodeGen/X86/select-testb-volatile-load.ll @@ -9,11 +9,11 @@ define void @testb_volatile(ptr%ptrptr) { ; CHECK: ## %bb.0: ## %entry ; CHECK-NEXT: movq (%rdi), %rax ; CHECK-NEXT: testl $1, (%rax) -; CHECK-NEXT: jne LBB0_1 -; CHECK-NEXT: ## %bb.2: ## %exit +; CHECK-NEXT: jne LBB0_2 +; CHECK-NEXT: ## %bb.1: ## %exit ; CHECK-NEXT: movl $1, (%rax) ; CHECK-NEXT: retq -; CHECK-NEXT: LBB0_1: ## %bb2 +; CHECK-NEXT: LBB0_2: ## %bb2 ; CHECK-NEXT: movl $0, (%rax) ; CHECK-NEXT: retq entry: diff --git a/llvm/test/CodeGen/X86/select-to-and-zext.ll b/llvm/test/CodeGen/X86/select-to-and-zext.ll index 7dadbd76a5bb1..63a2f597f5c9c 100644 --- a/llvm/test/CodeGen/X86/select-to-and-zext.ll +++ b/llvm/test/CodeGen/X86/select-to-and-zext.ll @@ -29,11 +29,11 @@ define i32 @from_cmpeq_fail_bad_andmask(i32 %xx, i32 %y) { ; X86-LABEL: from_cmpeq_fail_bad_andmask: ; X86: # %bb.0: ; X86-NEXT: cmpl $9, {{[0-9]+}}(%esp) -; X86-NEXT: je .LBB1_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: je .LBB1_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: xorl %eax, %eax ; X86-NEXT: retl -; X86-NEXT: .LBB1_1: +; X86-NEXT: .LBB1_2: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: andl $3, %eax ; X86-NEXT: retl @@ -115,11 +115,11 @@ define i32 @from_i1_fail_bad_select0(i1 %x, i32 %y) { ; X86-LABEL: from_i1_fail_bad_select0: ; X86: # %bb.0: ; X86-NEXT: testb $1, {{[0-9]+}}(%esp) -; X86-NEXT: jne .LBB5_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: jne .LBB5_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: movl $1, %eax ; X86-NEXT: retl -; X86-NEXT: .LBB5_1: +; X86-NEXT: .LBB5_2: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: andl $1, %eax ; X86-NEXT: retl diff --git a/llvm/test/CodeGen/X86/select.ll b/llvm/test/CodeGen/X86/select.ll index fe90028aa6aff..1fbbae57c3d37 100644 --- a/llvm/test/CodeGen/X86/select.ll +++ b/llvm/test/CodeGen/X86/select.ll @@ -61,12 +61,12 @@ define i32 @test2() nounwind { ; GENERIC-NEXT: movl $-3840, %eax ## imm = 0xF100 ; GENERIC-NEXT: cmovnel %ecx, %eax ; GENERIC-NEXT: cmpl $32768, %eax ## imm = 0x8000 -; GENERIC-NEXT: jge LBB1_1 -; GENERIC-NEXT: ## %bb.2: ## %bb91 +; GENERIC-NEXT: jge LBB1_2 +; GENERIC-NEXT: ## %bb.1: ## %bb91 ; GENERIC-NEXT: xorl %eax, %eax ; GENERIC-NEXT: popq %rcx ; GENERIC-NEXT: retq -; GENERIC-NEXT: LBB1_1: ## %bb90 +; GENERIC-NEXT: LBB1_2: ## %bb90 ; GENERIC-NEXT: ud2 ; ; ATOM-LABEL: test2: @@ -78,12 +78,12 @@ define i32 @test2() nounwind { ; ATOM-NEXT: testb $1, %al ; ATOM-NEXT: cmovnel %ecx, %edx ; ATOM-NEXT: cmpl $32768, %edx ## imm = 0x8000 -; ATOM-NEXT: jge LBB1_1 -; ATOM-NEXT: ## %bb.2: ## %bb91 +; ATOM-NEXT: jge LBB1_2 +; ATOM-NEXT: ## %bb.1: ## %bb91 ; ATOM-NEXT: xorl %eax, %eax ; ATOM-NEXT: popq %rcx ; ATOM-NEXT: retq -; ATOM-NEXT: LBB1_1: ## %bb90 +; ATOM-NEXT: LBB1_2: ## %bb90 ; ATOM-NEXT: ud2 ; ; ATHLON-LABEL: test2: @@ -95,12 +95,12 @@ define i32 @test2() nounwind { ; ATHLON-NEXT: movl $-3840, %eax ## imm = 0xF100 ; ATHLON-NEXT: cmovnel %ecx, %eax ; ATHLON-NEXT: cmpl $32768, %eax ## imm = 0x8000 -; ATHLON-NEXT: jge LBB1_1 -; ATHLON-NEXT: ## %bb.2: ## %bb91 +; ATHLON-NEXT: jge LBB1_2 +; ATHLON-NEXT: ## %bb.1: ## %bb91 ; ATHLON-NEXT: xorl %eax, %eax ; ATHLON-NEXT: addl $12, %esp ; ATHLON-NEXT: retl -; ATHLON-NEXT: LBB1_1: ## %bb90 +; ATHLON-NEXT: LBB1_2: ## %bb90 ; ATHLON-NEXT: ud2 ; ; MCU-LABEL: test2: @@ -111,11 +111,11 @@ define i32 @test2() nounwind { ; MCU-NEXT: decl %eax ; MCU-NEXT: andl $-3840, %eax # imm = 0xF100 ; MCU-NEXT: cmpl $32768, %eax # imm = 0x8000 -; MCU-NEXT: jge .LBB1_1 -; MCU-NEXT: # %bb.2: # %bb91 +; MCU-NEXT: jge .LBB1_2 +; MCU-NEXT: # %bb.1: # %bb91 ; MCU-NEXT: xorl %eax, %eax ; MCU-NEXT: retl -; MCU-NEXT: .LBB1_1: # %bb90 +; MCU-NEXT: .LBB1_2: # %bb90 entry: %tmp73 = tail call i1 @return_false() %g.0 = select i1 %tmp73, i16 0, i16 -480 @@ -280,12 +280,12 @@ define void @test6(i32 %C, ptr %A, ptr %B) nounwind { ; CHECK-LABEL: test6: ; CHECK: ## %bb.0: ; CHECK-NEXT: testl %edi, %edi -; CHECK-NEXT: je LBB5_1 -; CHECK-NEXT: ## %bb.2: +; CHECK-NEXT: je LBB5_2 +; CHECK-NEXT: ## %bb.1: ; CHECK-NEXT: movaps (%rsi), %xmm0 ; CHECK-NEXT: movaps %xmm0, (%rsi) ; CHECK-NEXT: retq -; CHECK-NEXT: LBB5_1: +; CHECK-NEXT: LBB5_2: ; CHECK-NEXT: movaps (%rdx), %xmm0 ; CHECK-NEXT: mulps %xmm0, %xmm0 ; CHECK-NEXT: movaps %xmm0, (%rsi) @@ -435,8 +435,8 @@ define void @test8(i1 %c, ptr %dst.addr, <6 x i32> %src1,<6 x i32> %src2) nounwi ; GENERIC-LABEL: test8: ; GENERIC: ## %bb.0: ; GENERIC-NEXT: testb $1, %dil -; GENERIC-NEXT: jne LBB7_1 -; GENERIC-NEXT: ## %bb.2: +; GENERIC-NEXT: jne LBB7_2 +; GENERIC-NEXT: ## %bb.1: ; GENERIC-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; GENERIC-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero ; GENERIC-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] @@ -447,7 +447,7 @@ define void @test8(i1 %c, ptr %dst.addr, <6 x i32> %src1,<6 x i32> %src2) nounwi ; GENERIC-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero ; GENERIC-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero ; GENERIC-NEXT: jmp LBB7_3 -; GENERIC-NEXT: LBB7_1: +; GENERIC-NEXT: LBB7_2: ; GENERIC-NEXT: movd %r9d, %xmm0 ; GENERIC-NEXT: movd %r8d, %xmm1 ; GENERIC-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] @@ -469,8 +469,8 @@ define void @test8(i1 %c, ptr %dst.addr, <6 x i32> %src1,<6 x i32> %src2) nounwi ; ATOM-LABEL: test8: ; ATOM: ## %bb.0: ; ATOM-NEXT: testb $1, %dil -; ATOM-NEXT: jne LBB7_1 -; ATOM-NEXT: ## %bb.2: +; ATOM-NEXT: jne LBB7_2 +; ATOM-NEXT: ## %bb.1: ; ATOM-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero ; ATOM-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero ; ATOM-NEXT: movd {{.*#+}} xmm3 = mem[0],zero,zero,zero @@ -480,7 +480,7 @@ define void @test8(i1 %c, ptr %dst.addr, <6 x i32> %src1,<6 x i32> %src2) nounwi ; ATOM-NEXT: movd {{.*#+}} xmm3 = mem[0],zero,zero,zero ; ATOM-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero ; ATOM-NEXT: jmp LBB7_3 -; ATOM-NEXT: LBB7_1: +; ATOM-NEXT: LBB7_2: ; ATOM-NEXT: movd %r9d, %xmm1 ; ATOM-NEXT: movd %r8d, %xmm2 ; ATOM-NEXT: movd %ecx, %xmm3 @@ -556,49 +556,49 @@ define void @test8(i1 %c, ptr %dst.addr, <6 x i32> %src1,<6 x i32> %src2) nounwi ; MCU-NEXT: pushl %edi ; MCU-NEXT: pushl %esi ; MCU-NEXT: testb $1, %al -; MCU-NEXT: jne .LBB7_1 -; MCU-NEXT: # %bb.2: +; MCU-NEXT: jne .LBB7_6 +; MCU-NEXT: # %bb.1: ; MCU-NEXT: leal {{[0-9]+}}(%esp), %edi -; MCU-NEXT: je .LBB7_5 -; MCU-NEXT: .LBB7_4: +; MCU-NEXT: je .LBB7_7 +; MCU-NEXT: .LBB7_2: ; MCU-NEXT: leal {{[0-9]+}}(%esp), %ecx ; MCU-NEXT: je .LBB7_8 -; MCU-NEXT: .LBB7_7: +; MCU-NEXT: .LBB7_3: ; MCU-NEXT: leal {{[0-9]+}}(%esp), %esi -; MCU-NEXT: je .LBB7_11 -; MCU-NEXT: .LBB7_10: +; MCU-NEXT: je .LBB7_9 +; MCU-NEXT: .LBB7_4: ; MCU-NEXT: leal {{[0-9]+}}(%esp), %ebp -; MCU-NEXT: je .LBB7_14 -; MCU-NEXT: .LBB7_13: +; MCU-NEXT: je .LBB7_10 +; MCU-NEXT: .LBB7_5: ; MCU-NEXT: leal {{[0-9]+}}(%esp), %eax -; MCU-NEXT: jmp .LBB7_15 -; MCU-NEXT: .LBB7_1: +; MCU-NEXT: jmp .LBB7_11 +; MCU-NEXT: .LBB7_6: ; MCU-NEXT: leal {{[0-9]+}}(%esp), %edi -; MCU-NEXT: jne .LBB7_4 -; MCU-NEXT: .LBB7_5: +; MCU-NEXT: jne .LBB7_2 +; MCU-NEXT: .LBB7_7: ; MCU-NEXT: leal {{[0-9]+}}(%esp), %ecx -; MCU-NEXT: jne .LBB7_7 +; MCU-NEXT: jne .LBB7_3 ; MCU-NEXT: .LBB7_8: ; MCU-NEXT: leal {{[0-9]+}}(%esp), %esi -; MCU-NEXT: jne .LBB7_10 -; MCU-NEXT: .LBB7_11: +; MCU-NEXT: jne .LBB7_4 +; MCU-NEXT: .LBB7_9: ; MCU-NEXT: leal {{[0-9]+}}(%esp), %ebp -; MCU-NEXT: jne .LBB7_13 -; MCU-NEXT: .LBB7_14: +; MCU-NEXT: jne .LBB7_5 +; MCU-NEXT: .LBB7_10: ; MCU-NEXT: leal {{[0-9]+}}(%esp), %eax -; MCU-NEXT: .LBB7_15: +; MCU-NEXT: .LBB7_11: ; MCU-NEXT: movl (%edi), %ebx ; MCU-NEXT: movl (%ecx), %edi ; MCU-NEXT: movl (%esi), %esi ; MCU-NEXT: movl (%ebp), %ecx ; MCU-NEXT: movl (%eax), %eax -; MCU-NEXT: jne .LBB7_16 -; MCU-NEXT: # %bb.17: +; MCU-NEXT: jne .LBB7_13 +; MCU-NEXT: # %bb.12: ; MCU-NEXT: leal {{[0-9]+}}(%esp), %ebp -; MCU-NEXT: jmp .LBB7_18 -; MCU-NEXT: .LBB7_16: +; MCU-NEXT: jmp .LBB7_14 +; MCU-NEXT: .LBB7_13: ; MCU-NEXT: leal {{[0-9]+}}(%esp), %ebp -; MCU-NEXT: .LBB7_18: +; MCU-NEXT: .LBB7_14: ; MCU-NEXT: movl (%ebp), %ebp ; MCU-NEXT: decl %ebp ; MCU-NEXT: decl %eax @@ -651,12 +651,12 @@ define i64 @test9(i64 %x, i64 %y) nounwind readnone ssp noredzone { ; MCU-LABEL: test9: ; MCU: # %bb.0: ; MCU-NEXT: orl %edx, %eax -; MCU-NEXT: jne .LBB8_1 -; MCU-NEXT: # %bb.2: +; MCU-NEXT: jne .LBB8_2 +; MCU-NEXT: # %bb.1: ; MCU-NEXT: movl $-1, %eax ; MCU-NEXT: movl $-1, %edx ; MCU-NEXT: retl -; MCU-NEXT: .LBB8_1: +; MCU-NEXT: .LBB8_2: ; MCU-NEXT: movl {{[0-9]+}}(%esp), %eax ; MCU-NEXT: movl {{[0-9]+}}(%esp), %edx ; MCU-NEXT: retl @@ -803,12 +803,12 @@ define i64 @test11(i64 %x, i64 %y) nounwind readnone ssp noredzone { ; MCU-LABEL: test11: ; MCU: # %bb.0: ; MCU-NEXT: orl %edx, %eax -; MCU-NEXT: je .LBB12_1 -; MCU-NEXT: # %bb.2: +; MCU-NEXT: je .LBB12_2 +; MCU-NEXT: # %bb.1: ; MCU-NEXT: movl $-1, %eax ; MCU-NEXT: movl $-1, %edx ; MCU-NEXT: retl -; MCU-NEXT: .LBB12_1: +; MCU-NEXT: .LBB12_2: ; MCU-NEXT: movl {{[0-9]+}}(%esp), %eax ; MCU-NEXT: movl {{[0-9]+}}(%esp), %edx ; MCU-NEXT: retl diff --git a/llvm/test/CodeGen/X86/select_const.ll b/llvm/test/CodeGen/X86/select_const.ll index 35f4655dd6d7c..cda5c45649c3d 100644 --- a/llvm/test/CodeGen/X86/select_const.ll +++ b/llvm/test/CodeGen/X86/select_const.ll @@ -349,17 +349,17 @@ define i64 @select_lea_3(i1 zeroext %cond) { ; X86: # %bb.0: ; X86-NEXT: cmpb $0, {{[0-9]+}}(%esp) ; X86-NEXT: movl $-2, %eax -; X86-NEXT: je .LBB19_1 -; X86-NEXT: # %bb.2: -; X86-NEXT: movl $-1, %edx ; X86-NEXT: je .LBB19_3 -; X86-NEXT: .LBB19_4: +; X86-NEXT: # %bb.1: +; X86-NEXT: movl $-1, %edx +; X86-NEXT: je .LBB19_4 +; X86-NEXT: .LBB19_2: ; X86-NEXT: retl -; X86-NEXT: .LBB19_1: +; X86-NEXT: .LBB19_3: ; X86-NEXT: movl $1, %eax ; X86-NEXT: movl $-1, %edx -; X86-NEXT: jne .LBB19_4 -; X86-NEXT: .LBB19_3: +; X86-NEXT: jne .LBB19_2 +; X86-NEXT: .LBB19_4: ; X86-NEXT: xorl %edx, %edx ; X86-NEXT: retl ; @@ -397,17 +397,17 @@ define i64 @select_lea_9(i1 zeroext %cond) { ; X86: # %bb.0: ; X86-NEXT: cmpb $0, {{[0-9]+}}(%esp) ; X86-NEXT: movl $-7, %eax -; X86-NEXT: je .LBB21_1 -; X86-NEXT: # %bb.2: -; X86-NEXT: movl $-1, %edx ; X86-NEXT: je .LBB21_3 -; X86-NEXT: .LBB21_4: +; X86-NEXT: # %bb.1: +; X86-NEXT: movl $-1, %edx +; X86-NEXT: je .LBB21_4 +; X86-NEXT: .LBB21_2: ; X86-NEXT: retl -; X86-NEXT: .LBB21_1: +; X86-NEXT: .LBB21_3: ; X86-NEXT: movl $2, %eax ; X86-NEXT: movl $-1, %edx -; X86-NEXT: jne .LBB21_4 -; X86-NEXT: .LBB21_3: +; X86-NEXT: jne .LBB21_2 +; X86-NEXT: .LBB21_4: ; X86-NEXT: xorl %edx, %edx ; X86-NEXT: retl ; @@ -610,17 +610,17 @@ define i64 @select_pow2_diff_neg_invert(i1 zeroext %cond) { ; X86: # %bb.0: ; X86-NEXT: cmpb $0, {{[0-9]+}}(%esp) ; X86-NEXT: movl $-99, %eax -; X86-NEXT: je .LBB30_1 -; X86-NEXT: # %bb.2: -; X86-NEXT: movl $-1, %edx ; X86-NEXT: je .LBB30_3 -; X86-NEXT: .LBB30_4: +; X86-NEXT: # %bb.1: +; X86-NEXT: movl $-1, %edx +; X86-NEXT: je .LBB30_4 +; X86-NEXT: .LBB30_2: ; X86-NEXT: retl -; X86-NEXT: .LBB30_1: +; X86-NEXT: .LBB30_3: ; X86-NEXT: movl $29, %eax ; X86-NEXT: movl $-1, %edx -; X86-NEXT: jne .LBB30_4 -; X86-NEXT: .LBB30_3: +; X86-NEXT: jne .LBB30_2 +; X86-NEXT: .LBB30_4: ; X86-NEXT: xorl %edx, %edx ; X86-NEXT: retl ; @@ -832,11 +832,11 @@ define <4 x i32> @sel_constants_add_constant_vec(i1 %cond) { ; X64-LABEL: sel_constants_add_constant_vec: ; X64: # %bb.0: ; X64-NEXT: testb $1, %dil -; X64-NEXT: jne .LBB37_1 -; X64-NEXT: # %bb.2: +; X64-NEXT: jne .LBB37_2 +; X64-NEXT: # %bb.1: ; X64-NEXT: movaps {{.*#+}} xmm0 = [12,13,14,15] ; X64-NEXT: retq -; X64-NEXT: .LBB37_1: +; X64-NEXT: .LBB37_2: ; X64-NEXT: movaps {{.*#+}} xmm0 = [4294967293,14,4,4] ; X64-NEXT: retq %sel = select i1 %cond, <4 x i32> , <4 x i32> @@ -869,11 +869,11 @@ define <2 x double> @sel_constants_fmul_constant_vec(i1 %cond) { ; X64-LABEL: sel_constants_fmul_constant_vec: ; X64: # %bb.0: ; X64-NEXT: testb $1, %dil -; X64-NEXT: jne .LBB38_1 -; X64-NEXT: # %bb.2: +; X64-NEXT: jne .LBB38_2 +; X64-NEXT: # %bb.1: ; X64-NEXT: movaps {{.*#+}} xmm0 = [1.1883E+2,3.4539999999999999E+1] ; X64-NEXT: retq -; X64-NEXT: .LBB38_1: +; X64-NEXT: .LBB38_2: ; X64-NEXT: movaps {{.*#+}} xmm0 = [-2.0399999999999999E+1,3.768E+1] ; X64-NEXT: retq %sel = select i1 %cond, <2 x double> , <2 x double> diff --git a/llvm/test/CodeGen/X86/setcc-freeze.ll b/llvm/test/CodeGen/X86/setcc-freeze.ll index 0fa5e757ec759..506e23cf8d884 100644 --- a/llvm/test/CodeGen/X86/setcc-freeze.ll +++ b/llvm/test/CodeGen/X86/setcc-freeze.ll @@ -5,11 +5,11 @@ define i32 @f(ptr %p) { ; CHECK-LABEL: f: ; CHECK: # %bb.0: ; CHECK-NEXT: testb $8, 1(%rdi) -; CHECK-NEXT: je .LBB0_1 -; CHECK-NEXT: # %bb.2: # %B +; CHECK-NEXT: je .LBB0_2 +; CHECK-NEXT: # %bb.1: # %B ; CHECK-NEXT: movl $20, %eax ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB0_1: # %A +; CHECK-NEXT: .LBB0_2: # %A ; CHECK-NEXT: movl $10, %eax ; CHECK-NEXT: retq %v = load i16, ptr %p, align 2 diff --git a/llvm/test/CodeGen/X86/setuge.ll b/llvm/test/CodeGen/X86/setuge.ll index c04287b7808c2..7cbc37327ec2d 100644 --- a/llvm/test/CodeGen/X86/setuge.ll +++ b/llvm/test/CodeGen/X86/setuge.ll @@ -14,12 +14,12 @@ define float @cmp(float %A, float %B, float %C, float %D) nounwind { ; CHECK-NEXT: fnstsw %ax ; CHECK-NEXT: # kill: def $ah killed $ah killed $ax ; CHECK-NEXT: sahf -; CHECK-NEXT: jbe .LBB0_1 -; CHECK-NEXT: # %bb.2: # %entry +; CHECK-NEXT: jbe .LBB0_2 +; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: leal {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: flds (%eax) ; CHECK-NEXT: retl -; CHECK-NEXT: .LBB0_1: +; CHECK-NEXT: .LBB0_2: ; CHECK-NEXT: leal {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: flds (%eax) ; CHECK-NEXT: retl diff --git a/llvm/test/CodeGen/X86/shadow-stack.ll b/llvm/test/CodeGen/X86/shadow-stack.ll index bf0a00732b88a..da1c8f8afa9ff 100644 --- a/llvm/test/CodeGen/X86/shadow-stack.ll +++ b/llvm/test/CodeGen/X86/shadow-stack.ll @@ -133,22 +133,22 @@ define i32 @foo(i32 %i) local_unnamed_addr { ; X86_64-NEXT: movq (%rax), %rax ; X86_64-NEXT: movq %rbp, (%rax) ; X86_64-NEXT: movq %rsp, 16(%rax) -; X86_64-NEXT: leaq LBB1_4(%rip), %rcx +; X86_64-NEXT: leaq LBB1_2(%rip), %rcx ; X86_64-NEXT: movq %rcx, 8(%rax) ; X86_64-NEXT: xorq %rcx, %rcx ; X86_64-NEXT: rdsspq %rcx ; X86_64-NEXT: movq %rcx, 24(%rax) -; X86_64-NEXT: #EH_SjLj_Setup LBB1_4 +; X86_64-NEXT: #EH_SjLj_Setup LBB1_2 ; X86_64-NEXT: ## %bb.1: ## %entry ; X86_64-NEXT: xorl %eax, %eax -; X86_64-NEXT: jmp LBB1_2 -; X86_64-NEXT: LBB1_4: ## Block address taken +; X86_64-NEXT: jmp LBB1_3 +; X86_64-NEXT: LBB1_2: ## Block address taken ; X86_64-NEXT: ## %entry ; X86_64-NEXT: movl $1, %eax -; X86_64-NEXT: LBB1_2: ## %entry +; X86_64-NEXT: LBB1_3: ## %entry ; X86_64-NEXT: testl %eax, %eax ; X86_64-NEXT: je LBB1_5 -; X86_64-NEXT: ## %bb.3: ## %if.end +; X86_64-NEXT: ## %bb.4: ## %if.end ; X86_64-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax ## 8-byte Reload ; X86_64-NEXT: shll $2, %eax ; X86_64-NEXT: leal (%rax,%rax,2), %eax @@ -182,21 +182,21 @@ define i32 @foo(i32 %i) local_unnamed_addr { ; X86-NEXT: movl (%eax), %eax ; X86-NEXT: movl %ebp, (%eax) ; X86-NEXT: movl %esp, 16(%eax) -; X86-NEXT: movl $LBB1_4, 4(%eax) +; X86-NEXT: movl $LBB1_2, 4(%eax) ; X86-NEXT: xorl %ecx, %ecx ; X86-NEXT: rdsspd %ecx ; X86-NEXT: movl %ecx, 12(%eax) -; X86-NEXT: #EH_SjLj_Setup LBB1_4 +; X86-NEXT: #EH_SjLj_Setup LBB1_2 ; X86-NEXT: ## %bb.1: ## %entry ; X86-NEXT: xorl %eax, %eax -; X86-NEXT: jmp LBB1_2 -; X86-NEXT: LBB1_4: ## Block address taken +; X86-NEXT: jmp LBB1_3 +; X86-NEXT: LBB1_2: ## Block address taken ; X86-NEXT: ## %entry ; X86-NEXT: movl $1, %eax -; X86-NEXT: LBB1_2: ## %entry +; X86-NEXT: LBB1_3: ## %entry ; X86-NEXT: testl %eax, %eax ; X86-NEXT: je LBB1_5 -; X86-NEXT: ## %bb.3: ## %if.end +; X86-NEXT: ## %bb.4: ## %if.end ; X86-NEXT: movl 8(%ebp), %eax ; X86-NEXT: shll $2, %eax ; X86-NEXT: leal (%eax,%eax,2), %eax diff --git a/llvm/test/CodeGen/X86/shift-combine.ll b/llvm/test/CodeGen/X86/shift-combine.ll index dfeef48897e06..034a209abe7c6 100644 --- a/llvm/test/CodeGen/X86/shift-combine.ll +++ b/llvm/test/CodeGen/X86/shift-combine.ll @@ -391,16 +391,16 @@ define dso_local void @PR42880(i32 %t0) { ; X86-LABEL: PR42880: ; X86: # %bb.0: ; X86-NEXT: testb %al, %al -; X86-NEXT: je .LBB16_1 -; X86-NEXT: # %bb.2: # %if -; X86-NEXT: .LBB16_1: # %then +; X86-NEXT: je .LBB16_2 +; X86-NEXT: # %bb.1: # %if +; X86-NEXT: .LBB16_2: # %then ; ; X64-LABEL: PR42880: ; X64: # %bb.0: ; X64-NEXT: testb %al, %al -; X64-NEXT: je .LBB16_1 -; X64-NEXT: # %bb.2: # %if -; X64-NEXT: .LBB16_1: # %then +; X64-NEXT: je .LBB16_2 +; X64-NEXT: # %bb.1: # %if +; X64-NEXT: .LBB16_2: # %then %sub = add nsw i32 %t0, -1 %add.ptr.i94 = getelementptr inbounds %"class.QPainterPath", ptr null, i32 %sub %x = ptrtoint ptr %add.ptr.i94 to i32 diff --git a/llvm/test/CodeGen/X86/shrink-compare-pgso.ll b/llvm/test/CodeGen/X86/shrink-compare-pgso.ll index 5a15ee36c0726..77ddb5176e67b 100644 --- a/llvm/test/CodeGen/X86/shrink-compare-pgso.ll +++ b/llvm/test/CodeGen/X86/shrink-compare-pgso.ll @@ -70,11 +70,11 @@ define i1 @test4(i64 %a, i32 %b) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: testl %esi, %esi -; CHECK-NEXT: je .LBB3_1 -; CHECK-NEXT: # %bb.2: # %lor.end +; CHECK-NEXT: je .LBB3_2 +; CHECK-NEXT: # %bb.1: # %lor.end ; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB3_1: # %lor.rhs +; CHECK-NEXT: .LBB3_2: # %lor.rhs ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: retq diff --git a/llvm/test/CodeGen/X86/shrink-compare.ll b/llvm/test/CodeGen/X86/shrink-compare.ll index 1a61451c26a03..398f5fa7a7072 100644 --- a/llvm/test/CodeGen/X86/shrink-compare.ll +++ b/llvm/test/CodeGen/X86/shrink-compare.ll @@ -70,11 +70,11 @@ define i1 @test4(i64 %a, i32 %b) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: testl %esi, %esi -; CHECK-NEXT: je .LBB3_1 -; CHECK-NEXT: # %bb.2: # %lor.end +; CHECK-NEXT: je .LBB3_2 +; CHECK-NEXT: # %bb.1: # %lor.end ; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB3_1: # %lor.rhs +; CHECK-NEXT: .LBB3_2: # %lor.rhs ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: retq diff --git a/llvm/test/CodeGen/X86/shuffle-half.ll b/llvm/test/CodeGen/X86/shuffle-half.ll index cc7bfb58c329b..d05db21471eb5 100644 --- a/llvm/test/CodeGen/X86/shuffle-half.ll +++ b/llvm/test/CodeGen/X86/shuffle-half.ll @@ -21,328 +21,328 @@ define <32 x half> @build_vec(ptr %p, <32 x i1> %mask) { ; CHECK-NEXT: vpsllw $7, %ymm0, %ymm0 ; CHECK-NEXT: vpmovmskb %ymm0, %eax ; CHECK-NEXT: testb $1, %al -; CHECK-NEXT: je .LBB1_1 -; CHECK-NEXT: # %bb.2: # %cond.load +; CHECK-NEXT: je .LBB1_2 +; CHECK-NEXT: # %bb.1: # %cond.load ; CHECK-NEXT: vpinsrw $0, (%rdi), %xmm0, %xmm0 ; CHECK-NEXT: vpbroadcastd {{.*#+}} zmm1 = [2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0] ; CHECK-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3,4,5,6,7] ; CHECK-NEXT: vinserti32x4 $0, %xmm0, %zmm1, %zmm0 ; CHECK-NEXT: testb $2, %al -; CHECK-NEXT: jne .LBB1_4 -; CHECK-NEXT: jmp .LBB1_5 -; CHECK-NEXT: .LBB1_1: +; CHECK-NEXT: jne .LBB1_3 +; CHECK-NEXT: jmp .LBB1_4 +; CHECK-NEXT: .LBB1_2: ; CHECK-NEXT: vpbroadcastw {{.*#+}} ymm0 = [2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0,2.0E+0] ; CHECK-NEXT: vinserti64x4 $1, %ymm0, %zmm0, %zmm0 ; CHECK-NEXT: testb $2, %al -; CHECK-NEXT: je .LBB1_5 -; CHECK-NEXT: .LBB1_4: # %cond.load1 +; CHECK-NEXT: je .LBB1_4 +; CHECK-NEXT: .LBB1_3: # %cond.load1 ; CHECK-NEXT: vpbroadcastw 2(%rdi), %xmm1 ; CHECK-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2,3,4,5,6,7] ; CHECK-NEXT: vinserti32x4 $0, %xmm1, %zmm0, %zmm0 -; CHECK-NEXT: .LBB1_5: # %else2 +; CHECK-NEXT: .LBB1_4: # %else2 ; CHECK-NEXT: testb $4, %al -; CHECK-NEXT: jne .LBB1_6 -; CHECK-NEXT: # %bb.7: # %else5 +; CHECK-NEXT: jne .LBB1_35 +; CHECK-NEXT: # %bb.5: # %else5 ; CHECK-NEXT: testb $8, %al -; CHECK-NEXT: jne .LBB1_8 -; CHECK-NEXT: .LBB1_9: # %else8 +; CHECK-NEXT: jne .LBB1_36 +; CHECK-NEXT: .LBB1_6: # %else8 ; CHECK-NEXT: testb $16, %al -; CHECK-NEXT: jne .LBB1_10 -; CHECK-NEXT: .LBB1_11: # %else11 +; CHECK-NEXT: jne .LBB1_37 +; CHECK-NEXT: .LBB1_7: # %else11 ; CHECK-NEXT: testb $32, %al -; CHECK-NEXT: jne .LBB1_12 -; CHECK-NEXT: .LBB1_13: # %else14 +; CHECK-NEXT: jne .LBB1_38 +; CHECK-NEXT: .LBB1_8: # %else14 ; CHECK-NEXT: testb $64, %al -; CHECK-NEXT: jne .LBB1_14 -; CHECK-NEXT: .LBB1_15: # %else17 +; CHECK-NEXT: jne .LBB1_39 +; CHECK-NEXT: .LBB1_9: # %else17 ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: js .LBB1_16 -; CHECK-NEXT: .LBB1_17: # %else20 +; CHECK-NEXT: js .LBB1_40 +; CHECK-NEXT: .LBB1_10: # %else20 ; CHECK-NEXT: testl $256, %eax # imm = 0x100 -; CHECK-NEXT: jne .LBB1_18 -; CHECK-NEXT: .LBB1_19: # %else23 +; CHECK-NEXT: jne .LBB1_41 +; CHECK-NEXT: .LBB1_11: # %else23 ; CHECK-NEXT: testl $512, %eax # imm = 0x200 -; CHECK-NEXT: jne .LBB1_20 -; CHECK-NEXT: .LBB1_21: # %else26 +; CHECK-NEXT: jne .LBB1_42 +; CHECK-NEXT: .LBB1_12: # %else26 ; CHECK-NEXT: testl $1024, %eax # imm = 0x400 -; CHECK-NEXT: jne .LBB1_22 -; CHECK-NEXT: .LBB1_23: # %else29 +; CHECK-NEXT: jne .LBB1_43 +; CHECK-NEXT: .LBB1_13: # %else29 ; CHECK-NEXT: testl $2048, %eax # imm = 0x800 -; CHECK-NEXT: jne .LBB1_24 -; CHECK-NEXT: .LBB1_25: # %else32 +; CHECK-NEXT: jne .LBB1_44 +; CHECK-NEXT: .LBB1_14: # %else32 ; CHECK-NEXT: testl $4096, %eax # imm = 0x1000 -; CHECK-NEXT: jne .LBB1_26 -; CHECK-NEXT: .LBB1_27: # %else35 +; CHECK-NEXT: jne .LBB1_45 +; CHECK-NEXT: .LBB1_15: # %else35 ; CHECK-NEXT: testl $8192, %eax # imm = 0x2000 -; CHECK-NEXT: jne .LBB1_28 -; CHECK-NEXT: .LBB1_29: # %else38 +; CHECK-NEXT: jne .LBB1_46 +; CHECK-NEXT: .LBB1_16: # %else38 ; CHECK-NEXT: testl $16384, %eax # imm = 0x4000 -; CHECK-NEXT: jne .LBB1_30 -; CHECK-NEXT: .LBB1_31: # %else41 +; CHECK-NEXT: jne .LBB1_47 +; CHECK-NEXT: .LBB1_17: # %else41 ; CHECK-NEXT: testw %ax, %ax -; CHECK-NEXT: js .LBB1_32 -; CHECK-NEXT: .LBB1_33: # %else44 +; CHECK-NEXT: js .LBB1_48 +; CHECK-NEXT: .LBB1_18: # %else44 ; CHECK-NEXT: testl $65536, %eax # imm = 0x10000 -; CHECK-NEXT: jne .LBB1_34 -; CHECK-NEXT: .LBB1_35: # %else47 +; CHECK-NEXT: jne .LBB1_49 +; CHECK-NEXT: .LBB1_19: # %else47 ; CHECK-NEXT: testl $131072, %eax # imm = 0x20000 -; CHECK-NEXT: jne .LBB1_36 -; CHECK-NEXT: .LBB1_37: # %else50 +; CHECK-NEXT: jne .LBB1_50 +; CHECK-NEXT: .LBB1_20: # %else50 ; CHECK-NEXT: testl $262144, %eax # imm = 0x40000 -; CHECK-NEXT: jne .LBB1_38 -; CHECK-NEXT: .LBB1_39: # %else53 +; CHECK-NEXT: jne .LBB1_51 +; CHECK-NEXT: .LBB1_21: # %else53 ; CHECK-NEXT: testl $524288, %eax # imm = 0x80000 -; CHECK-NEXT: jne .LBB1_40 -; CHECK-NEXT: .LBB1_41: # %else56 +; CHECK-NEXT: jne .LBB1_52 +; CHECK-NEXT: .LBB1_22: # %else56 ; CHECK-NEXT: testl $1048576, %eax # imm = 0x100000 -; CHECK-NEXT: jne .LBB1_42 -; CHECK-NEXT: .LBB1_43: # %else59 +; CHECK-NEXT: jne .LBB1_53 +; CHECK-NEXT: .LBB1_23: # %else59 ; CHECK-NEXT: testl $2097152, %eax # imm = 0x200000 -; CHECK-NEXT: jne .LBB1_44 -; CHECK-NEXT: .LBB1_45: # %else62 +; CHECK-NEXT: jne .LBB1_54 +; CHECK-NEXT: .LBB1_24: # %else62 ; CHECK-NEXT: testl $4194304, %eax # imm = 0x400000 -; CHECK-NEXT: jne .LBB1_46 -; CHECK-NEXT: .LBB1_47: # %else65 +; CHECK-NEXT: jne .LBB1_55 +; CHECK-NEXT: .LBB1_25: # %else65 ; CHECK-NEXT: testl $8388608, %eax # imm = 0x800000 -; CHECK-NEXT: jne .LBB1_48 -; CHECK-NEXT: .LBB1_49: # %else68 +; CHECK-NEXT: jne .LBB1_56 +; CHECK-NEXT: .LBB1_26: # %else68 ; CHECK-NEXT: testl $16777216, %eax # imm = 0x1000000 -; CHECK-NEXT: jne .LBB1_50 -; CHECK-NEXT: .LBB1_51: # %else71 +; CHECK-NEXT: jne .LBB1_57 +; CHECK-NEXT: .LBB1_27: # %else71 ; CHECK-NEXT: testl $33554432, %eax # imm = 0x2000000 -; CHECK-NEXT: jne .LBB1_52 -; CHECK-NEXT: .LBB1_53: # %else74 +; CHECK-NEXT: jne .LBB1_58 +; CHECK-NEXT: .LBB1_28: # %else74 ; CHECK-NEXT: testl $67108864, %eax # imm = 0x4000000 -; CHECK-NEXT: jne .LBB1_54 -; CHECK-NEXT: .LBB1_55: # %else77 +; CHECK-NEXT: jne .LBB1_59 +; CHECK-NEXT: .LBB1_29: # %else77 ; CHECK-NEXT: testl $134217728, %eax # imm = 0x8000000 -; CHECK-NEXT: jne .LBB1_56 -; CHECK-NEXT: .LBB1_57: # %else80 +; CHECK-NEXT: jne .LBB1_60 +; CHECK-NEXT: .LBB1_30: # %else80 ; CHECK-NEXT: testl $268435456, %eax # imm = 0x10000000 -; CHECK-NEXT: jne .LBB1_58 -; CHECK-NEXT: .LBB1_59: # %else83 +; CHECK-NEXT: jne .LBB1_61 +; CHECK-NEXT: .LBB1_31: # %else83 ; CHECK-NEXT: testl $536870912, %eax # imm = 0x20000000 -; CHECK-NEXT: jne .LBB1_60 -; CHECK-NEXT: .LBB1_61: # %else86 -; CHECK-NEXT: testl $1073741824, %eax # imm = 0x40000000 ; CHECK-NEXT: jne .LBB1_62 -; CHECK-NEXT: .LBB1_63: # %else89 +; CHECK-NEXT: .LBB1_32: # %else86 +; CHECK-NEXT: testl $1073741824, %eax # imm = 0x40000000 +; CHECK-NEXT: jne .LBB1_63 +; CHECK-NEXT: .LBB1_33: # %else89 ; CHECK-NEXT: testl $-2147483648, %eax # imm = 0x80000000 ; CHECK-NEXT: jne .LBB1_64 -; CHECK-NEXT: .LBB1_65: # %else92 +; CHECK-NEXT: .LBB1_34: # %else92 ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB1_6: # %cond.load4 +; CHECK-NEXT: .LBB1_35: # %cond.load4 ; CHECK-NEXT: vpbroadcastw 4(%rdi), %xmm1 ; CHECK-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2],xmm0[3,4,5,6,7] ; CHECK-NEXT: vinserti32x4 $0, %xmm1, %zmm0, %zmm0 ; CHECK-NEXT: testb $8, %al -; CHECK-NEXT: je .LBB1_9 -; CHECK-NEXT: .LBB1_8: # %cond.load7 +; CHECK-NEXT: je .LBB1_6 +; CHECK-NEXT: .LBB1_36: # %cond.load7 ; CHECK-NEXT: vpbroadcastw 6(%rdi), %xmm1 ; CHECK-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0,1,2],xmm1[3],xmm0[4,5,6,7] ; CHECK-NEXT: vinserti32x4 $0, %xmm1, %zmm0, %zmm0 ; CHECK-NEXT: testb $16, %al -; CHECK-NEXT: je .LBB1_11 -; CHECK-NEXT: .LBB1_10: # %cond.load10 +; CHECK-NEXT: je .LBB1_7 +; CHECK-NEXT: .LBB1_37: # %cond.load10 ; CHECK-NEXT: vpbroadcastw 8(%rdi), %xmm1 ; CHECK-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0,1,2,3],xmm1[4],xmm0[5,6,7] ; CHECK-NEXT: vinserti32x4 $0, %xmm1, %zmm0, %zmm0 ; CHECK-NEXT: testb $32, %al -; CHECK-NEXT: je .LBB1_13 -; CHECK-NEXT: .LBB1_12: # %cond.load13 +; CHECK-NEXT: je .LBB1_8 +; CHECK-NEXT: .LBB1_38: # %cond.load13 ; CHECK-NEXT: vpbroadcastw 10(%rdi), %xmm1 ; CHECK-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0,1,2,3,4],xmm1[5],xmm0[6,7] ; CHECK-NEXT: vinserti32x4 $0, %xmm1, %zmm0, %zmm0 ; CHECK-NEXT: testb $64, %al -; CHECK-NEXT: je .LBB1_15 -; CHECK-NEXT: .LBB1_14: # %cond.load16 +; CHECK-NEXT: je .LBB1_9 +; CHECK-NEXT: .LBB1_39: # %cond.load16 ; CHECK-NEXT: vpbroadcastw 12(%rdi), %xmm1 ; CHECK-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0,1,2,3,4,5],xmm1[6],xmm0[7] ; CHECK-NEXT: vinserti32x4 $0, %xmm1, %zmm0, %zmm0 ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jns .LBB1_17 -; CHECK-NEXT: .LBB1_16: # %cond.load19 +; CHECK-NEXT: jns .LBB1_10 +; CHECK-NEXT: .LBB1_40: # %cond.load19 ; CHECK-NEXT: vpbroadcastw 14(%rdi), %xmm1 ; CHECK-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0,1,2,3,4,5,6],xmm1[7] ; CHECK-NEXT: vinserti32x4 $0, %xmm1, %zmm0, %zmm0 ; CHECK-NEXT: testl $256, %eax # imm = 0x100 -; CHECK-NEXT: je .LBB1_19 -; CHECK-NEXT: .LBB1_18: # %cond.load22 +; CHECK-NEXT: je .LBB1_11 +; CHECK-NEXT: .LBB1_41: # %cond.load22 ; CHECK-NEXT: vpbroadcastw 16(%rdi), %ymm1 ; CHECK-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0],ymm0[1,2,3,4,5,6,7],ymm1[8],ymm0[9,10,11,12,13,14,15] ; CHECK-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm1[0,1,2,3],zmm0[4,5,6,7] ; CHECK-NEXT: testl $512, %eax # imm = 0x200 -; CHECK-NEXT: je .LBB1_21 -; CHECK-NEXT: .LBB1_20: # %cond.load25 +; CHECK-NEXT: je .LBB1_12 +; CHECK-NEXT: .LBB1_42: # %cond.load25 ; CHECK-NEXT: vpbroadcastw 18(%rdi), %ymm1 ; CHECK-NEXT: vpblendw {{.*#+}} ymm1 = ymm0[0],ymm1[1],ymm0[2,3,4,5,6,7,8],ymm1[9],ymm0[10,11,12,13,14,15] ; CHECK-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm1[0,1,2,3],zmm0[4,5,6,7] ; CHECK-NEXT: testl $1024, %eax # imm = 0x400 -; CHECK-NEXT: je .LBB1_23 -; CHECK-NEXT: .LBB1_22: # %cond.load28 +; CHECK-NEXT: je .LBB1_13 +; CHECK-NEXT: .LBB1_43: # %cond.load28 ; CHECK-NEXT: vpbroadcastw 20(%rdi), %ymm1 ; CHECK-NEXT: vpblendw {{.*#+}} ymm1 = ymm0[0,1],ymm1[2],ymm0[3,4,5,6,7,8,9],ymm1[10],ymm0[11,12,13,14,15] ; CHECK-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm1[0,1,2,3],zmm0[4,5,6,7] ; CHECK-NEXT: testl $2048, %eax # imm = 0x800 -; CHECK-NEXT: je .LBB1_25 -; CHECK-NEXT: .LBB1_24: # %cond.load31 +; CHECK-NEXT: je .LBB1_14 +; CHECK-NEXT: .LBB1_44: # %cond.load31 ; CHECK-NEXT: vpbroadcastw 22(%rdi), %ymm1 ; CHECK-NEXT: vpblendw {{.*#+}} ymm1 = ymm0[0,1,2],ymm1[3],ymm0[4,5,6,7,8,9,10],ymm1[11],ymm0[12,13,14,15] ; CHECK-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm1[0,1,2,3],zmm0[4,5,6,7] ; CHECK-NEXT: testl $4096, %eax # imm = 0x1000 -; CHECK-NEXT: je .LBB1_27 -; CHECK-NEXT: .LBB1_26: # %cond.load34 +; CHECK-NEXT: je .LBB1_15 +; CHECK-NEXT: .LBB1_45: # %cond.load34 ; CHECK-NEXT: vpbroadcastw 24(%rdi), %ymm1 ; CHECK-NEXT: vpblendw {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4],ymm0[5,6,7,8,9,10,11],ymm1[12],ymm0[13,14,15] ; CHECK-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm1[0,1,2,3],zmm0[4,5,6,7] ; CHECK-NEXT: testl $8192, %eax # imm = 0x2000 -; CHECK-NEXT: je .LBB1_29 -; CHECK-NEXT: .LBB1_28: # %cond.load37 +; CHECK-NEXT: je .LBB1_16 +; CHECK-NEXT: .LBB1_46: # %cond.load37 ; CHECK-NEXT: vpbroadcastw 26(%rdi), %ymm1 ; CHECK-NEXT: vpblendw {{.*#+}} ymm1 = ymm0[0,1,2,3,4],ymm1[5],ymm0[6,7,8,9,10,11,12],ymm1[13],ymm0[14,15] ; CHECK-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm1[0,1,2,3],zmm0[4,5,6,7] ; CHECK-NEXT: testl $16384, %eax # imm = 0x4000 -; CHECK-NEXT: je .LBB1_31 -; CHECK-NEXT: .LBB1_30: # %cond.load40 +; CHECK-NEXT: je .LBB1_17 +; CHECK-NEXT: .LBB1_47: # %cond.load40 ; CHECK-NEXT: vpbroadcastw 28(%rdi), %ymm1 ; CHECK-NEXT: vpblendw {{.*#+}} ymm1 = ymm0[0,1,2,3,4,5],ymm1[6],ymm0[7,8,9,10,11,12,13],ymm1[14],ymm0[15] ; CHECK-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm1[0,1,2,3],zmm0[4,5,6,7] ; CHECK-NEXT: testw %ax, %ax -; CHECK-NEXT: jns .LBB1_33 -; CHECK-NEXT: .LBB1_32: # %cond.load43 +; CHECK-NEXT: jns .LBB1_18 +; CHECK-NEXT: .LBB1_48: # %cond.load43 ; CHECK-NEXT: vpbroadcastw 30(%rdi), %ymm1 ; CHECK-NEXT: vpblendw {{.*#+}} ymm1 = ymm0[0,1,2,3,4,5,6],ymm1[7],ymm0[8,9,10,11,12,13,14],ymm1[15] ; CHECK-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; CHECK-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm1[0,1,2,3],zmm0[4,5,6,7] ; CHECK-NEXT: testl $65536, %eax # imm = 0x10000 -; CHECK-NEXT: je .LBB1_35 -; CHECK-NEXT: .LBB1_34: # %cond.load46 +; CHECK-NEXT: je .LBB1_19 +; CHECK-NEXT: .LBB1_49: # %cond.load46 ; CHECK-NEXT: vpinsrw $0, 32(%rdi), %xmm0, %xmm1 ; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm2 ; CHECK-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4,5,6,7] ; CHECK-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm2[4,5,6,7] ; CHECK-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0 ; CHECK-NEXT: testl $131072, %eax # imm = 0x20000 -; CHECK-NEXT: je .LBB1_37 -; CHECK-NEXT: .LBB1_36: # %cond.load49 +; CHECK-NEXT: je .LBB1_20 +; CHECK-NEXT: .LBB1_50: # %cond.load49 ; CHECK-NEXT: vpbroadcastw 34(%rdi), %xmm1 ; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm2 ; CHECK-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0],xmm1[1],xmm2[2,3,4,5,6,7] ; CHECK-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm2[4,5,6,7] ; CHECK-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0 ; CHECK-NEXT: testl $262144, %eax # imm = 0x40000 -; CHECK-NEXT: je .LBB1_39 -; CHECK-NEXT: .LBB1_38: # %cond.load52 +; CHECK-NEXT: je .LBB1_21 +; CHECK-NEXT: .LBB1_51: # %cond.load52 ; CHECK-NEXT: vpbroadcastw 36(%rdi), %xmm1 ; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm2 ; CHECK-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1],xmm1[2],xmm2[3,4,5,6,7] ; CHECK-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm2[4,5,6,7] ; CHECK-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0 ; CHECK-NEXT: testl $524288, %eax # imm = 0x80000 -; CHECK-NEXT: je .LBB1_41 -; CHECK-NEXT: .LBB1_40: # %cond.load55 +; CHECK-NEXT: je .LBB1_22 +; CHECK-NEXT: .LBB1_52: # %cond.load55 ; CHECK-NEXT: vpbroadcastw 38(%rdi), %xmm1 ; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm2 ; CHECK-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1,2],xmm1[3],xmm2[4,5,6,7] ; CHECK-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm2[4,5,6,7] ; CHECK-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0 ; CHECK-NEXT: testl $1048576, %eax # imm = 0x100000 -; CHECK-NEXT: je .LBB1_43 -; CHECK-NEXT: .LBB1_42: # %cond.load58 +; CHECK-NEXT: je .LBB1_23 +; CHECK-NEXT: .LBB1_53: # %cond.load58 ; CHECK-NEXT: vpbroadcastw 40(%rdi), %xmm1 ; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm2 ; CHECK-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1,2,3],xmm1[4],xmm2[5,6,7] ; CHECK-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm2[4,5,6,7] ; CHECK-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0 ; CHECK-NEXT: testl $2097152, %eax # imm = 0x200000 -; CHECK-NEXT: je .LBB1_45 -; CHECK-NEXT: .LBB1_44: # %cond.load61 +; CHECK-NEXT: je .LBB1_24 +; CHECK-NEXT: .LBB1_54: # %cond.load61 ; CHECK-NEXT: vpbroadcastw 42(%rdi), %xmm1 ; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm2 ; CHECK-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1,2,3,4],xmm1[5],xmm2[6,7] ; CHECK-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm2[4,5,6,7] ; CHECK-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0 ; CHECK-NEXT: testl $4194304, %eax # imm = 0x400000 -; CHECK-NEXT: je .LBB1_47 -; CHECK-NEXT: .LBB1_46: # %cond.load64 +; CHECK-NEXT: je .LBB1_25 +; CHECK-NEXT: .LBB1_55: # %cond.load64 ; CHECK-NEXT: vpbroadcastw 44(%rdi), %xmm1 ; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm2 ; CHECK-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1,2,3,4,5],xmm1[6],xmm2[7] ; CHECK-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm2[4,5,6,7] ; CHECK-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0 ; CHECK-NEXT: testl $8388608, %eax # imm = 0x800000 -; CHECK-NEXT: je .LBB1_49 -; CHECK-NEXT: .LBB1_48: # %cond.load67 +; CHECK-NEXT: je .LBB1_26 +; CHECK-NEXT: .LBB1_56: # %cond.load67 ; CHECK-NEXT: vpbroadcastw 46(%rdi), %xmm1 ; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm2 ; CHECK-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1,2,3,4,5,6],xmm1[7] ; CHECK-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm2[4,5,6,7] ; CHECK-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0 ; CHECK-NEXT: testl $16777216, %eax # imm = 0x1000000 -; CHECK-NEXT: je .LBB1_51 -; CHECK-NEXT: .LBB1_50: # %cond.load70 +; CHECK-NEXT: je .LBB1_27 +; CHECK-NEXT: .LBB1_57: # %cond.load70 ; CHECK-NEXT: vpbroadcastw 48(%rdi), %ymm1 ; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm2 ; CHECK-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0],ymm2[1,2,3,4,5,6,7],ymm1[8],ymm2[9,10,11,12,13,14,15] ; CHECK-NEXT: vpblendd {{.*#+}} ymm1 = ymm2[0,1,2,3],ymm1[4,5,6,7] ; CHECK-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0 ; CHECK-NEXT: testl $33554432, %eax # imm = 0x2000000 -; CHECK-NEXT: je .LBB1_53 -; CHECK-NEXT: .LBB1_52: # %cond.load73 +; CHECK-NEXT: je .LBB1_28 +; CHECK-NEXT: .LBB1_58: # %cond.load73 ; CHECK-NEXT: vpbroadcastw 50(%rdi), %ymm1 ; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm2 ; CHECK-NEXT: vpblendw {{.*#+}} ymm1 = ymm2[0],ymm1[1],ymm2[2,3,4,5,6,7,8],ymm1[9],ymm2[10,11,12,13,14,15] ; CHECK-NEXT: vpblendd {{.*#+}} ymm1 = ymm2[0,1,2,3],ymm1[4,5,6,7] ; CHECK-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0 ; CHECK-NEXT: testl $67108864, %eax # imm = 0x4000000 -; CHECK-NEXT: je .LBB1_55 -; CHECK-NEXT: .LBB1_54: # %cond.load76 +; CHECK-NEXT: je .LBB1_29 +; CHECK-NEXT: .LBB1_59: # %cond.load76 ; CHECK-NEXT: vpbroadcastw 52(%rdi), %ymm1 ; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm2 ; CHECK-NEXT: vpblendw {{.*#+}} ymm1 = ymm2[0,1],ymm1[2],ymm2[3,4,5,6,7,8,9],ymm1[10],ymm2[11,12,13,14,15] ; CHECK-NEXT: vpblendd {{.*#+}} ymm1 = ymm2[0,1,2,3],ymm1[4,5,6,7] ; CHECK-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0 ; CHECK-NEXT: testl $134217728, %eax # imm = 0x8000000 -; CHECK-NEXT: je .LBB1_57 -; CHECK-NEXT: .LBB1_56: # %cond.load79 +; CHECK-NEXT: je .LBB1_30 +; CHECK-NEXT: .LBB1_60: # %cond.load79 ; CHECK-NEXT: vpbroadcastw 54(%rdi), %ymm1 ; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm2 ; CHECK-NEXT: vpblendw {{.*#+}} ymm1 = ymm2[0,1,2],ymm1[3],ymm2[4,5,6,7,8,9,10],ymm1[11],ymm2[12,13,14,15] ; CHECK-NEXT: vpblendd {{.*#+}} ymm1 = ymm2[0,1,2,3],ymm1[4,5,6,7] ; CHECK-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0 ; CHECK-NEXT: testl $268435456, %eax # imm = 0x10000000 -; CHECK-NEXT: je .LBB1_59 -; CHECK-NEXT: .LBB1_58: # %cond.load82 +; CHECK-NEXT: je .LBB1_31 +; CHECK-NEXT: .LBB1_61: # %cond.load82 ; CHECK-NEXT: vpbroadcastw 56(%rdi), %ymm1 ; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm2 ; CHECK-NEXT: vpblendw {{.*#+}} ymm1 = ymm2[0,1,2,3],ymm1[4],ymm2[5,6,7,8,9,10,11],ymm1[12],ymm2[13,14,15] ; CHECK-NEXT: vpblendd {{.*#+}} ymm1 = ymm2[0,1,2,3],ymm1[4,5,6,7] ; CHECK-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0 ; CHECK-NEXT: testl $536870912, %eax # imm = 0x20000000 -; CHECK-NEXT: je .LBB1_61 -; CHECK-NEXT: .LBB1_60: # %cond.load85 +; CHECK-NEXT: je .LBB1_32 +; CHECK-NEXT: .LBB1_62: # %cond.load85 ; CHECK-NEXT: vpbroadcastw 58(%rdi), %ymm1 ; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm2 ; CHECK-NEXT: vpblendw {{.*#+}} ymm1 = ymm2[0,1,2,3,4],ymm1[5],ymm2[6,7,8,9,10,11,12],ymm1[13],ymm2[14,15] ; CHECK-NEXT: vpblendd {{.*#+}} ymm1 = ymm2[0,1,2,3],ymm1[4,5,6,7] ; CHECK-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0 ; CHECK-NEXT: testl $1073741824, %eax # imm = 0x40000000 -; CHECK-NEXT: je .LBB1_63 -; CHECK-NEXT: .LBB1_62: # %cond.load88 +; CHECK-NEXT: je .LBB1_33 +; CHECK-NEXT: .LBB1_63: # %cond.load88 ; CHECK-NEXT: vpbroadcastw 60(%rdi), %ymm1 ; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm2 ; CHECK-NEXT: vpblendw {{.*#+}} ymm1 = ymm2[0,1,2,3,4,5],ymm1[6],ymm2[7,8,9,10,11,12,13],ymm1[14],ymm2[15] ; CHECK-NEXT: vpblendd {{.*#+}} ymm1 = ymm2[0,1,2,3],ymm1[4,5,6,7] ; CHECK-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0 ; CHECK-NEXT: testl $-2147483648, %eax # imm = 0x80000000 -; CHECK-NEXT: je .LBB1_65 +; CHECK-NEXT: je .LBB1_34 ; CHECK-NEXT: .LBB1_64: # %cond.load91 ; CHECK-NEXT: vpbroadcastw 62(%rdi), %ymm1 ; CHECK-NEXT: vextracti64x4 $1, %zmm0, %ymm2 diff --git a/llvm/test/CodeGen/X86/sibcall.ll b/llvm/test/CodeGen/X86/sibcall.ll index d1137cac7d365..dd7274957e36b 100644 --- a/llvm/test/CodeGen/X86/sibcall.ll +++ b/llvm/test/CodeGen/X86/sibcall.ll @@ -297,11 +297,11 @@ define dso_local i32 @t12(i32 %x, i32 %y, ptr byval(%struct.t) align 4 %z) nounw ; X86: # %bb.0: # %entry ; X86-NEXT: subl $20, %esp ; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp) -; X86-NEXT: je .LBB12_1 -; X86-NEXT: # %bb.2: # %bb +; X86-NEXT: je .LBB12_2 +; X86-NEXT: # %bb.1: # %bb ; X86-NEXT: addl $20, %esp ; X86-NEXT: jmp foo6 # TAILCALL -; X86-NEXT: .LBB12_1: # %bb2 +; X86-NEXT: .LBB12_2: # %bb2 ; X86-NEXT: xorl %eax, %eax ; X86-NEXT: addl $20, %esp ; X86-NEXT: retl diff --git a/llvm/test/CodeGen/X86/smul-with-overflow.ll b/llvm/test/CodeGen/X86/smul-with-overflow.ll index df167338268c4..0ce288437deaf 100644 --- a/llvm/test/CodeGen/X86/smul-with-overflow.ll +++ b/llvm/test/CodeGen/X86/smul-with-overflow.ll @@ -11,14 +11,14 @@ define i1 @test1(i32 %v1, i32 %v2) nounwind { ; X86-NEXT: subl $12, %esp ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: imull {{[0-9]+}}(%esp), %eax -; X86-NEXT: jno .LBB0_1 -; X86-NEXT: # %bb.2: # %overflow +; X86-NEXT: jno .LBB0_2 +; X86-NEXT: # %bb.1: # %overflow ; X86-NEXT: movl $no, (%esp) ; X86-NEXT: calll printf@PLT ; X86-NEXT: xorl %eax, %eax ; X86-NEXT: addl $12, %esp ; X86-NEXT: retl -; X86-NEXT: .LBB0_1: # %normal +; X86-NEXT: .LBB0_2: # %normal ; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; X86-NEXT: movl $ok, (%esp) ; X86-NEXT: calll printf@PLT @@ -31,15 +31,15 @@ define i1 @test1(i32 %v1, i32 %v2) nounwind { ; X64-NEXT: pushq %rax ; X64-NEXT: movl %edi, %eax ; X64-NEXT: imull %esi, %eax -; X64-NEXT: jno .LBB0_1 -; X64-NEXT: # %bb.2: # %overflow +; X64-NEXT: jno .LBB0_2 +; X64-NEXT: # %bb.1: # %overflow ; X64-NEXT: movl $no, %edi ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: callq printf@PLT ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: popq %rcx ; X64-NEXT: retq -; X64-NEXT: .LBB0_1: # %normal +; X64-NEXT: .LBB0_2: # %normal ; X64-NEXT: movl $ok, %edi ; X64-NEXT: movl %eax, %esi ; X64-NEXT: xorl %eax, %eax diff --git a/llvm/test/CodeGen/X86/speculative-load-hardening-indirect.ll b/llvm/test/CodeGen/X86/speculative-load-hardening-indirect.ll index 2092fc9cd6e00..27b8e9255568d 100644 --- a/llvm/test/CodeGen/X86/speculative-load-hardening-indirect.ll +++ b/llvm/test/CodeGen/X86/speculative-load-hardening-indirect.ll @@ -267,25 +267,25 @@ define dso_local i32 @test_indirectbr(ptr %ptr) nounwind { ; X64-NEXT: movl $2, %eax ; X64-NEXT: orq %rcx, %rsp ; X64-NEXT: retq -; X64-NEXT: .LBB4_3: # Block address taken +; X64-NEXT: .LBB4_2: # Block address taken ; X64-NEXT: # %bb2 -; X64-NEXT: cmpq $.LBB4_3, %rdx +; X64-NEXT: cmpq $.LBB4_2, %rdx ; X64-NEXT: cmovneq %rax, %rcx ; X64-NEXT: shlq $47, %rcx ; X64-NEXT: movl $13, %eax ; X64-NEXT: orq %rcx, %rsp ; X64-NEXT: retq -; X64-NEXT: .LBB4_4: # Block address taken +; X64-NEXT: .LBB4_3: # Block address taken ; X64-NEXT: # %bb3 -; X64-NEXT: cmpq $.LBB4_4, %rdx +; X64-NEXT: cmpq $.LBB4_3, %rdx ; X64-NEXT: cmovneq %rax, %rcx ; X64-NEXT: shlq $47, %rcx ; X64-NEXT: movl $42, %eax ; X64-NEXT: orq %rcx, %rsp ; X64-NEXT: retq -; X64-NEXT: .LBB4_2: # Block address taken +; X64-NEXT: .LBB4_4: # Block address taken ; X64-NEXT: # %bb1 -; X64-NEXT: cmpq $.LBB4_2, %rdx +; X64-NEXT: cmpq $.LBB4_4, %rdx ; X64-NEXT: cmovneq %rax, %rcx ; X64-NEXT: shlq $47, %rcx ; X64-NEXT: movl $7, %eax @@ -309,27 +309,27 @@ define dso_local i32 @test_indirectbr(ptr %ptr) nounwind { ; X64-PIC-NEXT: movl $2, %eax ; X64-PIC-NEXT: orq %rcx, %rsp ; X64-PIC-NEXT: retq -; X64-PIC-NEXT: .LBB4_3: # Block address taken +; X64-PIC-NEXT: .LBB4_2: # Block address taken ; X64-PIC-NEXT: # %bb2 -; X64-PIC-NEXT: leaq .LBB4_3(%rip), %rsi +; X64-PIC-NEXT: leaq .LBB4_2(%rip), %rsi ; X64-PIC-NEXT: cmpq %rsi, %rdx ; X64-PIC-NEXT: cmovneq %rax, %rcx ; X64-PIC-NEXT: shlq $47, %rcx ; X64-PIC-NEXT: movl $13, %eax ; X64-PIC-NEXT: orq %rcx, %rsp ; X64-PIC-NEXT: retq -; X64-PIC-NEXT: .LBB4_4: # Block address taken +; X64-PIC-NEXT: .LBB4_3: # Block address taken ; X64-PIC-NEXT: # %bb3 -; X64-PIC-NEXT: leaq .LBB4_4(%rip), %rsi +; X64-PIC-NEXT: leaq .LBB4_3(%rip), %rsi ; X64-PIC-NEXT: cmpq %rsi, %rdx ; X64-PIC-NEXT: cmovneq %rax, %rcx ; X64-PIC-NEXT: shlq $47, %rcx ; X64-PIC-NEXT: movl $42, %eax ; X64-PIC-NEXT: orq %rcx, %rsp ; X64-PIC-NEXT: retq -; X64-PIC-NEXT: .LBB4_2: # Block address taken +; X64-PIC-NEXT: .LBB4_4: # Block address taken ; X64-PIC-NEXT: # %bb1 -; X64-PIC-NEXT: leaq .LBB4_2(%rip), %rsi +; X64-PIC-NEXT: leaq .LBB4_4(%rip), %rsi ; X64-PIC-NEXT: cmpq %rsi, %rdx ; X64-PIC-NEXT: cmovneq %rax, %rcx ; X64-PIC-NEXT: shlq $47, %rcx @@ -375,24 +375,24 @@ define dso_local i32 @test_indirectbr_global(i32 %idx) nounwind { ; X64-NEXT: orq %rcx, %rsp ; X64-NEXT: retq ; X64-NEXT: .Ltmp1: # Block address taken -; X64-NEXT: .LBB5_3: # %bb2 -; X64-NEXT: cmpq $.LBB5_3, %rdx +; X64-NEXT: .LBB5_2: # %bb2 +; X64-NEXT: cmpq $.LBB5_2, %rdx ; X64-NEXT: cmovneq %rax, %rcx ; X64-NEXT: shlq $47, %rcx ; X64-NEXT: movl $13, %eax ; X64-NEXT: orq %rcx, %rsp ; X64-NEXT: retq ; X64-NEXT: .Ltmp2: # Block address taken -; X64-NEXT: .LBB5_4: # %bb3 -; X64-NEXT: cmpq $.LBB5_4, %rdx +; X64-NEXT: .LBB5_3: # %bb3 +; X64-NEXT: cmpq $.LBB5_3, %rdx ; X64-NEXT: cmovneq %rax, %rcx ; X64-NEXT: shlq $47, %rcx ; X64-NEXT: movl $42, %eax ; X64-NEXT: orq %rcx, %rsp ; X64-NEXT: retq ; X64-NEXT: .Ltmp3: # Block address taken -; X64-NEXT: .LBB5_2: # %bb1 -; X64-NEXT: cmpq $.LBB5_2, %rdx +; X64-NEXT: .LBB5_4: # %bb1 +; X64-NEXT: cmpq $.LBB5_4, %rdx ; X64-NEXT: cmovneq %rax, %rcx ; X64-NEXT: shlq $47, %rcx ; X64-NEXT: movl $7, %eax @@ -419,8 +419,8 @@ define dso_local i32 @test_indirectbr_global(i32 %idx) nounwind { ; X64-PIC-NEXT: orq %rcx, %rsp ; X64-PIC-NEXT: retq ; X64-PIC-NEXT: .Ltmp1: # Block address taken -; X64-PIC-NEXT: .LBB5_3: # %bb2 -; X64-PIC-NEXT: leaq .LBB5_3(%rip), %rsi +; X64-PIC-NEXT: .LBB5_2: # %bb2 +; X64-PIC-NEXT: leaq .LBB5_2(%rip), %rsi ; X64-PIC-NEXT: cmpq %rsi, %rdx ; X64-PIC-NEXT: cmovneq %rax, %rcx ; X64-PIC-NEXT: shlq $47, %rcx @@ -428,8 +428,8 @@ define dso_local i32 @test_indirectbr_global(i32 %idx) nounwind { ; X64-PIC-NEXT: orq %rcx, %rsp ; X64-PIC-NEXT: retq ; X64-PIC-NEXT: .Ltmp2: # Block address taken -; X64-PIC-NEXT: .LBB5_4: # %bb3 -; X64-PIC-NEXT: leaq .LBB5_4(%rip), %rsi +; X64-PIC-NEXT: .LBB5_3: # %bb3 +; X64-PIC-NEXT: leaq .LBB5_3(%rip), %rsi ; X64-PIC-NEXT: cmpq %rsi, %rdx ; X64-PIC-NEXT: cmovneq %rax, %rcx ; X64-PIC-NEXT: shlq $47, %rcx @@ -437,8 +437,8 @@ define dso_local i32 @test_indirectbr_global(i32 %idx) nounwind { ; X64-PIC-NEXT: orq %rcx, %rsp ; X64-PIC-NEXT: retq ; X64-PIC-NEXT: .Ltmp3: # Block address taken -; X64-PIC-NEXT: .LBB5_2: # %bb1 -; X64-PIC-NEXT: leaq .LBB5_2(%rip), %rsi +; X64-PIC-NEXT: .LBB5_4: # %bb1 +; X64-PIC-NEXT: leaq .LBB5_4(%rip), %rsi ; X64-PIC-NEXT: cmpq %rsi, %rdx ; X64-PIC-NEXT: cmovneq %rax, %rcx ; X64-PIC-NEXT: shlq $47, %rcx @@ -455,34 +455,34 @@ define dso_local i32 @test_indirectbr_global(i32 %idx) nounwind { ; X64-RETPOLINE-NEXT: movq global_blockaddrs(,%rdx,8), %rdx ; X64-RETPOLINE-NEXT: orq %rcx, %rdx ; X64-RETPOLINE-NEXT: cmpq $2, %rdx -; X64-RETPOLINE-NEXT: je .LBB6_4 +; X64-RETPOLINE-NEXT: je .LBB6_5 ; X64-RETPOLINE-NEXT: # %bb.1: # %entry ; X64-RETPOLINE-NEXT: cmoveq %rax, %rcx ; X64-RETPOLINE-NEXT: cmpq $3, %rdx -; X64-RETPOLINE-NEXT: je .LBB6_5 +; X64-RETPOLINE-NEXT: je .LBB6_4 ; X64-RETPOLINE-NEXT: # %bb.2: # %entry ; X64-RETPOLINE-NEXT: cmoveq %rax, %rcx ; X64-RETPOLINE-NEXT: cmpq $4, %rdx -; X64-RETPOLINE-NEXT: jne .LBB6_3 -; X64-RETPOLINE-NEXT: # %bb.6: # %bb3 +; X64-RETPOLINE-NEXT: jne .LBB6_6 +; X64-RETPOLINE-NEXT: # %bb.3: # %bb3 ; X64-RETPOLINE-NEXT: cmovneq %rax, %rcx ; X64-RETPOLINE-NEXT: shlq $47, %rcx ; X64-RETPOLINE-NEXT: movl $42, %eax ; X64-RETPOLINE-NEXT: orq %rcx, %rsp ; X64-RETPOLINE-NEXT: retq -; X64-RETPOLINE-NEXT: .LBB6_5: # %bb2 +; X64-RETPOLINE-NEXT: .LBB6_4: # %bb2 ; X64-RETPOLINE-NEXT: cmovneq %rax, %rcx ; X64-RETPOLINE-NEXT: shlq $47, %rcx ; X64-RETPOLINE-NEXT: movl $13, %eax ; X64-RETPOLINE-NEXT: orq %rcx, %rsp ; X64-RETPOLINE-NEXT: retq -; X64-RETPOLINE-NEXT: .LBB6_4: # %bb1 +; X64-RETPOLINE-NEXT: .LBB6_5: # %bb1 ; X64-RETPOLINE-NEXT: cmovneq %rax, %rcx ; X64-RETPOLINE-NEXT: shlq $47, %rcx ; X64-RETPOLINE-NEXT: movl $7, %eax ; X64-RETPOLINE-NEXT: orq %rcx, %rsp ; X64-RETPOLINE-NEXT: retq -; X64-RETPOLINE-NEXT: .LBB6_3: # %bb0 +; X64-RETPOLINE-NEXT: .LBB6_6: # %bb0 ; X64-RETPOLINE-NEXT: cmoveq %rax, %rcx ; X64-RETPOLINE-NEXT: shlq $47, %rcx ; X64-RETPOLINE-NEXT: movl $2, %eax @@ -519,46 +519,46 @@ define dso_local i32 @test_switch_jumptable(i32 %idx) nounwind { ; X64-NEXT: movq $-1, %rax ; X64-NEXT: sarq $63, %rcx ; X64-NEXT: cmpl $3, %edi -; X64-NEXT: ja .LBB6_2 +; X64-NEXT: ja .LBB6_6 ; X64-NEXT: # %bb.1: # %entry ; X64-NEXT: cmovaq %rax, %rcx ; X64-NEXT: movl %edi, %edx ; X64-NEXT: movq .LJTI6_0(,%rdx,8), %rdx ; X64-NEXT: orq %rcx, %rdx ; X64-NEXT: jmpq *%rdx -; X64-NEXT: .LBB6_3: # Block address taken +; X64-NEXT: .LBB6_2: # Block address taken ; X64-NEXT: # %bb1 -; X64-NEXT: cmpq $.LBB6_3, %rdx +; X64-NEXT: cmpq $.LBB6_2, %rdx ; X64-NEXT: cmovneq %rax, %rcx ; X64-NEXT: shlq $47, %rcx ; X64-NEXT: movl $7, %eax ; X64-NEXT: orq %rcx, %rsp ; X64-NEXT: retq -; X64-NEXT: .LBB6_5: # Block address taken +; X64-NEXT: .LBB6_3: # Block address taken ; X64-NEXT: # %bb3 -; X64-NEXT: cmpq $.LBB6_5, %rdx +; X64-NEXT: cmpq $.LBB6_3, %rdx ; X64-NEXT: cmovneq %rax, %rcx ; X64-NEXT: shlq $47, %rcx ; X64-NEXT: movl $42, %eax ; X64-NEXT: orq %rcx, %rsp ; X64-NEXT: retq -; X64-NEXT: .LBB6_6: # Block address taken +; X64-NEXT: .LBB6_4: # Block address taken ; X64-NEXT: # %bb5 -; X64-NEXT: cmpq $.LBB6_6, %rdx +; X64-NEXT: cmpq $.LBB6_4, %rdx ; X64-NEXT: cmovneq %rax, %rcx ; X64-NEXT: shlq $47, %rcx ; X64-NEXT: movl $11, %eax ; X64-NEXT: orq %rcx, %rsp ; X64-NEXT: retq -; X64-NEXT: .LBB6_4: # Block address taken +; X64-NEXT: .LBB6_5: # Block address taken ; X64-NEXT: # %bb2 -; X64-NEXT: cmpq $.LBB6_4, %rdx +; X64-NEXT: cmpq $.LBB6_5, %rdx ; X64-NEXT: cmovneq %rax, %rcx ; X64-NEXT: shlq $47, %rcx ; X64-NEXT: movl $13, %eax ; X64-NEXT: orq %rcx, %rsp ; X64-NEXT: retq -; X64-NEXT: .LBB6_2: # %bb0 +; X64-NEXT: .LBB6_6: # %bb0 ; X64-NEXT: cmovbeq %rax, %rcx ; X64-NEXT: shlq $47, %rcx ; X64-NEXT: movl $2, %eax @@ -571,7 +571,7 @@ define dso_local i32 @test_switch_jumptable(i32 %idx) nounwind { ; X64-PIC-NEXT: movq $-1, %rax ; X64-PIC-NEXT: sarq $63, %rcx ; X64-PIC-NEXT: cmpl $3, %edi -; X64-PIC-NEXT: ja .LBB6_2 +; X64-PIC-NEXT: ja .LBB6_6 ; X64-PIC-NEXT: # %bb.1: # %entry ; X64-PIC-NEXT: cmovaq %rax, %rcx ; X64-PIC-NEXT: movl %edi, %edx @@ -580,43 +580,43 @@ define dso_local i32 @test_switch_jumptable(i32 %idx) nounwind { ; X64-PIC-NEXT: addq %rsi, %rdx ; X64-PIC-NEXT: orq %rcx, %rdx ; X64-PIC-NEXT: jmpq *%rdx -; X64-PIC-NEXT: .LBB6_3: # Block address taken +; X64-PIC-NEXT: .LBB6_2: # Block address taken ; X64-PIC-NEXT: # %bb1 -; X64-PIC-NEXT: leaq .LBB6_3(%rip), %rsi +; X64-PIC-NEXT: leaq .LBB6_2(%rip), %rsi ; X64-PIC-NEXT: cmpq %rsi, %rdx ; X64-PIC-NEXT: cmovneq %rax, %rcx ; X64-PIC-NEXT: shlq $47, %rcx ; X64-PIC-NEXT: movl $7, %eax ; X64-PIC-NEXT: orq %rcx, %rsp ; X64-PIC-NEXT: retq -; X64-PIC-NEXT: .LBB6_5: # Block address taken +; X64-PIC-NEXT: .LBB6_3: # Block address taken ; X64-PIC-NEXT: # %bb3 -; X64-PIC-NEXT: leaq .LBB6_5(%rip), %rsi +; X64-PIC-NEXT: leaq .LBB6_3(%rip), %rsi ; X64-PIC-NEXT: cmpq %rsi, %rdx ; X64-PIC-NEXT: cmovneq %rax, %rcx ; X64-PIC-NEXT: shlq $47, %rcx ; X64-PIC-NEXT: movl $42, %eax ; X64-PIC-NEXT: orq %rcx, %rsp ; X64-PIC-NEXT: retq -; X64-PIC-NEXT: .LBB6_6: # Block address taken +; X64-PIC-NEXT: .LBB6_4: # Block address taken ; X64-PIC-NEXT: # %bb5 -; X64-PIC-NEXT: leaq .LBB6_6(%rip), %rsi +; X64-PIC-NEXT: leaq .LBB6_4(%rip), %rsi ; X64-PIC-NEXT: cmpq %rsi, %rdx ; X64-PIC-NEXT: cmovneq %rax, %rcx ; X64-PIC-NEXT: shlq $47, %rcx ; X64-PIC-NEXT: movl $11, %eax ; X64-PIC-NEXT: orq %rcx, %rsp ; X64-PIC-NEXT: retq -; X64-PIC-NEXT: .LBB6_4: # Block address taken +; X64-PIC-NEXT: .LBB6_5: # Block address taken ; X64-PIC-NEXT: # %bb2 -; X64-PIC-NEXT: leaq .LBB6_4(%rip), %rsi +; X64-PIC-NEXT: leaq .LBB6_5(%rip), %rsi ; X64-PIC-NEXT: cmpq %rsi, %rdx ; X64-PIC-NEXT: cmovneq %rax, %rcx ; X64-PIC-NEXT: shlq $47, %rcx ; X64-PIC-NEXT: movl $13, %eax ; X64-PIC-NEXT: orq %rcx, %rsp ; X64-PIC-NEXT: retq -; X64-PIC-NEXT: .LBB6_2: # %bb0 +; X64-PIC-NEXT: .LBB6_6: # %bb0 ; X64-PIC-NEXT: cmovbeq %rax, %rcx ; X64-PIC-NEXT: shlq $47, %rcx ; X64-PIC-NEXT: movl $2, %eax @@ -633,11 +633,11 @@ define dso_local i32 @test_switch_jumptable(i32 %idx) nounwind { ; X64-RETPOLINE-NEXT: # %bb.1: # %entry ; X64-RETPOLINE-NEXT: cmovgq %rax, %rcx ; X64-RETPOLINE-NEXT: testl %edi, %edi -; X64-RETPOLINE-NEXT: je .LBB7_7 +; X64-RETPOLINE-NEXT: je .LBB7_8 ; X64-RETPOLINE-NEXT: # %bb.2: # %entry ; X64-RETPOLINE-NEXT: cmoveq %rax, %rcx ; X64-RETPOLINE-NEXT: cmpl $1, %edi -; X64-RETPOLINE-NEXT: jne .LBB7_6 +; X64-RETPOLINE-NEXT: jne .LBB7_7 ; X64-RETPOLINE-NEXT: # %bb.3: # %bb2 ; X64-RETPOLINE-NEXT: cmovneq %rax, %rcx ; X64-RETPOLINE-NEXT: shlq $47, %rcx @@ -647,30 +647,30 @@ define dso_local i32 @test_switch_jumptable(i32 %idx) nounwind { ; X64-RETPOLINE-NEXT: .LBB7_4: # %entry ; X64-RETPOLINE-NEXT: cmovleq %rax, %rcx ; X64-RETPOLINE-NEXT: cmpl $2, %edi -; X64-RETPOLINE-NEXT: je .LBB7_8 +; X64-RETPOLINE-NEXT: je .LBB7_9 ; X64-RETPOLINE-NEXT: # %bb.5: # %entry ; X64-RETPOLINE-NEXT: cmoveq %rax, %rcx ; X64-RETPOLINE-NEXT: cmpl $3, %edi -; X64-RETPOLINE-NEXT: jne .LBB7_6 -; X64-RETPOLINE-NEXT: # %bb.9: # %bb5 +; X64-RETPOLINE-NEXT: jne .LBB7_7 +; X64-RETPOLINE-NEXT: # %bb.6: # %bb5 ; X64-RETPOLINE-NEXT: cmovneq %rax, %rcx ; X64-RETPOLINE-NEXT: shlq $47, %rcx ; X64-RETPOLINE-NEXT: movl $11, %eax ; X64-RETPOLINE-NEXT: orq %rcx, %rsp ; X64-RETPOLINE-NEXT: retq -; X64-RETPOLINE-NEXT: .LBB7_6: +; X64-RETPOLINE-NEXT: .LBB7_7: ; X64-RETPOLINE-NEXT: cmoveq %rax, %rcx ; X64-RETPOLINE-NEXT: shlq $47, %rcx ; X64-RETPOLINE-NEXT: movl $2, %eax ; X64-RETPOLINE-NEXT: orq %rcx, %rsp ; X64-RETPOLINE-NEXT: retq -; X64-RETPOLINE-NEXT: .LBB7_7: # %bb1 +; X64-RETPOLINE-NEXT: .LBB7_8: # %bb1 ; X64-RETPOLINE-NEXT: cmovneq %rax, %rcx ; X64-RETPOLINE-NEXT: shlq $47, %rcx ; X64-RETPOLINE-NEXT: movl $7, %eax ; X64-RETPOLINE-NEXT: orq %rcx, %rsp ; X64-RETPOLINE-NEXT: retq -; X64-RETPOLINE-NEXT: .LBB7_8: # %bb3 +; X64-RETPOLINE-NEXT: .LBB7_9: # %bb3 ; X64-RETPOLINE-NEXT: cmovneq %rax, %rcx ; X64-RETPOLINE-NEXT: shlq $47, %rcx ; X64-RETPOLINE-NEXT: movl $42, %eax @@ -816,35 +816,35 @@ define dso_local i32 @test_switch_jumptable_fallthrough(i32 %idx, ptr %a.ptr, pt ; X64-RETPOLINE-NEXT: sarq $63, %r9 ; X64-RETPOLINE-NEXT: xorl %eax, %eax ; X64-RETPOLINE-NEXT: cmpl $1, %edi -; X64-RETPOLINE-NEXT: jg .LBB8_5 +; X64-RETPOLINE-NEXT: jg .LBB8_4 ; X64-RETPOLINE-NEXT: # %bb.1: # %entry ; X64-RETPOLINE-NEXT: cmovgq %r10, %r9 ; X64-RETPOLINE-NEXT: testl %edi, %edi -; X64-RETPOLINE-NEXT: je .LBB8_2 -; X64-RETPOLINE-NEXT: # %bb.3: # %entry +; X64-RETPOLINE-NEXT: je .LBB8_8 +; X64-RETPOLINE-NEXT: # %bb.2: # %entry ; X64-RETPOLINE-NEXT: cmoveq %r10, %r9 ; X64-RETPOLINE-NEXT: cmpl $1, %edi -; X64-RETPOLINE-NEXT: jne .LBB8_8 -; X64-RETPOLINE-NEXT: # %bb.4: +; X64-RETPOLINE-NEXT: jne .LBB8_7 +; X64-RETPOLINE-NEXT: # %bb.3: ; X64-RETPOLINE-NEXT: cmovneq %r10, %r9 ; X64-RETPOLINE-NEXT: jmp .LBB8_10 -; X64-RETPOLINE-NEXT: .LBB8_5: # %entry +; X64-RETPOLINE-NEXT: .LBB8_4: # %entry ; X64-RETPOLINE-NEXT: cmovleq %r10, %r9 ; X64-RETPOLINE-NEXT: cmpl $2, %edi -; X64-RETPOLINE-NEXT: je .LBB8_6 -; X64-RETPOLINE-NEXT: # %bb.7: # %entry +; X64-RETPOLINE-NEXT: je .LBB8_11 +; X64-RETPOLINE-NEXT: # %bb.5: # %entry ; X64-RETPOLINE-NEXT: cmoveq %r10, %r9 ; X64-RETPOLINE-NEXT: cmpl $3, %edi -; X64-RETPOLINE-NEXT: jne .LBB8_8 -; X64-RETPOLINE-NEXT: # %bb.13: +; X64-RETPOLINE-NEXT: jne .LBB8_7 +; X64-RETPOLINE-NEXT: # %bb.6: ; X64-RETPOLINE-NEXT: cmovneq %r10, %r9 -; X64-RETPOLINE-NEXT: jmp .LBB8_12 -; X64-RETPOLINE-NEXT: .LBB8_8: +; X64-RETPOLINE-NEXT: jmp .LBB8_13 +; X64-RETPOLINE-NEXT: .LBB8_7: ; X64-RETPOLINE-NEXT: cmoveq %r10, %r9 ; X64-RETPOLINE-NEXT: movl (%rsi), %edi ; X64-RETPOLINE-NEXT: orl %r9d, %edi ; X64-RETPOLINE-NEXT: jmp .LBB8_9 -; X64-RETPOLINE-NEXT: .LBB8_2: +; X64-RETPOLINE-NEXT: .LBB8_8: ; X64-RETPOLINE-NEXT: cmovneq %r10, %r9 ; X64-RETPOLINE-NEXT: .LBB8_9: # %bb1 ; X64-RETPOLINE-NEXT: addl (%rdx), %edi @@ -853,13 +853,13 @@ define dso_local i32 @test_switch_jumptable_fallthrough(i32 %idx, ptr %a.ptr, pt ; X64-RETPOLINE-NEXT: .LBB8_10: # %bb2 ; X64-RETPOLINE-NEXT: addl (%rcx), %eax ; X64-RETPOLINE-NEXT: orl %r9d, %eax -; X64-RETPOLINE-NEXT: jmp .LBB8_11 -; X64-RETPOLINE-NEXT: .LBB8_6: +; X64-RETPOLINE-NEXT: jmp .LBB8_12 +; X64-RETPOLINE-NEXT: .LBB8_11: ; X64-RETPOLINE-NEXT: cmovneq %r10, %r9 -; X64-RETPOLINE-NEXT: .LBB8_11: # %bb3 +; X64-RETPOLINE-NEXT: .LBB8_12: # %bb3 ; X64-RETPOLINE-NEXT: addl (%r8), %eax ; X64-RETPOLINE-NEXT: orl %r9d, %eax -; X64-RETPOLINE-NEXT: .LBB8_12: # %bb4 +; X64-RETPOLINE-NEXT: .LBB8_13: # %bb4 ; X64-RETPOLINE-NEXT: shlq $47, %r9 ; X64-RETPOLINE-NEXT: orq %r9, %rsp ; X64-RETPOLINE-NEXT: retq diff --git a/llvm/test/CodeGen/X86/speculative-load-hardening.ll b/llvm/test/CodeGen/X86/speculative-load-hardening.ll index 5fd1f77e166d4..30bc5cca7e1f4 100644 --- a/llvm/test/CodeGen/X86/speculative-load-hardening.ll +++ b/llvm/test/CodeGen/X86/speculative-load-hardening.ll @@ -45,14 +45,14 @@ define void @test_basic_conditions(i32 %a, i32 %b, i32 %c, ptr %ptr1, ptr %ptr2, ; X64-NEXT: movq $-1, %rbx ; X64-NEXT: sarq $63, %rax ; X64-NEXT: testl %edi, %edi -; X64-NEXT: jne .LBB1_1 -; X64-NEXT: # %bb.2: # %then1 +; X64-NEXT: jne .LBB1_2 +; X64-NEXT: # %bb.1: # %then1 ; X64-NEXT: cmovneq %rbx, %rax ; X64-NEXT: testl %esi, %esi ; X64-NEXT: je .LBB1_4 -; X64-NEXT: .LBB1_1: +; X64-NEXT: .LBB1_2: ; X64-NEXT: cmoveq %rbx, %rax -; X64-NEXT: .LBB1_8: # %exit +; X64-NEXT: .LBB1_3: # %exit ; X64-NEXT: shlq $47, %rax ; X64-NEXT: orq %rax, %rsp ; X64-NEXT: popq %rbx @@ -101,7 +101,7 @@ define void @test_basic_conditions(i32 %a, i32 %b, i32 %c, ptr %ptr1, ptr %ptr2, ; X64-NEXT: movslq (%r14), %rcx ; X64-NEXT: orq %rax, %rcx ; X64-NEXT: movl $0, (%r8,%rcx,4) -; X64-NEXT: jmp .LBB1_8 +; X64-NEXT: jmp .LBB1_3 ; ; X64-LFENCE-LABEL: test_basic_conditions: ; X64-LFENCE: # %bb.0: # %entry @@ -122,14 +122,14 @@ define void @test_basic_conditions(i32 %a, i32 %b, i32 %c, ptr %ptr1, ptr %ptr2, ; X64-LFENCE-NEXT: # %bb.2: # %then2 ; X64-LFENCE-NEXT: lfence ; X64-LFENCE-NEXT: testl %edx, %edx -; X64-LFENCE-NEXT: je .LBB1_3 -; X64-LFENCE-NEXT: # %bb.4: # %else3 +; X64-LFENCE-NEXT: je .LBB1_4 +; X64-LFENCE-NEXT: # %bb.3: # %else3 ; X64-LFENCE-NEXT: lfence ; X64-LFENCE-NEXT: movslq (%r9), %rax ; X64-LFENCE-NEXT: leaq (%r8,%rax,4), %rbx ; X64-LFENCE-NEXT: movl %eax, (%r8,%rax,4) ; X64-LFENCE-NEXT: jmp .LBB1_5 -; X64-LFENCE-NEXT: .LBB1_3: # %then3 +; X64-LFENCE-NEXT: .LBB1_4: # %then3 ; X64-LFENCE-NEXT: lfence ; X64-LFENCE-NEXT: movl (%rcx), %eax ; X64-LFENCE-NEXT: addl (%r8), %eax @@ -210,7 +210,7 @@ define void @test_basic_loop(i32 %a, i32 %b, ptr %ptr1, ptr %ptr2) nounwind spec ; X64-NEXT: je .LBB2_2 ; X64-NEXT: # %bb.1: ; X64-NEXT: cmoveq %r15, %rax -; X64-NEXT: jmp .LBB2_5 +; X64-NEXT: jmp .LBB2_6 ; X64-NEXT: .LBB2_2: # %l.header.preheader ; X64-NEXT: movq %rcx, %rbx ; X64-NEXT: movq %rdx, %r14 @@ -236,13 +236,13 @@ define void @test_basic_loop(i32 %a, i32 %b, ptr %ptr1, ptr %ptr2) nounwind spec ; X64-NEXT: cmovneq %r15, %rax ; X64-NEXT: incl %r12d ; X64-NEXT: cmpl %ebp, %r12d -; X64-NEXT: jge .LBB2_4 -; X64-NEXT: # %bb.6: # in Loop: Header=BB2_3 Depth=1 +; X64-NEXT: jge .LBB2_5 +; X64-NEXT: # %bb.4: # in Loop: Header=BB2_3 Depth=1 ; X64-NEXT: cmovgeq %r15, %rax ; X64-NEXT: jmp .LBB2_3 -; X64-NEXT: .LBB2_4: +; X64-NEXT: .LBB2_5: ; X64-NEXT: cmovlq %r15, %rax -; X64-NEXT: .LBB2_5: # %exit +; X64-NEXT: .LBB2_6: # %exit ; X64-NEXT: shlq $47, %rax ; X64-NEXT: orq %rax, %rsp ; X64-NEXT: popq %rbx @@ -320,7 +320,7 @@ define void @test_basic_nested_loop(i32 %a, i32 %b, i32 %c, ptr %ptr1, ptr %ptr2 ; X64-NEXT: je .LBB3_2 ; X64-NEXT: # %bb.1: ; X64-NEXT: cmoveq %r12, %rax -; X64-NEXT: jmp .LBB3_10 +; X64-NEXT: jmp .LBB3_11 ; X64-NEXT: .LBB3_2: # %l1.header.preheader ; X64-NEXT: movq %r8, %rbx ; X64-NEXT: movq %rcx, %r14 @@ -330,13 +330,13 @@ define void @test_basic_nested_loop(i32 %a, i32 %b, i32 %c, ptr %ptr1, ptr %ptr2 ; X64-NEXT: xorl %r13d, %r13d ; X64-NEXT: movl %esi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill ; X64-NEXT: testl %r15d, %r15d -; X64-NEXT: jle .LBB3_4 +; X64-NEXT: jle .LBB3_7 ; X64-NEXT: .p2align 4 -; X64-NEXT: .LBB3_5: # %l2.header.preheader +; X64-NEXT: .LBB3_3: # %l2.header.preheader ; X64-NEXT: cmovleq %r12, %rax ; X64-NEXT: xorl %r15d, %r15d ; X64-NEXT: .p2align 4 -; X64-NEXT: .LBB3_6: # %l2.header +; X64-NEXT: .LBB3_4: # %l2.header ; X64-NEXT: # =>This Inner Loop Header: Depth=1 ; X64-NEXT: movslq (%r14), %rcx ; X64-NEXT: orq %rax, %rcx @@ -354,17 +354,17 @@ define void @test_basic_nested_loop(i32 %a, i32 %b, i32 %c, ptr %ptr1, ptr %ptr2 ; X64-NEXT: cmovneq %r12, %rax ; X64-NEXT: incl %r15d ; X64-NEXT: cmpl %ebp, %r15d -; X64-NEXT: jge .LBB3_7 -; X64-NEXT: # %bb.11: # in Loop: Header=BB3_6 Depth=1 +; X64-NEXT: jge .LBB3_6 +; X64-NEXT: # %bb.5: # in Loop: Header=BB3_4 Depth=1 ; X64-NEXT: cmovgeq %r12, %rax -; X64-NEXT: jmp .LBB3_6 +; X64-NEXT: jmp .LBB3_4 ; X64-NEXT: .p2align 4 -; X64-NEXT: .LBB3_7: +; X64-NEXT: .LBB3_6: ; X64-NEXT: cmovlq %r12, %rax ; X64-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %r15d # 4-byte Reload ; X64-NEXT: jmp .LBB3_8 ; X64-NEXT: .p2align 4 -; X64-NEXT: .LBB3_4: +; X64-NEXT: .LBB3_7: ; X64-NEXT: cmovgq %r12, %rax ; X64-NEXT: .LBB3_8: # %l1.latch ; X64-NEXT: movslq (%r14), %rcx @@ -383,15 +383,15 @@ define void @test_basic_nested_loop(i32 %a, i32 %b, i32 %c, ptr %ptr1, ptr %ptr2 ; X64-NEXT: cmovneq %r12, %rax ; X64-NEXT: incl %r13d ; X64-NEXT: cmpl %r15d, %r13d -; X64-NEXT: jge .LBB3_9 -; X64-NEXT: # %bb.12: +; X64-NEXT: jge .LBB3_10 +; X64-NEXT: # %bb.9: ; X64-NEXT: cmovgeq %r12, %rax ; X64-NEXT: testl %r15d, %r15d -; X64-NEXT: jg .LBB3_5 -; X64-NEXT: jmp .LBB3_4 -; X64-NEXT: .LBB3_9: +; X64-NEXT: jg .LBB3_3 +; X64-NEXT: jmp .LBB3_7 +; X64-NEXT: .LBB3_10: ; X64-NEXT: cmovlq %r12, %rax -; X64-NEXT: .LBB3_10: # %exit +; X64-NEXT: .LBB3_11: # %exit ; X64-NEXT: shlq $47, %rax ; X64-NEXT: orq %rax, %rsp ; X64-NEXT: addq $8, %rsp @@ -413,8 +413,8 @@ define void @test_basic_nested_loop(i32 %a, i32 %b, i32 %c, ptr %ptr1, ptr %ptr2 ; X64-LFENCE-NEXT: pushq %rbx ; X64-LFENCE-NEXT: pushq %rax ; X64-LFENCE-NEXT: testl %edi, %edi -; X64-LFENCE-NEXT: je .LBB3_1 -; X64-LFENCE-NEXT: .LBB3_6: # %exit +; X64-LFENCE-NEXT: je .LBB3_2 +; X64-LFENCE-NEXT: .LBB3_1: # %exit ; X64-LFENCE-NEXT: lfence ; X64-LFENCE-NEXT: addq $8, %rsp ; X64-LFENCE-NEXT: popq %rbx @@ -424,37 +424,37 @@ define void @test_basic_nested_loop(i32 %a, i32 %b, i32 %c, ptr %ptr1, ptr %ptr2 ; X64-LFENCE-NEXT: popq %r15 ; X64-LFENCE-NEXT: popq %rbp ; X64-LFENCE-NEXT: retq -; X64-LFENCE-NEXT: .LBB3_1: # %l1.header.preheader +; X64-LFENCE-NEXT: .LBB3_2: # %l1.header.preheader ; X64-LFENCE-NEXT: movq %r8, %rbx ; X64-LFENCE-NEXT: movq %rcx, %r14 ; X64-LFENCE-NEXT: movl %edx, %ebp ; X64-LFENCE-NEXT: movl %esi, %r15d ; X64-LFENCE-NEXT: lfence ; X64-LFENCE-NEXT: xorl %r12d, %r12d -; X64-LFENCE-NEXT: jmp .LBB3_2 +; X64-LFENCE-NEXT: jmp .LBB3_4 ; X64-LFENCE-NEXT: .p2align 4 -; X64-LFENCE-NEXT: .LBB3_5: # %l1.latch -; X64-LFENCE-NEXT: # in Loop: Header=BB3_2 Depth=1 +; X64-LFENCE-NEXT: .LBB3_3: # %l1.latch +; X64-LFENCE-NEXT: # in Loop: Header=BB3_4 Depth=1 ; X64-LFENCE-NEXT: lfence ; X64-LFENCE-NEXT: movslq (%r14), %rax ; X64-LFENCE-NEXT: movl (%rbx,%rax,4), %edi ; X64-LFENCE-NEXT: callq sink@PLT ; X64-LFENCE-NEXT: incl %r12d ; X64-LFENCE-NEXT: cmpl %r15d, %r12d -; X64-LFENCE-NEXT: jge .LBB3_6 -; X64-LFENCE-NEXT: .LBB3_2: # %l1.header +; X64-LFENCE-NEXT: jge .LBB3_1 +; X64-LFENCE-NEXT: .LBB3_4: # %l1.header ; X64-LFENCE-NEXT: # =>This Loop Header: Depth=1 -; X64-LFENCE-NEXT: # Child Loop BB3_4 Depth 2 +; X64-LFENCE-NEXT: # Child Loop BB3_6 Depth 2 ; X64-LFENCE-NEXT: lfence ; X64-LFENCE-NEXT: testl %r15d, %r15d -; X64-LFENCE-NEXT: jle .LBB3_5 -; X64-LFENCE-NEXT: # %bb.3: # %l2.header.preheader -; X64-LFENCE-NEXT: # in Loop: Header=BB3_2 Depth=1 +; X64-LFENCE-NEXT: jle .LBB3_3 +; X64-LFENCE-NEXT: # %bb.5: # %l2.header.preheader +; X64-LFENCE-NEXT: # in Loop: Header=BB3_4 Depth=1 ; X64-LFENCE-NEXT: lfence ; X64-LFENCE-NEXT: xorl %r13d, %r13d ; X64-LFENCE-NEXT: .p2align 4 -; X64-LFENCE-NEXT: .LBB3_4: # %l2.header -; X64-LFENCE-NEXT: # Parent Loop BB3_2 Depth=1 +; X64-LFENCE-NEXT: .LBB3_6: # %l2.header +; X64-LFENCE-NEXT: # Parent Loop BB3_4 Depth=1 ; X64-LFENCE-NEXT: # => This Inner Loop Header: Depth=2 ; X64-LFENCE-NEXT: lfence ; X64-LFENCE-NEXT: movslq (%r14), %rax @@ -462,8 +462,8 @@ define void @test_basic_nested_loop(i32 %a, i32 %b, i32 %c, ptr %ptr1, ptr %ptr2 ; X64-LFENCE-NEXT: callq sink@PLT ; X64-LFENCE-NEXT: incl %r13d ; X64-LFENCE-NEXT: cmpl %ebp, %r13d -; X64-LFENCE-NEXT: jl .LBB3_4 -; X64-LFENCE-NEXT: jmp .LBB3_5 +; X64-LFENCE-NEXT: jl .LBB3_6 +; X64-LFENCE-NEXT: jmp .LBB3_3 entry: %a.cmp = icmp eq i32 %a, 0 br i1 %a.cmp, label %l1.header, label %exit @@ -523,8 +523,8 @@ define void @test_basic_eh(i32 %a, ptr %ptr1, ptr %ptr2) speculative_load_harden ; X64-NEXT: movq $-1, %rbx ; X64-NEXT: sarq $63, %rax ; X64-NEXT: cmpl $41, %edi -; X64-NEXT: jg .LBB4_1 -; X64-NEXT: # %bb.2: # %thrower +; X64-NEXT: jg .LBB4_2 +; X64-NEXT: # %bb.1: # %thrower ; X64-NEXT: movq %rdx, %r14 ; X64-NEXT: cmovgq %rbx, %rax ; X64-NEXT: movslq %edi, %rcx @@ -542,7 +542,7 @@ define void @test_basic_eh(i32 %a, ptr %ptr1, ptr %ptr2) speculative_load_harden ; X64-NEXT: cmpq $.Lslh_ret_addr4, %rdx ; X64-NEXT: cmovneq %rbx, %rcx ; X64-NEXT: movl %ebp, (%rax) -; X64-NEXT: .Ltmp0: +; X64-NEXT: .Ltmp0: # EH_LABEL ; X64-NEXT: shlq $47, %rcx ; X64-NEXT: movq %rax, %rdi ; X64-NEXT: xorl %esi, %esi @@ -555,9 +555,9 @@ define void @test_basic_eh(i32 %a, ptr %ptr1, ptr %ptr2) speculative_load_harden ; X64-NEXT: sarq $63, %rax ; X64-NEXT: cmpq $.Lslh_ret_addr5, %rcx ; X64-NEXT: cmovneq %rbx, %rax -; X64-NEXT: .Ltmp1: +; X64-NEXT: .Ltmp1: # EH_LABEL ; X64-NEXT: jmp .LBB4_3 -; X64-NEXT: .LBB4_1: +; X64-NEXT: .LBB4_2: ; X64-NEXT: cmovleq %rbx, %rax ; X64-NEXT: .LBB4_3: # %exit ; X64-NEXT: shlq $47, %rax @@ -575,7 +575,7 @@ define void @test_basic_eh(i32 %a, ptr %ptr1, ptr %ptr2) speculative_load_harden ; X64-NEXT: retq ; X64-NEXT: .LBB4_4: # %lpad ; X64-NEXT: .cfi_def_cfa_offset 48 -; X64-NEXT: .Ltmp2: +; X64-NEXT: .Ltmp2: # EH_LABEL ; X64-NEXT: movq %rsp, %rcx ; X64-NEXT: sarq $63, %rcx ; X64-NEXT: movl (%rax), %eax @@ -616,12 +616,12 @@ define void @test_basic_eh(i32 %a, ptr %ptr1, ptr %ptr2) speculative_load_harden ; X64-LFENCE-NEXT: movl $4, %edi ; X64-LFENCE-NEXT: callq __cxa_allocate_exception@PLT ; X64-LFENCE-NEXT: movl %ebp, (%rax) -; X64-LFENCE-NEXT: .Ltmp0: +; X64-LFENCE-NEXT: .Ltmp0: # EH_LABEL ; X64-LFENCE-NEXT: movq %rax, %rdi ; X64-LFENCE-NEXT: xorl %esi, %esi ; X64-LFENCE-NEXT: xorl %edx, %edx ; X64-LFENCE-NEXT: callq __cxa_throw@PLT -; X64-LFENCE-NEXT: .Ltmp1: +; X64-LFENCE-NEXT: .Ltmp1: # EH_LABEL ; X64-LFENCE-NEXT: .LBB4_2: # %exit ; X64-LFENCE-NEXT: lfence ; X64-LFENCE-NEXT: popq %rbx @@ -633,7 +633,7 @@ define void @test_basic_eh(i32 %a, ptr %ptr1, ptr %ptr2) speculative_load_harden ; X64-LFENCE-NEXT: retq ; X64-LFENCE-NEXT: .LBB4_3: # %lpad ; X64-LFENCE-NEXT: .cfi_def_cfa_offset 32 -; X64-LFENCE-NEXT: .Ltmp2: +; X64-LFENCE-NEXT: .Ltmp2: # EH_LABEL ; X64-LFENCE-NEXT: movl (%rax), %eax ; X64-LFENCE-NEXT: addl (%r14), %eax ; X64-LFENCE-NEXT: cltq diff --git a/llvm/test/CodeGen/X86/split-reg-with-hint.ll b/llvm/test/CodeGen/X86/split-reg-with-hint.ll index 689f83ff0adc4..96d106b84336b 100644 --- a/llvm/test/CodeGen/X86/split-reg-with-hint.ll +++ b/llvm/test/CodeGen/X86/split-reg-with-hint.ll @@ -10,11 +10,11 @@ define ptr @foo(ptr %ptr, i64 %p2, i64 %p3, i64 %p4, i64 %p5, i64 %p6) { ; CHECK-LABEL: foo: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: testq %rdi, %rdi -; CHECK-NEXT: je .LBB0_1 -; CHECK-NEXT: # %bb.2: # %if.end +; CHECK-NEXT: je .LBB0_2 +; CHECK-NEXT: # %bb.1: # %if.end ; CHECK-NEXT: incq %rdi ; CHECK-NEXT: jmp qux@PLT # TAILCALL -; CHECK-NEXT: .LBB0_1: # %if.then +; CHECK-NEXT: .LBB0_2: # %if.then ; CHECK-NEXT: pushq %r15 ; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: pushq %r14 diff --git a/llvm/test/CodeGen/X86/srem-seteq-optsize.ll b/llvm/test/CodeGen/X86/srem-seteq-optsize.ll index 2b980683cba75..2119e4b701e39 100644 --- a/llvm/test/CodeGen/X86/srem-seteq-optsize.ll +++ b/llvm/test/CodeGen/X86/srem-seteq-optsize.ll @@ -14,12 +14,12 @@ define i32 @test_minsize(i32 %X) optsize minsize nounwind readnone { ; X86-NEXT: cltd ; X86-NEXT: idivl %ecx ; X86-NEXT: testl %edx, %edx -; X86-NEXT: je .LBB0_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: je .LBB0_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: pushl $-10 ; X86-NEXT: popl %eax ; X86-NEXT: retl -; X86-NEXT: .LBB0_1: +; X86-NEXT: .LBB0_2: ; X86-NEXT: pushl $42 ; X86-NEXT: popl %eax ; X86-NEXT: retl diff --git a/llvm/test/CodeGen/X86/sse-load-ret.ll b/llvm/test/CodeGen/X86/sse-load-ret.ll index 0e9b24360e2f8..5e0af717339cf 100644 --- a/llvm/test/CodeGen/X86/sse-load-ret.ll +++ b/llvm/test/CodeGen/X86/sse-load-ret.ll @@ -31,11 +31,11 @@ define double @test3(i1 %B) { ; CHECK-NEXT: andl $-8, %esp ; CHECK-NEXT: subl $8, %esp ; CHECK-NEXT: testb $1, 8(%ebp) -; CHECK-NEXT: jne .LBB2_1 -; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: jne .LBB2_2 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: movsd {{.*#+}} xmm0 = [5.2301123123000002E+2,0.0E+0] ; CHECK-NEXT: jmp .LBB2_3 -; CHECK-NEXT: .LBB2_1: +; CHECK-NEXT: .LBB2_2: ; CHECK-NEXT: movsd {{.*#+}} xmm0 = [1.2341200000000001E+2,0.0E+0] ; CHECK-NEXT: .LBB2_3: ; CHECK-NEXT: movsd %xmm0, (%esp) diff --git a/llvm/test/CodeGen/X86/sse-scalar-fp-arith.ll b/llvm/test/CodeGen/X86/sse-scalar-fp-arith.ll index 325f735b09cd9..681fc3276c720 100644 --- a/llvm/test/CodeGen/X86/sse-scalar-fp-arith.ll +++ b/llvm/test/CodeGen/X86/sse-scalar-fp-arith.ll @@ -1266,11 +1266,11 @@ define <4 x float> @add_ss_mask(<4 x float> %a, <4 x float> %b, <4 x float> %c, ; X86-SSE-LABEL: add_ss_mask: ; X86-SSE: # %bb.0: ; X86-SSE-NEXT: testb $1, {{[0-9]+}}(%esp) -; X86-SSE-NEXT: jne .LBB70_1 -; X86-SSE-NEXT: # %bb.2: +; X86-SSE-NEXT: jne .LBB70_2 +; X86-SSE-NEXT: # %bb.1: ; X86-SSE-NEXT: movss {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3] ; X86-SSE-NEXT: retl -; X86-SSE-NEXT: .LBB70_1: +; X86-SSE-NEXT: .LBB70_2: ; X86-SSE-NEXT: addss %xmm0, %xmm1 ; X86-SSE-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] ; X86-SSE-NEXT: retl @@ -1296,11 +1296,11 @@ define <4 x float> @add_ss_mask(<4 x float> %a, <4 x float> %b, <4 x float> %c, ; X64-SSE-LABEL: add_ss_mask: ; X64-SSE: # %bb.0: ; X64-SSE-NEXT: testb $1, %dil -; X64-SSE-NEXT: jne .LBB70_1 -; X64-SSE-NEXT: # %bb.2: +; X64-SSE-NEXT: jne .LBB70_2 +; X64-SSE-NEXT: # %bb.1: ; X64-SSE-NEXT: movss {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3] ; X64-SSE-NEXT: retq -; X64-SSE-NEXT: .LBB70_1: +; X64-SSE-NEXT: .LBB70_2: ; X64-SSE-NEXT: addss %xmm0, %xmm1 ; X64-SSE-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] ; X64-SSE-NEXT: retq @@ -1336,11 +1336,11 @@ define <2 x double> @add_sd_mask(<2 x double> %a, <2 x double> %b, <2 x double> ; X86-SSE-LABEL: add_sd_mask: ; X86-SSE: # %bb.0: ; X86-SSE-NEXT: testb $1, {{[0-9]+}}(%esp) -; X86-SSE-NEXT: jne .LBB71_1 -; X86-SSE-NEXT: # %bb.2: +; X86-SSE-NEXT: jne .LBB71_2 +; X86-SSE-NEXT: # %bb.1: ; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1] ; X86-SSE-NEXT: retl -; X86-SSE-NEXT: .LBB71_1: +; X86-SSE-NEXT: .LBB71_2: ; X86-SSE-NEXT: addsd %xmm0, %xmm1 ; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] ; X86-SSE-NEXT: retl @@ -1366,11 +1366,11 @@ define <2 x double> @add_sd_mask(<2 x double> %a, <2 x double> %b, <2 x double> ; X64-SSE-LABEL: add_sd_mask: ; X64-SSE: # %bb.0: ; X64-SSE-NEXT: testb $1, %dil -; X64-SSE-NEXT: jne .LBB71_1 -; X64-SSE-NEXT: # %bb.2: +; X64-SSE-NEXT: jne .LBB71_2 +; X64-SSE-NEXT: # %bb.1: ; X64-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1] ; X64-SSE-NEXT: retq -; X64-SSE-NEXT: .LBB71_1: +; X64-SSE-NEXT: .LBB71_2: ; X64-SSE-NEXT: addsd %xmm0, %xmm1 ; X64-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] ; X64-SSE-NEXT: retq diff --git a/llvm/test/CodeGen/X86/sse1.ll b/llvm/test/CodeGen/X86/sse1.ll index 5005752b06de4..42860033d6f2c 100644 --- a/llvm/test/CodeGen/X86/sse1.ll +++ b/llvm/test/CodeGen/X86/sse1.ll @@ -46,37 +46,37 @@ define <4 x float> @vselect(ptr%p, <4 x i32> %q) { ; X86: # %bb.0: # %entry ; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp) ; X86-NEXT: xorps %xmm0, %xmm0 -; X86-NEXT: je .LBB1_1 -; X86-NEXT: # %bb.2: # %entry +; X86-NEXT: je .LBB1_4 +; X86-NEXT: # %bb.1: # %entry ; X86-NEXT: xorps %xmm1, %xmm1 ; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp) ; X86-NEXT: jne .LBB1_5 -; X86-NEXT: .LBB1_4: +; X86-NEXT: .LBB1_2: ; X86-NEXT: movss {{.*#+}} xmm2 = [3.0E+0,0.0E+0,0.0E+0,0.0E+0] ; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp) -; X86-NEXT: jne .LBB1_8 -; X86-NEXT: .LBB1_7: +; X86-NEXT: jne .LBB1_6 +; X86-NEXT: .LBB1_3: ; X86-NEXT: movss {{.*#+}} xmm3 = [4.0E+0,0.0E+0,0.0E+0,0.0E+0] ; X86-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] ; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp) -; X86-NEXT: je .LBB1_10 -; X86-NEXT: jmp .LBB1_11 -; X86-NEXT: .LBB1_1: +; X86-NEXT: je .LBB1_7 +; X86-NEXT: jmp .LBB1_8 +; X86-NEXT: .LBB1_4: ; X86-NEXT: movss {{.*#+}} xmm1 = [2.0E+0,0.0E+0,0.0E+0,0.0E+0] ; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp) -; X86-NEXT: je .LBB1_4 +; X86-NEXT: je .LBB1_2 ; X86-NEXT: .LBB1_5: # %entry ; X86-NEXT: xorps %xmm2, %xmm2 ; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp) -; X86-NEXT: je .LBB1_7 -; X86-NEXT: .LBB1_8: # %entry +; X86-NEXT: je .LBB1_3 +; X86-NEXT: .LBB1_6: # %entry ; X86-NEXT: xorps %xmm3, %xmm3 ; X86-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] ; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp) -; X86-NEXT: jne .LBB1_11 -; X86-NEXT: .LBB1_10: +; X86-NEXT: jne .LBB1_8 +; X86-NEXT: .LBB1_7: ; X86-NEXT: movss {{.*#+}} xmm0 = [1.0E+0,0.0E+0,0.0E+0,0.0E+0] -; X86-NEXT: .LBB1_11: # %entry +; X86-NEXT: .LBB1_8: # %entry ; X86-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; X86-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; X86-NEXT: retl @@ -85,37 +85,37 @@ define <4 x float> @vselect(ptr%p, <4 x i32> %q) { ; X64: # %bb.0: # %entry ; X64-NEXT: testl %edx, %edx ; X64-NEXT: xorps %xmm0, %xmm0 -; X64-NEXT: je .LBB1_1 -; X64-NEXT: # %bb.2: # %entry +; X64-NEXT: je .LBB1_4 +; X64-NEXT: # %bb.1: # %entry ; X64-NEXT: xorps %xmm1, %xmm1 ; X64-NEXT: testl %ecx, %ecx ; X64-NEXT: jne .LBB1_5 -; X64-NEXT: .LBB1_4: +; X64-NEXT: .LBB1_2: ; X64-NEXT: movss {{.*#+}} xmm2 = [3.0E+0,0.0E+0,0.0E+0,0.0E+0] ; X64-NEXT: testl %r8d, %r8d -; X64-NEXT: jne .LBB1_8 -; X64-NEXT: .LBB1_7: +; X64-NEXT: jne .LBB1_6 +; X64-NEXT: .LBB1_3: ; X64-NEXT: movss {{.*#+}} xmm3 = [4.0E+0,0.0E+0,0.0E+0,0.0E+0] ; X64-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] ; X64-NEXT: testl %esi, %esi -; X64-NEXT: je .LBB1_10 -; X64-NEXT: jmp .LBB1_11 -; X64-NEXT: .LBB1_1: +; X64-NEXT: je .LBB1_7 +; X64-NEXT: jmp .LBB1_8 +; X64-NEXT: .LBB1_4: ; X64-NEXT: movss {{.*#+}} xmm1 = [2.0E+0,0.0E+0,0.0E+0,0.0E+0] ; X64-NEXT: testl %ecx, %ecx -; X64-NEXT: je .LBB1_4 +; X64-NEXT: je .LBB1_2 ; X64-NEXT: .LBB1_5: # %entry ; X64-NEXT: xorps %xmm2, %xmm2 ; X64-NEXT: testl %r8d, %r8d -; X64-NEXT: je .LBB1_7 -; X64-NEXT: .LBB1_8: # %entry +; X64-NEXT: je .LBB1_3 +; X64-NEXT: .LBB1_6: # %entry ; X64-NEXT: xorps %xmm3, %xmm3 ; X64-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] ; X64-NEXT: testl %esi, %esi -; X64-NEXT: jne .LBB1_11 -; X64-NEXT: .LBB1_10: +; X64-NEXT: jne .LBB1_8 +; X64-NEXT: .LBB1_7: ; X64-NEXT: movss {{.*#+}} xmm0 = [1.0E+0,0.0E+0,0.0E+0,0.0E+0] -; X64-NEXT: .LBB1_11: # %entry +; X64-NEXT: .LBB1_8: # %entry ; X64-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; X64-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; X64-NEXT: retq diff --git a/llvm/test/CodeGen/X86/stack-clash-dynamic-alloca.ll b/llvm/test/CodeGen/X86/stack-clash-dynamic-alloca.ll index b7d1b593d1ab6..e259f31e9872b 100644 --- a/llvm/test/CodeGen/X86/stack-clash-dynamic-alloca.ll +++ b/llvm/test/CodeGen/X86/stack-clash-dynamic-alloca.ll @@ -16,13 +16,13 @@ define i32 @foo(i32 %n) local_unnamed_addr #0 { ; CHECK-X86-64-NEXT: andq $-16, %rcx ; CHECK-X86-64-NEXT: subq %rcx, %rax ; CHECK-X86-64-NEXT: cmpq %rsp, %rax -; CHECK-X86-64-NEXT: jge .LBB0_3 -; CHECK-X86-64-NEXT: .LBB0_2: # =>This Inner Loop Header: Depth=1 +; CHECK-X86-64-NEXT: jge .LBB0_2 +; CHECK-X86-64-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1 ; CHECK-X86-64-NEXT: xorq $0, (%rsp) ; CHECK-X86-64-NEXT: subq $4096, %rsp # imm = 0x1000 ; CHECK-X86-64-NEXT: cmpq %rsp, %rax -; CHECK-X86-64-NEXT: jl .LBB0_2 -; CHECK-X86-64-NEXT: .LBB0_3: +; CHECK-X86-64-NEXT: jl .LBB0_1 +; CHECK-X86-64-NEXT: .LBB0_2: ; CHECK-X86-64-NEXT: movq %rax, %rsp ; CHECK-X86-64-NEXT: movl $1, 4792(%rax) ; CHECK-X86-64-NEXT: movl (%rax), %eax @@ -45,13 +45,13 @@ define i32 @foo(i32 %n) local_unnamed_addr #0 { ; CHECK-X86-32-NEXT: andl $-16, %ecx ; CHECK-X86-32-NEXT: subl %ecx, %eax ; CHECK-X86-32-NEXT: cmpl %esp, %eax -; CHECK-X86-32-NEXT: jge .LBB0_3 -; CHECK-X86-32-NEXT: .LBB0_2: # =>This Inner Loop Header: Depth=1 +; CHECK-X86-32-NEXT: jge .LBB0_2 +; CHECK-X86-32-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1 ; CHECK-X86-32-NEXT: xorl $0, (%esp) ; CHECK-X86-32-NEXT: subl $4096, %esp # imm = 0x1000 ; CHECK-X86-32-NEXT: cmpl %esp, %eax -; CHECK-X86-32-NEXT: jl .LBB0_2 -; CHECK-X86-32-NEXT: .LBB0_3: +; CHECK-X86-32-NEXT: jl .LBB0_1 +; CHECK-X86-32-NEXT: .LBB0_2: ; CHECK-X86-32-NEXT: movl %eax, %esp ; CHECK-X86-32-NEXT: movl $1, 4792(%eax) ; CHECK-X86-32-NEXT: movl (%eax), %eax diff --git a/llvm/test/CodeGen/X86/stack-clash-small-alloc-medium-align.ll b/llvm/test/CodeGen/X86/stack-clash-small-alloc-medium-align.ll index ccf7e1d56da90..2f9571224f50a 100644 --- a/llvm/test/CodeGen/X86/stack-clash-small-alloc-medium-align.ll +++ b/llvm/test/CodeGen/X86/stack-clash-small-alloc-medium-align.ll @@ -103,13 +103,13 @@ define i32 @foo4(i64 %i) local_unnamed_addr #0 { ; CHECK-NEXT: andq $-16, %rcx ; CHECK-NEXT: subq %rcx, %rax ; CHECK-NEXT: cmpq %rsp, %rax -; CHECK-NEXT: jge .LBB3_3 -; CHECK-NEXT: .LBB3_2: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: jge .LBB3_2 +; CHECK-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: xorq $0, (%rsp) ; CHECK-NEXT: subq $4096, %rsp # imm = 0x1000 ; CHECK-NEXT: cmpq %rsp, %rax -; CHECK-NEXT: jl .LBB3_2 -; CHECK-NEXT: .LBB3_3: +; CHECK-NEXT: jl .LBB3_1 +; CHECK-NEXT: .LBB3_2: ; CHECK-NEXT: andq $-64, %rax ; CHECK-NEXT: movq %rax, %rsp ; CHECK-NEXT: movl (%rax), %eax diff --git a/llvm/test/CodeGen/X86/stack-coloring-wineh.ll b/llvm/test/CodeGen/X86/stack-coloring-wineh.ll index 74fe07e88aa33..df2d8d477b967 100644 --- a/llvm/test/CodeGen/X86/stack-coloring-wineh.ll +++ b/llvm/test/CodeGen/X86/stack-coloring-wineh.ll @@ -24,12 +24,12 @@ define void @pr66984(ptr %arg) personality ptr @__CxxFrameHandler3 { ; I686-NEXT: movl $1, -16(%ebp) ; I686-NEXT: calll _throw ; I686-NEXT: # %bb.1: # %bb14 -; I686-NEXT: LBB0_3: # Block address taken +; I686-NEXT: LBB0_2: # Block address taken ; I686-NEXT: # %bb17 ; I686-NEXT: addl $12, %ebp -; I686-NEXT: jmp LBB0_4 -; I686-NEXT: LBB0_4: # %exit -; I686-NEXT: $ehgcr_0_4: +; I686-NEXT: jmp LBB0_3 +; I686-NEXT: LBB0_3: # %exit +; I686-NEXT: $ehgcr_0_3: ; I686-NEXT: movl -24(%ebp), %eax ; I686-NEXT: movl %eax, %fs:0 ; I686-NEXT: addl $24, %esp @@ -38,20 +38,20 @@ define void @pr66984(ptr %arg) personality ptr @__CxxFrameHandler3 { ; I686-NEXT: popl %ebx ; I686-NEXT: popl %ebp ; I686-NEXT: retl -; I686-NEXT: .def "?catch$2@?0?pr66984@4HA"; +; I686-NEXT: .def "?catch$4@?0?pr66984@4HA"; ; I686-NEXT: .scl 3; ; I686-NEXT: .type 32; ; I686-NEXT: .endef ; I686-NEXT: .p2align 4 -; I686-NEXT: "?catch$2@?0?pr66984@4HA": -; I686-NEXT: LBB0_2: # %bb17 +; I686-NEXT: "?catch$4@?0?pr66984@4HA": +; I686-NEXT: LBB0_4: # %bb17 ; I686-NEXT: pushl %ebp ; I686-NEXT: addl $12, %ebp ; I686-NEXT: movl %esp, -28(%ebp) ; I686-NEXT: movl -36(%ebp), %ecx ; I686-NEXT: movl $2, -16(%ebp) ; I686-NEXT: calll _cleanup -; I686-NEXT: movl $LBB0_3, %eax +; I686-NEXT: movl $LBB0_2, %eax ; I686-NEXT: popl %ebp ; I686-NEXT: retl # CATCHRET ; I686-NEXT: .def "?dtor$5@?0?pr66984@4HA"; @@ -82,14 +82,14 @@ define void @pr66984(ptr %arg) personality ptr @__CxxFrameHandler3 { ; X86_64-NEXT: .seh_endprologue ; X86_64-NEXT: movq $-2, -16(%rbp) ; X86_64-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; X86_64-NEXT: .Ltmp0: +; X86_64-NEXT: .Ltmp0: # EH_LABEL ; X86_64-NEXT: callq throw ; X86_64-NEXT: nop -; X86_64-NEXT: .Ltmp1: +; X86_64-NEXT: .Ltmp1: # EH_LABEL ; X86_64-NEXT: # %bb.1: # %bb14 -; X86_64-NEXT: .LBB0_3: # Block address taken +; X86_64-NEXT: .LBB0_2: # Block address taken ; X86_64-NEXT: # %exit -; X86_64-NEXT: $ehgcr_0_3: +; X86_64-NEXT: $ehgcr_0_2: ; X86_64-NEXT: .seh_startepilogue ; X86_64-NEXT: addq $64, %rsp ; X86_64-NEXT: popq %rbp @@ -99,15 +99,15 @@ define void @pr66984(ptr %arg) personality ptr @__CxxFrameHandler3 { ; X86_64-NEXT: .long $cppxdata$pr66984@IMGREL ; X86_64-NEXT: .text ; X86_64-NEXT: .seh_endproc -; X86_64-NEXT: .def "?catch$2@?0?pr66984@4HA"; +; X86_64-NEXT: .def "?catch$3@?0?pr66984@4HA"; ; X86_64-NEXT: .scl 3; ; X86_64-NEXT: .type 32; ; X86_64-NEXT: .endef ; X86_64-NEXT: .p2align 4 -; X86_64-NEXT: "?catch$2@?0?pr66984@4HA": -; X86_64-NEXT: .seh_proc "?catch$2@?0?pr66984@4HA" +; X86_64-NEXT: "?catch$3@?0?pr66984@4HA": +; X86_64-NEXT: .seh_proc "?catch$3@?0?pr66984@4HA" ; X86_64-NEXT: .seh_handler __CxxFrameHandler3, @unwind, @except -; X86_64-NEXT: .LBB0_2: # %bb17 +; X86_64-NEXT: .LBB0_3: # %bb17 ; X86_64-NEXT: movq %rdx, {{[0-9]+}}(%rsp) ; X86_64-NEXT: pushq %rbp ; X86_64-NEXT: .seh_pushreg %rbp @@ -117,7 +117,7 @@ define void @pr66984(ptr %arg) personality ptr @__CxxFrameHandler3 { ; X86_64-NEXT: .seh_endprologue ; X86_64-NEXT: movq -8(%rbp), %rcx ; X86_64-NEXT: callq cleanup -; X86_64-NEXT: leaq .LBB0_3(%rip), %rax +; X86_64-NEXT: leaq .LBB0_2(%rip), %rax ; X86_64-NEXT: .seh_startepilogue ; X86_64-NEXT: addq $32, %rsp ; X86_64-NEXT: popq %rbp diff --git a/llvm/test/CodeGen/X86/stack-protector-msvc.ll b/llvm/test/CodeGen/X86/stack-protector-msvc.ll index 3109733e0b0b7..96dadbb410f72 100644 --- a/llvm/test/CodeGen/X86/stack-protector-msvc.ll +++ b/llvm/test/CodeGen/X86/stack-protector-msvc.ll @@ -90,13 +90,13 @@ define void @test(ptr %a) nounwind ssp { ; MSVC-X86-O0-NEXT: xorl %esp, %ecx ; MSVC-X86-O0-NEXT: movl ___security_cookie, %eax ; MSVC-X86-O0-NEXT: subl %ecx, %eax -; MSVC-X86-O0-NEXT: jne LBB0_3 -; MSVC-X86-O0-NEXT: jmp LBB0_2 -; MSVC-X86-O0-NEXT: LBB0_3: # %return +; MSVC-X86-O0-NEXT: jne LBB0_2 +; MSVC-X86-O0-NEXT: jmp LBB0_3 +; MSVC-X86-O0-NEXT: LBB0_2: # %return ; MSVC-X86-O0-NEXT: movl {{[0-9]+}}(%esp), %ecx ; MSVC-X86-O0-NEXT: xorl %esp, %ecx ; MSVC-X86-O0-NEXT: calll @__security_check_cookie@4 -; MSVC-X86-O0-NEXT: LBB0_2: # %return +; MSVC-X86-O0-NEXT: LBB0_3: # %return ; MSVC-X86-O0-NEXT: addl $20, %esp ; MSVC-X86-O0-NEXT: retl ; @@ -118,13 +118,13 @@ define void @test(ptr %a) nounwind ssp { ; MSVC-X64-O0-NEXT: xorq %rsp, %rcx ; MSVC-X64-O0-NEXT: movq __security_cookie(%rip), %rax ; MSVC-X64-O0-NEXT: subq %rcx, %rax -; MSVC-X64-O0-NEXT: jne .LBB0_3 -; MSVC-X64-O0-NEXT: jmp .LBB0_2 -; MSVC-X64-O0-NEXT: .LBB0_3: # %return +; MSVC-X64-O0-NEXT: jne .LBB0_2 +; MSVC-X64-O0-NEXT: jmp .LBB0_3 +; MSVC-X64-O0-NEXT: .LBB0_2: # %return ; MSVC-X64-O0-NEXT: movq {{[0-9]+}}(%rsp), %rcx ; MSVC-X64-O0-NEXT: xorq %rsp, %rcx ; MSVC-X64-O0-NEXT: callq __security_check_cookie -; MSVC-X64-O0-NEXT: .LBB0_2: # %return +; MSVC-X64-O0-NEXT: .LBB0_3: # %return ; MSVC-X64-O0-NEXT: addq $56, %rsp ; MSVC-X64-O0-NEXT: retq @@ -225,13 +225,13 @@ define void @test_vla(i32 %n) nounwind ssp { ; MSVC-X86-O0-NEXT: xorl %ebp, %ecx ; MSVC-X86-O0-NEXT: movl ___security_cookie, %eax ; MSVC-X86-O0-NEXT: subl %ecx, %eax -; MSVC-X86-O0-NEXT: jne LBB1_2 -; MSVC-X86-O0-NEXT: jmp LBB1_1 -; MSVC-X86-O0-NEXT: LBB1_2: +; MSVC-X86-O0-NEXT: jne LBB1_1 +; MSVC-X86-O0-NEXT: jmp LBB1_2 +; MSVC-X86-O0-NEXT: LBB1_1: ; MSVC-X86-O0-NEXT: movl -4(%ebp), %ecx ; MSVC-X86-O0-NEXT: xorl %ebp, %ecx ; MSVC-X86-O0-NEXT: calll @__security_check_cookie@4 -; MSVC-X86-O0-NEXT: LBB1_1: +; MSVC-X86-O0-NEXT: LBB1_2: ; MSVC-X86-O0-NEXT: movl %ebp, %esp ; MSVC-X86-O0-NEXT: popl %ebp ; MSVC-X86-O0-NEXT: retl @@ -258,14 +258,14 @@ define void @test_vla(i32 %n) nounwind ssp { ; MSVC-X64-O0-NEXT: xorq %rbp, %rcx ; MSVC-X64-O0-NEXT: movq __security_cookie(%rip), %rax ; MSVC-X64-O0-NEXT: subq %rcx, %rax -; MSVC-X64-O0-NEXT: jne .LBB1_2 -; MSVC-X64-O0-NEXT: jmp .LBB1_1 -; MSVC-X64-O0-NEXT: .LBB1_2: +; MSVC-X64-O0-NEXT: jne .LBB1_1 +; MSVC-X64-O0-NEXT: jmp .LBB1_2 +; MSVC-X64-O0-NEXT: .LBB1_1: ; MSVC-X64-O0-NEXT: movq -8(%rbp), %rcx ; MSVC-X64-O0-NEXT: xorq %rbp, %rcx ; MSVC-X64-O0-NEXT: subq $32, %rsp ; MSVC-X64-O0-NEXT: callq __security_check_cookie -; MSVC-X64-O0-NEXT: .LBB1_1: +; MSVC-X64-O0-NEXT: .LBB1_2: ; MSVC-X64-O0-NEXT: movq %rbp, %rsp ; MSVC-X64-O0-NEXT: popq %rbp ; MSVC-X64-O0-NEXT: retq @@ -387,13 +387,13 @@ define void @test_vla_realign(i32 %n) nounwind ssp { ; MSVC-X86-O0-NEXT: xorl %ebp, %ecx ; MSVC-X86-O0-NEXT: movl ___security_cookie, %eax ; MSVC-X86-O0-NEXT: subl %ecx, %eax -; MSVC-X86-O0-NEXT: jne LBB2_2 -; MSVC-X86-O0-NEXT: jmp LBB2_1 -; MSVC-X86-O0-NEXT: LBB2_2: +; MSVC-X86-O0-NEXT: jne LBB2_1 +; MSVC-X86-O0-NEXT: jmp LBB2_2 +; MSVC-X86-O0-NEXT: LBB2_1: ; MSVC-X86-O0-NEXT: movl 48(%esi), %ecx ; MSVC-X86-O0-NEXT: xorl %ebp, %ecx ; MSVC-X86-O0-NEXT: calll @__security_check_cookie@4 -; MSVC-X86-O0-NEXT: LBB2_1: +; MSVC-X86-O0-NEXT: LBB2_2: ; MSVC-X86-O0-NEXT: leal -4(%ebp), %esp ; MSVC-X86-O0-NEXT: popl %esi ; MSVC-X86-O0-NEXT: popl %ebp @@ -428,14 +428,14 @@ define void @test_vla_realign(i32 %n) nounwind ssp { ; MSVC-X64-O0-NEXT: xorq %rbp, %rcx ; MSVC-X64-O0-NEXT: movq __security_cookie(%rip), %rax ; MSVC-X64-O0-NEXT: subq %rcx, %rax -; MSVC-X64-O0-NEXT: jne .LBB2_2 -; MSVC-X64-O0-NEXT: jmp .LBB2_1 -; MSVC-X64-O0-NEXT: .LBB2_2: +; MSVC-X64-O0-NEXT: jne .LBB2_1 +; MSVC-X64-O0-NEXT: jmp .LBB2_2 +; MSVC-X64-O0-NEXT: .LBB2_1: ; MSVC-X64-O0-NEXT: movq 64(%rbx), %rcx ; MSVC-X64-O0-NEXT: xorq %rbp, %rcx ; MSVC-X64-O0-NEXT: subq $32, %rsp ; MSVC-X64-O0-NEXT: callq __security_check_cookie -; MSVC-X64-O0-NEXT: .LBB2_1: +; MSVC-X64-O0-NEXT: .LBB2_2: ; MSVC-X64-O0-NEXT: leaq 8(%rbp), %rsp ; MSVC-X64-O0-NEXT: popq %rbx ; MSVC-X64-O0-NEXT: popq %rbp diff --git a/llvm/test/CodeGen/X86/stack-protector-phi.ll b/llvm/test/CodeGen/X86/stack-protector-phi.ll index 8041869ad8783..e711dc6669d2f 100644 --- a/llvm/test/CodeGen/X86/stack-protector-phi.ll +++ b/llvm/test/CodeGen/X86/stack-protector-phi.ll @@ -9,11 +9,11 @@ define void @test_phi_diff_size(i1 %c) sspstrong { ; CHECK-NEXT: movq %fs:40, %rax ; CHECK-NEXT: movq %rax, {{[0-9]+}}(%rsp) ; CHECK-NEXT: testb $1, %dil -; CHECK-NEXT: je .LBB0_1 -; CHECK-NEXT: # %bb.2: # %if +; CHECK-NEXT: je .LBB0_2 +; CHECK-NEXT: # %bb.1: # %if ; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rax ; CHECK-NEXT: jmp .LBB0_3 -; CHECK-NEXT: .LBB0_1: +; CHECK-NEXT: .LBB0_2: ; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rax ; CHECK-NEXT: .LBB0_3: # %join ; CHECK-NEXT: movq $0, (%rax) diff --git a/llvm/test/CodeGen/X86/statepoint-invoke.ll b/llvm/test/CodeGen/X86/statepoint-invoke.ll index 34dbc21a8a8cb..cf080ba921d49 100644 --- a/llvm/test/CodeGen/X86/statepoint-invoke.ll +++ b/llvm/test/CodeGen/X86/statepoint-invoke.ll @@ -15,10 +15,10 @@ define ptr addrspace(1) @test_basic(ptr addrspace(1) %obj, ; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: movq %rdi, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movq %rsi, {{[0-9]+}}(%rsp) -; CHECK-NEXT: .Ltmp0: +; CHECK-NEXT: .Ltmp0: # EH_LABEL ; CHECK-NEXT: callq some_call@PLT ; CHECK-NEXT: .Ltmp3: -; CHECK-NEXT: .Ltmp1: +; CHECK-NEXT: .Ltmp1: # EH_LABEL ; CHECK-NEXT: # %bb.1: # %invoke_safepoint_normal_dest ; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax ; CHECK-NEXT: addq $24, %rsp @@ -26,7 +26,7 @@ define ptr addrspace(1) @test_basic(ptr addrspace(1) %obj, ; CHECK-NEXT: retq ; CHECK-NEXT: .LBB0_2: # %exceptional_return ; CHECK-NEXT: .cfi_def_cfa_offset 32 -; CHECK-NEXT: .Ltmp2: +; CHECK-NEXT: .Ltmp2: # EH_LABEL ; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax ; CHECK-NEXT: addq $24, %rsp ; CHECK-NEXT: .cfi_def_cfa_offset 8 @@ -64,17 +64,17 @@ define ptr addrspace(1) @test_result(ptr addrspace(1) %obj, ; CHECK-NEXT: pushq %rax ; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: movq %rdi, (%rsp) -; CHECK-NEXT: .Ltmp4: +; CHECK-NEXT: .Ltmp4: # EH_LABEL ; CHECK-NEXT: callq some_other_call@PLT ; CHECK-NEXT: .Ltmp7: -; CHECK-NEXT: .Ltmp5: +; CHECK-NEXT: .Ltmp5: # EH_LABEL ; CHECK-NEXT: # %bb.1: # %normal_return ; CHECK-NEXT: popq %rcx ; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: retq ; CHECK-NEXT: .LBB1_2: # %exceptional_return ; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: .Ltmp6: +; CHECK-NEXT: .Ltmp6: # EH_LABEL ; CHECK-NEXT: movq (%rsp), %rax ; CHECK-NEXT: popq %rcx ; CHECK-NEXT: .cfi_def_cfa_offset 8 @@ -115,11 +115,11 @@ define ptr addrspace(1) @test_same_val(i1 %cond, ptr addrspace(1) %val1, ptr add ; CHECK-NEXT: # %bb.1: # %left ; CHECK-NEXT: movq %rsi, (%rsp) ; CHECK-NEXT: movq %rdx, {{[0-9]+}}(%rsp) -; CHECK-NEXT: .Ltmp11: +; CHECK-NEXT: .Ltmp11: # EH_LABEL ; CHECK-NEXT: movq %rsi, %rdi ; CHECK-NEXT: callq some_call@PLT ; CHECK-NEXT: .Ltmp14: -; CHECK-NEXT: .Ltmp12: +; CHECK-NEXT: .Ltmp12: # EH_LABEL ; CHECK-NEXT: # %bb.2: # %left.relocs ; CHECK-NEXT: movq (%rsp), %rax ; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rcx @@ -127,11 +127,11 @@ define ptr addrspace(1) @test_same_val(i1 %cond, ptr addrspace(1) %val1, ptr add ; CHECK-NEXT: .LBB2_3: # %right ; CHECK-NEXT: movq %rdx, (%rsp) ; CHECK-NEXT: movq %rcx, {{[0-9]+}}(%rsp) -; CHECK-NEXT: .Ltmp8: +; CHECK-NEXT: .Ltmp8: # EH_LABEL ; CHECK-NEXT: movq %rsi, %rdi ; CHECK-NEXT: callq some_call@PLT ; CHECK-NEXT: .Ltmp15: -; CHECK-NEXT: .Ltmp9: +; CHECK-NEXT: .Ltmp9: # EH_LABEL ; CHECK-NEXT: # %bb.4: # %right.relocs ; CHECK-NEXT: movq (%rsp), %rcx ; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax @@ -144,13 +144,13 @@ define ptr addrspace(1) @test_same_val(i1 %cond, ptr addrspace(1) %val1, ptr add ; CHECK-NEXT: popq %rbx ; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB2_9: # %exceptional_return.right +; CHECK-NEXT: .LBB2_7: # %exceptional_return.right ; CHECK-NEXT: .cfi_def_cfa_offset 32 -; CHECK-NEXT: .Ltmp10: +; CHECK-NEXT: .Ltmp10: # EH_LABEL ; CHECK-NEXT: movq (%rsp), %rax ; CHECK-NEXT: jmp .LBB2_6 -; CHECK-NEXT: .LBB2_7: # %exceptional_return.left -; CHECK-NEXT: .Ltmp13: +; CHECK-NEXT: .LBB2_8: # %exceptional_return.left +; CHECK-NEXT: .Ltmp13: # EH_LABEL ; CHECK-NEXT: movq (%rsp), %rax ; CHECK-NEXT: jmp .LBB2_6 gc "statepoint-example" personality ptr @"personality_function" { @@ -199,10 +199,10 @@ define ptr addrspace(1) @test_null_undef(ptr addrspace(1) %val1) ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: pushq %rax ; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: .Ltmp16: +; CHECK-NEXT: .Ltmp16: # EH_LABEL ; CHECK-NEXT: callq some_call@PLT ; CHECK-NEXT: .Ltmp19: -; CHECK-NEXT: .Ltmp17: +; CHECK-NEXT: .Ltmp17: # EH_LABEL ; CHECK-NEXT: .LBB3_1: # %normal_return ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: popq %rcx @@ -210,7 +210,7 @@ define ptr addrspace(1) @test_null_undef(ptr addrspace(1) %val1) ; CHECK-NEXT: retq ; CHECK-NEXT: .LBB3_2: # %exceptional_return ; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: .Ltmp18: +; CHECK-NEXT: .Ltmp18: # EH_LABEL ; CHECK-NEXT: jmp .LBB3_1 gc "statepoint-example" personality ptr @"personality_function" { entry: @@ -235,10 +235,10 @@ define ptr addrspace(1) @test_alloca_and_const(ptr addrspace(1) %val1) ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: pushq %rax ; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: .Ltmp20: +; CHECK-NEXT: .Ltmp20: # EH_LABEL ; CHECK-NEXT: callq some_call@PLT ; CHECK-NEXT: .Ltmp23: -; CHECK-NEXT: .Ltmp21: +; CHECK-NEXT: .Ltmp21: # EH_LABEL ; CHECK-NEXT: # %bb.1: # %normal_return ; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rax ; CHECK-NEXT: popq %rcx @@ -246,7 +246,7 @@ define ptr addrspace(1) @test_alloca_and_const(ptr addrspace(1) %val1) ; CHECK-NEXT: retq ; CHECK-NEXT: .LBB4_2: # %exceptional_return ; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: .Ltmp22: +; CHECK-NEXT: .Ltmp22: # EH_LABEL ; CHECK-NEXT: movl $15, %eax ; CHECK-NEXT: popq %rcx ; CHECK-NEXT: .cfi_def_cfa_offset 8 diff --git a/llvm/test/CodeGen/X86/sub-with-overflow.ll b/llvm/test/CodeGen/X86/sub-with-overflow.ll index d3bd3b1cdf0ac..728a6e6df649c 100644 --- a/llvm/test/CodeGen/X86/sub-with-overflow.ll +++ b/llvm/test/CodeGen/X86/sub-with-overflow.ll @@ -10,14 +10,14 @@ define i1 @func1(i32 %v1, i32 %v2) nounwind { ; CHECK-NEXT: subl $12, %esp ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: subl {{[0-9]+}}(%esp), %eax -; CHECK-NEXT: jno .LBB0_1 -; CHECK-NEXT: # %bb.2: # %overflow +; CHECK-NEXT: jno .LBB0_2 +; CHECK-NEXT: # %bb.1: # %overflow ; CHECK-NEXT: movl $no, (%esp) ; CHECK-NEXT: calll printf@PLT ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: addl $12, %esp ; CHECK-NEXT: retl -; CHECK-NEXT: .LBB0_1: # %normal +; CHECK-NEXT: .LBB0_2: # %normal ; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp) ; CHECK-NEXT: movl $ok, (%esp) ; CHECK-NEXT: calll printf@PLT @@ -46,14 +46,14 @@ define i1 @func2(i32 %v1, i32 %v2) nounwind { ; CHECK-NEXT: subl $12, %esp ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: subl {{[0-9]+}}(%esp), %eax -; CHECK-NEXT: jae .LBB1_1 -; CHECK-NEXT: # %bb.2: # %carry +; CHECK-NEXT: jae .LBB1_2 +; CHECK-NEXT: # %bb.1: # %carry ; CHECK-NEXT: movl $no, (%esp) ; CHECK-NEXT: calll printf@PLT ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: addl $12, %esp ; CHECK-NEXT: retl -; CHECK-NEXT: .LBB1_1: # %normal +; CHECK-NEXT: .LBB1_2: # %normal ; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp) ; CHECK-NEXT: movl $ok, (%esp) ; CHECK-NEXT: calll printf@PLT diff --git a/llvm/test/CodeGen/X86/subreg-to-reg-6.ll b/llvm/test/CodeGen/X86/subreg-to-reg-6.ll index f0dc17b556613..8fdb4119166bf 100644 --- a/llvm/test/CodeGen/X86/subreg-to-reg-6.ll +++ b/llvm/test/CodeGen/X86/subreg-to-reg-6.ll @@ -5,14 +5,14 @@ define i64 @foo() nounwind { ; CHECK-LABEL: foo: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cmpl $12, 0 -; CHECK-NEXT: je .LBB0_1 -; CHECK-NEXT: # %bb.2: # %bb65 +; CHECK-NEXT: je .LBB0_2 +; CHECK-NEXT: # %bb.1: # %bb65 ; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: #APP ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB0_1: # %bb56 +; CHECK-NEXT: .LBB0_2: # %bb56 entry: %t0 = load i32, ptr null, align 8 switch i32 %t0, label %bb65 [ diff --git a/llvm/test/CodeGen/X86/switch-bt.ll b/llvm/test/CodeGen/X86/switch-bt.ll index 2bf7c46e67e18..6d4580cacd533 100644 --- a/llvm/test/CodeGen/X86/switch-bt.ll +++ b/llvm/test/CodeGen/X86/switch-bt.ll @@ -16,21 +16,21 @@ define void @test(ptr %l) nounwind { ; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: movabsq $2305843009482129440, %rcx # imm = 0x2000000010000020 ; CHECK-NEXT: btq %rax, %rcx -; CHECK-NEXT: jb .LBB0_6 +; CHECK-NEXT: jb .LBB0_4 ; CHECK-NEXT: # %bb.2: # %entry ; CHECK-NEXT: movl $671088640, %ecx # imm = 0x28000000 ; CHECK-NEXT: btq %rax, %rcx -; CHECK-NEXT: jae .LBB0_3 -; CHECK-NEXT: # %bb.5: # %sw.bb +; CHECK-NEXT: jae .LBB0_5 +; CHECK-NEXT: # %bb.3: # %sw.bb ; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: jmp .LBB0_8 -; CHECK-NEXT: .LBB0_6: # %sw.bb2 +; CHECK-NEXT: .LBB0_4: # %sw.bb2 ; CHECK-NEXT: movl $1, %edi ; CHECK-NEXT: jmp .LBB0_8 -; CHECK-NEXT: .LBB0_3: # %entry +; CHECK-NEXT: .LBB0_5: # %entry ; CHECK-NEXT: testq %rax, %rax ; CHECK-NEXT: jne .LBB0_7 -; CHECK-NEXT: # %bb.4: # %sw.bb4 +; CHECK-NEXT: # %bb.6: # %sw.bb4 ; CHECK-NEXT: movl $3, %edi ; CHECK-NEXT: jmp .LBB0_8 ; CHECK-NEXT: .LBB0_7: # %sw.default @@ -145,38 +145,38 @@ define void @test4(i32 %x, ptr %y) { ; CHECK-NEXT: je .LBB3_9 ; CHECK-NEXT: # %bb.2: # %entry ; CHECK-NEXT: cmpl $20, %edi -; CHECK-NEXT: je .LBB3_10 +; CHECK-NEXT: je .LBB3_12 ; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: cmpl $30, %edi -; CHECK-NEXT: jne .LBB3_13 +; CHECK-NEXT: jne .LBB3_11 ; CHECK-NEXT: # %bb.4: # %sw.bb2 ; CHECK-NEXT: movl $3, (%rsi) ; CHECK-NEXT: retq ; CHECK-NEXT: .LBB3_5: # %entry ; CHECK-NEXT: cmpl $40, %edi -; CHECK-NEXT: je .LBB3_11 +; CHECK-NEXT: je .LBB3_10 ; CHECK-NEXT: # %bb.6: # %entry ; CHECK-NEXT: cmpl $50, %edi -; CHECK-NEXT: je .LBB3_12 +; CHECK-NEXT: je .LBB3_13 ; CHECK-NEXT: # %bb.7: # %entry ; CHECK-NEXT: cmpl $60, %edi -; CHECK-NEXT: jne .LBB3_13 +; CHECK-NEXT: jne .LBB3_11 ; CHECK-NEXT: # %bb.8: # %sw.bb5 ; CHECK-NEXT: movl $6, (%rsi) ; CHECK-NEXT: retq ; CHECK-NEXT: .LBB3_9: # %sw.bb ; CHECK-NEXT: movl $1, (%rsi) ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB3_11: # %sw.bb3 +; CHECK-NEXT: .LBB3_10: # %sw.bb3 ; CHECK-NEXT: movl $4, (%rsi) ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB3_13: # %sw.default +; CHECK-NEXT: .LBB3_11: # %sw.default ; CHECK-NEXT: movl $7, (%rsi) ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB3_10: # %sw.bb1 +; CHECK-NEXT: .LBB3_12: # %sw.bb1 ; CHECK-NEXT: movl $2, (%rsi) ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB3_12: # %sw.bb4 +; CHECK-NEXT: .LBB3_13: # %sw.bb4 ; CHECK-NEXT: movl $5, (%rsi) ; CHECK-NEXT: retq @@ -231,14 +231,14 @@ define void @test5(i32 %x) { ; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: movl $146, %eax ; CHECK-NEXT: btl %edi, %eax -; CHECK-NEXT: jae .LBB4_2 -; CHECK-NEXT: # %bb.4: # %bb1 +; CHECK-NEXT: jae .LBB4_4 +; CHECK-NEXT: # %bb.2: # %bb1 ; CHECK-NEXT: movl $1, %edi ; CHECK-NEXT: callq g@PLT ; CHECK-NEXT: .LBB4_3: # %bb0 ; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: callq g@PLT -; CHECK-NEXT: .LBB4_2: # %bb2 +; CHECK-NEXT: .LBB4_4: # %bb2 ; CHECK-NEXT: movl $2, %edi ; CHECK-NEXT: callq g@PLT diff --git a/llvm/test/CodeGen/X86/switch-jump-table.ll b/llvm/test/CodeGen/X86/switch-jump-table.ll index 931206f3c6e8a..b8230b41f13dd 100644 --- a/llvm/test/CodeGen/X86/switch-jump-table.ll +++ b/llvm/test/CodeGen/X86/switch-jump-table.ll @@ -41,14 +41,13 @@ exit: default: unreachable -; The jump table has four entries. +; The jump table has five entries. ; CHECK-LABEL: .LJTI0_0: -; CHECK-NEXT: .long .LBB0_1 -; CHECK-NEXT: .long .LBB0_2 -; CHECK-NEXT: .long .LBB0_3 -; CHECK-NEXT: .long .LBB0_4 -; CHECK-NEXT: .long .LBB0_5 -; CHECK-NEXT: .long .LBB0_5 +; CHECK-NEXT: .long .LBB0_{{[0-9]+}} +; CHECK-NEXT: .long .LBB0_{{[0-9]+}} +; CHECK-NEXT: .long .LBB0_{{[0-9]+}} +; CHECK-NEXT: .long .LBB0_{{[0-9]+}} +; CHECK-NEXT: .long .LBB0_{{[0-9]+}} } ; Check if branch probabilities are correctly assigned to the jump table. diff --git a/llvm/test/CodeGen/X86/switch-phi-const.ll b/llvm/test/CodeGen/X86/switch-phi-const.ll index dba7666a14fc7..3c2cfaa6cf276 100644 --- a/llvm/test/CodeGen/X86/switch-phi-const.ll +++ b/llvm/test/CodeGen/X86/switch-phi-const.ll @@ -9,35 +9,35 @@ define void @switch_phi_const(i32 %x) { ; CHECK-NEXT: # kill: def $edi killed $edi def $rdi ; CHECK-NEXT: leal -1(%rdi), %eax ; CHECK-NEXT: cmpl $54, %eax -; CHECK-NEXT: ja .LBB0_9 +; CHECK-NEXT: ja .LBB0_8 ; CHECK-NEXT: # %bb.1: # %bb0 ; CHECK-NEXT: jmpq *.LJTI0_0(,%rax,8) -; CHECK-NEXT: .LBB0_3: # %case_7 +; CHECK-NEXT: .LBB0_2: # %case_7 ; CHECK-NEXT: movq g@GOTPCREL(%rip), %rax ; CHECK-NEXT: movl (%rax), %edi ; CHECK-NEXT: movq effect@GOTPCREL(%rip), %rax ; CHECK-NEXT: movl $7, (%rax) -; CHECK-NEXT: .LBB0_4: # %case_1_loop +; CHECK-NEXT: .LBB0_3: # %case_1_loop ; CHECK-NEXT: movq effect@GOTPCREL(%rip), %rax ; CHECK-NEXT: movl $1, (%rax) -; CHECK-NEXT: .LBB0_5: # %case_5 +; CHECK-NEXT: .LBB0_4: # %case_5 ; CHECK-NEXT: movq effect@GOTPCREL(%rip), %rax ; CHECK-NEXT: movl $5, (%rax) -; CHECK-NEXT: .LBB0_6: # %case_13 +; CHECK-NEXT: .LBB0_5: # %case_13 ; CHECK-NEXT: movq effect@GOTPCREL(%rip), %rax ; CHECK-NEXT: movl $13, (%rax) -; CHECK-NEXT: .LBB0_7: # %case_42 +; CHECK-NEXT: .LBB0_6: # %case_42 ; CHECK-NEXT: movq effect@GOTPCREL(%rip), %rax ; CHECK-NEXT: movl %edi, (%rax) ; CHECK-NEXT: movl $55, %eax -; CHECK-NEXT: .LBB0_8: # %case_55 +; CHECK-NEXT: .LBB0_7: # %case_55 ; CHECK-NEXT: movq effect@GOTPCREL(%rip), %rcx ; CHECK-NEXT: movl %eax, (%rcx) -; CHECK-NEXT: .LBB0_9: # %default +; CHECK-NEXT: .LBB0_8: # %default ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB0_2: +; CHECK-NEXT: .LBB0_9: ; CHECK-NEXT: movl $42, %eax -; CHECK-NEXT: jmp .LBB0_8 +; CHECK-NEXT: jmp .LBB0_7 bb0: switch i32 %x, label %default [ i32 1, label %case_1_loop @@ -96,36 +96,36 @@ define void @switch_trunc_phi_const(i32 %x) { ; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: leal -1(%rax), %ecx ; CHECK-NEXT: cmpl $54, %ecx -; CHECK-NEXT: ja .LBB1_9 +; CHECK-NEXT: ja .LBB1_3 ; CHECK-NEXT: # %bb.1: # %bb0 ; CHECK-NEXT: jmpq *.LJTI1_0(,%rcx,8) ; CHECK-NEXT: .LBB1_2: ; CHECK-NEXT: movl $3895, %eax # imm = 0xF37 -; CHECK-NEXT: jmp .LBB1_7 -; CHECK-NEXT: .LBB1_9: # %default +; CHECK-NEXT: jmp .LBB1_8 +; CHECK-NEXT: .LBB1_3: # %default ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB1_3: # %case_1_loop +; CHECK-NEXT: .LBB1_4: # %case_1_loop ; CHECK-NEXT: movq effect64@GOTPCREL(%rip), %rcx ; CHECK-NEXT: movq $1, (%rcx) -; CHECK-NEXT: .LBB1_4: # %case_5 +; CHECK-NEXT: .LBB1_5: # %case_5 ; CHECK-NEXT: movq effect64@GOTPCREL(%rip), %rcx ; CHECK-NEXT: movq $5, (%rcx) -; CHECK-NEXT: .LBB1_5: # %case_13 +; CHECK-NEXT: .LBB1_6: # %case_13 ; CHECK-NEXT: movq effect64@GOTPCREL(%rip), %rcx ; CHECK-NEXT: movq $13, (%rcx) -; CHECK-NEXT: .LBB1_6: # %case_42 +; CHECK-NEXT: .LBB1_7: # %case_42 ; CHECK-NEXT: movq effect64@GOTPCREL(%rip), %rcx ; CHECK-NEXT: movq %rax, (%rcx) ; CHECK-NEXT: movl $55, %eax -; CHECK-NEXT: .LBB1_7: # %case_55 +; CHECK-NEXT: .LBB1_8: # %case_55 ; CHECK-NEXT: movq effect64@GOTPCREL(%rip), %rcx ; CHECK-NEXT: movq %rax, (%rcx) -; CHECK-NEXT: .LBB1_8: # %case_7 +; CHECK-NEXT: .LBB1_9: # %case_7 ; CHECK-NEXT: movq g64@GOTPCREL(%rip), %rax ; CHECK-NEXT: movq (%rax), %rax ; CHECK-NEXT: movq effect64@GOTPCREL(%rip), %rcx ; CHECK-NEXT: movq $7, (%rcx) -; CHECK-NEXT: jmp .LBB1_3 +; CHECK-NEXT: jmp .LBB1_4 bb0: %x_trunc = trunc i32 %x to i8 switch i8 %x_trunc, label %default [ diff --git a/llvm/test/CodeGen/X86/switch-zextload.ll b/llvm/test/CodeGen/X86/switch-zextload.ll index f83908ce417e6..e5c29376957e6 100644 --- a/llvm/test/CodeGen/X86/switch-zextload.ll +++ b/llvm/test/CodeGen/X86/switch-zextload.ll @@ -13,12 +13,12 @@ define fastcc void @set_proof_and_disproof_numbers(ptr nocapture %node) nounwind ; CHECK: ## %bb.0: ## %entry ; CHECK-NEXT: movzbl 0, %eax ; CHECK-NEXT: cmpl $3, %eax -; CHECK-NEXT: ja LBB0_3 +; CHECK-NEXT: ja LBB0_2 ; CHECK-NEXT: ## %bb.1: ## %entry ; CHECK-NEXT: jmpl *LJTI0_0(,%eax,4) -; CHECK-NEXT: LBB0_3: ## %return +; CHECK-NEXT: LBB0_2: ## %return ; CHECK-NEXT: retl -; CHECK-NEXT: LBB0_2: ## %bb31 +; CHECK-NEXT: LBB0_3: ## %bb31 ; CHECK-NEXT: ud2 entry: %0 = load i8, ptr null, align 1 ; [#uses=1] diff --git a/llvm/test/CodeGen/X86/switch.ll b/llvm/test/CodeGen/X86/switch.ll index c75819c2fd2c5..46976512a322b 100644 --- a/llvm/test/CodeGen/X86/switch.ll +++ b/llvm/test/CodeGen/X86/switch.ll @@ -14,10 +14,10 @@ define void @basic(i32 %x) { ; CHECK-NEXT: ja .LBB0_4 ; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: jmpq *.LJTI0_0(,%rdi,8) -; CHECK-NEXT: .LBB0_3: # %bb2 +; CHECK-NEXT: .LBB0_2: # %bb2 ; CHECK-NEXT: movl $1, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB0_2: # %bb0 +; CHECK-NEXT: .LBB0_3: # %bb0 ; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL ; CHECK-NEXT: .LBB0_4: # %return @@ -32,23 +32,23 @@ define void @basic(i32 %x) { ; NOOPT-NEXT: movl %eax, %ecx ; NOOPT-NEXT: movq %rcx, (%rsp) # 8-byte Spill ; NOOPT-NEXT: subl $4, %eax -; NOOPT-NEXT: ja .LBB0_4 -; NOOPT-NEXT: # %bb.5: # %entry +; NOOPT-NEXT: ja .LBB0_5 +; NOOPT-NEXT: # %bb.1: # %entry ; NOOPT-NEXT: movq (%rsp), %rax # 8-byte Reload ; NOOPT-NEXT: movq .LJTI0_0(,%rax,8), %rax ; NOOPT-NEXT: jmpq *%rax -; NOOPT-NEXT: .LBB0_1: # %bb0 +; NOOPT-NEXT: .LBB0_2: # %bb0 ; NOOPT-NEXT: xorl %edi, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB0_4 -; NOOPT-NEXT: .LBB0_2: # %bb1 +; NOOPT-NEXT: jmp .LBB0_5 +; NOOPT-NEXT: .LBB0_3: # %bb1 ; NOOPT-NEXT: movl $1, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB0_4 -; NOOPT-NEXT: .LBB0_3: # %bb2 +; NOOPT-NEXT: jmp .LBB0_5 +; NOOPT-NEXT: .LBB0_4: # %bb2 ; NOOPT-NEXT: movl $1, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: .LBB0_4: # %return +; NOOPT-NEXT: .LBB0_5: # %return ; NOOPT-NEXT: popq %rax ; NOOPT-NEXT: .cfi_def_cfa_offset 8 ; NOOPT-NEXT: retq @@ -73,23 +73,23 @@ define void @basic_nojumptable(i32 %x) "no-jump-tables"="true" { ; CHECK-NEXT: jg .LBB1_4 ; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: cmpl $1, %edi -; CHECK-NEXT: je .LBB1_7 +; CHECK-NEXT: je .LBB1_6 ; CHECK-NEXT: # %bb.2: # %entry ; CHECK-NEXT: cmpl $3, %edi -; CHECK-NEXT: jne .LBB1_6 +; CHECK-NEXT: jne .LBB1_7 ; CHECK-NEXT: # %bb.3: # %bb0 ; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL ; CHECK-NEXT: .LBB1_4: # %entry ; CHECK-NEXT: cmpl $4, %edi -; CHECK-NEXT: je .LBB1_7 +; CHECK-NEXT: je .LBB1_6 ; CHECK-NEXT: # %bb.5: # %entry ; CHECK-NEXT: cmpl $5, %edi -; CHECK-NEXT: jne .LBB1_6 -; CHECK-NEXT: .LBB1_7: # %bb2 +; CHECK-NEXT: jne .LBB1_7 +; CHECK-NEXT: .LBB1_6: # %bb2 ; CHECK-NEXT: movl $1, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB1_6: # %return +; CHECK-NEXT: .LBB1_7: # %return ; CHECK-NEXT: retq ; ; NOOPT-LABEL: basic_nojumptable: @@ -98,35 +98,35 @@ define void @basic_nojumptable(i32 %x) "no-jump-tables"="true" { ; NOOPT-NEXT: .cfi_def_cfa_offset 16 ; NOOPT-NEXT: movl %edi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill ; NOOPT-NEXT: subl $1, %edi -; NOOPT-NEXT: je .LBB1_2 -; NOOPT-NEXT: jmp .LBB1_5 -; NOOPT-NEXT: .LBB1_5: # %entry +; NOOPT-NEXT: je .LBB1_5 +; NOOPT-NEXT: jmp .LBB1_1 +; NOOPT-NEXT: .LBB1_1: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $3, %eax -; NOOPT-NEXT: je .LBB1_1 -; NOOPT-NEXT: jmp .LBB1_6 -; NOOPT-NEXT: .LBB1_6: # %entry +; NOOPT-NEXT: je .LBB1_4 +; NOOPT-NEXT: jmp .LBB1_2 +; NOOPT-NEXT: .LBB1_2: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $4, %eax -; NOOPT-NEXT: je .LBB1_2 -; NOOPT-NEXT: jmp .LBB1_7 -; NOOPT-NEXT: .LBB1_7: # %entry +; NOOPT-NEXT: je .LBB1_5 +; NOOPT-NEXT: jmp .LBB1_3 +; NOOPT-NEXT: .LBB1_3: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $5, %eax -; NOOPT-NEXT: je .LBB1_3 -; NOOPT-NEXT: jmp .LBB1_4 -; NOOPT-NEXT: .LBB1_1: # %bb0 +; NOOPT-NEXT: je .LBB1_6 +; NOOPT-NEXT: jmp .LBB1_7 +; NOOPT-NEXT: .LBB1_4: # %bb0 ; NOOPT-NEXT: xorl %edi, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB1_4 -; NOOPT-NEXT: .LBB1_2: # %bb1 +; NOOPT-NEXT: jmp .LBB1_7 +; NOOPT-NEXT: .LBB1_5: # %bb1 ; NOOPT-NEXT: movl $1, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB1_4 -; NOOPT-NEXT: .LBB1_3: # %bb2 +; NOOPT-NEXT: jmp .LBB1_7 +; NOOPT-NEXT: .LBB1_6: # %bb2 ; NOOPT-NEXT: movl $1, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: .LBB1_4: # %return +; NOOPT-NEXT: .LBB1_7: # %return ; NOOPT-NEXT: popq %rax ; NOOPT-NEXT: .cfi_def_cfa_offset 8 ; NOOPT-NEXT: retq @@ -153,10 +153,10 @@ define void @basic_nojumptable_false(i32 %x) "no-jump-tables"="false" { ; CHECK-NEXT: ja .LBB2_4 ; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: jmpq *.LJTI2_0(,%rdi,8) -; CHECK-NEXT: .LBB2_3: # %bb2 +; CHECK-NEXT: .LBB2_2: # %bb2 ; CHECK-NEXT: movl $1, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB2_2: # %bb0 +; CHECK-NEXT: .LBB2_3: # %bb0 ; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL ; CHECK-NEXT: .LBB2_4: # %return @@ -171,23 +171,23 @@ define void @basic_nojumptable_false(i32 %x) "no-jump-tables"="false" { ; NOOPT-NEXT: movl %eax, %ecx ; NOOPT-NEXT: movq %rcx, (%rsp) # 8-byte Spill ; NOOPT-NEXT: subl $4, %eax -; NOOPT-NEXT: ja .LBB2_4 -; NOOPT-NEXT: # %bb.5: # %entry +; NOOPT-NEXT: ja .LBB2_5 +; NOOPT-NEXT: # %bb.1: # %entry ; NOOPT-NEXT: movq (%rsp), %rax # 8-byte Reload ; NOOPT-NEXT: movq .LJTI2_0(,%rax,8), %rax ; NOOPT-NEXT: jmpq *%rax -; NOOPT-NEXT: .LBB2_1: # %bb0 +; NOOPT-NEXT: .LBB2_2: # %bb0 ; NOOPT-NEXT: xorl %edi, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB2_4 -; NOOPT-NEXT: .LBB2_2: # %bb1 +; NOOPT-NEXT: jmp .LBB2_5 +; NOOPT-NEXT: .LBB2_3: # %bb1 ; NOOPT-NEXT: movl $1, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB2_4 -; NOOPT-NEXT: .LBB2_3: # %bb2 +; NOOPT-NEXT: jmp .LBB2_5 +; NOOPT-NEXT: .LBB2_4: # %bb2 ; NOOPT-NEXT: movl $1, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: .LBB2_4: # %return +; NOOPT-NEXT: .LBB2_5: # %return ; NOOPT-NEXT: popq %rax ; NOOPT-NEXT: .cfi_def_cfa_offset 8 ; NOOPT-NEXT: retq @@ -232,22 +232,22 @@ define void @simple_ranges(i32 %x) { ; NOOPT-NEXT: .cfi_def_cfa_offset 16 ; NOOPT-NEXT: movl %edi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill ; NOOPT-NEXT: subl $4, %edi -; NOOPT-NEXT: jb .LBB3_1 -; NOOPT-NEXT: jmp .LBB3_4 -; NOOPT-NEXT: .LBB3_4: # %entry +; NOOPT-NEXT: jb .LBB3_2 +; NOOPT-NEXT: jmp .LBB3_1 +; NOOPT-NEXT: .LBB3_1: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: addl $-100, %eax ; NOOPT-NEXT: subl $4, %eax -; NOOPT-NEXT: jb .LBB3_2 -; NOOPT-NEXT: jmp .LBB3_3 -; NOOPT-NEXT: .LBB3_1: # %bb0 +; NOOPT-NEXT: jb .LBB3_3 +; NOOPT-NEXT: jmp .LBB3_4 +; NOOPT-NEXT: .LBB3_2: # %bb0 ; NOOPT-NEXT: xorl %edi, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB3_3 -; NOOPT-NEXT: .LBB3_2: # %bb1 +; NOOPT-NEXT: jmp .LBB3_4 +; NOOPT-NEXT: .LBB3_3: # %bb1 ; NOOPT-NEXT: movl $1, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: .LBB3_3: # %return +; NOOPT-NEXT: .LBB3_4: # %return ; NOOPT-NEXT: popq %rax ; NOOPT-NEXT: .cfi_def_cfa_offset 8 ; NOOPT-NEXT: retq @@ -284,10 +284,10 @@ define void @jt_is_better(i32 %x) { ; CHECK-NEXT: .LBB4_3: # %bb1 ; CHECK-NEXT: movl $1, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB4_5: # %bb3 +; CHECK-NEXT: .LBB4_4: # %bb3 ; CHECK-NEXT: movl $3, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB4_4: # %bb2 +; CHECK-NEXT: .LBB4_5: # %bb2 ; CHECK-NEXT: movl $2, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL ; CHECK-NEXT: .LBB4_6: # %bb4 @@ -304,31 +304,31 @@ define void @jt_is_better(i32 %x) { ; NOOPT-NEXT: # kill: def $rax killed $eax ; NOOPT-NEXT: movq %rax, (%rsp) # 8-byte Spill ; NOOPT-NEXT: subl $8, %edi -; NOOPT-NEXT: ja .LBB4_6 -; NOOPT-NEXT: # %bb.7: # %entry +; NOOPT-NEXT: ja .LBB4_7 +; NOOPT-NEXT: # %bb.1: # %entry ; NOOPT-NEXT: movq (%rsp), %rax # 8-byte Reload ; NOOPT-NEXT: movq .LJTI4_0(,%rax,8), %rax ; NOOPT-NEXT: jmpq *%rax -; NOOPT-NEXT: .LBB4_1: # %bb0 +; NOOPT-NEXT: .LBB4_2: # %bb0 ; NOOPT-NEXT: xorl %edi, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB4_6 -; NOOPT-NEXT: .LBB4_2: # %bb1 +; NOOPT-NEXT: jmp .LBB4_7 +; NOOPT-NEXT: .LBB4_3: # %bb1 ; NOOPT-NEXT: movl $1, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB4_6 -; NOOPT-NEXT: .LBB4_3: # %bb2 +; NOOPT-NEXT: jmp .LBB4_7 +; NOOPT-NEXT: .LBB4_4: # %bb2 ; NOOPT-NEXT: movl $2, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB4_6 -; NOOPT-NEXT: .LBB4_4: # %bb3 +; NOOPT-NEXT: jmp .LBB4_7 +; NOOPT-NEXT: .LBB4_5: # %bb3 ; NOOPT-NEXT: movl $3, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB4_6 -; NOOPT-NEXT: .LBB4_5: # %bb4 +; NOOPT-NEXT: jmp .LBB4_7 +; NOOPT-NEXT: .LBB4_6: # %bb4 ; NOOPT-NEXT: movl $4, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: .LBB4_6: # %return +; NOOPT-NEXT: .LBB4_7: # %return ; NOOPT-NEXT: popq %rax ; NOOPT-NEXT: .cfi_def_cfa_offset 8 ; NOOPT-NEXT: retq @@ -362,25 +362,25 @@ define void @bt_is_better(i32 %x) { ; CHECK-LABEL: bt_is_better: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cmpl $8, %edi -; CHECK-NEXT: ja .LBB5_4 +; CHECK-NEXT: ja .LBB5_6 ; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: movl $73, %eax ; CHECK-NEXT: btl %edi, %eax -; CHECK-NEXT: jb .LBB5_5 +; CHECK-NEXT: jb .LBB5_4 ; CHECK-NEXT: # %bb.2: # %entry ; CHECK-NEXT: movl $146, %eax ; CHECK-NEXT: btl %edi, %eax -; CHECK-NEXT: jae .LBB5_3 -; CHECK-NEXT: # %bb.6: # %bb1 +; CHECK-NEXT: jae .LBB5_5 +; CHECK-NEXT: # %bb.3: # %bb1 ; CHECK-NEXT: movl $1, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB5_5: # %bb0 +; CHECK-NEXT: .LBB5_4: # %bb0 ; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB5_3: # %bb2 +; CHECK-NEXT: .LBB5_5: # %bb2 ; CHECK-NEXT: movl $2, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB5_4: # %return +; CHECK-NEXT: .LBB5_6: # %return ; CHECK-NEXT: retq ; ; NOOPT-LABEL: bt_is_better: @@ -389,60 +389,60 @@ define void @bt_is_better(i32 %x) { ; NOOPT-NEXT: .cfi_def_cfa_offset 16 ; NOOPT-NEXT: movl %edi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill ; NOOPT-NEXT: testl %edi, %edi -; NOOPT-NEXT: je .LBB5_1 -; NOOPT-NEXT: jmp .LBB5_5 -; NOOPT-NEXT: .LBB5_5: # %entry +; NOOPT-NEXT: je .LBB5_9 +; NOOPT-NEXT: jmp .LBB5_1 +; NOOPT-NEXT: .LBB5_1: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $1, %eax -; NOOPT-NEXT: je .LBB5_2 -; NOOPT-NEXT: jmp .LBB5_6 -; NOOPT-NEXT: .LBB5_6: # %entry +; NOOPT-NEXT: je .LBB5_10 +; NOOPT-NEXT: jmp .LBB5_2 +; NOOPT-NEXT: .LBB5_2: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $2, %eax -; NOOPT-NEXT: je .LBB5_3 -; NOOPT-NEXT: jmp .LBB5_7 -; NOOPT-NEXT: .LBB5_7: # %entry +; NOOPT-NEXT: je .LBB5_11 +; NOOPT-NEXT: jmp .LBB5_3 +; NOOPT-NEXT: .LBB5_3: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $3, %eax -; NOOPT-NEXT: je .LBB5_1 -; NOOPT-NEXT: jmp .LBB5_8 -; NOOPT-NEXT: .LBB5_8: # %entry +; NOOPT-NEXT: je .LBB5_9 +; NOOPT-NEXT: jmp .LBB5_4 +; NOOPT-NEXT: .LBB5_4: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $4, %eax -; NOOPT-NEXT: je .LBB5_2 -; NOOPT-NEXT: jmp .LBB5_9 -; NOOPT-NEXT: .LBB5_9: # %entry +; NOOPT-NEXT: je .LBB5_10 +; NOOPT-NEXT: jmp .LBB5_5 +; NOOPT-NEXT: .LBB5_5: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $5, %eax -; NOOPT-NEXT: je .LBB5_3 -; NOOPT-NEXT: jmp .LBB5_10 -; NOOPT-NEXT: .LBB5_10: # %entry +; NOOPT-NEXT: je .LBB5_11 +; NOOPT-NEXT: jmp .LBB5_6 +; NOOPT-NEXT: .LBB5_6: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $6, %eax -; NOOPT-NEXT: je .LBB5_1 -; NOOPT-NEXT: jmp .LBB5_11 -; NOOPT-NEXT: .LBB5_11: # %entry +; NOOPT-NEXT: je .LBB5_9 +; NOOPT-NEXT: jmp .LBB5_7 +; NOOPT-NEXT: .LBB5_7: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $7, %eax -; NOOPT-NEXT: je .LBB5_2 -; NOOPT-NEXT: jmp .LBB5_12 -; NOOPT-NEXT: .LBB5_12: # %entry +; NOOPT-NEXT: je .LBB5_10 +; NOOPT-NEXT: jmp .LBB5_8 +; NOOPT-NEXT: .LBB5_8: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $8, %eax -; NOOPT-NEXT: je .LBB5_3 -; NOOPT-NEXT: jmp .LBB5_4 -; NOOPT-NEXT: .LBB5_1: # %bb0 +; NOOPT-NEXT: je .LBB5_11 +; NOOPT-NEXT: jmp .LBB5_12 +; NOOPT-NEXT: .LBB5_9: # %bb0 ; NOOPT-NEXT: xorl %edi, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB5_4 -; NOOPT-NEXT: .LBB5_2: # %bb1 +; NOOPT-NEXT: jmp .LBB5_12 +; NOOPT-NEXT: .LBB5_10: # %bb1 ; NOOPT-NEXT: movl $1, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB5_4 -; NOOPT-NEXT: .LBB5_3: # %bb2 +; NOOPT-NEXT: jmp .LBB5_12 +; NOOPT-NEXT: .LBB5_11: # %bb2 ; NOOPT-NEXT: movl $2, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: .LBB5_4: # %return +; NOOPT-NEXT: .LBB5_12: # %return ; NOOPT-NEXT: popq %rax ; NOOPT-NEXT: .cfi_def_cfa_offset 8 ; NOOPT-NEXT: retq @@ -475,22 +475,22 @@ define void @bt_is_better2(i32 %x) { ; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: movl $73, %eax ; CHECK-NEXT: btl %edi, %eax -; CHECK-NEXT: jb .LBB6_5 +; CHECK-NEXT: jb .LBB6_4 ; CHECK-NEXT: # %bb.2: # %entry ; CHECK-NEXT: movl $146, %eax ; CHECK-NEXT: btl %edi, %eax -; CHECK-NEXT: jae .LBB6_3 -; CHECK-NEXT: # %bb.6: # %bb1 +; CHECK-NEXT: jae .LBB6_5 +; CHECK-NEXT: # %bb.3: # %bb1 ; CHECK-NEXT: movl $1, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB6_5: # %bb0 +; CHECK-NEXT: .LBB6_4: # %bb0 ; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB6_3: # %entry +; CHECK-NEXT: .LBB6_5: # %entry ; CHECK-NEXT: movl $260, %eax # imm = 0x104 ; CHECK-NEXT: btl %edi, %eax ; CHECK-NEXT: jae .LBB6_7 -; CHECK-NEXT: # %bb.4: # %bb2 +; CHECK-NEXT: # %bb.6: # %bb2 ; CHECK-NEXT: movl $2, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL ; CHECK-NEXT: .LBB6_7: # %return @@ -502,55 +502,55 @@ define void @bt_is_better2(i32 %x) { ; NOOPT-NEXT: .cfi_def_cfa_offset 16 ; NOOPT-NEXT: movl %edi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill ; NOOPT-NEXT: testl %edi, %edi -; NOOPT-NEXT: je .LBB6_1 -; NOOPT-NEXT: jmp .LBB6_5 -; NOOPT-NEXT: .LBB6_5: # %entry +; NOOPT-NEXT: je .LBB6_8 +; NOOPT-NEXT: jmp .LBB6_1 +; NOOPT-NEXT: .LBB6_1: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $1, %eax -; NOOPT-NEXT: je .LBB6_2 -; NOOPT-NEXT: jmp .LBB6_6 -; NOOPT-NEXT: .LBB6_6: # %entry +; NOOPT-NEXT: je .LBB6_9 +; NOOPT-NEXT: jmp .LBB6_2 +; NOOPT-NEXT: .LBB6_2: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $2, %eax -; NOOPT-NEXT: je .LBB6_3 -; NOOPT-NEXT: jmp .LBB6_7 -; NOOPT-NEXT: .LBB6_7: # %entry +; NOOPT-NEXT: je .LBB6_10 +; NOOPT-NEXT: jmp .LBB6_3 +; NOOPT-NEXT: .LBB6_3: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $3, %eax -; NOOPT-NEXT: je .LBB6_1 -; NOOPT-NEXT: jmp .LBB6_8 -; NOOPT-NEXT: .LBB6_8: # %entry +; NOOPT-NEXT: je .LBB6_8 +; NOOPT-NEXT: jmp .LBB6_4 +; NOOPT-NEXT: .LBB6_4: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $4, %eax -; NOOPT-NEXT: je .LBB6_2 -; NOOPT-NEXT: jmp .LBB6_9 -; NOOPT-NEXT: .LBB6_9: # %entry +; NOOPT-NEXT: je .LBB6_9 +; NOOPT-NEXT: jmp .LBB6_5 +; NOOPT-NEXT: .LBB6_5: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $6, %eax -; NOOPT-NEXT: je .LBB6_1 -; NOOPT-NEXT: jmp .LBB6_10 -; NOOPT-NEXT: .LBB6_10: # %entry +; NOOPT-NEXT: je .LBB6_8 +; NOOPT-NEXT: jmp .LBB6_6 +; NOOPT-NEXT: .LBB6_6: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $7, %eax -; NOOPT-NEXT: je .LBB6_2 -; NOOPT-NEXT: jmp .LBB6_11 -; NOOPT-NEXT: .LBB6_11: # %entry +; NOOPT-NEXT: je .LBB6_9 +; NOOPT-NEXT: jmp .LBB6_7 +; NOOPT-NEXT: .LBB6_7: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $8, %eax -; NOOPT-NEXT: je .LBB6_3 -; NOOPT-NEXT: jmp .LBB6_4 -; NOOPT-NEXT: .LBB6_1: # %bb0 +; NOOPT-NEXT: je .LBB6_10 +; NOOPT-NEXT: jmp .LBB6_11 +; NOOPT-NEXT: .LBB6_8: # %bb0 ; NOOPT-NEXT: xorl %edi, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB6_4 -; NOOPT-NEXT: .LBB6_2: # %bb1 +; NOOPT-NEXT: jmp .LBB6_11 +; NOOPT-NEXT: .LBB6_9: # %bb1 ; NOOPT-NEXT: movl $1, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB6_4 -; NOOPT-NEXT: .LBB6_3: # %bb2 +; NOOPT-NEXT: jmp .LBB6_11 +; NOOPT-NEXT: .LBB6_10: # %bb2 ; NOOPT-NEXT: movl $2, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: .LBB6_4: # %return +; NOOPT-NEXT: .LBB6_11: # %return ; NOOPT-NEXT: popq %rax ; NOOPT-NEXT: .cfi_def_cfa_offset 8 ; NOOPT-NEXT: retq @@ -579,22 +579,22 @@ define void @bt_is_better3(i32 %x) { ; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: movl $74752, %eax # imm = 0x12400 ; CHECK-NEXT: btl %edi, %eax -; CHECK-NEXT: jb .LBB7_5 +; CHECK-NEXT: jb .LBB7_4 ; CHECK-NEXT: # %bb.2: # %entry ; CHECK-NEXT: movl $149504, %eax # imm = 0x24800 ; CHECK-NEXT: btl %edi, %eax -; CHECK-NEXT: jae .LBB7_3 -; CHECK-NEXT: # %bb.6: # %bb1 +; CHECK-NEXT: jae .LBB7_5 +; CHECK-NEXT: # %bb.3: # %bb1 ; CHECK-NEXT: movl $1, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB7_5: # %bb0 +; CHECK-NEXT: .LBB7_4: # %bb0 ; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB7_3: # %entry +; CHECK-NEXT: .LBB7_5: # %entry ; CHECK-NEXT: movl $266240, %eax # imm = 0x41000 ; CHECK-NEXT: btl %edi, %eax ; CHECK-NEXT: jae .LBB7_7 -; CHECK-NEXT: # %bb.4: # %bb2 +; CHECK-NEXT: # %bb.6: # %bb2 ; CHECK-NEXT: movl $2, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL ; CHECK-NEXT: .LBB7_7: # %return @@ -606,55 +606,55 @@ define void @bt_is_better3(i32 %x) { ; NOOPT-NEXT: .cfi_def_cfa_offset 16 ; NOOPT-NEXT: movl %edi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill ; NOOPT-NEXT: subl $10, %edi -; NOOPT-NEXT: je .LBB7_1 -; NOOPT-NEXT: jmp .LBB7_5 -; NOOPT-NEXT: .LBB7_5: # %entry +; NOOPT-NEXT: je .LBB7_8 +; NOOPT-NEXT: jmp .LBB7_1 +; NOOPT-NEXT: .LBB7_1: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $11, %eax -; NOOPT-NEXT: je .LBB7_2 -; NOOPT-NEXT: jmp .LBB7_6 -; NOOPT-NEXT: .LBB7_6: # %entry +; NOOPT-NEXT: je .LBB7_9 +; NOOPT-NEXT: jmp .LBB7_2 +; NOOPT-NEXT: .LBB7_2: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $12, %eax -; NOOPT-NEXT: je .LBB7_3 -; NOOPT-NEXT: jmp .LBB7_7 -; NOOPT-NEXT: .LBB7_7: # %entry +; NOOPT-NEXT: je .LBB7_10 +; NOOPT-NEXT: jmp .LBB7_3 +; NOOPT-NEXT: .LBB7_3: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $13, %eax -; NOOPT-NEXT: je .LBB7_1 -; NOOPT-NEXT: jmp .LBB7_8 -; NOOPT-NEXT: .LBB7_8: # %entry +; NOOPT-NEXT: je .LBB7_8 +; NOOPT-NEXT: jmp .LBB7_4 +; NOOPT-NEXT: .LBB7_4: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $14, %eax -; NOOPT-NEXT: je .LBB7_2 -; NOOPT-NEXT: jmp .LBB7_9 -; NOOPT-NEXT: .LBB7_9: # %entry +; NOOPT-NEXT: je .LBB7_9 +; NOOPT-NEXT: jmp .LBB7_5 +; NOOPT-NEXT: .LBB7_5: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $16, %eax -; NOOPT-NEXT: je .LBB7_1 -; NOOPT-NEXT: jmp .LBB7_10 -; NOOPT-NEXT: .LBB7_10: # %entry +; NOOPT-NEXT: je .LBB7_8 +; NOOPT-NEXT: jmp .LBB7_6 +; NOOPT-NEXT: .LBB7_6: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $17, %eax -; NOOPT-NEXT: je .LBB7_2 -; NOOPT-NEXT: jmp .LBB7_11 -; NOOPT-NEXT: .LBB7_11: # %entry +; NOOPT-NEXT: je .LBB7_9 +; NOOPT-NEXT: jmp .LBB7_7 +; NOOPT-NEXT: .LBB7_7: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $18, %eax -; NOOPT-NEXT: je .LBB7_3 -; NOOPT-NEXT: jmp .LBB7_4 -; NOOPT-NEXT: .LBB7_1: # %bb0 +; NOOPT-NEXT: je .LBB7_10 +; NOOPT-NEXT: jmp .LBB7_11 +; NOOPT-NEXT: .LBB7_8: # %bb0 ; NOOPT-NEXT: xorl %edi, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB7_4 -; NOOPT-NEXT: .LBB7_2: # %bb1 +; NOOPT-NEXT: jmp .LBB7_11 +; NOOPT-NEXT: .LBB7_9: # %bb1 ; NOOPT-NEXT: movl $1, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB7_4 -; NOOPT-NEXT: .LBB7_3: # %bb2 +; NOOPT-NEXT: jmp .LBB7_11 +; NOOPT-NEXT: .LBB7_10: # %bb2 ; NOOPT-NEXT: movl $2, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: .LBB7_4: # %return +; NOOPT-NEXT: .LBB7_11: # %return ; NOOPT-NEXT: popq %rax ; NOOPT-NEXT: .cfi_def_cfa_offset 8 ; NOOPT-NEXT: retq @@ -723,41 +723,41 @@ define void @optimal_pivot1(i32 %x) { ; NOOPT-NEXT: .cfi_def_cfa_offset 16 ; NOOPT-NEXT: movl %edi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill ; NOOPT-NEXT: subl $100, %edi -; NOOPT-NEXT: je .LBB8_1 -; NOOPT-NEXT: jmp .LBB8_4 -; NOOPT-NEXT: .LBB8_4: # %entry +; NOOPT-NEXT: je .LBB8_6 +; NOOPT-NEXT: jmp .LBB8_1 +; NOOPT-NEXT: .LBB8_1: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $200, %eax -; NOOPT-NEXT: je .LBB8_2 -; NOOPT-NEXT: jmp .LBB8_5 -; NOOPT-NEXT: .LBB8_5: # %entry +; NOOPT-NEXT: je .LBB8_7 +; NOOPT-NEXT: jmp .LBB8_2 +; NOOPT-NEXT: .LBB8_2: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $300, %eax # imm = 0x12C -; NOOPT-NEXT: je .LBB8_1 -; NOOPT-NEXT: jmp .LBB8_6 -; NOOPT-NEXT: .LBB8_6: # %entry +; NOOPT-NEXT: je .LBB8_6 +; NOOPT-NEXT: jmp .LBB8_3 +; NOOPT-NEXT: .LBB8_3: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $400, %eax # imm = 0x190 -; NOOPT-NEXT: je .LBB8_2 -; NOOPT-NEXT: jmp .LBB8_7 -; NOOPT-NEXT: .LBB8_7: # %entry +; NOOPT-NEXT: je .LBB8_7 +; NOOPT-NEXT: jmp .LBB8_4 +; NOOPT-NEXT: .LBB8_4: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $500, %eax # imm = 0x1F4 -; NOOPT-NEXT: je .LBB8_1 -; NOOPT-NEXT: jmp .LBB8_8 -; NOOPT-NEXT: .LBB8_8: # %entry +; NOOPT-NEXT: je .LBB8_6 +; NOOPT-NEXT: jmp .LBB8_5 +; NOOPT-NEXT: .LBB8_5: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $600, %eax # imm = 0x258 -; NOOPT-NEXT: je .LBB8_2 -; NOOPT-NEXT: jmp .LBB8_3 -; NOOPT-NEXT: .LBB8_1: # %bb0 +; NOOPT-NEXT: je .LBB8_7 +; NOOPT-NEXT: jmp .LBB8_8 +; NOOPT-NEXT: .LBB8_6: # %bb0 ; NOOPT-NEXT: xorl %edi, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB8_3 -; NOOPT-NEXT: .LBB8_2: # %bb1 +; NOOPT-NEXT: jmp .LBB8_8 +; NOOPT-NEXT: .LBB8_7: # %bb1 ; NOOPT-NEXT: movl $1, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: .LBB8_3: # %return +; NOOPT-NEXT: .LBB8_8: # %return ; NOOPT-NEXT: popq %rax ; NOOPT-NEXT: .cfi_def_cfa_offset 8 ; NOOPT-NEXT: retq @@ -787,40 +787,40 @@ define void @optimal_pivot2(i32 %x) { ; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: leal -100(%rdi), %eax ; CHECK-NEXT: cmpl $3, %eax -; CHECK-NEXT: jbe .LBB9_12 +; CHECK-NEXT: jbe .LBB9_7 ; CHECK-NEXT: # %bb.2: # %entry ; CHECK-NEXT: addl $-200, %edi ; CHECK-NEXT: cmpl $3, %edi -; CHECK-NEXT: ja .LBB9_11 +; CHECK-NEXT: ja .LBB9_13 ; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: jmpq *.LJTI9_1(,%rdi,8) ; CHECK-NEXT: .LBB9_4: # %entry ; CHECK-NEXT: leal -300(%rdi), %eax ; CHECK-NEXT: cmpl $3, %eax -; CHECK-NEXT: jbe .LBB9_13 +; CHECK-NEXT: jbe .LBB9_8 ; CHECK-NEXT: # %bb.5: # %entry ; CHECK-NEXT: addl $-400, %edi # imm = 0xFE70 ; CHECK-NEXT: cmpl $3, %edi -; CHECK-NEXT: ja .LBB9_11 +; CHECK-NEXT: ja .LBB9_13 ; CHECK-NEXT: # %bb.6: # %entry ; CHECK-NEXT: jmpq *.LJTI9_3(,%rdi,8) -; CHECK-NEXT: .LBB9_12: # %entry +; CHECK-NEXT: .LBB9_7: # %entry ; CHECK-NEXT: jmpq *.LJTI9_0(,%rax,8) -; CHECK-NEXT: .LBB9_13: # %entry +; CHECK-NEXT: .LBB9_8: # %entry ; CHECK-NEXT: jmpq *.LJTI9_2(,%rax,8) -; CHECK-NEXT: .LBB9_7: # %bb0 +; CHECK-NEXT: .LBB9_9: # %bb0 ; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB9_9: # %bb2 +; CHECK-NEXT: .LBB9_10: # %bb2 ; CHECK-NEXT: movl $2, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB9_10: # %bb3 +; CHECK-NEXT: .LBB9_11: # %bb3 ; CHECK-NEXT: movl $3, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB9_8: # %bb1 +; CHECK-NEXT: .LBB9_12: # %bb1 ; CHECK-NEXT: movl $1, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB9_11: # %return +; CHECK-NEXT: .LBB9_13: # %return ; CHECK-NEXT: retq ; ; NOOPT-LABEL: optimal_pivot2: @@ -829,99 +829,99 @@ define void @optimal_pivot2(i32 %x) { ; NOOPT-NEXT: .cfi_def_cfa_offset 16 ; NOOPT-NEXT: movl %edi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill ; NOOPT-NEXT: subl $100, %edi -; NOOPT-NEXT: je .LBB9_1 +; NOOPT-NEXT: je .LBB9_16 +; NOOPT-NEXT: jmp .LBB9_1 +; NOOPT-NEXT: .LBB9_1: # %entry +; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; NOOPT-NEXT: subl $101, %eax +; NOOPT-NEXT: je .LBB9_17 +; NOOPT-NEXT: jmp .LBB9_2 +; NOOPT-NEXT: .LBB9_2: # %entry +; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; NOOPT-NEXT: subl $102, %eax +; NOOPT-NEXT: je .LBB9_18 +; NOOPT-NEXT: jmp .LBB9_3 +; NOOPT-NEXT: .LBB9_3: # %entry +; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; NOOPT-NEXT: subl $103, %eax +; NOOPT-NEXT: je .LBB9_19 +; NOOPT-NEXT: jmp .LBB9_4 +; NOOPT-NEXT: .LBB9_4: # %entry +; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; NOOPT-NEXT: subl $200, %eax +; NOOPT-NEXT: je .LBB9_16 +; NOOPT-NEXT: jmp .LBB9_5 +; NOOPT-NEXT: .LBB9_5: # %entry +; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload +; NOOPT-NEXT: subl $201, %eax +; NOOPT-NEXT: je .LBB9_17 ; NOOPT-NEXT: jmp .LBB9_6 ; NOOPT-NEXT: .LBB9_6: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload -; NOOPT-NEXT: subl $101, %eax -; NOOPT-NEXT: je .LBB9_2 +; NOOPT-NEXT: subl $202, %eax +; NOOPT-NEXT: je .LBB9_18 ; NOOPT-NEXT: jmp .LBB9_7 ; NOOPT-NEXT: .LBB9_7: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload -; NOOPT-NEXT: subl $102, %eax -; NOOPT-NEXT: je .LBB9_3 +; NOOPT-NEXT: subl $203, %eax +; NOOPT-NEXT: je .LBB9_19 ; NOOPT-NEXT: jmp .LBB9_8 ; NOOPT-NEXT: .LBB9_8: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload -; NOOPT-NEXT: subl $103, %eax -; NOOPT-NEXT: je .LBB9_4 +; NOOPT-NEXT: subl $300, %eax # imm = 0x12C +; NOOPT-NEXT: je .LBB9_16 ; NOOPT-NEXT: jmp .LBB9_9 ; NOOPT-NEXT: .LBB9_9: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload -; NOOPT-NEXT: subl $200, %eax -; NOOPT-NEXT: je .LBB9_1 +; NOOPT-NEXT: subl $301, %eax # imm = 0x12D +; NOOPT-NEXT: je .LBB9_17 ; NOOPT-NEXT: jmp .LBB9_10 ; NOOPT-NEXT: .LBB9_10: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload -; NOOPT-NEXT: subl $201, %eax -; NOOPT-NEXT: je .LBB9_2 +; NOOPT-NEXT: subl $302, %eax # imm = 0x12E +; NOOPT-NEXT: je .LBB9_18 ; NOOPT-NEXT: jmp .LBB9_11 ; NOOPT-NEXT: .LBB9_11: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload -; NOOPT-NEXT: subl $202, %eax -; NOOPT-NEXT: je .LBB9_3 +; NOOPT-NEXT: subl $303, %eax # imm = 0x12F +; NOOPT-NEXT: je .LBB9_19 ; NOOPT-NEXT: jmp .LBB9_12 ; NOOPT-NEXT: .LBB9_12: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload -; NOOPT-NEXT: subl $203, %eax -; NOOPT-NEXT: je .LBB9_4 +; NOOPT-NEXT: subl $400, %eax # imm = 0x190 +; NOOPT-NEXT: je .LBB9_16 ; NOOPT-NEXT: jmp .LBB9_13 ; NOOPT-NEXT: .LBB9_13: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload -; NOOPT-NEXT: subl $300, %eax # imm = 0x12C -; NOOPT-NEXT: je .LBB9_1 +; NOOPT-NEXT: subl $401, %eax # imm = 0x191 +; NOOPT-NEXT: je .LBB9_17 ; NOOPT-NEXT: jmp .LBB9_14 ; NOOPT-NEXT: .LBB9_14: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload -; NOOPT-NEXT: subl $301, %eax # imm = 0x12D -; NOOPT-NEXT: je .LBB9_2 +; NOOPT-NEXT: subl $402, %eax # imm = 0x192 +; NOOPT-NEXT: je .LBB9_18 ; NOOPT-NEXT: jmp .LBB9_15 ; NOOPT-NEXT: .LBB9_15: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload -; NOOPT-NEXT: subl $302, %eax # imm = 0x12E -; NOOPT-NEXT: je .LBB9_3 -; NOOPT-NEXT: jmp .LBB9_16 -; NOOPT-NEXT: .LBB9_16: # %entry -; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload -; NOOPT-NEXT: subl $303, %eax # imm = 0x12F -; NOOPT-NEXT: je .LBB9_4 -; NOOPT-NEXT: jmp .LBB9_17 -; NOOPT-NEXT: .LBB9_17: # %entry -; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload -; NOOPT-NEXT: subl $400, %eax # imm = 0x190 -; NOOPT-NEXT: je .LBB9_1 -; NOOPT-NEXT: jmp .LBB9_18 -; NOOPT-NEXT: .LBB9_18: # %entry -; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload -; NOOPT-NEXT: subl $401, %eax # imm = 0x191 -; NOOPT-NEXT: je .LBB9_2 -; NOOPT-NEXT: jmp .LBB9_19 -; NOOPT-NEXT: .LBB9_19: # %entry -; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload -; NOOPT-NEXT: subl $402, %eax # imm = 0x192 -; NOOPT-NEXT: je .LBB9_3 -; NOOPT-NEXT: jmp .LBB9_20 -; NOOPT-NEXT: .LBB9_20: # %entry -; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $403, %eax # imm = 0x193 -; NOOPT-NEXT: je .LBB9_4 -; NOOPT-NEXT: jmp .LBB9_5 -; NOOPT-NEXT: .LBB9_1: # %bb0 +; NOOPT-NEXT: je .LBB9_19 +; NOOPT-NEXT: jmp .LBB9_20 +; NOOPT-NEXT: .LBB9_16: # %bb0 ; NOOPT-NEXT: xorl %edi, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB9_5 -; NOOPT-NEXT: .LBB9_2: # %bb1 +; NOOPT-NEXT: jmp .LBB9_20 +; NOOPT-NEXT: .LBB9_17: # %bb1 ; NOOPT-NEXT: movl $1, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB9_5 -; NOOPT-NEXT: .LBB9_3: # %bb2 +; NOOPT-NEXT: jmp .LBB9_20 +; NOOPT-NEXT: .LBB9_18: # %bb2 ; NOOPT-NEXT: movl $2, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB9_5 -; NOOPT-NEXT: .LBB9_4: # %bb3 +; NOOPT-NEXT: jmp .LBB9_20 +; NOOPT-NEXT: .LBB9_19: # %bb3 ; NOOPT-NEXT: movl $3, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: .LBB9_5: # %return +; NOOPT-NEXT: .LBB9_20: # %return ; NOOPT-NEXT: popq %rax ; NOOPT-NEXT: .cfi_def_cfa_offset 8 ; NOOPT-NEXT: retq @@ -950,30 +950,30 @@ define void @optimal_jump_table1(i32 %x) { ; CHECK-NEXT: # kill: def $edi killed $edi def $rdi ; CHECK-NEXT: leal -5(%rdi), %eax ; CHECK-NEXT: cmpl $10, %eax -; CHECK-NEXT: ja .LBB10_1 -; CHECK-NEXT: # %bb.9: # %entry +; CHECK-NEXT: ja .LBB10_3 +; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: jmpq *.LJTI10_0(,%rax,8) -; CHECK-NEXT: .LBB10_3: # %bb1 +; CHECK-NEXT: .LBB10_2: # %bb1 ; CHECK-NEXT: movl $1, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB10_1: # %entry +; CHECK-NEXT: .LBB10_3: # %entry ; CHECK-NEXT: testl %edi, %edi -; CHECK-NEXT: jne .LBB10_8 -; CHECK-NEXT: # %bb.2: # %bb0 +; CHECK-NEXT: jne .LBB10_5 +; CHECK-NEXT: # %bb.4: # %bb0 ; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB10_8: # %return +; CHECK-NEXT: .LBB10_5: # %return ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB10_7: # %bb5 +; CHECK-NEXT: .LBB10_6: # %bb5 ; CHECK-NEXT: movl $5, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB10_5: # %bb3 +; CHECK-NEXT: .LBB10_7: # %bb3 ; CHECK-NEXT: movl $3, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB10_4: # %bb2 +; CHECK-NEXT: .LBB10_8: # %bb2 ; CHECK-NEXT: movl $2, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB10_6: # %bb4 +; CHECK-NEXT: .LBB10_9: # %bb4 ; CHECK-NEXT: movl $4, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL ; @@ -983,57 +983,57 @@ define void @optimal_jump_table1(i32 %x) { ; NOOPT-NEXT: .cfi_def_cfa_offset 16 ; NOOPT-NEXT: movl %edi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill ; NOOPT-NEXT: testl %edi, %edi -; NOOPT-NEXT: je .LBB10_1 -; NOOPT-NEXT: jmp .LBB10_8 -; NOOPT-NEXT: .LBB10_8: # %entry +; NOOPT-NEXT: je .LBB10_6 +; NOOPT-NEXT: jmp .LBB10_1 +; NOOPT-NEXT: .LBB10_1: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $5, %eax -; NOOPT-NEXT: je .LBB10_2 -; NOOPT-NEXT: jmp .LBB10_9 -; NOOPT-NEXT: .LBB10_9: # %entry +; NOOPT-NEXT: je .LBB10_7 +; NOOPT-NEXT: jmp .LBB10_2 +; NOOPT-NEXT: .LBB10_2: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $6, %eax -; NOOPT-NEXT: je .LBB10_3 -; NOOPT-NEXT: jmp .LBB10_10 -; NOOPT-NEXT: .LBB10_10: # %entry +; NOOPT-NEXT: je .LBB10_8 +; NOOPT-NEXT: jmp .LBB10_3 +; NOOPT-NEXT: .LBB10_3: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $12, %eax -; NOOPT-NEXT: je .LBB10_4 -; NOOPT-NEXT: jmp .LBB10_11 -; NOOPT-NEXT: .LBB10_11: # %entry +; NOOPT-NEXT: je .LBB10_9 +; NOOPT-NEXT: jmp .LBB10_4 +; NOOPT-NEXT: .LBB10_4: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $13, %eax -; NOOPT-NEXT: je .LBB10_5 -; NOOPT-NEXT: jmp .LBB10_12 -; NOOPT-NEXT: .LBB10_12: # %entry +; NOOPT-NEXT: je .LBB10_10 +; NOOPT-NEXT: jmp .LBB10_5 +; NOOPT-NEXT: .LBB10_5: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $15, %eax -; NOOPT-NEXT: je .LBB10_6 -; NOOPT-NEXT: jmp .LBB10_7 -; NOOPT-NEXT: .LBB10_1: # %bb0 +; NOOPT-NEXT: je .LBB10_11 +; NOOPT-NEXT: jmp .LBB10_12 +; NOOPT-NEXT: .LBB10_6: # %bb0 ; NOOPT-NEXT: xorl %edi, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB10_7 -; NOOPT-NEXT: .LBB10_2: # %bb1 +; NOOPT-NEXT: jmp .LBB10_12 +; NOOPT-NEXT: .LBB10_7: # %bb1 ; NOOPT-NEXT: movl $1, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB10_7 -; NOOPT-NEXT: .LBB10_3: # %bb2 +; NOOPT-NEXT: jmp .LBB10_12 +; NOOPT-NEXT: .LBB10_8: # %bb2 ; NOOPT-NEXT: movl $2, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB10_7 -; NOOPT-NEXT: .LBB10_4: # %bb3 +; NOOPT-NEXT: jmp .LBB10_12 +; NOOPT-NEXT: .LBB10_9: # %bb3 ; NOOPT-NEXT: movl $3, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB10_7 -; NOOPT-NEXT: .LBB10_5: # %bb4 +; NOOPT-NEXT: jmp .LBB10_12 +; NOOPT-NEXT: .LBB10_10: # %bb4 ; NOOPT-NEXT: movl $4, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB10_7 -; NOOPT-NEXT: .LBB10_6: # %bb5 +; NOOPT-NEXT: jmp .LBB10_12 +; NOOPT-NEXT: .LBB10_11: # %bb5 ; NOOPT-NEXT: movl $5, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: .LBB10_7: # %return +; NOOPT-NEXT: .LBB10_12: # %return ; NOOPT-NEXT: popq %rax ; NOOPT-NEXT: .cfi_def_cfa_offset 8 ; NOOPT-NEXT: retq @@ -1063,34 +1063,34 @@ define void @optimal_jump_table2(i32 %x) { ; CHECK-LABEL: optimal_jump_table2: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cmpl $9, %edi -; CHECK-NEXT: ja .LBB11_1 -; CHECK-NEXT: # %bb.10: # %entry +; CHECK-NEXT: ja .LBB11_3 +; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: jmpq *.LJTI11_0(,%rax,8) -; CHECK-NEXT: .LBB11_4: # %bb0 +; CHECK-NEXT: .LBB11_2: # %bb0 ; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB11_1: # %entry +; CHECK-NEXT: .LBB11_3: # %entry ; CHECK-NEXT: cmpl $14, %edi -; CHECK-NEXT: je .LBB11_8 -; CHECK-NEXT: # %bb.2: # %entry +; CHECK-NEXT: je .LBB11_10 +; CHECK-NEXT: # %bb.4: # %entry ; CHECK-NEXT: cmpl $15, %edi -; CHECK-NEXT: jne .LBB11_9 -; CHECK-NEXT: # %bb.3: # %bb5 +; CHECK-NEXT: jne .LBB11_6 +; CHECK-NEXT: # %bb.5: # %bb5 ; CHECK-NEXT: movl $5, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB11_9: # %return +; CHECK-NEXT: .LBB11_6: # %return ; CHECK-NEXT: retq ; CHECK-NEXT: .LBB11_7: # %bb3 ; CHECK-NEXT: movl $3, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB11_5: # %bb1 +; CHECK-NEXT: .LBB11_8: # %bb1 ; CHECK-NEXT: movl $1, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB11_6: # %bb2 +; CHECK-NEXT: .LBB11_9: # %bb2 ; CHECK-NEXT: movl $2, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB11_8: # %bb4 +; CHECK-NEXT: .LBB11_10: # %bb4 ; CHECK-NEXT: movl $4, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL ; @@ -1100,57 +1100,57 @@ define void @optimal_jump_table2(i32 %x) { ; NOOPT-NEXT: .cfi_def_cfa_offset 16 ; NOOPT-NEXT: movl %edi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill ; NOOPT-NEXT: testl %edi, %edi -; NOOPT-NEXT: je .LBB11_1 -; NOOPT-NEXT: jmp .LBB11_8 -; NOOPT-NEXT: .LBB11_8: # %entry +; NOOPT-NEXT: je .LBB11_6 +; NOOPT-NEXT: jmp .LBB11_1 +; NOOPT-NEXT: .LBB11_1: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $1, %eax -; NOOPT-NEXT: je .LBB11_2 -; NOOPT-NEXT: jmp .LBB11_9 -; NOOPT-NEXT: .LBB11_9: # %entry +; NOOPT-NEXT: je .LBB11_7 +; NOOPT-NEXT: jmp .LBB11_2 +; NOOPT-NEXT: .LBB11_2: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $2, %eax -; NOOPT-NEXT: je .LBB11_3 -; NOOPT-NEXT: jmp .LBB11_10 -; NOOPT-NEXT: .LBB11_10: # %entry +; NOOPT-NEXT: je .LBB11_8 +; NOOPT-NEXT: jmp .LBB11_3 +; NOOPT-NEXT: .LBB11_3: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $9, %eax -; NOOPT-NEXT: je .LBB11_4 -; NOOPT-NEXT: jmp .LBB11_11 -; NOOPT-NEXT: .LBB11_11: # %entry +; NOOPT-NEXT: je .LBB11_9 +; NOOPT-NEXT: jmp .LBB11_4 +; NOOPT-NEXT: .LBB11_4: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $14, %eax -; NOOPT-NEXT: je .LBB11_5 -; NOOPT-NEXT: jmp .LBB11_12 -; NOOPT-NEXT: .LBB11_12: # %entry +; NOOPT-NEXT: je .LBB11_10 +; NOOPT-NEXT: jmp .LBB11_5 +; NOOPT-NEXT: .LBB11_5: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $15, %eax -; NOOPT-NEXT: je .LBB11_6 -; NOOPT-NEXT: jmp .LBB11_7 -; NOOPT-NEXT: .LBB11_1: # %bb0 +; NOOPT-NEXT: je .LBB11_11 +; NOOPT-NEXT: jmp .LBB11_12 +; NOOPT-NEXT: .LBB11_6: # %bb0 ; NOOPT-NEXT: xorl %edi, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB11_7 -; NOOPT-NEXT: .LBB11_2: # %bb1 +; NOOPT-NEXT: jmp .LBB11_12 +; NOOPT-NEXT: .LBB11_7: # %bb1 ; NOOPT-NEXT: movl $1, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB11_7 -; NOOPT-NEXT: .LBB11_3: # %bb2 +; NOOPT-NEXT: jmp .LBB11_12 +; NOOPT-NEXT: .LBB11_8: # %bb2 ; NOOPT-NEXT: movl $2, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB11_7 -; NOOPT-NEXT: .LBB11_4: # %bb3 +; NOOPT-NEXT: jmp .LBB11_12 +; NOOPT-NEXT: .LBB11_9: # %bb3 ; NOOPT-NEXT: movl $3, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB11_7 -; NOOPT-NEXT: .LBB11_5: # %bb4 +; NOOPT-NEXT: jmp .LBB11_12 +; NOOPT-NEXT: .LBB11_10: # %bb4 ; NOOPT-NEXT: movl $4, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB11_7 -; NOOPT-NEXT: .LBB11_6: # %bb5 +; NOOPT-NEXT: jmp .LBB11_12 +; NOOPT-NEXT: .LBB11_11: # %bb5 ; NOOPT-NEXT: movl $5, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: .LBB11_7: # %return +; NOOPT-NEXT: .LBB11_12: # %return ; NOOPT-NEXT: popq %rax ; NOOPT-NEXT: .cfi_def_cfa_offset 8 ; NOOPT-NEXT: retq @@ -1182,25 +1182,25 @@ define void @optimal_jump_table3(i32 %x) { ; CHECK-NEXT: # kill: def $edi killed $edi def $rdi ; CHECK-NEXT: leal -1(%rdi), %eax ; CHECK-NEXT: cmpl $19, %eax -; CHECK-NEXT: ja .LBB12_1 -; CHECK-NEXT: # %bb.3: # %entry +; CHECK-NEXT: ja .LBB12_6 +; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: jmpq *.LJTI12_0(,%rax,8) -; CHECK-NEXT: .LBB12_4: # %bb0 +; CHECK-NEXT: .LBB12_2: # %bb0 ; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB12_6: # %bb2 +; CHECK-NEXT: .LBB12_3: # %bb2 ; CHECK-NEXT: movl $2, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB12_5: # %bb1 +; CHECK-NEXT: .LBB12_4: # %bb1 ; CHECK-NEXT: movl $1, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB12_7: # %bb3 +; CHECK-NEXT: .LBB12_5: # %bb3 ; CHECK-NEXT: movl $3, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB12_1: # %entry +; CHECK-NEXT: .LBB12_6: # %entry ; CHECK-NEXT: cmpl $25, %edi ; CHECK-NEXT: jne .LBB12_8 -; CHECK-NEXT: # %bb.2: # %bb4 +; CHECK-NEXT: # %bb.7: # %bb4 ; CHECK-NEXT: movl $4, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL ; CHECK-NEXT: .LBB12_8: # %return @@ -1212,68 +1212,68 @@ define void @optimal_jump_table3(i32 %x) { ; NOOPT-NEXT: .cfi_def_cfa_offset 16 ; NOOPT-NEXT: movl %edi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill ; NOOPT-NEXT: subl $1, %edi -; NOOPT-NEXT: je .LBB12_1 -; NOOPT-NEXT: jmp .LBB12_7 -; NOOPT-NEXT: .LBB12_7: # %entry +; NOOPT-NEXT: je .LBB12_9 +; NOOPT-NEXT: jmp .LBB12_1 +; NOOPT-NEXT: .LBB12_1: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $2, %eax -; NOOPT-NEXT: je .LBB12_2 -; NOOPT-NEXT: jmp .LBB12_8 -; NOOPT-NEXT: .LBB12_8: # %entry +; NOOPT-NEXT: je .LBB12_10 +; NOOPT-NEXT: jmp .LBB12_2 +; NOOPT-NEXT: .LBB12_2: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $3, %eax -; NOOPT-NEXT: je .LBB12_3 -; NOOPT-NEXT: jmp .LBB12_9 -; NOOPT-NEXT: .LBB12_9: # %entry +; NOOPT-NEXT: je .LBB12_11 +; NOOPT-NEXT: jmp .LBB12_3 +; NOOPT-NEXT: .LBB12_3: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $10, %eax -; NOOPT-NEXT: je .LBB12_4 -; NOOPT-NEXT: jmp .LBB12_10 -; NOOPT-NEXT: .LBB12_10: # %entry +; NOOPT-NEXT: je .LBB12_12 +; NOOPT-NEXT: jmp .LBB12_4 +; NOOPT-NEXT: .LBB12_4: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $13, %eax -; NOOPT-NEXT: je .LBB12_1 -; NOOPT-NEXT: jmp .LBB12_11 -; NOOPT-NEXT: .LBB12_11: # %entry +; NOOPT-NEXT: je .LBB12_9 +; NOOPT-NEXT: jmp .LBB12_5 +; NOOPT-NEXT: .LBB12_5: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $14, %eax -; NOOPT-NEXT: je .LBB12_2 -; NOOPT-NEXT: jmp .LBB12_12 -; NOOPT-NEXT: .LBB12_12: # %entry +; NOOPT-NEXT: je .LBB12_10 +; NOOPT-NEXT: jmp .LBB12_6 +; NOOPT-NEXT: .LBB12_6: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $15, %eax -; NOOPT-NEXT: je .LBB12_3 -; NOOPT-NEXT: jmp .LBB12_13 -; NOOPT-NEXT: .LBB12_13: # %entry +; NOOPT-NEXT: je .LBB12_11 +; NOOPT-NEXT: jmp .LBB12_7 +; NOOPT-NEXT: .LBB12_7: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $20, %eax -; NOOPT-NEXT: je .LBB12_4 -; NOOPT-NEXT: jmp .LBB12_14 -; NOOPT-NEXT: .LBB12_14: # %entry +; NOOPT-NEXT: je .LBB12_12 +; NOOPT-NEXT: jmp .LBB12_8 +; NOOPT-NEXT: .LBB12_8: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $25, %eax -; NOOPT-NEXT: je .LBB12_5 -; NOOPT-NEXT: jmp .LBB12_6 -; NOOPT-NEXT: .LBB12_1: # %bb0 +; NOOPT-NEXT: je .LBB12_13 +; NOOPT-NEXT: jmp .LBB12_14 +; NOOPT-NEXT: .LBB12_9: # %bb0 ; NOOPT-NEXT: xorl %edi, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB12_6 -; NOOPT-NEXT: .LBB12_2: # %bb1 +; NOOPT-NEXT: jmp .LBB12_14 +; NOOPT-NEXT: .LBB12_10: # %bb1 ; NOOPT-NEXT: movl $1, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB12_6 -; NOOPT-NEXT: .LBB12_3: # %bb2 +; NOOPT-NEXT: jmp .LBB12_14 +; NOOPT-NEXT: .LBB12_11: # %bb2 ; NOOPT-NEXT: movl $2, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB12_6 -; NOOPT-NEXT: .LBB12_4: # %bb3 +; NOOPT-NEXT: jmp .LBB12_14 +; NOOPT-NEXT: .LBB12_12: # %bb3 ; NOOPT-NEXT: movl $3, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB12_6 -; NOOPT-NEXT: .LBB12_5: # %bb4 +; NOOPT-NEXT: jmp .LBB12_14 +; NOOPT-NEXT: .LBB12_13: # %bb4 ; NOOPT-NEXT: movl $4, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: .LBB12_6: # %return +; NOOPT-NEXT: .LBB12_14: # %return ; NOOPT-NEXT: popq %rax ; NOOPT-NEXT: .cfi_def_cfa_offset 8 ; NOOPT-NEXT: retq @@ -1334,7 +1334,7 @@ define void @phi_node_trouble(ptr %s) { ; NOOPT-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload ; NOOPT-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; NOOPT-NEXT: cmpq $0, %rax -; NOOPT-NEXT: je .LBB13_3 +; NOOPT-NEXT: je .LBB13_6 ; NOOPT-NEXT: # %bb.2: # %loop ; NOOPT-NEXT: # in Loop: Header=BB13_1 Depth=1 ; NOOPT-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload @@ -1344,25 +1344,25 @@ define void @phi_node_trouble(ptr %s) { ; NOOPT-NEXT: subl $4, %ecx ; NOOPT-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; NOOPT-NEXT: je .LBB13_1 -; NOOPT-NEXT: jmp .LBB13_5 -; NOOPT-NEXT: .LBB13_5: # %loop +; NOOPT-NEXT: jmp .LBB13_3 +; NOOPT-NEXT: .LBB13_3: # %loop ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $25, %eax -; NOOPT-NEXT: je .LBB13_4 -; NOOPT-NEXT: jmp .LBB13_6 -; NOOPT-NEXT: .LBB13_6: # %loop +; NOOPT-NEXT: je .LBB13_7 +; NOOPT-NEXT: jmp .LBB13_4 +; NOOPT-NEXT: .LBB13_4: # %loop ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $36, %eax -; NOOPT-NEXT: je .LBB13_4 -; NOOPT-NEXT: jmp .LBB13_7 -; NOOPT-NEXT: .LBB13_7: # %loop +; NOOPT-NEXT: je .LBB13_7 +; NOOPT-NEXT: jmp .LBB13_5 +; NOOPT-NEXT: .LBB13_5: # %loop ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $69, %eax -; NOOPT-NEXT: je .LBB13_4 -; NOOPT-NEXT: jmp .LBB13_3 -; NOOPT-NEXT: .LBB13_3: # %exit +; NOOPT-NEXT: je .LBB13_7 +; NOOPT-NEXT: jmp .LBB13_6 +; NOOPT-NEXT: .LBB13_6: # %exit ; NOOPT-NEXT: retq -; NOOPT-NEXT: .LBB13_4: # %exit2 +; NOOPT-NEXT: .LBB13_7: # %exit2 ; NOOPT-NEXT: retq entry: br label %header @@ -1440,27 +1440,27 @@ define void @int_max_table_cluster(i8 %x) { ; NOOPT-NEXT: # kill: def $rcx killed $ecx ; NOOPT-NEXT: movq %rcx, (%rsp) # 8-byte Spill ; NOOPT-NEXT: subb $-65, %al -; NOOPT-NEXT: ja .LBB15_5 -; NOOPT-NEXT: # %bb.6: # %entry +; NOOPT-NEXT: ja .LBB15_6 +; NOOPT-NEXT: # %bb.1: # %entry ; NOOPT-NEXT: movq (%rsp), %rax # 8-byte Reload ; NOOPT-NEXT: movq .LJTI15_0(,%rax,8), %rax ; NOOPT-NEXT: jmpq *%rax -; NOOPT-NEXT: .LBB15_1: # %bb0 +; NOOPT-NEXT: .LBB15_2: # %bb0 ; NOOPT-NEXT: xorl %edi, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB15_5 -; NOOPT-NEXT: .LBB15_2: # %bb1 +; NOOPT-NEXT: jmp .LBB15_6 +; NOOPT-NEXT: .LBB15_3: # %bb1 ; NOOPT-NEXT: movl $1, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB15_5 -; NOOPT-NEXT: .LBB15_3: # %bb2 +; NOOPT-NEXT: jmp .LBB15_6 +; NOOPT-NEXT: .LBB15_4: # %bb2 ; NOOPT-NEXT: movl $1, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB15_5 -; NOOPT-NEXT: .LBB15_4: # %bb3 +; NOOPT-NEXT: jmp .LBB15_6 +; NOOPT-NEXT: .LBB15_5: # %bb3 ; NOOPT-NEXT: movl $1, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: .LBB15_5: # %return +; NOOPT-NEXT: .LBB15_6: # %return ; NOOPT-NEXT: popq %rax ; NOOPT-NEXT: .cfi_def_cfa_offset 8 ; NOOPT-NEXT: retq @@ -1534,18 +1534,18 @@ define void @bt_order_by_weight(i32 %x) { ; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: movl $146, %eax ; CHECK-NEXT: btl %edi, %eax -; CHECK-NEXT: jae .LBB16_2 -; CHECK-NEXT: # %bb.4: # %bb1 +; CHECK-NEXT: jae .LBB16_3 +; CHECK-NEXT: # %bb.2: # %bb1 ; CHECK-NEXT: movl $1, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB16_2: # %entry +; CHECK-NEXT: .LBB16_3: # %entry ; CHECK-NEXT: movl $804, %eax # imm = 0x324 ; CHECK-NEXT: btl %edi, %eax -; CHECK-NEXT: jae .LBB16_3 -; CHECK-NEXT: # %bb.5: # %bb2 +; CHECK-NEXT: jae .LBB16_5 +; CHECK-NEXT: # %bb.4: # %bb2 ; CHECK-NEXT: movl $2, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB16_3: # %bb0 +; CHECK-NEXT: .LBB16_5: # %bb0 ; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL ; CHECK-NEXT: .LBB16_6: # %return @@ -1557,61 +1557,61 @@ define void @bt_order_by_weight(i32 %x) { ; NOOPT-NEXT: .cfi_def_cfa_offset 16 ; NOOPT-NEXT: movl %edi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill ; NOOPT-NEXT: testl %edi, %edi -; NOOPT-NEXT: je .LBB16_1 -; NOOPT-NEXT: jmp .LBB16_5 -; NOOPT-NEXT: .LBB16_5: # %entry +; NOOPT-NEXT: je .LBB16_9 +; NOOPT-NEXT: jmp .LBB16_1 +; NOOPT-NEXT: .LBB16_1: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $1, %eax -; NOOPT-NEXT: je .LBB16_2 -; NOOPT-NEXT: jmp .LBB16_6 -; NOOPT-NEXT: .LBB16_6: # %entry +; NOOPT-NEXT: je .LBB16_10 +; NOOPT-NEXT: jmp .LBB16_2 +; NOOPT-NEXT: .LBB16_2: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $2, %eax -; NOOPT-NEXT: je .LBB16_3 -; NOOPT-NEXT: jmp .LBB16_7 -; NOOPT-NEXT: .LBB16_7: # %entry +; NOOPT-NEXT: je .LBB16_11 +; NOOPT-NEXT: jmp .LBB16_3 +; NOOPT-NEXT: .LBB16_3: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $3, %eax -; NOOPT-NEXT: je .LBB16_1 -; NOOPT-NEXT: jmp .LBB16_8 -; NOOPT-NEXT: .LBB16_8: # %entry +; NOOPT-NEXT: je .LBB16_9 +; NOOPT-NEXT: jmp .LBB16_4 +; NOOPT-NEXT: .LBB16_4: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $4, %eax -; NOOPT-NEXT: je .LBB16_2 -; NOOPT-NEXT: jmp .LBB16_9 -; NOOPT-NEXT: .LBB16_9: # %entry +; NOOPT-NEXT: je .LBB16_10 +; NOOPT-NEXT: jmp .LBB16_5 +; NOOPT-NEXT: .LBB16_5: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $5, %eax -; NOOPT-NEXT: je .LBB16_3 -; NOOPT-NEXT: jmp .LBB16_10 -; NOOPT-NEXT: .LBB16_10: # %entry +; NOOPT-NEXT: je .LBB16_11 +; NOOPT-NEXT: jmp .LBB16_6 +; NOOPT-NEXT: .LBB16_6: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $6, %eax -; NOOPT-NEXT: je .LBB16_1 -; NOOPT-NEXT: jmp .LBB16_11 -; NOOPT-NEXT: .LBB16_11: # %entry +; NOOPT-NEXT: je .LBB16_9 +; NOOPT-NEXT: jmp .LBB16_7 +; NOOPT-NEXT: .LBB16_7: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $7, %eax -; NOOPT-NEXT: je .LBB16_2 -; NOOPT-NEXT: jmp .LBB16_12 -; NOOPT-NEXT: .LBB16_12: # %entry +; NOOPT-NEXT: je .LBB16_10 +; NOOPT-NEXT: jmp .LBB16_8 +; NOOPT-NEXT: .LBB16_8: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: addl $-8, %eax ; NOOPT-NEXT: subl $2, %eax -; NOOPT-NEXT: jb .LBB16_3 -; NOOPT-NEXT: jmp .LBB16_4 -; NOOPT-NEXT: .LBB16_1: # %bb0 +; NOOPT-NEXT: jb .LBB16_11 +; NOOPT-NEXT: jmp .LBB16_12 +; NOOPT-NEXT: .LBB16_9: # %bb0 ; NOOPT-NEXT: xorl %edi, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB16_4 -; NOOPT-NEXT: .LBB16_2: # %bb1 +; NOOPT-NEXT: jmp .LBB16_12 +; NOOPT-NEXT: .LBB16_10: # %bb1 ; NOOPT-NEXT: movl $1, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB16_4 -; NOOPT-NEXT: .LBB16_3: # %bb2 +; NOOPT-NEXT: jmp .LBB16_12 +; NOOPT-NEXT: .LBB16_11: # %bb2 ; NOOPT-NEXT: movl $2, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: .LBB16_4: # %return +; NOOPT-NEXT: .LBB16_12: # %return ; NOOPT-NEXT: popq %rax ; NOOPT-NEXT: .cfi_def_cfa_offset 8 ; NOOPT-NEXT: retq @@ -1651,19 +1651,19 @@ define void @order_by_weight_and_fallthrough(i32 %x) { ; CHECK-LABEL: order_by_weight_and_fallthrough: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cmpl $200, %edi -; CHECK-NEXT: jne .LBB17_1 -; CHECK-NEXT: .LBB17_3: # %bb0 +; CHECK-NEXT: jne .LBB17_2 +; CHECK-NEXT: .LBB17_1: # %bb0 ; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB17_1: # %entry +; CHECK-NEXT: .LBB17_2: # %entry ; CHECK-NEXT: cmpl $100, %edi -; CHECK-NEXT: je .LBB17_4 -; CHECK-NEXT: # %bb.2: # %entry +; CHECK-NEXT: je .LBB17_5 +; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: cmpl $300, %edi # imm = 0x12C -; CHECK-NEXT: je .LBB17_3 -; CHECK-NEXT: # %bb.5: # %return +; CHECK-NEXT: je .LBB17_1 +; CHECK-NEXT: # %bb.4: # %return ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB17_4: # %bb1 +; CHECK-NEXT: .LBB17_5: # %bb1 ; CHECK-NEXT: movl $1, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL ; @@ -1673,26 +1673,26 @@ define void @order_by_weight_and_fallthrough(i32 %x) { ; NOOPT-NEXT: .cfi_def_cfa_offset 16 ; NOOPT-NEXT: movl %edi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill ; NOOPT-NEXT: subl $100, %edi -; NOOPT-NEXT: je .LBB17_2 -; NOOPT-NEXT: jmp .LBB17_4 -; NOOPT-NEXT: .LBB17_4: # %entry +; NOOPT-NEXT: je .LBB17_4 +; NOOPT-NEXT: jmp .LBB17_1 +; NOOPT-NEXT: .LBB17_1: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $200, %eax -; NOOPT-NEXT: je .LBB17_1 -; NOOPT-NEXT: jmp .LBB17_5 -; NOOPT-NEXT: .LBB17_5: # %entry +; NOOPT-NEXT: je .LBB17_3 +; NOOPT-NEXT: jmp .LBB17_2 +; NOOPT-NEXT: .LBB17_2: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $300, %eax # imm = 0x12C -; NOOPT-NEXT: jne .LBB17_3 -; NOOPT-NEXT: jmp .LBB17_1 -; NOOPT-NEXT: .LBB17_1: # %bb0 +; NOOPT-NEXT: jne .LBB17_5 +; NOOPT-NEXT: jmp .LBB17_3 +; NOOPT-NEXT: .LBB17_3: # %bb0 ; NOOPT-NEXT: xorl %edi, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB17_3 -; NOOPT-NEXT: .LBB17_2: # %bb1 +; NOOPT-NEXT: jmp .LBB17_5 +; NOOPT-NEXT: .LBB17_4: # %bb1 ; NOOPT-NEXT: movl $1, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: .LBB17_3: # %return +; NOOPT-NEXT: .LBB17_5: # %return ; NOOPT-NEXT: popq %rax ; NOOPT-NEXT: .cfi_def_cfa_offset 8 ; NOOPT-NEXT: retq @@ -1723,43 +1723,43 @@ define void @zero_weight_tree(i32 %x) { ; CHECK-LABEL: zero_weight_tree: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cmpl $29, %edi -; CHECK-NEXT: jg .LBB18_5 +; CHECK-NEXT: jg .LBB18_3 ; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: testl %edi, %edi -; CHECK-NEXT: jne .LBB18_2 -; CHECK-NEXT: # %bb.9: # %bb0 +; CHECK-NEXT: jne .LBB18_5 +; CHECK-NEXT: # %bb.2: # %bb0 ; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB18_5: # %entry +; CHECK-NEXT: .LBB18_3: # %entry ; CHECK-NEXT: cmpl $50, %edi -; CHECK-NEXT: jne .LBB18_6 -; CHECK-NEXT: # %bb.12: # %bb5 +; CHECK-NEXT: jne .LBB18_8 +; CHECK-NEXT: # %bb.4: # %bb5 ; CHECK-NEXT: movl $5, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB18_2: # %entry +; CHECK-NEXT: .LBB18_5: # %entry ; CHECK-NEXT: cmpl $10, %edi -; CHECK-NEXT: je .LBB18_10 -; CHECK-NEXT: # %bb.3: # %entry +; CHECK-NEXT: je .LBB18_11 +; CHECK-NEXT: # %bb.6: # %entry ; CHECK-NEXT: cmpl $20, %edi -; CHECK-NEXT: jne .LBB18_13 -; CHECK-NEXT: # %bb.4: # %bb2 +; CHECK-NEXT: jne .LBB18_10 +; CHECK-NEXT: # %bb.7: # %bb2 ; CHECK-NEXT: movl $2, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB18_6: # %entry +; CHECK-NEXT: .LBB18_8: # %entry ; CHECK-NEXT: cmpl $30, %edi -; CHECK-NEXT: je .LBB18_11 -; CHECK-NEXT: # %bb.7: # %entry +; CHECK-NEXT: je .LBB18_12 +; CHECK-NEXT: # %bb.9: # %entry ; CHECK-NEXT: cmpl $40, %edi -; CHECK-NEXT: je .LBB18_8 -; CHECK-NEXT: .LBB18_13: # %return +; CHECK-NEXT: je .LBB18_13 +; CHECK-NEXT: .LBB18_10: # %return ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB18_10: # %bb1 +; CHECK-NEXT: .LBB18_11: # %bb1 ; CHECK-NEXT: movl $1, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB18_11: # %bb3 +; CHECK-NEXT: .LBB18_12: # %bb3 ; CHECK-NEXT: movl $3, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB18_8: # %bb4 +; CHECK-NEXT: .LBB18_13: # %bb4 ; CHECK-NEXT: movl $4, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL ; @@ -1769,57 +1769,57 @@ define void @zero_weight_tree(i32 %x) { ; NOOPT-NEXT: .cfi_def_cfa_offset 16 ; NOOPT-NEXT: movl %edi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill ; NOOPT-NEXT: testl %edi, %edi -; NOOPT-NEXT: je .LBB18_1 -; NOOPT-NEXT: jmp .LBB18_8 -; NOOPT-NEXT: .LBB18_8: # %entry +; NOOPT-NEXT: je .LBB18_6 +; NOOPT-NEXT: jmp .LBB18_1 +; NOOPT-NEXT: .LBB18_1: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $10, %eax -; NOOPT-NEXT: je .LBB18_2 -; NOOPT-NEXT: jmp .LBB18_9 -; NOOPT-NEXT: .LBB18_9: # %entry +; NOOPT-NEXT: je .LBB18_7 +; NOOPT-NEXT: jmp .LBB18_2 +; NOOPT-NEXT: .LBB18_2: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $20, %eax -; NOOPT-NEXT: je .LBB18_3 -; NOOPT-NEXT: jmp .LBB18_10 -; NOOPT-NEXT: .LBB18_10: # %entry +; NOOPT-NEXT: je .LBB18_8 +; NOOPT-NEXT: jmp .LBB18_3 +; NOOPT-NEXT: .LBB18_3: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $30, %eax -; NOOPT-NEXT: je .LBB18_4 -; NOOPT-NEXT: jmp .LBB18_11 -; NOOPT-NEXT: .LBB18_11: # %entry +; NOOPT-NEXT: je .LBB18_9 +; NOOPT-NEXT: jmp .LBB18_4 +; NOOPT-NEXT: .LBB18_4: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $40, %eax -; NOOPT-NEXT: je .LBB18_5 -; NOOPT-NEXT: jmp .LBB18_12 -; NOOPT-NEXT: .LBB18_12: # %entry +; NOOPT-NEXT: je .LBB18_10 +; NOOPT-NEXT: jmp .LBB18_5 +; NOOPT-NEXT: .LBB18_5: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $50, %eax -; NOOPT-NEXT: je .LBB18_6 -; NOOPT-NEXT: jmp .LBB18_7 -; NOOPT-NEXT: .LBB18_1: # %bb0 +; NOOPT-NEXT: je .LBB18_11 +; NOOPT-NEXT: jmp .LBB18_12 +; NOOPT-NEXT: .LBB18_6: # %bb0 ; NOOPT-NEXT: xorl %edi, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB18_7 -; NOOPT-NEXT: .LBB18_2: # %bb1 +; NOOPT-NEXT: jmp .LBB18_12 +; NOOPT-NEXT: .LBB18_7: # %bb1 ; NOOPT-NEXT: movl $1, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB18_7 -; NOOPT-NEXT: .LBB18_3: # %bb2 +; NOOPT-NEXT: jmp .LBB18_12 +; NOOPT-NEXT: .LBB18_8: # %bb2 ; NOOPT-NEXT: movl $2, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB18_7 -; NOOPT-NEXT: .LBB18_4: # %bb3 +; NOOPT-NEXT: jmp .LBB18_12 +; NOOPT-NEXT: .LBB18_9: # %bb3 ; NOOPT-NEXT: movl $3, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB18_7 -; NOOPT-NEXT: .LBB18_5: # %bb4 +; NOOPT-NEXT: jmp .LBB18_12 +; NOOPT-NEXT: .LBB18_10: # %bb4 ; NOOPT-NEXT: movl $4, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB18_7 -; NOOPT-NEXT: .LBB18_6: # %bb5 +; NOOPT-NEXT: jmp .LBB18_12 +; NOOPT-NEXT: .LBB18_11: # %bb5 ; NOOPT-NEXT: movl $5, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: .LBB18_7: # %return +; NOOPT-NEXT: .LBB18_12: # %return ; NOOPT-NEXT: popq %rax ; NOOPT-NEXT: .cfi_def_cfa_offset 8 ; NOOPT-NEXT: retq @@ -1852,48 +1852,48 @@ define void @left_leaning_weight_balanced_tree(i32 %x) { ; CHECK-LABEL: left_leaning_weight_balanced_tree: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cmpl $49, %edi -; CHECK-NEXT: jle .LBB19_1 -; CHECK-NEXT: # %bb.11: # %entry +; CHECK-NEXT: jle .LBB19_3 +; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: cmpl $70, %edi -; CHECK-NEXT: jne .LBB19_12 -; CHECK-NEXT: .LBB19_14: # %bb6 +; CHECK-NEXT: jne .LBB19_10 +; CHECK-NEXT: .LBB19_2: # %bb6 ; CHECK-NEXT: movl $6, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB19_1: # %entry +; CHECK-NEXT: .LBB19_3: # %entry ; CHECK-NEXT: cmpl $9, %edi -; CHECK-NEXT: jg .LBB19_4 -; CHECK-NEXT: # %bb.2: # %entry +; CHECK-NEXT: jg .LBB19_6 +; CHECK-NEXT: # %bb.4: # %entry ; CHECK-NEXT: testl %edi, %edi -; CHECK-NEXT: jne .LBB19_18 -; CHECK-NEXT: # %bb.3: # %bb0 +; CHECK-NEXT: jne .LBB19_17 +; CHECK-NEXT: # %bb.5: # %bb0 ; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB19_4: # %entry +; CHECK-NEXT: .LBB19_6: # %entry ; CHECK-NEXT: cmpl $29, %edi -; CHECK-NEXT: jg .LBB19_8 -; CHECK-NEXT: # %bb.5: # %entry +; CHECK-NEXT: jg .LBB19_12 +; CHECK-NEXT: # %bb.7: # %entry ; CHECK-NEXT: cmpl $10, %edi ; CHECK-NEXT: je .LBB19_15 -; CHECK-NEXT: # %bb.6: # %entry +; CHECK-NEXT: # %bb.8: # %entry ; CHECK-NEXT: cmpl $20, %edi -; CHECK-NEXT: jne .LBB19_18 -; CHECK-NEXT: # %bb.7: # %bb2 +; CHECK-NEXT: jne .LBB19_17 +; CHECK-NEXT: # %bb.9: # %bb2 ; CHECK-NEXT: movl $2, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB19_12: # %entry +; CHECK-NEXT: .LBB19_10: # %entry ; CHECK-NEXT: cmpl $50, %edi -; CHECK-NEXT: je .LBB19_17 -; CHECK-NEXT: # %bb.13: # %entry +; CHECK-NEXT: je .LBB19_18 +; CHECK-NEXT: # %bb.11: # %entry ; CHECK-NEXT: cmpl $60, %edi -; CHECK-NEXT: je .LBB19_14 -; CHECK-NEXT: jmp .LBB19_18 -; CHECK-NEXT: .LBB19_8: # %entry +; CHECK-NEXT: je .LBB19_2 +; CHECK-NEXT: jmp .LBB19_17 +; CHECK-NEXT: .LBB19_12: # %entry ; CHECK-NEXT: cmpl $30, %edi ; CHECK-NEXT: je .LBB19_16 -; CHECK-NEXT: # %bb.9: # %entry +; CHECK-NEXT: # %bb.13: # %entry ; CHECK-NEXT: cmpl $40, %edi -; CHECK-NEXT: jne .LBB19_18 -; CHECK-NEXT: # %bb.10: # %bb4 +; CHECK-NEXT: jne .LBB19_17 +; CHECK-NEXT: # %bb.14: # %bb4 ; CHECK-NEXT: movl $4, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL ; CHECK-NEXT: .LBB19_15: # %bb1 @@ -1902,9 +1902,9 @@ define void @left_leaning_weight_balanced_tree(i32 %x) { ; CHECK-NEXT: .LBB19_16: # %bb3 ; CHECK-NEXT: movl $3, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB19_18: # %return +; CHECK-NEXT: .LBB19_17: # %return ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB19_17: # %bb5 +; CHECK-NEXT: .LBB19_18: # %bb5 ; CHECK-NEXT: movl $5, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL ; @@ -1914,71 +1914,71 @@ define void @left_leaning_weight_balanced_tree(i32 %x) { ; NOOPT-NEXT: .cfi_def_cfa_offset 16 ; NOOPT-NEXT: movl %edi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill ; NOOPT-NEXT: testl %edi, %edi -; NOOPT-NEXT: je .LBB19_1 -; NOOPT-NEXT: jmp .LBB19_9 -; NOOPT-NEXT: .LBB19_9: # %entry +; NOOPT-NEXT: je .LBB19_8 +; NOOPT-NEXT: jmp .LBB19_1 +; NOOPT-NEXT: .LBB19_1: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $10, %eax -; NOOPT-NEXT: je .LBB19_2 -; NOOPT-NEXT: jmp .LBB19_10 -; NOOPT-NEXT: .LBB19_10: # %entry +; NOOPT-NEXT: je .LBB19_9 +; NOOPT-NEXT: jmp .LBB19_2 +; NOOPT-NEXT: .LBB19_2: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $20, %eax -; NOOPT-NEXT: je .LBB19_3 -; NOOPT-NEXT: jmp .LBB19_11 -; NOOPT-NEXT: .LBB19_11: # %entry +; NOOPT-NEXT: je .LBB19_10 +; NOOPT-NEXT: jmp .LBB19_3 +; NOOPT-NEXT: .LBB19_3: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $30, %eax -; NOOPT-NEXT: je .LBB19_4 -; NOOPT-NEXT: jmp .LBB19_12 -; NOOPT-NEXT: .LBB19_12: # %entry +; NOOPT-NEXT: je .LBB19_11 +; NOOPT-NEXT: jmp .LBB19_4 +; NOOPT-NEXT: .LBB19_4: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $40, %eax -; NOOPT-NEXT: je .LBB19_5 -; NOOPT-NEXT: jmp .LBB19_13 -; NOOPT-NEXT: .LBB19_13: # %entry +; NOOPT-NEXT: je .LBB19_12 +; NOOPT-NEXT: jmp .LBB19_5 +; NOOPT-NEXT: .LBB19_5: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $50, %eax -; NOOPT-NEXT: je .LBB19_6 -; NOOPT-NEXT: jmp .LBB19_14 -; NOOPT-NEXT: .LBB19_14: # %entry +; NOOPT-NEXT: je .LBB19_13 +; NOOPT-NEXT: jmp .LBB19_6 +; NOOPT-NEXT: .LBB19_6: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $60, %eax -; NOOPT-NEXT: je .LBB19_7 -; NOOPT-NEXT: jmp .LBB19_15 -; NOOPT-NEXT: .LBB19_15: # %entry +; NOOPT-NEXT: je .LBB19_14 +; NOOPT-NEXT: jmp .LBB19_7 +; NOOPT-NEXT: .LBB19_7: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $70, %eax -; NOOPT-NEXT: je .LBB19_7 -; NOOPT-NEXT: jmp .LBB19_8 -; NOOPT-NEXT: .LBB19_1: # %bb0 +; NOOPT-NEXT: je .LBB19_14 +; NOOPT-NEXT: jmp .LBB19_15 +; NOOPT-NEXT: .LBB19_8: # %bb0 ; NOOPT-NEXT: xorl %edi, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB19_8 -; NOOPT-NEXT: .LBB19_2: # %bb1 +; NOOPT-NEXT: jmp .LBB19_15 +; NOOPT-NEXT: .LBB19_9: # %bb1 ; NOOPT-NEXT: movl $1, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB19_8 -; NOOPT-NEXT: .LBB19_3: # %bb2 +; NOOPT-NEXT: jmp .LBB19_15 +; NOOPT-NEXT: .LBB19_10: # %bb2 ; NOOPT-NEXT: movl $2, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB19_8 -; NOOPT-NEXT: .LBB19_4: # %bb3 +; NOOPT-NEXT: jmp .LBB19_15 +; NOOPT-NEXT: .LBB19_11: # %bb3 ; NOOPT-NEXT: movl $3, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB19_8 -; NOOPT-NEXT: .LBB19_5: # %bb4 +; NOOPT-NEXT: jmp .LBB19_15 +; NOOPT-NEXT: .LBB19_12: # %bb4 ; NOOPT-NEXT: movl $4, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB19_8 -; NOOPT-NEXT: .LBB19_6: # %bb5 +; NOOPT-NEXT: jmp .LBB19_15 +; NOOPT-NEXT: .LBB19_13: # %bb5 ; NOOPT-NEXT: movl $5, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB19_8 -; NOOPT-NEXT: .LBB19_7: # %bb6 +; NOOPT-NEXT: jmp .LBB19_15 +; NOOPT-NEXT: .LBB19_14: # %bb6 ; NOOPT-NEXT: movl $6, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: .LBB19_8: # %return +; NOOPT-NEXT: .LBB19_15: # %return ; NOOPT-NEXT: popq %rax ; NOOPT-NEXT: .cfi_def_cfa_offset 8 ; NOOPT-NEXT: retq @@ -2014,54 +2014,54 @@ define void @left_leaning_weight_balanced_tree2(i32 %x) { ; CHECK-LABEL: left_leaning_weight_balanced_tree2: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cmpl $59, %edi -; CHECK-NEXT: jle .LBB20_1 -; CHECK-NEXT: # %bb.10: # %entry +; CHECK-NEXT: jle .LBB20_3 +; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: cmpl $70, %edi -; CHECK-NEXT: jne .LBB20_11 -; CHECK-NEXT: .LBB20_12: # %bb6 +; CHECK-NEXT: jne .LBB20_6 +; CHECK-NEXT: .LBB20_2: # %bb6 ; CHECK-NEXT: movl $6, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB20_1: # %entry +; CHECK-NEXT: .LBB20_3: # %entry ; CHECK-NEXT: cmpl $29, %edi -; CHECK-NEXT: jle .LBB20_2 -; CHECK-NEXT: # %bb.6: # %entry +; CHECK-NEXT: jle .LBB20_7 +; CHECK-NEXT: # %bb.4: # %entry ; CHECK-NEXT: cmpl $50, %edi -; CHECK-NEXT: jne .LBB20_7 -; CHECK-NEXT: # %bb.16: # %bb5 +; CHECK-NEXT: jne .LBB20_12 +; CHECK-NEXT: # %bb.5: # %bb5 ; CHECK-NEXT: movl $5, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB20_11: # %entry +; CHECK-NEXT: .LBB20_6: # %entry ; CHECK-NEXT: cmpl $60, %edi -; CHECK-NEXT: je .LBB20_12 +; CHECK-NEXT: je .LBB20_2 ; CHECK-NEXT: jmp .LBB20_17 -; CHECK-NEXT: .LBB20_2: # %entry +; CHECK-NEXT: .LBB20_7: # %entry ; CHECK-NEXT: testl %edi, %edi -; CHECK-NEXT: jne .LBB20_3 -; CHECK-NEXT: # %bb.13: # %bb0 +; CHECK-NEXT: jne .LBB20_9 +; CHECK-NEXT: # %bb.8: # %bb0 ; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB20_3: # %entry +; CHECK-NEXT: .LBB20_9: # %entry ; CHECK-NEXT: cmpl $10, %edi -; CHECK-NEXT: je .LBB20_14 -; CHECK-NEXT: # %bb.4: # %entry +; CHECK-NEXT: je .LBB20_15 +; CHECK-NEXT: # %bb.10: # %entry ; CHECK-NEXT: cmpl $20, %edi ; CHECK-NEXT: jne .LBB20_17 -; CHECK-NEXT: # %bb.5: # %bb2 +; CHECK-NEXT: # %bb.11: # %bb2 ; CHECK-NEXT: movl $2, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB20_7: # %entry +; CHECK-NEXT: .LBB20_12: # %entry ; CHECK-NEXT: cmpl $30, %edi -; CHECK-NEXT: je .LBB20_15 -; CHECK-NEXT: # %bb.8: # %entry +; CHECK-NEXT: je .LBB20_16 +; CHECK-NEXT: # %bb.13: # %entry ; CHECK-NEXT: cmpl $40, %edi ; CHECK-NEXT: jne .LBB20_17 -; CHECK-NEXT: # %bb.9: # %bb4 +; CHECK-NEXT: # %bb.14: # %bb4 ; CHECK-NEXT: movl $4, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB20_14: # %bb1 +; CHECK-NEXT: .LBB20_15: # %bb1 ; CHECK-NEXT: movl $1, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB20_15: # %bb3 +; CHECK-NEXT: .LBB20_16: # %bb3 ; CHECK-NEXT: movl $3, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL ; CHECK-NEXT: .LBB20_17: # %return @@ -2073,71 +2073,71 @@ define void @left_leaning_weight_balanced_tree2(i32 %x) { ; NOOPT-NEXT: .cfi_def_cfa_offset 16 ; NOOPT-NEXT: movl %edi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill ; NOOPT-NEXT: testl %edi, %edi -; NOOPT-NEXT: je .LBB20_1 -; NOOPT-NEXT: jmp .LBB20_9 -; NOOPT-NEXT: .LBB20_9: # %entry +; NOOPT-NEXT: je .LBB20_8 +; NOOPT-NEXT: jmp .LBB20_1 +; NOOPT-NEXT: .LBB20_1: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $10, %eax -; NOOPT-NEXT: je .LBB20_2 -; NOOPT-NEXT: jmp .LBB20_10 -; NOOPT-NEXT: .LBB20_10: # %entry +; NOOPT-NEXT: je .LBB20_9 +; NOOPT-NEXT: jmp .LBB20_2 +; NOOPT-NEXT: .LBB20_2: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $20, %eax -; NOOPT-NEXT: je .LBB20_3 -; NOOPT-NEXT: jmp .LBB20_11 -; NOOPT-NEXT: .LBB20_11: # %entry +; NOOPT-NEXT: je .LBB20_10 +; NOOPT-NEXT: jmp .LBB20_3 +; NOOPT-NEXT: .LBB20_3: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $30, %eax -; NOOPT-NEXT: je .LBB20_4 -; NOOPT-NEXT: jmp .LBB20_12 -; NOOPT-NEXT: .LBB20_12: # %entry +; NOOPT-NEXT: je .LBB20_11 +; NOOPT-NEXT: jmp .LBB20_4 +; NOOPT-NEXT: .LBB20_4: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $40, %eax -; NOOPT-NEXT: je .LBB20_5 -; NOOPT-NEXT: jmp .LBB20_13 -; NOOPT-NEXT: .LBB20_13: # %entry +; NOOPT-NEXT: je .LBB20_12 +; NOOPT-NEXT: jmp .LBB20_5 +; NOOPT-NEXT: .LBB20_5: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $50, %eax -; NOOPT-NEXT: je .LBB20_6 -; NOOPT-NEXT: jmp .LBB20_14 -; NOOPT-NEXT: .LBB20_14: # %entry +; NOOPT-NEXT: je .LBB20_13 +; NOOPT-NEXT: jmp .LBB20_6 +; NOOPT-NEXT: .LBB20_6: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $60, %eax -; NOOPT-NEXT: je .LBB20_7 -; NOOPT-NEXT: jmp .LBB20_15 -; NOOPT-NEXT: .LBB20_15: # %entry +; NOOPT-NEXT: je .LBB20_14 +; NOOPT-NEXT: jmp .LBB20_7 +; NOOPT-NEXT: .LBB20_7: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $70, %eax -; NOOPT-NEXT: je .LBB20_7 -; NOOPT-NEXT: jmp .LBB20_8 -; NOOPT-NEXT: .LBB20_1: # %bb0 +; NOOPT-NEXT: je .LBB20_14 +; NOOPT-NEXT: jmp .LBB20_15 +; NOOPT-NEXT: .LBB20_8: # %bb0 ; NOOPT-NEXT: xorl %edi, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB20_8 -; NOOPT-NEXT: .LBB20_2: # %bb1 +; NOOPT-NEXT: jmp .LBB20_15 +; NOOPT-NEXT: .LBB20_9: # %bb1 ; NOOPT-NEXT: movl $1, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB20_8 -; NOOPT-NEXT: .LBB20_3: # %bb2 +; NOOPT-NEXT: jmp .LBB20_15 +; NOOPT-NEXT: .LBB20_10: # %bb2 ; NOOPT-NEXT: movl $2, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB20_8 -; NOOPT-NEXT: .LBB20_4: # %bb3 +; NOOPT-NEXT: jmp .LBB20_15 +; NOOPT-NEXT: .LBB20_11: # %bb3 ; NOOPT-NEXT: movl $3, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB20_8 -; NOOPT-NEXT: .LBB20_5: # %bb4 +; NOOPT-NEXT: jmp .LBB20_15 +; NOOPT-NEXT: .LBB20_12: # %bb4 ; NOOPT-NEXT: movl $4, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB20_8 -; NOOPT-NEXT: .LBB20_6: # %bb5 +; NOOPT-NEXT: jmp .LBB20_15 +; NOOPT-NEXT: .LBB20_13: # %bb5 ; NOOPT-NEXT: movl $5, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB20_8 -; NOOPT-NEXT: .LBB20_7: # %bb6 +; NOOPT-NEXT: jmp .LBB20_15 +; NOOPT-NEXT: .LBB20_14: # %bb6 ; NOOPT-NEXT: movl $6, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: .LBB20_8: # %return +; NOOPT-NEXT: .LBB20_15: # %return ; NOOPT-NEXT: popq %rax ; NOOPT-NEXT: .cfi_def_cfa_offset 8 ; NOOPT-NEXT: retq @@ -2171,56 +2171,56 @@ define void @right_leaning_weight_balanced_tree(i32 %x) { ; CHECK-LABEL: right_leaning_weight_balanced_tree: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cmpl $19, %edi -; CHECK-NEXT: jg .LBB21_4 +; CHECK-NEXT: jg .LBB21_3 ; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: testl %edi, %edi -; CHECK-NEXT: jne .LBB21_2 -; CHECK-NEXT: # %bb.13: # %bb0 +; CHECK-NEXT: jne .LBB21_14 +; CHECK-NEXT: # %bb.2: # %bb0 ; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB21_4: # %entry +; CHECK-NEXT: .LBB21_3: # %entry ; CHECK-NEXT: cmpl $49, %edi -; CHECK-NEXT: jle .LBB21_5 -; CHECK-NEXT: # %bb.9: # %entry +; CHECK-NEXT: jle .LBB21_6 +; CHECK-NEXT: # %bb.4: # %entry ; CHECK-NEXT: cmpl $70, %edi ; CHECK-NEXT: jne .LBB21_10 -; CHECK-NEXT: .LBB21_12: # %bb6 +; CHECK-NEXT: .LBB21_5: # %bb6 ; CHECK-NEXT: movl $6, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB21_5: # %entry +; CHECK-NEXT: .LBB21_6: # %entry ; CHECK-NEXT: cmpl $20, %edi -; CHECK-NEXT: je .LBB21_14 -; CHECK-NEXT: # %bb.6: # %entry -; CHECK-NEXT: cmpl $30, %edi -; CHECK-NEXT: je .LBB21_15 +; CHECK-NEXT: je .LBB21_12 ; CHECK-NEXT: # %bb.7: # %entry +; CHECK-NEXT: cmpl $30, %edi +; CHECK-NEXT: je .LBB21_13 +; CHECK-NEXT: # %bb.8: # %entry ; CHECK-NEXT: cmpl $40, %edi -; CHECK-NEXT: jne .LBB21_17 -; CHECK-NEXT: # %bb.8: # %bb4 +; CHECK-NEXT: jne .LBB21_16 +; CHECK-NEXT: # %bb.9: # %bb4 ; CHECK-NEXT: movl $4, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL ; CHECK-NEXT: .LBB21_10: # %entry ; CHECK-NEXT: cmpl $50, %edi -; CHECK-NEXT: je .LBB21_16 +; CHECK-NEXT: je .LBB21_17 ; CHECK-NEXT: # %bb.11: # %entry ; CHECK-NEXT: cmpl $60, %edi -; CHECK-NEXT: je .LBB21_12 -; CHECK-NEXT: jmp .LBB21_17 -; CHECK-NEXT: .LBB21_14: # %bb2 +; CHECK-NEXT: je .LBB21_5 +; CHECK-NEXT: jmp .LBB21_16 +; CHECK-NEXT: .LBB21_12: # %bb2 ; CHECK-NEXT: movl $2, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB21_15: # %bb3 +; CHECK-NEXT: .LBB21_13: # %bb3 ; CHECK-NEXT: movl $3, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB21_2: # %entry +; CHECK-NEXT: .LBB21_14: # %entry ; CHECK-NEXT: cmpl $10, %edi -; CHECK-NEXT: jne .LBB21_17 -; CHECK-NEXT: # %bb.3: # %bb1 +; CHECK-NEXT: jne .LBB21_16 +; CHECK-NEXT: # %bb.15: # %bb1 ; CHECK-NEXT: movl $1, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB21_17: # %return +; CHECK-NEXT: .LBB21_16: # %return ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB21_16: # %bb5 +; CHECK-NEXT: .LBB21_17: # %bb5 ; CHECK-NEXT: movl $5, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL ; @@ -2230,71 +2230,71 @@ define void @right_leaning_weight_balanced_tree(i32 %x) { ; NOOPT-NEXT: .cfi_def_cfa_offset 16 ; NOOPT-NEXT: movl %edi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill ; NOOPT-NEXT: testl %edi, %edi -; NOOPT-NEXT: je .LBB21_1 -; NOOPT-NEXT: jmp .LBB21_9 -; NOOPT-NEXT: .LBB21_9: # %entry +; NOOPT-NEXT: je .LBB21_8 +; NOOPT-NEXT: jmp .LBB21_1 +; NOOPT-NEXT: .LBB21_1: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $10, %eax -; NOOPT-NEXT: je .LBB21_2 -; NOOPT-NEXT: jmp .LBB21_10 -; NOOPT-NEXT: .LBB21_10: # %entry +; NOOPT-NEXT: je .LBB21_9 +; NOOPT-NEXT: jmp .LBB21_2 +; NOOPT-NEXT: .LBB21_2: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $20, %eax -; NOOPT-NEXT: je .LBB21_3 -; NOOPT-NEXT: jmp .LBB21_11 -; NOOPT-NEXT: .LBB21_11: # %entry +; NOOPT-NEXT: je .LBB21_10 +; NOOPT-NEXT: jmp .LBB21_3 +; NOOPT-NEXT: .LBB21_3: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $30, %eax -; NOOPT-NEXT: je .LBB21_4 -; NOOPT-NEXT: jmp .LBB21_12 -; NOOPT-NEXT: .LBB21_12: # %entry +; NOOPT-NEXT: je .LBB21_11 +; NOOPT-NEXT: jmp .LBB21_4 +; NOOPT-NEXT: .LBB21_4: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $40, %eax -; NOOPT-NEXT: je .LBB21_5 -; NOOPT-NEXT: jmp .LBB21_13 -; NOOPT-NEXT: .LBB21_13: # %entry +; NOOPT-NEXT: je .LBB21_12 +; NOOPT-NEXT: jmp .LBB21_5 +; NOOPT-NEXT: .LBB21_5: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $50, %eax -; NOOPT-NEXT: je .LBB21_6 -; NOOPT-NEXT: jmp .LBB21_14 -; NOOPT-NEXT: .LBB21_14: # %entry +; NOOPT-NEXT: je .LBB21_13 +; NOOPT-NEXT: jmp .LBB21_6 +; NOOPT-NEXT: .LBB21_6: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $60, %eax -; NOOPT-NEXT: je .LBB21_7 -; NOOPT-NEXT: jmp .LBB21_15 -; NOOPT-NEXT: .LBB21_15: # %entry +; NOOPT-NEXT: je .LBB21_14 +; NOOPT-NEXT: jmp .LBB21_7 +; NOOPT-NEXT: .LBB21_7: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $70, %eax -; NOOPT-NEXT: je .LBB21_7 -; NOOPT-NEXT: jmp .LBB21_8 -; NOOPT-NEXT: .LBB21_1: # %bb0 +; NOOPT-NEXT: je .LBB21_14 +; NOOPT-NEXT: jmp .LBB21_15 +; NOOPT-NEXT: .LBB21_8: # %bb0 ; NOOPT-NEXT: xorl %edi, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB21_8 -; NOOPT-NEXT: .LBB21_2: # %bb1 +; NOOPT-NEXT: jmp .LBB21_15 +; NOOPT-NEXT: .LBB21_9: # %bb1 ; NOOPT-NEXT: movl $1, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB21_8 -; NOOPT-NEXT: .LBB21_3: # %bb2 +; NOOPT-NEXT: jmp .LBB21_15 +; NOOPT-NEXT: .LBB21_10: # %bb2 ; NOOPT-NEXT: movl $2, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB21_8 -; NOOPT-NEXT: .LBB21_4: # %bb3 +; NOOPT-NEXT: jmp .LBB21_15 +; NOOPT-NEXT: .LBB21_11: # %bb3 ; NOOPT-NEXT: movl $3, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB21_8 -; NOOPT-NEXT: .LBB21_5: # %bb4 +; NOOPT-NEXT: jmp .LBB21_15 +; NOOPT-NEXT: .LBB21_12: # %bb4 ; NOOPT-NEXT: movl $4, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB21_8 -; NOOPT-NEXT: .LBB21_6: # %bb5 +; NOOPT-NEXT: jmp .LBB21_15 +; NOOPT-NEXT: .LBB21_13: # %bb5 ; NOOPT-NEXT: movl $5, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB21_8 -; NOOPT-NEXT: .LBB21_7: # %bb6 +; NOOPT-NEXT: jmp .LBB21_15 +; NOOPT-NEXT: .LBB21_14: # %bb6 ; NOOPT-NEXT: movl $6, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: .LBB21_8: # %return +; NOOPT-NEXT: .LBB21_15: # %return ; NOOPT-NEXT: popq %rax ; NOOPT-NEXT: .cfi_def_cfa_offset 8 ; NOOPT-NEXT: retq @@ -2330,32 +2330,32 @@ define void @jump_table_affects_balance(i32 %x) { ; CHECK-LABEL: jump_table_affects_balance: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cmpl $99, %edi -; CHECK-NEXT: jg .LBB22_3 +; CHECK-NEXT: jg .LBB22_4 ; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: cmpl $3, %edi ; CHECK-NEXT: ja .LBB22_10 ; CHECK-NEXT: # %bb.2: # %entry ; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: jmpq *.LJTI22_0(,%rax,8) -; CHECK-NEXT: .LBB22_9: # %bb3 +; CHECK-NEXT: .LBB22_3: # %bb3 ; CHECK-NEXT: movl $3, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB22_3: # %entry +; CHECK-NEXT: .LBB22_4: # %entry ; CHECK-NEXT: cmpl $300, %edi # imm = 0x12C ; CHECK-NEXT: je .LBB22_8 -; CHECK-NEXT: # %bb.4: # %entry -; CHECK-NEXT: cmpl $200, %edi -; CHECK-NEXT: je .LBB22_7 ; CHECK-NEXT: # %bb.5: # %entry +; CHECK-NEXT: cmpl $200, %edi +; CHECK-NEXT: je .LBB22_9 +; CHECK-NEXT: # %bb.6: # %entry ; CHECK-NEXT: cmpl $100, %edi ; CHECK-NEXT: jne .LBB22_10 -; CHECK-NEXT: .LBB22_6: # %bb0 +; CHECK-NEXT: .LBB22_7: # %bb0 ; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL ; CHECK-NEXT: .LBB22_8: # %bb2 ; CHECK-NEXT: movl $2, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB22_7: # %bb1 +; CHECK-NEXT: .LBB22_9: # %bb1 ; CHECK-NEXT: movl $1, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL ; CHECK-NEXT: .LBB22_10: # %return @@ -2367,54 +2367,54 @@ define void @jump_table_affects_balance(i32 %x) { ; NOOPT-NEXT: .cfi_def_cfa_offset 16 ; NOOPT-NEXT: movl %edi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill ; NOOPT-NEXT: testl %edi, %edi -; NOOPT-NEXT: je .LBB22_1 -; NOOPT-NEXT: jmp .LBB22_6 -; NOOPT-NEXT: .LBB22_6: # %entry +; NOOPT-NEXT: je .LBB22_7 +; NOOPT-NEXT: jmp .LBB22_1 +; NOOPT-NEXT: .LBB22_1: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $1, %eax -; NOOPT-NEXT: je .LBB22_2 -; NOOPT-NEXT: jmp .LBB22_7 -; NOOPT-NEXT: .LBB22_7: # %entry +; NOOPT-NEXT: je .LBB22_8 +; NOOPT-NEXT: jmp .LBB22_2 +; NOOPT-NEXT: .LBB22_2: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $2, %eax -; NOOPT-NEXT: je .LBB22_3 -; NOOPT-NEXT: jmp .LBB22_8 -; NOOPT-NEXT: .LBB22_8: # %entry +; NOOPT-NEXT: je .LBB22_9 +; NOOPT-NEXT: jmp .LBB22_3 +; NOOPT-NEXT: .LBB22_3: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $3, %eax -; NOOPT-NEXT: je .LBB22_4 -; NOOPT-NEXT: jmp .LBB22_9 -; NOOPT-NEXT: .LBB22_9: # %entry +; NOOPT-NEXT: je .LBB22_10 +; NOOPT-NEXT: jmp .LBB22_4 +; NOOPT-NEXT: .LBB22_4: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $100, %eax -; NOOPT-NEXT: je .LBB22_1 -; NOOPT-NEXT: jmp .LBB22_10 -; NOOPT-NEXT: .LBB22_10: # %entry +; NOOPT-NEXT: je .LBB22_7 +; NOOPT-NEXT: jmp .LBB22_5 +; NOOPT-NEXT: .LBB22_5: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $200, %eax -; NOOPT-NEXT: je .LBB22_2 -; NOOPT-NEXT: jmp .LBB22_11 -; NOOPT-NEXT: .LBB22_11: # %entry +; NOOPT-NEXT: je .LBB22_8 +; NOOPT-NEXT: jmp .LBB22_6 +; NOOPT-NEXT: .LBB22_6: # %entry ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $300, %eax # imm = 0x12C -; NOOPT-NEXT: je .LBB22_3 -; NOOPT-NEXT: jmp .LBB22_5 -; NOOPT-NEXT: .LBB22_1: # %bb0 +; NOOPT-NEXT: je .LBB22_9 +; NOOPT-NEXT: jmp .LBB22_11 +; NOOPT-NEXT: .LBB22_7: # %bb0 ; NOOPT-NEXT: xorl %edi, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB22_5 -; NOOPT-NEXT: .LBB22_2: # %bb1 +; NOOPT-NEXT: jmp .LBB22_11 +; NOOPT-NEXT: .LBB22_8: # %bb1 ; NOOPT-NEXT: movl $1, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB22_5 -; NOOPT-NEXT: .LBB22_3: # %bb2 +; NOOPT-NEXT: jmp .LBB22_11 +; NOOPT-NEXT: .LBB22_9: # %bb2 ; NOOPT-NEXT: movl $2, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB22_5 -; NOOPT-NEXT: .LBB22_4: # %bb3 +; NOOPT-NEXT: jmp .LBB22_11 +; NOOPT-NEXT: .LBB22_10: # %bb3 ; NOOPT-NEXT: movl $3, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: .LBB22_5: # %return +; NOOPT-NEXT: .LBB22_11: # %return ; NOOPT-NEXT: popq %rax ; NOOPT-NEXT: .cfi_def_cfa_offset 8 ; NOOPT-NEXT: retq @@ -2446,16 +2446,16 @@ define void @pr23738(i4 %x) { ; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: andb $15, %al ; CHECK-NEXT: cmpb $11, %al -; CHECK-NEXT: ja .LBB23_2 +; CHECK-NEXT: ja .LBB23_3 ; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: andl $15, %edi ; CHECK-NEXT: movl $2051, %eax # imm = 0x803 ; CHECK-NEXT: btl %edi, %eax -; CHECK-NEXT: jae .LBB23_2 -; CHECK-NEXT: # %bb.3: # %bb1 +; CHECK-NEXT: jae .LBB23_3 +; CHECK-NEXT: # %bb.2: # %bb1 ; CHECK-NEXT: movl $1, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB23_2: # %bb0 +; CHECK-NEXT: .LBB23_3: # %bb0 ; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL ; @@ -2467,22 +2467,22 @@ define void @pr23738(i4 %x) { ; NOOPT-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill ; NOOPT-NEXT: andb $15, %al ; NOOPT-NEXT: subb $11, %al -; NOOPT-NEXT: je .LBB23_2 -; NOOPT-NEXT: jmp .LBB23_4 -; NOOPT-NEXT: .LBB23_4: # %entry +; NOOPT-NEXT: je .LBB23_3 +; NOOPT-NEXT: jmp .LBB23_1 +; NOOPT-NEXT: .LBB23_1: # %entry ; NOOPT-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload ; NOOPT-NEXT: andb $15, %al ; NOOPT-NEXT: subb $2, %al -; NOOPT-NEXT: jb .LBB23_2 -; NOOPT-NEXT: jmp .LBB23_1 -; NOOPT-NEXT: .LBB23_1: # %bb0 +; NOOPT-NEXT: jb .LBB23_3 +; NOOPT-NEXT: jmp .LBB23_2 +; NOOPT-NEXT: .LBB23_2: # %bb0 ; NOOPT-NEXT: xorl %edi, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB23_3 -; NOOPT-NEXT: .LBB23_2: # %bb1 +; NOOPT-NEXT: jmp .LBB23_4 +; NOOPT-NEXT: .LBB23_3: # %bb1 ; NOOPT-NEXT: movl $1, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: .LBB23_3: # %return +; NOOPT-NEXT: .LBB23_4: # %return ; NOOPT-NEXT: popq %rax ; NOOPT-NEXT: .cfi_def_cfa_offset 8 ; NOOPT-NEXT: retq @@ -2507,20 +2507,20 @@ define i32 @pr27135(i32 %i) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB24_5 +; CHECK-NEXT: jne .LBB24_2 ; CHECK-NEXT: # %bb.1: # %sw ; CHECK-NEXT: movl $1, %eax ; CHECK-NEXT: addl $-96, %edi ; CHECK-NEXT: cmpl $5, %edi -; CHECK-NEXT: jbe .LBB24_2 -; CHECK-NEXT: .LBB24_5: # %end +; CHECK-NEXT: jbe .LBB24_3 +; CHECK-NEXT: .LBB24_2: # %end ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB24_2: # %sw +; CHECK-NEXT: .LBB24_3: # %sw ; CHECK-NEXT: movl $19, %eax ; CHECK-NEXT: btl %edi, %eax -; CHECK-NEXT: jae .LBB24_3 +; CHECK-NEXT: jae .LBB24_5 ; CHECK-NEXT: # %bb.4: # %sw.bb2 -; CHECK-NEXT: .LBB24_3: # %sw.bb +; CHECK-NEXT: .LBB24_5: # %sw.bb ; ; NOOPT-LABEL: pr27135: ; NOOPT: # %bb.0: # %entry @@ -2530,36 +2530,36 @@ define i32 @pr27135(i32 %i) { ; NOOPT-NEXT: testb $1, %cl ; NOOPT-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill ; NOOPT-NEXT: jne .LBB24_1 -; NOOPT-NEXT: jmp .LBB24_4 +; NOOPT-NEXT: jmp .LBB24_7 ; NOOPT-NEXT: .LBB24_1: # %sw ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: movl $1, %ecx ; NOOPT-NEXT: movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill ; NOOPT-NEXT: addl $-96, %eax ; NOOPT-NEXT: subl $2, %eax -; NOOPT-NEXT: jb .LBB24_3 -; NOOPT-NEXT: jmp .LBB24_5 -; NOOPT-NEXT: .LBB24_5: # %sw +; NOOPT-NEXT: jb .LBB24_6 +; NOOPT-NEXT: jmp .LBB24_2 +; NOOPT-NEXT: .LBB24_2: # %sw ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: addl $-98, %eax ; NOOPT-NEXT: subl $2, %eax -; NOOPT-NEXT: jb .LBB24_2 -; NOOPT-NEXT: jmp .LBB24_6 -; NOOPT-NEXT: .LBB24_6: # %sw +; NOOPT-NEXT: jb .LBB24_5 +; NOOPT-NEXT: jmp .LBB24_3 +; NOOPT-NEXT: .LBB24_3: # %sw ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: subl $100, %eax -; NOOPT-NEXT: je .LBB24_3 -; NOOPT-NEXT: jmp .LBB24_7 -; NOOPT-NEXT: .LBB24_7: # %sw +; NOOPT-NEXT: je .LBB24_6 +; NOOPT-NEXT: jmp .LBB24_4 +; NOOPT-NEXT: .LBB24_4: # %sw ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 4-byte Reload ; NOOPT-NEXT: subl $101, %ecx ; NOOPT-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill -; NOOPT-NEXT: jne .LBB24_4 -; NOOPT-NEXT: jmp .LBB24_2 -; NOOPT-NEXT: .LBB24_2: # %sw.bb -; NOOPT-NEXT: .LBB24_3: # %sw.bb2 -; NOOPT-NEXT: .LBB24_4: # %end +; NOOPT-NEXT: jne .LBB24_7 +; NOOPT-NEXT: jmp .LBB24_5 +; NOOPT-NEXT: .LBB24_5: # %sw.bb +; NOOPT-NEXT: .LBB24_6: # %sw.bb2 +; NOOPT-NEXT: .LBB24_7: # %end ; NOOPT-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload ; NOOPT-NEXT: retq entry: @@ -2590,11 +2590,11 @@ define void @range_with_unreachable_fallthrough(i32 %i) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addl $-4, %edi ; CHECK-NEXT: cmpl $3, %edi -; CHECK-NEXT: jae .LBB25_1 -; CHECK-NEXT: # %bb.2: # %bb2 +; CHECK-NEXT: jae .LBB25_2 +; CHECK-NEXT: # %bb.1: # %bb2 ; CHECK-NEXT: movl $1, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB25_1: # %bb1 +; CHECK-NEXT: .LBB25_2: # %bb1 ; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL ; @@ -2605,21 +2605,21 @@ define void @range_with_unreachable_fallthrough(i32 %i) { ; NOOPT-NEXT: movl %edi, %eax ; NOOPT-NEXT: decl %eax ; NOOPT-NEXT: subl $3, %eax -; NOOPT-NEXT: jb .LBB25_1 -; NOOPT-NEXT: jmp .LBB25_5 -; NOOPT-NEXT: .LBB25_5: # %entry -; NOOPT-NEXT: jmp .LBB25_2 -; NOOPT-NEXT: .LBB25_1: # %bb1 +; NOOPT-NEXT: jb .LBB25_2 +; NOOPT-NEXT: jmp .LBB25_1 +; NOOPT-NEXT: .LBB25_1: # %entry +; NOOPT-NEXT: jmp .LBB25_3 +; NOOPT-NEXT: .LBB25_2: # %bb1 ; NOOPT-NEXT: xorl %edi, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB25_4 -; NOOPT-NEXT: .LBB25_2: # %bb2 +; NOOPT-NEXT: jmp .LBB25_5 +; NOOPT-NEXT: .LBB25_3: # %bb2 ; NOOPT-NEXT: movl $1, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB25_4 -; NOOPT-NEXT: # %bb.3: # %default +; NOOPT-NEXT: jmp .LBB25_5 +; NOOPT-NEXT: # %bb.4: # %default ; NOOPT-NEXT: .cfi_def_cfa_offset 8 -; NOOPT-NEXT: .LBB25_4: # %return +; NOOPT-NEXT: .LBB25_5: # %return ; NOOPT-NEXT: .cfi_def_cfa_offset 16 ; NOOPT-NEXT: popq %rax ; NOOPT-NEXT: .cfi_def_cfa_offset 8 @@ -2651,33 +2651,33 @@ define void @switch_i8(i32 %a) { ; CHECK-NEXT: andl $127, %edi ; CHECK-NEXT: leal -1(%rdi), %eax ; CHECK-NEXT: cmpl $8, %eax -; CHECK-NEXT: ja .LBB26_1 -; CHECK-NEXT: # %bb.10: +; CHECK-NEXT: ja .LBB26_3 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: jmpq *.LJTI26_0(,%rax,8) -; CHECK-NEXT: .LBB26_4: # %bb0 +; CHECK-NEXT: .LBB26_2: # %bb0 ; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB26_1: +; CHECK-NEXT: .LBB26_3: ; CHECK-NEXT: cmpl $13, %edi -; CHECK-NEXT: je .LBB26_8 -; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: je .LBB26_10 +; CHECK-NEXT: # %bb.4: ; CHECK-NEXT: cmpl $42, %edi -; CHECK-NEXT: jne .LBB26_9 -; CHECK-NEXT: # %bb.3: # %bb5 +; CHECK-NEXT: jne .LBB26_6 +; CHECK-NEXT: # %bb.5: # %bb5 ; CHECK-NEXT: movl $5, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB26_9: # %return +; CHECK-NEXT: .LBB26_6: # %return ; CHECK-NEXT: retq ; CHECK-NEXT: .LBB26_7: # %bb3 ; CHECK-NEXT: movl $3, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB26_5: # %bb1 +; CHECK-NEXT: .LBB26_8: # %bb1 ; CHECK-NEXT: movl $1, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB26_6: # %bb2 +; CHECK-NEXT: .LBB26_9: # %bb2 ; CHECK-NEXT: movl $2, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL -; CHECK-NEXT: .LBB26_8: # %bb4 +; CHECK-NEXT: .LBB26_10: # %bb4 ; CHECK-NEXT: movl $4, %edi ; CHECK-NEXT: jmp g@PLT # TAILCALL ; @@ -2689,57 +2689,57 @@ define void @switch_i8(i32 %a) { ; NOOPT-NEXT: andb $127, %al ; NOOPT-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) # 1-byte Spill ; NOOPT-NEXT: subb $1, %al -; NOOPT-NEXT: je .LBB26_1 -; NOOPT-NEXT: jmp .LBB26_8 -; NOOPT-NEXT: .LBB26_8: +; NOOPT-NEXT: je .LBB26_6 +; NOOPT-NEXT: jmp .LBB26_1 +; NOOPT-NEXT: .LBB26_1: ; NOOPT-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload ; NOOPT-NEXT: subb $3, %al -; NOOPT-NEXT: je .LBB26_2 -; NOOPT-NEXT: jmp .LBB26_9 -; NOOPT-NEXT: .LBB26_9: +; NOOPT-NEXT: je .LBB26_7 +; NOOPT-NEXT: jmp .LBB26_2 +; NOOPT-NEXT: .LBB26_2: ; NOOPT-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload ; NOOPT-NEXT: subb $7, %al -; NOOPT-NEXT: je .LBB26_3 -; NOOPT-NEXT: jmp .LBB26_10 -; NOOPT-NEXT: .LBB26_10: +; NOOPT-NEXT: je .LBB26_8 +; NOOPT-NEXT: jmp .LBB26_3 +; NOOPT-NEXT: .LBB26_3: ; NOOPT-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload ; NOOPT-NEXT: subb $9, %al -; NOOPT-NEXT: je .LBB26_4 -; NOOPT-NEXT: jmp .LBB26_11 -; NOOPT-NEXT: .LBB26_11: +; NOOPT-NEXT: je .LBB26_9 +; NOOPT-NEXT: jmp .LBB26_4 +; NOOPT-NEXT: .LBB26_4: ; NOOPT-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload ; NOOPT-NEXT: subb $13, %al -; NOOPT-NEXT: je .LBB26_5 -; NOOPT-NEXT: jmp .LBB26_12 -; NOOPT-NEXT: .LBB26_12: +; NOOPT-NEXT: je .LBB26_10 +; NOOPT-NEXT: jmp .LBB26_5 +; NOOPT-NEXT: .LBB26_5: ; NOOPT-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al # 1-byte Reload ; NOOPT-NEXT: subb $42, %al -; NOOPT-NEXT: je .LBB26_6 -; NOOPT-NEXT: jmp .LBB26_7 -; NOOPT-NEXT: .LBB26_1: # %bb0 +; NOOPT-NEXT: je .LBB26_11 +; NOOPT-NEXT: jmp .LBB26_12 +; NOOPT-NEXT: .LBB26_6: # %bb0 ; NOOPT-NEXT: xorl %edi, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB26_7 -; NOOPT-NEXT: .LBB26_2: # %bb1 +; NOOPT-NEXT: jmp .LBB26_12 +; NOOPT-NEXT: .LBB26_7: # %bb1 ; NOOPT-NEXT: movl $1, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB26_7 -; NOOPT-NEXT: .LBB26_3: # %bb2 +; NOOPT-NEXT: jmp .LBB26_12 +; NOOPT-NEXT: .LBB26_8: # %bb2 ; NOOPT-NEXT: movl $2, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB26_7 -; NOOPT-NEXT: .LBB26_4: # %bb3 +; NOOPT-NEXT: jmp .LBB26_12 +; NOOPT-NEXT: .LBB26_9: # %bb3 ; NOOPT-NEXT: movl $3, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB26_7 -; NOOPT-NEXT: .LBB26_5: # %bb4 +; NOOPT-NEXT: jmp .LBB26_12 +; NOOPT-NEXT: .LBB26_10: # %bb4 ; NOOPT-NEXT: movl $4, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: jmp .LBB26_7 -; NOOPT-NEXT: .LBB26_6: # %bb5 +; NOOPT-NEXT: jmp .LBB26_12 +; NOOPT-NEXT: .LBB26_11: # %bb5 ; NOOPT-NEXT: movl $5, %edi ; NOOPT-NEXT: callq g@PLT -; NOOPT-NEXT: .LBB26_7: # %return +; NOOPT-NEXT: .LBB26_12: # %return ; NOOPT-NEXT: popq %rax ; NOOPT-NEXT: .cfi_def_cfa_offset 8 ; NOOPT-NEXT: retq diff --git a/llvm/test/CodeGen/X86/tail-dup-merge-loop-headers.ll b/llvm/test/CodeGen/X86/tail-dup-merge-loop-headers.ll index 72e4fe410e269..bcb294fe705ce 100644 --- a/llvm/test/CodeGen/X86/tail-dup-merge-loop-headers.ll +++ b/llvm/test/CodeGen/X86/tail-dup-merge-loop-headers.ll @@ -5,28 +5,28 @@ define void @tail_dup_merge_loops(i32 %a, ptr %b, ptr %c) local_unnamed_addr #0 { ; CHECK-LABEL: tail_dup_merge_loops: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: jmp .LBB0_1 +; CHECK-NEXT: jmp .LBB0_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_3: # %inner_loop_exit -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: .LBB0_1: # %inner_loop_exit +; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: incq %rsi -; CHECK-NEXT: .LBB0_1: # %outer_loop_top +; CHECK-NEXT: .LBB0_2: # %outer_loop_top ; CHECK-NEXT: # =>This Loop Header: Depth=1 ; CHECK-NEXT: # Child Loop BB0_4 Depth 2 ; CHECK-NEXT: testl %edi, %edi ; CHECK-NEXT: je .LBB0_5 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: # %bb.2: # %inner_loop_top -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: # %bb.3: # %inner_loop_top +; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 ; CHECK-NEXT: cmpb $0, (%rsi) -; CHECK-NEXT: js .LBB0_3 +; CHECK-NEXT: js .LBB0_1 ; CHECK-NEXT: .LBB0_4: # %inner_loop_latch -; CHECK-NEXT: # Parent Loop BB0_1 Depth=1 +; CHECK-NEXT: # Parent Loop BB0_2 Depth=1 ; CHECK-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-NEXT: addq $2, %rsi ; CHECK-NEXT: cmpb $0, (%rsi) ; CHECK-NEXT: jns .LBB0_4 -; CHECK-NEXT: jmp .LBB0_3 +; CHECK-NEXT: jmp .LBB0_1 ; CHECK-NEXT: .LBB0_5: # %exit ; CHECK-NEXT: retq entry: @@ -96,7 +96,7 @@ define i32 @loop_shared_header(ptr %exe, i32 %exesz, i32 %headsize, i32 %min, i3 ; CHECK-NEXT: movl $1, %ebx ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB1_12 +; CHECK-NEXT: jne .LBB1_17 ; CHECK-NEXT: # %bb.1: # %if.end19 ; CHECK-NEXT: movl (%rax), %r12d ; CHECK-NEXT: leal (,%r12,4), %ebp @@ -107,7 +107,7 @@ define i32 @loop_shared_header(ptr %exe, i32 %exesz, i32 %headsize, i32 %min, i3 ; CHECK-NEXT: movq %rax, %r14 ; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB1_12 +; CHECK-NEXT: jne .LBB1_17 ; CHECK-NEXT: # %bb.2: # %if.end50 ; CHECK-NEXT: movq %r14, %rdi ; CHECK-NEXT: movq %r15, %rdx @@ -117,62 +117,62 @@ define i32 @loop_shared_header(ptr %exe, i32 %exesz, i32 %headsize, i32 %min, i3 ; CHECK-NEXT: # %bb.3: # %shared_preheader ; CHECK-NEXT: movb $32, %cl ; CHECK-NEXT: xorl %eax, %eax -; CHECK-NEXT: jmp .LBB1_4 +; CHECK-NEXT: jmp .LBB1_5 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB1_15: # %merge_predecessor_split -; CHECK-NEXT: # in Loop: Header=BB1_4 Depth=1 +; CHECK-NEXT: .LBB1_4: # %merge_predecessor_split +; CHECK-NEXT: # in Loop: Header=BB1_5 Depth=1 ; CHECK-NEXT: movb $32, %cl -; CHECK-NEXT: .LBB1_4: # %outer_loop_header +; CHECK-NEXT: .LBB1_5: # %outer_loop_header ; CHECK-NEXT: # =>This Loop Header: Depth=1 -; CHECK-NEXT: # Child Loop BB1_8 Depth 2 +; CHECK-NEXT: # Child Loop BB1_6 Depth 2 ; CHECK-NEXT: testl %r12d, %r12d -; CHECK-NEXT: je .LBB1_5 +; CHECK-NEXT: je .LBB1_13 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB1_8: # %shared_loop_header -; CHECK-NEXT: # Parent Loop BB1_4 Depth=1 +; CHECK-NEXT: .LBB1_6: # %shared_loop_header +; CHECK-NEXT: # Parent Loop BB1_5 Depth=1 ; CHECK-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-NEXT: testq %r14, %r14 ; CHECK-NEXT: jne .LBB1_18 -; CHECK-NEXT: # %bb.9: # %inner_loop_body -; CHECK-NEXT: # in Loop: Header=BB1_8 Depth=2 +; CHECK-NEXT: # %bb.7: # %inner_loop_body +; CHECK-NEXT: # in Loop: Header=BB1_6 Depth=2 ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: je .LBB1_8 -; CHECK-NEXT: # %bb.10: # %if.end96.i -; CHECK-NEXT: # in Loop: Header=BB1_4 Depth=1 +; CHECK-NEXT: je .LBB1_6 +; CHECK-NEXT: # %bb.8: # %if.end96.i +; CHECK-NEXT: # in Loop: Header=BB1_5 Depth=1 ; CHECK-NEXT: cmpl $3, %r12d -; CHECK-NEXT: jae .LBB1_11 -; CHECK-NEXT: # %bb.13: # %if.end287.i -; CHECK-NEXT: # in Loop: Header=BB1_4 Depth=1 +; CHECK-NEXT: jae .LBB1_16 +; CHECK-NEXT: # %bb.9: # %if.end287.i +; CHECK-NEXT: # in Loop: Header=BB1_5 Depth=1 ; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: # implicit-def: $cl -; CHECK-NEXT: jne .LBB1_4 -; CHECK-NEXT: # %bb.14: # %if.end308.i -; CHECK-NEXT: # in Loop: Header=BB1_4 Depth=1 +; CHECK-NEXT: jne .LBB1_5 +; CHECK-NEXT: # %bb.10: # %if.end308.i +; CHECK-NEXT: # in Loop: Header=BB1_5 Depth=1 ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: je .LBB1_15 -; CHECK-NEXT: # %bb.16: # %if.end335.i -; CHECK-NEXT: # in Loop: Header=BB1_4 Depth=1 +; CHECK-NEXT: je .LBB1_4 +; CHECK-NEXT: # %bb.11: # %if.end335.i +; CHECK-NEXT: # in Loop: Header=BB1_5 Depth=1 ; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: testb %cl, %cl -; CHECK-NEXT: jne .LBB1_4 -; CHECK-NEXT: # %bb.17: # %merge_other -; CHECK-NEXT: # in Loop: Header=BB1_4 Depth=1 +; CHECK-NEXT: jne .LBB1_5 +; CHECK-NEXT: # %bb.12: # %merge_other +; CHECK-NEXT: # in Loop: Header=BB1_5 Depth=1 ; CHECK-NEXT: # implicit-def: $cl -; CHECK-NEXT: jmp .LBB1_4 -; CHECK-NEXT: .LBB1_5: # %while.cond.us1412.i +; CHECK-NEXT: jmp .LBB1_5 +; CHECK-NEXT: .LBB1_13: # %while.cond.us1412.i ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne .LBB1_7 -; CHECK-NEXT: # %bb.6: # %while.cond.us1412.i +; CHECK-NEXT: jne .LBB1_15 +; CHECK-NEXT: # %bb.14: # %while.cond.us1412.i ; CHECK-NEXT: decb %cl -; CHECK-NEXT: jne .LBB1_12 -; CHECK-NEXT: .LBB1_7: # %if.end41.us1436.i -; CHECK-NEXT: .LBB1_11: # %if.then99.i +; CHECK-NEXT: jne .LBB1_17 +; CHECK-NEXT: .LBB1_15: # %if.end41.us1436.i +; CHECK-NEXT: .LBB1_16: # %if.then99.i ; CHECK-NEXT: movq .str.6@GOTPCREL(%rip), %rdi ; CHECK-NEXT: xorl %ebx, %ebx ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: callq cli_dbgmsg@PLT -; CHECK-NEXT: .LBB1_12: # %cleanup +; CHECK-NEXT: .LBB1_17: # %cleanup ; CHECK-NEXT: movl %ebx, %eax ; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %r12 diff --git a/llvm/test/CodeGen/X86/tail-dup-multiple-latch-loop.ll b/llvm/test/CodeGen/X86/tail-dup-multiple-latch-loop.ll index 862f60c063804..651ef536b5182 100644 --- a/llvm/test/CodeGen/X86/tail-dup-multiple-latch-loop.ll +++ b/llvm/test/CodeGen/X86/tail-dup-multiple-latch-loop.ll @@ -132,42 +132,42 @@ define i32 @interp_switch(ptr nocapture readonly %0, i32 %1) { ; CHECK-LABEL: interp_switch: ; CHECK: # %bb.0: ; CHECK-NEXT: movl %esi, %eax -; CHECK-NEXT: jmp .LBB1_1 -; CHECK-NEXT: .LBB1_7: # in Loop: Header=BB1_1 Depth=1 +; CHECK-NEXT: jmp .LBB1_2 +; CHECK-NEXT: .LBB1_1: # in Loop: Header=BB1_2 Depth=1 ; CHECK-NEXT: addl $7, %eax ; CHECK-NEXT: incq %rdi ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: .LBB1_2: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: movzbl (%rdi), %ecx ; CHECK-NEXT: decl %ecx ; CHECK-NEXT: cmpl $5, %ecx ; CHECK-NEXT: ja .LBB1_9 -; CHECK-NEXT: # %bb.2: # in Loop: Header=BB1_1 Depth=1 +; CHECK-NEXT: # %bb.3: # in Loop: Header=BB1_2 Depth=1 ; CHECK-NEXT: jmpq *.LJTI1_0(,%rcx,8) -; CHECK-NEXT: .LBB1_3: # in Loop: Header=BB1_1 Depth=1 +; CHECK-NEXT: .LBB1_4: # in Loop: Header=BB1_2 Depth=1 ; CHECK-NEXT: incl %eax ; CHECK-NEXT: incq %rdi -; CHECK-NEXT: jmp .LBB1_1 -; CHECK-NEXT: .LBB1_5: # in Loop: Header=BB1_1 Depth=1 +; CHECK-NEXT: jmp .LBB1_2 +; CHECK-NEXT: .LBB1_5: # in Loop: Header=BB1_2 Depth=1 ; CHECK-NEXT: addl %eax, %eax ; CHECK-NEXT: incq %rdi -; CHECK-NEXT: jmp .LBB1_1 -; CHECK-NEXT: .LBB1_6: # in Loop: Header=BB1_1 Depth=1 +; CHECK-NEXT: jmp .LBB1_2 +; CHECK-NEXT: .LBB1_6: # in Loop: Header=BB1_2 Depth=1 ; CHECK-NEXT: movl %eax, %ecx ; CHECK-NEXT: shrl $31, %ecx ; CHECK-NEXT: addl %eax, %ecx ; CHECK-NEXT: sarl %ecx ; CHECK-NEXT: incq %rdi ; CHECK-NEXT: movl %ecx, %eax -; CHECK-NEXT: jmp .LBB1_1 -; CHECK-NEXT: .LBB1_4: # in Loop: Header=BB1_1 Depth=1 +; CHECK-NEXT: jmp .LBB1_2 +; CHECK-NEXT: .LBB1_7: # in Loop: Header=BB1_2 Depth=1 ; CHECK-NEXT: decl %eax ; CHECK-NEXT: incq %rdi -; CHECK-NEXT: jmp .LBB1_1 -; CHECK-NEXT: .LBB1_8: # in Loop: Header=BB1_1 Depth=1 +; CHECK-NEXT: jmp .LBB1_2 +; CHECK-NEXT: .LBB1_8: # in Loop: Header=BB1_2 Depth=1 ; CHECK-NEXT: negl %eax ; CHECK-NEXT: incq %rdi -; CHECK-NEXT: jmp .LBB1_1 +; CHECK-NEXT: jmp .LBB1_2 ; CHECK-NEXT: .LBB1_9: ; CHECK-NEXT: retq br label %3 diff --git a/llvm/test/CodeGen/X86/tail-dup-partial.ll b/llvm/test/CodeGen/X86/tail-dup-partial.ll index 292d59d3450d3..dfc926b77258a 100644 --- a/llvm/test/CodeGen/X86/tail-dup-partial.ll +++ b/llvm/test/CodeGen/X86/tail-dup-partial.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -O3 | FileCheck %s ; Function Attrs: uwtable @@ -7,74 +8,74 @@ define void @partial_tail_dup(i1 %a1, i1 %a2, ptr %a4, ptr %a5, ptr %a6, i32 %a7) #0 align 2 !prof !1 { ; CHECK-LABEL: partial_tail_dup: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_1: # %for.cond -; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: testb $1, %dil -; CHECK-NEXT: je .LBB0_3 -; CHECK-NEXT: # %bb.2: # %land.lhs.true -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 -; CHECK-NEXT: movl $10, (%rdx) -; CHECK-NEXT: movl $2, (%rcx) -; CHECK-NEXT: testl %r9d, %r9d -; CHECK-NEXT: je .LBB0_1 -; CHECK-NEXT: jmp .LBB0_8 -; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_6: # %dup2 -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 -; CHECK-NEXT: movl $2, (%rcx) -; CHECK-NEXT: testl %r9d, %r9d -; CHECK-NEXT: je .LBB0_1 -; CHECK-NEXT: jmp .LBB0_8 +; CHECK: # %bb.0: # %entry ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_3: # %if.end56 +; CHECK-NEXT: .LBB0_1: # %for.cond +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: testb $1, %dil +; CHECK-NEXT: je .LBB0_4 +; CHECK-NEXT: # %bb.2: # %land.lhs.true +; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: movl $10, (%rdx) +; CHECK-NEXT: movl $2, (%rcx) +; CHECK-NEXT: testl %r9d, %r9d +; CHECK-NEXT: je .LBB0_1 +; CHECK-NEXT: jmp .LBB0_7 +; CHECK-NEXT: .p2align 4 +; CHECK-NEXT: .LBB0_3: # %dup2 +; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: movl $2, (%rcx) +; CHECK-NEXT: testl %r9d, %r9d +; CHECK-NEXT: je .LBB0_1 +; CHECK-NEXT: jmp .LBB0_7 +; CHECK-NEXT: .p2align 4 +; CHECK-NEXT: .LBB0_4: # %if.end56 ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: testb $1, %sil -; CHECK-NEXT: je .LBB0_5 -; CHECK-NEXT: # %bb.4: # %if.then64 +; CHECK-NEXT: je .LBB0_6 +; CHECK-NEXT: # %bb.5: # %if.then64 ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: movb $1, (%r8) ; CHECK-NEXT: testl %r9d, %r9d ; CHECK-NEXT: je .LBB0_1 -; CHECK-NEXT: jmp .LBB0_8 -; CHECK-NEXT: .LBB0_5: # %if.end70 +; CHECK-NEXT: jmp .LBB0_7 +; CHECK-NEXT: .LBB0_6: # %if.end70 ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: movl $12, (%rdx) -; CHECK-NEXT: jne .LBB0_6 -; CHECK-NEXT: .LBB0_8: # %for.end +; CHECK-NEXT: jne .LBB0_3 +; CHECK-NEXT: .LBB0_7: # %for.end ; CHECK-NEXT: retq entry: br label %for.cond -for.cond: +for.cond: br i1 %a1, label %land.lhs.true, label %if.end56 -land.lhs.true: +land.lhs.true: store i32 10, ptr %a4, align 8 br label %dup2 -if.end56: +if.end56: br i1 %a2, label %if.then64, label %if.end70, !prof !2 -if.then64: +if.then64: store i8 1, ptr %a6, align 1 br label %dup1 -if.end70: +if.end70: store i32 12, ptr %a4, align 8 br i1 %a2, label %dup2, label %for.end -dup2: +dup2: store i32 2, ptr %a5, align 4 br label %dup1 -dup1: +dup1: %val = load i32, ptr %a4, align 8 %switch = icmp ult i32 %a7, 1 br i1 %switch, label %for.cond, label %for.end, !prof !3 -for.end: +for.end: ret void } diff --git a/llvm/test/CodeGen/X86/tail-dup-repeat.ll b/llvm/test/CodeGen/X86/tail-dup-repeat.ll index 7a9eb0c3fb85f..2b47e57814769 100644 --- a/llvm/test/CodeGen/X86/tail-dup-repeat.ll +++ b/llvm/test/CodeGen/X86/tail-dup-repeat.ll @@ -10,36 +10,36 @@ define void @repeated_tail_dup(i1 %a1, i1 %a2, ptr %a4, ptr %a5, ptr %a6, i32 %a7) #0 align 2 { ; CHECK-LABEL: repeated_tail_dup: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: jmp .LBB0_1 +; CHECK-NEXT: jmp .LBB0_3 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_2: # %land.lhs.true -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: .LBB0_1: # %land.lhs.true +; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1 ; CHECK-NEXT: movl $10, (%rdx) -; CHECK-NEXT: .LBB0_6: # %dup2 -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: .LBB0_2: # %dup2 +; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1 ; CHECK-NEXT: movl $2, (%rcx) ; CHECK-NEXT: testl %r9d, %r9d -; CHECK-NEXT: jne .LBB0_8 -; CHECK-NEXT: .LBB0_1: # %for.cond +; CHECK-NEXT: jne .LBB0_7 +; CHECK-NEXT: .LBB0_3: # %for.cond ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: testb $1, %dil -; CHECK-NEXT: jne .LBB0_2 -; CHECK-NEXT: # %bb.3: # %if.end56 -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: jne .LBB0_1 +; CHECK-NEXT: # %bb.4: # %if.end56 +; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1 ; CHECK-NEXT: testb $1, %sil -; CHECK-NEXT: je .LBB0_5 -; CHECK-NEXT: # %bb.4: # %if.then64 -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: je .LBB0_6 +; CHECK-NEXT: # %bb.5: # %if.then64 +; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1 ; CHECK-NEXT: movb $1, (%r8) ; CHECK-NEXT: testl %r9d, %r9d -; CHECK-NEXT: je .LBB0_1 -; CHECK-NEXT: jmp .LBB0_8 +; CHECK-NEXT: je .LBB0_3 +; CHECK-NEXT: jmp .LBB0_7 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_5: # %if.end70 -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: .LBB0_6: # %if.end70 +; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1 ; CHECK-NEXT: movl $12, (%rdx) -; CHECK-NEXT: jmp .LBB0_6 -; CHECK-NEXT: .LBB0_8: # %for.end +; CHECK-NEXT: jmp .LBB0_2 +; CHECK-NEXT: .LBB0_7: # %for.end ; CHECK-NEXT: retq entry: br label %for.cond diff --git a/llvm/test/CodeGen/X86/tail-opts.ll b/llvm/test/CodeGen/X86/tail-opts.ll index d9ab2f7d1f5fb..0b0b0835c1292 100644 --- a/llvm/test/CodeGen/X86/tail-opts.ll +++ b/llvm/test/CodeGen/X86/tail-opts.ll @@ -20,34 +20,34 @@ define dso_local void @tail_merge_me() nounwind { ; CHECK-NEXT: pushq %rax ; CHECK-NEXT: callq qux@PLT ; CHECK-NEXT: testb $1, %al -; CHECK-NEXT: je .LBB0_1 -; CHECK-NEXT: # %bb.6: # %A +; CHECK-NEXT: je .LBB0_2 +; CHECK-NEXT: # %bb.1: # %A ; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: callq bar -; CHECK-NEXT: jmp .LBB0_4 -; CHECK-NEXT: .LBB0_1: # %next +; CHECK-NEXT: jmp .LBB0_5 +; CHECK-NEXT: .LBB0_2: # %next ; CHECK-NEXT: callq qux@PLT ; CHECK-NEXT: testb $1, %al -; CHECK-NEXT: je .LBB0_3 -; CHECK-NEXT: # %bb.2: # %B +; CHECK-NEXT: je .LBB0_4 +; CHECK-NEXT: # %bb.3: # %B ; CHECK-NEXT: movl $1, %edi ; CHECK-NEXT: callq car -; CHECK-NEXT: jmp .LBB0_4 -; CHECK-NEXT: .LBB0_3: # %C +; CHECK-NEXT: jmp .LBB0_5 +; CHECK-NEXT: .LBB0_4: # %C ; CHECK-NEXT: movl $2, %edi ; CHECK-NEXT: callq dar -; CHECK-NEXT: .LBB0_4: # %M +; CHECK-NEXT: .LBB0_5: # %M ; CHECK-NEXT: movl $0, GHJK(%rip) ; CHECK-NEXT: movl $1, HABC(%rip) ; CHECK-NEXT: callq qux@PLT ; CHECK-NEXT: testb $1, %al -; CHECK-NEXT: je .LBB0_5 -; CHECK-NEXT: # %bb.7: # %return +; CHECK-NEXT: je .LBB0_7 +; CHECK-NEXT: # %bb.6: # %return ; CHECK-NEXT: movl $1000, %edi # imm = 0x3E8 ; CHECK-NEXT: callq ear ; CHECK-NEXT: popq %rax ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB0_5: # %altret +; CHECK-NEXT: .LBB0_7: # %altret ; CHECK-NEXT: movl $1001, %edi # imm = 0x3E9 ; CHECK-NEXT: callq far ; CHECK-NEXT: popq %rax @@ -105,36 +105,36 @@ define dso_local void @tail_duplicate_me() nounwind { ; CHECK-NEXT: callq choose@PLT ; CHECK-NEXT: movq %rax, %rbx ; CHECK-NEXT: testb $1, %bpl -; CHECK-NEXT: je .LBB1_1 -; CHECK-NEXT: # %bb.7: # %A +; CHECK-NEXT: je .LBB1_3 +; CHECK-NEXT: # %bb.1: # %A ; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: callq bar ; CHECK-NEXT: movl $0, GHJK(%rip) ; CHECK-NEXT: jmpq *%rbx ; CHECK-NEXT: .Ltmp0: # Block address taken -; CHECK-NEXT: .LBB1_4: # %return +; CHECK-NEXT: .LBB1_2: # %return ; CHECK-NEXT: movl $1000, %edi # imm = 0x3E8 ; CHECK-NEXT: callq ear -; CHECK-NEXT: jmp .LBB1_5 -; CHECK-NEXT: .LBB1_1: # %next +; CHECK-NEXT: jmp .LBB1_6 +; CHECK-NEXT: .LBB1_3: # %next ; CHECK-NEXT: callq qux@PLT ; CHECK-NEXT: testb $1, %al -; CHECK-NEXT: je .LBB1_3 -; CHECK-NEXT: # %bb.2: # %B +; CHECK-NEXT: je .LBB1_7 +; CHECK-NEXT: # %bb.4: # %B ; CHECK-NEXT: movl $1, %edi ; CHECK-NEXT: callq car ; CHECK-NEXT: movl $0, GHJK(%rip) ; CHECK-NEXT: jmpq *%rbx ; CHECK-NEXT: .Ltmp1: # Block address taken -; CHECK-NEXT: .LBB1_6: # %altret +; CHECK-NEXT: .LBB1_5: # %altret ; CHECK-NEXT: movl $1001, %edi # imm = 0x3E9 ; CHECK-NEXT: callq far -; CHECK-NEXT: .LBB1_5: # %return +; CHECK-NEXT: .LBB1_6: # %return ; CHECK-NEXT: addq $8, %rsp ; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %rbp ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB1_3: # %C +; CHECK-NEXT: .LBB1_7: # %C ; CHECK-NEXT: movl $2, %edi ; CHECK-NEXT: callq dar ; CHECK-NEXT: movl $0, GHJK(%rip) @@ -256,10 +256,10 @@ define fastcc void @c_expand_expr_stmt(ptr %expr) nounwind { ; CHECK-NEXT: movq 0, %rax ; CHECK-NEXT: movzbl (%rax), %ecx ; CHECK-NEXT: testl %ecx, %ecx -; CHECK-NEXT: je .LBB3_10 +; CHECK-NEXT: je .LBB3_11 ; CHECK-NEXT: # %bb.4: # %lvalue_p.exit ; CHECK-NEXT: cmpl $2, %ecx -; CHECK-NEXT: jne .LBB3_15 +; CHECK-NEXT: jne .LBB3_10 ; CHECK-NEXT: # %bb.5: # %bb.i1 ; CHECK-NEXT: movq 32(%rax), %rax ; CHECK-NEXT: movzbl 16(%rax), %ecx @@ -267,39 +267,39 @@ define fastcc void @c_expand_expr_stmt(ptr %expr) nounwind { ; CHECK-NEXT: je .LBB3_13 ; CHECK-NEXT: # %bb.6: # %bb.i1 ; CHECK-NEXT: cmpl $2, %ecx -; CHECK-NEXT: jne .LBB3_15 +; CHECK-NEXT: jne .LBB3_10 ; CHECK-NEXT: # %bb.7: # %bb.i.i ; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: callq lvalue_p@PLT ; CHECK-NEXT: testl %eax, %eax ; CHECK-NEXT: setne %al -; CHECK-NEXT: jmp .LBB3_16 +; CHECK-NEXT: jmp .LBB3_15 ; CHECK-NEXT: .LBB3_8: # %bb1 ; CHECK-NEXT: cmpb $23, %bl ; CHECK-NEXT: .LBB3_9: # %bb3 -; CHECK-NEXT: .LBB3_15: +; CHECK-NEXT: .LBB3_10: ; CHECK-NEXT: xorl %eax, %eax -; CHECK-NEXT: jmp .LBB3_16 -; CHECK-NEXT: .LBB3_10: # %bb2.i3 +; CHECK-NEXT: jmp .LBB3_15 +; CHECK-NEXT: .LBB3_11: # %bb2.i3 ; CHECK-NEXT: movq 8(%rax), %rax ; CHECK-NEXT: movzbl 16(%rax), %ecx ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: cmpl $23, %ecx -; CHECK-NEXT: je .LBB3_16 -; CHECK-NEXT: # %bb.11: # %bb2.i3 +; CHECK-NEXT: je .LBB3_15 +; CHECK-NEXT: # %bb.12: # %bb2.i3 ; CHECK-NEXT: cmpl $16, %ecx -; CHECK-NEXT: je .LBB3_16 +; CHECK-NEXT: je .LBB3_15 ; CHECK-NEXT: jmp .LBB3_9 ; CHECK-NEXT: .LBB3_13: # %bb2.i.i2 ; CHECK-NEXT: movq 8(%rax), %rax ; CHECK-NEXT: movzbl 16(%rax), %ecx ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: cmpl $16, %ecx -; CHECK-NEXT: je .LBB3_16 +; CHECK-NEXT: je .LBB3_15 ; CHECK-NEXT: # %bb.14: # %bb2.i.i2 ; CHECK-NEXT: cmpl $23, %ecx ; CHECK-NEXT: jne .LBB3_9 -; CHECK-NEXT: .LBB3_16: # %lvalue_p.exit4 +; CHECK-NEXT: .LBB3_15: # %lvalue_p.exit4 ; CHECK-NEXT: testb %bl, %bl ; CHECK-NEXT: sete %cl ; CHECK-NEXT: orb %al, %cl @@ -521,10 +521,10 @@ define dso_local void @two() nounwind optsize { ; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: je .LBB7_1 -; CHECK-NEXT: # %bb.2: # %return +; CHECK-NEXT: je .LBB7_2 +; CHECK-NEXT: # %bb.1: # %return ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB7_1: # %bb7 +; CHECK-NEXT: .LBB7_2: # %bb7 ; CHECK-NEXT: movl $0, XYZ(%rip) ; CHECK-NEXT: movl $1, XYZ(%rip) entry: @@ -562,10 +562,10 @@ define dso_local void @two_pgso() nounwind !prof !14 { ; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: je .LBB8_1 -; CHECK-NEXT: # %bb.2: # %return +; CHECK-NEXT: je .LBB8_2 +; CHECK-NEXT: # %bb.1: # %return ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB8_1: # %bb7 +; CHECK-NEXT: .LBB8_2: # %bb7 ; CHECK-NEXT: movl $0, XYZ(%rip) ; CHECK-NEXT: movl $1, XYZ(%rip) entry: @@ -605,10 +605,10 @@ define dso_local void @two_minsize() nounwind minsize { ; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: je .LBB9_1 -; CHECK-NEXT: # %bb.2: # %return +; CHECK-NEXT: je .LBB9_2 +; CHECK-NEXT: # %bb.1: # %return ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB9_1: # %bb7 +; CHECK-NEXT: .LBB9_2: # %bb7 ; CHECK-NEXT: movl $0, XYZ(%rip) ; CHECK-NEXT: movl $1, XYZ(%rip) entry: @@ -649,17 +649,17 @@ define dso_local void @two_nosize(i32 %x, i32 %y, i32 %z) nounwind { ; CHECK-NEXT: je .LBB10_3 ; CHECK-NEXT: # %bb.1: # %bby ; CHECK-NEXT: testl %esi, %esi -; CHECK-NEXT: je .LBB10_4 +; CHECK-NEXT: je .LBB10_5 ; CHECK-NEXT: # %bb.2: # %bb7 ; CHECK-NEXT: movl $0, XYZ(%rip) ; CHECK-NEXT: jmp tail_call_me # TAILCALL ; CHECK-NEXT: .LBB10_3: # %bbx ; CHECK-NEXT: cmpl $-1, %edx -; CHECK-NEXT: je .LBB10_4 -; CHECK-NEXT: # %bb.5: # %bb12 +; CHECK-NEXT: je .LBB10_5 +; CHECK-NEXT: # %bb.4: # %bb12 ; CHECK-NEXT: movl $0, XYZ(%rip) ; CHECK-NEXT: jmp tail_call_me # TAILCALL -; CHECK-NEXT: .LBB10_4: # %return +; CHECK-NEXT: .LBB10_5: # %return ; CHECK-NEXT: retq entry: %0 = icmp eq i32 %x, 0 @@ -849,25 +849,25 @@ define dso_local void @bfi_new_block_pgso(i32 %c) nounwind { ; CHECK-LABEL: bfi_new_block_pgso: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: testl %edi, %edi -; CHECK-NEXT: je .LBB14_6 +; CHECK-NEXT: je .LBB14_4 ; CHECK-NEXT: # %bb.1: # %bb1 ; CHECK-NEXT: pushq %rax ; CHECK-NEXT: cmpl $16, %edi -; CHECK-NEXT: je .LBB14_3 +; CHECK-NEXT: je .LBB14_6 ; CHECK-NEXT: # %bb.2: # %bb1 ; CHECK-NEXT: cmpl $17, %edi -; CHECK-NEXT: je .LBB14_4 -; CHECK-NEXT: # %bb.5: # %bb4 +; CHECK-NEXT: je .LBB14_7 +; CHECK-NEXT: # %bb.3: # %bb4 ; CHECK-NEXT: popq %rax ; CHECK-NEXT: jmp tail_call_me # TAILCALL -; CHECK-NEXT: .LBB14_6: # %bb5 +; CHECK-NEXT: .LBB14_4: # %bb5 ; CHECK-NEXT: cmpl $128, %edi ; CHECK-NEXT: jne tail_call_me # TAILCALL -; CHECK-NEXT: # %bb.7: # %return +; CHECK-NEXT: # %bb.5: # %return ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB14_3: # %bb3 +; CHECK-NEXT: .LBB14_6: # %bb3 ; CHECK-NEXT: movl $0, GV(%rip) -; CHECK-NEXT: .LBB14_4: # %bb4 +; CHECK-NEXT: .LBB14_7: # %bb4 ; CHECK-NEXT: callq func ; CHECK-NEXT: popq %rax ; CHECK-NEXT: jmp tail_call_me # TAILCALL diff --git a/llvm/test/CodeGen/X86/tail-threshold.ll b/llvm/test/CodeGen/X86/tail-threshold.ll index 41ea9127dfb42..a328618c9c8a5 100644 --- a/llvm/test/CodeGen/X86/tail-threshold.ll +++ b/llvm/test/CodeGen/X86/tail-threshold.ll @@ -11,15 +11,15 @@ define void @foo(i32 %xxx) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: pushq %rax ; CHECK-NEXT: cmpl $3, %edi -; CHECK-NEXT: ja .LBB0_4 +; CHECK-NEXT: ja .LBB0_3 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: jmpq *.LJTI0_0(,%rax,8) -; CHECK-NEXT: .LBB0_3: # %bb3 +; CHECK-NEXT: .LBB0_2: # %bb3 ; CHECK-NEXT: callq bar@PLT ; CHECK-NEXT: popq %rax ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB0_4: # %bb4 +; CHECK-NEXT: .LBB0_3: # %bb4 ; CHECK-NEXT: callq bar@PLT ; CHECK-NEXT: popq %rax ; CHECK-NEXT: retq diff --git a/llvm/test/CodeGen/X86/tailcall-cgp-dup.ll b/llvm/test/CodeGen/X86/tailcall-cgp-dup.ll index ecbbaf3ab362d..fe001fc492678 100644 --- a/llvm/test/CodeGen/X86/tailcall-cgp-dup.ll +++ b/llvm/test/CodeGen/X86/tailcall-cgp-dup.ll @@ -19,13 +19,13 @@ define i32 @foo(i32 %x) nounwind ssp { ; CHECK-NEXT: jmpq *%rcx ; CHECK-NEXT: LBB0_2: ## %sw.bb ; CHECK-NEXT: jmp _f1 ## TAILCALL -; CHECK-NEXT: LBB0_6: ## %sw.bb7 +; CHECK-NEXT: LBB0_3: ## %sw.bb7 ; CHECK-NEXT: jmp _f5 ## TAILCALL ; CHECK-NEXT: LBB0_4: ## %sw.bb3 ; CHECK-NEXT: jmp _f3 ## TAILCALL ; CHECK-NEXT: LBB0_5: ## %sw.bb5 ; CHECK-NEXT: jmp _f4 ## TAILCALL -; CHECK-NEXT: LBB0_3: ## %sw.bb1 +; CHECK-NEXT: LBB0_6: ## %sw.bb1 ; CHECK-NEXT: jmp _f2 ## TAILCALL ; CHECK-NEXT: LBB0_7: ## %sw.bb9 ; CHECK-NEXT: jmp _f6 ## TAILCALL @@ -35,17 +35,17 @@ define i32 @foo(i32 %x) nounwind ssp { ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: .data_region jt32 ; CHECK-NEXT: L0_0_set_2 = LBB0_2-LJTI0_0 -; CHECK-NEXT: L0_0_set_3 = LBB0_3-LJTI0_0 +; CHECK-NEXT: L0_0_set_6 = LBB0_6-LJTI0_0 ; CHECK-NEXT: L0_0_set_4 = LBB0_4-LJTI0_0 ; CHECK-NEXT: L0_0_set_5 = LBB0_5-LJTI0_0 -; CHECK-NEXT: L0_0_set_6 = LBB0_6-LJTI0_0 +; CHECK-NEXT: L0_0_set_3 = LBB0_3-LJTI0_0 ; CHECK-NEXT: L0_0_set_7 = LBB0_7-LJTI0_0 ; CHECK-NEXT: LJTI0_0: ; CHECK-NEXT: .long L0_0_set_2 -; CHECK-NEXT: .long L0_0_set_3 +; CHECK-NEXT: .long L0_0_set_6 ; CHECK-NEXT: .long L0_0_set_4 ; CHECK-NEXT: .long L0_0_set_5 -; CHECK-NEXT: .long L0_0_set_6 +; CHECK-NEXT: .long L0_0_set_3 ; CHECK-NEXT: .long L0_0_set_7 ; CHECK-NEXT: .end_data_region entry: @@ -188,12 +188,12 @@ define ptr @memset_tailc(ptr %ret_val, i64 %sz) nounwind { ; CHECK-LABEL: memset_tailc: ; CHECK: ## %bb.0: ## %entry ; CHECK-NEXT: testq %rdi, %rdi -; CHECK-NEXT: je LBB4_1 -; CHECK-NEXT: ## %bb.2: ## %if.then +; CHECK-NEXT: je LBB4_2 +; CHECK-NEXT: ## %bb.1: ## %if.then ; CHECK-NEXT: movq %rsi, %rdx ; CHECK-NEXT: xorl %esi, %esi ; CHECK-NEXT: jmp _memset ## TAILCALL -; CHECK-NEXT: LBB4_1: ## %return +; CHECK-NEXT: LBB4_2: ## %return ; CHECK-NEXT: movq %rdi, %rax ; CHECK-NEXT: retq entry: @@ -212,13 +212,13 @@ define ptr @memcpy_tailc(ptr %ret_val, i64 %sz, ptr %src) nounwind { ; CHECK-LABEL: memcpy_tailc: ; CHECK: ## %bb.0: ## %entry ; CHECK-NEXT: testq %rsi, %rsi -; CHECK-NEXT: je LBB5_1 -; CHECK-NEXT: ## %bb.2: ## %if.then +; CHECK-NEXT: je LBB5_2 +; CHECK-NEXT: ## %bb.1: ## %if.then ; CHECK-NEXT: movq %rsi, %rax ; CHECK-NEXT: movq %rdx, %rsi ; CHECK-NEXT: movq %rax, %rdx ; CHECK-NEXT: jmp _memcpy ## TAILCALL -; CHECK-NEXT: LBB5_1: ## %return +; CHECK-NEXT: LBB5_2: ## %return ; CHECK-NEXT: movq %rdx, %rax ; CHECK-NEXT: retq entry: @@ -246,15 +246,15 @@ define ptr @strcpy_legal_and_baz_illegal(ptr %arg, i64 %sz, ptr %2) nounwind { ; CHECK-NEXT: movq %rsi, %rdi ; CHECK-NEXT: callq _malloc ; CHECK-NEXT: testq %r15, %r15 -; CHECK-NEXT: je LBB6_1 -; CHECK-NEXT: ## %bb.2: ## %if.then +; CHECK-NEXT: je LBB6_2 +; CHECK-NEXT: ## %bb.1: ## %if.then ; CHECK-NEXT: movq %rax, %rdi ; CHECK-NEXT: movq %rbx, %rsi ; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %r14 ; CHECK-NEXT: popq %r15 ; CHECK-NEXT: jmp _strcpy ## TAILCALL -; CHECK-NEXT: LBB6_1: ## %if.else +; CHECK-NEXT: LBB6_2: ## %if.else ; CHECK-NEXT: movq %r14, %rdi ; CHECK-NEXT: movq %rbx, %rsi ; CHECK-NEXT: callq _baz diff --git a/llvm/test/CodeGen/X86/tailcc-ssp.ll b/llvm/test/CodeGen/X86/tailcc-ssp.ll index ac5dda7d69bde..61365e990b98e 100644 --- a/llvm/test/CodeGen/X86/tailcc-ssp.ll +++ b/llvm/test/CodeGen/X86/tailcc-ssp.ll @@ -17,8 +17,8 @@ define tailcc void @tailcall_frame(ptr %0, i64 %1) sspreq { ; WINDOWS-NEXT: xorq %rsp, %rax ; WINDOWS-NEXT: movq __security_cookie(%rip), %rcx ; WINDOWS-NEXT: cmpq %rax, %rcx -; WINDOWS-NEXT: jne .LBB0_1 -; WINDOWS-NEXT: # %bb.2: +; WINDOWS-NEXT: jne .LBB0_2 +; WINDOWS-NEXT: # %bb.1: ; WINDOWS-NEXT: xorl %ecx, %ecx ; WINDOWS-NEXT: xorl %edx, %edx ; WINDOWS-NEXT: xorl %r8d, %r8d @@ -26,7 +26,7 @@ define tailcc void @tailcall_frame(ptr %0, i64 %1) sspreq { ; WINDOWS-NEXT: addq $56, %rsp ; WINDOWS-NEXT: .seh_endepilogue ; WINDOWS-NEXT: jmp h # TAILCALL -; WINDOWS-NEXT: .LBB0_1: +; WINDOWS-NEXT: .LBB0_2: ; WINDOWS-NEXT: movq {{[0-9]+}}(%rsp), %rcx ; WINDOWS-NEXT: xorq %rsp, %rcx ; WINDOWS-NEXT: callq __security_check_cookie @@ -71,13 +71,13 @@ define void @tailcall_unrelated_frame() sspreq { ; WINDOWS-NEXT: xorq %rsp, %rax ; WINDOWS-NEXT: movq __security_cookie(%rip), %rcx ; WINDOWS-NEXT: cmpq %rax, %rcx -; WINDOWS-NEXT: jne .LBB1_1 -; WINDOWS-NEXT: # %bb.2: +; WINDOWS-NEXT: jne .LBB1_2 +; WINDOWS-NEXT: # %bb.1: ; WINDOWS-NEXT: .seh_startepilogue ; WINDOWS-NEXT: addq $40, %rsp ; WINDOWS-NEXT: .seh_endepilogue ; WINDOWS-NEXT: jmp bar # TAILCALL -; WINDOWS-NEXT: .LBB1_1: +; WINDOWS-NEXT: .LBB1_2: ; WINDOWS-NEXT: movq {{[0-9]+}}(%rsp), %rcx ; WINDOWS-NEXT: xorq %rsp, %rcx ; WINDOWS-NEXT: callq __security_check_cookie diff --git a/llvm/test/CodeGen/X86/test-shrink.ll b/llvm/test/CodeGen/X86/test-shrink.ll index 3ee6f6fb70f6b..500520c471ae8 100644 --- a/llvm/test/CodeGen/X86/test-shrink.ll +++ b/llvm/test/CodeGen/X86/test-shrink.ll @@ -261,10 +261,10 @@ define void @g64x16(i64 inreg %x) nounwind { ; CHECK-LINUX64-LABEL: g64x16: ; CHECK-LINUX64: # %bb.0: ; CHECK-LINUX64-NEXT: testl $32896, %edi # imm = 0x8080 -; CHECK-LINUX64-NEXT: je .LBB6_1 -; CHECK-LINUX64-NEXT: # %bb.2: # %no +; CHECK-LINUX64-NEXT: je .LBB6_2 +; CHECK-LINUX64-NEXT: # %bb.1: # %no ; CHECK-LINUX64-NEXT: retq -; CHECK-LINUX64-NEXT: .LBB6_1: # %yes +; CHECK-LINUX64-NEXT: .LBB6_2: # %yes ; CHECK-LINUX64-NEXT: pushq %rax ; CHECK-LINUX64-NEXT: callq bar@PLT ; CHECK-LINUX64-NEXT: popq %rax @@ -274,11 +274,11 @@ define void @g64x16(i64 inreg %x) nounwind { ; CHECK-WIN32-64: # %bb.0: ; CHECK-WIN32-64-NEXT: subq $40, %rsp ; CHECK-WIN32-64-NEXT: testl $32896, %ecx # imm = 0x8080 -; CHECK-WIN32-64-NEXT: je .LBB6_1 -; CHECK-WIN32-64-NEXT: # %bb.2: # %no +; CHECK-WIN32-64-NEXT: je .LBB6_2 +; CHECK-WIN32-64-NEXT: # %bb.1: # %no ; CHECK-WIN32-64-NEXT: addq $40, %rsp ; CHECK-WIN32-64-NEXT: retq -; CHECK-WIN32-64-NEXT: .LBB6_1: # %yes +; CHECK-WIN32-64-NEXT: .LBB6_2: # %yes ; CHECK-WIN32-64-NEXT: callq bar ; CHECK-WIN32-64-NEXT: addq $40, %rsp ; CHECK-WIN32-64-NEXT: retq @@ -286,10 +286,10 @@ define void @g64x16(i64 inreg %x) nounwind { ; CHECK-X86-LABEL: g64x16: ; CHECK-X86: # %bb.0: ; CHECK-X86-NEXT: testl $32896, %eax # imm = 0x8080 -; CHECK-X86-NEXT: je .LBB6_1 -; CHECK-X86-NEXT: # %bb.2: # %no +; CHECK-X86-NEXT: je .LBB6_2 +; CHECK-X86-NEXT: # %bb.1: # %no ; CHECK-X86-NEXT: retl -; CHECK-X86-NEXT: .LBB6_1: # %yes +; CHECK-X86-NEXT: .LBB6_2: # %yes ; CHECK-X86-NEXT: calll bar@PLT ; CHECK-X86-NEXT: retl %t = and i64 %x, 32896 @@ -307,10 +307,10 @@ define void @g64x16minsize(i64 inreg %x) nounwind minsize { ; CHECK-LINUX64-LABEL: g64x16minsize: ; CHECK-LINUX64: # %bb.0: ; CHECK-LINUX64-NEXT: testw $-32640, %di # imm = 0x8080 -; CHECK-LINUX64-NEXT: je .LBB7_1 -; CHECK-LINUX64-NEXT: # %bb.2: # %no +; CHECK-LINUX64-NEXT: je .LBB7_2 +; CHECK-LINUX64-NEXT: # %bb.1: # %no ; CHECK-LINUX64-NEXT: retq -; CHECK-LINUX64-NEXT: .LBB7_1: # %yes +; CHECK-LINUX64-NEXT: .LBB7_2: # %yes ; CHECK-LINUX64-NEXT: pushq %rax ; CHECK-LINUX64-NEXT: callq bar@PLT ; CHECK-LINUX64-NEXT: popq %rax @@ -330,10 +330,10 @@ define void @g64x16minsize(i64 inreg %x) nounwind minsize { ; CHECK-X86-LABEL: g64x16minsize: ; CHECK-X86: # %bb.0: ; CHECK-X86-NEXT: testw $-32640, %ax # imm = 0x8080 -; CHECK-X86-NEXT: je .LBB7_1 -; CHECK-X86-NEXT: # %bb.2: # %no +; CHECK-X86-NEXT: je .LBB7_2 +; CHECK-X86-NEXT: # %bb.1: # %no ; CHECK-X86-NEXT: retl -; CHECK-X86-NEXT: .LBB7_1: # %yes +; CHECK-X86-NEXT: .LBB7_2: # %yes ; CHECK-X86-NEXT: calll bar@PLT ; CHECK-X86-NEXT: retl %t = and i64 %x, 32896 @@ -351,10 +351,10 @@ define void @g32x16(i32 inreg %x) nounwind { ; CHECK-LINUX64-LABEL: g32x16: ; CHECK-LINUX64: # %bb.0: ; CHECK-LINUX64-NEXT: testl $32896, %edi # imm = 0x8080 -; CHECK-LINUX64-NEXT: je .LBB8_1 -; CHECK-LINUX64-NEXT: # %bb.2: # %no +; CHECK-LINUX64-NEXT: je .LBB8_2 +; CHECK-LINUX64-NEXT: # %bb.1: # %no ; CHECK-LINUX64-NEXT: retq -; CHECK-LINUX64-NEXT: .LBB8_1: # %yes +; CHECK-LINUX64-NEXT: .LBB8_2: # %yes ; CHECK-LINUX64-NEXT: pushq %rax ; CHECK-LINUX64-NEXT: callq bar@PLT ; CHECK-LINUX64-NEXT: popq %rax @@ -364,11 +364,11 @@ define void @g32x16(i32 inreg %x) nounwind { ; CHECK-WIN32-64: # %bb.0: ; CHECK-WIN32-64-NEXT: subq $40, %rsp ; CHECK-WIN32-64-NEXT: testl $32896, %ecx # imm = 0x8080 -; CHECK-WIN32-64-NEXT: je .LBB8_1 -; CHECK-WIN32-64-NEXT: # %bb.2: # %no +; CHECK-WIN32-64-NEXT: je .LBB8_2 +; CHECK-WIN32-64-NEXT: # %bb.1: # %no ; CHECK-WIN32-64-NEXT: addq $40, %rsp ; CHECK-WIN32-64-NEXT: retq -; CHECK-WIN32-64-NEXT: .LBB8_1: # %yes +; CHECK-WIN32-64-NEXT: .LBB8_2: # %yes ; CHECK-WIN32-64-NEXT: callq bar ; CHECK-WIN32-64-NEXT: addq $40, %rsp ; CHECK-WIN32-64-NEXT: retq @@ -376,10 +376,10 @@ define void @g32x16(i32 inreg %x) nounwind { ; CHECK-X86-LABEL: g32x16: ; CHECK-X86: # %bb.0: ; CHECK-X86-NEXT: testl $32896, %eax # imm = 0x8080 -; CHECK-X86-NEXT: je .LBB8_1 -; CHECK-X86-NEXT: # %bb.2: # %no +; CHECK-X86-NEXT: je .LBB8_2 +; CHECK-X86-NEXT: # %bb.1: # %no ; CHECK-X86-NEXT: retl -; CHECK-X86-NEXT: .LBB8_1: # %yes +; CHECK-X86-NEXT: .LBB8_2: # %yes ; CHECK-X86-NEXT: calll bar@PLT ; CHECK-X86-NEXT: retl %t = and i32 %x, 32896 @@ -397,10 +397,10 @@ define void @g32x16minsize(i32 inreg %x) nounwind minsize { ; CHECK-LINUX64-LABEL: g32x16minsize: ; CHECK-LINUX64: # %bb.0: ; CHECK-LINUX64-NEXT: testw $-32640, %di # imm = 0x8080 -; CHECK-LINUX64-NEXT: je .LBB9_1 -; CHECK-LINUX64-NEXT: # %bb.2: # %no +; CHECK-LINUX64-NEXT: je .LBB9_2 +; CHECK-LINUX64-NEXT: # %bb.1: # %no ; CHECK-LINUX64-NEXT: retq -; CHECK-LINUX64-NEXT: .LBB9_1: # %yes +; CHECK-LINUX64-NEXT: .LBB9_2: # %yes ; CHECK-LINUX64-NEXT: pushq %rax ; CHECK-LINUX64-NEXT: callq bar@PLT ; CHECK-LINUX64-NEXT: popq %rax @@ -420,10 +420,10 @@ define void @g32x16minsize(i32 inreg %x) nounwind minsize { ; CHECK-X86-LABEL: g32x16minsize: ; CHECK-X86: # %bb.0: ; CHECK-X86-NEXT: testw $-32640, %ax # imm = 0x8080 -; CHECK-X86-NEXT: je .LBB9_1 -; CHECK-X86-NEXT: # %bb.2: # %no +; CHECK-X86-NEXT: je .LBB9_2 +; CHECK-X86-NEXT: # %bb.1: # %no ; CHECK-X86-NEXT: retl -; CHECK-X86-NEXT: .LBB9_1: # %yes +; CHECK-X86-NEXT: .LBB9_2: # %yes ; CHECK-X86-NEXT: calll bar@PLT ; CHECK-X86-NEXT: retl %t = and i32 %x, 32896 @@ -441,10 +441,10 @@ define void @g64x32(i64 inreg %x) nounwind { ; CHECK-LINUX64-LABEL: g64x32: ; CHECK-LINUX64: # %bb.0: ; CHECK-LINUX64-NEXT: testl $268468352, %edi # imm = 0x10008080 -; CHECK-LINUX64-NEXT: je .LBB10_1 -; CHECK-LINUX64-NEXT: # %bb.2: # %no +; CHECK-LINUX64-NEXT: je .LBB10_2 +; CHECK-LINUX64-NEXT: # %bb.1: # %no ; CHECK-LINUX64-NEXT: retq -; CHECK-LINUX64-NEXT: .LBB10_1: # %yes +; CHECK-LINUX64-NEXT: .LBB10_2: # %yes ; CHECK-LINUX64-NEXT: pushq %rax ; CHECK-LINUX64-NEXT: callq bar@PLT ; CHECK-LINUX64-NEXT: popq %rax @@ -454,11 +454,11 @@ define void @g64x32(i64 inreg %x) nounwind { ; CHECK-WIN32-64: # %bb.0: ; CHECK-WIN32-64-NEXT: subq $40, %rsp ; CHECK-WIN32-64-NEXT: testl $268468352, %ecx # imm = 0x10008080 -; CHECK-WIN32-64-NEXT: je .LBB10_1 -; CHECK-WIN32-64-NEXT: # %bb.2: # %no +; CHECK-WIN32-64-NEXT: je .LBB10_2 +; CHECK-WIN32-64-NEXT: # %bb.1: # %no ; CHECK-WIN32-64-NEXT: addq $40, %rsp ; CHECK-WIN32-64-NEXT: retq -; CHECK-WIN32-64-NEXT: .LBB10_1: # %yes +; CHECK-WIN32-64-NEXT: .LBB10_2: # %yes ; CHECK-WIN32-64-NEXT: callq bar ; CHECK-WIN32-64-NEXT: addq $40, %rsp ; CHECK-WIN32-64-NEXT: retq @@ -466,10 +466,10 @@ define void @g64x32(i64 inreg %x) nounwind { ; CHECK-X86-LABEL: g64x32: ; CHECK-X86: # %bb.0: ; CHECK-X86-NEXT: testl $268468352, %eax # imm = 0x10008080 -; CHECK-X86-NEXT: je .LBB10_1 -; CHECK-X86-NEXT: # %bb.2: # %no +; CHECK-X86-NEXT: je .LBB10_2 +; CHECK-X86-NEXT: # %bb.1: # %no ; CHECK-X86-NEXT: retl -; CHECK-X86-NEXT: .LBB10_1: # %yes +; CHECK-X86-NEXT: .LBB10_2: # %yes ; CHECK-X86-NEXT: calll bar@PLT ; CHECK-X86-NEXT: retl %t = and i64 %x, 268468352 @@ -487,10 +487,10 @@ define void @truncand32(i16 inreg %x) nounwind { ; CHECK-LINUX64-LABEL: truncand32: ; CHECK-LINUX64: # %bb.0: ; CHECK-LINUX64-NEXT: testl $2049, %edi # imm = 0x801 -; CHECK-LINUX64-NEXT: je .LBB11_1 -; CHECK-LINUX64-NEXT: # %bb.2: # %no +; CHECK-LINUX64-NEXT: je .LBB11_2 +; CHECK-LINUX64-NEXT: # %bb.1: # %no ; CHECK-LINUX64-NEXT: retq -; CHECK-LINUX64-NEXT: .LBB11_1: # %yes +; CHECK-LINUX64-NEXT: .LBB11_2: # %yes ; CHECK-LINUX64-NEXT: pushq %rax ; CHECK-LINUX64-NEXT: callq bar@PLT ; CHECK-LINUX64-NEXT: popq %rax @@ -501,11 +501,11 @@ define void @truncand32(i16 inreg %x) nounwind { ; CHECK-WIN32-64-NEXT: subq $40, %rsp ; CHECK-WIN32-64-NEXT: # kill: def $cx killed $cx def $ecx ; CHECK-WIN32-64-NEXT: testl $2049, %ecx # imm = 0x801 -; CHECK-WIN32-64-NEXT: je .LBB11_1 -; CHECK-WIN32-64-NEXT: # %bb.2: # %no +; CHECK-WIN32-64-NEXT: je .LBB11_2 +; CHECK-WIN32-64-NEXT: # %bb.1: # %no ; CHECK-WIN32-64-NEXT: addq $40, %rsp ; CHECK-WIN32-64-NEXT: retq -; CHECK-WIN32-64-NEXT: .LBB11_1: # %yes +; CHECK-WIN32-64-NEXT: .LBB11_2: # %yes ; CHECK-WIN32-64-NEXT: callq bar ; CHECK-WIN32-64-NEXT: addq $40, %rsp ; CHECK-WIN32-64-NEXT: retq @@ -513,10 +513,10 @@ define void @truncand32(i16 inreg %x) nounwind { ; CHECK-X86-LABEL: truncand32: ; CHECK-X86: # %bb.0: ; CHECK-X86-NEXT: testl $2049, %eax # imm = 0x801 -; CHECK-X86-NEXT: je .LBB11_1 -; CHECK-X86-NEXT: # %bb.2: # %no +; CHECK-X86-NEXT: je .LBB11_2 +; CHECK-X86-NEXT: # %bb.1: # %no ; CHECK-X86-NEXT: retl -; CHECK-X86-NEXT: .LBB11_1: # %yes +; CHECK-X86-NEXT: .LBB11_2: # %yes ; CHECK-X86-NEXT: calll bar@PLT ; CHECK-X86-NEXT: retl %t = and i16 %x, 2049 @@ -534,10 +534,10 @@ define void @testw(i16 inreg %x) nounwind minsize { ; CHECK-LINUX64-LABEL: testw: ; CHECK-LINUX64: # %bb.0: ; CHECK-LINUX64-NEXT: testw $2049, %di # imm = 0x801 -; CHECK-LINUX64-NEXT: je .LBB12_1 -; CHECK-LINUX64-NEXT: # %bb.2: # %no +; CHECK-LINUX64-NEXT: je .LBB12_2 +; CHECK-LINUX64-NEXT: # %bb.1: # %no ; CHECK-LINUX64-NEXT: retq -; CHECK-LINUX64-NEXT: .LBB12_1: # %yes +; CHECK-LINUX64-NEXT: .LBB12_2: # %yes ; CHECK-LINUX64-NEXT: pushq %rax ; CHECK-LINUX64-NEXT: callq bar@PLT ; CHECK-LINUX64-NEXT: popq %rax @@ -557,10 +557,10 @@ define void @testw(i16 inreg %x) nounwind minsize { ; CHECK-X86-LABEL: testw: ; CHECK-X86: # %bb.0: ; CHECK-X86-NEXT: testw $2049, %ax # imm = 0x801 -; CHECK-X86-NEXT: je .LBB12_1 -; CHECK-X86-NEXT: # %bb.2: # %no +; CHECK-X86-NEXT: je .LBB12_2 +; CHECK-X86-NEXT: # %bb.1: # %no ; CHECK-X86-NEXT: retl -; CHECK-X86-NEXT: .LBB12_1: # %yes +; CHECK-X86-NEXT: .LBB12_2: # %yes ; CHECK-X86-NEXT: calll bar@PLT ; CHECK-X86-NEXT: retl %t = and i16 %x, 2049 diff --git a/llvm/test/CodeGen/X86/testb-je-fusion.ll b/llvm/test/CodeGen/X86/testb-je-fusion.ll index d4a2525744da3..a1e2fad5fa666 100644 --- a/llvm/test/CodeGen/X86/testb-je-fusion.ll +++ b/llvm/test/CodeGen/X86/testb-je-fusion.ll @@ -54,11 +54,11 @@ define i32 @macrofuse_cmp_je(i32 %flags, ptr %p) nounwind { ; NOFUSION: # %bb.0: # %entry ; NOFUSION-NEXT: cmpl $512, %edi # imm = 0x200 ; NOFUSION-NEXT: movb $1, (%rsi) -; NOFUSION-NEXT: je .LBB1_1 -; NOFUSION-NEXT: # %bb.2: # %if.then +; NOFUSION-NEXT: je .LBB1_2 +; NOFUSION-NEXT: # %bb.1: # %if.then ; NOFUSION-NEXT: movl $1, %eax ; NOFUSION-NEXT: retq -; NOFUSION-NEXT: .LBB1_1: +; NOFUSION-NEXT: .LBB1_2: ; NOFUSION-NEXT: xorl %eax, %eax ; NOFUSION-NEXT: retq ; @@ -66,11 +66,11 @@ define i32 @macrofuse_cmp_je(i32 %flags, ptr %p) nounwind { ; FUSION: # %bb.0: # %entry ; FUSION-NEXT: movb $1, (%rsi) ; FUSION-NEXT: cmpl $512, %edi # imm = 0x200 -; FUSION-NEXT: je .LBB1_1 -; FUSION-NEXT: # %bb.2: # %if.then +; FUSION-NEXT: je .LBB1_2 +; FUSION-NEXT: # %bb.1: # %if.then ; FUSION-NEXT: movl $1, %eax ; FUSION-NEXT: retq -; FUSION-NEXT: .LBB1_1: +; FUSION-NEXT: .LBB1_2: ; FUSION-NEXT: xorl %eax, %eax ; FUSION-NEXT: retq entry: diff --git a/llvm/test/CodeGen/X86/throws-cfi-fp.ll b/llvm/test/CodeGen/X86/throws-cfi-fp.ll index 1ad12823ec67e..6b4723940122d 100644 --- a/llvm/test/CodeGen/X86/throws-cfi-fp.ll +++ b/llvm/test/CodeGen/X86/throws-cfi-fp.ll @@ -17,7 +17,7 @@ define void @_Z6throwsv() #0 personality ptr @__gxx_personality_v0 { ; CHECK: popq %rbp ; CHECK-NEXT: .cfi_def_cfa %rsp, 8 ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB0_1: +; CHECK-NEXT: .L{{BB[0-9]+_[0-9]+}}: ; CHECK-NEXT: .cfi_def_cfa %rbp, 16 ; PEI-LABEL: name: _Z6throwsv @@ -29,7 +29,7 @@ define void @_Z6throwsv() #0 personality ptr @__gxx_personality_v0 { ; PEI-NEXT: frame-setup PUSH64r killed $rbx, implicit-def $rsp, implicit $rsp ; PEI-NEXT: frame-setup PUSH64r undef $rax, implicit-def $rsp, implicit $rsp ; PEI-NEXT: {{^ +}}CFI_INSTRUCTION offset $rbx, -24 -; PEI: bb.4.try.cont: +; PEI: bb.{{[0-9]+}}.try.cont: ; PEI-NEXT: $rsp = frame-destroy ADD64ri32 $rsp, 8, implicit-def dead $eflags ; PEI-NEXT: $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp ; PEI-NEXT: $rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp diff --git a/llvm/test/CodeGen/X86/throws-cfi-no-fp.ll b/llvm/test/CodeGen/X86/throws-cfi-no-fp.ll index 6663d91b75355..0b355cd2e2306 100644 --- a/llvm/test/CodeGen/X86/throws-cfi-no-fp.ll +++ b/llvm/test/CodeGen/X86/throws-cfi-no-fp.ll @@ -16,7 +16,7 @@ define void @_Z6throwsv() personality ptr @__gxx_personality_v0 { ; CHECK: popq %rbx ; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB0_1: +; CHECK-NEXT: .LBB0_2: ; CHECK-NEXT: .cfi_def_cfa_offset 16 entry: diff --git a/llvm/test/CodeGen/X86/twoaddr-lea.ll b/llvm/test/CodeGen/X86/twoaddr-lea.ll index 3ad3e9a0e7655..6e12eec2abfd5 100644 --- a/llvm/test/CodeGen/X86/twoaddr-lea.ll +++ b/llvm/test/CodeGen/X86/twoaddr-lea.ll @@ -70,51 +70,51 @@ define void @ham() { ; CHECK-NEXT: movq _global@GOTPCREL(%rip), %rdx ; CHECK-NEXT: movq _global2@GOTPCREL(%rip), %rsi ; CHECK-NEXT: testb %cl, %cl -; CHECK-NEXT: je LBB3_2 +; CHECK-NEXT: je LBB3_4 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: LBB3_6: ## %bb2 +; CHECK-NEXT: LBB3_1: ## %bb2 ; CHECK-NEXT: ## =>This Loop Header: Depth=1 -; CHECK-NEXT: ## Child Loop BB3_7 Depth 2 +; CHECK-NEXT: ## Child Loop BB3_2 Depth 2 ; CHECK-NEXT: movl (%rdx), %edi ; CHECK-NEXT: leal (%rdi,%rax), %r8d ; CHECK-NEXT: movslq %r8d, %r8 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: LBB3_7: ## %bb6 -; CHECK-NEXT: ## Parent Loop BB3_6 Depth=1 +; CHECK-NEXT: LBB3_2: ## %bb6 +; CHECK-NEXT: ## Parent Loop BB3_1 Depth=1 ; CHECK-NEXT: ## => This Inner Loop Header: Depth=2 ; CHECK-NEXT: movq %rax, (%rsi) ; CHECK-NEXT: movq %r8, (%rsi) ; CHECK-NEXT: movl %edi, (%rdx) ; CHECK-NEXT: testb %cl, %cl -; CHECK-NEXT: jne LBB3_7 -; CHECK-NEXT: ## %bb.8: ## %bb9 -; CHECK-NEXT: ## in Loop: Header=BB3_6 Depth=1 +; CHECK-NEXT: jne LBB3_2 +; CHECK-NEXT: ## %bb.3: ## %bb9 +; CHECK-NEXT: ## in Loop: Header=BB3_1 Depth=1 ; CHECK-NEXT: addq $4, %rax ; CHECK-NEXT: testb %cl, %cl -; CHECK-NEXT: jne LBB3_6 -; CHECK-NEXT: LBB3_2: ## %bb3.preheader +; CHECK-NEXT: jne LBB3_1 +; CHECK-NEXT: LBB3_4: ## %bb3.preheader ; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: LBB3_3: ## %bb3 +; CHECK-NEXT: LBB3_5: ## %bb3 ; CHECK-NEXT: ## =>This Loop Header: Depth=1 -; CHECK-NEXT: ## Child Loop BB3_4 Depth 2 +; CHECK-NEXT: ## Child Loop BB3_6 Depth 2 ; CHECK-NEXT: movq %rcx, %rdx ; CHECK-NEXT: addq $4, %rcx ; CHECK-NEXT: movl %eax, %esi ; CHECK-NEXT: subl %edx, %esi ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: LBB3_4: ## %bb4 -; CHECK-NEXT: ## Parent Loop BB3_3 Depth=1 +; CHECK-NEXT: LBB3_6: ## %bb4 +; CHECK-NEXT: ## Parent Loop BB3_5 Depth=1 ; CHECK-NEXT: ## => This Inner Loop Header: Depth=2 ; CHECK-NEXT: testl %esi, %esi -; CHECK-NEXT: jne LBB3_9 -; CHECK-NEXT: ## %bb.5: ## %bb5 -; CHECK-NEXT: ## in Loop: Header=BB3_4 Depth=2 +; CHECK-NEXT: jne LBB3_8 +; CHECK-NEXT: ## %bb.7: ## %bb5 +; CHECK-NEXT: ## in Loop: Header=BB3_6 Depth=2 ; CHECK-NEXT: incq %rdx ; CHECK-NEXT: cmpq %rcx, %rdx -; CHECK-NEXT: jl LBB3_4 -; CHECK-NEXT: jmp LBB3_3 -; CHECK-NEXT: LBB3_9: ## %bb8 +; CHECK-NEXT: jl LBB3_6 +; CHECK-NEXT: jmp LBB3_5 +; CHECK-NEXT: LBB3_8: ## %bb8 ; CHECK-NEXT: ud2 bb: br label %bb1 diff --git a/llvm/test/CodeGen/X86/ubsan-trap-merge.ll b/llvm/test/CodeGen/X86/ubsan-trap-merge.ll index 878260cbcaec2..48331b57e6094 100644 --- a/llvm/test/CodeGen/X86/ubsan-trap-merge.ll +++ b/llvm/test/CodeGen/X86/ubsan-trap-merge.ll @@ -17,11 +17,11 @@ define dso_local range(i32 -2147483523, -2147483648) i32 @f(i32 noundef %x) loca ; CHECK-LABEL: f: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addl $125, %edi -; CHECK-NEXT: jo .LBB0_1 -; CHECK-NEXT: # %bb.2: # %cont +; CHECK-NEXT: jo .LBB0_2 +; CHECK-NEXT: # %bb.1: # %cont ; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB0_1: # %trap +; CHECK-NEXT: .LBB0_2: # %trap ; CHECK-NEXT: ud1l (%eax), %eax entry: %0 = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %x, i32 125), !nosanitize !5 @@ -48,11 +48,11 @@ define dso_local range(i32 -2147483521, -2147483648) i32 @g(i32 noundef %x) loca ; CHECK-LABEL: g: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addl $127, %edi -; CHECK-NEXT: jo .LBB1_1 -; CHECK-NEXT: # %bb.2: # %cont +; CHECK-NEXT: jo .LBB1_2 +; CHECK-NEXT: # %bb.1: # %cont ; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB1_1: # %trap +; CHECK-NEXT: .LBB1_2: # %trap ; CHECK-NEXT: ud1l (%eax), %eax entry: %0 = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %x, i32 127), !nosanitize !5 diff --git a/llvm/test/CodeGen/X86/ubsan-trap-nomerge.ll b/llvm/test/CodeGen/X86/ubsan-trap-nomerge.ll index ffcbaac382d56..c90342be7f5db 100644 --- a/llvm/test/CodeGen/X86/ubsan-trap-nomerge.ll +++ b/llvm/test/CodeGen/X86/ubsan-trap-nomerge.ll @@ -16,11 +16,11 @@ define dso_local range(i32 -2147483523, -2147483648) i32 @f(i32 noundef %x) loca ; CHECK-LABEL: f: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addl $125, %edi -; CHECK-NEXT: jo .LBB0_1 -; CHECK-NEXT: # %bb.2: # %cont +; CHECK-NEXT: jo .LBB0_2 +; CHECK-NEXT: # %bb.1: # %cont ; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB0_1: # %trap +; CHECK-NEXT: .LBB0_2: # %trap ; CHECK-NEXT: ud1l (%eax), %eax entry: %0 = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %x, i32 125), !nosanitize !5 @@ -47,11 +47,11 @@ define dso_local range(i32 -2147483521, -2147483648) i32 @g(i32 noundef %x) loca ; CHECK-LABEL: g: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addl $127, %edi -; CHECK-NEXT: jo .LBB1_1 -; CHECK-NEXT: # %bb.2: # %cont +; CHECK-NEXT: jo .LBB1_2 +; CHECK-NEXT: # %bb.1: # %cont ; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB1_1: # %trap +; CHECK-NEXT: .LBB1_2: # %trap ; CHECK-NEXT: ud1l (%eax), %eax entry: %0 = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %x, i32 127), !nosanitize !5 diff --git a/llvm/test/CodeGen/X86/uint64-to-float.ll b/llvm/test/CodeGen/X86/uint64-to-float.ll index 03a8171589622..e3b26cdf7986c 100644 --- a/llvm/test/CodeGen/X86/uint64-to-float.ll +++ b/llvm/test/CodeGen/X86/uint64-to-float.ll @@ -32,11 +32,11 @@ define float @test(i64 %a) nounwind { ; X64-LABEL: test: ; X64: # %bb.0: # %entry ; X64-NEXT: testq %rdi, %rdi -; X64-NEXT: js .LBB0_1 -; X64-NEXT: # %bb.2: # %entry +; X64-NEXT: js .LBB0_2 +; X64-NEXT: # %bb.1: # %entry ; X64-NEXT: cvtsi2ss %rdi, %xmm0 ; X64-NEXT: retq -; X64-NEXT: .LBB0_1: +; X64-NEXT: .LBB0_2: ; X64-NEXT: movq %rdi, %rax ; X64-NEXT: shrq %rax ; X64-NEXT: andl $1, %edi @@ -74,11 +74,11 @@ define float @test(i64 %a) nounwind { ; X64-WIN-LABEL: test: ; X64-WIN: # %bb.0: # %entry ; X64-WIN-NEXT: testq %rcx, %rcx -; X64-WIN-NEXT: js .LBB0_1 -; X64-WIN-NEXT: # %bb.2: # %entry +; X64-WIN-NEXT: js .LBB0_2 +; X64-WIN-NEXT: # %bb.1: # %entry ; X64-WIN-NEXT: cvtsi2ss %rcx, %xmm0 ; X64-WIN-NEXT: retq -; X64-WIN-NEXT: .LBB0_1: +; X64-WIN-NEXT: .LBB0_2: ; X64-WIN-NEXT: movq %rcx, %rax ; X64-WIN-NEXT: shrq %rax ; X64-WIN-NEXT: andl $1, %ecx diff --git a/llvm/test/CodeGen/X86/umul-with-carry.ll b/llvm/test/CodeGen/X86/umul-with-carry.ll index 787ce2fc57d73..edcee5d55fe9f 100644 --- a/llvm/test/CodeGen/X86/umul-with-carry.ll +++ b/llvm/test/CodeGen/X86/umul-with-carry.ll @@ -11,14 +11,14 @@ define i1 @func(i32 %v1, i32 %v2) nounwind { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: mull {{[0-9]+}}(%esp) -; CHECK-NEXT: jno .LBB0_1 -; CHECK-NEXT: # %bb.2: # %carry +; CHECK-NEXT: jno .LBB0_2 +; CHECK-NEXT: # %bb.1: # %carry ; CHECK-NEXT: pushl $no ; CHECK-NEXT: calll printf@PLT ; CHECK-NEXT: addl $4, %esp ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: retl -; CHECK-NEXT: .LBB0_1: # %normal +; CHECK-NEXT: .LBB0_2: # %normal ; CHECK-NEXT: pushl %eax ; CHECK-NEXT: pushl $ok ; CHECK-NEXT: calll printf@PLT diff --git a/llvm/test/CodeGen/X86/urem-seteq-optsize.ll b/llvm/test/CodeGen/X86/urem-seteq-optsize.ll index 8b7d87da1d6e9..92de8733835dd 100644 --- a/llvm/test/CodeGen/X86/urem-seteq-optsize.ll +++ b/llvm/test/CodeGen/X86/urem-seteq-optsize.ll @@ -14,12 +14,12 @@ define i32 @test_minsize(i32 %X) optsize minsize nounwind readnone { ; X86-NEXT: xorl %edx, %edx ; X86-NEXT: divl %ecx ; X86-NEXT: testl %edx, %edx -; X86-NEXT: je .LBB0_1 -; X86-NEXT: # %bb.2: +; X86-NEXT: je .LBB0_2 +; X86-NEXT: # %bb.1: ; X86-NEXT: pushl $-10 ; X86-NEXT: popl %eax ; X86-NEXT: retl -; X86-NEXT: .LBB0_1: +; X86-NEXT: .LBB0_2: ; X86-NEXT: pushl $42 ; X86-NEXT: popl %eax ; X86-NEXT: retl diff --git a/llvm/test/CodeGen/X86/use-cr-result-of-dom-icmp-st.ll b/llvm/test/CodeGen/X86/use-cr-result-of-dom-icmp-st.ll index 95831d506d3c0..f43982fa03724 100644 --- a/llvm/test/CodeGen/X86/use-cr-result-of-dom-icmp-st.ll +++ b/llvm/test/CodeGen/X86/use-cr-result-of-dom-icmp-st.ll @@ -22,11 +22,11 @@ define i64 @ll_a_op_b__2(i64 %a, i64 %b) { ; DEFAULT-NEXT: movq %rdi, %rax ; DEFAULT-NEXT: shlq %cl, %rax ; DEFAULT-NEXT: cmpq $-2, %rax -; DEFAULT-NEXT: jle .LBB0_1 -; DEFAULT-NEXT: # %bb.2: # %return +; DEFAULT-NEXT: jle .LBB0_2 +; DEFAULT-NEXT: # %bb.1: # %return ; DEFAULT-NEXT: movq %rcx, %rax ; DEFAULT-NEXT: retq -; DEFAULT-NEXT: .LBB0_1: # %if.end +; DEFAULT-NEXT: .LBB0_2: # %if.end ; DEFAULT-NEXT: movl $1, %eax ; DEFAULT-NEXT: cmoveq %rcx, %rax ; DEFAULT-NEXT: imulq %rdi, %rax @@ -68,11 +68,11 @@ define i64 @ll_a_op_b__1(i64 %a, i64 %b) { ; DEFAULT-NEXT: movq %rdi, %rax ; DEFAULT-NEXT: shlq %cl, %rax ; DEFAULT-NEXT: testq %rax, %rax -; DEFAULT-NEXT: js .LBB1_1 -; DEFAULT-NEXT: # %bb.2: # %return +; DEFAULT-NEXT: js .LBB1_2 +; DEFAULT-NEXT: # %bb.1: # %return ; DEFAULT-NEXT: movq %rcx, %rax ; DEFAULT-NEXT: retq -; DEFAULT-NEXT: .LBB1_1: # %if.end +; DEFAULT-NEXT: .LBB1_2: # %if.end ; DEFAULT-NEXT: cmpq $-1, %rax ; DEFAULT-NEXT: movl $1, %eax ; DEFAULT-NEXT: cmoveq %rcx, %rax @@ -86,10 +86,10 @@ define i64 @ll_a_op_b__1(i64 %a, i64 %b) { ; EQ2ICMP-NEXT: movl %eax, %ecx ; EQ2ICMP-NEXT: shlq %cl, %rdx ; EQ2ICMP-NEXT: testq %rdx, %rdx -; EQ2ICMP-NEXT: js .LBB1_1 -; EQ2ICMP-NEXT: # %bb.2: # %return +; EQ2ICMP-NEXT: js .LBB1_2 +; EQ2ICMP-NEXT: # %bb.1: # %return ; EQ2ICMP-NEXT: retq -; EQ2ICMP-NEXT: .LBB1_1: # %if.end +; EQ2ICMP-NEXT: .LBB1_2: # %if.end ; EQ2ICMP-NEXT: cmpq $-1, %rdx ; EQ2ICMP-NEXT: movl $1, %ecx ; EQ2ICMP-NEXT: cmovlq %rcx, %rax @@ -117,11 +117,11 @@ define i64 @ll_a_op_b_0(i64 %a, i64 %b) { ; DEFAULT-NEXT: movq %rdi, %rax ; DEFAULT-NEXT: shlq %cl, %rax ; DEFAULT-NEXT: testq %rax, %rax -; DEFAULT-NEXT: jle .LBB2_1 -; DEFAULT-NEXT: # %bb.2: # %return +; DEFAULT-NEXT: jle .LBB2_2 +; DEFAULT-NEXT: # %bb.1: # %return ; DEFAULT-NEXT: movq %rcx, %rax ; DEFAULT-NEXT: retq -; DEFAULT-NEXT: .LBB2_1: # %if.end +; DEFAULT-NEXT: .LBB2_2: # %if.end ; DEFAULT-NEXT: movl $1, %eax ; DEFAULT-NEXT: cmoveq %rcx, %rax ; DEFAULT-NEXT: imulq %rdi, %rax @@ -134,10 +134,10 @@ define i64 @ll_a_op_b_0(i64 %a, i64 %b) { ; EQ2ICMP-NEXT: movl %eax, %ecx ; EQ2ICMP-NEXT: shlq %cl, %rdx ; EQ2ICMP-NEXT: testq %rdx, %rdx -; EQ2ICMP-NEXT: jle .LBB2_1 -; EQ2ICMP-NEXT: # %bb.2: # %return +; EQ2ICMP-NEXT: jle .LBB2_2 +; EQ2ICMP-NEXT: # %bb.1: # %return ; EQ2ICMP-NEXT: retq -; EQ2ICMP-NEXT: .LBB2_1: # %if.end +; EQ2ICMP-NEXT: .LBB2_2: # %if.end ; EQ2ICMP-NEXT: movl $1, %ecx ; EQ2ICMP-NEXT: cmovsq %rcx, %rax ; EQ2ICMP-NEXT: imulq %rdi, %rax @@ -164,11 +164,11 @@ define i64 @ll_a_op_b_1(i64 %a, i64 %b) { ; DEFAULT-NEXT: movq %rdi, %rax ; DEFAULT-NEXT: shlq %cl, %rax ; DEFAULT-NEXT: cmpq $1, %rax -; DEFAULT-NEXT: jle .LBB3_1 -; DEFAULT-NEXT: # %bb.2: # %return +; DEFAULT-NEXT: jle .LBB3_2 +; DEFAULT-NEXT: # %bb.1: # %return ; DEFAULT-NEXT: movq %rcx, %rax ; DEFAULT-NEXT: retq -; DEFAULT-NEXT: .LBB3_1: # %if.end +; DEFAULT-NEXT: .LBB3_2: # %if.end ; DEFAULT-NEXT: movl $1, %eax ; DEFAULT-NEXT: cmoveq %rcx, %rax ; DEFAULT-NEXT: imulq %rdi, %rax @@ -210,11 +210,11 @@ define i64 @ll_a_op_b_2(i64 %a, i64 %b) { ; DEFAULT-NEXT: movq %rdi, %rax ; DEFAULT-NEXT: shlq %cl, %rax ; DEFAULT-NEXT: cmpq $2, %rax -; DEFAULT-NEXT: jle .LBB4_1 -; DEFAULT-NEXT: # %bb.2: # %return +; DEFAULT-NEXT: jle .LBB4_2 +; DEFAULT-NEXT: # %bb.1: # %return ; DEFAULT-NEXT: movq %rcx, %rax ; DEFAULT-NEXT: retq -; DEFAULT-NEXT: .LBB4_1: # %if.end +; DEFAULT-NEXT: .LBB4_2: # %if.end ; DEFAULT-NEXT: movl $1, %eax ; DEFAULT-NEXT: cmoveq %rcx, %rax ; DEFAULT-NEXT: imulq %rdi, %rax @@ -253,11 +253,11 @@ define i64 @ll_a__2(i64 %a, i64 %b) { ; DEFAULT-LABEL: ll_a__2: ; DEFAULT: # %bb.0: # %entry ; DEFAULT-NEXT: cmpq $-2, %rdi -; DEFAULT-NEXT: jle .LBB5_1 -; DEFAULT-NEXT: # %bb.2: # %return +; DEFAULT-NEXT: jle .LBB5_2 +; DEFAULT-NEXT: # %bb.1: # %return ; DEFAULT-NEXT: movq %rsi, %rax ; DEFAULT-NEXT: retq -; DEFAULT-NEXT: .LBB5_1: # %if.end +; DEFAULT-NEXT: .LBB5_2: # %if.end ; DEFAULT-NEXT: movl $1, %eax ; DEFAULT-NEXT: cmoveq %rsi, %rax ; DEFAULT-NEXT: imulq %rdi, %rax @@ -292,11 +292,11 @@ define i64 @ll_a__1(i64 %a, i64 %b) { ; DEFAULT-LABEL: ll_a__1: ; DEFAULT: # %bb.0: # %entry ; DEFAULT-NEXT: testq %rdi, %rdi -; DEFAULT-NEXT: js .LBB6_1 -; DEFAULT-NEXT: # %bb.2: # %return +; DEFAULT-NEXT: js .LBB6_2 +; DEFAULT-NEXT: # %bb.1: # %return ; DEFAULT-NEXT: movq %rsi, %rax ; DEFAULT-NEXT: retq -; DEFAULT-NEXT: .LBB6_1: # %if.end +; DEFAULT-NEXT: .LBB6_2: # %if.end ; DEFAULT-NEXT: cmpq $-1, %rdi ; DEFAULT-NEXT: movl $1, %eax ; DEFAULT-NEXT: cmoveq %rsi, %rax @@ -307,10 +307,10 @@ define i64 @ll_a__1(i64 %a, i64 %b) { ; EQ2ICMP: # %bb.0: # %entry ; EQ2ICMP-NEXT: movq %rsi, %rax ; EQ2ICMP-NEXT: testq %rdi, %rdi -; EQ2ICMP-NEXT: js .LBB6_1 -; EQ2ICMP-NEXT: # %bb.2: # %return +; EQ2ICMP-NEXT: js .LBB6_2 +; EQ2ICMP-NEXT: # %bb.1: # %return ; EQ2ICMP-NEXT: retq -; EQ2ICMP-NEXT: .LBB6_1: # %if.end +; EQ2ICMP-NEXT: .LBB6_2: # %if.end ; EQ2ICMP-NEXT: cmpq $-1, %rdi ; EQ2ICMP-NEXT: movl $1, %ecx ; EQ2ICMP-NEXT: cmovlq %rcx, %rax @@ -334,11 +334,11 @@ define i64 @ll_a_0(i64 %a, i64 %b) { ; DEFAULT-LABEL: ll_a_0: ; DEFAULT: # %bb.0: # %entry ; DEFAULT-NEXT: testq %rdi, %rdi -; DEFAULT-NEXT: jle .LBB7_1 -; DEFAULT-NEXT: # %bb.2: # %return +; DEFAULT-NEXT: jle .LBB7_2 +; DEFAULT-NEXT: # %bb.1: # %return ; DEFAULT-NEXT: movq %rsi, %rax ; DEFAULT-NEXT: retq -; DEFAULT-NEXT: .LBB7_1: # %if.end +; DEFAULT-NEXT: .LBB7_2: # %if.end ; DEFAULT-NEXT: movl $1, %eax ; DEFAULT-NEXT: cmoveq %rsi, %rax ; DEFAULT-NEXT: imulq %rdi, %rax @@ -348,10 +348,10 @@ define i64 @ll_a_0(i64 %a, i64 %b) { ; EQ2ICMP: # %bb.0: # %entry ; EQ2ICMP-NEXT: movq %rsi, %rax ; EQ2ICMP-NEXT: testq %rdi, %rdi -; EQ2ICMP-NEXT: jle .LBB7_1 -; EQ2ICMP-NEXT: # %bb.2: # %return +; EQ2ICMP-NEXT: jle .LBB7_2 +; EQ2ICMP-NEXT: # %bb.1: # %return ; EQ2ICMP-NEXT: retq -; EQ2ICMP-NEXT: .LBB7_1: # %if.end +; EQ2ICMP-NEXT: .LBB7_2: # %if.end ; EQ2ICMP-NEXT: movl $1, %ecx ; EQ2ICMP-NEXT: cmovsq %rcx, %rax ; EQ2ICMP-NEXT: imulq %rdi, %rax @@ -374,11 +374,11 @@ define i64 @ll_a_1(i64 %a, i64 %b) { ; DEFAULT-LABEL: ll_a_1: ; DEFAULT: # %bb.0: # %entry ; DEFAULT-NEXT: cmpq $1, %rdi -; DEFAULT-NEXT: jle .LBB8_1 -; DEFAULT-NEXT: # %bb.2: # %return +; DEFAULT-NEXT: jle .LBB8_2 +; DEFAULT-NEXT: # %bb.1: # %return ; DEFAULT-NEXT: movq %rsi, %rax ; DEFAULT-NEXT: retq -; DEFAULT-NEXT: .LBB8_1: # %if.end +; DEFAULT-NEXT: .LBB8_2: # %if.end ; DEFAULT-NEXT: movl $1, %eax ; DEFAULT-NEXT: cmoveq %rsi, %rax ; DEFAULT-NEXT: imulq %rdi, %rax @@ -413,11 +413,11 @@ define i64 @ll_a_2(i64 %a, i64 %b) { ; DEFAULT-LABEL: ll_a_2: ; DEFAULT: # %bb.0: # %entry ; DEFAULT-NEXT: cmpq $2, %rdi -; DEFAULT-NEXT: jle .LBB9_1 -; DEFAULT-NEXT: # %bb.2: # %return +; DEFAULT-NEXT: jle .LBB9_2 +; DEFAULT-NEXT: # %bb.1: # %return ; DEFAULT-NEXT: movq %rsi, %rax ; DEFAULT-NEXT: retq -; DEFAULT-NEXT: .LBB9_1: # %if.end +; DEFAULT-NEXT: .LBB9_2: # %if.end ; DEFAULT-NEXT: movl $1, %eax ; DEFAULT-NEXT: cmoveq %rsi, %rax ; DEFAULT-NEXT: imulq %rdi, %rax @@ -503,11 +503,11 @@ define i64 @i_a_op_b__1(i32 signext %a, i32 signext %b) { ; DEFAULT-NEXT: movl %edi, %eax ; DEFAULT-NEXT: shll %cl, %eax ; DEFAULT-NEXT: testl %eax, %eax -; DEFAULT-NEXT: js .LBB11_1 -; DEFAULT-NEXT: # %bb.2: # %return +; DEFAULT-NEXT: js .LBB11_2 +; DEFAULT-NEXT: # %bb.1: # %return ; DEFAULT-NEXT: movslq %ecx, %rax ; DEFAULT-NEXT: retq -; DEFAULT-NEXT: .LBB11_1: # %if.end +; DEFAULT-NEXT: .LBB11_2: # %if.end ; DEFAULT-NEXT: cmpl $-1, %eax ; DEFAULT-NEXT: movl $1, %eax ; DEFAULT-NEXT: cmovel %ecx, %eax @@ -522,11 +522,11 @@ define i64 @i_a_op_b__1(i32 signext %a, i32 signext %b) { ; EQ2ICMP-NEXT: movl %edi, %eax ; EQ2ICMP-NEXT: shll %cl, %eax ; EQ2ICMP-NEXT: testl %eax, %eax -; EQ2ICMP-NEXT: js .LBB11_1 -; EQ2ICMP-NEXT: # %bb.2: # %return +; EQ2ICMP-NEXT: js .LBB11_2 +; EQ2ICMP-NEXT: # %bb.1: # %return ; EQ2ICMP-NEXT: movslq %ecx, %rax ; EQ2ICMP-NEXT: retq -; EQ2ICMP-NEXT: .LBB11_1: # %if.end +; EQ2ICMP-NEXT: .LBB11_2: # %if.end ; EQ2ICMP-NEXT: cmpl $-1, %eax ; EQ2ICMP-NEXT: movl $1, %eax ; EQ2ICMP-NEXT: cmovll %eax, %ecx @@ -557,11 +557,11 @@ define i64 @i_a_op_b_0(i32 signext %a, i32 signext %b) { ; DEFAULT-NEXT: movl %edi, %eax ; DEFAULT-NEXT: shll %cl, %eax ; DEFAULT-NEXT: testl %eax, %eax -; DEFAULT-NEXT: jle .LBB12_1 -; DEFAULT-NEXT: # %bb.2: # %return +; DEFAULT-NEXT: jle .LBB12_2 +; DEFAULT-NEXT: # %bb.1: # %return ; DEFAULT-NEXT: movslq %ecx, %rax ; DEFAULT-NEXT: retq -; DEFAULT-NEXT: .LBB12_1: # %if.end +; DEFAULT-NEXT: .LBB12_2: # %if.end ; DEFAULT-NEXT: movl $1, %eax ; DEFAULT-NEXT: cmovel %ecx, %eax ; DEFAULT-NEXT: imull %edi, %eax @@ -575,11 +575,11 @@ define i64 @i_a_op_b_0(i32 signext %a, i32 signext %b) { ; EQ2ICMP-NEXT: movl %edi, %eax ; EQ2ICMP-NEXT: shll %cl, %eax ; EQ2ICMP-NEXT: testl %eax, %eax -; EQ2ICMP-NEXT: jle .LBB12_1 -; EQ2ICMP-NEXT: # %bb.2: # %return +; EQ2ICMP-NEXT: jle .LBB12_2 +; EQ2ICMP-NEXT: # %bb.1: # %return ; EQ2ICMP-NEXT: movslq %ecx, %rax ; EQ2ICMP-NEXT: retq -; EQ2ICMP-NEXT: .LBB12_1: # %if.end +; EQ2ICMP-NEXT: .LBB12_2: # %if.end ; EQ2ICMP-NEXT: movl $1, %eax ; EQ2ICMP-NEXT: cmovsl %eax, %ecx ; EQ2ICMP-NEXT: imull %edi, %ecx @@ -743,11 +743,11 @@ define i64 @i_a__1(i32 signext %a, i32 signext %b) { ; DEFAULT-LABEL: i_a__1: ; DEFAULT: # %bb.0: # %entry ; DEFAULT-NEXT: testl %edi, %edi -; DEFAULT-NEXT: js .LBB16_1 -; DEFAULT-NEXT: # %bb.2: # %return +; DEFAULT-NEXT: js .LBB16_2 +; DEFAULT-NEXT: # %bb.1: # %return ; DEFAULT-NEXT: movslq %esi, %rax ; DEFAULT-NEXT: retq -; DEFAULT-NEXT: .LBB16_1: # %if.end +; DEFAULT-NEXT: .LBB16_2: # %if.end ; DEFAULT-NEXT: cmpl $-1, %edi ; DEFAULT-NEXT: movl $1, %eax ; DEFAULT-NEXT: cmovel %esi, %eax @@ -759,11 +759,11 @@ define i64 @i_a__1(i32 signext %a, i32 signext %b) { ; EQ2ICMP-LABEL: i_a__1: ; EQ2ICMP: # %bb.0: # %entry ; EQ2ICMP-NEXT: testl %edi, %edi -; EQ2ICMP-NEXT: js .LBB16_1 -; EQ2ICMP-NEXT: # %bb.2: # %return +; EQ2ICMP-NEXT: js .LBB16_2 +; EQ2ICMP-NEXT: # %bb.1: # %return ; EQ2ICMP-NEXT: movslq %esi, %rax ; EQ2ICMP-NEXT: retq -; EQ2ICMP-NEXT: .LBB16_1: # %if.end +; EQ2ICMP-NEXT: .LBB16_2: # %if.end ; EQ2ICMP-NEXT: cmpl $-1, %edi ; EQ2ICMP-NEXT: movl $1, %eax ; EQ2ICMP-NEXT: cmovll %eax, %esi @@ -790,11 +790,11 @@ define i64 @i_a_0(i32 signext %a, i32 signext %b) { ; DEFAULT-LABEL: i_a_0: ; DEFAULT: # %bb.0: # %entry ; DEFAULT-NEXT: testl %edi, %edi -; DEFAULT-NEXT: jle .LBB17_1 -; DEFAULT-NEXT: # %bb.2: # %return +; DEFAULT-NEXT: jle .LBB17_2 +; DEFAULT-NEXT: # %bb.1: # %return ; DEFAULT-NEXT: movslq %esi, %rax ; DEFAULT-NEXT: retq -; DEFAULT-NEXT: .LBB17_1: # %if.end +; DEFAULT-NEXT: .LBB17_2: # %if.end ; DEFAULT-NEXT: movl $1, %eax ; DEFAULT-NEXT: cmovel %esi, %eax ; DEFAULT-NEXT: imull %edi, %eax @@ -805,11 +805,11 @@ define i64 @i_a_0(i32 signext %a, i32 signext %b) { ; EQ2ICMP-LABEL: i_a_0: ; EQ2ICMP: # %bb.0: # %entry ; EQ2ICMP-NEXT: testl %edi, %edi -; EQ2ICMP-NEXT: jle .LBB17_1 -; EQ2ICMP-NEXT: # %bb.2: # %return +; EQ2ICMP-NEXT: jle .LBB17_2 +; EQ2ICMP-NEXT: # %bb.1: # %return ; EQ2ICMP-NEXT: movslq %esi, %rax ; EQ2ICMP-NEXT: retq -; EQ2ICMP-NEXT: .LBB17_1: # %if.end +; EQ2ICMP-NEXT: .LBB17_2: # %if.end ; EQ2ICMP-NEXT: movl $1, %eax ; EQ2ICMP-NEXT: cmovsl %eax, %esi ; EQ2ICMP-NEXT: imull %edi, %esi diff --git a/llvm/test/CodeGen/X86/vaargs-prolog-insert.ll b/llvm/test/CodeGen/X86/vaargs-prolog-insert.ll index 94799b5233847..92ba6081dd960 100644 --- a/llvm/test/CodeGen/X86/vaargs-prolog-insert.ll +++ b/llvm/test/CodeGen/X86/vaargs-prolog-insert.ll @@ -8,13 +8,13 @@ define void @reduce(i32, i32, i32, i32, i32, i32, ...) nounwind { ; CHECK-NEXT: subq $56, %rsp ; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: jne .LBB0_3 -; CHECK-NEXT: # %bb.4: -; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: je .LBB0_1 -; CHECK-NEXT: .LBB0_2: -; CHECK-NEXT: addq $56, %rsp +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: testb %al, %al +; CHECK-NEXT: je .LBB0_4 +; CHECK-NEXT: .LBB0_2: +; CHECK-NEXT: addq $56, %rsp ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB0_3: +; CHECK-NEXT: .LBB0_3: ; CHECK-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movaps %xmm2, -{{[0-9]+}}(%rsp) @@ -25,7 +25,7 @@ define void @reduce(i32, i32, i32, i32, i32, i32, ...) nounwind { ; CHECK-NEXT: movaps %xmm7, {{[0-9]+}}(%rsp) ; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: jne .LBB0_2 -; CHECK-NEXT: .LBB0_1: +; CHECK-NEXT: .LBB0_4: ; CHECK-NEXT: leaq -{{[0-9]+}}(%rsp), %rax ; CHECK-NEXT: movq %rax, 16 ; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rax diff --git a/llvm/test/CodeGen/X86/vastart-defs-eflags.ll b/llvm/test/CodeGen/X86/vastart-defs-eflags.ll index 14f14edc5c772..76f4d6605378a 100644 --- a/llvm/test/CodeGen/X86/vastart-defs-eflags.ll +++ b/llvm/test/CodeGen/X86/vastart-defs-eflags.ll @@ -15,8 +15,8 @@ define i32 @check_flag(i32 %flags, ...) nounwind { ; CHECK-NEXT: movq %r8, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movq %r9, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: je LBB0_4 -; CHECK-NEXT: ## %bb.3: ## %entry +; CHECK-NEXT: je LBB0_2 +; CHECK-NEXT: ## %bb.1: ## %entry ; CHECK-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movaps %xmm2, -{{[0-9]+}}(%rsp) @@ -25,11 +25,11 @@ define i32 @check_flag(i32 %flags, ...) nounwind { ; CHECK-NEXT: movaps %xmm5, (%rsp) ; CHECK-NEXT: movaps %xmm6, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movaps %xmm7, {{[0-9]+}}(%rsp) -; CHECK-NEXT: LBB0_4: ## %entry +; CHECK-NEXT: LBB0_2: ## %entry ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testl $512, %edi ## imm = 0x200 -; CHECK-NEXT: je LBB0_2 -; CHECK-NEXT: ## %bb.1: ## %if.then +; CHECK-NEXT: je LBB0_4 +; CHECK-NEXT: ## %bb.3: ## %if.then ; CHECK-NEXT: leaq -{{[0-9]+}}(%rsp), %rax ; CHECK-NEXT: movq %rax, 16 ; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rax @@ -37,7 +37,7 @@ define i32 @check_flag(i32 %flags, ...) nounwind { ; CHECK-NEXT: movl $48, 4 ; CHECK-NEXT: movl $8, 0 ; CHECK-NEXT: movl $1, %eax -; CHECK-NEXT: LBB0_2: ## %if.end +; CHECK-NEXT: LBB0_4: ## %if.end ; CHECK-NEXT: addq $56, %rsp ; CHECK-NEXT: retq entry: diff --git a/llvm/test/CodeGen/X86/vec_floor.ll b/llvm/test/CodeGen/X86/vec_floor.ll index c5c8c052ea347..2b9e07a27c4a1 100644 --- a/llvm/test/CodeGen/X86/vec_floor.ll +++ b/llvm/test/CodeGen/X86/vec_floor.ll @@ -1551,11 +1551,11 @@ define <4 x float> @floor_maskz_ss_trunc(<4 x float> %x, <4 x float> %y, i16 %k) ; SSE41-LABEL: floor_maskz_ss_trunc: ; SSE41: ## %bb.0: ; SSE41-NEXT: testb $1, %dil -; SSE41-NEXT: jne LBB57_1 -; SSE41-NEXT: ## %bb.2: +; SSE41-NEXT: jne LBB57_2 +; SSE41-NEXT: ## %bb.1: ; SSE41-NEXT: xorps %xmm0, %xmm0 ; SSE41-NEXT: jmp LBB57_3 -; SSE41-NEXT: LBB57_1: +; SSE41-NEXT: LBB57_2: ; SSE41-NEXT: roundss $9, %xmm0, %xmm0 ; SSE41-NEXT: LBB57_3: ; SSE41-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3] @@ -1565,12 +1565,12 @@ define <4 x float> @floor_maskz_ss_trunc(<4 x float> %x, <4 x float> %y, i16 %k) ; AVX-LABEL: floor_maskz_ss_trunc: ; AVX: ## %bb.0: ; AVX-NEXT: testb $1, %dil -; AVX-NEXT: jne LBB57_1 -; AVX-NEXT: ## %bb.2: +; AVX-NEXT: jne LBB57_2 +; AVX-NEXT: ## %bb.1: ; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3] ; AVX-NEXT: retq -; AVX-NEXT: LBB57_1: +; AVX-NEXT: LBB57_2: ; AVX-NEXT: vroundss $9, %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3] ; AVX-NEXT: retq @@ -1632,11 +1632,11 @@ define <2 x double> @floor_maskz_sd_trunc(<2 x double> %x, <2 x double> %y, i16 ; SSE41-LABEL: floor_maskz_sd_trunc: ; SSE41: ## %bb.0: ; SSE41-NEXT: testb $1, %dil -; SSE41-NEXT: jne LBB59_1 -; SSE41-NEXT: ## %bb.2: +; SSE41-NEXT: jne LBB59_2 +; SSE41-NEXT: ## %bb.1: ; SSE41-NEXT: xorpd %xmm0, %xmm0 ; SSE41-NEXT: jmp LBB59_3 -; SSE41-NEXT: LBB59_1: +; SSE41-NEXT: LBB59_2: ; SSE41-NEXT: roundsd $9, %xmm0, %xmm0 ; SSE41-NEXT: LBB59_3: ; SSE41-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1] @@ -1646,12 +1646,12 @@ define <2 x double> @floor_maskz_sd_trunc(<2 x double> %x, <2 x double> %y, i16 ; AVX-LABEL: floor_maskz_sd_trunc: ; AVX: ## %bb.0: ; AVX-NEXT: testb $1, %dil -; AVX-NEXT: jne LBB59_1 -; AVX-NEXT: ## %bb.2: +; AVX-NEXT: jne LBB59_2 +; AVX-NEXT: ## %bb.1: ; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vmovsd {{.*#+}} xmm0 = xmm0[0],xmm1[1] ; AVX-NEXT: retq -; AVX-NEXT: LBB59_1: +; AVX-NEXT: LBB59_2: ; AVX-NEXT: vroundsd $9, %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vmovsd {{.*#+}} xmm0 = xmm0[0],xmm1[1] ; AVX-NEXT: retq @@ -1841,7 +1841,7 @@ define <2 x double> @ceil_sd(<2 x double> %x, <2 x double> %y) nounwind { ; ; AVX512-LABEL: ceil_sd: ; AVX512: ## %bb.0: -; AVX512-NEXT: vroundsd $10, %xmm0, %xmm1, %xmm0 +; AVX512-NEXT: vroundsd $10, %xmm0, %xmm1, %xmm0 ; AVX512-NEXT: retq %s = extractelement <2 x double> %x, i32 0 %call = call double @llvm.ceil.f64(double %s) @@ -2537,11 +2537,11 @@ define <4 x float> @ceil_maskz_ss_trunc(<4 x float> %x, <4 x float> %y, i16 %k) ; SSE41-LABEL: ceil_maskz_ss_trunc: ; SSE41: ## %bb.0: ; SSE41-NEXT: testb $1, %dil -; SSE41-NEXT: jne LBB83_1 -; SSE41-NEXT: ## %bb.2: +; SSE41-NEXT: jne LBB83_2 +; SSE41-NEXT: ## %bb.1: ; SSE41-NEXT: xorps %xmm0, %xmm0 ; SSE41-NEXT: jmp LBB83_3 -; SSE41-NEXT: LBB83_1: +; SSE41-NEXT: LBB83_2: ; SSE41-NEXT: roundss $10, %xmm0, %xmm0 ; SSE41-NEXT: LBB83_3: ; SSE41-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3] @@ -2551,12 +2551,12 @@ define <4 x float> @ceil_maskz_ss_trunc(<4 x float> %x, <4 x float> %y, i16 %k) ; AVX-LABEL: ceil_maskz_ss_trunc: ; AVX: ## %bb.0: ; AVX-NEXT: testb $1, %dil -; AVX-NEXT: jne LBB83_1 -; AVX-NEXT: ## %bb.2: +; AVX-NEXT: jne LBB83_2 +; AVX-NEXT: ## %bb.1: ; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3] ; AVX-NEXT: retq -; AVX-NEXT: LBB83_1: +; AVX-NEXT: LBB83_2: ; AVX-NEXT: vroundss $10, %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3] ; AVX-NEXT: retq @@ -2618,11 +2618,11 @@ define <2 x double> @ceil_maskz_sd_trunc(<2 x double> %x, <2 x double> %y, i16 % ; SSE41-LABEL: ceil_maskz_sd_trunc: ; SSE41: ## %bb.0: ; SSE41-NEXT: testb $1, %dil -; SSE41-NEXT: jne LBB85_1 -; SSE41-NEXT: ## %bb.2: +; SSE41-NEXT: jne LBB85_2 +; SSE41-NEXT: ## %bb.1: ; SSE41-NEXT: xorpd %xmm0, %xmm0 ; SSE41-NEXT: jmp LBB85_3 -; SSE41-NEXT: LBB85_1: +; SSE41-NEXT: LBB85_2: ; SSE41-NEXT: roundsd $10, %xmm0, %xmm0 ; SSE41-NEXT: LBB85_3: ; SSE41-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1] @@ -2632,12 +2632,12 @@ define <2 x double> @ceil_maskz_sd_trunc(<2 x double> %x, <2 x double> %y, i16 % ; AVX-LABEL: ceil_maskz_sd_trunc: ; AVX: ## %bb.0: ; AVX-NEXT: testb $1, %dil -; AVX-NEXT: jne LBB85_1 -; AVX-NEXT: ## %bb.2: +; AVX-NEXT: jne LBB85_2 +; AVX-NEXT: ## %bb.1: ; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vmovsd {{.*#+}} xmm0 = xmm0[0],xmm1[1] ; AVX-NEXT: retq -; AVX-NEXT: LBB85_1: +; AVX-NEXT: LBB85_2: ; AVX-NEXT: vroundsd $10, %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vmovsd {{.*#+}} xmm0 = xmm0[0],xmm1[1] ; AVX-NEXT: retq diff --git a/llvm/test/CodeGen/X86/vec_int_to_fp.ll b/llvm/test/CodeGen/X86/vec_int_to_fp.ll index 236e564a162be..8782c6d87cf0f 100644 --- a/llvm/test/CodeGen/X86/vec_int_to_fp.ll +++ b/llvm/test/CodeGen/X86/vec_int_to_fp.ll @@ -1829,12 +1829,12 @@ define <4 x float> @uitofp_2i64_to_4f32(<2 x i64> %a) { ; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movq %xmm0, %rax ; SSE2-NEXT: testq %rax, %rax -; SSE2-NEXT: js .LBB41_1 -; SSE2-NEXT: # %bb.2: +; SSE2-NEXT: js .LBB41_2 +; SSE2-NEXT: # %bb.1: ; SSE2-NEXT: xorps %xmm0, %xmm0 ; SSE2-NEXT: cvtsi2ss %rax, %xmm0 ; SSE2-NEXT: jmp .LBB41_3 -; SSE2-NEXT: .LBB41_1: +; SSE2-NEXT: .LBB41_2: ; SSE2-NEXT: movq %rax, %rcx ; SSE2-NEXT: shrq %rcx ; SSE2-NEXT: andl $1, %eax @@ -1846,13 +1846,13 @@ define <4 x float> @uitofp_2i64_to_4f32(<2 x i64> %a) { ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3] ; SSE2-NEXT: movq %xmm1, %rax ; SSE2-NEXT: testq %rax, %rax -; SSE2-NEXT: js .LBB41_4 -; SSE2-NEXT: # %bb.5: +; SSE2-NEXT: js .LBB41_5 +; SSE2-NEXT: # %bb.4: ; SSE2-NEXT: xorps %xmm1, %xmm1 ; SSE2-NEXT: cvtsi2ss %rax, %xmm1 ; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; SSE2-NEXT: retq -; SSE2-NEXT: .LBB41_4: +; SSE2-NEXT: .LBB41_5: ; SSE2-NEXT: movq %rax, %rcx ; SSE2-NEXT: shrq %rcx ; SSE2-NEXT: andl $1, %eax @@ -1944,12 +1944,12 @@ define <4 x float> @uitofp_2i64_to_2f32(<2 x i64> %a) { ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3] ; SSE2-NEXT: movq %xmm1, %rax ; SSE2-NEXT: testq %rax, %rax -; SSE2-NEXT: js .LBB42_1 -; SSE2-NEXT: # %bb.2: +; SSE2-NEXT: js .LBB42_2 +; SSE2-NEXT: # %bb.1: ; SSE2-NEXT: xorps %xmm1, %xmm1 ; SSE2-NEXT: cvtsi2ss %rax, %xmm1 ; SSE2-NEXT: jmp .LBB42_3 -; SSE2-NEXT: .LBB42_1: +; SSE2-NEXT: .LBB42_2: ; SSE2-NEXT: movq %rax, %rcx ; SSE2-NEXT: shrq %rcx ; SSE2-NEXT: andl $1, %eax @@ -1960,12 +1960,12 @@ define <4 x float> @uitofp_2i64_to_2f32(<2 x i64> %a) { ; SSE2-NEXT: .LBB42_3: ; SSE2-NEXT: movq %xmm0, %rax ; SSE2-NEXT: testq %rax, %rax -; SSE2-NEXT: js .LBB42_4 -; SSE2-NEXT: # %bb.5: +; SSE2-NEXT: js .LBB42_5 +; SSE2-NEXT: # %bb.4: ; SSE2-NEXT: xorps %xmm0, %xmm0 ; SSE2-NEXT: cvtsi2ss %rax, %xmm0 ; SSE2-NEXT: jmp .LBB42_6 -; SSE2-NEXT: .LBB42_4: +; SSE2-NEXT: .LBB42_5: ; SSE2-NEXT: movq %rax, %rcx ; SSE2-NEXT: shrq %rcx ; SSE2-NEXT: andl $1, %eax @@ -2059,11 +2059,11 @@ define <4 x float> @uitofp_4i64_to_4f32_undef(<2 x i64> %a) { ; SSE2: # %bb.0: ; SSE2-NEXT: movq %xmm0, %rax ; SSE2-NEXT: testq %rax, %rax -; SSE2-NEXT: js .LBB43_1 -; SSE2-NEXT: # %bb.2: +; SSE2-NEXT: js .LBB43_2 +; SSE2-NEXT: # %bb.1: ; SSE2-NEXT: cvtsi2ss %rax, %xmm1 ; SSE2-NEXT: jmp .LBB43_3 -; SSE2-NEXT: .LBB43_1: +; SSE2-NEXT: .LBB43_2: ; SSE2-NEXT: movq %rax, %rcx ; SSE2-NEXT: shrq %rcx ; SSE2-NEXT: andl $1, %eax @@ -2074,12 +2074,12 @@ define <4 x float> @uitofp_4i64_to_4f32_undef(<2 x i64> %a) { ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3] ; SSE2-NEXT: movq %xmm0, %rax ; SSE2-NEXT: testq %rax, %rax -; SSE2-NEXT: js .LBB43_4 -; SSE2-NEXT: # %bb.5: +; SSE2-NEXT: js .LBB43_5 +; SSE2-NEXT: # %bb.4: ; SSE2-NEXT: xorps %xmm0, %xmm0 ; SSE2-NEXT: cvtsi2ss %rax, %xmm0 ; SSE2-NEXT: jmp .LBB43_6 -; SSE2-NEXT: .LBB43_4: +; SSE2-NEXT: .LBB43_5: ; SSE2-NEXT: movq %rax, %rcx ; SSE2-NEXT: shrq %rcx ; SSE2-NEXT: andl $1, %eax @@ -2383,11 +2383,11 @@ define <4 x float> @uitofp_4i64_to_4f32(<4 x i64> %a) { ; SSE2: # %bb.0: ; SSE2-NEXT: movq %xmm1, %rax ; SSE2-NEXT: testq %rax, %rax -; SSE2-NEXT: js .LBB49_1 -; SSE2-NEXT: # %bb.2: +; SSE2-NEXT: js .LBB49_2 +; SSE2-NEXT: # %bb.1: ; SSE2-NEXT: cvtsi2ss %rax, %xmm2 ; SSE2-NEXT: jmp .LBB49_3 -; SSE2-NEXT: .LBB49_1: +; SSE2-NEXT: .LBB49_2: ; SSE2-NEXT: movq %rax, %rcx ; SSE2-NEXT: shrq %rcx ; SSE2-NEXT: andl $1, %eax @@ -2398,11 +2398,11 @@ define <4 x float> @uitofp_4i64_to_4f32(<4 x i64> %a) { ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3] ; SSE2-NEXT: movq %xmm1, %rax ; SSE2-NEXT: testq %rax, %rax -; SSE2-NEXT: js .LBB49_4 -; SSE2-NEXT: # %bb.5: +; SSE2-NEXT: js .LBB49_5 +; SSE2-NEXT: # %bb.4: ; SSE2-NEXT: cvtsi2ss %rax, %xmm3 ; SSE2-NEXT: jmp .LBB49_6 -; SSE2-NEXT: .LBB49_4: +; SSE2-NEXT: .LBB49_5: ; SSE2-NEXT: movq %rax, %rcx ; SSE2-NEXT: shrq %rcx ; SSE2-NEXT: andl $1, %eax @@ -2412,12 +2412,12 @@ define <4 x float> @uitofp_4i64_to_4f32(<4 x i64> %a) { ; SSE2-NEXT: .LBB49_6: ; SSE2-NEXT: movq %xmm0, %rax ; SSE2-NEXT: testq %rax, %rax -; SSE2-NEXT: js .LBB49_7 -; SSE2-NEXT: # %bb.8: +; SSE2-NEXT: js .LBB49_8 +; SSE2-NEXT: # %bb.7: ; SSE2-NEXT: xorps %xmm1, %xmm1 ; SSE2-NEXT: cvtsi2ss %rax, %xmm1 ; SSE2-NEXT: jmp .LBB49_9 -; SSE2-NEXT: .LBB49_7: +; SSE2-NEXT: .LBB49_8: ; SSE2-NEXT: movq %rax, %rcx ; SSE2-NEXT: shrq %rcx ; SSE2-NEXT: andl $1, %eax @@ -2430,12 +2430,12 @@ define <4 x float> @uitofp_4i64_to_4f32(<4 x i64> %a) { ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3] ; SSE2-NEXT: movq %xmm0, %rax ; SSE2-NEXT: testq %rax, %rax -; SSE2-NEXT: js .LBB49_10 -; SSE2-NEXT: # %bb.11: +; SSE2-NEXT: js .LBB49_11 +; SSE2-NEXT: # %bb.10: ; SSE2-NEXT: xorps %xmm0, %xmm0 ; SSE2-NEXT: cvtsi2ss %rax, %xmm0 ; SSE2-NEXT: jmp .LBB49_12 -; SSE2-NEXT: .LBB49_10: +; SSE2-NEXT: .LBB49_11: ; SSE2-NEXT: movq %rax, %rcx ; SSE2-NEXT: shrq %rcx ; SSE2-NEXT: andl $1, %eax @@ -4133,11 +4133,11 @@ define <4 x float> @uitofp_load_4i64_to_4f32(ptr%a) { ; SSE2: # %bb.0: ; SSE2-NEXT: movq 24(%rdi), %rax ; SSE2-NEXT: testq %rax, %rax -; SSE2-NEXT: js .LBB83_1 -; SSE2-NEXT: # %bb.2: +; SSE2-NEXT: js .LBB83_2 +; SSE2-NEXT: # %bb.1: ; SSE2-NEXT: cvtsi2ss %rax, %xmm0 ; SSE2-NEXT: jmp .LBB83_3 -; SSE2-NEXT: .LBB83_1: +; SSE2-NEXT: .LBB83_2: ; SSE2-NEXT: movq %rax, %rcx ; SSE2-NEXT: shrq %rcx ; SSE2-NEXT: andl $1, %eax @@ -4147,11 +4147,11 @@ define <4 x float> @uitofp_load_4i64_to_4f32(ptr%a) { ; SSE2-NEXT: .LBB83_3: ; SSE2-NEXT: movq 16(%rdi), %rax ; SSE2-NEXT: testq %rax, %rax -; SSE2-NEXT: js .LBB83_4 -; SSE2-NEXT: # %bb.5: +; SSE2-NEXT: js .LBB83_5 +; SSE2-NEXT: # %bb.4: ; SSE2-NEXT: cvtsi2ss %rax, %xmm1 ; SSE2-NEXT: jmp .LBB83_6 -; SSE2-NEXT: .LBB83_4: +; SSE2-NEXT: .LBB83_5: ; SSE2-NEXT: movq %rax, %rcx ; SSE2-NEXT: shrq %rcx ; SSE2-NEXT: andl $1, %eax @@ -4162,11 +4162,11 @@ define <4 x float> @uitofp_load_4i64_to_4f32(ptr%a) { ; SSE2-NEXT: movq (%rdi), %rax ; SSE2-NEXT: movq 8(%rdi), %rcx ; SSE2-NEXT: testq %rcx, %rcx -; SSE2-NEXT: js .LBB83_7 -; SSE2-NEXT: # %bb.8: +; SSE2-NEXT: js .LBB83_8 +; SSE2-NEXT: # %bb.7: ; SSE2-NEXT: cvtsi2ss %rcx, %xmm2 ; SSE2-NEXT: jmp .LBB83_9 -; SSE2-NEXT: .LBB83_7: +; SSE2-NEXT: .LBB83_8: ; SSE2-NEXT: movq %rcx, %rdx ; SSE2-NEXT: shrq %rdx ; SSE2-NEXT: andl $1, %ecx @@ -4176,12 +4176,12 @@ define <4 x float> @uitofp_load_4i64_to_4f32(ptr%a) { ; SSE2-NEXT: .LBB83_9: ; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: testq %rax, %rax -; SSE2-NEXT: js .LBB83_10 -; SSE2-NEXT: # %bb.11: +; SSE2-NEXT: js .LBB83_11 +; SSE2-NEXT: # %bb.10: ; SSE2-NEXT: xorps %xmm0, %xmm0 ; SSE2-NEXT: cvtsi2ss %rax, %xmm0 ; SSE2-NEXT: jmp .LBB83_12 -; SSE2-NEXT: .LBB83_10: +; SSE2-NEXT: .LBB83_11: ; SSE2-NEXT: movq %rax, %rcx ; SSE2-NEXT: shrq %rcx ; SSE2-NEXT: andl $1, %eax @@ -4469,11 +4469,11 @@ define <8 x float> @uitofp_load_8i64_to_8f32(ptr%a) { ; SSE2: # %bb.0: ; SSE2-NEXT: movq 24(%rdi), %rax ; SSE2-NEXT: testq %rax, %rax -; SSE2-NEXT: js .LBB87_1 -; SSE2-NEXT: # %bb.2: +; SSE2-NEXT: js .LBB87_2 +; SSE2-NEXT: # %bb.1: ; SSE2-NEXT: cvtsi2ss %rax, %xmm2 ; SSE2-NEXT: jmp .LBB87_3 -; SSE2-NEXT: .LBB87_1: +; SSE2-NEXT: .LBB87_2: ; SSE2-NEXT: movq %rax, %rcx ; SSE2-NEXT: shrq %rcx ; SSE2-NEXT: andl $1, %eax @@ -4483,11 +4483,11 @@ define <8 x float> @uitofp_load_8i64_to_8f32(ptr%a) { ; SSE2-NEXT: .LBB87_3: ; SSE2-NEXT: movq 16(%rdi), %rax ; SSE2-NEXT: testq %rax, %rax -; SSE2-NEXT: js .LBB87_4 -; SSE2-NEXT: # %bb.5: +; SSE2-NEXT: js .LBB87_5 +; SSE2-NEXT: # %bb.4: ; SSE2-NEXT: cvtsi2ss %rax, %xmm1 ; SSE2-NEXT: jmp .LBB87_6 -; SSE2-NEXT: .LBB87_4: +; SSE2-NEXT: .LBB87_5: ; SSE2-NEXT: movq %rax, %rcx ; SSE2-NEXT: shrq %rcx ; SSE2-NEXT: andl $1, %eax @@ -4498,20 +4498,20 @@ define <8 x float> @uitofp_load_8i64_to_8f32(ptr%a) { ; SSE2-NEXT: movq (%rdi), %rax ; SSE2-NEXT: movq 8(%rdi), %rcx ; SSE2-NEXT: testq %rcx, %rcx -; SSE2-NEXT: js .LBB87_7 -; SSE2-NEXT: # %bb.8: +; SSE2-NEXT: js .LBB87_9 +; SSE2-NEXT: # %bb.7: ; SSE2-NEXT: cvtsi2ss %rcx, %xmm3 ; SSE2-NEXT: testq %rax, %rax -; SSE2-NEXT: jns .LBB87_11 -; SSE2-NEXT: .LBB87_10: +; SSE2-NEXT: jns .LBB87_10 +; SSE2-NEXT: .LBB87_8: ; SSE2-NEXT: movq %rax, %rcx ; SSE2-NEXT: shrq %rcx ; SSE2-NEXT: andl $1, %eax ; SSE2-NEXT: orq %rcx, %rax ; SSE2-NEXT: cvtsi2ss %rax, %xmm0 ; SSE2-NEXT: addss %xmm0, %xmm0 -; SSE2-NEXT: jmp .LBB87_12 -; SSE2-NEXT: .LBB87_7: +; SSE2-NEXT: jmp .LBB87_11 +; SSE2-NEXT: .LBB87_9: ; SSE2-NEXT: movq %rcx, %rdx ; SSE2-NEXT: shrq %rdx ; SSE2-NEXT: andl $1, %ecx @@ -4519,16 +4519,16 @@ define <8 x float> @uitofp_load_8i64_to_8f32(ptr%a) { ; SSE2-NEXT: cvtsi2ss %rcx, %xmm3 ; SSE2-NEXT: addss %xmm3, %xmm3 ; SSE2-NEXT: testq %rax, %rax -; SSE2-NEXT: js .LBB87_10 -; SSE2-NEXT: .LBB87_11: +; SSE2-NEXT: js .LBB87_8 +; SSE2-NEXT: .LBB87_10: ; SSE2-NEXT: cvtsi2ss %rax, %xmm0 -; SSE2-NEXT: .LBB87_12: +; SSE2-NEXT: .LBB87_11: ; SSE2-NEXT: movq 56(%rdi), %rax ; SSE2-NEXT: testq %rax, %rax ; SSE2-NEXT: js .LBB87_13 -; SSE2-NEXT: # %bb.14: +; SSE2-NEXT: # %bb.12: ; SSE2-NEXT: cvtsi2ss %rax, %xmm5 -; SSE2-NEXT: jmp .LBB87_15 +; SSE2-NEXT: jmp .LBB87_14 ; SSE2-NEXT: .LBB87_13: ; SSE2-NEXT: movq %rax, %rcx ; SSE2-NEXT: shrq %rcx @@ -4536,13 +4536,13 @@ define <8 x float> @uitofp_load_8i64_to_8f32(ptr%a) { ; SSE2-NEXT: orq %rcx, %rax ; SSE2-NEXT: cvtsi2ss %rax, %xmm5 ; SSE2-NEXT: addss %xmm5, %xmm5 -; SSE2-NEXT: .LBB87_15: +; SSE2-NEXT: .LBB87_14: ; SSE2-NEXT: movq 48(%rdi), %rax ; SSE2-NEXT: testq %rax, %rax ; SSE2-NEXT: js .LBB87_16 -; SSE2-NEXT: # %bb.17: +; SSE2-NEXT: # %bb.15: ; SSE2-NEXT: cvtsi2ss %rax, %xmm4 -; SSE2-NEXT: jmp .LBB87_18 +; SSE2-NEXT: jmp .LBB87_17 ; SSE2-NEXT: .LBB87_16: ; SSE2-NEXT: movq %rax, %rcx ; SSE2-NEXT: shrq %rcx @@ -4550,16 +4550,16 @@ define <8 x float> @uitofp_load_8i64_to_8f32(ptr%a) { ; SSE2-NEXT: orq %rcx, %rax ; SSE2-NEXT: cvtsi2ss %rax, %xmm4 ; SSE2-NEXT: addss %xmm4, %xmm4 -; SSE2-NEXT: .LBB87_18: +; SSE2-NEXT: .LBB87_17: ; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] ; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1] ; SSE2-NEXT: movq 40(%rdi), %rax ; SSE2-NEXT: testq %rax, %rax ; SSE2-NEXT: js .LBB87_19 -; SSE2-NEXT: # %bb.20: +; SSE2-NEXT: # %bb.18: ; SSE2-NEXT: xorps %xmm2, %xmm2 ; SSE2-NEXT: cvtsi2ss %rax, %xmm2 -; SSE2-NEXT: jmp .LBB87_21 +; SSE2-NEXT: jmp .LBB87_20 ; SSE2-NEXT: .LBB87_19: ; SSE2-NEXT: movq %rax, %rcx ; SSE2-NEXT: shrq %rcx @@ -4568,16 +4568,16 @@ define <8 x float> @uitofp_load_8i64_to_8f32(ptr%a) { ; SSE2-NEXT: xorps %xmm2, %xmm2 ; SSE2-NEXT: cvtsi2ss %rax, %xmm2 ; SSE2-NEXT: addss %xmm2, %xmm2 -; SSE2-NEXT: .LBB87_21: +; SSE2-NEXT: .LBB87_20: ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; SSE2-NEXT: unpcklps {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1] ; SSE2-NEXT: movq 32(%rdi), %rax ; SSE2-NEXT: testq %rax, %rax ; SSE2-NEXT: js .LBB87_22 -; SSE2-NEXT: # %bb.23: +; SSE2-NEXT: # %bb.21: ; SSE2-NEXT: xorps %xmm1, %xmm1 ; SSE2-NEXT: cvtsi2ss %rax, %xmm1 -; SSE2-NEXT: jmp .LBB87_24 +; SSE2-NEXT: jmp .LBB87_23 ; SSE2-NEXT: .LBB87_22: ; SSE2-NEXT: movq %rax, %rcx ; SSE2-NEXT: shrq %rcx @@ -4586,7 +4586,7 @@ define <8 x float> @uitofp_load_8i64_to_8f32(ptr%a) { ; SSE2-NEXT: xorps %xmm1, %xmm1 ; SSE2-NEXT: cvtsi2ss %rax, %xmm1 ; SSE2-NEXT: addss %xmm1, %xmm1 -; SSE2-NEXT: .LBB87_24: +; SSE2-NEXT: .LBB87_23: ; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] ; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm4[0] ; SSE2-NEXT: retq diff --git a/llvm/test/CodeGen/X86/vector-shift-by-select-loop.ll b/llvm/test/CodeGen/X86/vector-shift-by-select-loop.ll index b453f925b94e8..f6b84130ff980 100644 --- a/llvm/test/CodeGen/X86/vector-shift-by-select-loop.ll +++ b/llvm/test/CodeGen/X86/vector-shift-by-select-loop.ll @@ -15,7 +15,7 @@ define void @vector_variable_shift_left_loop(ptr nocapture %arr, ptr nocapture r ; SSE-LABEL: vector_variable_shift_left_loop: ; SSE: # %bb.0: # %entry ; SSE-NEXT: testl %edx, %edx -; SSE-NEXT: jle .LBB0_9 +; SSE-NEXT: jle .LBB0_6 ; SSE-NEXT: # %bb.1: # %for.body.preheader ; SSE-NEXT: movl %ecx, %eax ; SSE-NEXT: movl %edx, %r9d @@ -23,7 +23,7 @@ define void @vector_variable_shift_left_loop(ptr nocapture %arr, ptr nocapture r ; SSE-NEXT: ja .LBB0_3 ; SSE-NEXT: # %bb.2: ; SSE-NEXT: xorl %edx, %edx -; SSE-NEXT: jmp .LBB0_6 +; SSE-NEXT: jmp .LBB0_8 ; SSE-NEXT: .LBB0_3: # %vector.ph ; SSE-NEXT: movl %r9d, %edx ; SSE-NEXT: andl $-32, %edx @@ -116,31 +116,31 @@ define void @vector_variable_shift_left_loop(ptr nocapture %arr, ptr nocapture r ; SSE-NEXT: jne .LBB0_4 ; SSE-NEXT: # %bb.5: # %middle.block ; SSE-NEXT: cmpl %r9d, %edx -; SSE-NEXT: jne .LBB0_6 -; SSE-NEXT: .LBB0_9: # %for.cond.cleanup +; SSE-NEXT: jne .LBB0_8 +; SSE-NEXT: .LBB0_6: # %for.cond.cleanup ; SSE-NEXT: retq ; SSE-NEXT: .p2align 4 -; SSE-NEXT: .LBB0_8: # %for.body -; SSE-NEXT: # in Loop: Header=BB0_6 Depth=1 +; SSE-NEXT: .LBB0_7: # %for.body +; SSE-NEXT: # in Loop: Header=BB0_8 Depth=1 ; SSE-NEXT: # kill: def $cl killed $cl killed $ecx ; SSE-NEXT: shll %cl, (%rdi,%rdx,4) ; SSE-NEXT: incq %rdx ; SSE-NEXT: cmpq %rdx, %r9 -; SSE-NEXT: je .LBB0_9 -; SSE-NEXT: .LBB0_6: # %for.body +; SSE-NEXT: je .LBB0_6 +; SSE-NEXT: .LBB0_8: # %for.body ; SSE-NEXT: # =>This Inner Loop Header: Depth=1 ; SSE-NEXT: cmpb $0, (%rsi,%rdx) ; SSE-NEXT: movl %eax, %ecx -; SSE-NEXT: je .LBB0_8 -; SSE-NEXT: # %bb.7: # %for.body -; SSE-NEXT: # in Loop: Header=BB0_6 Depth=1 +; SSE-NEXT: je .LBB0_7 +; SSE-NEXT: # %bb.9: # %for.body +; SSE-NEXT: # in Loop: Header=BB0_8 Depth=1 ; SSE-NEXT: movl %r8d, %ecx -; SSE-NEXT: jmp .LBB0_8 +; SSE-NEXT: jmp .LBB0_7 ; ; AVX1-LABEL: vector_variable_shift_left_loop: ; AVX1: # %bb.0: # %entry ; AVX1-NEXT: testl %edx, %edx -; AVX1-NEXT: jle .LBB0_9 +; AVX1-NEXT: jle .LBB0_6 ; AVX1-NEXT: # %bb.1: # %for.body.preheader ; AVX1-NEXT: movl %ecx, %eax ; AVX1-NEXT: movl %edx, %r9d @@ -148,7 +148,7 @@ define void @vector_variable_shift_left_loop(ptr nocapture %arr, ptr nocapture r ; AVX1-NEXT: ja .LBB0_3 ; AVX1-NEXT: # %bb.2: ; AVX1-NEXT: xorl %edx, %edx -; AVX1-NEXT: jmp .LBB0_6 +; AVX1-NEXT: jmp .LBB0_8 ; AVX1-NEXT: .LBB0_3: # %vector.ph ; AVX1-NEXT: movl %r9d, %edx ; AVX1-NEXT: andl $-32, %edx @@ -240,32 +240,32 @@ define void @vector_variable_shift_left_loop(ptr nocapture %arr, ptr nocapture r ; AVX1-NEXT: jne .LBB0_4 ; AVX1-NEXT: # %bb.5: # %middle.block ; AVX1-NEXT: cmpl %r9d, %edx -; AVX1-NEXT: jne .LBB0_6 -; AVX1-NEXT: .LBB0_9: # %for.cond.cleanup +; AVX1-NEXT: jne .LBB0_8 +; AVX1-NEXT: .LBB0_6: # %for.cond.cleanup ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq ; AVX1-NEXT: .p2align 4 -; AVX1-NEXT: .LBB0_8: # %for.body -; AVX1-NEXT: # in Loop: Header=BB0_6 Depth=1 +; AVX1-NEXT: .LBB0_7: # %for.body +; AVX1-NEXT: # in Loop: Header=BB0_8 Depth=1 ; AVX1-NEXT: # kill: def $cl killed $cl killed $ecx ; AVX1-NEXT: shll %cl, (%rdi,%rdx,4) ; AVX1-NEXT: incq %rdx ; AVX1-NEXT: cmpq %rdx, %r9 -; AVX1-NEXT: je .LBB0_9 -; AVX1-NEXT: .LBB0_6: # %for.body +; AVX1-NEXT: je .LBB0_6 +; AVX1-NEXT: .LBB0_8: # %for.body ; AVX1-NEXT: # =>This Inner Loop Header: Depth=1 ; AVX1-NEXT: cmpb $0, (%rsi,%rdx) ; AVX1-NEXT: movl %eax, %ecx -; AVX1-NEXT: je .LBB0_8 -; AVX1-NEXT: # %bb.7: # %for.body -; AVX1-NEXT: # in Loop: Header=BB0_6 Depth=1 +; AVX1-NEXT: je .LBB0_7 +; AVX1-NEXT: # %bb.9: # %for.body +; AVX1-NEXT: # in Loop: Header=BB0_8 Depth=1 ; AVX1-NEXT: movl %r8d, %ecx -; AVX1-NEXT: jmp .LBB0_8 +; AVX1-NEXT: jmp .LBB0_7 ; ; AVX2-LABEL: vector_variable_shift_left_loop: ; AVX2: # %bb.0: # %entry ; AVX2-NEXT: testl %edx, %edx -; AVX2-NEXT: jle .LBB0_9 +; AVX2-NEXT: jle .LBB0_6 ; AVX2-NEXT: # %bb.1: # %for.body.preheader ; AVX2-NEXT: movl %ecx, %eax ; AVX2-NEXT: movl %edx, %r9d @@ -273,7 +273,7 @@ define void @vector_variable_shift_left_loop(ptr nocapture %arr, ptr nocapture r ; AVX2-NEXT: ja .LBB0_3 ; AVX2-NEXT: # %bb.2: ; AVX2-NEXT: xorl %edx, %edx -; AVX2-NEXT: jmp .LBB0_6 +; AVX2-NEXT: jmp .LBB0_8 ; AVX2-NEXT: .LBB0_3: # %vector.ph ; AVX2-NEXT: movl %r9d, %edx ; AVX2-NEXT: andl $-32, %edx @@ -315,32 +315,32 @@ define void @vector_variable_shift_left_loop(ptr nocapture %arr, ptr nocapture r ; AVX2-NEXT: jne .LBB0_4 ; AVX2-NEXT: # %bb.5: # %middle.block ; AVX2-NEXT: cmpl %r9d, %edx -; AVX2-NEXT: jne .LBB0_6 -; AVX2-NEXT: .LBB0_9: # %for.cond.cleanup +; AVX2-NEXT: jne .LBB0_8 +; AVX2-NEXT: .LBB0_6: # %for.cond.cleanup ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; AVX2-NEXT: .p2align 4 -; AVX2-NEXT: .LBB0_8: # %for.body -; AVX2-NEXT: # in Loop: Header=BB0_6 Depth=1 +; AVX2-NEXT: .LBB0_7: # %for.body +; AVX2-NEXT: # in Loop: Header=BB0_8 Depth=1 ; AVX2-NEXT: # kill: def $cl killed $cl killed $ecx ; AVX2-NEXT: shll %cl, (%rdi,%rdx,4) ; AVX2-NEXT: incq %rdx ; AVX2-NEXT: cmpq %rdx, %r9 -; AVX2-NEXT: je .LBB0_9 -; AVX2-NEXT: .LBB0_6: # %for.body +; AVX2-NEXT: je .LBB0_6 +; AVX2-NEXT: .LBB0_8: # %for.body ; AVX2-NEXT: # =>This Inner Loop Header: Depth=1 ; AVX2-NEXT: cmpb $0, (%rsi,%rdx) ; AVX2-NEXT: movl %eax, %ecx -; AVX2-NEXT: je .LBB0_8 -; AVX2-NEXT: # %bb.7: # %for.body -; AVX2-NEXT: # in Loop: Header=BB0_6 Depth=1 +; AVX2-NEXT: je .LBB0_7 +; AVX2-NEXT: # %bb.9: # %for.body +; AVX2-NEXT: # in Loop: Header=BB0_8 Depth=1 ; AVX2-NEXT: movl %r8d, %ecx -; AVX2-NEXT: jmp .LBB0_8 +; AVX2-NEXT: jmp .LBB0_7 ; ; XOP-LABEL: vector_variable_shift_left_loop: ; XOP: # %bb.0: # %entry ; XOP-NEXT: testl %edx, %edx -; XOP-NEXT: jle .LBB0_9 +; XOP-NEXT: jle .LBB0_6 ; XOP-NEXT: # %bb.1: # %for.body.preheader ; XOP-NEXT: movl %ecx, %eax ; XOP-NEXT: movl %edx, %r9d @@ -348,7 +348,7 @@ define void @vector_variable_shift_left_loop(ptr nocapture %arr, ptr nocapture r ; XOP-NEXT: ja .LBB0_3 ; XOP-NEXT: # %bb.2: ; XOP-NEXT: xorl %edx, %edx -; XOP-NEXT: jmp .LBB0_6 +; XOP-NEXT: jmp .LBB0_8 ; XOP-NEXT: .LBB0_3: # %vector.ph ; XOP-NEXT: movl %r9d, %edx ; XOP-NEXT: andl $-32, %edx @@ -414,27 +414,27 @@ define void @vector_variable_shift_left_loop(ptr nocapture %arr, ptr nocapture r ; XOP-NEXT: jne .LBB0_4 ; XOP-NEXT: # %bb.5: # %middle.block ; XOP-NEXT: cmpl %r9d, %edx -; XOP-NEXT: jne .LBB0_6 -; XOP-NEXT: .LBB0_9: # %for.cond.cleanup +; XOP-NEXT: jne .LBB0_8 +; XOP-NEXT: .LBB0_6: # %for.cond.cleanup ; XOP-NEXT: vzeroupper ; XOP-NEXT: retq ; XOP-NEXT: .p2align 4 -; XOP-NEXT: .LBB0_8: # %for.body -; XOP-NEXT: # in Loop: Header=BB0_6 Depth=1 +; XOP-NEXT: .LBB0_7: # %for.body +; XOP-NEXT: # in Loop: Header=BB0_8 Depth=1 ; XOP-NEXT: # kill: def $cl killed $cl killed $ecx ; XOP-NEXT: shll %cl, (%rdi,%rdx,4) ; XOP-NEXT: incq %rdx ; XOP-NEXT: cmpq %rdx, %r9 -; XOP-NEXT: je .LBB0_9 -; XOP-NEXT: .LBB0_6: # %for.body +; XOP-NEXT: je .LBB0_6 +; XOP-NEXT: .LBB0_8: # %for.body ; XOP-NEXT: # =>This Inner Loop Header: Depth=1 ; XOP-NEXT: cmpb $0, (%rsi,%rdx) ; XOP-NEXT: movl %eax, %ecx -; XOP-NEXT: je .LBB0_8 -; XOP-NEXT: # %bb.7: # %for.body -; XOP-NEXT: # in Loop: Header=BB0_6 Depth=1 +; XOP-NEXT: je .LBB0_7 +; XOP-NEXT: # %bb.9: # %for.body +; XOP-NEXT: # in Loop: Header=BB0_8 Depth=1 ; XOP-NEXT: movl %r8d, %ecx -; XOP-NEXT: jmp .LBB0_8 +; XOP-NEXT: jmp .LBB0_7 entry: %cmp12 = icmp sgt i32 %count, 0 br i1 %cmp12, label %for.body.preheader, label %for.cond.cleanup diff --git a/llvm/test/CodeGen/X86/wide-integer-cmp.ll b/llvm/test/CodeGen/X86/wide-integer-cmp.ll index 12dccca76eb19..c6d1ab3965568 100644 --- a/llvm/test/CodeGen/X86/wide-integer-cmp.ll +++ b/llvm/test/CodeGen/X86/wide-integer-cmp.ll @@ -103,13 +103,13 @@ define i32 @test_wide(i128 %a, i128 %b) { ; CHECK-NEXT: sbbl {{[0-9]+}}(%esp), %esi ; CHECK-NEXT: sbbl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: sbbl {{[0-9]+}}(%esp), %eax -; CHECK-NEXT: jge .LBB4_3 +; CHECK-NEXT: jge .LBB4_2 ; CHECK-NEXT: # %bb.1: # %bb1 ; CHECK-NEXT: movl $1, %eax -; CHECK-NEXT: jmp .LBB4_2 -; CHECK-NEXT: .LBB4_3: # %bb2 +; CHECK-NEXT: jmp .LBB4_3 +; CHECK-NEXT: .LBB4_2: # %bb2 ; CHECK-NEXT: movl $2, %eax -; CHECK-NEXT: .LBB4_2: # %bb1 +; CHECK-NEXT: .LBB4_3: # %bb1 ; CHECK-NEXT: addl $8, %esp ; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: popl %esi diff --git a/llvm/test/CodeGen/X86/widen_cast-1.ll b/llvm/test/CodeGen/X86/widen_cast-1.ll index 566dde0ca13d3..cef812a39e675 100644 --- a/llvm/test/CodeGen/X86/widen_cast-1.ll +++ b/llvm/test/CodeGen/X86/widen_cast-1.ll @@ -13,9 +13,9 @@ define void @convert(ptr %dst, ptr %src) nounwind { ; CHECK-NEXT: movl $0, (%esp) ; CHECK-NEXT: pcmpeqd %xmm0, %xmm0 ; CHECK-NEXT: cmpl $3, (%esp) -; CHECK-NEXT: jg .LBB0_3 +; CHECK-NEXT: jg .LBB0_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_2: # %forbody +; CHECK-NEXT: .LBB0_1: # %forbody ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: movl (%esp), %eax ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx @@ -25,8 +25,8 @@ define void @convert(ptr %dst, ptr %src) nounwind { ; CHECK-NEXT: movq %xmm1, (%ecx,%eax,8) ; CHECK-NEXT: incl (%esp) ; CHECK-NEXT: cmpl $3, (%esp) -; CHECK-NEXT: jle .LBB0_2 -; CHECK-NEXT: .LBB0_3: # %afterfor +; CHECK-NEXT: jle .LBB0_1 +; CHECK-NEXT: .LBB0_2: # %afterfor ; CHECK-NEXT: popl %eax ; CHECK-NEXT: retl ; @@ -36,9 +36,9 @@ define void @convert(ptr %dst, ptr %src) nounwind { ; ATOM-NEXT: pcmpeqd %xmm0, %xmm0 ; ATOM-NEXT: movl $0, (%esp) ; ATOM-NEXT: cmpl $3, (%esp) -; ATOM-NEXT: jg .LBB0_3 +; ATOM-NEXT: jg .LBB0_2 ; ATOM-NEXT: .p2align 4 -; ATOM-NEXT: .LBB0_2: # %forbody +; ATOM-NEXT: .LBB0_1: # %forbody ; ATOM-NEXT: # =>This Inner Loop Header: Depth=1 ; ATOM-NEXT: movl (%esp), %eax ; ATOM-NEXT: movl {{[0-9]+}}(%esp), %ecx @@ -48,8 +48,8 @@ define void @convert(ptr %dst, ptr %src) nounwind { ; ATOM-NEXT: movq %xmm1, (%ecx,%eax,8) ; ATOM-NEXT: incl (%esp) ; ATOM-NEXT: cmpl $3, (%esp) -; ATOM-NEXT: jle .LBB0_2 -; ATOM-NEXT: .LBB0_3: # %afterfor +; ATOM-NEXT: jle .LBB0_1 +; ATOM-NEXT: .LBB0_2: # %afterfor ; ATOM-NEXT: popl %eax ; ATOM-NEXT: retl entry: diff --git a/llvm/test/CodeGen/X86/widen_cast-2.ll b/llvm/test/CodeGen/X86/widen_cast-2.ll index cd06f27dcc55c..5affcce326f1e 100644 --- a/llvm/test/CodeGen/X86/widen_cast-2.ll +++ b/llvm/test/CodeGen/X86/widen_cast-2.ll @@ -9,9 +9,9 @@ define void @convert(ptr %dst, ptr %src) nounwind { ; CHECK-NEXT: movl $0, (%esp) ; CHECK-NEXT: pcmpeqd %xmm0, %xmm0 ; CHECK-NEXT: cmpl $3, (%esp) -; CHECK-NEXT: jg .LBB0_3 +; CHECK-NEXT: jg .LBB0_2 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB0_2: # %forbody +; CHECK-NEXT: .LBB0_1: # %forbody ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: movl (%esp), %eax ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx @@ -27,8 +27,8 @@ define void @convert(ptr %dst, ptr %src) nounwind { ; CHECK-NEXT: pextrd $2, %xmm2, 24(%ecx,%eax) ; CHECK-NEXT: incl (%esp) ; CHECK-NEXT: cmpl $3, (%esp) -; CHECK-NEXT: jle .LBB0_2 -; CHECK-NEXT: .LBB0_3: # %afterfor +; CHECK-NEXT: jle .LBB0_1 +; CHECK-NEXT: .LBB0_2: # %afterfor ; CHECK-NEXT: popl %eax ; CHECK-NEXT: retl entry: diff --git a/llvm/test/CodeGen/X86/win32-pic-jumptable.ll b/llvm/test/CodeGen/X86/win32-pic-jumptable.ll index 1b29a38a8ccd6..a9c620ddac0bc 100644 --- a/llvm/test/CodeGen/X86/win32-pic-jumptable.ll +++ b/llvm/test/CodeGen/X86/win32-pic-jumptable.ll @@ -9,10 +9,10 @@ ; CHECK-NEXT: jmpl *%eax ; CHECK: LJTI0_0: -; CHECK-NEXT: .long LBB0_2-L0$pb -; CHECK-NEXT: .long LBB0_3-L0$pb -; CHECK-NEXT: .long LBB0_4-L0$pb -; CHECK-NEXT: .long LBB0_5-L0$pb +; CHECK-NEXT: .long LBB0_{{[0-9]+}}-L0$pb +; CHECK-NEXT: .long LBB0_{{[0-9]+}}-L0$pb +; CHECK-NEXT: .long LBB0_{{[0-9]+}}-L0$pb +; CHECK-NEXT: .long LBB0_{{[0-9]+}}-L0$pb target triple = "i686--windows-itanium" diff --git a/llvm/test/CodeGen/X86/win32-seh-catchpad-realign.ll b/llvm/test/CodeGen/X86/win32-seh-catchpad-realign.ll index b88ba78b3e203..4df8536fdc8dd 100644 --- a/llvm/test/CodeGen/X86/win32-seh-catchpad-realign.ll +++ b/llvm/test/CodeGen/X86/win32-seh-catchpad-realign.ll @@ -57,7 +57,7 @@ declare i32 @_except_handler3(...) ; CHECK: calll _useit ; ; Epilogue -; CHECK: LBB0_2: # %__try.cont +; CHECK: LBB0_1: # %__try.cont ; CHECK: leal -12(%ebp), %esp ; CHECK: popl %esi ; CHECK: popl %edi @@ -65,7 +65,7 @@ declare i32 @_except_handler3(...) ; CHECK: popl %ebp ; CHECK: retl ; -; CHECK: LBB0_1: # %__except.ret +; CHECK: LBB0_2: # %__except.ret ; Restore ESP ; CHECK: movl -24(%ebp), %esp ; Recompute ESI by subtracting 60 from the end of the registration node. @@ -73,4 +73,4 @@ declare i32 @_except_handler3(...) ; Restore EBP ; CHECK: movl 12(%esi), %ebp ; Rejoin normal control flow -; CHECK: jmp LBB0_2 +; CHECK: jmp LBB0_1 diff --git a/llvm/test/CodeGen/X86/win32-seh-catchpad.ll b/llvm/test/CodeGen/X86/win32-seh-catchpad.ll index 0f5186641ca35..d9403563b574c 100644 --- a/llvm/test/CodeGen/X86/win32-seh-catchpad.ll +++ b/llvm/test/CodeGen/X86/win32-seh-catchpad.ll @@ -48,7 +48,7 @@ invoke.cont: ; preds = %entry ; CHECK: L__ehtable$try_except: ; CHECK: .long -1 # ToState ; CHECK: .long _try_except_filter_catchall # Filter -; CHECK: .long LBB0_1 +; CHECK: .long LBB define internal i32 @try_except_filter_catchall() #0 { entry: @@ -196,7 +196,7 @@ __except: ; CHECK-LABEL: _code_in_catchpad: ; CHECK: # %__except.ret -; CHECK-NEXT: $ehgcr_4_1: +; CHECK-NEXT: $ehgcr ; CHECK-NEXT: movl -24(%ebp), %esp ; CHECK-NEXT: addl $12, %ebp ; CHECK-NEXT: movl $-1, -16(%ebp) diff --git a/llvm/test/CodeGen/X86/win64-jumptable.ll b/llvm/test/CodeGen/X86/win64-jumptable.ll index 17ef0d333a727..a30d9e5f1514c 100644 --- a/llvm/test/CodeGen/X86/win64-jumptable.ll +++ b/llvm/test/CodeGen/X86/win64-jumptable.ll @@ -61,7 +61,7 @@ declare void @g(i32) ; CHECK: .seh_endproc ; Windows PIC code should use 32-bit entries -; PIC: .long .LBB0_2-.LJTI0_0 -; PIC: .long .LBB0_3-.LJTI0_0 -; PIC: .long .LBB0_4-.LJTI0_0 -; PIC: .long .LBB0_5-.LJTI0_0 +; PIC: .long .LBB0_{{[0-9]+}}-.LJTI0_0 +; PIC: .long .LBB0_{{[0-9]+}}-.LJTI0_0 +; PIC: .long .LBB0_{{[0-9]+}}-.LJTI0_0 +; PIC: .long .LBB0_{{[0-9]+}}-.LJTI0_0 diff --git a/llvm/test/CodeGen/X86/x32-va_start.ll b/llvm/test/CodeGen/X86/x32-va_start.ll index 31c8aee3fddec..5ca3d8ac69af6 100644 --- a/llvm/test/CodeGen/X86/x32-va_start.ll +++ b/llvm/test/CodeGen/X86/x32-va_start.ll @@ -33,8 +33,8 @@ define i32 @foo(float %a, ptr nocapture readnone %fmt, ...) nounwind { ; SSE-NEXT: movq %r8, -{{[0-9]+}}(%esp) ; SSE-NEXT: movq %r9, -{{[0-9]+}}(%esp) ; SSE-NEXT: testb %al, %al -; SSE-NEXT: je .LBB0_5 -; SSE-NEXT: # %bb.4: # %entry +; SSE-NEXT: je .LBB0_2 +; SSE-NEXT: # %bb.1: # %entry ; SSE-NEXT: movaps %xmm1, -{{[0-9]+}}(%esp) ; SSE-NEXT: movaps %xmm2, -{{[0-9]+}}(%esp) ; SSE-NEXT: movaps %xmm3, -{{[0-9]+}}(%esp) @@ -42,7 +42,7 @@ define i32 @foo(float %a, ptr nocapture readnone %fmt, ...) nounwind { ; SSE-NEXT: movaps %xmm5, {{[0-9]+}}(%esp) ; SSE-NEXT: movaps %xmm6, {{[0-9]+}}(%esp) ; SSE-NEXT: movaps %xmm7, {{[0-9]+}}(%esp) -; SSE-NEXT: .LBB0_5: # %entry +; SSE-NEXT: .LBB0_2: # %entry ; SSE-NEXT: leal -{{[0-9]+}}(%rsp), %eax ; SSE-NEXT: movl %eax, -{{[0-9]+}}(%esp) ; SSE-NEXT: leal {{[0-9]+}}(%rsp), %eax @@ -51,18 +51,18 @@ define i32 @foo(float %a, ptr nocapture readnone %fmt, ...) nounwind { ; SSE-NEXT: movq %rax, -{{[0-9]+}}(%esp) ; SSE-NEXT: movl $8, %ecx ; SSE-NEXT: cmpl $40, %ecx -; SSE-NEXT: ja .LBB0_2 -; SSE-NEXT: # %bb.1: # %vaarg.in_reg +; SSE-NEXT: ja .LBB0_4 +; SSE-NEXT: # %bb.3: # %vaarg.in_reg ; SSE-NEXT: movl -{{[0-9]+}}(%esp), %eax ; SSE-NEXT: addl %ecx, %eax ; SSE-NEXT: addl $8, %ecx ; SSE-NEXT: movl %ecx, -{{[0-9]+}}(%esp) -; SSE-NEXT: jmp .LBB0_3 -; SSE-NEXT: .LBB0_2: # %vaarg.in_mem +; SSE-NEXT: jmp .LBB0_5 +; SSE-NEXT: .LBB0_4: # %vaarg.in_mem ; SSE-NEXT: movl -{{[0-9]+}}(%esp), %eax ; SSE-NEXT: leal 8(%rax), %ecx ; SSE-NEXT: movl %ecx, -{{[0-9]+}}(%esp) -; SSE-NEXT: .LBB0_3: # %vaarg.end +; SSE-NEXT: .LBB0_5: # %vaarg.end ; SSE-NEXT: movl (%eax), %eax ; SSE-NEXT: addl $72, %esp ; SSE-NEXT: retq diff --git a/llvm/test/CodeGen/X86/x86-64-varargs.ll b/llvm/test/CodeGen/X86/x86-64-varargs.ll index f947327d4c562..8a1da30f5dd84 100644 --- a/llvm/test/CodeGen/X86/x86-64-varargs.ll +++ b/llvm/test/CodeGen/X86/x86-64-varargs.ll @@ -18,8 +18,8 @@ define void @func(...) nounwind { ; CHECK-X64-NEXT: pushq %rbx ; CHECK-X64-NEXT: subq $224, %rsp ; CHECK-X64-NEXT: testb %al, %al -; CHECK-X64-NEXT: je LBB0_47 -; CHECK-X64-NEXT: ## %bb.46: ## %entry +; CHECK-X64-NEXT: je LBB0_2 +; CHECK-X64-NEXT: ## %bb.1: ## %entry ; CHECK-X64-NEXT: movaps %xmm0, 96(%rsp) ; CHECK-X64-NEXT: movaps %xmm1, 112(%rsp) ; CHECK-X64-NEXT: movaps %xmm2, 128(%rsp) @@ -28,7 +28,7 @@ define void @func(...) nounwind { ; CHECK-X64-NEXT: movaps %xmm5, 176(%rsp) ; CHECK-X64-NEXT: movaps %xmm6, 192(%rsp) ; CHECK-X64-NEXT: movaps %xmm7, 208(%rsp) -; CHECK-X64-NEXT: LBB0_47: ## %entry +; CHECK-X64-NEXT: LBB0_2: ## %entry ; CHECK-X64-NEXT: movq %rdi, 48(%rsp) ; CHECK-X64-NEXT: movq %rsi, 56(%rsp) ; CHECK-X64-NEXT: movq %rdx, 64(%rsp) @@ -43,51 +43,51 @@ define void @func(...) nounwind { ; CHECK-X64-NEXT: movq %rax, 16(%rsp) ; CHECK-X64-NEXT: movl (%rsp), %ecx ; CHECK-X64-NEXT: cmpl $48, %ecx -; CHECK-X64-NEXT: jae LBB0_2 -; CHECK-X64-NEXT: ## %bb.1: ## %entry +; CHECK-X64-NEXT: jae LBB0_4 +; CHECK-X64-NEXT: ## %bb.3: ## %entry ; CHECK-X64-NEXT: movq 16(%rsp), %rax ; CHECK-X64-NEXT: addq %rcx, %rax ; CHECK-X64-NEXT: addl $8, %ecx ; CHECK-X64-NEXT: movl %ecx, (%rsp) -; CHECK-X64-NEXT: jmp LBB0_3 -; CHECK-X64-NEXT: LBB0_2: ## %entry +; CHECK-X64-NEXT: jmp LBB0_5 +; CHECK-X64-NEXT: LBB0_4: ## %entry ; CHECK-X64-NEXT: movq 8(%rsp), %rax ; CHECK-X64-NEXT: movq %rax, %rcx ; CHECK-X64-NEXT: addq $8, %rcx ; CHECK-X64-NEXT: movq %rcx, 8(%rsp) -; CHECK-X64-NEXT: LBB0_3: ## %entry +; CHECK-X64-NEXT: LBB0_5: ## %entry ; CHECK-X64-NEXT: movl (%rax), %r10d ; CHECK-X64-NEXT: movl (%rsp), %ecx ; CHECK-X64-NEXT: cmpl $48, %ecx -; CHECK-X64-NEXT: jae LBB0_5 -; CHECK-X64-NEXT: ## %bb.4: ## %entry +; CHECK-X64-NEXT: jae LBB0_7 +; CHECK-X64-NEXT: ## %bb.6: ## %entry ; CHECK-X64-NEXT: movq 16(%rsp), %rax ; CHECK-X64-NEXT: addq %rcx, %rax ; CHECK-X64-NEXT: addl $8, %ecx ; CHECK-X64-NEXT: movl %ecx, (%rsp) -; CHECK-X64-NEXT: jmp LBB0_6 -; CHECK-X64-NEXT: LBB0_5: ## %entry +; CHECK-X64-NEXT: jmp LBB0_8 +; CHECK-X64-NEXT: LBB0_7: ## %entry ; CHECK-X64-NEXT: movq 8(%rsp), %rax ; CHECK-X64-NEXT: movq %rax, %rcx ; CHECK-X64-NEXT: addq $8, %rcx ; CHECK-X64-NEXT: movq %rcx, 8(%rsp) -; CHECK-X64-NEXT: LBB0_6: ## %entry +; CHECK-X64-NEXT: LBB0_8: ## %entry ; CHECK-X64-NEXT: movl (%rax), %r11d ; CHECK-X64-NEXT: movl (%rsp), %ecx ; CHECK-X64-NEXT: cmpl $48, %ecx -; CHECK-X64-NEXT: jae LBB0_8 -; CHECK-X64-NEXT: ## %bb.7: ## %entry +; CHECK-X64-NEXT: jae LBB0_10 +; CHECK-X64-NEXT: ## %bb.9: ## %entry ; CHECK-X64-NEXT: movq 16(%rsp), %rax ; CHECK-X64-NEXT: addq %rcx, %rax ; CHECK-X64-NEXT: addl $8, %ecx ; CHECK-X64-NEXT: movl %ecx, (%rsp) -; CHECK-X64-NEXT: jmp LBB0_9 -; CHECK-X64-NEXT: LBB0_8: ## %entry +; CHECK-X64-NEXT: jmp LBB0_11 +; CHECK-X64-NEXT: LBB0_10: ## %entry ; CHECK-X64-NEXT: movq 8(%rsp), %rax ; CHECK-X64-NEXT: movq %rax, %rcx ; CHECK-X64-NEXT: addq $8, %rcx ; CHECK-X64-NEXT: movq %rcx, 8(%rsp) -; CHECK-X64-NEXT: LBB0_9: ## %entry +; CHECK-X64-NEXT: LBB0_11: ## %entry ; CHECK-X64-NEXT: movl (%rax), %r9d ; CHECK-X64-NEXT: movq 16(%rsp), %rax ; CHECK-X64-NEXT: movq %rax, 40(%rsp) @@ -97,172 +97,172 @@ define void @func(...) nounwind { ; CHECK-X64-NEXT: movq %rax, 24(%rsp) ; CHECK-X64-NEXT: movl 4(%rsp), %eax ; CHECK-X64-NEXT: cmpl $176, %eax -; CHECK-X64-NEXT: jae LBB0_11 -; CHECK-X64-NEXT: ## %bb.10: ## %entry +; CHECK-X64-NEXT: jae LBB0_13 +; CHECK-X64-NEXT: ## %bb.12: ## %entry ; CHECK-X64-NEXT: addl $16, %eax ; CHECK-X64-NEXT: movl %eax, 4(%rsp) -; CHECK-X64-NEXT: jmp LBB0_12 -; CHECK-X64-NEXT: LBB0_11: ## %entry +; CHECK-X64-NEXT: jmp LBB0_14 +; CHECK-X64-NEXT: LBB0_13: ## %entry ; CHECK-X64-NEXT: movq 8(%rsp), %rax ; CHECK-X64-NEXT: addq $8, %rax ; CHECK-X64-NEXT: movq %rax, 8(%rsp) -; CHECK-X64-NEXT: LBB0_12: ## %entry +; CHECK-X64-NEXT: LBB0_14: ## %entry ; CHECK-X64-NEXT: movl 28(%rsp), %ecx ; CHECK-X64-NEXT: cmpl $176, %ecx -; CHECK-X64-NEXT: jae LBB0_14 -; CHECK-X64-NEXT: ## %bb.13: ## %entry +; CHECK-X64-NEXT: jae LBB0_16 +; CHECK-X64-NEXT: ## %bb.15: ## %entry ; CHECK-X64-NEXT: movq 40(%rsp), %rax ; CHECK-X64-NEXT: addq %rcx, %rax ; CHECK-X64-NEXT: addl $16, %ecx ; CHECK-X64-NEXT: movl %ecx, 28(%rsp) -; CHECK-X64-NEXT: jmp LBB0_15 -; CHECK-X64-NEXT: LBB0_14: ## %entry +; CHECK-X64-NEXT: jmp LBB0_17 +; CHECK-X64-NEXT: LBB0_16: ## %entry ; CHECK-X64-NEXT: movq 32(%rsp), %rax ; CHECK-X64-NEXT: movq %rax, %rcx ; CHECK-X64-NEXT: addq $8, %rcx ; CHECK-X64-NEXT: movq %rcx, 32(%rsp) -; CHECK-X64-NEXT: LBB0_15: ## %entry +; CHECK-X64-NEXT: LBB0_17: ## %entry ; CHECK-X64-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero ; CHECK-X64-NEXT: movl (%rsp), %ecx ; CHECK-X64-NEXT: cmpl $48, %ecx -; CHECK-X64-NEXT: jae LBB0_17 -; CHECK-X64-NEXT: ## %bb.16: ## %entry +; CHECK-X64-NEXT: jae LBB0_19 +; CHECK-X64-NEXT: ## %bb.18: ## %entry ; CHECK-X64-NEXT: movq 16(%rsp), %rax ; CHECK-X64-NEXT: addq %rcx, %rax ; CHECK-X64-NEXT: addl $8, %ecx ; CHECK-X64-NEXT: movl %ecx, (%rsp) -; CHECK-X64-NEXT: jmp LBB0_18 -; CHECK-X64-NEXT: LBB0_17: ## %entry +; CHECK-X64-NEXT: jmp LBB0_20 +; CHECK-X64-NEXT: LBB0_19: ## %entry ; CHECK-X64-NEXT: movq 8(%rsp), %rax ; CHECK-X64-NEXT: movq %rax, %rcx ; CHECK-X64-NEXT: addq $8, %rcx ; CHECK-X64-NEXT: movq %rcx, 8(%rsp) -; CHECK-X64-NEXT: LBB0_18: ## %entry +; CHECK-X64-NEXT: LBB0_20: ## %entry ; CHECK-X64-NEXT: movl (%rax), %r8d ; CHECK-X64-NEXT: movl 24(%rsp), %eax ; CHECK-X64-NEXT: cmpl $48, %eax -; CHECK-X64-NEXT: jae LBB0_20 -; CHECK-X64-NEXT: ## %bb.19: ## %entry +; CHECK-X64-NEXT: jae LBB0_22 +; CHECK-X64-NEXT: ## %bb.21: ## %entry ; CHECK-X64-NEXT: addl $8, %eax ; CHECK-X64-NEXT: movl %eax, 24(%rsp) -; CHECK-X64-NEXT: jmp LBB0_21 -; CHECK-X64-NEXT: LBB0_20: ## %entry +; CHECK-X64-NEXT: jmp LBB0_23 +; CHECK-X64-NEXT: LBB0_22: ## %entry ; CHECK-X64-NEXT: movq 32(%rsp), %rax ; CHECK-X64-NEXT: addq $8, %rax ; CHECK-X64-NEXT: movq %rax, 32(%rsp) -; CHECK-X64-NEXT: LBB0_21: ## %entry +; CHECK-X64-NEXT: LBB0_23: ## %entry ; CHECK-X64-NEXT: movl (%rsp), %eax ; CHECK-X64-NEXT: cmpl $48, %eax -; CHECK-X64-NEXT: jae LBB0_23 -; CHECK-X64-NEXT: ## %bb.22: ## %entry +; CHECK-X64-NEXT: jae LBB0_25 +; CHECK-X64-NEXT: ## %bb.24: ## %entry ; CHECK-X64-NEXT: addl $8, %eax ; CHECK-X64-NEXT: movl %eax, (%rsp) -; CHECK-X64-NEXT: jmp LBB0_24 -; CHECK-X64-NEXT: LBB0_23: ## %entry +; CHECK-X64-NEXT: jmp LBB0_26 +; CHECK-X64-NEXT: LBB0_25: ## %entry ; CHECK-X64-NEXT: movq 8(%rsp), %rax ; CHECK-X64-NEXT: addq $8, %rax ; CHECK-X64-NEXT: movq %rax, 8(%rsp) -; CHECK-X64-NEXT: LBB0_24: ## %entry +; CHECK-X64-NEXT: LBB0_26: ## %entry ; CHECK-X64-NEXT: movl 24(%rsp), %ecx ; CHECK-X64-NEXT: cmpl $48, %ecx -; CHECK-X64-NEXT: jae LBB0_26 -; CHECK-X64-NEXT: ## %bb.25: ## %entry +; CHECK-X64-NEXT: jae LBB0_28 +; CHECK-X64-NEXT: ## %bb.27: ## %entry ; CHECK-X64-NEXT: movq 40(%rsp), %rax ; CHECK-X64-NEXT: addq %rcx, %rax ; CHECK-X64-NEXT: addl $8, %ecx ; CHECK-X64-NEXT: movl %ecx, 24(%rsp) -; CHECK-X64-NEXT: jmp LBB0_27 -; CHECK-X64-NEXT: LBB0_26: ## %entry +; CHECK-X64-NEXT: jmp LBB0_29 +; CHECK-X64-NEXT: LBB0_28: ## %entry ; CHECK-X64-NEXT: movq 32(%rsp), %rax ; CHECK-X64-NEXT: movq %rax, %rcx ; CHECK-X64-NEXT: addq $8, %rcx ; CHECK-X64-NEXT: movq %rcx, 32(%rsp) -; CHECK-X64-NEXT: LBB0_27: ## %entry +; CHECK-X64-NEXT: LBB0_29: ## %entry ; CHECK-X64-NEXT: movq (%rax), %rcx ; CHECK-X64-NEXT: movl (%rsp), %edx ; CHECK-X64-NEXT: cmpl $48, %edx -; CHECK-X64-NEXT: jae LBB0_29 -; CHECK-X64-NEXT: ## %bb.28: ## %entry +; CHECK-X64-NEXT: jae LBB0_31 +; CHECK-X64-NEXT: ## %bb.30: ## %entry ; CHECK-X64-NEXT: movq 16(%rsp), %rax ; CHECK-X64-NEXT: addq %rdx, %rax ; CHECK-X64-NEXT: addl $8, %edx ; CHECK-X64-NEXT: movl %edx, (%rsp) -; CHECK-X64-NEXT: jmp LBB0_30 -; CHECK-X64-NEXT: LBB0_29: ## %entry +; CHECK-X64-NEXT: jmp LBB0_32 +; CHECK-X64-NEXT: LBB0_31: ## %entry ; CHECK-X64-NEXT: movq 8(%rsp), %rax ; CHECK-X64-NEXT: movq %rax, %rdx ; CHECK-X64-NEXT: addq $8, %rdx ; CHECK-X64-NEXT: movq %rdx, 8(%rsp) -; CHECK-X64-NEXT: LBB0_30: ## %entry +; CHECK-X64-NEXT: LBB0_32: ## %entry ; CHECK-X64-NEXT: movl (%rax), %edx ; CHECK-X64-NEXT: movl 24(%rsp), %eax ; CHECK-X64-NEXT: cmpl $48, %eax -; CHECK-X64-NEXT: jae LBB0_32 -; CHECK-X64-NEXT: ## %bb.31: ## %entry +; CHECK-X64-NEXT: jae LBB0_34 +; CHECK-X64-NEXT: ## %bb.33: ## %entry ; CHECK-X64-NEXT: addl $8, %eax ; CHECK-X64-NEXT: movl %eax, 24(%rsp) -; CHECK-X64-NEXT: jmp LBB0_33 -; CHECK-X64-NEXT: LBB0_32: ## %entry +; CHECK-X64-NEXT: jmp LBB0_35 +; CHECK-X64-NEXT: LBB0_34: ## %entry ; CHECK-X64-NEXT: movq 32(%rsp), %rax ; CHECK-X64-NEXT: addq $8, %rax ; CHECK-X64-NEXT: movq %rax, 32(%rsp) -; CHECK-X64-NEXT: LBB0_33: ## %entry +; CHECK-X64-NEXT: LBB0_35: ## %entry ; CHECK-X64-NEXT: movl 4(%rsp), %eax ; CHECK-X64-NEXT: cmpl $176, %eax -; CHECK-X64-NEXT: jae LBB0_35 -; CHECK-X64-NEXT: ## %bb.34: ## %entry +; CHECK-X64-NEXT: jae LBB0_37 +; CHECK-X64-NEXT: ## %bb.36: ## %entry ; CHECK-X64-NEXT: addl $16, %eax ; CHECK-X64-NEXT: movl %eax, 4(%rsp) -; CHECK-X64-NEXT: jmp LBB0_36 -; CHECK-X64-NEXT: LBB0_35: ## %entry +; CHECK-X64-NEXT: jmp LBB0_38 +; CHECK-X64-NEXT: LBB0_37: ## %entry ; CHECK-X64-NEXT: movq 8(%rsp), %rax ; CHECK-X64-NEXT: addq $8, %rax ; CHECK-X64-NEXT: movq %rax, 8(%rsp) -; CHECK-X64-NEXT: LBB0_36: ## %entry +; CHECK-X64-NEXT: LBB0_38: ## %entry ; CHECK-X64-NEXT: movl 28(%rsp), %esi ; CHECK-X64-NEXT: cmpl $176, %esi -; CHECK-X64-NEXT: jae LBB0_38 -; CHECK-X64-NEXT: ## %bb.37: ## %entry +; CHECK-X64-NEXT: jae LBB0_40 +; CHECK-X64-NEXT: ## %bb.39: ## %entry ; CHECK-X64-NEXT: movq 40(%rsp), %rax ; CHECK-X64-NEXT: addq %rsi, %rax ; CHECK-X64-NEXT: addl $16, %esi ; CHECK-X64-NEXT: movl %esi, 28(%rsp) -; CHECK-X64-NEXT: jmp LBB0_39 -; CHECK-X64-NEXT: LBB0_38: ## %entry +; CHECK-X64-NEXT: jmp LBB0_41 +; CHECK-X64-NEXT: LBB0_40: ## %entry ; CHECK-X64-NEXT: movq 32(%rsp), %rax ; CHECK-X64-NEXT: movq %rax, %rsi ; CHECK-X64-NEXT: addq $8, %rsi ; CHECK-X64-NEXT: movq %rsi, 32(%rsp) -; CHECK-X64-NEXT: LBB0_39: ## %entry +; CHECK-X64-NEXT: LBB0_41: ## %entry ; CHECK-X64-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-X64-NEXT: movl (%rsp), %esi ; CHECK-X64-NEXT: cmpl $48, %esi -; CHECK-X64-NEXT: jae LBB0_41 -; CHECK-X64-NEXT: ## %bb.40: ## %entry +; CHECK-X64-NEXT: jae LBB0_43 +; CHECK-X64-NEXT: ## %bb.42: ## %entry ; CHECK-X64-NEXT: movq 16(%rsp), %rax ; CHECK-X64-NEXT: addq %rsi, %rax ; CHECK-X64-NEXT: addl $8, %esi ; CHECK-X64-NEXT: movl %esi, (%rsp) -; CHECK-X64-NEXT: jmp LBB0_42 -; CHECK-X64-NEXT: LBB0_41: ## %entry +; CHECK-X64-NEXT: jmp LBB0_44 +; CHECK-X64-NEXT: LBB0_43: ## %entry ; CHECK-X64-NEXT: movq 8(%rsp), %rax ; CHECK-X64-NEXT: movq %rax, %rsi ; CHECK-X64-NEXT: addq $8, %rsi ; CHECK-X64-NEXT: movq %rsi, 8(%rsp) -; CHECK-X64-NEXT: LBB0_42: ## %entry +; CHECK-X64-NEXT: LBB0_44: ## %entry ; CHECK-X64-NEXT: movl (%rax), %esi ; CHECK-X64-NEXT: movl 24(%rsp), %eax ; CHECK-X64-NEXT: cmpl $48, %eax -; CHECK-X64-NEXT: jae LBB0_44 -; CHECK-X64-NEXT: ## %bb.43: ## %entry +; CHECK-X64-NEXT: jae LBB0_46 +; CHECK-X64-NEXT: ## %bb.45: ## %entry ; CHECK-X64-NEXT: addl $8, %eax ; CHECK-X64-NEXT: movl %eax, 24(%rsp) -; CHECK-X64-NEXT: jmp LBB0_45 -; CHECK-X64-NEXT: LBB0_44: ## %entry +; CHECK-X64-NEXT: jmp LBB0_47 +; CHECK-X64-NEXT: LBB0_46: ## %entry ; CHECK-X64-NEXT: movq 32(%rsp), %rax ; CHECK-X64-NEXT: addq $8, %rax ; CHECK-X64-NEXT: movq %rax, 32(%rsp) -; CHECK-X64-NEXT: LBB0_45: ## %entry +; CHECK-X64-NEXT: LBB0_47: ## %entry ; CHECK-X64-NEXT: movabsq $_.str, %rdi ; CHECK-X64-NEXT: movabsq $_printf, %rbx ; CHECK-X64-NEXT: movb $2, %al @@ -277,8 +277,8 @@ define void @func(...) nounwind { ; CHECK-X32: # %bb.0: # %entry ; CHECK-X32-NEXT: subl $216, %esp ; CHECK-X32-NEXT: testb %al, %al -; CHECK-X32-NEXT: je .LBB0_47 -; CHECK-X32-NEXT: # %bb.46: # %entry +; CHECK-X32-NEXT: je .LBB0_2 +; CHECK-X32-NEXT: # %bb.1: # %entry ; CHECK-X32-NEXT: movaps %xmm0, 80(%esp) ; CHECK-X32-NEXT: movaps %xmm1, 96(%esp) ; CHECK-X32-NEXT: movaps %xmm2, 112(%esp) @@ -287,7 +287,7 @@ define void @func(...) nounwind { ; CHECK-X32-NEXT: movaps %xmm5, 160(%esp) ; CHECK-X32-NEXT: movaps %xmm6, 176(%esp) ; CHECK-X32-NEXT: movaps %xmm7, 192(%esp) -; CHECK-X32-NEXT: .LBB0_47: # %entry +; CHECK-X32-NEXT: .LBB0_2: # %entry ; CHECK-X32-NEXT: movq %rdi, 32(%esp) ; CHECK-X32-NEXT: movq %rsi, 40(%esp) ; CHECK-X32-NEXT: movq %rdx, 48(%esp) @@ -302,51 +302,51 @@ define void @func(...) nounwind { ; CHECK-X32-NEXT: movl %eax, 12(%esp) ; CHECK-X32-NEXT: movl (%esp), %ecx ; CHECK-X32-NEXT: cmpl $48, %ecx -; CHECK-X32-NEXT: jae .LBB0_2 -; CHECK-X32-NEXT: # %bb.1: # %entry +; CHECK-X32-NEXT: jae .LBB0_4 +; CHECK-X32-NEXT: # %bb.3: # %entry ; CHECK-X32-NEXT: movl 12(%esp), %eax ; CHECK-X32-NEXT: addl %ecx, %eax ; CHECK-X32-NEXT: addl $8, %ecx ; CHECK-X32-NEXT: movl %ecx, (%esp) -; CHECK-X32-NEXT: jmp .LBB0_3 -; CHECK-X32-NEXT: .LBB0_2: # %entry +; CHECK-X32-NEXT: jmp .LBB0_5 +; CHECK-X32-NEXT: .LBB0_4: # %entry ; CHECK-X32-NEXT: movl 8(%esp), %eax ; CHECK-X32-NEXT: movl %eax, %ecx ; CHECK-X32-NEXT: addl $8, %ecx ; CHECK-X32-NEXT: movl %ecx, 8(%esp) -; CHECK-X32-NEXT: .LBB0_3: # %entry +; CHECK-X32-NEXT: .LBB0_5: # %entry ; CHECK-X32-NEXT: movl (%eax), %r10d ; CHECK-X32-NEXT: movl (%esp), %ecx ; CHECK-X32-NEXT: cmpl $48, %ecx -; CHECK-X32-NEXT: jae .LBB0_5 -; CHECK-X32-NEXT: # %bb.4: # %entry +; CHECK-X32-NEXT: jae .LBB0_7 +; CHECK-X32-NEXT: # %bb.6: # %entry ; CHECK-X32-NEXT: movl 12(%esp), %eax ; CHECK-X32-NEXT: addl %ecx, %eax ; CHECK-X32-NEXT: addl $8, %ecx ; CHECK-X32-NEXT: movl %ecx, (%esp) -; CHECK-X32-NEXT: jmp .LBB0_6 -; CHECK-X32-NEXT: .LBB0_5: # %entry +; CHECK-X32-NEXT: jmp .LBB0_8 +; CHECK-X32-NEXT: .LBB0_7: # %entry ; CHECK-X32-NEXT: movl 8(%esp), %eax ; CHECK-X32-NEXT: movl %eax, %ecx ; CHECK-X32-NEXT: addl $8, %ecx ; CHECK-X32-NEXT: movl %ecx, 8(%esp) -; CHECK-X32-NEXT: .LBB0_6: # %entry +; CHECK-X32-NEXT: .LBB0_8: # %entry ; CHECK-X32-NEXT: movl (%eax), %r11d ; CHECK-X32-NEXT: movl (%esp), %ecx ; CHECK-X32-NEXT: cmpl $48, %ecx -; CHECK-X32-NEXT: jae .LBB0_8 -; CHECK-X32-NEXT: # %bb.7: # %entry +; CHECK-X32-NEXT: jae .LBB0_10 +; CHECK-X32-NEXT: # %bb.9: # %entry ; CHECK-X32-NEXT: movl 12(%esp), %eax ; CHECK-X32-NEXT: addl %ecx, %eax ; CHECK-X32-NEXT: addl $8, %ecx ; CHECK-X32-NEXT: movl %ecx, (%esp) -; CHECK-X32-NEXT: jmp .LBB0_9 -; CHECK-X32-NEXT: .LBB0_8: # %entry +; CHECK-X32-NEXT: jmp .LBB0_11 +; CHECK-X32-NEXT: .LBB0_10: # %entry ; CHECK-X32-NEXT: movl 8(%esp), %eax ; CHECK-X32-NEXT: movl %eax, %ecx ; CHECK-X32-NEXT: addl $8, %ecx ; CHECK-X32-NEXT: movl %ecx, 8(%esp) -; CHECK-X32-NEXT: .LBB0_9: # %entry +; CHECK-X32-NEXT: .LBB0_11: # %entry ; CHECK-X32-NEXT: movl (%eax), %r9d ; CHECK-X32-NEXT: movq (%esp), %rax ; CHECK-X32-NEXT: movq 8(%esp), %rcx @@ -354,172 +354,172 @@ define void @func(...) nounwind { ; CHECK-X32-NEXT: movq %rax, 16(%esp) ; CHECK-X32-NEXT: movl 4(%esp), %eax ; CHECK-X32-NEXT: cmpl $176, %eax -; CHECK-X32-NEXT: jae .LBB0_11 -; CHECK-X32-NEXT: # %bb.10: # %entry +; CHECK-X32-NEXT: jae .LBB0_13 +; CHECK-X32-NEXT: # %bb.12: # %entry ; CHECK-X32-NEXT: addl $16, %eax ; CHECK-X32-NEXT: movl %eax, 4(%esp) -; CHECK-X32-NEXT: jmp .LBB0_12 -; CHECK-X32-NEXT: .LBB0_11: # %entry +; CHECK-X32-NEXT: jmp .LBB0_14 +; CHECK-X32-NEXT: .LBB0_13: # %entry ; CHECK-X32-NEXT: movl 8(%esp), %eax ; CHECK-X32-NEXT: addl $8, %eax ; CHECK-X32-NEXT: movl %eax, 8(%esp) -; CHECK-X32-NEXT: .LBB0_12: # %entry +; CHECK-X32-NEXT: .LBB0_14: # %entry ; CHECK-X32-NEXT: movl 20(%esp), %ecx ; CHECK-X32-NEXT: cmpl $176, %ecx -; CHECK-X32-NEXT: jae .LBB0_14 -; CHECK-X32-NEXT: # %bb.13: # %entry +; CHECK-X32-NEXT: jae .LBB0_16 +; CHECK-X32-NEXT: # %bb.15: # %entry ; CHECK-X32-NEXT: movl 28(%esp), %eax ; CHECK-X32-NEXT: addl %ecx, %eax ; CHECK-X32-NEXT: addl $16, %ecx ; CHECK-X32-NEXT: movl %ecx, 20(%esp) -; CHECK-X32-NEXT: jmp .LBB0_15 -; CHECK-X32-NEXT: .LBB0_14: # %entry +; CHECK-X32-NEXT: jmp .LBB0_17 +; CHECK-X32-NEXT: .LBB0_16: # %entry ; CHECK-X32-NEXT: movl 24(%esp), %eax ; CHECK-X32-NEXT: movl %eax, %ecx ; CHECK-X32-NEXT: addl $8, %ecx ; CHECK-X32-NEXT: movl %ecx, 24(%esp) -; CHECK-X32-NEXT: .LBB0_15: # %entry +; CHECK-X32-NEXT: .LBB0_17: # %entry ; CHECK-X32-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero ; CHECK-X32-NEXT: movl (%esp), %ecx ; CHECK-X32-NEXT: cmpl $48, %ecx -; CHECK-X32-NEXT: jae .LBB0_17 -; CHECK-X32-NEXT: # %bb.16: # %entry +; CHECK-X32-NEXT: jae .LBB0_19 +; CHECK-X32-NEXT: # %bb.18: # %entry ; CHECK-X32-NEXT: movl 12(%esp), %eax ; CHECK-X32-NEXT: addl %ecx, %eax ; CHECK-X32-NEXT: addl $8, %ecx ; CHECK-X32-NEXT: movl %ecx, (%esp) -; CHECK-X32-NEXT: jmp .LBB0_18 -; CHECK-X32-NEXT: .LBB0_17: # %entry +; CHECK-X32-NEXT: jmp .LBB0_20 +; CHECK-X32-NEXT: .LBB0_19: # %entry ; CHECK-X32-NEXT: movl 8(%esp), %eax ; CHECK-X32-NEXT: movl %eax, %ecx ; CHECK-X32-NEXT: addl $8, %ecx ; CHECK-X32-NEXT: movl %ecx, 8(%esp) -; CHECK-X32-NEXT: .LBB0_18: # %entry +; CHECK-X32-NEXT: .LBB0_20: # %entry ; CHECK-X32-NEXT: movl (%eax), %r8d ; CHECK-X32-NEXT: movl 16(%esp), %eax ; CHECK-X32-NEXT: cmpl $48, %eax -; CHECK-X32-NEXT: jae .LBB0_20 -; CHECK-X32-NEXT: # %bb.19: # %entry +; CHECK-X32-NEXT: jae .LBB0_22 +; CHECK-X32-NEXT: # %bb.21: # %entry ; CHECK-X32-NEXT: addl $8, %eax ; CHECK-X32-NEXT: movl %eax, 16(%esp) -; CHECK-X32-NEXT: jmp .LBB0_21 -; CHECK-X32-NEXT: .LBB0_20: # %entry +; CHECK-X32-NEXT: jmp .LBB0_23 +; CHECK-X32-NEXT: .LBB0_22: # %entry ; CHECK-X32-NEXT: movl 24(%esp), %eax ; CHECK-X32-NEXT: addl $8, %eax ; CHECK-X32-NEXT: movl %eax, 24(%esp) -; CHECK-X32-NEXT: .LBB0_21: # %entry +; CHECK-X32-NEXT: .LBB0_23: # %entry ; CHECK-X32-NEXT: movl (%esp), %eax ; CHECK-X32-NEXT: cmpl $48, %eax -; CHECK-X32-NEXT: jae .LBB0_23 -; CHECK-X32-NEXT: # %bb.22: # %entry +; CHECK-X32-NEXT: jae .LBB0_25 +; CHECK-X32-NEXT: # %bb.24: # %entry ; CHECK-X32-NEXT: addl $8, %eax ; CHECK-X32-NEXT: movl %eax, (%esp) -; CHECK-X32-NEXT: jmp .LBB0_24 -; CHECK-X32-NEXT: .LBB0_23: # %entry +; CHECK-X32-NEXT: jmp .LBB0_26 +; CHECK-X32-NEXT: .LBB0_25: # %entry ; CHECK-X32-NEXT: movl 8(%esp), %eax ; CHECK-X32-NEXT: addl $8, %eax ; CHECK-X32-NEXT: movl %eax, 8(%esp) -; CHECK-X32-NEXT: .LBB0_24: # %entry +; CHECK-X32-NEXT: .LBB0_26: # %entry ; CHECK-X32-NEXT: movl 16(%esp), %ecx ; CHECK-X32-NEXT: cmpl $48, %ecx -; CHECK-X32-NEXT: jae .LBB0_26 -; CHECK-X32-NEXT: # %bb.25: # %entry +; CHECK-X32-NEXT: jae .LBB0_28 +; CHECK-X32-NEXT: # %bb.27: # %entry ; CHECK-X32-NEXT: movl 28(%esp), %eax ; CHECK-X32-NEXT: addl %ecx, %eax ; CHECK-X32-NEXT: addl $8, %ecx ; CHECK-X32-NEXT: movl %ecx, 16(%esp) -; CHECK-X32-NEXT: jmp .LBB0_27 -; CHECK-X32-NEXT: .LBB0_26: # %entry +; CHECK-X32-NEXT: jmp .LBB0_29 +; CHECK-X32-NEXT: .LBB0_28: # %entry ; CHECK-X32-NEXT: movl 24(%esp), %eax ; CHECK-X32-NEXT: movl %eax, %ecx ; CHECK-X32-NEXT: addl $8, %ecx ; CHECK-X32-NEXT: movl %ecx, 24(%esp) -; CHECK-X32-NEXT: .LBB0_27: # %entry +; CHECK-X32-NEXT: .LBB0_29: # %entry ; CHECK-X32-NEXT: movq (%eax), %rcx ; CHECK-X32-NEXT: movl (%esp), %edx ; CHECK-X32-NEXT: cmpl $48, %edx -; CHECK-X32-NEXT: jae .LBB0_29 -; CHECK-X32-NEXT: # %bb.28: # %entry +; CHECK-X32-NEXT: jae .LBB0_31 +; CHECK-X32-NEXT: # %bb.30: # %entry ; CHECK-X32-NEXT: movl 12(%esp), %eax ; CHECK-X32-NEXT: addl %edx, %eax ; CHECK-X32-NEXT: addl $8, %edx ; CHECK-X32-NEXT: movl %edx, (%esp) -; CHECK-X32-NEXT: jmp .LBB0_30 -; CHECK-X32-NEXT: .LBB0_29: # %entry +; CHECK-X32-NEXT: jmp .LBB0_32 +; CHECK-X32-NEXT: .LBB0_31: # %entry ; CHECK-X32-NEXT: movl 8(%esp), %eax ; CHECK-X32-NEXT: movl %eax, %edx ; CHECK-X32-NEXT: addl $8, %edx ; CHECK-X32-NEXT: movl %edx, 8(%esp) -; CHECK-X32-NEXT: .LBB0_30: # %entry +; CHECK-X32-NEXT: .LBB0_32: # %entry ; CHECK-X32-NEXT: movl (%eax), %edx ; CHECK-X32-NEXT: movl 16(%esp), %eax ; CHECK-X32-NEXT: cmpl $48, %eax -; CHECK-X32-NEXT: jae .LBB0_32 -; CHECK-X32-NEXT: # %bb.31: # %entry +; CHECK-X32-NEXT: jae .LBB0_34 +; CHECK-X32-NEXT: # %bb.33: # %entry ; CHECK-X32-NEXT: addl $8, %eax ; CHECK-X32-NEXT: movl %eax, 16(%esp) -; CHECK-X32-NEXT: jmp .LBB0_33 -; CHECK-X32-NEXT: .LBB0_32: # %entry +; CHECK-X32-NEXT: jmp .LBB0_35 +; CHECK-X32-NEXT: .LBB0_34: # %entry ; CHECK-X32-NEXT: movl 24(%esp), %eax ; CHECK-X32-NEXT: addl $8, %eax ; CHECK-X32-NEXT: movl %eax, 24(%esp) -; CHECK-X32-NEXT: .LBB0_33: # %entry +; CHECK-X32-NEXT: .LBB0_35: # %entry ; CHECK-X32-NEXT: movl 4(%esp), %eax ; CHECK-X32-NEXT: cmpl $176, %eax -; CHECK-X32-NEXT: jae .LBB0_35 -; CHECK-X32-NEXT: # %bb.34: # %entry +; CHECK-X32-NEXT: jae .LBB0_37 +; CHECK-X32-NEXT: # %bb.36: # %entry ; CHECK-X32-NEXT: addl $16, %eax ; CHECK-X32-NEXT: movl %eax, 4(%esp) -; CHECK-X32-NEXT: jmp .LBB0_36 -; CHECK-X32-NEXT: .LBB0_35: # %entry +; CHECK-X32-NEXT: jmp .LBB0_38 +; CHECK-X32-NEXT: .LBB0_37: # %entry ; CHECK-X32-NEXT: movl 8(%esp), %eax ; CHECK-X32-NEXT: addl $8, %eax ; CHECK-X32-NEXT: movl %eax, 8(%esp) -; CHECK-X32-NEXT: .LBB0_36: # %entry +; CHECK-X32-NEXT: .LBB0_38: # %entry ; CHECK-X32-NEXT: movl 20(%esp), %esi ; CHECK-X32-NEXT: cmpl $176, %esi -; CHECK-X32-NEXT: jae .LBB0_38 -; CHECK-X32-NEXT: # %bb.37: # %entry +; CHECK-X32-NEXT: jae .LBB0_40 +; CHECK-X32-NEXT: # %bb.39: # %entry ; CHECK-X32-NEXT: movl 28(%esp), %eax ; CHECK-X32-NEXT: addl %esi, %eax ; CHECK-X32-NEXT: addl $16, %esi ; CHECK-X32-NEXT: movl %esi, 20(%esp) -; CHECK-X32-NEXT: jmp .LBB0_39 -; CHECK-X32-NEXT: .LBB0_38: # %entry +; CHECK-X32-NEXT: jmp .LBB0_41 +; CHECK-X32-NEXT: .LBB0_40: # %entry ; CHECK-X32-NEXT: movl 24(%esp), %eax ; CHECK-X32-NEXT: movl %eax, %esi ; CHECK-X32-NEXT: addl $8, %esi ; CHECK-X32-NEXT: movl %esi, 24(%esp) -; CHECK-X32-NEXT: .LBB0_39: # %entry +; CHECK-X32-NEXT: .LBB0_41: # %entry ; CHECK-X32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-X32-NEXT: movl (%esp), %esi ; CHECK-X32-NEXT: cmpl $48, %esi -; CHECK-X32-NEXT: jae .LBB0_41 -; CHECK-X32-NEXT: # %bb.40: # %entry +; CHECK-X32-NEXT: jae .LBB0_43 +; CHECK-X32-NEXT: # %bb.42: # %entry ; CHECK-X32-NEXT: movl 12(%esp), %eax ; CHECK-X32-NEXT: addl %esi, %eax ; CHECK-X32-NEXT: addl $8, %esi ; CHECK-X32-NEXT: movl %esi, (%esp) -; CHECK-X32-NEXT: jmp .LBB0_42 -; CHECK-X32-NEXT: .LBB0_41: # %entry +; CHECK-X32-NEXT: jmp .LBB0_44 +; CHECK-X32-NEXT: .LBB0_43: # %entry ; CHECK-X32-NEXT: movl 8(%esp), %eax ; CHECK-X32-NEXT: movl %eax, %esi ; CHECK-X32-NEXT: addl $8, %esi ; CHECK-X32-NEXT: movl %esi, 8(%esp) -; CHECK-X32-NEXT: .LBB0_42: # %entry +; CHECK-X32-NEXT: .LBB0_44: # %entry ; CHECK-X32-NEXT: movl (%eax), %esi ; CHECK-X32-NEXT: movl 16(%esp), %eax ; CHECK-X32-NEXT: cmpl $48, %eax -; CHECK-X32-NEXT: jae .LBB0_44 -; CHECK-X32-NEXT: # %bb.43: # %entry +; CHECK-X32-NEXT: jae .LBB0_46 +; CHECK-X32-NEXT: # %bb.45: # %entry ; CHECK-X32-NEXT: addl $8, %eax ; CHECK-X32-NEXT: movl %eax, 16(%esp) -; CHECK-X32-NEXT: jmp .LBB0_45 -; CHECK-X32-NEXT: .LBB0_44: # %entry +; CHECK-X32-NEXT: jmp .LBB0_47 +; CHECK-X32-NEXT: .LBB0_46: # %entry ; CHECK-X32-NEXT: movl 24(%esp), %eax ; CHECK-X32-NEXT: addl $8, %eax ; CHECK-X32-NEXT: movl %eax, 24(%esp) -; CHECK-X32-NEXT: .LBB0_45: # %entry +; CHECK-X32-NEXT: .LBB0_47: # %entry ; CHECK-X32-NEXT: movl $.str, %edi ; CHECK-X32-NEXT: movb $2, %al ; CHECK-X32-NEXT: pushq %r10 diff --git a/llvm/test/CodeGen/X86/x86-shrink-wrap-unwind.ll b/llvm/test/CodeGen/X86/x86-shrink-wrap-unwind.ll index 02d4d88a21682..e4361204d6c9f 100644 --- a/llvm/test/CodeGen/X86/x86-shrink-wrap-unwind.ll +++ b/llvm/test/CodeGen/X86/x86-shrink-wrap-unwind.ll @@ -308,17 +308,17 @@ define void @with_nounwind(i1 %cond) nounwind personality ptr @my_personality { ; CHECK-NEXT: pushq %rax ; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: testb $1, %dil -; CHECK-NEXT: jne LBB4_1 -; CHECK-NEXT: ## %bb.4: ## %return +; CHECK-NEXT: jne LBB4_2 +; CHECK-NEXT: ## %bb.1: ## %return ; CHECK-NEXT: popq %rax ; CHECK-NEXT: retq -; CHECK-NEXT: LBB4_1: ## %throw +; CHECK-NEXT: LBB4_2: ## %throw ; CHECK-NEXT: Ltmp0: ## EH_LABEL ; CHECK-NEXT: callq _throw_exception ; CHECK-NEXT: Ltmp1: ## EH_LABEL -; CHECK-NEXT: ## %bb.2: ## %unreachable +; CHECK-NEXT: ## %bb.3: ## %unreachable ; CHECK-NEXT: ud2 -; CHECK-NEXT: LBB4_3: ## %landing +; CHECK-NEXT: LBB4_4: ## %landing ; CHECK-NEXT: Ltmp2: ## EH_LABEL ; CHECK-NEXT: popq %rax ; CHECK-NEXT: retq @@ -329,18 +329,18 @@ define void @with_nounwind(i1 %cond) nounwind personality ptr @my_personality { ; NOCOMPACTUNWIND-NEXT: pushq %rax ; NOCOMPACTUNWIND-NEXT: .cfi_def_cfa_offset 16 ; NOCOMPACTUNWIND-NEXT: testb $1, %dil -; NOCOMPACTUNWIND-NEXT: jne .LBB4_1 -; NOCOMPACTUNWIND-NEXT: # %bb.4: # %return +; NOCOMPACTUNWIND-NEXT: jne .LBB4_2 +; NOCOMPACTUNWIND-NEXT: # %bb.1: # %return ; NOCOMPACTUNWIND-NEXT: popq %rax ; NOCOMPACTUNWIND-NEXT: .cfi_def_cfa_offset 8 ; NOCOMPACTUNWIND-NEXT: retq -; NOCOMPACTUNWIND-NEXT: .LBB4_1: # %throw +; NOCOMPACTUNWIND-NEXT: .LBB4_2: # %throw ; NOCOMPACTUNWIND-NEXT: .cfi_def_cfa_offset 16 ; NOCOMPACTUNWIND-NEXT: .Ltmp0: # EH_LABEL ; NOCOMPACTUNWIND-NEXT: callq throw_exception@PLT ; NOCOMPACTUNWIND-NEXT: .Ltmp1: # EH_LABEL -; NOCOMPACTUNWIND-NEXT: # %bb.2: # %unreachable -; NOCOMPACTUNWIND-NEXT: .LBB4_3: # %landing +; NOCOMPACTUNWIND-NEXT: # %bb.3: # %unreachable +; NOCOMPACTUNWIND-NEXT: .LBB4_4: # %landing ; NOCOMPACTUNWIND-NEXT: .Ltmp2: # EH_LABEL ; NOCOMPACTUNWIND-NEXT: popq %rax ; NOCOMPACTUNWIND-NEXT: .cfi_def_cfa_offset 8 @@ -371,47 +371,47 @@ define void @with_nounwind_same_succ(i1 %cond) nounwind personality ptr @my_pers ; CHECK-LABEL: with_nounwind_same_succ: ; CHECK: ## %bb.0: ## %entry ; CHECK-NEXT: testb $1, %dil -; CHECK-NEXT: je LBB5_4 +; CHECK-NEXT: je LBB5_3 ; CHECK-NEXT: ## %bb.1: ## %throw ; CHECK-NEXT: pushq %rax ; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: Ltmp3: ## EH_LABEL ; CHECK-NEXT: callq _throw_exception ; CHECK-NEXT: Ltmp4: ## EH_LABEL -; CHECK-NEXT: LBB5_3: ## %fallthrough +; CHECK-NEXT: LBB5_2: ## %fallthrough ; CHECK-NEXT: ## InlineAsm Start ; CHECK-NEXT: nop ; CHECK-NEXT: ## InlineAsm End ; CHECK-NEXT: popq %rax -; CHECK-NEXT: LBB5_4: ## %return +; CHECK-NEXT: LBB5_3: ## %return ; CHECK-NEXT: retq -; CHECK-NEXT: LBB5_2: ## %landing +; CHECK-NEXT: LBB5_4: ## %landing ; CHECK-NEXT: Ltmp5: ## EH_LABEL -; CHECK-NEXT: jmp LBB5_3 +; CHECK-NEXT: jmp LBB5_2 ; CHECK-NEXT: Lfunc_end1: ; ; NOCOMPACTUNWIND-LABEL: with_nounwind_same_succ: ; NOCOMPACTUNWIND: # %bb.0: # %entry ; NOCOMPACTUNWIND-NEXT: testb $1, %dil -; NOCOMPACTUNWIND-NEXT: je .LBB5_4 +; NOCOMPACTUNWIND-NEXT: je .LBB5_3 ; NOCOMPACTUNWIND-NEXT: # %bb.1: # %throw ; NOCOMPACTUNWIND-NEXT: pushq %rax ; NOCOMPACTUNWIND-NEXT: .cfi_def_cfa_offset 16 ; NOCOMPACTUNWIND-NEXT: .Ltmp3: # EH_LABEL ; NOCOMPACTUNWIND-NEXT: callq throw_exception@PLT ; NOCOMPACTUNWIND-NEXT: .Ltmp4: # EH_LABEL -; NOCOMPACTUNWIND-NEXT: .LBB5_3: # %fallthrough +; NOCOMPACTUNWIND-NEXT: .LBB5_2: # %fallthrough ; NOCOMPACTUNWIND-NEXT: #APP ; NOCOMPACTUNWIND-NEXT: nop ; NOCOMPACTUNWIND-NEXT: #NO_APP ; NOCOMPACTUNWIND-NEXT: popq %rax ; NOCOMPACTUNWIND-NEXT: .cfi_def_cfa_offset 8 -; NOCOMPACTUNWIND-NEXT: .LBB5_4: # %return +; NOCOMPACTUNWIND-NEXT: .LBB5_3: # %return ; NOCOMPACTUNWIND-NEXT: retq -; NOCOMPACTUNWIND-NEXT: .LBB5_2: # %landing +; NOCOMPACTUNWIND-NEXT: .LBB5_4: # %landing ; NOCOMPACTUNWIND-NEXT: .cfi_def_cfa_offset 16 ; NOCOMPACTUNWIND-NEXT: .Ltmp5: # EH_LABEL -; NOCOMPACTUNWIND-NEXT: jmp .LBB5_3 +; NOCOMPACTUNWIND-NEXT: jmp .LBB5_2 entry: br i1 %cond, label %throw, label %return diff --git a/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll b/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll index 37620ecf8c1b8..5253c396bc1b8 100644 --- a/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll +++ b/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll @@ -640,10 +640,10 @@ define void @useLEA(ptr readonly %x) { ; ENABLE-LABEL: useLEA: ; ENABLE: ## %bb.0: ## %entry ; ENABLE-NEXT: testq %rdi, %rdi -; ENABLE-NEXT: je LBB8_9 +; ENABLE-NEXT: je LBB8_5 ; ENABLE-NEXT: ## %bb.1: ## %if.end ; ENABLE-NEXT: cmpw $66, (%rdi) -; ENABLE-NEXT: jne LBB8_9 +; ENABLE-NEXT: jne LBB8_5 ; ENABLE-NEXT: ## %bb.2: ## %lor.lhs.false ; ENABLE-NEXT: pushq %rax ; ENABLE-NEXT: .cfi_def_cfa_offset 16 @@ -651,62 +651,62 @@ define void @useLEA(ptr readonly %x) { ; ENABLE-NEXT: movzwl (%rdi), %eax ; ENABLE-NEXT: leal -54(%rax), %ecx ; ENABLE-NEXT: cmpl $14, %ecx -; ENABLE-NEXT: ja LBB8_3 -; ENABLE-NEXT: ## %bb.7: ## %lor.lhs.false +; ENABLE-NEXT: ja LBB8_6 +; ENABLE-NEXT: ## %bb.3: ## %lor.lhs.false ; ENABLE-NEXT: movl $24599, %edx ## imm = 0x6017 ; ENABLE-NEXT: btl %ecx, %edx -; ENABLE-NEXT: jae LBB8_3 -; ENABLE-NEXT: LBB8_8: +; ENABLE-NEXT: jae LBB8_6 +; ENABLE-NEXT: LBB8_4: ; ENABLE-NEXT: addq $8, %rsp -; ENABLE-NEXT: LBB8_9: ## %cleanup +; ENABLE-NEXT: LBB8_5: ## %cleanup ; ENABLE-NEXT: retq -; ENABLE-NEXT: LBB8_3: ## %lor.lhs.false +; ENABLE-NEXT: LBB8_6: ## %lor.lhs.false ; ENABLE-NEXT: cmpl $134, %eax -; ENABLE-NEXT: je LBB8_8 -; ENABLE-NEXT: ## %bb.4: ## %lor.lhs.false +; ENABLE-NEXT: je LBB8_4 +; ENABLE-NEXT: ## %bb.7: ## %lor.lhs.false ; ENABLE-NEXT: cmpl $140, %eax -; ENABLE-NEXT: je LBB8_8 -; ENABLE-NEXT: ## %bb.5: ## %if.end.55 +; ENABLE-NEXT: je LBB8_4 +; ENABLE-NEXT: ## %bb.8: ## %if.end.55 ; ENABLE-NEXT: callq _find_temp_slot_from_address ; ENABLE-NEXT: testq %rax, %rax -; ENABLE-NEXT: je LBB8_8 -; ENABLE-NEXT: ## %bb.6: ## %if.then.60 +; ENABLE-NEXT: je LBB8_4 +; ENABLE-NEXT: ## %bb.9: ## %if.then.60 ; ENABLE-NEXT: movb $1, 57(%rax) -; ENABLE-NEXT: jmp LBB8_8 +; ENABLE-NEXT: jmp LBB8_4 ; ; DISABLE-LABEL: useLEA: ; DISABLE: ## %bb.0: ## %entry ; DISABLE-NEXT: pushq %rax ; DISABLE-NEXT: .cfi_def_cfa_offset 16 ; DISABLE-NEXT: testq %rdi, %rdi -; DISABLE-NEXT: je LBB8_7 +; DISABLE-NEXT: je LBB8_4 ; DISABLE-NEXT: ## %bb.1: ## %if.end ; DISABLE-NEXT: cmpw $66, (%rdi) -; DISABLE-NEXT: jne LBB8_7 +; DISABLE-NEXT: jne LBB8_4 ; DISABLE-NEXT: ## %bb.2: ## %lor.lhs.false ; DISABLE-NEXT: movq 8(%rdi), %rdi ; DISABLE-NEXT: movzwl (%rdi), %eax ; DISABLE-NEXT: leal -54(%rax), %ecx ; DISABLE-NEXT: cmpl $14, %ecx -; DISABLE-NEXT: ja LBB8_3 -; DISABLE-NEXT: ## %bb.8: ## %lor.lhs.false +; DISABLE-NEXT: ja LBB8_5 +; DISABLE-NEXT: ## %bb.3: ## %lor.lhs.false ; DISABLE-NEXT: movl $24599, %edx ## imm = 0x6017 ; DISABLE-NEXT: btl %ecx, %edx -; DISABLE-NEXT: jae LBB8_3 -; DISABLE-NEXT: LBB8_7: ## %cleanup +; DISABLE-NEXT: jae LBB8_5 +; DISABLE-NEXT: LBB8_4: ## %cleanup ; DISABLE-NEXT: popq %rax ; DISABLE-NEXT: retq -; DISABLE-NEXT: LBB8_3: ## %lor.lhs.false +; DISABLE-NEXT: LBB8_5: ## %lor.lhs.false ; DISABLE-NEXT: cmpl $134, %eax -; DISABLE-NEXT: je LBB8_7 -; DISABLE-NEXT: ## %bb.4: ## %lor.lhs.false +; DISABLE-NEXT: je LBB8_4 +; DISABLE-NEXT: ## %bb.6: ## %lor.lhs.false ; DISABLE-NEXT: cmpl $140, %eax -; DISABLE-NEXT: je LBB8_7 -; DISABLE-NEXT: ## %bb.5: ## %if.end.55 +; DISABLE-NEXT: je LBB8_4 +; DISABLE-NEXT: ## %bb.7: ## %if.end.55 ; DISABLE-NEXT: callq _find_temp_slot_from_address ; DISABLE-NEXT: testq %rax, %rax -; DISABLE-NEXT: je LBB8_7 -; DISABLE-NEXT: ## %bb.6: ## %if.then.60 +; DISABLE-NEXT: je LBB8_4 +; DISABLE-NEXT: ## %bb.8: ## %if.then.60 ; DISABLE-NEXT: movb $1, 57(%rax) ; DISABLE-NEXT: popq %rax ; DISABLE-NEXT: retq @@ -904,15 +904,15 @@ define void @infiniteloop2() { ; ENABLE-NEXT: addq $-16, %rax ; ENABLE-NEXT: movq %rax, %rsp ; ENABLE-NEXT: xorl %ecx, %ecx -; ENABLE-NEXT: jmp LBB11_2 +; ENABLE-NEXT: jmp LBB11_3 ; ENABLE-NEXT: .p2align 4 -; ENABLE-NEXT: LBB11_4: ## %body2 -; ENABLE-NEXT: ## in Loop: Header=BB11_2 Depth=1 +; ENABLE-NEXT: LBB11_2: ## %body2 +; ENABLE-NEXT: ## in Loop: Header=BB11_3 Depth=1 ; ENABLE-NEXT: ## InlineAsm Start ; ENABLE-NEXT: nop ; ENABLE-NEXT: ## InlineAsm End ; ENABLE-NEXT: movl $1, %ecx -; ENABLE-NEXT: LBB11_2: ## %for.body +; ENABLE-NEXT: LBB11_3: ## %for.body ; ENABLE-NEXT: ## =>This Inner Loop Header: Depth=1 ; ENABLE-NEXT: movl %ecx, %edx ; ENABLE-NEXT: ## InlineAsm Start @@ -921,13 +921,13 @@ define void @infiniteloop2() { ; ENABLE-NEXT: addl %edx, %ecx ; ENABLE-NEXT: movl %ecx, (%rax) ; ENABLE-NEXT: testb %al, %al -; ENABLE-NEXT: jne LBB11_4 -; ENABLE-NEXT: ## %bb.3: ## %body1 -; ENABLE-NEXT: ## in Loop: Header=BB11_2 Depth=1 +; ENABLE-NEXT: jne LBB11_2 +; ENABLE-NEXT: ## %bb.4: ## %body1 +; ENABLE-NEXT: ## in Loop: Header=BB11_3 Depth=1 ; ENABLE-NEXT: ## InlineAsm Start ; ENABLE-NEXT: nop ; ENABLE-NEXT: ## InlineAsm End -; ENABLE-NEXT: jmp LBB11_2 +; ENABLE-NEXT: jmp LBB11_3 ; ENABLE-NEXT: LBB11_5: ## %if.end ; ENABLE-NEXT: leaq -8(%rbp), %rsp ; ENABLE-NEXT: popq %rbx @@ -951,15 +951,15 @@ define void @infiniteloop2() { ; DISABLE-NEXT: addq $-16, %rax ; DISABLE-NEXT: movq %rax, %rsp ; DISABLE-NEXT: xorl %ecx, %ecx -; DISABLE-NEXT: jmp LBB11_2 +; DISABLE-NEXT: jmp LBB11_3 ; DISABLE-NEXT: .p2align 4 -; DISABLE-NEXT: LBB11_4: ## %body2 -; DISABLE-NEXT: ## in Loop: Header=BB11_2 Depth=1 +; DISABLE-NEXT: LBB11_2: ## %body2 +; DISABLE-NEXT: ## in Loop: Header=BB11_3 Depth=1 ; DISABLE-NEXT: ## InlineAsm Start ; DISABLE-NEXT: nop ; DISABLE-NEXT: ## InlineAsm End ; DISABLE-NEXT: movl $1, %ecx -; DISABLE-NEXT: LBB11_2: ## %for.body +; DISABLE-NEXT: LBB11_3: ## %for.body ; DISABLE-NEXT: ## =>This Inner Loop Header: Depth=1 ; DISABLE-NEXT: movl %ecx, %edx ; DISABLE-NEXT: ## InlineAsm Start @@ -968,13 +968,13 @@ define void @infiniteloop2() { ; DISABLE-NEXT: addl %edx, %ecx ; DISABLE-NEXT: movl %ecx, (%rax) ; DISABLE-NEXT: testb %al, %al -; DISABLE-NEXT: jne LBB11_4 -; DISABLE-NEXT: ## %bb.3: ## %body1 -; DISABLE-NEXT: ## in Loop: Header=BB11_2 Depth=1 +; DISABLE-NEXT: jne LBB11_2 +; DISABLE-NEXT: ## %bb.4: ## %body1 +; DISABLE-NEXT: ## in Loop: Header=BB11_3 Depth=1 ; DISABLE-NEXT: ## InlineAsm Start ; DISABLE-NEXT: nop ; DISABLE-NEXT: ## InlineAsm End -; DISABLE-NEXT: jmp LBB11_2 +; DISABLE-NEXT: jmp LBB11_3 ; DISABLE-NEXT: LBB11_5: ## %if.end ; DISABLE-NEXT: leaq -8(%rbp), %rsp ; DISABLE-NEXT: popq %rbx @@ -1014,7 +1014,7 @@ define void @infiniteloop3() { ; ENABLE-NEXT: jne LBB12_2 ; ENABLE-NEXT: ## %bb.1: ## %body ; ENABLE-NEXT: testb %al, %al -; ENABLE-NEXT: jne LBB12_7 +; ENABLE-NEXT: jne LBB12_6 ; ENABLE-NEXT: LBB12_2: ## %loop2a.preheader ; ENABLE-NEXT: xorl %eax, %eax ; ENABLE-NEXT: xorl %ecx, %ecx @@ -1035,7 +1035,7 @@ define void @infiniteloop3() { ; ENABLE-NEXT: movq %rdx, %rax ; ENABLE-NEXT: movq %rdx, %rsi ; ENABLE-NEXT: jmp LBB12_4 -; ENABLE-NEXT: LBB12_7: ## %end +; ENABLE-NEXT: LBB12_6: ## %end ; ENABLE-NEXT: retq ; ; DISABLE-LABEL: infiniteloop3: @@ -1044,7 +1044,7 @@ define void @infiniteloop3() { ; DISABLE-NEXT: jne LBB12_2 ; DISABLE-NEXT: ## %bb.1: ## %body ; DISABLE-NEXT: testb %al, %al -; DISABLE-NEXT: jne LBB12_7 +; DISABLE-NEXT: jne LBB12_6 ; DISABLE-NEXT: LBB12_2: ## %loop2a.preheader ; DISABLE-NEXT: xorl %eax, %eax ; DISABLE-NEXT: xorl %ecx, %ecx @@ -1065,7 +1065,7 @@ define void @infiniteloop3() { ; DISABLE-NEXT: movq %rdx, %rax ; DISABLE-NEXT: movq %rdx, %rsi ; DISABLE-NEXT: jmp LBB12_4 -; DISABLE-NEXT: LBB12_7: ## %end +; DISABLE-NEXT: LBB12_6: ## %end ; DISABLE-NEXT: retq entry: br i1 poison, label %loop2a, label %body @@ -1376,15 +1376,15 @@ define i32 @irreducibleCFG() #4 { ; ENABLE-NEXT: LBB16_2: ## %split ; ENABLE-NEXT: movq _irreducibleCFGb@GOTPCREL(%rip), %rax ; ENABLE-NEXT: cmpl $0, (%rax) -; ENABLE-NEXT: je LBB16_3 -; ENABLE-NEXT: ## %bb.4: ## %for.body4.i +; ENABLE-NEXT: je LBB16_4 +; ENABLE-NEXT: ## %bb.3: ## %for.body4.i ; ENABLE-NEXT: movq _irreducibleCFGa@GOTPCREL(%rip), %rax ; ENABLE-NEXT: movl (%rax), %edi ; ENABLE-NEXT: xorl %ebx, %ebx ; ENABLE-NEXT: xorl %eax, %eax ; ENABLE-NEXT: callq _something ; ENABLE-NEXT: jmp LBB16_5 -; ENABLE-NEXT: LBB16_3: +; ENABLE-NEXT: LBB16_4: ; ENABLE-NEXT: xorl %ebx, %ebx ; ENABLE-NEXT: .p2align 4 ; ENABLE-NEXT: LBB16_5: ## %for.inc @@ -1419,15 +1419,15 @@ define i32 @irreducibleCFG() #4 { ; DISABLE-NEXT: LBB16_2: ## %split ; DISABLE-NEXT: movq _irreducibleCFGb@GOTPCREL(%rip), %rax ; DISABLE-NEXT: cmpl $0, (%rax) -; DISABLE-NEXT: je LBB16_3 -; DISABLE-NEXT: ## %bb.4: ## %for.body4.i +; DISABLE-NEXT: je LBB16_4 +; DISABLE-NEXT: ## %bb.3: ## %for.body4.i ; DISABLE-NEXT: movq _irreducibleCFGa@GOTPCREL(%rip), %rax ; DISABLE-NEXT: movl (%rax), %edi ; DISABLE-NEXT: xorl %ebx, %ebx ; DISABLE-NEXT: xorl %eax, %eax ; DISABLE-NEXT: callq _something ; DISABLE-NEXT: jmp LBB16_5 -; DISABLE-NEXT: LBB16_3: +; DISABLE-NEXT: LBB16_4: ; DISABLE-NEXT: xorl %ebx, %ebx ; DISABLE-NEXT: .p2align 4 ; DISABLE-NEXT: LBB16_5: ## %for.inc @@ -1502,18 +1502,18 @@ define void @infiniteLoopNoSuccessor() #5 { ; ENABLE-NEXT: callq _somethingElse ; ENABLE-NEXT: movq _y@GOTPCREL(%rip), %rax ; ENABLE-NEXT: cmpl $0, (%rax) -; ENABLE-NEXT: je LBB17_3 -; ENABLE-NEXT: ## %bb.5: +; ENABLE-NEXT: je LBB17_4 +; ENABLE-NEXT: ## %bb.3: ; ENABLE-NEXT: popq %rbp ; ENABLE-NEXT: retq -; ENABLE-NEXT: LBB17_3: +; ENABLE-NEXT: LBB17_4: ; ENABLE-NEXT: xorl %eax, %eax ; ENABLE-NEXT: callq _something ; ENABLE-NEXT: .p2align 4 -; ENABLE-NEXT: LBB17_4: ## =>This Inner Loop Header: Depth=1 +; ENABLE-NEXT: LBB17_5: ## =>This Inner Loop Header: Depth=1 ; ENABLE-NEXT: xorl %eax, %eax ; ENABLE-NEXT: callq _somethingElse -; ENABLE-NEXT: jmp LBB17_4 +; ENABLE-NEXT: jmp LBB17_5 ; ; DISABLE-LABEL: infiniteLoopNoSuccessor: ; DISABLE: ## %bb.0: @@ -1529,18 +1529,18 @@ define void @infiniteLoopNoSuccessor() #5 { ; DISABLE-NEXT: callq _somethingElse ; DISABLE-NEXT: movq _y@GOTPCREL(%rip), %rax ; DISABLE-NEXT: cmpl $0, (%rax) -; DISABLE-NEXT: je LBB17_3 -; DISABLE-NEXT: ## %bb.5: +; DISABLE-NEXT: je LBB17_4 +; DISABLE-NEXT: ## %bb.3: ; DISABLE-NEXT: popq %rbp ; DISABLE-NEXT: retq -; DISABLE-NEXT: LBB17_3: +; DISABLE-NEXT: LBB17_4: ; DISABLE-NEXT: xorl %eax, %eax ; DISABLE-NEXT: callq _something ; DISABLE-NEXT: .p2align 4 -; DISABLE-NEXT: LBB17_4: ## =>This Inner Loop Header: Depth=1 +; DISABLE-NEXT: LBB17_5: ## =>This Inner Loop Header: Depth=1 ; DISABLE-NEXT: xorl %eax, %eax ; DISABLE-NEXT: callq _somethingElse -; DISABLE-NEXT: jmp LBB17_4 +; DISABLE-NEXT: jmp LBB17_5 %1 = load i32, ptr @x, align 4 %2 = icmp ne i32 %1, 0 br i1 %2, label %3, label %4 diff --git a/llvm/test/CodeGen/X86/x86-win64-shrink-wrapping.ll b/llvm/test/CodeGen/X86/x86-win64-shrink-wrapping.ll index 8eccfe6664166..9826cc5cd7cf0 100644 --- a/llvm/test/CodeGen/X86/x86-win64-shrink-wrapping.ll +++ b/llvm/test/CodeGen/X86/x86-win64-shrink-wrapping.ll @@ -17,7 +17,7 @@ define i32 @loopInfoSaveOutsideLoop(i32 %cond, i32 %N) #0 { ; ENABLE-NEXT: .seh_pushreg %rbx ; ENABLE-NEXT: .seh_endprologue ; ENABLE-NEXT: testl %ecx, %ecx -; ENABLE-NEXT: je .LBB0_5 +; ENABLE-NEXT: je .LBB0_4 ; ENABLE-NEXT: # %bb.1: # %for.preheader ; ENABLE-NEXT: #APP ; ENABLE-NEXT: nop @@ -42,7 +42,7 @@ define i32 @loopInfoSaveOutsideLoop(i32 %cond, i32 %N) #0 { ; ENABLE-NEXT: popq %rbx ; ENABLE-NEXT: .seh_endepilogue ; ENABLE-NEXT: retq -; ENABLE-NEXT: .LBB0_5: # %if.else +; ENABLE-NEXT: .LBB0_4: # %if.else ; ENABLE-NEXT: movl %edx, %eax ; ENABLE-NEXT: addl %edx, %eax ; ENABLE-NEXT: .seh_startepilogue @@ -57,7 +57,7 @@ define i32 @loopInfoSaveOutsideLoop(i32 %cond, i32 %N) #0 { ; DISABLE-NEXT: .seh_pushreg %rbx ; DISABLE-NEXT: .seh_endprologue ; DISABLE-NEXT: testl %ecx, %ecx -; DISABLE-NEXT: je .LBB0_5 +; DISABLE-NEXT: je .LBB0_4 ; DISABLE-NEXT: # %bb.1: # %for.preheader ; DISABLE-NEXT: #APP ; DISABLE-NEXT: nop @@ -82,7 +82,7 @@ define i32 @loopInfoSaveOutsideLoop(i32 %cond, i32 %N) #0 { ; DISABLE-NEXT: popq %rbx ; DISABLE-NEXT: .seh_endepilogue ; DISABLE-NEXT: retq -; DISABLE-NEXT: .LBB0_5: # %if.else +; DISABLE-NEXT: .LBB0_4: # %if.else ; DISABLE-NEXT: movl %edx, %eax ; DISABLE-NEXT: addl %edx, %eax ; DISABLE-NEXT: .seh_startepilogue @@ -167,7 +167,7 @@ define i32 @loopInfoSaveOutsideLoop2(i32 %cond, i32 %N) #0 { ; DISABLE-NEXT: .seh_pushreg %rbx ; DISABLE-NEXT: .seh_endprologue ; DISABLE-NEXT: testl %ecx, %ecx -; DISABLE-NEXT: je .LBB1_5 +; DISABLE-NEXT: je .LBB1_4 ; DISABLE-NEXT: # %bb.1: # %for.preheader ; DISABLE-NEXT: #APP ; DISABLE-NEXT: nop @@ -192,7 +192,7 @@ define i32 @loopInfoSaveOutsideLoop2(i32 %cond, i32 %N) #0 { ; DISABLE-NEXT: popq %rbx ; DISABLE-NEXT: .seh_endepilogue ; DISABLE-NEXT: retq -; DISABLE-NEXT: .LBB1_5: # %if.else +; DISABLE-NEXT: .LBB1_4: # %if.else ; DISABLE-NEXT: addl %edx, %edx ; DISABLE-NEXT: movl %edx, %eax ; DISABLE-NEXT: .seh_startepilogue diff --git a/llvm/test/CodeGen/X86/xaluo.ll b/llvm/test/CodeGen/X86/xaluo.ll index c2a8002c949ce..3be69247a658a 100644 --- a/llvm/test/CodeGen/X86/xaluo.ll +++ b/llvm/test/CodeGen/X86/xaluo.ll @@ -641,23 +641,23 @@ define zeroext i1 @saddobri32(i32 %v1, i32 %v2) { ; SDAG-LABEL: saddobri32: ; SDAG: ## %bb.0: ; SDAG-NEXT: addl %esi, %edi -; SDAG-NEXT: jo LBB31_1 -; SDAG-NEXT: ## %bb.2: ## %continue +; SDAG-NEXT: jo LBB31_2 +; SDAG-NEXT: ## %bb.1: ## %continue ; SDAG-NEXT: movb $1, %al ; SDAG-NEXT: retq -; SDAG-NEXT: LBB31_1: ## %overflow +; SDAG-NEXT: LBB31_2: ## %overflow ; SDAG-NEXT: xorl %eax, %eax ; SDAG-NEXT: retq ; ; FAST-LABEL: saddobri32: ; FAST: ## %bb.0: ; FAST-NEXT: addl %esi, %edi -; FAST-NEXT: jo LBB31_1 -; FAST-NEXT: ## %bb.2: ## %continue +; FAST-NEXT: jo LBB31_2 +; FAST-NEXT: ## %bb.1: ## %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al ; FAST-NEXT: retq -; FAST-NEXT: LBB31_1: ## %overflow +; FAST-NEXT: LBB31_2: ## %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al ; FAST-NEXT: ## kill: def $al killed $al killed $eax @@ -678,23 +678,23 @@ define zeroext i1 @saddobri64(i64 %v1, i64 %v2) { ; SDAG-LABEL: saddobri64: ; SDAG: ## %bb.0: ; SDAG-NEXT: addq %rsi, %rdi -; SDAG-NEXT: jo LBB32_1 -; SDAG-NEXT: ## %bb.2: ## %continue +; SDAG-NEXT: jo LBB32_2 +; SDAG-NEXT: ## %bb.1: ## %continue ; SDAG-NEXT: movb $1, %al ; SDAG-NEXT: retq -; SDAG-NEXT: LBB32_1: ## %overflow +; SDAG-NEXT: LBB32_2: ## %overflow ; SDAG-NEXT: xorl %eax, %eax ; SDAG-NEXT: retq ; ; FAST-LABEL: saddobri64: ; FAST: ## %bb.0: ; FAST-NEXT: addq %rsi, %rdi -; FAST-NEXT: jo LBB32_1 -; FAST-NEXT: ## %bb.2: ## %continue +; FAST-NEXT: jo LBB32_2 +; FAST-NEXT: ## %bb.1: ## %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al ; FAST-NEXT: retq -; FAST-NEXT: LBB32_1: ## %overflow +; FAST-NEXT: LBB32_2: ## %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al ; FAST-NEXT: ## kill: def $al killed $al killed $eax @@ -715,23 +715,23 @@ define zeroext i1 @uaddobri32(i32 %v1, i32 %v2) { ; SDAG-LABEL: uaddobri32: ; SDAG: ## %bb.0: ; SDAG-NEXT: addl %esi, %edi -; SDAG-NEXT: jb LBB33_1 -; SDAG-NEXT: ## %bb.2: ## %continue +; SDAG-NEXT: jb LBB33_2 +; SDAG-NEXT: ## %bb.1: ## %continue ; SDAG-NEXT: movb $1, %al ; SDAG-NEXT: retq -; SDAG-NEXT: LBB33_1: ## %overflow +; SDAG-NEXT: LBB33_2: ## %overflow ; SDAG-NEXT: xorl %eax, %eax ; SDAG-NEXT: retq ; ; FAST-LABEL: uaddobri32: ; FAST: ## %bb.0: ; FAST-NEXT: addl %esi, %edi -; FAST-NEXT: jb LBB33_1 -; FAST-NEXT: ## %bb.2: ## %continue +; FAST-NEXT: jb LBB33_2 +; FAST-NEXT: ## %bb.1: ## %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al ; FAST-NEXT: retq -; FAST-NEXT: LBB33_1: ## %overflow +; FAST-NEXT: LBB33_2: ## %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al ; FAST-NEXT: ## kill: def $al killed $al killed $eax @@ -752,23 +752,23 @@ define zeroext i1 @uaddobri64(i64 %v1, i64 %v2) { ; SDAG-LABEL: uaddobri64: ; SDAG: ## %bb.0: ; SDAG-NEXT: addq %rsi, %rdi -; SDAG-NEXT: jb LBB34_1 -; SDAG-NEXT: ## %bb.2: ## %continue +; SDAG-NEXT: jb LBB34_2 +; SDAG-NEXT: ## %bb.1: ## %continue ; SDAG-NEXT: movb $1, %al ; SDAG-NEXT: retq -; SDAG-NEXT: LBB34_1: ## %overflow +; SDAG-NEXT: LBB34_2: ## %overflow ; SDAG-NEXT: xorl %eax, %eax ; SDAG-NEXT: retq ; ; FAST-LABEL: uaddobri64: ; FAST: ## %bb.0: ; FAST-NEXT: addq %rsi, %rdi -; FAST-NEXT: jb LBB34_1 -; FAST-NEXT: ## %bb.2: ## %continue +; FAST-NEXT: jb LBB34_2 +; FAST-NEXT: ## %bb.1: ## %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al ; FAST-NEXT: retq -; FAST-NEXT: LBB34_1: ## %overflow +; FAST-NEXT: LBB34_2: ## %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al ; FAST-NEXT: ## kill: def $al killed $al killed $eax @@ -789,23 +789,23 @@ define zeroext i1 @ssubobri32(i32 %v1, i32 %v2) { ; SDAG-LABEL: ssubobri32: ; SDAG: ## %bb.0: ; SDAG-NEXT: cmpl %esi, %edi -; SDAG-NEXT: jo LBB35_1 -; SDAG-NEXT: ## %bb.2: ## %continue +; SDAG-NEXT: jo LBB35_2 +; SDAG-NEXT: ## %bb.1: ## %continue ; SDAG-NEXT: movb $1, %al ; SDAG-NEXT: retq -; SDAG-NEXT: LBB35_1: ## %overflow +; SDAG-NEXT: LBB35_2: ## %overflow ; SDAG-NEXT: xorl %eax, %eax ; SDAG-NEXT: retq ; ; FAST-LABEL: ssubobri32: ; FAST: ## %bb.0: ; FAST-NEXT: cmpl %esi, %edi -; FAST-NEXT: jo LBB35_1 -; FAST-NEXT: ## %bb.2: ## %continue +; FAST-NEXT: jo LBB35_2 +; FAST-NEXT: ## %bb.1: ## %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al ; FAST-NEXT: retq -; FAST-NEXT: LBB35_1: ## %overflow +; FAST-NEXT: LBB35_2: ## %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al ; FAST-NEXT: ## kill: def $al killed $al killed $eax @@ -826,23 +826,23 @@ define zeroext i1 @ssubobri64(i64 %v1, i64 %v2) { ; SDAG-LABEL: ssubobri64: ; SDAG: ## %bb.0: ; SDAG-NEXT: cmpq %rsi, %rdi -; SDAG-NEXT: jo LBB36_1 -; SDAG-NEXT: ## %bb.2: ## %continue +; SDAG-NEXT: jo LBB36_2 +; SDAG-NEXT: ## %bb.1: ## %continue ; SDAG-NEXT: movb $1, %al ; SDAG-NEXT: retq -; SDAG-NEXT: LBB36_1: ## %overflow +; SDAG-NEXT: LBB36_2: ## %overflow ; SDAG-NEXT: xorl %eax, %eax ; SDAG-NEXT: retq ; ; FAST-LABEL: ssubobri64: ; FAST: ## %bb.0: ; FAST-NEXT: cmpq %rsi, %rdi -; FAST-NEXT: jo LBB36_1 -; FAST-NEXT: ## %bb.2: ## %continue +; FAST-NEXT: jo LBB36_2 +; FAST-NEXT: ## %bb.1: ## %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al ; FAST-NEXT: retq -; FAST-NEXT: LBB36_1: ## %overflow +; FAST-NEXT: LBB36_2: ## %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al ; FAST-NEXT: ## kill: def $al killed $al killed $eax @@ -863,23 +863,23 @@ define zeroext i1 @usubobri32(i32 %v1, i32 %v2) { ; SDAG-LABEL: usubobri32: ; SDAG: ## %bb.0: ; SDAG-NEXT: cmpl %esi, %edi -; SDAG-NEXT: jb LBB37_1 -; SDAG-NEXT: ## %bb.2: ## %continue +; SDAG-NEXT: jb LBB37_2 +; SDAG-NEXT: ## %bb.1: ## %continue ; SDAG-NEXT: movb $1, %al ; SDAG-NEXT: retq -; SDAG-NEXT: LBB37_1: ## %overflow +; SDAG-NEXT: LBB37_2: ## %overflow ; SDAG-NEXT: xorl %eax, %eax ; SDAG-NEXT: retq ; ; FAST-LABEL: usubobri32: ; FAST: ## %bb.0: ; FAST-NEXT: cmpl %esi, %edi -; FAST-NEXT: jb LBB37_1 -; FAST-NEXT: ## %bb.2: ## %continue +; FAST-NEXT: jb LBB37_2 +; FAST-NEXT: ## %bb.1: ## %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al ; FAST-NEXT: retq -; FAST-NEXT: LBB37_1: ## %overflow +; FAST-NEXT: LBB37_2: ## %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al ; FAST-NEXT: ## kill: def $al killed $al killed $eax @@ -900,23 +900,23 @@ define zeroext i1 @usubobri64(i64 %v1, i64 %v2) { ; SDAG-LABEL: usubobri64: ; SDAG: ## %bb.0: ; SDAG-NEXT: cmpq %rsi, %rdi -; SDAG-NEXT: jb LBB38_1 -; SDAG-NEXT: ## %bb.2: ## %continue +; SDAG-NEXT: jb LBB38_2 +; SDAG-NEXT: ## %bb.1: ## %continue ; SDAG-NEXT: movb $1, %al ; SDAG-NEXT: retq -; SDAG-NEXT: LBB38_1: ## %overflow +; SDAG-NEXT: LBB38_2: ## %overflow ; SDAG-NEXT: xorl %eax, %eax ; SDAG-NEXT: retq ; ; FAST-LABEL: usubobri64: ; FAST: ## %bb.0: ; FAST-NEXT: cmpq %rsi, %rdi -; FAST-NEXT: jb LBB38_1 -; FAST-NEXT: ## %bb.2: ## %continue +; FAST-NEXT: jb LBB38_2 +; FAST-NEXT: ## %bb.1: ## %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al ; FAST-NEXT: retq -; FAST-NEXT: LBB38_1: ## %overflow +; FAST-NEXT: LBB38_2: ## %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al ; FAST-NEXT: ## kill: def $al killed $al killed $eax diff --git a/llvm/test/CodeGen/X86/xchg-nofold.ll b/llvm/test/CodeGen/X86/xchg-nofold.ll index 16f07ad954abb..aa386f8907596 100644 --- a/llvm/test/CodeGen/X86/xchg-nofold.ll +++ b/llvm/test/CodeGen/X86/xchg-nofold.ll @@ -14,18 +14,18 @@ define zeroext i1 @_Z3fooRSt6atomicIbEb(ptr nocapture dereferenceable(1) %a, i1 ; CHECK-NEXT: shrq $3, %rcx ; CHECK-NEXT: movzbl 2147450880(%rcx), %ecx ; CHECK-NEXT: testb %cl, %cl -; CHECK-NEXT: je .LBB0_3 +; CHECK-NEXT: je .LBB0_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: movl %edi, %edx ; CHECK-NEXT: andb $7, %dl ; CHECK-NEXT: cmpb %cl, %dl -; CHECK-NEXT: jge .LBB0_2 -; CHECK-NEXT: .LBB0_3: +; CHECK-NEXT: jge .LBB0_3 +; CHECK-NEXT: .LBB0_2: ; CHECK-NEXT: movl %eax, %ecx ; CHECK-NEXT: xchgb %cl, (%rdi) ; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: retq -; CHECK-NEXT: .LBB0_2: +; CHECK-NEXT: .LBB0_3: ; CHECK-NEXT: pushq %rax ; CHECK-NEXT: callq __asan_report_store1@PLT ; CHECK-NEXT: #APP diff --git a/llvm/test/CodeGen/X86/xmulo.ll b/llvm/test/CodeGen/X86/xmulo.ll index a076d0d762aa3..c142426b51a1a 100644 --- a/llvm/test/CodeGen/X86/xmulo.ll +++ b/llvm/test/CodeGen/X86/xmulo.ll @@ -731,11 +731,11 @@ define zeroext i1 @smulobri8(i8 %v1, i8 %v2) { ; SDAG-NEXT: movl %edi, %eax ; SDAG-NEXT: # kill: def $al killed $al killed $eax ; SDAG-NEXT: imulb %sil -; SDAG-NEXT: jo .LBB15_1 -; SDAG-NEXT: # %bb.2: # %continue +; SDAG-NEXT: jo .LBB15_2 +; SDAG-NEXT: # %bb.1: # %continue ; SDAG-NEXT: movb $1, %al ; SDAG-NEXT: retq -; SDAG-NEXT: .LBB15_1: # %overflow +; SDAG-NEXT: .LBB15_2: # %overflow ; SDAG-NEXT: xorl %eax, %eax ; SDAG-NEXT: retq ; @@ -746,12 +746,12 @@ define zeroext i1 @smulobri8(i8 %v1, i8 %v2) { ; FAST-NEXT: imulb %sil ; FAST-NEXT: seto %al ; FAST-NEXT: testb $1, %al -; FAST-NEXT: jne .LBB15_1 -; FAST-NEXT: # %bb.2: # %continue +; FAST-NEXT: jne .LBB15_2 +; FAST-NEXT: # %bb.1: # %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al ; FAST-NEXT: retq -; FAST-NEXT: .LBB15_1: # %overflow +; FAST-NEXT: .LBB15_2: # %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al ; FAST-NEXT: # kill: def $al killed $al killed $eax @@ -761,11 +761,11 @@ define zeroext i1 @smulobri8(i8 %v1, i8 %v2) { ; WIN64: # %bb.0: ; WIN64-NEXT: movl %ecx, %eax ; WIN64-NEXT: imulb %dl -; WIN64-NEXT: jo .LBB15_1 -; WIN64-NEXT: # %bb.2: # %continue +; WIN64-NEXT: jo .LBB15_2 +; WIN64-NEXT: # %bb.1: # %continue ; WIN64-NEXT: movb $1, %al ; WIN64-NEXT: retq -; WIN64-NEXT: .LBB15_1: # %overflow +; WIN64-NEXT: .LBB15_2: # %overflow ; WIN64-NEXT: xorl %eax, %eax ; WIN64-NEXT: retq ; @@ -773,11 +773,11 @@ define zeroext i1 @smulobri8(i8 %v1, i8 %v2) { ; WIN32: # %bb.0: ; WIN32-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; WIN32-NEXT: imulb {{[0-9]+}}(%esp) -; WIN32-NEXT: jo LBB15_1 -; WIN32-NEXT: # %bb.2: # %continue +; WIN32-NEXT: jo LBB15_2 +; WIN32-NEXT: # %bb.1: # %continue ; WIN32-NEXT: movb $1, %al ; WIN32-NEXT: retl -; WIN32-NEXT: LBB15_1: # %overflow +; WIN32-NEXT: LBB15_2: # %overflow ; WIN32-NEXT: xorl %eax, %eax ; WIN32-NEXT: retl %t = call {i8, i1} @llvm.smul.with.overflow.i8(i8 %v1, i8 %v2) @@ -796,11 +796,11 @@ define zeroext i1 @smulobri16(i16 %v1, i16 %v2) { ; SDAG-LABEL: smulobri16: ; SDAG: # %bb.0: ; SDAG-NEXT: imulw %si, %di -; SDAG-NEXT: jo .LBB16_1 -; SDAG-NEXT: # %bb.2: # %continue +; SDAG-NEXT: jo .LBB16_2 +; SDAG-NEXT: # %bb.1: # %continue ; SDAG-NEXT: movb $1, %al ; SDAG-NEXT: retq -; SDAG-NEXT: .LBB16_1: # %overflow +; SDAG-NEXT: .LBB16_2: # %overflow ; SDAG-NEXT: xorl %eax, %eax ; SDAG-NEXT: retq ; @@ -809,12 +809,12 @@ define zeroext i1 @smulobri16(i16 %v1, i16 %v2) { ; FAST-NEXT: imulw %si, %di ; FAST-NEXT: seto %al ; FAST-NEXT: testb $1, %al -; FAST-NEXT: jne .LBB16_1 -; FAST-NEXT: # %bb.2: # %continue +; FAST-NEXT: jne .LBB16_2 +; FAST-NEXT: # %bb.1: # %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al ; FAST-NEXT: retq -; FAST-NEXT: .LBB16_1: # %overflow +; FAST-NEXT: .LBB16_2: # %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al ; FAST-NEXT: # kill: def $al killed $al killed $eax @@ -823,11 +823,11 @@ define zeroext i1 @smulobri16(i16 %v1, i16 %v2) { ; WIN64-LABEL: smulobri16: ; WIN64: # %bb.0: ; WIN64-NEXT: imulw %dx, %cx -; WIN64-NEXT: jo .LBB16_1 -; WIN64-NEXT: # %bb.2: # %continue +; WIN64-NEXT: jo .LBB16_2 +; WIN64-NEXT: # %bb.1: # %continue ; WIN64-NEXT: movb $1, %al ; WIN64-NEXT: retq -; WIN64-NEXT: .LBB16_1: # %overflow +; WIN64-NEXT: .LBB16_2: # %overflow ; WIN64-NEXT: xorl %eax, %eax ; WIN64-NEXT: retq ; @@ -835,11 +835,11 @@ define zeroext i1 @smulobri16(i16 %v1, i16 %v2) { ; WIN32: # %bb.0: ; WIN32-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; WIN32-NEXT: imulw {{[0-9]+}}(%esp), %ax -; WIN32-NEXT: jo LBB16_1 -; WIN32-NEXT: # %bb.2: # %continue +; WIN32-NEXT: jo LBB16_2 +; WIN32-NEXT: # %bb.1: # %continue ; WIN32-NEXT: movb $1, %al ; WIN32-NEXT: retl -; WIN32-NEXT: LBB16_1: # %overflow +; WIN32-NEXT: LBB16_2: # %overflow ; WIN32-NEXT: xorl %eax, %eax ; WIN32-NEXT: retl %t = call {i16, i1} @llvm.smul.with.overflow.i16(i16 %v1, i16 %v2) @@ -858,23 +858,23 @@ define zeroext i1 @smulobri32(i32 %v1, i32 %v2) { ; SDAG-LABEL: smulobri32: ; SDAG: # %bb.0: ; SDAG-NEXT: imull %esi, %edi -; SDAG-NEXT: jo .LBB17_1 -; SDAG-NEXT: # %bb.2: # %continue +; SDAG-NEXT: jo .LBB17_2 +; SDAG-NEXT: # %bb.1: # %continue ; SDAG-NEXT: movb $1, %al ; SDAG-NEXT: retq -; SDAG-NEXT: .LBB17_1: # %overflow +; SDAG-NEXT: .LBB17_2: # %overflow ; SDAG-NEXT: xorl %eax, %eax ; SDAG-NEXT: retq ; ; FAST-LABEL: smulobri32: ; FAST: # %bb.0: ; FAST-NEXT: imull %esi, %edi -; FAST-NEXT: jo .LBB17_1 -; FAST-NEXT: # %bb.2: # %continue +; FAST-NEXT: jo .LBB17_2 +; FAST-NEXT: # %bb.1: # %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al ; FAST-NEXT: retq -; FAST-NEXT: .LBB17_1: # %overflow +; FAST-NEXT: .LBB17_2: # %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al ; FAST-NEXT: # kill: def $al killed $al killed $eax @@ -883,11 +883,11 @@ define zeroext i1 @smulobri32(i32 %v1, i32 %v2) { ; WIN64-LABEL: smulobri32: ; WIN64: # %bb.0: ; WIN64-NEXT: imull %edx, %ecx -; WIN64-NEXT: jo .LBB17_1 -; WIN64-NEXT: # %bb.2: # %continue +; WIN64-NEXT: jo .LBB17_2 +; WIN64-NEXT: # %bb.1: # %continue ; WIN64-NEXT: movb $1, %al ; WIN64-NEXT: retq -; WIN64-NEXT: .LBB17_1: # %overflow +; WIN64-NEXT: .LBB17_2: # %overflow ; WIN64-NEXT: xorl %eax, %eax ; WIN64-NEXT: retq ; @@ -895,11 +895,11 @@ define zeroext i1 @smulobri32(i32 %v1, i32 %v2) { ; WIN32: # %bb.0: ; WIN32-NEXT: movl {{[0-9]+}}(%esp), %eax ; WIN32-NEXT: imull {{[0-9]+}}(%esp), %eax -; WIN32-NEXT: jo LBB17_1 -; WIN32-NEXT: # %bb.2: # %continue +; WIN32-NEXT: jo LBB17_2 +; WIN32-NEXT: # %bb.1: # %continue ; WIN32-NEXT: movb $1, %al ; WIN32-NEXT: retl -; WIN32-NEXT: LBB17_1: # %overflow +; WIN32-NEXT: LBB17_2: # %overflow ; WIN32-NEXT: xorl %eax, %eax ; WIN32-NEXT: retl %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2) @@ -918,23 +918,23 @@ define zeroext i1 @smulobri64(i64 %v1, i64 %v2) { ; SDAG-LABEL: smulobri64: ; SDAG: # %bb.0: ; SDAG-NEXT: imulq %rsi, %rdi -; SDAG-NEXT: jo .LBB18_1 -; SDAG-NEXT: # %bb.2: # %continue +; SDAG-NEXT: jo .LBB18_2 +; SDAG-NEXT: # %bb.1: # %continue ; SDAG-NEXT: movb $1, %al ; SDAG-NEXT: retq -; SDAG-NEXT: .LBB18_1: # %overflow +; SDAG-NEXT: .LBB18_2: # %overflow ; SDAG-NEXT: xorl %eax, %eax ; SDAG-NEXT: retq ; ; FAST-LABEL: smulobri64: ; FAST: # %bb.0: ; FAST-NEXT: imulq %rsi, %rdi -; FAST-NEXT: jo .LBB18_1 -; FAST-NEXT: # %bb.2: # %continue +; FAST-NEXT: jo .LBB18_2 +; FAST-NEXT: # %bb.1: # %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al ; FAST-NEXT: retq -; FAST-NEXT: .LBB18_1: # %overflow +; FAST-NEXT: .LBB18_2: # %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al ; FAST-NEXT: # kill: def $al killed $al killed $eax @@ -943,11 +943,11 @@ define zeroext i1 @smulobri64(i64 %v1, i64 %v2) { ; WIN64-LABEL: smulobri64: ; WIN64: # %bb.0: ; WIN64-NEXT: imulq %rdx, %rcx -; WIN64-NEXT: jo .LBB18_1 -; WIN64-NEXT: # %bb.2: # %continue +; WIN64-NEXT: jo .LBB18_2 +; WIN64-NEXT: # %bb.1: # %continue ; WIN64-NEXT: movb $1, %al ; WIN64-NEXT: retq -; WIN64-NEXT: .LBB18_1: # %overflow +; WIN64-NEXT: .LBB18_2: # %overflow ; WIN64-NEXT: xorl %eax, %eax ; WIN64-NEXT: retq ; @@ -998,8 +998,8 @@ define zeroext i1 @smulobri64(i64 %v1, i64 %v2) { ; WIN32-NEXT: xorl %esi, %edx ; WIN32-NEXT: xorl %eax, %esi ; WIN32-NEXT: orl %edx, %esi -; WIN32-NEXT: jne LBB18_1 -; WIN32-NEXT: # %bb.3: # %continue +; WIN32-NEXT: jne LBB18_3 +; WIN32-NEXT: # %bb.1: # %continue ; WIN32-NEXT: movb $1, %al ; WIN32-NEXT: LBB18_2: # %overflow ; WIN32-NEXT: addl $4, %esp @@ -1008,7 +1008,7 @@ define zeroext i1 @smulobri64(i64 %v1, i64 %v2) { ; WIN32-NEXT: popl %ebx ; WIN32-NEXT: popl %ebp ; WIN32-NEXT: retl -; WIN32-NEXT: LBB18_1: # %overflow +; WIN32-NEXT: LBB18_3: # %overflow ; WIN32-NEXT: xorl %eax, %eax ; WIN32-NEXT: jmp LBB18_2 %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2) @@ -1029,11 +1029,11 @@ define zeroext i1 @umulobri8(i8 %v1, i8 %v2) { ; SDAG-NEXT: movl %edi, %eax ; SDAG-NEXT: # kill: def $al killed $al killed $eax ; SDAG-NEXT: mulb %sil -; SDAG-NEXT: jo .LBB19_1 -; SDAG-NEXT: # %bb.2: # %continue +; SDAG-NEXT: jo .LBB19_2 +; SDAG-NEXT: # %bb.1: # %continue ; SDAG-NEXT: movb $1, %al ; SDAG-NEXT: retq -; SDAG-NEXT: .LBB19_1: # %overflow +; SDAG-NEXT: .LBB19_2: # %overflow ; SDAG-NEXT: xorl %eax, %eax ; SDAG-NEXT: retq ; @@ -1044,12 +1044,12 @@ define zeroext i1 @umulobri8(i8 %v1, i8 %v2) { ; FAST-NEXT: mulb %sil ; FAST-NEXT: seto %al ; FAST-NEXT: testb $1, %al -; FAST-NEXT: jne .LBB19_1 -; FAST-NEXT: # %bb.2: # %continue +; FAST-NEXT: jne .LBB19_2 +; FAST-NEXT: # %bb.1: # %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al ; FAST-NEXT: retq -; FAST-NEXT: .LBB19_1: # %overflow +; FAST-NEXT: .LBB19_2: # %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al ; FAST-NEXT: # kill: def $al killed $al killed $eax @@ -1059,11 +1059,11 @@ define zeroext i1 @umulobri8(i8 %v1, i8 %v2) { ; WIN64: # %bb.0: ; WIN64-NEXT: movl %ecx, %eax ; WIN64-NEXT: mulb %dl -; WIN64-NEXT: jo .LBB19_1 -; WIN64-NEXT: # %bb.2: # %continue +; WIN64-NEXT: jo .LBB19_2 +; WIN64-NEXT: # %bb.1: # %continue ; WIN64-NEXT: movb $1, %al ; WIN64-NEXT: retq -; WIN64-NEXT: .LBB19_1: # %overflow +; WIN64-NEXT: .LBB19_2: # %overflow ; WIN64-NEXT: xorl %eax, %eax ; WIN64-NEXT: retq ; @@ -1071,11 +1071,11 @@ define zeroext i1 @umulobri8(i8 %v1, i8 %v2) { ; WIN32: # %bb.0: ; WIN32-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; WIN32-NEXT: mulb {{[0-9]+}}(%esp) -; WIN32-NEXT: jo LBB19_1 -; WIN32-NEXT: # %bb.2: # %continue +; WIN32-NEXT: jo LBB19_2 +; WIN32-NEXT: # %bb.1: # %continue ; WIN32-NEXT: movb $1, %al ; WIN32-NEXT: retl -; WIN32-NEXT: LBB19_1: # %overflow +; WIN32-NEXT: LBB19_2: # %overflow ; WIN32-NEXT: xorl %eax, %eax ; WIN32-NEXT: retl %t = call {i8, i1} @llvm.umul.with.overflow.i8(i8 %v1, i8 %v2) @@ -1096,11 +1096,11 @@ define zeroext i1 @umulobri16(i16 %v1, i16 %v2) { ; SDAG-NEXT: movl %edi, %eax ; SDAG-NEXT: # kill: def $ax killed $ax killed $eax ; SDAG-NEXT: mulw %si -; SDAG-NEXT: jo .LBB20_1 -; SDAG-NEXT: # %bb.2: # %continue +; SDAG-NEXT: jo .LBB20_2 +; SDAG-NEXT: # %bb.1: # %continue ; SDAG-NEXT: movb $1, %al ; SDAG-NEXT: retq -; SDAG-NEXT: .LBB20_1: # %overflow +; SDAG-NEXT: .LBB20_2: # %overflow ; SDAG-NEXT: xorl %eax, %eax ; SDAG-NEXT: retq ; @@ -1111,12 +1111,12 @@ define zeroext i1 @umulobri16(i16 %v1, i16 %v2) { ; FAST-NEXT: mulw %si ; FAST-NEXT: seto %al ; FAST-NEXT: testb $1, %al -; FAST-NEXT: jne .LBB20_1 -; FAST-NEXT: # %bb.2: # %continue +; FAST-NEXT: jne .LBB20_2 +; FAST-NEXT: # %bb.1: # %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al ; FAST-NEXT: retq -; FAST-NEXT: .LBB20_1: # %overflow +; FAST-NEXT: .LBB20_2: # %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al ; FAST-NEXT: # kill: def $al killed $al killed $eax @@ -1126,11 +1126,11 @@ define zeroext i1 @umulobri16(i16 %v1, i16 %v2) { ; WIN64: # %bb.0: ; WIN64-NEXT: movl %ecx, %eax ; WIN64-NEXT: mulw %dx -; WIN64-NEXT: jo .LBB20_1 -; WIN64-NEXT: # %bb.2: # %continue +; WIN64-NEXT: jo .LBB20_2 +; WIN64-NEXT: # %bb.1: # %continue ; WIN64-NEXT: movb $1, %al ; WIN64-NEXT: retq -; WIN64-NEXT: .LBB20_1: # %overflow +; WIN64-NEXT: .LBB20_2: # %overflow ; WIN64-NEXT: xorl %eax, %eax ; WIN64-NEXT: retq ; @@ -1138,11 +1138,11 @@ define zeroext i1 @umulobri16(i16 %v1, i16 %v2) { ; WIN32: # %bb.0: ; WIN32-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; WIN32-NEXT: mulw {{[0-9]+}}(%esp) -; WIN32-NEXT: jo LBB20_1 -; WIN32-NEXT: # %bb.2: # %continue +; WIN32-NEXT: jo LBB20_2 +; WIN32-NEXT: # %bb.1: # %continue ; WIN32-NEXT: movb $1, %al ; WIN32-NEXT: retl -; WIN32-NEXT: LBB20_1: # %overflow +; WIN32-NEXT: LBB20_2: # %overflow ; WIN32-NEXT: xorl %eax, %eax ; WIN32-NEXT: retl %t = call {i16, i1} @llvm.umul.with.overflow.i16(i16 %v1, i16 %v2) @@ -1162,11 +1162,11 @@ define zeroext i1 @umulobri32(i32 %v1, i32 %v2) { ; SDAG: # %bb.0: ; SDAG-NEXT: movl %edi, %eax ; SDAG-NEXT: mull %esi -; SDAG-NEXT: jo .LBB21_1 -; SDAG-NEXT: # %bb.2: # %continue +; SDAG-NEXT: jo .LBB21_2 +; SDAG-NEXT: # %bb.1: # %continue ; SDAG-NEXT: movb $1, %al ; SDAG-NEXT: retq -; SDAG-NEXT: .LBB21_1: # %overflow +; SDAG-NEXT: .LBB21_2: # %overflow ; SDAG-NEXT: xorl %eax, %eax ; SDAG-NEXT: retq ; @@ -1174,12 +1174,12 @@ define zeroext i1 @umulobri32(i32 %v1, i32 %v2) { ; FAST: # %bb.0: ; FAST-NEXT: movl %edi, %eax ; FAST-NEXT: mull %esi -; FAST-NEXT: jo .LBB21_1 -; FAST-NEXT: # %bb.2: # %continue +; FAST-NEXT: jo .LBB21_2 +; FAST-NEXT: # %bb.1: # %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al ; FAST-NEXT: retq -; FAST-NEXT: .LBB21_1: # %overflow +; FAST-NEXT: .LBB21_2: # %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al ; FAST-NEXT: # kill: def $al killed $al killed $eax @@ -1189,11 +1189,11 @@ define zeroext i1 @umulobri32(i32 %v1, i32 %v2) { ; WIN64: # %bb.0: ; WIN64-NEXT: movl %ecx, %eax ; WIN64-NEXT: mull %edx -; WIN64-NEXT: jo .LBB21_1 -; WIN64-NEXT: # %bb.2: # %continue +; WIN64-NEXT: jo .LBB21_2 +; WIN64-NEXT: # %bb.1: # %continue ; WIN64-NEXT: movb $1, %al ; WIN64-NEXT: retq -; WIN64-NEXT: .LBB21_1: # %overflow +; WIN64-NEXT: .LBB21_2: # %overflow ; WIN64-NEXT: xorl %eax, %eax ; WIN64-NEXT: retq ; @@ -1201,11 +1201,11 @@ define zeroext i1 @umulobri32(i32 %v1, i32 %v2) { ; WIN32: # %bb.0: ; WIN32-NEXT: movl {{[0-9]+}}(%esp), %eax ; WIN32-NEXT: mull {{[0-9]+}}(%esp) -; WIN32-NEXT: jo LBB21_1 -; WIN32-NEXT: # %bb.2: # %continue +; WIN32-NEXT: jo LBB21_2 +; WIN32-NEXT: # %bb.1: # %continue ; WIN32-NEXT: movb $1, %al ; WIN32-NEXT: retl -; WIN32-NEXT: LBB21_1: # %overflow +; WIN32-NEXT: LBB21_2: # %overflow ; WIN32-NEXT: xorl %eax, %eax ; WIN32-NEXT: retl %t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2) @@ -1225,11 +1225,11 @@ define zeroext i1 @umulobri64(i64 %v1, i64 %v2) { ; SDAG: # %bb.0: ; SDAG-NEXT: movq %rdi, %rax ; SDAG-NEXT: mulq %rsi -; SDAG-NEXT: jo .LBB22_1 -; SDAG-NEXT: # %bb.2: # %continue +; SDAG-NEXT: jo .LBB22_2 +; SDAG-NEXT: # %bb.1: # %continue ; SDAG-NEXT: movb $1, %al ; SDAG-NEXT: retq -; SDAG-NEXT: .LBB22_1: # %overflow +; SDAG-NEXT: .LBB22_2: # %overflow ; SDAG-NEXT: xorl %eax, %eax ; SDAG-NEXT: retq ; @@ -1237,12 +1237,12 @@ define zeroext i1 @umulobri64(i64 %v1, i64 %v2) { ; FAST: # %bb.0: ; FAST-NEXT: movq %rdi, %rax ; FAST-NEXT: mulq %rsi -; FAST-NEXT: jo .LBB22_1 -; FAST-NEXT: # %bb.2: # %continue +; FAST-NEXT: jo .LBB22_2 +; FAST-NEXT: # %bb.1: # %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al ; FAST-NEXT: retq -; FAST-NEXT: .LBB22_1: # %overflow +; FAST-NEXT: .LBB22_2: # %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al ; FAST-NEXT: # kill: def $al killed $al killed $eax @@ -1252,11 +1252,11 @@ define zeroext i1 @umulobri64(i64 %v1, i64 %v2) { ; WIN64: # %bb.0: ; WIN64-NEXT: movq %rcx, %rax ; WIN64-NEXT: mulq %rdx -; WIN64-NEXT: jo .LBB22_1 -; WIN64-NEXT: # %bb.2: # %continue +; WIN64-NEXT: jo .LBB22_2 +; WIN64-NEXT: # %bb.1: # %continue ; WIN64-NEXT: movb $1, %al ; WIN64-NEXT: retq -; WIN64-NEXT: .LBB22_1: # %overflow +; WIN64-NEXT: .LBB22_2: # %overflow ; WIN64-NEXT: xorl %eax, %eax ; WIN64-NEXT: retq ; @@ -1289,8 +1289,8 @@ define zeroext i1 @umulobri64(i64 %v1, i64 %v2) { ; WIN32-NEXT: setb %al ; WIN32-NEXT: orb %ch, %al ; WIN32-NEXT: subb $1, %al -; WIN32-NEXT: je LBB22_1 -; WIN32-NEXT: # %bb.3: # %continue +; WIN32-NEXT: je LBB22_3 +; WIN32-NEXT: # %bb.1: # %continue ; WIN32-NEXT: movb $1, %al ; WIN32-NEXT: LBB22_2: # %overflow ; WIN32-NEXT: popl %esi @@ -1298,7 +1298,7 @@ define zeroext i1 @umulobri64(i64 %v1, i64 %v2) { ; WIN32-NEXT: popl %ebx ; WIN32-NEXT: popl %ebp ; WIN32-NEXT: retl -; WIN32-NEXT: LBB22_1: # %overflow +; WIN32-NEXT: LBB22_3: # %overflow ; WIN32-NEXT: xorl %eax, %eax ; WIN32-NEXT: jmp LBB22_2 %t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2) diff --git a/llvm/test/CodeGen/X86/xor-icmp.ll b/llvm/test/CodeGen/X86/xor-icmp.ll index 16a3b6cb855a7..2b668bb299ff0 100644 --- a/llvm/test/CodeGen/X86/xor-icmp.ll +++ b/llvm/test/CodeGen/X86/xor-icmp.ll @@ -61,11 +61,11 @@ define i32 @t2(i32 %x, i32 %y) nounwind ssp { ; X64-NEXT: testl %esi, %esi ; X64-NEXT: sete %cl ; X64-NEXT: cmpb %al, %cl -; X64-NEXT: je .LBB1_1 -; X64-NEXT: # %bb.2: # %bb +; X64-NEXT: je .LBB1_2 +; X64-NEXT: # %bb.1: # %bb ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: jmp foo # TAILCALL -; X64-NEXT: .LBB1_1: # %return +; X64-NEXT: .LBB1_2: # %return ; X64-NEXT: retq entry: diff --git a/llvm/test/CodeGen/X86/zero-call-used-regs-simd.ll b/llvm/test/CodeGen/X86/zero-call-used-regs-simd.ll index d9253e0ca127b..b29df3186de37 100644 --- a/llvm/test/CodeGen/X86/zero-call-used-regs-simd.ll +++ b/llvm/test/CodeGen/X86/zero-call-used-regs-simd.ll @@ -92,71 +92,71 @@ define void @zero_k(<8 x i32> %arg, <8 x i1> %mask) #0 { ; SSE-NEXT: packsswb %xmm2, %xmm2 ; SSE-NEXT: pmovmskb %xmm2, %eax ; SSE-NEXT: testb $1, %al -; SSE-NEXT: jne .LBB3_1 -; SSE-NEXT: # %bb.2: # %else +; SSE-NEXT: jne .LBB3_10 +; SSE-NEXT: # %bb.1: # %else ; SSE-NEXT: testb $2, %al -; SSE-NEXT: jne .LBB3_3 -; SSE-NEXT: .LBB3_4: # %else2 +; SSE-NEXT: jne .LBB3_11 +; SSE-NEXT: .LBB3_2: # %else2 ; SSE-NEXT: testb $4, %al -; SSE-NEXT: jne .LBB3_5 -; SSE-NEXT: .LBB3_6: # %else4 +; SSE-NEXT: jne .LBB3_12 +; SSE-NEXT: .LBB3_3: # %else4 ; SSE-NEXT: testb $8, %al -; SSE-NEXT: jne .LBB3_7 -; SSE-NEXT: .LBB3_8: # %else6 +; SSE-NEXT: jne .LBB3_13 +; SSE-NEXT: .LBB3_4: # %else6 ; SSE-NEXT: testb $16, %al -; SSE-NEXT: jne .LBB3_9 -; SSE-NEXT: .LBB3_10: # %else8 +; SSE-NEXT: jne .LBB3_14 +; SSE-NEXT: .LBB3_5: # %else8 ; SSE-NEXT: testb $32, %al -; SSE-NEXT: jne .LBB3_11 -; SSE-NEXT: .LBB3_12: # %else10 +; SSE-NEXT: jne .LBB3_15 +; SSE-NEXT: .LBB3_6: # %else10 ; SSE-NEXT: testb $64, %al -; SSE-NEXT: jne .LBB3_13 -; SSE-NEXT: .LBB3_14: # %else12 +; SSE-NEXT: jne .LBB3_16 +; SSE-NEXT: .LBB3_7: # %else12 ; SSE-NEXT: testb $-128, %al -; SSE-NEXT: je .LBB3_16 -; SSE-NEXT: .LBB3_15: # %cond.store13 +; SSE-NEXT: je .LBB3_9 +; SSE-NEXT: .LBB3_8: # %cond.store13 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[3,3,3,3] ; SSE-NEXT: movd %xmm0, 28 -; SSE-NEXT: .LBB3_16: # %else14 +; SSE-NEXT: .LBB3_9: # %else14 ; SSE-NEXT: xorl %eax, %eax ; SSE-NEXT: pxor %xmm0, %xmm0 ; SSE-NEXT: pxor %xmm1, %xmm1 ; SSE-NEXT: pxor %xmm2, %xmm2 ; SSE-NEXT: retq -; SSE-NEXT: .LBB3_1: # %cond.store +; SSE-NEXT: .LBB3_10: # %cond.store ; SSE-NEXT: movd %xmm0, 0 ; SSE-NEXT: testb $2, %al -; SSE-NEXT: je .LBB3_4 -; SSE-NEXT: .LBB3_3: # %cond.store1 +; SSE-NEXT: je .LBB3_2 +; SSE-NEXT: .LBB3_11: # %cond.store1 ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,1,1] ; SSE-NEXT: movd %xmm2, 4 ; SSE-NEXT: testb $4, %al -; SSE-NEXT: je .LBB3_6 -; SSE-NEXT: .LBB3_5: # %cond.store3 +; SSE-NEXT: je .LBB3_3 +; SSE-NEXT: .LBB3_12: # %cond.store3 ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,2,3] ; SSE-NEXT: movd %xmm2, 8 ; SSE-NEXT: testb $8, %al -; SSE-NEXT: je .LBB3_8 -; SSE-NEXT: .LBB3_7: # %cond.store5 +; SSE-NEXT: je .LBB3_4 +; SSE-NEXT: .LBB3_13: # %cond.store5 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE-NEXT: movd %xmm0, 12 ; SSE-NEXT: testb $16, %al -; SSE-NEXT: je .LBB3_10 -; SSE-NEXT: .LBB3_9: # %cond.store7 +; SSE-NEXT: je .LBB3_5 +; SSE-NEXT: .LBB3_14: # %cond.store7 ; SSE-NEXT: movd %xmm1, 16 ; SSE-NEXT: testb $32, %al -; SSE-NEXT: je .LBB3_12 -; SSE-NEXT: .LBB3_11: # %cond.store9 +; SSE-NEXT: je .LBB3_6 +; SSE-NEXT: .LBB3_15: # %cond.store9 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1] ; SSE-NEXT: movd %xmm0, 20 ; SSE-NEXT: testb $64, %al -; SSE-NEXT: je .LBB3_14 -; SSE-NEXT: .LBB3_13: # %cond.store11 +; SSE-NEXT: je .LBB3_7 +; SSE-NEXT: .LBB3_16: # %cond.store11 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3] ; SSE-NEXT: movd %xmm0, 24 ; SSE-NEXT: testb $-128, %al -; SSE-NEXT: jne .LBB3_15 -; SSE-NEXT: jmp .LBB3_16 +; SSE-NEXT: jne .LBB3_8 +; SSE-NEXT: jmp .LBB3_9 ; ; AVX1-LABEL: zero_k: ; AVX1: # %bb.0: diff --git a/llvm/test/CodeGen/X86/zext-extract_subreg.ll b/llvm/test/CodeGen/X86/zext-extract_subreg.ll index 877f11632b768..d5a6c7143646c 100644 --- a/llvm/test/CodeGen/X86/zext-extract_subreg.ll +++ b/llvm/test/CodeGen/X86/zext-extract_subreg.ll @@ -6,27 +6,27 @@ define void @t() nounwind ssp { ; CHECK: ## %bb.0: ## %entry ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne LBB0_6 +; CHECK-NEXT: jne LBB0_2 ; CHECK-NEXT: ## %bb.1: ## %if.end.i ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: je LBB0_2 -; CHECK-NEXT: LBB0_6: ## %return +; CHECK-NEXT: je LBB0_3 +; CHECK-NEXT: LBB0_2: ## %return ; CHECK-NEXT: retq -; CHECK-NEXT: LBB0_2: ## %if.end +; CHECK-NEXT: LBB0_3: ## %if.end ; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: testb %al, %al ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne LBB0_5 -; CHECK-NEXT: ## %bb.3: ## %cond.true190 +; CHECK-NEXT: jne LBB0_6 +; CHECK-NEXT: ## %bb.4: ## %cond.true190 ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: jne LBB0_5 -; CHECK-NEXT: ## %bb.4: ## %cond.true225 +; CHECK-NEXT: jne LBB0_6 +; CHECK-NEXT: ## %bb.5: ## %cond.true225 ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: LBB0_5: ## %cond.false205 +; CHECK-NEXT: LBB0_6: ## %cond.false205 ; CHECK-NEXT: ud2 entry: br i1 undef, label %return, label %if.end.i diff --git a/llvm/test/DebugInfo/COFF/fpo-funclet.ll b/llvm/test/DebugInfo/COFF/fpo-funclet.ll index 260bdd2434ec1..20181a933249d 100644 --- a/llvm/test/DebugInfo/COFF/fpo-funclet.ll +++ b/llvm/test/DebugInfo/COFF/fpo-funclet.ll @@ -21,7 +21,7 @@ ; CHECK: retl ; No FPO directives in the catchpad for now. -; CHECK: "?catch$2@?0??f@@YAXXZ@4HA": +; CHECK: "?catch$3@?0??f@@YAXXZ@4HA": ; CHECK-NOT: .cv_fpo ; CHECK: retl # CATCHRET ; FIXME: This endproc is for the parent function. To get FPO data for diff --git a/llvm/test/DebugInfo/COFF/pieces.ll b/llvm/test/DebugInfo/COFF/pieces.ll index 88c3b7d45a0bb..0c17688664f29 100644 --- a/llvm/test/DebugInfo/COFF/pieces.ll +++ b/llvm/test/DebugInfo/COFF/pieces.ll @@ -37,12 +37,12 @@ ; ASM-LABEL: loop_csr: # @loop_csr ; ASM: #DEBUG_VALUE: loop_csr:o <- [DW_OP_LLVM_fragment 0 32] 0 ; ASM: #DEBUG_VALUE: loop_csr:o <- [DW_OP_LLVM_fragment 32 32] 0 -; ASM: # %bb.2: # %for.body.preheader +; ASM: # %bb.1: # %for.body.preheader ; ASM: xorl %edi, %edi ; ASM: xorl %esi, %esi ; ASM: [[oy_ox_start:\.Ltmp[0-9]+]]: ; ASM: .p2align 4 -; ASM: .LBB0_3: # %for.body +; ASM: .LBB0_2: # %for.body ; ASM: #DEBUG_VALUE: loop_csr:o <- [DW_OP_LLVM_fragment 0 32] $edi ; ASM: #DEBUG_VALUE: loop_csr:o <- [DW_OP_LLVM_fragment 32 32] $esi ; ASM: .cv_loc 0 1 13 11 # t.c:13:11 @@ -58,7 +58,7 @@ ; ASM: [[oy_start:\.Ltmp[0-9]+]]: ; ASM: #DEBUG_VALUE: loop_csr:o <- [DW_OP_LLVM_fragment 32 32] $esi ; ASM: cmpl n(%rip), %eax -; ASM: jl .LBB0_3 +; ASM: jl .LBB0_2 ; ASM: [[loopskip_start:\.Ltmp[0-9]+]]: ; ASM: #DEBUG_VALUE: loop_csr:o <- [DW_OP_LLVM_fragment 0 32] 0 ; ASM: xorl %esi, %esi diff --git a/llvm/test/DebugInfo/X86/dbg-value-transfer-order.ll b/llvm/test/DebugInfo/X86/dbg-value-transfer-order.ll index 1261bc3a1cf6f..59afe24b3d7e3 100644 --- a/llvm/test/DebugInfo/X86/dbg-value-transfer-order.ll +++ b/llvm/test/DebugInfo/X86/dbg-value-transfer-order.ll @@ -24,20 +24,20 @@ ; with the Orders insertion point vector. ; CHECK-LABEL: f: # @f -; CHECK: .LBB0_4: +; CHECK: .LBB0_2: ; Check that this DEBUG_VALUE comes before the left shift. ; CHECK: #DEBUG_VALUE: bit_offset <- $ecx ; CHECK: .cv_loc 0 1 8 28 # t.c:8:28 ; CHECK: movl $1, %[[reg:[^ ]*]] ; CHECK: shll %cl, %[[reg]] -; CHECK: .LBB0_2: # %while.body +; CHECK: .LBB0_3: # %while.body ; CHECK: movl $32, %ecx ; CHECK: testl {{.*}} -; CHECK: jne .LBB0_4 -; CHECK: # %bb.3: # %if.then +; CHECK: jne .LBB0_2 +; CHECK: # %bb.4: # %if.then ; CHECK: callq if_then ; CHECK: movl %eax, %ecx -; CHECK: jmp .LBB0_4 +; CHECK: jmp .LBB0_2 ; ModuleID = 't.c' source_filename = "t.c" diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/lanai_generated_funcs.ll.generated.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/lanai_generated_funcs.ll.generated.expected index a41bc63a285b2..12faa6c68c2e9 100644 --- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/lanai_generated_funcs.ll.generated.expected +++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/lanai_generated_funcs.ll.generated.expected @@ -75,12 +75,12 @@ attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" } ; CHECK-NEXT: st %r0, -12[%fp] ; CHECK-NEXT: sub.f %r0, 0x0, %r0 ; CHECK-NEXT: st %r0, -16[%fp] -; CHECK-NEXT: beq .LBB0_1 +; CHECK-NEXT: beq .LBB0_2 ; CHECK-NEXT: mov 0x1, %r3 -; CHECK-NEXT: .LBB0_2: +; CHECK-NEXT: .LBB0_1: ; CHECK-NEXT: bt .LBB0_3 ; CHECK-NEXT: st %r3, -24[%fp] -; CHECK-NEXT: .LBB0_1: +; CHECK-NEXT: .LBB0_2: ; CHECK-NEXT: st %r3, -16[%fp] ; CHECK-NEXT: mov 0x2, %r3 ; CHECK-NEXT: st %r3, -20[%fp] @@ -91,13 +91,13 @@ attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" } ; CHECK-NEXT: .LBB0_3: ; CHECK-NEXT: ld -16[%fp], %r3 ; CHECK-NEXT: sub.f %r3, 0x0, %r0 -; CHECK-NEXT: beq .LBB0_4 +; CHECK-NEXT: beq .LBB0_5 ; CHECK-NEXT: nop -; CHECK-NEXT: .LBB0_5: +; CHECK-NEXT: .LBB0_4: ; CHECK-NEXT: mov 0x1, %r3 ; CHECK-NEXT: bt .LBB0_6 ; CHECK-NEXT: st %r3, -24[%fp] -; CHECK-NEXT: .LBB0_4: +; CHECK-NEXT: .LBB0_5: ; CHECK-NEXT: mov 0x1, %r3 ; CHECK-NEXT: st %r3, -16[%fp] ; CHECK-NEXT: mov 0x2, %r3 diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/lanai_generated_funcs.ll.nogenerated.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/lanai_generated_funcs.ll.nogenerated.expected index 35ebbf9984738..42e45cc9e5fde 100644 --- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/lanai_generated_funcs.ll.nogenerated.expected +++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/lanai_generated_funcs.ll.nogenerated.expected @@ -16,12 +16,12 @@ define dso_local i32 @check_boundaries() #0 { ; CHECK-NEXT: st %r0, -12[%fp] ; CHECK-NEXT: sub.f %r0, 0x0, %r0 ; CHECK-NEXT: st %r0, -16[%fp] -; CHECK-NEXT: beq .LBB0_1 +; CHECK-NEXT: beq .LBB0_2 ; CHECK-NEXT: mov 0x1, %r3 -; CHECK-NEXT: .LBB0_2: +; CHECK-NEXT: .LBB0_1: ; CHECK-NEXT: bt .LBB0_3 ; CHECK-NEXT: st %r3, -24[%fp] -; CHECK-NEXT: .LBB0_1: +; CHECK-NEXT: .LBB0_2: ; CHECK-NEXT: st %r3, -16[%fp] ; CHECK-NEXT: mov 0x2, %r3 ; CHECK-NEXT: st %r3, -20[%fp] @@ -32,13 +32,13 @@ define dso_local i32 @check_boundaries() #0 { ; CHECK-NEXT: .LBB0_3: ; CHECK-NEXT: ld -16[%fp], %r3 ; CHECK-NEXT: sub.f %r3, 0x0, %r0 -; CHECK-NEXT: beq .LBB0_4 +; CHECK-NEXT: beq .LBB0_5 ; CHECK-NEXT: nop -; CHECK-NEXT: .LBB0_5: +; CHECK-NEXT: .LBB0_4: ; CHECK-NEXT: mov 0x1, %r3 ; CHECK-NEXT: bt .LBB0_6 ; CHECK-NEXT: st %r3, -24[%fp] -; CHECK-NEXT: .LBB0_4: +; CHECK-NEXT: .LBB0_5: ; CHECK-NEXT: mov 0x1, %r3 ; CHECK-NEXT: st %r3, -16[%fp] ; CHECK-NEXT: mov 0x2, %r3 diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_generated_funcs.ll.generated.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_generated_funcs.ll.generated.expected index e74cc7c452034..670e17db21682 100644 --- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_generated_funcs.ll.generated.expected +++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_generated_funcs.ll.generated.expected @@ -74,21 +74,21 @@ attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" } ; CHECK-NEXT: movl $0, -8(%rbp) ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: je .LBB0_1 -; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: je .LBB0_3 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: movl $1, -4(%rbp) ; CHECK-NEXT: cmpl $0, -8(%rbp) ; CHECK-NEXT: je .LBB0_4 -; CHECK-NEXT: .LBB0_5: +; CHECK-NEXT: .LBB0_2: ; CHECK-NEXT: movl $1, -4(%rbp) -; CHECK-NEXT: jmp .LBB0_6 -; CHECK-NEXT: .LBB0_1: +; CHECK-NEXT: jmp .LBB0_5 +; CHECK-NEXT: .LBB0_3: ; CHECK-NEXT: callq OUTLINED_FUNCTION_0 ; CHECK-NEXT: cmpl $0, -8(%rbp) -; CHECK-NEXT: jne .LBB0_5 +; CHECK-NEXT: jne .LBB0_2 ; CHECK-NEXT: .LBB0_4: ; CHECK-NEXT: callq OUTLINED_FUNCTION_0 -; CHECK-NEXT: .LBB0_6: +; CHECK-NEXT: .LBB0_5: ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: addq $20, %rsp ; CHECK-NEXT: popq %rbp diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_generated_funcs.ll.nogenerated.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_generated_funcs.ll.nogenerated.expected index 96f3ac99e21bb..d51dc641aebed 100644 --- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_generated_funcs.ll.nogenerated.expected +++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_generated_funcs.ll.nogenerated.expected @@ -15,21 +15,21 @@ define dso_local i32 @check_boundaries() #0 { ; CHECK-NEXT: movl $0, -8(%rbp) ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al -; CHECK-NEXT: je .LBB0_1 -; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: je .LBB0_3 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: movl $1, -4(%rbp) ; CHECK-NEXT: cmpl $0, -8(%rbp) ; CHECK-NEXT: je .LBB0_4 -; CHECK-NEXT: .LBB0_5: +; CHECK-NEXT: .LBB0_2: ; CHECK-NEXT: movl $1, -4(%rbp) -; CHECK-NEXT: jmp .LBB0_6 -; CHECK-NEXT: .LBB0_1: +; CHECK-NEXT: jmp .LBB0_5 +; CHECK-NEXT: .LBB0_3: ; CHECK-NEXT: callq OUTLINED_FUNCTION_0 ; CHECK-NEXT: cmpl $0, -8(%rbp) -; CHECK-NEXT: jne .LBB0_5 +; CHECK-NEXT: jne .LBB0_2 ; CHECK-NEXT: .LBB0_4: ; CHECK-NEXT: callq OUTLINED_FUNCTION_0 -; CHECK-NEXT: .LBB0_6: +; CHECK-NEXT: .LBB0_5: ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: addq $20, %rsp ; CHECK-NEXT: popq %rbp