diff --git a/llvm/include/llvm/CodeGen/ValueTypes.h b/llvm/include/llvm/CodeGen/ValueTypes.h
index bd7c46c922a88..9ba33c33ecee5 100644
--- a/llvm/include/llvm/CodeGen/ValueTypes.h
+++ b/llvm/include/llvm/CodeGen/ValueTypes.h
@@ -455,14 +455,6 @@ namespace llvm {
       return changeElementType(Context, EltVT);
     }
 
-    /// Return a VT for an integer vector type with the size of the
-    /// elements doubled. The type returned may be an extended type.
-    EVT widenIntegerVectorElementType(LLVMContext &Context) const {
-      EVT EltVT = getVectorElementType();
-      EltVT = EVT::getIntegerVT(Context, 2 * EltVT.getSizeInBits());
-      return EVT::getVectorVT(Context, EltVT, getVectorElementCount());
-    }
-
     // Return a VT for a vector type with the same element type but
     // half the number of elements. The type returned may be an
     // extended type.
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 564bf3b7f152e..1de9e0b25b068 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -2910,7 +2910,7 @@ void DAGTypeLegalizer::SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo,
   if (SrcVT.getVectorElementCount().isKnownEven() &&
       SrcVT.getScalarSizeInBits() * 2 < DestVT.getScalarSizeInBits()) {
     LLVMContext &Ctx = *DAG.getContext();
-    EVT NewSrcVT = SrcVT.widenIntegerVectorElementType(Ctx);
+    EVT NewSrcVT = SrcVT.widenIntegerElementType(Ctx);
     EVT SplitSrcVT = SrcVT.getHalfNumVectorElementsVT(Ctx);
 
     EVT SplitLoVT, SplitHiVT;
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 38db1ac4a2fb9..d16983254e44a 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -26424,7 +26424,7 @@ static SDValue performMSTORECombine(SDNode *N,
           Value.getValueType().getHalfNumVectorElementsVT(*DAG.getContext());
       EVT InVT = Value.getOperand(0).getValueType();
 
-      if (HalfVT.widenIntegerVectorElementType(*DAG.getContext()) == InVT) {
+      if (HalfVT.widenIntegerElementType(*DAG.getContext()) == InVT) {
         unsigned MinSVESize = Subtarget->getMinSVEVectorSizeInBits();
         unsigned PgPattern = Mask->getConstantOperandVal(0);
 
@@ -30093,7 +30093,7 @@ void AArch64TargetLowering::ReplaceExtractSubVectorResults(
 
   unsigned Opcode = (Index == 0) ? (unsigned)ISD::ANY_EXTEND_VECTOR_INREG
                                  : (unsigned)AArch64ISD::UUNPKHI;
-  EVT ExtendedHalfVT = VT.widenIntegerVectorElementType(*DAG.getContext());
+  EVT ExtendedHalfVT = VT.widenIntegerElementType(*DAG.getContext());
 
   SDValue Half = DAG.getNode(Opcode, DL, ExtendedHalfVT, N->getOperand(0));
   Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, Half));
@@ -31778,11 +31778,11 @@ SDValue AArch64TargetLowering::LowerFixedLengthVectorIntDivideToSVE(
 
   // Scalable vector i8/i16 DIV is not supported. Promote it to i32.
   EVT HalfVT = VT.getHalfNumVectorElementsVT(*DAG.getContext());
-  EVT PromVT = HalfVT.widenIntegerVectorElementType(*DAG.getContext());
+  EVT PromVT = HalfVT.widenIntegerElementType(*DAG.getContext());
   unsigned ExtendOpcode = Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
 
   // If the wider type is legal: extend, op, and truncate.
-  EVT WideVT = VT.widenIntegerVectorElementType(*DAG.getContext());
+  EVT WideVT = VT.widenIntegerElementType(*DAG.getContext());
   if (DAG.getTargetLoweringInfo().isTypeLegal(WideVT)) {
     SDValue Op0 = DAG.getNode(ExtendOpcode, DL, WideVT, Op.getOperand(0));
     SDValue Op1 = DAG.getNode(ExtendOpcode, DL, WideVT, Op.getOperand(1));
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
index 874ea2be79a33..9cdd841e2e5be 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -2377,7 +2377,7 @@ WebAssemblyTargetLowering::LowerEXTEND_VECTOR_INREG(SDValue Op,
   while (Scale != 1) {
     Ret = DAG.getNode(Ext, DL,
                       Ret.getValueType()
-                          .widenIntegerVectorElementType(*DAG.getContext())
+                          .widenIntegerElementType(*DAG.getContext())
                           .getHalfNumVectorElementsVT(*DAG.getContext()),
                       Ret);
     Scale /= 2;
diff --git a/llvm/unittests/CodeGen/ScalableVectorMVTsTest.cpp b/llvm/unittests/CodeGen/ScalableVectorMVTsTest.cpp
index c343465ae4c72..42b4737b17baf 100644
--- a/llvm/unittests/CodeGen/ScalableVectorMVTsTest.cpp
+++ b/llvm/unittests/CodeGen/ScalableVectorMVTsTest.cpp
@@ -58,7 +58,7 @@ TEST(ScalableVectorMVTsTest, HelperFuncs) {
   ASSERT_TRUE(Vnx2i64.isScalableVector());
 
   // Check that changing scalar types/element count works
-  EXPECT_EQ(Vnx2i32.widenIntegerVectorElementType(Ctx), Vnx2i64);
+  EXPECT_EQ(Vnx2i32.widenIntegerElementType(Ctx), Vnx2i64);
   EXPECT_EQ(Vnx4i32.getHalfNumVectorElementsVT(Ctx), Vnx2i32);
 
   // Check that operators work
@@ -94,7 +94,7 @@ TEST(ScalableVectorMVTsTest, IRToVTTranslation) {
   VectorType *ScV8Int64Ty =
       VectorType::get(Int64Ty, ElementCount::getScalable(8));
 
-  // Check that we can map a scalable IR type to an MVT 
+  // Check that we can map a scalable IR type to an MVT
   MVT Mnxv8i64 = MVT::getVT(ScV8Int64Ty);
   ASSERT_TRUE(Mnxv8i64.isScalableVector());
   ASSERT_EQ(ScV8Int64Ty->getElementCount(), Mnxv8i64.getVectorElementCount());