diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index d9d303cd07b92..62a1fb16c0a44 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -2122,14 +2122,18 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr,
   case NEON::BI__builtin_neon_vdups_laneq_f32:
   case NEON::BI__builtin_neon_vgetq_lane_f64:
   case NEON::BI__builtin_neon_vdupd_laneq_f64:
-  case NEON::BI__builtin_neon_vaddh_f16:
-  case NEON::BI__builtin_neon_vsubh_f16:
-  case NEON::BI__builtin_neon_vmulh_f16:
-  case NEON::BI__builtin_neon_vdivh_f16:
     cgm.errorNYI(expr->getSourceRange(),
                  std::string("unimplemented AArch64 builtin call: ") +
                      getContext().BuiltinInfo.getName(builtinID));
     return mlir::Value{};
+  case NEON::BI__builtin_neon_vaddh_f16:
+    return builder.createFAdd(loc, ops[0], ops[1]);
+  case NEON::BI__builtin_neon_vsubh_f16:
+    return builder.createFSub(loc, ops[0], ops[1]);
+  case NEON::BI__builtin_neon_vmulh_f16:
+    return builder.createFMul(loc, ops[0], ops[1]);
+  case NEON::BI__builtin_neon_vdivh_f16:
+    return builder.createFDiv(loc, ops[0], ops[1]);
   case NEON::BI__builtin_neon_vfmah_f16:
     // NEON intrinsic puts accumulator first, unlike the LLVM fma.
     std::rotate(ops.begin(), ops.begin() + 1, ops.end());
diff --git a/clang/test/CodeGen/AArch64/neon/fullfp16.c b/clang/test/CodeGen/AArch64/neon/fullfp16.c
index 619d07538eaaf..db0b20fe62799 100644
--- a/clang/test/CodeGen/AArch64/neon/fullfp16.c
+++ b/clang/test/CodeGen/AArch64/neon/fullfp16.c
@@ -33,6 +33,58 @@
 
 #include <arm_fp16.h>
 
+//===------------------------------------------------------===//
+// 2.5.1.1.  Addition
+//===------------------------------------------------------===//
+// ALL-LABEL: @test_vaddh_f16(
+float16_t test_vaddh_f16(float16_t a, float16_t b) {
+// CIR: {{%.*}} = cir.add {{%.*}}, {{%.*}} : !cir.f16
+
+// LLVM-SAME: half {{.*}} [[A:%.*]], half{{.*}} [[B:%.*]]) {{.*}} {
+// LLVM:  [[ADD:%.*]] = fadd half [[A]], [[B]]
+// LLVM:  ret half [[ADD]]
+  return vaddh_f16(a, b);
+}
+
+//===------------------------------------------------------===//
+// 2.5.10.1.  Subtraction
+//===------------------------------------------------------===//
+// ALL-LABEL: @test_vsubh_f16(
+float16_t test_vsubh_f16(float16_t a, float16_t b) {
+// CIR: {{%.*}} = cir.sub {{%.*}}, {{%.*}} : !cir.f16
+
+// LLVM-SAME: half {{.*}} [[A:%.]], half {{.*}} [[B:%.]]) {{.*}} {
+// LLVM:  [[SUB:%.*]] = fsub half [[A]], [[B]]
+// LLVM:  ret half [[SUB]]
+  return vsubh_f16(a, b);
+}
+
+//===------------------------------------------------------===//
+// 2.5.9.1.  Multiplication
+//===------------------------------------------------------===//
+// ALL-LABEL: @test_vmulh_f16(
+float16_t test_vmulh_f16(float16_t a, float16_t b) {
+// CIR: {{%.*}} = cir.mul {{%.*}}, {{%.*}} : !cir.f16
+
+// LLVM-SAME: half {{.*}} [[A:%.]], half {{.*}} [[B:%.]]) {{.*}} {
+// LLVM:  [[MUL:%.*]] = fmul half [[A]], [[B]]
+// LLVM:  ret half [[MUL]]
+  return vmulh_f16(a, b);
+}
+
+//===------------------------------------------------------===//
+// 2.5.1.6.  Division
+//===------------------------------------------------------===//
+// ALL-LABEL: @test_vdivh_f16(
+float16_t test_vdivh_f16(float16_t a, float16_t b) {
+// CIR: {{%.*}} = cir.div {{%.*}}, {{%.*}} : !cir.f16
+
+// LLVM-SAME: half {{.*}} [[A:%.]], half {{.*}} [[B:%.]]) {{.*}} {
+// LLVM:  [[DIV:%.*]] = fdiv half [[A]], [[B]]
+// LLVM:  ret half [[DIV]]
+  return vdivh_f16(a, b);
+}
+
 //===------------------------------------------------------===//
 // 2.5.2.1.  Bitwise equal to zero
 //===------------------------------------------------------===//
diff --git a/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c b/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
index c80d9e9d7f759..f1fd42a8ea26c 100644
--- a/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
+++ b/clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c
@@ -368,13 +368,6 @@ float16_t test_vsqrth_f16(float16_t a) {
   return vsqrth_f16(a);
 }
 
-// CHECK-LABEL: test_vaddh_f16
-// CHECK:  [[ADD:%.*]] = fadd half %a, %b
-// CHECK:  ret half [[ADD]]
-float16_t test_vaddh_f16(float16_t a, float16_t b) {
-  return vaddh_f16(a, b);
-}
-
 // CHECK-LABEL: test_vabdh_f16
 // CHECK:  [[ABD:%.*]] = call half @llvm.aarch64.sisd.fabd.f16(half %a, half %b)
 // CHECK:  ret half [[ABD]]
@@ -542,13 +535,6 @@ int64_t test_vcvth_n_u64_f16(float16_t a) {
   return vcvth_n_u64_f16(a, 1);
 }
 
-// CHECK-LABEL: test_vdivh_f16
-// CHECK:  [[DIV:%.*]] = fdiv half %a, %b
-// CHECK:  ret half [[DIV]]
-float16_t test_vdivh_f16(float16_t a, float16_t b) {
-  return vdivh_f16(a, b);
-}
-
 // CHECK-LABEL: test_vmaxh_f16
 // CHECK:  [[MAX:%.*]] = call half @llvm.aarch64.neon.fmax.f16(half %a, half %b)
 // CHECK:  ret half [[MAX]]
@@ -577,13 +563,6 @@ float16_t test_vminnmh_f16(float16_t a, float16_t b) {
   return vminnmh_f16(a, b);
 }
 
-// CHECK-LABEL: test_vmulh_f16
-// CHECK:  [[MUL:%.*]] = fmul half %a, %b
-// CHECK:  ret half [[MUL]]
-float16_t test_vmulh_f16(float16_t a, float16_t b) {
-  return vmulh_f16(a, b);
-}
-
 // CHECK-LABEL: test_vmulxh_f16
 // CHECK:  [[MUL:%.*]] = call half @llvm.aarch64.neon.fmulx.f16(half %a, half %b)
 // CHECK:  ret half [[MUL]]
@@ -604,10 +583,3 @@ float16_t test_vrecpsh_f16(float16_t a, float16_t b) {
 float16_t test_vrsqrtsh_f16(float16_t a, float16_t b) {
   return vrsqrtsh_f16(a, b);
 }
-
-// CHECK-LABEL: test_vsubh_f16
-// CHECK:  [[SUB:%.*]] = fsub half %a, %b
-// CHECK:  ret half [[SUB]]
-float16_t test_vsubh_f16(float16_t a, float16_t b) {
-  return vsubh_f16(a, b);
-}