diff --git a/clang/lib/Sema/SemaOpenMP.cpp b/clang/lib/Sema/SemaOpenMP.cpp index ec9b2e68ef6cf..676889de15303 100644 --- a/clang/lib/Sema/SemaOpenMP.cpp +++ b/clang/lib/Sema/SemaOpenMP.cpp @@ -14959,11 +14959,22 @@ StmtResult SemaOpenMP::ActOnOpenMPTileDirective(ArrayRef Clauses, SmallVector PreInits; CaptureVars CopyTransformer(SemaRef); + // Emit the intra-tile loop in canonical (rectangular + predicate) form only + // when a consuming OpenMP construct requires canonical input; otherwise keep + // the original min(.floor.iv + T, N) bound. + OpenMPDirectiveKind ParentDirective = DSAStack->getParentDirective(); + const bool IntraTileMustBeCanonical = + isOpenMPLoopTransformationDirective(ParentDirective) || + isOpenMPLoopDirective(ParentDirective); + // Create iteration variables for the generated loops. SmallVector FloorIndVars; SmallVector TileIndVars; + SmallVector TileCntVars; FloorIndVars.resize(NumLoops); TileIndVars.resize(NumLoops); + if (IntraTileMustBeCanonical) + TileCntVars.resize(NumLoops); for (unsigned I = 0; I < NumLoops; ++I) { OMPLoopBasedDirective::HelperExprs &LoopHelper = LoopHelpers[I]; @@ -14983,27 +14994,105 @@ StmtResult SemaOpenMP::ActOnOpenMPTileDirective(ArrayRef Clauses, FloorIndVars[I] = FloorCntDecl; } - // Iteration variable for the tile (i.e. inner) loop. + // Logical iteration variable for the tile loop. Retains the meaning of + // the original logical iteration number (floor_iv + tile_cnt) so that + // LoopHelper.Updates can derive the original loop variable unchanged. { - std::string TileCntName = + std::string TileIVName = (Twine(".tile_") + llvm::utostr(I) + ".iv." + OrigVarName).str(); - // Reuse the iteration variable created by checkOpenMPLoop. It is also - // used by the expressions to derive the original iteration variable's - // value from the logical iteration number. - auto *TileCntDecl = cast(IterVarRef->getDecl()); - TileCntDecl->setDeclName( - &SemaRef.PP.getIdentifierTable().get(TileCntName)); - TileIndVars[I] = TileCntDecl; + auto *TileIVDecl = cast(IterVarRef->getDecl()); + TileIVDecl->setDeclName(&SemaRef.PP.getIdentifierTable().get(TileIVName)); + TileIndVars[I] = TileIVDecl; + } + + // Loop counter for the rectangular tile loop [0, TileSize). + if (IntraTileMustBeCanonical) { + std::string TileCntName = + (Twine(".tile.cnt.") + llvm::utostr(I) + ".iv." + OrigVarName).str(); + VarDecl *TileCntDecl = + buildVarDecl(SemaRef, {}, CntTy, TileCntName, nullptr, OrigCntVar); + TileCntVars[I] = TileCntDecl; } addLoopPreInits(Context, LoopHelper, LoopStmts[I], OriginalInits[I], PreInits); + + // Declare the logical tile IV in PreInits so it is in scope for the + // entire loop nest (it will be assigned in each tile loop body). + if (IntraTileMustBeCanonical) { + Decl *TileIVDeclPtr = TileIndVars[I]; + PreInits.push_back(new (Context) DeclStmt( + DeclGroupRef::Create(Context, &TileIVDeclPtr, 1), {}, {})); + } } // Once the original iteration values are set, append the innermost body. Stmt *Inner = Body; + // Build a combined validity predicate that guards the innermost body. + // For each tiled dimension, check that the logical iteration number + // (.tile.iv) is within the original trip count. This is required because the + // tile loop now has rectangular (constant) bounds and may overshoot on the + // remainder tile. The predicate is: .tile.iv.0 < N0 && .tile.iv.1 < N1 ... + // + // Optimization: if every dimension's trip count is a compile-time constant + // that is evenly divisible by the corresponding tile size (also a constant), + // then the remainder tile is empty and the predicate is trivially true. + // + // The min-bounded path clamps the tile loop's upper bound directly so no + // predicate is needed. + if (IntraTileMustBeCanonical) { + bool PredicateNeeded = false; + for (unsigned I = 0; I < NumLoops; ++I) { + Expr *TSExpr = SizesClause->getSizesRefs()[I]; + Expr *NExpr = LoopHelpers[I].NumIterations; + bool TSConst = + !TSExpr->containsErrors() && TSExpr->isIntegerConstantExpr(Context); + bool NConst = NExpr->isIntegerConstantExpr(Context); + if (TSConst && NConst) { + Expr::EvalResult TSResult; + TSExpr->EvaluateAsInt(TSResult, Context); + llvm::APSInt TileVal = TSResult.Val.getInt(); + Expr::EvalResult NResult; + NExpr->EvaluateAsInt(NResult, Context); + llvm::APSInt TripVal = NResult.Val.getInt(); + if (TileVal.isStrictlyPositive() && TripVal.srem(TileVal).isZero()) + continue; + } + PredicateNeeded = true; + break; + } + + if (PredicateNeeded) { + Expr *CombinedPred = nullptr; + for (unsigned I = 0; I < NumLoops; ++I) { + auto *OrigCntVar = cast(LoopHelpers[I].Counters[0]); + QualType IVTy = LoopHelpers[I].NumIterations->getType(); + Expr *TileIVRef = buildDeclRefExpr(SemaRef, TileIndVars[I], IVTy, + OrigCntVar->getExprLoc()); + ExprResult DimPred = + SemaRef.BuildBinOp(CurScope, OrigCntVar->getExprLoc(), BO_LT, + TileIVRef, LoopHelpers[I].NumIterations); + if (!DimPred.isUsable()) + return StmtError(); + if (CombinedPred) { + ExprResult Combined = + SemaRef.BuildBinOp(CurScope, OrigCntVar->getExprLoc(), BO_LAnd, + CombinedPred, DimPred.get()); + if (!Combined.isUsable()) + return StmtError(); + CombinedPred = Combined.get(); + } else { + CombinedPred = DimPred.get(); + } + } + Inner = IfStmt::Create( + Context, SourceLocation(), IfStatementKind::Ordinary, nullptr, + nullptr, CombinedPred, SourceLocation(), SourceLocation(), Inner); + } + } + auto MakeDimTileSize = [&SemaRef = this->SemaRef, &CopyTransformer, &Context, SizesClause, CurScope](int I) -> Expr * { Expr *DimTileSizeExpr = SizesClause->getSizesRefs()[I]; @@ -15011,7 +15100,7 @@ StmtResult SemaOpenMP::ActOnOpenMPTileDirective(ArrayRef Clauses, if (DimTileSizeExpr->containsErrors()) return nullptr; - if (isa(DimTileSizeExpr)) + if (DimTileSizeExpr->isIntegerConstantExpr(Context)) return AssertSuccess(CopyTransformer.TransformExpr(DimTileSizeExpr)); // When the tile size is not a constant but a variable, it is possible to @@ -15047,6 +15136,11 @@ StmtResult SemaOpenMP::ActOnOpenMPTileDirective(ArrayRef Clauses, }; // Create tile loops from the inside to the outside. + // Each tile loop uses .tile.cnt as its counter with rectangular bounds + // [0, TileSize), and computes .tile.iv = .floor.iv + .tile.cnt to set + // the logical iteration number for LoopHelper.Updates. + // The min-bounded path instead uses .tile.iv directly, initialized to + // .floor.iv and bounded by min(.floor.iv + DimTileSize, NumIterations). for (int I = NumLoops - 1; I >= 0; --I) { OMPLoopBasedDirective::HelperExprs &LoopHelper = LoopHelpers[I]; Expr *NumIterations = LoopHelper.NumIterations; @@ -15057,70 +15151,107 @@ StmtResult SemaOpenMP::ActOnOpenMPTileDirective(ArrayRef Clauses, // Commonly used variables. One of the constraints of an AST is that every // node object must appear at most once, hence we define a lambda that // creates a new AST node at every use. + auto MakeTileCntRef = [&SemaRef = this->SemaRef, &TileCntVars, I, IVTy, + OrigCntVar]() { + return buildDeclRefExpr(SemaRef, TileCntVars[I], IVTy, + OrigCntVar->getExprLoc()); + }; auto MakeTileIVRef = [&SemaRef = this->SemaRef, &TileIndVars, I, IVTy, OrigCntVar]() { return buildDeclRefExpr(SemaRef, TileIndVars[I], IVTy, OrigCntVar->getExprLoc()); }; - // For init-statement: auto .tile.iv = .floor.iv - SemaRef.AddInitializerToDecl( - TileIndVars[I], - SemaRef - .DefaultLvalueConversion( - makeFloorIVRef(SemaRef, FloorIndVars, I, IVTy, OrigCntVar)) - .get(), - /*DirectInit=*/false); - Decl *CounterDecl = TileIndVars[I]; - StmtResult InitStmt = new (Context) - DeclStmt(DeclGroupRef::Create(Context, &CounterDecl, 1), - OrigCntVar->getBeginLoc(), OrigCntVar->getEndLoc()); - if (!InitStmt.isUsable()) - return StmtError(); - - // For cond-expression: - // .tile.iv < min(.floor.iv + DimTileSize, NumIterations) Expr *DimTileSize = MakeDimTileSize(I); if (!DimTileSize) return StmtError(); - ExprResult EndOfTile = SemaRef.BuildBinOp( - CurScope, LoopHelper.Cond->getExprLoc(), BO_Add, - makeFloorIVRef(SemaRef, FloorIndVars, I, IVTy, OrigCntVar), - DimTileSize); - if (!EndOfTile.isUsable()) - return StmtError(); - ExprResult IsPartialTile = - SemaRef.BuildBinOp(CurScope, LoopHelper.Cond->getExprLoc(), BO_LT, - NumIterations, EndOfTile.get()); - if (!IsPartialTile.isUsable()) - return StmtError(); - ExprResult MinTileAndIterSpace = SemaRef.ActOnConditionalOp( - LoopHelper.Cond->getBeginLoc(), LoopHelper.Cond->getEndLoc(), - IsPartialTile.get(), NumIterations, EndOfTile.get()); - if (!MinTileAndIterSpace.isUsable()) - return StmtError(); - ExprResult CondExpr = - SemaRef.BuildBinOp(CurScope, LoopHelper.Cond->getExprLoc(), BO_LT, - MakeTileIVRef(), MinTileAndIterSpace.get()); - if (!CondExpr.isUsable()) - return StmtError(); - // For incr-statement: ++.tile.iv - ExprResult IncrStmt = SemaRef.BuildUnaryOp( - CurScope, LoopHelper.Inc->getExprLoc(), UO_PreInc, MakeTileIVRef()); - if (!IncrStmt.isUsable()) + StmtResult InitStmt; + ExprResult CondExpr; + ExprResult IncrStmt; + Stmt *TileIVAssignStmt = nullptr; + + if (IntraTileMustBeCanonical) { + // For init-statement: auto .tile.cnt = 0 + SemaRef.AddInitializerToDecl( + TileCntVars[I], + SemaRef.ActOnIntegerConstant(LoopHelper.Init->getExprLoc(), 0).get(), + /*DirectInit=*/false); + Decl *CounterDecl = TileCntVars[I]; + InitStmt = new (Context) + DeclStmt(DeclGroupRef::Create(Context, &CounterDecl, 1), + OrigCntVar->getBeginLoc(), OrigCntVar->getEndLoc()); + + // For cond-expression: .tile.cnt < DimTileSize (rectangular bound) + CondExpr = SemaRef.BuildBinOp(CurScope, LoopHelper.Cond->getExprLoc(), + BO_LT, MakeTileCntRef(), DimTileSize); + + // For incr-statement: ++.tile.cnt + IncrStmt = SemaRef.BuildUnaryOp(CurScope, LoopHelper.Inc->getExprLoc(), + UO_PreInc, MakeTileCntRef()); + + // Compute the logical iteration number: + // .tile.iv = .floor.iv + .tile.cnt + ExprResult FloorPlusCnt = SemaRef.BuildBinOp( + CurScope, OrigCntVar->getExprLoc(), BO_Add, + makeFloorIVRef(SemaRef, FloorIndVars, I, IVTy, OrigCntVar), + MakeTileCntRef()); + if (!FloorPlusCnt.isUsable()) + return StmtError(); + ExprResult TileIVAssign = + SemaRef.BuildBinOp(CurScope, OrigCntVar->getExprLoc(), BO_Assign, + MakeTileIVRef(), FloorPlusCnt.get()); + if (!TileIVAssign.isUsable()) + return StmtError(); + TileIVAssignStmt = TileIVAssign.get(); + } else { + // Min-bounded path: .tile.iv is itself the loop counter, initialized to + // .floor.iv and bounded by min(.floor.iv + DimTileSize, NumIterations). + SemaRef.AddInitializerToDecl( + TileIndVars[I], + SemaRef + .DefaultLvalueConversion( + makeFloorIVRef(SemaRef, FloorIndVars, I, IVTy, OrigCntVar)) + .get(), + /*DirectInit=*/false); + Decl *CounterDecl = TileIndVars[I]; + InitStmt = new (Context) + DeclStmt(DeclGroupRef::Create(Context, &CounterDecl, 1), + OrigCntVar->getBeginLoc(), OrigCntVar->getEndLoc()); + + ExprResult EndOfTile = SemaRef.BuildBinOp( + CurScope, LoopHelper.Cond->getExprLoc(), BO_Add, + makeFloorIVRef(SemaRef, FloorIndVars, I, IVTy, OrigCntVar), + DimTileSize); + if (!EndOfTile.isUsable()) + return StmtError(); + ExprResult IsPartialTile = + SemaRef.BuildBinOp(CurScope, LoopHelper.Cond->getExprLoc(), BO_LT, + NumIterations, EndOfTile.get()); + if (!IsPartialTile.isUsable()) + return StmtError(); + ExprResult MinTileAndIterSpace = SemaRef.ActOnConditionalOp( + LoopHelper.Cond->getBeginLoc(), LoopHelper.Cond->getEndLoc(), + IsPartialTile.get(), NumIterations, EndOfTile.get()); + if (!MinTileAndIterSpace.isUsable()) + return StmtError(); + CondExpr = + SemaRef.BuildBinOp(CurScope, LoopHelper.Cond->getExprLoc(), BO_LT, + MakeTileIVRef(), MinTileAndIterSpace.get()); + + IncrStmt = SemaRef.BuildUnaryOp(CurScope, LoopHelper.Inc->getExprLoc(), + UO_PreInc, MakeTileIVRef()); + } + + if (!InitStmt.isUsable() || !CondExpr.isUsable() || !IncrStmt.isUsable()) return StmtError(); - // Statements to set the original iteration variable's value from the - // logical iteration number. // Generated for loop is: // \code - // Original_for_init; - // for (auto .tile.iv = .floor.iv; - // .tile.iv < min(.floor.iv + DimTileSize, NumIterations); - // ++.tile.iv) { - // Original_Body; - // Original_counter_update; + // for (auto .tile.cnt = 0; .tile.cnt < DimTileSize; ++.tile.cnt) { + // .tile.iv = .floor.iv + .tile.cnt; + // Original_counter_update; // derives orig var from .tile.iv + // Inner; // predicated body or inner tile loops // } // \endcode // FIXME: If the innermost body is an loop itself, inserting these @@ -15128,6 +15259,8 @@ StmtResult SemaOpenMP::ActOnOpenMPTileDirective(ArrayRef Clauses, // for applying tiling again). If this is the case, sink the expressions // further into the inner loop. SmallVector BodyParts; + if (TileIVAssignStmt) + BodyParts.push_back(TileIVAssignStmt); BodyParts.append(LoopHelper.Updates.begin(), LoopHelper.Updates.end()); if (auto *SourceCXXFor = dyn_cast(LoopStmt)) BodyParts.push_back(SourceCXXFor->getLoopVarStmt()); diff --git a/clang/test/OpenMP/interchange_codegen.cpp b/clang/test/OpenMP/interchange_codegen.cpp index 8e833c9df324c..b062d42c9f162 100644 --- a/clang/test/OpenMP/interchange_codegen.cpp +++ b/clang/test/OpenMP/interchange_codegen.cpp @@ -123,6 +123,7 @@ extern "C" void foo10() { #endif /* HEADER */ + // CHECK1-LABEL: define {{[^@]+}}@body // CHECK1-SAME: (...) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: @@ -156,7 +157,7 @@ extern "C" void foo10() { // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] // CHECK1: for.end: // CHECK1-NEXT: ret void // @@ -262,14 +263,14 @@ extern "C" void foo10() { // CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4 // CHECK1-NEXT: [[INC:%.*]] = add i32 [[TMP28]], 1 // CHECK1-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_1_IV_I]], align 4 -// CHECK1-NEXT: br label [[FOR_COND16]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND16]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK1: for.end: // CHECK1-NEXT: br label [[FOR_INC22:%.*]] // CHECK1: for.inc22: // CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4 // CHECK1-NEXT: [[INC23:%.*]] = add i32 [[TMP29]], 1 // CHECK1-NEXT: store i32 [[INC23]], ptr [[DOTPERMUTED_0_IV_J]], align 4 -// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK1: for.end24: // CHECK1-NEXT: ret void // @@ -342,7 +343,7 @@ extern "C" void foo10() { // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 // CHECK1-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_1_IV_I]], align 4 -// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK1: for.end: // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -439,7 +440,7 @@ extern "C" void foo10() { // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1 // CHECK1-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_1_IV_I]], align 4 -// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK1: for.end: // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -754,28 +755,28 @@ extern "C" void foo10() { // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTPERMUTED_3_IV_I]], align 4 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 // CHECK1-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_3_IV_I]], align 4 -// CHECK1-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK1: for.end: // CHECK1-NEXT: br label [[FOR_INC16:%.*]] // CHECK1: for.inc16: // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTPERMUTED_2_IV_L]], align 4 // CHECK1-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP13]], 1 // CHECK1-NEXT: store i32 [[INC17]], ptr [[DOTPERMUTED_2_IV_L]], align 4 -// CHECK1-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK1: for.end18: // CHECK1-NEXT: br label [[FOR_INC19:%.*]] // CHECK1: for.inc19: // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_K]], align 4 // CHECK1-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP14]], 1 // CHECK1-NEXT: store i32 [[INC20]], ptr [[DOTPERMUTED_1_IV_K]], align 4 -// CHECK1-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK1: for.end21: // CHECK1-NEXT: br label [[FOR_INC22:%.*]] // CHECK1: for.inc22: // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4 // CHECK1-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP15]], 1 // CHECK1-NEXT: store i32 [[INC23]], ptr [[DOTPERMUTED_0_IV_J]], align 4 -// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK1: for.end24: // CHECK1-NEXT: ret void // @@ -810,22 +811,21 @@ extern "C" void foo10() { // CHECK1-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTNEW_STEP10:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTTILE_0_IV_K:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_14:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTCAPTURE_EXPR_16:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i64, align 8 +// CHECK1-NEXT: [[DOTCAPTURE_EXPR_16:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTFLOOR_0_IV_K:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTTILE_0_IV_K:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTTILE_CNT_0_IV_K:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[I49:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[J50:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTFLOOR_0_IV_K51:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTTILE_0_IV_K52:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[I35:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[J36:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTFLOOR_0_IV_K37:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTTILE_CNT_0_IV_K38:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) // CHECK1-NEXT: store i32 [[START]], ptr [[START_ADDR]], align 4 // CHECK1-NEXT: store i32 [[END]], ptr [[END_ADDR]], align 4 @@ -863,630 +863,452 @@ extern "C" void foo10() { // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4 // CHECK1-NEXT: [[ADD15:%.*]] = add i32 [[TMP15]], 1 // CHECK1-NEXT: store i32 [[ADD15]], ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[_TMP2]], align 4 -// CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4 -// CHECK1-NEXT: [[ADD18:%.*]] = add i32 [[TMP17]], 1 -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[_TMP2]], align 4 -// CHECK1-NEXT: [[ADD19:%.*]] = add i32 [[TMP18]], 32 -// CHECK1-NEXT: [[CMP:%.*]] = icmp ult i32 [[ADD18]], [[ADD19]] -// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK1: cond.true: -// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4 -// CHECK1-NEXT: [[ADD20:%.*]] = add i32 [[TMP19]], 1 -// CHECK1-NEXT: br label [[COND_END:%.*]] -// CHECK1: cond.false: -// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[_TMP2]], align 4 -// CHECK1-NEXT: [[ADD21:%.*]] = add i32 [[TMP20]], 32 -// CHECK1-NEXT: br label [[COND_END]] -// CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[ADD20]], [[COND_TRUE]] ], [ [[ADD21]], [[COND_FALSE]] ] -// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK1-NEXT: [[SUB23:%.*]] = sub i32 [[TMP21]], [[TMP22]] -// CHECK1-NEXT: [[SUB24:%.*]] = sub i32 [[SUB23]], 1 -// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 -// CHECK1-NEXT: [[ADD25:%.*]] = add i32 [[SUB24]], [[TMP23]] -// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 -// CHECK1-NEXT: [[DIV26:%.*]] = udiv i32 [[ADD25]], [[TMP24]] -// CHECK1-NEXT: [[CONV:%.*]] = zext i32 [[DIV26]] to i64 -// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK1-NEXT: [[SUB17:%.*]] = sub i32 [[TMP16]], [[TMP17]] +// CHECK1-NEXT: [[SUB18:%.*]] = sub i32 [[SUB17]], 1 +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 +// CHECK1-NEXT: [[ADD19:%.*]] = add i32 [[SUB18]], [[TMP18]] +// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 +// CHECK1-NEXT: [[DIV20:%.*]] = udiv i32 [[ADD19]], [[TMP19]] +// CHECK1-NEXT: [[CONV:%.*]] = zext i32 [[DIV20]] to i64 +// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK1-NEXT: [[SUB21:%.*]] = sub i32 [[TMP20]], [[TMP21]] +// CHECK1-NEXT: [[SUB22:%.*]] = sub i32 [[SUB21]], 1 +// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[ADD23:%.*]] = add i32 [[SUB22]], [[TMP22]] +// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[DIV24:%.*]] = udiv i32 [[ADD23]], [[TMP23]] +// CHECK1-NEXT: [[CONV25:%.*]] = zext i32 [[DIV24]] to i64 +// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV25]] +// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB26:%.*]] = sub i32 [[TMP24]], -31 +// CHECK1-NEXT: [[DIV27:%.*]] = udiv i32 [[SUB26]], 32 +// CHECK1-NEXT: [[CONV28:%.*]] = zext i32 [[DIV27]] to i64 +// CHECK1-NEXT: [[MUL29:%.*]] = mul nsw i64 [[MUL]], [[CONV28]] +// CHECK1-NEXT: [[MUL30:%.*]] = mul nsw i64 [[MUL29]], 32 +// CHECK1-NEXT: [[SUB31:%.*]] = sub nsw i64 [[MUL30]], 1 +// CHECK1-NEXT: store i64 [[SUB31]], ptr [[DOTCAPTURE_EXPR_16]], align 8 +// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK1-NEXT: store i32 [[TMP25]], ptr [[I]], align 4 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK1-NEXT: [[SUB27:%.*]] = sub i32 [[TMP25]], [[TMP26]] -// CHECK1-NEXT: [[SUB28:%.*]] = sub i32 [[SUB27]], 1 -// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[ADD29:%.*]] = add i32 [[SUB28]], [[TMP27]] -// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[DIV30:%.*]] = udiv i32 [[ADD29]], [[TMP28]] -// CHECK1-NEXT: [[CONV31:%.*]] = zext i32 [[DIV30]] to i64 -// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV31]] -// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB32:%.*]] = sub i32 [[TMP29]], -31 -// CHECK1-NEXT: [[DIV33:%.*]] = udiv i32 [[SUB32]], 32 -// CHECK1-NEXT: [[CONV34:%.*]] = zext i32 [[DIV33]] to i64 -// CHECK1-NEXT: [[MUL35:%.*]] = mul nsw i64 [[MUL]], [[CONV34]] -// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB36:%.*]] = sub i32 [[TMP30]], [[TMP31]] -// CHECK1-NEXT: [[SUB37:%.*]] = sub i32 [[SUB36]], 1 -// CHECK1-NEXT: [[ADD38:%.*]] = add i32 [[SUB37]], 1 -// CHECK1-NEXT: [[DIV39:%.*]] = udiv i32 [[ADD38]], 1 -// CHECK1-NEXT: [[CONV40:%.*]] = zext i32 [[DIV39]] to i64 -// CHECK1-NEXT: [[MUL41:%.*]] = mul nsw i64 [[MUL35]], [[CONV40]] -// CHECK1-NEXT: [[SUB42:%.*]] = sub nsw i64 [[MUL41]], 1 -// CHECK1-NEXT: store i64 [[SUB42]], ptr [[DOTCAPTURE_EXPR_22]], align 8 -// CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK1-NEXT: store i32 [[TMP32]], ptr [[I]], align 4 -// CHECK1-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK1-NEXT: store i32 [[TMP33]], ptr [[J]], align 4 +// CHECK1-NEXT: store i32 [[TMP26]], ptr [[J]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_K]], align 4 -// CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: store i32 [[TMP34]], ptr [[DOTTILE_0_IV_K]], align 4 -// CHECK1-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK1-NEXT: [[CMP43:%.*]] = icmp slt i32 [[TMP35]], [[TMP36]] -// CHECK1-NEXT: br i1 [[CMP43]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK1-NEXT: store i32 0, ptr [[DOTTILE_CNT_0_IV_K]], align 4 +// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP27]], [[TMP28]] +// CHECK1-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK1: land.lhs.true: -// CHECK1-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK1-NEXT: [[CMP44:%.*]] = icmp slt i32 [[TMP37]], [[TMP38]] -// CHECK1-NEXT: br i1 [[CMP44]], label [[LAND_LHS_TRUE45:%.*]], label [[OMP_PRECOND_END]] -// CHECK1: land.lhs.true45: -// CHECK1-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[CMP46:%.*]] = icmp ult i32 0, [[TMP39]] -// CHECK1-NEXT: br i1 [[CMP46]], label [[LAND_LHS_TRUE47:%.*]], label [[OMP_PRECOND_END]] -// CHECK1: land.lhs.true47: -// CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[CMP48:%.*]] = icmp ult i32 [[TMP40]], [[TMP41]] -// CHECK1-NEXT: br i1 [[CMP48]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK1-NEXT: [[CMP32:%.*]] = icmp slt i32 [[TMP29]], [[TMP30]] +// CHECK1-NEXT: br i1 [[CMP32]], label [[LAND_LHS_TRUE33:%.*]], label [[OMP_PRECOND_END]] +// CHECK1: land.lhs.true33: +// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[CMP34:%.*]] = icmp ult i32 0, [[TMP31]] +// CHECK1-NEXT: br i1 [[CMP34]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] // CHECK1: omp.precond.then: // CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 -// CHECK1-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8 -// CHECK1-NEXT: store i64 [[TMP42]], ptr [[DOTOMP_UB]], align 8 +// CHECK1-NEXT: [[TMP32:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_16]], align 8 +// CHECK1-NEXT: store i64 [[TMP32]], ptr [[DOTOMP_UB]], align 8 // CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK1-NEXT: [[TMP43:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 -// CHECK1-NEXT: [[TMP44:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8 -// CHECK1-NEXT: [[CMP53:%.*]] = icmp sgt i64 [[TMP43]], [[TMP44]] -// CHECK1-NEXT: br i1 [[CMP53]], label [[COND_TRUE54:%.*]], label [[COND_FALSE55:%.*]] -// CHECK1: cond.true54: -// CHECK1-NEXT: [[TMP45:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8 -// CHECK1-NEXT: br label [[COND_END56:%.*]] -// CHECK1: cond.false55: -// CHECK1-NEXT: [[TMP46:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 -// CHECK1-NEXT: br label [[COND_END56]] -// CHECK1: cond.end56: -// CHECK1-NEXT: [[COND57:%.*]] = phi i64 [ [[TMP45]], [[COND_TRUE54]] ], [ [[TMP46]], [[COND_FALSE55]] ] -// CHECK1-NEXT: store i64 [[COND57]], ptr [[DOTOMP_UB]], align 8 -// CHECK1-NEXT: [[TMP47:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 -// CHECK1-NEXT: store i64 [[TMP47]], ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[TMP33:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 +// CHECK1-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_16]], align 8 +// CHECK1-NEXT: [[CMP39:%.*]] = icmp sgt i64 [[TMP33]], [[TMP34]] +// CHECK1-NEXT: br i1 [[CMP39]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK1: cond.true: +// CHECK1-NEXT: [[TMP35:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_16]], align 8 +// CHECK1-NEXT: br label [[COND_END:%.*]] +// CHECK1: cond.false: +// CHECK1-NEXT: [[TMP36:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 +// CHECK1-NEXT: br label [[COND_END]] +// CHECK1: cond.end: +// CHECK1-NEXT: [[COND:%.*]] = phi i64 [ [[TMP35]], [[COND_TRUE]] ], [ [[TMP36]], [[COND_FALSE]] ] +// CHECK1-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 +// CHECK1-NEXT: [[TMP37:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 +// CHECK1-NEXT: store i64 [[TMP37]], ptr [[DOTOMP_IV]], align 8 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP48:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP49:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 -// CHECK1-NEXT: [[CMP58:%.*]] = icmp sle i64 [[TMP48]], [[TMP49]] -// CHECK1-NEXT: br i1 [[CMP58]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK1-NEXT: [[TMP38:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 +// CHECK1-NEXT: [[CMP40:%.*]] = icmp sle i64 [[TMP38]], [[TMP39]] +// CHECK1-NEXT: br i1 [[CMP40]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK1-NEXT: [[CONV59:%.*]] = sext i32 [[TMP50]] to i64 -// CHECK1-NEXT: [[TMP51:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP52:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK1-NEXT: [[TMP53:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK1-NEXT: [[SUB60:%.*]] = sub i32 [[TMP52]], [[TMP53]] -// CHECK1-NEXT: [[SUB61:%.*]] = sub i32 [[SUB60]], 1 +// CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK1-NEXT: [[CONV41:%.*]] = sext i32 [[TMP40]] to i64 +// CHECK1-NEXT: [[TMP41:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK1-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK1-NEXT: [[SUB42:%.*]] = sub i32 [[TMP42]], [[TMP43]] +// CHECK1-NEXT: [[SUB43:%.*]] = sub i32 [[SUB42]], 1 +// CHECK1-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[ADD44:%.*]] = add i32 [[SUB43]], [[TMP44]] +// CHECK1-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[DIV45:%.*]] = udiv i32 [[ADD44]], [[TMP45]] +// CHECK1-NEXT: [[MUL46:%.*]] = mul i32 1, [[DIV45]] +// CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB47:%.*]] = sub i32 [[TMP46]], -31 +// CHECK1-NEXT: [[DIV48:%.*]] = udiv i32 [[SUB47]], 32 +// CHECK1-NEXT: [[MUL49:%.*]] = mul i32 [[MUL46]], [[DIV48]] +// CHECK1-NEXT: [[MUL50:%.*]] = mul i32 [[MUL49]], 32 +// CHECK1-NEXT: [[CONV51:%.*]] = zext i32 [[MUL50]] to i64 +// CHECK1-NEXT: [[DIV52:%.*]] = sdiv i64 [[TMP41]], [[CONV51]] +// CHECK1-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 +// CHECK1-NEXT: [[CONV53:%.*]] = sext i32 [[TMP47]] to i64 +// CHECK1-NEXT: [[MUL54:%.*]] = mul nsw i64 [[DIV52]], [[CONV53]] +// CHECK1-NEXT: [[ADD55:%.*]] = add nsw i64 [[CONV41]], [[MUL54]] +// CHECK1-NEXT: [[CONV56:%.*]] = trunc i64 [[ADD55]] to i32 +// CHECK1-NEXT: store i32 [[CONV56]], ptr [[I35]], align 4 +// CHECK1-NEXT: [[TMP48:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK1-NEXT: [[CONV57:%.*]] = sext i32 [[TMP48]] to i64 +// CHECK1-NEXT: [[TMP49:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[TMP50:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[TMP51:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK1-NEXT: [[TMP52:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK1-NEXT: [[SUB58:%.*]] = sub i32 [[TMP51]], [[TMP52]] +// CHECK1-NEXT: [[SUB59:%.*]] = sub i32 [[SUB58]], 1 +// CHECK1-NEXT: [[TMP53:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[ADD60:%.*]] = add i32 [[SUB59]], [[TMP53]] // CHECK1-NEXT: [[TMP54:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[ADD62:%.*]] = add i32 [[SUB61]], [[TMP54]] -// CHECK1-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[DIV63:%.*]] = udiv i32 [[ADD62]], [[TMP55]] -// CHECK1-NEXT: [[MUL64:%.*]] = mul i32 1, [[DIV63]] -// CHECK1-NEXT: [[TMP56:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB65:%.*]] = sub i32 [[TMP56]], -31 -// CHECK1-NEXT: [[DIV66:%.*]] = udiv i32 [[SUB65]], 32 -// CHECK1-NEXT: [[MUL67:%.*]] = mul i32 [[MUL64]], [[DIV66]] -// CHECK1-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB68:%.*]] = sub i32 [[TMP57]], [[TMP58]] -// CHECK1-NEXT: [[SUB69:%.*]] = sub i32 [[SUB68]], 1 -// CHECK1-NEXT: [[ADD70:%.*]] = add i32 [[SUB69]], 1 -// CHECK1-NEXT: [[DIV71:%.*]] = udiv i32 [[ADD70]], 1 -// CHECK1-NEXT: [[MUL72:%.*]] = mul i32 [[MUL67]], [[DIV71]] -// CHECK1-NEXT: [[CONV73:%.*]] = zext i32 [[MUL72]] to i64 -// CHECK1-NEXT: [[DIV74:%.*]] = sdiv i64 [[TMP51]], [[CONV73]] -// CHECK1-NEXT: [[TMP59:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 -// CHECK1-NEXT: [[CONV75:%.*]] = sext i32 [[TMP59]] to i64 -// CHECK1-NEXT: [[MUL76:%.*]] = mul nsw i64 [[DIV74]], [[CONV75]] -// CHECK1-NEXT: [[ADD77:%.*]] = add nsw i64 [[CONV59]], [[MUL76]] -// CHECK1-NEXT: [[CONV78:%.*]] = trunc i64 [[ADD77]] to i32 -// CHECK1-NEXT: store i32 [[CONV78]], ptr [[I49]], align 4 -// CHECK1-NEXT: [[TMP60:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK1-NEXT: [[CONV79:%.*]] = sext i32 [[TMP60]] to i64 -// CHECK1-NEXT: [[TMP61:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP62:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP63:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK1-NEXT: [[TMP64:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK1-NEXT: [[SUB80:%.*]] = sub i32 [[TMP63]], [[TMP64]] -// CHECK1-NEXT: [[SUB81:%.*]] = sub i32 [[SUB80]], 1 -// CHECK1-NEXT: [[TMP65:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[ADD82:%.*]] = add i32 [[SUB81]], [[TMP65]] -// CHECK1-NEXT: [[TMP66:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[DIV83:%.*]] = udiv i32 [[ADD82]], [[TMP66]] -// CHECK1-NEXT: [[MUL84:%.*]] = mul i32 1, [[DIV83]] -// CHECK1-NEXT: [[TMP67:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB85:%.*]] = sub i32 [[TMP67]], -31 -// CHECK1-NEXT: [[DIV86:%.*]] = udiv i32 [[SUB85]], 32 -// CHECK1-NEXT: [[MUL87:%.*]] = mul i32 [[MUL84]], [[DIV86]] -// CHECK1-NEXT: [[TMP68:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP69:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB88:%.*]] = sub i32 [[TMP68]], [[TMP69]] -// CHECK1-NEXT: [[SUB89:%.*]] = sub i32 [[SUB88]], 1 -// CHECK1-NEXT: [[ADD90:%.*]] = add i32 [[SUB89]], 1 -// CHECK1-NEXT: [[DIV91:%.*]] = udiv i32 [[ADD90]], 1 -// CHECK1-NEXT: [[MUL92:%.*]] = mul i32 [[MUL87]], [[DIV91]] -// CHECK1-NEXT: [[CONV93:%.*]] = zext i32 [[MUL92]] to i64 -// CHECK1-NEXT: [[DIV94:%.*]] = sdiv i64 [[TMP62]], [[CONV93]] +// CHECK1-NEXT: [[DIV61:%.*]] = udiv i32 [[ADD60]], [[TMP54]] +// CHECK1-NEXT: [[MUL62:%.*]] = mul i32 1, [[DIV61]] +// CHECK1-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB63:%.*]] = sub i32 [[TMP55]], -31 +// CHECK1-NEXT: [[DIV64:%.*]] = udiv i32 [[SUB63]], 32 +// CHECK1-NEXT: [[MUL65:%.*]] = mul i32 [[MUL62]], [[DIV64]] +// CHECK1-NEXT: [[MUL66:%.*]] = mul i32 [[MUL65]], 32 +// CHECK1-NEXT: [[CONV67:%.*]] = zext i32 [[MUL66]] to i64 +// CHECK1-NEXT: [[DIV68:%.*]] = sdiv i64 [[TMP50]], [[CONV67]] +// CHECK1-NEXT: [[TMP56:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK1-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK1-NEXT: [[SUB69:%.*]] = sub i32 [[TMP56]], [[TMP57]] +// CHECK1-NEXT: [[SUB70:%.*]] = sub i32 [[SUB69]], 1 +// CHECK1-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[ADD71:%.*]] = add i32 [[SUB70]], [[TMP58]] +// CHECK1-NEXT: [[TMP59:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[DIV72:%.*]] = udiv i32 [[ADD71]], [[TMP59]] +// CHECK1-NEXT: [[MUL73:%.*]] = mul i32 1, [[DIV72]] +// CHECK1-NEXT: [[TMP60:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB74:%.*]] = sub i32 [[TMP60]], -31 +// CHECK1-NEXT: [[DIV75:%.*]] = udiv i32 [[SUB74]], 32 +// CHECK1-NEXT: [[MUL76:%.*]] = mul i32 [[MUL73]], [[DIV75]] +// CHECK1-NEXT: [[MUL77:%.*]] = mul i32 [[MUL76]], 32 +// CHECK1-NEXT: [[CONV78:%.*]] = zext i32 [[MUL77]] to i64 +// CHECK1-NEXT: [[MUL79:%.*]] = mul nsw i64 [[DIV68]], [[CONV78]] +// CHECK1-NEXT: [[SUB80:%.*]] = sub nsw i64 [[TMP49]], [[MUL79]] +// CHECK1-NEXT: [[TMP61:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB81:%.*]] = sub i32 [[TMP61]], -31 +// CHECK1-NEXT: [[DIV82:%.*]] = udiv i32 [[SUB81]], 32 +// CHECK1-NEXT: [[MUL83:%.*]] = mul i32 1, [[DIV82]] +// CHECK1-NEXT: [[MUL84:%.*]] = mul i32 [[MUL83]], 32 +// CHECK1-NEXT: [[CONV85:%.*]] = zext i32 [[MUL84]] to i64 +// CHECK1-NEXT: [[DIV86:%.*]] = sdiv i64 [[SUB80]], [[CONV85]] +// CHECK1-NEXT: [[TMP62:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[CONV87:%.*]] = sext i32 [[TMP62]] to i64 +// CHECK1-NEXT: [[MUL88:%.*]] = mul nsw i64 [[DIV86]], [[CONV87]] +// CHECK1-NEXT: [[ADD89:%.*]] = add nsw i64 [[CONV57]], [[MUL88]] +// CHECK1-NEXT: [[CONV90:%.*]] = trunc i64 [[ADD89]] to i32 +// CHECK1-NEXT: store i32 [[CONV90]], ptr [[J36]], align 4 +// CHECK1-NEXT: [[TMP63:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[TMP64:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[TMP65:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK1-NEXT: [[TMP66:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK1-NEXT: [[SUB91:%.*]] = sub i32 [[TMP65]], [[TMP66]] +// CHECK1-NEXT: [[SUB92:%.*]] = sub i32 [[SUB91]], 1 +// CHECK1-NEXT: [[TMP67:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[ADD93:%.*]] = add i32 [[SUB92]], [[TMP67]] +// CHECK1-NEXT: [[TMP68:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[DIV94:%.*]] = udiv i32 [[ADD93]], [[TMP68]] +// CHECK1-NEXT: [[MUL95:%.*]] = mul i32 1, [[DIV94]] +// CHECK1-NEXT: [[TMP69:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB96:%.*]] = sub i32 [[TMP69]], -31 +// CHECK1-NEXT: [[DIV97:%.*]] = udiv i32 [[SUB96]], 32 +// CHECK1-NEXT: [[MUL98:%.*]] = mul i32 [[MUL95]], [[DIV97]] +// CHECK1-NEXT: [[MUL99:%.*]] = mul i32 [[MUL98]], 32 +// CHECK1-NEXT: [[CONV100:%.*]] = zext i32 [[MUL99]] to i64 +// CHECK1-NEXT: [[DIV101:%.*]] = sdiv i64 [[TMP64]], [[CONV100]] // CHECK1-NEXT: [[TMP70:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 // CHECK1-NEXT: [[TMP71:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK1-NEXT: [[SUB95:%.*]] = sub i32 [[TMP70]], [[TMP71]] -// CHECK1-NEXT: [[SUB96:%.*]] = sub i32 [[SUB95]], 1 +// CHECK1-NEXT: [[SUB102:%.*]] = sub i32 [[TMP70]], [[TMP71]] +// CHECK1-NEXT: [[SUB103:%.*]] = sub i32 [[SUB102]], 1 // CHECK1-NEXT: [[TMP72:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[ADD97:%.*]] = add i32 [[SUB96]], [[TMP72]] +// CHECK1-NEXT: [[ADD104:%.*]] = add i32 [[SUB103]], [[TMP72]] // CHECK1-NEXT: [[TMP73:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[DIV98:%.*]] = udiv i32 [[ADD97]], [[TMP73]] -// CHECK1-NEXT: [[MUL99:%.*]] = mul i32 1, [[DIV98]] +// CHECK1-NEXT: [[DIV105:%.*]] = udiv i32 [[ADD104]], [[TMP73]] +// CHECK1-NEXT: [[MUL106:%.*]] = mul i32 1, [[DIV105]] // CHECK1-NEXT: [[TMP74:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB100:%.*]] = sub i32 [[TMP74]], -31 -// CHECK1-NEXT: [[DIV101:%.*]] = udiv i32 [[SUB100]], 32 -// CHECK1-NEXT: [[MUL102:%.*]] = mul i32 [[MUL99]], [[DIV101]] -// CHECK1-NEXT: [[TMP75:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP76:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB103:%.*]] = sub i32 [[TMP75]], [[TMP76]] -// CHECK1-NEXT: [[SUB104:%.*]] = sub i32 [[SUB103]], 1 -// CHECK1-NEXT: [[ADD105:%.*]] = add i32 [[SUB104]], 1 -// CHECK1-NEXT: [[DIV106:%.*]] = udiv i32 [[ADD105]], 1 -// CHECK1-NEXT: [[MUL107:%.*]] = mul i32 [[MUL102]], [[DIV106]] -// CHECK1-NEXT: [[CONV108:%.*]] = zext i32 [[MUL107]] to i64 -// CHECK1-NEXT: [[MUL109:%.*]] = mul nsw i64 [[DIV94]], [[CONV108]] -// CHECK1-NEXT: [[SUB110:%.*]] = sub nsw i64 [[TMP61]], [[MUL109]] -// CHECK1-NEXT: [[TMP77:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB111:%.*]] = sub i32 [[TMP77]], -31 -// CHECK1-NEXT: [[DIV112:%.*]] = udiv i32 [[SUB111]], 32 -// CHECK1-NEXT: [[MUL113:%.*]] = mul i32 1, [[DIV112]] -// CHECK1-NEXT: [[TMP78:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP79:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB114:%.*]] = sub i32 [[TMP78]], [[TMP79]] +// CHECK1-NEXT: [[SUB107:%.*]] = sub i32 [[TMP74]], -31 +// CHECK1-NEXT: [[DIV108:%.*]] = udiv i32 [[SUB107]], 32 +// CHECK1-NEXT: [[MUL109:%.*]] = mul i32 [[MUL106]], [[DIV108]] +// CHECK1-NEXT: [[MUL110:%.*]] = mul i32 [[MUL109]], 32 +// CHECK1-NEXT: [[CONV111:%.*]] = zext i32 [[MUL110]] to i64 +// CHECK1-NEXT: [[MUL112:%.*]] = mul nsw i64 [[DIV101]], [[CONV111]] +// CHECK1-NEXT: [[SUB113:%.*]] = sub nsw i64 [[TMP63]], [[MUL112]] +// CHECK1-NEXT: [[TMP75:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[TMP76:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[TMP77:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK1-NEXT: [[TMP78:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK1-NEXT: [[SUB114:%.*]] = sub i32 [[TMP77]], [[TMP78]] // CHECK1-NEXT: [[SUB115:%.*]] = sub i32 [[SUB114]], 1 -// CHECK1-NEXT: [[ADD116:%.*]] = add i32 [[SUB115]], 1 -// CHECK1-NEXT: [[DIV117:%.*]] = udiv i32 [[ADD116]], 1 -// CHECK1-NEXT: [[MUL118:%.*]] = mul i32 [[MUL113]], [[DIV117]] -// CHECK1-NEXT: [[CONV119:%.*]] = zext i32 [[MUL118]] to i64 -// CHECK1-NEXT: [[DIV120:%.*]] = sdiv i64 [[SUB110]], [[CONV119]] +// CHECK1-NEXT: [[TMP79:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[ADD116:%.*]] = add i32 [[SUB115]], [[TMP79]] // CHECK1-NEXT: [[TMP80:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[CONV121:%.*]] = sext i32 [[TMP80]] to i64 -// CHECK1-NEXT: [[MUL122:%.*]] = mul nsw i64 [[DIV120]], [[CONV121]] -// CHECK1-NEXT: [[ADD123:%.*]] = add nsw i64 [[CONV79]], [[MUL122]] -// CHECK1-NEXT: [[CONV124:%.*]] = trunc i64 [[ADD123]] to i32 -// CHECK1-NEXT: store i32 [[CONV124]], ptr [[J50]], align 4 -// CHECK1-NEXT: [[TMP81:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP82:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP83:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK1-NEXT: [[TMP84:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK1-NEXT: [[SUB125:%.*]] = sub i32 [[TMP83]], [[TMP84]] +// CHECK1-NEXT: [[DIV117:%.*]] = udiv i32 [[ADD116]], [[TMP80]] +// CHECK1-NEXT: [[MUL118:%.*]] = mul i32 1, [[DIV117]] +// CHECK1-NEXT: [[TMP81:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB119:%.*]] = sub i32 [[TMP81]], -31 +// CHECK1-NEXT: [[DIV120:%.*]] = udiv i32 [[SUB119]], 32 +// CHECK1-NEXT: [[MUL121:%.*]] = mul i32 [[MUL118]], [[DIV120]] +// CHECK1-NEXT: [[MUL122:%.*]] = mul i32 [[MUL121]], 32 +// CHECK1-NEXT: [[CONV123:%.*]] = zext i32 [[MUL122]] to i64 +// CHECK1-NEXT: [[DIV124:%.*]] = sdiv i64 [[TMP76]], [[CONV123]] +// CHECK1-NEXT: [[TMP82:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK1-NEXT: [[TMP83:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK1-NEXT: [[SUB125:%.*]] = sub i32 [[TMP82]], [[TMP83]] // CHECK1-NEXT: [[SUB126:%.*]] = sub i32 [[SUB125]], 1 +// CHECK1-NEXT: [[TMP84:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[ADD127:%.*]] = add i32 [[SUB126]], [[TMP84]] // CHECK1-NEXT: [[TMP85:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[ADD127:%.*]] = add i32 [[SUB126]], [[TMP85]] -// CHECK1-NEXT: [[TMP86:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[DIV128:%.*]] = udiv i32 [[ADD127]], [[TMP86]] +// CHECK1-NEXT: [[DIV128:%.*]] = udiv i32 [[ADD127]], [[TMP85]] // CHECK1-NEXT: [[MUL129:%.*]] = mul i32 1, [[DIV128]] -// CHECK1-NEXT: [[TMP87:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB130:%.*]] = sub i32 [[TMP87]], -31 +// CHECK1-NEXT: [[TMP86:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB130:%.*]] = sub i32 [[TMP86]], -31 // CHECK1-NEXT: [[DIV131:%.*]] = udiv i32 [[SUB130]], 32 // CHECK1-NEXT: [[MUL132:%.*]] = mul i32 [[MUL129]], [[DIV131]] -// CHECK1-NEXT: [[TMP88:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP89:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB133:%.*]] = sub i32 [[TMP88]], [[TMP89]] -// CHECK1-NEXT: [[SUB134:%.*]] = sub i32 [[SUB133]], 1 -// CHECK1-NEXT: [[ADD135:%.*]] = add i32 [[SUB134]], 1 -// CHECK1-NEXT: [[DIV136:%.*]] = udiv i32 [[ADD135]], 1 -// CHECK1-NEXT: [[MUL137:%.*]] = mul i32 [[MUL132]], [[DIV136]] -// CHECK1-NEXT: [[CONV138:%.*]] = zext i32 [[MUL137]] to i64 -// CHECK1-NEXT: [[DIV139:%.*]] = sdiv i64 [[TMP82]], [[CONV138]] -// CHECK1-NEXT: [[TMP90:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK1-NEXT: [[TMP91:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK1-NEXT: [[SUB140:%.*]] = sub i32 [[TMP90]], [[TMP91]] -// CHECK1-NEXT: [[SUB141:%.*]] = sub i32 [[SUB140]], 1 -// CHECK1-NEXT: [[TMP92:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[ADD142:%.*]] = add i32 [[SUB141]], [[TMP92]] +// CHECK1-NEXT: [[MUL133:%.*]] = mul i32 [[MUL132]], 32 +// CHECK1-NEXT: [[CONV134:%.*]] = zext i32 [[MUL133]] to i64 +// CHECK1-NEXT: [[MUL135:%.*]] = mul nsw i64 [[DIV124]], [[CONV134]] +// CHECK1-NEXT: [[SUB136:%.*]] = sub nsw i64 [[TMP75]], [[MUL135]] +// CHECK1-NEXT: [[TMP87:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB137:%.*]] = sub i32 [[TMP87]], -31 +// CHECK1-NEXT: [[DIV138:%.*]] = udiv i32 [[SUB137]], 32 +// CHECK1-NEXT: [[MUL139:%.*]] = mul i32 1, [[DIV138]] +// CHECK1-NEXT: [[MUL140:%.*]] = mul i32 [[MUL139]], 32 +// CHECK1-NEXT: [[CONV141:%.*]] = zext i32 [[MUL140]] to i64 +// CHECK1-NEXT: [[DIV142:%.*]] = sdiv i64 [[SUB136]], [[CONV141]] +// CHECK1-NEXT: [[TMP88:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB143:%.*]] = sub i32 [[TMP88]], -31 +// CHECK1-NEXT: [[DIV144:%.*]] = udiv i32 [[SUB143]], 32 +// CHECK1-NEXT: [[MUL145:%.*]] = mul i32 1, [[DIV144]] +// CHECK1-NEXT: [[MUL146:%.*]] = mul i32 [[MUL145]], 32 +// CHECK1-NEXT: [[CONV147:%.*]] = zext i32 [[MUL146]] to i64 +// CHECK1-NEXT: [[MUL148:%.*]] = mul nsw i64 [[DIV142]], [[CONV147]] +// CHECK1-NEXT: [[SUB149:%.*]] = sub nsw i64 [[SUB113]], [[MUL148]] +// CHECK1-NEXT: [[DIV150:%.*]] = sdiv i64 [[SUB149]], 32 +// CHECK1-NEXT: [[MUL151:%.*]] = mul nsw i64 [[DIV150]], 32 +// CHECK1-NEXT: [[ADD152:%.*]] = add nsw i64 0, [[MUL151]] +// CHECK1-NEXT: [[CONV153:%.*]] = trunc i64 [[ADD152]] to i32 +// CHECK1-NEXT: store i32 [[CONV153]], ptr [[DOTFLOOR_0_IV_K37]], align 4 +// CHECK1-NEXT: [[TMP89:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[TMP90:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[TMP91:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK1-NEXT: [[TMP92:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK1-NEXT: [[SUB154:%.*]] = sub i32 [[TMP91]], [[TMP92]] +// CHECK1-NEXT: [[SUB155:%.*]] = sub i32 [[SUB154]], 1 // CHECK1-NEXT: [[TMP93:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[DIV143:%.*]] = udiv i32 [[ADD142]], [[TMP93]] -// CHECK1-NEXT: [[MUL144:%.*]] = mul i32 1, [[DIV143]] -// CHECK1-NEXT: [[TMP94:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB145:%.*]] = sub i32 [[TMP94]], -31 -// CHECK1-NEXT: [[DIV146:%.*]] = udiv i32 [[SUB145]], 32 -// CHECK1-NEXT: [[MUL147:%.*]] = mul i32 [[MUL144]], [[DIV146]] -// CHECK1-NEXT: [[TMP95:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP96:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB148:%.*]] = sub i32 [[TMP95]], [[TMP96]] -// CHECK1-NEXT: [[SUB149:%.*]] = sub i32 [[SUB148]], 1 -// CHECK1-NEXT: [[ADD150:%.*]] = add i32 [[SUB149]], 1 -// CHECK1-NEXT: [[DIV151:%.*]] = udiv i32 [[ADD150]], 1 -// CHECK1-NEXT: [[MUL152:%.*]] = mul i32 [[MUL147]], [[DIV151]] -// CHECK1-NEXT: [[CONV153:%.*]] = zext i32 [[MUL152]] to i64 -// CHECK1-NEXT: [[MUL154:%.*]] = mul nsw i64 [[DIV139]], [[CONV153]] -// CHECK1-NEXT: [[SUB155:%.*]] = sub nsw i64 [[TMP81]], [[MUL154]] -// CHECK1-NEXT: [[TMP97:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP98:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP99:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK1-NEXT: [[TMP100:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK1-NEXT: [[SUB156:%.*]] = sub i32 [[TMP99]], [[TMP100]] -// CHECK1-NEXT: [[SUB157:%.*]] = sub i32 [[SUB156]], 1 -// CHECK1-NEXT: [[TMP101:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[ADD158:%.*]] = add i32 [[SUB157]], [[TMP101]] -// CHECK1-NEXT: [[TMP102:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[DIV159:%.*]] = udiv i32 [[ADD158]], [[TMP102]] -// CHECK1-NEXT: [[MUL160:%.*]] = mul i32 1, [[DIV159]] -// CHECK1-NEXT: [[TMP103:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB161:%.*]] = sub i32 [[TMP103]], -31 -// CHECK1-NEXT: [[DIV162:%.*]] = udiv i32 [[SUB161]], 32 -// CHECK1-NEXT: [[MUL163:%.*]] = mul i32 [[MUL160]], [[DIV162]] -// CHECK1-NEXT: [[TMP104:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP105:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB164:%.*]] = sub i32 [[TMP104]], [[TMP105]] -// CHECK1-NEXT: [[SUB165:%.*]] = sub i32 [[SUB164]], 1 -// CHECK1-NEXT: [[ADD166:%.*]] = add i32 [[SUB165]], 1 -// CHECK1-NEXT: [[DIV167:%.*]] = udiv i32 [[ADD166]], 1 -// CHECK1-NEXT: [[MUL168:%.*]] = mul i32 [[MUL163]], [[DIV167]] -// CHECK1-NEXT: [[CONV169:%.*]] = zext i32 [[MUL168]] to i64 -// CHECK1-NEXT: [[DIV170:%.*]] = sdiv i64 [[TMP98]], [[CONV169]] -// CHECK1-NEXT: [[TMP106:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK1-NEXT: [[TMP107:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK1-NEXT: [[SUB171:%.*]] = sub i32 [[TMP106]], [[TMP107]] -// CHECK1-NEXT: [[SUB172:%.*]] = sub i32 [[SUB171]], 1 -// CHECK1-NEXT: [[TMP108:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[ADD173:%.*]] = add i32 [[SUB172]], [[TMP108]] -// CHECK1-NEXT: [[TMP109:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[DIV174:%.*]] = udiv i32 [[ADD173]], [[TMP109]] -// CHECK1-NEXT: [[MUL175:%.*]] = mul i32 1, [[DIV174]] -// CHECK1-NEXT: [[TMP110:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB176:%.*]] = sub i32 [[TMP110]], -31 -// CHECK1-NEXT: [[DIV177:%.*]] = udiv i32 [[SUB176]], 32 -// CHECK1-NEXT: [[MUL178:%.*]] = mul i32 [[MUL175]], [[DIV177]] -// CHECK1-NEXT: [[TMP111:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP112:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB179:%.*]] = sub i32 [[TMP111]], [[TMP112]] -// CHECK1-NEXT: [[SUB180:%.*]] = sub i32 [[SUB179]], 1 -// CHECK1-NEXT: [[ADD181:%.*]] = add i32 [[SUB180]], 1 -// CHECK1-NEXT: [[DIV182:%.*]] = udiv i32 [[ADD181]], 1 -// CHECK1-NEXT: [[MUL183:%.*]] = mul i32 [[MUL178]], [[DIV182]] -// CHECK1-NEXT: [[CONV184:%.*]] = zext i32 [[MUL183]] to i64 -// CHECK1-NEXT: [[MUL185:%.*]] = mul nsw i64 [[DIV170]], [[CONV184]] -// CHECK1-NEXT: [[SUB186:%.*]] = sub nsw i64 [[TMP97]], [[MUL185]] +// CHECK1-NEXT: [[ADD156:%.*]] = add i32 [[SUB155]], [[TMP93]] +// CHECK1-NEXT: [[TMP94:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[DIV157:%.*]] = udiv i32 [[ADD156]], [[TMP94]] +// CHECK1-NEXT: [[MUL158:%.*]] = mul i32 1, [[DIV157]] +// CHECK1-NEXT: [[TMP95:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB159:%.*]] = sub i32 [[TMP95]], -31 +// CHECK1-NEXT: [[DIV160:%.*]] = udiv i32 [[SUB159]], 32 +// CHECK1-NEXT: [[MUL161:%.*]] = mul i32 [[MUL158]], [[DIV160]] +// CHECK1-NEXT: [[MUL162:%.*]] = mul i32 [[MUL161]], 32 +// CHECK1-NEXT: [[CONV163:%.*]] = zext i32 [[MUL162]] to i64 +// CHECK1-NEXT: [[DIV164:%.*]] = sdiv i64 [[TMP90]], [[CONV163]] +// CHECK1-NEXT: [[TMP96:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK1-NEXT: [[TMP97:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK1-NEXT: [[SUB165:%.*]] = sub i32 [[TMP96]], [[TMP97]] +// CHECK1-NEXT: [[SUB166:%.*]] = sub i32 [[SUB165]], 1 +// CHECK1-NEXT: [[TMP98:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[ADD167:%.*]] = add i32 [[SUB166]], [[TMP98]] +// CHECK1-NEXT: [[TMP99:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[DIV168:%.*]] = udiv i32 [[ADD167]], [[TMP99]] +// CHECK1-NEXT: [[MUL169:%.*]] = mul i32 1, [[DIV168]] +// CHECK1-NEXT: [[TMP100:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB170:%.*]] = sub i32 [[TMP100]], -31 +// CHECK1-NEXT: [[DIV171:%.*]] = udiv i32 [[SUB170]], 32 +// CHECK1-NEXT: [[MUL172:%.*]] = mul i32 [[MUL169]], [[DIV171]] +// CHECK1-NEXT: [[MUL173:%.*]] = mul i32 [[MUL172]], 32 +// CHECK1-NEXT: [[CONV174:%.*]] = zext i32 [[MUL173]] to i64 +// CHECK1-NEXT: [[MUL175:%.*]] = mul nsw i64 [[DIV164]], [[CONV174]] +// CHECK1-NEXT: [[SUB176:%.*]] = sub nsw i64 [[TMP89]], [[MUL175]] +// CHECK1-NEXT: [[TMP101:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[TMP102:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[TMP103:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK1-NEXT: [[TMP104:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK1-NEXT: [[SUB177:%.*]] = sub i32 [[TMP103]], [[TMP104]] +// CHECK1-NEXT: [[SUB178:%.*]] = sub i32 [[SUB177]], 1 +// CHECK1-NEXT: [[TMP105:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[ADD179:%.*]] = add i32 [[SUB178]], [[TMP105]] +// CHECK1-NEXT: [[TMP106:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[DIV180:%.*]] = udiv i32 [[ADD179]], [[TMP106]] +// CHECK1-NEXT: [[MUL181:%.*]] = mul i32 1, [[DIV180]] +// CHECK1-NEXT: [[TMP107:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB182:%.*]] = sub i32 [[TMP107]], -31 +// CHECK1-NEXT: [[DIV183:%.*]] = udiv i32 [[SUB182]], 32 +// CHECK1-NEXT: [[MUL184:%.*]] = mul i32 [[MUL181]], [[DIV183]] +// CHECK1-NEXT: [[MUL185:%.*]] = mul i32 [[MUL184]], 32 +// CHECK1-NEXT: [[CONV186:%.*]] = zext i32 [[MUL185]] to i64 +// CHECK1-NEXT: [[DIV187:%.*]] = sdiv i64 [[TMP102]], [[CONV186]] +// CHECK1-NEXT: [[TMP108:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK1-NEXT: [[TMP109:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK1-NEXT: [[SUB188:%.*]] = sub i32 [[TMP108]], [[TMP109]] +// CHECK1-NEXT: [[SUB189:%.*]] = sub i32 [[SUB188]], 1 +// CHECK1-NEXT: [[TMP110:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[ADD190:%.*]] = add i32 [[SUB189]], [[TMP110]] +// CHECK1-NEXT: [[TMP111:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[DIV191:%.*]] = udiv i32 [[ADD190]], [[TMP111]] +// CHECK1-NEXT: [[MUL192:%.*]] = mul i32 1, [[DIV191]] +// CHECK1-NEXT: [[TMP112:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB193:%.*]] = sub i32 [[TMP112]], -31 +// CHECK1-NEXT: [[DIV194:%.*]] = udiv i32 [[SUB193]], 32 +// CHECK1-NEXT: [[MUL195:%.*]] = mul i32 [[MUL192]], [[DIV194]] +// CHECK1-NEXT: [[MUL196:%.*]] = mul i32 [[MUL195]], 32 +// CHECK1-NEXT: [[CONV197:%.*]] = zext i32 [[MUL196]] to i64 +// CHECK1-NEXT: [[MUL198:%.*]] = mul nsw i64 [[DIV187]], [[CONV197]] +// CHECK1-NEXT: [[SUB199:%.*]] = sub nsw i64 [[TMP101]], [[MUL198]] // CHECK1-NEXT: [[TMP113:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB187:%.*]] = sub i32 [[TMP113]], -31 -// CHECK1-NEXT: [[DIV188:%.*]] = udiv i32 [[SUB187]], 32 -// CHECK1-NEXT: [[MUL189:%.*]] = mul i32 1, [[DIV188]] -// CHECK1-NEXT: [[TMP114:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP115:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB190:%.*]] = sub i32 [[TMP114]], [[TMP115]] -// CHECK1-NEXT: [[SUB191:%.*]] = sub i32 [[SUB190]], 1 -// CHECK1-NEXT: [[ADD192:%.*]] = add i32 [[SUB191]], 1 -// CHECK1-NEXT: [[DIV193:%.*]] = udiv i32 [[ADD192]], 1 -// CHECK1-NEXT: [[MUL194:%.*]] = mul i32 [[MUL189]], [[DIV193]] -// CHECK1-NEXT: [[CONV195:%.*]] = zext i32 [[MUL194]] to i64 -// CHECK1-NEXT: [[DIV196:%.*]] = sdiv i64 [[SUB186]], [[CONV195]] -// CHECK1-NEXT: [[TMP116:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB197:%.*]] = sub i32 [[TMP116]], -31 -// CHECK1-NEXT: [[DIV198:%.*]] = udiv i32 [[SUB197]], 32 -// CHECK1-NEXT: [[MUL199:%.*]] = mul i32 1, [[DIV198]] -// CHECK1-NEXT: [[TMP117:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP118:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB200:%.*]] = sub i32 [[TMP117]], [[TMP118]] -// CHECK1-NEXT: [[SUB201:%.*]] = sub i32 [[SUB200]], 1 -// CHECK1-NEXT: [[ADD202:%.*]] = add i32 [[SUB201]], 1 -// CHECK1-NEXT: [[DIV203:%.*]] = udiv i32 [[ADD202]], 1 -// CHECK1-NEXT: [[MUL204:%.*]] = mul i32 [[MUL199]], [[DIV203]] -// CHECK1-NEXT: [[CONV205:%.*]] = zext i32 [[MUL204]] to i64 -// CHECK1-NEXT: [[MUL206:%.*]] = mul nsw i64 [[DIV196]], [[CONV205]] -// CHECK1-NEXT: [[SUB207:%.*]] = sub nsw i64 [[SUB155]], [[MUL206]] -// CHECK1-NEXT: [[TMP119:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP120:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB208:%.*]] = sub i32 [[TMP119]], [[TMP120]] -// CHECK1-NEXT: [[SUB209:%.*]] = sub i32 [[SUB208]], 1 -// CHECK1-NEXT: [[ADD210:%.*]] = add i32 [[SUB209]], 1 -// CHECK1-NEXT: [[DIV211:%.*]] = udiv i32 [[ADD210]], 1 -// CHECK1-NEXT: [[MUL212:%.*]] = mul i32 1, [[DIV211]] -// CHECK1-NEXT: [[CONV213:%.*]] = zext i32 [[MUL212]] to i64 -// CHECK1-NEXT: [[DIV214:%.*]] = sdiv i64 [[SUB207]], [[CONV213]] -// CHECK1-NEXT: [[MUL215:%.*]] = mul nsw i64 [[DIV214]], 32 -// CHECK1-NEXT: [[ADD216:%.*]] = add nsw i64 0, [[MUL215]] -// CHECK1-NEXT: [[CONV217:%.*]] = trunc i64 [[ADD216]] to i32 -// CHECK1-NEXT: store i32 [[CONV217]], ptr [[DOTFLOOR_0_IV_K51]], align 4 -// CHECK1-NEXT: [[TMP121:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[CONV218:%.*]] = zext i32 [[TMP121]] to i64 -// CHECK1-NEXT: [[TMP122:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP123:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP124:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK1-NEXT: [[TMP125:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK1-NEXT: [[SUB219:%.*]] = sub i32 [[TMP124]], [[TMP125]] -// CHECK1-NEXT: [[SUB220:%.*]] = sub i32 [[SUB219]], 1 -// CHECK1-NEXT: [[TMP126:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[ADD221:%.*]] = add i32 [[SUB220]], [[TMP126]] -// CHECK1-NEXT: [[TMP127:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[DIV222:%.*]] = udiv i32 [[ADD221]], [[TMP127]] -// CHECK1-NEXT: [[MUL223:%.*]] = mul i32 1, [[DIV222]] -// CHECK1-NEXT: [[TMP128:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB224:%.*]] = sub i32 [[TMP128]], -31 -// CHECK1-NEXT: [[DIV225:%.*]] = udiv i32 [[SUB224]], 32 -// CHECK1-NEXT: [[MUL226:%.*]] = mul i32 [[MUL223]], [[DIV225]] -// CHECK1-NEXT: [[TMP129:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP130:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB227:%.*]] = sub i32 [[TMP129]], [[TMP130]] -// CHECK1-NEXT: [[SUB228:%.*]] = sub i32 [[SUB227]], 1 -// CHECK1-NEXT: [[ADD229:%.*]] = add i32 [[SUB228]], 1 -// CHECK1-NEXT: [[DIV230:%.*]] = udiv i32 [[ADD229]], 1 -// CHECK1-NEXT: [[MUL231:%.*]] = mul i32 [[MUL226]], [[DIV230]] -// CHECK1-NEXT: [[CONV232:%.*]] = zext i32 [[MUL231]] to i64 -// CHECK1-NEXT: [[DIV233:%.*]] = sdiv i64 [[TMP123]], [[CONV232]] -// CHECK1-NEXT: [[TMP131:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK1-NEXT: [[TMP132:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK1-NEXT: [[SUB234:%.*]] = sub i32 [[TMP131]], [[TMP132]] -// CHECK1-NEXT: [[SUB235:%.*]] = sub i32 [[SUB234]], 1 -// CHECK1-NEXT: [[TMP133:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[ADD236:%.*]] = add i32 [[SUB235]], [[TMP133]] -// CHECK1-NEXT: [[TMP134:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[DIV237:%.*]] = udiv i32 [[ADD236]], [[TMP134]] -// CHECK1-NEXT: [[MUL238:%.*]] = mul i32 1, [[DIV237]] -// CHECK1-NEXT: [[TMP135:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB239:%.*]] = sub i32 [[TMP135]], -31 -// CHECK1-NEXT: [[DIV240:%.*]] = udiv i32 [[SUB239]], 32 -// CHECK1-NEXT: [[MUL241:%.*]] = mul i32 [[MUL238]], [[DIV240]] -// CHECK1-NEXT: [[TMP136:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP137:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB242:%.*]] = sub i32 [[TMP136]], [[TMP137]] -// CHECK1-NEXT: [[SUB243:%.*]] = sub i32 [[SUB242]], 1 -// CHECK1-NEXT: [[ADD244:%.*]] = add i32 [[SUB243]], 1 -// CHECK1-NEXT: [[DIV245:%.*]] = udiv i32 [[ADD244]], 1 -// CHECK1-NEXT: [[MUL246:%.*]] = mul i32 [[MUL241]], [[DIV245]] -// CHECK1-NEXT: [[CONV247:%.*]] = zext i32 [[MUL246]] to i64 -// CHECK1-NEXT: [[MUL248:%.*]] = mul nsw i64 [[DIV233]], [[CONV247]] -// CHECK1-NEXT: [[SUB249:%.*]] = sub nsw i64 [[TMP122]], [[MUL248]] -// CHECK1-NEXT: [[TMP138:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP139:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP140:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK1-NEXT: [[TMP141:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK1-NEXT: [[SUB250:%.*]] = sub i32 [[TMP140]], [[TMP141]] -// CHECK1-NEXT: [[SUB251:%.*]] = sub i32 [[SUB250]], 1 -// CHECK1-NEXT: [[TMP142:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[ADD252:%.*]] = add i32 [[SUB251]], [[TMP142]] -// CHECK1-NEXT: [[TMP143:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[DIV253:%.*]] = udiv i32 [[ADD252]], [[TMP143]] -// CHECK1-NEXT: [[MUL254:%.*]] = mul i32 1, [[DIV253]] -// CHECK1-NEXT: [[TMP144:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB255:%.*]] = sub i32 [[TMP144]], -31 -// CHECK1-NEXT: [[DIV256:%.*]] = udiv i32 [[SUB255]], 32 -// CHECK1-NEXT: [[MUL257:%.*]] = mul i32 [[MUL254]], [[DIV256]] -// CHECK1-NEXT: [[TMP145:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP146:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB258:%.*]] = sub i32 [[TMP145]], [[TMP146]] -// CHECK1-NEXT: [[SUB259:%.*]] = sub i32 [[SUB258]], 1 -// CHECK1-NEXT: [[ADD260:%.*]] = add i32 [[SUB259]], 1 -// CHECK1-NEXT: [[DIV261:%.*]] = udiv i32 [[ADD260]], 1 -// CHECK1-NEXT: [[MUL262:%.*]] = mul i32 [[MUL257]], [[DIV261]] +// CHECK1-NEXT: [[SUB200:%.*]] = sub i32 [[TMP113]], -31 +// CHECK1-NEXT: [[DIV201:%.*]] = udiv i32 [[SUB200]], 32 +// CHECK1-NEXT: [[MUL202:%.*]] = mul i32 1, [[DIV201]] +// CHECK1-NEXT: [[MUL203:%.*]] = mul i32 [[MUL202]], 32 +// CHECK1-NEXT: [[CONV204:%.*]] = zext i32 [[MUL203]] to i64 +// CHECK1-NEXT: [[DIV205:%.*]] = sdiv i64 [[SUB199]], [[CONV204]] +// CHECK1-NEXT: [[TMP114:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB206:%.*]] = sub i32 [[TMP114]], -31 +// CHECK1-NEXT: [[DIV207:%.*]] = udiv i32 [[SUB206]], 32 +// CHECK1-NEXT: [[MUL208:%.*]] = mul i32 1, [[DIV207]] +// CHECK1-NEXT: [[MUL209:%.*]] = mul i32 [[MUL208]], 32 +// CHECK1-NEXT: [[CONV210:%.*]] = zext i32 [[MUL209]] to i64 +// CHECK1-NEXT: [[MUL211:%.*]] = mul nsw i64 [[DIV205]], [[CONV210]] +// CHECK1-NEXT: [[SUB212:%.*]] = sub nsw i64 [[SUB176]], [[MUL211]] +// CHECK1-NEXT: [[TMP115:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[TMP116:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[TMP117:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK1-NEXT: [[TMP118:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK1-NEXT: [[SUB213:%.*]] = sub i32 [[TMP117]], [[TMP118]] +// CHECK1-NEXT: [[SUB214:%.*]] = sub i32 [[SUB213]], 1 +// CHECK1-NEXT: [[TMP119:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[ADD215:%.*]] = add i32 [[SUB214]], [[TMP119]] +// CHECK1-NEXT: [[TMP120:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[DIV216:%.*]] = udiv i32 [[ADD215]], [[TMP120]] +// CHECK1-NEXT: [[MUL217:%.*]] = mul i32 1, [[DIV216]] +// CHECK1-NEXT: [[TMP121:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB218:%.*]] = sub i32 [[TMP121]], -31 +// CHECK1-NEXT: [[DIV219:%.*]] = udiv i32 [[SUB218]], 32 +// CHECK1-NEXT: [[MUL220:%.*]] = mul i32 [[MUL217]], [[DIV219]] +// CHECK1-NEXT: [[MUL221:%.*]] = mul i32 [[MUL220]], 32 +// CHECK1-NEXT: [[CONV222:%.*]] = zext i32 [[MUL221]] to i64 +// CHECK1-NEXT: [[DIV223:%.*]] = sdiv i64 [[TMP116]], [[CONV222]] +// CHECK1-NEXT: [[TMP122:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK1-NEXT: [[TMP123:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK1-NEXT: [[SUB224:%.*]] = sub i32 [[TMP122]], [[TMP123]] +// CHECK1-NEXT: [[SUB225:%.*]] = sub i32 [[SUB224]], 1 +// CHECK1-NEXT: [[TMP124:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[ADD226:%.*]] = add i32 [[SUB225]], [[TMP124]] +// CHECK1-NEXT: [[TMP125:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[DIV227:%.*]] = udiv i32 [[ADD226]], [[TMP125]] +// CHECK1-NEXT: [[MUL228:%.*]] = mul i32 1, [[DIV227]] +// CHECK1-NEXT: [[TMP126:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB229:%.*]] = sub i32 [[TMP126]], -31 +// CHECK1-NEXT: [[DIV230:%.*]] = udiv i32 [[SUB229]], 32 +// CHECK1-NEXT: [[MUL231:%.*]] = mul i32 [[MUL228]], [[DIV230]] +// CHECK1-NEXT: [[MUL232:%.*]] = mul i32 [[MUL231]], 32 +// CHECK1-NEXT: [[CONV233:%.*]] = zext i32 [[MUL232]] to i64 +// CHECK1-NEXT: [[MUL234:%.*]] = mul nsw i64 [[DIV223]], [[CONV233]] +// CHECK1-NEXT: [[SUB235:%.*]] = sub nsw i64 [[TMP115]], [[MUL234]] +// CHECK1-NEXT: [[TMP127:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[TMP128:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[TMP129:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK1-NEXT: [[TMP130:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK1-NEXT: [[SUB236:%.*]] = sub i32 [[TMP129]], [[TMP130]] +// CHECK1-NEXT: [[SUB237:%.*]] = sub i32 [[SUB236]], 1 +// CHECK1-NEXT: [[TMP131:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[ADD238:%.*]] = add i32 [[SUB237]], [[TMP131]] +// CHECK1-NEXT: [[TMP132:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[DIV239:%.*]] = udiv i32 [[ADD238]], [[TMP132]] +// CHECK1-NEXT: [[MUL240:%.*]] = mul i32 1, [[DIV239]] +// CHECK1-NEXT: [[TMP133:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB241:%.*]] = sub i32 [[TMP133]], -31 +// CHECK1-NEXT: [[DIV242:%.*]] = udiv i32 [[SUB241]], 32 +// CHECK1-NEXT: [[MUL243:%.*]] = mul i32 [[MUL240]], [[DIV242]] +// CHECK1-NEXT: [[MUL244:%.*]] = mul i32 [[MUL243]], 32 +// CHECK1-NEXT: [[CONV245:%.*]] = zext i32 [[MUL244]] to i64 +// CHECK1-NEXT: [[DIV246:%.*]] = sdiv i64 [[TMP128]], [[CONV245]] +// CHECK1-NEXT: [[TMP134:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK1-NEXT: [[TMP135:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK1-NEXT: [[SUB247:%.*]] = sub i32 [[TMP134]], [[TMP135]] +// CHECK1-NEXT: [[SUB248:%.*]] = sub i32 [[SUB247]], 1 +// CHECK1-NEXT: [[TMP136:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[ADD249:%.*]] = add i32 [[SUB248]], [[TMP136]] +// CHECK1-NEXT: [[TMP137:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[DIV250:%.*]] = udiv i32 [[ADD249]], [[TMP137]] +// CHECK1-NEXT: [[MUL251:%.*]] = mul i32 1, [[DIV250]] +// CHECK1-NEXT: [[TMP138:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB252:%.*]] = sub i32 [[TMP138]], -31 +// CHECK1-NEXT: [[DIV253:%.*]] = udiv i32 [[SUB252]], 32 +// CHECK1-NEXT: [[MUL254:%.*]] = mul i32 [[MUL251]], [[DIV253]] +// CHECK1-NEXT: [[MUL255:%.*]] = mul i32 [[MUL254]], 32 +// CHECK1-NEXT: [[CONV256:%.*]] = zext i32 [[MUL255]] to i64 +// CHECK1-NEXT: [[MUL257:%.*]] = mul nsw i64 [[DIV246]], [[CONV256]] +// CHECK1-NEXT: [[SUB258:%.*]] = sub nsw i64 [[TMP127]], [[MUL257]] +// CHECK1-NEXT: [[TMP139:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB259:%.*]] = sub i32 [[TMP139]], -31 +// CHECK1-NEXT: [[DIV260:%.*]] = udiv i32 [[SUB259]], 32 +// CHECK1-NEXT: [[MUL261:%.*]] = mul i32 1, [[DIV260]] +// CHECK1-NEXT: [[MUL262:%.*]] = mul i32 [[MUL261]], 32 // CHECK1-NEXT: [[CONV263:%.*]] = zext i32 [[MUL262]] to i64 -// CHECK1-NEXT: [[DIV264:%.*]] = sdiv i64 [[TMP139]], [[CONV263]] -// CHECK1-NEXT: [[TMP147:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK1-NEXT: [[TMP148:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK1-NEXT: [[SUB265:%.*]] = sub i32 [[TMP147]], [[TMP148]] -// CHECK1-NEXT: [[SUB266:%.*]] = sub i32 [[SUB265]], 1 -// CHECK1-NEXT: [[TMP149:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[ADD267:%.*]] = add i32 [[SUB266]], [[TMP149]] -// CHECK1-NEXT: [[TMP150:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[DIV268:%.*]] = udiv i32 [[ADD267]], [[TMP150]] -// CHECK1-NEXT: [[MUL269:%.*]] = mul i32 1, [[DIV268]] -// CHECK1-NEXT: [[TMP151:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB270:%.*]] = sub i32 [[TMP151]], -31 -// CHECK1-NEXT: [[DIV271:%.*]] = udiv i32 [[SUB270]], 32 -// CHECK1-NEXT: [[MUL272:%.*]] = mul i32 [[MUL269]], [[DIV271]] -// CHECK1-NEXT: [[TMP152:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP153:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB273:%.*]] = sub i32 [[TMP152]], [[TMP153]] -// CHECK1-NEXT: [[SUB274:%.*]] = sub i32 [[SUB273]], 1 -// CHECK1-NEXT: [[ADD275:%.*]] = add i32 [[SUB274]], 1 -// CHECK1-NEXT: [[DIV276:%.*]] = udiv i32 [[ADD275]], 1 -// CHECK1-NEXT: [[MUL277:%.*]] = mul i32 [[MUL272]], [[DIV276]] -// CHECK1-NEXT: [[CONV278:%.*]] = zext i32 [[MUL277]] to i64 -// CHECK1-NEXT: [[MUL279:%.*]] = mul nsw i64 [[DIV264]], [[CONV278]] -// CHECK1-NEXT: [[SUB280:%.*]] = sub nsw i64 [[TMP138]], [[MUL279]] -// CHECK1-NEXT: [[TMP154:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB281:%.*]] = sub i32 [[TMP154]], -31 -// CHECK1-NEXT: [[DIV282:%.*]] = udiv i32 [[SUB281]], 32 -// CHECK1-NEXT: [[MUL283:%.*]] = mul i32 1, [[DIV282]] -// CHECK1-NEXT: [[TMP155:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP156:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB284:%.*]] = sub i32 [[TMP155]], [[TMP156]] -// CHECK1-NEXT: [[SUB285:%.*]] = sub i32 [[SUB284]], 1 -// CHECK1-NEXT: [[ADD286:%.*]] = add i32 [[SUB285]], 1 -// CHECK1-NEXT: [[DIV287:%.*]] = udiv i32 [[ADD286]], 1 -// CHECK1-NEXT: [[MUL288:%.*]] = mul i32 [[MUL283]], [[DIV287]] -// CHECK1-NEXT: [[CONV289:%.*]] = zext i32 [[MUL288]] to i64 -// CHECK1-NEXT: [[DIV290:%.*]] = sdiv i64 [[SUB280]], [[CONV289]] -// CHECK1-NEXT: [[TMP157:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB291:%.*]] = sub i32 [[TMP157]], -31 -// CHECK1-NEXT: [[DIV292:%.*]] = udiv i32 [[SUB291]], 32 -// CHECK1-NEXT: [[MUL293:%.*]] = mul i32 1, [[DIV292]] -// CHECK1-NEXT: [[TMP158:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP159:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB294:%.*]] = sub i32 [[TMP158]], [[TMP159]] -// CHECK1-NEXT: [[SUB295:%.*]] = sub i32 [[SUB294]], 1 -// CHECK1-NEXT: [[ADD296:%.*]] = add i32 [[SUB295]], 1 -// CHECK1-NEXT: [[DIV297:%.*]] = udiv i32 [[ADD296]], 1 -// CHECK1-NEXT: [[MUL298:%.*]] = mul i32 [[MUL293]], [[DIV297]] -// CHECK1-NEXT: [[CONV299:%.*]] = zext i32 [[MUL298]] to i64 -// CHECK1-NEXT: [[MUL300:%.*]] = mul nsw i64 [[DIV290]], [[CONV299]] -// CHECK1-NEXT: [[SUB301:%.*]] = sub nsw i64 [[SUB249]], [[MUL300]] -// CHECK1-NEXT: [[TMP160:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP161:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP162:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK1-NEXT: [[TMP163:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK1-NEXT: [[SUB302:%.*]] = sub i32 [[TMP162]], [[TMP163]] -// CHECK1-NEXT: [[SUB303:%.*]] = sub i32 [[SUB302]], 1 -// CHECK1-NEXT: [[TMP164:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[ADD304:%.*]] = add i32 [[SUB303]], [[TMP164]] -// CHECK1-NEXT: [[TMP165:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[DIV305:%.*]] = udiv i32 [[ADD304]], [[TMP165]] -// CHECK1-NEXT: [[MUL306:%.*]] = mul i32 1, [[DIV305]] -// CHECK1-NEXT: [[TMP166:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB307:%.*]] = sub i32 [[TMP166]], -31 -// CHECK1-NEXT: [[DIV308:%.*]] = udiv i32 [[SUB307]], 32 -// CHECK1-NEXT: [[MUL309:%.*]] = mul i32 [[MUL306]], [[DIV308]] -// CHECK1-NEXT: [[TMP167:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP168:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB310:%.*]] = sub i32 [[TMP167]], [[TMP168]] -// CHECK1-NEXT: [[SUB311:%.*]] = sub i32 [[SUB310]], 1 -// CHECK1-NEXT: [[ADD312:%.*]] = add i32 [[SUB311]], 1 -// CHECK1-NEXT: [[DIV313:%.*]] = udiv i32 [[ADD312]], 1 -// CHECK1-NEXT: [[MUL314:%.*]] = mul i32 [[MUL309]], [[DIV313]] -// CHECK1-NEXT: [[CONV315:%.*]] = zext i32 [[MUL314]] to i64 -// CHECK1-NEXT: [[DIV316:%.*]] = sdiv i64 [[TMP161]], [[CONV315]] -// CHECK1-NEXT: [[TMP169:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK1-NEXT: [[TMP170:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK1-NEXT: [[SUB317:%.*]] = sub i32 [[TMP169]], [[TMP170]] -// CHECK1-NEXT: [[SUB318:%.*]] = sub i32 [[SUB317]], 1 -// CHECK1-NEXT: [[TMP171:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[ADD319:%.*]] = add i32 [[SUB318]], [[TMP171]] -// CHECK1-NEXT: [[TMP172:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[DIV320:%.*]] = udiv i32 [[ADD319]], [[TMP172]] -// CHECK1-NEXT: [[MUL321:%.*]] = mul i32 1, [[DIV320]] -// CHECK1-NEXT: [[TMP173:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB322:%.*]] = sub i32 [[TMP173]], -31 -// CHECK1-NEXT: [[DIV323:%.*]] = udiv i32 [[SUB322]], 32 -// CHECK1-NEXT: [[MUL324:%.*]] = mul i32 [[MUL321]], [[DIV323]] -// CHECK1-NEXT: [[TMP174:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP175:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB325:%.*]] = sub i32 [[TMP174]], [[TMP175]] -// CHECK1-NEXT: [[SUB326:%.*]] = sub i32 [[SUB325]], 1 -// CHECK1-NEXT: [[ADD327:%.*]] = add i32 [[SUB326]], 1 -// CHECK1-NEXT: [[DIV328:%.*]] = udiv i32 [[ADD327]], 1 -// CHECK1-NEXT: [[MUL329:%.*]] = mul i32 [[MUL324]], [[DIV328]] -// CHECK1-NEXT: [[CONV330:%.*]] = zext i32 [[MUL329]] to i64 -// CHECK1-NEXT: [[MUL331:%.*]] = mul nsw i64 [[DIV316]], [[CONV330]] -// CHECK1-NEXT: [[SUB332:%.*]] = sub nsw i64 [[TMP160]], [[MUL331]] -// CHECK1-NEXT: [[TMP176:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP177:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP178:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK1-NEXT: [[TMP179:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK1-NEXT: [[SUB333:%.*]] = sub i32 [[TMP178]], [[TMP179]] -// CHECK1-NEXT: [[SUB334:%.*]] = sub i32 [[SUB333]], 1 -// CHECK1-NEXT: [[TMP180:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[ADD335:%.*]] = add i32 [[SUB334]], [[TMP180]] -// CHECK1-NEXT: [[TMP181:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[DIV336:%.*]] = udiv i32 [[ADD335]], [[TMP181]] -// CHECK1-NEXT: [[MUL337:%.*]] = mul i32 1, [[DIV336]] -// CHECK1-NEXT: [[TMP182:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB338:%.*]] = sub i32 [[TMP182]], -31 -// CHECK1-NEXT: [[DIV339:%.*]] = udiv i32 [[SUB338]], 32 -// CHECK1-NEXT: [[MUL340:%.*]] = mul i32 [[MUL337]], [[DIV339]] -// CHECK1-NEXT: [[TMP183:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP184:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB341:%.*]] = sub i32 [[TMP183]], [[TMP184]] -// CHECK1-NEXT: [[SUB342:%.*]] = sub i32 [[SUB341]], 1 -// CHECK1-NEXT: [[ADD343:%.*]] = add i32 [[SUB342]], 1 -// CHECK1-NEXT: [[DIV344:%.*]] = udiv i32 [[ADD343]], 1 -// CHECK1-NEXT: [[MUL345:%.*]] = mul i32 [[MUL340]], [[DIV344]] -// CHECK1-NEXT: [[CONV346:%.*]] = zext i32 [[MUL345]] to i64 -// CHECK1-NEXT: [[DIV347:%.*]] = sdiv i64 [[TMP177]], [[CONV346]] -// CHECK1-NEXT: [[TMP185:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK1-NEXT: [[TMP186:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK1-NEXT: [[SUB348:%.*]] = sub i32 [[TMP185]], [[TMP186]] -// CHECK1-NEXT: [[SUB349:%.*]] = sub i32 [[SUB348]], 1 -// CHECK1-NEXT: [[TMP187:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[ADD350:%.*]] = add i32 [[SUB349]], [[TMP187]] -// CHECK1-NEXT: [[TMP188:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[DIV351:%.*]] = udiv i32 [[ADD350]], [[TMP188]] -// CHECK1-NEXT: [[MUL352:%.*]] = mul i32 1, [[DIV351]] -// CHECK1-NEXT: [[TMP189:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB353:%.*]] = sub i32 [[TMP189]], -31 -// CHECK1-NEXT: [[DIV354:%.*]] = udiv i32 [[SUB353]], 32 -// CHECK1-NEXT: [[MUL355:%.*]] = mul i32 [[MUL352]], [[DIV354]] -// CHECK1-NEXT: [[TMP190:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP191:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB356:%.*]] = sub i32 [[TMP190]], [[TMP191]] -// CHECK1-NEXT: [[SUB357:%.*]] = sub i32 [[SUB356]], 1 -// CHECK1-NEXT: [[ADD358:%.*]] = add i32 [[SUB357]], 1 -// CHECK1-NEXT: [[DIV359:%.*]] = udiv i32 [[ADD358]], 1 -// CHECK1-NEXT: [[MUL360:%.*]] = mul i32 [[MUL355]], [[DIV359]] -// CHECK1-NEXT: [[CONV361:%.*]] = zext i32 [[MUL360]] to i64 -// CHECK1-NEXT: [[MUL362:%.*]] = mul nsw i64 [[DIV347]], [[CONV361]] -// CHECK1-NEXT: [[SUB363:%.*]] = sub nsw i64 [[TMP176]], [[MUL362]] -// CHECK1-NEXT: [[TMP192:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB364:%.*]] = sub i32 [[TMP192]], -31 -// CHECK1-NEXT: [[DIV365:%.*]] = udiv i32 [[SUB364]], 32 -// CHECK1-NEXT: [[MUL366:%.*]] = mul i32 1, [[DIV365]] -// CHECK1-NEXT: [[TMP193:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP194:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB367:%.*]] = sub i32 [[TMP193]], [[TMP194]] -// CHECK1-NEXT: [[SUB368:%.*]] = sub i32 [[SUB367]], 1 -// CHECK1-NEXT: [[ADD369:%.*]] = add i32 [[SUB368]], 1 -// CHECK1-NEXT: [[DIV370:%.*]] = udiv i32 [[ADD369]], 1 -// CHECK1-NEXT: [[MUL371:%.*]] = mul i32 [[MUL366]], [[DIV370]] -// CHECK1-NEXT: [[CONV372:%.*]] = zext i32 [[MUL371]] to i64 -// CHECK1-NEXT: [[DIV373:%.*]] = sdiv i64 [[SUB363]], [[CONV372]] -// CHECK1-NEXT: [[TMP195:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB374:%.*]] = sub i32 [[TMP195]], -31 -// CHECK1-NEXT: [[DIV375:%.*]] = udiv i32 [[SUB374]], 32 -// CHECK1-NEXT: [[MUL376:%.*]] = mul i32 1, [[DIV375]] -// CHECK1-NEXT: [[TMP196:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP197:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB377:%.*]] = sub i32 [[TMP196]], [[TMP197]] -// CHECK1-NEXT: [[SUB378:%.*]] = sub i32 [[SUB377]], 1 -// CHECK1-NEXT: [[ADD379:%.*]] = add i32 [[SUB378]], 1 -// CHECK1-NEXT: [[DIV380:%.*]] = udiv i32 [[ADD379]], 1 -// CHECK1-NEXT: [[MUL381:%.*]] = mul i32 [[MUL376]], [[DIV380]] -// CHECK1-NEXT: [[CONV382:%.*]] = zext i32 [[MUL381]] to i64 -// CHECK1-NEXT: [[MUL383:%.*]] = mul nsw i64 [[DIV373]], [[CONV382]] -// CHECK1-NEXT: [[SUB384:%.*]] = sub nsw i64 [[SUB332]], [[MUL383]] -// CHECK1-NEXT: [[TMP198:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP199:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB385:%.*]] = sub i32 [[TMP198]], [[TMP199]] -// CHECK1-NEXT: [[SUB386:%.*]] = sub i32 [[SUB385]], 1 -// CHECK1-NEXT: [[ADD387:%.*]] = add i32 [[SUB386]], 1 -// CHECK1-NEXT: [[DIV388:%.*]] = udiv i32 [[ADD387]], 1 -// CHECK1-NEXT: [[MUL389:%.*]] = mul i32 1, [[DIV388]] -// CHECK1-NEXT: [[CONV390:%.*]] = zext i32 [[MUL389]] to i64 -// CHECK1-NEXT: [[DIV391:%.*]] = sdiv i64 [[SUB384]], [[CONV390]] -// CHECK1-NEXT: [[TMP200:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP201:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB392:%.*]] = sub i32 [[TMP200]], [[TMP201]] -// CHECK1-NEXT: [[SUB393:%.*]] = sub i32 [[SUB392]], 1 -// CHECK1-NEXT: [[ADD394:%.*]] = add i32 [[SUB393]], 1 -// CHECK1-NEXT: [[DIV395:%.*]] = udiv i32 [[ADD394]], 1 -// CHECK1-NEXT: [[MUL396:%.*]] = mul i32 1, [[DIV395]] -// CHECK1-NEXT: [[CONV397:%.*]] = zext i32 [[MUL396]] to i64 -// CHECK1-NEXT: [[MUL398:%.*]] = mul nsw i64 [[DIV391]], [[CONV397]] -// CHECK1-NEXT: [[SUB399:%.*]] = sub nsw i64 [[SUB301]], [[MUL398]] -// CHECK1-NEXT: [[MUL400:%.*]] = mul nsw i64 [[SUB399]], 1 -// CHECK1-NEXT: [[ADD401:%.*]] = add nsw i64 [[CONV218]], [[MUL400]] -// CHECK1-NEXT: [[CONV402:%.*]] = trunc i64 [[ADD401]] to i32 -// CHECK1-NEXT: store i32 [[CONV402]], ptr [[DOTTILE_0_IV_K52]], align 4 -// CHECK1-NEXT: [[TMP202:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 4 -// CHECK1-NEXT: [[TMP203:%.*]] = load i32, ptr [[DOTTILE_0_IV_K52]], align 4 -// CHECK1-NEXT: [[TMP204:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4 -// CHECK1-NEXT: [[MUL403:%.*]] = mul i32 [[TMP203]], [[TMP204]] -// CHECK1-NEXT: [[ADD404:%.*]] = add i32 [[TMP202]], [[MUL403]] -// CHECK1-NEXT: store i32 [[ADD404]], ptr [[K]], align 4 -// CHECK1-NEXT: [[TMP205:%.*]] = load i32, ptr [[I49]], align 4 -// CHECK1-NEXT: [[TMP206:%.*]] = load i32, ptr [[J50]], align 4 -// CHECK1-NEXT: [[TMP207:%.*]] = load i32, ptr [[K]], align 4 -// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP205]], i32 noundef [[TMP206]], i32 noundef [[TMP207]]) +// CHECK1-NEXT: [[DIV264:%.*]] = sdiv i64 [[SUB258]], [[CONV263]] +// CHECK1-NEXT: [[TMP140:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB265:%.*]] = sub i32 [[TMP140]], -31 +// CHECK1-NEXT: [[DIV266:%.*]] = udiv i32 [[SUB265]], 32 +// CHECK1-NEXT: [[MUL267:%.*]] = mul i32 1, [[DIV266]] +// CHECK1-NEXT: [[MUL268:%.*]] = mul i32 [[MUL267]], 32 +// CHECK1-NEXT: [[CONV269:%.*]] = zext i32 [[MUL268]] to i64 +// CHECK1-NEXT: [[MUL270:%.*]] = mul nsw i64 [[DIV264]], [[CONV269]] +// CHECK1-NEXT: [[SUB271:%.*]] = sub nsw i64 [[SUB235]], [[MUL270]] +// CHECK1-NEXT: [[DIV272:%.*]] = sdiv i64 [[SUB271]], 32 +// CHECK1-NEXT: [[MUL273:%.*]] = mul nsw i64 [[DIV272]], 32 +// CHECK1-NEXT: [[SUB274:%.*]] = sub nsw i64 [[SUB212]], [[MUL273]] +// CHECK1-NEXT: [[MUL275:%.*]] = mul nsw i64 [[SUB274]], 1 +// CHECK1-NEXT: [[ADD276:%.*]] = add nsw i64 0, [[MUL275]] +// CHECK1-NEXT: [[CONV277:%.*]] = trunc i64 [[ADD276]] to i32 +// CHECK1-NEXT: store i32 [[CONV277]], ptr [[DOTTILE_CNT_0_IV_K38]], align 4 +// CHECK1-NEXT: [[TMP141:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_K37]], align 4 +// CHECK1-NEXT: [[TMP142:%.*]] = load i32, ptr [[DOTTILE_CNT_0_IV_K38]], align 4 +// CHECK1-NEXT: [[ADD278:%.*]] = add i32 [[TMP141]], [[TMP142]] +// CHECK1-NEXT: store i32 [[ADD278]], ptr [[DOTTILE_0_IV_K]], align 4 +// CHECK1-NEXT: [[TMP143:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 4 +// CHECK1-NEXT: [[TMP144:%.*]] = load i32, ptr [[DOTTILE_0_IV_K]], align 4 +// CHECK1-NEXT: [[TMP145:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4 +// CHECK1-NEXT: [[MUL279:%.*]] = mul i32 [[TMP144]], [[TMP145]] +// CHECK1-NEXT: [[ADD280:%.*]] = add i32 [[TMP143]], [[MUL279]] +// CHECK1-NEXT: store i32 [[ADD280]], ptr [[K]], align 4 +// CHECK1-NEXT: [[TMP146:%.*]] = load i32, ptr [[DOTTILE_0_IV_K]], align 4 +// CHECK1-NEXT: [[TMP147:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4 +// CHECK1-NEXT: [[ADD281:%.*]] = add i32 [[TMP147]], 1 +// CHECK1-NEXT: [[CMP282:%.*]] = icmp ult i32 [[TMP146]], [[ADD281]] +// CHECK1-NEXT: br i1 [[CMP282]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] +// CHECK1: if.then: +// CHECK1-NEXT: [[TMP148:%.*]] = load i32, ptr [[I35]], align 4 +// CHECK1-NEXT: [[TMP149:%.*]] = load i32, ptr [[J36]], align 4 +// CHECK1-NEXT: [[TMP150:%.*]] = load i32, ptr [[K]], align 4 +// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP148]], i32 noundef [[TMP149]], i32 noundef [[TMP150]]) +// CHECK1-NEXT: br label [[IF_END]] +// CHECK1: if.end: // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP208:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[ADD405:%.*]] = add nsw i64 [[TMP208]], 1 -// CHECK1-NEXT: store i64 [[ADD405]], ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[TMP151:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[ADD283:%.*]] = add nsw i64 [[TMP151]], 1 +// CHECK1-NEXT: store i64 [[ADD283]], ptr [[DOTOMP_IV]], align 8 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -1520,22 +1342,21 @@ extern "C" void foo10() { // CHECK1-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTNEW_STEP10:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTTILE_0_IV_K:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_14:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTCAPTURE_EXPR_16:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i64, align 8 +// CHECK1-NEXT: [[DOTCAPTURE_EXPR_16:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTFLOOR_0_IV_K:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTTILE_0_IV_K:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTTILE_CNT_0_IV_K:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[I49:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[J50:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTFLOOR_0_IV_K51:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTTILE_0_IV_K52:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[I35:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[J36:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTFLOOR_0_IV_K37:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTTILE_CNT_0_IV_K38:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) // CHECK1-NEXT: store i32 [[START]], ptr [[START_ADDR]], align 4 // CHECK1-NEXT: store i32 [[END]], ptr [[END_ADDR]], align 4 @@ -1573,630 +1394,452 @@ extern "C" void foo10() { // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4 // CHECK1-NEXT: [[ADD15:%.*]] = add i32 [[TMP15]], 1 // CHECK1-NEXT: store i32 [[ADD15]], ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[_TMP2]], align 4 -// CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4 -// CHECK1-NEXT: [[ADD18:%.*]] = add i32 [[TMP17]], 1 -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[_TMP2]], align 4 -// CHECK1-NEXT: [[ADD19:%.*]] = add i32 [[TMP18]], 64 -// CHECK1-NEXT: [[CMP:%.*]] = icmp ult i32 [[ADD18]], [[ADD19]] -// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK1: cond.true: -// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4 -// CHECK1-NEXT: [[ADD20:%.*]] = add i32 [[TMP19]], 1 -// CHECK1-NEXT: br label [[COND_END:%.*]] -// CHECK1: cond.false: -// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[_TMP2]], align 4 -// CHECK1-NEXT: [[ADD21:%.*]] = add i32 [[TMP20]], 64 -// CHECK1-NEXT: br label [[COND_END]] -// CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[ADD20]], [[COND_TRUE]] ], [ [[ADD21]], [[COND_FALSE]] ] -// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK1-NEXT: [[SUB23:%.*]] = sub i32 [[TMP21]], [[TMP22]] -// CHECK1-NEXT: [[SUB24:%.*]] = sub i32 [[SUB23]], 1 -// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 -// CHECK1-NEXT: [[ADD25:%.*]] = add i32 [[SUB24]], [[TMP23]] -// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 -// CHECK1-NEXT: [[DIV26:%.*]] = udiv i32 [[ADD25]], [[TMP24]] -// CHECK1-NEXT: [[CONV:%.*]] = zext i32 [[DIV26]] to i64 -// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK1-NEXT: [[SUB17:%.*]] = sub i32 [[TMP16]], [[TMP17]] +// CHECK1-NEXT: [[SUB18:%.*]] = sub i32 [[SUB17]], 1 +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 +// CHECK1-NEXT: [[ADD19:%.*]] = add i32 [[SUB18]], [[TMP18]] +// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 +// CHECK1-NEXT: [[DIV20:%.*]] = udiv i32 [[ADD19]], [[TMP19]] +// CHECK1-NEXT: [[CONV:%.*]] = zext i32 [[DIV20]] to i64 +// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK1-NEXT: [[SUB21:%.*]] = sub i32 [[TMP20]], [[TMP21]] +// CHECK1-NEXT: [[SUB22:%.*]] = sub i32 [[SUB21]], 1 +// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[ADD23:%.*]] = add i32 [[SUB22]], [[TMP22]] +// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[DIV24:%.*]] = udiv i32 [[ADD23]], [[TMP23]] +// CHECK1-NEXT: [[CONV25:%.*]] = zext i32 [[DIV24]] to i64 +// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV25]] +// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB26:%.*]] = sub i32 [[TMP24]], -63 +// CHECK1-NEXT: [[DIV27:%.*]] = udiv i32 [[SUB26]], 64 +// CHECK1-NEXT: [[CONV28:%.*]] = zext i32 [[DIV27]] to i64 +// CHECK1-NEXT: [[MUL29:%.*]] = mul nsw i64 [[MUL]], [[CONV28]] +// CHECK1-NEXT: [[MUL30:%.*]] = mul nsw i64 [[MUL29]], 64 +// CHECK1-NEXT: [[SUB31:%.*]] = sub nsw i64 [[MUL30]], 1 +// CHECK1-NEXT: store i64 [[SUB31]], ptr [[DOTCAPTURE_EXPR_16]], align 8 +// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK1-NEXT: store i32 [[TMP25]], ptr [[I]], align 4 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK1-NEXT: [[SUB27:%.*]] = sub i32 [[TMP25]], [[TMP26]] -// CHECK1-NEXT: [[SUB28:%.*]] = sub i32 [[SUB27]], 1 -// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[ADD29:%.*]] = add i32 [[SUB28]], [[TMP27]] -// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[DIV30:%.*]] = udiv i32 [[ADD29]], [[TMP28]] -// CHECK1-NEXT: [[CONV31:%.*]] = zext i32 [[DIV30]] to i64 -// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV31]] -// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB32:%.*]] = sub i32 [[TMP29]], -63 -// CHECK1-NEXT: [[DIV33:%.*]] = udiv i32 [[SUB32]], 64 -// CHECK1-NEXT: [[CONV34:%.*]] = zext i32 [[DIV33]] to i64 -// CHECK1-NEXT: [[MUL35:%.*]] = mul nsw i64 [[MUL]], [[CONV34]] -// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB36:%.*]] = sub i32 [[TMP30]], [[TMP31]] -// CHECK1-NEXT: [[SUB37:%.*]] = sub i32 [[SUB36]], 1 -// CHECK1-NEXT: [[ADD38:%.*]] = add i32 [[SUB37]], 1 -// CHECK1-NEXT: [[DIV39:%.*]] = udiv i32 [[ADD38]], 1 -// CHECK1-NEXT: [[CONV40:%.*]] = zext i32 [[DIV39]] to i64 -// CHECK1-NEXT: [[MUL41:%.*]] = mul nsw i64 [[MUL35]], [[CONV40]] -// CHECK1-NEXT: [[SUB42:%.*]] = sub nsw i64 [[MUL41]], 1 -// CHECK1-NEXT: store i64 [[SUB42]], ptr [[DOTCAPTURE_EXPR_22]], align 8 -// CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK1-NEXT: store i32 [[TMP32]], ptr [[I]], align 4 -// CHECK1-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK1-NEXT: store i32 [[TMP33]], ptr [[J]], align 4 +// CHECK1-NEXT: store i32 [[TMP26]], ptr [[J]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_K]], align 4 -// CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: store i32 [[TMP34]], ptr [[DOTTILE_0_IV_K]], align 4 -// CHECK1-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK1-NEXT: [[CMP43:%.*]] = icmp slt i32 [[TMP35]], [[TMP36]] -// CHECK1-NEXT: br i1 [[CMP43]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK1-NEXT: store i32 0, ptr [[DOTTILE_CNT_0_IV_K]], align 4 +// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP27]], [[TMP28]] +// CHECK1-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK1: land.lhs.true: -// CHECK1-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK1-NEXT: [[CMP44:%.*]] = icmp slt i32 [[TMP37]], [[TMP38]] -// CHECK1-NEXT: br i1 [[CMP44]], label [[LAND_LHS_TRUE45:%.*]], label [[OMP_PRECOND_END]] -// CHECK1: land.lhs.true45: -// CHECK1-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[CMP46:%.*]] = icmp ult i32 0, [[TMP39]] -// CHECK1-NEXT: br i1 [[CMP46]], label [[LAND_LHS_TRUE47:%.*]], label [[OMP_PRECOND_END]] -// CHECK1: land.lhs.true47: -// CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[CMP48:%.*]] = icmp ult i32 [[TMP40]], [[TMP41]] -// CHECK1-NEXT: br i1 [[CMP48]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK1-NEXT: [[CMP32:%.*]] = icmp slt i32 [[TMP29]], [[TMP30]] +// CHECK1-NEXT: br i1 [[CMP32]], label [[LAND_LHS_TRUE33:%.*]], label [[OMP_PRECOND_END]] +// CHECK1: land.lhs.true33: +// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[CMP34:%.*]] = icmp ult i32 0, [[TMP31]] +// CHECK1-NEXT: br i1 [[CMP34]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] // CHECK1: omp.precond.then: // CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 -// CHECK1-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8 -// CHECK1-NEXT: store i64 [[TMP42]], ptr [[DOTOMP_UB]], align 8 +// CHECK1-NEXT: [[TMP32:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_16]], align 8 +// CHECK1-NEXT: store i64 [[TMP32]], ptr [[DOTOMP_UB]], align 8 // CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK1-NEXT: [[TMP43:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 -// CHECK1-NEXT: [[TMP44:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8 -// CHECK1-NEXT: [[CMP53:%.*]] = icmp sgt i64 [[TMP43]], [[TMP44]] -// CHECK1-NEXT: br i1 [[CMP53]], label [[COND_TRUE54:%.*]], label [[COND_FALSE55:%.*]] -// CHECK1: cond.true54: -// CHECK1-NEXT: [[TMP45:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8 -// CHECK1-NEXT: br label [[COND_END56:%.*]] -// CHECK1: cond.false55: -// CHECK1-NEXT: [[TMP46:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 -// CHECK1-NEXT: br label [[COND_END56]] -// CHECK1: cond.end56: -// CHECK1-NEXT: [[COND57:%.*]] = phi i64 [ [[TMP45]], [[COND_TRUE54]] ], [ [[TMP46]], [[COND_FALSE55]] ] -// CHECK1-NEXT: store i64 [[COND57]], ptr [[DOTOMP_UB]], align 8 -// CHECK1-NEXT: [[TMP47:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 -// CHECK1-NEXT: store i64 [[TMP47]], ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[TMP33:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 +// CHECK1-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_16]], align 8 +// CHECK1-NEXT: [[CMP39:%.*]] = icmp sgt i64 [[TMP33]], [[TMP34]] +// CHECK1-NEXT: br i1 [[CMP39]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK1: cond.true: +// CHECK1-NEXT: [[TMP35:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_16]], align 8 +// CHECK1-NEXT: br label [[COND_END:%.*]] +// CHECK1: cond.false: +// CHECK1-NEXT: [[TMP36:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 +// CHECK1-NEXT: br label [[COND_END]] +// CHECK1: cond.end: +// CHECK1-NEXT: [[COND:%.*]] = phi i64 [ [[TMP35]], [[COND_TRUE]] ], [ [[TMP36]], [[COND_FALSE]] ] +// CHECK1-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 +// CHECK1-NEXT: [[TMP37:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 +// CHECK1-NEXT: store i64 [[TMP37]], ptr [[DOTOMP_IV]], align 8 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP48:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP49:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 -// CHECK1-NEXT: [[CMP58:%.*]] = icmp sle i64 [[TMP48]], [[TMP49]] -// CHECK1-NEXT: br i1 [[CMP58]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK1-NEXT: [[TMP38:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 +// CHECK1-NEXT: [[CMP40:%.*]] = icmp sle i64 [[TMP38]], [[TMP39]] +// CHECK1-NEXT: br i1 [[CMP40]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK1-NEXT: [[CONV59:%.*]] = sext i32 [[TMP50]] to i64 -// CHECK1-NEXT: [[TMP51:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP52:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK1-NEXT: [[TMP53:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK1-NEXT: [[SUB60:%.*]] = sub i32 [[TMP52]], [[TMP53]] -// CHECK1-NEXT: [[SUB61:%.*]] = sub i32 [[SUB60]], 1 +// CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK1-NEXT: [[CONV41:%.*]] = sext i32 [[TMP40]] to i64 +// CHECK1-NEXT: [[TMP41:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK1-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK1-NEXT: [[SUB42:%.*]] = sub i32 [[TMP42]], [[TMP43]] +// CHECK1-NEXT: [[SUB43:%.*]] = sub i32 [[SUB42]], 1 +// CHECK1-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[ADD44:%.*]] = add i32 [[SUB43]], [[TMP44]] +// CHECK1-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[DIV45:%.*]] = udiv i32 [[ADD44]], [[TMP45]] +// CHECK1-NEXT: [[MUL46:%.*]] = mul i32 1, [[DIV45]] +// CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB47:%.*]] = sub i32 [[TMP46]], -63 +// CHECK1-NEXT: [[DIV48:%.*]] = udiv i32 [[SUB47]], 64 +// CHECK1-NEXT: [[MUL49:%.*]] = mul i32 [[MUL46]], [[DIV48]] +// CHECK1-NEXT: [[MUL50:%.*]] = mul i32 [[MUL49]], 64 +// CHECK1-NEXT: [[CONV51:%.*]] = zext i32 [[MUL50]] to i64 +// CHECK1-NEXT: [[DIV52:%.*]] = sdiv i64 [[TMP41]], [[CONV51]] +// CHECK1-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 +// CHECK1-NEXT: [[CONV53:%.*]] = sext i32 [[TMP47]] to i64 +// CHECK1-NEXT: [[MUL54:%.*]] = mul nsw i64 [[DIV52]], [[CONV53]] +// CHECK1-NEXT: [[ADD55:%.*]] = add nsw i64 [[CONV41]], [[MUL54]] +// CHECK1-NEXT: [[CONV56:%.*]] = trunc i64 [[ADD55]] to i32 +// CHECK1-NEXT: store i32 [[CONV56]], ptr [[I35]], align 4 +// CHECK1-NEXT: [[TMP48:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK1-NEXT: [[CONV57:%.*]] = sext i32 [[TMP48]] to i64 +// CHECK1-NEXT: [[TMP49:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[TMP50:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[TMP51:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK1-NEXT: [[TMP52:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK1-NEXT: [[SUB58:%.*]] = sub i32 [[TMP51]], [[TMP52]] +// CHECK1-NEXT: [[SUB59:%.*]] = sub i32 [[SUB58]], 1 +// CHECK1-NEXT: [[TMP53:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[ADD60:%.*]] = add i32 [[SUB59]], [[TMP53]] // CHECK1-NEXT: [[TMP54:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[ADD62:%.*]] = add i32 [[SUB61]], [[TMP54]] -// CHECK1-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[DIV63:%.*]] = udiv i32 [[ADD62]], [[TMP55]] -// CHECK1-NEXT: [[MUL64:%.*]] = mul i32 1, [[DIV63]] -// CHECK1-NEXT: [[TMP56:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB65:%.*]] = sub i32 [[TMP56]], -63 -// CHECK1-NEXT: [[DIV66:%.*]] = udiv i32 [[SUB65]], 64 -// CHECK1-NEXT: [[MUL67:%.*]] = mul i32 [[MUL64]], [[DIV66]] -// CHECK1-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB68:%.*]] = sub i32 [[TMP57]], [[TMP58]] -// CHECK1-NEXT: [[SUB69:%.*]] = sub i32 [[SUB68]], 1 -// CHECK1-NEXT: [[ADD70:%.*]] = add i32 [[SUB69]], 1 -// CHECK1-NEXT: [[DIV71:%.*]] = udiv i32 [[ADD70]], 1 -// CHECK1-NEXT: [[MUL72:%.*]] = mul i32 [[MUL67]], [[DIV71]] -// CHECK1-NEXT: [[CONV73:%.*]] = zext i32 [[MUL72]] to i64 -// CHECK1-NEXT: [[DIV74:%.*]] = sdiv i64 [[TMP51]], [[CONV73]] -// CHECK1-NEXT: [[TMP59:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 -// CHECK1-NEXT: [[CONV75:%.*]] = sext i32 [[TMP59]] to i64 -// CHECK1-NEXT: [[MUL76:%.*]] = mul nsw i64 [[DIV74]], [[CONV75]] -// CHECK1-NEXT: [[ADD77:%.*]] = add nsw i64 [[CONV59]], [[MUL76]] -// CHECK1-NEXT: [[CONV78:%.*]] = trunc i64 [[ADD77]] to i32 -// CHECK1-NEXT: store i32 [[CONV78]], ptr [[I49]], align 4 -// CHECK1-NEXT: [[TMP60:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK1-NEXT: [[CONV79:%.*]] = sext i32 [[TMP60]] to i64 -// CHECK1-NEXT: [[TMP61:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP62:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP63:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK1-NEXT: [[TMP64:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK1-NEXT: [[SUB80:%.*]] = sub i32 [[TMP63]], [[TMP64]] -// CHECK1-NEXT: [[SUB81:%.*]] = sub i32 [[SUB80]], 1 -// CHECK1-NEXT: [[TMP65:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[ADD82:%.*]] = add i32 [[SUB81]], [[TMP65]] -// CHECK1-NEXT: [[TMP66:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[DIV83:%.*]] = udiv i32 [[ADD82]], [[TMP66]] -// CHECK1-NEXT: [[MUL84:%.*]] = mul i32 1, [[DIV83]] -// CHECK1-NEXT: [[TMP67:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB85:%.*]] = sub i32 [[TMP67]], -63 -// CHECK1-NEXT: [[DIV86:%.*]] = udiv i32 [[SUB85]], 64 -// CHECK1-NEXT: [[MUL87:%.*]] = mul i32 [[MUL84]], [[DIV86]] -// CHECK1-NEXT: [[TMP68:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP69:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB88:%.*]] = sub i32 [[TMP68]], [[TMP69]] -// CHECK1-NEXT: [[SUB89:%.*]] = sub i32 [[SUB88]], 1 -// CHECK1-NEXT: [[ADD90:%.*]] = add i32 [[SUB89]], 1 -// CHECK1-NEXT: [[DIV91:%.*]] = udiv i32 [[ADD90]], 1 -// CHECK1-NEXT: [[MUL92:%.*]] = mul i32 [[MUL87]], [[DIV91]] -// CHECK1-NEXT: [[CONV93:%.*]] = zext i32 [[MUL92]] to i64 -// CHECK1-NEXT: [[DIV94:%.*]] = sdiv i64 [[TMP62]], [[CONV93]] +// CHECK1-NEXT: [[DIV61:%.*]] = udiv i32 [[ADD60]], [[TMP54]] +// CHECK1-NEXT: [[MUL62:%.*]] = mul i32 1, [[DIV61]] +// CHECK1-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB63:%.*]] = sub i32 [[TMP55]], -63 +// CHECK1-NEXT: [[DIV64:%.*]] = udiv i32 [[SUB63]], 64 +// CHECK1-NEXT: [[MUL65:%.*]] = mul i32 [[MUL62]], [[DIV64]] +// CHECK1-NEXT: [[MUL66:%.*]] = mul i32 [[MUL65]], 64 +// CHECK1-NEXT: [[CONV67:%.*]] = zext i32 [[MUL66]] to i64 +// CHECK1-NEXT: [[DIV68:%.*]] = sdiv i64 [[TMP50]], [[CONV67]] +// CHECK1-NEXT: [[TMP56:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK1-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK1-NEXT: [[SUB69:%.*]] = sub i32 [[TMP56]], [[TMP57]] +// CHECK1-NEXT: [[SUB70:%.*]] = sub i32 [[SUB69]], 1 +// CHECK1-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[ADD71:%.*]] = add i32 [[SUB70]], [[TMP58]] +// CHECK1-NEXT: [[TMP59:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[DIV72:%.*]] = udiv i32 [[ADD71]], [[TMP59]] +// CHECK1-NEXT: [[MUL73:%.*]] = mul i32 1, [[DIV72]] +// CHECK1-NEXT: [[TMP60:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB74:%.*]] = sub i32 [[TMP60]], -63 +// CHECK1-NEXT: [[DIV75:%.*]] = udiv i32 [[SUB74]], 64 +// CHECK1-NEXT: [[MUL76:%.*]] = mul i32 [[MUL73]], [[DIV75]] +// CHECK1-NEXT: [[MUL77:%.*]] = mul i32 [[MUL76]], 64 +// CHECK1-NEXT: [[CONV78:%.*]] = zext i32 [[MUL77]] to i64 +// CHECK1-NEXT: [[MUL79:%.*]] = mul nsw i64 [[DIV68]], [[CONV78]] +// CHECK1-NEXT: [[SUB80:%.*]] = sub nsw i64 [[TMP49]], [[MUL79]] +// CHECK1-NEXT: [[TMP61:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB81:%.*]] = sub i32 [[TMP61]], -63 +// CHECK1-NEXT: [[DIV82:%.*]] = udiv i32 [[SUB81]], 64 +// CHECK1-NEXT: [[MUL83:%.*]] = mul i32 1, [[DIV82]] +// CHECK1-NEXT: [[MUL84:%.*]] = mul i32 [[MUL83]], 64 +// CHECK1-NEXT: [[CONV85:%.*]] = zext i32 [[MUL84]] to i64 +// CHECK1-NEXT: [[DIV86:%.*]] = sdiv i64 [[SUB80]], [[CONV85]] +// CHECK1-NEXT: [[TMP62:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[CONV87:%.*]] = sext i32 [[TMP62]] to i64 +// CHECK1-NEXT: [[MUL88:%.*]] = mul nsw i64 [[DIV86]], [[CONV87]] +// CHECK1-NEXT: [[ADD89:%.*]] = add nsw i64 [[CONV57]], [[MUL88]] +// CHECK1-NEXT: [[CONV90:%.*]] = trunc i64 [[ADD89]] to i32 +// CHECK1-NEXT: store i32 [[CONV90]], ptr [[J36]], align 4 +// CHECK1-NEXT: [[TMP63:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[TMP64:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[TMP65:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK1-NEXT: [[TMP66:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK1-NEXT: [[SUB91:%.*]] = sub i32 [[TMP65]], [[TMP66]] +// CHECK1-NEXT: [[SUB92:%.*]] = sub i32 [[SUB91]], 1 +// CHECK1-NEXT: [[TMP67:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[ADD93:%.*]] = add i32 [[SUB92]], [[TMP67]] +// CHECK1-NEXT: [[TMP68:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[DIV94:%.*]] = udiv i32 [[ADD93]], [[TMP68]] +// CHECK1-NEXT: [[MUL95:%.*]] = mul i32 1, [[DIV94]] +// CHECK1-NEXT: [[TMP69:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB96:%.*]] = sub i32 [[TMP69]], -63 +// CHECK1-NEXT: [[DIV97:%.*]] = udiv i32 [[SUB96]], 64 +// CHECK1-NEXT: [[MUL98:%.*]] = mul i32 [[MUL95]], [[DIV97]] +// CHECK1-NEXT: [[MUL99:%.*]] = mul i32 [[MUL98]], 64 +// CHECK1-NEXT: [[CONV100:%.*]] = zext i32 [[MUL99]] to i64 +// CHECK1-NEXT: [[DIV101:%.*]] = sdiv i64 [[TMP64]], [[CONV100]] // CHECK1-NEXT: [[TMP70:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 // CHECK1-NEXT: [[TMP71:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK1-NEXT: [[SUB95:%.*]] = sub i32 [[TMP70]], [[TMP71]] -// CHECK1-NEXT: [[SUB96:%.*]] = sub i32 [[SUB95]], 1 +// CHECK1-NEXT: [[SUB102:%.*]] = sub i32 [[TMP70]], [[TMP71]] +// CHECK1-NEXT: [[SUB103:%.*]] = sub i32 [[SUB102]], 1 // CHECK1-NEXT: [[TMP72:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[ADD97:%.*]] = add i32 [[SUB96]], [[TMP72]] +// CHECK1-NEXT: [[ADD104:%.*]] = add i32 [[SUB103]], [[TMP72]] // CHECK1-NEXT: [[TMP73:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[DIV98:%.*]] = udiv i32 [[ADD97]], [[TMP73]] -// CHECK1-NEXT: [[MUL99:%.*]] = mul i32 1, [[DIV98]] +// CHECK1-NEXT: [[DIV105:%.*]] = udiv i32 [[ADD104]], [[TMP73]] +// CHECK1-NEXT: [[MUL106:%.*]] = mul i32 1, [[DIV105]] // CHECK1-NEXT: [[TMP74:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB100:%.*]] = sub i32 [[TMP74]], -63 -// CHECK1-NEXT: [[DIV101:%.*]] = udiv i32 [[SUB100]], 64 -// CHECK1-NEXT: [[MUL102:%.*]] = mul i32 [[MUL99]], [[DIV101]] -// CHECK1-NEXT: [[TMP75:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP76:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB103:%.*]] = sub i32 [[TMP75]], [[TMP76]] -// CHECK1-NEXT: [[SUB104:%.*]] = sub i32 [[SUB103]], 1 -// CHECK1-NEXT: [[ADD105:%.*]] = add i32 [[SUB104]], 1 -// CHECK1-NEXT: [[DIV106:%.*]] = udiv i32 [[ADD105]], 1 -// CHECK1-NEXT: [[MUL107:%.*]] = mul i32 [[MUL102]], [[DIV106]] -// CHECK1-NEXT: [[CONV108:%.*]] = zext i32 [[MUL107]] to i64 -// CHECK1-NEXT: [[MUL109:%.*]] = mul nsw i64 [[DIV94]], [[CONV108]] -// CHECK1-NEXT: [[SUB110:%.*]] = sub nsw i64 [[TMP61]], [[MUL109]] -// CHECK1-NEXT: [[TMP77:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB111:%.*]] = sub i32 [[TMP77]], -63 -// CHECK1-NEXT: [[DIV112:%.*]] = udiv i32 [[SUB111]], 64 -// CHECK1-NEXT: [[MUL113:%.*]] = mul i32 1, [[DIV112]] -// CHECK1-NEXT: [[TMP78:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP79:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB114:%.*]] = sub i32 [[TMP78]], [[TMP79]] +// CHECK1-NEXT: [[SUB107:%.*]] = sub i32 [[TMP74]], -63 +// CHECK1-NEXT: [[DIV108:%.*]] = udiv i32 [[SUB107]], 64 +// CHECK1-NEXT: [[MUL109:%.*]] = mul i32 [[MUL106]], [[DIV108]] +// CHECK1-NEXT: [[MUL110:%.*]] = mul i32 [[MUL109]], 64 +// CHECK1-NEXT: [[CONV111:%.*]] = zext i32 [[MUL110]] to i64 +// CHECK1-NEXT: [[MUL112:%.*]] = mul nsw i64 [[DIV101]], [[CONV111]] +// CHECK1-NEXT: [[SUB113:%.*]] = sub nsw i64 [[TMP63]], [[MUL112]] +// CHECK1-NEXT: [[TMP75:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[TMP76:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[TMP77:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK1-NEXT: [[TMP78:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK1-NEXT: [[SUB114:%.*]] = sub i32 [[TMP77]], [[TMP78]] // CHECK1-NEXT: [[SUB115:%.*]] = sub i32 [[SUB114]], 1 -// CHECK1-NEXT: [[ADD116:%.*]] = add i32 [[SUB115]], 1 -// CHECK1-NEXT: [[DIV117:%.*]] = udiv i32 [[ADD116]], 1 -// CHECK1-NEXT: [[MUL118:%.*]] = mul i32 [[MUL113]], [[DIV117]] -// CHECK1-NEXT: [[CONV119:%.*]] = zext i32 [[MUL118]] to i64 -// CHECK1-NEXT: [[DIV120:%.*]] = sdiv i64 [[SUB110]], [[CONV119]] +// CHECK1-NEXT: [[TMP79:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[ADD116:%.*]] = add i32 [[SUB115]], [[TMP79]] // CHECK1-NEXT: [[TMP80:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[CONV121:%.*]] = sext i32 [[TMP80]] to i64 -// CHECK1-NEXT: [[MUL122:%.*]] = mul nsw i64 [[DIV120]], [[CONV121]] -// CHECK1-NEXT: [[ADD123:%.*]] = add nsw i64 [[CONV79]], [[MUL122]] -// CHECK1-NEXT: [[CONV124:%.*]] = trunc i64 [[ADD123]] to i32 -// CHECK1-NEXT: store i32 [[CONV124]], ptr [[J50]], align 4 -// CHECK1-NEXT: [[TMP81:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP82:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP83:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK1-NEXT: [[TMP84:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK1-NEXT: [[SUB125:%.*]] = sub i32 [[TMP83]], [[TMP84]] +// CHECK1-NEXT: [[DIV117:%.*]] = udiv i32 [[ADD116]], [[TMP80]] +// CHECK1-NEXT: [[MUL118:%.*]] = mul i32 1, [[DIV117]] +// CHECK1-NEXT: [[TMP81:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB119:%.*]] = sub i32 [[TMP81]], -63 +// CHECK1-NEXT: [[DIV120:%.*]] = udiv i32 [[SUB119]], 64 +// CHECK1-NEXT: [[MUL121:%.*]] = mul i32 [[MUL118]], [[DIV120]] +// CHECK1-NEXT: [[MUL122:%.*]] = mul i32 [[MUL121]], 64 +// CHECK1-NEXT: [[CONV123:%.*]] = zext i32 [[MUL122]] to i64 +// CHECK1-NEXT: [[DIV124:%.*]] = sdiv i64 [[TMP76]], [[CONV123]] +// CHECK1-NEXT: [[TMP82:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK1-NEXT: [[TMP83:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK1-NEXT: [[SUB125:%.*]] = sub i32 [[TMP82]], [[TMP83]] // CHECK1-NEXT: [[SUB126:%.*]] = sub i32 [[SUB125]], 1 +// CHECK1-NEXT: [[TMP84:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[ADD127:%.*]] = add i32 [[SUB126]], [[TMP84]] // CHECK1-NEXT: [[TMP85:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[ADD127:%.*]] = add i32 [[SUB126]], [[TMP85]] -// CHECK1-NEXT: [[TMP86:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[DIV128:%.*]] = udiv i32 [[ADD127]], [[TMP86]] +// CHECK1-NEXT: [[DIV128:%.*]] = udiv i32 [[ADD127]], [[TMP85]] // CHECK1-NEXT: [[MUL129:%.*]] = mul i32 1, [[DIV128]] -// CHECK1-NEXT: [[TMP87:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB130:%.*]] = sub i32 [[TMP87]], -63 +// CHECK1-NEXT: [[TMP86:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB130:%.*]] = sub i32 [[TMP86]], -63 // CHECK1-NEXT: [[DIV131:%.*]] = udiv i32 [[SUB130]], 64 // CHECK1-NEXT: [[MUL132:%.*]] = mul i32 [[MUL129]], [[DIV131]] -// CHECK1-NEXT: [[TMP88:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP89:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB133:%.*]] = sub i32 [[TMP88]], [[TMP89]] -// CHECK1-NEXT: [[SUB134:%.*]] = sub i32 [[SUB133]], 1 -// CHECK1-NEXT: [[ADD135:%.*]] = add i32 [[SUB134]], 1 -// CHECK1-NEXT: [[DIV136:%.*]] = udiv i32 [[ADD135]], 1 -// CHECK1-NEXT: [[MUL137:%.*]] = mul i32 [[MUL132]], [[DIV136]] -// CHECK1-NEXT: [[CONV138:%.*]] = zext i32 [[MUL137]] to i64 -// CHECK1-NEXT: [[DIV139:%.*]] = sdiv i64 [[TMP82]], [[CONV138]] -// CHECK1-NEXT: [[TMP90:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK1-NEXT: [[TMP91:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK1-NEXT: [[SUB140:%.*]] = sub i32 [[TMP90]], [[TMP91]] -// CHECK1-NEXT: [[SUB141:%.*]] = sub i32 [[SUB140]], 1 -// CHECK1-NEXT: [[TMP92:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[ADD142:%.*]] = add i32 [[SUB141]], [[TMP92]] +// CHECK1-NEXT: [[MUL133:%.*]] = mul i32 [[MUL132]], 64 +// CHECK1-NEXT: [[CONV134:%.*]] = zext i32 [[MUL133]] to i64 +// CHECK1-NEXT: [[MUL135:%.*]] = mul nsw i64 [[DIV124]], [[CONV134]] +// CHECK1-NEXT: [[SUB136:%.*]] = sub nsw i64 [[TMP75]], [[MUL135]] +// CHECK1-NEXT: [[TMP87:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB137:%.*]] = sub i32 [[TMP87]], -63 +// CHECK1-NEXT: [[DIV138:%.*]] = udiv i32 [[SUB137]], 64 +// CHECK1-NEXT: [[MUL139:%.*]] = mul i32 1, [[DIV138]] +// CHECK1-NEXT: [[MUL140:%.*]] = mul i32 [[MUL139]], 64 +// CHECK1-NEXT: [[CONV141:%.*]] = zext i32 [[MUL140]] to i64 +// CHECK1-NEXT: [[DIV142:%.*]] = sdiv i64 [[SUB136]], [[CONV141]] +// CHECK1-NEXT: [[TMP88:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB143:%.*]] = sub i32 [[TMP88]], -63 +// CHECK1-NEXT: [[DIV144:%.*]] = udiv i32 [[SUB143]], 64 +// CHECK1-NEXT: [[MUL145:%.*]] = mul i32 1, [[DIV144]] +// CHECK1-NEXT: [[MUL146:%.*]] = mul i32 [[MUL145]], 64 +// CHECK1-NEXT: [[CONV147:%.*]] = zext i32 [[MUL146]] to i64 +// CHECK1-NEXT: [[MUL148:%.*]] = mul nsw i64 [[DIV142]], [[CONV147]] +// CHECK1-NEXT: [[SUB149:%.*]] = sub nsw i64 [[SUB113]], [[MUL148]] +// CHECK1-NEXT: [[DIV150:%.*]] = sdiv i64 [[SUB149]], 64 +// CHECK1-NEXT: [[MUL151:%.*]] = mul nsw i64 [[DIV150]], 64 +// CHECK1-NEXT: [[ADD152:%.*]] = add nsw i64 0, [[MUL151]] +// CHECK1-NEXT: [[CONV153:%.*]] = trunc i64 [[ADD152]] to i32 +// CHECK1-NEXT: store i32 [[CONV153]], ptr [[DOTFLOOR_0_IV_K37]], align 4 +// CHECK1-NEXT: [[TMP89:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[TMP90:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[TMP91:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK1-NEXT: [[TMP92:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK1-NEXT: [[SUB154:%.*]] = sub i32 [[TMP91]], [[TMP92]] +// CHECK1-NEXT: [[SUB155:%.*]] = sub i32 [[SUB154]], 1 // CHECK1-NEXT: [[TMP93:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[DIV143:%.*]] = udiv i32 [[ADD142]], [[TMP93]] -// CHECK1-NEXT: [[MUL144:%.*]] = mul i32 1, [[DIV143]] -// CHECK1-NEXT: [[TMP94:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB145:%.*]] = sub i32 [[TMP94]], -63 -// CHECK1-NEXT: [[DIV146:%.*]] = udiv i32 [[SUB145]], 64 -// CHECK1-NEXT: [[MUL147:%.*]] = mul i32 [[MUL144]], [[DIV146]] -// CHECK1-NEXT: [[TMP95:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP96:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB148:%.*]] = sub i32 [[TMP95]], [[TMP96]] -// CHECK1-NEXT: [[SUB149:%.*]] = sub i32 [[SUB148]], 1 -// CHECK1-NEXT: [[ADD150:%.*]] = add i32 [[SUB149]], 1 -// CHECK1-NEXT: [[DIV151:%.*]] = udiv i32 [[ADD150]], 1 -// CHECK1-NEXT: [[MUL152:%.*]] = mul i32 [[MUL147]], [[DIV151]] -// CHECK1-NEXT: [[CONV153:%.*]] = zext i32 [[MUL152]] to i64 -// CHECK1-NEXT: [[MUL154:%.*]] = mul nsw i64 [[DIV139]], [[CONV153]] -// CHECK1-NEXT: [[SUB155:%.*]] = sub nsw i64 [[TMP81]], [[MUL154]] -// CHECK1-NEXT: [[TMP97:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP98:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP99:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK1-NEXT: [[TMP100:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK1-NEXT: [[SUB156:%.*]] = sub i32 [[TMP99]], [[TMP100]] -// CHECK1-NEXT: [[SUB157:%.*]] = sub i32 [[SUB156]], 1 -// CHECK1-NEXT: [[TMP101:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[ADD158:%.*]] = add i32 [[SUB157]], [[TMP101]] -// CHECK1-NEXT: [[TMP102:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[DIV159:%.*]] = udiv i32 [[ADD158]], [[TMP102]] -// CHECK1-NEXT: [[MUL160:%.*]] = mul i32 1, [[DIV159]] -// CHECK1-NEXT: [[TMP103:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB161:%.*]] = sub i32 [[TMP103]], -63 -// CHECK1-NEXT: [[DIV162:%.*]] = udiv i32 [[SUB161]], 64 -// CHECK1-NEXT: [[MUL163:%.*]] = mul i32 [[MUL160]], [[DIV162]] -// CHECK1-NEXT: [[TMP104:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP105:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB164:%.*]] = sub i32 [[TMP104]], [[TMP105]] -// CHECK1-NEXT: [[SUB165:%.*]] = sub i32 [[SUB164]], 1 -// CHECK1-NEXT: [[ADD166:%.*]] = add i32 [[SUB165]], 1 -// CHECK1-NEXT: [[DIV167:%.*]] = udiv i32 [[ADD166]], 1 -// CHECK1-NEXT: [[MUL168:%.*]] = mul i32 [[MUL163]], [[DIV167]] -// CHECK1-NEXT: [[CONV169:%.*]] = zext i32 [[MUL168]] to i64 -// CHECK1-NEXT: [[DIV170:%.*]] = sdiv i64 [[TMP98]], [[CONV169]] -// CHECK1-NEXT: [[TMP106:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK1-NEXT: [[TMP107:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK1-NEXT: [[SUB171:%.*]] = sub i32 [[TMP106]], [[TMP107]] -// CHECK1-NEXT: [[SUB172:%.*]] = sub i32 [[SUB171]], 1 -// CHECK1-NEXT: [[TMP108:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[ADD173:%.*]] = add i32 [[SUB172]], [[TMP108]] -// CHECK1-NEXT: [[TMP109:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[DIV174:%.*]] = udiv i32 [[ADD173]], [[TMP109]] -// CHECK1-NEXT: [[MUL175:%.*]] = mul i32 1, [[DIV174]] -// CHECK1-NEXT: [[TMP110:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB176:%.*]] = sub i32 [[TMP110]], -63 -// CHECK1-NEXT: [[DIV177:%.*]] = udiv i32 [[SUB176]], 64 -// CHECK1-NEXT: [[MUL178:%.*]] = mul i32 [[MUL175]], [[DIV177]] -// CHECK1-NEXT: [[TMP111:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP112:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB179:%.*]] = sub i32 [[TMP111]], [[TMP112]] -// CHECK1-NEXT: [[SUB180:%.*]] = sub i32 [[SUB179]], 1 -// CHECK1-NEXT: [[ADD181:%.*]] = add i32 [[SUB180]], 1 -// CHECK1-NEXT: [[DIV182:%.*]] = udiv i32 [[ADD181]], 1 -// CHECK1-NEXT: [[MUL183:%.*]] = mul i32 [[MUL178]], [[DIV182]] -// CHECK1-NEXT: [[CONV184:%.*]] = zext i32 [[MUL183]] to i64 -// CHECK1-NEXT: [[MUL185:%.*]] = mul nsw i64 [[DIV170]], [[CONV184]] -// CHECK1-NEXT: [[SUB186:%.*]] = sub nsw i64 [[TMP97]], [[MUL185]] +// CHECK1-NEXT: [[ADD156:%.*]] = add i32 [[SUB155]], [[TMP93]] +// CHECK1-NEXT: [[TMP94:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[DIV157:%.*]] = udiv i32 [[ADD156]], [[TMP94]] +// CHECK1-NEXT: [[MUL158:%.*]] = mul i32 1, [[DIV157]] +// CHECK1-NEXT: [[TMP95:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB159:%.*]] = sub i32 [[TMP95]], -63 +// CHECK1-NEXT: [[DIV160:%.*]] = udiv i32 [[SUB159]], 64 +// CHECK1-NEXT: [[MUL161:%.*]] = mul i32 [[MUL158]], [[DIV160]] +// CHECK1-NEXT: [[MUL162:%.*]] = mul i32 [[MUL161]], 64 +// CHECK1-NEXT: [[CONV163:%.*]] = zext i32 [[MUL162]] to i64 +// CHECK1-NEXT: [[DIV164:%.*]] = sdiv i64 [[TMP90]], [[CONV163]] +// CHECK1-NEXT: [[TMP96:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK1-NEXT: [[TMP97:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK1-NEXT: [[SUB165:%.*]] = sub i32 [[TMP96]], [[TMP97]] +// CHECK1-NEXT: [[SUB166:%.*]] = sub i32 [[SUB165]], 1 +// CHECK1-NEXT: [[TMP98:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[ADD167:%.*]] = add i32 [[SUB166]], [[TMP98]] +// CHECK1-NEXT: [[TMP99:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[DIV168:%.*]] = udiv i32 [[ADD167]], [[TMP99]] +// CHECK1-NEXT: [[MUL169:%.*]] = mul i32 1, [[DIV168]] +// CHECK1-NEXT: [[TMP100:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB170:%.*]] = sub i32 [[TMP100]], -63 +// CHECK1-NEXT: [[DIV171:%.*]] = udiv i32 [[SUB170]], 64 +// CHECK1-NEXT: [[MUL172:%.*]] = mul i32 [[MUL169]], [[DIV171]] +// CHECK1-NEXT: [[MUL173:%.*]] = mul i32 [[MUL172]], 64 +// CHECK1-NEXT: [[CONV174:%.*]] = zext i32 [[MUL173]] to i64 +// CHECK1-NEXT: [[MUL175:%.*]] = mul nsw i64 [[DIV164]], [[CONV174]] +// CHECK1-NEXT: [[SUB176:%.*]] = sub nsw i64 [[TMP89]], [[MUL175]] +// CHECK1-NEXT: [[TMP101:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[TMP102:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[TMP103:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK1-NEXT: [[TMP104:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK1-NEXT: [[SUB177:%.*]] = sub i32 [[TMP103]], [[TMP104]] +// CHECK1-NEXT: [[SUB178:%.*]] = sub i32 [[SUB177]], 1 +// CHECK1-NEXT: [[TMP105:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[ADD179:%.*]] = add i32 [[SUB178]], [[TMP105]] +// CHECK1-NEXT: [[TMP106:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[DIV180:%.*]] = udiv i32 [[ADD179]], [[TMP106]] +// CHECK1-NEXT: [[MUL181:%.*]] = mul i32 1, [[DIV180]] +// CHECK1-NEXT: [[TMP107:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB182:%.*]] = sub i32 [[TMP107]], -63 +// CHECK1-NEXT: [[DIV183:%.*]] = udiv i32 [[SUB182]], 64 +// CHECK1-NEXT: [[MUL184:%.*]] = mul i32 [[MUL181]], [[DIV183]] +// CHECK1-NEXT: [[MUL185:%.*]] = mul i32 [[MUL184]], 64 +// CHECK1-NEXT: [[CONV186:%.*]] = zext i32 [[MUL185]] to i64 +// CHECK1-NEXT: [[DIV187:%.*]] = sdiv i64 [[TMP102]], [[CONV186]] +// CHECK1-NEXT: [[TMP108:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK1-NEXT: [[TMP109:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK1-NEXT: [[SUB188:%.*]] = sub i32 [[TMP108]], [[TMP109]] +// CHECK1-NEXT: [[SUB189:%.*]] = sub i32 [[SUB188]], 1 +// CHECK1-NEXT: [[TMP110:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[ADD190:%.*]] = add i32 [[SUB189]], [[TMP110]] +// CHECK1-NEXT: [[TMP111:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[DIV191:%.*]] = udiv i32 [[ADD190]], [[TMP111]] +// CHECK1-NEXT: [[MUL192:%.*]] = mul i32 1, [[DIV191]] +// CHECK1-NEXT: [[TMP112:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB193:%.*]] = sub i32 [[TMP112]], -63 +// CHECK1-NEXT: [[DIV194:%.*]] = udiv i32 [[SUB193]], 64 +// CHECK1-NEXT: [[MUL195:%.*]] = mul i32 [[MUL192]], [[DIV194]] +// CHECK1-NEXT: [[MUL196:%.*]] = mul i32 [[MUL195]], 64 +// CHECK1-NEXT: [[CONV197:%.*]] = zext i32 [[MUL196]] to i64 +// CHECK1-NEXT: [[MUL198:%.*]] = mul nsw i64 [[DIV187]], [[CONV197]] +// CHECK1-NEXT: [[SUB199:%.*]] = sub nsw i64 [[TMP101]], [[MUL198]] // CHECK1-NEXT: [[TMP113:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB187:%.*]] = sub i32 [[TMP113]], -63 -// CHECK1-NEXT: [[DIV188:%.*]] = udiv i32 [[SUB187]], 64 -// CHECK1-NEXT: [[MUL189:%.*]] = mul i32 1, [[DIV188]] -// CHECK1-NEXT: [[TMP114:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP115:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB190:%.*]] = sub i32 [[TMP114]], [[TMP115]] -// CHECK1-NEXT: [[SUB191:%.*]] = sub i32 [[SUB190]], 1 -// CHECK1-NEXT: [[ADD192:%.*]] = add i32 [[SUB191]], 1 -// CHECK1-NEXT: [[DIV193:%.*]] = udiv i32 [[ADD192]], 1 -// CHECK1-NEXT: [[MUL194:%.*]] = mul i32 [[MUL189]], [[DIV193]] -// CHECK1-NEXT: [[CONV195:%.*]] = zext i32 [[MUL194]] to i64 -// CHECK1-NEXT: [[DIV196:%.*]] = sdiv i64 [[SUB186]], [[CONV195]] -// CHECK1-NEXT: [[TMP116:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB197:%.*]] = sub i32 [[TMP116]], -63 -// CHECK1-NEXT: [[DIV198:%.*]] = udiv i32 [[SUB197]], 64 -// CHECK1-NEXT: [[MUL199:%.*]] = mul i32 1, [[DIV198]] -// CHECK1-NEXT: [[TMP117:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP118:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB200:%.*]] = sub i32 [[TMP117]], [[TMP118]] -// CHECK1-NEXT: [[SUB201:%.*]] = sub i32 [[SUB200]], 1 -// CHECK1-NEXT: [[ADD202:%.*]] = add i32 [[SUB201]], 1 -// CHECK1-NEXT: [[DIV203:%.*]] = udiv i32 [[ADD202]], 1 -// CHECK1-NEXT: [[MUL204:%.*]] = mul i32 [[MUL199]], [[DIV203]] -// CHECK1-NEXT: [[CONV205:%.*]] = zext i32 [[MUL204]] to i64 -// CHECK1-NEXT: [[MUL206:%.*]] = mul nsw i64 [[DIV196]], [[CONV205]] -// CHECK1-NEXT: [[SUB207:%.*]] = sub nsw i64 [[SUB155]], [[MUL206]] -// CHECK1-NEXT: [[TMP119:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP120:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB208:%.*]] = sub i32 [[TMP119]], [[TMP120]] -// CHECK1-NEXT: [[SUB209:%.*]] = sub i32 [[SUB208]], 1 -// CHECK1-NEXT: [[ADD210:%.*]] = add i32 [[SUB209]], 1 -// CHECK1-NEXT: [[DIV211:%.*]] = udiv i32 [[ADD210]], 1 -// CHECK1-NEXT: [[MUL212:%.*]] = mul i32 1, [[DIV211]] -// CHECK1-NEXT: [[CONV213:%.*]] = zext i32 [[MUL212]] to i64 -// CHECK1-NEXT: [[DIV214:%.*]] = sdiv i64 [[SUB207]], [[CONV213]] -// CHECK1-NEXT: [[MUL215:%.*]] = mul nsw i64 [[DIV214]], 64 -// CHECK1-NEXT: [[ADD216:%.*]] = add nsw i64 0, [[MUL215]] -// CHECK1-NEXT: [[CONV217:%.*]] = trunc i64 [[ADD216]] to i32 -// CHECK1-NEXT: store i32 [[CONV217]], ptr [[DOTFLOOR_0_IV_K51]], align 4 -// CHECK1-NEXT: [[TMP121:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[CONV218:%.*]] = zext i32 [[TMP121]] to i64 -// CHECK1-NEXT: [[TMP122:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP123:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP124:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK1-NEXT: [[TMP125:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK1-NEXT: [[SUB219:%.*]] = sub i32 [[TMP124]], [[TMP125]] -// CHECK1-NEXT: [[SUB220:%.*]] = sub i32 [[SUB219]], 1 -// CHECK1-NEXT: [[TMP126:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[ADD221:%.*]] = add i32 [[SUB220]], [[TMP126]] -// CHECK1-NEXT: [[TMP127:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[DIV222:%.*]] = udiv i32 [[ADD221]], [[TMP127]] -// CHECK1-NEXT: [[MUL223:%.*]] = mul i32 1, [[DIV222]] -// CHECK1-NEXT: [[TMP128:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB224:%.*]] = sub i32 [[TMP128]], -63 -// CHECK1-NEXT: [[DIV225:%.*]] = udiv i32 [[SUB224]], 64 -// CHECK1-NEXT: [[MUL226:%.*]] = mul i32 [[MUL223]], [[DIV225]] -// CHECK1-NEXT: [[TMP129:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP130:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB227:%.*]] = sub i32 [[TMP129]], [[TMP130]] -// CHECK1-NEXT: [[SUB228:%.*]] = sub i32 [[SUB227]], 1 -// CHECK1-NEXT: [[ADD229:%.*]] = add i32 [[SUB228]], 1 -// CHECK1-NEXT: [[DIV230:%.*]] = udiv i32 [[ADD229]], 1 -// CHECK1-NEXT: [[MUL231:%.*]] = mul i32 [[MUL226]], [[DIV230]] -// CHECK1-NEXT: [[CONV232:%.*]] = zext i32 [[MUL231]] to i64 -// CHECK1-NEXT: [[DIV233:%.*]] = sdiv i64 [[TMP123]], [[CONV232]] -// CHECK1-NEXT: [[TMP131:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK1-NEXT: [[TMP132:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK1-NEXT: [[SUB234:%.*]] = sub i32 [[TMP131]], [[TMP132]] -// CHECK1-NEXT: [[SUB235:%.*]] = sub i32 [[SUB234]], 1 -// CHECK1-NEXT: [[TMP133:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[ADD236:%.*]] = add i32 [[SUB235]], [[TMP133]] -// CHECK1-NEXT: [[TMP134:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[DIV237:%.*]] = udiv i32 [[ADD236]], [[TMP134]] -// CHECK1-NEXT: [[MUL238:%.*]] = mul i32 1, [[DIV237]] -// CHECK1-NEXT: [[TMP135:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB239:%.*]] = sub i32 [[TMP135]], -63 -// CHECK1-NEXT: [[DIV240:%.*]] = udiv i32 [[SUB239]], 64 -// CHECK1-NEXT: [[MUL241:%.*]] = mul i32 [[MUL238]], [[DIV240]] -// CHECK1-NEXT: [[TMP136:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP137:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB242:%.*]] = sub i32 [[TMP136]], [[TMP137]] -// CHECK1-NEXT: [[SUB243:%.*]] = sub i32 [[SUB242]], 1 -// CHECK1-NEXT: [[ADD244:%.*]] = add i32 [[SUB243]], 1 -// CHECK1-NEXT: [[DIV245:%.*]] = udiv i32 [[ADD244]], 1 -// CHECK1-NEXT: [[MUL246:%.*]] = mul i32 [[MUL241]], [[DIV245]] -// CHECK1-NEXT: [[CONV247:%.*]] = zext i32 [[MUL246]] to i64 -// CHECK1-NEXT: [[MUL248:%.*]] = mul nsw i64 [[DIV233]], [[CONV247]] -// CHECK1-NEXT: [[SUB249:%.*]] = sub nsw i64 [[TMP122]], [[MUL248]] -// CHECK1-NEXT: [[TMP138:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP139:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP140:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK1-NEXT: [[TMP141:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK1-NEXT: [[SUB250:%.*]] = sub i32 [[TMP140]], [[TMP141]] -// CHECK1-NEXT: [[SUB251:%.*]] = sub i32 [[SUB250]], 1 -// CHECK1-NEXT: [[TMP142:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[ADD252:%.*]] = add i32 [[SUB251]], [[TMP142]] -// CHECK1-NEXT: [[TMP143:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[DIV253:%.*]] = udiv i32 [[ADD252]], [[TMP143]] -// CHECK1-NEXT: [[MUL254:%.*]] = mul i32 1, [[DIV253]] -// CHECK1-NEXT: [[TMP144:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB255:%.*]] = sub i32 [[TMP144]], -63 -// CHECK1-NEXT: [[DIV256:%.*]] = udiv i32 [[SUB255]], 64 -// CHECK1-NEXT: [[MUL257:%.*]] = mul i32 [[MUL254]], [[DIV256]] -// CHECK1-NEXT: [[TMP145:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP146:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB258:%.*]] = sub i32 [[TMP145]], [[TMP146]] -// CHECK1-NEXT: [[SUB259:%.*]] = sub i32 [[SUB258]], 1 -// CHECK1-NEXT: [[ADD260:%.*]] = add i32 [[SUB259]], 1 -// CHECK1-NEXT: [[DIV261:%.*]] = udiv i32 [[ADD260]], 1 -// CHECK1-NEXT: [[MUL262:%.*]] = mul i32 [[MUL257]], [[DIV261]] +// CHECK1-NEXT: [[SUB200:%.*]] = sub i32 [[TMP113]], -63 +// CHECK1-NEXT: [[DIV201:%.*]] = udiv i32 [[SUB200]], 64 +// CHECK1-NEXT: [[MUL202:%.*]] = mul i32 1, [[DIV201]] +// CHECK1-NEXT: [[MUL203:%.*]] = mul i32 [[MUL202]], 64 +// CHECK1-NEXT: [[CONV204:%.*]] = zext i32 [[MUL203]] to i64 +// CHECK1-NEXT: [[DIV205:%.*]] = sdiv i64 [[SUB199]], [[CONV204]] +// CHECK1-NEXT: [[TMP114:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB206:%.*]] = sub i32 [[TMP114]], -63 +// CHECK1-NEXT: [[DIV207:%.*]] = udiv i32 [[SUB206]], 64 +// CHECK1-NEXT: [[MUL208:%.*]] = mul i32 1, [[DIV207]] +// CHECK1-NEXT: [[MUL209:%.*]] = mul i32 [[MUL208]], 64 +// CHECK1-NEXT: [[CONV210:%.*]] = zext i32 [[MUL209]] to i64 +// CHECK1-NEXT: [[MUL211:%.*]] = mul nsw i64 [[DIV205]], [[CONV210]] +// CHECK1-NEXT: [[SUB212:%.*]] = sub nsw i64 [[SUB176]], [[MUL211]] +// CHECK1-NEXT: [[TMP115:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[TMP116:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[TMP117:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK1-NEXT: [[TMP118:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK1-NEXT: [[SUB213:%.*]] = sub i32 [[TMP117]], [[TMP118]] +// CHECK1-NEXT: [[SUB214:%.*]] = sub i32 [[SUB213]], 1 +// CHECK1-NEXT: [[TMP119:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[ADD215:%.*]] = add i32 [[SUB214]], [[TMP119]] +// CHECK1-NEXT: [[TMP120:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[DIV216:%.*]] = udiv i32 [[ADD215]], [[TMP120]] +// CHECK1-NEXT: [[MUL217:%.*]] = mul i32 1, [[DIV216]] +// CHECK1-NEXT: [[TMP121:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB218:%.*]] = sub i32 [[TMP121]], -63 +// CHECK1-NEXT: [[DIV219:%.*]] = udiv i32 [[SUB218]], 64 +// CHECK1-NEXT: [[MUL220:%.*]] = mul i32 [[MUL217]], [[DIV219]] +// CHECK1-NEXT: [[MUL221:%.*]] = mul i32 [[MUL220]], 64 +// CHECK1-NEXT: [[CONV222:%.*]] = zext i32 [[MUL221]] to i64 +// CHECK1-NEXT: [[DIV223:%.*]] = sdiv i64 [[TMP116]], [[CONV222]] +// CHECK1-NEXT: [[TMP122:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK1-NEXT: [[TMP123:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK1-NEXT: [[SUB224:%.*]] = sub i32 [[TMP122]], [[TMP123]] +// CHECK1-NEXT: [[SUB225:%.*]] = sub i32 [[SUB224]], 1 +// CHECK1-NEXT: [[TMP124:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[ADD226:%.*]] = add i32 [[SUB225]], [[TMP124]] +// CHECK1-NEXT: [[TMP125:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[DIV227:%.*]] = udiv i32 [[ADD226]], [[TMP125]] +// CHECK1-NEXT: [[MUL228:%.*]] = mul i32 1, [[DIV227]] +// CHECK1-NEXT: [[TMP126:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB229:%.*]] = sub i32 [[TMP126]], -63 +// CHECK1-NEXT: [[DIV230:%.*]] = udiv i32 [[SUB229]], 64 +// CHECK1-NEXT: [[MUL231:%.*]] = mul i32 [[MUL228]], [[DIV230]] +// CHECK1-NEXT: [[MUL232:%.*]] = mul i32 [[MUL231]], 64 +// CHECK1-NEXT: [[CONV233:%.*]] = zext i32 [[MUL232]] to i64 +// CHECK1-NEXT: [[MUL234:%.*]] = mul nsw i64 [[DIV223]], [[CONV233]] +// CHECK1-NEXT: [[SUB235:%.*]] = sub nsw i64 [[TMP115]], [[MUL234]] +// CHECK1-NEXT: [[TMP127:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[TMP128:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[TMP129:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK1-NEXT: [[TMP130:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK1-NEXT: [[SUB236:%.*]] = sub i32 [[TMP129]], [[TMP130]] +// CHECK1-NEXT: [[SUB237:%.*]] = sub i32 [[SUB236]], 1 +// CHECK1-NEXT: [[TMP131:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[ADD238:%.*]] = add i32 [[SUB237]], [[TMP131]] +// CHECK1-NEXT: [[TMP132:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[DIV239:%.*]] = udiv i32 [[ADD238]], [[TMP132]] +// CHECK1-NEXT: [[MUL240:%.*]] = mul i32 1, [[DIV239]] +// CHECK1-NEXT: [[TMP133:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB241:%.*]] = sub i32 [[TMP133]], -63 +// CHECK1-NEXT: [[DIV242:%.*]] = udiv i32 [[SUB241]], 64 +// CHECK1-NEXT: [[MUL243:%.*]] = mul i32 [[MUL240]], [[DIV242]] +// CHECK1-NEXT: [[MUL244:%.*]] = mul i32 [[MUL243]], 64 +// CHECK1-NEXT: [[CONV245:%.*]] = zext i32 [[MUL244]] to i64 +// CHECK1-NEXT: [[DIV246:%.*]] = sdiv i64 [[TMP128]], [[CONV245]] +// CHECK1-NEXT: [[TMP134:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK1-NEXT: [[TMP135:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK1-NEXT: [[SUB247:%.*]] = sub i32 [[TMP134]], [[TMP135]] +// CHECK1-NEXT: [[SUB248:%.*]] = sub i32 [[SUB247]], 1 +// CHECK1-NEXT: [[TMP136:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[ADD249:%.*]] = add i32 [[SUB248]], [[TMP136]] +// CHECK1-NEXT: [[TMP137:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK1-NEXT: [[DIV250:%.*]] = udiv i32 [[ADD249]], [[TMP137]] +// CHECK1-NEXT: [[MUL251:%.*]] = mul i32 1, [[DIV250]] +// CHECK1-NEXT: [[TMP138:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB252:%.*]] = sub i32 [[TMP138]], -63 +// CHECK1-NEXT: [[DIV253:%.*]] = udiv i32 [[SUB252]], 64 +// CHECK1-NEXT: [[MUL254:%.*]] = mul i32 [[MUL251]], [[DIV253]] +// CHECK1-NEXT: [[MUL255:%.*]] = mul i32 [[MUL254]], 64 +// CHECK1-NEXT: [[CONV256:%.*]] = zext i32 [[MUL255]] to i64 +// CHECK1-NEXT: [[MUL257:%.*]] = mul nsw i64 [[DIV246]], [[CONV256]] +// CHECK1-NEXT: [[SUB258:%.*]] = sub nsw i64 [[TMP127]], [[MUL257]] +// CHECK1-NEXT: [[TMP139:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB259:%.*]] = sub i32 [[TMP139]], -63 +// CHECK1-NEXT: [[DIV260:%.*]] = udiv i32 [[SUB259]], 64 +// CHECK1-NEXT: [[MUL261:%.*]] = mul i32 1, [[DIV260]] +// CHECK1-NEXT: [[MUL262:%.*]] = mul i32 [[MUL261]], 64 // CHECK1-NEXT: [[CONV263:%.*]] = zext i32 [[MUL262]] to i64 -// CHECK1-NEXT: [[DIV264:%.*]] = sdiv i64 [[TMP139]], [[CONV263]] -// CHECK1-NEXT: [[TMP147:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK1-NEXT: [[TMP148:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK1-NEXT: [[SUB265:%.*]] = sub i32 [[TMP147]], [[TMP148]] -// CHECK1-NEXT: [[SUB266:%.*]] = sub i32 [[SUB265]], 1 -// CHECK1-NEXT: [[TMP149:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[ADD267:%.*]] = add i32 [[SUB266]], [[TMP149]] -// CHECK1-NEXT: [[TMP150:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[DIV268:%.*]] = udiv i32 [[ADD267]], [[TMP150]] -// CHECK1-NEXT: [[MUL269:%.*]] = mul i32 1, [[DIV268]] -// CHECK1-NEXT: [[TMP151:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB270:%.*]] = sub i32 [[TMP151]], -63 -// CHECK1-NEXT: [[DIV271:%.*]] = udiv i32 [[SUB270]], 64 -// CHECK1-NEXT: [[MUL272:%.*]] = mul i32 [[MUL269]], [[DIV271]] -// CHECK1-NEXT: [[TMP152:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP153:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB273:%.*]] = sub i32 [[TMP152]], [[TMP153]] -// CHECK1-NEXT: [[SUB274:%.*]] = sub i32 [[SUB273]], 1 -// CHECK1-NEXT: [[ADD275:%.*]] = add i32 [[SUB274]], 1 -// CHECK1-NEXT: [[DIV276:%.*]] = udiv i32 [[ADD275]], 1 -// CHECK1-NEXT: [[MUL277:%.*]] = mul i32 [[MUL272]], [[DIV276]] -// CHECK1-NEXT: [[CONV278:%.*]] = zext i32 [[MUL277]] to i64 -// CHECK1-NEXT: [[MUL279:%.*]] = mul nsw i64 [[DIV264]], [[CONV278]] -// CHECK1-NEXT: [[SUB280:%.*]] = sub nsw i64 [[TMP138]], [[MUL279]] -// CHECK1-NEXT: [[TMP154:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB281:%.*]] = sub i32 [[TMP154]], -63 -// CHECK1-NEXT: [[DIV282:%.*]] = udiv i32 [[SUB281]], 64 -// CHECK1-NEXT: [[MUL283:%.*]] = mul i32 1, [[DIV282]] -// CHECK1-NEXT: [[TMP155:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP156:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB284:%.*]] = sub i32 [[TMP155]], [[TMP156]] -// CHECK1-NEXT: [[SUB285:%.*]] = sub i32 [[SUB284]], 1 -// CHECK1-NEXT: [[ADD286:%.*]] = add i32 [[SUB285]], 1 -// CHECK1-NEXT: [[DIV287:%.*]] = udiv i32 [[ADD286]], 1 -// CHECK1-NEXT: [[MUL288:%.*]] = mul i32 [[MUL283]], [[DIV287]] -// CHECK1-NEXT: [[CONV289:%.*]] = zext i32 [[MUL288]] to i64 -// CHECK1-NEXT: [[DIV290:%.*]] = sdiv i64 [[SUB280]], [[CONV289]] -// CHECK1-NEXT: [[TMP157:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB291:%.*]] = sub i32 [[TMP157]], -63 -// CHECK1-NEXT: [[DIV292:%.*]] = udiv i32 [[SUB291]], 64 -// CHECK1-NEXT: [[MUL293:%.*]] = mul i32 1, [[DIV292]] -// CHECK1-NEXT: [[TMP158:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP159:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB294:%.*]] = sub i32 [[TMP158]], [[TMP159]] -// CHECK1-NEXT: [[SUB295:%.*]] = sub i32 [[SUB294]], 1 -// CHECK1-NEXT: [[ADD296:%.*]] = add i32 [[SUB295]], 1 -// CHECK1-NEXT: [[DIV297:%.*]] = udiv i32 [[ADD296]], 1 -// CHECK1-NEXT: [[MUL298:%.*]] = mul i32 [[MUL293]], [[DIV297]] -// CHECK1-NEXT: [[CONV299:%.*]] = zext i32 [[MUL298]] to i64 -// CHECK1-NEXT: [[MUL300:%.*]] = mul nsw i64 [[DIV290]], [[CONV299]] -// CHECK1-NEXT: [[SUB301:%.*]] = sub nsw i64 [[SUB249]], [[MUL300]] -// CHECK1-NEXT: [[TMP160:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP161:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP162:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK1-NEXT: [[TMP163:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK1-NEXT: [[SUB302:%.*]] = sub i32 [[TMP162]], [[TMP163]] -// CHECK1-NEXT: [[SUB303:%.*]] = sub i32 [[SUB302]], 1 -// CHECK1-NEXT: [[TMP164:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[ADD304:%.*]] = add i32 [[SUB303]], [[TMP164]] -// CHECK1-NEXT: [[TMP165:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[DIV305:%.*]] = udiv i32 [[ADD304]], [[TMP165]] -// CHECK1-NEXT: [[MUL306:%.*]] = mul i32 1, [[DIV305]] -// CHECK1-NEXT: [[TMP166:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB307:%.*]] = sub i32 [[TMP166]], -63 -// CHECK1-NEXT: [[DIV308:%.*]] = udiv i32 [[SUB307]], 64 -// CHECK1-NEXT: [[MUL309:%.*]] = mul i32 [[MUL306]], [[DIV308]] -// CHECK1-NEXT: [[TMP167:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP168:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB310:%.*]] = sub i32 [[TMP167]], [[TMP168]] -// CHECK1-NEXT: [[SUB311:%.*]] = sub i32 [[SUB310]], 1 -// CHECK1-NEXT: [[ADD312:%.*]] = add i32 [[SUB311]], 1 -// CHECK1-NEXT: [[DIV313:%.*]] = udiv i32 [[ADD312]], 1 -// CHECK1-NEXT: [[MUL314:%.*]] = mul i32 [[MUL309]], [[DIV313]] -// CHECK1-NEXT: [[CONV315:%.*]] = zext i32 [[MUL314]] to i64 -// CHECK1-NEXT: [[DIV316:%.*]] = sdiv i64 [[TMP161]], [[CONV315]] -// CHECK1-NEXT: [[TMP169:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK1-NEXT: [[TMP170:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK1-NEXT: [[SUB317:%.*]] = sub i32 [[TMP169]], [[TMP170]] -// CHECK1-NEXT: [[SUB318:%.*]] = sub i32 [[SUB317]], 1 -// CHECK1-NEXT: [[TMP171:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[ADD319:%.*]] = add i32 [[SUB318]], [[TMP171]] -// CHECK1-NEXT: [[TMP172:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[DIV320:%.*]] = udiv i32 [[ADD319]], [[TMP172]] -// CHECK1-NEXT: [[MUL321:%.*]] = mul i32 1, [[DIV320]] -// CHECK1-NEXT: [[TMP173:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB322:%.*]] = sub i32 [[TMP173]], -63 -// CHECK1-NEXT: [[DIV323:%.*]] = udiv i32 [[SUB322]], 64 -// CHECK1-NEXT: [[MUL324:%.*]] = mul i32 [[MUL321]], [[DIV323]] -// CHECK1-NEXT: [[TMP174:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP175:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB325:%.*]] = sub i32 [[TMP174]], [[TMP175]] -// CHECK1-NEXT: [[SUB326:%.*]] = sub i32 [[SUB325]], 1 -// CHECK1-NEXT: [[ADD327:%.*]] = add i32 [[SUB326]], 1 -// CHECK1-NEXT: [[DIV328:%.*]] = udiv i32 [[ADD327]], 1 -// CHECK1-NEXT: [[MUL329:%.*]] = mul i32 [[MUL324]], [[DIV328]] -// CHECK1-NEXT: [[CONV330:%.*]] = zext i32 [[MUL329]] to i64 -// CHECK1-NEXT: [[MUL331:%.*]] = mul nsw i64 [[DIV316]], [[CONV330]] -// CHECK1-NEXT: [[SUB332:%.*]] = sub nsw i64 [[TMP160]], [[MUL331]] -// CHECK1-NEXT: [[TMP176:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP177:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP178:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK1-NEXT: [[TMP179:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK1-NEXT: [[SUB333:%.*]] = sub i32 [[TMP178]], [[TMP179]] -// CHECK1-NEXT: [[SUB334:%.*]] = sub i32 [[SUB333]], 1 -// CHECK1-NEXT: [[TMP180:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[ADD335:%.*]] = add i32 [[SUB334]], [[TMP180]] -// CHECK1-NEXT: [[TMP181:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[DIV336:%.*]] = udiv i32 [[ADD335]], [[TMP181]] -// CHECK1-NEXT: [[MUL337:%.*]] = mul i32 1, [[DIV336]] -// CHECK1-NEXT: [[TMP182:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB338:%.*]] = sub i32 [[TMP182]], -63 -// CHECK1-NEXT: [[DIV339:%.*]] = udiv i32 [[SUB338]], 64 -// CHECK1-NEXT: [[MUL340:%.*]] = mul i32 [[MUL337]], [[DIV339]] -// CHECK1-NEXT: [[TMP183:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP184:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB341:%.*]] = sub i32 [[TMP183]], [[TMP184]] -// CHECK1-NEXT: [[SUB342:%.*]] = sub i32 [[SUB341]], 1 -// CHECK1-NEXT: [[ADD343:%.*]] = add i32 [[SUB342]], 1 -// CHECK1-NEXT: [[DIV344:%.*]] = udiv i32 [[ADD343]], 1 -// CHECK1-NEXT: [[MUL345:%.*]] = mul i32 [[MUL340]], [[DIV344]] -// CHECK1-NEXT: [[CONV346:%.*]] = zext i32 [[MUL345]] to i64 -// CHECK1-NEXT: [[DIV347:%.*]] = sdiv i64 [[TMP177]], [[CONV346]] -// CHECK1-NEXT: [[TMP185:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK1-NEXT: [[TMP186:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK1-NEXT: [[SUB348:%.*]] = sub i32 [[TMP185]], [[TMP186]] -// CHECK1-NEXT: [[SUB349:%.*]] = sub i32 [[SUB348]], 1 -// CHECK1-NEXT: [[TMP187:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[ADD350:%.*]] = add i32 [[SUB349]], [[TMP187]] -// CHECK1-NEXT: [[TMP188:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK1-NEXT: [[DIV351:%.*]] = udiv i32 [[ADD350]], [[TMP188]] -// CHECK1-NEXT: [[MUL352:%.*]] = mul i32 1, [[DIV351]] -// CHECK1-NEXT: [[TMP189:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB353:%.*]] = sub i32 [[TMP189]], -63 -// CHECK1-NEXT: [[DIV354:%.*]] = udiv i32 [[SUB353]], 64 -// CHECK1-NEXT: [[MUL355:%.*]] = mul i32 [[MUL352]], [[DIV354]] -// CHECK1-NEXT: [[TMP190:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP191:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB356:%.*]] = sub i32 [[TMP190]], [[TMP191]] -// CHECK1-NEXT: [[SUB357:%.*]] = sub i32 [[SUB356]], 1 -// CHECK1-NEXT: [[ADD358:%.*]] = add i32 [[SUB357]], 1 -// CHECK1-NEXT: [[DIV359:%.*]] = udiv i32 [[ADD358]], 1 -// CHECK1-NEXT: [[MUL360:%.*]] = mul i32 [[MUL355]], [[DIV359]] -// CHECK1-NEXT: [[CONV361:%.*]] = zext i32 [[MUL360]] to i64 -// CHECK1-NEXT: [[MUL362:%.*]] = mul nsw i64 [[DIV347]], [[CONV361]] -// CHECK1-NEXT: [[SUB363:%.*]] = sub nsw i64 [[TMP176]], [[MUL362]] -// CHECK1-NEXT: [[TMP192:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB364:%.*]] = sub i32 [[TMP192]], -63 -// CHECK1-NEXT: [[DIV365:%.*]] = udiv i32 [[SUB364]], 64 -// CHECK1-NEXT: [[MUL366:%.*]] = mul i32 1, [[DIV365]] -// CHECK1-NEXT: [[TMP193:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP194:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB367:%.*]] = sub i32 [[TMP193]], [[TMP194]] -// CHECK1-NEXT: [[SUB368:%.*]] = sub i32 [[SUB367]], 1 -// CHECK1-NEXT: [[ADD369:%.*]] = add i32 [[SUB368]], 1 -// CHECK1-NEXT: [[DIV370:%.*]] = udiv i32 [[ADD369]], 1 -// CHECK1-NEXT: [[MUL371:%.*]] = mul i32 [[MUL366]], [[DIV370]] -// CHECK1-NEXT: [[CONV372:%.*]] = zext i32 [[MUL371]] to i64 -// CHECK1-NEXT: [[DIV373:%.*]] = sdiv i64 [[SUB363]], [[CONV372]] -// CHECK1-NEXT: [[TMP195:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK1-NEXT: [[SUB374:%.*]] = sub i32 [[TMP195]], -63 -// CHECK1-NEXT: [[DIV375:%.*]] = udiv i32 [[SUB374]], 64 -// CHECK1-NEXT: [[MUL376:%.*]] = mul i32 1, [[DIV375]] -// CHECK1-NEXT: [[TMP196:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP197:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB377:%.*]] = sub i32 [[TMP196]], [[TMP197]] -// CHECK1-NEXT: [[SUB378:%.*]] = sub i32 [[SUB377]], 1 -// CHECK1-NEXT: [[ADD379:%.*]] = add i32 [[SUB378]], 1 -// CHECK1-NEXT: [[DIV380:%.*]] = udiv i32 [[ADD379]], 1 -// CHECK1-NEXT: [[MUL381:%.*]] = mul i32 [[MUL376]], [[DIV380]] -// CHECK1-NEXT: [[CONV382:%.*]] = zext i32 [[MUL381]] to i64 -// CHECK1-NEXT: [[MUL383:%.*]] = mul nsw i64 [[DIV373]], [[CONV382]] -// CHECK1-NEXT: [[SUB384:%.*]] = sub nsw i64 [[SUB332]], [[MUL383]] -// CHECK1-NEXT: [[TMP198:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP199:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB385:%.*]] = sub i32 [[TMP198]], [[TMP199]] -// CHECK1-NEXT: [[SUB386:%.*]] = sub i32 [[SUB385]], 1 -// CHECK1-NEXT: [[ADD387:%.*]] = add i32 [[SUB386]], 1 -// CHECK1-NEXT: [[DIV388:%.*]] = udiv i32 [[ADD387]], 1 -// CHECK1-NEXT: [[MUL389:%.*]] = mul i32 1, [[DIV388]] -// CHECK1-NEXT: [[CONV390:%.*]] = zext i32 [[MUL389]] to i64 -// CHECK1-NEXT: [[DIV391:%.*]] = sdiv i64 [[SUB384]], [[CONV390]] -// CHECK1-NEXT: [[TMP200:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK1-NEXT: [[TMP201:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK1-NEXT: [[SUB392:%.*]] = sub i32 [[TMP200]], [[TMP201]] -// CHECK1-NEXT: [[SUB393:%.*]] = sub i32 [[SUB392]], 1 -// CHECK1-NEXT: [[ADD394:%.*]] = add i32 [[SUB393]], 1 -// CHECK1-NEXT: [[DIV395:%.*]] = udiv i32 [[ADD394]], 1 -// CHECK1-NEXT: [[MUL396:%.*]] = mul i32 1, [[DIV395]] -// CHECK1-NEXT: [[CONV397:%.*]] = zext i32 [[MUL396]] to i64 -// CHECK1-NEXT: [[MUL398:%.*]] = mul nsw i64 [[DIV391]], [[CONV397]] -// CHECK1-NEXT: [[SUB399:%.*]] = sub nsw i64 [[SUB301]], [[MUL398]] -// CHECK1-NEXT: [[MUL400:%.*]] = mul nsw i64 [[SUB399]], 1 -// CHECK1-NEXT: [[ADD401:%.*]] = add nsw i64 [[CONV218]], [[MUL400]] -// CHECK1-NEXT: [[CONV402:%.*]] = trunc i64 [[ADD401]] to i32 -// CHECK1-NEXT: store i32 [[CONV402]], ptr [[DOTTILE_0_IV_K52]], align 4 -// CHECK1-NEXT: [[TMP202:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 4 -// CHECK1-NEXT: [[TMP203:%.*]] = load i32, ptr [[DOTTILE_0_IV_K52]], align 4 -// CHECK1-NEXT: [[TMP204:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4 -// CHECK1-NEXT: [[MUL403:%.*]] = mul i32 [[TMP203]], [[TMP204]] -// CHECK1-NEXT: [[ADD404:%.*]] = add i32 [[TMP202]], [[MUL403]] -// CHECK1-NEXT: store i32 [[ADD404]], ptr [[K]], align 4 -// CHECK1-NEXT: [[TMP205:%.*]] = load i32, ptr [[I49]], align 4 -// CHECK1-NEXT: [[TMP206:%.*]] = load i32, ptr [[J50]], align 4 -// CHECK1-NEXT: [[TMP207:%.*]] = load i32, ptr [[K]], align 4 -// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP205]], i32 noundef [[TMP206]], i32 noundef [[TMP207]]) +// CHECK1-NEXT: [[DIV264:%.*]] = sdiv i64 [[SUB258]], [[CONV263]] +// CHECK1-NEXT: [[TMP140:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK1-NEXT: [[SUB265:%.*]] = sub i32 [[TMP140]], -63 +// CHECK1-NEXT: [[DIV266:%.*]] = udiv i32 [[SUB265]], 64 +// CHECK1-NEXT: [[MUL267:%.*]] = mul i32 1, [[DIV266]] +// CHECK1-NEXT: [[MUL268:%.*]] = mul i32 [[MUL267]], 64 +// CHECK1-NEXT: [[CONV269:%.*]] = zext i32 [[MUL268]] to i64 +// CHECK1-NEXT: [[MUL270:%.*]] = mul nsw i64 [[DIV264]], [[CONV269]] +// CHECK1-NEXT: [[SUB271:%.*]] = sub nsw i64 [[SUB235]], [[MUL270]] +// CHECK1-NEXT: [[DIV272:%.*]] = sdiv i64 [[SUB271]], 64 +// CHECK1-NEXT: [[MUL273:%.*]] = mul nsw i64 [[DIV272]], 64 +// CHECK1-NEXT: [[SUB274:%.*]] = sub nsw i64 [[SUB212]], [[MUL273]] +// CHECK1-NEXT: [[MUL275:%.*]] = mul nsw i64 [[SUB274]], 1 +// CHECK1-NEXT: [[ADD276:%.*]] = add nsw i64 0, [[MUL275]] +// CHECK1-NEXT: [[CONV277:%.*]] = trunc i64 [[ADD276]] to i32 +// CHECK1-NEXT: store i32 [[CONV277]], ptr [[DOTTILE_CNT_0_IV_K38]], align 4 +// CHECK1-NEXT: [[TMP141:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_K37]], align 4 +// CHECK1-NEXT: [[TMP142:%.*]] = load i32, ptr [[DOTTILE_CNT_0_IV_K38]], align 4 +// CHECK1-NEXT: [[ADD278:%.*]] = add i32 [[TMP141]], [[TMP142]] +// CHECK1-NEXT: store i32 [[ADD278]], ptr [[DOTTILE_0_IV_K]], align 4 +// CHECK1-NEXT: [[TMP143:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 4 +// CHECK1-NEXT: [[TMP144:%.*]] = load i32, ptr [[DOTTILE_0_IV_K]], align 4 +// CHECK1-NEXT: [[TMP145:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4 +// CHECK1-NEXT: [[MUL279:%.*]] = mul i32 [[TMP144]], [[TMP145]] +// CHECK1-NEXT: [[ADD280:%.*]] = add i32 [[TMP143]], [[MUL279]] +// CHECK1-NEXT: store i32 [[ADD280]], ptr [[K]], align 4 +// CHECK1-NEXT: [[TMP146:%.*]] = load i32, ptr [[DOTTILE_0_IV_K]], align 4 +// CHECK1-NEXT: [[TMP147:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4 +// CHECK1-NEXT: [[ADD281:%.*]] = add i32 [[TMP147]], 1 +// CHECK1-NEXT: [[CMP282:%.*]] = icmp ult i32 [[TMP146]], [[ADD281]] +// CHECK1-NEXT: br i1 [[CMP282]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] +// CHECK1: if.then: +// CHECK1-NEXT: [[TMP148:%.*]] = load i32, ptr [[I35]], align 4 +// CHECK1-NEXT: [[TMP149:%.*]] = load i32, ptr [[J36]], align 4 +// CHECK1-NEXT: [[TMP150:%.*]] = load i32, ptr [[K]], align 4 +// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP148]], i32 noundef [[TMP149]], i32 noundef [[TMP150]]) +// CHECK1-NEXT: br label [[IF_END]] +// CHECK1: if.end: // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP208:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[ADD405:%.*]] = add nsw i64 [[TMP208]], 1 -// CHECK1-NEXT: store i64 [[ADD405]], ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[TMP151:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[ADD283:%.*]] = add nsw i64 [[TMP151]], 1 +// CHECK1-NEXT: store i64 [[ADD283]], ptr [[DOTOMP_IV]], align 8 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -2225,14 +1868,14 @@ extern "C" void foo10() { // CHECK1-NEXT: [[V:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store double 4.200000e+01, ptr [[C]], align 8 // CHECK1-NEXT: store ptr [[ARR]], ptr [[__RANGE2]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__RANGE2]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META12:![0-9]+]], !align [[META13:![0-9]+]] // CHECK1-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP0]], i64 0, i64 0 // CHECK1-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY]], i64 128 // CHECK1-NEXT: store ptr [[ADD_PTR]], ptr [[__END2]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE2]], align 8 +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META12]], !align [[META13]] // CHECK1-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP1]], i64 0, i64 0 // CHECK1-NEXT: store ptr [[ARRAYDECAY1]], ptr [[__BEGIN2]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE2]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META12]], !align [[META13]] // CHECK1-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP2]], i64 0, i64 0 // CHECK1-NEXT: store ptr [[ARRAYDECAY2]], ptr [[DOTCAPTURE_EXPR_]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__END2]], align 8 @@ -2277,7 +1920,7 @@ extern "C" void foo10() { // CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[__BEGIN2]], align 8 // CHECK1-NEXT: store ptr [[TMP12]], ptr [[V]], align 8 // CHECK1-NEXT: [[TMP13:%.*]] = load double, ptr [[C]], align 8 -// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[V]], align 8 +// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[V]], align 8, !nonnull [[META12]], !align [[META13]] // CHECK1-NEXT: [[TMP15:%.*]] = load double, ptr [[TMP14]], align 8 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: call void (...) @body(double noundef [[TMP13]], double noundef [[TMP15]], i32 noundef [[TMP16]]) @@ -2286,14 +1929,14 @@ extern "C" void foo10() { // CHECK1-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 8 // CHECK1-NEXT: [[INC:%.*]] = add nsw i64 [[TMP17]], 1 // CHECK1-NEXT: store i64 [[INC]], ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 8 -// CHECK1-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK1: for.end: // CHECK1-NEXT: br label [[FOR_INC13:%.*]] // CHECK1: for.inc13: // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_I]], align 4 // CHECK1-NEXT: [[INC14:%.*]] = add nsw i32 [[TMP18]], 1 // CHECK1-NEXT: store i32 [[INC14]], ptr [[DOTPERMUTED_0_IV_I]], align 4 -// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] // CHECK1: for.end15: // CHECK1-NEXT: ret void // @@ -2342,14 +1985,14 @@ extern "C" void foo10() { // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) // CHECK1-NEXT: store double 4.200000e+01, ptr [[C]], align 8 // CHECK1-NEXT: store ptr [[A]], ptr [[__RANGE3]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE3]], align 8 +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE3]], align 8, !nonnull [[META12]], !align [[META13]] // CHECK1-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP1]], i64 0, i64 0 // CHECK1-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY]], i64 128 // CHECK1-NEXT: store ptr [[ADD_PTR]], ptr [[__END3]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE3]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE3]], align 8, !nonnull [[META12]], !align [[META13]] // CHECK1-NEXT: [[ARRAYDECAY4:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP2]], i64 0, i64 0 // CHECK1-NEXT: store ptr [[ARRAYDECAY4]], ptr [[__BEGIN3]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__RANGE3]], align 8 +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__RANGE3]], align 8, !nonnull [[META12]], !align [[META13]] // CHECK1-NEXT: [[ARRAYDECAY5:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP3]], i64 0, i64 0 // CHECK1-NEXT: store ptr [[ARRAYDECAY5]], ptr [[DOTCAPTURE_EXPR_]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[__END3]], align 8 @@ -2367,14 +2010,14 @@ extern "C" void foo10() { // CHECK1-NEXT: store i64 [[SUB8]], ptr [[DOTCAPTURE_EXPR_7]], align 8 // CHECK1-NEXT: store double 4.200000e+01, ptr [[D]], align 8 // CHECK1-NEXT: store ptr [[B]], ptr [[__RANGE4]], align 8 -// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[__RANGE4]], align 8 +// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[__RANGE4]], align 8, !nonnull [[META12]], !align [[META13]] // CHECK1-NEXT: [[ARRAYDECAY9:%.*]] = getelementptr inbounds [16 x double], ptr [[TMP7]], i64 0, i64 0 // CHECK1-NEXT: [[ADD_PTR10:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY9]], i64 16 // CHECK1-NEXT: store ptr [[ADD_PTR10]], ptr [[__END4]], align 8 -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__RANGE4]], align 8 +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__RANGE4]], align 8, !nonnull [[META12]], !align [[META13]] // CHECK1-NEXT: [[ARRAYDECAY11:%.*]] = getelementptr inbounds [16 x double], ptr [[TMP8]], i64 0, i64 0 // CHECK1-NEXT: store ptr [[ARRAYDECAY11]], ptr [[__BEGIN4]], align 8 -// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__RANGE4]], align 8 +// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__RANGE4]], align 8, !nonnull [[META12]], !align [[META13]] // CHECK1-NEXT: [[ARRAYDECAY13:%.*]] = getelementptr inbounds [16 x double], ptr [[TMP9]], i64 0, i64 0 // CHECK1-NEXT: store ptr [[ARRAYDECAY13]], ptr [[DOTCAPTURE_EXPR_12]], align 8 // CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[__END4]], align 8 @@ -2701,7 +2344,7 @@ extern "C" void foo10() { // CHECK1-NEXT: [[TMP87:%.*]] = load double, ptr [[C]], align 8 // CHECK1-NEXT: [[TMP88:%.*]] = load double, ptr [[AA]], align 8 // CHECK1-NEXT: [[TMP89:%.*]] = load double, ptr [[D]], align 8 -// CHECK1-NEXT: [[TMP90:%.*]] = load ptr, ptr [[BB]], align 8 +// CHECK1-NEXT: [[TMP90:%.*]] = load ptr, ptr [[BB]], align 8, !nonnull [[META12]], !align [[META13]] // CHECK1-NEXT: [[TMP91:%.*]] = load double, ptr [[TMP90]], align 8 // CHECK1-NEXT: [[TMP92:%.*]] = load i32, ptr [[J40]], align 4 // CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP86]], double noundef [[TMP87]], double noundef [[TMP88]], double noundef [[TMP89]], double noundef [[TMP91]], i32 noundef [[TMP92]]) @@ -2756,7 +2399,7 @@ extern "C" void foo10() { // CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], [[TMP4]] // CHECK2-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] // CHECK2: for.end: // CHECK2-NEXT: ret void // @@ -2805,14 +2448,14 @@ extern "C" void foo10() { // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) // CHECK2-NEXT: store double 4.200000e+01, ptr [[C]], align 8 // CHECK2-NEXT: store ptr [[A]], ptr [[__RANGE3]], align 8 -// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE3]], align 8 +// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE3]], align 8, !nonnull [[META4:![0-9]+]], !align [[META5:![0-9]+]] // CHECK2-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP1]], i64 0, i64 0 // CHECK2-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY]], i64 128 // CHECK2-NEXT: store ptr [[ADD_PTR]], ptr [[__END3]], align 8 -// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE3]], align 8 +// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE3]], align 8, !nonnull [[META4]], !align [[META5]] // CHECK2-NEXT: [[ARRAYDECAY4:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP2]], i64 0, i64 0 // CHECK2-NEXT: store ptr [[ARRAYDECAY4]], ptr [[__BEGIN3]], align 8 -// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__RANGE3]], align 8 +// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__RANGE3]], align 8, !nonnull [[META4]], !align [[META5]] // CHECK2-NEXT: [[ARRAYDECAY5:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP3]], i64 0, i64 0 // CHECK2-NEXT: store ptr [[ARRAYDECAY5]], ptr [[DOTCAPTURE_EXPR_]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[__END3]], align 8 @@ -2830,14 +2473,14 @@ extern "C" void foo10() { // CHECK2-NEXT: store i64 [[SUB8]], ptr [[DOTCAPTURE_EXPR_7]], align 8 // CHECK2-NEXT: store double 4.200000e+01, ptr [[D]], align 8 // CHECK2-NEXT: store ptr [[B]], ptr [[__RANGE4]], align 8 -// CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[__RANGE4]], align 8 +// CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[__RANGE4]], align 8, !nonnull [[META4]], !align [[META5]] // CHECK2-NEXT: [[ARRAYDECAY9:%.*]] = getelementptr inbounds [16 x double], ptr [[TMP7]], i64 0, i64 0 // CHECK2-NEXT: [[ADD_PTR10:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY9]], i64 16 // CHECK2-NEXT: store ptr [[ADD_PTR10]], ptr [[__END4]], align 8 -// CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__RANGE4]], align 8 +// CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__RANGE4]], align 8, !nonnull [[META4]], !align [[META5]] // CHECK2-NEXT: [[ARRAYDECAY11:%.*]] = getelementptr inbounds [16 x double], ptr [[TMP8]], i64 0, i64 0 // CHECK2-NEXT: store ptr [[ARRAYDECAY11]], ptr [[__BEGIN4]], align 8 -// CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__RANGE4]], align 8 +// CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__RANGE4]], align 8, !nonnull [[META4]], !align [[META5]] // CHECK2-NEXT: [[ARRAYDECAY13:%.*]] = getelementptr inbounds [16 x double], ptr [[TMP9]], i64 0, i64 0 // CHECK2-NEXT: store ptr [[ARRAYDECAY13]], ptr [[DOTCAPTURE_EXPR_12]], align 8 // CHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[__END4]], align 8 @@ -3164,7 +2807,7 @@ extern "C" void foo10() { // CHECK2-NEXT: [[TMP87:%.*]] = load double, ptr [[C]], align 8 // CHECK2-NEXT: [[TMP88:%.*]] = load double, ptr [[AA]], align 8 // CHECK2-NEXT: [[TMP89:%.*]] = load double, ptr [[D]], align 8 -// CHECK2-NEXT: [[TMP90:%.*]] = load ptr, ptr [[BB]], align 8 +// CHECK2-NEXT: [[TMP90:%.*]] = load ptr, ptr [[BB]], align 8, !nonnull [[META4]], !align [[META5]] // CHECK2-NEXT: [[TMP91:%.*]] = load double, ptr [[TMP90]], align 8 // CHECK2-NEXT: [[TMP92:%.*]] = load i32, ptr [[J40]], align 4 // CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP86]], double noundef [[TMP87]], double noundef [[TMP88]], double noundef [[TMP89]], double noundef [[TMP91]], i32 noundef [[TMP92]]) @@ -3287,14 +2930,14 @@ extern "C" void foo10() { // CHECK2-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4 // CHECK2-NEXT: [[INC:%.*]] = add i32 [[TMP28]], 1 // CHECK2-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_1_IV_I]], align 4 -// CHECK2-NEXT: br label [[FOR_COND16]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND16]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK2: for.end: // CHECK2-NEXT: br label [[FOR_INC22:%.*]] // CHECK2: for.inc22: // CHECK2-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4 // CHECK2-NEXT: [[INC23:%.*]] = add i32 [[TMP29]], 1 // CHECK2-NEXT: store i32 [[INC23]], ptr [[DOTPERMUTED_0_IV_J]], align 4 -// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK2: for.end24: // CHECK2-NEXT: ret void // @@ -3367,7 +3010,7 @@ extern "C" void foo10() { // CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 // CHECK2-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_1_IV_I]], align 4 -// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK2: for.end: // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: @@ -3464,7 +3107,7 @@ extern "C" void foo10() { // CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_I]], align 4 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1 // CHECK2-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_1_IV_I]], align 4 -// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK2: for.end: // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: @@ -3779,28 +3422,28 @@ extern "C" void foo10() { // CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTPERMUTED_3_IV_I]], align 4 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 // CHECK2-NEXT: store i32 [[INC]], ptr [[DOTPERMUTED_3_IV_I]], align 4 -// CHECK2-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND11]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK2: for.end: // CHECK2-NEXT: br label [[FOR_INC16:%.*]] // CHECK2: for.inc16: // CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTPERMUTED_2_IV_L]], align 4 // CHECK2-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP13]], 1 // CHECK2-NEXT: store i32 [[INC17]], ptr [[DOTPERMUTED_2_IV_L]], align 4 -// CHECK2-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK2: for.end18: // CHECK2-NEXT: br label [[FOR_INC19:%.*]] // CHECK2: for.inc19: // CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTPERMUTED_1_IV_K]], align 4 // CHECK2-NEXT: [[INC20:%.*]] = add nsw i32 [[TMP14]], 1 // CHECK2-NEXT: store i32 [[INC20]], ptr [[DOTPERMUTED_1_IV_K]], align 4 -// CHECK2-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK2: for.end21: // CHECK2-NEXT: br label [[FOR_INC22:%.*]] // CHECK2: for.inc22: // CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_J]], align 4 // CHECK2-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP15]], 1 // CHECK2-NEXT: store i32 [[INC23]], ptr [[DOTPERMUTED_0_IV_J]], align 4 -// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK2: for.end24: // CHECK2-NEXT: ret void // @@ -3822,14 +3465,14 @@ extern "C" void foo10() { // CHECK2-NEXT: [[V:%.*]] = alloca ptr, align 8 // CHECK2-NEXT: store double 4.200000e+01, ptr [[C]], align 8 // CHECK2-NEXT: store ptr [[ARR]], ptr [[__RANGE2]], align 8 -// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__RANGE2]], align 8 +// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META4]], !align [[META5]] // CHECK2-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP0]], i64 0, i64 0 // CHECK2-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY]], i64 128 // CHECK2-NEXT: store ptr [[ADD_PTR]], ptr [[__END2]], align 8 -// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE2]], align 8 +// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META4]], !align [[META5]] // CHECK2-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP1]], i64 0, i64 0 // CHECK2-NEXT: store ptr [[ARRAYDECAY1]], ptr [[__BEGIN2]], align 8 -// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE2]], align 8 +// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META4]], !align [[META5]] // CHECK2-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [128 x double], ptr [[TMP2]], i64 0, i64 0 // CHECK2-NEXT: store ptr [[ARRAYDECAY2]], ptr [[DOTCAPTURE_EXPR_]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__END2]], align 8 @@ -3874,7 +3517,7 @@ extern "C" void foo10() { // CHECK2-NEXT: [[TMP12:%.*]] = load ptr, ptr [[__BEGIN2]], align 8 // CHECK2-NEXT: store ptr [[TMP12]], ptr [[V]], align 8 // CHECK2-NEXT: [[TMP13:%.*]] = load double, ptr [[C]], align 8 -// CHECK2-NEXT: [[TMP14:%.*]] = load ptr, ptr [[V]], align 8 +// CHECK2-NEXT: [[TMP14:%.*]] = load ptr, ptr [[V]], align 8, !nonnull [[META4]], !align [[META5]] // CHECK2-NEXT: [[TMP15:%.*]] = load double, ptr [[TMP14]], align 8 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 // CHECK2-NEXT: call void (...) @body(double noundef [[TMP13]], double noundef [[TMP15]], i32 noundef [[TMP16]]) @@ -3883,14 +3526,14 @@ extern "C" void foo10() { // CHECK2-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 8 // CHECK2-NEXT: [[INC:%.*]] = add nsw i64 [[TMP17]], 1 // CHECK2-NEXT: store i64 [[INC]], ptr [[DOTPERMUTED_1_IV___BEGIN2]], align 8 -// CHECK2-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK2: for.end: // CHECK2-NEXT: br label [[FOR_INC13:%.*]] // CHECK2: for.inc13: // CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTPERMUTED_0_IV_I]], align 4 // CHECK2-NEXT: [[INC14:%.*]] = add nsw i32 [[TMP18]], 1 // CHECK2-NEXT: store i32 [[INC14]], ptr [[DOTPERMUTED_0_IV_I]], align 4 -// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] // CHECK2: for.end15: // CHECK2-NEXT: ret void // @@ -3925,22 +3568,21 @@ extern "C" void foo10() { // CHECK2-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTNEW_STEP10:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4 +// CHECK2-NEXT: [[DOTTILE_0_IV_K:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_14:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[DOTCAPTURE_EXPR_16:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i64, align 8 +// CHECK2-NEXT: [[DOTCAPTURE_EXPR_16:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[J:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTFLOOR_0_IV_K:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[DOTTILE_0_IV_K:%.*]] = alloca i32, align 4 +// CHECK2-NEXT: [[DOTTILE_CNT_0_IV_K:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[I49:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[J50:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[DOTFLOOR_0_IV_K51:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[DOTTILE_0_IV_K52:%.*]] = alloca i32, align 4 +// CHECK2-NEXT: [[I35:%.*]] = alloca i32, align 4 +// CHECK2-NEXT: [[J36:%.*]] = alloca i32, align 4 +// CHECK2-NEXT: [[DOTFLOOR_0_IV_K37:%.*]] = alloca i32, align 4 +// CHECK2-NEXT: [[DOTTILE_CNT_0_IV_K38:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) // CHECK2-NEXT: store i32 [[START]], ptr [[START_ADDR]], align 4 // CHECK2-NEXT: store i32 [[END]], ptr [[END_ADDR]], align 4 @@ -3978,630 +3620,452 @@ extern "C" void foo10() { // CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4 // CHECK2-NEXT: [[ADD15:%.*]] = add i32 [[TMP15]], 1 // CHECK2-NEXT: store i32 [[ADD15]], ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[_TMP2]], align 4 -// CHECK2-NEXT: store i32 [[TMP16]], ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4 -// CHECK2-NEXT: [[ADD18:%.*]] = add i32 [[TMP17]], 1 -// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[_TMP2]], align 4 -// CHECK2-NEXT: [[ADD19:%.*]] = add i32 [[TMP18]], 32 -// CHECK2-NEXT: [[CMP:%.*]] = icmp ult i32 [[ADD18]], [[ADD19]] -// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK2: cond.true: -// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4 -// CHECK2-NEXT: [[ADD20:%.*]] = add i32 [[TMP19]], 1 -// CHECK2-NEXT: br label [[COND_END:%.*]] -// CHECK2: cond.false: -// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[_TMP2]], align 4 -// CHECK2-NEXT: [[ADD21:%.*]] = add i32 [[TMP20]], 32 -// CHECK2-NEXT: br label [[COND_END]] -// CHECK2: cond.end: -// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ [[ADD20]], [[COND_TRUE]] ], [ [[ADD21]], [[COND_FALSE]] ] -// CHECK2-NEXT: store i32 [[COND]], ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK2-NEXT: [[SUB23:%.*]] = sub i32 [[TMP21]], [[TMP22]] -// CHECK2-NEXT: [[SUB24:%.*]] = sub i32 [[SUB23]], 1 -// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 -// CHECK2-NEXT: [[ADD25:%.*]] = add i32 [[SUB24]], [[TMP23]] -// CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 -// CHECK2-NEXT: [[DIV26:%.*]] = udiv i32 [[ADD25]], [[TMP24]] -// CHECK2-NEXT: [[CONV:%.*]] = zext i32 [[DIV26]] to i64 -// CHECK2-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK2-NEXT: [[SUB17:%.*]] = sub i32 [[TMP16]], [[TMP17]] +// CHECK2-NEXT: [[SUB18:%.*]] = sub i32 [[SUB17]], 1 +// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 +// CHECK2-NEXT: [[ADD19:%.*]] = add i32 [[SUB18]], [[TMP18]] +// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 +// CHECK2-NEXT: [[DIV20:%.*]] = udiv i32 [[ADD19]], [[TMP19]] +// CHECK2-NEXT: [[CONV:%.*]] = zext i32 [[DIV20]] to i64 +// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK2-NEXT: [[SUB21:%.*]] = sub i32 [[TMP20]], [[TMP21]] +// CHECK2-NEXT: [[SUB22:%.*]] = sub i32 [[SUB21]], 1 +// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[ADD23:%.*]] = add i32 [[SUB22]], [[TMP22]] +// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[DIV24:%.*]] = udiv i32 [[ADD23]], [[TMP23]] +// CHECK2-NEXT: [[CONV25:%.*]] = zext i32 [[DIV24]] to i64 +// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV25]] +// CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB26:%.*]] = sub i32 [[TMP24]], -31 +// CHECK2-NEXT: [[DIV27:%.*]] = udiv i32 [[SUB26]], 32 +// CHECK2-NEXT: [[CONV28:%.*]] = zext i32 [[DIV27]] to i64 +// CHECK2-NEXT: [[MUL29:%.*]] = mul nsw i64 [[MUL]], [[CONV28]] +// CHECK2-NEXT: [[MUL30:%.*]] = mul nsw i64 [[MUL29]], 32 +// CHECK2-NEXT: [[SUB31:%.*]] = sub nsw i64 [[MUL30]], 1 +// CHECK2-NEXT: store i64 [[SUB31]], ptr [[DOTCAPTURE_EXPR_16]], align 8 +// CHECK2-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK2-NEXT: store i32 [[TMP25]], ptr [[I]], align 4 // CHECK2-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK2-NEXT: [[SUB27:%.*]] = sub i32 [[TMP25]], [[TMP26]] -// CHECK2-NEXT: [[SUB28:%.*]] = sub i32 [[SUB27]], 1 -// CHECK2-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[ADD29:%.*]] = add i32 [[SUB28]], [[TMP27]] -// CHECK2-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[DIV30:%.*]] = udiv i32 [[ADD29]], [[TMP28]] -// CHECK2-NEXT: [[CONV31:%.*]] = zext i32 [[DIV30]] to i64 -// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV31]] -// CHECK2-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB32:%.*]] = sub i32 [[TMP29]], -31 -// CHECK2-NEXT: [[DIV33:%.*]] = udiv i32 [[SUB32]], 32 -// CHECK2-NEXT: [[CONV34:%.*]] = zext i32 [[DIV33]] to i64 -// CHECK2-NEXT: [[MUL35:%.*]] = mul nsw i64 [[MUL]], [[CONV34]] -// CHECK2-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB36:%.*]] = sub i32 [[TMP30]], [[TMP31]] -// CHECK2-NEXT: [[SUB37:%.*]] = sub i32 [[SUB36]], 1 -// CHECK2-NEXT: [[ADD38:%.*]] = add i32 [[SUB37]], 1 -// CHECK2-NEXT: [[DIV39:%.*]] = udiv i32 [[ADD38]], 1 -// CHECK2-NEXT: [[CONV40:%.*]] = zext i32 [[DIV39]] to i64 -// CHECK2-NEXT: [[MUL41:%.*]] = mul nsw i64 [[MUL35]], [[CONV40]] -// CHECK2-NEXT: [[SUB42:%.*]] = sub nsw i64 [[MUL41]], 1 -// CHECK2-NEXT: store i64 [[SUB42]], ptr [[DOTCAPTURE_EXPR_22]], align 8 -// CHECK2-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK2-NEXT: store i32 [[TMP32]], ptr [[I]], align 4 -// CHECK2-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK2-NEXT: store i32 [[TMP33]], ptr [[J]], align 4 +// CHECK2-NEXT: store i32 [[TMP26]], ptr [[J]], align 4 // CHECK2-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_K]], align 4 -// CHECK2-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: store i32 [[TMP34]], ptr [[DOTTILE_0_IV_K]], align 4 -// CHECK2-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK2-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK2-NEXT: [[CMP43:%.*]] = icmp slt i32 [[TMP35]], [[TMP36]] -// CHECK2-NEXT: br i1 [[CMP43]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK2-NEXT: store i32 0, ptr [[DOTTILE_CNT_0_IV_K]], align 4 +// CHECK2-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK2-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP27]], [[TMP28]] +// CHECK2-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK2: land.lhs.true: -// CHECK2-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK2-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK2-NEXT: [[CMP44:%.*]] = icmp slt i32 [[TMP37]], [[TMP38]] -// CHECK2-NEXT: br i1 [[CMP44]], label [[LAND_LHS_TRUE45:%.*]], label [[OMP_PRECOND_END]] -// CHECK2: land.lhs.true45: -// CHECK2-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[CMP46:%.*]] = icmp ult i32 0, [[TMP39]] -// CHECK2-NEXT: br i1 [[CMP46]], label [[LAND_LHS_TRUE47:%.*]], label [[OMP_PRECOND_END]] -// CHECK2: land.lhs.true47: -// CHECK2-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[CMP48:%.*]] = icmp ult i32 [[TMP40]], [[TMP41]] -// CHECK2-NEXT: br i1 [[CMP48]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// CHECK2-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK2-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK2-NEXT: [[CMP32:%.*]] = icmp slt i32 [[TMP29]], [[TMP30]] +// CHECK2-NEXT: br i1 [[CMP32]], label [[LAND_LHS_TRUE33:%.*]], label [[OMP_PRECOND_END]] +// CHECK2: land.lhs.true33: +// CHECK2-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[CMP34:%.*]] = icmp ult i32 0, [[TMP31]] +// CHECK2-NEXT: br i1 [[CMP34]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] // CHECK2: omp.precond.then: // CHECK2-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 -// CHECK2-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8 -// CHECK2-NEXT: store i64 [[TMP42]], ptr [[DOTOMP_UB]], align 8 +// CHECK2-NEXT: [[TMP32:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_16]], align 8 +// CHECK2-NEXT: store i64 [[TMP32]], ptr [[DOTOMP_UB]], align 8 // CHECK2-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 // CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK2-NEXT: [[TMP43:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 -// CHECK2-NEXT: [[TMP44:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8 -// CHECK2-NEXT: [[CMP53:%.*]] = icmp sgt i64 [[TMP43]], [[TMP44]] -// CHECK2-NEXT: br i1 [[CMP53]], label [[COND_TRUE54:%.*]], label [[COND_FALSE55:%.*]] -// CHECK2: cond.true54: -// CHECK2-NEXT: [[TMP45:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8 -// CHECK2-NEXT: br label [[COND_END56:%.*]] -// CHECK2: cond.false55: -// CHECK2-NEXT: [[TMP46:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 -// CHECK2-NEXT: br label [[COND_END56]] -// CHECK2: cond.end56: -// CHECK2-NEXT: [[COND57:%.*]] = phi i64 [ [[TMP45]], [[COND_TRUE54]] ], [ [[TMP46]], [[COND_FALSE55]] ] -// CHECK2-NEXT: store i64 [[COND57]], ptr [[DOTOMP_UB]], align 8 -// CHECK2-NEXT: [[TMP47:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 -// CHECK2-NEXT: store i64 [[TMP47]], ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[TMP33:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 +// CHECK2-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_16]], align 8 +// CHECK2-NEXT: [[CMP39:%.*]] = icmp sgt i64 [[TMP33]], [[TMP34]] +// CHECK2-NEXT: br i1 [[CMP39]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK2: cond.true: +// CHECK2-NEXT: [[TMP35:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_16]], align 8 +// CHECK2-NEXT: br label [[COND_END:%.*]] +// CHECK2: cond.false: +// CHECK2-NEXT: [[TMP36:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 +// CHECK2-NEXT: br label [[COND_END]] +// CHECK2: cond.end: +// CHECK2-NEXT: [[COND:%.*]] = phi i64 [ [[TMP35]], [[COND_TRUE]] ], [ [[TMP36]], [[COND_FALSE]] ] +// CHECK2-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 +// CHECK2-NEXT: [[TMP37:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 +// CHECK2-NEXT: store i64 [[TMP37]], ptr [[DOTOMP_IV]], align 8 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP48:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP49:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 -// CHECK2-NEXT: [[CMP58:%.*]] = icmp sle i64 [[TMP48]], [[TMP49]] -// CHECK2-NEXT: br i1 [[CMP58]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK2-NEXT: [[TMP38:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 +// CHECK2-NEXT: [[CMP40:%.*]] = icmp sle i64 [[TMP38]], [[TMP39]] +// CHECK2-NEXT: br i1 [[CMP40]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK2-NEXT: [[CONV59:%.*]] = sext i32 [[TMP50]] to i64 -// CHECK2-NEXT: [[TMP51:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP52:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK2-NEXT: [[TMP53:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK2-NEXT: [[SUB60:%.*]] = sub i32 [[TMP52]], [[TMP53]] -// CHECK2-NEXT: [[SUB61:%.*]] = sub i32 [[SUB60]], 1 +// CHECK2-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK2-NEXT: [[CONV41:%.*]] = sext i32 [[TMP40]] to i64 +// CHECK2-NEXT: [[TMP41:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK2-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK2-NEXT: [[SUB42:%.*]] = sub i32 [[TMP42]], [[TMP43]] +// CHECK2-NEXT: [[SUB43:%.*]] = sub i32 [[SUB42]], 1 +// CHECK2-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[ADD44:%.*]] = add i32 [[SUB43]], [[TMP44]] +// CHECK2-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[DIV45:%.*]] = udiv i32 [[ADD44]], [[TMP45]] +// CHECK2-NEXT: [[MUL46:%.*]] = mul i32 1, [[DIV45]] +// CHECK2-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB47:%.*]] = sub i32 [[TMP46]], -31 +// CHECK2-NEXT: [[DIV48:%.*]] = udiv i32 [[SUB47]], 32 +// CHECK2-NEXT: [[MUL49:%.*]] = mul i32 [[MUL46]], [[DIV48]] +// CHECK2-NEXT: [[MUL50:%.*]] = mul i32 [[MUL49]], 32 +// CHECK2-NEXT: [[CONV51:%.*]] = zext i32 [[MUL50]] to i64 +// CHECK2-NEXT: [[DIV52:%.*]] = sdiv i64 [[TMP41]], [[CONV51]] +// CHECK2-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 +// CHECK2-NEXT: [[CONV53:%.*]] = sext i32 [[TMP47]] to i64 +// CHECK2-NEXT: [[MUL54:%.*]] = mul nsw i64 [[DIV52]], [[CONV53]] +// CHECK2-NEXT: [[ADD55:%.*]] = add nsw i64 [[CONV41]], [[MUL54]] +// CHECK2-NEXT: [[CONV56:%.*]] = trunc i64 [[ADD55]] to i32 +// CHECK2-NEXT: store i32 [[CONV56]], ptr [[I35]], align 4 +// CHECK2-NEXT: [[TMP48:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK2-NEXT: [[CONV57:%.*]] = sext i32 [[TMP48]] to i64 +// CHECK2-NEXT: [[TMP49:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[TMP50:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[TMP51:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK2-NEXT: [[TMP52:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK2-NEXT: [[SUB58:%.*]] = sub i32 [[TMP51]], [[TMP52]] +// CHECK2-NEXT: [[SUB59:%.*]] = sub i32 [[SUB58]], 1 +// CHECK2-NEXT: [[TMP53:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[ADD60:%.*]] = add i32 [[SUB59]], [[TMP53]] // CHECK2-NEXT: [[TMP54:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[ADD62:%.*]] = add i32 [[SUB61]], [[TMP54]] -// CHECK2-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[DIV63:%.*]] = udiv i32 [[ADD62]], [[TMP55]] -// CHECK2-NEXT: [[MUL64:%.*]] = mul i32 1, [[DIV63]] -// CHECK2-NEXT: [[TMP56:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB65:%.*]] = sub i32 [[TMP56]], -31 -// CHECK2-NEXT: [[DIV66:%.*]] = udiv i32 [[SUB65]], 32 -// CHECK2-NEXT: [[MUL67:%.*]] = mul i32 [[MUL64]], [[DIV66]] -// CHECK2-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB68:%.*]] = sub i32 [[TMP57]], [[TMP58]] -// CHECK2-NEXT: [[SUB69:%.*]] = sub i32 [[SUB68]], 1 -// CHECK2-NEXT: [[ADD70:%.*]] = add i32 [[SUB69]], 1 -// CHECK2-NEXT: [[DIV71:%.*]] = udiv i32 [[ADD70]], 1 -// CHECK2-NEXT: [[MUL72:%.*]] = mul i32 [[MUL67]], [[DIV71]] -// CHECK2-NEXT: [[CONV73:%.*]] = zext i32 [[MUL72]] to i64 -// CHECK2-NEXT: [[DIV74:%.*]] = sdiv i64 [[TMP51]], [[CONV73]] -// CHECK2-NEXT: [[TMP59:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 -// CHECK2-NEXT: [[CONV75:%.*]] = sext i32 [[TMP59]] to i64 -// CHECK2-NEXT: [[MUL76:%.*]] = mul nsw i64 [[DIV74]], [[CONV75]] -// CHECK2-NEXT: [[ADD77:%.*]] = add nsw i64 [[CONV59]], [[MUL76]] -// CHECK2-NEXT: [[CONV78:%.*]] = trunc i64 [[ADD77]] to i32 -// CHECK2-NEXT: store i32 [[CONV78]], ptr [[I49]], align 4 -// CHECK2-NEXT: [[TMP60:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK2-NEXT: [[CONV79:%.*]] = sext i32 [[TMP60]] to i64 -// CHECK2-NEXT: [[TMP61:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP62:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP63:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK2-NEXT: [[TMP64:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK2-NEXT: [[SUB80:%.*]] = sub i32 [[TMP63]], [[TMP64]] -// CHECK2-NEXT: [[SUB81:%.*]] = sub i32 [[SUB80]], 1 -// CHECK2-NEXT: [[TMP65:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[ADD82:%.*]] = add i32 [[SUB81]], [[TMP65]] -// CHECK2-NEXT: [[TMP66:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[DIV83:%.*]] = udiv i32 [[ADD82]], [[TMP66]] -// CHECK2-NEXT: [[MUL84:%.*]] = mul i32 1, [[DIV83]] -// CHECK2-NEXT: [[TMP67:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB85:%.*]] = sub i32 [[TMP67]], -31 -// CHECK2-NEXT: [[DIV86:%.*]] = udiv i32 [[SUB85]], 32 -// CHECK2-NEXT: [[MUL87:%.*]] = mul i32 [[MUL84]], [[DIV86]] -// CHECK2-NEXT: [[TMP68:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP69:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB88:%.*]] = sub i32 [[TMP68]], [[TMP69]] -// CHECK2-NEXT: [[SUB89:%.*]] = sub i32 [[SUB88]], 1 -// CHECK2-NEXT: [[ADD90:%.*]] = add i32 [[SUB89]], 1 -// CHECK2-NEXT: [[DIV91:%.*]] = udiv i32 [[ADD90]], 1 -// CHECK2-NEXT: [[MUL92:%.*]] = mul i32 [[MUL87]], [[DIV91]] -// CHECK2-NEXT: [[CONV93:%.*]] = zext i32 [[MUL92]] to i64 -// CHECK2-NEXT: [[DIV94:%.*]] = sdiv i64 [[TMP62]], [[CONV93]] +// CHECK2-NEXT: [[DIV61:%.*]] = udiv i32 [[ADD60]], [[TMP54]] +// CHECK2-NEXT: [[MUL62:%.*]] = mul i32 1, [[DIV61]] +// CHECK2-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB63:%.*]] = sub i32 [[TMP55]], -31 +// CHECK2-NEXT: [[DIV64:%.*]] = udiv i32 [[SUB63]], 32 +// CHECK2-NEXT: [[MUL65:%.*]] = mul i32 [[MUL62]], [[DIV64]] +// CHECK2-NEXT: [[MUL66:%.*]] = mul i32 [[MUL65]], 32 +// CHECK2-NEXT: [[CONV67:%.*]] = zext i32 [[MUL66]] to i64 +// CHECK2-NEXT: [[DIV68:%.*]] = sdiv i64 [[TMP50]], [[CONV67]] +// CHECK2-NEXT: [[TMP56:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK2-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK2-NEXT: [[SUB69:%.*]] = sub i32 [[TMP56]], [[TMP57]] +// CHECK2-NEXT: [[SUB70:%.*]] = sub i32 [[SUB69]], 1 +// CHECK2-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[ADD71:%.*]] = add i32 [[SUB70]], [[TMP58]] +// CHECK2-NEXT: [[TMP59:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[DIV72:%.*]] = udiv i32 [[ADD71]], [[TMP59]] +// CHECK2-NEXT: [[MUL73:%.*]] = mul i32 1, [[DIV72]] +// CHECK2-NEXT: [[TMP60:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB74:%.*]] = sub i32 [[TMP60]], -31 +// CHECK2-NEXT: [[DIV75:%.*]] = udiv i32 [[SUB74]], 32 +// CHECK2-NEXT: [[MUL76:%.*]] = mul i32 [[MUL73]], [[DIV75]] +// CHECK2-NEXT: [[MUL77:%.*]] = mul i32 [[MUL76]], 32 +// CHECK2-NEXT: [[CONV78:%.*]] = zext i32 [[MUL77]] to i64 +// CHECK2-NEXT: [[MUL79:%.*]] = mul nsw i64 [[DIV68]], [[CONV78]] +// CHECK2-NEXT: [[SUB80:%.*]] = sub nsw i64 [[TMP49]], [[MUL79]] +// CHECK2-NEXT: [[TMP61:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB81:%.*]] = sub i32 [[TMP61]], -31 +// CHECK2-NEXT: [[DIV82:%.*]] = udiv i32 [[SUB81]], 32 +// CHECK2-NEXT: [[MUL83:%.*]] = mul i32 1, [[DIV82]] +// CHECK2-NEXT: [[MUL84:%.*]] = mul i32 [[MUL83]], 32 +// CHECK2-NEXT: [[CONV85:%.*]] = zext i32 [[MUL84]] to i64 +// CHECK2-NEXT: [[DIV86:%.*]] = sdiv i64 [[SUB80]], [[CONV85]] +// CHECK2-NEXT: [[TMP62:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[CONV87:%.*]] = sext i32 [[TMP62]] to i64 +// CHECK2-NEXT: [[MUL88:%.*]] = mul nsw i64 [[DIV86]], [[CONV87]] +// CHECK2-NEXT: [[ADD89:%.*]] = add nsw i64 [[CONV57]], [[MUL88]] +// CHECK2-NEXT: [[CONV90:%.*]] = trunc i64 [[ADD89]] to i32 +// CHECK2-NEXT: store i32 [[CONV90]], ptr [[J36]], align 4 +// CHECK2-NEXT: [[TMP63:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[TMP64:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[TMP65:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK2-NEXT: [[TMP66:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK2-NEXT: [[SUB91:%.*]] = sub i32 [[TMP65]], [[TMP66]] +// CHECK2-NEXT: [[SUB92:%.*]] = sub i32 [[SUB91]], 1 +// CHECK2-NEXT: [[TMP67:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[ADD93:%.*]] = add i32 [[SUB92]], [[TMP67]] +// CHECK2-NEXT: [[TMP68:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[DIV94:%.*]] = udiv i32 [[ADD93]], [[TMP68]] +// CHECK2-NEXT: [[MUL95:%.*]] = mul i32 1, [[DIV94]] +// CHECK2-NEXT: [[TMP69:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB96:%.*]] = sub i32 [[TMP69]], -31 +// CHECK2-NEXT: [[DIV97:%.*]] = udiv i32 [[SUB96]], 32 +// CHECK2-NEXT: [[MUL98:%.*]] = mul i32 [[MUL95]], [[DIV97]] +// CHECK2-NEXT: [[MUL99:%.*]] = mul i32 [[MUL98]], 32 +// CHECK2-NEXT: [[CONV100:%.*]] = zext i32 [[MUL99]] to i64 +// CHECK2-NEXT: [[DIV101:%.*]] = sdiv i64 [[TMP64]], [[CONV100]] // CHECK2-NEXT: [[TMP70:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 // CHECK2-NEXT: [[TMP71:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK2-NEXT: [[SUB95:%.*]] = sub i32 [[TMP70]], [[TMP71]] -// CHECK2-NEXT: [[SUB96:%.*]] = sub i32 [[SUB95]], 1 +// CHECK2-NEXT: [[SUB102:%.*]] = sub i32 [[TMP70]], [[TMP71]] +// CHECK2-NEXT: [[SUB103:%.*]] = sub i32 [[SUB102]], 1 // CHECK2-NEXT: [[TMP72:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[ADD97:%.*]] = add i32 [[SUB96]], [[TMP72]] +// CHECK2-NEXT: [[ADD104:%.*]] = add i32 [[SUB103]], [[TMP72]] // CHECK2-NEXT: [[TMP73:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[DIV98:%.*]] = udiv i32 [[ADD97]], [[TMP73]] -// CHECK2-NEXT: [[MUL99:%.*]] = mul i32 1, [[DIV98]] +// CHECK2-NEXT: [[DIV105:%.*]] = udiv i32 [[ADD104]], [[TMP73]] +// CHECK2-NEXT: [[MUL106:%.*]] = mul i32 1, [[DIV105]] // CHECK2-NEXT: [[TMP74:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB100:%.*]] = sub i32 [[TMP74]], -31 -// CHECK2-NEXT: [[DIV101:%.*]] = udiv i32 [[SUB100]], 32 -// CHECK2-NEXT: [[MUL102:%.*]] = mul i32 [[MUL99]], [[DIV101]] -// CHECK2-NEXT: [[TMP75:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP76:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB103:%.*]] = sub i32 [[TMP75]], [[TMP76]] -// CHECK2-NEXT: [[SUB104:%.*]] = sub i32 [[SUB103]], 1 -// CHECK2-NEXT: [[ADD105:%.*]] = add i32 [[SUB104]], 1 -// CHECK2-NEXT: [[DIV106:%.*]] = udiv i32 [[ADD105]], 1 -// CHECK2-NEXT: [[MUL107:%.*]] = mul i32 [[MUL102]], [[DIV106]] -// CHECK2-NEXT: [[CONV108:%.*]] = zext i32 [[MUL107]] to i64 -// CHECK2-NEXT: [[MUL109:%.*]] = mul nsw i64 [[DIV94]], [[CONV108]] -// CHECK2-NEXT: [[SUB110:%.*]] = sub nsw i64 [[TMP61]], [[MUL109]] -// CHECK2-NEXT: [[TMP77:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB111:%.*]] = sub i32 [[TMP77]], -31 -// CHECK2-NEXT: [[DIV112:%.*]] = udiv i32 [[SUB111]], 32 -// CHECK2-NEXT: [[MUL113:%.*]] = mul i32 1, [[DIV112]] -// CHECK2-NEXT: [[TMP78:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP79:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB114:%.*]] = sub i32 [[TMP78]], [[TMP79]] +// CHECK2-NEXT: [[SUB107:%.*]] = sub i32 [[TMP74]], -31 +// CHECK2-NEXT: [[DIV108:%.*]] = udiv i32 [[SUB107]], 32 +// CHECK2-NEXT: [[MUL109:%.*]] = mul i32 [[MUL106]], [[DIV108]] +// CHECK2-NEXT: [[MUL110:%.*]] = mul i32 [[MUL109]], 32 +// CHECK2-NEXT: [[CONV111:%.*]] = zext i32 [[MUL110]] to i64 +// CHECK2-NEXT: [[MUL112:%.*]] = mul nsw i64 [[DIV101]], [[CONV111]] +// CHECK2-NEXT: [[SUB113:%.*]] = sub nsw i64 [[TMP63]], [[MUL112]] +// CHECK2-NEXT: [[TMP75:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[TMP76:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[TMP77:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK2-NEXT: [[TMP78:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK2-NEXT: [[SUB114:%.*]] = sub i32 [[TMP77]], [[TMP78]] // CHECK2-NEXT: [[SUB115:%.*]] = sub i32 [[SUB114]], 1 -// CHECK2-NEXT: [[ADD116:%.*]] = add i32 [[SUB115]], 1 -// CHECK2-NEXT: [[DIV117:%.*]] = udiv i32 [[ADD116]], 1 -// CHECK2-NEXT: [[MUL118:%.*]] = mul i32 [[MUL113]], [[DIV117]] -// CHECK2-NEXT: [[CONV119:%.*]] = zext i32 [[MUL118]] to i64 -// CHECK2-NEXT: [[DIV120:%.*]] = sdiv i64 [[SUB110]], [[CONV119]] +// CHECK2-NEXT: [[TMP79:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[ADD116:%.*]] = add i32 [[SUB115]], [[TMP79]] // CHECK2-NEXT: [[TMP80:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[CONV121:%.*]] = sext i32 [[TMP80]] to i64 -// CHECK2-NEXT: [[MUL122:%.*]] = mul nsw i64 [[DIV120]], [[CONV121]] -// CHECK2-NEXT: [[ADD123:%.*]] = add nsw i64 [[CONV79]], [[MUL122]] -// CHECK2-NEXT: [[CONV124:%.*]] = trunc i64 [[ADD123]] to i32 -// CHECK2-NEXT: store i32 [[CONV124]], ptr [[J50]], align 4 -// CHECK2-NEXT: [[TMP81:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP82:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP83:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK2-NEXT: [[TMP84:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK2-NEXT: [[SUB125:%.*]] = sub i32 [[TMP83]], [[TMP84]] +// CHECK2-NEXT: [[DIV117:%.*]] = udiv i32 [[ADD116]], [[TMP80]] +// CHECK2-NEXT: [[MUL118:%.*]] = mul i32 1, [[DIV117]] +// CHECK2-NEXT: [[TMP81:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB119:%.*]] = sub i32 [[TMP81]], -31 +// CHECK2-NEXT: [[DIV120:%.*]] = udiv i32 [[SUB119]], 32 +// CHECK2-NEXT: [[MUL121:%.*]] = mul i32 [[MUL118]], [[DIV120]] +// CHECK2-NEXT: [[MUL122:%.*]] = mul i32 [[MUL121]], 32 +// CHECK2-NEXT: [[CONV123:%.*]] = zext i32 [[MUL122]] to i64 +// CHECK2-NEXT: [[DIV124:%.*]] = sdiv i64 [[TMP76]], [[CONV123]] +// CHECK2-NEXT: [[TMP82:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK2-NEXT: [[TMP83:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK2-NEXT: [[SUB125:%.*]] = sub i32 [[TMP82]], [[TMP83]] // CHECK2-NEXT: [[SUB126:%.*]] = sub i32 [[SUB125]], 1 +// CHECK2-NEXT: [[TMP84:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[ADD127:%.*]] = add i32 [[SUB126]], [[TMP84]] // CHECK2-NEXT: [[TMP85:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[ADD127:%.*]] = add i32 [[SUB126]], [[TMP85]] -// CHECK2-NEXT: [[TMP86:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[DIV128:%.*]] = udiv i32 [[ADD127]], [[TMP86]] +// CHECK2-NEXT: [[DIV128:%.*]] = udiv i32 [[ADD127]], [[TMP85]] // CHECK2-NEXT: [[MUL129:%.*]] = mul i32 1, [[DIV128]] -// CHECK2-NEXT: [[TMP87:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB130:%.*]] = sub i32 [[TMP87]], -31 +// CHECK2-NEXT: [[TMP86:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB130:%.*]] = sub i32 [[TMP86]], -31 // CHECK2-NEXT: [[DIV131:%.*]] = udiv i32 [[SUB130]], 32 // CHECK2-NEXT: [[MUL132:%.*]] = mul i32 [[MUL129]], [[DIV131]] -// CHECK2-NEXT: [[TMP88:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP89:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB133:%.*]] = sub i32 [[TMP88]], [[TMP89]] -// CHECK2-NEXT: [[SUB134:%.*]] = sub i32 [[SUB133]], 1 -// CHECK2-NEXT: [[ADD135:%.*]] = add i32 [[SUB134]], 1 -// CHECK2-NEXT: [[DIV136:%.*]] = udiv i32 [[ADD135]], 1 -// CHECK2-NEXT: [[MUL137:%.*]] = mul i32 [[MUL132]], [[DIV136]] -// CHECK2-NEXT: [[CONV138:%.*]] = zext i32 [[MUL137]] to i64 -// CHECK2-NEXT: [[DIV139:%.*]] = sdiv i64 [[TMP82]], [[CONV138]] -// CHECK2-NEXT: [[TMP90:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK2-NEXT: [[TMP91:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK2-NEXT: [[SUB140:%.*]] = sub i32 [[TMP90]], [[TMP91]] -// CHECK2-NEXT: [[SUB141:%.*]] = sub i32 [[SUB140]], 1 -// CHECK2-NEXT: [[TMP92:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[ADD142:%.*]] = add i32 [[SUB141]], [[TMP92]] +// CHECK2-NEXT: [[MUL133:%.*]] = mul i32 [[MUL132]], 32 +// CHECK2-NEXT: [[CONV134:%.*]] = zext i32 [[MUL133]] to i64 +// CHECK2-NEXT: [[MUL135:%.*]] = mul nsw i64 [[DIV124]], [[CONV134]] +// CHECK2-NEXT: [[SUB136:%.*]] = sub nsw i64 [[TMP75]], [[MUL135]] +// CHECK2-NEXT: [[TMP87:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB137:%.*]] = sub i32 [[TMP87]], -31 +// CHECK2-NEXT: [[DIV138:%.*]] = udiv i32 [[SUB137]], 32 +// CHECK2-NEXT: [[MUL139:%.*]] = mul i32 1, [[DIV138]] +// CHECK2-NEXT: [[MUL140:%.*]] = mul i32 [[MUL139]], 32 +// CHECK2-NEXT: [[CONV141:%.*]] = zext i32 [[MUL140]] to i64 +// CHECK2-NEXT: [[DIV142:%.*]] = sdiv i64 [[SUB136]], [[CONV141]] +// CHECK2-NEXT: [[TMP88:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB143:%.*]] = sub i32 [[TMP88]], -31 +// CHECK2-NEXT: [[DIV144:%.*]] = udiv i32 [[SUB143]], 32 +// CHECK2-NEXT: [[MUL145:%.*]] = mul i32 1, [[DIV144]] +// CHECK2-NEXT: [[MUL146:%.*]] = mul i32 [[MUL145]], 32 +// CHECK2-NEXT: [[CONV147:%.*]] = zext i32 [[MUL146]] to i64 +// CHECK2-NEXT: [[MUL148:%.*]] = mul nsw i64 [[DIV142]], [[CONV147]] +// CHECK2-NEXT: [[SUB149:%.*]] = sub nsw i64 [[SUB113]], [[MUL148]] +// CHECK2-NEXT: [[DIV150:%.*]] = sdiv i64 [[SUB149]], 32 +// CHECK2-NEXT: [[MUL151:%.*]] = mul nsw i64 [[DIV150]], 32 +// CHECK2-NEXT: [[ADD152:%.*]] = add nsw i64 0, [[MUL151]] +// CHECK2-NEXT: [[CONV153:%.*]] = trunc i64 [[ADD152]] to i32 +// CHECK2-NEXT: store i32 [[CONV153]], ptr [[DOTFLOOR_0_IV_K37]], align 4 +// CHECK2-NEXT: [[TMP89:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[TMP90:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[TMP91:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK2-NEXT: [[TMP92:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK2-NEXT: [[SUB154:%.*]] = sub i32 [[TMP91]], [[TMP92]] +// CHECK2-NEXT: [[SUB155:%.*]] = sub i32 [[SUB154]], 1 // CHECK2-NEXT: [[TMP93:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[DIV143:%.*]] = udiv i32 [[ADD142]], [[TMP93]] -// CHECK2-NEXT: [[MUL144:%.*]] = mul i32 1, [[DIV143]] -// CHECK2-NEXT: [[TMP94:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB145:%.*]] = sub i32 [[TMP94]], -31 -// CHECK2-NEXT: [[DIV146:%.*]] = udiv i32 [[SUB145]], 32 -// CHECK2-NEXT: [[MUL147:%.*]] = mul i32 [[MUL144]], [[DIV146]] -// CHECK2-NEXT: [[TMP95:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP96:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB148:%.*]] = sub i32 [[TMP95]], [[TMP96]] -// CHECK2-NEXT: [[SUB149:%.*]] = sub i32 [[SUB148]], 1 -// CHECK2-NEXT: [[ADD150:%.*]] = add i32 [[SUB149]], 1 -// CHECK2-NEXT: [[DIV151:%.*]] = udiv i32 [[ADD150]], 1 -// CHECK2-NEXT: [[MUL152:%.*]] = mul i32 [[MUL147]], [[DIV151]] -// CHECK2-NEXT: [[CONV153:%.*]] = zext i32 [[MUL152]] to i64 -// CHECK2-NEXT: [[MUL154:%.*]] = mul nsw i64 [[DIV139]], [[CONV153]] -// CHECK2-NEXT: [[SUB155:%.*]] = sub nsw i64 [[TMP81]], [[MUL154]] -// CHECK2-NEXT: [[TMP97:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP98:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP99:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK2-NEXT: [[TMP100:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK2-NEXT: [[SUB156:%.*]] = sub i32 [[TMP99]], [[TMP100]] -// CHECK2-NEXT: [[SUB157:%.*]] = sub i32 [[SUB156]], 1 -// CHECK2-NEXT: [[TMP101:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[ADD158:%.*]] = add i32 [[SUB157]], [[TMP101]] -// CHECK2-NEXT: [[TMP102:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[DIV159:%.*]] = udiv i32 [[ADD158]], [[TMP102]] -// CHECK2-NEXT: [[MUL160:%.*]] = mul i32 1, [[DIV159]] -// CHECK2-NEXT: [[TMP103:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB161:%.*]] = sub i32 [[TMP103]], -31 -// CHECK2-NEXT: [[DIV162:%.*]] = udiv i32 [[SUB161]], 32 -// CHECK2-NEXT: [[MUL163:%.*]] = mul i32 [[MUL160]], [[DIV162]] -// CHECK2-NEXT: [[TMP104:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP105:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB164:%.*]] = sub i32 [[TMP104]], [[TMP105]] -// CHECK2-NEXT: [[SUB165:%.*]] = sub i32 [[SUB164]], 1 -// CHECK2-NEXT: [[ADD166:%.*]] = add i32 [[SUB165]], 1 -// CHECK2-NEXT: [[DIV167:%.*]] = udiv i32 [[ADD166]], 1 -// CHECK2-NEXT: [[MUL168:%.*]] = mul i32 [[MUL163]], [[DIV167]] -// CHECK2-NEXT: [[CONV169:%.*]] = zext i32 [[MUL168]] to i64 -// CHECK2-NEXT: [[DIV170:%.*]] = sdiv i64 [[TMP98]], [[CONV169]] -// CHECK2-NEXT: [[TMP106:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK2-NEXT: [[TMP107:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK2-NEXT: [[SUB171:%.*]] = sub i32 [[TMP106]], [[TMP107]] -// CHECK2-NEXT: [[SUB172:%.*]] = sub i32 [[SUB171]], 1 -// CHECK2-NEXT: [[TMP108:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[ADD173:%.*]] = add i32 [[SUB172]], [[TMP108]] -// CHECK2-NEXT: [[TMP109:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[DIV174:%.*]] = udiv i32 [[ADD173]], [[TMP109]] -// CHECK2-NEXT: [[MUL175:%.*]] = mul i32 1, [[DIV174]] -// CHECK2-NEXT: [[TMP110:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB176:%.*]] = sub i32 [[TMP110]], -31 -// CHECK2-NEXT: [[DIV177:%.*]] = udiv i32 [[SUB176]], 32 -// CHECK2-NEXT: [[MUL178:%.*]] = mul i32 [[MUL175]], [[DIV177]] -// CHECK2-NEXT: [[TMP111:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP112:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB179:%.*]] = sub i32 [[TMP111]], [[TMP112]] -// CHECK2-NEXT: [[SUB180:%.*]] = sub i32 [[SUB179]], 1 -// CHECK2-NEXT: [[ADD181:%.*]] = add i32 [[SUB180]], 1 -// CHECK2-NEXT: [[DIV182:%.*]] = udiv i32 [[ADD181]], 1 -// CHECK2-NEXT: [[MUL183:%.*]] = mul i32 [[MUL178]], [[DIV182]] -// CHECK2-NEXT: [[CONV184:%.*]] = zext i32 [[MUL183]] to i64 -// CHECK2-NEXT: [[MUL185:%.*]] = mul nsw i64 [[DIV170]], [[CONV184]] -// CHECK2-NEXT: [[SUB186:%.*]] = sub nsw i64 [[TMP97]], [[MUL185]] +// CHECK2-NEXT: [[ADD156:%.*]] = add i32 [[SUB155]], [[TMP93]] +// CHECK2-NEXT: [[TMP94:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[DIV157:%.*]] = udiv i32 [[ADD156]], [[TMP94]] +// CHECK2-NEXT: [[MUL158:%.*]] = mul i32 1, [[DIV157]] +// CHECK2-NEXT: [[TMP95:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB159:%.*]] = sub i32 [[TMP95]], -31 +// CHECK2-NEXT: [[DIV160:%.*]] = udiv i32 [[SUB159]], 32 +// CHECK2-NEXT: [[MUL161:%.*]] = mul i32 [[MUL158]], [[DIV160]] +// CHECK2-NEXT: [[MUL162:%.*]] = mul i32 [[MUL161]], 32 +// CHECK2-NEXT: [[CONV163:%.*]] = zext i32 [[MUL162]] to i64 +// CHECK2-NEXT: [[DIV164:%.*]] = sdiv i64 [[TMP90]], [[CONV163]] +// CHECK2-NEXT: [[TMP96:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK2-NEXT: [[TMP97:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK2-NEXT: [[SUB165:%.*]] = sub i32 [[TMP96]], [[TMP97]] +// CHECK2-NEXT: [[SUB166:%.*]] = sub i32 [[SUB165]], 1 +// CHECK2-NEXT: [[TMP98:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[ADD167:%.*]] = add i32 [[SUB166]], [[TMP98]] +// CHECK2-NEXT: [[TMP99:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[DIV168:%.*]] = udiv i32 [[ADD167]], [[TMP99]] +// CHECK2-NEXT: [[MUL169:%.*]] = mul i32 1, [[DIV168]] +// CHECK2-NEXT: [[TMP100:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB170:%.*]] = sub i32 [[TMP100]], -31 +// CHECK2-NEXT: [[DIV171:%.*]] = udiv i32 [[SUB170]], 32 +// CHECK2-NEXT: [[MUL172:%.*]] = mul i32 [[MUL169]], [[DIV171]] +// CHECK2-NEXT: [[MUL173:%.*]] = mul i32 [[MUL172]], 32 +// CHECK2-NEXT: [[CONV174:%.*]] = zext i32 [[MUL173]] to i64 +// CHECK2-NEXT: [[MUL175:%.*]] = mul nsw i64 [[DIV164]], [[CONV174]] +// CHECK2-NEXT: [[SUB176:%.*]] = sub nsw i64 [[TMP89]], [[MUL175]] +// CHECK2-NEXT: [[TMP101:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[TMP102:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[TMP103:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK2-NEXT: [[TMP104:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK2-NEXT: [[SUB177:%.*]] = sub i32 [[TMP103]], [[TMP104]] +// CHECK2-NEXT: [[SUB178:%.*]] = sub i32 [[SUB177]], 1 +// CHECK2-NEXT: [[TMP105:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[ADD179:%.*]] = add i32 [[SUB178]], [[TMP105]] +// CHECK2-NEXT: [[TMP106:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[DIV180:%.*]] = udiv i32 [[ADD179]], [[TMP106]] +// CHECK2-NEXT: [[MUL181:%.*]] = mul i32 1, [[DIV180]] +// CHECK2-NEXT: [[TMP107:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB182:%.*]] = sub i32 [[TMP107]], -31 +// CHECK2-NEXT: [[DIV183:%.*]] = udiv i32 [[SUB182]], 32 +// CHECK2-NEXT: [[MUL184:%.*]] = mul i32 [[MUL181]], [[DIV183]] +// CHECK2-NEXT: [[MUL185:%.*]] = mul i32 [[MUL184]], 32 +// CHECK2-NEXT: [[CONV186:%.*]] = zext i32 [[MUL185]] to i64 +// CHECK2-NEXT: [[DIV187:%.*]] = sdiv i64 [[TMP102]], [[CONV186]] +// CHECK2-NEXT: [[TMP108:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK2-NEXT: [[TMP109:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK2-NEXT: [[SUB188:%.*]] = sub i32 [[TMP108]], [[TMP109]] +// CHECK2-NEXT: [[SUB189:%.*]] = sub i32 [[SUB188]], 1 +// CHECK2-NEXT: [[TMP110:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[ADD190:%.*]] = add i32 [[SUB189]], [[TMP110]] +// CHECK2-NEXT: [[TMP111:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[DIV191:%.*]] = udiv i32 [[ADD190]], [[TMP111]] +// CHECK2-NEXT: [[MUL192:%.*]] = mul i32 1, [[DIV191]] +// CHECK2-NEXT: [[TMP112:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB193:%.*]] = sub i32 [[TMP112]], -31 +// CHECK2-NEXT: [[DIV194:%.*]] = udiv i32 [[SUB193]], 32 +// CHECK2-NEXT: [[MUL195:%.*]] = mul i32 [[MUL192]], [[DIV194]] +// CHECK2-NEXT: [[MUL196:%.*]] = mul i32 [[MUL195]], 32 +// CHECK2-NEXT: [[CONV197:%.*]] = zext i32 [[MUL196]] to i64 +// CHECK2-NEXT: [[MUL198:%.*]] = mul nsw i64 [[DIV187]], [[CONV197]] +// CHECK2-NEXT: [[SUB199:%.*]] = sub nsw i64 [[TMP101]], [[MUL198]] // CHECK2-NEXT: [[TMP113:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB187:%.*]] = sub i32 [[TMP113]], -31 -// CHECK2-NEXT: [[DIV188:%.*]] = udiv i32 [[SUB187]], 32 -// CHECK2-NEXT: [[MUL189:%.*]] = mul i32 1, [[DIV188]] -// CHECK2-NEXT: [[TMP114:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP115:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB190:%.*]] = sub i32 [[TMP114]], [[TMP115]] -// CHECK2-NEXT: [[SUB191:%.*]] = sub i32 [[SUB190]], 1 -// CHECK2-NEXT: [[ADD192:%.*]] = add i32 [[SUB191]], 1 -// CHECK2-NEXT: [[DIV193:%.*]] = udiv i32 [[ADD192]], 1 -// CHECK2-NEXT: [[MUL194:%.*]] = mul i32 [[MUL189]], [[DIV193]] -// CHECK2-NEXT: [[CONV195:%.*]] = zext i32 [[MUL194]] to i64 -// CHECK2-NEXT: [[DIV196:%.*]] = sdiv i64 [[SUB186]], [[CONV195]] -// CHECK2-NEXT: [[TMP116:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB197:%.*]] = sub i32 [[TMP116]], -31 -// CHECK2-NEXT: [[DIV198:%.*]] = udiv i32 [[SUB197]], 32 -// CHECK2-NEXT: [[MUL199:%.*]] = mul i32 1, [[DIV198]] -// CHECK2-NEXT: [[TMP117:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP118:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB200:%.*]] = sub i32 [[TMP117]], [[TMP118]] -// CHECK2-NEXT: [[SUB201:%.*]] = sub i32 [[SUB200]], 1 -// CHECK2-NEXT: [[ADD202:%.*]] = add i32 [[SUB201]], 1 -// CHECK2-NEXT: [[DIV203:%.*]] = udiv i32 [[ADD202]], 1 -// CHECK2-NEXT: [[MUL204:%.*]] = mul i32 [[MUL199]], [[DIV203]] -// CHECK2-NEXT: [[CONV205:%.*]] = zext i32 [[MUL204]] to i64 -// CHECK2-NEXT: [[MUL206:%.*]] = mul nsw i64 [[DIV196]], [[CONV205]] -// CHECK2-NEXT: [[SUB207:%.*]] = sub nsw i64 [[SUB155]], [[MUL206]] -// CHECK2-NEXT: [[TMP119:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP120:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB208:%.*]] = sub i32 [[TMP119]], [[TMP120]] -// CHECK2-NEXT: [[SUB209:%.*]] = sub i32 [[SUB208]], 1 -// CHECK2-NEXT: [[ADD210:%.*]] = add i32 [[SUB209]], 1 -// CHECK2-NEXT: [[DIV211:%.*]] = udiv i32 [[ADD210]], 1 -// CHECK2-NEXT: [[MUL212:%.*]] = mul i32 1, [[DIV211]] -// CHECK2-NEXT: [[CONV213:%.*]] = zext i32 [[MUL212]] to i64 -// CHECK2-NEXT: [[DIV214:%.*]] = sdiv i64 [[SUB207]], [[CONV213]] -// CHECK2-NEXT: [[MUL215:%.*]] = mul nsw i64 [[DIV214]], 32 -// CHECK2-NEXT: [[ADD216:%.*]] = add nsw i64 0, [[MUL215]] -// CHECK2-NEXT: [[CONV217:%.*]] = trunc i64 [[ADD216]] to i32 -// CHECK2-NEXT: store i32 [[CONV217]], ptr [[DOTFLOOR_0_IV_K51]], align 4 -// CHECK2-NEXT: [[TMP121:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[CONV218:%.*]] = zext i32 [[TMP121]] to i64 -// CHECK2-NEXT: [[TMP122:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP123:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP124:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK2-NEXT: [[TMP125:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK2-NEXT: [[SUB219:%.*]] = sub i32 [[TMP124]], [[TMP125]] -// CHECK2-NEXT: [[SUB220:%.*]] = sub i32 [[SUB219]], 1 -// CHECK2-NEXT: [[TMP126:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[ADD221:%.*]] = add i32 [[SUB220]], [[TMP126]] -// CHECK2-NEXT: [[TMP127:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[DIV222:%.*]] = udiv i32 [[ADD221]], [[TMP127]] -// CHECK2-NEXT: [[MUL223:%.*]] = mul i32 1, [[DIV222]] -// CHECK2-NEXT: [[TMP128:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB224:%.*]] = sub i32 [[TMP128]], -31 -// CHECK2-NEXT: [[DIV225:%.*]] = udiv i32 [[SUB224]], 32 -// CHECK2-NEXT: [[MUL226:%.*]] = mul i32 [[MUL223]], [[DIV225]] -// CHECK2-NEXT: [[TMP129:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP130:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB227:%.*]] = sub i32 [[TMP129]], [[TMP130]] -// CHECK2-NEXT: [[SUB228:%.*]] = sub i32 [[SUB227]], 1 -// CHECK2-NEXT: [[ADD229:%.*]] = add i32 [[SUB228]], 1 -// CHECK2-NEXT: [[DIV230:%.*]] = udiv i32 [[ADD229]], 1 -// CHECK2-NEXT: [[MUL231:%.*]] = mul i32 [[MUL226]], [[DIV230]] -// CHECK2-NEXT: [[CONV232:%.*]] = zext i32 [[MUL231]] to i64 -// CHECK2-NEXT: [[DIV233:%.*]] = sdiv i64 [[TMP123]], [[CONV232]] -// CHECK2-NEXT: [[TMP131:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK2-NEXT: [[TMP132:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK2-NEXT: [[SUB234:%.*]] = sub i32 [[TMP131]], [[TMP132]] -// CHECK2-NEXT: [[SUB235:%.*]] = sub i32 [[SUB234]], 1 -// CHECK2-NEXT: [[TMP133:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[ADD236:%.*]] = add i32 [[SUB235]], [[TMP133]] -// CHECK2-NEXT: [[TMP134:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[DIV237:%.*]] = udiv i32 [[ADD236]], [[TMP134]] -// CHECK2-NEXT: [[MUL238:%.*]] = mul i32 1, [[DIV237]] -// CHECK2-NEXT: [[TMP135:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB239:%.*]] = sub i32 [[TMP135]], -31 -// CHECK2-NEXT: [[DIV240:%.*]] = udiv i32 [[SUB239]], 32 -// CHECK2-NEXT: [[MUL241:%.*]] = mul i32 [[MUL238]], [[DIV240]] -// CHECK2-NEXT: [[TMP136:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP137:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB242:%.*]] = sub i32 [[TMP136]], [[TMP137]] -// CHECK2-NEXT: [[SUB243:%.*]] = sub i32 [[SUB242]], 1 -// CHECK2-NEXT: [[ADD244:%.*]] = add i32 [[SUB243]], 1 -// CHECK2-NEXT: [[DIV245:%.*]] = udiv i32 [[ADD244]], 1 -// CHECK2-NEXT: [[MUL246:%.*]] = mul i32 [[MUL241]], [[DIV245]] -// CHECK2-NEXT: [[CONV247:%.*]] = zext i32 [[MUL246]] to i64 -// CHECK2-NEXT: [[MUL248:%.*]] = mul nsw i64 [[DIV233]], [[CONV247]] -// CHECK2-NEXT: [[SUB249:%.*]] = sub nsw i64 [[TMP122]], [[MUL248]] -// CHECK2-NEXT: [[TMP138:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP139:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP140:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK2-NEXT: [[TMP141:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK2-NEXT: [[SUB250:%.*]] = sub i32 [[TMP140]], [[TMP141]] -// CHECK2-NEXT: [[SUB251:%.*]] = sub i32 [[SUB250]], 1 -// CHECK2-NEXT: [[TMP142:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[ADD252:%.*]] = add i32 [[SUB251]], [[TMP142]] -// CHECK2-NEXT: [[TMP143:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[DIV253:%.*]] = udiv i32 [[ADD252]], [[TMP143]] -// CHECK2-NEXT: [[MUL254:%.*]] = mul i32 1, [[DIV253]] -// CHECK2-NEXT: [[TMP144:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB255:%.*]] = sub i32 [[TMP144]], -31 -// CHECK2-NEXT: [[DIV256:%.*]] = udiv i32 [[SUB255]], 32 -// CHECK2-NEXT: [[MUL257:%.*]] = mul i32 [[MUL254]], [[DIV256]] -// CHECK2-NEXT: [[TMP145:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP146:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB258:%.*]] = sub i32 [[TMP145]], [[TMP146]] -// CHECK2-NEXT: [[SUB259:%.*]] = sub i32 [[SUB258]], 1 -// CHECK2-NEXT: [[ADD260:%.*]] = add i32 [[SUB259]], 1 -// CHECK2-NEXT: [[DIV261:%.*]] = udiv i32 [[ADD260]], 1 -// CHECK2-NEXT: [[MUL262:%.*]] = mul i32 [[MUL257]], [[DIV261]] +// CHECK2-NEXT: [[SUB200:%.*]] = sub i32 [[TMP113]], -31 +// CHECK2-NEXT: [[DIV201:%.*]] = udiv i32 [[SUB200]], 32 +// CHECK2-NEXT: [[MUL202:%.*]] = mul i32 1, [[DIV201]] +// CHECK2-NEXT: [[MUL203:%.*]] = mul i32 [[MUL202]], 32 +// CHECK2-NEXT: [[CONV204:%.*]] = zext i32 [[MUL203]] to i64 +// CHECK2-NEXT: [[DIV205:%.*]] = sdiv i64 [[SUB199]], [[CONV204]] +// CHECK2-NEXT: [[TMP114:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB206:%.*]] = sub i32 [[TMP114]], -31 +// CHECK2-NEXT: [[DIV207:%.*]] = udiv i32 [[SUB206]], 32 +// CHECK2-NEXT: [[MUL208:%.*]] = mul i32 1, [[DIV207]] +// CHECK2-NEXT: [[MUL209:%.*]] = mul i32 [[MUL208]], 32 +// CHECK2-NEXT: [[CONV210:%.*]] = zext i32 [[MUL209]] to i64 +// CHECK2-NEXT: [[MUL211:%.*]] = mul nsw i64 [[DIV205]], [[CONV210]] +// CHECK2-NEXT: [[SUB212:%.*]] = sub nsw i64 [[SUB176]], [[MUL211]] +// CHECK2-NEXT: [[TMP115:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[TMP116:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[TMP117:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK2-NEXT: [[TMP118:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK2-NEXT: [[SUB213:%.*]] = sub i32 [[TMP117]], [[TMP118]] +// CHECK2-NEXT: [[SUB214:%.*]] = sub i32 [[SUB213]], 1 +// CHECK2-NEXT: [[TMP119:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[ADD215:%.*]] = add i32 [[SUB214]], [[TMP119]] +// CHECK2-NEXT: [[TMP120:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[DIV216:%.*]] = udiv i32 [[ADD215]], [[TMP120]] +// CHECK2-NEXT: [[MUL217:%.*]] = mul i32 1, [[DIV216]] +// CHECK2-NEXT: [[TMP121:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB218:%.*]] = sub i32 [[TMP121]], -31 +// CHECK2-NEXT: [[DIV219:%.*]] = udiv i32 [[SUB218]], 32 +// CHECK2-NEXT: [[MUL220:%.*]] = mul i32 [[MUL217]], [[DIV219]] +// CHECK2-NEXT: [[MUL221:%.*]] = mul i32 [[MUL220]], 32 +// CHECK2-NEXT: [[CONV222:%.*]] = zext i32 [[MUL221]] to i64 +// CHECK2-NEXT: [[DIV223:%.*]] = sdiv i64 [[TMP116]], [[CONV222]] +// CHECK2-NEXT: [[TMP122:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK2-NEXT: [[TMP123:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK2-NEXT: [[SUB224:%.*]] = sub i32 [[TMP122]], [[TMP123]] +// CHECK2-NEXT: [[SUB225:%.*]] = sub i32 [[SUB224]], 1 +// CHECK2-NEXT: [[TMP124:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[ADD226:%.*]] = add i32 [[SUB225]], [[TMP124]] +// CHECK2-NEXT: [[TMP125:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[DIV227:%.*]] = udiv i32 [[ADD226]], [[TMP125]] +// CHECK2-NEXT: [[MUL228:%.*]] = mul i32 1, [[DIV227]] +// CHECK2-NEXT: [[TMP126:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB229:%.*]] = sub i32 [[TMP126]], -31 +// CHECK2-NEXT: [[DIV230:%.*]] = udiv i32 [[SUB229]], 32 +// CHECK2-NEXT: [[MUL231:%.*]] = mul i32 [[MUL228]], [[DIV230]] +// CHECK2-NEXT: [[MUL232:%.*]] = mul i32 [[MUL231]], 32 +// CHECK2-NEXT: [[CONV233:%.*]] = zext i32 [[MUL232]] to i64 +// CHECK2-NEXT: [[MUL234:%.*]] = mul nsw i64 [[DIV223]], [[CONV233]] +// CHECK2-NEXT: [[SUB235:%.*]] = sub nsw i64 [[TMP115]], [[MUL234]] +// CHECK2-NEXT: [[TMP127:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[TMP128:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[TMP129:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK2-NEXT: [[TMP130:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK2-NEXT: [[SUB236:%.*]] = sub i32 [[TMP129]], [[TMP130]] +// CHECK2-NEXT: [[SUB237:%.*]] = sub i32 [[SUB236]], 1 +// CHECK2-NEXT: [[TMP131:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[ADD238:%.*]] = add i32 [[SUB237]], [[TMP131]] +// CHECK2-NEXT: [[TMP132:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[DIV239:%.*]] = udiv i32 [[ADD238]], [[TMP132]] +// CHECK2-NEXT: [[MUL240:%.*]] = mul i32 1, [[DIV239]] +// CHECK2-NEXT: [[TMP133:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB241:%.*]] = sub i32 [[TMP133]], -31 +// CHECK2-NEXT: [[DIV242:%.*]] = udiv i32 [[SUB241]], 32 +// CHECK2-NEXT: [[MUL243:%.*]] = mul i32 [[MUL240]], [[DIV242]] +// CHECK2-NEXT: [[MUL244:%.*]] = mul i32 [[MUL243]], 32 +// CHECK2-NEXT: [[CONV245:%.*]] = zext i32 [[MUL244]] to i64 +// CHECK2-NEXT: [[DIV246:%.*]] = sdiv i64 [[TMP128]], [[CONV245]] +// CHECK2-NEXT: [[TMP134:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK2-NEXT: [[TMP135:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK2-NEXT: [[SUB247:%.*]] = sub i32 [[TMP134]], [[TMP135]] +// CHECK2-NEXT: [[SUB248:%.*]] = sub i32 [[SUB247]], 1 +// CHECK2-NEXT: [[TMP136:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[ADD249:%.*]] = add i32 [[SUB248]], [[TMP136]] +// CHECK2-NEXT: [[TMP137:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[DIV250:%.*]] = udiv i32 [[ADD249]], [[TMP137]] +// CHECK2-NEXT: [[MUL251:%.*]] = mul i32 1, [[DIV250]] +// CHECK2-NEXT: [[TMP138:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB252:%.*]] = sub i32 [[TMP138]], -31 +// CHECK2-NEXT: [[DIV253:%.*]] = udiv i32 [[SUB252]], 32 +// CHECK2-NEXT: [[MUL254:%.*]] = mul i32 [[MUL251]], [[DIV253]] +// CHECK2-NEXT: [[MUL255:%.*]] = mul i32 [[MUL254]], 32 +// CHECK2-NEXT: [[CONV256:%.*]] = zext i32 [[MUL255]] to i64 +// CHECK2-NEXT: [[MUL257:%.*]] = mul nsw i64 [[DIV246]], [[CONV256]] +// CHECK2-NEXT: [[SUB258:%.*]] = sub nsw i64 [[TMP127]], [[MUL257]] +// CHECK2-NEXT: [[TMP139:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB259:%.*]] = sub i32 [[TMP139]], -31 +// CHECK2-NEXT: [[DIV260:%.*]] = udiv i32 [[SUB259]], 32 +// CHECK2-NEXT: [[MUL261:%.*]] = mul i32 1, [[DIV260]] +// CHECK2-NEXT: [[MUL262:%.*]] = mul i32 [[MUL261]], 32 // CHECK2-NEXT: [[CONV263:%.*]] = zext i32 [[MUL262]] to i64 -// CHECK2-NEXT: [[DIV264:%.*]] = sdiv i64 [[TMP139]], [[CONV263]] -// CHECK2-NEXT: [[TMP147:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK2-NEXT: [[TMP148:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK2-NEXT: [[SUB265:%.*]] = sub i32 [[TMP147]], [[TMP148]] -// CHECK2-NEXT: [[SUB266:%.*]] = sub i32 [[SUB265]], 1 -// CHECK2-NEXT: [[TMP149:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[ADD267:%.*]] = add i32 [[SUB266]], [[TMP149]] -// CHECK2-NEXT: [[TMP150:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[DIV268:%.*]] = udiv i32 [[ADD267]], [[TMP150]] -// CHECK2-NEXT: [[MUL269:%.*]] = mul i32 1, [[DIV268]] -// CHECK2-NEXT: [[TMP151:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB270:%.*]] = sub i32 [[TMP151]], -31 -// CHECK2-NEXT: [[DIV271:%.*]] = udiv i32 [[SUB270]], 32 -// CHECK2-NEXT: [[MUL272:%.*]] = mul i32 [[MUL269]], [[DIV271]] -// CHECK2-NEXT: [[TMP152:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP153:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB273:%.*]] = sub i32 [[TMP152]], [[TMP153]] -// CHECK2-NEXT: [[SUB274:%.*]] = sub i32 [[SUB273]], 1 -// CHECK2-NEXT: [[ADD275:%.*]] = add i32 [[SUB274]], 1 -// CHECK2-NEXT: [[DIV276:%.*]] = udiv i32 [[ADD275]], 1 -// CHECK2-NEXT: [[MUL277:%.*]] = mul i32 [[MUL272]], [[DIV276]] -// CHECK2-NEXT: [[CONV278:%.*]] = zext i32 [[MUL277]] to i64 -// CHECK2-NEXT: [[MUL279:%.*]] = mul nsw i64 [[DIV264]], [[CONV278]] -// CHECK2-NEXT: [[SUB280:%.*]] = sub nsw i64 [[TMP138]], [[MUL279]] -// CHECK2-NEXT: [[TMP154:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB281:%.*]] = sub i32 [[TMP154]], -31 -// CHECK2-NEXT: [[DIV282:%.*]] = udiv i32 [[SUB281]], 32 -// CHECK2-NEXT: [[MUL283:%.*]] = mul i32 1, [[DIV282]] -// CHECK2-NEXT: [[TMP155:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP156:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB284:%.*]] = sub i32 [[TMP155]], [[TMP156]] -// CHECK2-NEXT: [[SUB285:%.*]] = sub i32 [[SUB284]], 1 -// CHECK2-NEXT: [[ADD286:%.*]] = add i32 [[SUB285]], 1 -// CHECK2-NEXT: [[DIV287:%.*]] = udiv i32 [[ADD286]], 1 -// CHECK2-NEXT: [[MUL288:%.*]] = mul i32 [[MUL283]], [[DIV287]] -// CHECK2-NEXT: [[CONV289:%.*]] = zext i32 [[MUL288]] to i64 -// CHECK2-NEXT: [[DIV290:%.*]] = sdiv i64 [[SUB280]], [[CONV289]] -// CHECK2-NEXT: [[TMP157:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB291:%.*]] = sub i32 [[TMP157]], -31 -// CHECK2-NEXT: [[DIV292:%.*]] = udiv i32 [[SUB291]], 32 -// CHECK2-NEXT: [[MUL293:%.*]] = mul i32 1, [[DIV292]] -// CHECK2-NEXT: [[TMP158:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP159:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB294:%.*]] = sub i32 [[TMP158]], [[TMP159]] -// CHECK2-NEXT: [[SUB295:%.*]] = sub i32 [[SUB294]], 1 -// CHECK2-NEXT: [[ADD296:%.*]] = add i32 [[SUB295]], 1 -// CHECK2-NEXT: [[DIV297:%.*]] = udiv i32 [[ADD296]], 1 -// CHECK2-NEXT: [[MUL298:%.*]] = mul i32 [[MUL293]], [[DIV297]] -// CHECK2-NEXT: [[CONV299:%.*]] = zext i32 [[MUL298]] to i64 -// CHECK2-NEXT: [[MUL300:%.*]] = mul nsw i64 [[DIV290]], [[CONV299]] -// CHECK2-NEXT: [[SUB301:%.*]] = sub nsw i64 [[SUB249]], [[MUL300]] -// CHECK2-NEXT: [[TMP160:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP161:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP162:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK2-NEXT: [[TMP163:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK2-NEXT: [[SUB302:%.*]] = sub i32 [[TMP162]], [[TMP163]] -// CHECK2-NEXT: [[SUB303:%.*]] = sub i32 [[SUB302]], 1 -// CHECK2-NEXT: [[TMP164:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[ADD304:%.*]] = add i32 [[SUB303]], [[TMP164]] -// CHECK2-NEXT: [[TMP165:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[DIV305:%.*]] = udiv i32 [[ADD304]], [[TMP165]] -// CHECK2-NEXT: [[MUL306:%.*]] = mul i32 1, [[DIV305]] -// CHECK2-NEXT: [[TMP166:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB307:%.*]] = sub i32 [[TMP166]], -31 -// CHECK2-NEXT: [[DIV308:%.*]] = udiv i32 [[SUB307]], 32 -// CHECK2-NEXT: [[MUL309:%.*]] = mul i32 [[MUL306]], [[DIV308]] -// CHECK2-NEXT: [[TMP167:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP168:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB310:%.*]] = sub i32 [[TMP167]], [[TMP168]] -// CHECK2-NEXT: [[SUB311:%.*]] = sub i32 [[SUB310]], 1 -// CHECK2-NEXT: [[ADD312:%.*]] = add i32 [[SUB311]], 1 -// CHECK2-NEXT: [[DIV313:%.*]] = udiv i32 [[ADD312]], 1 -// CHECK2-NEXT: [[MUL314:%.*]] = mul i32 [[MUL309]], [[DIV313]] -// CHECK2-NEXT: [[CONV315:%.*]] = zext i32 [[MUL314]] to i64 -// CHECK2-NEXT: [[DIV316:%.*]] = sdiv i64 [[TMP161]], [[CONV315]] -// CHECK2-NEXT: [[TMP169:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK2-NEXT: [[TMP170:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK2-NEXT: [[SUB317:%.*]] = sub i32 [[TMP169]], [[TMP170]] -// CHECK2-NEXT: [[SUB318:%.*]] = sub i32 [[SUB317]], 1 -// CHECK2-NEXT: [[TMP171:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[ADD319:%.*]] = add i32 [[SUB318]], [[TMP171]] -// CHECK2-NEXT: [[TMP172:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[DIV320:%.*]] = udiv i32 [[ADD319]], [[TMP172]] -// CHECK2-NEXT: [[MUL321:%.*]] = mul i32 1, [[DIV320]] -// CHECK2-NEXT: [[TMP173:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB322:%.*]] = sub i32 [[TMP173]], -31 -// CHECK2-NEXT: [[DIV323:%.*]] = udiv i32 [[SUB322]], 32 -// CHECK2-NEXT: [[MUL324:%.*]] = mul i32 [[MUL321]], [[DIV323]] -// CHECK2-NEXT: [[TMP174:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP175:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB325:%.*]] = sub i32 [[TMP174]], [[TMP175]] -// CHECK2-NEXT: [[SUB326:%.*]] = sub i32 [[SUB325]], 1 -// CHECK2-NEXT: [[ADD327:%.*]] = add i32 [[SUB326]], 1 -// CHECK2-NEXT: [[DIV328:%.*]] = udiv i32 [[ADD327]], 1 -// CHECK2-NEXT: [[MUL329:%.*]] = mul i32 [[MUL324]], [[DIV328]] -// CHECK2-NEXT: [[CONV330:%.*]] = zext i32 [[MUL329]] to i64 -// CHECK2-NEXT: [[MUL331:%.*]] = mul nsw i64 [[DIV316]], [[CONV330]] -// CHECK2-NEXT: [[SUB332:%.*]] = sub nsw i64 [[TMP160]], [[MUL331]] -// CHECK2-NEXT: [[TMP176:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP177:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP178:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK2-NEXT: [[TMP179:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK2-NEXT: [[SUB333:%.*]] = sub i32 [[TMP178]], [[TMP179]] -// CHECK2-NEXT: [[SUB334:%.*]] = sub i32 [[SUB333]], 1 -// CHECK2-NEXT: [[TMP180:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[ADD335:%.*]] = add i32 [[SUB334]], [[TMP180]] -// CHECK2-NEXT: [[TMP181:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[DIV336:%.*]] = udiv i32 [[ADD335]], [[TMP181]] -// CHECK2-NEXT: [[MUL337:%.*]] = mul i32 1, [[DIV336]] -// CHECK2-NEXT: [[TMP182:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB338:%.*]] = sub i32 [[TMP182]], -31 -// CHECK2-NEXT: [[DIV339:%.*]] = udiv i32 [[SUB338]], 32 -// CHECK2-NEXT: [[MUL340:%.*]] = mul i32 [[MUL337]], [[DIV339]] -// CHECK2-NEXT: [[TMP183:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP184:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB341:%.*]] = sub i32 [[TMP183]], [[TMP184]] -// CHECK2-NEXT: [[SUB342:%.*]] = sub i32 [[SUB341]], 1 -// CHECK2-NEXT: [[ADD343:%.*]] = add i32 [[SUB342]], 1 -// CHECK2-NEXT: [[DIV344:%.*]] = udiv i32 [[ADD343]], 1 -// CHECK2-NEXT: [[MUL345:%.*]] = mul i32 [[MUL340]], [[DIV344]] -// CHECK2-NEXT: [[CONV346:%.*]] = zext i32 [[MUL345]] to i64 -// CHECK2-NEXT: [[DIV347:%.*]] = sdiv i64 [[TMP177]], [[CONV346]] -// CHECK2-NEXT: [[TMP185:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK2-NEXT: [[TMP186:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK2-NEXT: [[SUB348:%.*]] = sub i32 [[TMP185]], [[TMP186]] -// CHECK2-NEXT: [[SUB349:%.*]] = sub i32 [[SUB348]], 1 -// CHECK2-NEXT: [[TMP187:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[ADD350:%.*]] = add i32 [[SUB349]], [[TMP187]] -// CHECK2-NEXT: [[TMP188:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[DIV351:%.*]] = udiv i32 [[ADD350]], [[TMP188]] -// CHECK2-NEXT: [[MUL352:%.*]] = mul i32 1, [[DIV351]] -// CHECK2-NEXT: [[TMP189:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB353:%.*]] = sub i32 [[TMP189]], -31 -// CHECK2-NEXT: [[DIV354:%.*]] = udiv i32 [[SUB353]], 32 -// CHECK2-NEXT: [[MUL355:%.*]] = mul i32 [[MUL352]], [[DIV354]] -// CHECK2-NEXT: [[TMP190:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP191:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB356:%.*]] = sub i32 [[TMP190]], [[TMP191]] -// CHECK2-NEXT: [[SUB357:%.*]] = sub i32 [[SUB356]], 1 -// CHECK2-NEXT: [[ADD358:%.*]] = add i32 [[SUB357]], 1 -// CHECK2-NEXT: [[DIV359:%.*]] = udiv i32 [[ADD358]], 1 -// CHECK2-NEXT: [[MUL360:%.*]] = mul i32 [[MUL355]], [[DIV359]] -// CHECK2-NEXT: [[CONV361:%.*]] = zext i32 [[MUL360]] to i64 -// CHECK2-NEXT: [[MUL362:%.*]] = mul nsw i64 [[DIV347]], [[CONV361]] -// CHECK2-NEXT: [[SUB363:%.*]] = sub nsw i64 [[TMP176]], [[MUL362]] -// CHECK2-NEXT: [[TMP192:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB364:%.*]] = sub i32 [[TMP192]], -31 -// CHECK2-NEXT: [[DIV365:%.*]] = udiv i32 [[SUB364]], 32 -// CHECK2-NEXT: [[MUL366:%.*]] = mul i32 1, [[DIV365]] -// CHECK2-NEXT: [[TMP193:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP194:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB367:%.*]] = sub i32 [[TMP193]], [[TMP194]] -// CHECK2-NEXT: [[SUB368:%.*]] = sub i32 [[SUB367]], 1 -// CHECK2-NEXT: [[ADD369:%.*]] = add i32 [[SUB368]], 1 -// CHECK2-NEXT: [[DIV370:%.*]] = udiv i32 [[ADD369]], 1 -// CHECK2-NEXT: [[MUL371:%.*]] = mul i32 [[MUL366]], [[DIV370]] -// CHECK2-NEXT: [[CONV372:%.*]] = zext i32 [[MUL371]] to i64 -// CHECK2-NEXT: [[DIV373:%.*]] = sdiv i64 [[SUB363]], [[CONV372]] -// CHECK2-NEXT: [[TMP195:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB374:%.*]] = sub i32 [[TMP195]], -31 -// CHECK2-NEXT: [[DIV375:%.*]] = udiv i32 [[SUB374]], 32 -// CHECK2-NEXT: [[MUL376:%.*]] = mul i32 1, [[DIV375]] -// CHECK2-NEXT: [[TMP196:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP197:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB377:%.*]] = sub i32 [[TMP196]], [[TMP197]] -// CHECK2-NEXT: [[SUB378:%.*]] = sub i32 [[SUB377]], 1 -// CHECK2-NEXT: [[ADD379:%.*]] = add i32 [[SUB378]], 1 -// CHECK2-NEXT: [[DIV380:%.*]] = udiv i32 [[ADD379]], 1 -// CHECK2-NEXT: [[MUL381:%.*]] = mul i32 [[MUL376]], [[DIV380]] -// CHECK2-NEXT: [[CONV382:%.*]] = zext i32 [[MUL381]] to i64 -// CHECK2-NEXT: [[MUL383:%.*]] = mul nsw i64 [[DIV373]], [[CONV382]] -// CHECK2-NEXT: [[SUB384:%.*]] = sub nsw i64 [[SUB332]], [[MUL383]] -// CHECK2-NEXT: [[TMP198:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP199:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB385:%.*]] = sub i32 [[TMP198]], [[TMP199]] -// CHECK2-NEXT: [[SUB386:%.*]] = sub i32 [[SUB385]], 1 -// CHECK2-NEXT: [[ADD387:%.*]] = add i32 [[SUB386]], 1 -// CHECK2-NEXT: [[DIV388:%.*]] = udiv i32 [[ADD387]], 1 -// CHECK2-NEXT: [[MUL389:%.*]] = mul i32 1, [[DIV388]] -// CHECK2-NEXT: [[CONV390:%.*]] = zext i32 [[MUL389]] to i64 -// CHECK2-NEXT: [[DIV391:%.*]] = sdiv i64 [[SUB384]], [[CONV390]] -// CHECK2-NEXT: [[TMP200:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP201:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB392:%.*]] = sub i32 [[TMP200]], [[TMP201]] -// CHECK2-NEXT: [[SUB393:%.*]] = sub i32 [[SUB392]], 1 -// CHECK2-NEXT: [[ADD394:%.*]] = add i32 [[SUB393]], 1 -// CHECK2-NEXT: [[DIV395:%.*]] = udiv i32 [[ADD394]], 1 -// CHECK2-NEXT: [[MUL396:%.*]] = mul i32 1, [[DIV395]] -// CHECK2-NEXT: [[CONV397:%.*]] = zext i32 [[MUL396]] to i64 -// CHECK2-NEXT: [[MUL398:%.*]] = mul nsw i64 [[DIV391]], [[CONV397]] -// CHECK2-NEXT: [[SUB399:%.*]] = sub nsw i64 [[SUB301]], [[MUL398]] -// CHECK2-NEXT: [[MUL400:%.*]] = mul nsw i64 [[SUB399]], 1 -// CHECK2-NEXT: [[ADD401:%.*]] = add nsw i64 [[CONV218]], [[MUL400]] -// CHECK2-NEXT: [[CONV402:%.*]] = trunc i64 [[ADD401]] to i32 -// CHECK2-NEXT: store i32 [[CONV402]], ptr [[DOTTILE_0_IV_K52]], align 4 -// CHECK2-NEXT: [[TMP202:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 4 -// CHECK2-NEXT: [[TMP203:%.*]] = load i32, ptr [[DOTTILE_0_IV_K52]], align 4 -// CHECK2-NEXT: [[TMP204:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4 -// CHECK2-NEXT: [[MUL403:%.*]] = mul i32 [[TMP203]], [[TMP204]] -// CHECK2-NEXT: [[ADD404:%.*]] = add i32 [[TMP202]], [[MUL403]] -// CHECK2-NEXT: store i32 [[ADD404]], ptr [[K]], align 4 -// CHECK2-NEXT: [[TMP205:%.*]] = load i32, ptr [[I49]], align 4 -// CHECK2-NEXT: [[TMP206:%.*]] = load i32, ptr [[J50]], align 4 -// CHECK2-NEXT: [[TMP207:%.*]] = load i32, ptr [[K]], align 4 -// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP205]], i32 noundef [[TMP206]], i32 noundef [[TMP207]]) +// CHECK2-NEXT: [[DIV264:%.*]] = sdiv i64 [[SUB258]], [[CONV263]] +// CHECK2-NEXT: [[TMP140:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB265:%.*]] = sub i32 [[TMP140]], -31 +// CHECK2-NEXT: [[DIV266:%.*]] = udiv i32 [[SUB265]], 32 +// CHECK2-NEXT: [[MUL267:%.*]] = mul i32 1, [[DIV266]] +// CHECK2-NEXT: [[MUL268:%.*]] = mul i32 [[MUL267]], 32 +// CHECK2-NEXT: [[CONV269:%.*]] = zext i32 [[MUL268]] to i64 +// CHECK2-NEXT: [[MUL270:%.*]] = mul nsw i64 [[DIV264]], [[CONV269]] +// CHECK2-NEXT: [[SUB271:%.*]] = sub nsw i64 [[SUB235]], [[MUL270]] +// CHECK2-NEXT: [[DIV272:%.*]] = sdiv i64 [[SUB271]], 32 +// CHECK2-NEXT: [[MUL273:%.*]] = mul nsw i64 [[DIV272]], 32 +// CHECK2-NEXT: [[SUB274:%.*]] = sub nsw i64 [[SUB212]], [[MUL273]] +// CHECK2-NEXT: [[MUL275:%.*]] = mul nsw i64 [[SUB274]], 1 +// CHECK2-NEXT: [[ADD276:%.*]] = add nsw i64 0, [[MUL275]] +// CHECK2-NEXT: [[CONV277:%.*]] = trunc i64 [[ADD276]] to i32 +// CHECK2-NEXT: store i32 [[CONV277]], ptr [[DOTTILE_CNT_0_IV_K38]], align 4 +// CHECK2-NEXT: [[TMP141:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_K37]], align 4 +// CHECK2-NEXT: [[TMP142:%.*]] = load i32, ptr [[DOTTILE_CNT_0_IV_K38]], align 4 +// CHECK2-NEXT: [[ADD278:%.*]] = add i32 [[TMP141]], [[TMP142]] +// CHECK2-NEXT: store i32 [[ADD278]], ptr [[DOTTILE_0_IV_K]], align 4 +// CHECK2-NEXT: [[TMP143:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 4 +// CHECK2-NEXT: [[TMP144:%.*]] = load i32, ptr [[DOTTILE_0_IV_K]], align 4 +// CHECK2-NEXT: [[TMP145:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4 +// CHECK2-NEXT: [[MUL279:%.*]] = mul i32 [[TMP144]], [[TMP145]] +// CHECK2-NEXT: [[ADD280:%.*]] = add i32 [[TMP143]], [[MUL279]] +// CHECK2-NEXT: store i32 [[ADD280]], ptr [[K]], align 4 +// CHECK2-NEXT: [[TMP146:%.*]] = load i32, ptr [[DOTTILE_0_IV_K]], align 4 +// CHECK2-NEXT: [[TMP147:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4 +// CHECK2-NEXT: [[ADD281:%.*]] = add i32 [[TMP147]], 1 +// CHECK2-NEXT: [[CMP282:%.*]] = icmp ult i32 [[TMP146]], [[ADD281]] +// CHECK2-NEXT: br i1 [[CMP282]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] +// CHECK2: if.then: +// CHECK2-NEXT: [[TMP148:%.*]] = load i32, ptr [[I35]], align 4 +// CHECK2-NEXT: [[TMP149:%.*]] = load i32, ptr [[J36]], align 4 +// CHECK2-NEXT: [[TMP150:%.*]] = load i32, ptr [[K]], align 4 +// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP148]], i32 noundef [[TMP149]], i32 noundef [[TMP150]]) +// CHECK2-NEXT: br label [[IF_END]] +// CHECK2: if.end: // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP208:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[ADD405:%.*]] = add nsw i64 [[TMP208]], 1 -// CHECK2-NEXT: store i64 [[ADD405]], ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[TMP151:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[ADD283:%.*]] = add nsw i64 [[TMP151]], 1 +// CHECK2-NEXT: store i64 [[ADD283]], ptr [[DOTOMP_IV]], align 8 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -4635,22 +4099,21 @@ extern "C" void foo10() { // CHECK2-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTNEW_STEP10:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4 +// CHECK2-NEXT: [[DOTTILE_0_IV_K:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_14:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[DOTCAPTURE_EXPR_16:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[DOTCAPTURE_EXPR_22:%.*]] = alloca i64, align 8 +// CHECK2-NEXT: [[DOTCAPTURE_EXPR_16:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[J:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTFLOOR_0_IV_K:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[DOTTILE_0_IV_K:%.*]] = alloca i32, align 4 +// CHECK2-NEXT: [[DOTTILE_CNT_0_IV_K:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[I49:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[J50:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[DOTFLOOR_0_IV_K51:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[DOTTILE_0_IV_K52:%.*]] = alloca i32, align 4 +// CHECK2-NEXT: [[I35:%.*]] = alloca i32, align 4 +// CHECK2-NEXT: [[J36:%.*]] = alloca i32, align 4 +// CHECK2-NEXT: [[DOTFLOOR_0_IV_K37:%.*]] = alloca i32, align 4 +// CHECK2-NEXT: [[DOTTILE_CNT_0_IV_K38:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) // CHECK2-NEXT: store i32 [[START]], ptr [[START_ADDR]], align 4 // CHECK2-NEXT: store i32 [[END]], ptr [[END_ADDR]], align 4 @@ -4688,630 +4151,452 @@ extern "C" void foo10() { // CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4 // CHECK2-NEXT: [[ADD15:%.*]] = add i32 [[TMP15]], 1 // CHECK2-NEXT: store i32 [[ADD15]], ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[_TMP2]], align 4 -// CHECK2-NEXT: store i32 [[TMP16]], ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4 -// CHECK2-NEXT: [[ADD18:%.*]] = add i32 [[TMP17]], 1 -// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[_TMP2]], align 4 -// CHECK2-NEXT: [[ADD19:%.*]] = add i32 [[TMP18]], 64 -// CHECK2-NEXT: [[CMP:%.*]] = icmp ult i32 [[ADD18]], [[ADD19]] -// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK2: cond.true: -// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4 -// CHECK2-NEXT: [[ADD20:%.*]] = add i32 [[TMP19]], 1 -// CHECK2-NEXT: br label [[COND_END:%.*]] -// CHECK2: cond.false: -// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[_TMP2]], align 4 -// CHECK2-NEXT: [[ADD21:%.*]] = add i32 [[TMP20]], 64 -// CHECK2-NEXT: br label [[COND_END]] -// CHECK2: cond.end: -// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ [[ADD20]], [[COND_TRUE]] ], [ [[ADD21]], [[COND_FALSE]] ] -// CHECK2-NEXT: store i32 [[COND]], ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK2-NEXT: [[SUB23:%.*]] = sub i32 [[TMP21]], [[TMP22]] -// CHECK2-NEXT: [[SUB24:%.*]] = sub i32 [[SUB23]], 1 -// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 -// CHECK2-NEXT: [[ADD25:%.*]] = add i32 [[SUB24]], [[TMP23]] -// CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 -// CHECK2-NEXT: [[DIV26:%.*]] = udiv i32 [[ADD25]], [[TMP24]] -// CHECK2-NEXT: [[CONV:%.*]] = zext i32 [[DIV26]] to i64 -// CHECK2-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK2-NEXT: [[SUB17:%.*]] = sub i32 [[TMP16]], [[TMP17]] +// CHECK2-NEXT: [[SUB18:%.*]] = sub i32 [[SUB17]], 1 +// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 +// CHECK2-NEXT: [[ADD19:%.*]] = add i32 [[SUB18]], [[TMP18]] +// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 +// CHECK2-NEXT: [[DIV20:%.*]] = udiv i32 [[ADD19]], [[TMP19]] +// CHECK2-NEXT: [[CONV:%.*]] = zext i32 [[DIV20]] to i64 +// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK2-NEXT: [[SUB21:%.*]] = sub i32 [[TMP20]], [[TMP21]] +// CHECK2-NEXT: [[SUB22:%.*]] = sub i32 [[SUB21]], 1 +// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[ADD23:%.*]] = add i32 [[SUB22]], [[TMP22]] +// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[DIV24:%.*]] = udiv i32 [[ADD23]], [[TMP23]] +// CHECK2-NEXT: [[CONV25:%.*]] = zext i32 [[DIV24]] to i64 +// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV25]] +// CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB26:%.*]] = sub i32 [[TMP24]], -63 +// CHECK2-NEXT: [[DIV27:%.*]] = udiv i32 [[SUB26]], 64 +// CHECK2-NEXT: [[CONV28:%.*]] = zext i32 [[DIV27]] to i64 +// CHECK2-NEXT: [[MUL29:%.*]] = mul nsw i64 [[MUL]], [[CONV28]] +// CHECK2-NEXT: [[MUL30:%.*]] = mul nsw i64 [[MUL29]], 64 +// CHECK2-NEXT: [[SUB31:%.*]] = sub nsw i64 [[MUL30]], 1 +// CHECK2-NEXT: store i64 [[SUB31]], ptr [[DOTCAPTURE_EXPR_16]], align 8 +// CHECK2-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK2-NEXT: store i32 [[TMP25]], ptr [[I]], align 4 // CHECK2-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK2-NEXT: [[SUB27:%.*]] = sub i32 [[TMP25]], [[TMP26]] -// CHECK2-NEXT: [[SUB28:%.*]] = sub i32 [[SUB27]], 1 -// CHECK2-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[ADD29:%.*]] = add i32 [[SUB28]], [[TMP27]] -// CHECK2-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[DIV30:%.*]] = udiv i32 [[ADD29]], [[TMP28]] -// CHECK2-NEXT: [[CONV31:%.*]] = zext i32 [[DIV30]] to i64 -// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV31]] -// CHECK2-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB32:%.*]] = sub i32 [[TMP29]], -63 -// CHECK2-NEXT: [[DIV33:%.*]] = udiv i32 [[SUB32]], 64 -// CHECK2-NEXT: [[CONV34:%.*]] = zext i32 [[DIV33]] to i64 -// CHECK2-NEXT: [[MUL35:%.*]] = mul nsw i64 [[MUL]], [[CONV34]] -// CHECK2-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB36:%.*]] = sub i32 [[TMP30]], [[TMP31]] -// CHECK2-NEXT: [[SUB37:%.*]] = sub i32 [[SUB36]], 1 -// CHECK2-NEXT: [[ADD38:%.*]] = add i32 [[SUB37]], 1 -// CHECK2-NEXT: [[DIV39:%.*]] = udiv i32 [[ADD38]], 1 -// CHECK2-NEXT: [[CONV40:%.*]] = zext i32 [[DIV39]] to i64 -// CHECK2-NEXT: [[MUL41:%.*]] = mul nsw i64 [[MUL35]], [[CONV40]] -// CHECK2-NEXT: [[SUB42:%.*]] = sub nsw i64 [[MUL41]], 1 -// CHECK2-NEXT: store i64 [[SUB42]], ptr [[DOTCAPTURE_EXPR_22]], align 8 -// CHECK2-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK2-NEXT: store i32 [[TMP32]], ptr [[I]], align 4 -// CHECK2-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK2-NEXT: store i32 [[TMP33]], ptr [[J]], align 4 +// CHECK2-NEXT: store i32 [[TMP26]], ptr [[J]], align 4 // CHECK2-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_K]], align 4 -// CHECK2-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: store i32 [[TMP34]], ptr [[DOTTILE_0_IV_K]], align 4 -// CHECK2-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK2-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK2-NEXT: [[CMP43:%.*]] = icmp slt i32 [[TMP35]], [[TMP36]] -// CHECK2-NEXT: br i1 [[CMP43]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// CHECK2-NEXT: store i32 0, ptr [[DOTTILE_CNT_0_IV_K]], align 4 +// CHECK2-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK2-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP27]], [[TMP28]] +// CHECK2-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK2: land.lhs.true: -// CHECK2-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK2-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK2-NEXT: [[CMP44:%.*]] = icmp slt i32 [[TMP37]], [[TMP38]] -// CHECK2-NEXT: br i1 [[CMP44]], label [[LAND_LHS_TRUE45:%.*]], label [[OMP_PRECOND_END]] -// CHECK2: land.lhs.true45: -// CHECK2-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[CMP46:%.*]] = icmp ult i32 0, [[TMP39]] -// CHECK2-NEXT: br i1 [[CMP46]], label [[LAND_LHS_TRUE47:%.*]], label [[OMP_PRECOND_END]] -// CHECK2: land.lhs.true47: -// CHECK2-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[CMP48:%.*]] = icmp ult i32 [[TMP40]], [[TMP41]] -// CHECK2-NEXT: br i1 [[CMP48]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// CHECK2-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK2-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK2-NEXT: [[CMP32:%.*]] = icmp slt i32 [[TMP29]], [[TMP30]] +// CHECK2-NEXT: br i1 [[CMP32]], label [[LAND_LHS_TRUE33:%.*]], label [[OMP_PRECOND_END]] +// CHECK2: land.lhs.true33: +// CHECK2-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[CMP34:%.*]] = icmp ult i32 0, [[TMP31]] +// CHECK2-NEXT: br i1 [[CMP34]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] // CHECK2: omp.precond.then: // CHECK2-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 -// CHECK2-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8 -// CHECK2-NEXT: store i64 [[TMP42]], ptr [[DOTOMP_UB]], align 8 +// CHECK2-NEXT: [[TMP32:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_16]], align 8 +// CHECK2-NEXT: store i64 [[TMP32]], ptr [[DOTOMP_UB]], align 8 // CHECK2-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 // CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK2-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK2-NEXT: [[TMP43:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 -// CHECK2-NEXT: [[TMP44:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8 -// CHECK2-NEXT: [[CMP53:%.*]] = icmp sgt i64 [[TMP43]], [[TMP44]] -// CHECK2-NEXT: br i1 [[CMP53]], label [[COND_TRUE54:%.*]], label [[COND_FALSE55:%.*]] -// CHECK2: cond.true54: -// CHECK2-NEXT: [[TMP45:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_22]], align 8 -// CHECK2-NEXT: br label [[COND_END56:%.*]] -// CHECK2: cond.false55: -// CHECK2-NEXT: [[TMP46:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 -// CHECK2-NEXT: br label [[COND_END56]] -// CHECK2: cond.end56: -// CHECK2-NEXT: [[COND57:%.*]] = phi i64 [ [[TMP45]], [[COND_TRUE54]] ], [ [[TMP46]], [[COND_FALSE55]] ] -// CHECK2-NEXT: store i64 [[COND57]], ptr [[DOTOMP_UB]], align 8 -// CHECK2-NEXT: [[TMP47:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 -// CHECK2-NEXT: store i64 [[TMP47]], ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[TMP33:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 +// CHECK2-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_16]], align 8 +// CHECK2-NEXT: [[CMP39:%.*]] = icmp sgt i64 [[TMP33]], [[TMP34]] +// CHECK2-NEXT: br i1 [[CMP39]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK2: cond.true: +// CHECK2-NEXT: [[TMP35:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_16]], align 8 +// CHECK2-NEXT: br label [[COND_END:%.*]] +// CHECK2: cond.false: +// CHECK2-NEXT: [[TMP36:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 +// CHECK2-NEXT: br label [[COND_END]] +// CHECK2: cond.end: +// CHECK2-NEXT: [[COND:%.*]] = phi i64 [ [[TMP35]], [[COND_TRUE]] ], [ [[TMP36]], [[COND_FALSE]] ] +// CHECK2-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 +// CHECK2-NEXT: [[TMP37:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 +// CHECK2-NEXT: store i64 [[TMP37]], ptr [[DOTOMP_IV]], align 8 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP48:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP49:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 -// CHECK2-NEXT: [[CMP58:%.*]] = icmp sle i64 [[TMP48]], [[TMP49]] -// CHECK2-NEXT: br i1 [[CMP58]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK2-NEXT: [[TMP38:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 +// CHECK2-NEXT: [[CMP40:%.*]] = icmp sle i64 [[TMP38]], [[TMP39]] +// CHECK2-NEXT: br i1 [[CMP40]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK2-NEXT: [[CONV59:%.*]] = sext i32 [[TMP50]] to i64 -// CHECK2-NEXT: [[TMP51:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP52:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK2-NEXT: [[TMP53:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK2-NEXT: [[SUB60:%.*]] = sub i32 [[TMP52]], [[TMP53]] -// CHECK2-NEXT: [[SUB61:%.*]] = sub i32 [[SUB60]], 1 +// CHECK2-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK2-NEXT: [[CONV41:%.*]] = sext i32 [[TMP40]] to i64 +// CHECK2-NEXT: [[TMP41:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK2-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK2-NEXT: [[SUB42:%.*]] = sub i32 [[TMP42]], [[TMP43]] +// CHECK2-NEXT: [[SUB43:%.*]] = sub i32 [[SUB42]], 1 +// CHECK2-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[ADD44:%.*]] = add i32 [[SUB43]], [[TMP44]] +// CHECK2-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[DIV45:%.*]] = udiv i32 [[ADD44]], [[TMP45]] +// CHECK2-NEXT: [[MUL46:%.*]] = mul i32 1, [[DIV45]] +// CHECK2-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB47:%.*]] = sub i32 [[TMP46]], -63 +// CHECK2-NEXT: [[DIV48:%.*]] = udiv i32 [[SUB47]], 64 +// CHECK2-NEXT: [[MUL49:%.*]] = mul i32 [[MUL46]], [[DIV48]] +// CHECK2-NEXT: [[MUL50:%.*]] = mul i32 [[MUL49]], 64 +// CHECK2-NEXT: [[CONV51:%.*]] = zext i32 [[MUL50]] to i64 +// CHECK2-NEXT: [[DIV52:%.*]] = sdiv i64 [[TMP41]], [[CONV51]] +// CHECK2-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 +// CHECK2-NEXT: [[CONV53:%.*]] = sext i32 [[TMP47]] to i64 +// CHECK2-NEXT: [[MUL54:%.*]] = mul nsw i64 [[DIV52]], [[CONV53]] +// CHECK2-NEXT: [[ADD55:%.*]] = add nsw i64 [[CONV41]], [[MUL54]] +// CHECK2-NEXT: [[CONV56:%.*]] = trunc i64 [[ADD55]] to i32 +// CHECK2-NEXT: store i32 [[CONV56]], ptr [[I35]], align 4 +// CHECK2-NEXT: [[TMP48:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK2-NEXT: [[CONV57:%.*]] = sext i32 [[TMP48]] to i64 +// CHECK2-NEXT: [[TMP49:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[TMP50:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[TMP51:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK2-NEXT: [[TMP52:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK2-NEXT: [[SUB58:%.*]] = sub i32 [[TMP51]], [[TMP52]] +// CHECK2-NEXT: [[SUB59:%.*]] = sub i32 [[SUB58]], 1 +// CHECK2-NEXT: [[TMP53:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[ADD60:%.*]] = add i32 [[SUB59]], [[TMP53]] // CHECK2-NEXT: [[TMP54:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[ADD62:%.*]] = add i32 [[SUB61]], [[TMP54]] -// CHECK2-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[DIV63:%.*]] = udiv i32 [[ADD62]], [[TMP55]] -// CHECK2-NEXT: [[MUL64:%.*]] = mul i32 1, [[DIV63]] -// CHECK2-NEXT: [[TMP56:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB65:%.*]] = sub i32 [[TMP56]], -63 -// CHECK2-NEXT: [[DIV66:%.*]] = udiv i32 [[SUB65]], 64 -// CHECK2-NEXT: [[MUL67:%.*]] = mul i32 [[MUL64]], [[DIV66]] -// CHECK2-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB68:%.*]] = sub i32 [[TMP57]], [[TMP58]] -// CHECK2-NEXT: [[SUB69:%.*]] = sub i32 [[SUB68]], 1 -// CHECK2-NEXT: [[ADD70:%.*]] = add i32 [[SUB69]], 1 -// CHECK2-NEXT: [[DIV71:%.*]] = udiv i32 [[ADD70]], 1 -// CHECK2-NEXT: [[MUL72:%.*]] = mul i32 [[MUL67]], [[DIV71]] -// CHECK2-NEXT: [[CONV73:%.*]] = zext i32 [[MUL72]] to i64 -// CHECK2-NEXT: [[DIV74:%.*]] = sdiv i64 [[TMP51]], [[CONV73]] -// CHECK2-NEXT: [[TMP59:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 -// CHECK2-NEXT: [[CONV75:%.*]] = sext i32 [[TMP59]] to i64 -// CHECK2-NEXT: [[MUL76:%.*]] = mul nsw i64 [[DIV74]], [[CONV75]] -// CHECK2-NEXT: [[ADD77:%.*]] = add nsw i64 [[CONV59]], [[MUL76]] -// CHECK2-NEXT: [[CONV78:%.*]] = trunc i64 [[ADD77]] to i32 -// CHECK2-NEXT: store i32 [[CONV78]], ptr [[I49]], align 4 -// CHECK2-NEXT: [[TMP60:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK2-NEXT: [[CONV79:%.*]] = sext i32 [[TMP60]] to i64 -// CHECK2-NEXT: [[TMP61:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP62:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP63:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK2-NEXT: [[TMP64:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK2-NEXT: [[SUB80:%.*]] = sub i32 [[TMP63]], [[TMP64]] -// CHECK2-NEXT: [[SUB81:%.*]] = sub i32 [[SUB80]], 1 -// CHECK2-NEXT: [[TMP65:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[ADD82:%.*]] = add i32 [[SUB81]], [[TMP65]] -// CHECK2-NEXT: [[TMP66:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[DIV83:%.*]] = udiv i32 [[ADD82]], [[TMP66]] -// CHECK2-NEXT: [[MUL84:%.*]] = mul i32 1, [[DIV83]] -// CHECK2-NEXT: [[TMP67:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB85:%.*]] = sub i32 [[TMP67]], -63 -// CHECK2-NEXT: [[DIV86:%.*]] = udiv i32 [[SUB85]], 64 -// CHECK2-NEXT: [[MUL87:%.*]] = mul i32 [[MUL84]], [[DIV86]] -// CHECK2-NEXT: [[TMP68:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP69:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB88:%.*]] = sub i32 [[TMP68]], [[TMP69]] -// CHECK2-NEXT: [[SUB89:%.*]] = sub i32 [[SUB88]], 1 -// CHECK2-NEXT: [[ADD90:%.*]] = add i32 [[SUB89]], 1 -// CHECK2-NEXT: [[DIV91:%.*]] = udiv i32 [[ADD90]], 1 -// CHECK2-NEXT: [[MUL92:%.*]] = mul i32 [[MUL87]], [[DIV91]] -// CHECK2-NEXT: [[CONV93:%.*]] = zext i32 [[MUL92]] to i64 -// CHECK2-NEXT: [[DIV94:%.*]] = sdiv i64 [[TMP62]], [[CONV93]] +// CHECK2-NEXT: [[DIV61:%.*]] = udiv i32 [[ADD60]], [[TMP54]] +// CHECK2-NEXT: [[MUL62:%.*]] = mul i32 1, [[DIV61]] +// CHECK2-NEXT: [[TMP55:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB63:%.*]] = sub i32 [[TMP55]], -63 +// CHECK2-NEXT: [[DIV64:%.*]] = udiv i32 [[SUB63]], 64 +// CHECK2-NEXT: [[MUL65:%.*]] = mul i32 [[MUL62]], [[DIV64]] +// CHECK2-NEXT: [[MUL66:%.*]] = mul i32 [[MUL65]], 64 +// CHECK2-NEXT: [[CONV67:%.*]] = zext i32 [[MUL66]] to i64 +// CHECK2-NEXT: [[DIV68:%.*]] = sdiv i64 [[TMP50]], [[CONV67]] +// CHECK2-NEXT: [[TMP56:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK2-NEXT: [[TMP57:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK2-NEXT: [[SUB69:%.*]] = sub i32 [[TMP56]], [[TMP57]] +// CHECK2-NEXT: [[SUB70:%.*]] = sub i32 [[SUB69]], 1 +// CHECK2-NEXT: [[TMP58:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[ADD71:%.*]] = add i32 [[SUB70]], [[TMP58]] +// CHECK2-NEXT: [[TMP59:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[DIV72:%.*]] = udiv i32 [[ADD71]], [[TMP59]] +// CHECK2-NEXT: [[MUL73:%.*]] = mul i32 1, [[DIV72]] +// CHECK2-NEXT: [[TMP60:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB74:%.*]] = sub i32 [[TMP60]], -63 +// CHECK2-NEXT: [[DIV75:%.*]] = udiv i32 [[SUB74]], 64 +// CHECK2-NEXT: [[MUL76:%.*]] = mul i32 [[MUL73]], [[DIV75]] +// CHECK2-NEXT: [[MUL77:%.*]] = mul i32 [[MUL76]], 64 +// CHECK2-NEXT: [[CONV78:%.*]] = zext i32 [[MUL77]] to i64 +// CHECK2-NEXT: [[MUL79:%.*]] = mul nsw i64 [[DIV68]], [[CONV78]] +// CHECK2-NEXT: [[SUB80:%.*]] = sub nsw i64 [[TMP49]], [[MUL79]] +// CHECK2-NEXT: [[TMP61:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB81:%.*]] = sub i32 [[TMP61]], -63 +// CHECK2-NEXT: [[DIV82:%.*]] = udiv i32 [[SUB81]], 64 +// CHECK2-NEXT: [[MUL83:%.*]] = mul i32 1, [[DIV82]] +// CHECK2-NEXT: [[MUL84:%.*]] = mul i32 [[MUL83]], 64 +// CHECK2-NEXT: [[CONV85:%.*]] = zext i32 [[MUL84]] to i64 +// CHECK2-NEXT: [[DIV86:%.*]] = sdiv i64 [[SUB80]], [[CONV85]] +// CHECK2-NEXT: [[TMP62:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[CONV87:%.*]] = sext i32 [[TMP62]] to i64 +// CHECK2-NEXT: [[MUL88:%.*]] = mul nsw i64 [[DIV86]], [[CONV87]] +// CHECK2-NEXT: [[ADD89:%.*]] = add nsw i64 [[CONV57]], [[MUL88]] +// CHECK2-NEXT: [[CONV90:%.*]] = trunc i64 [[ADD89]] to i32 +// CHECK2-NEXT: store i32 [[CONV90]], ptr [[J36]], align 4 +// CHECK2-NEXT: [[TMP63:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[TMP64:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[TMP65:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK2-NEXT: [[TMP66:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK2-NEXT: [[SUB91:%.*]] = sub i32 [[TMP65]], [[TMP66]] +// CHECK2-NEXT: [[SUB92:%.*]] = sub i32 [[SUB91]], 1 +// CHECK2-NEXT: [[TMP67:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[ADD93:%.*]] = add i32 [[SUB92]], [[TMP67]] +// CHECK2-NEXT: [[TMP68:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[DIV94:%.*]] = udiv i32 [[ADD93]], [[TMP68]] +// CHECK2-NEXT: [[MUL95:%.*]] = mul i32 1, [[DIV94]] +// CHECK2-NEXT: [[TMP69:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB96:%.*]] = sub i32 [[TMP69]], -63 +// CHECK2-NEXT: [[DIV97:%.*]] = udiv i32 [[SUB96]], 64 +// CHECK2-NEXT: [[MUL98:%.*]] = mul i32 [[MUL95]], [[DIV97]] +// CHECK2-NEXT: [[MUL99:%.*]] = mul i32 [[MUL98]], 64 +// CHECK2-NEXT: [[CONV100:%.*]] = zext i32 [[MUL99]] to i64 +// CHECK2-NEXT: [[DIV101:%.*]] = sdiv i64 [[TMP64]], [[CONV100]] // CHECK2-NEXT: [[TMP70:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 // CHECK2-NEXT: [[TMP71:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK2-NEXT: [[SUB95:%.*]] = sub i32 [[TMP70]], [[TMP71]] -// CHECK2-NEXT: [[SUB96:%.*]] = sub i32 [[SUB95]], 1 +// CHECK2-NEXT: [[SUB102:%.*]] = sub i32 [[TMP70]], [[TMP71]] +// CHECK2-NEXT: [[SUB103:%.*]] = sub i32 [[SUB102]], 1 // CHECK2-NEXT: [[TMP72:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[ADD97:%.*]] = add i32 [[SUB96]], [[TMP72]] +// CHECK2-NEXT: [[ADD104:%.*]] = add i32 [[SUB103]], [[TMP72]] // CHECK2-NEXT: [[TMP73:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[DIV98:%.*]] = udiv i32 [[ADD97]], [[TMP73]] -// CHECK2-NEXT: [[MUL99:%.*]] = mul i32 1, [[DIV98]] +// CHECK2-NEXT: [[DIV105:%.*]] = udiv i32 [[ADD104]], [[TMP73]] +// CHECK2-NEXT: [[MUL106:%.*]] = mul i32 1, [[DIV105]] // CHECK2-NEXT: [[TMP74:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB100:%.*]] = sub i32 [[TMP74]], -63 -// CHECK2-NEXT: [[DIV101:%.*]] = udiv i32 [[SUB100]], 64 -// CHECK2-NEXT: [[MUL102:%.*]] = mul i32 [[MUL99]], [[DIV101]] -// CHECK2-NEXT: [[TMP75:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP76:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB103:%.*]] = sub i32 [[TMP75]], [[TMP76]] -// CHECK2-NEXT: [[SUB104:%.*]] = sub i32 [[SUB103]], 1 -// CHECK2-NEXT: [[ADD105:%.*]] = add i32 [[SUB104]], 1 -// CHECK2-NEXT: [[DIV106:%.*]] = udiv i32 [[ADD105]], 1 -// CHECK2-NEXT: [[MUL107:%.*]] = mul i32 [[MUL102]], [[DIV106]] -// CHECK2-NEXT: [[CONV108:%.*]] = zext i32 [[MUL107]] to i64 -// CHECK2-NEXT: [[MUL109:%.*]] = mul nsw i64 [[DIV94]], [[CONV108]] -// CHECK2-NEXT: [[SUB110:%.*]] = sub nsw i64 [[TMP61]], [[MUL109]] -// CHECK2-NEXT: [[TMP77:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB111:%.*]] = sub i32 [[TMP77]], -63 -// CHECK2-NEXT: [[DIV112:%.*]] = udiv i32 [[SUB111]], 64 -// CHECK2-NEXT: [[MUL113:%.*]] = mul i32 1, [[DIV112]] -// CHECK2-NEXT: [[TMP78:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP79:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB114:%.*]] = sub i32 [[TMP78]], [[TMP79]] +// CHECK2-NEXT: [[SUB107:%.*]] = sub i32 [[TMP74]], -63 +// CHECK2-NEXT: [[DIV108:%.*]] = udiv i32 [[SUB107]], 64 +// CHECK2-NEXT: [[MUL109:%.*]] = mul i32 [[MUL106]], [[DIV108]] +// CHECK2-NEXT: [[MUL110:%.*]] = mul i32 [[MUL109]], 64 +// CHECK2-NEXT: [[CONV111:%.*]] = zext i32 [[MUL110]] to i64 +// CHECK2-NEXT: [[MUL112:%.*]] = mul nsw i64 [[DIV101]], [[CONV111]] +// CHECK2-NEXT: [[SUB113:%.*]] = sub nsw i64 [[TMP63]], [[MUL112]] +// CHECK2-NEXT: [[TMP75:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[TMP76:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[TMP77:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK2-NEXT: [[TMP78:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK2-NEXT: [[SUB114:%.*]] = sub i32 [[TMP77]], [[TMP78]] // CHECK2-NEXT: [[SUB115:%.*]] = sub i32 [[SUB114]], 1 -// CHECK2-NEXT: [[ADD116:%.*]] = add i32 [[SUB115]], 1 -// CHECK2-NEXT: [[DIV117:%.*]] = udiv i32 [[ADD116]], 1 -// CHECK2-NEXT: [[MUL118:%.*]] = mul i32 [[MUL113]], [[DIV117]] -// CHECK2-NEXT: [[CONV119:%.*]] = zext i32 [[MUL118]] to i64 -// CHECK2-NEXT: [[DIV120:%.*]] = sdiv i64 [[SUB110]], [[CONV119]] +// CHECK2-NEXT: [[TMP79:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[ADD116:%.*]] = add i32 [[SUB115]], [[TMP79]] // CHECK2-NEXT: [[TMP80:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[CONV121:%.*]] = sext i32 [[TMP80]] to i64 -// CHECK2-NEXT: [[MUL122:%.*]] = mul nsw i64 [[DIV120]], [[CONV121]] -// CHECK2-NEXT: [[ADD123:%.*]] = add nsw i64 [[CONV79]], [[MUL122]] -// CHECK2-NEXT: [[CONV124:%.*]] = trunc i64 [[ADD123]] to i32 -// CHECK2-NEXT: store i32 [[CONV124]], ptr [[J50]], align 4 -// CHECK2-NEXT: [[TMP81:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP82:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP83:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK2-NEXT: [[TMP84:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK2-NEXT: [[SUB125:%.*]] = sub i32 [[TMP83]], [[TMP84]] +// CHECK2-NEXT: [[DIV117:%.*]] = udiv i32 [[ADD116]], [[TMP80]] +// CHECK2-NEXT: [[MUL118:%.*]] = mul i32 1, [[DIV117]] +// CHECK2-NEXT: [[TMP81:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB119:%.*]] = sub i32 [[TMP81]], -63 +// CHECK2-NEXT: [[DIV120:%.*]] = udiv i32 [[SUB119]], 64 +// CHECK2-NEXT: [[MUL121:%.*]] = mul i32 [[MUL118]], [[DIV120]] +// CHECK2-NEXT: [[MUL122:%.*]] = mul i32 [[MUL121]], 64 +// CHECK2-NEXT: [[CONV123:%.*]] = zext i32 [[MUL122]] to i64 +// CHECK2-NEXT: [[DIV124:%.*]] = sdiv i64 [[TMP76]], [[CONV123]] +// CHECK2-NEXT: [[TMP82:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK2-NEXT: [[TMP83:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK2-NEXT: [[SUB125:%.*]] = sub i32 [[TMP82]], [[TMP83]] // CHECK2-NEXT: [[SUB126:%.*]] = sub i32 [[SUB125]], 1 +// CHECK2-NEXT: [[TMP84:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[ADD127:%.*]] = add i32 [[SUB126]], [[TMP84]] // CHECK2-NEXT: [[TMP85:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[ADD127:%.*]] = add i32 [[SUB126]], [[TMP85]] -// CHECK2-NEXT: [[TMP86:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[DIV128:%.*]] = udiv i32 [[ADD127]], [[TMP86]] +// CHECK2-NEXT: [[DIV128:%.*]] = udiv i32 [[ADD127]], [[TMP85]] // CHECK2-NEXT: [[MUL129:%.*]] = mul i32 1, [[DIV128]] -// CHECK2-NEXT: [[TMP87:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB130:%.*]] = sub i32 [[TMP87]], -63 +// CHECK2-NEXT: [[TMP86:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB130:%.*]] = sub i32 [[TMP86]], -63 // CHECK2-NEXT: [[DIV131:%.*]] = udiv i32 [[SUB130]], 64 // CHECK2-NEXT: [[MUL132:%.*]] = mul i32 [[MUL129]], [[DIV131]] -// CHECK2-NEXT: [[TMP88:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP89:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB133:%.*]] = sub i32 [[TMP88]], [[TMP89]] -// CHECK2-NEXT: [[SUB134:%.*]] = sub i32 [[SUB133]], 1 -// CHECK2-NEXT: [[ADD135:%.*]] = add i32 [[SUB134]], 1 -// CHECK2-NEXT: [[DIV136:%.*]] = udiv i32 [[ADD135]], 1 -// CHECK2-NEXT: [[MUL137:%.*]] = mul i32 [[MUL132]], [[DIV136]] -// CHECK2-NEXT: [[CONV138:%.*]] = zext i32 [[MUL137]] to i64 -// CHECK2-NEXT: [[DIV139:%.*]] = sdiv i64 [[TMP82]], [[CONV138]] -// CHECK2-NEXT: [[TMP90:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK2-NEXT: [[TMP91:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK2-NEXT: [[SUB140:%.*]] = sub i32 [[TMP90]], [[TMP91]] -// CHECK2-NEXT: [[SUB141:%.*]] = sub i32 [[SUB140]], 1 -// CHECK2-NEXT: [[TMP92:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[ADD142:%.*]] = add i32 [[SUB141]], [[TMP92]] +// CHECK2-NEXT: [[MUL133:%.*]] = mul i32 [[MUL132]], 64 +// CHECK2-NEXT: [[CONV134:%.*]] = zext i32 [[MUL133]] to i64 +// CHECK2-NEXT: [[MUL135:%.*]] = mul nsw i64 [[DIV124]], [[CONV134]] +// CHECK2-NEXT: [[SUB136:%.*]] = sub nsw i64 [[TMP75]], [[MUL135]] +// CHECK2-NEXT: [[TMP87:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB137:%.*]] = sub i32 [[TMP87]], -63 +// CHECK2-NEXT: [[DIV138:%.*]] = udiv i32 [[SUB137]], 64 +// CHECK2-NEXT: [[MUL139:%.*]] = mul i32 1, [[DIV138]] +// CHECK2-NEXT: [[MUL140:%.*]] = mul i32 [[MUL139]], 64 +// CHECK2-NEXT: [[CONV141:%.*]] = zext i32 [[MUL140]] to i64 +// CHECK2-NEXT: [[DIV142:%.*]] = sdiv i64 [[SUB136]], [[CONV141]] +// CHECK2-NEXT: [[TMP88:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB143:%.*]] = sub i32 [[TMP88]], -63 +// CHECK2-NEXT: [[DIV144:%.*]] = udiv i32 [[SUB143]], 64 +// CHECK2-NEXT: [[MUL145:%.*]] = mul i32 1, [[DIV144]] +// CHECK2-NEXT: [[MUL146:%.*]] = mul i32 [[MUL145]], 64 +// CHECK2-NEXT: [[CONV147:%.*]] = zext i32 [[MUL146]] to i64 +// CHECK2-NEXT: [[MUL148:%.*]] = mul nsw i64 [[DIV142]], [[CONV147]] +// CHECK2-NEXT: [[SUB149:%.*]] = sub nsw i64 [[SUB113]], [[MUL148]] +// CHECK2-NEXT: [[DIV150:%.*]] = sdiv i64 [[SUB149]], 64 +// CHECK2-NEXT: [[MUL151:%.*]] = mul nsw i64 [[DIV150]], 64 +// CHECK2-NEXT: [[ADD152:%.*]] = add nsw i64 0, [[MUL151]] +// CHECK2-NEXT: [[CONV153:%.*]] = trunc i64 [[ADD152]] to i32 +// CHECK2-NEXT: store i32 [[CONV153]], ptr [[DOTFLOOR_0_IV_K37]], align 4 +// CHECK2-NEXT: [[TMP89:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[TMP90:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[TMP91:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK2-NEXT: [[TMP92:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK2-NEXT: [[SUB154:%.*]] = sub i32 [[TMP91]], [[TMP92]] +// CHECK2-NEXT: [[SUB155:%.*]] = sub i32 [[SUB154]], 1 // CHECK2-NEXT: [[TMP93:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[DIV143:%.*]] = udiv i32 [[ADD142]], [[TMP93]] -// CHECK2-NEXT: [[MUL144:%.*]] = mul i32 1, [[DIV143]] -// CHECK2-NEXT: [[TMP94:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB145:%.*]] = sub i32 [[TMP94]], -63 -// CHECK2-NEXT: [[DIV146:%.*]] = udiv i32 [[SUB145]], 64 -// CHECK2-NEXT: [[MUL147:%.*]] = mul i32 [[MUL144]], [[DIV146]] -// CHECK2-NEXT: [[TMP95:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP96:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB148:%.*]] = sub i32 [[TMP95]], [[TMP96]] -// CHECK2-NEXT: [[SUB149:%.*]] = sub i32 [[SUB148]], 1 -// CHECK2-NEXT: [[ADD150:%.*]] = add i32 [[SUB149]], 1 -// CHECK2-NEXT: [[DIV151:%.*]] = udiv i32 [[ADD150]], 1 -// CHECK2-NEXT: [[MUL152:%.*]] = mul i32 [[MUL147]], [[DIV151]] -// CHECK2-NEXT: [[CONV153:%.*]] = zext i32 [[MUL152]] to i64 -// CHECK2-NEXT: [[MUL154:%.*]] = mul nsw i64 [[DIV139]], [[CONV153]] -// CHECK2-NEXT: [[SUB155:%.*]] = sub nsw i64 [[TMP81]], [[MUL154]] -// CHECK2-NEXT: [[TMP97:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP98:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP99:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK2-NEXT: [[TMP100:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK2-NEXT: [[SUB156:%.*]] = sub i32 [[TMP99]], [[TMP100]] -// CHECK2-NEXT: [[SUB157:%.*]] = sub i32 [[SUB156]], 1 -// CHECK2-NEXT: [[TMP101:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[ADD158:%.*]] = add i32 [[SUB157]], [[TMP101]] -// CHECK2-NEXT: [[TMP102:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[DIV159:%.*]] = udiv i32 [[ADD158]], [[TMP102]] -// CHECK2-NEXT: [[MUL160:%.*]] = mul i32 1, [[DIV159]] -// CHECK2-NEXT: [[TMP103:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB161:%.*]] = sub i32 [[TMP103]], -63 -// CHECK2-NEXT: [[DIV162:%.*]] = udiv i32 [[SUB161]], 64 -// CHECK2-NEXT: [[MUL163:%.*]] = mul i32 [[MUL160]], [[DIV162]] -// CHECK2-NEXT: [[TMP104:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP105:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB164:%.*]] = sub i32 [[TMP104]], [[TMP105]] -// CHECK2-NEXT: [[SUB165:%.*]] = sub i32 [[SUB164]], 1 -// CHECK2-NEXT: [[ADD166:%.*]] = add i32 [[SUB165]], 1 -// CHECK2-NEXT: [[DIV167:%.*]] = udiv i32 [[ADD166]], 1 -// CHECK2-NEXT: [[MUL168:%.*]] = mul i32 [[MUL163]], [[DIV167]] -// CHECK2-NEXT: [[CONV169:%.*]] = zext i32 [[MUL168]] to i64 -// CHECK2-NEXT: [[DIV170:%.*]] = sdiv i64 [[TMP98]], [[CONV169]] -// CHECK2-NEXT: [[TMP106:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK2-NEXT: [[TMP107:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK2-NEXT: [[SUB171:%.*]] = sub i32 [[TMP106]], [[TMP107]] -// CHECK2-NEXT: [[SUB172:%.*]] = sub i32 [[SUB171]], 1 -// CHECK2-NEXT: [[TMP108:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[ADD173:%.*]] = add i32 [[SUB172]], [[TMP108]] -// CHECK2-NEXT: [[TMP109:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[DIV174:%.*]] = udiv i32 [[ADD173]], [[TMP109]] -// CHECK2-NEXT: [[MUL175:%.*]] = mul i32 1, [[DIV174]] -// CHECK2-NEXT: [[TMP110:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB176:%.*]] = sub i32 [[TMP110]], -63 -// CHECK2-NEXT: [[DIV177:%.*]] = udiv i32 [[SUB176]], 64 -// CHECK2-NEXT: [[MUL178:%.*]] = mul i32 [[MUL175]], [[DIV177]] -// CHECK2-NEXT: [[TMP111:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP112:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB179:%.*]] = sub i32 [[TMP111]], [[TMP112]] -// CHECK2-NEXT: [[SUB180:%.*]] = sub i32 [[SUB179]], 1 -// CHECK2-NEXT: [[ADD181:%.*]] = add i32 [[SUB180]], 1 -// CHECK2-NEXT: [[DIV182:%.*]] = udiv i32 [[ADD181]], 1 -// CHECK2-NEXT: [[MUL183:%.*]] = mul i32 [[MUL178]], [[DIV182]] -// CHECK2-NEXT: [[CONV184:%.*]] = zext i32 [[MUL183]] to i64 -// CHECK2-NEXT: [[MUL185:%.*]] = mul nsw i64 [[DIV170]], [[CONV184]] -// CHECK2-NEXT: [[SUB186:%.*]] = sub nsw i64 [[TMP97]], [[MUL185]] +// CHECK2-NEXT: [[ADD156:%.*]] = add i32 [[SUB155]], [[TMP93]] +// CHECK2-NEXT: [[TMP94:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[DIV157:%.*]] = udiv i32 [[ADD156]], [[TMP94]] +// CHECK2-NEXT: [[MUL158:%.*]] = mul i32 1, [[DIV157]] +// CHECK2-NEXT: [[TMP95:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB159:%.*]] = sub i32 [[TMP95]], -63 +// CHECK2-NEXT: [[DIV160:%.*]] = udiv i32 [[SUB159]], 64 +// CHECK2-NEXT: [[MUL161:%.*]] = mul i32 [[MUL158]], [[DIV160]] +// CHECK2-NEXT: [[MUL162:%.*]] = mul i32 [[MUL161]], 64 +// CHECK2-NEXT: [[CONV163:%.*]] = zext i32 [[MUL162]] to i64 +// CHECK2-NEXT: [[DIV164:%.*]] = sdiv i64 [[TMP90]], [[CONV163]] +// CHECK2-NEXT: [[TMP96:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK2-NEXT: [[TMP97:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK2-NEXT: [[SUB165:%.*]] = sub i32 [[TMP96]], [[TMP97]] +// CHECK2-NEXT: [[SUB166:%.*]] = sub i32 [[SUB165]], 1 +// CHECK2-NEXT: [[TMP98:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[ADD167:%.*]] = add i32 [[SUB166]], [[TMP98]] +// CHECK2-NEXT: [[TMP99:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[DIV168:%.*]] = udiv i32 [[ADD167]], [[TMP99]] +// CHECK2-NEXT: [[MUL169:%.*]] = mul i32 1, [[DIV168]] +// CHECK2-NEXT: [[TMP100:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB170:%.*]] = sub i32 [[TMP100]], -63 +// CHECK2-NEXT: [[DIV171:%.*]] = udiv i32 [[SUB170]], 64 +// CHECK2-NEXT: [[MUL172:%.*]] = mul i32 [[MUL169]], [[DIV171]] +// CHECK2-NEXT: [[MUL173:%.*]] = mul i32 [[MUL172]], 64 +// CHECK2-NEXT: [[CONV174:%.*]] = zext i32 [[MUL173]] to i64 +// CHECK2-NEXT: [[MUL175:%.*]] = mul nsw i64 [[DIV164]], [[CONV174]] +// CHECK2-NEXT: [[SUB176:%.*]] = sub nsw i64 [[TMP89]], [[MUL175]] +// CHECK2-NEXT: [[TMP101:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[TMP102:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[TMP103:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK2-NEXT: [[TMP104:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK2-NEXT: [[SUB177:%.*]] = sub i32 [[TMP103]], [[TMP104]] +// CHECK2-NEXT: [[SUB178:%.*]] = sub i32 [[SUB177]], 1 +// CHECK2-NEXT: [[TMP105:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[ADD179:%.*]] = add i32 [[SUB178]], [[TMP105]] +// CHECK2-NEXT: [[TMP106:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[DIV180:%.*]] = udiv i32 [[ADD179]], [[TMP106]] +// CHECK2-NEXT: [[MUL181:%.*]] = mul i32 1, [[DIV180]] +// CHECK2-NEXT: [[TMP107:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB182:%.*]] = sub i32 [[TMP107]], -63 +// CHECK2-NEXT: [[DIV183:%.*]] = udiv i32 [[SUB182]], 64 +// CHECK2-NEXT: [[MUL184:%.*]] = mul i32 [[MUL181]], [[DIV183]] +// CHECK2-NEXT: [[MUL185:%.*]] = mul i32 [[MUL184]], 64 +// CHECK2-NEXT: [[CONV186:%.*]] = zext i32 [[MUL185]] to i64 +// CHECK2-NEXT: [[DIV187:%.*]] = sdiv i64 [[TMP102]], [[CONV186]] +// CHECK2-NEXT: [[TMP108:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK2-NEXT: [[TMP109:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK2-NEXT: [[SUB188:%.*]] = sub i32 [[TMP108]], [[TMP109]] +// CHECK2-NEXT: [[SUB189:%.*]] = sub i32 [[SUB188]], 1 +// CHECK2-NEXT: [[TMP110:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[ADD190:%.*]] = add i32 [[SUB189]], [[TMP110]] +// CHECK2-NEXT: [[TMP111:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[DIV191:%.*]] = udiv i32 [[ADD190]], [[TMP111]] +// CHECK2-NEXT: [[MUL192:%.*]] = mul i32 1, [[DIV191]] +// CHECK2-NEXT: [[TMP112:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB193:%.*]] = sub i32 [[TMP112]], -63 +// CHECK2-NEXT: [[DIV194:%.*]] = udiv i32 [[SUB193]], 64 +// CHECK2-NEXT: [[MUL195:%.*]] = mul i32 [[MUL192]], [[DIV194]] +// CHECK2-NEXT: [[MUL196:%.*]] = mul i32 [[MUL195]], 64 +// CHECK2-NEXT: [[CONV197:%.*]] = zext i32 [[MUL196]] to i64 +// CHECK2-NEXT: [[MUL198:%.*]] = mul nsw i64 [[DIV187]], [[CONV197]] +// CHECK2-NEXT: [[SUB199:%.*]] = sub nsw i64 [[TMP101]], [[MUL198]] // CHECK2-NEXT: [[TMP113:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB187:%.*]] = sub i32 [[TMP113]], -63 -// CHECK2-NEXT: [[DIV188:%.*]] = udiv i32 [[SUB187]], 64 -// CHECK2-NEXT: [[MUL189:%.*]] = mul i32 1, [[DIV188]] -// CHECK2-NEXT: [[TMP114:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP115:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB190:%.*]] = sub i32 [[TMP114]], [[TMP115]] -// CHECK2-NEXT: [[SUB191:%.*]] = sub i32 [[SUB190]], 1 -// CHECK2-NEXT: [[ADD192:%.*]] = add i32 [[SUB191]], 1 -// CHECK2-NEXT: [[DIV193:%.*]] = udiv i32 [[ADD192]], 1 -// CHECK2-NEXT: [[MUL194:%.*]] = mul i32 [[MUL189]], [[DIV193]] -// CHECK2-NEXT: [[CONV195:%.*]] = zext i32 [[MUL194]] to i64 -// CHECK2-NEXT: [[DIV196:%.*]] = sdiv i64 [[SUB186]], [[CONV195]] -// CHECK2-NEXT: [[TMP116:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB197:%.*]] = sub i32 [[TMP116]], -63 -// CHECK2-NEXT: [[DIV198:%.*]] = udiv i32 [[SUB197]], 64 -// CHECK2-NEXT: [[MUL199:%.*]] = mul i32 1, [[DIV198]] -// CHECK2-NEXT: [[TMP117:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP118:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB200:%.*]] = sub i32 [[TMP117]], [[TMP118]] -// CHECK2-NEXT: [[SUB201:%.*]] = sub i32 [[SUB200]], 1 -// CHECK2-NEXT: [[ADD202:%.*]] = add i32 [[SUB201]], 1 -// CHECK2-NEXT: [[DIV203:%.*]] = udiv i32 [[ADD202]], 1 -// CHECK2-NEXT: [[MUL204:%.*]] = mul i32 [[MUL199]], [[DIV203]] -// CHECK2-NEXT: [[CONV205:%.*]] = zext i32 [[MUL204]] to i64 -// CHECK2-NEXT: [[MUL206:%.*]] = mul nsw i64 [[DIV196]], [[CONV205]] -// CHECK2-NEXT: [[SUB207:%.*]] = sub nsw i64 [[SUB155]], [[MUL206]] -// CHECK2-NEXT: [[TMP119:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP120:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB208:%.*]] = sub i32 [[TMP119]], [[TMP120]] -// CHECK2-NEXT: [[SUB209:%.*]] = sub i32 [[SUB208]], 1 -// CHECK2-NEXT: [[ADD210:%.*]] = add i32 [[SUB209]], 1 -// CHECK2-NEXT: [[DIV211:%.*]] = udiv i32 [[ADD210]], 1 -// CHECK2-NEXT: [[MUL212:%.*]] = mul i32 1, [[DIV211]] -// CHECK2-NEXT: [[CONV213:%.*]] = zext i32 [[MUL212]] to i64 -// CHECK2-NEXT: [[DIV214:%.*]] = sdiv i64 [[SUB207]], [[CONV213]] -// CHECK2-NEXT: [[MUL215:%.*]] = mul nsw i64 [[DIV214]], 64 -// CHECK2-NEXT: [[ADD216:%.*]] = add nsw i64 0, [[MUL215]] -// CHECK2-NEXT: [[CONV217:%.*]] = trunc i64 [[ADD216]] to i32 -// CHECK2-NEXT: store i32 [[CONV217]], ptr [[DOTFLOOR_0_IV_K51]], align 4 -// CHECK2-NEXT: [[TMP121:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[CONV218:%.*]] = zext i32 [[TMP121]] to i64 -// CHECK2-NEXT: [[TMP122:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP123:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP124:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK2-NEXT: [[TMP125:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK2-NEXT: [[SUB219:%.*]] = sub i32 [[TMP124]], [[TMP125]] -// CHECK2-NEXT: [[SUB220:%.*]] = sub i32 [[SUB219]], 1 -// CHECK2-NEXT: [[TMP126:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[ADD221:%.*]] = add i32 [[SUB220]], [[TMP126]] -// CHECK2-NEXT: [[TMP127:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[DIV222:%.*]] = udiv i32 [[ADD221]], [[TMP127]] -// CHECK2-NEXT: [[MUL223:%.*]] = mul i32 1, [[DIV222]] -// CHECK2-NEXT: [[TMP128:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB224:%.*]] = sub i32 [[TMP128]], -63 -// CHECK2-NEXT: [[DIV225:%.*]] = udiv i32 [[SUB224]], 64 -// CHECK2-NEXT: [[MUL226:%.*]] = mul i32 [[MUL223]], [[DIV225]] -// CHECK2-NEXT: [[TMP129:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP130:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB227:%.*]] = sub i32 [[TMP129]], [[TMP130]] -// CHECK2-NEXT: [[SUB228:%.*]] = sub i32 [[SUB227]], 1 -// CHECK2-NEXT: [[ADD229:%.*]] = add i32 [[SUB228]], 1 -// CHECK2-NEXT: [[DIV230:%.*]] = udiv i32 [[ADD229]], 1 -// CHECK2-NEXT: [[MUL231:%.*]] = mul i32 [[MUL226]], [[DIV230]] -// CHECK2-NEXT: [[CONV232:%.*]] = zext i32 [[MUL231]] to i64 -// CHECK2-NEXT: [[DIV233:%.*]] = sdiv i64 [[TMP123]], [[CONV232]] -// CHECK2-NEXT: [[TMP131:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK2-NEXT: [[TMP132:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK2-NEXT: [[SUB234:%.*]] = sub i32 [[TMP131]], [[TMP132]] -// CHECK2-NEXT: [[SUB235:%.*]] = sub i32 [[SUB234]], 1 -// CHECK2-NEXT: [[TMP133:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[ADD236:%.*]] = add i32 [[SUB235]], [[TMP133]] -// CHECK2-NEXT: [[TMP134:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[DIV237:%.*]] = udiv i32 [[ADD236]], [[TMP134]] -// CHECK2-NEXT: [[MUL238:%.*]] = mul i32 1, [[DIV237]] -// CHECK2-NEXT: [[TMP135:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB239:%.*]] = sub i32 [[TMP135]], -63 -// CHECK2-NEXT: [[DIV240:%.*]] = udiv i32 [[SUB239]], 64 -// CHECK2-NEXT: [[MUL241:%.*]] = mul i32 [[MUL238]], [[DIV240]] -// CHECK2-NEXT: [[TMP136:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP137:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB242:%.*]] = sub i32 [[TMP136]], [[TMP137]] -// CHECK2-NEXT: [[SUB243:%.*]] = sub i32 [[SUB242]], 1 -// CHECK2-NEXT: [[ADD244:%.*]] = add i32 [[SUB243]], 1 -// CHECK2-NEXT: [[DIV245:%.*]] = udiv i32 [[ADD244]], 1 -// CHECK2-NEXT: [[MUL246:%.*]] = mul i32 [[MUL241]], [[DIV245]] -// CHECK2-NEXT: [[CONV247:%.*]] = zext i32 [[MUL246]] to i64 -// CHECK2-NEXT: [[MUL248:%.*]] = mul nsw i64 [[DIV233]], [[CONV247]] -// CHECK2-NEXT: [[SUB249:%.*]] = sub nsw i64 [[TMP122]], [[MUL248]] -// CHECK2-NEXT: [[TMP138:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP139:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP140:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK2-NEXT: [[TMP141:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK2-NEXT: [[SUB250:%.*]] = sub i32 [[TMP140]], [[TMP141]] -// CHECK2-NEXT: [[SUB251:%.*]] = sub i32 [[SUB250]], 1 -// CHECK2-NEXT: [[TMP142:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[ADD252:%.*]] = add i32 [[SUB251]], [[TMP142]] -// CHECK2-NEXT: [[TMP143:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[DIV253:%.*]] = udiv i32 [[ADD252]], [[TMP143]] -// CHECK2-NEXT: [[MUL254:%.*]] = mul i32 1, [[DIV253]] -// CHECK2-NEXT: [[TMP144:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB255:%.*]] = sub i32 [[TMP144]], -63 -// CHECK2-NEXT: [[DIV256:%.*]] = udiv i32 [[SUB255]], 64 -// CHECK2-NEXT: [[MUL257:%.*]] = mul i32 [[MUL254]], [[DIV256]] -// CHECK2-NEXT: [[TMP145:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP146:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB258:%.*]] = sub i32 [[TMP145]], [[TMP146]] -// CHECK2-NEXT: [[SUB259:%.*]] = sub i32 [[SUB258]], 1 -// CHECK2-NEXT: [[ADD260:%.*]] = add i32 [[SUB259]], 1 -// CHECK2-NEXT: [[DIV261:%.*]] = udiv i32 [[ADD260]], 1 -// CHECK2-NEXT: [[MUL262:%.*]] = mul i32 [[MUL257]], [[DIV261]] +// CHECK2-NEXT: [[SUB200:%.*]] = sub i32 [[TMP113]], -63 +// CHECK2-NEXT: [[DIV201:%.*]] = udiv i32 [[SUB200]], 64 +// CHECK2-NEXT: [[MUL202:%.*]] = mul i32 1, [[DIV201]] +// CHECK2-NEXT: [[MUL203:%.*]] = mul i32 [[MUL202]], 64 +// CHECK2-NEXT: [[CONV204:%.*]] = zext i32 [[MUL203]] to i64 +// CHECK2-NEXT: [[DIV205:%.*]] = sdiv i64 [[SUB199]], [[CONV204]] +// CHECK2-NEXT: [[TMP114:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB206:%.*]] = sub i32 [[TMP114]], -63 +// CHECK2-NEXT: [[DIV207:%.*]] = udiv i32 [[SUB206]], 64 +// CHECK2-NEXT: [[MUL208:%.*]] = mul i32 1, [[DIV207]] +// CHECK2-NEXT: [[MUL209:%.*]] = mul i32 [[MUL208]], 64 +// CHECK2-NEXT: [[CONV210:%.*]] = zext i32 [[MUL209]] to i64 +// CHECK2-NEXT: [[MUL211:%.*]] = mul nsw i64 [[DIV205]], [[CONV210]] +// CHECK2-NEXT: [[SUB212:%.*]] = sub nsw i64 [[SUB176]], [[MUL211]] +// CHECK2-NEXT: [[TMP115:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[TMP116:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[TMP117:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK2-NEXT: [[TMP118:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK2-NEXT: [[SUB213:%.*]] = sub i32 [[TMP117]], [[TMP118]] +// CHECK2-NEXT: [[SUB214:%.*]] = sub i32 [[SUB213]], 1 +// CHECK2-NEXT: [[TMP119:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[ADD215:%.*]] = add i32 [[SUB214]], [[TMP119]] +// CHECK2-NEXT: [[TMP120:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[DIV216:%.*]] = udiv i32 [[ADD215]], [[TMP120]] +// CHECK2-NEXT: [[MUL217:%.*]] = mul i32 1, [[DIV216]] +// CHECK2-NEXT: [[TMP121:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB218:%.*]] = sub i32 [[TMP121]], -63 +// CHECK2-NEXT: [[DIV219:%.*]] = udiv i32 [[SUB218]], 64 +// CHECK2-NEXT: [[MUL220:%.*]] = mul i32 [[MUL217]], [[DIV219]] +// CHECK2-NEXT: [[MUL221:%.*]] = mul i32 [[MUL220]], 64 +// CHECK2-NEXT: [[CONV222:%.*]] = zext i32 [[MUL221]] to i64 +// CHECK2-NEXT: [[DIV223:%.*]] = sdiv i64 [[TMP116]], [[CONV222]] +// CHECK2-NEXT: [[TMP122:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK2-NEXT: [[TMP123:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK2-NEXT: [[SUB224:%.*]] = sub i32 [[TMP122]], [[TMP123]] +// CHECK2-NEXT: [[SUB225:%.*]] = sub i32 [[SUB224]], 1 +// CHECK2-NEXT: [[TMP124:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[ADD226:%.*]] = add i32 [[SUB225]], [[TMP124]] +// CHECK2-NEXT: [[TMP125:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[DIV227:%.*]] = udiv i32 [[ADD226]], [[TMP125]] +// CHECK2-NEXT: [[MUL228:%.*]] = mul i32 1, [[DIV227]] +// CHECK2-NEXT: [[TMP126:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB229:%.*]] = sub i32 [[TMP126]], -63 +// CHECK2-NEXT: [[DIV230:%.*]] = udiv i32 [[SUB229]], 64 +// CHECK2-NEXT: [[MUL231:%.*]] = mul i32 [[MUL228]], [[DIV230]] +// CHECK2-NEXT: [[MUL232:%.*]] = mul i32 [[MUL231]], 64 +// CHECK2-NEXT: [[CONV233:%.*]] = zext i32 [[MUL232]] to i64 +// CHECK2-NEXT: [[MUL234:%.*]] = mul nsw i64 [[DIV223]], [[CONV233]] +// CHECK2-NEXT: [[SUB235:%.*]] = sub nsw i64 [[TMP115]], [[MUL234]] +// CHECK2-NEXT: [[TMP127:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[TMP128:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[TMP129:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK2-NEXT: [[TMP130:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK2-NEXT: [[SUB236:%.*]] = sub i32 [[TMP129]], [[TMP130]] +// CHECK2-NEXT: [[SUB237:%.*]] = sub i32 [[SUB236]], 1 +// CHECK2-NEXT: [[TMP131:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[ADD238:%.*]] = add i32 [[SUB237]], [[TMP131]] +// CHECK2-NEXT: [[TMP132:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[DIV239:%.*]] = udiv i32 [[ADD238]], [[TMP132]] +// CHECK2-NEXT: [[MUL240:%.*]] = mul i32 1, [[DIV239]] +// CHECK2-NEXT: [[TMP133:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB241:%.*]] = sub i32 [[TMP133]], -63 +// CHECK2-NEXT: [[DIV242:%.*]] = udiv i32 [[SUB241]], 64 +// CHECK2-NEXT: [[MUL243:%.*]] = mul i32 [[MUL240]], [[DIV242]] +// CHECK2-NEXT: [[MUL244:%.*]] = mul i32 [[MUL243]], 64 +// CHECK2-NEXT: [[CONV245:%.*]] = zext i32 [[MUL244]] to i64 +// CHECK2-NEXT: [[DIV246:%.*]] = sdiv i64 [[TMP128]], [[CONV245]] +// CHECK2-NEXT: [[TMP134:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 +// CHECK2-NEXT: [[TMP135:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// CHECK2-NEXT: [[SUB247:%.*]] = sub i32 [[TMP134]], [[TMP135]] +// CHECK2-NEXT: [[SUB248:%.*]] = sub i32 [[SUB247]], 1 +// CHECK2-NEXT: [[TMP136:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[ADD249:%.*]] = add i32 [[SUB248]], [[TMP136]] +// CHECK2-NEXT: [[TMP137:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 +// CHECK2-NEXT: [[DIV250:%.*]] = udiv i32 [[ADD249]], [[TMP137]] +// CHECK2-NEXT: [[MUL251:%.*]] = mul i32 1, [[DIV250]] +// CHECK2-NEXT: [[TMP138:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB252:%.*]] = sub i32 [[TMP138]], -63 +// CHECK2-NEXT: [[DIV253:%.*]] = udiv i32 [[SUB252]], 64 +// CHECK2-NEXT: [[MUL254:%.*]] = mul i32 [[MUL251]], [[DIV253]] +// CHECK2-NEXT: [[MUL255:%.*]] = mul i32 [[MUL254]], 64 +// CHECK2-NEXT: [[CONV256:%.*]] = zext i32 [[MUL255]] to i64 +// CHECK2-NEXT: [[MUL257:%.*]] = mul nsw i64 [[DIV246]], [[CONV256]] +// CHECK2-NEXT: [[SUB258:%.*]] = sub nsw i64 [[TMP127]], [[MUL257]] +// CHECK2-NEXT: [[TMP139:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB259:%.*]] = sub i32 [[TMP139]], -63 +// CHECK2-NEXT: [[DIV260:%.*]] = udiv i32 [[SUB259]], 64 +// CHECK2-NEXT: [[MUL261:%.*]] = mul i32 1, [[DIV260]] +// CHECK2-NEXT: [[MUL262:%.*]] = mul i32 [[MUL261]], 64 // CHECK2-NEXT: [[CONV263:%.*]] = zext i32 [[MUL262]] to i64 -// CHECK2-NEXT: [[DIV264:%.*]] = sdiv i64 [[TMP139]], [[CONV263]] -// CHECK2-NEXT: [[TMP147:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK2-NEXT: [[TMP148:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK2-NEXT: [[SUB265:%.*]] = sub i32 [[TMP147]], [[TMP148]] -// CHECK2-NEXT: [[SUB266:%.*]] = sub i32 [[SUB265]], 1 -// CHECK2-NEXT: [[TMP149:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[ADD267:%.*]] = add i32 [[SUB266]], [[TMP149]] -// CHECK2-NEXT: [[TMP150:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[DIV268:%.*]] = udiv i32 [[ADD267]], [[TMP150]] -// CHECK2-NEXT: [[MUL269:%.*]] = mul i32 1, [[DIV268]] -// CHECK2-NEXT: [[TMP151:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB270:%.*]] = sub i32 [[TMP151]], -63 -// CHECK2-NEXT: [[DIV271:%.*]] = udiv i32 [[SUB270]], 64 -// CHECK2-NEXT: [[MUL272:%.*]] = mul i32 [[MUL269]], [[DIV271]] -// CHECK2-NEXT: [[TMP152:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP153:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB273:%.*]] = sub i32 [[TMP152]], [[TMP153]] -// CHECK2-NEXT: [[SUB274:%.*]] = sub i32 [[SUB273]], 1 -// CHECK2-NEXT: [[ADD275:%.*]] = add i32 [[SUB274]], 1 -// CHECK2-NEXT: [[DIV276:%.*]] = udiv i32 [[ADD275]], 1 -// CHECK2-NEXT: [[MUL277:%.*]] = mul i32 [[MUL272]], [[DIV276]] -// CHECK2-NEXT: [[CONV278:%.*]] = zext i32 [[MUL277]] to i64 -// CHECK2-NEXT: [[MUL279:%.*]] = mul nsw i64 [[DIV264]], [[CONV278]] -// CHECK2-NEXT: [[SUB280:%.*]] = sub nsw i64 [[TMP138]], [[MUL279]] -// CHECK2-NEXT: [[TMP154:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB281:%.*]] = sub i32 [[TMP154]], -63 -// CHECK2-NEXT: [[DIV282:%.*]] = udiv i32 [[SUB281]], 64 -// CHECK2-NEXT: [[MUL283:%.*]] = mul i32 1, [[DIV282]] -// CHECK2-NEXT: [[TMP155:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP156:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB284:%.*]] = sub i32 [[TMP155]], [[TMP156]] -// CHECK2-NEXT: [[SUB285:%.*]] = sub i32 [[SUB284]], 1 -// CHECK2-NEXT: [[ADD286:%.*]] = add i32 [[SUB285]], 1 -// CHECK2-NEXT: [[DIV287:%.*]] = udiv i32 [[ADD286]], 1 -// CHECK2-NEXT: [[MUL288:%.*]] = mul i32 [[MUL283]], [[DIV287]] -// CHECK2-NEXT: [[CONV289:%.*]] = zext i32 [[MUL288]] to i64 -// CHECK2-NEXT: [[DIV290:%.*]] = sdiv i64 [[SUB280]], [[CONV289]] -// CHECK2-NEXT: [[TMP157:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB291:%.*]] = sub i32 [[TMP157]], -63 -// CHECK2-NEXT: [[DIV292:%.*]] = udiv i32 [[SUB291]], 64 -// CHECK2-NEXT: [[MUL293:%.*]] = mul i32 1, [[DIV292]] -// CHECK2-NEXT: [[TMP158:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP159:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB294:%.*]] = sub i32 [[TMP158]], [[TMP159]] -// CHECK2-NEXT: [[SUB295:%.*]] = sub i32 [[SUB294]], 1 -// CHECK2-NEXT: [[ADD296:%.*]] = add i32 [[SUB295]], 1 -// CHECK2-NEXT: [[DIV297:%.*]] = udiv i32 [[ADD296]], 1 -// CHECK2-NEXT: [[MUL298:%.*]] = mul i32 [[MUL293]], [[DIV297]] -// CHECK2-NEXT: [[CONV299:%.*]] = zext i32 [[MUL298]] to i64 -// CHECK2-NEXT: [[MUL300:%.*]] = mul nsw i64 [[DIV290]], [[CONV299]] -// CHECK2-NEXT: [[SUB301:%.*]] = sub nsw i64 [[SUB249]], [[MUL300]] -// CHECK2-NEXT: [[TMP160:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP161:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP162:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK2-NEXT: [[TMP163:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK2-NEXT: [[SUB302:%.*]] = sub i32 [[TMP162]], [[TMP163]] -// CHECK2-NEXT: [[SUB303:%.*]] = sub i32 [[SUB302]], 1 -// CHECK2-NEXT: [[TMP164:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[ADD304:%.*]] = add i32 [[SUB303]], [[TMP164]] -// CHECK2-NEXT: [[TMP165:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[DIV305:%.*]] = udiv i32 [[ADD304]], [[TMP165]] -// CHECK2-NEXT: [[MUL306:%.*]] = mul i32 1, [[DIV305]] -// CHECK2-NEXT: [[TMP166:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB307:%.*]] = sub i32 [[TMP166]], -63 -// CHECK2-NEXT: [[DIV308:%.*]] = udiv i32 [[SUB307]], 64 -// CHECK2-NEXT: [[MUL309:%.*]] = mul i32 [[MUL306]], [[DIV308]] -// CHECK2-NEXT: [[TMP167:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP168:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB310:%.*]] = sub i32 [[TMP167]], [[TMP168]] -// CHECK2-NEXT: [[SUB311:%.*]] = sub i32 [[SUB310]], 1 -// CHECK2-NEXT: [[ADD312:%.*]] = add i32 [[SUB311]], 1 -// CHECK2-NEXT: [[DIV313:%.*]] = udiv i32 [[ADD312]], 1 -// CHECK2-NEXT: [[MUL314:%.*]] = mul i32 [[MUL309]], [[DIV313]] -// CHECK2-NEXT: [[CONV315:%.*]] = zext i32 [[MUL314]] to i64 -// CHECK2-NEXT: [[DIV316:%.*]] = sdiv i64 [[TMP161]], [[CONV315]] -// CHECK2-NEXT: [[TMP169:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK2-NEXT: [[TMP170:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK2-NEXT: [[SUB317:%.*]] = sub i32 [[TMP169]], [[TMP170]] -// CHECK2-NEXT: [[SUB318:%.*]] = sub i32 [[SUB317]], 1 -// CHECK2-NEXT: [[TMP171:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[ADD319:%.*]] = add i32 [[SUB318]], [[TMP171]] -// CHECK2-NEXT: [[TMP172:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[DIV320:%.*]] = udiv i32 [[ADD319]], [[TMP172]] -// CHECK2-NEXT: [[MUL321:%.*]] = mul i32 1, [[DIV320]] -// CHECK2-NEXT: [[TMP173:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB322:%.*]] = sub i32 [[TMP173]], -63 -// CHECK2-NEXT: [[DIV323:%.*]] = udiv i32 [[SUB322]], 64 -// CHECK2-NEXT: [[MUL324:%.*]] = mul i32 [[MUL321]], [[DIV323]] -// CHECK2-NEXT: [[TMP174:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP175:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB325:%.*]] = sub i32 [[TMP174]], [[TMP175]] -// CHECK2-NEXT: [[SUB326:%.*]] = sub i32 [[SUB325]], 1 -// CHECK2-NEXT: [[ADD327:%.*]] = add i32 [[SUB326]], 1 -// CHECK2-NEXT: [[DIV328:%.*]] = udiv i32 [[ADD327]], 1 -// CHECK2-NEXT: [[MUL329:%.*]] = mul i32 [[MUL324]], [[DIV328]] -// CHECK2-NEXT: [[CONV330:%.*]] = zext i32 [[MUL329]] to i64 -// CHECK2-NEXT: [[MUL331:%.*]] = mul nsw i64 [[DIV316]], [[CONV330]] -// CHECK2-NEXT: [[SUB332:%.*]] = sub nsw i64 [[TMP160]], [[MUL331]] -// CHECK2-NEXT: [[TMP176:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP177:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP178:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK2-NEXT: [[TMP179:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK2-NEXT: [[SUB333:%.*]] = sub i32 [[TMP178]], [[TMP179]] -// CHECK2-NEXT: [[SUB334:%.*]] = sub i32 [[SUB333]], 1 -// CHECK2-NEXT: [[TMP180:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[ADD335:%.*]] = add i32 [[SUB334]], [[TMP180]] -// CHECK2-NEXT: [[TMP181:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[DIV336:%.*]] = udiv i32 [[ADD335]], [[TMP181]] -// CHECK2-NEXT: [[MUL337:%.*]] = mul i32 1, [[DIV336]] -// CHECK2-NEXT: [[TMP182:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB338:%.*]] = sub i32 [[TMP182]], -63 -// CHECK2-NEXT: [[DIV339:%.*]] = udiv i32 [[SUB338]], 64 -// CHECK2-NEXT: [[MUL340:%.*]] = mul i32 [[MUL337]], [[DIV339]] -// CHECK2-NEXT: [[TMP183:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP184:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB341:%.*]] = sub i32 [[TMP183]], [[TMP184]] -// CHECK2-NEXT: [[SUB342:%.*]] = sub i32 [[SUB341]], 1 -// CHECK2-NEXT: [[ADD343:%.*]] = add i32 [[SUB342]], 1 -// CHECK2-NEXT: [[DIV344:%.*]] = udiv i32 [[ADD343]], 1 -// CHECK2-NEXT: [[MUL345:%.*]] = mul i32 [[MUL340]], [[DIV344]] -// CHECK2-NEXT: [[CONV346:%.*]] = zext i32 [[MUL345]] to i64 -// CHECK2-NEXT: [[DIV347:%.*]] = sdiv i64 [[TMP177]], [[CONV346]] -// CHECK2-NEXT: [[TMP185:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_6]], align 4 -// CHECK2-NEXT: [[TMP186:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 -// CHECK2-NEXT: [[SUB348:%.*]] = sub i32 [[TMP185]], [[TMP186]] -// CHECK2-NEXT: [[SUB349:%.*]] = sub i32 [[SUB348]], 1 -// CHECK2-NEXT: [[TMP187:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[ADD350:%.*]] = add i32 [[SUB349]], [[TMP187]] -// CHECK2-NEXT: [[TMP188:%.*]] = load i32, ptr [[DOTNEW_STEP7]], align 4 -// CHECK2-NEXT: [[DIV351:%.*]] = udiv i32 [[ADD350]], [[TMP188]] -// CHECK2-NEXT: [[MUL352:%.*]] = mul i32 1, [[DIV351]] -// CHECK2-NEXT: [[TMP189:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB353:%.*]] = sub i32 [[TMP189]], -63 -// CHECK2-NEXT: [[DIV354:%.*]] = udiv i32 [[SUB353]], 64 -// CHECK2-NEXT: [[MUL355:%.*]] = mul i32 [[MUL352]], [[DIV354]] -// CHECK2-NEXT: [[TMP190:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP191:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB356:%.*]] = sub i32 [[TMP190]], [[TMP191]] -// CHECK2-NEXT: [[SUB357:%.*]] = sub i32 [[SUB356]], 1 -// CHECK2-NEXT: [[ADD358:%.*]] = add i32 [[SUB357]], 1 -// CHECK2-NEXT: [[DIV359:%.*]] = udiv i32 [[ADD358]], 1 -// CHECK2-NEXT: [[MUL360:%.*]] = mul i32 [[MUL355]], [[DIV359]] -// CHECK2-NEXT: [[CONV361:%.*]] = zext i32 [[MUL360]] to i64 -// CHECK2-NEXT: [[MUL362:%.*]] = mul nsw i64 [[DIV347]], [[CONV361]] -// CHECK2-NEXT: [[SUB363:%.*]] = sub nsw i64 [[TMP176]], [[MUL362]] -// CHECK2-NEXT: [[TMP192:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB364:%.*]] = sub i32 [[TMP192]], -63 -// CHECK2-NEXT: [[DIV365:%.*]] = udiv i32 [[SUB364]], 64 -// CHECK2-NEXT: [[MUL366:%.*]] = mul i32 1, [[DIV365]] -// CHECK2-NEXT: [[TMP193:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP194:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB367:%.*]] = sub i32 [[TMP193]], [[TMP194]] -// CHECK2-NEXT: [[SUB368:%.*]] = sub i32 [[SUB367]], 1 -// CHECK2-NEXT: [[ADD369:%.*]] = add i32 [[SUB368]], 1 -// CHECK2-NEXT: [[DIV370:%.*]] = udiv i32 [[ADD369]], 1 -// CHECK2-NEXT: [[MUL371:%.*]] = mul i32 [[MUL366]], [[DIV370]] -// CHECK2-NEXT: [[CONV372:%.*]] = zext i32 [[MUL371]] to i64 -// CHECK2-NEXT: [[DIV373:%.*]] = sdiv i64 [[SUB363]], [[CONV372]] -// CHECK2-NEXT: [[TMP195:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 -// CHECK2-NEXT: [[SUB374:%.*]] = sub i32 [[TMP195]], -63 -// CHECK2-NEXT: [[DIV375:%.*]] = udiv i32 [[SUB374]], 64 -// CHECK2-NEXT: [[MUL376:%.*]] = mul i32 1, [[DIV375]] -// CHECK2-NEXT: [[TMP196:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP197:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB377:%.*]] = sub i32 [[TMP196]], [[TMP197]] -// CHECK2-NEXT: [[SUB378:%.*]] = sub i32 [[SUB377]], 1 -// CHECK2-NEXT: [[ADD379:%.*]] = add i32 [[SUB378]], 1 -// CHECK2-NEXT: [[DIV380:%.*]] = udiv i32 [[ADD379]], 1 -// CHECK2-NEXT: [[MUL381:%.*]] = mul i32 [[MUL376]], [[DIV380]] -// CHECK2-NEXT: [[CONV382:%.*]] = zext i32 [[MUL381]] to i64 -// CHECK2-NEXT: [[MUL383:%.*]] = mul nsw i64 [[DIV373]], [[CONV382]] -// CHECK2-NEXT: [[SUB384:%.*]] = sub nsw i64 [[SUB332]], [[MUL383]] -// CHECK2-NEXT: [[TMP198:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP199:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB385:%.*]] = sub i32 [[TMP198]], [[TMP199]] -// CHECK2-NEXT: [[SUB386:%.*]] = sub i32 [[SUB385]], 1 -// CHECK2-NEXT: [[ADD387:%.*]] = add i32 [[SUB386]], 1 -// CHECK2-NEXT: [[DIV388:%.*]] = udiv i32 [[ADD387]], 1 -// CHECK2-NEXT: [[MUL389:%.*]] = mul i32 1, [[DIV388]] -// CHECK2-NEXT: [[CONV390:%.*]] = zext i32 [[MUL389]] to i64 -// CHECK2-NEXT: [[DIV391:%.*]] = sdiv i64 [[SUB384]], [[CONV390]] -// CHECK2-NEXT: [[TMP200:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4 -// CHECK2-NEXT: [[TMP201:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_16]], align 4 -// CHECK2-NEXT: [[SUB392:%.*]] = sub i32 [[TMP200]], [[TMP201]] -// CHECK2-NEXT: [[SUB393:%.*]] = sub i32 [[SUB392]], 1 -// CHECK2-NEXT: [[ADD394:%.*]] = add i32 [[SUB393]], 1 -// CHECK2-NEXT: [[DIV395:%.*]] = udiv i32 [[ADD394]], 1 -// CHECK2-NEXT: [[MUL396:%.*]] = mul i32 1, [[DIV395]] -// CHECK2-NEXT: [[CONV397:%.*]] = zext i32 [[MUL396]] to i64 -// CHECK2-NEXT: [[MUL398:%.*]] = mul nsw i64 [[DIV391]], [[CONV397]] -// CHECK2-NEXT: [[SUB399:%.*]] = sub nsw i64 [[SUB301]], [[MUL398]] -// CHECK2-NEXT: [[MUL400:%.*]] = mul nsw i64 [[SUB399]], 1 -// CHECK2-NEXT: [[ADD401:%.*]] = add nsw i64 [[CONV218]], [[MUL400]] -// CHECK2-NEXT: [[CONV402:%.*]] = trunc i64 [[ADD401]] to i32 -// CHECK2-NEXT: store i32 [[CONV402]], ptr [[DOTTILE_0_IV_K52]], align 4 -// CHECK2-NEXT: [[TMP202:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 4 -// CHECK2-NEXT: [[TMP203:%.*]] = load i32, ptr [[DOTTILE_0_IV_K52]], align 4 -// CHECK2-NEXT: [[TMP204:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4 -// CHECK2-NEXT: [[MUL403:%.*]] = mul i32 [[TMP203]], [[TMP204]] -// CHECK2-NEXT: [[ADD404:%.*]] = add i32 [[TMP202]], [[MUL403]] -// CHECK2-NEXT: store i32 [[ADD404]], ptr [[K]], align 4 -// CHECK2-NEXT: [[TMP205:%.*]] = load i32, ptr [[I49]], align 4 -// CHECK2-NEXT: [[TMP206:%.*]] = load i32, ptr [[J50]], align 4 -// CHECK2-NEXT: [[TMP207:%.*]] = load i32, ptr [[K]], align 4 -// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP205]], i32 noundef [[TMP206]], i32 noundef [[TMP207]]) +// CHECK2-NEXT: [[DIV264:%.*]] = sdiv i64 [[SUB258]], [[CONV263]] +// CHECK2-NEXT: [[TMP140:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_14]], align 4 +// CHECK2-NEXT: [[SUB265:%.*]] = sub i32 [[TMP140]], -63 +// CHECK2-NEXT: [[DIV266:%.*]] = udiv i32 [[SUB265]], 64 +// CHECK2-NEXT: [[MUL267:%.*]] = mul i32 1, [[DIV266]] +// CHECK2-NEXT: [[MUL268:%.*]] = mul i32 [[MUL267]], 64 +// CHECK2-NEXT: [[CONV269:%.*]] = zext i32 [[MUL268]] to i64 +// CHECK2-NEXT: [[MUL270:%.*]] = mul nsw i64 [[DIV264]], [[CONV269]] +// CHECK2-NEXT: [[SUB271:%.*]] = sub nsw i64 [[SUB235]], [[MUL270]] +// CHECK2-NEXT: [[DIV272:%.*]] = sdiv i64 [[SUB271]], 64 +// CHECK2-NEXT: [[MUL273:%.*]] = mul nsw i64 [[DIV272]], 64 +// CHECK2-NEXT: [[SUB274:%.*]] = sub nsw i64 [[SUB212]], [[MUL273]] +// CHECK2-NEXT: [[MUL275:%.*]] = mul nsw i64 [[SUB274]], 1 +// CHECK2-NEXT: [[ADD276:%.*]] = add nsw i64 0, [[MUL275]] +// CHECK2-NEXT: [[CONV277:%.*]] = trunc i64 [[ADD276]] to i32 +// CHECK2-NEXT: store i32 [[CONV277]], ptr [[DOTTILE_CNT_0_IV_K38]], align 4 +// CHECK2-NEXT: [[TMP141:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_K37]], align 4 +// CHECK2-NEXT: [[TMP142:%.*]] = load i32, ptr [[DOTTILE_CNT_0_IV_K38]], align 4 +// CHECK2-NEXT: [[ADD278:%.*]] = add i32 [[TMP141]], [[TMP142]] +// CHECK2-NEXT: store i32 [[ADD278]], ptr [[DOTTILE_0_IV_K]], align 4 +// CHECK2-NEXT: [[TMP143:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_8]], align 4 +// CHECK2-NEXT: [[TMP144:%.*]] = load i32, ptr [[DOTTILE_0_IV_K]], align 4 +// CHECK2-NEXT: [[TMP145:%.*]] = load i32, ptr [[DOTNEW_STEP10]], align 4 +// CHECK2-NEXT: [[MUL279:%.*]] = mul i32 [[TMP144]], [[TMP145]] +// CHECK2-NEXT: [[ADD280:%.*]] = add i32 [[TMP143]], [[MUL279]] +// CHECK2-NEXT: store i32 [[ADD280]], ptr [[K]], align 4 +// CHECK2-NEXT: [[TMP146:%.*]] = load i32, ptr [[DOTTILE_0_IV_K]], align 4 +// CHECK2-NEXT: [[TMP147:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4 +// CHECK2-NEXT: [[ADD281:%.*]] = add i32 [[TMP147]], 1 +// CHECK2-NEXT: [[CMP282:%.*]] = icmp ult i32 [[TMP146]], [[ADD281]] +// CHECK2-NEXT: br i1 [[CMP282]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] +// CHECK2: if.then: +// CHECK2-NEXT: [[TMP148:%.*]] = load i32, ptr [[I35]], align 4 +// CHECK2-NEXT: [[TMP149:%.*]] = load i32, ptr [[J36]], align 4 +// CHECK2-NEXT: [[TMP150:%.*]] = load i32, ptr [[K]], align 4 +// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP148]], i32 noundef [[TMP149]], i32 noundef [[TMP150]]) +// CHECK2-NEXT: br label [[IF_END]] +// CHECK2: if.end: // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP208:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[ADD405:%.*]] = add nsw i64 [[TMP208]], 1 -// CHECK2-NEXT: store i64 [[ADD405]], ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[TMP151:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[ADD283:%.*]] = add nsw i64 [[TMP151]], 1 +// CHECK2-NEXT: store i64 [[ADD283]], ptr [[DOTOMP_IV]], align 8 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -5321,4 +4606,4 @@ extern "C" void foo10() { // CHECK2: omp.precond.end: // CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]]) // CHECK2-NEXT: ret void - +// diff --git a/clang/test/OpenMP/irbuilder_unroll_partial_factor_for.c b/clang/test/OpenMP/irbuilder_unroll_partial_factor_for.c index cf4fa21c9a31c..43711af5f2e33 100644 --- a/clang/test/OpenMP/irbuilder_unroll_partial_factor_for.c +++ b/clang/test/OpenMP/irbuilder_unroll_partial_factor_for.c @@ -79,8 +79,6 @@ void unroll_partial_heuristic_for(int n, float *a, float *b, float *c, float *d) // CHECK-NEXT: br i1 [[OMP_FLOOR0_CMP]], label [[OMP_FLOOR0_BODY:%.*]], label [[OMP_FLOOR0_EXIT:%.*]] // CHECK: omp_floor0.body: // CHECK-NEXT: [[TMP13:%.*]] = add i32 [[OMP_FLOOR0_IV]], [[TMP9]] -// CHECK-NEXT: [[TMP14:%.*]] = icmp eq i32 [[TMP13]], [[TMP4]] -// CHECK-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i32 [[TMP5]], i32 13 // CHECK-NEXT: br label [[OMP_TILE0_PREHEADER:%.*]] // CHECK: omp_tile0.preheader: // CHECK-NEXT: br label [[OMP_TILE0_HEADER:%.*]] @@ -88,36 +86,39 @@ void unroll_partial_heuristic_for(int n, float *a, float *b, float *c, float *d) // CHECK-NEXT: [[OMP_TILE0_IV:%.*]] = phi i32 [ 0, [[OMP_TILE0_PREHEADER]] ], [ [[OMP_TILE0_NEXT:%.*]], [[OMP_TILE0_INC:%.*]] ] // CHECK-NEXT: br label [[OMP_TILE0_COND:%.*]] // CHECK: omp_tile0.cond: -// CHECK-NEXT: [[OMP_TILE0_CMP:%.*]] = icmp ult i32 [[OMP_TILE0_IV]], [[TMP15]] +// CHECK-NEXT: [[OMP_TILE0_CMP:%.*]] = icmp ult i32 [[OMP_TILE0_IV]], 13 // CHECK-NEXT: br i1 [[OMP_TILE0_CMP]], label [[OMP_TILE0_BODY:%.*]], label [[OMP_TILE0_EXIT:%.*]] // CHECK: omp_tile0.body: -// CHECK-NEXT: [[TMP16:%.*]] = mul nuw i32 13, [[TMP13]] -// CHECK-NEXT: [[TMP17:%.*]] = add nuw i32 [[TMP16]], [[OMP_TILE0_IV]] -// CHECK-NEXT: br label [[OMP_LOOP_BODY:%.*]] +// CHECK-NEXT: [[TMP14:%.*]] = mul nuw i32 13, [[TMP13]] +// CHECK-NEXT: [[TMP15:%.*]] = add nuw i32 [[TMP14]], [[OMP_TILE0_IV]] +// CHECK-NEXT: [[OMP_TILE0_INBOUNDS:%.*]] = icmp ult i32 [[TMP15]], [[DOTCOUNT]] +// CHECK-NEXT: br i1 [[OMP_TILE0_INBOUNDS]], label [[OMP_LOOP_BODY:%.*]], label [[OMP_TILE_BODY_MERGE:%.*]] // CHECK: omp_loop.body: -// CHECK-NEXT: call void @__captured_stmt.1(ptr [[I]], i32 [[TMP17]], ptr [[AGG_CAPTURED1]]) -// CHECK-NEXT: [[TMP18:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 -// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM]] -// CHECK-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4 -// CHECK-NEXT: [[TMP21:%.*]] = load ptr, ptr [[C_ADDR]], align 8 -// CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[I]], align 4 -// CHECK-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP22]] to i64 -// CHECK-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM2]] -// CHECK-NEXT: [[TMP23:%.*]] = load float, ptr [[ARRAYIDX3]], align 4 -// CHECK-NEXT: [[MUL:%.*]] = fmul float [[TMP20]], [[TMP23]] -// CHECK-NEXT: [[TMP24:%.*]] = load ptr, ptr [[D_ADDR]], align 8 -// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[I]], align 4 -// CHECK-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP25]] to i64 -// CHECK-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP24]], i64 [[IDXPROM4]] -// CHECK-NEXT: [[TMP26:%.*]] = load float, ptr [[ARRAYIDX5]], align 4 -// CHECK-NEXT: [[MUL6:%.*]] = fmul float [[MUL]], [[TMP26]] -// CHECK-NEXT: [[TMP27:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK-NEXT: [[TMP28:%.*]] = load i32, ptr [[I]], align 4 -// CHECK-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP28]] to i64 -// CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, ptr [[TMP27]], i64 [[IDXPROM7]] +// CHECK-NEXT: call void @__captured_stmt.1(ptr [[I]], i32 [[TMP15]], ptr [[AGG_CAPTURED1]]) +// CHECK-NEXT: [[TMP16:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: [[TMP19:%.*]] = load ptr, ptr [[C_ADDR]], align 8 +// CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[I]], align 4 +// CHECK-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP20]] to i64 +// CHECK-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP19]], i64 [[IDXPROM2]] +// CHECK-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX3]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = fmul float [[TMP18]], [[TMP21]] +// CHECK-NEXT: [[TMP22:%.*]] = load ptr, ptr [[D_ADDR]], align 8 +// CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[I]], align 4 +// CHECK-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP23]] to i64 +// CHECK-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP22]], i64 [[IDXPROM4]] +// CHECK-NEXT: [[TMP24:%.*]] = load float, ptr [[ARRAYIDX5]], align 4 +// CHECK-NEXT: [[MUL6:%.*]] = fmul float [[MUL]], [[TMP24]] +// CHECK-NEXT: [[TMP25:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr [[I]], align 4 +// CHECK-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP26]] to i64 +// CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, ptr [[TMP25]], i64 [[IDXPROM7]] // CHECK-NEXT: store float [[MUL6]], ptr [[ARRAYIDX8]], align 4 +// CHECK-NEXT: br label [[OMP_TILE_BODY_MERGE]] +// CHECK: omp_tile.body.merge: // CHECK-NEXT: br label [[OMP_TILE0_INC]] // CHECK: omp_tile0.inc: // CHECK-NEXT: [[OMP_TILE0_NEXT]] = add nuw i32 [[OMP_TILE0_IV]], 1 diff --git a/clang/test/OpenMP/irbuilder_unroll_partial_heuristic_constant_for.c b/clang/test/OpenMP/irbuilder_unroll_partial_heuristic_constant_for.c index acf0e5164411c..b8a993c9cd8a7 100644 --- a/clang/test/OpenMP/irbuilder_unroll_partial_heuristic_constant_for.c +++ b/clang/test/OpenMP/irbuilder_unroll_partial_heuristic_constant_for.c @@ -85,8 +85,6 @@ void unroll_partial_heuristic_constant_for(float *a, float *b, float *c, float * // CHECK-NEXT: br i1 [[OMP_FLOOR0_CMP]], label [[OMP_FLOOR0_BODY:%.*]], label [[OMP_FLOOR0_EXIT:%.*]] // CHECK: omp_floor0.body: // CHECK-NEXT: [[TMP12:%.*]] = add i32 [[OMP_FLOOR0_IV]], [[TMP8]] -// CHECK-NEXT: [[TMP13:%.*]] = icmp eq i32 [[TMP12]], [[TMP3]] -// CHECK-NEXT: [[TMP14:%.*]] = select i1 [[TMP13]], i32 [[TMP4]], i32 4 // CHECK-NEXT: br label [[OMP_TILE0_PREHEADER:%.*]] // CHECK: omp_tile0.preheader: // CHECK-NEXT: br label [[OMP_TILE0_HEADER:%.*]] @@ -94,54 +92,57 @@ void unroll_partial_heuristic_constant_for(float *a, float *b, float *c, float * // CHECK-NEXT: [[OMP_TILE0_IV:%.*]] = phi i32 [ 0, [[OMP_TILE0_PREHEADER]] ], [ [[OMP_TILE0_NEXT:%.*]], [[OMP_TILE0_INC:%.*]] ] // CHECK-NEXT: br label [[OMP_TILE0_COND:%.*]] // CHECK: omp_tile0.cond: -// CHECK-NEXT: [[OMP_TILE0_CMP:%.*]] = icmp ult i32 [[OMP_TILE0_IV]], [[TMP14]] +// CHECK-NEXT: [[OMP_TILE0_CMP:%.*]] = icmp ult i32 [[OMP_TILE0_IV]], 4 // CHECK-NEXT: br i1 [[OMP_TILE0_CMP]], label [[OMP_TILE0_BODY:%.*]], label [[OMP_TILE0_EXIT:%.*]] // CHECK: omp_tile0.body: -// CHECK-NEXT: [[TMP15:%.*]] = mul nuw i32 4, [[TMP12]] -// CHECK-NEXT: [[TMP16:%.*]] = add nuw i32 [[TMP15]], [[OMP_TILE0_IV]] -// CHECK-NEXT: br label [[OMP_LOOP_BODY:%.*]] +// CHECK-NEXT: [[TMP13:%.*]] = mul nuw i32 4, [[TMP12]] +// CHECK-NEXT: [[TMP14:%.*]] = add nuw i32 [[TMP13]], [[OMP_TILE0_IV]] +// CHECK-NEXT: [[OMP_TILE0_INBOUNDS:%.*]] = icmp ult i32 [[TMP14]], [[DOTCOUNT]] +// CHECK-NEXT: br i1 [[OMP_TILE0_INBOUNDS]], label [[OMP_LOOP_BODY:%.*]], label [[OMP_TILE_BODY_MERGE:%.*]] // CHECK: omp_loop.body: -// CHECK-NEXT: call void @__captured_stmt.1(ptr [[I]], i32 [[TMP16]], ptr [[AGG_CAPTURED1]]) -// CHECK-NEXT: [[TMP17:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 -// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i64 [[IDXPROM]] -// CHECK-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX]], align 4 -// CHECK-NEXT: [[CONV:%.*]] = fpext float [[TMP19]] to double +// CHECK-NEXT: call void @__captured_stmt.1(ptr [[I]], i32 [[TMP14]], ptr [[AGG_CAPTURED1]]) +// CHECK-NEXT: [[TMP15:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: [[CONV:%.*]] = fpext float [[TMP17]] to double // CHECK-NEXT: [[CALL:%.*]] = call double @sind(double noundef [[CONV]]) -// CHECK-NEXT: [[TMP20:%.*]] = load ptr, ptr [[C_ADDR]], align 8 -// CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4 -// CHECK-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP21]] to i64 -// CHECK-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i64 [[IDXPROM2]] -// CHECK-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX3]], align 4 -// CHECK-NEXT: [[CONV4:%.*]] = fpext float [[TMP22]] to double +// CHECK-NEXT: [[TMP18:%.*]] = load ptr, ptr [[C_ADDR]], align 8 +// CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 +// CHECK-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM2]] +// CHECK-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX3]], align 4 +// CHECK-NEXT: [[CONV4:%.*]] = fpext float [[TMP20]] to double // CHECK-NEXT: [[MUL:%.*]] = fmul double [[CALL]], [[CONV4]] -// CHECK-NEXT: [[TMP23:%.*]] = load ptr, ptr [[D_ADDR]], align 8 -// CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr [[I]], align 4 -// CHECK-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP24]] to i64 -// CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i64 [[IDXPROM5]] -// CHECK-NEXT: [[TMP25:%.*]] = load float, ptr [[ARRAYIDX6]], align 4 -// CHECK-NEXT: [[CONV7:%.*]] = fpext float [[TMP25]] to double +// CHECK-NEXT: [[TMP21:%.*]] = load ptr, ptr [[D_ADDR]], align 8 +// CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[I]], align 4 +// CHECK-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP22]] to i64 +// CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM5]] +// CHECK-NEXT: [[TMP23:%.*]] = load float, ptr [[ARRAYIDX6]], align 4 +// CHECK-NEXT: [[CONV7:%.*]] = fpext float [[TMP23]] to double // CHECK-NEXT: [[MUL8:%.*]] = fmul double [[MUL]], [[CONV7]] -// CHECK-NEXT: [[TMP26:%.*]] = load ptr, ptr [[E_ADDR]], align 8 -// CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr [[I]], align 4 -// CHECK-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP27]] to i64 -// CHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP26]], i64 [[IDXPROM9]] -// CHECK-NEXT: [[TMP28:%.*]] = load float, ptr [[ARRAYIDX10]], align 4 -// CHECK-NEXT: [[CONV11:%.*]] = fpext float [[TMP28]] to double +// CHECK-NEXT: [[TMP24:%.*]] = load ptr, ptr [[E_ADDR]], align 8 +// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[I]], align 4 +// CHECK-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP25]] to i64 +// CHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP24]], i64 [[IDXPROM9]] +// CHECK-NEXT: [[TMP26:%.*]] = load float, ptr [[ARRAYIDX10]], align 4 +// CHECK-NEXT: [[CONV11:%.*]] = fpext float [[TMP26]] to double // CHECK-NEXT: [[MUL12:%.*]] = fmul double [[MUL8]], [[CONV11]] -// CHECK-NEXT: [[TMP29:%.*]] = load float, ptr [[OFFSET_ADDR]], align 4 -// CHECK-NEXT: [[CONV13:%.*]] = fpext float [[TMP29]] to double +// CHECK-NEXT: [[TMP27:%.*]] = load float, ptr [[OFFSET_ADDR]], align 4 +// CHECK-NEXT: [[CONV13:%.*]] = fpext float [[TMP27]] to double // CHECK-NEXT: [[ADD:%.*]] = fadd double [[MUL12]], [[CONV13]] -// CHECK-NEXT: [[TMP30:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr [[I]], align 4 -// CHECK-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP31]] to i64 -// CHECK-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds float, ptr [[TMP30]], i64 [[IDXPROM14]] -// CHECK-NEXT: [[TMP32:%.*]] = load float, ptr [[ARRAYIDX15]], align 4 -// CHECK-NEXT: [[CONV16:%.*]] = fpext float [[TMP32]] to double +// CHECK-NEXT: [[TMP28:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// CHECK-NEXT: [[TMP29:%.*]] = load i32, ptr [[I]], align 4 +// CHECK-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP29]] to i64 +// CHECK-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds float, ptr [[TMP28]], i64 [[IDXPROM14]] +// CHECK-NEXT: [[TMP30:%.*]] = load float, ptr [[ARRAYIDX15]], align 4 +// CHECK-NEXT: [[CONV16:%.*]] = fpext float [[TMP30]] to double // CHECK-NEXT: [[ADD17:%.*]] = fadd double [[CONV16]], [[ADD]] // CHECK-NEXT: [[CONV18:%.*]] = fptrunc double [[ADD17]] to float // CHECK-NEXT: store float [[CONV18]], ptr [[ARRAYIDX15]], align 4 +// CHECK-NEXT: br label [[OMP_TILE_BODY_MERGE]] +// CHECK: omp_tile.body.merge: // CHECK-NEXT: br label [[OMP_TILE0_INC]] // CHECK: omp_tile0.inc: // CHECK-NEXT: [[OMP_TILE0_NEXT]] = add nuw i32 [[OMP_TILE0_IV]], 1 diff --git a/clang/test/OpenMP/irbuilder_unroll_partial_heuristic_runtime_for.c b/clang/test/OpenMP/irbuilder_unroll_partial_heuristic_runtime_for.c index 8fee5773e53b4..6b48e3ca22888 100644 --- a/clang/test/OpenMP/irbuilder_unroll_partial_heuristic_runtime_for.c +++ b/clang/test/OpenMP/irbuilder_unroll_partial_heuristic_runtime_for.c @@ -87,8 +87,6 @@ void unroll_partial_heuristic_runtime_for(int n, float *a, float *b, float *c, f // CHECK-NEXT: br i1 [[OMP_FLOOR0_CMP]], label [[OMP_FLOOR0_BODY:%.*]], label [[OMP_FLOOR0_EXIT:%.*]] // CHECK: omp_floor0.body: // CHECK-NEXT: [[TMP13:%.*]] = add i32 [[OMP_FLOOR0_IV]], [[TMP9]] -// CHECK-NEXT: [[TMP14:%.*]] = icmp eq i32 [[TMP13]], [[TMP4]] -// CHECK-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i32 [[TMP5]], i32 4 // CHECK-NEXT: br label [[OMP_TILE0_PREHEADER:%.*]] // CHECK: omp_tile0.preheader: // CHECK-NEXT: br label [[OMP_TILE0_HEADER:%.*]] @@ -96,54 +94,57 @@ void unroll_partial_heuristic_runtime_for(int n, float *a, float *b, float *c, f // CHECK-NEXT: [[OMP_TILE0_IV:%.*]] = phi i32 [ 0, [[OMP_TILE0_PREHEADER]] ], [ [[OMP_TILE0_NEXT:%.*]], [[OMP_TILE0_INC:%.*]] ] // CHECK-NEXT: br label [[OMP_TILE0_COND:%.*]] // CHECK: omp_tile0.cond: -// CHECK-NEXT: [[OMP_TILE0_CMP:%.*]] = icmp ult i32 [[OMP_TILE0_IV]], [[TMP15]] +// CHECK-NEXT: [[OMP_TILE0_CMP:%.*]] = icmp ult i32 [[OMP_TILE0_IV]], 4 // CHECK-NEXT: br i1 [[OMP_TILE0_CMP]], label [[OMP_TILE0_BODY:%.*]], label [[OMP_TILE0_EXIT:%.*]] // CHECK: omp_tile0.body: -// CHECK-NEXT: [[TMP16:%.*]] = mul nuw i32 4, [[TMP13]] -// CHECK-NEXT: [[TMP17:%.*]] = add nuw i32 [[TMP16]], [[OMP_TILE0_IV]] -// CHECK-NEXT: br label [[OMP_LOOP_BODY:%.*]] +// CHECK-NEXT: [[TMP14:%.*]] = mul nuw i32 4, [[TMP13]] +// CHECK-NEXT: [[TMP15:%.*]] = add nuw i32 [[TMP14]], [[OMP_TILE0_IV]] +// CHECK-NEXT: [[OMP_TILE0_INBOUNDS:%.*]] = icmp ult i32 [[TMP15]], [[DOTCOUNT]] +// CHECK-NEXT: br i1 [[OMP_TILE0_INBOUNDS]], label [[OMP_LOOP_BODY:%.*]], label [[OMP_TILE_BODY_MERGE:%.*]] // CHECK: omp_loop.body: -// CHECK-NEXT: call void @__captured_stmt.1(ptr [[I]], i32 [[TMP17]], ptr [[AGG_CAPTURED1]]) -// CHECK-NEXT: [[TMP18:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 -// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM]] -// CHECK-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4 -// CHECK-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double +// CHECK-NEXT: call void @__captured_stmt.1(ptr [[I]], i32 [[TMP15]], ptr [[AGG_CAPTURED1]]) +// CHECK-NEXT: [[TMP16:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: [[CONV:%.*]] = fpext float [[TMP18]] to double // CHECK-NEXT: [[CALL:%.*]] = call double @sind(double noundef [[CONV]]) -// CHECK-NEXT: [[TMP21:%.*]] = load ptr, ptr [[C_ADDR]], align 8 -// CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[I]], align 4 -// CHECK-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP22]] to i64 -// CHECK-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM2]] -// CHECK-NEXT: [[TMP23:%.*]] = load float, ptr [[ARRAYIDX3]], align 4 -// CHECK-NEXT: [[CONV4:%.*]] = fpext float [[TMP23]] to double +// CHECK-NEXT: [[TMP19:%.*]] = load ptr, ptr [[C_ADDR]], align 8 +// CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[I]], align 4 +// CHECK-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP20]] to i64 +// CHECK-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP19]], i64 [[IDXPROM2]] +// CHECK-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX3]], align 4 +// CHECK-NEXT: [[CONV4:%.*]] = fpext float [[TMP21]] to double // CHECK-NEXT: [[MUL:%.*]] = fmul double [[CALL]], [[CONV4]] -// CHECK-NEXT: [[TMP24:%.*]] = load ptr, ptr [[D_ADDR]], align 8 -// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[I]], align 4 -// CHECK-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP25]] to i64 -// CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP24]], i64 [[IDXPROM5]] -// CHECK-NEXT: [[TMP26:%.*]] = load float, ptr [[ARRAYIDX6]], align 4 -// CHECK-NEXT: [[CONV7:%.*]] = fpext float [[TMP26]] to double +// CHECK-NEXT: [[TMP22:%.*]] = load ptr, ptr [[D_ADDR]], align 8 +// CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[I]], align 4 +// CHECK-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP23]] to i64 +// CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP22]], i64 [[IDXPROM5]] +// CHECK-NEXT: [[TMP24:%.*]] = load float, ptr [[ARRAYIDX6]], align 4 +// CHECK-NEXT: [[CONV7:%.*]] = fpext float [[TMP24]] to double // CHECK-NEXT: [[MUL8:%.*]] = fmul double [[MUL]], [[CONV7]] -// CHECK-NEXT: [[TMP27:%.*]] = load ptr, ptr [[E_ADDR]], align 8 -// CHECK-NEXT: [[TMP28:%.*]] = load i32, ptr [[I]], align 4 -// CHECK-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP28]] to i64 -// CHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP27]], i64 [[IDXPROM9]] -// CHECK-NEXT: [[TMP29:%.*]] = load float, ptr [[ARRAYIDX10]], align 4 -// CHECK-NEXT: [[CONV11:%.*]] = fpext float [[TMP29]] to double +// CHECK-NEXT: [[TMP25:%.*]] = load ptr, ptr [[E_ADDR]], align 8 +// CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr [[I]], align 4 +// CHECK-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP26]] to i64 +// CHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP25]], i64 [[IDXPROM9]] +// CHECK-NEXT: [[TMP27:%.*]] = load float, ptr [[ARRAYIDX10]], align 4 +// CHECK-NEXT: [[CONV11:%.*]] = fpext float [[TMP27]] to double // CHECK-NEXT: [[MUL12:%.*]] = fmul double [[MUL8]], [[CONV11]] -// CHECK-NEXT: [[TMP30:%.*]] = load float, ptr [[OFFSET_ADDR]], align 4 -// CHECK-NEXT: [[CONV13:%.*]] = fpext float [[TMP30]] to double +// CHECK-NEXT: [[TMP28:%.*]] = load float, ptr [[OFFSET_ADDR]], align 4 +// CHECK-NEXT: [[CONV13:%.*]] = fpext float [[TMP28]] to double // CHECK-NEXT: [[ADD:%.*]] = fadd double [[MUL12]], [[CONV13]] -// CHECK-NEXT: [[TMP31:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[I]], align 4 -// CHECK-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP32]] to i64 -// CHECK-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds float, ptr [[TMP31]], i64 [[IDXPROM14]] -// CHECK-NEXT: [[TMP33:%.*]] = load float, ptr [[ARRAYIDX15]], align 4 -// CHECK-NEXT: [[CONV16:%.*]] = fpext float [[TMP33]] to double +// CHECK-NEXT: [[TMP29:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[I]], align 4 +// CHECK-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP30]] to i64 +// CHECK-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds float, ptr [[TMP29]], i64 [[IDXPROM14]] +// CHECK-NEXT: [[TMP31:%.*]] = load float, ptr [[ARRAYIDX15]], align 4 +// CHECK-NEXT: [[CONV16:%.*]] = fpext float [[TMP31]] to double // CHECK-NEXT: [[ADD17:%.*]] = fadd double [[CONV16]], [[ADD]] // CHECK-NEXT: [[CONV18:%.*]] = fptrunc double [[ADD17]] to float // CHECK-NEXT: store float [[CONV18]], ptr [[ARRAYIDX15]], align 4 +// CHECK-NEXT: br label [[OMP_TILE_BODY_MERGE]] +// CHECK: omp_tile.body.merge: // CHECK-NEXT: br label [[OMP_TILE0_INC]] // CHECK: omp_tile0.inc: // CHECK-NEXT: [[OMP_TILE0_NEXT]] = add nuw i32 [[OMP_TILE0_IV]], 1 diff --git a/clang/test/OpenMP/irbuilder_unroll_unroll_partial_factor.c b/clang/test/OpenMP/irbuilder_unroll_unroll_partial_factor.c index c4ebcddb097bc..65bd495ca0426 100644 --- a/clang/test/OpenMP/irbuilder_unroll_unroll_partial_factor.c +++ b/clang/test/OpenMP/irbuilder_unroll_unroll_partial_factor.c @@ -75,8 +75,6 @@ void unroll_partial_factor_for(float *a, float *b, float *c, float *d) { // CHECK-NEXT: br i1 [[OMP_FLOOR0_CMP]], label [[OMP_FLOOR0_BODY:%.*]], label [[OMP_FLOOR0_EXIT:%.*]] // CHECK: omp_floor0.body: // CHECK-NEXT: [[TMP12:%.*]] = add i32 [[OMP_FLOOR0_IV]], [[TMP8]] -// CHECK-NEXT: [[TMP13:%.*]] = icmp eq i32 [[TMP12]], [[TMP3]] -// CHECK-NEXT: [[TMP14:%.*]] = select i1 [[TMP13]], i32 [[TMP4]], i32 2 // CHECK-NEXT: br label [[OMP_TILE0_PREHEADER:%.*]] // CHECK: omp_tile0.preheader: // CHECK-NEXT: br label [[OMP_TILE0_HEADER:%.*]] @@ -84,36 +82,39 @@ void unroll_partial_factor_for(float *a, float *b, float *c, float *d) { // CHECK-NEXT: [[OMP_TILE0_IV:%.*]] = phi i32 [ 0, [[OMP_TILE0_PREHEADER]] ], [ [[OMP_TILE0_NEXT:%.*]], [[OMP_TILE0_INC:%.*]] ] // CHECK-NEXT: br label [[OMP_TILE0_COND:%.*]] // CHECK: omp_tile0.cond: -// CHECK-NEXT: [[OMP_TILE0_CMP:%.*]] = icmp ult i32 [[OMP_TILE0_IV]], [[TMP14]] +// CHECK-NEXT: [[OMP_TILE0_CMP:%.*]] = icmp ult i32 [[OMP_TILE0_IV]], 2 // CHECK-NEXT: br i1 [[OMP_TILE0_CMP]], label [[OMP_TILE0_BODY:%.*]], label [[OMP_TILE0_EXIT:%.*]] // CHECK: omp_tile0.body: -// CHECK-NEXT: [[TMP15:%.*]] = mul nuw i32 2, [[TMP12]] -// CHECK-NEXT: [[TMP16:%.*]] = add nuw i32 [[TMP15]], [[OMP_TILE0_IV]] -// CHECK-NEXT: br label [[OMP_LOOP_BODY:%.*]] +// CHECK-NEXT: [[TMP13:%.*]] = mul nuw i32 2, [[TMP12]] +// CHECK-NEXT: [[TMP14:%.*]] = add nuw i32 [[TMP13]], [[OMP_TILE0_IV]] +// CHECK-NEXT: [[OMP_TILE0_INBOUNDS:%.*]] = icmp ult i32 [[TMP14]], [[DOTCOUNT]] +// CHECK-NEXT: br i1 [[OMP_TILE0_INBOUNDS]], label [[OMP_LOOP_BODY:%.*]], label [[OMP_TILE_BODY_MERGE:%.*]] // CHECK: omp_loop.body: -// CHECK-NEXT: call void @__captured_stmt.1(ptr [[I]], i32 [[TMP16]], ptr [[AGG_CAPTURED1]]) -// CHECK-NEXT: [[TMP17:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 -// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i64 [[IDXPROM]] -// CHECK-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX]], align 4 -// CHECK-NEXT: [[TMP20:%.*]] = load ptr, ptr [[C_ADDR]], align 8 -// CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4 -// CHECK-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP21]] to i64 -// CHECK-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i64 [[IDXPROM2]] -// CHECK-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX3]], align 4 -// CHECK-NEXT: [[MUL:%.*]] = fmul float [[TMP19]], [[TMP22]] -// CHECK-NEXT: [[TMP23:%.*]] = load ptr, ptr [[D_ADDR]], align 8 -// CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr [[I]], align 4 -// CHECK-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP24]] to i64 -// CHECK-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i64 [[IDXPROM4]] -// CHECK-NEXT: [[TMP25:%.*]] = load float, ptr [[ARRAYIDX5]], align 4 -// CHECK-NEXT: [[MUL6:%.*]] = fmul float [[MUL]], [[TMP25]] -// CHECK-NEXT: [[TMP26:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr [[I]], align 4 -// CHECK-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP27]] to i64 -// CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, ptr [[TMP26]], i64 [[IDXPROM7]] +// CHECK-NEXT: call void @__captured_stmt.1(ptr [[I]], i32 [[TMP14]], ptr [[AGG_CAPTURED1]]) +// CHECK-NEXT: [[TMP15:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: [[TMP18:%.*]] = load ptr, ptr [[C_ADDR]], align 8 +// CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 +// CHECK-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM2]] +// CHECK-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX3]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = fmul float [[TMP17]], [[TMP20]] +// CHECK-NEXT: [[TMP21:%.*]] = load ptr, ptr [[D_ADDR]], align 8 +// CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[I]], align 4 +// CHECK-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP22]] to i64 +// CHECK-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM4]] +// CHECK-NEXT: [[TMP23:%.*]] = load float, ptr [[ARRAYIDX5]], align 4 +// CHECK-NEXT: [[MUL6:%.*]] = fmul float [[MUL]], [[TMP23]] +// CHECK-NEXT: [[TMP24:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[I]], align 4 +// CHECK-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP25]] to i64 +// CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, ptr [[TMP24]], i64 [[IDXPROM7]] // CHECK-NEXT: store float [[MUL6]], ptr [[ARRAYIDX8]], align 4 +// CHECK-NEXT: br label [[OMP_TILE_BODY_MERGE]] +// CHECK: omp_tile.body.merge: // CHECK-NEXT: br label [[OMP_TILE0_INC]] // CHECK: omp_tile0.inc: // CHECK-NEXT: [[OMP_TILE0_NEXT]] = add nuw i32 [[OMP_TILE0_IV]], 1 diff --git a/clang/test/OpenMP/irbuilder_unroll_unroll_partial_heuristic.c b/clang/test/OpenMP/irbuilder_unroll_unroll_partial_heuristic.c index 24d42d265d6a6..c2b7d46588f66 100644 --- a/clang/test/OpenMP/irbuilder_unroll_unroll_partial_heuristic.c +++ b/clang/test/OpenMP/irbuilder_unroll_unroll_partial_heuristic.c @@ -59,8 +59,6 @@ void unroll_unroll_partial_heuristic(float *a, float *b, float *c, float *d) { // CHECK-NEXT: [[OMP_FLOOR0_CMP:%.*]] = icmp ult i32 [[OMP_FLOOR0_IV]], [[OMP_FLOOR0_TRIPCOUNT]] // CHECK-NEXT: br i1 [[OMP_FLOOR0_CMP]], label [[OMP_FLOOR0_BODY:%.*]], label [[OMP_FLOOR0_EXIT:%.*]] // CHECK: omp_floor0.body: -// CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[OMP_FLOOR0_IV]], [[TMP3]] -// CHECK-NEXT: [[TMP8:%.*]] = select i1 [[TMP7]], i32 [[TMP4]], i32 8 // CHECK-NEXT: br label [[OMP_TILE0_PREHEADER:%.*]] // CHECK: omp_tile0.preheader: // CHECK-NEXT: br label [[OMP_TILE0_HEADER:%.*]] @@ -68,47 +66,50 @@ void unroll_unroll_partial_heuristic(float *a, float *b, float *c, float *d) { // CHECK-NEXT: [[OMP_TILE0_IV:%.*]] = phi i32 [ 0, [[OMP_TILE0_PREHEADER]] ], [ [[OMP_TILE0_NEXT:%.*]], [[OMP_TILE0_INC:%.*]] ] // CHECK-NEXT: br label [[OMP_TILE0_COND:%.*]] // CHECK: omp_tile0.cond: -// CHECK-NEXT: [[OMP_TILE0_CMP:%.*]] = icmp ult i32 [[OMP_TILE0_IV]], [[TMP8]] +// CHECK-NEXT: [[OMP_TILE0_CMP:%.*]] = icmp ult i32 [[OMP_TILE0_IV]], 8 // CHECK-NEXT: br i1 [[OMP_TILE0_CMP]], label [[OMP_TILE0_BODY:%.*]], label [[OMP_TILE0_EXIT:%.*]] // CHECK: omp_tile0.body: -// CHECK-NEXT: [[TMP9:%.*]] = mul nuw i32 8, [[OMP_FLOOR0_IV]] -// CHECK-NEXT: [[TMP10:%.*]] = add nuw i32 [[TMP9]], [[OMP_TILE0_IV]] -// CHECK-NEXT: br label [[OMP_LOOP_BODY:%.*]] +// CHECK-NEXT: [[TMP7:%.*]] = mul nuw i32 8, [[OMP_FLOOR0_IV]] +// CHECK-NEXT: [[TMP8:%.*]] = add nuw i32 [[TMP7]], [[OMP_TILE0_IV]] +// CHECK-NEXT: [[OMP_TILE0_INBOUNDS:%.*]] = icmp ult i32 [[TMP8]], [[DOTCOUNT]] +// CHECK-NEXT: br i1 [[OMP_TILE0_INBOUNDS]], label [[OMP_LOOP_BODY:%.*]], label [[OMP_TILE_BODY_MERGE:%.*]] // CHECK: omp_loop.body: -// CHECK-NEXT: call void @__captured_stmt.1(ptr [[I]], i32 [[TMP10]], ptr [[AGG_CAPTURED1]]) -// CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4 -// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP11]], i64 [[IDXPROM]] -// CHECK-NEXT: [[TMP13:%.*]] = load float, ptr [[ARRAYIDX]], align 4 -// CHECK-NEXT: [[TMP14:%.*]] = load ptr, ptr [[C_ADDR]], align 8 -// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 -// CHECK-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[IDXPROM2]] -// CHECK-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX3]], align 4 -// CHECK-NEXT: [[MUL:%.*]] = fmul float [[TMP13]], [[TMP16]] -// CHECK-NEXT: [[TMP17:%.*]] = load ptr, ptr [[D_ADDR]], align 8 -// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 -// CHECK-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i64 [[IDXPROM4]] -// CHECK-NEXT: [[TMP19:%.*]] = load float, ptr [[ARRAYIDX5]], align 4 -// CHECK-NEXT: [[MUL6:%.*]] = fmul float [[MUL]], [[TMP19]] -// CHECK-NEXT: [[TMP20:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4 -// CHECK-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP21]] to i64 -// CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i64 [[IDXPROM7]] +// CHECK-NEXT: call void @__captured_stmt.1(ptr [[I]], i32 [[TMP8]], ptr [[AGG_CAPTURED1]]) +// CHECK-NEXT: [[TMP9:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 +// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP9]], i64 [[IDXPROM]] +// CHECK-NEXT: [[TMP11:%.*]] = load float, ptr [[ARRAYIDX]], align 4 +// CHECK-NEXT: [[TMP12:%.*]] = load ptr, ptr [[C_ADDR]], align 8 +// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 +// CHECK-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM2]] +// CHECK-NEXT: [[TMP14:%.*]] = load float, ptr [[ARRAYIDX3]], align 4 +// CHECK-NEXT: [[MUL:%.*]] = fmul float [[TMP11]], [[TMP14]] +// CHECK-NEXT: [[TMP15:%.*]] = load ptr, ptr [[D_ADDR]], align 8 +// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 +// CHECK-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP16]] to i64 +// CHECK-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM4]] +// CHECK-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX5]], align 4 +// CHECK-NEXT: [[MUL6:%.*]] = fmul float [[MUL]], [[TMP17]] +// CHECK-NEXT: [[TMP18:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 +// CHECK-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM7]] // CHECK-NEXT: store float [[MUL6]], ptr [[ARRAYIDX8]], align 4 +// CHECK-NEXT: br label [[OMP_TILE_BODY_MERGE]] +// CHECK: omp_tile.body.merge: // CHECK-NEXT: br label [[OMP_TILE0_INC]] // CHECK: omp_tile0.inc: // CHECK-NEXT: [[OMP_TILE0_NEXT]] = add nuw i32 [[OMP_TILE0_IV]], 1 -// CHECK-NEXT: br label [[OMP_TILE0_HEADER]], !llvm.loop [[LOOP3:![0-9]+]] +// CHECK-NEXT: br label [[OMP_TILE0_HEADER]], !llvm.loop [[LOOP2:![0-9]+]] // CHECK: omp_tile0.exit: // CHECK-NEXT: br label [[OMP_TILE0_AFTER:%.*]] // CHECK: omp_tile0.after: // CHECK-NEXT: br label [[OMP_FLOOR0_INC]] // CHECK: omp_floor0.inc: // CHECK-NEXT: [[OMP_FLOOR0_NEXT]] = add nuw i32 [[OMP_FLOOR0_IV]], 1 -// CHECK-NEXT: br label [[OMP_FLOOR0_HEADER]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK-NEXT: br label [[OMP_FLOOR0_HEADER]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK: omp_floor0.exit: // CHECK-NEXT: br label [[OMP_FLOOR0_AFTER:%.*]] // CHECK: omp_floor0.after: @@ -129,7 +130,7 @@ void unroll_unroll_partial_heuristic(float *a, float *b, float *c, float *d) { // CHECK-NEXT: store ptr [[__CONTEXT]], ptr [[__CONTEXT_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__CONTEXT_ADDR]], align 8 // CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP0]], i32 0, i32 0 -// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]] // CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 // CHECK-NEXT: store i32 [[TMP3]], ptr [[DOTSTART]], align 4 // CHECK-NEXT: store i32 2, ptr [[DOTSTOP]], align 4 @@ -152,7 +153,7 @@ void unroll_unroll_partial_heuristic(float *a, float *b, float *c, float *d) { // CHECK-NEXT: br label [[COND_END]] // CHECK: cond.end: // CHECK-NEXT: [[COND:%.*]] = phi i32 [ [[DIV]], [[COND_TRUE]] ], [ 0, [[COND_FALSE]] ] -// CHECK-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DISTANCE_ADDR]], align 8 +// CHECK-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DISTANCE_ADDR]], align 8, !nonnull [[META6]], !align [[META7]] // CHECK-NEXT: store i32 [[COND]], ptr [[TMP10]], align 4 // CHECK-NEXT: ret void // @@ -172,7 +173,7 @@ void unroll_unroll_partial_heuristic(float *a, float *b, float *c, float *d) { // CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[LOGICAL_ADDR]], align 4 // CHECK-NEXT: [[MUL:%.*]] = mul i32 1, [[TMP3]] // CHECK-NEXT: [[ADD:%.*]] = add i32 [[TMP2]], [[MUL]] -// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[LOOPVAR_ADDR]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[LOOPVAR_ADDR]], align 8, !nonnull [[META6]], !align [[META7]] // CHECK-NEXT: store i32 [[ADD]], ptr [[TMP4]], align 4 // CHECK-NEXT: ret void // diff --git a/clang/test/OpenMP/tile_codegen.cpp b/clang/test/OpenMP/tile_codegen.cpp index 85b004dc73f4f..65fd3a327ad64 100644 --- a/clang/test/OpenMP/tile_codegen.cpp +++ b/clang/test/OpenMP/tile_codegen.cpp @@ -56,7 +56,7 @@ extern "C" void foo4() { extern "C" void foo5() { -#pragma omp for collapse(3) +#pragma omp for collapse(2) #pragma omp tile sizes(5) for (int i = 7; i < 17; i += 3) for (int j = 7; j < 17; j += 3) @@ -174,9 +174,9 @@ extern "C" void foo10(data_t data) { // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 3 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 7, [[MUL]] -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[I2]], align 8 +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[I2]], align 8, !nonnull [[META2:![0-9]+]], !align [[META3:![0-9]+]] // CHECK1-NEXT: store i32 [[ADD9]], ptr [[TMP6]], align 4 -// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[I2]], align 8 +// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[I2]], align 8, !nonnull [[META2]], !align [[META3]] // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 // CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP8]]) // CHECK1-NEXT: br label [[FOR_INC:%.*]] @@ -184,14 +184,14 @@ extern "C" void foo10(data_t data) { // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK1-NEXT: store i32 [[INC]], ptr [[DOTTILE_0_IV_I]], align 4 -// CHECK1-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP3:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK1: for.end: // CHECK1-NEXT: br label [[FOR_INC10:%.*]] // CHECK1: for.inc10: // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP10]], 5 // CHECK1-NEXT: store i32 [[ADD11]], ptr [[DOTFLOOR_0_IV_I]], align 4 -// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK1: for.end12: // CHECK1-NEXT: ret void // @@ -276,14 +276,14 @@ extern "C" void foo10(data_t data) { // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 // CHECK1-NEXT: [[INC:%.*]] = add i32 [[TMP20]], 1 // CHECK1-NEXT: store i32 [[INC]], ptr [[DOTTILE_0_IV_I]], align 4 -// CHECK1-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK1: for.end: // CHECK1-NEXT: br label [[FOR_INC15:%.*]] // CHECK1: for.inc15: // CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 // CHECK1-NEXT: [[ADD16:%.*]] = add i32 [[TMP21]], 5 // CHECK1-NEXT: store i32 [[ADD16]], ptr [[DOTFLOOR_0_IV_I]], align 4 -// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK1: for.end17: // CHECK1-NEXT: ret void // @@ -375,28 +375,28 @@ extern "C" void foo10(data_t data) { // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTTILE_1_IV_J]], align 4 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1 // CHECK1-NEXT: store i32 [[INC]], ptr [[DOTTILE_1_IV_J]], align 4 -// CHECK1-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK1: for.end: // CHECK1-NEXT: br label [[FOR_INC22:%.*]] // CHECK1: for.inc22: // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 // CHECK1-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP15]], 1 // CHECK1-NEXT: store i32 [[INC23]], ptr [[DOTTILE_0_IV_I]], align 4 -// CHECK1-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK1: for.end24: // CHECK1-NEXT: br label [[FOR_INC25:%.*]] // CHECK1: for.inc25: // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4 // CHECK1-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP16]], 5 // CHECK1-NEXT: store i32 [[ADD26]], ptr [[DOTFLOOR_1_IV_J]], align 4 -// CHECK1-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK1: for.end27: // CHECK1-NEXT: br label [[FOR_INC28:%.*]] // CHECK1: for.inc28: // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 // CHECK1-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP17]], 5 // CHECK1-NEXT: store i32 [[ADD29]], ptr [[DOTFLOOR_0_IV_I]], align 4 -// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK1: for.end30: // CHECK1-NEXT: ret void // @@ -407,15 +407,17 @@ extern "C" void foo10(data_t data) { // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTTILE_1_IV_J:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTFLOOR_1_IV_J:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTTILE_1_IV_J:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTTILE_CNT_0_IV_I:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTTILE_CNT_1_IV_J:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) // CHECK1-NEXT: store i32 7, ptr [[I]], align 4 // CHECK1-NEXT: store i32 7, ptr [[J]], align 4 @@ -453,87 +455,79 @@ extern "C" void foo10(data_t data) { // CHECK1: for.cond: // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4 // CHECK1-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP7]], 4 -// CHECK1-NEXT: br i1 [[CMP2]], label [[FOR_BODY:%.*]], label [[FOR_END32:%.*]] +// CHECK1-NEXT: br i1 [[CMP2]], label [[FOR_BODY:%.*]], label [[FOR_END22:%.*]] // CHECK1: for.body: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 -// CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTTILE_0_IV_I]], align 4 +// CHECK1-NEXT: store i32 0, ptr [[DOTTILE_CNT_0_IV_I]], align 4 // CHECK1-NEXT: br label [[FOR_COND3:%.*]] // CHECK1: for.cond3: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 -// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 5 -// CHECK1-NEXT: [[CMP5:%.*]] = icmp slt i32 4, [[ADD4]] -// CHECK1-NEXT: br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]] -// CHECK1: cond.true6: -// CHECK1-NEXT: br label [[COND_END9:%.*]] -// CHECK1: cond.false7: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 -// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP11]], 5 -// CHECK1-NEXT: br label [[COND_END9]] -// CHECK1: cond.end9: -// CHECK1-NEXT: [[COND10:%.*]] = phi i32 [ 4, [[COND_TRUE6]] ], [ [[ADD8]], [[COND_FALSE7]] ] -// CHECK1-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP9]], [[COND10]] -// CHECK1-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END29:%.*]] -// CHECK1: for.body12: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 -// CHECK1-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP12]], 3 -// CHECK1-NEXT: [[ADD14:%.*]] = add nsw i32 7, [[MUL13]] -// CHECK1-NEXT: store i32 [[ADD14]], ptr [[I]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTTILE_CNT_0_IV_I]], align 4 +// CHECK1-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP8]], 5 +// CHECK1-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END19:%.*]] +// CHECK1: for.body5: +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTTILE_CNT_0_IV_I]], align 4 +// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] +// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTTILE_0_IV_I]], align 4 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 +// CHECK1-NEXT: [[MUL7:%.*]] = mul nsw i32 [[TMP11]], 3 +// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 7, [[MUL7]] +// CHECK1-NEXT: store i32 [[ADD8]], ptr [[I]], align 4 +// CHECK1-NEXT: store i32 0, ptr [[DOTTILE_CNT_1_IV_J]], align 4 +// CHECK1-NEXT: br label [[FOR_COND9:%.*]] +// CHECK1: for.cond9: +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTTILE_CNT_1_IV_J]], align 4 +// CHECK1-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP12]], 5 +// CHECK1-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END:%.*]] +// CHECK1: for.body11: // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4 -// CHECK1-NEXT: store i32 [[TMP13]], ptr [[DOTTILE_1_IV_J]], align 4 -// CHECK1-NEXT: br label [[FOR_COND15:%.*]] -// CHECK1: for.cond15: -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTTILE_1_IV_J]], align 4 -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4 -// CHECK1-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP15]], 5 -// CHECK1-NEXT: [[CMP17:%.*]] = icmp slt i32 4, [[ADD16]] -// CHECK1-NEXT: br i1 [[CMP17]], label [[COND_TRUE18:%.*]], label [[COND_FALSE19:%.*]] -// CHECK1: cond.true18: -// CHECK1-NEXT: br label [[COND_END21:%.*]] -// CHECK1: cond.false19: -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4 -// CHECK1-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP16]], 5 -// CHECK1-NEXT: br label [[COND_END21]] -// CHECK1: cond.end21: -// CHECK1-NEXT: [[COND22:%.*]] = phi i32 [ 4, [[COND_TRUE18]] ], [ [[ADD20]], [[COND_FALSE19]] ] -// CHECK1-NEXT: [[CMP23:%.*]] = icmp slt i32 [[TMP14]], [[COND22]] -// CHECK1-NEXT: br i1 [[CMP23]], label [[FOR_BODY24:%.*]], label [[FOR_END:%.*]] -// CHECK1: for.body24: +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTTILE_CNT_1_IV_J]], align 4 +// CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK1-NEXT: store i32 [[ADD12]], ptr [[DOTTILE_1_IV_J]], align 4 +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTTILE_1_IV_J]], align 4 +// CHECK1-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 3 +// CHECK1-NEXT: [[ADD14:%.*]] = add nsw i32 7, [[MUL13]] +// CHECK1-NEXT: store i32 [[ADD14]], ptr [[J]], align 4 +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 +// CHECK1-NEXT: [[CMP15:%.*]] = icmp slt i32 [[TMP16]], 4 +// CHECK1-NEXT: br i1 [[CMP15]], label [[LAND_LHS_TRUE:%.*]], label [[IF_END:%.*]] +// CHECK1: land.lhs.true: // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTTILE_1_IV_J]], align 4 -// CHECK1-NEXT: [[MUL25:%.*]] = mul nsw i32 [[TMP17]], 3 -// CHECK1-NEXT: [[ADD26:%.*]] = add nsw i32 7, [[MUL25]] -// CHECK1-NEXT: store i32 [[ADD26]], ptr [[J]], align 4 +// CHECK1-NEXT: [[CMP16:%.*]] = icmp slt i32 [[TMP17]], 4 +// CHECK1-NEXT: br i1 [[CMP16]], label [[IF_THEN:%.*]], label [[IF_END]] +// CHECK1: if.then: // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[J]], align 4 // CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP18]], i32 noundef [[TMP19]]) +// CHECK1-NEXT: br label [[IF_END]] +// CHECK1: if.end: // CHECK1-NEXT: br label [[FOR_INC:%.*]] // CHECK1: for.inc: -// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTTILE_1_IV_J]], align 4 +// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTTILE_CNT_1_IV_J]], align 4 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTTILE_1_IV_J]], align 4 -// CHECK1-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTTILE_CNT_1_IV_J]], align 4 +// CHECK1-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK1: for.end: -// CHECK1-NEXT: br label [[FOR_INC27:%.*]] -// CHECK1: for.inc27: -// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 -// CHECK1-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK1-NEXT: store i32 [[INC28]], ptr [[DOTTILE_0_IV_I]], align 4 -// CHECK1-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP13:![0-9]+]] -// CHECK1: for.end29: -// CHECK1-NEXT: br label [[FOR_INC30:%.*]] -// CHECK1: for.inc30: +// CHECK1-NEXT: br label [[FOR_INC17:%.*]] +// CHECK1: for.inc17: +// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTTILE_CNT_0_IV_I]], align 4 +// CHECK1-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP21]], 1 +// CHECK1-NEXT: store i32 [[INC18]], ptr [[DOTTILE_CNT_0_IV_I]], align 4 +// CHECK1-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK1: for.end19: +// CHECK1-NEXT: br label [[FOR_INC20:%.*]] +// CHECK1: for.inc20: // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4 -// CHECK1-NEXT: [[ADD31:%.*]] = add nsw i32 [[TMP22]], 5 -// CHECK1-NEXT: store i32 [[ADD31]], ptr [[DOTFLOOR_1_IV_J]], align 4 -// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] -// CHECK1: for.end32: +// CHECK1-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP22]], 5 +// CHECK1-NEXT: store i32 [[ADD21]], ptr [[DOTFLOOR_1_IV_J]], align 4 +// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK1: for.end22: // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[ADD33:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK1-NEXT: store i32 [[ADD33]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK1-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -550,7 +544,9 @@ extern "C" void foo10(data_t data) { // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTTILE_1_IV_J:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 @@ -558,8 +554,8 @@ extern "C" void foo10(data_t data) { // CHECK1-NEXT: [[K:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTFLOOR_1_IV_J:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTTILE_1_IV_J:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTTILE_CNT_0_IV_I:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTTILE_CNT_1_IV_J:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) // CHECK1-NEXT: store i32 7, ptr [[I]], align 4 // CHECK1-NEXT: store i32 7, ptr [[J]], align 4 @@ -606,87 +602,79 @@ extern "C" void foo10(data_t data) { // CHECK1: for.cond: // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4 // CHECK1-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP9]], 4 -// CHECK1-NEXT: br i1 [[CMP7]], label [[FOR_BODY:%.*]], label [[FOR_END37:%.*]] +// CHECK1-NEXT: br i1 [[CMP7]], label [[FOR_BODY:%.*]], label [[FOR_END27:%.*]] // CHECK1: for.body: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 -// CHECK1-NEXT: store i32 [[TMP10]], ptr [[DOTTILE_0_IV_I]], align 4 +// CHECK1-NEXT: store i32 0, ptr [[DOTTILE_CNT_0_IV_I]], align 4 // CHECK1-NEXT: br label [[FOR_COND8:%.*]] // CHECK1: for.cond8: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 -// CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP12]], 5 -// CHECK1-NEXT: [[CMP10:%.*]] = icmp slt i32 4, [[ADD9]] -// CHECK1-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] -// CHECK1: cond.true11: -// CHECK1-NEXT: br label [[COND_END14:%.*]] -// CHECK1: cond.false12: -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 -// CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP13]], 5 -// CHECK1-NEXT: br label [[COND_END14]] -// CHECK1: cond.end14: -// CHECK1-NEXT: [[COND15:%.*]] = phi i32 [ 4, [[COND_TRUE11]] ], [ [[ADD13]], [[COND_FALSE12]] ] -// CHECK1-NEXT: [[CMP16:%.*]] = icmp slt i32 [[TMP11]], [[COND15]] -// CHECK1-NEXT: br i1 [[CMP16]], label [[FOR_BODY17:%.*]], label [[FOR_END34:%.*]] -// CHECK1: for.body17: -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 -// CHECK1-NEXT: [[MUL18:%.*]] = mul nsw i32 [[TMP14]], 3 -// CHECK1-NEXT: [[ADD19:%.*]] = add nsw i32 7, [[MUL18]] -// CHECK1-NEXT: store i32 [[ADD19]], ptr [[I]], align 4 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTTILE_CNT_0_IV_I]], align 4 +// CHECK1-NEXT: [[CMP9:%.*]] = icmp slt i32 [[TMP10]], 5 +// CHECK1-NEXT: br i1 [[CMP9]], label [[FOR_BODY10:%.*]], label [[FOR_END24:%.*]] +// CHECK1: for.body10: +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTTILE_CNT_0_IV_I]], align 4 +// CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK1-NEXT: store i32 [[ADD11]], ptr [[DOTTILE_0_IV_I]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 +// CHECK1-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP13]], 3 +// CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 7, [[MUL12]] +// CHECK1-NEXT: store i32 [[ADD13]], ptr [[I]], align 4 +// CHECK1-NEXT: store i32 0, ptr [[DOTTILE_CNT_1_IV_J]], align 4 +// CHECK1-NEXT: br label [[FOR_COND14:%.*]] +// CHECK1: for.cond14: +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTTILE_CNT_1_IV_J]], align 4 +// CHECK1-NEXT: [[CMP15:%.*]] = icmp slt i32 [[TMP14]], 5 +// CHECK1-NEXT: br i1 [[CMP15]], label [[FOR_BODY16:%.*]], label [[FOR_END:%.*]] +// CHECK1: for.body16: // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4 -// CHECK1-NEXT: store i32 [[TMP15]], ptr [[DOTTILE_1_IV_J]], align 4 -// CHECK1-NEXT: br label [[FOR_COND20:%.*]] -// CHECK1: for.cond20: -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTTILE_1_IV_J]], align 4 -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4 -// CHECK1-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP17]], 5 -// CHECK1-NEXT: [[CMP22:%.*]] = icmp slt i32 4, [[ADD21]] -// CHECK1-NEXT: br i1 [[CMP22]], label [[COND_TRUE23:%.*]], label [[COND_FALSE24:%.*]] -// CHECK1: cond.true23: -// CHECK1-NEXT: br label [[COND_END26:%.*]] -// CHECK1: cond.false24: -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4 -// CHECK1-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP18]], 5 -// CHECK1-NEXT: br label [[COND_END26]] -// CHECK1: cond.end26: -// CHECK1-NEXT: [[COND27:%.*]] = phi i32 [ 4, [[COND_TRUE23]] ], [ [[ADD25]], [[COND_FALSE24]] ] -// CHECK1-NEXT: [[CMP28:%.*]] = icmp slt i32 [[TMP16]], [[COND27]] -// CHECK1-NEXT: br i1 [[CMP28]], label [[FOR_BODY29:%.*]], label [[FOR_END:%.*]] -// CHECK1: for.body29: +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTTILE_CNT_1_IV_J]], align 4 +// CHECK1-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] +// CHECK1-NEXT: store i32 [[ADD17]], ptr [[DOTTILE_1_IV_J]], align 4 +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTTILE_1_IV_J]], align 4 +// CHECK1-NEXT: [[MUL18:%.*]] = mul nsw i32 [[TMP17]], 3 +// CHECK1-NEXT: [[ADD19:%.*]] = add nsw i32 7, [[MUL18]] +// CHECK1-NEXT: store i32 [[ADD19]], ptr [[J]], align 4 +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 +// CHECK1-NEXT: [[CMP20:%.*]] = icmp slt i32 [[TMP18]], 4 +// CHECK1-NEXT: br i1 [[CMP20]], label [[LAND_LHS_TRUE:%.*]], label [[IF_END:%.*]] +// CHECK1: land.lhs.true: // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTTILE_1_IV_J]], align 4 -// CHECK1-NEXT: [[MUL30:%.*]] = mul nsw i32 [[TMP19]], 3 -// CHECK1-NEXT: [[ADD31:%.*]] = add nsw i32 7, [[MUL30]] -// CHECK1-NEXT: store i32 [[ADD31]], ptr [[J]], align 4 +// CHECK1-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP19]], 4 +// CHECK1-NEXT: br i1 [[CMP21]], label [[IF_THEN:%.*]], label [[IF_END]] +// CHECK1: if.then: // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[J]], align 4 // CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP20]], i32 noundef [[TMP21]]) +// CHECK1-NEXT: br label [[IF_END]] +// CHECK1: if.end: // CHECK1-NEXT: br label [[FOR_INC:%.*]] // CHECK1: for.inc: -// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTTILE_1_IV_J]], align 4 +// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTTILE_CNT_1_IV_J]], align 4 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTTILE_1_IV_J]], align 4 -// CHECK1-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP15:![0-9]+]] +// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTTILE_CNT_1_IV_J]], align 4 +// CHECK1-NEXT: br label [[FOR_COND14]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK1: for.end: -// CHECK1-NEXT: br label [[FOR_INC32:%.*]] -// CHECK1: for.inc32: -// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 -// CHECK1-NEXT: [[INC33:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK1-NEXT: store i32 [[INC33]], ptr [[DOTTILE_0_IV_I]], align 4 -// CHECK1-NEXT: br label [[FOR_COND8]], !llvm.loop [[LOOP16:![0-9]+]] -// CHECK1: for.end34: -// CHECK1-NEXT: br label [[FOR_INC35:%.*]] -// CHECK1: for.inc35: +// CHECK1-NEXT: br label [[FOR_INC22:%.*]] +// CHECK1: for.inc22: +// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTTILE_CNT_0_IV_I]], align 4 +// CHECK1-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK1-NEXT: store i32 [[INC23]], ptr [[DOTTILE_CNT_0_IV_I]], align 4 +// CHECK1-NEXT: br label [[FOR_COND8]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK1: for.end24: +// CHECK1-NEXT: br label [[FOR_INC25:%.*]] +// CHECK1: for.inc25: // CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4 -// CHECK1-NEXT: [[ADD36:%.*]] = add nsw i32 [[TMP24]], 5 -// CHECK1-NEXT: store i32 [[ADD36]], ptr [[DOTFLOOR_1_IV_J]], align 4 -// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] -// CHECK1: for.end37: +// CHECK1-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP24]], 5 +// CHECK1-NEXT: store i32 [[ADD26]], ptr [[DOTFLOOR_1_IV_J]], align 4 +// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK1: for.end27: // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: // CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[ADD38:%.*]] = add nsw i32 [[TMP25]], 1 -// CHECK1-NEXT: store i32 [[ADD38]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP25]], 1 +// CHECK1-NEXT: store i32 [[ADD28]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -699,208 +687,101 @@ extern "C" void foo10(data_t data) { // CHECK1-LABEL: define dso_local void @foo5( // CHECK1-SAME: ) #[[ATTR0]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTFLOOR_0_IV_I11:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTTILE_0_IV_I12:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[J13:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTTILE_CNT_0_IV_I:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) // CHECK1-NEXT: store i32 7, ptr [[I]], align 4 -// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP]], align 4 -// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP]], align 4 -// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 5 -// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 4, [[ADD]] +// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 +// CHECK1-NEXT: store i32 4, ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 +// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 4 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK1: cond.true: // CHECK1-NEXT: br label [[COND_END:%.*]] // CHECK1: cond.false: -// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP]], align 4 -// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 5 +// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: br label [[COND_END]] // CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[ADD4]], [[COND_FALSE]] ] -// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP4]], [[TMP5]] -// CHECK1-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 -// CHECK1-NEXT: [[ADD7:%.*]] = add i32 [[SUB6]], 1 -// CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD7]], 1 -// CHECK1-NEXT: [[CONV:%.*]] = zext i32 [[DIV]] to i64 -// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 1, [[CONV]] -// CHECK1-NEXT: [[MUL8:%.*]] = mul nsw i64 [[MUL]], 4 -// CHECK1-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL8]], 1 -// CHECK1-NEXT: store i64 [[SUB9]], ptr [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK1-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_I]], align 4 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTTILE_0_IV_I]], align 4 -// CHECK1-NEXT: store i32 7, ptr [[J]], align 4 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK1-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK1-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK1: omp.precond.then: -// CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 -// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK1-NEXT: store i64 [[TMP9]], ptr [[DOTOMP_UB]], align 8 -// CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 -// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK1-NEXT: [[CMP14:%.*]] = icmp sgt i64 [[TMP10]], [[TMP11]] -// CHECK1-NEXT: br i1 [[CMP14]], label [[COND_TRUE15:%.*]], label [[COND_FALSE16:%.*]] -// CHECK1: cond.true15: -// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK1-NEXT: br label [[COND_END17:%.*]] -// CHECK1: cond.false16: -// CHECK1-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 -// CHECK1-NEXT: br label [[COND_END17]] -// CHECK1: cond.end17: -// CHECK1-NEXT: [[COND18:%.*]] = phi i64 [ [[TMP12]], [[COND_TRUE15]] ], [ [[TMP13]], [[COND_FALSE16]] ] -// CHECK1-NEXT: store i64 [[COND18]], ptr [[DOTOMP_UB]], align 8 -// CHECK1-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 -// CHECK1-NEXT: store i64 [[TMP14]], ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ] +// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 +// CHECK1-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 -// CHECK1-NEXT: [[CMP19:%.*]] = icmp sle i64 [[TMP15]], [[TMP16]] -// CHECK1-NEXT: br i1 [[CMP19]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] +// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK1-NEXT: [[SUB20:%.*]] = sub i32 [[TMP18]], [[TMP19]] -// CHECK1-NEXT: [[SUB21:%.*]] = sub i32 [[SUB20]], 1 -// CHECK1-NEXT: [[ADD22:%.*]] = add i32 [[SUB21]], 1 -// CHECK1-NEXT: [[DIV23:%.*]] = udiv i32 [[ADD22]], 1 -// CHECK1-NEXT: [[MUL24:%.*]] = mul i32 1, [[DIV23]] -// CHECK1-NEXT: [[MUL25:%.*]] = mul i32 [[MUL24]], 4 -// CHECK1-NEXT: [[CONV26:%.*]] = zext i32 [[MUL25]] to i64 -// CHECK1-NEXT: [[DIV27:%.*]] = sdiv i64 [[TMP17]], [[CONV26]] -// CHECK1-NEXT: [[MUL28:%.*]] = mul nsw i64 [[DIV27]], 5 -// CHECK1-NEXT: [[ADD29:%.*]] = add nsw i64 0, [[MUL28]] -// CHECK1-NEXT: [[CONV30:%.*]] = trunc i64 [[ADD29]] to i32 -// CHECK1-NEXT: store i32 [[CONV30]], ptr [[DOTFLOOR_0_IV_I11]], align 4 -// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK1-NEXT: [[CONV31:%.*]] = sext i32 [[TMP20]] to i64 -// CHECK1-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK1-NEXT: [[SUB32:%.*]] = sub i32 [[TMP23]], [[TMP24]] -// CHECK1-NEXT: [[SUB33:%.*]] = sub i32 [[SUB32]], 1 -// CHECK1-NEXT: [[ADD34:%.*]] = add i32 [[SUB33]], 1 -// CHECK1-NEXT: [[DIV35:%.*]] = udiv i32 [[ADD34]], 1 -// CHECK1-NEXT: [[MUL36:%.*]] = mul i32 1, [[DIV35]] -// CHECK1-NEXT: [[MUL37:%.*]] = mul i32 [[MUL36]], 4 -// CHECK1-NEXT: [[CONV38:%.*]] = zext i32 [[MUL37]] to i64 -// CHECK1-NEXT: [[DIV39:%.*]] = sdiv i64 [[TMP22]], [[CONV38]] -// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK1-NEXT: [[SUB40:%.*]] = sub i32 [[TMP25]], [[TMP26]] -// CHECK1-NEXT: [[SUB41:%.*]] = sub i32 [[SUB40]], 1 -// CHECK1-NEXT: [[ADD42:%.*]] = add i32 [[SUB41]], 1 -// CHECK1-NEXT: [[DIV43:%.*]] = udiv i32 [[ADD42]], 1 -// CHECK1-NEXT: [[MUL44:%.*]] = mul i32 1, [[DIV43]] -// CHECK1-NEXT: [[MUL45:%.*]] = mul i32 [[MUL44]], 4 -// CHECK1-NEXT: [[CONV46:%.*]] = zext i32 [[MUL45]] to i64 -// CHECK1-NEXT: [[MUL47:%.*]] = mul nsw i64 [[DIV39]], [[CONV46]] -// CHECK1-NEXT: [[SUB48:%.*]] = sub nsw i64 [[TMP21]], [[MUL47]] -// CHECK1-NEXT: [[DIV49:%.*]] = sdiv i64 [[SUB48]], 4 -// CHECK1-NEXT: [[MUL50:%.*]] = mul nsw i64 [[DIV49]], 1 -// CHECK1-NEXT: [[ADD51:%.*]] = add nsw i64 [[CONV31]], [[MUL50]] -// CHECK1-NEXT: [[CONV52:%.*]] = trunc i64 [[ADD51]] to i32 -// CHECK1-NEXT: store i32 [[CONV52]], ptr [[DOTTILE_0_IV_I12]], align 4 -// CHECK1-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK1-NEXT: [[SUB53:%.*]] = sub i32 [[TMP29]], [[TMP30]] -// CHECK1-NEXT: [[SUB54:%.*]] = sub i32 [[SUB53]], 1 -// CHECK1-NEXT: [[ADD55:%.*]] = add i32 [[SUB54]], 1 -// CHECK1-NEXT: [[DIV56:%.*]] = udiv i32 [[ADD55]], 1 -// CHECK1-NEXT: [[MUL57:%.*]] = mul i32 1, [[DIV56]] -// CHECK1-NEXT: [[MUL58:%.*]] = mul i32 [[MUL57]], 4 -// CHECK1-NEXT: [[CONV59:%.*]] = zext i32 [[MUL58]] to i64 -// CHECK1-NEXT: [[DIV60:%.*]] = sdiv i64 [[TMP28]], [[CONV59]] -// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK1-NEXT: [[SUB61:%.*]] = sub i32 [[TMP31]], [[TMP32]] -// CHECK1-NEXT: [[SUB62:%.*]] = sub i32 [[SUB61]], 1 -// CHECK1-NEXT: [[ADD63:%.*]] = add i32 [[SUB62]], 1 -// CHECK1-NEXT: [[DIV64:%.*]] = udiv i32 [[ADD63]], 1 -// CHECK1-NEXT: [[MUL65:%.*]] = mul i32 1, [[DIV64]] -// CHECK1-NEXT: [[MUL66:%.*]] = mul i32 [[MUL65]], 4 -// CHECK1-NEXT: [[CONV67:%.*]] = zext i32 [[MUL66]] to i64 -// CHECK1-NEXT: [[MUL68:%.*]] = mul nsw i64 [[DIV60]], [[CONV67]] -// CHECK1-NEXT: [[SUB69:%.*]] = sub nsw i64 [[TMP27]], [[MUL68]] -// CHECK1-NEXT: [[TMP33:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK1-NEXT: [[SUB70:%.*]] = sub i32 [[TMP35]], [[TMP36]] -// CHECK1-NEXT: [[SUB71:%.*]] = sub i32 [[SUB70]], 1 -// CHECK1-NEXT: [[ADD72:%.*]] = add i32 [[SUB71]], 1 -// CHECK1-NEXT: [[DIV73:%.*]] = udiv i32 [[ADD72]], 1 -// CHECK1-NEXT: [[MUL74:%.*]] = mul i32 1, [[DIV73]] -// CHECK1-NEXT: [[MUL75:%.*]] = mul i32 [[MUL74]], 4 -// CHECK1-NEXT: [[CONV76:%.*]] = zext i32 [[MUL75]] to i64 -// CHECK1-NEXT: [[DIV77:%.*]] = sdiv i64 [[TMP34]], [[CONV76]] -// CHECK1-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK1-NEXT: [[SUB78:%.*]] = sub i32 [[TMP37]], [[TMP38]] -// CHECK1-NEXT: [[SUB79:%.*]] = sub i32 [[SUB78]], 1 -// CHECK1-NEXT: [[ADD80:%.*]] = add i32 [[SUB79]], 1 -// CHECK1-NEXT: [[DIV81:%.*]] = udiv i32 [[ADD80]], 1 -// CHECK1-NEXT: [[MUL82:%.*]] = mul i32 1, [[DIV81]] -// CHECK1-NEXT: [[MUL83:%.*]] = mul i32 [[MUL82]], 4 -// CHECK1-NEXT: [[CONV84:%.*]] = zext i32 [[MUL83]] to i64 -// CHECK1-NEXT: [[MUL85:%.*]] = mul nsw i64 [[DIV77]], [[CONV84]] -// CHECK1-NEXT: [[SUB86:%.*]] = sub nsw i64 [[TMP33]], [[MUL85]] -// CHECK1-NEXT: [[DIV87:%.*]] = sdiv i64 [[SUB86]], 4 -// CHECK1-NEXT: [[MUL88:%.*]] = mul nsw i64 [[DIV87]], 4 -// CHECK1-NEXT: [[SUB89:%.*]] = sub nsw i64 [[SUB69]], [[MUL88]] -// CHECK1-NEXT: [[MUL90:%.*]] = mul nsw i64 [[SUB89]], 3 -// CHECK1-NEXT: [[ADD91:%.*]] = add nsw i64 7, [[MUL90]] -// CHECK1-NEXT: [[CONV92:%.*]] = trunc i64 [[ADD91]] to i32 -// CHECK1-NEXT: store i32 [[CONV92]], ptr [[J13]], align 4 -// CHECK1-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTTILE_0_IV_I12]], align 4 -// CHECK1-NEXT: [[MUL93:%.*]] = mul nsw i32 [[TMP39]], 3 -// CHECK1-NEXT: [[ADD94:%.*]] = add nsw i32 7, [[MUL93]] -// CHECK1-NEXT: store i32 [[ADD94]], ptr [[I]], align 4 -// CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[I]], align 4 -// CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[J13]], align 4 -// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP40]], i32 noundef [[TMP41]]) +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP6]], 5 +// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 5 +// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTFLOOR_0_IV_I]], align 4 +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP8]], 5 +// CHECK1-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 5 +// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], [[MUL4]] +// CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 +// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] +// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTTILE_CNT_0_IV_I]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTTILE_CNT_0_IV_I]], align 4 +// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] +// CHECK1-NEXT: store i32 [[ADD7]], ptr [[DOTTILE_0_IV_I]], align 4 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 +// CHECK1-NEXT: [[MUL8:%.*]] = mul nsw i32 [[TMP11]], 3 +// CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 7, [[MUL8]] +// CHECK1-NEXT: store i32 [[ADD9]], ptr [[I]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 +// CHECK1-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP12]], 4 +// CHECK1-NEXT: br i1 [[CMP10]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] +// CHECK1: if.then: +// CHECK1-NEXT: store i32 7, ptr [[J]], align 4 +// CHECK1-NEXT: br label [[FOR_COND:%.*]] +// CHECK1: for.cond: +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[J]], align 4 +// CHECK1-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP13]], 17 +// CHECK1-NEXT: br i1 [[CMP11]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK1: for.body: +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[J]], align 4 +// CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP14]], i32 noundef [[TMP15]]) +// CHECK1-NEXT: br label [[FOR_INC:%.*]] +// CHECK1: for.inc: +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[J]], align 4 +// CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP16]], 3 +// CHECK1-NEXT: store i32 [[ADD12]], ptr [[J]], align 4 +// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK1: for.end: +// CHECK1-NEXT: br label [[IF_END]] +// CHECK1: if.end: // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK1-NEXT: [[ADD95:%.*]] = add nsw i64 [[TMP42]], 1 -// CHECK1-NEXT: store i64 [[ADD95]], ptr [[DOTOMP_IV]], align 8 +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK1-NEXT: store i32 [[ADD13]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]]) -// CHECK1-NEXT: br label [[OMP_PRECOND_END]] -// CHECK1: omp.precond.end: // CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]]) // CHECK1-NEXT: ret void // @@ -920,12 +801,13 @@ extern "C" void foo10(data_t data) { // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTTILE_CNT_0_IV_I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32 7, ptr [[I]], align 4 @@ -960,46 +842,43 @@ extern "C" void foo10(data_t data) { // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTFLOOR_0_IV_I]], align 4 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 -// CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTTILE_0_IV_I]], align 4 +// CHECK1-NEXT: store i32 0, ptr [[DOTTILE_CNT_0_IV_I]], align 4 // CHECK1-NEXT: br label [[FOR_COND:%.*]] // CHECK1: for.cond: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 -// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 5 -// CHECK1-NEXT: [[CMP3:%.*]] = icmp slt i32 4, [[ADD2]] -// CHECK1-NEXT: br i1 [[CMP3]], label [[COND_TRUE4:%.*]], label [[COND_FALSE5:%.*]] -// CHECK1: cond.true4: -// CHECK1-NEXT: br label [[COND_END7:%.*]] -// CHECK1: cond.false5: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 -// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 5 -// CHECK1-NEXT: br label [[COND_END7]] -// CHECK1: cond.end7: -// CHECK1-NEXT: [[COND8:%.*]] = phi i32 [ 4, [[COND_TRUE4]] ], [ [[ADD6]], [[COND_FALSE5]] ] -// CHECK1-NEXT: [[CMP9:%.*]] = icmp slt i32 [[TMP9]], [[COND8]] -// CHECK1-NEXT: br i1 [[CMP9]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTTILE_CNT_0_IV_I]], align 4 +// CHECK1-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP8]], 5 +// CHECK1-NEXT: br i1 [[CMP2]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] // CHECK1: for.body: +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTTILE_CNT_0_IV_I]], align 4 +// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] +// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTTILE_0_IV_I]], align 4 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 +// CHECK1-NEXT: [[MUL4:%.*]] = mul nsw i32 [[TMP11]], 3 +// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 7, [[MUL4]] +// CHECK1-NEXT: store i32 [[ADD5]], ptr [[I]], align 4 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 -// CHECK1-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP12]], 3 -// CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 7, [[MUL10]] -// CHECK1-NEXT: store i32 [[ADD11]], ptr [[I]], align 4 +// CHECK1-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP12]], 4 +// CHECK1-NEXT: br i1 [[CMP6]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] +// CHECK1: if.then: // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: call void (...) @body(i32 noundef [[TMP13]]) +// CHECK1-NEXT: br label [[IF_END]] +// CHECK1: if.end: // CHECK1-NEXT: br label [[FOR_INC:%.*]] // CHECK1: for.inc: -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTTILE_CNT_0_IV_I]], align 4 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTTILE_0_IV_I]], align 4 -// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK1-NEXT: store i32 [[INC]], ptr [[DOTTILE_CNT_0_IV_I]], align 4 +// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK1: for.end: // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK1-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK1-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -1087,14 +966,14 @@ extern "C" void foo10(data_t data) { // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 // CHECK1-NEXT: [[INC:%.*]] = add i32 [[TMP16]], 1 // CHECK1-NEXT: store i32 [[INC]], ptr [[DOTTILE_0_IV_I]], align 4 -// CHECK1-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP21:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP23:![0-9]+]] // CHECK1: for.end: // CHECK1-NEXT: br label [[FOR_INC15:%.*]] // CHECK1: for.inc15: // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 // CHECK1-NEXT: [[ADD16:%.*]] = add i32 [[TMP17]], 5 // CHECK1-NEXT: store i32 [[ADD16]], ptr [[DOTFLOOR_0_IV_I]], align 4 -// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] // CHECK1: for.end17: // CHECK1-NEXT: ret void // @@ -1166,7 +1045,7 @@ extern "C" void foo10(data_t data) { // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK1-NEXT: store i32 [[INC]], ptr [[DOTTILE_0_IV_I]], align 4 -// CHECK1-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP25:![0-9]+]] // CHECK1: for.end: // CHECK1-NEXT: br label [[FOR_INC17:%.*]] // CHECK1: for.inc17: @@ -1183,7 +1062,7 @@ extern "C" void foo10(data_t data) { // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 // CHECK1-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP14]], [[COND22]] // CHECK1-NEXT: store i32 [[ADD23]], ptr [[DOTFLOOR_0_IV_I]], align 4 -// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] // CHECK1: for.end24: // CHECK1-NEXT: ret void // @@ -1202,14 +1081,14 @@ extern "C" void foo10(data_t data) { // CHECK1-NEXT: [[V:%.*]] = alloca double, align 8 // CHECK1-NEXT: [[ARRAY:%.*]] = getelementptr inbounds nuw [[STRUCT_DATA_T]], ptr [[DATA]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[ARRAY]], ptr [[__RANGE2]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__RANGE2]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META2]], !align [[META27:![0-9]+]] // CHECK1-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [12 x double], ptr [[TMP0]], i64 0, i64 0 // CHECK1-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY]], i64 12 // CHECK1-NEXT: store ptr [[ADD_PTR]], ptr [[__END2]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE2]], align 8 +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META2]], !align [[META27]] // CHECK1-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [12 x double], ptr [[TMP1]], i64 0, i64 0 // CHECK1-NEXT: store ptr [[ARRAYDECAY1]], ptr [[__BEGIN2]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE2]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META2]], !align [[META27]] // CHECK1-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [12 x double], ptr [[TMP2]], i64 0, i64 0 // CHECK1-NEXT: store ptr [[ARRAYDECAY2]], ptr [[DOTCAPTURE_EXPR_]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__END2]], align 8 @@ -1273,14 +1152,14 @@ extern "C" void foo10(data_t data) { // CHECK1-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTTILE_0_IV___BEGIN2]], align 8 // CHECK1-NEXT: [[INC:%.*]] = add nsw i64 [[TMP19]], 1 // CHECK1-NEXT: store i64 [[INC]], ptr [[DOTTILE_0_IV___BEGIN2]], align 8 -// CHECK1-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP28:![0-9]+]] // CHECK1: for.end: // CHECK1-NEXT: br label [[FOR_INC16:%.*]] // CHECK1: for.inc16: // CHECK1-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTFLOOR_0_IV___BEGIN2]], align 8 // CHECK1-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP20]], 5 // CHECK1-NEXT: store i64 [[ADD17]], ptr [[DOTFLOOR_0_IV___BEGIN2]], align 8 -// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] // CHECK1: for.end18: // CHECK1-NEXT: ret void // @@ -1301,14 +1180,14 @@ extern "C" void foo10(data_t data) { // CHECK1-NEXT: store double 4.200000e+01, ptr [[C]], align 8 // CHECK1-NEXT: [[ARRAY:%.*]] = getelementptr inbounds nuw [[STRUCT_DATA_T]], ptr [[DATA]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[ARRAY]], ptr [[__RANGE2]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__RANGE2]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META2]], !align [[META27]] // CHECK1-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [12 x double], ptr [[TMP0]], i64 0, i64 0 // CHECK1-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY]], i64 12 // CHECK1-NEXT: store ptr [[ADD_PTR]], ptr [[__END2]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE2]], align 8 +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META2]], !align [[META27]] // CHECK1-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [12 x double], ptr [[TMP1]], i64 0, i64 0 // CHECK1-NEXT: store ptr [[ARRAYDECAY1]], ptr [[__BEGIN2]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE2]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META2]], !align [[META27]] // CHECK1-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [12 x double], ptr [[TMP2]], i64 0, i64 0 // CHECK1-NEXT: store ptr [[ARRAYDECAY2]], ptr [[DOTCAPTURE_EXPR_]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__END2]], align 8 @@ -1373,14 +1252,14 @@ extern "C" void foo10(data_t data) { // CHECK1-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTTILE_0_IV___BEGIN2]], align 8 // CHECK1-NEXT: [[INC:%.*]] = add nsw i64 [[TMP20]], 1 // CHECK1-NEXT: store i64 [[INC]], ptr [[DOTTILE_0_IV___BEGIN2]], align 8 -// CHECK1-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP27:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP30:![0-9]+]] // CHECK1: for.end: // CHECK1-NEXT: br label [[FOR_INC16:%.*]] // CHECK1: for.inc16: // CHECK1-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTFLOOR_0_IV___BEGIN2]], align 8 // CHECK1-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP21]], 5 // CHECK1-NEXT: store i64 [[ADD17]], ptr [[DOTFLOOR_0_IV___BEGIN2]], align 8 -// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] +// CHECK1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] // CHECK1: for.end18: // CHECK1-NEXT: ret void // @@ -1452,9 +1331,9 @@ extern "C" void foo10(data_t data) { // CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 3 // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 7, [[MUL]] -// CHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[I2]], align 8 +// CHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[I2]], align 8, !nonnull [[META2:![0-9]+]], !align [[META3:![0-9]+]] // CHECK2-NEXT: store i32 [[ADD9]], ptr [[TMP6]], align 4 -// CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[I2]], align 8 +// CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[I2]], align 8, !nonnull [[META2]], !align [[META3]] // CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 // CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP8]]) // CHECK2-NEXT: br label [[FOR_INC:%.*]] @@ -1462,14 +1341,14 @@ extern "C" void foo10(data_t data) { // CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK2-NEXT: store i32 [[INC]], ptr [[DOTTILE_0_IV_I]], align 4 -// CHECK2-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP3:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK2: for.end: // CHECK2-NEXT: br label [[FOR_INC10:%.*]] // CHECK2: for.inc10: // CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 // CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP10]], 5 // CHECK2-NEXT: store i32 [[ADD11]], ptr [[DOTFLOOR_0_IV_I]], align 4 -// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK2: for.end12: // CHECK2-NEXT: ret void // @@ -1560,14 +1439,14 @@ extern "C" void foo10(data_t data) { // CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 // CHECK2-NEXT: [[INC:%.*]] = add i32 [[TMP20]], 1 // CHECK2-NEXT: store i32 [[INC]], ptr [[DOTTILE_0_IV_I]], align 4 -// CHECK2-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP6:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP7:![0-9]+]] // CHECK2: for.end: // CHECK2-NEXT: br label [[FOR_INC15:%.*]] // CHECK2: for.inc15: // CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 // CHECK2-NEXT: [[ADD16:%.*]] = add i32 [[TMP21]], 5 // CHECK2-NEXT: store i32 [[ADD16]], ptr [[DOTFLOOR_0_IV_I]], align 4 -// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] // CHECK2: for.end17: // CHECK2-NEXT: ret void // @@ -1588,14 +1467,14 @@ extern "C" void foo10(data_t data) { // CHECK2-NEXT: store double 4.200000e+01, ptr [[C]], align 8 // CHECK2-NEXT: [[ARRAY:%.*]] = getelementptr inbounds nuw [[STRUCT_DATA_T]], ptr [[DATA]], i32 0, i32 0 // CHECK2-NEXT: store ptr [[ARRAY]], ptr [[__RANGE2]], align 8 -// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__RANGE2]], align 8 +// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META2]], !align [[META9:![0-9]+]] // CHECK2-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [12 x double], ptr [[TMP0]], i64 0, i64 0 // CHECK2-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY]], i64 12 // CHECK2-NEXT: store ptr [[ADD_PTR]], ptr [[__END2]], align 8 -// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE2]], align 8 +// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META2]], !align [[META9]] // CHECK2-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [12 x double], ptr [[TMP1]], i64 0, i64 0 // CHECK2-NEXT: store ptr [[ARRAYDECAY1]], ptr [[__BEGIN2]], align 8 -// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE2]], align 8 +// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META2]], !align [[META9]] // CHECK2-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [12 x double], ptr [[TMP2]], i64 0, i64 0 // CHECK2-NEXT: store ptr [[ARRAYDECAY2]], ptr [[DOTCAPTURE_EXPR_]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__END2]], align 8 @@ -1660,14 +1539,14 @@ extern "C" void foo10(data_t data) { // CHECK2-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTTILE_0_IV___BEGIN2]], align 8 // CHECK2-NEXT: [[INC:%.*]] = add nsw i64 [[TMP20]], 1 // CHECK2-NEXT: store i64 [[INC]], ptr [[DOTTILE_0_IV___BEGIN2]], align 8 -// CHECK2-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP8:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK2: for.end: // CHECK2-NEXT: br label [[FOR_INC16:%.*]] // CHECK2: for.inc16: // CHECK2-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTFLOOR_0_IV___BEGIN2]], align 8 // CHECK2-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP21]], 5 // CHECK2-NEXT: store i64 [[ADD17]], ptr [[DOTFLOOR_0_IV___BEGIN2]], align 8 -// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] // CHECK2: for.end18: // CHECK2-NEXT: ret void // @@ -1759,28 +1638,28 @@ extern "C" void foo10(data_t data) { // CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTTILE_1_IV_J]], align 4 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1 // CHECK2-NEXT: store i32 [[INC]], ptr [[DOTTILE_1_IV_J]], align 4 -// CHECK2-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND10]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK2: for.end: // CHECK2-NEXT: br label [[FOR_INC22:%.*]] // CHECK2: for.inc22: // CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 // CHECK2-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP15]], 1 // CHECK2-NEXT: store i32 [[INC23]], ptr [[DOTTILE_0_IV_I]], align 4 -// CHECK2-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP11:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND4]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK2: for.end24: // CHECK2-NEXT: br label [[FOR_INC25:%.*]] // CHECK2: for.inc25: // CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4 // CHECK2-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP16]], 5 // CHECK2-NEXT: store i32 [[ADD26]], ptr [[DOTFLOOR_1_IV_J]], align 4 -// CHECK2-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP12:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP14:![0-9]+]] // CHECK2: for.end27: // CHECK2-NEXT: br label [[FOR_INC28:%.*]] // CHECK2: for.inc28: // CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 // CHECK2-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP17]], 5 // CHECK2-NEXT: store i32 [[ADD29]], ptr [[DOTFLOOR_0_IV_I]], align 4 -// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] // CHECK2: for.end30: // CHECK2-NEXT: ret void // @@ -1791,15 +1670,17 @@ extern "C" void foo10(data_t data) { // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK2-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK2-NEXT: [[DOTTILE_1_IV_J:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTFLOOR_1_IV_J:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[DOTTILE_1_IV_J:%.*]] = alloca i32, align 4 +// CHECK2-NEXT: [[DOTTILE_CNT_0_IV_I:%.*]] = alloca i32, align 4 +// CHECK2-NEXT: [[DOTTILE_CNT_1_IV_J:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) // CHECK2-NEXT: store i32 7, ptr [[I]], align 4 // CHECK2-NEXT: store i32 7, ptr [[J]], align 4 @@ -1837,87 +1718,79 @@ extern "C" void foo10(data_t data) { // CHECK2: for.cond: // CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4 // CHECK2-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP7]], 4 -// CHECK2-NEXT: br i1 [[CMP2]], label [[FOR_BODY:%.*]], label [[FOR_END32:%.*]] +// CHECK2-NEXT: br i1 [[CMP2]], label [[FOR_BODY:%.*]], label [[FOR_END22:%.*]] // CHECK2: for.body: -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 -// CHECK2-NEXT: store i32 [[TMP8]], ptr [[DOTTILE_0_IV_I]], align 4 +// CHECK2-NEXT: store i32 0, ptr [[DOTTILE_CNT_0_IV_I]], align 4 // CHECK2-NEXT: br label [[FOR_COND3:%.*]] // CHECK2: for.cond3: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 -// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 5 -// CHECK2-NEXT: [[CMP5:%.*]] = icmp slt i32 4, [[ADD4]] -// CHECK2-NEXT: br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]] -// CHECK2: cond.true6: -// CHECK2-NEXT: br label [[COND_END9:%.*]] -// CHECK2: cond.false7: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 -// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP11]], 5 -// CHECK2-NEXT: br label [[COND_END9]] -// CHECK2: cond.end9: -// CHECK2-NEXT: [[COND10:%.*]] = phi i32 [ 4, [[COND_TRUE6]] ], [ [[ADD8]], [[COND_FALSE7]] ] -// CHECK2-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP9]], [[COND10]] -// CHECK2-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END29:%.*]] -// CHECK2: for.body12: -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 -// CHECK2-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP12]], 3 -// CHECK2-NEXT: [[ADD14:%.*]] = add nsw i32 7, [[MUL13]] -// CHECK2-NEXT: store i32 [[ADD14]], ptr [[I]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTTILE_CNT_0_IV_I]], align 4 +// CHECK2-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP8]], 5 +// CHECK2-NEXT: br i1 [[CMP4]], label [[FOR_BODY5:%.*]], label [[FOR_END19:%.*]] +// CHECK2: for.body5: +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTTILE_CNT_0_IV_I]], align 4 +// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] +// CHECK2-NEXT: store i32 [[ADD6]], ptr [[DOTTILE_0_IV_I]], align 4 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 +// CHECK2-NEXT: [[MUL7:%.*]] = mul nsw i32 [[TMP11]], 3 +// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 7, [[MUL7]] +// CHECK2-NEXT: store i32 [[ADD8]], ptr [[I]], align 4 +// CHECK2-NEXT: store i32 0, ptr [[DOTTILE_CNT_1_IV_J]], align 4 +// CHECK2-NEXT: br label [[FOR_COND9:%.*]] +// CHECK2: for.cond9: +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTTILE_CNT_1_IV_J]], align 4 +// CHECK2-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP12]], 5 +// CHECK2-NEXT: br i1 [[CMP10]], label [[FOR_BODY11:%.*]], label [[FOR_END:%.*]] +// CHECK2: for.body11: // CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4 -// CHECK2-NEXT: store i32 [[TMP13]], ptr [[DOTTILE_1_IV_J]], align 4 -// CHECK2-NEXT: br label [[FOR_COND15:%.*]] -// CHECK2: for.cond15: -// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTTILE_1_IV_J]], align 4 -// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4 -// CHECK2-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP15]], 5 -// CHECK2-NEXT: [[CMP17:%.*]] = icmp slt i32 4, [[ADD16]] -// CHECK2-NEXT: br i1 [[CMP17]], label [[COND_TRUE18:%.*]], label [[COND_FALSE19:%.*]] -// CHECK2: cond.true18: -// CHECK2-NEXT: br label [[COND_END21:%.*]] -// CHECK2: cond.false19: -// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4 -// CHECK2-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP16]], 5 -// CHECK2-NEXT: br label [[COND_END21]] -// CHECK2: cond.end21: -// CHECK2-NEXT: [[COND22:%.*]] = phi i32 [ 4, [[COND_TRUE18]] ], [ [[ADD20]], [[COND_FALSE19]] ] -// CHECK2-NEXT: [[CMP23:%.*]] = icmp slt i32 [[TMP14]], [[COND22]] -// CHECK2-NEXT: br i1 [[CMP23]], label [[FOR_BODY24:%.*]], label [[FOR_END:%.*]] -// CHECK2: for.body24: +// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTTILE_CNT_1_IV_J]], align 4 +// CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK2-NEXT: store i32 [[ADD12]], ptr [[DOTTILE_1_IV_J]], align 4 +// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTTILE_1_IV_J]], align 4 +// CHECK2-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 3 +// CHECK2-NEXT: [[ADD14:%.*]] = add nsw i32 7, [[MUL13]] +// CHECK2-NEXT: store i32 [[ADD14]], ptr [[J]], align 4 +// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 +// CHECK2-NEXT: [[CMP15:%.*]] = icmp slt i32 [[TMP16]], 4 +// CHECK2-NEXT: br i1 [[CMP15]], label [[LAND_LHS_TRUE:%.*]], label [[IF_END:%.*]] +// CHECK2: land.lhs.true: // CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTTILE_1_IV_J]], align 4 -// CHECK2-NEXT: [[MUL25:%.*]] = mul nsw i32 [[TMP17]], 3 -// CHECK2-NEXT: [[ADD26:%.*]] = add nsw i32 7, [[MUL25]] -// CHECK2-NEXT: store i32 [[ADD26]], ptr [[J]], align 4 +// CHECK2-NEXT: [[CMP16:%.*]] = icmp slt i32 [[TMP17]], 4 +// CHECK2-NEXT: br i1 [[CMP16]], label [[IF_THEN:%.*]], label [[IF_END]] +// CHECK2: if.then: // CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[J]], align 4 // CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP18]], i32 noundef [[TMP19]]) +// CHECK2-NEXT: br label [[IF_END]] +// CHECK2: if.end: // CHECK2-NEXT: br label [[FOR_INC:%.*]] // CHECK2: for.inc: -// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTTILE_1_IV_J]], align 4 +// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTTILE_CNT_1_IV_J]], align 4 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTTILE_1_IV_J]], align 4 -// CHECK2-NEXT: br label [[FOR_COND15]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTTILE_CNT_1_IV_J]], align 4 +// CHECK2-NEXT: br label [[FOR_COND9]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK2: for.end: -// CHECK2-NEXT: br label [[FOR_INC27:%.*]] -// CHECK2: for.inc27: -// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 -// CHECK2-NEXT: [[INC28:%.*]] = add nsw i32 [[TMP21]], 1 -// CHECK2-NEXT: store i32 [[INC28]], ptr [[DOTTILE_0_IV_I]], align 4 -// CHECK2-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP15:![0-9]+]] -// CHECK2: for.end29: -// CHECK2-NEXT: br label [[FOR_INC30:%.*]] -// CHECK2: for.inc30: +// CHECK2-NEXT: br label [[FOR_INC17:%.*]] +// CHECK2: for.inc17: +// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTTILE_CNT_0_IV_I]], align 4 +// CHECK2-NEXT: [[INC18:%.*]] = add nsw i32 [[TMP21]], 1 +// CHECK2-NEXT: store i32 [[INC18]], ptr [[DOTTILE_CNT_0_IV_I]], align 4 +// CHECK2-NEXT: br label [[FOR_COND3]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK2: for.end19: +// CHECK2-NEXT: br label [[FOR_INC20:%.*]] +// CHECK2: for.inc20: // CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4 -// CHECK2-NEXT: [[ADD31:%.*]] = add nsw i32 [[TMP22]], 5 -// CHECK2-NEXT: store i32 [[ADD31]], ptr [[DOTFLOOR_1_IV_J]], align 4 -// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] -// CHECK2: for.end32: +// CHECK2-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP22]], 5 +// CHECK2-NEXT: store i32 [[ADD21]], ptr [[DOTFLOOR_1_IV_J]], align 4 +// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] +// CHECK2: for.end22: // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: // CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK2-NEXT: [[ADD33:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK2-NEXT: store i32 [[ADD33]], ptr [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK2-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -1934,7 +1807,9 @@ extern "C" void foo10(data_t data) { // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK2-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[J:%.*]] = alloca i32, align 4 +// CHECK2-NEXT: [[DOTTILE_1_IV_J:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 @@ -1942,8 +1817,8 @@ extern "C" void foo10(data_t data) { // CHECK2-NEXT: [[K:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTFLOOR_1_IV_J:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[DOTTILE_1_IV_J:%.*]] = alloca i32, align 4 +// CHECK2-NEXT: [[DOTTILE_CNT_0_IV_I:%.*]] = alloca i32, align 4 +// CHECK2-NEXT: [[DOTTILE_CNT_1_IV_J:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) // CHECK2-NEXT: store i32 7, ptr [[I]], align 4 // CHECK2-NEXT: store i32 7, ptr [[J]], align 4 @@ -1990,87 +1865,79 @@ extern "C" void foo10(data_t data) { // CHECK2: for.cond: // CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4 // CHECK2-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP9]], 4 -// CHECK2-NEXT: br i1 [[CMP7]], label [[FOR_BODY:%.*]], label [[FOR_END37:%.*]] +// CHECK2-NEXT: br i1 [[CMP7]], label [[FOR_BODY:%.*]], label [[FOR_END27:%.*]] // CHECK2: for.body: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 -// CHECK2-NEXT: store i32 [[TMP10]], ptr [[DOTTILE_0_IV_I]], align 4 +// CHECK2-NEXT: store i32 0, ptr [[DOTTILE_CNT_0_IV_I]], align 4 // CHECK2-NEXT: br label [[FOR_COND8:%.*]] // CHECK2: for.cond8: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 -// CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP12]], 5 -// CHECK2-NEXT: [[CMP10:%.*]] = icmp slt i32 4, [[ADD9]] -// CHECK2-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] -// CHECK2: cond.true11: -// CHECK2-NEXT: br label [[COND_END14:%.*]] -// CHECK2: cond.false12: -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 -// CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP13]], 5 -// CHECK2-NEXT: br label [[COND_END14]] -// CHECK2: cond.end14: -// CHECK2-NEXT: [[COND15:%.*]] = phi i32 [ 4, [[COND_TRUE11]] ], [ [[ADD13]], [[COND_FALSE12]] ] -// CHECK2-NEXT: [[CMP16:%.*]] = icmp slt i32 [[TMP11]], [[COND15]] -// CHECK2-NEXT: br i1 [[CMP16]], label [[FOR_BODY17:%.*]], label [[FOR_END34:%.*]] -// CHECK2: for.body17: -// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 -// CHECK2-NEXT: [[MUL18:%.*]] = mul nsw i32 [[TMP14]], 3 -// CHECK2-NEXT: [[ADD19:%.*]] = add nsw i32 7, [[MUL18]] -// CHECK2-NEXT: store i32 [[ADD19]], ptr [[I]], align 4 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTTILE_CNT_0_IV_I]], align 4 +// CHECK2-NEXT: [[CMP9:%.*]] = icmp slt i32 [[TMP10]], 5 +// CHECK2-NEXT: br i1 [[CMP9]], label [[FOR_BODY10:%.*]], label [[FOR_END24:%.*]] +// CHECK2: for.body10: +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTTILE_CNT_0_IV_I]], align 4 +// CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] +// CHECK2-NEXT: store i32 [[ADD11]], ptr [[DOTTILE_0_IV_I]], align 4 +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 +// CHECK2-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP13]], 3 +// CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 7, [[MUL12]] +// CHECK2-NEXT: store i32 [[ADD13]], ptr [[I]], align 4 +// CHECK2-NEXT: store i32 0, ptr [[DOTTILE_CNT_1_IV_J]], align 4 +// CHECK2-NEXT: br label [[FOR_COND14:%.*]] +// CHECK2: for.cond14: +// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTTILE_CNT_1_IV_J]], align 4 +// CHECK2-NEXT: [[CMP15:%.*]] = icmp slt i32 [[TMP14]], 5 +// CHECK2-NEXT: br i1 [[CMP15]], label [[FOR_BODY16:%.*]], label [[FOR_END:%.*]] +// CHECK2: for.body16: // CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4 -// CHECK2-NEXT: store i32 [[TMP15]], ptr [[DOTTILE_1_IV_J]], align 4 -// CHECK2-NEXT: br label [[FOR_COND20:%.*]] -// CHECK2: for.cond20: -// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTTILE_1_IV_J]], align 4 -// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4 -// CHECK2-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP17]], 5 -// CHECK2-NEXT: [[CMP22:%.*]] = icmp slt i32 4, [[ADD21]] -// CHECK2-NEXT: br i1 [[CMP22]], label [[COND_TRUE23:%.*]], label [[COND_FALSE24:%.*]] -// CHECK2: cond.true23: -// CHECK2-NEXT: br label [[COND_END26:%.*]] -// CHECK2: cond.false24: -// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4 -// CHECK2-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP18]], 5 -// CHECK2-NEXT: br label [[COND_END26]] -// CHECK2: cond.end26: -// CHECK2-NEXT: [[COND27:%.*]] = phi i32 [ 4, [[COND_TRUE23]] ], [ [[ADD25]], [[COND_FALSE24]] ] -// CHECK2-NEXT: [[CMP28:%.*]] = icmp slt i32 [[TMP16]], [[COND27]] -// CHECK2-NEXT: br i1 [[CMP28]], label [[FOR_BODY29:%.*]], label [[FOR_END:%.*]] -// CHECK2: for.body29: +// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTTILE_CNT_1_IV_J]], align 4 +// CHECK2-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] +// CHECK2-NEXT: store i32 [[ADD17]], ptr [[DOTTILE_1_IV_J]], align 4 +// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTTILE_1_IV_J]], align 4 +// CHECK2-NEXT: [[MUL18:%.*]] = mul nsw i32 [[TMP17]], 3 +// CHECK2-NEXT: [[ADD19:%.*]] = add nsw i32 7, [[MUL18]] +// CHECK2-NEXT: store i32 [[ADD19]], ptr [[J]], align 4 +// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 +// CHECK2-NEXT: [[CMP20:%.*]] = icmp slt i32 [[TMP18]], 4 +// CHECK2-NEXT: br i1 [[CMP20]], label [[LAND_LHS_TRUE:%.*]], label [[IF_END:%.*]] +// CHECK2: land.lhs.true: // CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTTILE_1_IV_J]], align 4 -// CHECK2-NEXT: [[MUL30:%.*]] = mul nsw i32 [[TMP19]], 3 -// CHECK2-NEXT: [[ADD31:%.*]] = add nsw i32 7, [[MUL30]] -// CHECK2-NEXT: store i32 [[ADD31]], ptr [[J]], align 4 +// CHECK2-NEXT: [[CMP21:%.*]] = icmp slt i32 [[TMP19]], 4 +// CHECK2-NEXT: br i1 [[CMP21]], label [[IF_THEN:%.*]], label [[IF_END]] +// CHECK2: if.then: // CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[I]], align 4 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[J]], align 4 // CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP20]], i32 noundef [[TMP21]]) +// CHECK2-NEXT: br label [[IF_END]] +// CHECK2: if.end: // CHECK2-NEXT: br label [[FOR_INC:%.*]] // CHECK2: for.inc: -// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTTILE_1_IV_J]], align 4 +// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTTILE_CNT_1_IV_J]], align 4 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP22]], 1 -// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTTILE_1_IV_J]], align 4 -// CHECK2-NEXT: br label [[FOR_COND20]], !llvm.loop [[LOOP17:![0-9]+]] +// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTTILE_CNT_1_IV_J]], align 4 +// CHECK2-NEXT: br label [[FOR_COND14]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK2: for.end: -// CHECK2-NEXT: br label [[FOR_INC32:%.*]] -// CHECK2: for.inc32: -// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 -// CHECK2-NEXT: [[INC33:%.*]] = add nsw i32 [[TMP23]], 1 -// CHECK2-NEXT: store i32 [[INC33]], ptr [[DOTTILE_0_IV_I]], align 4 -// CHECK2-NEXT: br label [[FOR_COND8]], !llvm.loop [[LOOP18:![0-9]+]] -// CHECK2: for.end34: -// CHECK2-NEXT: br label [[FOR_INC35:%.*]] -// CHECK2: for.inc35: +// CHECK2-NEXT: br label [[FOR_INC22:%.*]] +// CHECK2: for.inc22: +// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTTILE_CNT_0_IV_I]], align 4 +// CHECK2-NEXT: [[INC23:%.*]] = add nsw i32 [[TMP23]], 1 +// CHECK2-NEXT: store i32 [[INC23]], ptr [[DOTTILE_CNT_0_IV_I]], align 4 +// CHECK2-NEXT: br label [[FOR_COND8]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK2: for.end24: +// CHECK2-NEXT: br label [[FOR_INC25:%.*]] +// CHECK2: for.inc25: // CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4 -// CHECK2-NEXT: [[ADD36:%.*]] = add nsw i32 [[TMP24]], 5 -// CHECK2-NEXT: store i32 [[ADD36]], ptr [[DOTFLOOR_1_IV_J]], align 4 -// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] -// CHECK2: for.end37: +// CHECK2-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP24]], 5 +// CHECK2-NEXT: store i32 [[ADD26]], ptr [[DOTFLOOR_1_IV_J]], align 4 +// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] +// CHECK2: for.end27: // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: // CHECK2-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK2-NEXT: [[ADD38:%.*]] = add nsw i32 [[TMP25]], 1 -// CHECK2-NEXT: store i32 [[ADD38]], ptr [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP25]], 1 +// CHECK2-NEXT: store i32 [[ADD28]], ptr [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -2083,208 +1950,101 @@ extern "C" void foo10(data_t data) { // CHECK2-LABEL: define dso_local void @foo5( // CHECK2-SAME: ) #[[ATTR1]] { // CHECK2-NEXT: entry: -// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 -// CHECK2-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[DOTFLOOR_0_IV_I11:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[DOTTILE_0_IV_I12:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[J13:%.*]] = alloca i32, align 4 +// CHECK2-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4 +// CHECK2-NEXT: [[DOTTILE_CNT_0_IV_I:%.*]] = alloca i32, align 4 +// CHECK2-NEXT: [[J:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) // CHECK2-NEXT: store i32 7, ptr [[I]], align 4 -// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP]], align 4 -// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP]], align 4 -// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 5 -// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 4, [[ADD]] +// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 +// CHECK2-NEXT: store i32 4, ptr [[DOTOMP_UB]], align 4 +// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 +// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// CHECK2-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 4 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK2: cond.true: // CHECK2-NEXT: br label [[COND_END:%.*]] // CHECK2: cond.false: -// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP]], align 4 -// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 5 +// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK2-NEXT: br label [[COND_END]] // CHECK2: cond.end: -// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[ADD4]], [[COND_FALSE]] ] -// CHECK2-NEXT: store i32 [[COND]], ptr [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK2-NEXT: [[SUB:%.*]] = sub i32 [[TMP4]], [[TMP5]] -// CHECK2-NEXT: [[SUB6:%.*]] = sub i32 [[SUB]], 1 -// CHECK2-NEXT: [[ADD7:%.*]] = add i32 [[SUB6]], 1 -// CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD7]], 1 -// CHECK2-NEXT: [[CONV:%.*]] = zext i32 [[DIV]] to i64 -// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 1, [[CONV]] -// CHECK2-NEXT: [[MUL8:%.*]] = mul nsw i64 [[MUL]], 4 -// CHECK2-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL8]], 1 -// CHECK2-NEXT: store i64 [[SUB9]], ptr [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK2-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_I]], align 4 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK2-NEXT: store i32 [[TMP6]], ptr [[DOTTILE_0_IV_I]], align 4 -// CHECK2-NEXT: store i32 7, ptr [[J]], align 4 -// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK2-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP7]], [[TMP8]] -// CHECK2-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK2: omp.precond.then: -// CHECK2-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 -// CHECK2-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK2-NEXT: store i64 [[TMP9]], ptr [[DOTOMP_UB]], align 8 -// CHECK2-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 -// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK2-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK2-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 -// CHECK2-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK2-NEXT: [[CMP14:%.*]] = icmp sgt i64 [[TMP10]], [[TMP11]] -// CHECK2-NEXT: br i1 [[CMP14]], label [[COND_TRUE15:%.*]], label [[COND_FALSE16:%.*]] -// CHECK2: cond.true15: -// CHECK2-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK2-NEXT: br label [[COND_END17:%.*]] -// CHECK2: cond.false16: -// CHECK2-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 -// CHECK2-NEXT: br label [[COND_END17]] -// CHECK2: cond.end17: -// CHECK2-NEXT: [[COND18:%.*]] = phi i64 [ [[TMP12]], [[COND_TRUE15]] ], [ [[TMP13]], [[COND_FALSE16]] ] -// CHECK2-NEXT: store i64 [[COND18]], ptr [[DOTOMP_UB]], align 8 -// CHECK2-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 -// CHECK2-NEXT: store i64 [[TMP14]], ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ] +// CHECK2-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 +// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 +// CHECK2-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 -// CHECK2-NEXT: [[CMP19:%.*]] = icmp sle i64 [[TMP15]], [[TMP16]] -// CHECK2-NEXT: br i1 [[CMP19]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK2-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] +// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK2-NEXT: [[SUB20:%.*]] = sub i32 [[TMP18]], [[TMP19]] -// CHECK2-NEXT: [[SUB21:%.*]] = sub i32 [[SUB20]], 1 -// CHECK2-NEXT: [[ADD22:%.*]] = add i32 [[SUB21]], 1 -// CHECK2-NEXT: [[DIV23:%.*]] = udiv i32 [[ADD22]], 1 -// CHECK2-NEXT: [[MUL24:%.*]] = mul i32 1, [[DIV23]] -// CHECK2-NEXT: [[MUL25:%.*]] = mul i32 [[MUL24]], 4 -// CHECK2-NEXT: [[CONV26:%.*]] = zext i32 [[MUL25]] to i64 -// CHECK2-NEXT: [[DIV27:%.*]] = sdiv i64 [[TMP17]], [[CONV26]] -// CHECK2-NEXT: [[MUL28:%.*]] = mul nsw i64 [[DIV27]], 5 -// CHECK2-NEXT: [[ADD29:%.*]] = add nsw i64 0, [[MUL28]] -// CHECK2-NEXT: [[CONV30:%.*]] = trunc i64 [[ADD29]] to i32 -// CHECK2-NEXT: store i32 [[CONV30]], ptr [[DOTFLOOR_0_IV_I11]], align 4 -// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK2-NEXT: [[CONV31:%.*]] = sext i32 [[TMP20]] to i64 -// CHECK2-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK2-NEXT: [[SUB32:%.*]] = sub i32 [[TMP23]], [[TMP24]] -// CHECK2-NEXT: [[SUB33:%.*]] = sub i32 [[SUB32]], 1 -// CHECK2-NEXT: [[ADD34:%.*]] = add i32 [[SUB33]], 1 -// CHECK2-NEXT: [[DIV35:%.*]] = udiv i32 [[ADD34]], 1 -// CHECK2-NEXT: [[MUL36:%.*]] = mul i32 1, [[DIV35]] -// CHECK2-NEXT: [[MUL37:%.*]] = mul i32 [[MUL36]], 4 -// CHECK2-NEXT: [[CONV38:%.*]] = zext i32 [[MUL37]] to i64 -// CHECK2-NEXT: [[DIV39:%.*]] = sdiv i64 [[TMP22]], [[CONV38]] -// CHECK2-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK2-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK2-NEXT: [[SUB40:%.*]] = sub i32 [[TMP25]], [[TMP26]] -// CHECK2-NEXT: [[SUB41:%.*]] = sub i32 [[SUB40]], 1 -// CHECK2-NEXT: [[ADD42:%.*]] = add i32 [[SUB41]], 1 -// CHECK2-NEXT: [[DIV43:%.*]] = udiv i32 [[ADD42]], 1 -// CHECK2-NEXT: [[MUL44:%.*]] = mul i32 1, [[DIV43]] -// CHECK2-NEXT: [[MUL45:%.*]] = mul i32 [[MUL44]], 4 -// CHECK2-NEXT: [[CONV46:%.*]] = zext i32 [[MUL45]] to i64 -// CHECK2-NEXT: [[MUL47:%.*]] = mul nsw i64 [[DIV39]], [[CONV46]] -// CHECK2-NEXT: [[SUB48:%.*]] = sub nsw i64 [[TMP21]], [[MUL47]] -// CHECK2-NEXT: [[DIV49:%.*]] = sdiv i64 [[SUB48]], 4 -// CHECK2-NEXT: [[MUL50:%.*]] = mul nsw i64 [[DIV49]], 1 -// CHECK2-NEXT: [[ADD51:%.*]] = add nsw i64 [[CONV31]], [[MUL50]] -// CHECK2-NEXT: [[CONV52:%.*]] = trunc i64 [[ADD51]] to i32 -// CHECK2-NEXT: store i32 [[CONV52]], ptr [[DOTTILE_0_IV_I12]], align 4 -// CHECK2-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK2-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK2-NEXT: [[SUB53:%.*]] = sub i32 [[TMP29]], [[TMP30]] -// CHECK2-NEXT: [[SUB54:%.*]] = sub i32 [[SUB53]], 1 -// CHECK2-NEXT: [[ADD55:%.*]] = add i32 [[SUB54]], 1 -// CHECK2-NEXT: [[DIV56:%.*]] = udiv i32 [[ADD55]], 1 -// CHECK2-NEXT: [[MUL57:%.*]] = mul i32 1, [[DIV56]] -// CHECK2-NEXT: [[MUL58:%.*]] = mul i32 [[MUL57]], 4 -// CHECK2-NEXT: [[CONV59:%.*]] = zext i32 [[MUL58]] to i64 -// CHECK2-NEXT: [[DIV60:%.*]] = sdiv i64 [[TMP28]], [[CONV59]] -// CHECK2-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK2-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK2-NEXT: [[SUB61:%.*]] = sub i32 [[TMP31]], [[TMP32]] -// CHECK2-NEXT: [[SUB62:%.*]] = sub i32 [[SUB61]], 1 -// CHECK2-NEXT: [[ADD63:%.*]] = add i32 [[SUB62]], 1 -// CHECK2-NEXT: [[DIV64:%.*]] = udiv i32 [[ADD63]], 1 -// CHECK2-NEXT: [[MUL65:%.*]] = mul i32 1, [[DIV64]] -// CHECK2-NEXT: [[MUL66:%.*]] = mul i32 [[MUL65]], 4 -// CHECK2-NEXT: [[CONV67:%.*]] = zext i32 [[MUL66]] to i64 -// CHECK2-NEXT: [[MUL68:%.*]] = mul nsw i64 [[DIV60]], [[CONV67]] -// CHECK2-NEXT: [[SUB69:%.*]] = sub nsw i64 [[TMP27]], [[MUL68]] -// CHECK2-NEXT: [[TMP33:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK2-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK2-NEXT: [[SUB70:%.*]] = sub i32 [[TMP35]], [[TMP36]] -// CHECK2-NEXT: [[SUB71:%.*]] = sub i32 [[SUB70]], 1 -// CHECK2-NEXT: [[ADD72:%.*]] = add i32 [[SUB71]], 1 -// CHECK2-NEXT: [[DIV73:%.*]] = udiv i32 [[ADD72]], 1 -// CHECK2-NEXT: [[MUL74:%.*]] = mul i32 1, [[DIV73]] -// CHECK2-NEXT: [[MUL75:%.*]] = mul i32 [[MUL74]], 4 -// CHECK2-NEXT: [[CONV76:%.*]] = zext i32 [[MUL75]] to i64 -// CHECK2-NEXT: [[DIV77:%.*]] = sdiv i64 [[TMP34]], [[CONV76]] -// CHECK2-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 -// CHECK2-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK2-NEXT: [[SUB78:%.*]] = sub i32 [[TMP37]], [[TMP38]] -// CHECK2-NEXT: [[SUB79:%.*]] = sub i32 [[SUB78]], 1 -// CHECK2-NEXT: [[ADD80:%.*]] = add i32 [[SUB79]], 1 -// CHECK2-NEXT: [[DIV81:%.*]] = udiv i32 [[ADD80]], 1 -// CHECK2-NEXT: [[MUL82:%.*]] = mul i32 1, [[DIV81]] -// CHECK2-NEXT: [[MUL83:%.*]] = mul i32 [[MUL82]], 4 -// CHECK2-NEXT: [[CONV84:%.*]] = zext i32 [[MUL83]] to i64 -// CHECK2-NEXT: [[MUL85:%.*]] = mul nsw i64 [[DIV77]], [[CONV84]] -// CHECK2-NEXT: [[SUB86:%.*]] = sub nsw i64 [[TMP33]], [[MUL85]] -// CHECK2-NEXT: [[DIV87:%.*]] = sdiv i64 [[SUB86]], 4 -// CHECK2-NEXT: [[MUL88:%.*]] = mul nsw i64 [[DIV87]], 4 -// CHECK2-NEXT: [[SUB89:%.*]] = sub nsw i64 [[SUB69]], [[MUL88]] -// CHECK2-NEXT: [[MUL90:%.*]] = mul nsw i64 [[SUB89]], 3 -// CHECK2-NEXT: [[ADD91:%.*]] = add nsw i64 7, [[MUL90]] -// CHECK2-NEXT: [[CONV92:%.*]] = trunc i64 [[ADD91]] to i32 -// CHECK2-NEXT: store i32 [[CONV92]], ptr [[J13]], align 4 -// CHECK2-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTTILE_0_IV_I12]], align 4 -// CHECK2-NEXT: [[MUL93:%.*]] = mul nsw i32 [[TMP39]], 3 -// CHECK2-NEXT: [[ADD94:%.*]] = add nsw i32 7, [[MUL93]] -// CHECK2-NEXT: store i32 [[ADD94]], ptr [[I]], align 4 -// CHECK2-NEXT: [[TMP40:%.*]] = load i32, ptr [[I]], align 4 -// CHECK2-NEXT: [[TMP41:%.*]] = load i32, ptr [[J13]], align 4 -// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP40]], i32 noundef [[TMP41]]) +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP6]], 5 +// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 5 +// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK2-NEXT: store i32 [[ADD]], ptr [[DOTFLOOR_0_IV_I]], align 4 +// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP8]], 5 +// CHECK2-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 5 +// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], [[MUL4]] +// CHECK2-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 +// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] +// CHECK2-NEXT: store i32 [[ADD6]], ptr [[DOTTILE_CNT_0_IV_I]], align 4 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTTILE_CNT_0_IV_I]], align 4 +// CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] +// CHECK2-NEXT: store i32 [[ADD7]], ptr [[DOTTILE_0_IV_I]], align 4 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 +// CHECK2-NEXT: [[MUL8:%.*]] = mul nsw i32 [[TMP11]], 3 +// CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 7, [[MUL8]] +// CHECK2-NEXT: store i32 [[ADD9]], ptr [[I]], align 4 +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 +// CHECK2-NEXT: [[CMP10:%.*]] = icmp slt i32 [[TMP12]], 4 +// CHECK2-NEXT: br i1 [[CMP10]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] +// CHECK2: if.then: +// CHECK2-NEXT: store i32 7, ptr [[J]], align 4 +// CHECK2-NEXT: br label [[FOR_COND:%.*]] +// CHECK2: for.cond: +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[J]], align 4 +// CHECK2-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP13]], 17 +// CHECK2-NEXT: br i1 [[CMP11]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK2: for.body: +// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 +// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[J]], align 4 +// CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP14]], i32 noundef [[TMP15]]) +// CHECK2-NEXT: br label [[FOR_INC:%.*]] +// CHECK2: for.inc: +// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[J]], align 4 +// CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP16]], 3 +// CHECK2-NEXT: store i32 [[ADD12]], ptr [[J]], align 4 +// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK2: for.end: +// CHECK2-NEXT: br label [[IF_END]] +// CHECK2: if.end: // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK2-NEXT: [[ADD95:%.*]] = add nsw i64 [[TMP42]], 1 -// CHECK2-NEXT: store i64 [[ADD95]], ptr [[DOTOMP_IV]], align 8 +// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK2-NEXT: store i32 [[ADD13]], ptr [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: // CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]]) -// CHECK2-NEXT: br label [[OMP_PRECOND_END]] -// CHECK2: omp.precond.end: // CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]]) // CHECK2-NEXT: ret void // @@ -2304,12 +2064,13 @@ extern "C" void foo10(data_t data) { // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK2-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4 +// CHECK2-NEXT: [[DOTTILE_CNT_0_IV_I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store i32 7, ptr [[I]], align 4 @@ -2344,46 +2105,43 @@ extern "C" void foo10(data_t data) { // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK2-NEXT: store i32 [[ADD]], ptr [[DOTFLOOR_0_IV_I]], align 4 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 -// CHECK2-NEXT: store i32 [[TMP8]], ptr [[DOTTILE_0_IV_I]], align 4 +// CHECK2-NEXT: store i32 0, ptr [[DOTTILE_CNT_0_IV_I]], align 4 // CHECK2-NEXT: br label [[FOR_COND:%.*]] // CHECK2: for.cond: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 -// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 5 -// CHECK2-NEXT: [[CMP3:%.*]] = icmp slt i32 4, [[ADD2]] -// CHECK2-NEXT: br i1 [[CMP3]], label [[COND_TRUE4:%.*]], label [[COND_FALSE5:%.*]] -// CHECK2: cond.true4: -// CHECK2-NEXT: br label [[COND_END7:%.*]] -// CHECK2: cond.false5: -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 -// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 5 -// CHECK2-NEXT: br label [[COND_END7]] -// CHECK2: cond.end7: -// CHECK2-NEXT: [[COND8:%.*]] = phi i32 [ 4, [[COND_TRUE4]] ], [ [[ADD6]], [[COND_FALSE5]] ] -// CHECK2-NEXT: [[CMP9:%.*]] = icmp slt i32 [[TMP9]], [[COND8]] -// CHECK2-NEXT: br i1 [[CMP9]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTTILE_CNT_0_IV_I]], align 4 +// CHECK2-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP8]], 5 +// CHECK2-NEXT: br i1 [[CMP2]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] // CHECK2: for.body: +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTTILE_CNT_0_IV_I]], align 4 +// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] +// CHECK2-NEXT: store i32 [[ADD3]], ptr [[DOTTILE_0_IV_I]], align 4 +// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 +// CHECK2-NEXT: [[MUL4:%.*]] = mul nsw i32 [[TMP11]], 3 +// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 7, [[MUL4]] +// CHECK2-NEXT: store i32 [[ADD5]], ptr [[I]], align 4 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 -// CHECK2-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP12]], 3 -// CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 7, [[MUL10]] -// CHECK2-NEXT: store i32 [[ADD11]], ptr [[I]], align 4 +// CHECK2-NEXT: [[CMP6:%.*]] = icmp slt i32 [[TMP12]], 4 +// CHECK2-NEXT: br i1 [[CMP6]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] +// CHECK2: if.then: // CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK2-NEXT: call void (...) @body(i32 noundef [[TMP13]]) +// CHECK2-NEXT: br label [[IF_END]] +// CHECK2: if.end: // CHECK2-NEXT: br label [[FOR_INC:%.*]] // CHECK2: for.inc: -// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 +// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTTILE_CNT_0_IV_I]], align 4 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTTILE_0_IV_I]], align 4 -// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] +// CHECK2-NEXT: store i32 [[INC]], ptr [[DOTTILE_CNT_0_IV_I]], align 4 +// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] // CHECK2: for.end: // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: // CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK2-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK2-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -2459,7 +2217,7 @@ extern "C" void foo10(data_t data) { // CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK2-NEXT: store i32 [[INC]], ptr [[DOTTILE_0_IV_I]], align 4 -// CHECK2-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP23:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP26:![0-9]+]] // CHECK2: for.end: // CHECK2-NEXT: br label [[FOR_INC17:%.*]] // CHECK2: for.inc17: @@ -2476,7 +2234,7 @@ extern "C" void foo10(data_t data) { // CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 // CHECK2-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP14]], [[COND22]] // CHECK2-NEXT: store i32 [[ADD23]], ptr [[DOTFLOOR_0_IV_I]], align 4 -// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] // CHECK2: for.end24: // CHECK2-NEXT: ret void // @@ -2495,14 +2253,14 @@ extern "C" void foo10(data_t data) { // CHECK2-NEXT: [[V:%.*]] = alloca double, align 8 // CHECK2-NEXT: [[ARRAY:%.*]] = getelementptr inbounds nuw [[STRUCT_DATA_T]], ptr [[DATA]], i32 0, i32 0 // CHECK2-NEXT: store ptr [[ARRAY]], ptr [[__RANGE2]], align 8 -// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__RANGE2]], align 8 +// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META2]], !align [[META9]] // CHECK2-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [12 x double], ptr [[TMP0]], i64 0, i64 0 // CHECK2-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY]], i64 12 // CHECK2-NEXT: store ptr [[ADD_PTR]], ptr [[__END2]], align 8 -// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE2]], align 8 +// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META2]], !align [[META9]] // CHECK2-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [12 x double], ptr [[TMP1]], i64 0, i64 0 // CHECK2-NEXT: store ptr [[ARRAYDECAY1]], ptr [[__BEGIN2]], align 8 -// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE2]], align 8 +// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[__RANGE2]], align 8, !nonnull [[META2]], !align [[META9]] // CHECK2-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [12 x double], ptr [[TMP2]], i64 0, i64 0 // CHECK2-NEXT: store ptr [[ARRAYDECAY2]], ptr [[DOTCAPTURE_EXPR_]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[__END2]], align 8 @@ -2566,14 +2324,14 @@ extern "C" void foo10(data_t data) { // CHECK2-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTTILE_0_IV___BEGIN2]], align 8 // CHECK2-NEXT: [[INC:%.*]] = add nsw i64 [[TMP19]], 1 // CHECK2-NEXT: store i64 [[INC]], ptr [[DOTTILE_0_IV___BEGIN2]], align 8 -// CHECK2-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND7]], !llvm.loop [[LOOP28:![0-9]+]] // CHECK2: for.end: // CHECK2-NEXT: br label [[FOR_INC16:%.*]] // CHECK2: for.inc16: // CHECK2-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTFLOOR_0_IV___BEGIN2]], align 8 // CHECK2-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP20]], 5 // CHECK2-NEXT: store i64 [[ADD17]], ptr [[DOTFLOOR_0_IV___BEGIN2]], align 8 -// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] // CHECK2: for.end18: // CHECK2-NEXT: ret void // @@ -2657,14 +2415,14 @@ extern "C" void foo10(data_t data) { // CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 // CHECK2-NEXT: [[INC:%.*]] = add i32 [[TMP16]], 1 // CHECK2-NEXT: store i32 [[INC]], ptr [[DOTTILE_0_IV_I]], align 4 -// CHECK2-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP27:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND6]], !llvm.loop [[LOOP30:![0-9]+]] // CHECK2: for.end: // CHECK2-NEXT: br label [[FOR_INC15:%.*]] // CHECK2: for.inc15: // CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 // CHECK2-NEXT: [[ADD16:%.*]] = add i32 [[TMP17]], 5 // CHECK2-NEXT: store i32 [[ADD16]], ptr [[DOTFLOOR_0_IV_I]], align 4 -// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] +// CHECK2-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] // CHECK2: for.end17: // CHECK2-NEXT: ret void // @@ -2676,53 +2434,61 @@ extern "C" void foo10(data_t data) { // CHECK2-NEXT: ret void // //. -// CHECK1: [[LOOP3]] = distinct !{[[LOOP3]], [[META4:![0-9]+]]} -// CHECK1: [[META4]] = !{!"llvm.loop.mustprogress"} -// CHECK1: [[LOOP5]] = distinct !{[[LOOP5]], [[META4]]} -// CHECK1: [[LOOP6]] = distinct !{[[LOOP6]], [[META4]]} -// CHECK1: [[LOOP7]] = distinct !{[[LOOP7]], [[META4]]} -// CHECK1: [[LOOP8]] = distinct !{[[LOOP8]], [[META4]]} -// CHECK1: [[LOOP9]] = distinct !{[[LOOP9]], [[META4]]} -// CHECK1: [[LOOP10]] = distinct !{[[LOOP10]], [[META4]]} -// CHECK1: [[LOOP11]] = distinct !{[[LOOP11]], [[META4]]} -// CHECK1: [[LOOP12]] = distinct !{[[LOOP12]], [[META4]]} -// CHECK1: [[LOOP13]] = distinct !{[[LOOP13]], [[META4]]} -// CHECK1: [[LOOP14]] = distinct !{[[LOOP14]], [[META4]]} -// CHECK1: [[LOOP15]] = distinct !{[[LOOP15]], [[META4]]} -// CHECK1: [[LOOP16]] = distinct !{[[LOOP16]], [[META4]]} -// CHECK1: [[LOOP17]] = distinct !{[[LOOP17]], [[META4]]} -// CHECK1: [[LOOP18]] = distinct !{[[LOOP18]], [[META4]]} -// CHECK1: [[LOOP21]] = distinct !{[[LOOP21]], [[META4]]} -// CHECK1: [[LOOP22]] = distinct !{[[LOOP22]], [[META4]]} -// CHECK1: [[LOOP23]] = distinct !{[[LOOP23]], [[META4]]} -// CHECK1: [[LOOP24]] = distinct !{[[LOOP24]], [[META4]]} -// CHECK1: [[LOOP25]] = distinct !{[[LOOP25]], [[META4]]} -// CHECK1: [[LOOP26]] = distinct !{[[LOOP26]], [[META4]]} -// CHECK1: [[LOOP27]] = distinct !{[[LOOP27]], [[META4]]} -// CHECK1: [[LOOP28]] = distinct !{[[LOOP28]], [[META4]]} +// CHECK1: [[META2]] = !{} +// CHECK1: [[META3]] = !{i64 4} +// CHECK1: [[LOOP4]] = distinct !{[[LOOP4]], [[META5:![0-9]+]]} +// CHECK1: [[META5]] = !{!"llvm.loop.mustprogress"} +// CHECK1: [[LOOP6]] = distinct !{[[LOOP6]], [[META5]]} +// CHECK1: [[LOOP7]] = distinct !{[[LOOP7]], [[META5]]} +// CHECK1: [[LOOP8]] = distinct !{[[LOOP8]], [[META5]]} +// CHECK1: [[LOOP9]] = distinct !{[[LOOP9]], [[META5]]} +// CHECK1: [[LOOP10]] = distinct !{[[LOOP10]], [[META5]]} +// CHECK1: [[LOOP11]] = distinct !{[[LOOP11]], [[META5]]} +// CHECK1: [[LOOP12]] = distinct !{[[LOOP12]], [[META5]]} +// CHECK1: [[LOOP13]] = distinct !{[[LOOP13]], [[META5]]} +// CHECK1: [[LOOP14]] = distinct !{[[LOOP14]], [[META5]]} +// CHECK1: [[LOOP15]] = distinct !{[[LOOP15]], [[META5]]} +// CHECK1: [[LOOP16]] = distinct !{[[LOOP16]], [[META5]]} +// CHECK1: [[LOOP17]] = distinct !{[[LOOP17]], [[META5]]} +// CHECK1: [[LOOP18]] = distinct !{[[LOOP18]], [[META5]]} +// CHECK1: [[LOOP19]] = distinct !{[[LOOP19]], [[META5]]} +// CHECK1: [[LOOP20]] = distinct !{[[LOOP20]], [[META5]]} +// CHECK1: [[LOOP23]] = distinct !{[[LOOP23]], [[META5]]} +// CHECK1: [[LOOP24]] = distinct !{[[LOOP24]], [[META5]]} +// CHECK1: [[LOOP25]] = distinct !{[[LOOP25]], [[META5]]} +// CHECK1: [[LOOP26]] = distinct !{[[LOOP26]], [[META5]]} +// CHECK1: [[META27]] = !{i64 8} +// CHECK1: [[LOOP28]] = distinct !{[[LOOP28]], [[META5]]} +// CHECK1: [[LOOP29]] = distinct !{[[LOOP29]], [[META5]]} +// CHECK1: [[LOOP30]] = distinct !{[[LOOP30]], [[META5]]} +// CHECK1: [[LOOP31]] = distinct !{[[LOOP31]], [[META5]]} //. -// CHECK2: [[LOOP3]] = distinct !{[[LOOP3]], [[META4:![0-9]+]]} -// CHECK2: [[META4]] = !{!"llvm.loop.mustprogress"} -// CHECK2: [[LOOP5]] = distinct !{[[LOOP5]], [[META4]]} -// CHECK2: [[LOOP6]] = distinct !{[[LOOP6]], [[META4]]} -// CHECK2: [[LOOP7]] = distinct !{[[LOOP7]], [[META4]]} -// CHECK2: [[LOOP8]] = distinct !{[[LOOP8]], [[META4]]} -// CHECK2: [[LOOP9]] = distinct !{[[LOOP9]], [[META4]]} -// CHECK2: [[LOOP10]] = distinct !{[[LOOP10]], [[META4]]} -// CHECK2: [[LOOP11]] = distinct !{[[LOOP11]], [[META4]]} -// CHECK2: [[LOOP12]] = distinct !{[[LOOP12]], [[META4]]} -// CHECK2: [[LOOP13]] = distinct !{[[LOOP13]], [[META4]]} -// CHECK2: [[LOOP14]] = distinct !{[[LOOP14]], [[META4]]} -// CHECK2: [[LOOP15]] = distinct !{[[LOOP15]], [[META4]]} -// CHECK2: [[LOOP16]] = distinct !{[[LOOP16]], [[META4]]} -// CHECK2: [[LOOP17]] = distinct !{[[LOOP17]], [[META4]]} -// CHECK2: [[LOOP18]] = distinct !{[[LOOP18]], [[META4]]} -// CHECK2: [[LOOP19]] = distinct !{[[LOOP19]], [[META4]]} -// CHECK2: [[LOOP20]] = distinct !{[[LOOP20]], [[META4]]} -// CHECK2: [[LOOP23]] = distinct !{[[LOOP23]], [[META4]]} -// CHECK2: [[LOOP24]] = distinct !{[[LOOP24]], [[META4]]} -// CHECK2: [[LOOP25]] = distinct !{[[LOOP25]], [[META4]]} -// CHECK2: [[LOOP26]] = distinct !{[[LOOP26]], [[META4]]} -// CHECK2: [[LOOP27]] = distinct !{[[LOOP27]], [[META4]]} -// CHECK2: [[LOOP28]] = distinct !{[[LOOP28]], [[META4]]} +// CHECK2: [[META2]] = !{} +// CHECK2: [[META3]] = !{i64 4} +// CHECK2: [[LOOP4]] = distinct !{[[LOOP4]], [[META5:![0-9]+]]} +// CHECK2: [[META5]] = !{!"llvm.loop.mustprogress"} +// CHECK2: [[LOOP6]] = distinct !{[[LOOP6]], [[META5]]} +// CHECK2: [[LOOP7]] = distinct !{[[LOOP7]], [[META5]]} +// CHECK2: [[LOOP8]] = distinct !{[[LOOP8]], [[META5]]} +// CHECK2: [[META9]] = !{i64 8} +// CHECK2: [[LOOP10]] = distinct !{[[LOOP10]], [[META5]]} +// CHECK2: [[LOOP11]] = distinct !{[[LOOP11]], [[META5]]} +// CHECK2: [[LOOP12]] = distinct !{[[LOOP12]], [[META5]]} +// CHECK2: [[LOOP13]] = distinct !{[[LOOP13]], [[META5]]} +// CHECK2: [[LOOP14]] = distinct !{[[LOOP14]], [[META5]]} +// CHECK2: [[LOOP15]] = distinct !{[[LOOP15]], [[META5]]} +// CHECK2: [[LOOP16]] = distinct !{[[LOOP16]], [[META5]]} +// CHECK2: [[LOOP17]] = distinct !{[[LOOP17]], [[META5]]} +// CHECK2: [[LOOP18]] = distinct !{[[LOOP18]], [[META5]]} +// CHECK2: [[LOOP19]] = distinct !{[[LOOP19]], [[META5]]} +// CHECK2: [[LOOP20]] = distinct !{[[LOOP20]], [[META5]]} +// CHECK2: [[LOOP21]] = distinct !{[[LOOP21]], [[META5]]} +// CHECK2: [[LOOP22]] = distinct !{[[LOOP22]], [[META5]]} +// CHECK2: [[LOOP23]] = distinct !{[[LOOP23]], [[META5]]} +// CHECK2: [[LOOP26]] = distinct !{[[LOOP26]], [[META5]]} +// CHECK2: [[LOOP27]] = distinct !{[[LOOP27]], [[META5]]} +// CHECK2: [[LOOP28]] = distinct !{[[LOOP28]], [[META5]]} +// CHECK2: [[LOOP29]] = distinct !{[[LOOP29]], [[META5]]} +// CHECK2: [[LOOP30]] = distinct !{[[LOOP30]], [[META5]]} +// CHECK2: [[LOOP31]] = distinct !{[[LOOP31]], [[META5]]} //. diff --git a/clang/test/OpenMP/tile_codegen_for_dependent.cpp b/clang/test/OpenMP/tile_codegen_for_dependent.cpp index 820d33d15287b..aadc8e58bebfc 100644 --- a/clang/test/OpenMP/tile_codegen_for_dependent.cpp +++ b/clang/test/OpenMP/tile_codegen_for_dependent.cpp @@ -1,3 +1,4 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6 // Check code generation // RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fopenmp -emit-llvm %s -o - | FileCheck %s --check-prefix=IR @@ -17,172 +18,151 @@ extern "C" void body(...) {} -// IR-LABEL: define {{.*}}@func( -// IR-NEXT: [[ENTRY:.*]]: -// IR-NEXT: %[[START_ADDR:.+]] = alloca i32, align 4 -// IR-NEXT: %[[END_ADDR:.+]] = alloca i32, align 4 -// IR-NEXT: %[[STEP_ADDR:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTOMP_IV:.+]] = alloca i32, align 4 -// IR-NEXT: %[[TMP:.+]] = alloca i32, align 4 -// IR-NEXT: %[[I:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTCAPTURE_EXPR_:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTCAPTURE_EXPR_1:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTNEW_STEP:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTCAPTURE_EXPR_2:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTCAPTURE_EXPR_5:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTCAPTURE_EXPR_7:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTFLOOR_0_IV_I:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTOMP_LB:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTOMP_UB:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTOMP_STRIDE:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTOMP_IS_LAST:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTFLOOR_0_IV_I11:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTTILE_0_IV_I:.+]] = alloca i32, align 4 -// IR-NEXT: %[[TMP0:.+]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:.+]]) -// IR-NEXT: store i32 %[[START:.+]], ptr %[[START_ADDR]], align 4 -// IR-NEXT: store i32 %[[END:.+]], ptr %[[END_ADDR]], align 4 -// IR-NEXT: store i32 %[[STEP:.+]], ptr %[[STEP_ADDR]], align 4 -// IR-NEXT: %[[TMP1:.+]] = load i32, ptr %[[START_ADDR]], align 4 -// IR-NEXT: store i32 %[[TMP1]], ptr %[[I]], align 4 -// IR-NEXT: %[[TMP2:.+]] = load i32, ptr %[[START_ADDR]], align 4 -// IR-NEXT: store i32 %[[TMP2]], ptr %[[DOTCAPTURE_EXPR_]], align 4 -// IR-NEXT: %[[TMP3:.+]] = load i32, ptr %[[END_ADDR]], align 4 -// IR-NEXT: store i32 %[[TMP3]], ptr %[[DOTCAPTURE_EXPR_1]], align 4 -// IR-NEXT: %[[TMP4:.+]] = load i32, ptr %[[STEP_ADDR]], align 4 -// IR-NEXT: store i32 %[[TMP4]], ptr %[[DOTNEW_STEP]], align 4 -// IR-NEXT: %[[TMP5:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_1]], align 4 -// IR-NEXT: %[[TMP6:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_]], align 4 -// IR-NEXT: %[[SUB:.+]] = sub i32 %[[TMP5]], %[[TMP6]] -// IR-NEXT: %[[SUB3:.+]] = sub i32 %[[SUB]], 1 -// IR-NEXT: %[[TMP7:.+]] = load i32, ptr %[[DOTNEW_STEP]], align 4 -// IR-NEXT: %[[ADD:.+]] = add i32 %[[SUB3]], %[[TMP7]] -// IR-NEXT: %[[TMP8:.+]] = load i32, ptr %[[DOTNEW_STEP]], align 4 -// IR-NEXT: %[[DIV:.+]] = udiv i32 %[[ADD]], %[[TMP8]] -// IR-NEXT: %[[SUB4:.+]] = sub i32 %[[DIV]], 1 -// IR-NEXT: store i32 %[[SUB4]], ptr %[[DOTCAPTURE_EXPR_2]], align 4 -// IR-NEXT: %[[TMP9:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_2]], align 4 -// IR-NEXT: %[[ADD6:.+]] = add i32 %[[TMP9]], 1 -// IR-NEXT: store i32 %[[ADD6]], ptr %[[DOTCAPTURE_EXPR_5]], align 4 -// IR-NEXT: %[[TMP10:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_5]], align 4 -// IR-NEXT: %[[SUB8:.+]] = sub i32 %[[TMP10]], -3 -// IR-NEXT: %[[DIV9:.+]] = udiv i32 %[[SUB8]], 4 -// IR-NEXT: %[[SUB10:.+]] = sub i32 %[[DIV9]], 1 -// IR-NEXT: store i32 %[[SUB10]], ptr %[[DOTCAPTURE_EXPR_7]], align 4 -// IR-NEXT: store i32 0, ptr %[[DOTFLOOR_0_IV_I]], align 4 -// IR-NEXT: %[[TMP11:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_5]], align 4 -// IR-NEXT: %[[CMP:.+]] = icmp ult i32 0, %[[TMP11]] -// IR-NEXT: br i1 %[[CMP]], label %[[OMP_PRECOND_THEN:.+]], label %[[OMP_PRECOND_END:.+]] -// IR-EMPTY: -// IR-NEXT: [[OMP_PRECOND_THEN]]: -// IR-NEXT: store i32 0, ptr %[[DOTOMP_LB]], align 4 -// IR-NEXT: %[[TMP12:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_7]], align 4 -// IR-NEXT: store i32 %[[TMP12]], ptr %[[DOTOMP_UB]], align 4 -// IR-NEXT: store i32 1, ptr %[[DOTOMP_STRIDE]], align 4 -// IR-NEXT: store i32 0, ptr %[[DOTOMP_IS_LAST]], align 4 -// IR-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1:.+]], i32 %[[TMP0]], i32 34, ptr %[[DOTOMP_IS_LAST]], ptr %[[DOTOMP_LB]], ptr %[[DOTOMP_UB]], ptr %[[DOTOMP_STRIDE]], i32 1, i32 1) -// IR-NEXT: %[[TMP13:.+]] = load i32, ptr %[[DOTOMP_UB]], align 4 -// IR-NEXT: %[[TMP14:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_7]], align 4 -// IR-NEXT: %[[CMP12:.+]] = icmp ugt i32 %[[TMP13]], %[[TMP14]] -// IR-NEXT: br i1 %[[CMP12]], label %[[COND_TRUE:.+]], label %[[COND_FALSE:.+]] -// IR-EMPTY: -// IR-NEXT: [[COND_TRUE]]: -// IR-NEXT: %[[TMP15:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_7]], align 4 -// IR-NEXT: br label %[[COND_END:.+]] -// IR-EMPTY: -// IR-NEXT: [[COND_FALSE]]: -// IR-NEXT: %[[TMP16:.+]] = load i32, ptr %[[DOTOMP_UB]], align 4 +// IR-LABEL: define dso_local void @func( +// IR-SAME: i32 noundef [[START:%.*]], i32 noundef [[END:%.*]], i32 noundef [[STEP:%.*]]) #[[ATTR0:[0-9]+]] { +// IR-NEXT: [[ENTRY:.*:]] +// IR-NEXT: [[START_ADDR:%.*]] = alloca i32, align 4 +// IR-NEXT: [[END_ADDR:%.*]] = alloca i32, align 4 +// IR-NEXT: [[STEP_ADDR:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// IR-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// IR-NEXT: [[I:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTNEW_STEP:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTCAPTURE_EXPR_7:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTFLOOR_0_IV_I11:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTTILE_CNT_0_IV_I:%.*]] = alloca i32, align 4 +// IR-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) +// IR-NEXT: store i32 [[START]], ptr [[START_ADDR]], align 4 +// IR-NEXT: store i32 [[END]], ptr [[END_ADDR]], align 4 +// IR-NEXT: store i32 [[STEP]], ptr [[STEP_ADDR]], align 4 +// IR-NEXT: [[TMP1:%.*]] = load i32, ptr [[START_ADDR]], align 4 +// IR-NEXT: store i32 [[TMP1]], ptr [[I]], align 4 +// IR-NEXT: [[TMP2:%.*]] = load i32, ptr [[START_ADDR]], align 4 +// IR-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-NEXT: [[TMP3:%.*]] = load i32, ptr [[END_ADDR]], align 4 +// IR-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_1]], align 4 +// IR-NEXT: [[TMP4:%.*]] = load i32, ptr [[STEP_ADDR]], align 4 +// IR-NEXT: store i32 [[TMP4]], ptr [[DOTNEW_STEP]], align 4 +// IR-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// IR-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-NEXT: [[SUB:%.*]] = sub i32 [[TMP5]], [[TMP6]] +// IR-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 +// IR-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 +// IR-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], [[TMP7]] +// IR-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 +// IR-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP8]] +// IR-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 +// IR-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4 +// IR-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 +// IR-NEXT: [[ADD6:%.*]] = add i32 [[TMP9]], 1 +// IR-NEXT: store i32 [[ADD6]], ptr [[DOTCAPTURE_EXPR_5]], align 4 +// IR-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// IR-NEXT: [[SUB8:%.*]] = sub i32 [[TMP10]], -3 +// IR-NEXT: [[DIV9:%.*]] = udiv i32 [[SUB8]], 4 +// IR-NEXT: [[SUB10:%.*]] = sub i32 [[DIV9]], 1 +// IR-NEXT: store i32 [[SUB10]], ptr [[DOTCAPTURE_EXPR_7]], align 4 +// IR-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// IR-NEXT: [[CMP:%.*]] = icmp ult i32 0, [[TMP11]] +// IR-NEXT: br i1 [[CMP]], label %[[OMP_PRECOND_THEN:.*]], label %[[OMP_PRECOND_END:.*]] +// IR: [[OMP_PRECOND_THEN]]: +// IR-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 +// IR-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_7]], align 4 +// IR-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_UB]], align 4 +// IR-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 +// IR-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// IR-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// IR-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// IR-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_7]], align 4 +// IR-NEXT: [[CMP12:%.*]] = icmp ugt i32 [[TMP13]], [[TMP14]] +// IR-NEXT: br i1 [[CMP12]], label %[[COND_TRUE:.*]], label %[[COND_FALSE:.*]] +// IR: [[COND_TRUE]]: +// IR-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_7]], align 4 +// IR-NEXT: br label %[[COND_END:.*]] +// IR: [[COND_FALSE]]: +// IR-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // IR-NEXT: br label %[[COND_END]] -// IR-EMPTY: -// IR-NEXT: [[COND_END]]: -// IR-NEXT: %[[COND:.+]] = phi i32 [ %[[TMP15]], %[[COND_TRUE]] ], [ %[[TMP16]], %[[COND_FALSE]] ] -// IR-NEXT: store i32 %[[COND]], ptr %[[DOTOMP_UB]], align 4 -// IR-NEXT: %[[TMP17:.+]] = load i32, ptr %[[DOTOMP_LB]], align 4 -// IR-NEXT: store i32 %[[TMP17]], ptr %[[DOTOMP_IV]], align 4 -// IR-NEXT: br label %[[OMP_INNER_FOR_COND:.+]] -// IR-EMPTY: -// IR-NEXT: [[OMP_INNER_FOR_COND]]: -// IR-NEXT: %[[TMP18:.+]] = load i32, ptr %[[DOTOMP_IV]], align 4 -// IR-NEXT: %[[TMP19:.+]] = load i32, ptr %[[DOTOMP_UB]], align 4 -// IR-NEXT: %[[ADD13:.+]] = add i32 %[[TMP19]], 1 -// IR-NEXT: %[[CMP14:.+]] = icmp ult i32 %[[TMP18]], %[[ADD13]] -// IR-NEXT: br i1 %[[CMP14]], label %[[OMP_INNER_FOR_BODY:.+]], label %[[OMP_INNER_FOR_END:.+]] -// IR-EMPTY: -// IR-NEXT: [[OMP_INNER_FOR_BODY]]: -// IR-NEXT: %[[TMP20:.+]] = load i32, ptr %[[DOTOMP_IV]], align 4 -// IR-NEXT: %[[MUL:.+]] = mul i32 %[[TMP20]], 4 -// IR-NEXT: %[[ADD15:.+]] = add i32 0, %[[MUL]] -// IR-NEXT: store i32 %[[ADD15]], ptr %[[DOTFLOOR_0_IV_I11]], align 4 -// IR-NEXT: %[[TMP21:.+]] = load i32, ptr %[[DOTFLOOR_0_IV_I11]], align 4 -// IR-NEXT: store i32 %[[TMP21]], ptr %[[DOTTILE_0_IV_I]], align 4 -// IR-NEXT: br label %[[FOR_COND:.+]] -// IR-EMPTY: -// IR-NEXT: [[FOR_COND]]: -// IR-NEXT: %[[TMP22:.+]] = load i32, ptr %[[DOTTILE_0_IV_I]], align 4 -// IR-NEXT: %[[TMP23:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_2]], align 4 -// IR-NEXT: %[[ADD16:.+]] = add i32 %[[TMP23]], 1 -// IR-NEXT: %[[TMP24:.+]] = load i32, ptr %[[DOTFLOOR_0_IV_I11]], align 4 -// IR-NEXT: %[[ADD17:.+]] = add i32 %[[TMP24]], 4 -// IR-NEXT: %[[CMP18:.+]] = icmp ult i32 %[[ADD16]], %[[ADD17]] -// IR-NEXT: br i1 %[[CMP18]], label %[[COND_TRUE19:.+]], label %[[COND_FALSE21:.+]] -// IR-EMPTY: -// IR-NEXT: [[COND_TRUE19]]: -// IR-NEXT: %[[TMP25:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_2]], align 4 -// IR-NEXT: %[[ADD20:.+]] = add i32 %[[TMP25]], 1 -// IR-NEXT: br label %[[COND_END23:.+]] -// IR-EMPTY: -// IR-NEXT: [[COND_FALSE21]]: -// IR-NEXT: %[[TMP26:.+]] = load i32, ptr %[[DOTFLOOR_0_IV_I11]], align 4 -// IR-NEXT: %[[ADD22:.+]] = add i32 %[[TMP26]], 4 -// IR-NEXT: br label %[[COND_END23]] -// IR-EMPTY: -// IR-NEXT: [[COND_END23]]: -// IR-NEXT: %[[COND24:.+]] = phi i32 [ %[[ADD20]], %[[COND_TRUE19]] ], [ %[[ADD22]], %[[COND_FALSE21]] ] -// IR-NEXT: %[[CMP25:.+]] = icmp ult i32 %[[TMP22]], %[[COND24]] -// IR-NEXT: br i1 %[[CMP25]], label %[[FOR_BODY:.+]], label %[[FOR_END:.+]] -// IR-EMPTY: -// IR-NEXT: [[FOR_BODY]]: -// IR-NEXT: %[[TMP27:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_]], align 4 -// IR-NEXT: %[[TMP28:.+]] = load i32, ptr %[[DOTTILE_0_IV_I]], align 4 -// IR-NEXT: %[[TMP29:.+]] = load i32, ptr %[[DOTNEW_STEP]], align 4 -// IR-NEXT: %[[MUL26:.+]] = mul i32 %[[TMP28]], %[[TMP29]] -// IR-NEXT: %[[ADD27:.+]] = add i32 %[[TMP27]], %[[MUL26]] -// IR-NEXT: store i32 %[[ADD27]], ptr %[[I]], align 4 -// IR-NEXT: %[[TMP30:.+]] = load i32, ptr %[[START_ADDR]], align 4 -// IR-NEXT: %[[TMP31:.+]] = load i32, ptr %[[END_ADDR]], align 4 -// IR-NEXT: %[[TMP32:.+]] = load i32, ptr %[[STEP_ADDR]], align 4 -// IR-NEXT: %[[TMP33:.+]] = load i32, ptr %[[I]], align 4 -// IR-NEXT: call void (...) @body(i32 noundef %[[TMP30]], i32 noundef %[[TMP31]], i32 noundef %[[TMP32]], i32 noundef %[[TMP33]]) -// IR-NEXT: br label %[[FOR_INC:.+]] -// IR-EMPTY: -// IR-NEXT: [[FOR_INC]]: -// IR-NEXT: %[[TMP34:.+]] = load i32, ptr %[[DOTTILE_0_IV_I]], align 4 -// IR-NEXT: %[[INC:.+]] = add i32 %[[TMP34]], 1 -// IR-NEXT: store i32 %[[INC]], ptr %[[DOTTILE_0_IV_I]], align 4 -// IR-NEXT: br label %[[FOR_COND]], !llvm.loop ![[LOOP3:[0-9]+]] -// IR-EMPTY: -// IR-NEXT: [[FOR_END]]: -// IR-NEXT: br label %[[OMP_BODY_CONTINUE:.+]] -// IR-EMPTY: -// IR-NEXT: [[OMP_BODY_CONTINUE]]: -// IR-NEXT: br label %[[OMP_INNER_FOR_INC:.+]] -// IR-EMPTY: -// IR-NEXT: [[OMP_INNER_FOR_INC]]: -// IR-NEXT: %[[TMP35:.+]] = load i32, ptr %[[DOTOMP_IV]], align 4 -// IR-NEXT: %[[ADD28:.+]] = add i32 %[[TMP35]], 1 -// IR-NEXT: store i32 %[[ADD28]], ptr %[[DOTOMP_IV]], align 4 +// IR: [[COND_END]]: +// IR-NEXT: [[COND:%.*]] = phi i32 [ [[TMP15]], %[[COND_TRUE]] ], [ [[TMP16]], %[[COND_FALSE]] ] +// IR-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 +// IR-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 +// IR-NEXT: store i32 [[TMP17]], ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: br label %[[OMP_INNER_FOR_COND:.*]] +// IR: [[OMP_INNER_FOR_COND]]: +// IR-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// IR-NEXT: [[ADD13:%.*]] = add i32 [[TMP19]], 1 +// IR-NEXT: [[CMP14:%.*]] = icmp ult i32 [[TMP18]], [[ADD13]] +// IR-NEXT: br i1 [[CMP14]], label %[[OMP_INNER_FOR_BODY:.*]], label %[[OMP_INNER_FOR_END:.*]] +// IR: [[OMP_INNER_FOR_BODY]]: +// IR-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: [[MUL:%.*]] = mul i32 [[TMP20]], 4 +// IR-NEXT: [[ADD15:%.*]] = add i32 0, [[MUL]] +// IR-NEXT: store i32 [[ADD15]], ptr [[DOTFLOOR_0_IV_I11]], align 4 +// IR-NEXT: store i32 0, ptr [[DOTTILE_CNT_0_IV_I]], align 4 +// IR-NEXT: br label %[[FOR_COND:.*]] +// IR: [[FOR_COND]]: +// IR-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTTILE_CNT_0_IV_I]], align 4 +// IR-NEXT: [[CMP16:%.*]] = icmp ult i32 [[TMP21]], 4 +// IR-NEXT: br i1 [[CMP16]], label %[[FOR_BODY:.*]], label %[[FOR_END:.*]] +// IR: [[FOR_BODY]]: +// IR-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I11]], align 4 +// IR-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTTILE_CNT_0_IV_I]], align 4 +// IR-NEXT: [[ADD17:%.*]] = add i32 [[TMP22]], [[TMP23]] +// IR-NEXT: store i32 [[ADD17]], ptr [[DOTTILE_0_IV_I]], align 4 +// IR-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 +// IR-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 +// IR-NEXT: [[MUL18:%.*]] = mul i32 [[TMP25]], [[TMP26]] +// IR-NEXT: [[ADD19:%.*]] = add i32 [[TMP24]], [[MUL18]] +// IR-NEXT: store i32 [[ADD19]], ptr [[I]], align 4 +// IR-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 +// IR-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 +// IR-NEXT: [[ADD20:%.*]] = add i32 [[TMP28]], 1 +// IR-NEXT: [[CMP21:%.*]] = icmp ult i32 [[TMP27]], [[ADD20]] +// IR-NEXT: br i1 [[CMP21]], label %[[IF_THEN:.*]], label %[[IF_END:.*]] +// IR: [[IF_THEN]]: +// IR-NEXT: [[TMP29:%.*]] = load i32, ptr [[START_ADDR]], align 4 +// IR-NEXT: [[TMP30:%.*]] = load i32, ptr [[END_ADDR]], align 4 +// IR-NEXT: [[TMP31:%.*]] = load i32, ptr [[STEP_ADDR]], align 4 +// IR-NEXT: [[TMP32:%.*]] = load i32, ptr [[I]], align 4 +// IR-NEXT: call void (...) @body(i32 noundef [[TMP29]], i32 noundef [[TMP30]], i32 noundef [[TMP31]], i32 noundef [[TMP32]]) +// IR-NEXT: br label %[[IF_END]] +// IR: [[IF_END]]: +// IR-NEXT: br label %[[FOR_INC:.*]] +// IR: [[FOR_INC]]: +// IR-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTTILE_CNT_0_IV_I]], align 4 +// IR-NEXT: [[INC:%.*]] = add i32 [[TMP33]], 1 +// IR-NEXT: store i32 [[INC]], ptr [[DOTTILE_CNT_0_IV_I]], align 4 +// IR-NEXT: br label %[[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] +// IR: [[FOR_END]]: +// IR-NEXT: br label %[[OMP_BODY_CONTINUE:.*]] +// IR: [[OMP_BODY_CONTINUE]]: +// IR-NEXT: br label %[[OMP_INNER_FOR_INC:.*]] +// IR: [[OMP_INNER_FOR_INC]]: +// IR-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: [[ADD22:%.*]] = add i32 [[TMP34]], 1 +// IR-NEXT: store i32 [[ADD22]], ptr [[DOTOMP_IV]], align 4 // IR-NEXT: br label %[[OMP_INNER_FOR_COND]] -// IR-EMPTY: -// IR-NEXT: [[OMP_INNER_FOR_END]]: -// IR-NEXT: br label %[[OMP_LOOP_EXIT:.+]] -// IR-EMPTY: -// IR-NEXT: [[OMP_LOOP_EXIT]]: -// IR-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 %[[TMP0]]) +// IR: [[OMP_INNER_FOR_END]]: +// IR-NEXT: br label %[[OMP_LOOP_EXIT:.*]] +// IR: [[OMP_LOOP_EXIT]]: +// IR-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]]) // IR-NEXT: br label %[[OMP_PRECOND_END]] -// IR-EMPTY: -// IR-NEXT: [[OMP_PRECOND_END]]: -// IR-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:.+]], i32 %[[TMP0]]) +// IR: [[OMP_PRECOND_END]]: +// IR-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP0]]) // IR-NEXT: ret void -// IR-NEXT: } +// extern "C" void func(int start, int end, int step) { #pragma omp for #pragma omp tile sizes(4) @@ -191,3 +171,7 @@ extern "C" void func(int start, int end, int step) { } #endif /* HEADER */ +//. +// IR: [[LOOP2]] = distinct !{[[LOOP2]], [[META3:![0-9]+]]} +// IR: [[META3]] = !{!"llvm.loop.mustprogress"} +//. diff --git a/clang/test/OpenMP/tile_codegen_tile_for.cpp b/clang/test/OpenMP/tile_codegen_tile_for.cpp index 8a844c78c54a6..8153f76b7e1a9 100644 --- a/clang/test/OpenMP/tile_codegen_tile_for.cpp +++ b/clang/test/OpenMP/tile_codegen_tile_for.cpp @@ -1,3 +1,4 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6 // Check code generation // RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fopenmp -emit-llvm %s -o - | FileCheck %s --check-prefix=IR @@ -16,229 +17,197 @@ extern "C" void body(...) {} -// IR-LABEL: define {{.*}}@func( -// IR-NEXT: [[ENTRY:.*]]: -// IR-NEXT: %[[START_ADDR:.+]] = alloca i32, align 4 -// IR-NEXT: %[[END_ADDR:.+]] = alloca i32, align 4 -// IR-NEXT: %[[STEP_ADDR:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTOMP_IV:.+]] = alloca i32, align 4 -// IR-NEXT: %[[TMP:.+]] = alloca i32, align 4 -// IR-NEXT: %[[I:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTCAPTURE_EXPR_:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTCAPTURE_EXPR_1:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTNEW_STEP:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTCAPTURE_EXPR_2:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTFLOOR_0_IV_I:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTCAPTURE_EXPR_5:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTCAPTURE_EXPR_7:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTCAPTURE_EXPR_11:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTCAPTURE_EXPR_13:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTFLOOR_0_IV__FLOOR_0_IV_I:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTOMP_LB:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTOMP_UB:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTOMP_STRIDE:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTOMP_IS_LAST:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTFLOOR_0_IV__FLOOR_0_IV_I17:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTTILE_0_IV__FLOOR_0_IV_I:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTTILE_0_IV_I:.+]] = alloca i32, align 4 -// IR-NEXT: %[[TMP0:.+]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:.+]]) -// IR-NEXT: store i32 %[[START:.+]], ptr %[[START_ADDR]], align 4 -// IR-NEXT: store i32 %[[END:.+]], ptr %[[END_ADDR]], align 4 -// IR-NEXT: store i32 %[[STEP:.+]], ptr %[[STEP_ADDR]], align 4 -// IR-NEXT: %[[TMP1:.+]] = load i32, ptr %[[START_ADDR]], align 4 -// IR-NEXT: store i32 %[[TMP1]], ptr %[[I]], align 4 -// IR-NEXT: %[[TMP2:.+]] = load i32, ptr %[[START_ADDR]], align 4 -// IR-NEXT: store i32 %[[TMP2]], ptr %[[DOTCAPTURE_EXPR_]], align 4 -// IR-NEXT: %[[TMP3:.+]] = load i32, ptr %[[END_ADDR]], align 4 -// IR-NEXT: store i32 %[[TMP3]], ptr %[[DOTCAPTURE_EXPR_1]], align 4 -// IR-NEXT: %[[TMP4:.+]] = load i32, ptr %[[STEP_ADDR]], align 4 -// IR-NEXT: store i32 %[[TMP4]], ptr %[[DOTNEW_STEP]], align 4 -// IR-NEXT: %[[TMP5:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_1]], align 4 -// IR-NEXT: %[[TMP6:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_]], align 4 -// IR-NEXT: %[[SUB:.+]] = sub i32 %[[TMP5]], %[[TMP6]] -// IR-NEXT: %[[SUB3:.+]] = sub i32 %[[SUB]], 1 -// IR-NEXT: %[[TMP7:.+]] = load i32, ptr %[[DOTNEW_STEP]], align 4 -// IR-NEXT: %[[ADD:.+]] = add i32 %[[SUB3]], %[[TMP7]] -// IR-NEXT: %[[TMP8:.+]] = load i32, ptr %[[DOTNEW_STEP]], align 4 -// IR-NEXT: %[[DIV:.+]] = udiv i32 %[[ADD]], %[[TMP8]] -// IR-NEXT: %[[SUB4:.+]] = sub i32 %[[DIV]], 1 -// IR-NEXT: store i32 %[[SUB4]], ptr %[[DOTCAPTURE_EXPR_2]], align 4 -// IR-NEXT: store i32 0, ptr %[[DOTFLOOR_0_IV_I]], align 4 -// IR-NEXT: %[[TMP9:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_2]], align 4 -// IR-NEXT: %[[ADD6:.+]] = add i32 %[[TMP9]], 1 -// IR-NEXT: store i32 %[[ADD6]], ptr %[[DOTCAPTURE_EXPR_5]], align 4 -// IR-NEXT: %[[TMP10:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_5]], align 4 -// IR-NEXT: %[[SUB8:.+]] = sub i32 %[[TMP10]], -3 -// IR-NEXT: %[[DIV9:.+]] = udiv i32 %[[SUB8]], 4 -// IR-NEXT: %[[SUB10:.+]] = sub i32 %[[DIV9]], 1 -// IR-NEXT: store i32 %[[SUB10]], ptr %[[DOTCAPTURE_EXPR_7]], align 4 -// IR-NEXT: %[[TMP11:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_7]], align 4 -// IR-NEXT: %[[ADD12:.+]] = add i32 %[[TMP11]], 1 -// IR-NEXT: store i32 %[[ADD12]], ptr %[[DOTCAPTURE_EXPR_11]], align 4 -// IR-NEXT: %[[TMP12:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_11]], align 4 -// IR-NEXT: %[[SUB14:.+]] = sub i32 %[[TMP12]], -2 -// IR-NEXT: %[[DIV15:.+]] = udiv i32 %[[SUB14]], 3 -// IR-NEXT: %[[SUB16:.+]] = sub i32 %[[DIV15]], 1 -// IR-NEXT: store i32 %[[SUB16]], ptr %[[DOTCAPTURE_EXPR_13]], align 4 -// IR-NEXT: store i32 0, ptr %[[DOTFLOOR_0_IV__FLOOR_0_IV_I]], align 4 -// IR-NEXT: %[[TMP13:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_11]], align 4 -// IR-NEXT: %[[CMP:.+]] = icmp ult i32 0, %[[TMP13]] -// IR-NEXT: br i1 %[[CMP]], label %[[OMP_PRECOND_THEN:.+]], label %[[OMP_PRECOND_END:.+]] -// IR-EMPTY: -// IR-NEXT: [[OMP_PRECOND_THEN]]: -// IR-NEXT: store i32 0, ptr %[[DOTOMP_LB]], align 4 -// IR-NEXT: %[[TMP14:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_13]], align 4 -// IR-NEXT: store i32 %[[TMP14]], ptr %[[DOTOMP_UB]], align 4 -// IR-NEXT: store i32 1, ptr %[[DOTOMP_STRIDE]], align 4 -// IR-NEXT: store i32 0, ptr %[[DOTOMP_IS_LAST]], align 4 -// IR-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1:.+]], i32 %[[TMP0]], i32 34, ptr %[[DOTOMP_IS_LAST]], ptr %[[DOTOMP_LB]], ptr %[[DOTOMP_UB]], ptr %[[DOTOMP_STRIDE]], i32 1, i32 1) -// IR-NEXT: %[[TMP15:.+]] = load i32, ptr %[[DOTOMP_UB]], align 4 -// IR-NEXT: %[[TMP16:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_13]], align 4 -// IR-NEXT: %[[CMP18:.+]] = icmp ugt i32 %[[TMP15]], %[[TMP16]] -// IR-NEXT: br i1 %[[CMP18]], label %[[COND_TRUE:.+]], label %[[COND_FALSE:.+]] -// IR-EMPTY: -// IR-NEXT: [[COND_TRUE]]: -// IR-NEXT: %[[TMP17:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_13]], align 4 -// IR-NEXT: br label %[[COND_END:.+]] -// IR-EMPTY: -// IR-NEXT: [[COND_FALSE]]: -// IR-NEXT: %[[TMP18:.+]] = load i32, ptr %[[DOTOMP_UB]], align 4 + + +// IR-LABEL: define dso_local void @func( +// IR-SAME: i32 noundef [[START:%.*]], i32 noundef [[END:%.*]], i32 noundef [[STEP:%.*]]) #[[ATTR0:[0-9]+]] { +// IR-NEXT: [[ENTRY:.*:]] +// IR-NEXT: [[START_ADDR:%.*]] = alloca i32, align 4 +// IR-NEXT: [[END_ADDR:%.*]] = alloca i32, align 4 +// IR-NEXT: [[STEP_ADDR:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// IR-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// IR-NEXT: [[I:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTNEW_STEP:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTCAPTURE_EXPR_7:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTTILE_0_IV__FLOOR_0_IV_I:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTCAPTURE_EXPR_13:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTFLOOR_0_IV__FLOOR_0_IV_I:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTFLOOR_0_IV__FLOOR_0_IV_I17:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTTILE_CNT_0_IV__FLOOR_0_IV_I:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTTILE_CNT_0_IV_I:%.*]] = alloca i32, align 4 +// IR-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) +// IR-NEXT: store i32 [[START]], ptr [[START_ADDR]], align 4 +// IR-NEXT: store i32 [[END]], ptr [[END_ADDR]], align 4 +// IR-NEXT: store i32 [[STEP]], ptr [[STEP_ADDR]], align 4 +// IR-NEXT: [[TMP1:%.*]] = load i32, ptr [[START_ADDR]], align 4 +// IR-NEXT: store i32 [[TMP1]], ptr [[I]], align 4 +// IR-NEXT: [[TMP2:%.*]] = load i32, ptr [[START_ADDR]], align 4 +// IR-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-NEXT: [[TMP3:%.*]] = load i32, ptr [[END_ADDR]], align 4 +// IR-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_1]], align 4 +// IR-NEXT: [[TMP4:%.*]] = load i32, ptr [[STEP_ADDR]], align 4 +// IR-NEXT: store i32 [[TMP4]], ptr [[DOTNEW_STEP]], align 4 +// IR-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// IR-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-NEXT: [[SUB:%.*]] = sub i32 [[TMP5]], [[TMP6]] +// IR-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 +// IR-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 +// IR-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], [[TMP7]] +// IR-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 +// IR-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP8]] +// IR-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 +// IR-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4 +// IR-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 +// IR-NEXT: [[ADD6:%.*]] = add i32 [[TMP9]], 1 +// IR-NEXT: store i32 [[ADD6]], ptr [[DOTCAPTURE_EXPR_5]], align 4 +// IR-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// IR-NEXT: [[SUB8:%.*]] = sub i32 [[TMP10]], -3 +// IR-NEXT: [[DIV9:%.*]] = udiv i32 [[SUB8]], 4 +// IR-NEXT: [[SUB10:%.*]] = sub i32 [[DIV9]], 1 +// IR-NEXT: store i32 [[SUB10]], ptr [[DOTCAPTURE_EXPR_7]], align 4 +// IR-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_7]], align 4 +// IR-NEXT: [[ADD12:%.*]] = add i32 [[TMP11]], 1 +// IR-NEXT: store i32 [[ADD12]], ptr [[DOTCAPTURE_EXPR_11]], align 4 +// IR-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4 +// IR-NEXT: [[SUB14:%.*]] = sub i32 [[TMP12]], -2 +// IR-NEXT: [[DIV15:%.*]] = udiv i32 [[SUB14]], 3 +// IR-NEXT: [[SUB16:%.*]] = sub i32 [[DIV15]], 1 +// IR-NEXT: store i32 [[SUB16]], ptr [[DOTCAPTURE_EXPR_13]], align 4 +// IR-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV__FLOOR_0_IV_I]], align 4 +// IR-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4 +// IR-NEXT: [[CMP:%.*]] = icmp ult i32 0, [[TMP13]] +// IR-NEXT: br i1 [[CMP]], label %[[OMP_PRECOND_THEN:.*]], label %[[OMP_PRECOND_END:.*]] +// IR: [[OMP_PRECOND_THEN]]: +// IR-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 +// IR-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_13]], align 4 +// IR-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_UB]], align 4 +// IR-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 +// IR-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// IR-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// IR-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// IR-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_13]], align 4 +// IR-NEXT: [[CMP18:%.*]] = icmp ugt i32 [[TMP15]], [[TMP16]] +// IR-NEXT: br i1 [[CMP18]], label %[[COND_TRUE:.*]], label %[[COND_FALSE:.*]] +// IR: [[COND_TRUE]]: +// IR-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_13]], align 4 +// IR-NEXT: br label %[[COND_END:.*]] +// IR: [[COND_FALSE]]: +// IR-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // IR-NEXT: br label %[[COND_END]] -// IR-EMPTY: -// IR-NEXT: [[COND_END]]: -// IR-NEXT: %[[COND:.+]] = phi i32 [ %[[TMP17]], %[[COND_TRUE]] ], [ %[[TMP18]], %[[COND_FALSE]] ] -// IR-NEXT: store i32 %[[COND]], ptr %[[DOTOMP_UB]], align 4 -// IR-NEXT: %[[TMP19:.+]] = load i32, ptr %[[DOTOMP_LB]], align 4 -// IR-NEXT: store i32 %[[TMP19]], ptr %[[DOTOMP_IV]], align 4 -// IR-NEXT: br label %[[OMP_INNER_FOR_COND:.+]] -// IR-EMPTY: -// IR-NEXT: [[OMP_INNER_FOR_COND]]: -// IR-NEXT: %[[TMP20:.+]] = load i32, ptr %[[DOTOMP_IV]], align 4 -// IR-NEXT: %[[TMP21:.+]] = load i32, ptr %[[DOTOMP_UB]], align 4 -// IR-NEXT: %[[ADD19:.+]] = add i32 %[[TMP21]], 1 -// IR-NEXT: %[[CMP20:.+]] = icmp ult i32 %[[TMP20]], %[[ADD19]] -// IR-NEXT: br i1 %[[CMP20]], label %[[OMP_INNER_FOR_BODY:.+]], label %[[OMP_INNER_FOR_END:.+]] -// IR-EMPTY: -// IR-NEXT: [[OMP_INNER_FOR_BODY]]: -// IR-NEXT: %[[TMP22:.+]] = load i32, ptr %[[DOTOMP_IV]], align 4 -// IR-NEXT: %[[MUL:.+]] = mul i32 %[[TMP22]], 3 -// IR-NEXT: %[[ADD21:.+]] = add i32 0, %[[MUL]] -// IR-NEXT: store i32 %[[ADD21]], ptr %[[DOTFLOOR_0_IV__FLOOR_0_IV_I17]], align 4 -// IR-NEXT: %[[TMP23:.+]] = load i32, ptr %[[DOTFLOOR_0_IV__FLOOR_0_IV_I17]], align 4 -// IR-NEXT: store i32 %[[TMP23]], ptr %[[DOTTILE_0_IV__FLOOR_0_IV_I]], align 4 -// IR-NEXT: br label %[[FOR_COND:.+]] -// IR-EMPTY: -// IR-NEXT: [[FOR_COND]]: -// IR-NEXT: %[[TMP24:.+]] = load i32, ptr %[[DOTTILE_0_IV__FLOOR_0_IV_I]], align 4 -// IR-NEXT: %[[TMP25:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_7]], align 4 -// IR-NEXT: %[[ADD22:.+]] = add i32 %[[TMP25]], 1 -// IR-NEXT: %[[TMP26:.+]] = load i32, ptr %[[DOTFLOOR_0_IV__FLOOR_0_IV_I17]], align 4 -// IR-NEXT: %[[ADD23:.+]] = add i32 %[[TMP26]], 3 -// IR-NEXT: %[[CMP24:.+]] = icmp ult i32 %[[ADD22]], %[[ADD23]] -// IR-NEXT: br i1 %[[CMP24]], label %[[COND_TRUE25:.+]], label %[[COND_FALSE27:.+]] -// IR-EMPTY: -// IR-NEXT: [[COND_TRUE25]]: -// IR-NEXT: %[[TMP27:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_7]], align 4 -// IR-NEXT: %[[ADD26:.+]] = add i32 %[[TMP27]], 1 -// IR-NEXT: br label %[[COND_END29:.+]] -// IR-EMPTY: -// IR-NEXT: [[COND_FALSE27]]: -// IR-NEXT: %[[TMP28:.+]] = load i32, ptr %[[DOTFLOOR_0_IV__FLOOR_0_IV_I17]], align 4 -// IR-NEXT: %[[ADD28:.+]] = add i32 %[[TMP28]], 3 -// IR-NEXT: br label %[[COND_END29]] -// IR-EMPTY: -// IR-NEXT: [[COND_END29]]: -// IR-NEXT: %[[COND30:.+]] = phi i32 [ %[[ADD26]], %[[COND_TRUE25]] ], [ %[[ADD28]], %[[COND_FALSE27]] ] -// IR-NEXT: %[[CMP31:.+]] = icmp ult i32 %[[TMP24]], %[[COND30]] -// IR-NEXT: br i1 %[[CMP31]], label %[[FOR_BODY:.+]], label %[[FOR_END50:.+]] -// IR-EMPTY: -// IR-NEXT: [[FOR_BODY]]: -// IR-NEXT: %[[TMP29:.+]] = load i32, ptr %[[DOTTILE_0_IV__FLOOR_0_IV_I]], align 4 -// IR-NEXT: %[[MUL32:.+]] = mul i32 %[[TMP29]], 4 -// IR-NEXT: %[[ADD33:.+]] = add i32 0, %[[MUL32]] -// IR-NEXT: store i32 %[[ADD33]], ptr %[[DOTFLOOR_0_IV_I]], align 4 -// IR-NEXT: %[[TMP30:.+]] = load i32, ptr %[[DOTFLOOR_0_IV_I]], align 4 -// IR-NEXT: store i32 %[[TMP30]], ptr %[[DOTTILE_0_IV_I]], align 4 -// IR-NEXT: br label %[[FOR_COND34:.+]] -// IR-EMPTY: -// IR-NEXT: [[FOR_COND34]]: -// IR-NEXT: %[[TMP31:.+]] = load i32, ptr %[[DOTTILE_0_IV_I]], align 4 -// IR-NEXT: %[[TMP32:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_2]], align 4 -// IR-NEXT: %[[ADD35:.+]] = add i32 %[[TMP32]], 1 -// IR-NEXT: %[[TMP33:.+]] = load i32, ptr %[[DOTFLOOR_0_IV_I]], align 4 -// IR-NEXT: %[[ADD36:.+]] = add i32 %[[TMP33]], 4 -// IR-NEXT: %[[CMP37:.+]] = icmp ult i32 %[[ADD35]], %[[ADD36]] -// IR-NEXT: br i1 %[[CMP37]], label %[[COND_TRUE38:.+]], label %[[COND_FALSE40:.+]] -// IR-EMPTY: -// IR-NEXT: [[COND_TRUE38]]: -// IR-NEXT: %[[TMP34:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_2]], align 4 -// IR-NEXT: %[[ADD39:.+]] = add i32 %[[TMP34]], 1 -// IR-NEXT: br label %[[COND_END42:.+]] -// IR-EMPTY: -// IR-NEXT: [[COND_FALSE40]]: -// IR-NEXT: %[[TMP35:.+]] = load i32, ptr %[[DOTFLOOR_0_IV_I]], align 4 -// IR-NEXT: %[[ADD41:.+]] = add i32 %[[TMP35]], 4 -// IR-NEXT: br label %[[COND_END42]] -// IR-EMPTY: -// IR-NEXT: [[COND_END42]]: -// IR-NEXT: %[[COND43:.+]] = phi i32 [ %[[ADD39]], %[[COND_TRUE38]] ], [ %[[ADD41]], %[[COND_FALSE40]] ] -// IR-NEXT: %[[CMP44:.+]] = icmp ult i32 %[[TMP31]], %[[COND43]] -// IR-NEXT: br i1 %[[CMP44]], label %[[FOR_BODY45:.+]], label %[[FOR_END:.+]] -// IR-EMPTY: -// IR-NEXT: [[FOR_BODY45]]: -// IR-NEXT: %[[TMP36:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_]], align 4 -// IR-NEXT: %[[TMP37:.+]] = load i32, ptr %[[DOTTILE_0_IV_I]], align 4 -// IR-NEXT: %[[TMP38:.+]] = load i32, ptr %[[DOTNEW_STEP]], align 4 -// IR-NEXT: %[[MUL46:.+]] = mul i32 %[[TMP37]], %[[TMP38]] -// IR-NEXT: %[[ADD47:.+]] = add i32 %[[TMP36]], %[[MUL46]] -// IR-NEXT: store i32 %[[ADD47]], ptr %[[I]], align 4 -// IR-NEXT: %[[TMP39:.+]] = load i32, ptr %[[START_ADDR]], align 4 -// IR-NEXT: %[[TMP40:.+]] = load i32, ptr %[[END_ADDR]], align 4 -// IR-NEXT: %[[TMP41:.+]] = load i32, ptr %[[STEP_ADDR]], align 4 -// IR-NEXT: %[[TMP42:.+]] = load i32, ptr %[[I]], align 4 -// IR-NEXT: call void (...) @body(i32 noundef %[[TMP39]], i32 noundef %[[TMP40]], i32 noundef %[[TMP41]], i32 noundef %[[TMP42]]) -// IR-NEXT: br label %[[FOR_INC:.+]] -// IR-EMPTY: -// IR-NEXT: [[FOR_INC]]: -// IR-NEXT: %[[TMP43:.+]] = load i32, ptr %[[DOTTILE_0_IV_I]], align 4 -// IR-NEXT: %[[INC:.+]] = add i32 %[[TMP43]], 1 -// IR-NEXT: store i32 %[[INC]], ptr %[[DOTTILE_0_IV_I]], align 4 -// IR-NEXT: br label %[[FOR_COND34]], !llvm.loop ![[LOOP2:[0-9]+]] -// IR-EMPTY: -// IR-NEXT: [[FOR_END]]: -// IR-NEXT: br label %[[FOR_INC48:.+]] -// IR-EMPTY: -// IR-NEXT: [[FOR_INC48]]: -// IR-NEXT: %[[TMP44:.+]] = load i32, ptr %[[DOTTILE_0_IV__FLOOR_0_IV_I]], align 4 -// IR-NEXT: %[[INC49:.+]] = add i32 %[[TMP44]], 1 -// IR-NEXT: store i32 %[[INC49]], ptr %[[DOTTILE_0_IV__FLOOR_0_IV_I]], align 4 -// IR-NEXT: br label %[[FOR_COND]], !llvm.loop ![[LOOP4:[0-9]+]] -// IR-EMPTY: -// IR-NEXT: [[FOR_END50]]: -// IR-NEXT: br label %[[OMP_BODY_CONTINUE:.+]] -// IR-EMPTY: -// IR-NEXT: [[OMP_BODY_CONTINUE]]: -// IR-NEXT: br label %[[OMP_INNER_FOR_INC:.+]] -// IR-EMPTY: -// IR-NEXT: [[OMP_INNER_FOR_INC]]: -// IR-NEXT: %[[TMP45:.+]] = load i32, ptr %[[DOTOMP_IV]], align 4 -// IR-NEXT: %[[ADD51:.+]] = add i32 %[[TMP45]], 1 -// IR-NEXT: store i32 %[[ADD51]], ptr %[[DOTOMP_IV]], align 4 +// IR: [[COND_END]]: +// IR-NEXT: [[COND:%.*]] = phi i32 [ [[TMP17]], %[[COND_TRUE]] ], [ [[TMP18]], %[[COND_FALSE]] ] +// IR-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 +// IR-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 +// IR-NEXT: store i32 [[TMP19]], ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: br label %[[OMP_INNER_FOR_COND:.*]] +// IR: [[OMP_INNER_FOR_COND]]: +// IR-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// IR-NEXT: [[ADD19:%.*]] = add i32 [[TMP21]], 1 +// IR-NEXT: [[CMP20:%.*]] = icmp ult i32 [[TMP20]], [[ADD19]] +// IR-NEXT: br i1 [[CMP20]], label %[[OMP_INNER_FOR_BODY:.*]], label %[[OMP_INNER_FOR_END:.*]] +// IR: [[OMP_INNER_FOR_BODY]]: +// IR-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: [[MUL:%.*]] = mul i32 [[TMP22]], 3 +// IR-NEXT: [[ADD21:%.*]] = add i32 0, [[MUL]] +// IR-NEXT: store i32 [[ADD21]], ptr [[DOTFLOOR_0_IV__FLOOR_0_IV_I17]], align 4 +// IR-NEXT: store i32 0, ptr [[DOTTILE_CNT_0_IV__FLOOR_0_IV_I]], align 4 +// IR-NEXT: br label %[[FOR_COND:.*]] +// IR: [[FOR_COND]]: +// IR-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTTILE_CNT_0_IV__FLOOR_0_IV_I]], align 4 +// IR-NEXT: [[CMP22:%.*]] = icmp ult i32 [[TMP23]], 3 +// IR-NEXT: br i1 [[CMP22]], label %[[FOR_BODY:.*]], label %[[FOR_END40:.*]] +// IR: [[FOR_BODY]]: +// IR-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTFLOOR_0_IV__FLOOR_0_IV_I17]], align 4 +// IR-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTTILE_CNT_0_IV__FLOOR_0_IV_I]], align 4 +// IR-NEXT: [[ADD23:%.*]] = add i32 [[TMP24]], [[TMP25]] +// IR-NEXT: store i32 [[ADD23]], ptr [[DOTTILE_0_IV__FLOOR_0_IV_I]], align 4 +// IR-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTTILE_0_IV__FLOOR_0_IV_I]], align 4 +// IR-NEXT: [[MUL24:%.*]] = mul i32 [[TMP26]], 4 +// IR-NEXT: [[ADD25:%.*]] = add i32 0, [[MUL24]] +// IR-NEXT: store i32 [[ADD25]], ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTTILE_0_IV__FLOOR_0_IV_I]], align 4 +// IR-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_7]], align 4 +// IR-NEXT: [[ADD26:%.*]] = add i32 [[TMP28]], 1 +// IR-NEXT: [[CMP27:%.*]] = icmp ult i32 [[TMP27]], [[ADD26]] +// IR-NEXT: br i1 [[CMP27]], label %[[IF_THEN:.*]], label %[[IF_END37:.*]] +// IR: [[IF_THEN]]: +// IR-NEXT: store i32 0, ptr [[DOTTILE_CNT_0_IV_I]], align 4 +// IR-NEXT: br label %[[FOR_COND28:.*]] +// IR: [[FOR_COND28]]: +// IR-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTTILE_CNT_0_IV_I]], align 4 +// IR-NEXT: [[CMP29:%.*]] = icmp ult i32 [[TMP29]], 4 +// IR-NEXT: br i1 [[CMP29]], label %[[FOR_BODY30:.*]], label %[[FOR_END:.*]] +// IR: [[FOR_BODY30]]: +// IR-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTTILE_CNT_0_IV_I]], align 4 +// IR-NEXT: [[ADD31:%.*]] = add i32 [[TMP30]], [[TMP31]] +// IR-NEXT: store i32 [[ADD31]], ptr [[DOTTILE_0_IV_I]], align 4 +// IR-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 +// IR-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 +// IR-NEXT: [[MUL32:%.*]] = mul i32 [[TMP33]], [[TMP34]] +// IR-NEXT: [[ADD33:%.*]] = add i32 [[TMP32]], [[MUL32]] +// IR-NEXT: store i32 [[ADD33]], ptr [[I]], align 4 +// IR-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 +// IR-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 +// IR-NEXT: [[ADD34:%.*]] = add i32 [[TMP36]], 1 +// IR-NEXT: [[CMP35:%.*]] = icmp ult i32 [[TMP35]], [[ADD34]] +// IR-NEXT: br i1 [[CMP35]], label %[[IF_THEN36:.*]], label %[[IF_END:.*]] +// IR: [[IF_THEN36]]: +// IR-NEXT: [[TMP37:%.*]] = load i32, ptr [[START_ADDR]], align 4 +// IR-NEXT: [[TMP38:%.*]] = load i32, ptr [[END_ADDR]], align 4 +// IR-NEXT: [[TMP39:%.*]] = load i32, ptr [[STEP_ADDR]], align 4 +// IR-NEXT: [[TMP40:%.*]] = load i32, ptr [[I]], align 4 +// IR-NEXT: call void (...) @body(i32 noundef [[TMP37]], i32 noundef [[TMP38]], i32 noundef [[TMP39]], i32 noundef [[TMP40]]) +// IR-NEXT: br label %[[IF_END]] +// IR: [[IF_END]]: +// IR-NEXT: br label %[[FOR_INC:.*]] +// IR: [[FOR_INC]]: +// IR-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTTILE_CNT_0_IV_I]], align 4 +// IR-NEXT: [[INC:%.*]] = add i32 [[TMP41]], 1 +// IR-NEXT: store i32 [[INC]], ptr [[DOTTILE_CNT_0_IV_I]], align 4 +// IR-NEXT: br label %[[FOR_COND28]], !llvm.loop [[LOOP2:![0-9]+]] +// IR: [[FOR_END]]: +// IR-NEXT: br label %[[IF_END37]] +// IR: [[IF_END37]]: +// IR-NEXT: br label %[[FOR_INC38:.*]] +// IR: [[FOR_INC38]]: +// IR-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTTILE_CNT_0_IV__FLOOR_0_IV_I]], align 4 +// IR-NEXT: [[INC39:%.*]] = add i32 [[TMP42]], 1 +// IR-NEXT: store i32 [[INC39]], ptr [[DOTTILE_CNT_0_IV__FLOOR_0_IV_I]], align 4 +// IR-NEXT: br label %[[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] +// IR: [[FOR_END40]]: +// IR-NEXT: br label %[[OMP_BODY_CONTINUE:.*]] +// IR: [[OMP_BODY_CONTINUE]]: +// IR-NEXT: br label %[[OMP_INNER_FOR_INC:.*]] +// IR: [[OMP_INNER_FOR_INC]]: +// IR-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: [[ADD41:%.*]] = add i32 [[TMP43]], 1 +// IR-NEXT: store i32 [[ADD41]], ptr [[DOTOMP_IV]], align 4 // IR-NEXT: br label %[[OMP_INNER_FOR_COND]] -// IR-EMPTY: -// IR-NEXT: [[OMP_INNER_FOR_END]]: -// IR-NEXT: br label %[[OMP_LOOP_EXIT:.+]] -// IR-EMPTY: -// IR-NEXT: [[OMP_LOOP_EXIT]]: -// IR-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 %[[TMP0]]) +// IR: [[OMP_INNER_FOR_END]]: +// IR-NEXT: br label %[[OMP_LOOP_EXIT:.*]] +// IR: [[OMP_LOOP_EXIT]]: +// IR-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]]) // IR-NEXT: br label %[[OMP_PRECOND_END]] -// IR-EMPTY: -// IR-NEXT: [[OMP_PRECOND_END]]: -// IR-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:.+]], i32 %[[TMP0]]) +// IR: [[OMP_PRECOND_END]]: +// IR-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP0]]) // IR-NEXT: ret void -// IR-NEXT: } - - +// extern "C" void func(int start, int end, int step) { #pragma omp for #pragma omp tile sizes(3) @@ -249,8 +218,8 @@ extern "C" void func(int start, int end, int step) { #endif /* HEADER */ -// IR: ![[META0:[0-9]+]] = !{i32 7, !"openmp", i32 51} -// IR: ![[META1:[0-9]+]] = -// IR: ![[LOOP2]] = distinct !{![[LOOP2]], ![[LOOPPROP3:[0-9]+]]} -// IR: ![[LOOPPROP3]] = !{!"llvm.loop.mustprogress"} -// IR: ![[LOOP4]] = distinct !{![[LOOP4]], ![[LOOPPROP3]]} +//. +// IR: [[LOOP2]] = distinct !{[[LOOP2]], [[META3:![0-9]+]]} +// IR: [[META3]] = !{!"llvm.loop.mustprogress"} +// IR: [[LOOP4]] = distinct !{[[LOOP4]], [[META3]]} +//. diff --git a/clang/test/OpenMP/tile_messages.cpp b/clang/test/OpenMP/tile_messages.cpp index e1f5155c924e5..8915d1bb3c546 100644 --- a/clang/test/OpenMP/tile_messages.cpp +++ b/clang/test/OpenMP/tile_messages.cpp @@ -101,7 +101,7 @@ void func() { for (int j = 0; j < i; ++j) ; - // expected-error@+5 {{expected 3 for loops after '#pragma omp for', but found only 2}} + // expected-error@* {{expected 3 for loops after '#pragma omp for', but found only 2}} // expected-note@+1 {{as specified in 'collapse' clause}} #pragma omp for collapse(3) #pragma omp tile sizes(5) diff --git a/clang/test/OpenMP/tile_rect_codegen.cpp b/clang/test/OpenMP/tile_rect_codegen.cpp new file mode 100644 index 0000000000000..589914eb9d63e --- /dev/null +++ b/clang/test/OpenMP/tile_rect_codegen.cpp @@ -0,0 +1,50 @@ +// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fclang-abi-compat=latest -std=c++20 -fopenmp -ast-print %s | FileCheck %s +// expected-no-diagnostics + +extern "C" void body(...) {} + +// CHECK-LABEL: void rect_tile_1d( +void rect_tile_1d() { + // Tile size 5, trip count 4: 4 % 5 != 0, so predicate is needed. + // The tile loop should have rectangular bound (the tile size) and + // the body should be guarded by a validity predicate. + // + // CHECK: #pragma omp tile sizes(5) + // CHECK-NEXT: for (int i = 7; i < 17; i += 3) + #pragma omp tile sizes(5) + for (int i = 7; i < 17; i += 3) + body(i); +} + +// CHECK-LABEL: void rect_tile_2d( +void rect_tile_2d() { + // CHECK: #pragma omp tile sizes(5, 5) + // CHECK-NEXT: for (int i = 7; i < 17; i += 3) + // CHECK-NEXT: for (int j = 7; j < 17; j += 3) + #pragma omp tile sizes(5, 5) + for (int i = 7; i < 17; i += 3) + for (int j = 7; j < 17; j += 3) + body(i, j); +} + +// CHECK-LABEL: void rect_tile_exact_div( +void rect_tile_exact_div() { + // Tile size 5, trip count 10: 10 % 5 == 0, so predicate is NOT needed. + // CHECK: #pragma omp tile sizes(5) + // CHECK-NEXT: for (int i = 0; i < 10; i += 1) + #pragma omp tile sizes(5) + for (int i = 0; i < 10; i += 1) + body(i); +} + +// CHECK-LABEL: void rect_tile_nested_body_loop( +void rect_tile_nested_body_loop(int n) { + // After tiling i, the j loop (from the associated body) should be part + // of the same canonical nest as the floor and tile loops. + // CHECK: #pragma omp tile sizes(4) + // CHECK-NEXT: for (int i = 0; i < 6; i += 1) + #pragma omp tile sizes(4) + for (int i = 0; i < 6; i += 1) + for (int j = 0; j < n; ++j) + body(i, j); +} diff --git a/clang/test/OpenMP/tile_rect_codegen_ir.cpp b/clang/test/OpenMP/tile_rect_codegen_ir.cpp new file mode 100644 index 0000000000000..808f1cf0a3d0c --- /dev/null +++ b/clang/test/OpenMP/tile_rect_codegen_ir.cpp @@ -0,0 +1,513 @@ +// Regression tests for rectangular #pragma omp tile lowering: +// - Inner loop counter .tile.cnt.* with bound == tile size (constant). +// - Validity guard (icmp + branch) when remainder iterations exist or trip count +// is not proven divisible at compile time. +// +// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fopenmp -emit-llvm -o - %s | FileCheck %s --check-prefix=IR +// expected-no-diagnostics + +extern "C" void body(int); + +// Trip count 6, tile 4 → remainder; body must be guarded. +// IR-LABEL: define dso_local void @_Z18remainder_6_tile_4v( +// IR-SAME: ) #[[ATTR0:[0-9]+]] { +// IR-NEXT: [[ENTRY:.*:]] +// IR-NEXT: [[I:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4 +// IR-NEXT: store i32 0, ptr [[I]], align 4 +// IR-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: br label %[[FOR_COND:.*]] +// IR: [[FOR_COND]]: +// IR-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 6 +// IR-NEXT: br i1 [[CMP]], label %[[FOR_BODY:.*]], label %[[FOR_END9:.*]] +// IR: [[FOR_BODY]]: +// IR-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: store i32 [[TMP1]], ptr [[DOTTILE_0_IV_I]], align 4 +// IR-NEXT: br label %[[FOR_COND1:.*]] +// IR: [[FOR_COND1]]: +// IR-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 +// IR-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 4 +// IR-NEXT: [[CMP2:%.*]] = icmp slt i32 6, [[ADD]] +// IR-NEXT: br i1 [[CMP2]], label %[[COND_TRUE:.*]], label %[[COND_FALSE:.*]] +// IR: [[COND_TRUE]]: +// IR-NEXT: br label %[[COND_END:.*]] +// IR: [[COND_FALSE]]: +// IR-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP4]], 4 +// IR-NEXT: br label %[[COND_END]] +// IR: [[COND_END]]: +// IR-NEXT: [[COND:%.*]] = phi i32 [ 6, %[[COND_TRUE]] ], [ [[ADD3]], %[[COND_FALSE]] ] +// IR-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP2]], [[COND]] +// IR-NEXT: br i1 [[CMP4]], label %[[FOR_BODY5:.*]], label %[[FOR_END:.*]] +// IR: [[FOR_BODY5]]: +// IR-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 +// IR-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 1 +// IR-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL]] +// IR-NEXT: store i32 [[ADD6]], ptr [[I]], align 4 +// IR-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4 +// IR-NEXT: call void @body(i32 noundef [[TMP6]]) +// IR-NEXT: br label %[[FOR_INC:.*]] +// IR: [[FOR_INC]]: +// IR-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 +// IR-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 +// IR-NEXT: store i32 [[INC]], ptr [[DOTTILE_0_IV_I]], align 4 +// IR-NEXT: br label %[[FOR_COND1]], !llvm.loop [[LOOP2:![0-9]+]] +// IR: [[FOR_END]]: +// IR-NEXT: br label %[[FOR_INC7:.*]] +// IR: [[FOR_INC7]]: +// IR-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 4 +// IR-NEXT: store i32 [[ADD8]], ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: br label %[[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] +// IR: [[FOR_END9]]: +// IR-NEXT: ret void +// +void remainder_6_tile_4(void) { + // Rectangular tile counter and constant tile-size bound. +#pragma omp tile sizes(4) + for (int i = 0; i < 6; ++i) + body(i); +} + +// Simple stride-1 loop; tile size matches full tiles only (10, tile 5). +// IR-LABEL: define dso_local void @_Z15full_tiles_10_5v( +// IR-SAME: ) #[[ATTR0]] { +// IR-NEXT: [[ENTRY:.*:]] +// IR-NEXT: [[I:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4 +// IR-NEXT: store i32 0, ptr [[I]], align 4 +// IR-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: br label %[[FOR_COND:.*]] +// IR: [[FOR_COND]]: +// IR-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10 +// IR-NEXT: br i1 [[CMP]], label %[[FOR_BODY:.*]], label %[[FOR_END9:.*]] +// IR: [[FOR_BODY]]: +// IR-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: store i32 [[TMP1]], ptr [[DOTTILE_0_IV_I]], align 4 +// IR-NEXT: br label %[[FOR_COND1:.*]] +// IR: [[FOR_COND1]]: +// IR-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 +// IR-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 5 +// IR-NEXT: [[CMP2:%.*]] = icmp slt i32 10, [[ADD]] +// IR-NEXT: br i1 [[CMP2]], label %[[COND_TRUE:.*]], label %[[COND_FALSE:.*]] +// IR: [[COND_TRUE]]: +// IR-NEXT: br label %[[COND_END:.*]] +// IR: [[COND_FALSE]]: +// IR-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP4]], 5 +// IR-NEXT: br label %[[COND_END]] +// IR: [[COND_END]]: +// IR-NEXT: [[COND:%.*]] = phi i32 [ 10, %[[COND_TRUE]] ], [ [[ADD3]], %[[COND_FALSE]] ] +// IR-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP2]], [[COND]] +// IR-NEXT: br i1 [[CMP4]], label %[[FOR_BODY5:.*]], label %[[FOR_END:.*]] +// IR: [[FOR_BODY5]]: +// IR-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 +// IR-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 1 +// IR-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL]] +// IR-NEXT: store i32 [[ADD6]], ptr [[I]], align 4 +// IR-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4 +// IR-NEXT: call void @body(i32 noundef [[TMP6]]) +// IR-NEXT: br label %[[FOR_INC:.*]] +// IR: [[FOR_INC]]: +// IR-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 +// IR-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 +// IR-NEXT: store i32 [[INC]], ptr [[DOTTILE_0_IV_I]], align 4 +// IR-NEXT: br label %[[FOR_COND1]], !llvm.loop [[LOOP5:![0-9]+]] +// IR: [[FOR_END]]: +// IR-NEXT: br label %[[FOR_INC7:.*]] +// IR: [[FOR_INC7]]: +// IR-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 5 +// IR-NEXT: store i32 [[ADD8]], ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: br label %[[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] +// IR: [[FOR_END9]]: +// IR-NEXT: ret void +// +void full_tiles_10_5(void) { +#pragma omp tile sizes(5) + for (int i = 0; i < 10; ++i) + body(i); +} + +// Variable tile size: clamp (TS<=0 ? 1 : TS) is inlined; bound compares to %cond. +// IR-LABEL: define dso_local void @_Z8var_tilei( +// IR-SAME: i32 noundef [[TS:%.*]]) #[[ATTR0]] { +// IR-NEXT: [[ENTRY:.*:]] +// IR-NEXT: [[TS_ADDR:%.*]] = alloca i32, align 4 +// IR-NEXT: [[I:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4 +// IR-NEXT: store i32 [[TS]], ptr [[TS_ADDR]], align 4 +// IR-NEXT: store i32 0, ptr [[I]], align 4 +// IR-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: br label %[[FOR_COND:.*]] +// IR: [[FOR_COND]]: +// IR-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 12 +// IR-NEXT: br i1 [[CMP]], label %[[FOR_BODY:.*]], label %[[FOR_END24:.*]] +// IR: [[FOR_BODY]]: +// IR-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: store i32 [[TMP1]], ptr [[DOTTILE_0_IV_I]], align 4 +// IR-NEXT: br label %[[FOR_COND1:.*]] +// IR: [[FOR_COND1]]: +// IR-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 +// IR-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: [[TMP4:%.*]] = load i32, ptr [[TS_ADDR]], align 4 +// IR-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP4]], 0 +// IR-NEXT: br i1 [[CMP2]], label %[[COND_TRUE:.*]], label %[[COND_FALSE:.*]] +// IR: [[COND_TRUE]]: +// IR-NEXT: br label %[[COND_END:.*]] +// IR: [[COND_FALSE]]: +// IR-NEXT: [[TMP5:%.*]] = load i32, ptr [[TS_ADDR]], align 4 +// IR-NEXT: br label %[[COND_END]] +// IR: [[COND_END]]: +// IR-NEXT: [[COND:%.*]] = phi i32 [ 1, %[[COND_TRUE]] ], [ [[TMP5]], %[[COND_FALSE]] ] +// IR-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[COND]] +// IR-NEXT: [[CMP3:%.*]] = icmp slt i32 12, [[ADD]] +// IR-NEXT: br i1 [[CMP3]], label %[[COND_TRUE4:.*]], label %[[COND_FALSE5:.*]] +// IR: [[COND_TRUE4]]: +// IR-NEXT: br label %[[COND_END12:.*]] +// IR: [[COND_FALSE5]]: +// IR-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: [[TMP7:%.*]] = load i32, ptr [[TS_ADDR]], align 4 +// IR-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP7]], 0 +// IR-NEXT: br i1 [[CMP6]], label %[[COND_TRUE7:.*]], label %[[COND_FALSE8:.*]] +// IR: [[COND_TRUE7]]: +// IR-NEXT: br label %[[COND_END9:.*]] +// IR: [[COND_FALSE8]]: +// IR-NEXT: [[TMP8:%.*]] = load i32, ptr [[TS_ADDR]], align 4 +// IR-NEXT: br label %[[COND_END9]] +// IR: [[COND_END9]]: +// IR-NEXT: [[COND10:%.*]] = phi i32 [ 1, %[[COND_TRUE7]] ], [ [[TMP8]], %[[COND_FALSE8]] ] +// IR-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP6]], [[COND10]] +// IR-NEXT: br label %[[COND_END12]] +// IR: [[COND_END12]]: +// IR-NEXT: [[COND13:%.*]] = phi i32 [ 12, %[[COND_TRUE4]] ], [ [[ADD11]], %[[COND_END9]] ] +// IR-NEXT: [[CMP14:%.*]] = icmp slt i32 [[TMP2]], [[COND13]] +// IR-NEXT: br i1 [[CMP14]], label %[[FOR_BODY15:.*]], label %[[FOR_END:.*]] +// IR: [[FOR_BODY15]]: +// IR-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 +// IR-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// IR-NEXT: [[ADD16:%.*]] = add nsw i32 0, [[MUL]] +// IR-NEXT: store i32 [[ADD16]], ptr [[I]], align 4 +// IR-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 +// IR-NEXT: call void @body(i32 noundef [[TMP10]]) +// IR-NEXT: br label %[[FOR_INC:.*]] +// IR: [[FOR_INC]]: +// IR-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 +// IR-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1 +// IR-NEXT: store i32 [[INC]], ptr [[DOTTILE_0_IV_I]], align 4 +// IR-NEXT: br label %[[FOR_COND1]], !llvm.loop [[LOOP7:![0-9]+]] +// IR: [[FOR_END]]: +// IR-NEXT: br label %[[FOR_INC17:.*]] +// IR: [[FOR_INC17]]: +// IR-NEXT: [[TMP12:%.*]] = load i32, ptr [[TS_ADDR]], align 4 +// IR-NEXT: [[CMP18:%.*]] = icmp sle i32 [[TMP12]], 0 +// IR-NEXT: br i1 [[CMP18]], label %[[COND_TRUE19:.*]], label %[[COND_FALSE20:.*]] +// IR: [[COND_TRUE19]]: +// IR-NEXT: br label %[[COND_END21:.*]] +// IR: [[COND_FALSE20]]: +// IR-NEXT: [[TMP13:%.*]] = load i32, ptr [[TS_ADDR]], align 4 +// IR-NEXT: br label %[[COND_END21]] +// IR: [[COND_END21]]: +// IR-NEXT: [[COND22:%.*]] = phi i32 [ 1, %[[COND_TRUE19]] ], [ [[TMP13]], %[[COND_FALSE20]] ] +// IR-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP14]], [[COND22]] +// IR-NEXT: store i32 [[ADD23]], ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: br label %[[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] +// IR: [[FOR_END24]]: +// IR-NEXT: ret void +// +void var_tile(int ts) { +#pragma omp tile sizes(ts) + for (int i = 0; i < 12; ++i) + body(i); +} + +// Two tiled dimensions → two tile counters. +// IR-LABEL: define dso_local void @_Z7two_dimv( +// IR-SAME: ) #[[ATTR0]] { +// IR-NEXT: [[ENTRY:.*:]] +// IR-NEXT: [[I:%.*]] = alloca i32, align 4 +// IR-NEXT: [[J:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTFLOOR_1_IV_J:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTTILE_1_IV_J:%.*]] = alloca i32, align 4 +// IR-NEXT: store i32 0, ptr [[I]], align 4 +// IR-NEXT: store i32 0, ptr [[J]], align 4 +// IR-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: br label %[[FOR_COND:.*]] +// IR: [[FOR_COND]]: +// IR-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 3 +// IR-NEXT: br i1 [[CMP]], label %[[FOR_BODY:.*]], label %[[FOR_END31:.*]] +// IR: [[FOR_BODY]]: +// IR-NEXT: store i32 0, ptr [[DOTFLOOR_1_IV_J]], align 4 +// IR-NEXT: br label %[[FOR_COND1:.*]] +// IR: [[FOR_COND1]]: +// IR-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4 +// IR-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 3 +// IR-NEXT: br i1 [[CMP2]], label %[[FOR_BODY3:.*]], label %[[FOR_END28:.*]] +// IR: [[FOR_BODY3]]: +// IR-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: store i32 [[TMP2]], ptr [[DOTTILE_0_IV_I]], align 4 +// IR-NEXT: br label %[[FOR_COND4:.*]] +// IR: [[FOR_COND4]]: +// IR-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 +// IR-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], 2 +// IR-NEXT: [[CMP5:%.*]] = icmp slt i32 3, [[ADD]] +// IR-NEXT: br i1 [[CMP5]], label %[[COND_TRUE:.*]], label %[[COND_FALSE:.*]] +// IR: [[COND_TRUE]]: +// IR-NEXT: br label %[[COND_END:.*]] +// IR: [[COND_FALSE]]: +// IR-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP5]], 2 +// IR-NEXT: br label %[[COND_END]] +// IR: [[COND_END]]: +// IR-NEXT: [[COND:%.*]] = phi i32 [ 3, %[[COND_TRUE]] ], [ [[ADD6]], %[[COND_FALSE]] ] +// IR-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP3]], [[COND]] +// IR-NEXT: br i1 [[CMP7]], label %[[FOR_BODY8:.*]], label %[[FOR_END25:.*]] +// IR: [[FOR_BODY8]]: +// IR-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 +// IR-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1 +// IR-NEXT: [[ADD9:%.*]] = add nsw i32 0, [[MUL]] +// IR-NEXT: store i32 [[ADD9]], ptr [[I]], align 4 +// IR-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4 +// IR-NEXT: store i32 [[TMP7]], ptr [[DOTTILE_1_IV_J]], align 4 +// IR-NEXT: br label %[[FOR_COND10:.*]] +// IR: [[FOR_COND10]]: +// IR-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTTILE_1_IV_J]], align 4 +// IR-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4 +// IR-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP9]], 2 +// IR-NEXT: [[CMP12:%.*]] = icmp slt i32 3, [[ADD11]] +// IR-NEXT: br i1 [[CMP12]], label %[[COND_TRUE13:.*]], label %[[COND_FALSE14:.*]] +// IR: [[COND_TRUE13]]: +// IR-NEXT: br label %[[COND_END16:.*]] +// IR: [[COND_FALSE14]]: +// IR-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4 +// IR-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP10]], 2 +// IR-NEXT: br label %[[COND_END16]] +// IR: [[COND_END16]]: +// IR-NEXT: [[COND17:%.*]] = phi i32 [ 3, %[[COND_TRUE13]] ], [ [[ADD15]], %[[COND_FALSE14]] ] +// IR-NEXT: [[CMP18:%.*]] = icmp slt i32 [[TMP8]], [[COND17]] +// IR-NEXT: br i1 [[CMP18]], label %[[FOR_BODY19:.*]], label %[[FOR_END:.*]] +// IR: [[FOR_BODY19]]: +// IR-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTTILE_1_IV_J]], align 4 +// IR-NEXT: [[MUL20:%.*]] = mul nsw i32 [[TMP11]], 1 +// IR-NEXT: [[ADD21:%.*]] = add nsw i32 0, [[MUL20]] +// IR-NEXT: store i32 [[ADD21]], ptr [[J]], align 4 +// IR-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4 +// IR-NEXT: [[TMP13:%.*]] = load i32, ptr [[J]], align 4 +// IR-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] +// IR-NEXT: call void @body(i32 noundef [[ADD22]]) +// IR-NEXT: br label %[[FOR_INC:.*]] +// IR: [[FOR_INC]]: +// IR-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTTILE_1_IV_J]], align 4 +// IR-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1 +// IR-NEXT: store i32 [[INC]], ptr [[DOTTILE_1_IV_J]], align 4 +// IR-NEXT: br label %[[FOR_COND10]], !llvm.loop [[LOOP9:![0-9]+]] +// IR: [[FOR_END]]: +// IR-NEXT: br label %[[FOR_INC23:.*]] +// IR: [[FOR_INC23]]: +// IR-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 +// IR-NEXT: [[INC24:%.*]] = add nsw i32 [[TMP15]], 1 +// IR-NEXT: store i32 [[INC24]], ptr [[DOTTILE_0_IV_I]], align 4 +// IR-NEXT: br label %[[FOR_COND4]], !llvm.loop [[LOOP10:![0-9]+]] +// IR: [[FOR_END25]]: +// IR-NEXT: br label %[[FOR_INC26:.*]] +// IR: [[FOR_INC26]]: +// IR-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTFLOOR_1_IV_J]], align 4 +// IR-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP16]], 2 +// IR-NEXT: store i32 [[ADD27]], ptr [[DOTFLOOR_1_IV_J]], align 4 +// IR-NEXT: br label %[[FOR_COND1]], !llvm.loop [[LOOP11:![0-9]+]] +// IR: [[FOR_END28]]: +// IR-NEXT: br label %[[FOR_INC29:.*]] +// IR: [[FOR_INC29]]: +// IR-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: [[ADD30:%.*]] = add nsw i32 [[TMP17]], 2 +// IR-NEXT: store i32 [[ADD30]], ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: br label %[[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] +// IR: [[FOR_END31]]: +// IR-NEXT: ret void +// +void two_dim(void) { +#pragma omp tile sizes(2, 2) + for (int i = 0; i < 3; ++i) + for (int j = 0; j < 3; ++j) + body(i + j); +} + +// Nested loop in tile body: outer nest still uses .tile.cnt for tiled dim. +// IR-LABEL: define dso_local void @_Z14nested_inner_ji( +// IR-SAME: i32 noundef [[N:%.*]]) #[[ATTR0]] { +// IR-NEXT: [[ENTRY:.*:]] +// IR-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 +// IR-NEXT: [[I:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4 +// IR-NEXT: [[J:%.*]] = alloca i32, align 4 +// IR-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 +// IR-NEXT: store i32 0, ptr [[I]], align 4 +// IR-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: br label %[[FOR_COND:.*]] +// IR: [[FOR_COND]]: +// IR-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 6 +// IR-NEXT: br i1 [[CMP]], label %[[FOR_BODY:.*]], label %[[FOR_END16:.*]] +// IR: [[FOR_BODY]]: +// IR-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: store i32 [[TMP1]], ptr [[DOTTILE_0_IV_I]], align 4 +// IR-NEXT: br label %[[FOR_COND1:.*]] +// IR: [[FOR_COND1]]: +// IR-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 +// IR-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 4 +// IR-NEXT: [[CMP2:%.*]] = icmp slt i32 6, [[ADD]] +// IR-NEXT: br i1 [[CMP2]], label %[[COND_TRUE:.*]], label %[[COND_FALSE:.*]] +// IR: [[COND_TRUE]]: +// IR-NEXT: br label %[[COND_END:.*]] +// IR: [[COND_FALSE]]: +// IR-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP4]], 4 +// IR-NEXT: br label %[[COND_END]] +// IR: [[COND_END]]: +// IR-NEXT: [[COND:%.*]] = phi i32 [ 6, %[[COND_TRUE]] ], [ [[ADD3]], %[[COND_FALSE]] ] +// IR-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP2]], [[COND]] +// IR-NEXT: br i1 [[CMP4]], label %[[FOR_BODY5:.*]], label %[[FOR_END13:.*]] +// IR: [[FOR_BODY5]]: +// IR-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 +// IR-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 1 +// IR-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL]] +// IR-NEXT: store i32 [[ADD6]], ptr [[I]], align 4 +// IR-NEXT: store i32 0, ptr [[J]], align 4 +// IR-NEXT: br label %[[FOR_COND7:.*]] +// IR: [[FOR_COND7]]: +// IR-NEXT: [[TMP6:%.*]] = load i32, ptr [[J]], align 4 +// IR-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-NEXT: [[CMP8:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]] +// IR-NEXT: br i1 [[CMP8]], label %[[FOR_BODY9:.*]], label %[[FOR_END:.*]] +// IR: [[FOR_BODY9]]: +// IR-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4 +// IR-NEXT: [[TMP9:%.*]] = load i32, ptr [[J]], align 4 +// IR-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] +// IR-NEXT: call void @body(i32 noundef [[ADD10]]) +// IR-NEXT: br label %[[FOR_INC:.*]] +// IR: [[FOR_INC]]: +// IR-NEXT: [[TMP10:%.*]] = load i32, ptr [[J]], align 4 +// IR-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 +// IR-NEXT: store i32 [[INC]], ptr [[J]], align 4 +// IR-NEXT: br label %[[FOR_COND7]], !llvm.loop [[LOOP13:![0-9]+]] +// IR: [[FOR_END]]: +// IR-NEXT: br label %[[FOR_INC11:.*]] +// IR: [[FOR_INC11]]: +// IR-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 +// IR-NEXT: [[INC12:%.*]] = add nsw i32 [[TMP11]], 1 +// IR-NEXT: store i32 [[INC12]], ptr [[DOTTILE_0_IV_I]], align 4 +// IR-NEXT: br label %[[FOR_COND1]], !llvm.loop [[LOOP14:![0-9]+]] +// IR: [[FOR_END13]]: +// IR-NEXT: br label %[[FOR_INC14:.*]] +// IR: [[FOR_INC14]]: +// IR-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP12]], 4 +// IR-NEXT: store i32 [[ADD15]], ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: br label %[[FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] +// IR: [[FOR_END16]]: +// IR-NEXT: ret void +// +void nested_inner_j(int n) { +#pragma omp tile sizes(4) + for (int i = 0; i < 6; ++i) + for (int j = 0; j < n; ++j) + body(i + j); +} + +// Predicate elision: when trip count is evenly divisible by constant tile size, +// no if-guard is needed (no icmp against trip count in tile body). +// IR-LABEL: define dso_local void @_Z16elided_predicatev( +// IR-SAME: ) #[[ATTR0]] { +// IR-NEXT: [[ENTRY:.*:]] +// IR-NEXT: [[I:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTFLOOR_0_IV_I:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTTILE_0_IV_I:%.*]] = alloca i32, align 4 +// IR-NEXT: store i32 0, ptr [[I]], align 4 +// IR-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: br label %[[FOR_COND:.*]] +// IR: [[FOR_COND]]: +// IR-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 12 +// IR-NEXT: br i1 [[CMP]], label %[[FOR_BODY:.*]], label %[[FOR_END9:.*]] +// IR: [[FOR_BODY]]: +// IR-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: store i32 [[TMP1]], ptr [[DOTTILE_0_IV_I]], align 4 +// IR-NEXT: br label %[[FOR_COND1:.*]] +// IR: [[FOR_COND1]]: +// IR-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 +// IR-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 4 +// IR-NEXT: [[CMP2:%.*]] = icmp slt i32 12, [[ADD]] +// IR-NEXT: br i1 [[CMP2]], label %[[COND_TRUE:.*]], label %[[COND_FALSE:.*]] +// IR: [[COND_TRUE]]: +// IR-NEXT: br label %[[COND_END:.*]] +// IR: [[COND_FALSE]]: +// IR-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP4]], 4 +// IR-NEXT: br label %[[COND_END]] +// IR: [[COND_END]]: +// IR-NEXT: [[COND:%.*]] = phi i32 [ 12, %[[COND_TRUE]] ], [ [[ADD3]], %[[COND_FALSE]] ] +// IR-NEXT: [[CMP4:%.*]] = icmp slt i32 [[TMP2]], [[COND]] +// IR-NEXT: br i1 [[CMP4]], label %[[FOR_BODY5:.*]], label %[[FOR_END:.*]] +// IR: [[FOR_BODY5]]: +// IR-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 +// IR-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP5]], 1 +// IR-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL]] +// IR-NEXT: store i32 [[ADD6]], ptr [[I]], align 4 +// IR-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4 +// IR-NEXT: call void @body(i32 noundef [[TMP6]]) +// IR-NEXT: br label %[[FOR_INC:.*]] +// IR: [[FOR_INC]]: +// IR-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTTILE_0_IV_I]], align 4 +// IR-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 +// IR-NEXT: store i32 [[INC]], ptr [[DOTTILE_0_IV_I]], align 4 +// IR-NEXT: br label %[[FOR_COND1]], !llvm.loop [[LOOP16:![0-9]+]] +// IR: [[FOR_END]]: +// IR-NEXT: br label %[[FOR_INC7:.*]] +// IR: [[FOR_INC7]]: +// IR-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 4 +// IR-NEXT: store i32 [[ADD8]], ptr [[DOTFLOOR_0_IV_I]], align 4 +// IR-NEXT: br label %[[FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]] +// IR: [[FOR_END9]]: +// IR-NEXT: ret void +// +void elided_predicate(void) { + // Trip count 12, tile size 4 → 12 % 4 == 0, no predicate. +#pragma omp tile sizes(4) + for (int i = 0; i < 12; ++i) + body(i); +} +//. +// IR: [[LOOP2]] = distinct !{[[LOOP2]], [[META3:![0-9]+]]} +// IR: [[META3]] = !{!"llvm.loop.mustprogress"} +// IR: [[LOOP4]] = distinct !{[[LOOP4]], [[META3]]} +// IR: [[LOOP5]] = distinct !{[[LOOP5]], [[META3]]} +// IR: [[LOOP6]] = distinct !{[[LOOP6]], [[META3]]} +// IR: [[LOOP7]] = distinct !{[[LOOP7]], [[META3]]} +// IR: [[LOOP8]] = distinct !{[[LOOP8]], [[META3]]} +// IR: [[LOOP9]] = distinct !{[[LOOP9]], [[META3]]} +// IR: [[LOOP10]] = distinct !{[[LOOP10]], [[META3]]} +// IR: [[LOOP11]] = distinct !{[[LOOP11]], [[META3]]} +// IR: [[LOOP12]] = distinct !{[[LOOP12]], [[META3]]} +// IR: [[LOOP13]] = distinct !{[[LOOP13]], [[META3]]} +// IR: [[LOOP14]] = distinct !{[[LOOP14]], [[META3]]} +// IR: [[LOOP15]] = distinct !{[[LOOP15]], [[META3]]} +// IR: [[LOOP16]] = distinct !{[[LOOP16]], [[META3]]} +// IR: [[LOOP17]] = distinct !{[[LOOP17]], [[META3]]} +//. diff --git a/clang/test/OpenMP/unroll_codegen_tile_for.cpp b/clang/test/OpenMP/unroll_codegen_tile_for.cpp index ccfc9f38f5a24..6f13f6b67c8cd 100644 --- a/clang/test/OpenMP/unroll_codegen_tile_for.cpp +++ b/clang/test/OpenMP/unroll_codegen_tile_for.cpp @@ -1,3 +1,4 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6 // Check code generation // RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fopenmp -emit-llvm %s -o - | FileCheck %s --check-prefix=IR @@ -13,221 +14,194 @@ extern "C" void body(...) {} -// IR-LABEL: @func( -// IR-NEXT: [[ENTRY:.*]]: -// IR-NEXT: %[[START_ADDR:.+]] = alloca i32, align 4 -// IR-NEXT: %[[END_ADDR:.+]] = alloca i32, align 4 -// IR-NEXT: %[[STEP_ADDR:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTOMP_IV:.+]] = alloca i32, align 4 -// IR-NEXT: %[[TMP:.+]] = alloca i32, align 4 -// IR-NEXT: %[[I:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTCAPTURE_EXPR_:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTCAPTURE_EXPR_1:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTCAPTURE_EXPR_2:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTCAPTURE_EXPR_3:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTUNROLLED_IV_I:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTCAPTURE_EXPR_6:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTCAPTURE_EXPR_8:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTCAPTURE_EXPR_12:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTCAPTURE_EXPR_14:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTFLOOR_0_IV__UNROLLED_IV_I:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTOMP_LB:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTOMP_UB:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTOMP_STRIDE:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTOMP_IS_LAST:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTFLOOR_0_IV__UNROLLED_IV_I18:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTTILE_0_IV__UNROLLED_IV_I:.+]] = alloca i32, align 4 -// IR-NEXT: %[[DOTUNROLL_INNER_IV_I:.+]] = alloca i32, align 4 -// IR-NEXT: %[[TMP0:.+]] = call i32 @__kmpc_global_thread_num(ptr @2) -// IR-NEXT: store i32 %[[START:.+]], ptr %[[START_ADDR]], align 4 -// IR-NEXT: store i32 %[[END:.+]], ptr %[[END_ADDR]], align 4 -// IR-NEXT: store i32 %[[STEP:.+]], ptr %[[STEP_ADDR]], align 4 -// IR-NEXT: %[[TMP1:.+]] = load i32, ptr %[[START_ADDR]], align 4 -// IR-NEXT: store i32 %[[TMP1]], ptr %[[I]], align 4 -// IR-NEXT: %[[TMP2:.+]] = load i32, ptr %[[START_ADDR]], align 4 -// IR-NEXT: store i32 %[[TMP2]], ptr %[[DOTCAPTURE_EXPR_]], align 4 -// IR-NEXT: %[[TMP3:.+]] = load i32, ptr %[[END_ADDR]], align 4 -// IR-NEXT: store i32 %[[TMP3]], ptr %[[DOTCAPTURE_EXPR_1]], align 4 -// IR-NEXT: %[[TMP4:.+]] = load i32, ptr %[[STEP_ADDR]], align 4 -// IR-NEXT: store i32 %[[TMP4]], ptr %[[DOTCAPTURE_EXPR_2]], align 4 -// IR-NEXT: %[[TMP5:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_1]], align 4 -// IR-NEXT: %[[TMP6:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_]], align 4 -// IR-NEXT: %[[SUB:.+]] = sub i32 %[[TMP5]], %[[TMP6]] -// IR-NEXT: %[[SUB4:.+]] = sub i32 %[[SUB]], 1 -// IR-NEXT: %[[TMP7:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_2]], align 4 -// IR-NEXT: %[[ADD:.+]] = add i32 %[[SUB4]], %[[TMP7]] -// IR-NEXT: %[[TMP8:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_2]], align 4 -// IR-NEXT: %[[DIV:.+]] = udiv i32 %[[ADD]], %[[TMP8]] -// IR-NEXT: %[[SUB5:.+]] = sub i32 %[[DIV]], 1 -// IR-NEXT: store i32 %[[SUB5]], ptr %[[DOTCAPTURE_EXPR_3]], align 4 -// IR-NEXT: store i32 0, ptr %[[DOTUNROLLED_IV_I]], align 4 -// IR-NEXT: %[[TMP9:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_3]], align 4 -// IR-NEXT: %[[ADD7:.+]] = add i32 %[[TMP9]], 1 -// IR-NEXT: store i32 %[[ADD7]], ptr %[[DOTCAPTURE_EXPR_6]], align 4 -// IR-NEXT: %[[TMP10:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_6]], align 4 -// IR-NEXT: %[[SUB9:.+]] = sub i32 %[[TMP10]], -1 -// IR-NEXT: %[[DIV10:.+]] = udiv i32 %[[SUB9]], 2 -// IR-NEXT: %[[SUB11:.+]] = sub i32 %[[DIV10]], 1 -// IR-NEXT: store i32 %[[SUB11]], ptr %[[DOTCAPTURE_EXPR_8]], align 4 -// IR-NEXT: %[[TMP11:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_8]], align 4 -// IR-NEXT: %[[ADD13:.+]] = add i32 %[[TMP11]], 1 -// IR-NEXT: store i32 %[[ADD13]], ptr %[[DOTCAPTURE_EXPR_12]], align 4 -// IR-NEXT: %[[TMP12:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_12]], align 4 -// IR-NEXT: %[[SUB15:.+]] = sub i32 %[[TMP12]], -3 -// IR-NEXT: %[[DIV16:.+]] = udiv i32 %[[SUB15]], 4 -// IR-NEXT: %[[SUB17:.+]] = sub i32 %[[DIV16]], 1 -// IR-NEXT: store i32 %[[SUB17]], ptr %[[DOTCAPTURE_EXPR_14]], align 4 -// IR-NEXT: store i32 0, ptr %[[DOTFLOOR_0_IV__UNROLLED_IV_I]], align 4 -// IR-NEXT: %[[TMP13:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_12]], align 4 -// IR-NEXT: %[[CMP:.+]] = icmp ult i32 0, %[[TMP13]] -// IR-NEXT: br i1 %[[CMP]], label %[[OMP_PRECOND_THEN:.+]], label %[[OMP_PRECOND_END:.+]] -// IR-EMPTY: -// IR-NEXT: [[OMP_PRECOND_THEN]]: -// IR-NEXT: store i32 0, ptr %[[DOTOMP_LB]], align 4 -// IR-NEXT: %[[TMP14:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_14]], align 4 -// IR-NEXT: store i32 %[[TMP14]], ptr %[[DOTOMP_UB]], align 4 -// IR-NEXT: store i32 1, ptr %[[DOTOMP_STRIDE]], align 4 -// IR-NEXT: store i32 0, ptr %[[DOTOMP_IS_LAST]], align 4 -// IR-NEXT: call void @__kmpc_for_static_init_4u(ptr @1, i32 %[[TMP0]], i32 34, ptr %[[DOTOMP_IS_LAST]], ptr %[[DOTOMP_LB]], ptr %[[DOTOMP_UB]], ptr %[[DOTOMP_STRIDE]], i32 1, i32 1) -// IR-NEXT: %[[TMP15:.+]] = load i32, ptr %[[DOTOMP_UB]], align 4 -// IR-NEXT: %[[TMP16:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_14]], align 4 -// IR-NEXT: %[[CMP19:.+]] = icmp ugt i32 %[[TMP15]], %[[TMP16]] -// IR-NEXT: br i1 %[[CMP19]], label %[[COND_TRUE:.+]], label %[[COND_FALSE:.+]] -// IR-EMPTY: -// IR-NEXT: [[COND_TRUE]]: -// IR-NEXT: %[[TMP17:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_14]], align 4 -// IR-NEXT: br label %[[COND_END:.+]] -// IR-EMPTY: -// IR-NEXT: [[COND_FALSE]]: -// IR-NEXT: %[[TMP18:.+]] = load i32, ptr %[[DOTOMP_UB]], align 4 +// IR-LABEL: define dso_local void @func( +// IR-SAME: i32 noundef [[START:%.*]], i32 noundef [[END:%.*]], i32 noundef [[STEP:%.*]]) #[[ATTR0:[0-9]+]] { +// IR-NEXT: [[ENTRY:.*:]] +// IR-NEXT: [[START_ADDR:%.*]] = alloca i32, align 4 +// IR-NEXT: [[END_ADDR:%.*]] = alloca i32, align 4 +// IR-NEXT: [[STEP_ADDR:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// IR-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// IR-NEXT: [[I:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTNEW_STEP:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTUNROLLED_IV_I:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTCAPTURE_EXPR_7:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTTILE_0_IV__UNROLLED_IV_I:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTCAPTURE_EXPR_11:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTCAPTURE_EXPR_13:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTFLOOR_0_IV__UNROLLED_IV_I:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTFLOOR_0_IV__UNROLLED_IV_I17:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTTILE_CNT_0_IV__UNROLLED_IV_I:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTUNROLL_INNER_IV_I:%.*]] = alloca i32, align 4 +// IR-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) +// IR-NEXT: store i32 [[START]], ptr [[START_ADDR]], align 4 +// IR-NEXT: store i32 [[END]], ptr [[END_ADDR]], align 4 +// IR-NEXT: store i32 [[STEP]], ptr [[STEP_ADDR]], align 4 +// IR-NEXT: [[TMP1:%.*]] = load i32, ptr [[START_ADDR]], align 4 +// IR-NEXT: store i32 [[TMP1]], ptr [[I]], align 4 +// IR-NEXT: [[TMP2:%.*]] = load i32, ptr [[START_ADDR]], align 4 +// IR-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-NEXT: [[TMP3:%.*]] = load i32, ptr [[END_ADDR]], align 4 +// IR-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_1]], align 4 +// IR-NEXT: [[TMP4:%.*]] = load i32, ptr [[STEP_ADDR]], align 4 +// IR-NEXT: store i32 [[TMP4]], ptr [[DOTNEW_STEP]], align 4 +// IR-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// IR-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-NEXT: [[SUB:%.*]] = sub i32 [[TMP5]], [[TMP6]] +// IR-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1 +// IR-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 +// IR-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], [[TMP7]] +// IR-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 +// IR-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], [[TMP8]] +// IR-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1 +// IR-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4 +// IR-NEXT: store i32 0, ptr [[DOTUNROLLED_IV_I]], align 4 +// IR-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 +// IR-NEXT: [[ADD6:%.*]] = add i32 [[TMP9]], 1 +// IR-NEXT: store i32 [[ADD6]], ptr [[DOTCAPTURE_EXPR_5]], align 4 +// IR-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_5]], align 4 +// IR-NEXT: [[SUB8:%.*]] = sub i32 [[TMP10]], -1 +// IR-NEXT: [[DIV9:%.*]] = udiv i32 [[SUB8]], 2 +// IR-NEXT: [[SUB10:%.*]] = sub i32 [[DIV9]], 1 +// IR-NEXT: store i32 [[SUB10]], ptr [[DOTCAPTURE_EXPR_7]], align 4 +// IR-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_7]], align 4 +// IR-NEXT: [[ADD12:%.*]] = add i32 [[TMP11]], 1 +// IR-NEXT: store i32 [[ADD12]], ptr [[DOTCAPTURE_EXPR_11]], align 4 +// IR-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4 +// IR-NEXT: [[SUB14:%.*]] = sub i32 [[TMP12]], -3 +// IR-NEXT: [[DIV15:%.*]] = udiv i32 [[SUB14]], 4 +// IR-NEXT: [[SUB16:%.*]] = sub i32 [[DIV15]], 1 +// IR-NEXT: store i32 [[SUB16]], ptr [[DOTCAPTURE_EXPR_13]], align 4 +// IR-NEXT: store i32 0, ptr [[DOTFLOOR_0_IV__UNROLLED_IV_I]], align 4 +// IR-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_11]], align 4 +// IR-NEXT: [[CMP:%.*]] = icmp ult i32 0, [[TMP13]] +// IR-NEXT: br i1 [[CMP]], label %[[OMP_PRECOND_THEN:.*]], label %[[OMP_PRECOND_END:.*]] +// IR: [[OMP_PRECOND_THEN]]: +// IR-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 +// IR-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_13]], align 4 +// IR-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_UB]], align 4 +// IR-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 +// IR-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// IR-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// IR-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// IR-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_13]], align 4 +// IR-NEXT: [[CMP18:%.*]] = icmp ugt i32 [[TMP15]], [[TMP16]] +// IR-NEXT: br i1 [[CMP18]], label %[[COND_TRUE:.*]], label %[[COND_FALSE:.*]] +// IR: [[COND_TRUE]]: +// IR-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_13]], align 4 +// IR-NEXT: br label %[[COND_END:.*]] +// IR: [[COND_FALSE]]: +// IR-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // IR-NEXT: br label %[[COND_END]] -// IR-EMPTY: -// IR-NEXT: [[COND_END]]: -// IR-NEXT: %[[COND:.+]] = phi i32 [ %[[TMP17]], %[[COND_TRUE]] ], [ %[[TMP18]], %[[COND_FALSE]] ] -// IR-NEXT: store i32 %[[COND]], ptr %[[DOTOMP_UB]], align 4 -// IR-NEXT: %[[TMP19:.+]] = load i32, ptr %[[DOTOMP_LB]], align 4 -// IR-NEXT: store i32 %[[TMP19]], ptr %[[DOTOMP_IV]], align 4 -// IR-NEXT: br label %[[OMP_INNER_FOR_COND:.+]] -// IR-EMPTY: -// IR-NEXT: [[OMP_INNER_FOR_COND]]: -// IR-NEXT: %[[TMP20:.+]] = load i32, ptr %[[DOTOMP_IV]], align 4 -// IR-NEXT: %[[TMP21:.+]] = load i32, ptr %[[DOTOMP_UB]], align 4 -// IR-NEXT: %[[ADD20:.+]] = add i32 %[[TMP21]], 1 -// IR-NEXT: %[[CMP21:.+]] = icmp ult i32 %[[TMP20]], %[[ADD20]] -// IR-NEXT: br i1 %[[CMP21]], label %[[OMP_INNER_FOR_BODY:.+]], label %[[OMP_INNER_FOR_END:.+]] -// IR-EMPTY: -// IR-NEXT: [[OMP_INNER_FOR_BODY]]: -// IR-NEXT: %[[TMP22:.+]] = load i32, ptr %[[DOTOMP_IV]], align 4 -// IR-NEXT: %[[MUL:.+]] = mul i32 %[[TMP22]], 4 -// IR-NEXT: %[[ADD22:.+]] = add i32 0, %[[MUL]] -// IR-NEXT: store i32 %[[ADD22]], ptr %[[DOTFLOOR_0_IV__UNROLLED_IV_I18]], align 4 -// IR-NEXT: %[[TMP23:.+]] = load i32, ptr %[[DOTFLOOR_0_IV__UNROLLED_IV_I18]], align 4 -// IR-NEXT: store i32 %[[TMP23]], ptr %[[DOTTILE_0_IV__UNROLLED_IV_I]], align 4 -// IR-NEXT: br label %[[FOR_COND:.+]] -// IR-EMPTY: -// IR-NEXT: [[FOR_COND]]: -// IR-NEXT: %[[TMP24:.+]] = load i32, ptr %[[DOTTILE_0_IV__UNROLLED_IV_I]], align 4 -// IR-NEXT: %[[TMP25:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_8]], align 4 -// IR-NEXT: %[[ADD23:.+]] = add i32 %[[TMP25]], 1 -// IR-NEXT: %[[TMP26:.+]] = load i32, ptr %[[DOTFLOOR_0_IV__UNROLLED_IV_I18]], align 4 -// IR-NEXT: %[[ADD24:.+]] = add i32 %[[TMP26]], 4 -// IR-NEXT: %[[CMP25:.+]] = icmp ult i32 %[[ADD23]], %[[ADD24]] -// IR-NEXT: br i1 %[[CMP25]], label %[[COND_TRUE26:.+]], label %[[COND_FALSE28:.+]] -// IR-EMPTY: -// IR-NEXT: [[COND_TRUE26]]: -// IR-NEXT: %[[TMP27:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_8]], align 4 -// IR-NEXT: %[[ADD27:.+]] = add i32 %[[TMP27]], 1 -// IR-NEXT: br label %[[COND_END30:.+]] -// IR-EMPTY: -// IR-NEXT: [[COND_FALSE28]]: -// IR-NEXT: %[[TMP28:.+]] = load i32, ptr %[[DOTFLOOR_0_IV__UNROLLED_IV_I18]], align 4 -// IR-NEXT: %[[ADD29:.+]] = add i32 %[[TMP28]], 4 -// IR-NEXT: br label %[[COND_END30]] -// IR-EMPTY: -// IR-NEXT: [[COND_END30]]: -// IR-NEXT: %[[COND31:.+]] = phi i32 [ %[[ADD27]], %[[COND_TRUE26]] ], [ %[[ADD29]], %[[COND_FALSE28]] ] -// IR-NEXT: %[[CMP32:.+]] = icmp ult i32 %[[TMP24]], %[[COND31]] -// IR-NEXT: br i1 %[[CMP32]], label %[[FOR_BODY:.+]], label %[[FOR_END45:.+]] -// IR-EMPTY: -// IR-NEXT: [[FOR_BODY]]: -// IR-NEXT: %[[TMP29:.+]] = load i32, ptr %[[DOTTILE_0_IV__UNROLLED_IV_I]], align 4 -// IR-NEXT: %[[MUL33:.+]] = mul i32 %[[TMP29]], 2 -// IR-NEXT: %[[ADD34:.+]] = add i32 0, %[[MUL33]] -// IR-NEXT: store i32 %[[ADD34]], ptr %[[DOTUNROLLED_IV_I]], align 4 -// IR-NEXT: %[[TMP30:.+]] = load i32, ptr %[[DOTUNROLLED_IV_I]], align 4 -// IR-NEXT: store i32 %[[TMP30]], ptr %[[DOTUNROLL_INNER_IV_I]], align 4 -// IR-NEXT: br label %[[FOR_COND35:.+]] -// IR-EMPTY: -// IR-NEXT: [[FOR_COND35]]: -// IR-NEXT: %[[TMP31:.+]] = load i32, ptr %[[DOTUNROLL_INNER_IV_I]], align 4 -// IR-NEXT: %[[TMP32:.+]] = load i32, ptr %[[DOTUNROLLED_IV_I]], align 4 -// IR-NEXT: %[[ADD36:.+]] = add i32 %[[TMP32]], 2 -// IR-NEXT: %[[CMP37:.+]] = icmp ult i32 %[[TMP31]], %[[ADD36]] -// IR-NEXT: br i1 %[[CMP37]], label %[[LAND_RHS:.+]], label %[[LAND_END:.+]] -// IR-EMPTY: -// IR-NEXT: [[LAND_RHS]]: -// IR-NEXT: %[[TMP33:.+]] = load i32, ptr %[[DOTUNROLL_INNER_IV_I]], align 4 -// IR-NEXT: %[[TMP34:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_3]], align 4 -// IR-NEXT: %[[ADD38:.+]] = add i32 %[[TMP34]], 1 -// IR-NEXT: %[[CMP39:.+]] = icmp ult i32 %[[TMP33]], %[[ADD38]] +// IR: [[COND_END]]: +// IR-NEXT: [[COND:%.*]] = phi i32 [ [[TMP17]], %[[COND_TRUE]] ], [ [[TMP18]], %[[COND_FALSE]] ] +// IR-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 +// IR-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 +// IR-NEXT: store i32 [[TMP19]], ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: br label %[[OMP_INNER_FOR_COND:.*]] +// IR: [[OMP_INNER_FOR_COND]]: +// IR-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// IR-NEXT: [[ADD19:%.*]] = add i32 [[TMP21]], 1 +// IR-NEXT: [[CMP20:%.*]] = icmp ult i32 [[TMP20]], [[ADD19]] +// IR-NEXT: br i1 [[CMP20]], label %[[OMP_INNER_FOR_BODY:.*]], label %[[OMP_INNER_FOR_END:.*]] +// IR: [[OMP_INNER_FOR_BODY]]: +// IR-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: [[MUL:%.*]] = mul i32 [[TMP22]], 4 +// IR-NEXT: [[ADD21:%.*]] = add i32 0, [[MUL]] +// IR-NEXT: store i32 [[ADD21]], ptr [[DOTFLOOR_0_IV__UNROLLED_IV_I17]], align 4 +// IR-NEXT: store i32 0, ptr [[DOTTILE_CNT_0_IV__UNROLLED_IV_I]], align 4 +// IR-NEXT: br label %[[FOR_COND:.*]] +// IR: [[FOR_COND]]: +// IR-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTTILE_CNT_0_IV__UNROLLED_IV_I]], align 4 +// IR-NEXT: [[CMP22:%.*]] = icmp ult i32 [[TMP23]], 4 +// IR-NEXT: br i1 [[CMP22]], label %[[FOR_BODY:.*]], label %[[FOR_END38:.*]] +// IR: [[FOR_BODY]]: +// IR-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTFLOOR_0_IV__UNROLLED_IV_I17]], align 4 +// IR-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTTILE_CNT_0_IV__UNROLLED_IV_I]], align 4 +// IR-NEXT: [[ADD23:%.*]] = add i32 [[TMP24]], [[TMP25]] +// IR-NEXT: store i32 [[ADD23]], ptr [[DOTTILE_0_IV__UNROLLED_IV_I]], align 4 +// IR-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTTILE_0_IV__UNROLLED_IV_I]], align 4 +// IR-NEXT: [[MUL24:%.*]] = mul i32 [[TMP26]], 2 +// IR-NEXT: [[ADD25:%.*]] = add i32 0, [[MUL24]] +// IR-NEXT: store i32 [[ADD25]], ptr [[DOTUNROLLED_IV_I]], align 4 +// IR-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTTILE_0_IV__UNROLLED_IV_I]], align 4 +// IR-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_7]], align 4 +// IR-NEXT: [[ADD26:%.*]] = add i32 [[TMP28]], 1 +// IR-NEXT: [[CMP27:%.*]] = icmp ult i32 [[TMP27]], [[ADD26]] +// IR-NEXT: br i1 [[CMP27]], label %[[IF_THEN:.*]], label %[[IF_END:.*]] +// IR: [[IF_THEN]]: +// IR-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTUNROLLED_IV_I]], align 4 +// IR-NEXT: store i32 [[TMP29]], ptr [[DOTUNROLL_INNER_IV_I]], align 4 +// IR-NEXT: br label %[[FOR_COND28:.*]] +// IR: [[FOR_COND28]]: +// IR-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTUNROLL_INNER_IV_I]], align 4 +// IR-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTUNROLLED_IV_I]], align 4 +// IR-NEXT: [[ADD29:%.*]] = add i32 [[TMP31]], 2 +// IR-NEXT: [[CMP30:%.*]] = icmp ult i32 [[TMP30]], [[ADD29]] +// IR-NEXT: br i1 [[CMP30]], label %[[LAND_RHS:.*]], label %[[LAND_END:.*]] +// IR: [[LAND_RHS]]: +// IR-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTUNROLL_INNER_IV_I]], align 4 +// IR-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 +// IR-NEXT: [[ADD31:%.*]] = add i32 [[TMP33]], 1 +// IR-NEXT: [[CMP32:%.*]] = icmp ult i32 [[TMP32]], [[ADD31]] // IR-NEXT: br label %[[LAND_END]] -// IR-EMPTY: -// IR-NEXT: [[LAND_END]]: -// IR-NEXT: %[[TMP35:.+]] = phi i1 [ false, %[[FOR_COND35]] ], [ %[[CMP39]], %[[LAND_RHS]] ] -// IR-NEXT: br i1 %[[TMP35]], label %[[FOR_BODY40:.+]], label %[[FOR_END:.+]] -// IR-EMPTY: -// IR-NEXT: [[FOR_BODY40]]: -// IR-NEXT: %[[TMP36:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_]], align 4 -// IR-NEXT: %[[TMP37:.+]] = load i32, ptr %[[DOTUNROLL_INNER_IV_I]], align 4 -// IR-NEXT: %[[TMP38:.+]] = load i32, ptr %[[DOTCAPTURE_EXPR_2]], align 4 -// IR-NEXT: %[[MUL41:.+]] = mul i32 %[[TMP37]], %[[TMP38]] -// IR-NEXT: %[[ADD42:.+]] = add i32 %[[TMP36]], %[[MUL41]] -// IR-NEXT: store i32 %[[ADD42]], ptr %[[I]], align 4 -// IR-NEXT: %[[TMP39:.+]] = load i32, ptr %[[START_ADDR]], align 4 -// IR-NEXT: %[[TMP40:.+]] = load i32, ptr %[[END_ADDR]], align 4 -// IR-NEXT: %[[TMP41:.+]] = load i32, ptr %[[STEP_ADDR]], align 4 -// IR-NEXT: %[[TMP42:.+]] = load i32, ptr %[[I]], align 4 -// IR-NEXT: call void (...) @body(i32 noundef %[[TMP39]], i32 noundef %[[TMP40]], i32 noundef %[[TMP41]], i32 noundef %[[TMP42]]) -// IR-NEXT: br label %[[FOR_INC:.+]] -// IR-EMPTY: -// IR-NEXT: [[FOR_INC]]: -// IR-NEXT: %[[TMP43:.+]] = load i32, ptr %[[DOTUNROLL_INNER_IV_I]], align 4 -// IR-NEXT: %[[INC:.+]] = add i32 %[[TMP43]], 1 -// IR-NEXT: store i32 %[[INC]], ptr %[[DOTUNROLL_INNER_IV_I]], align 4 -// IR-NEXT: br label %[[FOR_COND35]], !llvm.loop ![[LOOP2:[0-9]+]] -// IR-EMPTY: -// IR-NEXT: [[FOR_END]]: -// IR-NEXT: br label %[[FOR_INC43:.+]] -// IR-EMPTY: -// IR-NEXT: [[FOR_INC43]]: -// IR-NEXT: %[[TMP44:.+]] = load i32, ptr %[[DOTTILE_0_IV__UNROLLED_IV_I]], align 4 -// IR-NEXT: %[[INC44:.+]] = add i32 %[[TMP44]], 1 -// IR-NEXT: store i32 %[[INC44]], ptr %[[DOTTILE_0_IV__UNROLLED_IV_I]], align 4 -// IR-NEXT: br label %[[FOR_COND]], !llvm.loop ![[LOOP5:[0-9]+]] -// IR-EMPTY: -// IR-NEXT: [[FOR_END45]]: -// IR-NEXT: br label %[[OMP_BODY_CONTINUE:.+]] -// IR-EMPTY: -// IR-NEXT: [[OMP_BODY_CONTINUE]]: -// IR-NEXT: br label %[[OMP_INNER_FOR_INC:.+]] -// IR-EMPTY: -// IR-NEXT: [[OMP_INNER_FOR_INC]]: -// IR-NEXT: %[[TMP45:.+]] = load i32, ptr %[[DOTOMP_IV]], align 4 -// IR-NEXT: %[[ADD46:.+]] = add i32 %[[TMP45]], 1 -// IR-NEXT: store i32 %[[ADD46]], ptr %[[DOTOMP_IV]], align 4 +// IR: [[LAND_END]]: +// IR-NEXT: [[TMP34:%.*]] = phi i1 [ false, %[[FOR_COND28]] ], [ [[CMP32]], %[[LAND_RHS]] ] +// IR-NEXT: br i1 [[TMP34]], label %[[FOR_BODY33:.*]], label %[[FOR_END:.*]] +// IR: [[FOR_BODY33]]: +// IR-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTUNROLL_INNER_IV_I]], align 4 +// IR-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTNEW_STEP]], align 4 +// IR-NEXT: [[MUL34:%.*]] = mul i32 [[TMP36]], [[TMP37]] +// IR-NEXT: [[ADD35:%.*]] = add i32 [[TMP35]], [[MUL34]] +// IR-NEXT: store i32 [[ADD35]], ptr [[I]], align 4 +// IR-NEXT: [[TMP38:%.*]] = load i32, ptr [[START_ADDR]], align 4 +// IR-NEXT: [[TMP39:%.*]] = load i32, ptr [[END_ADDR]], align 4 +// IR-NEXT: [[TMP40:%.*]] = load i32, ptr [[STEP_ADDR]], align 4 +// IR-NEXT: [[TMP41:%.*]] = load i32, ptr [[I]], align 4 +// IR-NEXT: call void (...) @body(i32 noundef [[TMP38]], i32 noundef [[TMP39]], i32 noundef [[TMP40]], i32 noundef [[TMP41]]) +// IR-NEXT: br label %[[FOR_INC:.*]] +// IR: [[FOR_INC]]: +// IR-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTUNROLL_INNER_IV_I]], align 4 +// IR-NEXT: [[INC:%.*]] = add i32 [[TMP42]], 1 +// IR-NEXT: store i32 [[INC]], ptr [[DOTUNROLL_INNER_IV_I]], align 4 +// IR-NEXT: br label %[[FOR_COND28]], !llvm.loop [[LOOP2:![0-9]+]] +// IR: [[FOR_END]]: +// IR-NEXT: br label %[[IF_END]] +// IR: [[IF_END]]: +// IR-NEXT: br label %[[FOR_INC36:.*]] +// IR: [[FOR_INC36]]: +// IR-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTTILE_CNT_0_IV__UNROLLED_IV_I]], align 4 +// IR-NEXT: [[INC37:%.*]] = add i32 [[TMP43]], 1 +// IR-NEXT: store i32 [[INC37]], ptr [[DOTTILE_CNT_0_IV__UNROLLED_IV_I]], align 4 +// IR-NEXT: br label %[[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// IR: [[FOR_END38]]: +// IR-NEXT: br label %[[OMP_BODY_CONTINUE:.*]] +// IR: [[OMP_BODY_CONTINUE]]: +// IR-NEXT: br label %[[OMP_INNER_FOR_INC:.*]] +// IR: [[OMP_INNER_FOR_INC]]: +// IR-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: [[ADD39:%.*]] = add i32 [[TMP44]], 1 +// IR-NEXT: store i32 [[ADD39]], ptr [[DOTOMP_IV]], align 4 // IR-NEXT: br label %[[OMP_INNER_FOR_COND]] -// IR-EMPTY: -// IR-NEXT: [[OMP_INNER_FOR_END]]: -// IR-NEXT: br label %[[OMP_LOOP_EXIT:.+]] -// IR-EMPTY: -// IR-NEXT: [[OMP_LOOP_EXIT]]: -// IR-NEXT: call void @__kmpc_for_static_fini(ptr @1, i32 %[[TMP0]]) +// IR: [[OMP_INNER_FOR_END]]: +// IR-NEXT: br label %[[OMP_LOOP_EXIT:.*]] +// IR: [[OMP_LOOP_EXIT]]: +// IR-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]]) // IR-NEXT: br label %[[OMP_PRECOND_END]] -// IR-EMPTY: -// IR-NEXT: [[OMP_PRECOND_END]]: -// IR-NEXT: call void @__kmpc_barrier(ptr @3, i32 %[[TMP0]]) +// IR: [[OMP_PRECOND_END]]: +// IR-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP0]]) // IR-NEXT: ret void -// IR-NEXT: } +// extern "C" void func(int start, int end, int step) { #pragma omp for #pragma omp tile sizes(4) @@ -239,7 +213,9 @@ extern "C" void func(int start, int end, int step) { #endif /* HEADER */ -// IR: ![[LOOP2]] = distinct !{![[LOOP2]], ![[LOOPPROP3:[0-9]+]], ![[LOOPPROP4:[0-9]+]]} -// IR: ![[LOOPPROP3]] = !{!"llvm.loop.mustprogress"} -// IR: ![[LOOPPROP4]] = !{!"llvm.loop.unroll.count", i32 2} -// IR: ![[LOOP5]] = distinct !{![[LOOP5]], ![[LOOPPROP3]]} +//. +// IR: [[LOOP2]] = distinct !{[[LOOP2]], [[META3:![0-9]+]], [[META4:![0-9]+]]} +// IR: [[META3]] = !{!"llvm.loop.mustprogress"} +// IR: [[META4]] = !{!"llvm.loop.unroll.count", i32 2} +// IR: [[LOOP5]] = distinct !{[[LOOP5]], [[META3]]} +//. diff --git a/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp b/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp index 125620bd49502..bdc8c6ce7158c 100644 --- a/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp +++ b/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp @@ -6539,7 +6539,7 @@ OpenMPIRBuilder::tileLoops(DebugLoc DL, ArrayRef Loops, // Compute the trip counts of the floor loops. Builder.SetCurrentDebugLocation(DL); Builder.restoreIP(OutermostLoop->getPreheaderIP()); - SmallVector FloorCompleteCount, FloorCount, FloorRems; + SmallVector FloorCount; for (int i = 0; i < NumLoops; ++i) { Value *TileSize = TileSizes[i]; Value *OrigTripCount = OrigTripCounts[i]; @@ -6563,10 +6563,7 @@ OpenMPIRBuilder::tileLoops(DebugLoc DL, ArrayRef Loops, Builder.CreateAdd(FloorCompleteTripCount, FloorTripOverflow, "omp_floor" + Twine(i) + ".tripcount", true); - // Remember some values for later use. - FloorCompleteCount.push_back(FloorCompleteTripCount); FloorCount.push_back(FloorTripCount); - FloorRems.push_back(FloorTripRem); } // Generate the new loop nest, from the outermost to the innermost. @@ -6610,23 +6607,10 @@ OpenMPIRBuilder::tileLoops(DebugLoc DL, ArrayRef Loops, EmbeddNewLoops(FloorCount, "floor"); - // Within the innermost floor loop, emit the code that computes the tile - // sizes. - Builder.SetInsertPoint(Enter->getTerminator()); - SmallVector TileCounts; - for (int i = 0; i < NumLoops; ++i) { - CanonicalLoopInfo *FloorLoop = Result[i]; - Value *TileSize = TileSizes[i]; - - Value *FloorIsEpilogue = - Builder.CreateICmpEQ(FloorLoop->getIndVar(), FloorCompleteCount[i]); - Value *TileTripCount = - Builder.CreateSelect(FloorIsEpilogue, FloorRems[i], TileSize); - - TileCounts.push_back(TileTripCount); - } - - // Create the tile loops. + // Create the tile loops with rectangular (constant) trip counts equal to + // the tile sizes. A validity predicate in the body guards against + // out-of-bounds iterations in the remainder tile. + SmallVector TileCounts(TileSizes.begin(), TileSizes.end()); EmbeddNewLoops(TileCounts, "tile"); // Insert the inbetween code into the body. @@ -6655,6 +6639,7 @@ OpenMPIRBuilder::tileLoops(DebugLoc DL, ArrayRef Loops, // Replace the original induction variable with an induction variable computed // from the tile and floor induction variables. Builder.restoreIP(Result.back()->getBodyIP()); + SmallVector ShiftValues; for (int i = 0; i < NumLoops; ++i) { CanonicalLoopInfo *FloorLoop = Result[i]; CanonicalLoopInfo *TileLoop = Result[NumLoops + i]; @@ -6666,18 +6651,47 @@ OpenMPIRBuilder::tileLoops(DebugLoc DL, ArrayRef Loops, Value *Shift = Builder.CreateAdd(Scale, TileLoop->getIndVar(), {}, /*HasNUW=*/true); OrigIndVar->replaceAllUsesWith(Shift); + ShiftValues.push_back(Shift); + } + + // Build a validity predicate: for each tiled dimension, check that the + // computed original index is within the original trip count. This guards + // against executing out-of-bounds iterations in the remainder tile. + Value *Pred = nullptr; + for (int i = 0; i < NumLoops; ++i) { + Value *DimPred = Builder.CreateICmpULT(ShiftValues[i], OrigTripCounts[i], + "omp_tile" + Twine(i) + ".inbounds"); + Pred = Pred ? Builder.CreateAnd(Pred, DimPred) : DimPred; } + // Insert the conditional guard: split the body flow so that out-of-bounds + // iterations skip directly to a merge block before the tile latch. + BasicBlock *TileBodyBB = Builder.GetInsertBlock(); + Instruction *BodyTerm = TileBodyBB->getTerminator(); + BasicBlock *BodySucc = cast(BodyTerm)->getSuccessor(0); + BasicBlock *TileLatch = Result.back()->getLatch(); + + BasicBlock *MergeBB = + BasicBlock::Create(F->getContext(), "omp_tile.body.merge", F, TileLatch); + Builder.SetInsertPoint(MergeBB); + Builder.CreateBr(TileLatch); + + // Redirect the body chain's exit from the tile latch to the merge block. + for (BasicBlock *PredBB : llvm::make_early_inc_range(predecessors(TileLatch))) + if (PredBB != MergeBB) + PredBB->getTerminator()->replaceUsesOfWith(TileLatch, MergeBB); + + // Replace the tile body's unconditional branch with a conditional one. + BodyTerm->eraseFromParent(); + Builder.SetInsertPoint(TileBodyBB); + Builder.CreateCondBr(Pred, BodySucc, MergeBB); + // Remove unused parts of the original loops. removeUnusedBlocksFromParent(OldControlBBs); for (CanonicalLoopInfo *L : Loops) L->invalidate(); -#ifndef NDEBUG - for (CanonicalLoopInfo *GenL : Result) - GenL->assertOK(); -#endif return Result; } diff --git a/llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp b/llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp index 5b9b280ec7671..3f68242e6620b 100644 --- a/llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp +++ b/llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp @@ -1618,12 +1618,27 @@ TEST_F(OpenMPIRBuilderTest, TileSingleLoop) { CanonicalLoopInfo *Floor = GenLoops[0]; CanonicalLoopInfo *Tile = GenLoops[1]; + // The merge block sits between the body code and the tile latch. + BasicBlock *MergeBB = Tile->getLatch()->getSinglePredecessor(); + ASSERT_NE(MergeBB, nullptr); + BasicBlock *RefOrder[] = { - Floor->getPreheader(), Floor->getHeader(), Floor->getCond(), - Floor->getBody(), Tile->getPreheader(), Tile->getHeader(), - Tile->getCond(), Tile->getBody(), BodyCode, - Tile->getLatch(), Tile->getExit(), Tile->getAfter(), - Floor->getLatch(), Floor->getExit(), Floor->getAfter(), + Floor->getPreheader(), + Floor->getHeader(), + Floor->getCond(), + Floor->getBody(), + Tile->getPreheader(), + Tile->getHeader(), + Tile->getCond(), + Tile->getBody(), + BodyCode, + MergeBB, + Tile->getLatch(), + Tile->getExit(), + Tile->getAfter(), + Floor->getLatch(), + Floor->getExit(), + Floor->getAfter(), }; EXPECT_TRUE(verifyDFSOrder(F, RefOrder)); EXPECT_TRUE(verifyListOrder(F, RefOrder)); @@ -1693,6 +1708,10 @@ TEST_F(OpenMPIRBuilderTest, TileNestedLoops) { CanonicalLoopInfo *Tile1 = GenLoops[2]; CanonicalLoopInfo *Tile2 = GenLoops[3]; + // The merge block sits between the body code and the innermost tile latch. + BasicBlock *MergeBB = Tile2->getLatch()->getSinglePredecessor(); + ASSERT_NE(MergeBB, nullptr); + BasicBlock *RefOrder[] = { Floor1->getPreheader(), Floor1->getHeader(), @@ -1711,6 +1730,7 @@ TEST_F(OpenMPIRBuilderTest, TileNestedLoops) { Tile2->getCond(), Tile2->getBody(), BodyCode, + MergeBB, Tile2->getLatch(), Tile2->getExit(), Tile2->getAfter(), @@ -1801,6 +1821,10 @@ TEST_F(OpenMPIRBuilderTest, TileNestedLoopsWithBounds) { CanonicalLoopInfo *Tile0 = GenLoops[2]; CanonicalLoopInfo *Tile1 = GenLoops[3]; + // The merge block sits between the body code and the innermost tile latch. + BasicBlock *MergeBB = Tile1->getLatch()->getSinglePredecessor(); + ASSERT_NE(MergeBB, nullptr); + BasicBlock *RefOrder[] = { Floor0->getPreheader(), Floor0->getHeader(), @@ -1819,6 +1843,7 @@ TEST_F(OpenMPIRBuilderTest, TileNestedLoopsWithBounds) { Tile1->getCond(), Tile1->getBody(), BodyCode, + MergeBB, Tile1->getLatch(), Tile1->getExit(), Tile1->getAfter(), diff --git a/mlir/test/Target/LLVMIR/openmp-cli-tile01.mlir b/mlir/test/Target/LLVMIR/openmp-cli-tile01.mlir index 0d559b69a3ad1..948a9815851a5 100644 --- a/mlir/test/Target/LLVMIR/openmp-cli-tile01.mlir +++ b/mlir/test/Target/LLVMIR/openmp-cli-tile01.mlir @@ -38,8 +38,6 @@ llvm.func @tile_trivial_loop(%baseptr: !llvm.ptr, %tc: i32, %ts: i32) -> () { // CHECK-NEXT: br i1 %[[OMP_FLOOR0_CMP:.+]], label %[[OMP_FLOOR0_BODY:.+]], label %[[OMP_FLOOR0_EXIT:.+]] // CHECK-EMPTY: // CHECK-NEXT: [[OMP_FLOOR0_BODY]]: -// CHECK-NEXT: %[[TMP8:.+]] = icmp eq i32 %[[OMP_FLOOR0_IV:.+]], %[[TMP4:.+]] -// CHECK-NEXT: %[[TMP9:.+]] = select i1 %[[TMP8:.+]], i32 %[[TMP5:.+]], i32 %[[TMP2:.+]] // CHECK-NEXT: br label %[[OMP_TILE0_PREHEADER:.+]] // CHECK-EMPTY: // CHECK-NEXT: [[OMP_TILE0_PREHEADER]]: @@ -50,23 +48,27 @@ llvm.func @tile_trivial_loop(%baseptr: !llvm.ptr, %tc: i32, %ts: i32) -> () { // CHECK-NEXT: br label %[[OMP_TILE0_COND:.+]] // CHECK-EMPTY: // CHECK-NEXT: [[OMP_TILE0_COND]]: -// CHECK-NEXT: %[[OMP_TILE0_CMP:.+]] = icmp ult i32 %[[OMP_TILE0_IV:.+]], %[[TMP9:.+]] +// CHECK-NEXT: %[[OMP_TILE0_CMP:.+]] = icmp ult i32 %[[OMP_TILE0_IV:.+]], %[[TMP2:.+]] // CHECK-NEXT: br i1 %[[OMP_TILE0_CMP:.+]], label %[[OMP_TILE0_BODY:.+]], label %[[OMP_TILE0_EXIT:.+]] // CHECK-EMPTY: // CHECK-NEXT: [[OMP_TILE0_BODY]]: -// CHECK-NEXT: %[[TMP10:.+]] = mul nuw i32 %[[TMP2:.+]], %[[OMP_FLOOR0_IV:.+]] -// CHECK-NEXT: %[[TMP11:.+]] = add nuw i32 %[[TMP10:.+]], %[[OMP_TILE0_IV:.+]] -// CHECK-NEXT: br label %[[OMP_OMP_LOOP_BODY:.+]] +// CHECK-NEXT: %[[TMP8:.+]] = mul nuw i32 %[[TMP2:.+]], %[[OMP_FLOOR0_IV:.+]] +// CHECK-NEXT: %[[TMP9:.+]] = add nuw i32 %[[TMP8:.+]], %[[OMP_TILE0_IV:.+]] +// CHECK-NEXT: %[[OMP_TILE0_INBOUNDS:.+]] = icmp ult i32 %[[TMP9:.+]], %[[TMP1:.+]] +// CHECK-NEXT: br i1 %[[OMP_TILE0_INBOUNDS:.+]], label %[[OMP_OMP_LOOP_BODY:.+]], label %[[OMP_TILE_BODY_MERGE:.+]] // CHECK-EMPTY: // CHECK-NEXT: [[OMP_OMP_LOOP_BODY]]: // CHECK-NEXT: br label %[[OMP_LOOP_REGION:.+]] // CHECK-EMPTY: // CHECK-NEXT: [[OMP_LOOP_REGION]]: -// CHECK-NEXT: %[[TMP12:.+]] = getelementptr inbounds float, ptr %[[TMP0:.+]], i32 %[[TMP11:.+]] -// CHECK-NEXT: store float 4.200000e+01, ptr %[[TMP12:.+]], align 4 +// CHECK-NEXT: %[[TMP10:.+]] = getelementptr inbounds float, ptr %[[TMP0:.+]], i32 %[[TMP9:.+]] +// CHECK-NEXT: store float 4.200000e+01, ptr %[[TMP10:.+]], align 4 // CHECK-NEXT: br label %[[OMP_REGION_CONT:.+]] // CHECK-EMPTY: // CHECK-NEXT: [[OMP_REGION_CONT]]: +// CHECK-NEXT: br label %[[OMP_TILE_BODY_MERGE:.+]] +// CHECK-EMPTY: +// CHECK-NEXT: [[OMP_TILE_BODY_MERGE]]: // CHECK-NEXT: br label %[[OMP_TILE0_INC:.+]] // CHECK-EMPTY: // CHECK-NEXT: [[OMP_TILE0_INC]]: diff --git a/mlir/test/Target/LLVMIR/openmp-cli-tile02.mlir b/mlir/test/Target/LLVMIR/openmp-cli-tile02.mlir index 22c2973164159..59ffa50037f4b 100644 --- a/mlir/test/Target/LLVMIR/openmp-cli-tile02.mlir +++ b/mlir/test/Target/LLVMIR/openmp-cli-tile02.mlir @@ -79,10 +79,6 @@ llvm.func @tile_2d_loop(%baseptr: !llvm.ptr, %tc1: i32, %tc2: i32, %ts1: i32, %t // CHECK-NEXT: br i1 %[[OMP_FLOOR1_CMP:.+]], label %[[OMP_FLOOR1_BODY:.+]], label %[[OMP_FLOOR1_EXIT:.+]] // CHECK-EMPTY: // CHECK-NEXT: [[OMP_FLOOR1_BODY]]: -// CHECK-NEXT: %[[TMP14:.+]] = icmp eq i32 %[[OMP_FLOOR0_IV:.+]], %[[TMP6:.+]] -// CHECK-NEXT: %[[TMP15:.+]] = select i1 %[[TMP14:.+]], i32 %[[TMP7:.+]], i32 %[[TMP3:.+]] -// CHECK-NEXT: %[[TMP16:.+]] = icmp eq i32 %[[OMP_FLOOR1_IV:.+]], %[[TMP10:.+]] -// CHECK-NEXT: %[[TMP17:.+]] = select i1 %[[TMP16:.+]], i32 %[[TMP11:.+]], i32 %[[TMP4:.+]] // CHECK-NEXT: br label %[[OMP_TILE0_PREHEADER:.+]] // CHECK-EMPTY: // CHECK-NEXT: [[OMP_TILE0_PREHEADER]]: @@ -93,7 +89,7 @@ llvm.func @tile_2d_loop(%baseptr: !llvm.ptr, %tc1: i32, %tc2: i32, %ts1: i32, %t // CHECK-NEXT: br label %[[OMP_TILE0_COND:.+]] // CHECK-EMPTY: // CHECK-NEXT: [[OMP_TILE0_COND]]: -// CHECK-NEXT: %[[OMP_TILE0_CMP:.+]] = icmp ult i32 %[[OMP_TILE0_IV:.+]], %[[TMP15:.+]] +// CHECK-NEXT: %[[OMP_TILE0_CMP:.+]] = icmp ult i32 %[[OMP_TILE0_IV:.+]], %[[TMP3:.+]] // CHECK-NEXT: br i1 %[[OMP_TILE0_CMP:.+]], label %[[OMP_TILE0_BODY:.+]], label %[[OMP_TILE0_EXIT:.+]] // CHECK-EMPTY: // CHECK-NEXT: [[OMP_TILE0_BODY]]: @@ -107,26 +103,32 @@ llvm.func @tile_2d_loop(%baseptr: !llvm.ptr, %tc1: i32, %tc2: i32, %ts1: i32, %t // CHECK-NEXT: br label %[[OMP_TILE1_COND:.+]] // CHECK-EMPTY: // CHECK-NEXT: [[OMP_TILE1_COND]]: -// CHECK-NEXT: %[[OMP_TILE1_CMP:.+]] = icmp ult i32 %[[OMP_TILE1_IV:.+]], %[[TMP17:.+]] +// CHECK-NEXT: %[[OMP_TILE1_CMP:.+]] = icmp ult i32 %[[OMP_TILE1_IV:.+]], %[[TMP4:.+]] // CHECK-NEXT: br i1 %[[OMP_TILE1_CMP:.+]], label %[[OMP_TILE1_BODY:.+]], label %[[OMP_TILE1_EXIT:.+]] // CHECK-EMPTY: // CHECK-NEXT: [[OMP_TILE1_BODY]]: -// CHECK-NEXT: %[[TMP18:.+]] = mul nuw i32 %[[TMP3:.+]], %[[OMP_FLOOR0_IV:.+]] -// CHECK-NEXT: %[[TMP19:.+]] = add nuw i32 %[[TMP18:.+]], %[[OMP_TILE0_IV:.+]] -// CHECK-NEXT: %[[TMP20:.+]] = mul nuw i32 %[[TMP4:.+]], %[[OMP_FLOOR1_IV:.+]] -// CHECK-NEXT: %[[TMP21:.+]] = add nuw i32 %[[TMP20:.+]], %[[OMP_TILE1_IV:.+]] -// CHECK-NEXT: br label %[[OMP_OMP_LOOP_BODY:.+]] +// CHECK-NEXT: %[[TMP14:.+]] = mul nuw i32 %[[TMP3:.+]], %[[OMP_FLOOR0_IV:.+]] +// CHECK-NEXT: %[[TMP15:.+]] = add nuw i32 %[[TMP14:.+]], %[[OMP_TILE0_IV:.+]] +// CHECK-NEXT: %[[TMP16:.+]] = mul nuw i32 %[[TMP4:.+]], %[[OMP_FLOOR1_IV:.+]] +// CHECK-NEXT: %[[TMP17:.+]] = add nuw i32 %[[TMP16:.+]], %[[OMP_TILE1_IV:.+]] +// CHECK-NEXT: %[[OMP_TILE0_INBOUNDS:.+]] = icmp ult i32 %[[TMP15:.+]], %[[TMP1:.+]] +// CHECK-NEXT: %[[OMP_TILE1_INBOUNDS:.+]] = icmp ult i32 %[[TMP17:.+]], %[[TMP2:.+]] +// CHECK-NEXT: %[[OMP_TILE_PRED:.+]] = and i1 %[[OMP_TILE0_INBOUNDS:.+]], %[[OMP_TILE1_INBOUNDS:.+]] +// CHECK-NEXT: br i1 %[[OMP_TILE_PRED:.+]], label %[[OMP_OMP_LOOP_BODY:.+]], label %[[OMP_TILE_BODY_MERGE:.+]] // CHECK-EMPTY: // CHECK-NEXT: [[OMP_OMP_LOOP_BODY4]]: // CHECK-NEXT: br label %[[OMP_LOOP_REGION12:.+]] // CHECK-EMPTY: // CHECK-NEXT: [[OMP_LOOP_REGION12]]: -// CHECK-NEXT: %[[TMP22:.+]] = add i32 %[[TMP19:.+]], %[[TMP21:.+]] -// CHECK-NEXT: %[[TMP23:.+]] = getelementptr inbounds float, ptr %[[TMP0:.+]], i32 %[[TMP22:.+]] -// CHECK-NEXT: store float 4.200000e+01, ptr %[[TMP23:.+]], align 4 +// CHECK-NEXT: %[[TMP18:.+]] = add i32 %[[TMP15:.+]], %[[TMP17:.+]] +// CHECK-NEXT: %[[TMP19:.+]] = getelementptr inbounds float, ptr %[[TMP0:.+]], i32 %[[TMP18:.+]] +// CHECK-NEXT: store float 4.200000e+01, ptr %[[TMP19:.+]], align 4 // CHECK-NEXT: br label %[[OMP_REGION_CONT11:.+]] // CHECK-EMPTY: // CHECK-NEXT: [[OMP_REGION_CONT11]]: +// CHECK-NEXT: br label %[[OMP_TILE_BODY_MERGE:.+]] +// CHECK-EMPTY: +// CHECK-NEXT: [[OMP_TILE_BODY_MERGE]]: // CHECK-NEXT: br label %[[OMP_TILE1_INC:.+]] // CHECK-EMPTY: // CHECK-NEXT: [[OMP_TILE1_INC]]: diff --git a/mlir/test/Target/LLVMIR/openmp-cli-tile03.mlir b/mlir/test/Target/LLVMIR/openmp-cli-tile03.mlir index 0747ff8909362..fcc37af2ca8f3 100644 --- a/mlir/test/Target/LLVMIR/openmp-cli-tile03.mlir +++ b/mlir/test/Target/LLVMIR/openmp-cli-tile03.mlir @@ -56,8 +56,6 @@ llvm.func @tile_composition(%baseptr: !llvm.ptr, %tc: i32, %ts: i32, %grid_ts: i // CHECK-NEXT: br i1 %[[OMP_FLOOR0_CMP10:.+]], label %[[OMP_FLOOR0_BODY5:.+]], label %[[OMP_FLOOR0_EXIT7:.+]] // CHECK-EMPTY: // CHECK-NEXT: [[OMP_FLOOR0_BODY5]]: -// CHECK-NEXT: %[[TMP14:.+]] = icmp eq i32 %[[OMP_FLOOR0_IV9:.+]], %[[TMP10:.+]] -// CHECK-NEXT: %[[TMP15:.+]] = select i1 %[[TMP14:.+]], i32 %[[TMP11:.+]], i32 %[[TMP3:.+]] // CHECK-NEXT: br label %[[OMP_TILE0_PREHEADER12:.+]] // CHECK-EMPTY: // CHECK-NEXT: [[OMP_TILE0_PREHEADER12]]: @@ -68,83 +66,88 @@ llvm.func @tile_composition(%baseptr: !llvm.ptr, %tc: i32, %ts: i32, %grid_ts: i // CHECK-NEXT: br label %[[OMP_TILE0_COND14:.+]] // CHECK-EMPTY: // CHECK-NEXT: [[OMP_TILE0_COND14]]: -// CHECK-NEXT: %[[OMP_TILE0_CMP20:.+]] = icmp ult i32 %[[OMP_TILE0_IV19:.+]], %[[TMP15:.+]] +// CHECK-NEXT: %[[OMP_TILE0_CMP20:.+]] = icmp ult i32 %[[OMP_TILE0_IV19:.+]], %[[TMP3:.+]] // CHECK-NEXT: br i1 %[[OMP_TILE0_CMP20:.+]], label %[[OMP_TILE0_BODY15:.+]], label %[[OMP_TILE0_EXIT17:.+]] // CHECK-EMPTY: // CHECK-NEXT: [[OMP_TILE0_BODY15]]: -// CHECK-NEXT: %[[TMP16:.+]] = mul nuw i32 %[[TMP3:.+]], %[[OMP_FLOOR0_IV9:.+]] -// CHECK-NEXT: %[[TMP17:.+]] = add nuw i32 %[[TMP16:.+]], %[[OMP_TILE0_IV19:.+]] -// CHECK-NEXT: br label %[[OMP_FLOOR0_BODY:.+]] -// CHECK-EMPTY: -// CHECK-NEXT: [[OMP_FLOOR0_BODY]]: -// CHECK-NEXT: %[[TMP18:.+]] = icmp eq i32 %[[TMP17:.+]], %[[TMP6:.+]] -// CHECK-NEXT: %[[TMP19:.+]] = select i1 %[[TMP18:.+]], i32 %[[TMP7:.+]], i32 %[[TMP2:.+]] -// CHECK-NEXT: br label %[[OMP_TILE0_PREHEADER:.+]] -// CHECK-EMPTY: -// CHECK-NEXT: [[OMP_TILE0_PREHEADER]]: -// CHECK-NEXT: %[[TMP20:.+]] = udiv i32 %[[TMP19:.+]], %[[TMP4:.+]] -// CHECK-NEXT: %[[TMP21:.+]] = urem i32 %[[TMP19:.+]], %[[TMP4:.+]] -// CHECK-NEXT: %[[TMP22:.+]] = icmp ne i32 %[[TMP21:.+]], 0 -// CHECK-NEXT: %[[TMP23:.+]] = zext i1 %[[TMP22:.+]] to i32 -// CHECK-NEXT: %[[OMP_FLOOR0_TRIPCOUNT22:.+]] = add nuw i32 %[[TMP20:.+]], %[[TMP23:.+]] -// CHECK-NEXT: br label %[[OMP_FLOOR0_PREHEADER23:.+]] -// CHECK-EMPTY: -// CHECK-NEXT: [[OMP_FLOOR0_PREHEADER23]]: +// CHECK-NEXT: %[[TMP14:.+]] = mul nuw i32 %[[TMP3:.+]], %[[OMP_FLOOR0_IV9:.+]] +// CHECK-NEXT: %[[TMP15:.+]] = add nuw i32 %[[TMP14:.+]], %[[OMP_TILE0_IV19:.+]] +// CHECK-NEXT: %[[OMP_TILE0_INBOUNDS22:.+]] = icmp ult i32 %[[TMP15:.+]], %[[OMP_FLOOR0_TRIPCOUNT:.+]] +// CHECK-NEXT: br i1 %[[OMP_TILE0_INBOUNDS22:.+]], label %[[OMP_FLOOR_INNER_ENTRY:.+]], label %[[OMP_TILE_BODY_MERGE23:.+]] +// CHECK-EMPTY: +// CHECK-NEXT: [[OMP_FLOOR_INNER_ENTRY]]: +// CHECK-NEXT: br label %[[OMP_TILE0_PREHEADER_INNER:.+]] +// CHECK-EMPTY: +// CHECK-NEXT: [[OMP_TILE0_PREHEADER_INNER]]: +// CHECK-NEXT: %[[TMP16:.+]] = udiv i32 %[[TMP2:.+]], %[[TMP4:.+]] +// CHECK-NEXT: %[[TMP17:.+]] = urem i32 %[[TMP2:.+]], %[[TMP4:.+]] +// CHECK-NEXT: %[[TMP18:.+]] = icmp ne i32 %[[TMP17:.+]], 0 +// CHECK-NEXT: %[[TMP19:.+]] = zext i1 %[[TMP18:.+]] to i32 +// CHECK-NEXT: %[[OMP_FLOOR0_TRIPCOUNT24:.+]] = add nuw i32 %[[TMP16:.+]], %[[TMP19:.+]] +// CHECK-NEXT: br label %[[OMP_FLOOR0_PREHEADER25:.+]] +// CHECK-EMPTY: +// CHECK-NEXT: [[OMP_FLOOR0_PREHEADER25]]: // CHECK-NEXT: br label %[[OMP_FLOOR0_HEADER:.+]] // CHECK-EMPTY: // CHECK-NEXT: [[OMP_FLOOR0_HEADER]]: -// CHECK-NEXT: %[[OMP_FLOOR0_IV:.+]] = phi i32 [ 0, %[[OMP_FLOOR0_PREHEADER23:.+]] ], [ %[[OMP_FLOOR0_NEXT:.+]], %[[OMP_FLOOR0_INC:.+]] ] +// CHECK-NEXT: %[[OMP_FLOOR0_IV:.+]] = phi i32 [ 0, %[[OMP_FLOOR0_PREHEADER25:.+]] ], [ %[[OMP_FLOOR0_NEXT:.+]], %[[OMP_FLOOR0_INC:.+]] ] // CHECK-NEXT: br label %[[OMP_FLOOR0_COND:.+]] // CHECK-EMPTY: // CHECK-NEXT: [[OMP_FLOOR0_COND]]: -// CHECK-NEXT: %[[OMP_FLOOR0_CMP:.+]] = icmp ult i32 %[[OMP_FLOOR0_IV:.+]], %[[OMP_FLOOR0_TRIPCOUNT22:.+]] -// CHECK-NEXT: br i1 %[[OMP_FLOOR0_CMP:.+]], label %[[OMP_FLOOR0_BODY24:.+]], label %[[OMP_FLOOR0_EXIT:.+]] +// CHECK-NEXT: %[[OMP_FLOOR0_CMP:.+]] = icmp ult i32 %[[OMP_FLOOR0_IV:.+]], %[[OMP_FLOOR0_TRIPCOUNT24:.+]] +// CHECK-NEXT: br i1 %[[OMP_FLOOR0_CMP:.+]], label %[[OMP_FLOOR0_BODY26:.+]], label %[[OMP_FLOOR0_EXIT:.+]] // CHECK-EMPTY: -// CHECK-NEXT: [[OMP_FLOOR0_BODY24]]: -// CHECK-NEXT: %[[TMP24:.+]] = icmp eq i32 %[[OMP_FLOOR0_IV:.+]], %[[TMP20:.+]] -// CHECK-NEXT: %[[TMP25:.+]] = select i1 %[[TMP24:.+]], i32 %[[TMP21:.+]], i32 %[[TMP4:.+]] -// CHECK-NEXT: br label %[[OMP_TILE0_PREHEADER26:.+]] +// CHECK-NEXT: [[OMP_FLOOR0_BODY26]]: +// CHECK-NEXT: br label %[[OMP_TILE0_PREHEADER28:.+]] // CHECK-EMPTY: -// CHECK-NEXT: [[OMP_TILE0_PREHEADER26]]: -// CHECK-NEXT: br label %[[OMP_TILE0_HEADER27:.+]] +// CHECK-NEXT: [[OMP_TILE0_PREHEADER28]]: +// CHECK-NEXT: br label %[[OMP_TILE0_HEADER29:.+]] // CHECK-EMPTY: -// CHECK-NEXT: [[OMP_TILE0_HEADER27]]: -// CHECK-NEXT: %[[OMP_TILE0_IV33:.+]] = phi i32 [ 0, %[[OMP_TILE0_PREHEADER26:.+]] ], [ %[[OMP_TILE0_NEXT35:.+]], %[[OMP_TILE0_INC30:.+]] ] -// CHECK-NEXT: br label %[[OMP_TILE0_COND28:.+]] +// CHECK-NEXT: [[OMP_TILE0_HEADER29]]: +// CHECK-NEXT: %[[OMP_TILE0_IV35:.+]] = phi i32 [ 0, %[[OMP_TILE0_PREHEADER28:.+]] ], [ %[[OMP_TILE0_NEXT37:.+]], %[[OMP_TILE0_INC32:.+]] ] +// CHECK-NEXT: br label %[[OMP_TILE0_COND30:.+]] // CHECK-EMPTY: -// CHECK-NEXT: [[OMP_TILE0_COND28]]: -// CHECK-NEXT: %[[OMP_TILE0_CMP34:.+]] = icmp ult i32 %[[OMP_TILE0_IV33:.+]], %[[TMP25:.+]] -// CHECK-NEXT: br i1 %[[OMP_TILE0_CMP34:.+]], label %[[OMP_TILE0_BODY29:.+]], label %[[OMP_TILE0_EXIT31:.+]] +// CHECK-NEXT: [[OMP_TILE0_COND30]]: +// CHECK-NEXT: %[[OMP_TILE0_CMP36:.+]] = icmp ult i32 %[[OMP_TILE0_IV35:.+]], %[[TMP4:.+]] +// CHECK-NEXT: br i1 %[[OMP_TILE0_CMP36:.+]], label %[[OMP_TILE0_BODY31:.+]], label %[[OMP_TILE0_EXIT33:.+]] // CHECK-EMPTY: -// CHECK-NEXT: [[OMP_TILE0_BODY29]]: -// CHECK-NEXT: %[[TMP26:.+]] = mul nuw i32 %[[TMP4:.+]], %[[OMP_FLOOR0_IV:.+]] -// CHECK-NEXT: %[[TMP27:.+]] = add nuw i32 %[[TMP26:.+]], %[[OMP_TILE0_IV33:.+]] -// CHECK-NEXT: br label %[[OMP_TILE0_BODY:.+]] +// CHECK-NEXT: [[OMP_TILE0_BODY31]]: +// CHECK-NEXT: %[[TMP20:.+]] = mul nuw i32 %[[TMP4:.+]], %[[OMP_FLOOR0_IV:.+]] +// CHECK-NEXT: %[[TMP21:.+]] = add nuw i32 %[[TMP20:.+]], %[[OMP_TILE0_IV35:.+]] +// CHECK-NEXT: %[[OMP_TILE0_INBOUNDS38:.+]] = icmp ult i32 %[[TMP21:.+]], %[[TMP2:.+]] +// CHECK-NEXT: br i1 %[[OMP_TILE0_INBOUNDS38:.+]], label %[[OMP_TILE0_BODY_STORE:.+]], label %[[OMP_TILE_BODY_MERGE39:.+]] // CHECK-EMPTY: -// CHECK-NEXT: [[OMP_TILE0_BODY]]: -// CHECK-NEXT: %[[TMP28:.+]] = mul nuw i32 %[[TMP2:.+]], %[[TMP17:.+]] -// CHECK-NEXT: %[[TMP29:.+]] = add nuw i32 %[[TMP28:.+]], %[[TMP27:.+]] -// CHECK-NEXT: br label %[[OMP_OMP_LOOP_BODY:.+]] +// CHECK-NEXT: [[OMP_TILE0_BODY_STORE]]: +// CHECK-NEXT: %[[TMP22:.+]] = mul nuw i32 %[[TMP2:.+]], %[[TMP15:.+]] +// CHECK-NEXT: %[[TMP23:.+]] = add nuw i32 %[[TMP22:.+]], %[[TMP21:.+]] +// CHECK-NEXT: %[[OMP_TILE0_INBOUNDS:.+]] = icmp ult i32 %[[TMP23:.+]], %[[TMP1:.+]] +// CHECK-NEXT: br i1 %[[OMP_TILE0_INBOUNDS:.+]], label %[[OMP_OMP_LOOP_BODY:.+]], label %[[OMP_TILE_BODY_MERGE:.+]] // CHECK-EMPTY: // CHECK-NEXT: [[OMP_OMP_LOOP_BODY]]: // CHECK-NEXT: br label %[[OMP_LOOP_REGION:.+]] // CHECK-EMPTY: // CHECK-NEXT: [[OMP_LOOP_REGION]]: -// CHECK-NEXT: %[[TMP30:.+]] = getelementptr inbounds float, ptr %[[TMP0:.+]], i32 %[[TMP29:.+]] -// CHECK-NEXT: store float 4.200000e+01, ptr %[[TMP30:.+]], align 4 +// CHECK-NEXT: %[[TMP24:.+]] = getelementptr inbounds float, ptr %[[TMP0:.+]], i32 %[[TMP23:.+]] +// CHECK-NEXT: store float 4.200000e+01, ptr %[[TMP24:.+]], align 4 // CHECK-NEXT: br label %[[OMP_REGION_CONT:.+]] // CHECK-EMPTY: // CHECK-NEXT: [[OMP_REGION_CONT]]: -// CHECK-NEXT: br label %[[OMP_TILE0_INC30:.+]] +// CHECK-NEXT: br label %[[OMP_TILE_BODY_MERGE:.+]] // CHECK-EMPTY: -// CHECK-NEXT: [[OMP_TILE0_INC30]]: -// CHECK-NEXT: %[[OMP_TILE0_NEXT35:.+]] = add nuw i32 %[[OMP_TILE0_IV33:.+]], 1 -// CHECK-NEXT: br label %[[OMP_TILE0_HEADER27:.+]] +// CHECK-NEXT: [[OMP_TILE_BODY_MERGE]]: +// CHECK-NEXT: br label %[[OMP_TILE_BODY_MERGE39:.+]] // CHECK-EMPTY: -// CHECK-NEXT: [[OMP_TILE0_EXIT31]]: -// CHECK-NEXT: br label %[[OMP_TILE0_AFTER32:.+]] +// CHECK-NEXT: [[OMP_TILE_BODY_MERGE39]]: +// CHECK-NEXT: br label %[[OMP_TILE0_INC32:.+]] // CHECK-EMPTY: -// CHECK-NEXT: [[OMP_TILE0_AFTER32]]: +// CHECK-NEXT: [[OMP_TILE0_INC32]]: +// CHECK-NEXT: %[[OMP_TILE0_NEXT37:.+]] = add nuw i32 %[[OMP_TILE0_IV35:.+]], 1 +// CHECK-NEXT: br label %[[OMP_TILE0_HEADER29:.+]] +// CHECK-EMPTY: +// CHECK-NEXT: [[OMP_TILE0_EXIT33]]: +// CHECK-NEXT: br label %[[OMP_TILE0_AFTER34:.+]] +// CHECK-EMPTY: +// CHECK-NEXT: [[OMP_TILE0_AFTER34]]: // CHECK-NEXT: br label %[[OMP_FLOOR0_INC:.+]] // CHECK-EMPTY: // CHECK-NEXT: [[OMP_FLOOR0_INC]]: @@ -152,12 +155,15 @@ llvm.func @tile_composition(%baseptr: !llvm.ptr, %tc: i32, %ts: i32, %grid_ts: i // CHECK-NEXT: br label %[[OMP_FLOOR0_HEADER:.+]] // CHECK-EMPTY: // CHECK-NEXT: [[OMP_FLOOR0_EXIT]]: -// CHECK-NEXT: br label %[[OMP_FLOOR0_AFTER25:.+]] +// CHECK-NEXT: br label %[[OMP_FLOOR0_AFTER27:.+]] +// CHECK-EMPTY: +// CHECK-NEXT: [[OMP_FLOOR0_AFTER27]]: +// CHECK-NEXT: br label %[[OMP_TILE0_AFTER_INNER:.+]] // CHECK-EMPTY: -// CHECK-NEXT: [[OMP_FLOOR0_AFTER25]]: -// CHECK-NEXT: br label %[[OMP_TILE0_AFTER:.+]] +// CHECK-NEXT: [[OMP_TILE0_AFTER_INNER]]: +// CHECK-NEXT: br label %[[OMP_TILE_BODY_MERGE23:.+]] // CHECK-EMPTY: -// CHECK-NEXT: [[OMP_TILE0_AFTER]]: +// CHECK-NEXT: [[OMP_TILE_BODY_MERGE23]]: // CHECK-NEXT: br label %[[OMP_TILE0_INC16:.+]] // CHECK-EMPTY: // CHECK-NEXT: [[OMP_TILE0_INC16]]: diff --git a/openmp/runtime/test/transform/tile/foreach.cpp b/openmp/runtime/test/transform/tile/foreach.cpp index 4fb3595760974..17031a4acf187 100644 --- a/openmp/runtime/test/transform/tile/foreach.cpp +++ b/openmp/runtime/test/transform/tile/foreach.cpp @@ -182,6 +182,10 @@ int main() { // CHECK-NEXT: [B] iterator deref: 2 // CHECK-NEXT: v=0 w=2 // CHECK-NEXT: [B] iterator dtor +// CHECK-NEXT: [B] iterator advance: 0 += 3 +// CHECK-NEXT: [B] iterator move assign +// CHECK-NEXT: [B] iterator deref: 3 +// CHECK-NEXT: [B] iterator dtor // CHECK-NEXT: [A] iterator dtor // CHECK-NEXT: [A] iterator advance: 0 += 1 // CHECK-NEXT: [A] iterator move assign @@ -191,6 +195,10 @@ int main() { // CHECK-NEXT: [B] iterator deref: 2 // CHECK-NEXT: v=1 w=2 // CHECK-NEXT: [B] iterator dtor +// CHECK-NEXT: [B] iterator advance: 0 += 3 +// CHECK-NEXT: [B] iterator move assign +// CHECK-NEXT: [B] iterator deref: 3 +// CHECK-NEXT: [B] iterator dtor // CHECK-NEXT: [A] iterator dtor // CHECK-NEXT: [A] iterator advance: 0 += 2 // CHECK-NEXT: [A] iterator move assign @@ -206,6 +214,18 @@ int main() { // CHECK-NEXT: v=2 w=1 // CHECK-NEXT: [B] iterator dtor // CHECK-NEXT: [A] iterator dtor +// CHECK-NEXT: [A] iterator advance: 0 += 3 +// CHECK-NEXT: [A] iterator move assign +// CHECK-NEXT: [A] iterator deref: 3 +// CHECK-NEXT: [B] iterator advance: 0 += 0 +// CHECK-NEXT: [B] iterator move assign +// CHECK-NEXT: [B] iterator deref: 0 +// CHECK-NEXT: [B] iterator dtor +// CHECK-NEXT: [B] iterator advance: 0 += 1 +// CHECK-NEXT: [B] iterator move assign +// CHECK-NEXT: [B] iterator deref: 1 +// CHECK-NEXT: [B] iterator dtor +// CHECK-NEXT: [A] iterator dtor // CHECK-NEXT: [A] iterator advance: 0 += 2 // CHECK-NEXT: [A] iterator move assign // CHECK-NEXT: [A] iterator deref: 2 @@ -214,6 +234,22 @@ int main() { // CHECK-NEXT: [B] iterator deref: 2 // CHECK-NEXT: v=2 w=2 // CHECK-NEXT: [B] iterator dtor +// CHECK-NEXT: [B] iterator advance: 0 += 3 +// CHECK-NEXT: [B] iterator move assign +// CHECK-NEXT: [B] iterator deref: 3 +// CHECK-NEXT: [B] iterator dtor +// CHECK-NEXT: [A] iterator dtor +// CHECK-NEXT: [A] iterator advance: 0 += 3 +// CHECK-NEXT: [A] iterator move assign +// CHECK-NEXT: [A] iterator deref: 3 +// CHECK-NEXT: [B] iterator advance: 0 += 2 +// CHECK-NEXT: [B] iterator move assign +// CHECK-NEXT: [B] iterator deref: 2 +// CHECK-NEXT: [B] iterator dtor +// CHECK-NEXT: [B] iterator advance: 0 += 3 +// CHECK-NEXT: [B] iterator move assign +// CHECK-NEXT: [B] iterator deref: 3 +// CHECK-NEXT: [B] iterator dtor // CHECK-NEXT: [A] iterator dtor // CHECK-NEXT: [B] iterator dtor // CHECK-NEXT: [B] iterator dtor diff --git a/openmp/runtime/test/transform/tile/intfor.c b/openmp/runtime/test/transform/tile/intfor.c index 4a930eab6730a..e980165277b79 100644 --- a/openmp/runtime/test/transform/tile/intfor.c +++ b/openmp/runtime/test/transform/tile/intfor.c @@ -30,77 +30,85 @@ int main() { // CHECK: do // CHECK-NEXT: tilesize(1) // CHECK-NEXT: tilesize(1) -// CHECK-NEXT: tilesize(1) -// CHECK-NEXT: tilesize(1) // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) +// CHECK-NEXT: i=7 j=7 // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) -// CHECK-NEXT: i=7 j=7 +// CHECK-NEXT: i=7 j=10 // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) +// CHECK-NEXT: i=7 j=13 // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) -// CHECK-NEXT: i=7 j=10 +// CHECK-NEXT: tilesize(1) +// CHECK-NEXT: tilesize(1) // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) +// CHECK-NEXT: i=10 j=7 // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) -// CHECK-NEXT: i=7 j=13 +// CHECK-NEXT: i=10 j=10 // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) +// CHECK-NEXT: i=10 j=13 // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(1) // CHECK-NEXT: tilesize(1) -// CHECK-NEXT: tilesize(1) -// CHECK-NEXT: tilesize(1) // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) +// CHECK-NEXT: i=13 j=7 // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) -// CHECK-NEXT: i=10 j=7 +// CHECK-NEXT: i=13 j=10 +// CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) +// CHECK-NEXT: i=13 j=13 // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) +// CHECK-NEXT: tilesize(1) +// CHECK-NEXT: tilesize(1) // CHECK-NEXT: tilesize(2) -// CHECK-NEXT: i=10 j=10 // CHECK-NEXT: tilesize(2) +// CHECK-NEXT: tilesize(1) +// CHECK-NEXT: tilesize(1) // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) +// CHECK-NEXT: i=7 j=16 // CHECK-NEXT: tilesize(2) -// CHECK-NEXT: i=10 j=13 +// CHECK-NEXT: tilesize(2) +// CHECK-NEXT: i=7 j=19 // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) -// CHECK-NEXT: tilesize(1) -// CHECK-NEXT: tilesize(1) // CHECK-NEXT: tilesize(1) // CHECK-NEXT: tilesize(1) // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) +// CHECK-NEXT: i=10 j=16 // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) -// CHECK-NEXT: i=13 j=7 +// CHECK-NEXT: i=10 j=19 // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) -// CHECK-NEXT: i=13 j=10 +// CHECK-NEXT: tilesize(1) +// CHECK-NEXT: tilesize(1) // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) +// CHECK-NEXT: i=13 j=16 // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) -// CHECK-NEXT: i=13 j=13 +// CHECK-NEXT: i=13 j=19 // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(1) // CHECK-NEXT: tilesize(1) -// CHECK-NEXT: tilesize(1) -// CHECK-NEXT: tilesize(1) // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(1) @@ -109,61 +117,57 @@ int main() { // CHECK-NEXT: tilesize(1) // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) -// CHECK-NEXT: i=7 j=16 +// CHECK-NEXT: i=16 j=7 // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) -// CHECK-NEXT: i=7 j=19 +// CHECK-NEXT: i=16 j=10 +// CHECK-NEXT: tilesize(2) +// CHECK-NEXT: tilesize(2) +// CHECK-NEXT: i=16 j=13 // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) -// CHECK-NEXT: tilesize(1) -// CHECK-NEXT: tilesize(1) // CHECK-NEXT: tilesize(1) // CHECK-NEXT: tilesize(1) // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) -// CHECK-NEXT: i=10 j=16 // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) -// CHECK-NEXT: i=10 j=19 // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) -// CHECK-NEXT: tilesize(1) -// CHECK-NEXT: tilesize(1) +// CHECK-NEXT: tilesize(2) +// CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(1) // CHECK-NEXT: tilesize(1) // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) -// CHECK-NEXT: i=13 j=16 // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) -// CHECK-NEXT: i=13 j=19 // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) -// CHECK-NEXT: tilesize(1) -// CHECK-NEXT: tilesize(1) -// CHECK-NEXT: tilesize(1) -// CHECK-NEXT: tilesize(1) // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(1) // CHECK-NEXT: tilesize(1) +// CHECK-NEXT: tilesize(2) +// CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(1) // CHECK-NEXT: tilesize(1) // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) +// CHECK-NEXT: i=16 j=16 // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) -// CHECK-NEXT: i=16 j=7 +// CHECK-NEXT: i=16 j=19 // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) -// CHECK-NEXT: i=16 j=10 +// CHECK-NEXT: tilesize(1) +// CHECK-NEXT: tilesize(1) // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) -// CHECK-NEXT: i=16 j=13 // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) @@ -172,14 +176,10 @@ int main() { // CHECK-NEXT: tilesize(1) // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) -// CHECK-NEXT: tilesize(1) -// CHECK-NEXT: tilesize(1) // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) -// CHECK-NEXT: i=16 j=16 // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) -// CHECK-NEXT: i=16 j=19 // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(1) @@ -188,4 +188,4 @@ int main() { // CHECK-NEXT: tilesize(2) // CHECK-NEXT: tilesize(1) // CHECK-NEXT: tilesize(1) -// CHECK-NEXT: done \ No newline at end of file +// CHECK-NEXT: done diff --git a/openmp/runtime/test/transform/tile/iterfor.cpp b/openmp/runtime/test/transform/tile/iterfor.cpp index 05b5677bf9c4f..d07b10b3e841a 100644 --- a/openmp/runtime/test/transform/tile/iterfor.cpp +++ b/openmp/runtime/test/transform/tile/iterfor.cpp @@ -190,6 +190,9 @@ int main() { // CHECK-NEXT: [B] iterator deref: 2 // CHECK-NEXT: i=0 j=2 // CHECK-NEXT: [B] iterator dtor +// CHECK-NEXT: [B] iterator advance: 0 += 3 +// CHECK-NEXT: [B] iterator move assign +// CHECK-NEXT: [B] iterator dtor // CHECK-NEXT: [A] iterator dtor // CHECK-NEXT: [A] iterator advance: 0 += 1 // CHECK-NEXT: [A] iterator move assign @@ -199,6 +202,9 @@ int main() { // CHECK-NEXT: [B] iterator deref: 2 // CHECK-NEXT: i=1 j=2 // CHECK-NEXT: [B] iterator dtor +// CHECK-NEXT: [B] iterator advance: 0 += 3 +// CHECK-NEXT: [B] iterator move assign +// CHECK-NEXT: [B] iterator dtor // CHECK-NEXT: [A] iterator dtor // CHECK-NEXT: [A] iterator advance: 0 += 2 // CHECK-NEXT: [A] iterator move assign @@ -215,6 +221,15 @@ int main() { // CHECK-NEXT: i=2 j=1 // CHECK-NEXT: [B] iterator dtor // CHECK-NEXT: [A] iterator dtor +// CHECK-NEXT: [A] iterator advance: 0 += 3 +// CHECK-NEXT: [A] iterator move assign +// CHECK-NEXT: [B] iterator advance: 0 += 0 +// CHECK-NEXT: [B] iterator move assign +// CHECK-NEXT: [B] iterator dtor +// CHECK-NEXT: [B] iterator advance: 0 += 1 +// CHECK-NEXT: [B] iterator move assign +// CHECK-NEXT: [B] iterator dtor +// CHECK-NEXT: [A] iterator dtor // CHECK-NEXT: [A] iterator advance: 0 += 2 // CHECK-NEXT: [A] iterator move assign // CHECK-NEXT: [B] iterator advance: 0 += 2 @@ -223,6 +238,18 @@ int main() { // CHECK-NEXT: [B] iterator deref: 2 // CHECK-NEXT: i=2 j=2 // CHECK-NEXT: [B] iterator dtor +// CHECK-NEXT: [B] iterator advance: 0 += 3 +// CHECK-NEXT: [B] iterator move assign +// CHECK-NEXT: [B] iterator dtor +// CHECK-NEXT: [A] iterator dtor +// CHECK-NEXT: [A] iterator advance: 0 += 3 +// CHECK-NEXT: [A] iterator move assign +// CHECK-NEXT: [B] iterator advance: 0 += 2 +// CHECK-NEXT: [B] iterator move assign +// CHECK-NEXT: [B] iterator dtor +// CHECK-NEXT: [B] iterator advance: 0 += 3 +// CHECK-NEXT: [B] iterator move assign +// CHECK-NEXT: [B] iterator dtor // CHECK-NEXT: [A] iterator dtor // CHECK-NEXT: [B] iterator dtor // CHECK-NEXT: [B] iterator dtor diff --git a/openmp/runtime/test/transform/tile/parallel-wsloop-collapse-foreach.cpp b/openmp/runtime/test/transform/tile/parallel-wsloop-collapse-foreach.cpp index b1f4d98a52ddc..966ff7f84f548 100644 --- a/openmp/runtime/test/transform/tile/parallel-wsloop-collapse-foreach.cpp +++ b/openmp/runtime/test/transform/tile/parallel-wsloop-collapse-foreach.cpp @@ -182,6 +182,10 @@ int main() { // CHECK-NEXT: [B] iterator deref: 2 // CHECK-NEXT: i=0 v=0 w=2 // CHECK-NEXT: [B] iterator dtor +// CHECK-NEXT: [B] iterator advance: 0 += 3 +// CHECK-NEXT: [B] iterator move assign +// CHECK-NEXT: [B] iterator deref: 3 +// CHECK-NEXT: [B] iterator dtor // CHECK-NEXT: [A] iterator dtor // CHECK-NEXT: [A] iterator advance: 0 += 1 // CHECK-NEXT: [A] iterator move assign @@ -191,6 +195,10 @@ int main() { // CHECK-NEXT: [B] iterator deref: 2 // CHECK-NEXT: i=0 v=1 w=2 // CHECK-NEXT: [B] iterator dtor +// CHECK-NEXT: [B] iterator advance: 0 += 3 +// CHECK-NEXT: [B] iterator move assign +// CHECK-NEXT: [B] iterator deref: 3 +// CHECK-NEXT: [B] iterator dtor // CHECK-NEXT: [A] iterator dtor // CHECK-NEXT: [A] iterator advance: 0 += 2 // CHECK-NEXT: [A] iterator move assign @@ -206,6 +214,18 @@ int main() { // CHECK-NEXT: i=0 v=2 w=1 // CHECK-NEXT: [B] iterator dtor // CHECK-NEXT: [A] iterator dtor +// CHECK-NEXT: [A] iterator advance: 0 += 3 +// CHECK-NEXT: [A] iterator move assign +// CHECK-NEXT: [A] iterator deref: 3 +// CHECK-NEXT: [B] iterator advance: 0 += 0 +// CHECK-NEXT: [B] iterator move assign +// CHECK-NEXT: [B] iterator deref: 0 +// CHECK-NEXT: [B] iterator dtor +// CHECK-NEXT: [B] iterator advance: 0 += 1 +// CHECK-NEXT: [B] iterator move assign +// CHECK-NEXT: [B] iterator deref: 1 +// CHECK-NEXT: [B] iterator dtor +// CHECK-NEXT: [A] iterator dtor // CHECK-NEXT: [A] iterator advance: 0 += 2 // CHECK-NEXT: [A] iterator move assign // CHECK-NEXT: [A] iterator deref: 2 @@ -214,6 +234,22 @@ int main() { // CHECK-NEXT: [B] iterator deref: 2 // CHECK-NEXT: i=0 v=2 w=2 // CHECK-NEXT: [B] iterator dtor +// CHECK-NEXT: [B] iterator advance: 0 += 3 +// CHECK-NEXT: [B] iterator move assign +// CHECK-NEXT: [B] iterator deref: 3 +// CHECK-NEXT: [B] iterator dtor +// CHECK-NEXT: [A] iterator dtor +// CHECK-NEXT: [A] iterator advance: 0 += 3 +// CHECK-NEXT: [A] iterator move assign +// CHECK-NEXT: [A] iterator deref: 3 +// CHECK-NEXT: [B] iterator advance: 0 += 2 +// CHECK-NEXT: [B] iterator move assign +// CHECK-NEXT: [B] iterator deref: 2 +// CHECK-NEXT: [B] iterator dtor +// CHECK-NEXT: [B] iterator advance: 0 += 3 +// CHECK-NEXT: [B] iterator move assign +// CHECK-NEXT: [B] iterator deref: 3 +// CHECK-NEXT: [B] iterator dtor // CHECK-NEXT: [A] iterator dtor // CHECK-NEXT: [A] iterator advance: 0 += 0 // CHECK-NEXT: [A] iterator move assign @@ -251,6 +287,10 @@ int main() { // CHECK-NEXT: [B] iterator deref: 2 // CHECK-NEXT: i=1 v=0 w=2 // CHECK-NEXT: [B] iterator dtor +// CHECK-NEXT: [B] iterator advance: 0 += 3 +// CHECK-NEXT: [B] iterator move assign +// CHECK-NEXT: [B] iterator deref: 3 +// CHECK-NEXT: [B] iterator dtor // CHECK-NEXT: [A] iterator dtor // CHECK-NEXT: [A] iterator advance: 0 += 1 // CHECK-NEXT: [A] iterator move assign @@ -260,6 +300,10 @@ int main() { // CHECK-NEXT: [B] iterator deref: 2 // CHECK-NEXT: i=1 v=1 w=2 // CHECK-NEXT: [B] iterator dtor +// CHECK-NEXT: [B] iterator advance: 0 += 3 +// CHECK-NEXT: [B] iterator move assign +// CHECK-NEXT: [B] iterator deref: 3 +// CHECK-NEXT: [B] iterator dtor // CHECK-NEXT: [A] iterator dtor // CHECK-NEXT: [A] iterator advance: 0 += 2 // CHECK-NEXT: [A] iterator move assign @@ -275,6 +319,18 @@ int main() { // CHECK-NEXT: i=1 v=2 w=1 // CHECK-NEXT: [B] iterator dtor // CHECK-NEXT: [A] iterator dtor +// CHECK-NEXT: [A] iterator advance: 0 += 3 +// CHECK-NEXT: [A] iterator move assign +// CHECK-NEXT: [A] iterator deref: 3 +// CHECK-NEXT: [B] iterator advance: 0 += 0 +// CHECK-NEXT: [B] iterator move assign +// CHECK-NEXT: [B] iterator deref: 0 +// CHECK-NEXT: [B] iterator dtor +// CHECK-NEXT: [B] iterator advance: 0 += 1 +// CHECK-NEXT: [B] iterator move assign +// CHECK-NEXT: [B] iterator deref: 1 +// CHECK-NEXT: [B] iterator dtor +// CHECK-NEXT: [A] iterator dtor // CHECK-NEXT: [A] iterator advance: 0 += 2 // CHECK-NEXT: [A] iterator move assign // CHECK-NEXT: [A] iterator deref: 2 @@ -283,6 +339,22 @@ int main() { // CHECK-NEXT: [B] iterator deref: 2 // CHECK-NEXT: i=1 v=2 w=2 // CHECK-NEXT: [B] iterator dtor +// CHECK-NEXT: [B] iterator advance: 0 += 3 +// CHECK-NEXT: [B] iterator move assign +// CHECK-NEXT: [B] iterator deref: 3 +// CHECK-NEXT: [B] iterator dtor +// CHECK-NEXT: [A] iterator dtor +// CHECK-NEXT: [A] iterator advance: 0 += 3 +// CHECK-NEXT: [A] iterator move assign +// CHECK-NEXT: [A] iterator deref: 3 +// CHECK-NEXT: [B] iterator advance: 0 += 2 +// CHECK-NEXT: [B] iterator move assign +// CHECK-NEXT: [B] iterator deref: 2 +// CHECK-NEXT: [B] iterator dtor +// CHECK-NEXT: [B] iterator advance: 0 += 3 +// CHECK-NEXT: [B] iterator move assign +// CHECK-NEXT: [B] iterator deref: 3 +// CHECK-NEXT: [B] iterator dtor // CHECK-NEXT: [A] iterator dtor // CHECK-NEXT: [A] iterator advance: 0 += 0 // CHECK-NEXT: [A] iterator move assign @@ -320,6 +392,10 @@ int main() { // CHECK-NEXT: [B] iterator deref: 2 // CHECK-NEXT: i=2 v=0 w=2 // CHECK-NEXT: [B] iterator dtor +// CHECK-NEXT: [B] iterator advance: 0 += 3 +// CHECK-NEXT: [B] iterator move assign +// CHECK-NEXT: [B] iterator deref: 3 +// CHECK-NEXT: [B] iterator dtor // CHECK-NEXT: [A] iterator dtor // CHECK-NEXT: [A] iterator advance: 0 += 1 // CHECK-NEXT: [A] iterator move assign @@ -329,6 +405,10 @@ int main() { // CHECK-NEXT: [B] iterator deref: 2 // CHECK-NEXT: i=2 v=1 w=2 // CHECK-NEXT: [B] iterator dtor +// CHECK-NEXT: [B] iterator advance: 0 += 3 +// CHECK-NEXT: [B] iterator move assign +// CHECK-NEXT: [B] iterator deref: 3 +// CHECK-NEXT: [B] iterator dtor // CHECK-NEXT: [A] iterator dtor // CHECK-NEXT: [A] iterator advance: 0 += 2 // CHECK-NEXT: [A] iterator move assign @@ -344,6 +424,18 @@ int main() { // CHECK-NEXT: i=2 v=2 w=1 // CHECK-NEXT: [B] iterator dtor // CHECK-NEXT: [A] iterator dtor +// CHECK-NEXT: [A] iterator advance: 0 += 3 +// CHECK-NEXT: [A] iterator move assign +// CHECK-NEXT: [A] iterator deref: 3 +// CHECK-NEXT: [B] iterator advance: 0 += 0 +// CHECK-NEXT: [B] iterator move assign +// CHECK-NEXT: [B] iterator deref: 0 +// CHECK-NEXT: [B] iterator dtor +// CHECK-NEXT: [B] iterator advance: 0 += 1 +// CHECK-NEXT: [B] iterator move assign +// CHECK-NEXT: [B] iterator deref: 1 +// CHECK-NEXT: [B] iterator dtor +// CHECK-NEXT: [A] iterator dtor // CHECK-NEXT: [A] iterator advance: 0 += 2 // CHECK-NEXT: [A] iterator move assign // CHECK-NEXT: [A] iterator deref: 2 @@ -352,6 +444,22 @@ int main() { // CHECK-NEXT: [B] iterator deref: 2 // CHECK-NEXT: i=2 v=2 w=2 // CHECK-NEXT: [B] iterator dtor +// CHECK-NEXT: [B] iterator advance: 0 += 3 +// CHECK-NEXT: [B] iterator move assign +// CHECK-NEXT: [B] iterator deref: 3 +// CHECK-NEXT: [B] iterator dtor +// CHECK-NEXT: [A] iterator dtor +// CHECK-NEXT: [A] iterator advance: 0 += 3 +// CHECK-NEXT: [A] iterator move assign +// CHECK-NEXT: [A] iterator deref: 3 +// CHECK-NEXT: [B] iterator advance: 0 += 2 +// CHECK-NEXT: [B] iterator move assign +// CHECK-NEXT: [B] iterator deref: 2 +// CHECK-NEXT: [B] iterator dtor +// CHECK-NEXT: [B] iterator advance: 0 += 3 +// CHECK-NEXT: [B] iterator move assign +// CHECK-NEXT: [B] iterator deref: 3 +// CHECK-NEXT: [B] iterator dtor // CHECK-NEXT: [A] iterator dtor // CHECK-NEXT: [B] iterator dtor // CHECK-NEXT: [B] iterator dtor