diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index c3157c9441027..3d3b517e3096e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1493,31 +1493,19 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
       .Uni(S32, {{Sgpr32}, {IntrId}});
 
   // Intrinsics with no register operands.
-  addRulesForIOpcs({amdgcn_endpgm,
-                    amdgcn_init_exec,
-                    amdgcn_s_barrier,
-                    amdgcn_s_barrier_signal,
-                    amdgcn_s_barrier_wait,
-                    amdgcn_s_monitor_sleep,
-                    amdgcn_s_nop,
-                    amdgcn_s_sethalt,
-                    amdgcn_s_setprio,
-                    amdgcn_s_setprio_inc_wg,
-                    amdgcn_s_sleep,
-                    amdgcn_s_ttracedata_imm,
-                    amdgcn_s_wait_asynccnt,
-                    amdgcn_s_wait_bvhcnt,
-                    amdgcn_s_wait_dscnt,
-                    amdgcn_s_wait_event,
-                    amdgcn_s_wait_event_export_ready,
-                    amdgcn_s_wait_expcnt,
-                    amdgcn_s_wait_kmcnt,
-                    amdgcn_s_wait_loadcnt,
-                    amdgcn_s_wait_samplecnt,
-                    amdgcn_s_wait_storecnt,
-                    amdgcn_s_wait_tensorcnt,
-                    amdgcn_s_waitcnt,
-                    amdgcn_wave_barrier})
+  addRulesForIOpcs({amdgcn_endpgm,           amdgcn_init_exec,
+                    amdgcn_s_barrier,        amdgcn_s_barrier_leave,
+                    amdgcn_s_barrier_signal, amdgcn_s_barrier_wait,
+                    amdgcn_s_monitor_sleep,  amdgcn_s_nop,
+                    amdgcn_s_sethalt,        amdgcn_s_setprio,
+                    amdgcn_s_setprio_inc_wg, amdgcn_s_sleep,
+                    amdgcn_s_ttracedata_imm, amdgcn_s_wait_asynccnt,
+                    amdgcn_s_wait_bvhcnt,    amdgcn_s_wait_dscnt,
+                    amdgcn_s_wait_event,     amdgcn_s_wait_event_export_ready,
+                    amdgcn_s_wait_expcnt,    amdgcn_s_wait_kmcnt,
+                    amdgcn_s_wait_loadcnt,   amdgcn_s_wait_samplecnt,
+                    amdgcn_s_wait_storecnt,  amdgcn_s_wait_tensorcnt,
+                    amdgcn_s_waitcnt,        amdgcn_wave_barrier})
       .Any({{}, {{}, {}}});
 
   addRulesForIOpcs({amdgcn_init_exec_from_input})
@@ -1528,6 +1516,19 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
   addRulesForIOpcs({amdgcn_s_sleep_var})
       .Any({{}, {{}, {IntrId, SgprB32_ReadFirstLane}}});
 
+  addRulesForIOpcs({amdgcn_s_barrier_join, amdgcn_s_wakeup_barrier})
+      .Any({{}, {{}, {IntrId, SgprB32_M0}}});
+
+  addRulesForIOpcs({amdgcn_s_barrier_signal_var, amdgcn_s_barrier_init})
+      .Any({{}, {{}, {IntrId, SgprB32_M0, SgprB32_M0}}});
+
+  addRulesForIOpcs({amdgcn_s_barrier_signal_isfirst})
+      .Any({{UniS1}, {{Sgpr32Trunc}, {}}});
+
+  addRulesForIOpcs(
+      {amdgcn_s_get_named_barrier_state, amdgcn_s_get_barrier_state}, Standard)
+      .Uni(S32, {{Sgpr32}, {IntrId, SgprB32_M0}});
+
   addRulesForIOpcs({amdgcn_s_prefetch_data})
       .Any({{}, {{}, {IntrId, SgprB64_ReadFirstLane, SgprB32_ReadFirstLane}}});
 
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.signal.isfirst.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.signal.isfirst.ll
index d92255e1bb1b7..aa61d7446c768 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.signal.isfirst.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.signal.isfirst.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200  < %s | FileCheck -check-prefixes=GFX12-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200  < %s | FileCheck -check-prefixes=GFX12-GISEL %s
 
 define i1 @func1() {
 ; GFX12-SDAG-LABEL: func1:
diff --git a/llvm/test/CodeGen/AMDGPU/s-barrier.ll b/llvm/test/CodeGen/AMDGPU/s-barrier.ll
index 6c438ed94c863..248d6a7a5f1d2 100644
--- a/llvm/test/CodeGen/AMDGPU/s-barrier.ll
+++ b/llvm/test/CodeGen/AMDGPU/s-barrier.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
 
 @bar = internal addrspace(3) global target("amdgcn.named.barrier", 0) poison
 @bar2 = internal addrspace(3) global target("amdgcn.named.barrier", 0) poison
diff --git a/llvm/test/CodeGen/AMDGPU/s-wakeup-barrier.ll b/llvm/test/CodeGen/AMDGPU/s-wakeup-barrier.ll
index bc995f4738af8..2ecb380e6c37e 100644
--- a/llvm/test/CodeGen/AMDGPU/s-wakeup-barrier.ll
+++ b/llvm/test/CodeGen/AMDGPU/s-wakeup-barrier.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX1250-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX1250-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1250 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX1250-GISEL %s
 
 @bar = internal addrspace(3) global target("amdgcn.named.barrier", 0) poison