diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 5753d74168e59..9b4533b7e167d 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -10847,8 +10847,11 @@ void SelectionDAGBuilder::visitVACopy(const CallInst &I) { SDValue SelectionDAGBuilder::lowerRangeToAssertZExt(SelectionDAG &DAG, const Instruction &I, SDValue Op) { - std::optional CR = getRange(I); + return lowerRangeToAssertZExt(DAG, getRange(I), Op); +} +SDValue SelectionDAGBuilder::lowerRangeToAssertZExt( + SelectionDAG &DAG, std::optional CR, SDValue Op) { if (!CR || CR->isFullSet() || CR->isEmptySet() || CR->isUpperWrapped()) return Op; @@ -12198,6 +12201,9 @@ void SelectionDAGISel::LowerArguments(const Function &F) { OutVal = DAG.getNode(ISD::AssertNoFPClass, dl, OutVal.getValueType(), OutVal, SDNoFPClass); } + if (NumValues == 1 && VT.isInteger() && + !isa(OutVal)) + OutVal = SDB->lowerRangeToAssertZExt(DAG, Arg.getRange(), OutVal); ArgValues.push_back(OutVal); } diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h index 21aac333a73cd..7edf005586989 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h @@ -429,6 +429,8 @@ class SelectionDAGBuilder { // floor power of two. SDValue lowerRangeToAssertZExt(SelectionDAG &DAG, const Instruction &I, SDValue Op); + SDValue lowerRangeToAssertZExt(SelectionDAG &DAG, + std::optional CR, SDValue Op); // Lower nofpclass attributes to AssertNoFPClass SDValue lowerNoFPClassToAssertNoFPClass(SelectionDAG &DAG, diff --git a/llvm/test/CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll b/llvm/test/CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll index ad26dfa7f93e8..a0b37d415a3fc 100644 --- a/llvm/test/CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll +++ b/llvm/test/CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll @@ -5,13 +5,13 @@ ; operations. -; Should be able to reduce this to a 32-bit or plus a copy +; Should be able to reduce this to a 32-bit xor plus a copy ; https://alive2.llvm.org/ce/z/9LddFX define i64 @v_xor_i64_known_hi_i32_from_arg_range(i64 range(i64 0, 4294967296) %arg0, i64 %arg1) { ; CHECK-LABEL: v_xor_i64_known_hi_i32_from_arg_range: ; CHECK: ; %bb.0: ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; CHECK-NEXT: v_xor_b32_e32 v1, v1, v3 +; CHECK-NEXT: v_mov_b32_e32 v1, v3 ; CHECK-NEXT: v_xor_b32_e32 v0, v0, v2 ; CHECK-NEXT: s_setpc_b64 s[30:31] %xor = xor i64 %arg0, %arg1 @@ -24,7 +24,7 @@ define i64 @v_or_i64_known_hi_i32_from_arg_range(i64 range(i64 0, 4294967296) %a ; CHECK-LABEL: v_or_i64_known_hi_i32_from_arg_range: ; CHECK: ; %bb.0: ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; CHECK-NEXT: v_or_b32_e32 v1, v1, v3 +; CHECK-NEXT: v_mov_b32_e32 v1, v3 ; CHECK-NEXT: v_or_b32_e32 v0, v0, v2 ; CHECK-NEXT: s_setpc_b64 s[30:31] %or = or i64 %arg0, %arg1 @@ -32,7 +32,7 @@ define i64 @v_or_i64_known_hi_i32_from_arg_range(i64 range(i64 0, 4294967296) %a } ; https://alive2.llvm.org/ce/z/M96Ror -; Should be able to reduce this to a 32-bit plus a copy +; Should be able to reduce this to a 32-bit and plus a copy define i64 @v_and_i64_known_i32_from_arg_range(i64 range(i64 -4294967296, 0) %arg0, i64 %arg1) { ; CHECK-LABEL: v_and_i64_known_i32_from_arg_range: ; CHECK: ; %bb.0: @@ -50,7 +50,7 @@ define i64 @s_xor_i64_known_i32_from_arg_range(i64 range(i64 0, 65) inreg %arg) ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_not_b64 s[4:5], s[16:17] ; CHECK-NEXT: v_mov_b32_e32 v0, s4 -; CHECK-NEXT: v_mov_b32_e32 v1, s5 +; CHECK-NEXT: v_mov_b32_e32 v1, -1 ; CHECK-NEXT: s_setpc_b64 s[30:31] %xor = xor i64 %arg, -1 ret i64 %xor diff --git a/llvm/test/CodeGen/X86/argument-range-attr.ll b/llvm/test/CodeGen/X86/argument-range-attr.ll new file mode 100644 index 0000000000000..c6ae1a6e6c895 --- /dev/null +++ b/llvm/test/CodeGen/X86/argument-range-attr.ll @@ -0,0 +1,132 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s + +; range: 0..2^61 +; mask: 2^61 - 8 +define i64 @arg_range_top3(i64 range(i64 0, 2305843009213693952) %n) { +; CHECK-LABEL: arg_range_top3: +; CHECK: # %bb.0: +; CHECK-NEXT: movq %rdi, %rax +; CHECK-NEXT: andq $-8, %rax +; CHECK-NEXT: retq + %r = and i64 %n, 2305843009213693944 + ret i64 %r +} + +; range: 0..256 +; mask: 0xF8 = 248 +define i64 @arg_range_byte(i64 range(i64 0, 256) %n) { +; CHECK-LABEL: arg_range_byte: +; CHECK: # %bb.0: +; CHECK-NEXT: movq %rdi, %rax +; CHECK-NEXT: andl $-8, %eax +; CHECK-NEXT: retq + %r = and i64 %n, 248 + ret i64 %r +} + +define i64 @arg_range_nonzero_lo(i64 range(i64 1, 2305843009213693952) %n) { +; CHECK-LABEL: arg_range_nonzero_lo: +; CHECK: # %bb.0: +; CHECK-NEXT: movq %rdi, %rax +; CHECK-NEXT: andq $-8, %rax +; CHECK-NEXT: retq + %r = and i64 %n, 2305843009213693944 + ret i64 %r +} + +define i64 @arg_range_byte_nonzero_lo(i64 range(i64 1, 256) %n) { +; CHECK-LABEL: arg_range_byte_nonzero_lo: +; CHECK: # %bb.0: +; CHECK-NEXT: movq %rdi, %rax +; CHECK-NEXT: andl $-8, %eax +; CHECK-NEXT: retq + %r = and i64 %n, 248 + ret i64 %r +} + +define i32 @arg_range_i32_byte(i32 range(i32 0, 256) %n) { +; CHECK-LABEL: arg_range_i32_byte: +; CHECK: # %bb.0: +; CHECK-NEXT: movl %edi, %eax +; CHECK-NEXT: andl $-8, %eax +; CHECK-NEXT: retq + %r = and i32 %n, 248 + ret i32 %r +} + +define i64 @arg_range_top1(i64 range(i64 0, 9223372036854775808) %n) { +; CHECK-LABEL: arg_range_top1: +; CHECK: # %bb.0: +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: retq + %r = lshr i64 %n, 63 + ret i64 %r +} + +define i64 @arg_range_two_args(i64 range(i64 0, 256) %a, i64 range(i64 0, 65536) %b) { +; CHECK-LABEL: arg_range_two_args: +; CHECK: # %bb.0: +; CHECK-NEXT: movq %rdi, %rax +; CHECK-NEXT: orl %esi, %eax +; CHECK-NEXT: andl $-8, %eax +; CHECK-NEXT: retq + %ra = and i64 %a, 248 + %rb = and i64 %b, 65528 + %r = or i64 %ra, %rb + ret i64 %r +} + +define i32 @arg_range_zeroext(i8 zeroext range(i8 0, 16) %n) { +; CHECK-LABEL: arg_range_zeroext: +; CHECK: # %bb.0: +; CHECK-NEXT: movl %edi, %eax +; CHECK-NEXT: andl $-2, %eax +; CHECK-NEXT: retq + %z = zext i8 %n to i32 + %r = and i32 %z, 14 + ret i32 %r +} + +; The 7th integer arg is passed on the stack on x86-64 SysV. +define i64 @arg_range_stack(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, i64 range(i64 0, 256) %g) { +; CHECK-LABEL: arg_range_stack: +; CHECK: # %bb.0: +; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax +; CHECK-NEXT: andl $248, %eax +; CHECK-NEXT: retq + %r = and i64 %g, 248 + ret i64 %r +} + +; Negative tests + +define i64 @neg_no_range(i64 %n) { +; CHECK-LABEL: neg_no_range: +; CHECK: # %bb.0: +; CHECK-NEXT: movabsq $2305843009213693944, %rax # imm = 0x1FFFFFFFFFFFFFF8 +; CHECK-NEXT: andq %rdi, %rax +; CHECK-NEXT: retq + %r = and i64 %n, 2305843009213693944 + ret i64 %r +} + +define i64 @neg_wrapped_range(i64 range(i64 -100, 100) %n) { +; CHECK-LABEL: neg_wrapped_range: +; CHECK: # %bb.0: +; CHECK-NEXT: movabsq $2305843009213693944, %rax # imm = 0x1FFFFFFFFFFFFFF8 +; CHECK-NEXT: andq %rdi, %rax +; CHECK-NEXT: retq + %r = and i64 %n, 2305843009213693944 + ret i64 %r +} + +define i32 @neg_near_full_range(i32 range(i32 0, -1) %n) { +; CHECK-LABEL: neg_near_full_range: +; CHECK: # %bb.0: +; CHECK-NEXT: movl %edi, %eax +; CHECK-NEXT: andl $248, %eax +; CHECK-NEXT: retq + %r = and i32 %n, 248 + ret i32 %r +}