diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPreloadKernArgProlog.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPreloadKernArgProlog.cpp index c943d6fa2dd92f..cf8f12c4704fc0 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUPreloadKernArgProlog.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUPreloadKernArgProlog.cpp @@ -183,7 +183,7 @@ void AMDGPUPreloadKernArgProlog::addBackCompatLoads( MachineBasicBlock *BackCompatMBB, Register KernArgSegmentPtr, unsigned NumKernArgPreloadSGPRs) { Register KernArgPreloadSGPR = MFI.getArgInfo().FirstKernArgPreloadReg; - unsigned Offset = 0; + unsigned Offset = ST.getExplicitKernelArgOffset(); // Fill all user SGPRs used for kernarg preloading with sequential data from // the kernarg segment while (NumKernArgPreloadSGPRs > 0) { diff --git a/llvm/test/CodeGen/AMDGPU/lds-dma-workgroup-release.ll b/llvm/test/CodeGen/AMDGPU/lds-dma-workgroup-release.ll index f99718de977657..21e73cf8a303a8 100644 --- a/llvm/test/CodeGen/AMDGPU/lds-dma-workgroup-release.ll +++ b/llvm/test/CodeGen/AMDGPU/lds-dma-workgroup-release.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s --check-prefixes=GFX900 -; RUN: llc -mtriple=amdgcn -mcpu=gfx90a < %s | FileCheck %s --check-prefixes=GFX90A -; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -mattr=+tgsplit < %s | FileCheck %s --check-prefixes=GFX90A-TGSPLIT -; RUN: llc -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck %s --check-prefixes=GFX942 -; RUN: llc -mtriple=amdgcn -mcpu=gfx942 -mattr=+tgsplit < %s | FileCheck %s --check-prefixes=GFX942-TGSPLIT -; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck %s -check-prefixes=GFX10WGP -; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+cumode < %s | FileCheck %s -check-prefixes=GFX10CU +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s --check-prefixes=GFX900 +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a < %s | FileCheck %s --check-prefixes=GFX90A +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -mattr=+tgsplit < %s | FileCheck %s --check-prefixes=GFX90A-TGSPLIT +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck %s --check-prefixes=GFX942 +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -mattr=+tgsplit < %s | FileCheck %s --check-prefixes=GFX942-TGSPLIT +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck %s -check-prefixes=GFX10WGP +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+cumode < %s | FileCheck %s -check-prefixes=GFX10CU ; In each of these tests, an LDS DMA operation is followed by a release pattern ; at workgroup scope. The fence in such a release (implicit or explicit) should @@ -18,64 +18,54 @@ declare void @llvm.amdgcn.raw.buffer.load.lds(<4 x i32> %rsrc, ptr addrspace(3) define amdgpu_kernel void @barrier_release(<4 x i32> inreg %rsrc, ; GFX900-LABEL: barrier_release: ; GFX900: ; %bb.0: ; %main_body -; GFX900-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x24 +; GFX900-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x0 ; GFX900-NEXT: v_mov_b32_e32 v0, 0x800 ; GFX900-NEXT: v_mov_b32_e32 v1, 0 ; GFX900-NEXT: s_waitcnt lgkmcnt(0) -; GFX900-NEXT: s_mov_b32 m0, s12 +; GFX900-NEXT: s_mov_b32 m0, s4 ; GFX900-NEXT: s_nop 0 -; GFX900-NEXT: buffer_load_dword v0, s[8:11], 0 offen lds -; GFX900-NEXT: v_mov_b32_e32 v0, s13 +; GFX900-NEXT: buffer_load_dword v0, s[0:3], 0 offen lds +; GFX900-NEXT: v_mov_b32_e32 v0, s5 ; GFX900-NEXT: s_waitcnt vmcnt(0) ; GFX900-NEXT: s_barrier ; GFX900-NEXT: ds_read_b32 v0, v0 ; GFX900-NEXT: s_waitcnt lgkmcnt(0) -; GFX900-NEXT: global_store_dword v1, v0, s[14:15] +; GFX900-NEXT: global_store_dword v1, v0, s[6:7] ; GFX900-NEXT: s_endpgm ; ; GFX90A-LABEL: barrier_release: -; GFX90A: ; %bb.1: -; GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 -; GFX90A-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10 -; GFX90A-NEXT: s_waitcnt lgkmcnt(0) -; GFX90A-NEXT: s_branch .LBB0_0 -; GFX90A-NEXT: .p2align 8 -; GFX90A-NEXT: ; %bb.2: -; GFX90A-NEXT: .LBB0_0: ; %main_body -; GFX90A-NEXT: s_mov_b32 m0, s12 +; GFX90A: ; %bb.0: ; %main_body +; GFX90A-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x0 ; GFX90A-NEXT: v_mov_b32_e32 v0, 0x800 -; GFX90A-NEXT: buffer_load_dword v0, s[8:11], 0 offen lds -; GFX90A-NEXT: v_mov_b32_e32 v0, s13 -; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x3c -; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX90A-NEXT: s_waitcnt lgkmcnt(0) +; GFX90A-NEXT: s_mov_b32 m0, s4 +; GFX90A-NEXT: s_nop 0 +; GFX90A-NEXT: buffer_load_dword v0, s[0:3], 0 offen lds +; GFX90A-NEXT: v_mov_b32_e32 v0, s5 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: s_barrier ; GFX90A-NEXT: ds_read_b32 v1, v0 ; GFX90A-NEXT: v_mov_b32_e32 v0, 0 ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) -; GFX90A-NEXT: global_store_dword v0, v1, s[0:1] +; GFX90A-NEXT: global_store_dword v0, v1, s[6:7] ; GFX90A-NEXT: s_endpgm ; ; GFX90A-TGSPLIT-LABEL: barrier_release: -; GFX90A-TGSPLIT: ; %bb.1: -; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 -; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10 -; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0) -; GFX90A-TGSPLIT-NEXT: s_branch .LBB0_0 -; GFX90A-TGSPLIT-NEXT: .p2align 8 -; GFX90A-TGSPLIT-NEXT: ; %bb.2: -; GFX90A-TGSPLIT-NEXT: .LBB0_0: ; %main_body -; GFX90A-TGSPLIT-NEXT: s_mov_b32 m0, s12 +; GFX90A-TGSPLIT: ; %bb.0: ; %main_body +; GFX90A-TGSPLIT-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x0 ; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, 0x800 -; GFX90A-TGSPLIT-NEXT: buffer_load_dword v0, s[8:11], 0 offen lds -; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s13 -; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x3c -; GFX90A-TGSPLIT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0) +; GFX90A-TGSPLIT-NEXT: s_mov_b32 m0, s4 +; GFX90A-TGSPLIT-NEXT: s_nop 0 +; GFX90A-TGSPLIT-NEXT: buffer_load_dword v0, s[0:3], 0 offen lds +; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, s5 +; GFX90A-TGSPLIT-NEXT: s_waitcnt vmcnt(0) ; GFX90A-TGSPLIT-NEXT: s_barrier ; GFX90A-TGSPLIT-NEXT: buffer_wbinvl1_vol ; GFX90A-TGSPLIT-NEXT: ds_read_b32 v1, v0 ; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, 0 ; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0) -; GFX90A-TGSPLIT-NEXT: global_store_dword v0, v1, s[0:1] +; GFX90A-TGSPLIT-NEXT: global_store_dword v0, v1, s[6:7] ; GFX90A-TGSPLIT-NEXT: s_endpgm ; ; GFX942-LABEL: barrier_release: @@ -91,7 +81,7 @@ define amdgpu_kernel void @barrier_release(<4 x i32> inreg %rsrc, ; GFX942-NEXT: v_mov_b32_e32 v0, 0x800 ; GFX942-NEXT: buffer_load_dword v0, s[8:11], 0 offen lds ; GFX942-NEXT: v_mov_b32_e32 v0, s13 -; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x3c +; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x18 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: s_barrier ; GFX942-NEXT: ds_read_b32 v1, v0 @@ -113,7 +103,7 @@ define amdgpu_kernel void @barrier_release(<4 x i32> inreg %rsrc, ; GFX942-TGSPLIT-NEXT: v_mov_b32_e32 v0, 0x800 ; GFX942-TGSPLIT-NEXT: buffer_load_dword v0, s[8:11], 0 offen lds ; GFX942-TGSPLIT-NEXT: v_mov_b32_e32 v0, s13 -; GFX942-TGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x3c +; GFX942-TGSPLIT-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x18 ; GFX942-TGSPLIT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-TGSPLIT-NEXT: s_barrier ; GFX942-TGSPLIT-NEXT: buffer_inv sc0 @@ -125,35 +115,35 @@ define amdgpu_kernel void @barrier_release(<4 x i32> inreg %rsrc, ; ; GFX10WGP-LABEL: barrier_release: ; GFX10WGP: ; %bb.0: ; %main_body -; GFX10WGP-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x24 +; GFX10WGP-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x0 ; GFX10WGP-NEXT: v_mov_b32_e32 v0, 0x800 ; GFX10WGP-NEXT: v_mov_b32_e32 v1, 0 ; GFX10WGP-NEXT: s_waitcnt lgkmcnt(0) -; GFX10WGP-NEXT: s_mov_b32 m0, s12 -; GFX10WGP-NEXT: buffer_load_dword v0, s[8:11], 0 offen lds -; GFX10WGP-NEXT: v_mov_b32_e32 v0, s13 +; GFX10WGP-NEXT: s_mov_b32 m0, s4 +; GFX10WGP-NEXT: buffer_load_dword v0, s[0:3], 0 offen lds +; GFX10WGP-NEXT: v_mov_b32_e32 v0, s5 ; GFX10WGP-NEXT: s_waitcnt vmcnt(0) ; GFX10WGP-NEXT: s_barrier ; GFX10WGP-NEXT: buffer_gl0_inv ; GFX10WGP-NEXT: ds_read_b32 v0, v0 ; GFX10WGP-NEXT: s_waitcnt lgkmcnt(0) -; GFX10WGP-NEXT: global_store_dword v1, v0, s[14:15] +; GFX10WGP-NEXT: global_store_dword v1, v0, s[6:7] ; GFX10WGP-NEXT: s_endpgm ; ; GFX10CU-LABEL: barrier_release: ; GFX10CU: ; %bb.0: ; %main_body -; GFX10CU-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x24 +; GFX10CU-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x0 ; GFX10CU-NEXT: v_mov_b32_e32 v0, 0x800 ; GFX10CU-NEXT: v_mov_b32_e32 v1, 0 ; GFX10CU-NEXT: s_waitcnt lgkmcnt(0) -; GFX10CU-NEXT: s_mov_b32 m0, s12 -; GFX10CU-NEXT: buffer_load_dword v0, s[8:11], 0 offen lds -; GFX10CU-NEXT: v_mov_b32_e32 v0, s13 +; GFX10CU-NEXT: s_mov_b32 m0, s4 +; GFX10CU-NEXT: buffer_load_dword v0, s[0:3], 0 offen lds +; GFX10CU-NEXT: v_mov_b32_e32 v0, s5 ; GFX10CU-NEXT: s_waitcnt vmcnt(0) ; GFX10CU-NEXT: s_barrier ; GFX10CU-NEXT: ds_read_b32 v0, v0 ; GFX10CU-NEXT: s_waitcnt lgkmcnt(0) -; GFX10CU-NEXT: global_store_dword v1, v0, s[14:15] +; GFX10CU-NEXT: global_store_dword v1, v0, s[6:7] ; GFX10CU-NEXT: s_endpgm ptr addrspace(3) inreg %lds1, ptr addrspace(3) inreg %lds2, @@ -171,75 +161,69 @@ main_body: define amdgpu_kernel void @fence_fence(<4 x i32> inreg %rsrc, ; GFX900-LABEL: fence_fence: ; GFX900: ; %bb.0: ; %main_body -; GFX900-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34 -; GFX900-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 -; GFX900-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x3c +; GFX900-NEXT: s_load_dwordx2 s[10:11], s[8:9], 0x10 +; GFX900-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 +; GFX900-NEXT: s_load_dwordx4 s[4:7], s[8:9], 0x18 ; GFX900-NEXT: v_mov_b32_e32 v1, 0x800 ; GFX900-NEXT: v_mov_b32_e32 v0, 0 ; GFX900-NEXT: s_waitcnt lgkmcnt(0) -; GFX900-NEXT: s_mov_b32 m0, s6 +; GFX900-NEXT: s_mov_b32 m0, s10 ; GFX900-NEXT: s_nop 0 ; GFX900-NEXT: buffer_load_dword v1, s[0:3], 0 offen lds ; GFX900-NEXT: v_mov_b32_e32 v1, 1 ; GFX900-NEXT: s_waitcnt vmcnt(0) -; GFX900-NEXT: global_store_dword v0, v1, s[8:9] -; GFX900-NEXT: global_load_dword v1, v0, s[8:9] +; GFX900-NEXT: global_store_dword v0, v1, s[4:5] +; GFX900-NEXT: global_load_dword v1, v0, s[4:5] ; GFX900-NEXT: s_waitcnt vmcnt(0) -; GFX900-NEXT: v_mov_b32_e32 v1, s7 +; GFX900-NEXT: v_mov_b32_e32 v1, s11 ; GFX900-NEXT: ds_read_b32 v1, v1 ; GFX900-NEXT: s_waitcnt lgkmcnt(0) -; GFX900-NEXT: global_store_dword v0, v1, s[10:11] +; GFX900-NEXT: global_store_dword v0, v1, s[6:7] ; GFX900-NEXT: s_endpgm ; ; GFX90A-LABEL: fence_fence: -; GFX90A: ; %bb.1: -; GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 -; GFX90A-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10 -; GFX90A-NEXT: s_waitcnt lgkmcnt(0) -; GFX90A-NEXT: s_branch .LBB1_0 -; GFX90A-NEXT: .p2align 8 -; GFX90A-NEXT: ; %bb.2: -; GFX90A-NEXT: .LBB1_0: ; %main_body -; GFX90A-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x3c -; GFX90A-NEXT: s_mov_b32 m0, s12 +; GFX90A: ; %bb.0: ; %main_body +; GFX90A-NEXT: s_load_dwordx2 s[10:11], s[8:9], 0x10 +; GFX90A-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 +; GFX90A-NEXT: s_load_dwordx4 s[4:7], s[8:9], 0x18 ; GFX90A-NEXT: v_mov_b32_e32 v1, 0x800 ; GFX90A-NEXT: v_mov_b32_e32 v0, 0 -; GFX90A-NEXT: buffer_load_dword v1, s[8:11], 0 offen lds +; GFX90A-NEXT: s_waitcnt lgkmcnt(0) +; GFX90A-NEXT: s_mov_b32 m0, s10 +; GFX90A-NEXT: s_nop 0 +; GFX90A-NEXT: buffer_load_dword v1, s[0:3], 0 offen lds ; GFX90A-NEXT: v_mov_b32_e32 v1, 1 -; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX90A-NEXT: global_store_dword v0, v1, s[0:1] -; GFX90A-NEXT: global_load_dword v1, v0, s[0:1] ; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: v_mov_b32_e32 v1, s13 +; GFX90A-NEXT: global_store_dword v0, v1, s[4:5] +; GFX90A-NEXT: global_load_dword v1, v0, s[4:5] +; GFX90A-NEXT: s_waitcnt vmcnt(0) +; GFX90A-NEXT: v_mov_b32_e32 v1, s11 ; GFX90A-NEXT: ds_read_b32 v1, v1 ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) -; GFX90A-NEXT: global_store_dword v0, v1, s[2:3] +; GFX90A-NEXT: global_store_dword v0, v1, s[6:7] ; GFX90A-NEXT: s_endpgm ; ; GFX90A-TGSPLIT-LABEL: fence_fence: -; GFX90A-TGSPLIT: ; %bb.1: -; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 -; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10 -; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0) -; GFX90A-TGSPLIT-NEXT: s_branch .LBB1_0 -; GFX90A-TGSPLIT-NEXT: .p2align 8 -; GFX90A-TGSPLIT-NEXT: ; %bb.2: -; GFX90A-TGSPLIT-NEXT: .LBB1_0: ; %main_body -; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x3c -; GFX90A-TGSPLIT-NEXT: s_mov_b32 m0, s12 +; GFX90A-TGSPLIT: ; %bb.0: ; %main_body +; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[10:11], s[8:9], 0x10 +; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 +; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[4:7], s[8:9], 0x18 ; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, 0x800 ; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, 0 -; GFX90A-TGSPLIT-NEXT: buffer_load_dword v1, s[8:11], 0 offen lds +; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0) +; GFX90A-TGSPLIT-NEXT: s_mov_b32 m0, s10 +; GFX90A-TGSPLIT-NEXT: s_nop 0 +; GFX90A-TGSPLIT-NEXT: buffer_load_dword v1, s[0:3], 0 offen lds ; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, 1 -; GFX90A-TGSPLIT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX90A-TGSPLIT-NEXT: global_store_dword v0, v1, s[0:1] -; GFX90A-TGSPLIT-NEXT: global_load_dword v1, v0, s[0:1] glc ; GFX90A-TGSPLIT-NEXT: s_waitcnt vmcnt(0) -; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s13 +; GFX90A-TGSPLIT-NEXT: global_store_dword v0, v1, s[4:5] +; GFX90A-TGSPLIT-NEXT: global_load_dword v1, v0, s[4:5] glc +; GFX90A-TGSPLIT-NEXT: s_waitcnt vmcnt(0) +; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s11 ; GFX90A-TGSPLIT-NEXT: buffer_wbinvl1_vol ; GFX90A-TGSPLIT-NEXT: ds_read_b32 v1, v1 ; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0) -; GFX90A-TGSPLIT-NEXT: global_store_dword v0, v1, s[2:3] +; GFX90A-TGSPLIT-NEXT: global_store_dword v0, v1, s[6:7] ; GFX90A-TGSPLIT-NEXT: s_endpgm ; ; GFX942-LABEL: fence_fence: @@ -251,7 +235,7 @@ define amdgpu_kernel void @fence_fence(<4 x i32> inreg %rsrc, ; GFX942-NEXT: .p2align 8 ; GFX942-NEXT: ; %bb.2: ; GFX942-NEXT: .LBB1_0: ; %main_body -; GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x3c +; GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x18 ; GFX942-NEXT: s_mov_b32 m0, s12 ; GFX942-NEXT: v_mov_b32_e32 v1, 0x800 ; GFX942-NEXT: v_mov_b32_e32 v0, 0 @@ -276,7 +260,7 @@ define amdgpu_kernel void @fence_fence(<4 x i32> inreg %rsrc, ; GFX942-TGSPLIT-NEXT: .p2align 8 ; GFX942-TGSPLIT-NEXT: ; %bb.2: ; GFX942-TGSPLIT-NEXT: .LBB1_0: ; %main_body -; GFX942-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x3c +; GFX942-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x18 ; GFX942-TGSPLIT-NEXT: s_mov_b32 m0, s12 ; GFX942-TGSPLIT-NEXT: v_mov_b32_e32 v1, 0x800 ; GFX942-TGSPLIT-NEXT: v_mov_b32_e32 v0, 0 @@ -296,47 +280,47 @@ define amdgpu_kernel void @fence_fence(<4 x i32> inreg %rsrc, ; GFX10WGP-LABEL: fence_fence: ; GFX10WGP: ; %bb.0: ; %main_body ; GFX10WGP-NEXT: s_clause 0x2 -; GFX10WGP-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34 -; GFX10WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 -; GFX10WGP-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x3c +; GFX10WGP-NEXT: s_load_dwordx2 s[10:11], s[8:9], 0x10 +; GFX10WGP-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 +; GFX10WGP-NEXT: s_load_dwordx4 s[4:7], s[8:9], 0x18 ; GFX10WGP-NEXT: v_mov_b32_e32 v0, 0x800 ; GFX10WGP-NEXT: v_mov_b32_e32 v1, 0 ; GFX10WGP-NEXT: v_mov_b32_e32 v2, 1 ; GFX10WGP-NEXT: s_waitcnt lgkmcnt(0) -; GFX10WGP-NEXT: s_mov_b32 m0, s6 +; GFX10WGP-NEXT: s_mov_b32 m0, s10 ; GFX10WGP-NEXT: buffer_load_dword v0, s[0:3], 0 offen lds ; GFX10WGP-NEXT: s_waitcnt vmcnt(0) -; GFX10WGP-NEXT: global_store_dword v1, v2, s[8:9] -; GFX10WGP-NEXT: global_load_dword v0, v1, s[8:9] glc +; GFX10WGP-NEXT: global_store_dword v1, v2, s[4:5] +; GFX10WGP-NEXT: global_load_dword v0, v1, s[4:5] glc ; GFX10WGP-NEXT: s_waitcnt vmcnt(0) -; GFX10WGP-NEXT: v_mov_b32_e32 v0, s7 +; GFX10WGP-NEXT: v_mov_b32_e32 v0, s11 ; GFX10WGP-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10WGP-NEXT: buffer_gl0_inv ; GFX10WGP-NEXT: ds_read_b32 v0, v0 ; GFX10WGP-NEXT: s_waitcnt lgkmcnt(0) -; GFX10WGP-NEXT: global_store_dword v1, v0, s[10:11] +; GFX10WGP-NEXT: global_store_dword v1, v0, s[6:7] ; GFX10WGP-NEXT: s_endpgm ; ; GFX10CU-LABEL: fence_fence: ; GFX10CU: ; %bb.0: ; %main_body ; GFX10CU-NEXT: s_clause 0x2 -; GFX10CU-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34 -; GFX10CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 -; GFX10CU-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x3c +; GFX10CU-NEXT: s_load_dwordx2 s[10:11], s[8:9], 0x10 +; GFX10CU-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 +; GFX10CU-NEXT: s_load_dwordx4 s[4:7], s[8:9], 0x18 ; GFX10CU-NEXT: v_mov_b32_e32 v0, 0x800 ; GFX10CU-NEXT: v_mov_b32_e32 v1, 0 ; GFX10CU-NEXT: v_mov_b32_e32 v2, 1 ; GFX10CU-NEXT: s_waitcnt lgkmcnt(0) -; GFX10CU-NEXT: s_mov_b32 m0, s6 +; GFX10CU-NEXT: s_mov_b32 m0, s10 ; GFX10CU-NEXT: buffer_load_dword v0, s[0:3], 0 offen lds ; GFX10CU-NEXT: s_waitcnt vmcnt(0) -; GFX10CU-NEXT: global_store_dword v1, v2, s[8:9] -; GFX10CU-NEXT: global_load_dword v0, v1, s[8:9] +; GFX10CU-NEXT: global_store_dword v1, v2, s[4:5] +; GFX10CU-NEXT: global_load_dword v0, v1, s[4:5] ; GFX10CU-NEXT: s_waitcnt vmcnt(0) -; GFX10CU-NEXT: v_mov_b32_e32 v0, s7 +; GFX10CU-NEXT: v_mov_b32_e32 v0, s11 ; GFX10CU-NEXT: ds_read_b32 v0, v0 ; GFX10CU-NEXT: s_waitcnt lgkmcnt(0) -; GFX10CU-NEXT: global_store_dword v1, v0, s[10:11] +; GFX10CU-NEXT: global_store_dword v1, v0, s[6:7] ; GFX10CU-NEXT: s_endpgm ptr addrspace(3) inreg %lds1, ptr addrspace(3) inreg %lds2, @@ -356,75 +340,69 @@ main_body: define amdgpu_kernel void @release_acquire(<4 x i32> inreg %rsrc, ; GFX900-LABEL: release_acquire: ; GFX900: ; %bb.0: ; %main_body -; GFX900-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34 -; GFX900-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 -; GFX900-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x3c +; GFX900-NEXT: s_load_dwordx2 s[10:11], s[8:9], 0x10 +; GFX900-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 +; GFX900-NEXT: s_load_dwordx4 s[4:7], s[8:9], 0x18 ; GFX900-NEXT: v_mov_b32_e32 v1, 0x800 ; GFX900-NEXT: v_mov_b32_e32 v0, 0 ; GFX900-NEXT: s_waitcnt lgkmcnt(0) -; GFX900-NEXT: s_mov_b32 m0, s6 +; GFX900-NEXT: s_mov_b32 m0, s10 ; GFX900-NEXT: s_nop 0 ; GFX900-NEXT: buffer_load_dword v1, s[0:3], 0 offen lds ; GFX900-NEXT: v_mov_b32_e32 v1, 1 ; GFX900-NEXT: s_waitcnt vmcnt(0) -; GFX900-NEXT: global_store_dword v0, v1, s[8:9] -; GFX900-NEXT: global_load_dword v1, v0, s[8:9] +; GFX900-NEXT: global_store_dword v0, v1, s[4:5] +; GFX900-NEXT: global_load_dword v1, v0, s[4:5] ; GFX900-NEXT: s_waitcnt vmcnt(0) -; GFX900-NEXT: v_mov_b32_e32 v1, s7 +; GFX900-NEXT: v_mov_b32_e32 v1, s11 ; GFX900-NEXT: ds_read_b32 v1, v1 ; GFX900-NEXT: s_waitcnt lgkmcnt(0) -; GFX900-NEXT: global_store_dword v0, v1, s[10:11] +; GFX900-NEXT: global_store_dword v0, v1, s[6:7] ; GFX900-NEXT: s_endpgm ; ; GFX90A-LABEL: release_acquire: -; GFX90A: ; %bb.1: -; GFX90A-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 -; GFX90A-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10 -; GFX90A-NEXT: s_waitcnt lgkmcnt(0) -; GFX90A-NEXT: s_branch .LBB2_0 -; GFX90A-NEXT: .p2align 8 -; GFX90A-NEXT: ; %bb.2: -; GFX90A-NEXT: .LBB2_0: ; %main_body -; GFX90A-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x3c -; GFX90A-NEXT: s_mov_b32 m0, s12 +; GFX90A: ; %bb.0: ; %main_body +; GFX90A-NEXT: s_load_dwordx2 s[10:11], s[8:9], 0x10 +; GFX90A-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 +; GFX90A-NEXT: s_load_dwordx4 s[4:7], s[8:9], 0x18 ; GFX90A-NEXT: v_mov_b32_e32 v1, 0x800 ; GFX90A-NEXT: v_mov_b32_e32 v0, 0 -; GFX90A-NEXT: buffer_load_dword v1, s[8:11], 0 offen lds +; GFX90A-NEXT: s_waitcnt lgkmcnt(0) +; GFX90A-NEXT: s_mov_b32 m0, s10 +; GFX90A-NEXT: s_nop 0 +; GFX90A-NEXT: buffer_load_dword v1, s[0:3], 0 offen lds ; GFX90A-NEXT: v_mov_b32_e32 v1, 1 -; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX90A-NEXT: global_store_dword v0, v1, s[0:1] -; GFX90A-NEXT: global_load_dword v1, v0, s[0:1] ; GFX90A-NEXT: s_waitcnt vmcnt(0) -; GFX90A-NEXT: v_mov_b32_e32 v1, s13 +; GFX90A-NEXT: global_store_dword v0, v1, s[4:5] +; GFX90A-NEXT: global_load_dword v1, v0, s[4:5] +; GFX90A-NEXT: s_waitcnt vmcnt(0) +; GFX90A-NEXT: v_mov_b32_e32 v1, s11 ; GFX90A-NEXT: ds_read_b32 v1, v1 ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) -; GFX90A-NEXT: global_store_dword v0, v1, s[2:3] +; GFX90A-NEXT: global_store_dword v0, v1, s[6:7] ; GFX90A-NEXT: s_endpgm ; ; GFX90A-TGSPLIT-LABEL: release_acquire: -; GFX90A-TGSPLIT: ; %bb.1: -; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 -; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x10 -; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0) -; GFX90A-TGSPLIT-NEXT: s_branch .LBB2_0 -; GFX90A-TGSPLIT-NEXT: .p2align 8 -; GFX90A-TGSPLIT-NEXT: ; %bb.2: -; GFX90A-TGSPLIT-NEXT: .LBB2_0: ; %main_body -; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x3c -; GFX90A-TGSPLIT-NEXT: s_mov_b32 m0, s12 +; GFX90A-TGSPLIT: ; %bb.0: ; %main_body +; GFX90A-TGSPLIT-NEXT: s_load_dwordx2 s[10:11], s[8:9], 0x10 +; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 +; GFX90A-TGSPLIT-NEXT: s_load_dwordx4 s[4:7], s[8:9], 0x18 ; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, 0x800 ; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v0, 0 -; GFX90A-TGSPLIT-NEXT: buffer_load_dword v1, s[8:11], 0 offen lds +; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0) +; GFX90A-TGSPLIT-NEXT: s_mov_b32 m0, s10 +; GFX90A-TGSPLIT-NEXT: s_nop 0 +; GFX90A-TGSPLIT-NEXT: buffer_load_dword v1, s[0:3], 0 offen lds ; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, 1 -; GFX90A-TGSPLIT-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX90A-TGSPLIT-NEXT: global_store_dword v0, v1, s[0:1] -; GFX90A-TGSPLIT-NEXT: global_load_dword v1, v0, s[0:1] glc +; GFX90A-TGSPLIT-NEXT: s_waitcnt vmcnt(0) +; GFX90A-TGSPLIT-NEXT: global_store_dword v0, v1, s[4:5] +; GFX90A-TGSPLIT-NEXT: global_load_dword v1, v0, s[4:5] glc ; GFX90A-TGSPLIT-NEXT: s_waitcnt vmcnt(0) ; GFX90A-TGSPLIT-NEXT: buffer_wbinvl1_vol -; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s13 +; GFX90A-TGSPLIT-NEXT: v_mov_b32_e32 v1, s11 ; GFX90A-TGSPLIT-NEXT: ds_read_b32 v1, v1 ; GFX90A-TGSPLIT-NEXT: s_waitcnt lgkmcnt(0) -; GFX90A-TGSPLIT-NEXT: global_store_dword v0, v1, s[2:3] +; GFX90A-TGSPLIT-NEXT: global_store_dword v0, v1, s[6:7] ; GFX90A-TGSPLIT-NEXT: s_endpgm ; ; GFX942-LABEL: release_acquire: @@ -436,7 +414,7 @@ define amdgpu_kernel void @release_acquire(<4 x i32> inreg %rsrc, ; GFX942-NEXT: .p2align 8 ; GFX942-NEXT: ; %bb.2: ; GFX942-NEXT: .LBB2_0: ; %main_body -; GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x3c +; GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x18 ; GFX942-NEXT: s_mov_b32 m0, s12 ; GFX942-NEXT: v_mov_b32_e32 v1, 0x800 ; GFX942-NEXT: v_mov_b32_e32 v0, 0 @@ -461,7 +439,7 @@ define amdgpu_kernel void @release_acquire(<4 x i32> inreg %rsrc, ; GFX942-TGSPLIT-NEXT: .p2align 8 ; GFX942-TGSPLIT-NEXT: ; %bb.2: ; GFX942-TGSPLIT-NEXT: .LBB2_0: ; %main_body -; GFX942-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x3c +; GFX942-TGSPLIT-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x18 ; GFX942-TGSPLIT-NEXT: s_mov_b32 m0, s12 ; GFX942-TGSPLIT-NEXT: v_mov_b32_e32 v1, 0x800 ; GFX942-TGSPLIT-NEXT: v_mov_b32_e32 v0, 0 @@ -481,46 +459,46 @@ define amdgpu_kernel void @release_acquire(<4 x i32> inreg %rsrc, ; GFX10WGP-LABEL: release_acquire: ; GFX10WGP: ; %bb.0: ; %main_body ; GFX10WGP-NEXT: s_clause 0x2 -; GFX10WGP-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34 -; GFX10WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 -; GFX10WGP-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x3c +; GFX10WGP-NEXT: s_load_dwordx2 s[10:11], s[8:9], 0x10 +; GFX10WGP-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 +; GFX10WGP-NEXT: s_load_dwordx4 s[4:7], s[8:9], 0x18 ; GFX10WGP-NEXT: v_mov_b32_e32 v0, 0 ; GFX10WGP-NEXT: v_mov_b32_e32 v1, 0x800 ; GFX10WGP-NEXT: v_mov_b32_e32 v2, 1 ; GFX10WGP-NEXT: s_waitcnt lgkmcnt(0) -; GFX10WGP-NEXT: s_mov_b32 m0, s6 +; GFX10WGP-NEXT: s_mov_b32 m0, s10 ; GFX10WGP-NEXT: buffer_load_dword v1, s[0:3], 0 offen lds ; GFX10WGP-NEXT: s_waitcnt vmcnt(0) -; GFX10WGP-NEXT: global_store_dword v0, v2, s[8:9] -; GFX10WGP-NEXT: global_load_dword v1, v0, s[8:9] glc +; GFX10WGP-NEXT: global_store_dword v0, v2, s[4:5] +; GFX10WGP-NEXT: global_load_dword v1, v0, s[4:5] glc ; GFX10WGP-NEXT: s_waitcnt vmcnt(0) ; GFX10WGP-NEXT: buffer_gl0_inv -; GFX10WGP-NEXT: v_mov_b32_e32 v1, s7 +; GFX10WGP-NEXT: v_mov_b32_e32 v1, s11 ; GFX10WGP-NEXT: ds_read_b32 v1, v1 ; GFX10WGP-NEXT: s_waitcnt lgkmcnt(0) -; GFX10WGP-NEXT: global_store_dword v0, v1, s[10:11] +; GFX10WGP-NEXT: global_store_dword v0, v1, s[6:7] ; GFX10WGP-NEXT: s_endpgm ; ; GFX10CU-LABEL: release_acquire: ; GFX10CU: ; %bb.0: ; %main_body ; GFX10CU-NEXT: s_clause 0x2 -; GFX10CU-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34 -; GFX10CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 -; GFX10CU-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x3c +; GFX10CU-NEXT: s_load_dwordx2 s[10:11], s[8:9], 0x10 +; GFX10CU-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 +; GFX10CU-NEXT: s_load_dwordx4 s[4:7], s[8:9], 0x18 ; GFX10CU-NEXT: v_mov_b32_e32 v0, 0 ; GFX10CU-NEXT: v_mov_b32_e32 v1, 0x800 ; GFX10CU-NEXT: v_mov_b32_e32 v2, 1 ; GFX10CU-NEXT: s_waitcnt lgkmcnt(0) -; GFX10CU-NEXT: s_mov_b32 m0, s6 +; GFX10CU-NEXT: s_mov_b32 m0, s10 ; GFX10CU-NEXT: buffer_load_dword v1, s[0:3], 0 offen lds ; GFX10CU-NEXT: s_waitcnt vmcnt(0) -; GFX10CU-NEXT: global_store_dword v0, v2, s[8:9] -; GFX10CU-NEXT: global_load_dword v1, v0, s[8:9] +; GFX10CU-NEXT: global_store_dword v0, v2, s[4:5] +; GFX10CU-NEXT: global_load_dword v1, v0, s[4:5] ; GFX10CU-NEXT: s_waitcnt vmcnt(0) -; GFX10CU-NEXT: v_mov_b32_e32 v1, s7 +; GFX10CU-NEXT: v_mov_b32_e32 v1, s11 ; GFX10CU-NEXT: ds_read_b32 v1, v1 ; GFX10CU-NEXT: s_waitcnt lgkmcnt(0) -; GFX10CU-NEXT: global_store_dword v0, v1, s[10:11] +; GFX10CU-NEXT: global_store_dword v0, v1, s[6:7] ; GFX10CU-NEXT: s_endpgm ptr addrspace(3) inreg %lds1, ptr addrspace(3) inreg %lds2, diff --git a/llvm/test/CodeGen/AMDGPU/preload-kernarg-header.ll b/llvm/test/CodeGen/AMDGPU/preload-kernarg-header.ll index 84aa948ac11b39..505b5d4bb2cd96 100644 --- a/llvm/test/CodeGen/AMDGPU/preload-kernarg-header.ll +++ b/llvm/test/CodeGen/AMDGPU/preload-kernarg-header.ll @@ -1,5 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -asm-verbose=0 < %s | FileCheck -check-prefixes=ASM %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -asm-verbose=0 < %s | FileCheck -check-prefixes=CHECK,ASM %s +; On non-AMDHSA triples the explicit kernarg segment starts at byte 36, so the +; back-compat prolog must load preloaded args from that offset, not from 0. +; RUN: llc -mtriple=amdgcn-- -mcpu=gfx942 -asm-verbose=0 < %s | FileCheck -check-prefixes=CHECK,NONHSA %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -filetype=obj < %s | llvm-objdump --arch=amdgcn --mcpu=gfx942 --disassemble - | FileCheck -check-prefixes=OBJ %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -amdgpu-kernarg-preload-count=1 -asm-verbose=0 < %s | llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx942 -filetype=obj | llvm-objdump --arch=amdgcn --mcpu=gfx942 --disassemble - | FileCheck -check-prefixes=OBJ %s @@ -16,6 +19,17 @@ define amdgpu_kernel void @preload_ptr_kernarg_header(ptr inreg %arg) { ; ASM-NEXT: v_mov_b64_e32 v[2:3], s[8:9] ; ASM-NEXT: flat_store_dwordx2 v[0:1], v[2:3] ; ASM-NEXT: s_endpgm +; +; NONHSA-LABEL: preload_ptr_kernarg_header: +; NONHSA: s_load_dwordx2 s[8:9], s[4:5], 0x24 +; NONHSA-NEXT: s_waitcnt lgkmcnt(0) +; NONHSA-NEXT: s_branch .LBB0_0 +; NONHSA-NEXT: .p2align 8 +; NONHSA-NEXT: .LBB0_0: +; NONHSA-NEXT: v_mov_b64_e32 v[0:1], s[8:9] +; NONHSA-NEXT: v_mov_b64_e32 v[2:3], s[8:9] +; NONHSA-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; NONHSA-NEXT: s_endpgm store ptr %arg, ptr %arg ret void } @@ -34,6 +48,18 @@ define amdgpu_kernel void @preload_i32_kernarg_header(ptr inreg %arg, i32 inreg ; ASM-NEXT: v_mov_b32_e32 v2, s10 ; ASM-NEXT: flat_store_dword v[0:1], v2 ; ASM-NEXT: s_endpgm +; +; NONHSA-LABEL: preload_i32_kernarg_header: +; NONHSA: s_load_dwordx2 s[8:9], s[4:5], 0x24 +; NONHSA-NEXT: s_load_dword s10, s[4:5], 0x2c +; NONHSA-NEXT: s_waitcnt lgkmcnt(0) +; NONHSA-NEXT: s_branch .LBB1_0 +; NONHSA-NEXT: .p2align 8 +; NONHSA-NEXT: .LBB1_0: +; NONHSA-NEXT: v_mov_b64_e32 v[0:1], s[8:9] +; NONHSA-NEXT: v_mov_b32_e32 v2, s10 +; NONHSA-NEXT: flat_store_dword v[0:1], v2 +; NONHSA-NEXT: s_endpgm store i32 %arg1, ptr %arg ret void } @@ -43,11 +69,11 @@ define amdgpu_kernel void @preload_i32_kernarg_header(ptr inreg %arg, i32 inreg ; OBJ-NOT: s_branch ; ASM-NOT: s_branch define void @non_kernel_function(ptr %arg) { -; ASM-LABEL: non_kernel_function: -; ASM: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; ASM-NEXT: flat_store_dwordx2 v[0:1], v[0:1] -; ASM-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; ASM-NEXT: s_setpc_b64 s[30:31] +; CHECK-LABEL: non_kernel_function: +; CHECK: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: flat_store_dwordx2 v[0:1], v[0:1] +; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; CHECK-NEXT: s_setpc_b64 s[30:31] store ptr %arg, ptr %arg ret void }