diff --git a/compiler-rt/lib/builtins/cpu_model/riscv.c b/compiler-rt/lib/builtins/cpu_model/riscv.c
index 1c729c8bd7e05..48397f889440a 100644
--- a/compiler-rt/lib/builtins/cpu_model/riscv.c
+++ b/compiler-rt/lib/builtins/cpu_model/riscv.c
@@ -146,6 +146,8 @@ struct {
 #define ZIFENCEI_BITMASK (1ULL << 11)
 #define ZMMUL_GROUPID 1
 #define ZMMUL_BITMASK (1ULL << 12)
+#define ZICFISS_GROUPID 1
+#define ZICFISS_BITMASK (1ULL << 27)
 
 #if defined(__linux__)
 
@@ -222,6 +224,8 @@ static long syscall_impl_5_args(long number, long arg1, long arg2, long arg3,
 #define RISCV_HWPROBE_EXT_ZCF (1ULL << 46)
 #define RISCV_HWPROBE_EXT_ZCMOP (1ULL << 47)
 #define RISCV_HWPROBE_EXT_ZAWRS (1ULL << 48)
+#define RISCV_HWPROBE_KEY_IMA_EXT_1 16
+#define RISCV_HWPROBE_EXT_ZICFISS (1ULL << 0)
 #define RISCV_HWPROBE_KEY_CPUPERF_0 5
 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
 #define RISCV_HWPROBE_MISALIGNED_EMULATED (1ULL << 0)
@@ -230,7 +234,6 @@ static long syscall_impl_5_args(long number, long arg1, long arg2, long arg3,
 #define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0)
 #define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0)
 #define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6
-/* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
 
 struct riscv_hwprobe {
   long long key;
@@ -242,8 +245,8 @@ static long initHwProbe(struct riscv_hwprobe *Hwprobes, int len) {
   return syscall_impl_5_args(__NR_riscv_hwprobe, (long)Hwprobes, len, 0, 0, 0);
 }
 
-#define SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(EXTNAME)                    \
-  SET_SINGLE_IMAEXT_RISCV_FEATURE(RISCV_HWPROBE_EXT_##EXTNAME, EXTNAME)
+#define SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(KEYVAR, EXTNAME)            \
+  SET_SINGLE_RISCV_FEATURE(KEYVAR &RISCV_HWPROBE_EXT_##EXTNAME, EXTNAME)
 
 #define SET_SINGLE_IMAEXT_RISCV_FEATURE(HWPROBE_BITMASK, EXT)                  \
   SET_SINGLE_RISCV_FEATURE(IMAEXT0Value &HWPROBE_BITMASK, EXT)
@@ -292,52 +295,56 @@ static void initRISCVFeature(struct riscv_hwprobe Hwprobes[]) {
 
   SET_SINGLE_IMAEXT_RISCV_FEATURE(RISCV_HWPROBE_IMA_C, C);
   SET_SINGLE_IMAEXT_RISCV_FEATURE(RISCV_HWPROBE_IMA_V, V);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZBA);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZBB);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZBS);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZICBOZ);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZBC);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZBKB);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZBKC);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZBKX);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZKND);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZKNE);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZKNH);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZKSED);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZKSH);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZKT);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVBB);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVBC);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVKB);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVKG);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVKNED);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVKNHA);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVKNHB);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVKSED);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVKSH);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVKT);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZFH);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZFHMIN);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZIHINTNTL);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZIHINTPAUSE);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVFH);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVFHMIN);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZFA);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZTSO);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZACAS);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZICOND);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVE32X);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVE32F);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVE64X);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVE64F);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZVE64D);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZIMOP);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZCA);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZCB);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZCD);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZCF);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZCMOP);
-  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZAWRS);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZBA);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZBB);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZBS);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZICBOZ);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZBC);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZBKB);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZBKC);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZBKX);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZKND);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZKNE);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZKNH);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZKSED);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZKSH);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZKT);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZVBB);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZVBC);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZVKB);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZVKG);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZVKNED);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZVKNHA);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZVKNHB);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZVKSED);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZVKSH);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZVKT);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZFH);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZFHMIN);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZIHINTNTL);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZIHINTPAUSE);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZVFH);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZVFHMIN);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZFA);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZTSO);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZACAS);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZICOND);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZVE32X);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZVE32F);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZVE64X);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZVE64F);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZVE64D);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZIMOP);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZCA);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZCB);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZCD);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZCF);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZCMOP);
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT0Value, ZAWRS);
+
+  // Check RISCV_HWPROBE_KEY_IMA_EXT_1
+  unsigned long long IMAEXT1Value = Hwprobes[5].value;
+  SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(IMAEXT1Value, ZICFISS);
 
   for (i = 0; i < RISCV_FEATURE_BITS_LENGTH; i++)
     __riscv_feature_bits.features[i] = features[i];
@@ -374,7 +381,7 @@ void __init_riscv_feature_bits(void *PlatformArgs) {
   struct riscv_hwprobe Hwprobes[] = {
       {RISCV_HWPROBE_KEY_BASE_BEHAVIOR, 0}, {RISCV_HWPROBE_KEY_IMA_EXT_0, 0},
       {RISCV_HWPROBE_KEY_MVENDORID, 0},     {RISCV_HWPROBE_KEY_MARCHID, 0},
-      {RISCV_HWPROBE_KEY_MIMPID, 0},
+      {RISCV_HWPROBE_KEY_MIMPID, 0},        {RISCV_HWPROBE_KEY_IMA_EXT_1, 0},
   };
   if (initHwProbe(Hwprobes, sizeof(Hwprobes) / sizeof(Hwprobes[0])))
     return;
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index f3e6e69e5e0e9..23d444fca365d 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -181,7 +181,8 @@ def FeatureStdExtZicfilp
 
 def FeatureStdExtZicfiss
     : RISCVExperimentalExtension<1, 0, "Shadow stack",
-                                 [FeatureStdExtZicsr, FeatureStdExtZimop]>;
+                                 [FeatureStdExtZicsr, FeatureStdExtZimop]>,
+      RISCVExtensionBitmask<1, 27>;
 def HasStdExtZicfiss : Predicate<"Subtarget->hasStdExtZicfiss()">,
                        AssemblerPredicate<(all_of FeatureStdExtZicfiss),
                                           "'Zicfiss' (Shadow stack)">;
diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp
index dfe97f178bd46..9239134904430 100644
--- a/llvm/lib/TargetParser/Host.cpp
+++ b/llvm/lib/TargetParser/Host.cpp
@@ -2459,7 +2459,8 @@ StringMap<bool> sys::getHostCPUFeatures() {
 StringMap<bool> sys::getHostCPUFeatures() {
   RISCVHwProbe Query[]{{/*RISCV_HWPROBE_KEY_BASE_BEHAVIOR=*/3, 0},
                        {/*RISCV_HWPROBE_KEY_IMA_EXT_0=*/4, 0},
-                       {/*RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF=*/9, 0}};
+                       {/*RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF=*/9, 0},
+                       {/*RISCV_HWPROBE_KEY_IMA_EXT_1=*/16, 0}};
   int Ret = syscall(/*__NR_riscv_hwprobe=*/258, /*pairs=*/Query,
                     /*pair_count=*/std::size(Query), /*cpu_count=*/0,
                     /*cpus=*/0, /*flags=*/0);
@@ -2528,6 +2529,9 @@ StringMap<bool> sys::getHostCPUFeatures() {
   Features["zcmop"] = ExtMask & (1ULL << 47);  // RISCV_HWPROBE_EXT_ZCMOP
   Features["zawrs"] = ExtMask & (1ULL << 48);  // RISCV_HWPROBE_EXT_ZAWRS
 
+  uint64_t Ext1Mask = Query[3].Value;
+  Features["zicfiss"] = Ext1Mask & (1ULL << 0); // RISCV_HWPROBE_EXT_ZICFISS
+
   // Check whether the processor supports fast misaligned scalar memory access.
   // NOTE: RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF is only available on
   // Linux 6.11 or later. If it is not recognized, the key field will be cleared