diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index ee06217fc5d87..a00fb1ddbd65c 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -2598,6 +2598,31 @@ instCombineSVEVectorMlaU(InstCombiner &IC, IntrinsicInst &II) {
   return std::nullopt;
 }
 
+static std::optional<Instruction *>
+instCombineSVEPairwiseAddLong(InstCombiner &IC, IntrinsicInst &II) {
+  assert((II.getIntrinsicID() == Intrinsic::aarch64_sve_sadalp ||
+          II.getIntrinsicID() == Intrinsic::aarch64_sve_uadalp) &&
+         "Expected SADALP or UADALP intrinsic");
+
+  // We are looking for add(adalp(%pred, zeroinitializer, %in), %acc)
+  if (!II.hasOneUse() || !match(II.getArgOperand(1), m_Zero()))
+    return std::nullopt;
+
+  auto *User = cast<Instruction>(*II.user_begin());
+  Value *Acc;
+  if (!match(User, m_c_Add(m_Specific(&II), m_Value(Acc))))
+    return std::nullopt;
+
+  IC.Builder.SetInsertPoint(User);
+  Value *PairwiseAddLong = IC.Builder.CreateIntrinsic(
+      II.getIntrinsicID(), {II.getType()},
+      {II.getArgOperand(0), Acc, II.getArgOperand(2)});
+
+  IC.replaceInstUsesWith(*User, PairwiseAddLong);
+  IC.eraseInstFromFunction(*User);
+  return &II; // II is now trivially dead and will get erased.
+}
+
 static std::optional<Instruction *> instCombineSVEVectorAdd(InstCombiner &IC,
                                                             IntrinsicInst &II) {
   if (auto MLA = instCombineSVEVectorFuseMulAddSub<Intrinsic::aarch64_sve_mul,
@@ -3165,6 +3190,9 @@ AArch64TTIImpl::instCombineIntrinsic(InstCombiner &IC,
         IC, II, true);
   case Intrinsic::aarch64_sve_mla_u:
     return instCombineSVEVectorMlaU(IC, II);
+  case Intrinsic::aarch64_sve_sadalp:
+  case Intrinsic::aarch64_sve_uadalp:
+    return instCombineSVEPairwiseAddLong(IC, II);
   case Intrinsic::aarch64_sve_sub:
     return instCombineSVEVectorSub(IC, II);
   case Intrinsic::aarch64_sve_sub_u:
diff --git a/llvm/test/Transforms/InstCombine/AArch64/sve-pairwise-add-long.ll b/llvm/test/Transforms/InstCombine/AArch64/sve-pairwise-add-long.ll
new file mode 100644
index 0000000000000..323ce50737aa3
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/AArch64/sve-pairwise-add-long.ll
@@ -0,0 +1,96 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -S -passes=instcombine < %s | FileCheck %s
+
+target triple = "aarch64-unknown-linux-gnu"
+
+; When sadalp or uadalp accumulate into a zeroregister and they are followed by
+; an add instruction, the latter can be folded in.
+
+define <vscale x 8 x i16> @sadalp_i8_separate_add(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 16 x i8> %b) {
+; CHECK-LABEL: define <vscale x 8 x i16> @sadalp_i8_separate_add(
+; CHECK-SAME: <vscale x 8 x i1> [[PG:%.*]], <vscale x 8 x i16> [[A:%.*]], <vscale x 16 x i8> [[B:%.*]]) {
+; CHECK-NEXT:    [[OUT2:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.sadalp.nxv8i16(<vscale x 8 x i1> [[PG]], <vscale x 8 x i16> [[A]], <vscale x 16 x i8> [[B]])
+; CHECK-NEXT:    ret <vscale x 8 x i16> [[OUT2]]
+;
+  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sadalp.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> zeroinitializer, <vscale x 16 x i8> %b)
+  %out2 = add <vscale x 8 x i16> %out, %a
+  ret <vscale x 8 x i16> %out2
+}
+
+define <vscale x 4 x i32> @sadalp_i16_separate_add(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 8 x i16> %b) {
+; CHECK-LABEL: define <vscale x 4 x i32> @sadalp_i16_separate_add(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]], <vscale x 4 x i32> [[A:%.*]], <vscale x 8 x i16> [[B:%.*]]) {
+; CHECK-NEXT:    [[OUT2:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sadalp.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> [[A]], <vscale x 8 x i16> [[B]])
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[OUT2]]
+;
+  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sadalp.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> zeroinitializer, <vscale x 8 x i16> %b)
+  %out2 = add <vscale x 4 x i32> %out, %a
+  ret <vscale x 4 x i32> %out2
+}
+
+define <vscale x 2 x i64> @sadalp_i32_separate_add(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 4 x i32> %b) {
+; CHECK-LABEL: define <vscale x 2 x i64> @sadalp_i32_separate_add(
+; CHECK-SAME: <vscale x 2 x i1> [[PG:%.*]], <vscale x 2 x i64> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) {
+; CHECK-NEXT:    [[OUT2:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sadalp.nxv2i64(<vscale x 2 x i1> [[PG]], <vscale x 2 x i64> [[A]], <vscale x 4 x i32> [[B]])
+; CHECK-NEXT:    ret <vscale x 2 x i64> [[OUT2]]
+;
+  %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sadalp.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> zeroinitializer, <vscale x 4 x i32> %b)
+  %out2 = add <vscale x 2 x i64> %out, %a
+  ret <vscale x 2 x i64> %out2
+}
+
+define <vscale x 2 x i64> @sadalp_i32_separate_add_rev(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 4 x i32> %b) {
+; CHECK-LABEL: define <vscale x 2 x i64> @sadalp_i32_separate_add_rev(
+; CHECK-SAME: <vscale x 2 x i1> [[PG:%.*]], <vscale x 2 x i64> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) {
+; CHECK-NEXT:    [[OUT2:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sadalp.nxv2i64(<vscale x 2 x i1> [[PG]], <vscale x 2 x i64> [[A]], <vscale x 4 x i32> [[B]])
+; CHECK-NEXT:    ret <vscale x 2 x i64> [[OUT2]]
+;
+  %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sadalp.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> zeroinitializer, <vscale x 4 x i32> %b)
+  %out2 = add <vscale x 2 x i64> %a, %out
+  ret <vscale x 2 x i64> %out2
+}
+
+define <vscale x 8 x i16> @uadalp_i8_separate_add(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 16 x i8> %b) {
+; CHECK-LABEL: define <vscale x 8 x i16> @uadalp_i8_separate_add(
+; CHECK-SAME: <vscale x 8 x i1> [[PG:%.*]], <vscale x 8 x i16> [[A:%.*]], <vscale x 16 x i8> [[B:%.*]]) {
+; CHECK-NEXT:    [[OUT2:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.uadalp.nxv8i16(<vscale x 8 x i1> [[PG]], <vscale x 8 x i16> [[A]], <vscale x 16 x i8> [[B]])
+; CHECK-NEXT:    ret <vscale x 8 x i16> [[OUT2]]
+;
+  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uadalp.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> zeroinitializer, <vscale x 16 x i8> %b)
+  %out2 = add <vscale x 8 x i16> %out, %a
+  ret <vscale x 8 x i16> %out2
+}
+
+define <vscale x 4 x i32> @uadalp_i16_separate_add(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 8 x i16> %b) {
+; CHECK-LABEL: define <vscale x 4 x i32> @uadalp_i16_separate_add(
+; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]], <vscale x 4 x i32> [[A:%.*]], <vscale x 8 x i16> [[B:%.*]]) {
+; CHECK-NEXT:    [[OUT2:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.uadalp.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> [[A]], <vscale x 8 x i16> [[B]])
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[OUT2]]
+;
+  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uadalp.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> zeroinitializer, <vscale x 8 x i16> %b)
+  %out2 = add <vscale x 4 x i32> %out, %a
+  ret <vscale x 4 x i32> %out2
+}
+
+define <vscale x 2 x i64> @uadalp_i32_separate_add(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 4 x i32> %b) {
+; CHECK-LABEL: define <vscale x 2 x i64> @uadalp_i32_separate_add(
+; CHECK-SAME: <vscale x 2 x i1> [[PG:%.*]], <vscale x 2 x i64> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) {
+; CHECK-NEXT:    [[OUT2:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.uadalp.nxv2i64(<vscale x 2 x i1> [[PG]], <vscale x 2 x i64> [[A]], <vscale x 4 x i32> [[B]])
+; CHECK-NEXT:    ret <vscale x 2 x i64> [[OUT2]]
+;
+  %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uadalp.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> zeroinitializer, <vscale x 4 x i32> %b)
+  %out2 = add <vscale x 2 x i64> %out, %a
+  ret <vscale x 2 x i64> %out2
+}
+
+define <vscale x 2 x i64> @sadalp_nonzero_accumulator(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 4 x i32> %b, <vscale x 2 x i64> %c) {
+; CHECK-LABEL: define <vscale x 2 x i64> @sadalp_nonzero_accumulator(
+; CHECK-SAME: <vscale x 2 x i1> [[PG:%.*]], <vscale x 2 x i64> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]], <vscale x 2 x i64> [[C:%.*]]) {
+; CHECK-NEXT:    [[OUT:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.sadalp.nxv2i64(<vscale x 2 x i1> [[PG]], <vscale x 2 x i64> [[C]], <vscale x 4 x i32> [[B]])
+; CHECK-NEXT:    [[OUT2:%.*]] = add <vscale x 2 x i64> [[OUT]], [[A]]
+; CHECK-NEXT:    ret <vscale x 2 x i64> [[OUT2]]
+;
+  %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sadalp.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %c, <vscale x 4 x i32> %b)
+  %out2 = add <vscale x 2 x i64> %out, %a
+  ret <vscale x 2 x i64> %out2
+}