diff --git a/llvm/test/Transforms/SLPVectorizer/X86/store-expand-non-pow2.ll b/llvm/test/Transforms/SLPVectorizer/X86/store-expand-non-pow2.ll
new file mode 100644
index 0000000000000..5196bf5cca882
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/store-expand-non-pow2.ll
@@ -0,0 +1,24 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -mtriple=x86_64-apple-macosx10.8.0 -mcpu=skylake-avx512 -passes=slp-vectorizer -S -slp-vectorize-non-power-of-2 %s | FileCheck %s
+; RUN: opt -mtriple=x86_64-apple-macosx10.8.0 -mcpu=skylake-avx512 -passes=slp-vectorizer -slp-enable-masked-stores=false -slp-vectorize-non-power-of-2 -S %s | FileCheck %s
+
+; A tight (gap-free), non-power-of-2 run of 3 consecutive stores. On AVX512 a
+; direct <3 x float> vector store is more expensive than a masked store of the
+; next full width (<4 x float>) with the last lane disabled
+define void @test_v4f32_v3f32_store(<4 x float> %f, ptr %p) {
+; CHECK-LABEL: define void @test_v4f32_v3f32_store(
+; CHECK-SAME: <4 x float> [[F:%.*]], ptr [[P:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x float> [[F]], <4 x float> poison, <3 x i32> <i32 0, i32 1, i32 2>
+; CHECK-NEXT:    store <3 x float> [[TMP1]], ptr [[P]], align 4
+; CHECK-NEXT:    ret void
+;
+  %x0 = extractelement <4 x float> %f, i64 0
+  %x1 = extractelement <4 x float> %f, i64 1
+  %x2 = extractelement <4 x float> %f, i64 2
+  %p1 = getelementptr inbounds float, ptr %p, i64 1
+  %p2 = getelementptr inbounds float, ptr %p, i64 2
+  store float %x0, ptr %p, align 4
+  store float %x1, ptr %p1, align 4
+  store float %x2, ptr %p2, align 4
+  ret void
+}