diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp index 5c4052f942011..a5654613e93c1 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp @@ -133,6 +133,9 @@ class AMDGPURegBankLegalizeCombiner { std::pair tryMatch(Register Src, unsigned Opcode); Register tryMatchUnmergeDefs(SmallVectorImpl &DefRegs); SmallVector tryMatchMergeReadAnyLane(GMergeLikeInstr *Merge); + bool tryMatchMergeReadAnyLaneOrUniform(GMergeLikeInstr *Merge, + SmallVectorImpl &Srcs, + SmallVectorImpl &NeedsBroadcast); SmallVector getReadAnyLaneSrcs(Register Src); void replaceRegWithOrBuildCopy(Register Dst, Register Src); @@ -187,6 +190,29 @@ SmallVector AMDGPURegBankLegalizeCombiner::tryMatchMergeReadAnyLane( return ReadAnyLaneSrcs; } +bool AMDGPURegBankLegalizeCombiner::tryMatchMergeReadAnyLaneOrUniform( + GMergeLikeInstr *Merge, SmallVectorImpl &Srcs, + SmallVectorImpl &NeedsBroadcast) { + bool SawReadAnyLane = false; + for (unsigned I = 0; I < Merge->getNumSources(); ++I) { + Register Op = Merge->getSourceReg(I); + Register RALSrc; + if (mi_match(Op, MRI, m_GAMDGPUReadAnyLane(m_Reg(RALSrc)))) { + Srcs.push_back(RALSrc); + NeedsBroadcast.push_back(false); + SawReadAnyLane = true; + continue; + } + if (MRI.getRegBankOrNull(Op) == SgprRB) { // uniform: broadcast is legal + Srcs.push_back(Op); + NeedsBroadcast.push_back(true); + continue; + } + return false; + } + return SawReadAnyLane; +} + SmallVector AMDGPURegBankLegalizeCombiner::getReadAnyLaneSrcs(Register Src) { // Src = G_AMDGPU_READANYLANE RALSrc @@ -280,8 +306,26 @@ bool AMDGPURegBankLegalizeCombiner::tryEliminateReadAnyLane( B.setInstrAndDebugLoc(Copy); SmallVector ReadAnyLaneSrcRegs = getReadAnyLaneSrcs(RALDst); - if (ReadAnyLaneSrcRegs.empty()) + if (ReadAnyLaneSrcRegs.empty()) { + if (SrcMI.getOpcode() != AMDGPU::G_BITCAST) { + if (auto *Merge = getOpcodeDef(RALDst, MRI)) { + SmallVector Srcs; + SmallVector NeedsBroadcast; + if (tryMatchMergeReadAnyLaneOrUniform(Merge, Srcs, NeedsBroadcast)) { + for (unsigned I = 0; I < Srcs.size(); ++I) + if (NeedsBroadcast[I]) + Srcs[I] = B.buildCopy({VgprRB, MRI.getType(Srcs[I])}, Srcs[I]) + .getReg(0); + auto VgprMerge = + B.buildMergeLikeInstr({VgprRB, MRI.getType(RALDst)}, Srcs); + replaceRegWithOrBuildCopy(Dst, VgprMerge.getReg(0)); + eraseInstr(Copy, MRI); + return true; + } + } + } return false; + } Register ReadAnyLaneSrc; if (ReadAnyLaneSrcRegs.size() == 1) { diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll index 620cba152f5a2..2b0a81b6d278b 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll @@ -248,9 +248,8 @@ define amdgpu_ps void @insertelement_s_v2i8_v_s(ptr addrspace(4) inreg %ptr, i8 ; GFX9-NEXT: v_mov_b32_e32 v3, 0 ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: v_readfirstlane_b32 s0, v1 -; GFX9-NEXT: s_lshr_b32 s1, s0, 8 -; GFX9-NEXT: v_mov_b32_e32 v2, s1 -; GFX9-NEXT: v_mov_b32_e32 v1, s0 +; GFX9-NEXT: s_lshr_b32 s0, s0, 8 +; GFX9-NEXT: v_mov_b32_e32 v2, s0 ; GFX9-NEXT: s_set_gpr_idx_on s4, gpr_idx(DST) ; GFX9-NEXT: v_mov_b32_e32 v1, v0 ; GFX9-NEXT: s_set_gpr_idx_off @@ -270,9 +269,8 @@ define amdgpu_ps void @insertelement_s_v2i8_v_s(ptr addrspace(4) inreg %ptr, i8 ; GFX8-NEXT: v_mov_b32_e32 v3, 0 ; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: v_readfirstlane_b32 s0, v1 -; GFX8-NEXT: s_lshr_b32 s1, s0, 8 -; GFX8-NEXT: v_mov_b32_e32 v2, s1 -; GFX8-NEXT: v_mov_b32_e32 v1, s0 +; GFX8-NEXT: s_lshr_b32 s0, s0, 8 +; GFX8-NEXT: v_mov_b32_e32 v2, s0 ; GFX8-NEXT: v_movreld_b32_e32 v1, v0 ; GFX8-NEXT: v_and_b32_e32 v0, 0xff, v2 ; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0 @@ -292,9 +290,8 @@ define amdgpu_ps void @insertelement_s_v2i8_v_s(ptr addrspace(4) inreg %ptr, i8 ; GFX7-NEXT: s_mov_b64 s[0:1], 0 ; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: v_readfirstlane_b32 s4, v1 -; GFX7-NEXT: s_lshr_b32 s5, s4, 8 -; GFX7-NEXT: v_mov_b32_e32 v1, s4 -; GFX7-NEXT: v_mov_b32_e32 v2, s5 +; GFX7-NEXT: s_lshr_b32 s4, s4, 8 +; GFX7-NEXT: v_mov_b32_e32 v2, s4 ; GFX7-NEXT: v_movreld_b32_e32 v1, v0 ; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v1 ; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v2 @@ -311,9 +308,8 @@ define amdgpu_ps void @insertelement_s_v2i8_v_s(ptr addrspace(4) inreg %ptr, i8 ; GFX10-NEXT: global_load_ushort v1, v1, s[2:3] ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_readfirstlane_b32 s0, v1 -; GFX10-NEXT: s_lshr_b32 s1, s0, 8 -; GFX10-NEXT: v_mov_b32_e32 v1, s0 -; GFX10-NEXT: v_mov_b32_e32 v2, s1 +; GFX10-NEXT: s_lshr_b32 s0, s0, 8 +; GFX10-NEXT: v_mov_b32_e32 v2, s0 ; GFX10-NEXT: v_movreld_b32_e32 v1, v0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0xff ; GFX10-NEXT: v_and_b32_sdwa v0, v2, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD @@ -329,17 +325,17 @@ define amdgpu_ps void @insertelement_s_v2i8_v_s(ptr addrspace(4) inreg %ptr, i8 ; GFX11-TRUE16-NEXT: global_load_u16 v1, v1, s[2:3] ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v1 -; GFX11-TRUE16-NEXT: s_and_b32 s1, 0xffff, s0 +; GFX11-TRUE16-NEXT: s_and_b32 s0, 0xffff, s0 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s1, 8 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, s1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: s_lshr_b32 s0, s0, 8 +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, s0 ; GFX11-TRUE16-NEXT: v_movreld_b32_e32 v1, v0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) ; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v2.l ; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.l ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v0.l +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.h, v0.l ; GFX11-TRUE16-NEXT: global_store_b16 v[1:2], v0, off ; GFX11-TRUE16-NEXT: s_endpgm @@ -351,16 +347,15 @@ define amdgpu_ps void @insertelement_s_v2i8_v_s(ptr addrspace(4) inreg %ptr, i8 ; GFX11-FAKE16-NEXT: global_load_u16 v1, v1, s[2:3] ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s0, v1 -; GFX11-FAKE16-NEXT: s_lshr_b32 s1, s0, 8 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, s1 +; GFX11-FAKE16-NEXT: s_lshr_b32 s0, s0, 8 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, s0 ; GFX11-FAKE16-NEXT: v_movreld_b32_e32 v1, v0 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v2 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v2, 0xff, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v0 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3 ; GFX11-FAKE16-NEXT: global_store_b16 v[0:1], v2, off ; GFX11-FAKE16-NEXT: s_endpgm @@ -379,17 +374,16 @@ define amdgpu_ps void @insertelement_s_v2i8_s_v(ptr addrspace(4) inreg %ptr, i8 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: v_readfirstlane_b32 s0, v1 -; GFX9-NEXT: s_lshr_b32 s1, s0, 8 +; GFX9-NEXT: s_lshr_b32 s0, s0, 8 +; GFX9-NEXT: v_cndmask_b32_e32 v3, v1, v2, vcc ; GFX9-NEXT: v_mov_b32_e32 v1, s0 -; GFX9-NEXT: v_mov_b32_e32 v3, s1 -; GFX9-NEXT: v_cndmask_b32_e32 v4, v1, v2, vcc ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc ; GFX9-NEXT: v_and_b32_e32 v0, 0xff, v0 ; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0 -; GFX9-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX9-NEXT: global_store_short v[0:1], v2, off ; GFX9-NEXT: s_endpgm ; @@ -402,17 +396,16 @@ define amdgpu_ps void @insertelement_s_v2i8_s_v(ptr addrspace(4) inreg %ptr, i8 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: v_readfirstlane_b32 s0, v1 -; GFX8-NEXT: s_lshr_b32 s1, s0, 8 +; GFX8-NEXT: s_lshr_b32 s0, s0, 8 +; GFX8-NEXT: v_cndmask_b32_e32 v3, v1, v2, vcc ; GFX8-NEXT: v_mov_b32_e32 v1, s0 -; GFX8-NEXT: v_mov_b32_e32 v3, s1 -; GFX8-NEXT: v_cndmask_b32_e32 v4, v1, v2, vcc ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 -; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc ; GFX8-NEXT: v_and_b32_e32 v0, 0xff, v0 ; GFX8-NEXT: v_lshlrev_b16_e32 v2, 8, v0 ; GFX8-NEXT: v_mov_b32_e32 v0, 0 ; GFX8-NEXT: v_mov_b32_e32 v1, 0 -; GFX8-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX8-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX8-NEXT: flat_store_short v[0:1], v2 ; GFX8-NEXT: s_endpgm ; @@ -428,10 +421,9 @@ define amdgpu_ps void @insertelement_s_v2i8_s_v(ptr addrspace(4) inreg %ptr, i8 ; GFX7-NEXT: s_mov_b64 s[0:1], 0 ; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: v_readfirstlane_b32 s4, v1 -; GFX7-NEXT: s_lshr_b32 s5, s4, 8 -; GFX7-NEXT: v_mov_b32_e32 v1, s4 -; GFX7-NEXT: v_mov_b32_e32 v3, s5 +; GFX7-NEXT: s_lshr_b32 s4, s4, 8 ; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; GFX7-NEXT: v_mov_b32_e32 v3, s4 ; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 ; GFX7-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v0 @@ -444,69 +436,65 @@ define amdgpu_ps void @insertelement_s_v2i8_s_v(ptr addrspace(4) inreg %ptr, i8 ; GFX10-LABEL: insertelement_s_v2i8_s_v: ; GFX10: ; %bb.0: ; GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GFX10-NEXT: v_mov_b32_e32 v2, s4 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 ; GFX10-NEXT: v_mov_b32_e32 v3, 0xff ; GFX10-NEXT: global_load_ushort v1, v1, s[2:3] ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_readfirstlane_b32 s0, v1 -; GFX10-NEXT: s_lshr_b32 s1, s0, 8 -; GFX10-NEXT: v_mov_b32_e32 v2, s0 -; GFX10-NEXT: v_mov_b32_e32 v1, s1 -; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo +; GFX10-NEXT: s_lshr_b32 s0, s0, 8 +; GFX10-NEXT: v_cndmask_b32_e32 v2, s0, v2, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0 -; GFX10-NEXT: v_and_b32_sdwa v3, v1, v3 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s4, vcc_lo +; GFX10-NEXT: v_and_b32_sdwa v2, v2, v3 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX10-NEXT: v_cndmask_b32_e64 v4, v1, s4, vcc_lo ; GFX10-NEXT: v_mov_b32_e32 v1, 0 -; GFX10-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX10-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX10-NEXT: global_store_short v[0:1], v2, off ; GFX10-NEXT: s_endpgm ; ; GFX11-TRUE16-LABEL: insertelement_s_v2i8_s_v: ; GFX11-TRUE16: ; %bb.0: -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s4 ; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 ; GFX11-TRUE16-NEXT: global_load_u16 v1, v1, s[2:3] ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v1 -; GFX11-TRUE16-NEXT: s_and_b32 s1, 0xffff, s0 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, s0 -; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s1, 8 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo +; GFX11-TRUE16-NEXT: s_and_b32 s0, 0xffff, s0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-TRUE16-NEXT: s_lshr_b32 s0, s0, 8 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, s0, v2, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v1.l -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v2, s4, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.l ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v0.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.l +; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v2.l ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v0.l +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.h, v0.l ; GFX11-TRUE16-NEXT: global_store_b16 v[1:2], v0, off ; GFX11-TRUE16-NEXT: s_endpgm ; ; GFX11-FAKE16-LABEL: insertelement_s_v2i8_s_v: ; GFX11-FAKE16: ; %bb.0: -; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s4 ; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 ; GFX11-FAKE16-NEXT: global_load_u16 v1, v1, s[2:3] ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s0, v1 -; GFX11-FAKE16-NEXT: s_lshr_b32 s1, s0, 8 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v1, s1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo +; GFX11-FAKE16-NEXT: s_lshr_b32 s0, s0, 8 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, s0, v2, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v2, s4, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v1 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v2, 0xff, v0 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v1, s4, vcc_lo +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v2 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v0 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v1 +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, 0 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3 ; GFX11-FAKE16-NEXT: global_store_b16 v[0:1], v2, off @@ -525,10 +513,9 @@ define amdgpu_ps void @insertelement_s_v2i8_v_v(ptr addrspace(4) inreg %ptr, i8 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: v_readfirstlane_b32 s0, v2 -; GFX9-NEXT: s_lshr_b32 s1, s0, 8 -; GFX9-NEXT: v_mov_b32_e32 v2, s0 -; GFX9-NEXT: v_mov_b32_e32 v3, s1 +; GFX9-NEXT: s_lshr_b32 s0, s0, 8 ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc +; GFX9-NEXT: v_mov_b32_e32 v3, s0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX9-NEXT: v_and_b32_e32 v0, 0xff, v0 @@ -547,10 +534,9 @@ define amdgpu_ps void @insertelement_s_v2i8_v_v(ptr addrspace(4) inreg %ptr, i8 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: v_readfirstlane_b32 s0, v2 -; GFX8-NEXT: s_lshr_b32 s1, s0, 8 -; GFX8-NEXT: v_mov_b32_e32 v2, s0 -; GFX8-NEXT: v_mov_b32_e32 v3, s1 +; GFX8-NEXT: s_lshr_b32 s0, s0, 8 ; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc +; GFX8-NEXT: v_mov_b32_e32 v3, s0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX8-NEXT: v_and_b32_e32 v0, 0xff, v0 @@ -572,10 +558,9 @@ define amdgpu_ps void @insertelement_s_v2i8_v_v(ptr addrspace(4) inreg %ptr, i8 ; GFX7-NEXT: s_mov_b64 s[0:1], 0 ; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: v_readfirstlane_b32 s4, v2 -; GFX7-NEXT: s_lshr_b32 s5, s4, 8 -; GFX7-NEXT: v_mov_b32_e32 v2, s4 -; GFX7-NEXT: v_mov_b32_e32 v3, s5 +; GFX7-NEXT: s_lshr_b32 s4, s4, 8 ; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc +; GFX7-NEXT: v_mov_b32_e32 v3, s4 ; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1 ; GFX7-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v0 @@ -589,18 +574,18 @@ define amdgpu_ps void @insertelement_s_v2i8_v_v(ptr addrspace(4) inreg %ptr, i8 ; GFX10: ; %bb.0: ; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 -; GFX10-NEXT: v_mov_b32_e32 v3, 0xff +; GFX10-NEXT: v_mov_b32_e32 v4, 0xff ; GFX10-NEXT: global_load_ushort v2, v2, s[2:3] ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_readfirstlane_b32 s0, v2 -; GFX10-NEXT: s_lshr_b32 s1, s0, 8 -; GFX10-NEXT: v_cndmask_b32_e32 v2, s1, v0, vcc_lo +; GFX10-NEXT: s_lshr_b32 s0, s0, 8 +; GFX10-NEXT: v_cndmask_b32_e32 v3, s0, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 ; GFX10-NEXT: v_mov_b32_e32 v1, 0 -; GFX10-NEXT: v_and_b32_sdwa v2, v2, v3 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX10-NEXT: v_cndmask_b32_e32 v4, s0, v0, vcc_lo +; GFX10-NEXT: v_and_b32_sdwa v3, v3, v4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo ; GFX10-NEXT: v_mov_b32_e32 v0, 0 -; GFX10-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX10-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX10-NEXT: global_store_short v[0:1], v2, off ; GFX10-NEXT: s_endpgm ; @@ -611,19 +596,18 @@ define amdgpu_ps void @insertelement_s_v2i8_v_v(ptr addrspace(4) inreg %ptr, i8 ; GFX11-TRUE16-NEXT: global_load_u16 v2, v2, s[2:3] ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v2 -; GFX11-TRUE16-NEXT: s_and_b32 s1, 0xffff, s0 +; GFX11-TRUE16-NEXT: s_and_b32 s0, 0xffff, s0 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s1, 8 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, s1, v0, vcc_lo +; GFX11-TRUE16-NEXT: s_lshr_b32 s0, s0, 8 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, s0, v0, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, s0, v0, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v2.l -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v2, v0 :: v_dual_mov_b32 v2, 0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v3.l ; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v0.l ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v0.l ; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.h, v0.l ; GFX11-TRUE16-NEXT: global_store_b16 v[1:2], v0, off ; GFX11-TRUE16-NEXT: s_endpgm @@ -635,15 +619,14 @@ define amdgpu_ps void @insertelement_s_v2i8_v_v(ptr addrspace(4) inreg %ptr, i8 ; GFX11-FAKE16-NEXT: global_load_u16 v2, v2, s[2:3] ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s0, v2 -; GFX11-FAKE16-NEXT: s_lshr_b32 s1, s0, 8 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, s1, v0, vcc_lo +; GFX11-FAKE16-NEXT: s_lshr_b32 s0, s0, 8 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, s0, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v2 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, s0, v0, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v0 -; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_and_b32 v1, 0xff, v3 ; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v1 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, 0 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll index aacb305a003ab..9359a668aa1e6 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll @@ -3851,15 +3851,13 @@ define amdgpu_kernel void @s_mul_u64_zext_with_sregs(ptr addrspace(1) %out, ptr ; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 ; GFX7-NEXT: v_mov_b32_e32 v0, 0x50 ; GFX7-NEXT: s_waitcnt lgkmcnt(0) -; GFX7-NEXT: s_load_dword s3, s[2:3], 0x0 -; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_load_dword s2, s[2:3], 0x0 ; GFX7-NEXT: s_waitcnt lgkmcnt(0) -; GFX7-NEXT: v_mul_hi_u32 v0, s3, v0 -; GFX7-NEXT: s_mul_i32 s4, s3, 0x50 +; GFX7-NEXT: v_mul_hi_u32 v1, s2, v0 +; GFX7-NEXT: s_mul_i32 s3, s2, 0x50 +; GFX7-NEXT: v_mov_b32_e32 v0, s3 +; GFX7-NEXT: s_mov_b32 s2, -1 ; GFX7-NEXT: s_mov_b32 s3, 0xf000 -; GFX7-NEXT: v_readfirstlane_b32 s5, v0 -; GFX7-NEXT: v_mov_b32_e32 v0, s4 -; GFX7-NEXT: v_mov_b32_e32 v1, s5 ; GFX7-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX7-NEXT: s_endpgm ; @@ -3872,11 +3870,9 @@ define amdgpu_kernel void @s_mul_u64_zext_with_sregs(ptr addrspace(1) %out, ptr ; GFX8-NEXT: v_mov_b32_e32 v3, s1 ; GFX8-NEXT: v_mov_b32_e32 v2, s0 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) -; GFX8-NEXT: v_mul_hi_u32 v0, s2, v0 +; GFX8-NEXT: v_mul_hi_u32 v1, s2, v0 ; GFX8-NEXT: s_mulk_i32 s2, 0x50 -; GFX8-NEXT: v_readfirstlane_b32 s3, v0 ; GFX8-NEXT: v_mov_b32_e32 v0, s2 -; GFX8-NEXT: v_mov_b32_e32 v1, s3 ; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; GFX8-NEXT: s_endpgm ; diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.mir index 69789b3bef9be..c68185f3edcc3 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/readanylane-combines.mir @@ -501,3 +501,61 @@ body: | SI_RETURN_TO_EPILOG implicit $vgpr0_vgpr1 ... +--- +name: op_readanylane_and_uniform_merge_to_virtual_vgpr +legalized: true +body: | + bb.0: + liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 + + ; CHECK-LABEL: name: op_readanylane_and_uniform_merge_to_virtual_vgpr + ; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 + ; CHECK-NEXT: [[MV:%[0-9]+]]:sgpr(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY3]](s32) + ; CHECK-NEXT: [[FCANONICALIZE:%[0-9]+]]:vgpr(s32) = G_FCANONICALIZE [[COPY4]] + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY5]](s32), [[FCANONICALIZE]](s32) + ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s32>), [[MV]](p1) :: (store (<2 x s32>), addrspace 1) + ; CHECK-NEXT: S_ENDPGM 0 + %0:sgpr(s32) = COPY $sgpr0 + %1:sgpr(s32) = COPY $sgpr1 + %2:sgpr(p1) = G_MERGE_VALUES %0(s32), %1(s32) + %3:sgpr(s32) = COPY $sgpr2 + %4:sgpr(s32) = COPY $sgpr3 + %5:sgpr(s32) = G_FCANONICALIZE %4 + %6:sgpr(<2 x s32>) = G_BUILD_VECTOR %3(s32), %5(s32) + G_STORE %6(<2 x s32>), %2(p1) :: (store (<2 x s32>), addrspace 1) + S_ENDPGM 0 +... + +--- +name: op_readanylane_and_uniform_merge_to_physical_vgpr +legalized: true +body: | + bb.0: + liveins: $sgpr0, $sgpr1 + + ; CHECK-LABEL: name: op_readanylane_and_uniform_merge_to_physical_vgpr + ; CHECK: liveins: $sgpr0, $sgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) + ; CHECK-NEXT: [[FCANONICALIZE:%[0-9]+]]:vgpr(s32) = G_FCANONICALIZE [[COPY2]] + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[FCANONICALIZE]](s32) + ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) + ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0_vgpr1 + %0:sgpr(s32) = COPY $sgpr0 + %1:sgpr(s32) = COPY $sgpr1 + %2:sgpr(s32) = G_FCANONICALIZE %1 + %3:sgpr(<2 x s32>) = G_BUILD_VECTOR %0(s32), %2(s32) + $vgpr0_vgpr1 = COPY %3(<2 x s32>) + SI_RETURN_TO_EPILOG implicit $vgpr0_vgpr1 +... + diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll index d8117b76fb576..2220d2425881f 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll @@ -224,77 +224,40 @@ define amdgpu_ps <4 x float> @image_bvh_intersect_ray_a16(i32 inreg %node_ptr, f ; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX10-SDAG-NEXT: ; return to shader part epilog ; -; GFX1013-GISEL-LABEL: image_bvh_intersect_ray_a16: -; GFX1013-GISEL: ; %bb.0: ; %main_body -; GFX1013-GISEL-NEXT: s_and_b32 s8, s8, 0xffff -; GFX1013-GISEL-NEXT: s_mov_b32 s16, s9 -; GFX1013-GISEL-NEXT: v_alignbit_b32 v0, s8, s7, 16 -; GFX1013-GISEL-NEXT: s_lshr_b32 s9, s5, 16 -; GFX1013-GISEL-NEXT: s_and_b32 s5, s5, 0xffff -; GFX1013-GISEL-NEXT: s_lshl_b32 s8, s9, 16 -; GFX1013-GISEL-NEXT: s_and_b32 s9, s7, 0xffff -; GFX1013-GISEL-NEXT: v_readfirstlane_b32 s7, v0 -; GFX1013-GISEL-NEXT: s_and_b32 s6, s6, 0xffff -; GFX1013-GISEL-NEXT: s_lshl_b32 s9, s9, 16 -; GFX1013-GISEL-NEXT: s_or_b32 s5, s5, s8 -; GFX1013-GISEL-NEXT: s_or_b32 s6, s6, s9 -; GFX1013-GISEL-NEXT: v_mov_b32_e32 v0, s0 -; GFX1013-GISEL-NEXT: v_mov_b32_e32 v1, s1 -; GFX1013-GISEL-NEXT: v_mov_b32_e32 v2, s2 -; GFX1013-GISEL-NEXT: v_mov_b32_e32 v3, s3 -; GFX1013-GISEL-NEXT: v_mov_b32_e32 v4, s4 -; GFX1013-GISEL-NEXT: v_mov_b32_e32 v5, s5 -; GFX1013-GISEL-NEXT: v_mov_b32_e32 v6, s6 -; GFX1013-GISEL-NEXT: v_mov_b32_e32 v7, s7 -; GFX1013-GISEL-NEXT: s_mov_b32 s17, s10 -; GFX1013-GISEL-NEXT: s_mov_b32 s18, s11 -; GFX1013-GISEL-NEXT: s_mov_b32 s19, s12 -; GFX1013-GISEL-NEXT: image_bvh_intersect_ray v[0:3], v[0:7], s[16:19] a16 -; GFX1013-GISEL-NEXT: s_waitcnt vmcnt(0) -; GFX1013-GISEL-NEXT: v_readfirstlane_b32 s0, v0 -; GFX1013-GISEL-NEXT: v_readfirstlane_b32 s1, v1 -; GFX1013-GISEL-NEXT: v_readfirstlane_b32 s2, v2 -; GFX1013-GISEL-NEXT: v_readfirstlane_b32 s3, v3 -; GFX1013-GISEL-NEXT: v_mov_b32_e32 v0, s0 -; GFX1013-GISEL-NEXT: v_mov_b32_e32 v1, s1 -; GFX1013-GISEL-NEXT: v_mov_b32_e32 v2, s2 -; GFX1013-GISEL-NEXT: v_mov_b32_e32 v3, s3 -; GFX1013-GISEL-NEXT: ; return to shader part epilog -; -; GFX1030-GISEL-LABEL: image_bvh_intersect_ray_a16: -; GFX1030-GISEL: ; %bb.0: ; %main_body -; GFX1030-GISEL-NEXT: s_mov_b32 s16, s9 -; GFX1030-GISEL-NEXT: s_lshr_b32 s9, s5, 16 -; GFX1030-GISEL-NEXT: s_and_b32 s5, s5, 0xffff -; GFX1030-GISEL-NEXT: s_lshl_b32 s9, s9, 16 -; GFX1030-GISEL-NEXT: s_and_b32 s6, s6, 0xffff -; GFX1030-GISEL-NEXT: s_or_b32 s5, s5, s9 -; GFX1030-GISEL-NEXT: s_and_b32 s9, s7, 0xffff -; GFX1030-GISEL-NEXT: s_and_b32 s8, s8, 0xffff -; GFX1030-GISEL-NEXT: s_lshl_b32 s9, s9, 16 -; GFX1030-GISEL-NEXT: v_alignbit_b32 v7, s8, s7, 16 -; GFX1030-GISEL-NEXT: s_or_b32 s6, s6, s9 -; GFX1030-GISEL-NEXT: v_mov_b32_e32 v0, s0 -; GFX1030-GISEL-NEXT: v_mov_b32_e32 v1, s1 -; GFX1030-GISEL-NEXT: v_mov_b32_e32 v2, s2 -; GFX1030-GISEL-NEXT: v_mov_b32_e32 v3, s3 -; GFX1030-GISEL-NEXT: v_mov_b32_e32 v4, s4 -; GFX1030-GISEL-NEXT: v_mov_b32_e32 v5, s5 -; GFX1030-GISEL-NEXT: v_mov_b32_e32 v6, s6 -; GFX1030-GISEL-NEXT: s_mov_b32 s17, s10 -; GFX1030-GISEL-NEXT: s_mov_b32 s18, s11 -; GFX1030-GISEL-NEXT: s_mov_b32 s19, s12 -; GFX1030-GISEL-NEXT: image_bvh_intersect_ray v[0:3], v[0:7], s[16:19] a16 -; GFX1030-GISEL-NEXT: s_waitcnt vmcnt(0) -; GFX1030-GISEL-NEXT: v_readfirstlane_b32 s0, v0 -; GFX1030-GISEL-NEXT: v_readfirstlane_b32 s1, v1 -; GFX1030-GISEL-NEXT: v_readfirstlane_b32 s2, v2 -; GFX1030-GISEL-NEXT: v_readfirstlane_b32 s3, v3 -; GFX1030-GISEL-NEXT: v_mov_b32_e32 v0, s0 -; GFX1030-GISEL-NEXT: v_mov_b32_e32 v1, s1 -; GFX1030-GISEL-NEXT: v_mov_b32_e32 v2, s2 -; GFX1030-GISEL-NEXT: v_mov_b32_e32 v3, s3 -; GFX1030-GISEL-NEXT: ; return to shader part epilog +; GFX10-GISEL-LABEL: image_bvh_intersect_ray_a16: +; GFX10-GISEL: ; %bb.0: ; %main_body +; GFX10-GISEL-NEXT: s_mov_b32 s16, s9 +; GFX10-GISEL-NEXT: s_lshr_b32 s9, s5, 16 +; GFX10-GISEL-NEXT: s_and_b32 s5, s5, 0xffff +; GFX10-GISEL-NEXT: s_lshl_b32 s9, s9, 16 +; GFX10-GISEL-NEXT: s_and_b32 s6, s6, 0xffff +; GFX10-GISEL-NEXT: s_or_b32 s5, s5, s9 +; GFX10-GISEL-NEXT: s_and_b32 s9, s7, 0xffff +; GFX10-GISEL-NEXT: s_and_b32 s8, s8, 0xffff +; GFX10-GISEL-NEXT: s_lshl_b32 s9, s9, 16 +; GFX10-GISEL-NEXT: v_alignbit_b32 v7, s8, s7, 16 +; GFX10-GISEL-NEXT: s_or_b32 s6, s6, s9 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s2 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s3 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v4, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v5, s5 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v6, s6 +; GFX10-GISEL-NEXT: s_mov_b32 s17, s10 +; GFX10-GISEL-NEXT: s_mov_b32 s18, s11 +; GFX10-GISEL-NEXT: s_mov_b32 s19, s12 +; GFX10-GISEL-NEXT: image_bvh_intersect_ray v[0:3], v[0:7], s[16:19] a16 +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX10-GISEL-NEXT: v_readfirstlane_b32 s0, v0 +; GFX10-GISEL-NEXT: v_readfirstlane_b32 s1, v1 +; GFX10-GISEL-NEXT: v_readfirstlane_b32 s2, v2 +; GFX10-GISEL-NEXT: v_readfirstlane_b32 s3, v3 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s2 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s3 +; GFX10-GISEL-NEXT: ; return to shader part epilog ; ; GFX11-SDAG-LABEL: image_bvh_intersect_ray_a16: ; GFX11-SDAG: ; %bb.0: ; %main_body @@ -526,79 +489,41 @@ define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_a16(i64 inreg %node_ptr, ; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX10-SDAG-NEXT: ; return to shader part epilog ; -; GFX1013-GISEL-LABEL: image_bvh64_intersect_ray_a16: -; GFX1013-GISEL: ; %bb.0: ; %main_body -; GFX1013-GISEL-NEXT: s_and_b32 s9, s9, 0xffff -; GFX1013-GISEL-NEXT: s_mov_b32 s16, s10 -; GFX1013-GISEL-NEXT: v_alignbit_b32 v0, s9, s8, 16 -; GFX1013-GISEL-NEXT: s_lshr_b32 s10, s6, 16 -; GFX1013-GISEL-NEXT: s_and_b32 s6, s6, 0xffff -; GFX1013-GISEL-NEXT: s_lshl_b32 s9, s10, 16 -; GFX1013-GISEL-NEXT: s_and_b32 s10, s8, 0xffff -; GFX1013-GISEL-NEXT: v_readfirstlane_b32 s8, v0 -; GFX1013-GISEL-NEXT: s_and_b32 s7, s7, 0xffff -; GFX1013-GISEL-NEXT: s_lshl_b32 s10, s10, 16 -; GFX1013-GISEL-NEXT: s_or_b32 s6, s6, s9 -; GFX1013-GISEL-NEXT: s_or_b32 s7, s7, s10 -; GFX1013-GISEL-NEXT: v_mov_b32_e32 v0, s0 -; GFX1013-GISEL-NEXT: v_mov_b32_e32 v1, s1 -; GFX1013-GISEL-NEXT: v_mov_b32_e32 v2, s2 -; GFX1013-GISEL-NEXT: v_mov_b32_e32 v3, s3 -; GFX1013-GISEL-NEXT: v_mov_b32_e32 v4, s4 -; GFX1013-GISEL-NEXT: v_mov_b32_e32 v5, s5 -; GFX1013-GISEL-NEXT: v_mov_b32_e32 v6, s6 -; GFX1013-GISEL-NEXT: v_mov_b32_e32 v7, s7 -; GFX1013-GISEL-NEXT: v_mov_b32_e32 v8, s8 -; GFX1013-GISEL-NEXT: s_mov_b32 s17, s11 -; GFX1013-GISEL-NEXT: s_mov_b32 s18, s12 -; GFX1013-GISEL-NEXT: s_mov_b32 s19, s13 -; GFX1013-GISEL-NEXT: image_bvh64_intersect_ray v[0:3], v[0:8], s[16:19] a16 -; GFX1013-GISEL-NEXT: s_waitcnt vmcnt(0) -; GFX1013-GISEL-NEXT: v_readfirstlane_b32 s0, v0 -; GFX1013-GISEL-NEXT: v_readfirstlane_b32 s1, v1 -; GFX1013-GISEL-NEXT: v_readfirstlane_b32 s2, v2 -; GFX1013-GISEL-NEXT: v_readfirstlane_b32 s3, v3 -; GFX1013-GISEL-NEXT: v_mov_b32_e32 v0, s0 -; GFX1013-GISEL-NEXT: v_mov_b32_e32 v1, s1 -; GFX1013-GISEL-NEXT: v_mov_b32_e32 v2, s2 -; GFX1013-GISEL-NEXT: v_mov_b32_e32 v3, s3 -; GFX1013-GISEL-NEXT: ; return to shader part epilog -; -; GFX1030-GISEL-LABEL: image_bvh64_intersect_ray_a16: -; GFX1030-GISEL: ; %bb.0: ; %main_body -; GFX1030-GISEL-NEXT: s_mov_b32 s16, s10 -; GFX1030-GISEL-NEXT: s_lshr_b32 s10, s6, 16 -; GFX1030-GISEL-NEXT: s_and_b32 s6, s6, 0xffff -; GFX1030-GISEL-NEXT: s_lshl_b32 s10, s10, 16 -; GFX1030-GISEL-NEXT: s_and_b32 s7, s7, 0xffff -; GFX1030-GISEL-NEXT: s_or_b32 s6, s6, s10 -; GFX1030-GISEL-NEXT: s_and_b32 s10, s8, 0xffff -; GFX1030-GISEL-NEXT: s_and_b32 s9, s9, 0xffff -; GFX1030-GISEL-NEXT: s_lshl_b32 s10, s10, 16 -; GFX1030-GISEL-NEXT: v_alignbit_b32 v8, s9, s8, 16 -; GFX1030-GISEL-NEXT: s_or_b32 s7, s7, s10 -; GFX1030-GISEL-NEXT: v_mov_b32_e32 v0, s0 -; GFX1030-GISEL-NEXT: v_mov_b32_e32 v1, s1 -; GFX1030-GISEL-NEXT: v_mov_b32_e32 v2, s2 -; GFX1030-GISEL-NEXT: v_mov_b32_e32 v3, s3 -; GFX1030-GISEL-NEXT: v_mov_b32_e32 v4, s4 -; GFX1030-GISEL-NEXT: v_mov_b32_e32 v5, s5 -; GFX1030-GISEL-NEXT: v_mov_b32_e32 v6, s6 -; GFX1030-GISEL-NEXT: v_mov_b32_e32 v7, s7 -; GFX1030-GISEL-NEXT: s_mov_b32 s17, s11 -; GFX1030-GISEL-NEXT: s_mov_b32 s18, s12 -; GFX1030-GISEL-NEXT: s_mov_b32 s19, s13 -; GFX1030-GISEL-NEXT: image_bvh64_intersect_ray v[0:3], v[0:8], s[16:19] a16 -; GFX1030-GISEL-NEXT: s_waitcnt vmcnt(0) -; GFX1030-GISEL-NEXT: v_readfirstlane_b32 s0, v0 -; GFX1030-GISEL-NEXT: v_readfirstlane_b32 s1, v1 -; GFX1030-GISEL-NEXT: v_readfirstlane_b32 s2, v2 -; GFX1030-GISEL-NEXT: v_readfirstlane_b32 s3, v3 -; GFX1030-GISEL-NEXT: v_mov_b32_e32 v0, s0 -; GFX1030-GISEL-NEXT: v_mov_b32_e32 v1, s1 -; GFX1030-GISEL-NEXT: v_mov_b32_e32 v2, s2 -; GFX1030-GISEL-NEXT: v_mov_b32_e32 v3, s3 -; GFX1030-GISEL-NEXT: ; return to shader part epilog +; GFX10-GISEL-LABEL: image_bvh64_intersect_ray_a16: +; GFX10-GISEL: ; %bb.0: ; %main_body +; GFX10-GISEL-NEXT: s_mov_b32 s16, s10 +; GFX10-GISEL-NEXT: s_lshr_b32 s10, s6, 16 +; GFX10-GISEL-NEXT: s_and_b32 s6, s6, 0xffff +; GFX10-GISEL-NEXT: s_lshl_b32 s10, s10, 16 +; GFX10-GISEL-NEXT: s_and_b32 s7, s7, 0xffff +; GFX10-GISEL-NEXT: s_or_b32 s6, s6, s10 +; GFX10-GISEL-NEXT: s_and_b32 s10, s8, 0xffff +; GFX10-GISEL-NEXT: s_and_b32 s9, s9, 0xffff +; GFX10-GISEL-NEXT: s_lshl_b32 s10, s10, 16 +; GFX10-GISEL-NEXT: v_alignbit_b32 v8, s9, s8, 16 +; GFX10-GISEL-NEXT: s_or_b32 s7, s7, s10 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s2 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s3 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v4, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v5, s5 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v6, s6 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v7, s7 +; GFX10-GISEL-NEXT: s_mov_b32 s17, s11 +; GFX10-GISEL-NEXT: s_mov_b32 s18, s12 +; GFX10-GISEL-NEXT: s_mov_b32 s19, s13 +; GFX10-GISEL-NEXT: image_bvh64_intersect_ray v[0:3], v[0:8], s[16:19] a16 +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX10-GISEL-NEXT: v_readfirstlane_b32 s0, v0 +; GFX10-GISEL-NEXT: v_readfirstlane_b32 s1, v1 +; GFX10-GISEL-NEXT: v_readfirstlane_b32 s2, v2 +; GFX10-GISEL-NEXT: v_readfirstlane_b32 s3, v3 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s2 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s3 +; GFX10-GISEL-NEXT: ; return to shader part epilog ; ; GFX11-SDAG-LABEL: image_bvh64_intersect_ray_a16: ; GFX11-SDAG: ; %bb.0: ; %main_body diff --git a/llvm/test/CodeGen/AMDGPU/packed-fp32.ll b/llvm/test/CodeGen/AMDGPU/packed-fp32.ll index 8544b84a6d6f5..d2c674beca80d 100644 --- a/llvm/test/CodeGen/AMDGPU/packed-fp32.ll +++ b/llvm/test/CodeGen/AMDGPU/packed-fp32.ll @@ -1047,37 +1047,20 @@ define amdgpu_kernel void @fadd_v2_v_fneg_lo(ptr addrspace(1) %a, float %x) { ; PACKED-SDAG-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; PACKED-SDAG-NEXT: s_endpgm ; -; GFX90A-GISEL-LABEL: fadd_v2_v_fneg_lo: -; GFX90A-GISEL: ; %bb.0: -; GFX90A-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 -; GFX90A-GISEL-NEXT: s_load_dword s3, s[4:5], 0x2c -; GFX90A-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0 -; GFX90A-GISEL-NEXT: v_lshlrev_b32_e32 v2, 3, v0 -; GFX90A-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX90A-GISEL-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1] -; GFX90A-GISEL-NEXT: v_max_f32_e64 v3, -s3, -s3 -; GFX90A-GISEL-NEXT: v_readfirstlane_b32 s2, v3 -; GFX90A-GISEL-NEXT: s_waitcnt vmcnt(0) -; GFX90A-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], s[2:3] -; GFX90A-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] -; GFX90A-GISEL-NEXT: s_endpgm -; -; GFX942-GISEL-LABEL: fadd_v2_v_fneg_lo: -; GFX942-GISEL: ; %bb.0: -; GFX942-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 -; GFX942-GISEL-NEXT: s_load_dword s3, s[4:5], 0x2c -; GFX942-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0 -; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v2, 3, v0 -; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-GISEL-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1] -; GFX942-GISEL-NEXT: v_max_f32_e64 v3, -s3, -s3 -; GFX942-GISEL-NEXT: s_nop 0 -; GFX942-GISEL-NEXT: v_readfirstlane_b32 s2, v3 -; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0) -; GFX942-GISEL-NEXT: s_nop 0 -; GFX942-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], s[2:3] -; GFX942-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] -; GFX942-GISEL-NEXT: s_endpgm +; PACKED-GISEL-LABEL: fadd_v2_v_fneg_lo: +; PACKED-GISEL: ; %bb.0: +; PACKED-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; PACKED-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c +; PACKED-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; PACKED-GISEL-NEXT: v_lshlrev_b32_e32 v4, 3, v0 +; PACKED-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; PACKED-GISEL-NEXT: global_load_dwordx2 v[0:1], v4, s[0:1] +; PACKED-GISEL-NEXT: v_mov_b32_e32 v3, s2 +; PACKED-GISEL-NEXT: v_max_f32_e64 v2, -s2, -s2 +; PACKED-GISEL-NEXT: s_waitcnt vmcnt(0) +; PACKED-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], v[2:3] +; PACKED-GISEL-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1] +; PACKED-GISEL-NEXT: s_endpgm ; ; GFX1250-SDAG-LABEL: fadd_v2_v_fneg_lo: ; GFX1250-SDAG: ; %bb.0: @@ -1102,11 +1085,8 @@ define amdgpu_kernel void @fadd_v2_v_fneg_lo(ptr addrspace(1) %a, float %x) { ; GFX1250-GISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v0 ; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX1250-GISEL-NEXT: global_load_b64 v[0:1], v4, s[0:1] scale_offset +; GFX1250-GISEL-NEXT: v_mov_b32_e32 v3, s2 ; GFX1250-GISEL-NEXT: v_max_num_f32_e64 v2, -s2, -s2 -; GFX1250-GISEL-NEXT: s_mov_b32 s5, s2 -; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s4, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[4:5] ; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0 ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], v[2:3] @@ -1150,37 +1130,20 @@ define amdgpu_kernel void @fadd_v2_v_fneg_hi(ptr addrspace(1) %a, float %x) { ; PACKED-SDAG-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; PACKED-SDAG-NEXT: s_endpgm ; -; GFX90A-GISEL-LABEL: fadd_v2_v_fneg_hi: -; GFX90A-GISEL: ; %bb.0: -; GFX90A-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 -; GFX90A-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c -; GFX90A-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0 -; GFX90A-GISEL-NEXT: v_lshlrev_b32_e32 v2, 3, v0 -; GFX90A-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX90A-GISEL-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1] -; GFX90A-GISEL-NEXT: v_max_f32_e64 v3, -s2, -s2 -; GFX90A-GISEL-NEXT: v_readfirstlane_b32 s3, v3 -; GFX90A-GISEL-NEXT: s_waitcnt vmcnt(0) -; GFX90A-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], s[2:3] -; GFX90A-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] -; GFX90A-GISEL-NEXT: s_endpgm -; -; GFX942-GISEL-LABEL: fadd_v2_v_fneg_hi: -; GFX942-GISEL: ; %bb.0: -; GFX942-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 -; GFX942-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c -; GFX942-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0 -; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v2, 3, v0 -; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-GISEL-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1] -; GFX942-GISEL-NEXT: v_max_f32_e64 v3, -s2, -s2 -; GFX942-GISEL-NEXT: s_nop 0 -; GFX942-GISEL-NEXT: v_readfirstlane_b32 s3, v3 -; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0) -; GFX942-GISEL-NEXT: s_nop 0 -; GFX942-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], s[2:3] -; GFX942-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] -; GFX942-GISEL-NEXT: s_endpgm +; PACKED-GISEL-LABEL: fadd_v2_v_fneg_hi: +; PACKED-GISEL: ; %bb.0: +; PACKED-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; PACKED-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c +; PACKED-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; PACKED-GISEL-NEXT: v_lshlrev_b32_e32 v4, 3, v0 +; PACKED-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; PACKED-GISEL-NEXT: global_load_dwordx2 v[0:1], v4, s[0:1] +; PACKED-GISEL-NEXT: v_mov_b32_e32 v2, s2 +; PACKED-GISEL-NEXT: v_max_f32_e64 v3, -s2, -s2 +; PACKED-GISEL-NEXT: s_waitcnt vmcnt(0) +; PACKED-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], v[2:3] +; PACKED-GISEL-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1] +; PACKED-GISEL-NEXT: s_endpgm ; ; GFX1250-SDAG-LABEL: fadd_v2_v_fneg_hi: ; GFX1250-SDAG: ; %bb.0: @@ -1205,10 +1168,8 @@ define amdgpu_kernel void @fadd_v2_v_fneg_hi(ptr addrspace(1) %a, float %x) { ; GFX1250-GISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v0 ; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX1250-GISEL-NEXT: global_load_b64 v[0:1], v4, s[0:1] scale_offset -; GFX1250-GISEL-NEXT: v_max_num_f32_e64 v2, -s2, -s2 -; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b32_e32 v2, s2 +; GFX1250-GISEL-NEXT: v_max_num_f32_e64 v3, -s2, -s2 ; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0 ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], v[2:3] @@ -1250,35 +1211,19 @@ define amdgpu_kernel void @fadd_v2_v_fneg_lo2(ptr addrspace(1) %a, float %x, flo ; PACKED-SDAG-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; PACKED-SDAG-NEXT: s_endpgm ; -; GFX90A-GISEL-LABEL: fadd_v2_v_fneg_lo2: -; GFX90A-GISEL: ; %bb.0: -; GFX90A-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 -; GFX90A-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0 -; GFX90A-GISEL-NEXT: v_lshlrev_b32_e32 v2, 3, v0 -; GFX90A-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX90A-GISEL-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1] -; GFX90A-GISEL-NEXT: v_max_f32_e64 v3, -s2, -s2 -; GFX90A-GISEL-NEXT: v_readfirstlane_b32 s2, v3 -; GFX90A-GISEL-NEXT: s_waitcnt vmcnt(0) -; GFX90A-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], s[2:3] -; GFX90A-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] -; GFX90A-GISEL-NEXT: s_endpgm -; -; GFX942-GISEL-LABEL: fadd_v2_v_fneg_lo2: -; GFX942-GISEL: ; %bb.0: -; GFX942-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 -; GFX942-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0 -; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v2, 3, v0 -; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-GISEL-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1] -; GFX942-GISEL-NEXT: v_max_f32_e64 v3, -s2, -s2 -; GFX942-GISEL-NEXT: s_nop 0 -; GFX942-GISEL-NEXT: v_readfirstlane_b32 s2, v3 -; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0) -; GFX942-GISEL-NEXT: s_nop 0 -; GFX942-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], s[2:3] -; GFX942-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] -; GFX942-GISEL-NEXT: s_endpgm +; PACKED-GISEL-LABEL: fadd_v2_v_fneg_lo2: +; PACKED-GISEL: ; %bb.0: +; PACKED-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; PACKED-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; PACKED-GISEL-NEXT: v_lshlrev_b32_e32 v4, 3, v0 +; PACKED-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; PACKED-GISEL-NEXT: global_load_dwordx2 v[0:1], v4, s[0:1] +; PACKED-GISEL-NEXT: v_max_f32_e64 v2, -s2, -s2 +; PACKED-GISEL-NEXT: v_mov_b32_e32 v3, s3 +; PACKED-GISEL-NEXT: s_waitcnt vmcnt(0) +; PACKED-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], v[2:3] +; PACKED-GISEL-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1] +; PACKED-GISEL-NEXT: s_endpgm ; ; GFX1250-SDAG-LABEL: fadd_v2_v_fneg_lo2: ; GFX1250-SDAG: ; %bb.0: @@ -1306,9 +1251,7 @@ define amdgpu_kernel void @fadd_v2_v_fneg_lo2(ptr addrspace(1) %a, float %x, flo ; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX1250-GISEL-NEXT: global_load_b64 v[0:1], v4, s[0:1] scale_offset ; GFX1250-GISEL-NEXT: v_max_num_f32_e64 v2, -s2, -s2 -; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b32_e32 v3, s3 ; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0 ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], v[2:3] @@ -1350,36 +1293,19 @@ define amdgpu_kernel void @fadd_v2_v_fneg_hi2(ptr addrspace(1) %a, float %x, flo ; PACKED-SDAG-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; PACKED-SDAG-NEXT: s_endpgm ; -; GFX90A-GISEL-LABEL: fadd_v2_v_fneg_hi2: -; GFX90A-GISEL: ; %bb.0: -; GFX90A-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 -; GFX90A-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0 -; GFX90A-GISEL-NEXT: v_lshlrev_b32_e32 v2, 3, v0 -; GFX90A-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX90A-GISEL-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1] -; GFX90A-GISEL-NEXT: v_max_f32_e64 v3, -s2, -s2 -; GFX90A-GISEL-NEXT: v_readfirstlane_b32 s5, v3 -; GFX90A-GISEL-NEXT: s_mov_b32 s4, s3 -; GFX90A-GISEL-NEXT: s_waitcnt vmcnt(0) -; GFX90A-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], s[4:5] -; GFX90A-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] -; GFX90A-GISEL-NEXT: s_endpgm -; -; GFX942-GISEL-LABEL: fadd_v2_v_fneg_hi2: -; GFX942-GISEL: ; %bb.0: -; GFX942-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 -; GFX942-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0 -; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v2, 3, v0 -; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX942-GISEL-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1] -; GFX942-GISEL-NEXT: v_max_f32_e64 v3, -s2, -s2 -; GFX942-GISEL-NEXT: s_mov_b32 s4, s3 -; GFX942-GISEL-NEXT: v_readfirstlane_b32 s5, v3 -; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0) -; GFX942-GISEL-NEXT: s_nop 0 -; GFX942-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], s[4:5] -; GFX942-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] -; GFX942-GISEL-NEXT: s_endpgm +; PACKED-GISEL-LABEL: fadd_v2_v_fneg_hi2: +; PACKED-GISEL: ; %bb.0: +; PACKED-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; PACKED-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; PACKED-GISEL-NEXT: v_lshlrev_b32_e32 v4, 3, v0 +; PACKED-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; PACKED-GISEL-NEXT: global_load_dwordx2 v[0:1], v4, s[0:1] +; PACKED-GISEL-NEXT: v_max_f32_e64 v3, -s2, -s2 +; PACKED-GISEL-NEXT: v_mov_b32_e32 v2, s3 +; PACKED-GISEL-NEXT: s_waitcnt vmcnt(0) +; PACKED-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], v[2:3] +; PACKED-GISEL-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1] +; PACKED-GISEL-NEXT: s_endpgm ; ; GFX1250-SDAG-LABEL: fadd_v2_v_fneg_hi2: ; GFX1250-SDAG: ; %bb.0: @@ -1406,11 +1332,8 @@ define amdgpu_kernel void @fadd_v2_v_fneg_hi2(ptr addrspace(1) %a, float %x, flo ; GFX1250-GISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v0 ; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX1250-GISEL-NEXT: global_load_b64 v[0:1], v4, s[0:1] scale_offset -; GFX1250-GISEL-NEXT: v_max_num_f32_e64 v2, -s2, -s2 -; GFX1250-GISEL-NEXT: s_mov_b32 s4, s3 -; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[4:5] +; GFX1250-GISEL-NEXT: v_max_num_f32_e64 v3, -s2, -s2 +; GFX1250-GISEL-NEXT: v_mov_b32_e32 v2, s3 ; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0 ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], v[2:3] diff --git a/llvm/test/CodeGen/AMDGPU/packed-fp64.ll b/llvm/test/CodeGen/AMDGPU/packed-fp64.ll index 1a85ac9397b9c..5e948144960f1 100644 --- a/llvm/test/CodeGen/AMDGPU/packed-fp64.ll +++ b/llvm/test/CodeGen/AMDGPU/packed-fp64.ll @@ -2669,7 +2669,7 @@ define void @strict_fma_v2_vv(<2 x double> %x, <2 x double> %y, <2 x double> %z, define amdgpu_kernel void @fma_v2_s_imm_imm(ptr addrspace(1) %a) { ; GFX1251-SDAG-LABEL: fma_v2_s_imm_imm: ; GFX1251-SDAG: ; %bb.0: -; GFX1251-SDAG-NEXT: global_wb +; GFX1251-SDAG-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE ; GFX1251-SDAG-NEXT: v_nop ; GFX1251-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1251-SDAG-NEXT: s_load_b64 s[2:3], s[4:5], 0x24 nv @@ -2688,7 +2688,7 @@ define amdgpu_kernel void @fma_v2_s_imm_imm(ptr addrspace(1) %a) { ; ; GFX1251-GISEL-LABEL: fma_v2_s_imm_imm: ; GFX1251-GISEL: ; %bb.0: -; GFX1251-GISEL-NEXT: global_wb +; GFX1251-GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE ; GFX1251-GISEL-NEXT: v_nop ; GFX1251-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1251-GISEL-NEXT: s_load_b64 s[8:9], s[4:5], 0x24 nv @@ -2731,7 +2731,7 @@ define amdgpu_kernel void @fma_v2_s_imm_imm(ptr addrspace(1) %a) { define amdgpu_kernel void @fma_v2_imm_imm_s(ptr addrspace(1) %a) { ; GFX1251-SDAG-LABEL: fma_v2_imm_imm_s: ; GFX1251-SDAG: ; %bb.0: -; GFX1251-SDAG-NEXT: global_wb +; GFX1251-SDAG-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE ; GFX1251-SDAG-NEXT: v_nop ; GFX1251-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1251-SDAG-NEXT: s_load_b64 s[2:3], s[4:5], 0x24 nv @@ -2749,7 +2749,7 @@ define amdgpu_kernel void @fma_v2_imm_imm_s(ptr addrspace(1) %a) { ; ; GFX1251-GISEL-LABEL: fma_v2_imm_imm_s: ; GFX1251-GISEL: ; %bb.0: -; GFX1251-GISEL-NEXT: global_wb +; GFX1251-GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE ; GFX1251-GISEL-NEXT: v_nop ; GFX1251-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1251-GISEL-NEXT: s_load_b64 s[8:9], s[4:5], 0x24 nv