diff --git a/llvm/lib/Target/RISCV/RISCVSchedSpacemitX100.td b/llvm/lib/Target/RISCV/RISCVSchedSpacemitX100.td index 141fcb617ae7a..6b75a0748a37c 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSpacemitX100.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSpacemitX100.td @@ -11,6 +11,75 @@ // Scheduler model for the SpacemiT-X100 processor. // //===----------------------------------------------------------------------===// +// Latency helper classes + +// Used for: arithmetic (min/max/vmerge/vmv) +class Get2348Latency { + int c = GetLMULValue<[/*MF8=*/2, /*MF4=*/2, /*MF2=*/2, /*M1=*/2, /*M2=*/3, /*M4=*/4, /*M8=*/8], mx>.c; +} + +//===----------------------------------------------------------------------===// + +class SMTX100IsWorstCaseMX MxList> { + string LLMUL = LargestLMUL.r; + bit c = !eq(mx, LLMUL); +} + +class SMTX100IsWorstCaseMXSEW MxList, bit isF = 0> { + string LLMUL = LargestLMUL.r; + int SSEW = SmallestSEW.r; + bit c = !and(!eq(mx, LLMUL), !eq(sew, SSEW)); +} + +defvar SMTX100VLEN = 256; +defvar SMTX100DLEN = !div(SMTX100VLEN, 2); + +class SMTX100GetLMulCycles { + int c = !cond( + !eq(mx, "M1") : 1, + !eq(mx, "M2") : 2, + !eq(mx, "M4") : 4, + !eq(mx, "M8") : 8, + !eq(mx, "MF2") : 1, + !eq(mx, "MF4") : 1, + !eq(mx, "MF8") : 1 + ); +} + +class SMTX100GetVLMAX { + defvar LMUL = SMTX100GetLMulCycles.c; + int val = !cond( + !eq(mx, "MF2") : !div(!div(SMTX100VLEN, 2), sew), + !eq(mx, "MF4") : !div(!div(SMTX100VLEN, 4), sew), + !eq(mx, "MF8") : !div(!div(SMTX100VLEN, 8), sew), + true: !div(!mul(SMTX100VLEN, LMUL), sew) + ); +} + +// Latency for segmented loads and stores are calculated as vl * nf. +class SMTX100SegmentedLdStCycles { + int c = !mul(SMTX100GetVLMAX.val, nf); +} + +class SMTX100GetVLDSLat { + defvar Base = [4, 5, 9, 22, 50, 114, 242]; + defvar Index = !cond( + !eq(mx, "MF8"): 0, + !eq(mx, "MF4"): 1, + !eq(mx, "MF2"): 2, + !eq(mx, "M1"): 3, + !eq(mx, "M2"): 4, + !eq(mx, "M4"): 5, + !eq(mx, "M8"): 6, + ); + defvar Shift = !cond( + !eq(sew, 8): 0, + !eq(sew, 16): 1, + !eq(sew, 32): 2, + !eq(sew, 64): 3, + ); + int val = !if(!lt(Index, Shift), 0, Base[!sub(Index, Shift)]); +} def SpacemitX100Model : SchedMachineModel { let IssueWidth = 4; // 4 micro-ops are dispatched per cycle. @@ -22,8 +91,7 @@ def SpacemitX100Model : SchedMachineModel { let CompleteModel = 0; let UnsupportedFeatures = [HasStdExtZknd, HasStdExtZkne, HasStdExtZknh, - HasStdExtZksed, HasStdExtZksh, HasStdExtZkr, - HasVInstructions]; + HasStdExtZksed, HasStdExtZksh, HasStdExtZkr]; } let SchedModel = SpacemitX100Model in { @@ -51,6 +119,17 @@ let BufferSize = 4 in { def SMTX100_IQ : ProcResGroup<[SMTX100_IQ0, SMTX100_IQ1]>; def SMTX100_FQ : ProcResGroup<[SMTX100_FQ0, SMTX100_FQ1]>; +// all vector computre inst in VEU0/VEU1 +def SMTX100_VEU0 : ProcResource<1>; +def SMTX100_VEU1 : ProcResource<1>; +// all vector memory inst in VEU2/VEU3 +def SMTX100_VEU2 : ProcResource<1>; +def SMTX100_VEU3 : ProcResource<1>; + +def SMTX100_VIEU : ProcResGroup<[SMTX100_VEU0, SMTX100_VEU1]>; +def SMTX100_VFPU : ProcResGroup<[SMTX100_VEU0, SMTX100_VEU1]>; +def SMTX100_VLSU : ProcResGroup<[SMTX100_VEU2, SMTX100_VEU3]>; + //===----------------------------------------------------------------------===// // Branching @@ -245,6 +324,790 @@ let Latency = 3 in { // Others def : WriteRes; def : WriteRes; +def : WriteRes; + +// 6. Configuration-Setting Instructions +def : WriteRes; +def : WriteRes; +def : WriteRes; + +// 7. Vector Loads and Stores +foreach mx = SchedMxList in { + defvar IsWorstCase = SMTX100IsWorstCaseMX.c; + + // Unit-stride loads and stores + defvar VLDELat = ConstValueUntilLMULThenDoubleBase<"M4", 4, 6, mx>.c; + defvar VLDEOcc = ConstValueUntilLMULThenDoubleBase<"M2", 2, 3, mx>.c; + let Latency = VLDELat, ReleaseAtCycles = [VLDEOcc] in + defm "" : LMULWriteResMX<"WriteVLDE", [SMTX100_VLSU], mx, IsWorstCase>; + + defvar VSTELatAndOcc = GetLMULValue<[2, 2, 2, 3, 5, 10, 18], mx>.c; + let Latency = VSTELatAndOcc, ReleaseAtCycles = [VSTELatAndOcc] in + defm "" : LMULWriteResMX<"WriteVSTE", [SMTX100_VLSU], mx, IsWorstCase>; + + defvar VLDFFLat = ConstValueUntilLMULThenDoubleBase<"M4", 4, 6, mx>.c; + defvar VLDFFOcc = ConstValueUntilLMULThenDoubleBase<"M2", 2, 3, mx>.c; + let Latency = VLDFFLat, ReleaseAtCycles = [VLDFFOcc] in + defm "" : LMULWriteResMX<"WriteVLDFF", [SMTX100_VLSU], mx, IsWorstCase>; + + // Mask loads and stores + let Latency = 4, ReleaseAtCycles = [2] in + defm "" : LMULWriteResMX<"WriteVLDM", [SMTX100_VLSU], mx, IsWorstCase>; + + let Latency = 2, ReleaseAtCycles = [2] in + defm "" : LMULWriteResMX<"WriteVSTM", [SMTX100_VEU2], mx, IsWorstCase>; + + // Strided and indexed loads and stores + // vlse + // e8 = [4, 5, 9, 22, 50, 114, 242] + // e16 = [ 4, 5, 9, 22, 50, 114] + // e32 = [ 4, 5, 9, 22, 50] + // e64 = [ 4, 5, 9, 22] + + // Latency only decides by element + // vsse + // e8 = [4, 8, 16, 32, 64, 128, 256] + // e16 = [ 4, 8, 16, 32, 64, 128] + // e32 = [ 4, 8, 16, 32, 64] + // e64 = [ 4, 8, 16, 32] + foreach eew = [8, 16, 32, 64] in { + defvar VLDSLatAndOcc = SMTX100GetVLDSLat.val; + let Latency = VLDSLatAndOcc, ReleaseAtCycles = [VLDSLatAndOcc] in + defm "" : LMULWriteResMX<"WriteVLDS" # eew, [SMTX100_VLSU], mx, IsWorstCase>; + + defvar VSTSLatAndOcc = SMTX100GetVLMAX.val; + let Latency = VSTSLatAndOcc, ReleaseAtCycles = [VSTSLatAndOcc] in + defm "" : LMULWriteResMX<"WriteVSTS" # eew, [SMTX100_VEU2], mx, IsWorstCase>; + } + + foreach eew = [8, 16, 32, 64] in { + defvar IdxLdStLatAndOcc = !div(SMTX100GetVLMAX.val, 2); + let Latency = IdxLdStLatAndOcc, ReleaseAtCycles = [IdxLdStLatAndOcc] in { + defm "" : LMULWriteResMX<"WriteVLDUX" # eew, [SMTX100_VEU2], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVLDOX" # eew, [SMTX100_VEU2], mx, IsWorstCase>; + + defm "" : LMULWriteResMX<"WriteVSTUX" # eew, [SMTX100_VEU2], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSTOX" # eew, [SMTX100_VEU2], mx, IsWorstCase>; + } + } +} + +// Segmented loads and stores +foreach mx = SchedMxList in { + foreach nf=2-8 in { + foreach eew = [8, 16, 32, 64] in { + defvar IsWorstCase = SMTX100IsWorstCaseMX.c; + + defvar EffectiveNF= !if(!le(nf, 4), 1, nf); + defvar SegLdStLatAndOcc = SMTX100SegmentedLdStCycles.c; + let Latency = SegLdStLatAndOcc, ReleaseAtCycles = [SegLdStLatAndOcc] in { + // Unit-stride segmented + defm "" : LMULWriteResMX<"WriteVLSEG" # nf # "e" #eew, [SMTX100_VLSU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVLSEGFF" # nf # "e" #eew, [SMTX100_VLSU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSSEG" # nf # "e" #eew, [SMTX100_VLSU], mx, IsWorstCase>; + + // Strided/indexed segmented + defm "" : LMULWriteResMX<"WriteVLSSEG" # nf # "e" #eew, [SMTX100_VLSU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSSSEG" # nf # "e" #eew, [SMTX100_VLSU], mx, IsWorstCase>; + } + + defvar IdxSegLdStLatAndOcc = SMTX100SegmentedLdStCycles.c; + let Latency = IdxSegLdStLatAndOcc, ReleaseAtCycles = [IdxSegLdStLatAndOcc] in { + // Indexed segmented + defm "" : LMULWriteResMX<"WriteVLOXSEG" # nf # "e" #eew, [SMTX100_VEU2], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVLUXSEG" # nf # "e" #eew, [SMTX100_VEU2], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSUXSEG" # nf # "e" #eew, [SMTX100_VEU2], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSOXSEG" # nf # "e" #eew, [SMTX100_VEU2], mx, IsWorstCase>; + } + } + } +} + +// Whole register move/load/store +foreach LMul = [1, 2, 4, 8] in { + defvar WholeLdLatandOcc = !cond( + !eq(LMul, 1) : 2, + !eq(LMul, 2) : 3, + !eq(LMul, 4) : 6, + !eq(LMul, 8) : 18); + let Latency = WholeLdLatandOcc, ReleaseAtCycles = [WholeLdLatandOcc] in + def : WriteRes("WriteVLD" # LMul # "R"), [SMTX100_VLSU]>; + + defvar WholeStLatandOcc = !cond( + !eq(LMul, 1) : 3, + !eq(LMul, 2) : 5, + !eq(LMul, 4) : 10, + !eq(LMul, 8) : 18); + let Latency = WholeStLatandOcc, ReleaseAtCycles = [WholeStLatandOcc] in + def : WriteRes("WriteVST" # LMul # "R"), [SMTX100_VEU2]>; + + // Whole Vector Register Move + defvar VMovLat = !cond( + !eq(LMul, 1) : 2, + !eq(LMul, 2) : 3, + !eq(LMul, 4) : 4, + !eq(LMul, 8) : 8); + let Latency = VMovLat, ReleaseAtCycles = [LMul] in + def : WriteRes("WriteVMov" # LMul # "V"), [SMTX100_VEU0]>; +} + +// 11. Vector Integer Arithmetic Instructions +foreach mx = SchedMxList in { + defvar IsWorstCase = SMTX100IsWorstCaseMX.c; + + defvar VIALUOcc = ConstOneUntilM1ThenDouble.c; + // Vector Integer Min/Max Instructions + let Latency = Get2348Latency.c, ReleaseAtCycles = [VIALUOcc] in { + defm "" : LMULWriteResMX<"WriteVIMinMaxV", [SMTX100_VIEU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIMinMaxX", [SMTX100_VIEU], mx, IsWorstCase>; + } + + // Latency of vadd, vsub, vrsub: 3/3/4/8 + // Latency of vand, vor, vxor: 2/3/4/8 + // ReleaseAtCycles : 1/2/4/8 + // They are grouped together, so we used the worst case 3/3/4/8 + // TODO: use InstRW to override individual instructions' scheduling data + defvar VIALULat = ConstValueUntilLMULThenDoubleBase<"M4", 3, 4, mx>.c; + let Latency = VIALULat, ReleaseAtCycles = [VIALUOcc] in { + defm "" : LMULWriteResMX<"WriteVIALUV", [SMTX100_VIEU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIALUX", [SMTX100_VIEU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIALUI", [SMTX100_VIEU], mx, IsWorstCase>; + } + + // let Latency = VIALULat in + // def SMX100WriteVCOPY_ # mx : SchedWriteRes<[]>; + + let Latency = Get2348Latency.c, ReleaseAtCycles = [VIALUOcc] in { + // Vector Integer Merge Instructions + defm "" : LMULWriteResMX<"WriteVIMergeV", [SMTX100_VIEU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIMergeX", [SMTX100_VIEU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIMergeI", [SMTX100_VIEU], mx, IsWorstCase>; + // Vector Integer Move Instructions + defm "" : LMULWriteResMX<"WriteVIMovV", [SMTX100_VIEU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIMovX", [SMTX100_VIEU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIMovI", [SMTX100_VIEU], mx, IsWorstCase>; + } + + defvar VIShiftLat = ConstValueUntilLMULThenDoubleBase<"M2", 3, 4, mx>.c; + defvar VIShiftOcc = ConstOneUntilMF2ThenDouble.c; + let Latency = VIShiftLat, ReleaseAtCycles = [VIShiftOcc] in { + // Vector Integer Extension Instructions + defm "" : LMULWriteResMX<"WriteVExtV", [SMTX100_VEU0], mx, IsWorstCase>; + // Vector Single-Width Bit Shift Instructions + defm "" : LMULWriteResMX<"WriteVShiftV", [SMTX100_VEU0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVShiftX", [SMTX100_VEU0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVShiftI", [SMTX100_VEU0], mx, IsWorstCase>; + } + + defvar VICALULat = ConstValueUntilLMULThenDoubleBase<"M4", 3, 4, mx>.c; + let Latency = VICALULat, ReleaseAtCycles = [VIALUOcc] in { + // Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions + defm "" : LMULWriteResMX<"WriteVICALUV", [SMTX100_VEU0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVICALUX", [SMTX100_VEU0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVICALUI", [SMTX100_VEU0], mx, IsWorstCase>; + } + + defvar VICmpCarryLat = GetLMULValue<[3, 3, 3, 4, 6, 10, 18], mx>.c; + // ReleaseAtCycles: e8 = 1/2/3/5/11, e16/e32/e64 = 1/2/3/5/18 + // but we use the worse case + defvar VICmpCarryOcc = GetLMULValue<[1, 1, 1, 2, 3, 5, 18], mx>.c; + let Latency = VICmpCarryLat, ReleaseAtCycles = [VICmpCarryOcc] in { + defm "" : LMULWriteResMX<"WriteVICALUMV", [SMTX100_VEU0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVICALUMX", [SMTX100_VEU0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVICALUMI", [SMTX100_VEU0], mx, IsWorstCase>; + // Vector Integer Comparison Instructions + defm "" : LMULWriteResMX<"WriteVICmpV", [SMTX100_VIEU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVICmpX", [SMTX100_VIEU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVICmpI", [SMTX100_VIEU], mx, IsWorstCase>; + } + + // Latency of vmacc, vmadd, vmul, vmulh, etc.: e8/e16 = 3/3/4/8, e32 = 4/4/5/8, + // e64 = 7/8/16/32. We use the worst-case until we can split the SEW. + // ReleaseAtCycles: e8/e16/e32 = 1,2,4,8, e64 = 4/8/16/32 + // TODO: change WriteVIMulV, etc to be defined with LMULSEWSchedWrites + defvar VIMulLat = ConstValueUntilLMULThenDoubleBase<"M4", 7, 8, mx>.c; + defvar VIMulOcc = ConstValueUntilLMULThenDouble<"M1", 4, mx>.c; + let Latency = VIMulLat, ReleaseAtCycles = [VIMulOcc] in { + // Vector Single-Width Integer Multiply Instructions + defm "" : LMULWriteResMX<"WriteVIMulV", [SMTX100_VIEU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIMulX", [SMTX100_VIEU], mx, IsWorstCase>; + // Vector Single-Width Integer Multiply-Add Instructions + defm "" : LMULWriteResMX<"WriteVIMulAddV", [SMTX100_VIEU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIMulAddX", [SMTX100_VIEU], mx, IsWorstCase>; + } +} + +// Widening +foreach mx = SchedMxListW in { + defvar IsWorstCase = SMTX100IsWorstCaseMX.c; + + // Vector Widening Integer Add/Subtract + defvar VIWIntLat = ConstValueUntilLMULThenDoubleBase<"M2", 3, 4, mx>.c; + defvar VIWideningOcc = GetLMULValue<[1, 1, 2, 2, 4, 8], mx>.c; + let Latency = VIWIntLat, ReleaseAtCycles = [VIWideningOcc] in { + defm "" : LMULWriteResMX<"WriteVIWALUV", [SMTX100_VIEU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIWALUX", [SMTX100_VIEU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIWALUI", [SMTX100_VIEU], mx, IsWorstCase>; + } + + // Pattern of vwmul/vwmacc, etc: e8/e16 = 3/3/4/8, e32 = 4/4/5/8 + defvar VIWMulLat = ConstValueUntilLMULThenDoubleBase<"M2", 4, 5, mx>.c; + let Latency = VIWMulLat, ReleaseAtCycles = [VIWideningOcc] in { + // Vector Widening Integer Multiply Instructions + defm "" : LMULWriteResMX<"WriteVIWMulV", [SMTX100_VIEU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIWMulX", [SMTX100_VIEU], mx, IsWorstCase>; + // Vector Widening Integer Multiply-Add Instructions + defm "" : LMULWriteResMX<"WriteVIWMulAddV", [SMTX100_VIEU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIWMulAddX", [SMTX100_VIEU], mx, IsWorstCase>; + } +} + +// Division and remainder operations +// Pattern of vdivu: 17/17/17/25/52/102/205 +// Pattern of vdiv: 17/17/17/22/44/88/176 +// Pattern of vremu: 15/15/15/20/40/80/160 +// Pattern of vrem: 15/15/15/22/45/89/176 +// We use for all: 17/17/17/25/52/104/208 +foreach mx = SchedMxList in { + foreach sew = SchedSEWSet.val in { + defvar IsWorstCase = SMTX100IsWorstCaseMXSEW.c; + + // Not pipelined + defvar VIDivLatAndOcc = ConstValueUntilLMULThenDoubleBase<"M1", 17, 25, mx>.c; + let Latency = VIDivLatAndOcc, ReleaseAtCycles = [VIDivLatAndOcc] in { + defm "" : LMULSEWWriteResMXSEW<"WriteVIDivV", [SMTX100_VEU0], mx, sew, IsWorstCase>; + defm "" : LMULSEWWriteResMXSEW<"WriteVIDivX", [SMTX100_VEU0], mx, sew, IsWorstCase>; + } + } +} + +// Narrowing Shift and Clips +foreach mx = SchedMxListW in { + defvar IsWorstCase = SMTX100IsWorstCaseMX.c; + + defvar VNarrowingLat = ConstValueUntilLMULThenDoubleBase<"M1", 3, 4, mx>.c; + defvar VNarrowingOcc = ConstOneUntilMF4ThenDouble.c; + let Latency = VNarrowingLat, ReleaseAtCycles = [VNarrowingOcc] in { + defm "" : LMULWriteResMX<"WriteVNShiftV", [SMTX100_VEU0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVNShiftX", [SMTX100_VEU0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVNShiftI", [SMTX100_VEU0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVNClipV", [SMTX100_VEU0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVNClipX", [SMTX100_VEU0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVNClipI", [SMTX100_VEU0], mx, IsWorstCase>; + } +} + +// 12. Vector Fixed-Point Arithmetic Instructions +foreach mx = SchedMxList in { + defvar IsWorstCase = SMTX100IsWorstCaseMX.c; + + defvar VFALULat = ConstValueUntilLMULThenDoubleBase<"M4", 3, 4, mx>.c; + let Latency = VFALULat, ReleaseAtCycles = [ConstOneUntilM1ThenDouble.c] in { + defm "" : LMULWriteResMX<"WriteVSALUV", [SMTX100_VIEU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSALUX", [SMTX100_VIEU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSALUI", [SMTX100_VIEU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVAALUV", [SMTX100_VIEU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVAALUX", [SMTX100_VIEU], mx, IsWorstCase>; + } + + // Latency of vsmul: e8/e16 = 3/3/4/8, e32 = 4/4/5/8, e64 = 7/8/16/32 + // We use the worst-case until we can split the SEW. + defvar VSMulLat = ConstValueUntilLMULThenDoubleBase<"M2", 7, 8, mx>.c; + // ReleaseAtCycles of vsmul: e8/e16/e32 = 1/2/4/8, e64 = 4/8/16/32 + // We use the worst-case until we can split the SEW. + defvar VSMulOcc = ConstValueUntilLMULThenDoubleBase<"M1", 1, 4, mx>.c; + // TODO: change WriteVSMulV/X to be defined with LMULSEWSchedWrites + let Latency = VSMulLat, ReleaseAtCycles = [VSMulOcc] in { + defm "" : LMULWriteResMX<"WriteVSMulV", [SMTX100_VIEU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSMulX", [SMTX100_VIEU], mx, IsWorstCase>; + } + + defvar VSShiftLat = ConstValueUntilLMULThenDoubleBase<"M2", 3, 4, mx>.c; + defvar VSShiftOcc = ConstOneUntilMF2ThenDouble.c; + let Latency = VSShiftLat, ReleaseAtCycles = [VSShiftOcc] in { + defm "" : LMULWriteResMX<"WriteVSShiftV", [SMTX100_VEU0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSShiftX", [SMTX100_VEU0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSShiftI", [SMTX100_VEU0], mx, IsWorstCase>; + } +} + +// 13. Vector Floating-Point Instructions +foreach mx = SchedMxListF in { + foreach sew = SchedSEWSet.val in { + defvar IsWorstCase = SMTX100IsWorstCaseMXSEW.c; + + defvar VFALUOcc = ConstOneUntilM1ThenDouble.c; + let Latency = Get4458Latency.c, ReleaseAtCycles = [VFALUOcc] in { + defm "" : LMULSEWWriteResMXSEW<"WriteVFALUV", [SMTX100_VFPU], mx, sew, IsWorstCase>; + defm "" : LMULSEWWriteResMXSEW<"WriteVFALUF", [SMTX100_VFPU], mx, sew, IsWorstCase>; + } + + defvar VFMaxMinLat = ConstValueUntilLMULThenDoubleBase<"M4", 3, 4, mx>.c; + let Latency = VFMaxMinLat, ReleaseAtCycles = [VFALUOcc] in { + defm "" : LMULSEWWriteResMXSEW<"WriteVFMinMaxV", [SMTX100_VFPU], mx, sew, IsWorstCase>; + defm "" : LMULSEWWriteResMXSEW<"WriteVFMinMaxF", [SMTX100_VFPU], mx, sew, IsWorstCase>; + } + + // Latency: e32 = 4/4/5/8, e64 = 5/5/5/8 + // Slightly increased latency for sew == 64 + defvar VFMulLat = !if(!eq(sew, 64), ConstValueUntilLMULThenDoubleBase<"M8", 5, 8, mx>.c, + Get4458Latency.c); + let Latency = VFMulLat, ReleaseAtCycles = [ConstOneUntilM1ThenDouble.c] in { + defm "" : LMULSEWWriteResMXSEW<"WriteVFMulV", [SMTX100_VFPU], mx, sew, IsWorstCase>; + defm "" : LMULSEWWriteResMXSEW<"WriteVFMulF", [SMTX100_VFPU], mx, sew, IsWorstCase>; + } + + defvar VFSgnjLat = ConstValueUntilLMULThenDoubleBase<"M2", 3, 4, mx>.c; + defvar VFSgnjOcc = ConstOneUntilMF2ThenDouble.c; + let Latency = VFSgnjLat, ReleaseAtCycles = [VFSgnjOcc] in { + defm "" : LMULSEWWriteResMXSEW<"WriteVFRecpV", [SMTX100_VEU0], mx, sew, IsWorstCase>; + defm "" : LMULSEWWriteResMXSEW<"WriteVFSgnjV", [SMTX100_VEU0], mx, sew, IsWorstCase>; + defm "" : LMULSEWWriteResMXSEW<"WriteVFSgnjF", [SMTX100_VEU0], mx, sew, IsWorstCase>; + defm "" : LMULSEWWriteResMXSEW<"WriteVFCvtIToFV", [SMTX100_VEU0], mx, sew, IsWorstCase>; + } + + // The following covers vfmacc, vfmsac, vfmadd and their vfn* variants in the same group, but the + // ReleaseAtCycles takes one extra cycle for the vfn* variants on lmul == 4 + // vfmacc/vfmacc/vfmadd/vfmsub: 1/2/4/8 and vfn* variants: 1/2/5/8 + // Latency: e32 = 4/4/5/8, e64 = 5/5/5/8 + defvar VFFulAddLat = !if(!eq(sew, 64), ConstValueUntilLMULThenDoubleBase<"M8", 5, 8, mx>.c, + Get4458Latency.c); + let Latency = VFFulAddLat, ReleaseAtCycles = [ConstOneUntilM1ThenDouble.c] in { + defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddV", [SMTX100_VFPU], mx, sew, IsWorstCase>; + defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddF", [SMTX100_VFPU], mx, sew, IsWorstCase>; + } + } +} + +foreach mx = SchedMxList in { + defvar IsWorstCase = SMTX100IsWorstCaseMX.c; + + defvar VFCmpLat = GetLMULValue<[3, 3, 3, 4, 6, 10, 18], mx>.c; + defvar VFCmpOcc = GetLMULValue<[1, 1, 1, 2, 3, 5, 18], mx>.c; + let Latency = VFCmpLat, ReleaseAtCycles = [VFCmpOcc] in { + defm "" : LMULWriteResMX<"WriteVFCmpV", [SMTX100_VFPU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVFCmpF", [SMTX100_VFPU], mx, IsWorstCase>; + } + + defvar VFClassLat = ConstValueUntilLMULThenDoubleBase<"M2", 3, 4, mx>.c; + defvar VFClassOcc = ConstOneUntilMF2ThenDouble.c; + let Latency = VFClassLat, ReleaseAtCycles = [VFClassOcc] in { + defm "" : LMULWriteResMX<"WriteVFClassV", [SMTX100_VEU0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVFMergeV", [SMTX100_VEU0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVFMovV", [SMTX100_VEU0], mx, IsWorstCase>; + // TODO TEST LMUL = MF8 + defm "" : LMULWriteResMX<"WriteVFCvtFToIV", [SMTX100_VEU0], mx, IsWorstCase>; + } +} + +// Widening +foreach mx = SchedMxListW in { + foreach sew = SchedSEWSet.val in { + defvar IsWorstCase = SMTX100IsWorstCaseMXSEW.c; + defvar VFWCvtILat = ConstValueUntilLMULThenDoubleBase<"M2", 3, 4, mx>.c; + defvar VFWCvtIOcc = ConstOneUntilMF4ThenDouble.c; + let Latency = VFWCvtILat, ReleaseAtCycles = [VFWCvtIOcc] in + defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtIToFV", [SMTX100_VEU0], mx, sew, IsWorstCase>; + } +} + +foreach mx = SchedMxListFW in { + defvar IsWorstCase = SMTX100IsWorstCaseMX.c; + + defvar VFWCvtFToIVLat = ConstValueUntilLMULThenDoubleBase<"M1", 3, 4, mx>.c; + defvar VFWCvtFToIVOcc = ConstOneUntilMF4ThenDouble.c; + let Latency = VFWCvtFToIVLat, ReleaseAtCycles = [VFWCvtFToIVOcc] in + defm "" : LMULWriteResMX<"WriteVFWCvtFToIV", [SMTX100_VEU0], mx, IsWorstCase>; +} + +foreach mx = SchedMxListFW in { + foreach sew = SchedSEWSet.val in { + defvar IsWorstCase = SMTX100IsWorstCaseMXSEW.c; + + defvar VFWCvtFToFVLat = ConstValueUntilLMULThenDoubleBase<"M1", 3, 4, mx>.c; + defvar VFWCvtFToFVOcc = ConstOneUntilMF4ThenDouble.c; + let Latency = VFWCvtFToFVLat, ReleaseAtCycles = [VFWCvtFToFVOcc] in + defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtFToFV", [SMTX100_VEU0], mx, sew, IsWorstCase>; + + // Latency for vfwsub/vfwadd.vv, vfwsub/vfwadd.vf: + // e16 = 3/3/3/4/8, e32 = 4/4/5/8 + // ReleaseAtCycles for vfwsub/vfwadd.vv, vfwsub/vfwadd.vf: 1/2/2/4/8 + // Latency for vfwsub/vfwadd.wv, vfwsub/vfwadd.wf: + // e16 = 4/4/6/8/16, e32 = 5/6/8/16 + // ReleaseAtCycles for vfwsub/vfwadd.wv, vfwsub/vfwadd.wf: 2/2/4/8/16 + // We use the worst-case + // TODO: Split .vv/.wv variants into separate scheduling classes + defvar VFWALULat = !if(!eq(sew, 16), + GetLMULValue<[4, 4, 4, 6, 8, 16], mx>.c, + GetLMULValue<[5, 5, 5, 6, 8, 16], mx>.c + ); + defvar VFWALUOcc = GetLMULValue<[2, 2, 2, 4, 8, 16], mx>.c; + let Latency = VFWALULat, ReleaseAtCycles = [VFWALUOcc] in { + defm "" : LMULSEWWriteResMXSEW<"WriteVFWALUV", [SMTX100_VFPU], mx, sew, IsWorstCase>; + defm "" : LMULSEWWriteResMXSEW<"WriteVFWALUF", [SMTX100_VFPU], mx, sew, IsWorstCase>; + } + + // Latency for vfwmul, vfwmacc, vfwnmacc, etc: e16 = 4/4/4/5/8; e32 = 5/5/5/8 + defvar VFWMulLat = !if(!eq(sew, 16), + GetLMULValue<[4, 4, 4, 4, 5, 8], mx>.c, + GetLMULValue<[5, 5, 5, 5, 5, 8], mx>.c + ); + defvar VFWMulOcc = GetLMULValue<[1, 1, 2, 2, 4, 8], mx>.c; + let Latency = VFWMulLat, ReleaseAtCycles = [VFWMulOcc] in { + defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulF", [SMTX100_VFPU], mx, sew, IsWorstCase>; + defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulV", [SMTX100_VFPU], mx, sew, IsWorstCase>; + defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulAddV", [SMTX100_VFPU], mx, sew, IsWorstCase>; + defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulAddF", [SMTX100_VFPU], mx, sew, IsWorstCase>; + } + } +} + +// Narrowing +foreach mx = SchedMxListW in { + defvar IsWorstCase = SMTX100IsWorstCaseMX.c; + + defvar VFNCvtFToIVLat = GetLMULValue<[3, 3, 4, 4, 8, 16], mx>.c; + defvar VFNCvtFToIVOcc = ConstOneUntilMF4ThenDouble.c; + let Latency = VFNCvtFToIVLat, ReleaseAtCycles = [VFNCvtFToIVOcc] in + defm "" : LMULWriteResMX<"WriteVFNCvtFToIV", [SMTX100_VEU0], mx, IsWorstCase>; +} + +foreach mx = SchedMxListFW in { + foreach sew = SchedSEWSet.val in { + defvar IsWorstCase = SMTX100IsWorstCaseMXSEW.c; + + defvar VFNCvtToFVLat = GetLMULValue<[3, 3, 4, 4, 8, 16], mx>.c; + defvar VFNCvtToFVOcc = ConstOneUntilMF4ThenDouble.c; + let Latency = VFNCvtToFVLat, ReleaseAtCycles = [VFNCvtToFVOcc] in { + defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtIToFV", [SMTX100_VEU0], mx, sew, IsWorstCase>; + defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtFToFV", [SMTX100_VEU0], mx, sew, IsWorstCase>; + } + } +} + +// Vector Floating-Point Division and Square Root +foreach mx = SchedMxListF in { + foreach sew = SchedSEWSet.val in { + defvar IsWorstCase = SMTX100IsWorstCaseMXSEW.c; + + // Compute ReleaseAtCycles based on SEW + // vfdiv.vf and vfrdiv.vf a slight latency difference + // e16 = 14/28/57/116 , e32 = 24/48/82/193, e64 = 12/24/48/96 + defvar VFDivFLatAndOcc = !cond( + !eq(sew, 16): 14, + !eq(sew, 32): 24, + !eq(sew, 64): 12, + ); + let Latency = VFDivFLatAndOcc, ReleaseAtCycles = [VFDivFLatAndOcc] in + defm "" : LMULSEWWriteResMXSEW<"WriteVFDivF", [SMTX100_VEU0], mx, sew, IsWorstCase>; + + // e16 = 28/56/112/224, e32 = 36/72/145/290, e64 = 66/132/263/527 + defvar VFDivVFactor = !cond( + !eq(sew, 16): 28, + !eq(sew, 32): 36, + !eq(sew, 64): 66, + ); + defvar VFDivVLatAndOcc = !mul(ConstOneUntilM1ThenDouble.c, VFDivVFactor); + let Latency = VFDivVLatAndOcc, ReleaseAtCycles = [VFDivVLatAndOcc] in + defm "" : LMULSEWWriteResMXSEW<"WriteVFDivV", [SMTX100_VEU0], mx, sew, IsWorstCase>; + } +} + +// Pattern for vfsqrt.v: e16 = 26/52/104/208; e32 = 35/72/140/276; e64 = 52/99/216/412 +foreach mx = SchedMxListF in { + foreach sew = SchedSEWSet.val in { + defvar IsWorstCase = SMTX100IsWorstCaseMXSEW.c; + + defvar VFSqrtVFactor = !cond( + !eq(sew, 16): 26, + !eq(sew, 32): 35, + !eq(sew, 64): 52, + ); + defvar VFSqrtVLatAndOcc = !mul(ConstOneUntilM1ThenDouble.c, VFSqrtVFactor); + let Latency = VFSqrtVLatAndOcc, ReleaseAtCycles = [VFSqrtVLatAndOcc] in + defm "" : LMULSEWWriteResMXSEW<"WriteVFSqrtV", [SMTX100_VEU0], mx, sew, IsWorstCase>; + } +} + +// 14. Vector Reduction Operations +foreach mx = SchedMxList in { + foreach sew = SchedSEWSet.val in { + defvar IsWorstCase = SMTX100IsWorstCaseMXSEW.c; + + defvar VIRedLat = GetLMULValue<[4, 4, 4, 5, 7, 11, 19], mx>.c; + defvar VIRedOcc = GetLMULValue<[1, 1, 1, 1, 2, 6, 19], mx>.c; + let Latency = VIRedLat, ReleaseAtCycles = [VIRedOcc] in { + defm "" : LMULSEWWriteResMXSEW<"WriteVIRedMinMaxV_From", [SMTX100_VIEU], mx, sew, IsWorstCase>; + + // Latency: + // Pattern for vredsum: 4/4/4/5/7/11/19 + // Pattern for vredand, vredor, vredxor: 3/3/3/4/6/10/18 + // ReleaseAtCycles: + // Pattern for vredsum: 1/1/1/1/2/6/19 + // Pattern for vredand, vredor, vredxor: 1/1/1/1/2/5/18 + // They are grouped together, so we use the worst-case vredsum latency. + // TODO: split vredand, vredor, vredxor into separate scheduling classe. + defm "" : LMULSEWWriteResMXSEW<"WriteVIRedV_From", [SMTX100_VIEU], mx, sew, IsWorstCase>; + } + } +} + +foreach mx = SchedMxListWRed in { + foreach sew = SchedSEWSet.val in { + defvar IsWorstCase = SMTX100IsWorstCaseMXSEW.c; + + defvar VIRedLat = GetLMULValue<[4, 4, 4, 5, 7, 11, 19], mx>.c; + defvar VIRedOcc = GetLMULValue<[1, 1, 1, 1, 2, 6, 19], mx>.c; + let Latency = VIRedLat, ReleaseAtCycles = [VIRedOcc] in + defm "" : LMULSEWWriteResMXSEW<"WriteVIWRedV_From", [SMTX100_VIEU], mx, sew, IsWorstCase>; + } +} + +foreach mx = SchedMxListF in { + foreach sew = SchedSEWSet.val in { + defvar IsWorstCase = SMTX100IsWorstCaseMXSEW.c; + + // Latency is slightly lower for e16/e32, We use the worst-case + defvar VFRedLat = GetLMULValue<[12, 12, 12, 15, 21, 33, 57], mx>.c; + defvar VFRedOcc = GetLMULValue<[8, 8, 8, 8, 14, 20, 57], mx>.c; + let Latency = VFRedLat, ReleaseAtCycles = [VFRedOcc] in { + defm "" : LMULSEWWriteResMXSEW<"WriteVFRedV_From", [SMTX100_VFPU], mx, sew, IsWorstCase>; + defm "" : LMULSEWWriteResMXSEW<"WriteVFRedMinMaxV_From", [SMTX100_VFPU], mx, sew, IsWorstCase>; + } + } +} + +foreach mx = SchedMxListF in { + foreach sew = SchedSEWSet.val in { + defvar IsWorstCase = SMTX100IsWorstCaseMXSEW.c; + + // Compute latency based on SEW + defvar VFRedOV_FromLat = !cond( + !eq(sew, 16) : ConstValueUntilLMULThenDouble<"MF4", 12, mx>.c, + !eq(sew, 32) : ConstValueUntilLMULThenDouble<"MF2", 12, mx>.c, + !eq(sew, 64) : ConstValueUntilLMULThenDouble<"M1", 12, mx>.c + ); + defvar VFRedOV_FromOcc = !cond( + !eq(sew, 16) : GetLMULValue<[8, 8, 20, 23, 47, 96, 384], mx>.c, + !eq(sew, 32) : GetLMULValue<[8, 8, 8, 11, 23, 48, 192], mx>.c, + !eq(sew, 64) : GetLMULValue<[6, 6, 6, 6, 12, 25, 97], mx>.c + ); + let Latency = VFRedOV_FromLat, ReleaseAtCycles = [VFRedOV_FromOcc] in + defm "" : LMULSEWWriteResMXSEW<"WriteVFRedOV_From", [SMTX100_VFPU], mx, sew, IsWorstCase>; + } +} + +foreach mx = SchedMxListFWRed in { + foreach sew = SchedSEWSet.val in { + defvar IsWorstCase = SMTX100IsWorstCaseMXSEW.c; + + defvar VFRedOVLat = !cond( + !eq(sew, 16) : ConstValueUntilLMULThenDouble<"MF4", 16, mx>.c, + !eq(sew, 32) : ConstValueUntilLMULThenDouble<"MF2", 16, mx>.c, + ); + defvar VFRedOVOcc = !cond( + !eq(sew, 16) : GetLMULValue<[10, 10, 26, 31, 64, 128, 512], mx>.c, + !eq(sew, 32) : GetLMULValue<[10, 10, 10, 15, 31, 66, 256], mx>.c, + ); + let Latency = VFRedOVLat, ReleaseAtCycles = [VFRedOVOcc] in { + defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedV_From", [SMTX100_VFPU], mx, sew, IsWorstCase>; + defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedOV_From", [SMTX100_VFPU], mx, sew, IsWorstCase>; + } + } +} + +// 15. Vector Mask Instructions +foreach mx = SchedMxList in { + defvar IsWorstCase = SMTX100IsWorstCaseMX.c; + + let Latency = 2, ReleaseAtCycles = [1] in + defm "" : LMULWriteResMX<"WriteVMALUV", [SMTX100_VEU0], mx, IsWorstCase>; + + let Latency = 3, ReleaseAtCycles = [GetLMULValue<[1, 1, 1, 1, 1, 2, 3], mx>.c] in + defm "" : LMULWriteResMX<"WriteVMSFSV", [SMTX100_VEU0], mx, IsWorstCase>; + + let Latency = 6, ReleaseAtCycles = [6] in { + defm "" : LMULWriteResMX<"WriteVMPopV", [SMTX100_VEU0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVMFFSV", [SMTX100_VEU0], mx, IsWorstCase>; + } + + defvar VIotaLat = ConstValueUntilLMULThenDoubleBase<"M2", 3, 4, mx>.c; + defvar VIotaOcc = ConstOneUntilMF2ThenDouble.c; + let Latency = VIotaLat, ReleaseAtCycles = [VIotaOcc] in { + defm "" : LMULWriteResMX<"WriteVIotaV", [SMTX100_VEU0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIdxV", [SMTX100_VEU0], mx, IsWorstCase>; + } +} + +// 16. Vector Permutation Instructions +// Slide +foreach mx = SchedMxList in { + defvar IsWorstCase = SMTX100IsWorstCaseMX.c; + + defvar VSlideUpLat = ConstValueUntilLMULThenDoubleBase<"M2", 3, 4, mx>.c; + defvar VSlideUpOcc = ConstOneUntilMF2ThenDouble.c; + let Latency = VSlideUpLat, ReleaseAtCycles =[VSlideUpOcc] in { + defm "" : LMULWriteResMX<"WriteVSlideUpX", [SMTX100_VEU0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSlideUpI", [SMTX100_VEU0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVISlide1Up", [SMTX100_VEU0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVFSlide1Up", [SMTX100_VEU0], mx, IsWorstCase>; + } + + defvar VSlideDownLat = GetLMULValue<[3, 3, 3, 4, 5, 9, 17], mx>.c; + defvar VSlideDownOcc = GetLMULValue<[1, 1, 1, 3, 5, 9, 17], mx>.c; + let Latency = VSlideDownLat, ReleaseAtCycles =[VSlideDownOcc] in { + defm "" : LMULWriteResMX<"WriteVSlideDownX", [SMTX100_VEU0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSlideDownI", [SMTX100_VEU0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVISlide1Down", [SMTX100_VEU0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVFSlide1Down", [SMTX100_VEU0], mx, IsWorstCase>; + } +} + +// ReleaseAtCycles is 2/2/2/2/2/3/6, but we can't set based on MX for now +// TODO: Split this into separate WriteRes for each MX +let Latency = 6, ReleaseAtCycles = [6] in { + def : WriteRes; + def : WriteRes; +} + +// ReleaseAtCycles is 1/1/1/1/1/2/3, but we can't set based on MX for now +// TODO: Split this into separate WriteRes for each MX +let Latency = 3, ReleaseAtCycles = [3] in { + def : WriteRes; + def : WriteRes; +} + +// Integer LMUL Gather and Compress +foreach mx = SchedMxList in { + defvar IsWorstCase = SMTX100IsWorstCaseMX.c; + + defvar VRGatherLat = ConstValueUntilLMULThenDoubleBase<"M2", 3, 4, mx>.c; + let Latency = VRGatherLat, ReleaseAtCycles = [ConstOneUntilMF2ThenDouble.c] in { + defm "" : LMULWriteResMX<"WriteVRGatherVX", [SMTX100_VEU0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVRGatherVI", [SMTX100_VEU0], mx, IsWorstCase>; + } + + foreach sew = SchedSEWSet.val in { + defvar IsWorstCaseSEW = SMTX100IsWorstCaseMXSEW.c; + + defvar VRGatherVVLat = GetLMULValue<[3, 3, 3, 3, 8, 32, 128], mx>.c; + defvar VRGatherVVOcc = GetLMULValue<[1, 1, 1, 2, 8, 32, 128], mx>.c; + let Latency = VRGatherVVLat, ReleaseAtCycles = [VRGatherVVOcc] in + defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherVV", [SMTX100_VEU0], mx, sew, IsWorstCaseSEW>; + + defvar VRGatherEI16Lat = !if(!eq(sew, 8), + GetLMULValue<[3, 3, 4, 4, 16, 64, 128], mx>.c, + GetLMULValue<[3, 3, 3, 3, 8, 32, 128], mx>.c); + defvar VRGatherEI16Occ = !if(!eq(sew, 8), + GetLMULValue<[1, 1, 2, 4, 16, 64, 128], mx>.c, + GetLMULValue<[1, 1, 1, 2, 8, 32, 128], mx>.c); + let Latency = VRGatherEI16Lat, ReleaseAtCycles = [VRGatherEI16Occ] in + defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherEI16VV", [SMTX100_VEU0], mx, sew, IsWorstCaseSEW>; + + defvar VCompressVLat = GetLMULValue<[3, 3, 3, 4, 10, 36, 136], mx>.c; + defvar VCompressVOcc = GetLMULValue<[1, 1, 1, 3, 10, 36, 136], mx>.c; + let Latency = VCompressVLat, ReleaseAtCycles = [VCompressVOcc] in + defm "" : LMULSEWWriteResMXSEW<"WriteVCompressV", [SMTX100_VEU0], mx, sew, IsWorstCaseSEW>; + } +} + +// Vector Crypto +foreach mx = SchedMxList in { + defvar IsWorstCase = SMTX100IsWorstCaseMX.c; + defvar LMulOcc = !mul(SMTX100GetLMulCycles.c, 2); + + defvar Lat = ConstValueUntilLMULThenDoubleBase<"M2", 3, 4, mx>.c; + defvar Occ = ConstValueUntilLMULThenDouble<"MF2", 1, mx>.c; + let Latency = Lat, ReleaseAtCycles = [Occ] in { + // Zvbb + defm "" : LMULWriteResMX<"WriteVBREVV", [SMTX100_VEU0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVCLZV", [SMTX100_VEU0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVCTZV", [SMTX100_VEU0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVCPOPV", [SMTX100_VEU0], mx, IsWorstCase>; + // Zvkb + // VANDN uses WriteVIALU[V|X|I] + defm "" : LMULWriteResMX<"WriteVBREV8V", [SMTX100_VEU0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVREV8V", [SMTX100_VEU0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVRotV", [SMTX100_VEU0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVRotX", [SMTX100_VEU0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVRotI", [SMTX100_VEU0], mx, IsWorstCase>; + } + + defvar VCLAndVGLat = ConstValueUntilLMULThenDoubleBase<"M2", 3, 4, mx>.c; + let Latency = VCLAndVGLat, ReleaseAtCycles = [LMulOcc] in { + // Zvbc + defm "" : LMULWriteResMX<"WriteVCLMULV", [SMTX100_VEU0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVCLMULX", [SMTX100_VEU0], mx, IsWorstCase>; + + // Zvkg + defm "" : LMULWriteResMX<"WriteVGHSHV", [SMTX100_VEU0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVGMULV", [SMTX100_VEU0], mx, IsWorstCase>; + } + + // ZvknhaOrZvknhb + // vsha2ch.vv / vsha2cl.vv are modeled LMUL-only using the SEW=32 curve: + // M2=4, M4=8, M8=16 + // e32: M2=4, M4=8, M8=16 + // e64: M4=4, M8=8 + // TODO: Shold set vsha2ch.vv / vsha2cl.vv SEW-aware? + defvar VSHALatandOcc = ConstValueUntilLMULThenDouble<"M2", 4, mx>.c; + let Latency = VSHALatandOcc, ReleaseAtCycles = [VSHALatandOcc] in { + defm "" : LMULWriteResMX<"WriteVSHA2CHV", [SMTX100_VIEU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSHA2CLV", [SMTX100_VIEU], mx, IsWorstCase>; + } + + // vsha2ms.vv latency depends on SEW: doubling SEW shifts the doubling + // threshold right by one LMUL step. + // e32: M2=4, M4=8, M8=16 + // e64: M4=4, M8=8 + defvar ZvknhSEWs = !listremove(SchedSEWSet.val, [8, 16]); + // Smallest SEW (=32) carries the highest latency, so the WorstCase fallback + // is designated to the smallest SEW at the largest LMUL. + defvar SmallestZvknhSEW = !head(ZvknhSEWs); + foreach sew = ZvknhSEWs in { + defvar IsWorstCaseVSHA2MSV = !and(IsWorstCase, !eq(sew, SmallestZvknhSEW)); + defvar VSHA2MSLatandOcc = + ConstValueUntilLMULThenDouble.c; + let Latency = VSHA2MSLatandOcc, ReleaseAtCycles = [VSHA2MSLatandOcc] in + defm "" : LMULSEWWriteResMXSEW<"WriteVSHA2MSV", [SMTX100_VIEU], mx, sew, + IsWorstCaseVSHA2MSV>; + } + + // Zvkned + defvar VASELatandOcc = ConstValueUntilLMULThenDouble<"M1", 2, mx>.c; + let Latency = VASELatandOcc, ReleaseAtCycles = [VASELatandOcc] in { + defm "" : LMULWriteResMX<"WriteVAESMVV", [SMTX100_VEU0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVAESKF1V", [SMTX100_VEU0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVAESKF2V", [SMTX100_VEU0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVAESZV", [SMTX100_VEU0], mx, IsWorstCase>; + } + + defvar VSM3CLat = ConstValueUntilLMULThenDouble<"M4", 4, mx>.c; + let Latency = VSM3CLat, ReleaseAtCycles = [SMTX100GetLMulCycles.c] in + defm "" : LMULWriteResMX<"WriteVSM3CV", [SMTX100_VIEU], mx, IsWorstCase>; + + defvar VSM3MLat = ConstValueUntilLMULThenDoubleBase<"M4", 3, 4, mx>.c; + let Latency = VSM3MLat, ReleaseAtCycles = [SMTX100GetLMulCycles.c] in + defm "" : LMULWriteResMX<"WriteVSM3MEV", [SMTX100_VIEU], mx, IsWorstCase>; + + defvar VSM4Lat = ConstValueUntilLMULThenDouble<"M2", 4, mx>.c; + let Latency = 3, ReleaseAtCycles = [LMulOcc] in { + defm "" : LMULWriteResMX<"WriteVSM4KV", [SMTX100_VIEU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVSM4RV", [SMTX100_VIEU], mx, IsWorstCase>; + } +} + +foreach mx = SchedMxListW in { + defvar IsWorstCase = SMTX100IsWorstCaseMX.c; + + defvar VWSLat = ConstValueUntilLMULThenDoubleBase<"M1", 3, 4, mx>.c; + defvar VWSOcc = ConstValueUntilLMULThenDouble<"MF4", 1, mx>.c; + let Latency = VWSLat, ReleaseAtCycles = [VWSOcc] in { + defm "" : LMULWriteResMX<"WriteVWSLLV", [SMTX100_VEU0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVWSLLX", [SMTX100_VEU0], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVWSLLI", [SMTX100_VEU0], mx, IsWorstCase>; + } +} //===----------------------------------------------------------------------===// // Bypass and advance @@ -355,16 +1218,224 @@ def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; +// 6. Configuration-Setting Instructions +def : ReadAdvance; +def : ReadAdvance; + +// 7. Vector Loads and Stores +def : ReadAdvance; +def : ReadAdvance; +defm "" : LMULReadAdvance<"ReadVSTEV", 0>; +defm "" : LMULReadAdvance<"ReadVSTM", 0>; +def : ReadAdvance; +def : ReadAdvance; +defm "" : LMULReadAdvance<"ReadVSTS8V", 0>; +defm "" : LMULReadAdvance<"ReadVSTS16V", 0>; +defm "" : LMULReadAdvance<"ReadVSTS32V", 0>; +defm "" : LMULReadAdvance<"ReadVSTS64V", 0>; +defm "" : LMULReadAdvance<"ReadVLDUXV", 0>; +defm "" : LMULReadAdvance<"ReadVLDOXV", 0>; +defm "" : LMULReadAdvance<"ReadVSTUX8", 0>; +defm "" : LMULReadAdvance<"ReadVSTUX16", 0>; +defm "" : LMULReadAdvance<"ReadVSTUX32", 0>; +defm "" : LMULReadAdvance<"ReadVSTUX64", 0>; +defm "" : LMULReadAdvance<"ReadVSTUXV", 0>; +defm "" : LMULReadAdvance<"ReadVSTUX8V", 0>; +defm "" : LMULReadAdvance<"ReadVSTUX16V", 0>; +defm "" : LMULReadAdvance<"ReadVSTUX32V", 0>; +defm "" : LMULReadAdvance<"ReadVSTUX64V", 0>; +defm "" : LMULReadAdvance<"ReadVSTOX8", 0>; +defm "" : LMULReadAdvance<"ReadVSTOX16", 0>; +defm "" : LMULReadAdvance<"ReadVSTOX32", 0>; +defm "" : LMULReadAdvance<"ReadVSTOX64", 0>; +defm "" : LMULReadAdvance<"ReadVSTOXV", 0>; +defm "" : LMULReadAdvance<"ReadVSTOX8V", 0>; +defm "" : LMULReadAdvance<"ReadVSTOX16V", 0>; +defm "" : LMULReadAdvance<"ReadVSTOX32V", 0>; +defm "" : LMULReadAdvance<"ReadVSTOX64V", 0>; +// LMUL Aware +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; + +// 11. Vector Integer Arithmetic Instructions +defm : LMULReadAdvance<"ReadVIALUV", 0>; +defm : LMULReadAdvance<"ReadVIALUX", 0>; +defm : LMULReadAdvanceW<"ReadVIWALUV", 0>; +defm : LMULReadAdvanceW<"ReadVIWALUX", 0>; +defm : LMULReadAdvance<"ReadVExtV", 0>; +defm : LMULReadAdvance<"ReadVICALUV", 0>; +defm : LMULReadAdvance<"ReadVICALUX", 0>; +defm : LMULReadAdvance<"ReadVShiftV", 0>; +defm : LMULReadAdvance<"ReadVShiftX", 0>; +defm : LMULReadAdvanceW<"ReadVNShiftV", 0>; +defm : LMULReadAdvanceW<"ReadVNShiftX", 0>; +defm : LMULReadAdvance<"ReadVICmpV", 0>; +defm : LMULReadAdvance<"ReadVICmpX", 0>; +defm : LMULReadAdvance<"ReadVIMinMaxV", 0>; +defm : LMULReadAdvance<"ReadVIMinMaxX", 0>; +defm : LMULReadAdvance<"ReadVIMulV", 0>; +defm : LMULReadAdvance<"ReadVIMulX", 0>; +defm : LMULSEWReadAdvance<"ReadVIDivV", 0>; +defm : LMULSEWReadAdvance<"ReadVIDivX", 0>; +defm : LMULReadAdvanceW<"ReadVIWMulV", 0>; +defm : LMULReadAdvanceW<"ReadVIWMulX", 0>; +defm : LMULReadAdvance<"ReadVIMulAddV", 0>; +defm : LMULReadAdvance<"ReadVIMulAddX", 0>; +defm : LMULReadAdvanceW<"ReadVIWMulAddV", 0>; +defm : LMULReadAdvanceW<"ReadVIWMulAddX", 0>; +defm : LMULReadAdvance<"ReadVIMergeV", 0>; +defm : LMULReadAdvance<"ReadVIMergeX", 0>; +defm : LMULReadAdvance<"ReadVIMovV", 0>; +defm : LMULReadAdvance<"ReadVIMovX", 0>; + +// 12. Vector Fixed-Point Arithmetic Instructions +defm "" : LMULReadAdvance<"ReadVSALUV", 0>; +defm "" : LMULReadAdvance<"ReadVSALUX", 0>; +defm "" : LMULReadAdvance<"ReadVAALUV", 0>; +defm "" : LMULReadAdvance<"ReadVAALUX", 0>; +defm "" : LMULReadAdvance<"ReadVSMulV", 0>; +defm "" : LMULReadAdvance<"ReadVSMulX", 0>; +defm "" : LMULReadAdvance<"ReadVSShiftV", 0>; +defm "" : LMULReadAdvance<"ReadVSShiftX", 0>; +defm "" : LMULReadAdvanceW<"ReadVNClipV", 0>; +defm "" : LMULReadAdvanceW<"ReadVNClipX", 0>; + +// 13. Vector Floating-Point Instructions +defm "" : LMULSEWReadAdvanceF<"ReadVFALUV", 0>; +defm "" : LMULSEWReadAdvanceF<"ReadVFALUF", 0>; +defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUV", 0>; +defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUF", 0>; +defm "" : LMULSEWReadAdvanceF<"ReadVFMulV", 0>; +defm "" : LMULSEWReadAdvanceF<"ReadVFMulF", 0>; +defm "" : LMULSEWReadAdvanceF<"ReadVFDivV", 0>; +defm "" : LMULSEWReadAdvanceF<"ReadVFDivF", 0>; +defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulV", 0>; +defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulF", 0>; +defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddV", 0>; +defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddF", 0>; +defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddV", 0>; +defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddF", 0>; +defm "" : LMULSEWReadAdvanceF<"ReadVFSqrtV", 0>; +defm "" : LMULSEWReadAdvanceF<"ReadVFRecpV", 0>; +defm "" : LMULReadAdvance<"ReadVFCmpV", 0>; +defm "" : LMULReadAdvance<"ReadVFCmpF", 0>; +defm "" : LMULSEWReadAdvanceF<"ReadVFMinMaxV", 0>; +defm "" : LMULSEWReadAdvanceF<"ReadVFMinMaxF", 0>; +defm "" : LMULSEWReadAdvanceF<"ReadVFSgnjV", 0>; +defm "" : LMULSEWReadAdvanceF<"ReadVFSgnjF", 0>; +defm "" : LMULReadAdvance<"ReadVFClassV", 0>; +defm "" : LMULReadAdvance<"ReadVFMergeV", 0>; +defm "" : LMULReadAdvance<"ReadVFMergeF", 0>; +defm "" : LMULReadAdvance<"ReadVFMovF", 0>; +defm "" : LMULSEWReadAdvanceF<"ReadVFCvtIToFV", 0>; +defm "" : LMULReadAdvance<"ReadVFCvtFToIV", 0>; +defm "" : LMULSEWReadAdvanceW<"ReadVFWCvtIToFV", 0>; +defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToIV", 0>; +defm "" : LMULSEWReadAdvanceFW<"ReadVFWCvtFToFV", 0>; +defm "" : LMULSEWReadAdvanceFW<"ReadVFNCvtIToFV", 0>; +defm "" : LMULReadAdvanceW<"ReadVFNCvtFToIV", 0>; +defm "" : LMULSEWReadAdvanceFW<"ReadVFNCvtFToFV", 0>; + +// 14. Vector Reduction Operations +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; + +// 15. Vector Mask Instructions +defm "" : LMULReadAdvance<"ReadVMALUV", 0>; +defm "" : LMULReadAdvance<"ReadVMPopV", 0>; +defm "" : LMULReadAdvance<"ReadVMFFSV", 0>; +defm "" : LMULReadAdvance<"ReadVMSFSV", 0>; +defm "" : LMULReadAdvance<"ReadVIotaV", 0>; + +// 16. Vector Permutation Instructions +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +defm "" : LMULReadAdvance<"ReadVISlideV", 0>; +defm "" : LMULReadAdvance<"ReadVISlideX", 0>; +defm "" : LMULReadAdvance<"ReadVFSlideV", 0>; +defm "" : LMULReadAdvance<"ReadVFSlideF", 0>; +defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_data", 0>; +defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_index", 0>; +defm "" : LMULSEWReadAdvance<"ReadVRGatherEI16VV_data", 0>; +defm "" : LMULSEWReadAdvance<"ReadVRGatherEI16VV_index", 0>; +defm "" : LMULReadAdvance<"ReadVRGatherVX_data", 0>; +defm "" : LMULReadAdvance<"ReadVRGatherVX_index", 0>; +defm "" : LMULReadAdvance<"ReadVRGatherVI_data", 0>; +defm "" : LMULSEWReadAdvance<"ReadVCompressV", 0>; +// LMUL Aware +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; + +// Vector Crypto Extensions +// Zvbb +defm "" : LMULReadAdvance<"ReadVBREVV", 0>; +defm "" : LMULReadAdvance<"ReadVCLZV", 0>; +defm "" : LMULReadAdvance<"ReadVCPOPV", 0>; +defm "" : LMULReadAdvance<"ReadVCTZV", 0>; +defm "" : LMULReadAdvance<"ReadVWSLLV", 0>; +defm "" : LMULReadAdvance<"ReadVWSLLX", 0>; +// Zvbc +defm "" : LMULReadAdvance<"ReadVCLMULV", 0>; +defm "" : LMULReadAdvance<"ReadVCLMULX", 0>; +// Zvkb +// VANDN uses ReadVIALU[V|X|I] +defm "" : LMULReadAdvance<"ReadVBREV8V", 0>; +defm "" : LMULReadAdvance<"ReadVREV8V", 0>; +defm "" : LMULReadAdvance<"ReadVRotV", 0>; +defm "" : LMULReadAdvance<"ReadVRotX", 0>; +// Zvkg +defm "" : LMULReadAdvance<"ReadVGHSHV", 0>; +defm "" : LMULReadAdvance<"ReadVGMULV", 0>; +// Zvknha or Zvknhb +defm "" : LMULReadAdvance<"ReadVSHA2CHV", 0>; +defm "" : LMULReadAdvance<"ReadVSHA2CLV", 0>; +defm "" : LMULSEWReadAdvance<"ReadVSHA2MSV", 0>; +// Zvkned +defm "" : LMULReadAdvance<"ReadVAESMVV", 0>; +defm "" : LMULReadAdvance<"ReadVAESKF1V", 0>; +defm "" : LMULReadAdvance<"ReadVAESKF2V", 0>; +defm "" : LMULReadAdvance<"ReadVAESZV", 0>; +// Zvksed +defm "" : LMULReadAdvance<"ReadVSM4KV", 0>; +defm "" : LMULReadAdvance<"ReadVSM4RV", 0>; +// Zbksh +defm "" : LMULReadAdvance<"ReadVSM3CV", 0>; +defm "" : LMULReadAdvance<"ReadVSM3MEV", 0>; + +// Others +def : ReadAdvance; +def : ReadAdvance; +foreach mx = SchedMxList in { + def : ReadAdvance("ReadVPassthru_" # mx), 0>; + foreach sew = SchedSEWSet.val in + def : ReadAdvance("ReadVPassthru_" # mx # "_E" # sew), 0>; +} + //===----------------------------------------------------------------------===// // Unsupported extensions defm : UnsupportedSchedQ; -defm : UnsupportedSchedV; defm : UnsupportedSchedZabha; defm : UnsupportedSchedZbkb; defm : UnsupportedSchedZbkx; defm : UnsupportedSchedZfaWithQ; -defm : UnsupportedSchedZvk; defm : UnsupportedSchedSFB; defm : UnsupportedSchedXsf; } - diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/atomic.test b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/atomic.test index 68128557b7d7b..c82b7f887fb14 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/atomic.test +++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/atomic.test @@ -10,6 +10,13 @@ # CHECK-NEXT: [5] - SMTX100_IQ0:2 # CHECK-NEXT: [6] - SMTX100_IQ1:2 # CHECK-NEXT: [7] - SMTX100_LSQ:4 +# CHECK-NEXT: [8] - SMTX100_VEU0:1 +# CHECK-NEXT: [9] - SMTX100_VEU1:1 +# CHECK-NEXT: [10] - SMTX100_VEU2:1 +# CHECK-NEXT: [11] - SMTX100_VEU3:1 +# CHECK-NEXT: [12] - SMTX100_VFPU:2 SMTX100_VEU0, SMTX100_VEU1 +# CHECK-NEXT: [13] - SMTX100_VIEU:2 SMTX100_VEU0, SMTX100_VEU1 +# CHECK-NEXT: [14] - SMTX100_VLSU:2 SMTX100_VEU2, SMTX100_VEU3 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -127,98 +134,102 @@ # CHECK-NEXT: [5.1] - SMTX100_LSQ # CHECK-NEXT: [5.2] - SMTX100_LSQ # CHECK-NEXT: [5.3] - SMTX100_LSQ +# CHECK-NEXT: [6] - SMTX100_VEU0 +# CHECK-NEXT: [7] - SMTX100_VEU1 +# CHECK-NEXT: [8] - SMTX100_VEU2 +# CHECK-NEXT: [9] - SMTX100_VEU3 # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [3.0] [3.1] [4.0] [4.1] [5.0] [5.1] [5.2] [5.3] -# CHECK-NEXT: - - - - - - - - - - 22.00 22.00 22.00 22.00 +# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [3.0] [3.1] [4.0] [4.1] [5.0] [5.1] [5.2] [5.3] [6] [7] [8] [9] +# CHECK-NEXT: - - - - - - - - - - 22.00 22.00 22.00 22.00 - - - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [3.0] [3.1] [4.0] [4.1] [5.0] [5.1] [5.2] [5.3] Instructions: -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 lr.w t0, (t1) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 lr.w.aq t1, (t2) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 lr.w.rl t2, (t3) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 lr.w.aqrl t3, (t4) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 sc.w t6, t5, (t4) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 sc.w.aq t5, t4, (t3) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 sc.w.rl t4, t3, (t2) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 sc.w.aqrl t3, t2, (t1) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 lr.d t0, (t1) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 lr.d.aq t1, (t2) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 lr.d.rl t2, (t3) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 lr.d.aqrl t3, (t4) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 sc.d t6, t5, (t4) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 sc.d.aq t5, t4, (t3) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 sc.d.rl t4, t3, (t2) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 sc.d.aqrl t3, t2, (t1) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoswap.w a4, ra, (s0) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoadd.w a1, a2, (a3) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoxor.w a2, a3, (a4) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoand.w a3, a4, (a5) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoor.w a4, a5, (a6) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amomin.w a5, a6, (a7) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amomax.w s7, s6, (s5) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amominu.w s6, s5, (s4) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amomaxu.w s5, s4, (s3) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoswap.w.aq a4, ra, (s0) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoadd.w.aq a1, a2, (a3) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoxor.w.aq a2, a3, (a4) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoand.w.aq a3, a4, (a5) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoor.w.aq a4, a5, (a6) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amomin.w.aq a5, a6, (a7) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amomax.w.aq s7, s6, (s5) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amominu.w.aq s6, s5, (s4) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amomaxu.w.aq s5, s4, (s3) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoswap.w.rl a4, ra, (s0) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoadd.w.rl a1, a2, (a3) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoxor.w.rl a2, a3, (a4) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoand.w.rl a3, a4, (a5) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoor.w.rl a4, a5, (a6) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amomin.w.rl a5, a6, (a7) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amomax.w.rl s7, s6, (s5) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amominu.w.rl s6, s5, (s4) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amomaxu.w.rl s5, s4, (s3) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoswap.w.aqrl a4, ra, (s0) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoadd.w.aqrl a1, a2, (a3) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoxor.w.aqrl a2, a3, (a4) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoand.w.aqrl a3, a4, (a5) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoor.w.aqrl a4, a5, (a6) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amomin.w.aqrl a5, a6, (a7) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amomax.w.aqrl s7, s6, (s5) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amominu.w.aqrl s6, s5, (s4) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amomaxu.w.aqrl s5, s4, (s3) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoswap.d a4, ra, (s0) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoadd.d a1, a2, (a3) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoxor.d a2, a3, (a4) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoand.d a3, a4, (a5) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoor.d a4, a5, (a6) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amomin.d a5, a6, (a7) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amomax.d s7, s6, (s5) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amominu.d s6, s5, (s4) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amomaxu.d s5, s4, (s3) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoswap.d.aq a4, ra, (s0) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoadd.d.aq a1, a2, (a3) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoxor.d.aq a2, a3, (a4) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoand.d.aq a3, a4, (a5) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoor.d.aq a4, a5, (a6) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amomin.d.aq a5, a6, (a7) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amomax.d.aq s7, s6, (s5) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amominu.d.aq s6, s5, (s4) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amomaxu.d.aq s5, s4, (s3) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoswap.d.rl a4, ra, (s0) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoadd.d.rl a1, a2, (a3) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoxor.d.rl a2, a3, (a4) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoand.d.rl a3, a4, (a5) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoor.d.rl a4, a5, (a6) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amomin.d.rl a5, a6, (a7) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amomax.d.rl s7, s6, (s5) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amominu.d.rl s6, s5, (s4) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amomaxu.d.rl s5, s4, (s3) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoswap.d.aqrl a4, ra, (s0) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoadd.d.aqrl a1, a2, (a3) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoxor.d.aqrl a2, a3, (a4) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoand.d.aqrl a3, a4, (a5) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amoor.d.aqrl a4, a5, (a6) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amomin.d.aqrl a5, a6, (a7) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amomax.d.aqrl s7, s6, (s5) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amominu.d.aqrl s6, s5, (s4) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 amomaxu.d.aqrl s5, s4, (s3) +# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [3.0] [3.1] [4.0] [4.1] [5.0] [5.1] [5.2] [5.3] [6] [7] [8] [9] Instructions: +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - lr.w t0, (t1) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - lr.w.aq t1, (t2) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - lr.w.rl t2, (t3) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - lr.w.aqrl t3, (t4) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - sc.w t6, t5, (t4) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - sc.w.aq t5, t4, (t3) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - sc.w.rl t4, t3, (t2) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - sc.w.aqrl t3, t2, (t1) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - lr.d t0, (t1) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - lr.d.aq t1, (t2) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - lr.d.rl t2, (t3) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - lr.d.aqrl t3, (t4) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - sc.d t6, t5, (t4) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - sc.d.aq t5, t4, (t3) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - sc.d.rl t4, t3, (t2) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - sc.d.aqrl t3, t2, (t1) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoswap.w a4, ra, (s0) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoadd.w a1, a2, (a3) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoxor.w a2, a3, (a4) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoand.w a3, a4, (a5) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoor.w a4, a5, (a6) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amomin.w a5, a6, (a7) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amomax.w s7, s6, (s5) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amominu.w s6, s5, (s4) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amomaxu.w s5, s4, (s3) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoswap.w.aq a4, ra, (s0) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoadd.w.aq a1, a2, (a3) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoxor.w.aq a2, a3, (a4) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoand.w.aq a3, a4, (a5) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoor.w.aq a4, a5, (a6) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amomin.w.aq a5, a6, (a7) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amomax.w.aq s7, s6, (s5) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amominu.w.aq s6, s5, (s4) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amomaxu.w.aq s5, s4, (s3) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoswap.w.rl a4, ra, (s0) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoadd.w.rl a1, a2, (a3) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoxor.w.rl a2, a3, (a4) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoand.w.rl a3, a4, (a5) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoor.w.rl a4, a5, (a6) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amomin.w.rl a5, a6, (a7) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amomax.w.rl s7, s6, (s5) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amominu.w.rl s6, s5, (s4) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amomaxu.w.rl s5, s4, (s3) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoswap.w.aqrl a4, ra, (s0) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoadd.w.aqrl a1, a2, (a3) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoxor.w.aqrl a2, a3, (a4) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoand.w.aqrl a3, a4, (a5) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoor.w.aqrl a4, a5, (a6) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amomin.w.aqrl a5, a6, (a7) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amomax.w.aqrl s7, s6, (s5) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amominu.w.aqrl s6, s5, (s4) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amomaxu.w.aqrl s5, s4, (s3) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoswap.d a4, ra, (s0) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoadd.d a1, a2, (a3) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoxor.d a2, a3, (a4) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoand.d a3, a4, (a5) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoor.d a4, a5, (a6) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amomin.d a5, a6, (a7) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amomax.d s7, s6, (s5) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amominu.d s6, s5, (s4) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amomaxu.d s5, s4, (s3) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoswap.d.aq a4, ra, (s0) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoadd.d.aq a1, a2, (a3) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoxor.d.aq a2, a3, (a4) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoand.d.aq a3, a4, (a5) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoor.d.aq a4, a5, (a6) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amomin.d.aq a5, a6, (a7) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amomax.d.aq s7, s6, (s5) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amominu.d.aq s6, s5, (s4) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amomaxu.d.aq s5, s4, (s3) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoswap.d.rl a4, ra, (s0) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoadd.d.rl a1, a2, (a3) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoxor.d.rl a2, a3, (a4) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoand.d.rl a3, a4, (a5) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoor.d.rl a4, a5, (a6) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amomin.d.rl a5, a6, (a7) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amomax.d.rl s7, s6, (s5) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amominu.d.rl s6, s5, (s4) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amomaxu.d.rl s5, s4, (s3) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoswap.d.aqrl a4, ra, (s0) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoadd.d.aqrl a1, a2, (a3) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoxor.d.aqrl a2, a3, (a4) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoand.d.aqrl a3, a4, (a5) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amoor.d.aqrl a4, a5, (a6) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amomin.d.aqrl a5, a6, (a7) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amomax.d.aqrl s7, s6, (s5) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amominu.d.aqrl s6, s5, (s4) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - amomaxu.d.aqrl s5, s4, (s3) diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/floating-point.test b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/floating-point.test index 26c2fe941da13..856a7da3775b2 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/floating-point.test +++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/floating-point.test @@ -10,6 +10,13 @@ # CHECK-NEXT: [5] - SMTX100_IQ0:2 # CHECK-NEXT: [6] - SMTX100_IQ1:2 # CHECK-NEXT: [7] - SMTX100_LSQ:4 +# CHECK-NEXT: [8] - SMTX100_VEU0:1 +# CHECK-NEXT: [9] - SMTX100_VEU1:1 +# CHECK-NEXT: [10] - SMTX100_VEU2:1 +# CHECK-NEXT: [11] - SMTX100_VEU3:1 +# CHECK-NEXT: [12] - SMTX100_VFPU:2 SMTX100_VEU0, SMTX100_VEU1 +# CHECK-NEXT: [13] - SMTX100_VIEU:2 SMTX100_VEU0, SMTX100_VEU1 +# CHECK-NEXT: [14] - SMTX100_VLSU:2 SMTX100_VEU2, SMTX100_VEU3 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -99,70 +106,74 @@ # CHECK-NEXT: [5.1] - SMTX100_LSQ # CHECK-NEXT: [5.2] - SMTX100_LSQ # CHECK-NEXT: [5.3] - SMTX100_LSQ +# CHECK-NEXT: [6] - SMTX100_VEU0 +# CHECK-NEXT: [7] - SMTX100_VEU1 +# CHECK-NEXT: [8] - SMTX100_VEU2 +# CHECK-NEXT: [9] - SMTX100_VEU3 # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [3.0] [3.1] [4.0] [4.1] [5.0] [5.1] [5.2] [5.3] -# CHECK-NEXT: - - 40.50 40.50 17.50 17.50 - - - - 1.00 1.00 1.00 1.00 +# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [3.0] [3.1] [4.0] [4.1] [5.0] [5.1] [5.2] [5.3] [6] [7] [8] [9] +# CHECK-NEXT: - - 40.50 40.50 17.50 17.50 - - - - 1.00 1.00 1.00 1.00 - - - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [3.0] [3.1] [4.0] [4.1] [5.0] [5.1] [5.2] [5.3] Instructions: -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 flw ft0, 0(a0) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 fsw ft0, 0(a0) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 fld ft0, 0(a0) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 fsd ft0, 0(a0) -# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - fadd.s fs10, fs11, ft8 -# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - fsub.s ft9, ft10, ft11 -# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - fmul.s ft0, ft1, ft2 -# CHECK-NEXT: - - 6.00 6.00 - - - - - - - - - - fdiv.s ft3, ft4, ft5 -# CHECK-NEXT: - - 6.00 6.00 - - - - - - - - - - fsqrt.s ft6, ft7 -# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - fmin.s fa5, fa6, fa7 -# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - fmax.s fs2, fs3, fs4 -# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - fmadd.s fa0, fa1, fa2, ft11 -# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - fmsub.s fa4, fa5, fa6, fa7 -# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - fnmsub.s fs2, fs3, fs4, fs5 -# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - fnmadd.s fs6, fs7, fs8, fs9 -# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - fadd.d fs10, fs11, ft8 -# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - fsub.d ft9, ft10, ft11 -# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - fmul.d ft0, ft1, ft2 -# CHECK-NEXT: - - 10.00 10.00 - - - - - - - - - - fdiv.d ft3, ft4, ft5 -# CHECK-NEXT: - - 10.00 10.00 - - - - - - - - - - fsqrt.d ft6, ft7 -# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - fmin.d fa5, fa6, fa7 -# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - fmax.d fs2, fs3, fs4 -# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - fmadd.d fa0, fa1, fa2, ft11 -# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - fmsub.d fa4, fa5, fa6, fa7 -# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - fnmsub.d fs2, fs3, fs4, fs5 -# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - fnmadd.d fs6, fs7, fs8, fs9 -# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - fcvt.w.s a0, fs5 -# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - fcvt.wu.s a1, fs6 -# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - fcvt.s.w ft11, a4 -# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - fcvt.s.wu ft0, a5 -# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - fcvt.l.s a0, ft0 -# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - fcvt.lu.s a1, ft1 -# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - fcvt.s.l ft2, a2 -# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - fcvt.s.lu ft3, a3 -# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - fmv.x.w a2, fs7 -# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - fmv.w.x ft1, a6 -# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - fsgnj.s fs1, fa0, fa1 -# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - fsgnjn.s fa1, fa3, fa4 -# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - fcvt.wu.d a4, ft11 -# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - fcvt.w.d a4, ft11 -# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - fcvt.d.w ft0, a5 -# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - fcvt.d.wu ft1, a6 -# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - fcvt.s.d fs5, fs6 -# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - fcvt.d.s fs7, fs8 -# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - fcvt.l.d a0, ft0 -# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - fcvt.lu.d a1, ft1 -# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - fcvt.d.l ft3, a3 -# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - fcvt.d.lu ft4, a4 -# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - fmv.x.d a2, ft2 -# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - fmv.d.x ft5, a5 -# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - fsgnj.d fs1, fa0, fa1 -# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - fsgnjn.d fa1, fa3, fa4 -# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - feq.s a1, fs8, fs9 -# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - flt.s a2, fs10, fs11 -# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - fle.s a3, ft8, ft9 -# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - feq.d a1, fs8, fs9 -# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - flt.d a2, fs10, fs11 -# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - fle.d a3, ft8, ft9 -# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - fclass.s a3, ft10 -# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - fclass.d a3, ft10 +# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [3.0] [3.1] [4.0] [4.1] [5.0] [5.1] [5.2] [5.3] [6] [7] [8] [9] Instructions: +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - flw ft0, 0(a0) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - fsw ft0, 0(a0) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - fld ft0, 0(a0) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - fsd ft0, 0(a0) +# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - fadd.s fs10, fs11, ft8 +# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - fsub.s ft9, ft10, ft11 +# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - fmul.s ft0, ft1, ft2 +# CHECK-NEXT: - - 6.00 6.00 - - - - - - - - - - - - - - fdiv.s ft3, ft4, ft5 +# CHECK-NEXT: - - 6.00 6.00 - - - - - - - - - - - - - - fsqrt.s ft6, ft7 +# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - fmin.s fa5, fa6, fa7 +# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - fmax.s fs2, fs3, fs4 +# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - fmadd.s fa0, fa1, fa2, ft11 +# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - fmsub.s fa4, fa5, fa6, fa7 +# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - fnmsub.s fs2, fs3, fs4, fs5 +# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - fnmadd.s fs6, fs7, fs8, fs9 +# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - fadd.d fs10, fs11, ft8 +# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - fsub.d ft9, ft10, ft11 +# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - fmul.d ft0, ft1, ft2 +# CHECK-NEXT: - - 10.00 10.00 - - - - - - - - - - - - - - fdiv.d ft3, ft4, ft5 +# CHECK-NEXT: - - 10.00 10.00 - - - - - - - - - - - - - - fsqrt.d ft6, ft7 +# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - fmin.d fa5, fa6, fa7 +# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - fmax.d fs2, fs3, fs4 +# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - fmadd.d fa0, fa1, fa2, ft11 +# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - fmsub.d fa4, fa5, fa6, fa7 +# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - fnmsub.d fs2, fs3, fs4, fs5 +# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - fnmadd.d fs6, fs7, fs8, fs9 +# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - fcvt.w.s a0, fs5 +# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - fcvt.wu.s a1, fs6 +# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - fcvt.s.w ft11, a4 +# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - fcvt.s.wu ft0, a5 +# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - fcvt.l.s a0, ft0 +# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - fcvt.lu.s a1, ft1 +# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - fcvt.s.l ft2, a2 +# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - fcvt.s.lu ft3, a3 +# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - fmv.x.w a2, fs7 +# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - fmv.w.x ft1, a6 +# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - fsgnj.s fs1, fa0, fa1 +# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - fsgnjn.s fa1, fa3, fa4 +# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - fcvt.wu.d a4, ft11 +# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - fcvt.w.d a4, ft11 +# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - fcvt.d.w ft0, a5 +# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - fcvt.d.wu ft1, a6 +# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - fcvt.s.d fs5, fs6 +# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - fcvt.d.s fs7, fs8 +# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - fcvt.l.d a0, ft0 +# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - fcvt.lu.d a1, ft1 +# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - fcvt.d.l ft3, a3 +# CHECK-NEXT: - - - - 0.50 0.50 - - - - - - - - - - - - fcvt.d.lu ft4, a4 +# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - fmv.x.d a2, ft2 +# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - fmv.d.x ft5, a5 +# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - fsgnj.d fs1, fa0, fa1 +# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - fsgnjn.d fa1, fa3, fa4 +# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - feq.s a1, fs8, fs9 +# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - flt.s a2, fs10, fs11 +# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - fle.s a3, ft8, ft9 +# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - feq.d a1, fs8, fs9 +# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - flt.d a2, fs10, fs11 +# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - fle.d a3, ft8, ft9 +# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - fclass.s a3, ft10 +# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - - - - - - - fclass.d a3, ft10 diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/integer.test b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/integer.test index 453cc07cb1792..7dbf89e10c4c5 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/integer.test +++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/integer.test @@ -10,6 +10,13 @@ # CHECK-NEXT: [5] - SMTX100_IQ0:2 # CHECK-NEXT: [6] - SMTX100_IQ1:2 # CHECK-NEXT: [7] - SMTX100_LSQ:4 +# CHECK-NEXT: [8] - SMTX100_VEU0:1 +# CHECK-NEXT: [9] - SMTX100_VEU1:1 +# CHECK-NEXT: [10] - SMTX100_VEU2:1 +# CHECK-NEXT: [11] - SMTX100_VEU3:1 +# CHECK-NEXT: [12] - SMTX100_VFPU:2 SMTX100_VEU0, SMTX100_VEU1 +# CHECK-NEXT: [13] - SMTX100_VIEU:2 SMTX100_VEU0, SMTX100_VEU1 +# CHECK-NEXT: [14] - SMTX100_VLSU:2 SMTX100_VEU2, SMTX100_VEU3 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -95,66 +102,70 @@ # CHECK-NEXT: [5.1] - SMTX100_LSQ # CHECK-NEXT: [5.2] - SMTX100_LSQ # CHECK-NEXT: [5.3] - SMTX100_LSQ +# CHECK-NEXT: [6] - SMTX100_VEU0 +# CHECK-NEXT: [7] - SMTX100_VEU1 +# CHECK-NEXT: [8] - SMTX100_VEU2 +# CHECK-NEXT: [9] - SMTX100_VEU3 # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [3.0] [3.1] [4.0] [4.1] [5.0] [5.1] [5.2] [5.3] -# CHECK-NEXT: 4.00 4.00 - - - - 10.75 10.75 7.75 7.75 2.75 2.75 2.75 2.75 +# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [3.0] [3.1] [4.0] [4.1] [5.0] [5.1] [5.2] [5.3] [6] [7] [8] [9] +# CHECK-NEXT: 4.00 4.00 - - - - 10.75 10.75 7.75 7.75 2.75 2.75 2.75 2.75 - - - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [3.0] [3.1] [4.0] [4.1] [5.0] [5.1] [5.2] [5.3] Instructions: -# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - addi a0, a0, 1 -# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - addiw a0, a0, 1 -# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - slti a0, a0, 1 -# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - seqz a0, a0 -# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - andi a0, a0, 1 -# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - ori a0, a0, 1 -# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - xori a0, a0, 1 -# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - slli a0, a0, 1 -# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - srli a0, a0, 1 -# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - srai a0, a0, 1 -# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - slliw a0, a0, 1 -# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - srliw a0, a0, 1 -# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - sraiw a0, a0, 1 -# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - lui a0, 1 -# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - auipc a1, 1 -# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - add a0, a0, a1 -# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - addw a0, a0, a0 -# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - slt a0, a0, a0 -# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - sltu a0, a0, a0 -# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - and a0, a0, a0 -# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - or a0, a0, a0 -# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - xor a0, a0, a0 -# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - sll a0, a0, a0 -# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - srl a0, a0, a0 -# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - sra a0, a0, a0 -# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - sllw a0, a0, a0 -# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - srlw a0, a0, a0 -# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - sraw a0, a0, a0 -# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - sub a0, a0, a0 -# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - subw a0, a0, a0 -# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - jal a0, .Ltmp0 -# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - jalr a0 -# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - beq a0, a0, .Ltmp1 -# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - bne a0, a0, .Ltmp2 -# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - blt a0, a0, .Ltmp3 -# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - bltu a0, a0, .Ltmp4 -# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - bge a0, a0, .Ltmp5 -# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - bgeu a0, a0, .Ltmp6 -# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - add a0, a0, a0 -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 lb t0, 0(a0) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 lbu t0, 0(a0) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 lh t0, 0(a0) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 lhu t0, 0(a0) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 lw t0, 0(a0) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 lwu t0, 0(a0) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 ld t0, 0(a0) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 sb t0, 0(a0) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 sh t0, 0(a0) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 sw t0, 0(a0) -# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 sd t0, 0(a0) -# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - csrrw t0, 4095, t1 -# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - csrrs s3, fflags, s5 -# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - csrrc sp, 0, ra -# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - csrrwi a5, 0, 0 -# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - csrrsi t2, 4095, 31 -# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - csrrci t1, sscratch, 5 +# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [3.0] [3.1] [4.0] [4.1] [5.0] [5.1] [5.2] [5.3] [6] [7] [8] [9] Instructions: +# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - addi a0, a0, 1 +# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - addiw a0, a0, 1 +# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - slti a0, a0, 1 +# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - seqz a0, a0 +# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - andi a0, a0, 1 +# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - ori a0, a0, 1 +# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - xori a0, a0, 1 +# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - slli a0, a0, 1 +# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - srli a0, a0, 1 +# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - srai a0, a0, 1 +# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - slliw a0, a0, 1 +# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - srliw a0, a0, 1 +# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - sraiw a0, a0, 1 +# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - lui a0, 1 +# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - auipc a1, 1 +# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - add a0, a0, a1 +# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - addw a0, a0, a0 +# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - slt a0, a0, a0 +# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - sltu a0, a0, a0 +# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - and a0, a0, a0 +# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - or a0, a0, a0 +# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - xor a0, a0, a0 +# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - sll a0, a0, a0 +# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - srl a0, a0, a0 +# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - sra a0, a0, a0 +# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - sllw a0, a0, a0 +# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - srlw a0, a0, a0 +# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - sraw a0, a0, a0 +# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - sub a0, a0, a0 +# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - subw a0, a0, a0 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - jal a0, .Ltmp0 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - jalr a0 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - beq a0, a0, .Ltmp1 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - bne a0, a0, .Ltmp2 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - blt a0, a0, .Ltmp3 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - bltu a0, a0, .Ltmp4 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - bge a0, a0, .Ltmp5 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - bgeu a0, a0, .Ltmp6 +# CHECK-NEXT: - - - - - - 0.25 0.25 0.25 0.25 - - - - - - - - add a0, a0, a0 +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - lb t0, 0(a0) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - lbu t0, 0(a0) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - lh t0, 0(a0) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - lhu t0, 0(a0) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - lw t0, 0(a0) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - lwu t0, 0(a0) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - ld t0, 0(a0) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - sb t0, 0(a0) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - sh t0, 0(a0) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - sw t0, 0(a0) +# CHECK-NEXT: - - - - - - - - - - 0.25 0.25 0.25 0.25 - - - - sd t0, 0(a0) +# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - csrrw t0, 4095, t1 +# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - csrrs s3, fflags, s5 +# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - csrrc sp, 0, ra +# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - csrrwi a5, 0, 0 +# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - csrrsi t2, 4095, 31 +# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - csrrci t1, sscratch, 5 diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/mul-div.test b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/mul-div.test index 2718c787e8d09..e5349c0363121 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/mul-div.test +++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/mul-div.test @@ -10,6 +10,13 @@ # CHECK-NEXT: [5] - SMTX100_IQ0:2 # CHECK-NEXT: [6] - SMTX100_IQ1:2 # CHECK-NEXT: [7] - SMTX100_LSQ:4 +# CHECK-NEXT: [8] - SMTX100_VEU0:1 +# CHECK-NEXT: [9] - SMTX100_VEU1:1 +# CHECK-NEXT: [10] - SMTX100_VEU2:1 +# CHECK-NEXT: [11] - SMTX100_VEU3:1 +# CHECK-NEXT: [12] - SMTX100_VFPU:2 SMTX100_VEU0, SMTX100_VEU1 +# CHECK-NEXT: [13] - SMTX100_VIEU:2 SMTX100_VEU0, SMTX100_VEU1 +# CHECK-NEXT: [14] - SMTX100_VLSU:2 SMTX100_VEU2, SMTX100_VEU3 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -52,23 +59,27 @@ # CHECK-NEXT: [5.1] - SMTX100_LSQ # CHECK-NEXT: [5.2] - SMTX100_LSQ # CHECK-NEXT: [5.3] - SMTX100_LSQ +# CHECK-NEXT: [6] - SMTX100_VEU0 +# CHECK-NEXT: [7] - SMTX100_VEU1 +# CHECK-NEXT: [8] - SMTX100_VEU2 +# CHECK-NEXT: [9] - SMTX100_VEU3 # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [3.0] [3.1] [4.0] [4.1] [5.0] [5.1] [5.2] [5.3] -# CHECK-NEXT: - - - - - - 72.00 72.00 2.50 2.50 - - - - +# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [3.0] [3.1] [4.0] [4.1] [5.0] [5.1] [5.2] [5.3] [6] [7] [8] [9] +# CHECK-NEXT: - - - - - - 72.00 72.00 2.50 2.50 - - - - - - - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [3.0] [3.1] [4.0] [4.1] [5.0] [5.1] [5.2] [5.3] Instructions: -# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - mul a0, a0, a0 -# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - mulh a0, a0, a0 -# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - mulhu a0, a0, a0 -# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - mulhsu a0, a0, a0 -# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - mulw a0, a0, a0 -# CHECK-NEXT: - - - - - - 11.00 11.00 - - - - - - div a0, a1, a2 -# CHECK-NEXT: - - - - - - 11.00 11.00 - - - - - - divu a0, a1, a2 -# CHECK-NEXT: - - - - - - 11.00 11.00 - - - - - - rem a0, a1, a2 -# CHECK-NEXT: - - - - - - 11.00 11.00 - - - - - - remu a0, a1, a2 -# CHECK-NEXT: - - - - - - 7.00 7.00 - - - - - - divw a0, a1, a2 -# CHECK-NEXT: - - - - - - 7.00 7.00 - - - - - - divuw a0, a1, a2 -# CHECK-NEXT: - - - - - - 7.00 7.00 - - - - - - remw a0, a1, a2 -# CHECK-NEXT: - - - - - - 7.00 7.00 - - - - - - remuw a0, a1, a2 +# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [3.0] [3.1] [4.0] [4.1] [5.0] [5.1] [5.2] [5.3] [6] [7] [8] [9] Instructions: +# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - mul a0, a0, a0 +# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - mulh a0, a0, a0 +# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - mulhu a0, a0, a0 +# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - mulhsu a0, a0, a0 +# CHECK-NEXT: - - - - - - - - 0.50 0.50 - - - - - - - - mulw a0, a0, a0 +# CHECK-NEXT: - - - - - - 11.00 11.00 - - - - - - - - - - div a0, a1, a2 +# CHECK-NEXT: - - - - - - 11.00 11.00 - - - - - - - - - - divu a0, a1, a2 +# CHECK-NEXT: - - - - - - 11.00 11.00 - - - - - - - - - - rem a0, a1, a2 +# CHECK-NEXT: - - - - - - 11.00 11.00 - - - - - - - - - - remu a0, a1, a2 +# CHECK-NEXT: - - - - - - 7.00 7.00 - - - - - - - - - - divw a0, a1, a2 +# CHECK-NEXT: - - - - - - 7.00 7.00 - - - - - - - - - - divuw a0, a1, a2 +# CHECK-NEXT: - - - - - - 7.00 7.00 - - - - - - - - - - remw a0, a1, a2 +# CHECK-NEXT: - - - - - - 7.00 7.00 - - - - - - - - - - remuw a0, a1, a2 diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/arithmetic.test b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/arithmetic.test new file mode 100644 index 0000000000000..ca13a241d77cf --- /dev/null +++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/arithmetic.test @@ -0,0 +1,4539 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x100 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/arithmetic.s | FileCheck %s + +# CHECK: Resources: +# CHECK-NEXT: [0] - SMTX100_BQ:2 +# CHECK-NEXT: [1] - SMTX100_FQ:4 SMTX100_FQ0, SMTX100_FQ0, SMTX100_FQ1, SMTX100_FQ1 +# CHECK-NEXT: [2] - SMTX100_FQ0:2 +# CHECK-NEXT: [3] - SMTX100_FQ1:2 +# CHECK-NEXT: [4] - SMTX100_IQ:4 SMTX100_IQ0, SMTX100_IQ0, SMTX100_IQ1, SMTX100_IQ1 +# CHECK-NEXT: [5] - SMTX100_IQ0:2 +# CHECK-NEXT: [6] - SMTX100_IQ1:2 +# CHECK-NEXT: [7] - SMTX100_LSQ:4 +# CHECK-NEXT: [8] - SMTX100_VEU0:1 +# CHECK-NEXT: [9] - SMTX100_VEU1:1 +# CHECK-NEXT: [10] - SMTX100_VEU2:1 +# CHECK-NEXT: [11] - SMTX100_VEU3:1 +# CHECK-NEXT: [12] - SMTX100_VFPU:2 SMTX100_VEU0, SMTX100_VEU1 +# CHECK-NEXT: [13] - SMTX100_VIEU:2 SMTX100_VEU0, SMTX100_VEU1 +# CHECK-NEXT: [14] - SMTX100_VLSU:2 SMTX100_VEU2, SMTX100_VEU3 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) +# CHECK-NEXT: [7]: Bypass Latency +# CHECK-NEXT: [8]: Resources ( | [] | [, | [] | [, | [] | [, | [] | [, | [] | [, | [] | [, | [] | [, | [] | [, | [] | [, | [] | [, | [] | [, | [] | [, | [] | [, | [] | [, | [] | [,