diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp index 7f504c3f717f2..d27b40cfe7241 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp @@ -769,6 +769,55 @@ static cir::VectorType getIntVecFromVecTy(CIRGenBuilderTy &builder, "Unsupported element type in getVecOfIntTypeWithSameEltWidth"); } +/// The vld1_xN builtins move their data through an aggregate of N vectors. +/// Return N, or 0 if `builtinID` is not one of them. +static unsigned getNeonMultiVecCount(unsigned builtinID) { + switch (builtinID) { + default: + return 0; + case NEON::BI__builtin_neon_vld1_x2_v: + case NEON::BI__builtin_neon_vld1q_x2_v: + return 2; + case NEON::BI__builtin_neon_vld1_x3_v: + case NEON::BI__builtin_neon_vld1q_x3_v: + return 3; + case NEON::BI__builtin_neon_vld1_x4_v: + case NEON::BI__builtin_neon_vld1q_x4_v: + return 4; + } +} + +/// Return the anonymous record type `{vecTy, ..., vecTy}` (`numVecs` members) +/// modelling the struct returned by LLVM's multi-vector NEON load intrinsics. +static cir::RecordType getNeonMultiVecTy(CIRGenBuilderTy &builder, + mlir::Type vecTy, unsigned numVecs) { + llvm::SmallVector members(numVecs, vecTy); + return builder.getAnonRecordTy(members, /*packed=*/false, + cir::RecordType::getAllDataKinds(members)); +} + +/// Emit a multi-vector NEON load: call `llvmIntrinsic` on the source pointer +/// `ops[1]` and store the resulting aggregate to the destination pointer +/// `ops[0]`. Mirrors the `CreateCall` + `CreateDefaultAlignedStore` pair in +/// `EmitCommonNeonBuiltinExpr` (ARM.cpp). +static mlir::Value emitNeonMultiVecLoad(CIRGenFunction &cgf, + llvm::ArrayRef ops, + unsigned llvmIntrinsic, mlir::Type ty, + unsigned numVecs, mlir::Location loc) { + CIRGenBuilderTy &builder = cgf.getBuilder(); + cir::RecordType recTy = getNeonMultiVecTy(builder, ty, numVecs); + llvm::SmallVector srcOp = {ops[1]}; + mlir::Value result = emitNeonCall( + cgf.getCIRGenModule(), builder, {builder.getVoidPtrTy()}, srcOp, + getLLVMIntrNameNoPrefix(static_cast(llvmIntrinsic)), + recTy, loc); + Address dest(builder.createPtrBitcast(ops[0], recTy), recTy, + clang::CharUnits::fromQuantity( + cgf.cgm.getDataLayout().getABITypeAlign(recTy))); + builder.createStore(loc, result, dest); + return nullptr; +} + static mlir::Value emitCommonNeonBuiltinExpr( CIRGenFunction &cgf, unsigned builtinID, unsigned llvmIntrinsic, unsigned altLLVMIntrinsic, const char *nameHint, unsigned modifier, @@ -1049,14 +1098,16 @@ static mlir::Value emitCommonNeonBuiltinExpr( return emitNeonCallToOp(cgf.cgm, cgf.getBuilder(), {ty, ty, ty}, fmaOps, std::nullopt, ty, loc); } - case NEON::BI__builtin_neon_vld1_v: - case NEON::BI__builtin_neon_vld1q_v: case NEON::BI__builtin_neon_vld1_x2_v: case NEON::BI__builtin_neon_vld1q_x2_v: case NEON::BI__builtin_neon_vld1_x3_v: case NEON::BI__builtin_neon_vld1q_x3_v: case NEON::BI__builtin_neon_vld1_x4_v: case NEON::BI__builtin_neon_vld1q_x4_v: + return emitNeonMultiVecLoad(cgf, ops, llvmIntrinsic, ty, + getNeonMultiVecCount(builtinID), loc); + case NEON::BI__builtin_neon_vld1_v: + case NEON::BI__builtin_neon_vld1q_v: case NEON::BI__builtin_neon_vld2_v: case NEON::BI__builtin_neon_vld2q_v: case NEON::BI__builtin_neon_vld3_v: @@ -2522,11 +2573,6 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr, case NEON::BI__builtin_neon_vld1q_dup_v: case NEON::BI__builtin_neon_vld1_lane_v: case NEON::BI__builtin_neon_vld1q_lane_v: - cgm.errorNYI( - expr->getSourceRange(), - std::string("unimplemented AArch64 builtin argument handling ") + - getContext().BuiltinInfo.getName(builtinID)); - break; case NEON::BI__builtin_neon_vst1_v: case NEON::BI__builtin_neon_vst1q_v: case NEON::BI__builtin_neon_vst1_lane_v: @@ -3472,10 +3518,7 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr, } case NEON::BI__builtin_neon_vld1_v: case NEON::BI__builtin_neon_vld1q_v: - cgm.errorNYI(expr->getSourceRange(), - std::string("unimplemented AArch64 builtin call: ") + - getContext().BuiltinInfo.getName(builtinID)); - return mlir::Value{}; + return builder.createLoad(loc, ptrOp0.withElementType(builder, ty)); case NEON::BI__builtin_neon_vst1_v: case NEON::BI__builtin_neon_vst1q_v: { ops[1] = builder.createBitcast(ops[1], ty); @@ -3483,11 +3526,20 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr, return nullptr; } case NEON::BI__builtin_neon_vld1_lane_v: - case NEON::BI__builtin_neon_vld1q_lane_v: + case NEON::BI__builtin_neon_vld1q_lane_v: { + ops[1] = builder.createBitcast(ops[1], ty); + mlir::Value scalar = builder.createLoad( + loc, ptrOp0.withElementType(builder, ty.getElementType())); + return cir::VecInsertOp::create(builder, loc, ops[1], scalar, ops[2]); + } + case NEON::BI__builtin_neon_vld1_dup_v: + case NEON::BI__builtin_neon_vld1q_dup_v: { + mlir::Value scalar = builder.createLoad( + loc, ptrOp0.withElementType(builder, ty.getElementType())); + return cir::VecSplatOp::create(builder, loc, ty, scalar); + } case NEON::BI__builtin_neon_vldap1_lane_s64: case NEON::BI__builtin_neon_vldap1q_lane_s64: - case NEON::BI__builtin_neon_vld1_dup_v: - case NEON::BI__builtin_neon_vld1q_dup_v: cgm.errorNYI(expr->getSourceRange(), std::string("unimplemented AArch64 builtin call: ") + getContext().BuiltinInfo.getName(builtinID)); diff --git a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp index 22e0dfc55157f..f3d5c5c47e788 100644 --- a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp +++ b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp @@ -1417,12 +1417,6 @@ Value *CodeGenFunction::EmitCommonNeonBuiltinExpr( *this, Intrinsic::fma, Intrinsic::experimental_constrained_fma, Ty, {Ops[1], Ops[2], Ops[0]}); } - case NEON::BI__builtin_neon_vld1_v: - case NEON::BI__builtin_neon_vld1q_v: { - llvm::Type *Tys[] = {Ty, Int8PtrTy}; - Ops.push_back(getAlignmentValue32(PtrOp0)); - return EmitNeonCall(CGM.getIntrinsic(LLVMIntrinsic, Tys), Ops, "vld1"); - } case NEON::BI__builtin_neon_vld1_x2_v: case NEON::BI__builtin_neon_vld1q_x2_v: case NEON::BI__builtin_neon_vld1_x3_v: @@ -1434,6 +1428,12 @@ Value *CodeGenFunction::EmitCommonNeonBuiltinExpr( Ops[1] = Builder.CreateCall(F, Ops[1], "vld1xN"); return Builder.CreateDefaultAlignedStore(Ops[1], Ops[0]); } + case NEON::BI__builtin_neon_vld1_v: + case NEON::BI__builtin_neon_vld1q_v: { + llvm::Type *Tys[] = {Ty, Int8PtrTy}; + Ops.push_back(getAlignmentValue32(PtrOp0)); + return EmitNeonCall(CGM.getIntrinsic(LLVMIntrinsic, Tys), Ops, "vld1"); + } case NEON::BI__builtin_neon_vld2_v: case NEON::BI__builtin_neon_vld2q_v: case NEON::BI__builtin_neon_vld3_v: diff --git a/clang/test/CodeGen/AArch64/neon-intrinsics.c b/clang/test/CodeGen/AArch64/neon-intrinsics.c index 79cb1c42cd5af..8dc0b8f9a2942 100644 --- a/clang/test/CodeGen/AArch64/neon-intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon-intrinsics.c @@ -5388,416 +5388,6 @@ float64_t test_vrsqrted_f64(float64_t a) { return vrsqrted_f64(a); } -// CHECK-LABEL: define dso_local <16 x i8> @test_vld1q_u8( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[A]], align 1 -// CHECK-NEXT: ret <16 x i8> [[TMP0]] -// -uint8x16_t test_vld1q_u8(uint8_t const *a) { - return vld1q_u8(a); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vld1q_u16( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, ptr [[A]], align 2 -// CHECK-NEXT: ret <8 x i16> [[TMP0]] -// -uint16x8_t test_vld1q_u16(uint16_t const *a) { - return vld1q_u16(a); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vld1q_u32( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[A]], align 4 -// CHECK-NEXT: ret <4 x i32> [[TMP0]] -// -uint32x4_t test_vld1q_u32(uint32_t const *a) { - return vld1q_u32(a); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vld1q_u64( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr [[A]], align 8 -// CHECK-NEXT: ret <2 x i64> [[TMP0]] -// -uint64x2_t test_vld1q_u64(uint64_t const *a) { - return vld1q_u64(a); -} - -// CHECK-LABEL: define dso_local <16 x i8> @test_vld1q_s8( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[A]], align 1 -// CHECK-NEXT: ret <16 x i8> [[TMP0]] -// -int8x16_t test_vld1q_s8(int8_t const *a) { - return vld1q_s8(a); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vld1q_s16( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, ptr [[A]], align 2 -// CHECK-NEXT: ret <8 x i16> [[TMP0]] -// -int16x8_t test_vld1q_s16(int16_t const *a) { - return vld1q_s16(a); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vld1q_s32( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[A]], align 4 -// CHECK-NEXT: ret <4 x i32> [[TMP0]] -// -int32x4_t test_vld1q_s32(int32_t const *a) { - return vld1q_s32(a); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vld1q_s64( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr [[A]], align 8 -// CHECK-NEXT: ret <2 x i64> [[TMP0]] -// -int64x2_t test_vld1q_s64(int64_t const *a) { - return vld1q_s64(a); -} - -// CHECK-LABEL: define dso_local <8 x half> @test_vld1q_f16( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <8 x half>, ptr [[A]], align 2 -// CHECK-NEXT: ret <8 x half> [[TMP0]] -// -float16x8_t test_vld1q_f16(float16_t const *a) { - return vld1q_f16(a); -} - -// CHECK-LABEL: define dso_local <4 x float> @test_vld1q_f32( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[A]], align 4 -// CHECK-NEXT: ret <4 x float> [[TMP0]] -// -float32x4_t test_vld1q_f32(float32_t const *a) { - return vld1q_f32(a); -} - -// CHECK-LABEL: define dso_local <2 x double> @test_vld1q_f64( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr [[A]], align 8 -// CHECK-NEXT: ret <2 x double> [[TMP0]] -// -float64x2_t test_vld1q_f64(float64_t const *a) { - return vld1q_f64(a); -} - -// CHECK-LABEL: define dso_local <16 x i8> @test_vld1q_mf8( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[A]], align 1 -// CHECK-NEXT: ret <16 x i8> [[TMP0]] -// -mfloat8x16_t test_vld1q_mf8(mfloat8_t const *a) { - return vld1q_mf8(a); -} - -// CHECK-LABEL: define dso_local <16 x i8> @test_vld1q_p8( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr [[A]], align 1 -// CHECK-NEXT: ret <16 x i8> [[TMP0]] -// -poly8x16_t test_vld1q_p8(poly8_t const *a) { - return vld1q_p8(a); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vld1q_p16( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, ptr [[A]], align 2 -// CHECK-NEXT: ret <8 x i16> [[TMP0]] -// -poly16x8_t test_vld1q_p16(poly16_t const *a) { - return vld1q_p16(a); -} - -// CHECK-LABEL: define dso_local <8 x i8> @test_vld1_u8( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <8 x i8>, ptr [[A]], align 1 -// CHECK-NEXT: ret <8 x i8> [[TMP0]] -// -uint8x8_t test_vld1_u8(uint8_t const *a) { - return vld1_u8(a); -} - -// CHECK-LABEL: define dso_local <4 x i16> @test_vld1_u16( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <4 x i16>, ptr [[A]], align 2 -// CHECK-NEXT: ret <4 x i16> [[TMP0]] -// -uint16x4_t test_vld1_u16(uint16_t const *a) { - return vld1_u16(a); -} - -// CHECK-LABEL: define dso_local <2 x i32> @test_vld1_u32( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <2 x i32>, ptr [[A]], align 4 -// CHECK-NEXT: ret <2 x i32> [[TMP0]] -// -uint32x2_t test_vld1_u32(uint32_t const *a) { - return vld1_u32(a); -} - -// CHECK-LABEL: define dso_local <1 x i64> @test_vld1_u64( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <1 x i64>, ptr [[A]], align 8 -// CHECK-NEXT: ret <1 x i64> [[TMP0]] -// -uint64x1_t test_vld1_u64(uint64_t const *a) { - return vld1_u64(a); -} - -// CHECK-LABEL: define dso_local <8 x i8> @test_vld1_s8( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <8 x i8>, ptr [[A]], align 1 -// CHECK-NEXT: ret <8 x i8> [[TMP0]] -// -int8x8_t test_vld1_s8(int8_t const *a) { - return vld1_s8(a); -} - -// CHECK-LABEL: define dso_local <4 x i16> @test_vld1_s16( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <4 x i16>, ptr [[A]], align 2 -// CHECK-NEXT: ret <4 x i16> [[TMP0]] -// -int16x4_t test_vld1_s16(int16_t const *a) { - return vld1_s16(a); -} - -// CHECK-LABEL: define dso_local <2 x i32> @test_vld1_s32( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <2 x i32>, ptr [[A]], align 4 -// CHECK-NEXT: ret <2 x i32> [[TMP0]] -// -int32x2_t test_vld1_s32(int32_t const *a) { - return vld1_s32(a); -} - -// CHECK-LABEL: define dso_local <1 x i64> @test_vld1_s64( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <1 x i64>, ptr [[A]], align 8 -// CHECK-NEXT: ret <1 x i64> [[TMP0]] -// -int64x1_t test_vld1_s64(int64_t const *a) { - return vld1_s64(a); -} - -// CHECK-LABEL: define dso_local <4 x half> @test_vld1_f16( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <4 x half>, ptr [[A]], align 2 -// CHECK-NEXT: ret <4 x half> [[TMP0]] -// -float16x4_t test_vld1_f16(float16_t const *a) { - return vld1_f16(a); -} - -// CHECK-LABEL: define dso_local <2 x float> @test_vld1_f32( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <2 x float>, ptr [[A]], align 4 -// CHECK-NEXT: ret <2 x float> [[TMP0]] -// -float32x2_t test_vld1_f32(float32_t const *a) { - return vld1_f32(a); -} - -// CHECK-LABEL: define dso_local <1 x double> @test_vld1_f64( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <1 x double>, ptr [[A]], align 8 -// CHECK-NEXT: ret <1 x double> [[TMP0]] -// -float64x1_t test_vld1_f64(float64_t const *a) { - return vld1_f64(a); -} - -// CHECK-LABEL: define dso_local <8 x i8> @test_vld1_mf8( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <8 x i8>, ptr [[A]], align 1 -// CHECK-NEXT: ret <8 x i8> [[TMP0]] -// -mfloat8x8_t test_vld1_mf8(mfloat8_t const *a) { - return vld1_mf8(a); -} - -// CHECK-LABEL: define dso_local <8 x i8> @test_vld1_p8( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <8 x i8>, ptr [[A]], align 1 -// CHECK-NEXT: ret <8 x i8> [[TMP0]] -// -poly8x8_t test_vld1_p8(poly8_t const *a) { - return vld1_p8(a); -} - -// CHECK-LABEL: define dso_local <4 x i16> @test_vld1_p16( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <4 x i16>, ptr [[A]], align 2 -// CHECK-NEXT: ret <4 x i16> [[TMP0]] -// -poly16x4_t test_vld1_p16(poly16_t const *a) { - return vld1_p16(a); -} - -// CHECK-LABEL: define dso_local <8 x i8> @test_vld1_u8_void( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <8 x i8>, ptr [[A]], align 1 -// CHECK-NEXT: ret <8 x i8> [[TMP0]] -// -uint8x8_t test_vld1_u8_void(void *a) { - return vld1_u8(a); -} - -// CHECK-LABEL: define dso_local <4 x i16> @test_vld1_u16_void( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <4 x i16>, ptr [[A]], align 1 -// CHECK-NEXT: ret <4 x i16> [[TMP0]] -// -uint16x4_t test_vld1_u16_void(void *a) { - return vld1_u16(a); -} - -// CHECK-LABEL: define dso_local <2 x i32> @test_vld1_u32_void( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <2 x i32>, ptr [[A]], align 1 -// CHECK-NEXT: ret <2 x i32> [[TMP0]] -// -uint32x2_t test_vld1_u32_void(void *a) { - return vld1_u32(a); -} - -// CHECK-LABEL: define dso_local <1 x i64> @test_vld1_u64_void( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <1 x i64>, ptr [[A]], align 1 -// CHECK-NEXT: ret <1 x i64> [[TMP0]] -// -uint64x1_t test_vld1_u64_void(void *a) { - return vld1_u64(a); -} - -// CHECK-LABEL: define dso_local <8 x i8> @test_vld1_s8_void( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <8 x i8>, ptr [[A]], align 1 -// CHECK-NEXT: ret <8 x i8> [[TMP0]] -// -int8x8_t test_vld1_s8_void(void *a) { - return vld1_s8(a); -} - -// CHECK-LABEL: define dso_local <4 x i16> @test_vld1_s16_void( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <4 x i16>, ptr [[A]], align 1 -// CHECK-NEXT: ret <4 x i16> [[TMP0]] -// -int16x4_t test_vld1_s16_void(void *a) { - return vld1_s16(a); -} - -// CHECK-LABEL: define dso_local <2 x i32> @test_vld1_s32_void( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <2 x i32>, ptr [[A]], align 1 -// CHECK-NEXT: ret <2 x i32> [[TMP0]] -// -int32x2_t test_vld1_s32_void(void *a) { - return vld1_s32(a); -} - -// CHECK-LABEL: define dso_local <1 x i64> @test_vld1_s64_void( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <1 x i64>, ptr [[A]], align 1 -// CHECK-NEXT: ret <1 x i64> [[TMP0]] -// -int64x1_t test_vld1_s64_void(void *a) { - return vld1_s64(a); -} - -// CHECK-LABEL: define dso_local <4 x half> @test_vld1_f16_void( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <4 x half>, ptr [[A]], align 1 -// CHECK-NEXT: ret <4 x half> [[TMP0]] -// -float16x4_t test_vld1_f16_void(void *a) { - return vld1_f16(a); -} - -// CHECK-LABEL: define dso_local <2 x float> @test_vld1_f32_void( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <2 x float>, ptr [[A]], align 1 -// CHECK-NEXT: ret <2 x float> [[TMP0]] -// -float32x2_t test_vld1_f32_void(void *a) { - return vld1_f32(a); -} - -// CHECK-LABEL: define dso_local <1 x double> @test_vld1_f64_void( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <1 x double>, ptr [[A]], align 1 -// CHECK-NEXT: ret <1 x double> [[TMP0]] -// -float64x1_t test_vld1_f64_void(void *a) { - return vld1_f64(a); -} - -// CHECK-LABEL: define dso_local <8 x i8> @test_vld1_p8_void( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <8 x i8>, ptr [[A]], align 1 -// CHECK-NEXT: ret <8 x i8> [[TMP0]] -// -poly8x8_t test_vld1_p8_void(void *a) { - return vld1_p8(a); -} - -// CHECK-LABEL: define dso_local <4 x i16> @test_vld1_p16_void( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <4 x i16>, ptr [[A]], align 1 -// CHECK-NEXT: ret <4 x i16> [[TMP0]] -// -poly16x4_t test_vld1_p16_void(void *a) { - return vld1_p16(a); -} - // CHECK-LABEL: define dso_local %struct.uint8x16x2_t @test_vld2q_u8( // CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] @@ -7142,294 +6732,6 @@ poly16x4x4_t test_vld4_p16(poly16_t const *a) { return vld4_p16(a); } -// CHECK-LABEL: define dso_local %struct.float64x2x2_t @test_vld1q_f64_x2( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VLD1XN:%.*]] = call { <2 x double>, <2 x double> } @llvm.aarch64.neon.ld1x2.v2f64.p0(ptr [[A]]) -// CHECK-NEXT: [[VLD1XN_FCA_0_EXTRACT:%.*]] = extractvalue { <2 x double>, <2 x double> } [[VLD1XN]], 0 -// CHECK-NEXT: [[VLD1XN_FCA_1_EXTRACT:%.*]] = extractvalue { <2 x double>, <2 x double> } [[VLD1XN]], 1 -// CHECK-NEXT: [[DOTFCA_0_0_INSERT:%.*]] = insertvalue [[STRUCT_FLOAT64X2X2_T:%.*]] poison, <2 x double> [[VLD1XN_FCA_0_EXTRACT]], 0, 0 -// CHECK-NEXT: [[DOTFCA_0_1_INSERT:%.*]] = insertvalue [[STRUCT_FLOAT64X2X2_T]] [[DOTFCA_0_0_INSERT]], <2 x double> [[VLD1XN_FCA_1_EXTRACT]], 0, 1 -// CHECK-NEXT: ret [[STRUCT_FLOAT64X2X2_T]] [[DOTFCA_0_1_INSERT]] -// -float64x2x2_t test_vld1q_f64_x2(float64_t const *a) { - return vld1q_f64_x2(a); -} - -// CHECK-LABEL: define dso_local %struct.mfloat8x16x2_t @test_vld1q_mf8_x2( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld1x2.v16i8.p0(ptr [[A]]) -// CHECK-NEXT: [[VLD1XN_FCA_0_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[VLD1XN]], 0 -// CHECK-NEXT: [[VLD1XN_FCA_1_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[VLD1XN]], 1 -// CHECK-NEXT: [[DOTFCA_0_0_INSERT:%.*]] = insertvalue [[STRUCT_MFLOAT8X16X2_T:%.*]] poison, <16 x i8> [[VLD1XN_FCA_0_EXTRACT]], 0, 0 -// CHECK-NEXT: [[DOTFCA_0_1_INSERT:%.*]] = insertvalue [[STRUCT_MFLOAT8X16X2_T]] [[DOTFCA_0_0_INSERT]], <16 x i8> [[VLD1XN_FCA_1_EXTRACT]], 0, 1 -// CHECK-NEXT: ret [[STRUCT_MFLOAT8X16X2_T]] [[DOTFCA_0_1_INSERT]] -// -mfloat8x16x2_t test_vld1q_mf8_x2(mfloat8_t const *a) { - return vld1q_mf8_x2(a); -} - -// CHECK-LABEL: define dso_local %struct.poly64x2x2_t @test_vld1q_p64_x2( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld1x2.v2i64.p0(ptr [[A]]) -// CHECK-NEXT: [[VLD1XN_FCA_0_EXTRACT:%.*]] = extractvalue { <2 x i64>, <2 x i64> } [[VLD1XN]], 0 -// CHECK-NEXT: [[VLD1XN_FCA_1_EXTRACT:%.*]] = extractvalue { <2 x i64>, <2 x i64> } [[VLD1XN]], 1 -// CHECK-NEXT: [[DOTFCA_0_0_INSERT:%.*]] = insertvalue [[STRUCT_POLY64X2X2_T:%.*]] poison, <2 x i64> [[VLD1XN_FCA_0_EXTRACT]], 0, 0 -// CHECK-NEXT: [[DOTFCA_0_1_INSERT:%.*]] = insertvalue [[STRUCT_POLY64X2X2_T]] [[DOTFCA_0_0_INSERT]], <2 x i64> [[VLD1XN_FCA_1_EXTRACT]], 0, 1 -// CHECK-NEXT: ret [[STRUCT_POLY64X2X2_T]] [[DOTFCA_0_1_INSERT]] -// -poly64x2x2_t test_vld1q_p64_x2(poly64_t const *a) { - return vld1q_p64_x2(a); -} - -// CHECK-LABEL: define dso_local %struct.float64x1x2_t @test_vld1_f64_x2( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VLD1XN:%.*]] = call { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld1x2.v1f64.p0(ptr [[A]]) -// CHECK-NEXT: [[VLD1XN_FCA_0_EXTRACT:%.*]] = extractvalue { <1 x double>, <1 x double> } [[VLD1XN]], 0 -// CHECK-NEXT: [[VLD1XN_FCA_1_EXTRACT:%.*]] = extractvalue { <1 x double>, <1 x double> } [[VLD1XN]], 1 -// CHECK-NEXT: [[DOTFCA_0_0_INSERT:%.*]] = insertvalue [[STRUCT_FLOAT64X1X2_T:%.*]] poison, <1 x double> [[VLD1XN_FCA_0_EXTRACT]], 0, 0 -// CHECK-NEXT: [[DOTFCA_0_1_INSERT:%.*]] = insertvalue [[STRUCT_FLOAT64X1X2_T]] [[DOTFCA_0_0_INSERT]], <1 x double> [[VLD1XN_FCA_1_EXTRACT]], 0, 1 -// CHECK-NEXT: ret [[STRUCT_FLOAT64X1X2_T]] [[DOTFCA_0_1_INSERT]] -// -float64x1x2_t test_vld1_f64_x2(float64_t const *a) { - return vld1_f64_x2(a); -} - -// CHECK-LABEL: define dso_local %struct.mfloat8x8x2_t @test_vld1_mf8_x2( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld1x2.v8i8.p0(ptr [[A]]) -// CHECK-NEXT: [[VLD1XN_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8> } [[VLD1XN]], 0 -// CHECK-NEXT: [[VLD1XN_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8> } [[VLD1XN]], 1 -// CHECK-NEXT: [[DOTFCA_0_0_INSERT:%.*]] = insertvalue [[STRUCT_MFLOAT8X8X2_T:%.*]] poison, <8 x i8> [[VLD1XN_FCA_0_EXTRACT]], 0, 0 -// CHECK-NEXT: [[DOTFCA_0_1_INSERT:%.*]] = insertvalue [[STRUCT_MFLOAT8X8X2_T]] [[DOTFCA_0_0_INSERT]], <8 x i8> [[VLD1XN_FCA_1_EXTRACT]], 0, 1 -// CHECK-NEXT: ret [[STRUCT_MFLOAT8X8X2_T]] [[DOTFCA_0_1_INSERT]] -// -mfloat8x8x2_t test_vld1_mf8_x2(mfloat8_t const *a) { - return vld1_mf8_x2(a); -} - -// CHECK-LABEL: define dso_local %struct.poly64x1x2_t @test_vld1_p64_x2( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld1x2.v1i64.p0(ptr [[A]]) -// CHECK-NEXT: [[VLD1XN_FCA_0_EXTRACT:%.*]] = extractvalue { <1 x i64>, <1 x i64> } [[VLD1XN]], 0 -// CHECK-NEXT: [[VLD1XN_FCA_1_EXTRACT:%.*]] = extractvalue { <1 x i64>, <1 x i64> } [[VLD1XN]], 1 -// CHECK-NEXT: [[DOTFCA_0_0_INSERT:%.*]] = insertvalue [[STRUCT_POLY64X1X2_T:%.*]] poison, <1 x i64> [[VLD1XN_FCA_0_EXTRACT]], 0, 0 -// CHECK-NEXT: [[DOTFCA_0_1_INSERT:%.*]] = insertvalue [[STRUCT_POLY64X1X2_T]] [[DOTFCA_0_0_INSERT]], <1 x i64> [[VLD1XN_FCA_1_EXTRACT]], 0, 1 -// CHECK-NEXT: ret [[STRUCT_POLY64X1X2_T]] [[DOTFCA_0_1_INSERT]] -// -poly64x1x2_t test_vld1_p64_x2(poly64_t const *a) { - return vld1_p64_x2(a); -} - -// CHECK-LABEL: define dso_local %struct.float64x2x3_t @test_vld1q_f64_x3( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VLD1XN:%.*]] = call { <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld1x3.v2f64.p0(ptr [[A]]) -// CHECK-NEXT: [[VLD1XN_FCA_0_EXTRACT:%.*]] = extractvalue { <2 x double>, <2 x double>, <2 x double> } [[VLD1XN]], 0 -// CHECK-NEXT: [[VLD1XN_FCA_1_EXTRACT:%.*]] = extractvalue { <2 x double>, <2 x double>, <2 x double> } [[VLD1XN]], 1 -// CHECK-NEXT: [[VLD1XN_FCA_2_EXTRACT:%.*]] = extractvalue { <2 x double>, <2 x double>, <2 x double> } [[VLD1XN]], 2 -// CHECK-NEXT: [[DOTFCA_0_0_INSERT:%.*]] = insertvalue [[STRUCT_FLOAT64X2X3_T:%.*]] poison, <2 x double> [[VLD1XN_FCA_0_EXTRACT]], 0, 0 -// CHECK-NEXT: [[DOTFCA_0_1_INSERT:%.*]] = insertvalue [[STRUCT_FLOAT64X2X3_T]] [[DOTFCA_0_0_INSERT]], <2 x double> [[VLD1XN_FCA_1_EXTRACT]], 0, 1 -// CHECK-NEXT: [[DOTFCA_0_2_INSERT:%.*]] = insertvalue [[STRUCT_FLOAT64X2X3_T]] [[DOTFCA_0_1_INSERT]], <2 x double> [[VLD1XN_FCA_2_EXTRACT]], 0, 2 -// CHECK-NEXT: ret [[STRUCT_FLOAT64X2X3_T]] [[DOTFCA_0_2_INSERT]] -// -float64x2x3_t test_vld1q_f64_x3(float64_t const *a) { - return vld1q_f64_x3(a); -} - -// CHECK-LABEL: define dso_local %struct.mfloat8x16x3_t @test_vld1q_mf8_x3( -// CHECK-SAME: ptr noundef [[PTR:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld1x3.v16i8.p0(ptr [[PTR]]) -// CHECK-NEXT: [[VLD1XN_FCA_0_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], 0 -// CHECK-NEXT: [[VLD1XN_FCA_1_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], 1 -// CHECK-NEXT: [[VLD1XN_FCA_2_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], 2 -// CHECK-NEXT: [[DOTFCA_0_0_INSERT:%.*]] = insertvalue [[STRUCT_MFLOAT8X16X3_T:%.*]] poison, <16 x i8> [[VLD1XN_FCA_0_EXTRACT]], 0, 0 -// CHECK-NEXT: [[DOTFCA_0_1_INSERT:%.*]] = insertvalue [[STRUCT_MFLOAT8X16X3_T]] [[DOTFCA_0_0_INSERT]], <16 x i8> [[VLD1XN_FCA_1_EXTRACT]], 0, 1 -// CHECK-NEXT: [[DOTFCA_0_2_INSERT:%.*]] = insertvalue [[STRUCT_MFLOAT8X16X3_T]] [[DOTFCA_0_1_INSERT]], <16 x i8> [[VLD1XN_FCA_2_EXTRACT]], 0, 2 -// CHECK-NEXT: ret [[STRUCT_MFLOAT8X16X3_T]] [[DOTFCA_0_2_INSERT]] -// -mfloat8x16x3_t test_vld1q_mf8_x3(mfloat8_t const *ptr) { - return vld1q_mf8_x3(ptr); -} - -// CHECK-LABEL: define dso_local %struct.poly64x2x3_t @test_vld1q_p64_x3( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld1x3.v2i64.p0(ptr [[A]]) -// CHECK-NEXT: [[VLD1XN_FCA_0_EXTRACT:%.*]] = extractvalue { <2 x i64>, <2 x i64>, <2 x i64> } [[VLD1XN]], 0 -// CHECK-NEXT: [[VLD1XN_FCA_1_EXTRACT:%.*]] = extractvalue { <2 x i64>, <2 x i64>, <2 x i64> } [[VLD1XN]], 1 -// CHECK-NEXT: [[VLD1XN_FCA_2_EXTRACT:%.*]] = extractvalue { <2 x i64>, <2 x i64>, <2 x i64> } [[VLD1XN]], 2 -// CHECK-NEXT: [[DOTFCA_0_0_INSERT:%.*]] = insertvalue [[STRUCT_POLY64X2X3_T:%.*]] poison, <2 x i64> [[VLD1XN_FCA_0_EXTRACT]], 0, 0 -// CHECK-NEXT: [[DOTFCA_0_1_INSERT:%.*]] = insertvalue [[STRUCT_POLY64X2X3_T]] [[DOTFCA_0_0_INSERT]], <2 x i64> [[VLD1XN_FCA_1_EXTRACT]], 0, 1 -// CHECK-NEXT: [[DOTFCA_0_2_INSERT:%.*]] = insertvalue [[STRUCT_POLY64X2X3_T]] [[DOTFCA_0_1_INSERT]], <2 x i64> [[VLD1XN_FCA_2_EXTRACT]], 0, 2 -// CHECK-NEXT: ret [[STRUCT_POLY64X2X3_T]] [[DOTFCA_0_2_INSERT]] -// -poly64x2x3_t test_vld1q_p64_x3(poly64_t const *a) { - return vld1q_p64_x3(a); -} - -// CHECK-LABEL: define dso_local %struct.float64x1x3_t @test_vld1_f64_x3( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VLD1XN:%.*]] = call { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld1x3.v1f64.p0(ptr [[A]]) -// CHECK-NEXT: [[VLD1XN_FCA_0_EXTRACT:%.*]] = extractvalue { <1 x double>, <1 x double>, <1 x double> } [[VLD1XN]], 0 -// CHECK-NEXT: [[VLD1XN_FCA_1_EXTRACT:%.*]] = extractvalue { <1 x double>, <1 x double>, <1 x double> } [[VLD1XN]], 1 -// CHECK-NEXT: [[VLD1XN_FCA_2_EXTRACT:%.*]] = extractvalue { <1 x double>, <1 x double>, <1 x double> } [[VLD1XN]], 2 -// CHECK-NEXT: [[DOTFCA_0_0_INSERT:%.*]] = insertvalue [[STRUCT_FLOAT64X1X3_T:%.*]] poison, <1 x double> [[VLD1XN_FCA_0_EXTRACT]], 0, 0 -// CHECK-NEXT: [[DOTFCA_0_1_INSERT:%.*]] = insertvalue [[STRUCT_FLOAT64X1X3_T]] [[DOTFCA_0_0_INSERT]], <1 x double> [[VLD1XN_FCA_1_EXTRACT]], 0, 1 -// CHECK-NEXT: [[DOTFCA_0_2_INSERT:%.*]] = insertvalue [[STRUCT_FLOAT64X1X3_T]] [[DOTFCA_0_1_INSERT]], <1 x double> [[VLD1XN_FCA_2_EXTRACT]], 0, 2 -// CHECK-NEXT: ret [[STRUCT_FLOAT64X1X3_T]] [[DOTFCA_0_2_INSERT]] -// -float64x1x3_t test_vld1_f64_x3(float64_t const *a) { - return vld1_f64_x3(a); -} - -// CHECK-LABEL: define dso_local %struct.mfloat8x8x3_t @test_vld1_mf8_x3( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld1x3.v8i8.p0(ptr [[A]]) -// CHECK-NEXT: [[VLD1XN_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], 0 -// CHECK-NEXT: [[VLD1XN_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], 1 -// CHECK-NEXT: [[VLD1XN_FCA_2_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], 2 -// CHECK-NEXT: [[DOTFCA_0_0_INSERT:%.*]] = insertvalue [[STRUCT_MFLOAT8X8X3_T:%.*]] poison, <8 x i8> [[VLD1XN_FCA_0_EXTRACT]], 0, 0 -// CHECK-NEXT: [[DOTFCA_0_1_INSERT:%.*]] = insertvalue [[STRUCT_MFLOAT8X8X3_T]] [[DOTFCA_0_0_INSERT]], <8 x i8> [[VLD1XN_FCA_1_EXTRACT]], 0, 1 -// CHECK-NEXT: [[DOTFCA_0_2_INSERT:%.*]] = insertvalue [[STRUCT_MFLOAT8X8X3_T]] [[DOTFCA_0_1_INSERT]], <8 x i8> [[VLD1XN_FCA_2_EXTRACT]], 0, 2 -// CHECK-NEXT: ret [[STRUCT_MFLOAT8X8X3_T]] [[DOTFCA_0_2_INSERT]] -// -mfloat8x8x3_t test_vld1_mf8_x3(mfloat8_t const *a) { - return vld1_mf8_x3(a); -} - -// CHECK-LABEL: define dso_local %struct.poly64x1x3_t @test_vld1_p64_x3( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld1x3.v1i64.p0(ptr [[A]]) -// CHECK-NEXT: [[VLD1XN_FCA_0_EXTRACT:%.*]] = extractvalue { <1 x i64>, <1 x i64>, <1 x i64> } [[VLD1XN]], 0 -// CHECK-NEXT: [[VLD1XN_FCA_1_EXTRACT:%.*]] = extractvalue { <1 x i64>, <1 x i64>, <1 x i64> } [[VLD1XN]], 1 -// CHECK-NEXT: [[VLD1XN_FCA_2_EXTRACT:%.*]] = extractvalue { <1 x i64>, <1 x i64>, <1 x i64> } [[VLD1XN]], 2 -// CHECK-NEXT: [[DOTFCA_0_0_INSERT:%.*]] = insertvalue [[STRUCT_POLY64X1X3_T:%.*]] poison, <1 x i64> [[VLD1XN_FCA_0_EXTRACT]], 0, 0 -// CHECK-NEXT: [[DOTFCA_0_1_INSERT:%.*]] = insertvalue [[STRUCT_POLY64X1X3_T]] [[DOTFCA_0_0_INSERT]], <1 x i64> [[VLD1XN_FCA_1_EXTRACT]], 0, 1 -// CHECK-NEXT: [[DOTFCA_0_2_INSERT:%.*]] = insertvalue [[STRUCT_POLY64X1X3_T]] [[DOTFCA_0_1_INSERT]], <1 x i64> [[VLD1XN_FCA_2_EXTRACT]], 0, 2 -// CHECK-NEXT: ret [[STRUCT_POLY64X1X3_T]] [[DOTFCA_0_2_INSERT]] -// -poly64x1x3_t test_vld1_p64_x3(poly64_t const *a) { - return vld1_p64_x3(a); -} - -// CHECK-LABEL: define dso_local %struct.float64x2x4_t @test_vld1q_f64_x4( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VLD1XN:%.*]] = call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld1x4.v2f64.p0(ptr [[A]]) -// CHECK-NEXT: [[VLD1XN_FCA_0_EXTRACT:%.*]] = extractvalue { <2 x double>, <2 x double>, <2 x double>, <2 x double> } [[VLD1XN]], 0 -// CHECK-NEXT: [[VLD1XN_FCA_1_EXTRACT:%.*]] = extractvalue { <2 x double>, <2 x double>, <2 x double>, <2 x double> } [[VLD1XN]], 1 -// CHECK-NEXT: [[VLD1XN_FCA_2_EXTRACT:%.*]] = extractvalue { <2 x double>, <2 x double>, <2 x double>, <2 x double> } [[VLD1XN]], 2 -// CHECK-NEXT: [[VLD1XN_FCA_3_EXTRACT:%.*]] = extractvalue { <2 x double>, <2 x double>, <2 x double>, <2 x double> } [[VLD1XN]], 3 -// CHECK-NEXT: [[DOTFCA_0_0_INSERT:%.*]] = insertvalue [[STRUCT_FLOAT64X2X4_T:%.*]] poison, <2 x double> [[VLD1XN_FCA_0_EXTRACT]], 0, 0 -// CHECK-NEXT: [[DOTFCA_0_1_INSERT:%.*]] = insertvalue [[STRUCT_FLOAT64X2X4_T]] [[DOTFCA_0_0_INSERT]], <2 x double> [[VLD1XN_FCA_1_EXTRACT]], 0, 1 -// CHECK-NEXT: [[DOTFCA_0_2_INSERT:%.*]] = insertvalue [[STRUCT_FLOAT64X2X4_T]] [[DOTFCA_0_1_INSERT]], <2 x double> [[VLD1XN_FCA_2_EXTRACT]], 0, 2 -// CHECK-NEXT: [[DOTFCA_0_3_INSERT:%.*]] = insertvalue [[STRUCT_FLOAT64X2X4_T]] [[DOTFCA_0_2_INSERT]], <2 x double> [[VLD1XN_FCA_3_EXTRACT]], 0, 3 -// CHECK-NEXT: ret [[STRUCT_FLOAT64X2X4_T]] [[DOTFCA_0_3_INSERT]] -// -float64x2x4_t test_vld1q_f64_x4(float64_t const *a) { - return vld1q_f64_x4(a); -} - -// CHECK-LABEL: define dso_local %struct.mfloat8x16x4_t @test_vld1q_mf8_x4( -// CHECK-SAME: ptr noundef [[PTR:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld1x4.v16i8.p0(ptr [[PTR]]) -// CHECK-NEXT: [[VLD1XN_FCA_0_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], 0 -// CHECK-NEXT: [[VLD1XN_FCA_1_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], 1 -// CHECK-NEXT: [[VLD1XN_FCA_2_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], 2 -// CHECK-NEXT: [[VLD1XN_FCA_3_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], 3 -// CHECK-NEXT: [[DOTFCA_0_0_INSERT:%.*]] = insertvalue [[STRUCT_MFLOAT8X16X4_T:%.*]] poison, <16 x i8> [[VLD1XN_FCA_0_EXTRACT]], 0, 0 -// CHECK-NEXT: [[DOTFCA_0_1_INSERT:%.*]] = insertvalue [[STRUCT_MFLOAT8X16X4_T]] [[DOTFCA_0_0_INSERT]], <16 x i8> [[VLD1XN_FCA_1_EXTRACT]], 0, 1 -// CHECK-NEXT: [[DOTFCA_0_2_INSERT:%.*]] = insertvalue [[STRUCT_MFLOAT8X16X4_T]] [[DOTFCA_0_1_INSERT]], <16 x i8> [[VLD1XN_FCA_2_EXTRACT]], 0, 2 -// CHECK-NEXT: [[DOTFCA_0_3_INSERT:%.*]] = insertvalue [[STRUCT_MFLOAT8X16X4_T]] [[DOTFCA_0_2_INSERT]], <16 x i8> [[VLD1XN_FCA_3_EXTRACT]], 0, 3 -// CHECK-NEXT: ret [[STRUCT_MFLOAT8X16X4_T]] [[DOTFCA_0_3_INSERT]] -// -mfloat8x16x4_t test_vld1q_mf8_x4(mfloat8_t const *ptr) { - return vld1q_mf8_x4(ptr); -} - -// CHECK-LABEL: define dso_local %struct.poly64x2x4_t @test_vld1q_p64_x4( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld1x4.v2i64.p0(ptr [[A]]) -// CHECK-NEXT: [[VLD1XN_FCA_0_EXTRACT:%.*]] = extractvalue { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[VLD1XN]], 0 -// CHECK-NEXT: [[VLD1XN_FCA_1_EXTRACT:%.*]] = extractvalue { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[VLD1XN]], 1 -// CHECK-NEXT: [[VLD1XN_FCA_2_EXTRACT:%.*]] = extractvalue { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[VLD1XN]], 2 -// CHECK-NEXT: [[VLD1XN_FCA_3_EXTRACT:%.*]] = extractvalue { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[VLD1XN]], 3 -// CHECK-NEXT: [[DOTFCA_0_0_INSERT:%.*]] = insertvalue [[STRUCT_POLY64X2X4_T:%.*]] poison, <2 x i64> [[VLD1XN_FCA_0_EXTRACT]], 0, 0 -// CHECK-NEXT: [[DOTFCA_0_1_INSERT:%.*]] = insertvalue [[STRUCT_POLY64X2X4_T]] [[DOTFCA_0_0_INSERT]], <2 x i64> [[VLD1XN_FCA_1_EXTRACT]], 0, 1 -// CHECK-NEXT: [[DOTFCA_0_2_INSERT:%.*]] = insertvalue [[STRUCT_POLY64X2X4_T]] [[DOTFCA_0_1_INSERT]], <2 x i64> [[VLD1XN_FCA_2_EXTRACT]], 0, 2 -// CHECK-NEXT: [[DOTFCA_0_3_INSERT:%.*]] = insertvalue [[STRUCT_POLY64X2X4_T]] [[DOTFCA_0_2_INSERT]], <2 x i64> [[VLD1XN_FCA_3_EXTRACT]], 0, 3 -// CHECK-NEXT: ret [[STRUCT_POLY64X2X4_T]] [[DOTFCA_0_3_INSERT]] -// -poly64x2x4_t test_vld1q_p64_x4(poly64_t const *a) { - return vld1q_p64_x4(a); -} - -// CHECK-LABEL: define dso_local %struct.float64x1x4_t @test_vld1_f64_x4( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VLD1XN:%.*]] = call { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld1x4.v1f64.p0(ptr [[A]]) -// CHECK-NEXT: [[VLD1XN_FCA_0_EXTRACT:%.*]] = extractvalue { <1 x double>, <1 x double>, <1 x double>, <1 x double> } [[VLD1XN]], 0 -// CHECK-NEXT: [[VLD1XN_FCA_1_EXTRACT:%.*]] = extractvalue { <1 x double>, <1 x double>, <1 x double>, <1 x double> } [[VLD1XN]], 1 -// CHECK-NEXT: [[VLD1XN_FCA_2_EXTRACT:%.*]] = extractvalue { <1 x double>, <1 x double>, <1 x double>, <1 x double> } [[VLD1XN]], 2 -// CHECK-NEXT: [[VLD1XN_FCA_3_EXTRACT:%.*]] = extractvalue { <1 x double>, <1 x double>, <1 x double>, <1 x double> } [[VLD1XN]], 3 -// CHECK-NEXT: [[DOTFCA_0_0_INSERT:%.*]] = insertvalue [[STRUCT_FLOAT64X1X4_T:%.*]] poison, <1 x double> [[VLD1XN_FCA_0_EXTRACT]], 0, 0 -// CHECK-NEXT: [[DOTFCA_0_1_INSERT:%.*]] = insertvalue [[STRUCT_FLOAT64X1X4_T]] [[DOTFCA_0_0_INSERT]], <1 x double> [[VLD1XN_FCA_1_EXTRACT]], 0, 1 -// CHECK-NEXT: [[DOTFCA_0_2_INSERT:%.*]] = insertvalue [[STRUCT_FLOAT64X1X4_T]] [[DOTFCA_0_1_INSERT]], <1 x double> [[VLD1XN_FCA_2_EXTRACT]], 0, 2 -// CHECK-NEXT: [[DOTFCA_0_3_INSERT:%.*]] = insertvalue [[STRUCT_FLOAT64X1X4_T]] [[DOTFCA_0_2_INSERT]], <1 x double> [[VLD1XN_FCA_3_EXTRACT]], 0, 3 -// CHECK-NEXT: ret [[STRUCT_FLOAT64X1X4_T]] [[DOTFCA_0_3_INSERT]] -// -float64x1x4_t test_vld1_f64_x4(float64_t const *a) { - return vld1_f64_x4(a); -} - -// CHECK-LABEL: define dso_local %struct.mfloat8x8x4_t @test_vld1_mf8_x4( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld1x4.v8i8.p0(ptr [[A]]) -// CHECK-NEXT: [[VLD1XN_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], 0 -// CHECK-NEXT: [[VLD1XN_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], 1 -// CHECK-NEXT: [[VLD1XN_FCA_2_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], 2 -// CHECK-NEXT: [[VLD1XN_FCA_3_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], 3 -// CHECK-NEXT: [[DOTFCA_0_0_INSERT:%.*]] = insertvalue [[STRUCT_MFLOAT8X8X4_T:%.*]] poison, <8 x i8> [[VLD1XN_FCA_0_EXTRACT]], 0, 0 -// CHECK-NEXT: [[DOTFCA_0_1_INSERT:%.*]] = insertvalue [[STRUCT_MFLOAT8X8X4_T]] [[DOTFCA_0_0_INSERT]], <8 x i8> [[VLD1XN_FCA_1_EXTRACT]], 0, 1 -// CHECK-NEXT: [[DOTFCA_0_2_INSERT:%.*]] = insertvalue [[STRUCT_MFLOAT8X8X4_T]] [[DOTFCA_0_1_INSERT]], <8 x i8> [[VLD1XN_FCA_2_EXTRACT]], 0, 2 -// CHECK-NEXT: [[DOTFCA_0_3_INSERT:%.*]] = insertvalue [[STRUCT_MFLOAT8X8X4_T]] [[DOTFCA_0_2_INSERT]], <8 x i8> [[VLD1XN_FCA_3_EXTRACT]], 0, 3 -// CHECK-NEXT: ret [[STRUCT_MFLOAT8X8X4_T]] [[DOTFCA_0_3_INSERT]] -// -mfloat8x8x4_t test_vld1_mf8_x4(mfloat8_t const *a) { - return vld1_mf8_x4(a); -} - -// CHECK-LABEL: define dso_local %struct.poly64x1x4_t @test_vld1_p64_x4( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld1x4.v1i64.p0(ptr [[A]]) -// CHECK-NEXT: [[VLD1XN_FCA_0_EXTRACT:%.*]] = extractvalue { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } [[VLD1XN]], 0 -// CHECK-NEXT: [[VLD1XN_FCA_1_EXTRACT:%.*]] = extractvalue { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } [[VLD1XN]], 1 -// CHECK-NEXT: [[VLD1XN_FCA_2_EXTRACT:%.*]] = extractvalue { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } [[VLD1XN]], 2 -// CHECK-NEXT: [[VLD1XN_FCA_3_EXTRACT:%.*]] = extractvalue { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } [[VLD1XN]], 3 -// CHECK-NEXT: [[DOTFCA_0_0_INSERT:%.*]] = insertvalue [[STRUCT_POLY64X1X4_T:%.*]] poison, <1 x i64> [[VLD1XN_FCA_0_EXTRACT]], 0, 0 -// CHECK-NEXT: [[DOTFCA_0_1_INSERT:%.*]] = insertvalue [[STRUCT_POLY64X1X4_T]] [[DOTFCA_0_0_INSERT]], <1 x i64> [[VLD1XN_FCA_1_EXTRACT]], 0, 1 -// CHECK-NEXT: [[DOTFCA_0_2_INSERT:%.*]] = insertvalue [[STRUCT_POLY64X1X4_T]] [[DOTFCA_0_1_INSERT]], <1 x i64> [[VLD1XN_FCA_2_EXTRACT]], 0, 2 -// CHECK-NEXT: [[DOTFCA_0_3_INSERT:%.*]] = insertvalue [[STRUCT_POLY64X1X4_T]] [[DOTFCA_0_2_INSERT]], <1 x i64> [[VLD1XN_FCA_3_EXTRACT]], 0, 3 -// CHECK-NEXT: ret [[STRUCT_POLY64X1X4_T]] [[DOTFCA_0_3_INSERT]] -// -poly64x1x4_t test_vld1_p64_x4(poly64_t const *a) { - return vld1_p64_x4(a); -} - // CHECK-LABEL: define dso_local i64 @test_vceqd_s64( // CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] diff --git a/clang/test/CodeGen/AArch64/neon-ldst-one.c b/clang/test/CodeGen/AArch64/neon-ldst-one.c index 39821630db859..bc06e33c78fc0 100644 --- a/clang/test/CodeGen/AArch64/neon-ldst-one.c +++ b/clang/test/CodeGen/AArch64/neon-ldst-one.c @@ -7,368 +7,8 @@ #include -// CHECK-LABEL: define dso_local <16 x i8> @test_vld1q_dup_u8( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <16 x i8> poison, i8 [[TMP0]], i32 0 -// CHECK-NEXT: [[LANE:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> [[TMP1]], <16 x i32> zeroinitializer -// CHECK-NEXT: ret <16 x i8> [[LANE]] -// -uint8x16_t test_vld1q_dup_u8(uint8_t *a) { - return vld1q_dup_u8(a); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vld1q_dup_u16( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A]], align 2 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i16> poison, i16 [[TMP0]], i32 0 -// CHECK-NEXT: [[LANE:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> [[TMP1]], <8 x i32> zeroinitializer -// CHECK-NEXT: ret <8 x i16> [[LANE]] -// -uint16x8_t test_vld1q_dup_u16(uint16_t *a) { - return vld1q_dup_u16(a); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vld1q_dup_u32( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i32 0 -// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> [[TMP1]], <4 x i32> zeroinitializer -// CHECK-NEXT: ret <4 x i32> [[LANE]] -// -uint32x4_t test_vld1q_dup_u32(uint32_t *a) { - return vld1q_dup_u32(a); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vld1q_dup_u64( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A]], align 8 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> poison, i64 [[TMP0]], i32 0 -// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> [[TMP1]], <2 x i32> zeroinitializer -// CHECK-NEXT: ret <2 x i64> [[LANE]] -// -uint64x2_t test_vld1q_dup_u64(uint64_t *a) { - return vld1q_dup_u64(a); -} - -// CHECK-LABEL: define dso_local <16 x i8> @test_vld1q_dup_s8( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <16 x i8> poison, i8 [[TMP0]], i32 0 -// CHECK-NEXT: [[LANE:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> [[TMP1]], <16 x i32> zeroinitializer -// CHECK-NEXT: ret <16 x i8> [[LANE]] -// -int8x16_t test_vld1q_dup_s8(int8_t *a) { - return vld1q_dup_s8(a); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vld1q_dup_s16( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A]], align 2 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i16> poison, i16 [[TMP0]], i32 0 -// CHECK-NEXT: [[LANE:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> [[TMP1]], <8 x i32> zeroinitializer -// CHECK-NEXT: ret <8 x i16> [[LANE]] -// -int16x8_t test_vld1q_dup_s16(int16_t *a) { - return vld1q_dup_s16(a); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vld1q_dup_s32( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i32 0 -// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> [[TMP1]], <4 x i32> zeroinitializer -// CHECK-NEXT: ret <4 x i32> [[LANE]] -// -int32x4_t test_vld1q_dup_s32(int32_t *a) { - return vld1q_dup_s32(a); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vld1q_dup_s64( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A]], align 8 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> poison, i64 [[TMP0]], i32 0 -// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> [[TMP1]], <2 x i32> zeroinitializer -// CHECK-NEXT: ret <2 x i64> [[LANE]] -// -int64x2_t test_vld1q_dup_s64(int64_t *a) { - return vld1q_dup_s64(a); -} - -// CHECK-LABEL: define dso_local <8 x half> @test_vld1q_dup_f16( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[A]], align 2 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x half> poison, half [[TMP0]], i32 0 -// CHECK-NEXT: [[LANE:%.*]] = shufflevector <8 x half> [[TMP1]], <8 x half> [[TMP1]], <8 x i32> zeroinitializer -// CHECK-NEXT: ret <8 x half> [[LANE]] -// -float16x8_t test_vld1q_dup_f16(float16_t *a) { - return vld1q_dup_f16(a); -} - -// CHECK-LABEL: define dso_local <4 x float> @test_vld1q_dup_f32( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[A]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> poison, float [[TMP0]], i32 0 -// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> [[TMP1]], <4 x i32> zeroinitializer -// CHECK-NEXT: ret <4 x float> [[LANE]] -// -float32x4_t test_vld1q_dup_f32(float32_t *a) { - return vld1q_dup_f32(a); -} - -// CHECK-LABEL: define dso_local <2 x double> @test_vld1q_dup_f64( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load double, ptr [[A]], align 8 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> poison, double [[TMP0]], i32 0 -// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> [[TMP1]], <2 x i32> zeroinitializer -// CHECK-NEXT: ret <2 x double> [[LANE]] -// -float64x2_t test_vld1q_dup_f64(float64_t *a) { - return vld1q_dup_f64(a); -} - -// CHECK-LABEL: define dso_local <16 x i8> @test_vld1q_dup_mf8( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <16 x i8> poison, i8 [[TMP0]], i32 0 -// CHECK-NEXT: [[LANE:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> [[TMP1]], <16 x i32> zeroinitializer -// CHECK-NEXT: ret <16 x i8> [[LANE]] -// -mfloat8x16_t test_vld1q_dup_mf8(mfloat8_t *a) { - return vld1q_dup_mf8(a); -} - -// CHECK-LABEL: define dso_local <16 x i8> @test_vld1q_dup_p8( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <16 x i8> poison, i8 [[TMP0]], i32 0 -// CHECK-NEXT: [[LANE:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> [[TMP1]], <16 x i32> zeroinitializer -// CHECK-NEXT: ret <16 x i8> [[LANE]] -// -poly8x16_t test_vld1q_dup_p8(poly8_t *a) { - return vld1q_dup_p8(a); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vld1q_dup_p16( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A]], align 2 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i16> poison, i16 [[TMP0]], i32 0 -// CHECK-NEXT: [[LANE:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> [[TMP1]], <8 x i32> zeroinitializer -// CHECK-NEXT: ret <8 x i16> [[LANE]] -// -poly16x8_t test_vld1q_dup_p16(poly16_t *a) { - return vld1q_dup_p16(a); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vld1q_dup_p64( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A]], align 8 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> poison, i64 [[TMP0]], i32 0 -// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> [[TMP1]], <2 x i32> zeroinitializer -// CHECK-NEXT: ret <2 x i64> [[LANE]] -// -poly64x2_t test_vld1q_dup_p64(poly64_t *a) { - return vld1q_dup_p64(a); -} - -// CHECK-LABEL: define dso_local <8 x i8> @test_vld1_dup_u8( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i8> poison, i8 [[TMP0]], i32 0 -// CHECK-NEXT: [[LANE:%.*]] = shufflevector <8 x i8> [[TMP1]], <8 x i8> [[TMP1]], <8 x i32> zeroinitializer -// CHECK-NEXT: ret <8 x i8> [[LANE]] -// -uint8x8_t test_vld1_dup_u8(uint8_t *a) { - return vld1_dup_u8(a); -} - -// CHECK-LABEL: define dso_local <4 x i16> @test_vld1_dup_u16( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A]], align 2 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[TMP0]], i32 0 -// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> [[TMP1]], <4 x i32> zeroinitializer -// CHECK-NEXT: ret <4 x i16> [[LANE]] -// -uint16x4_t test_vld1_dup_u16(uint16_t *a) { - return vld1_dup_u16(a); -} - -// CHECK-LABEL: define dso_local <2 x i32> @test_vld1_dup_u32( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[TMP0]], i32 0 -// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP1]], <2 x i32> zeroinitializer -// CHECK-NEXT: ret <2 x i32> [[LANE]] -// -uint32x2_t test_vld1_dup_u32(uint32_t *a) { - return vld1_dup_u32(a); -} - -// CHECK-LABEL: define dso_local <1 x i64> @test_vld1_dup_u64( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A]], align 8 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <1 x i64> poison, i64 [[TMP0]], i32 0 -// CHECK-NEXT: [[LANE:%.*]] = shufflevector <1 x i64> [[TMP1]], <1 x i64> [[TMP1]], <1 x i32> zeroinitializer -// CHECK-NEXT: ret <1 x i64> [[LANE]] -// -uint64x1_t test_vld1_dup_u64(uint64_t *a) { - return vld1_dup_u64(a); -} - -// CHECK-LABEL: define dso_local <8 x i8> @test_vld1_dup_s8( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i8> poison, i8 [[TMP0]], i32 0 -// CHECK-NEXT: [[LANE:%.*]] = shufflevector <8 x i8> [[TMP1]], <8 x i8> [[TMP1]], <8 x i32> zeroinitializer -// CHECK-NEXT: ret <8 x i8> [[LANE]] -// -int8x8_t test_vld1_dup_s8(int8_t *a) { - return vld1_dup_s8(a); -} - -// CHECK-LABEL: define dso_local <4 x i16> @test_vld1_dup_s16( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A]], align 2 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[TMP0]], i32 0 -// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> [[TMP1]], <4 x i32> zeroinitializer -// CHECK-NEXT: ret <4 x i16> [[LANE]] -// -int16x4_t test_vld1_dup_s16(int16_t *a) { - return vld1_dup_s16(a); -} - -// CHECK-LABEL: define dso_local <2 x i32> @test_vld1_dup_s32( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[TMP0]], i32 0 -// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> [[TMP1]], <2 x i32> zeroinitializer -// CHECK-NEXT: ret <2 x i32> [[LANE]] -// -int32x2_t test_vld1_dup_s32(int32_t *a) { - return vld1_dup_s32(a); -} - -// CHECK-LABEL: define dso_local <1 x i64> @test_vld1_dup_s64( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A]], align 8 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <1 x i64> poison, i64 [[TMP0]], i32 0 -// CHECK-NEXT: [[LANE:%.*]] = shufflevector <1 x i64> [[TMP1]], <1 x i64> [[TMP1]], <1 x i32> zeroinitializer -// CHECK-NEXT: ret <1 x i64> [[LANE]] -// -int64x1_t test_vld1_dup_s64(int64_t *a) { - return vld1_dup_s64(a); -} - -// CHECK-LABEL: define dso_local <4 x half> @test_vld1_dup_f16( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[A]], align 2 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x half> poison, half [[TMP0]], i32 0 -// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x half> [[TMP1]], <4 x half> [[TMP1]], <4 x i32> zeroinitializer -// CHECK-NEXT: ret <4 x half> [[LANE]] -// -float16x4_t test_vld1_dup_f16(float16_t *a) { - return vld1_dup_f16(a); -} - -// CHECK-LABEL: define dso_local <2 x float> @test_vld1_dup_f32( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[A]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> poison, float [[TMP0]], i32 0 -// CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> [[TMP1]], <2 x i32> zeroinitializer -// CHECK-NEXT: ret <2 x float> [[LANE]] -// -float32x2_t test_vld1_dup_f32(float32_t *a) { - return vld1_dup_f32(a); -} - -// CHECK-LABEL: define dso_local <1 x double> @test_vld1_dup_f64( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load double, ptr [[A]], align 8 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <1 x double> poison, double [[TMP0]], i32 0 -// CHECK-NEXT: [[LANE:%.*]] = shufflevector <1 x double> [[TMP1]], <1 x double> [[TMP1]], <1 x i32> zeroinitializer -// CHECK-NEXT: ret <1 x double> [[LANE]] -// -float64x1_t test_vld1_dup_f64(float64_t *a) { - return vld1_dup_f64(a); -} - -// CHECK-LABEL: define dso_local <8 x i8> @test_vld1_dup_mf8( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i8> poison, i8 [[TMP0]], i32 0 -// CHECK-NEXT: [[LANE:%.*]] = shufflevector <8 x i8> [[TMP1]], <8 x i8> [[TMP1]], <8 x i32> zeroinitializer -// CHECK-NEXT: ret <8 x i8> [[LANE]] -// -mfloat8x8_t test_vld1_dup_mf8(mfloat8_t *a) { - return vld1_dup_mf8(a); -} - -// CHECK-LABEL: define dso_local <8 x i8> @test_vld1_dup_p8( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i8> poison, i8 [[TMP0]], i32 0 -// CHECK-NEXT: [[LANE:%.*]] = shufflevector <8 x i8> [[TMP1]], <8 x i8> [[TMP1]], <8 x i32> zeroinitializer -// CHECK-NEXT: ret <8 x i8> [[LANE]] -// -poly8x8_t test_vld1_dup_p8(poly8_t *a) { - return vld1_dup_p8(a); -} - -// CHECK-LABEL: define dso_local <4 x i16> @test_vld1_dup_p16( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A]], align 2 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[TMP0]], i32 0 -// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> [[TMP1]], <4 x i32> zeroinitializer -// CHECK-NEXT: ret <4 x i16> [[LANE]] -// -poly16x4_t test_vld1_dup_p16(poly16_t *a) { - return vld1_dup_p16(a); -} - -// CHECK-LABEL: define dso_local <1 x i64> @test_vld1_dup_p64( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A]], align 8 -// CHECK-NEXT: [[TMP1:%.*]] = insertelement <1 x i64> poison, i64 [[TMP0]], i32 0 -// CHECK-NEXT: [[LANE:%.*]] = shufflevector <1 x i64> [[TMP1]], <1 x i64> [[TMP1]], <1 x i32> zeroinitializer -// CHECK-NEXT: ret <1 x i64> [[LANE]] -// -poly64x1_t test_vld1_dup_p64(poly64_t *a) { - return vld1_dup_p64(a); -} - // CHECK-LABEL: define dso_local %struct.uint64x2x2_t @test_vld2q_dup_u64( -// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[VLD2:%.*]] = call { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld2r.v2i64.p0(ptr [[A]]) // CHECK-NEXT: [[VLD2_FCA_0_EXTRACT:%.*]] = extractvalue { <2 x i64>, <2 x i64> } [[VLD2]], 0 @@ -757,387 +397,6 @@ poly64x1x4_t test_vld4_dup_p64(poly64_t *a) { return vld4_dup_p64(a); } -// CHECK-LABEL: define dso_local <16 x i8> @test_vld1q_lane_u8( -// CHECK-SAME: ptr noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 -// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <16 x i8> [[B]], i8 [[TMP0]], i32 15 -// CHECK-NEXT: ret <16 x i8> [[VLD1_LANE]] -// -uint8x16_t test_vld1q_lane_u8(uint8_t *a, uint8x16_t b) { - return vld1q_lane_u8(a, b, 15); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vld1q_lane_u16( -// CHECK-SAME: ptr noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> -// CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[A]], align 2 -// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <8 x i16> [[TMP1]], i16 [[TMP2]], i32 7 -// CHECK-NEXT: ret <8 x i16> [[VLD1_LANE]] -// -uint16x8_t test_vld1q_lane_u16(uint16_t *a, uint16x8_t b) { - return vld1q_lane_u16(a, b, 7); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vld1q_lane_u32( -// CHECK-SAME: ptr noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> -// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 -// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[TMP2]], i32 3 -// CHECK-NEXT: ret <4 x i32> [[VLD1_LANE]] -// -uint32x4_t test_vld1q_lane_u32(uint32_t *a, uint32x4_t b) { - return vld1q_lane_u32(a, b, 3); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vld1q_lane_u64( -// CHECK-SAME: ptr noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> -// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[A]], align 8 -// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <2 x i64> [[TMP1]], i64 [[TMP2]], i32 1 -// CHECK-NEXT: ret <2 x i64> [[VLD1_LANE]] -// -uint64x2_t test_vld1q_lane_u64(uint64_t *a, uint64x2_t b) { - return vld1q_lane_u64(a, b, 1); -} - -// CHECK-LABEL: define dso_local <16 x i8> @test_vld1q_lane_s8( -// CHECK-SAME: ptr noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 -// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <16 x i8> [[B]], i8 [[TMP0]], i32 15 -// CHECK-NEXT: ret <16 x i8> [[VLD1_LANE]] -// -int8x16_t test_vld1q_lane_s8(int8_t *a, int8x16_t b) { - return vld1q_lane_s8(a, b, 15); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vld1q_lane_s16( -// CHECK-SAME: ptr noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> -// CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[A]], align 2 -// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <8 x i16> [[TMP1]], i16 [[TMP2]], i32 7 -// CHECK-NEXT: ret <8 x i16> [[VLD1_LANE]] -// -int16x8_t test_vld1q_lane_s16(int16_t *a, int16x8_t b) { - return vld1q_lane_s16(a, b, 7); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vld1q_lane_s32( -// CHECK-SAME: ptr noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> -// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 -// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[TMP2]], i32 3 -// CHECK-NEXT: ret <4 x i32> [[VLD1_LANE]] -// -int32x4_t test_vld1q_lane_s32(int32_t *a, int32x4_t b) { - return vld1q_lane_s32(a, b, 3); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vld1q_lane_s64( -// CHECK-SAME: ptr noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> -// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[A]], align 8 -// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <2 x i64> [[TMP1]], i64 [[TMP2]], i32 1 -// CHECK-NEXT: ret <2 x i64> [[VLD1_LANE]] -// -int64x2_t test_vld1q_lane_s64(int64_t *a, int64x2_t b) { - return vld1q_lane_s64(a, b, 1); -} - -// CHECK-LABEL: define dso_local <8 x half> @test_vld1q_lane_f16( -// CHECK-SAME: ptr noundef [[A:%.*]], <8 x half> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[B]] to <8 x i16> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half> -// CHECK-NEXT: [[TMP3:%.*]] = load half, ptr [[A]], align 2 -// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <8 x half> [[TMP2]], half [[TMP3]], i32 7 -// CHECK-NEXT: ret <8 x half> [[VLD1_LANE]] -// -float16x8_t test_vld1q_lane_f16(float16_t *a, float16x8_t b) { - return vld1q_lane_f16(a, b, 7); -} - -// CHECK-LABEL: define dso_local <4 x float> @test_vld1q_lane_f32( -// CHECK-SAME: ptr noundef [[A:%.*]], <4 x float> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[B]] to <4 x i32> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float> -// CHECK-NEXT: [[TMP3:%.*]] = load float, ptr [[A]], align 4 -// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <4 x float> [[TMP2]], float [[TMP3]], i32 3 -// CHECK-NEXT: ret <4 x float> [[VLD1_LANE]] -// -float32x4_t test_vld1q_lane_f32(float32_t *a, float32x4_t b) { - return vld1q_lane_f32(a, b, 3); -} - -// CHECK-LABEL: define dso_local <2 x double> @test_vld1q_lane_f64( -// CHECK-SAME: ptr noundef [[A:%.*]], <2 x double> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x double> [[B]] to <2 x i64> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <16 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double> -// CHECK-NEXT: [[TMP3:%.*]] = load double, ptr [[A]], align 8 -// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <2 x double> [[TMP2]], double [[TMP3]], i32 1 -// CHECK-NEXT: ret <2 x double> [[VLD1_LANE]] -// -float64x2_t test_vld1q_lane_f64(float64_t *a, float64x2_t b) { - return vld1q_lane_f64(a, b, 1); -} - -// CHECK-LABEL: define dso_local <16 x i8> @test_vld1q_lane_mf8( -// CHECK-SAME: ptr noundef [[A:%.*]], <16 x i8> [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 -// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <16 x i8> [[B]], i8 [[TMP0]], i32 15 -// CHECK-NEXT: ret <16 x i8> [[VLD1_LANE]] -// -mfloat8x16_t test_vld1q_lane_mf8(mfloat8_t *a, mfloat8x16_t b) { - return vld1q_lane_mf8(a, b, 15); -} - -// CHECK-LABEL: define dso_local <16 x i8> @test_vld1q_lane_p8( -// CHECK-SAME: ptr noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 -// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <16 x i8> [[B]], i8 [[TMP0]], i32 15 -// CHECK-NEXT: ret <16 x i8> [[VLD1_LANE]] -// -poly8x16_t test_vld1q_lane_p8(poly8_t *a, poly8x16_t b) { - return vld1q_lane_p8(a, b, 15); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vld1q_lane_p16( -// CHECK-SAME: ptr noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> -// CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[A]], align 2 -// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <8 x i16> [[TMP1]], i16 [[TMP2]], i32 7 -// CHECK-NEXT: ret <8 x i16> [[VLD1_LANE]] -// -poly16x8_t test_vld1q_lane_p16(poly16_t *a, poly16x8_t b) { - return vld1q_lane_p16(a, b, 7); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vld1q_lane_p64( -// CHECK-SAME: ptr noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> -// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[A]], align 8 -// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <2 x i64> [[TMP1]], i64 [[TMP2]], i32 1 -// CHECK-NEXT: ret <2 x i64> [[VLD1_LANE]] -// -poly64x2_t test_vld1q_lane_p64(poly64_t *a, poly64x2_t b) { - return vld1q_lane_p64(a, b, 1); -} - -// CHECK-LABEL: define dso_local <8 x i8> @test_vld1_lane_u8( -// CHECK-SAME: ptr noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 -// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <8 x i8> [[B]], i8 [[TMP0]], i32 7 -// CHECK-NEXT: ret <8 x i8> [[VLD1_LANE]] -// -uint8x8_t test_vld1_lane_u8(uint8_t *a, uint8x8_t b) { - return vld1_lane_u8(a, b, 7); -} - -// CHECK-LABEL: define dso_local <4 x i16> @test_vld1_lane_u16( -// CHECK-SAME: ptr noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[A]], align 2 -// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <4 x i16> [[TMP1]], i16 [[TMP2]], i32 3 -// CHECK-NEXT: ret <4 x i16> [[VLD1_LANE]] -// -uint16x4_t test_vld1_lane_u16(uint16_t *a, uint16x4_t b) { - return vld1_lane_u16(a, b, 3); -} - -// CHECK-LABEL: define dso_local <2 x i32> @test_vld1_lane_u32( -// CHECK-SAME: ptr noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> -// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 -// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[TMP2]], i32 1 -// CHECK-NEXT: ret <2 x i32> [[VLD1_LANE]] -// -uint32x2_t test_vld1_lane_u32(uint32_t *a, uint32x2_t b) { - return vld1_lane_u32(a, b, 1); -} - -// CHECK-LABEL: define dso_local <1 x i64> @test_vld1_lane_u64( -// CHECK-SAME: ptr noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> -// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[A]], align 8 -// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <1 x i64> [[TMP1]], i64 [[TMP2]], i32 0 -// CHECK-NEXT: ret <1 x i64> [[VLD1_LANE]] -// -uint64x1_t test_vld1_lane_u64(uint64_t *a, uint64x1_t b) { - return vld1_lane_u64(a, b, 0); -} - -// CHECK-LABEL: define dso_local <8 x i8> @test_vld1_lane_s8( -// CHECK-SAME: ptr noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 -// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <8 x i8> [[B]], i8 [[TMP0]], i32 7 -// CHECK-NEXT: ret <8 x i8> [[VLD1_LANE]] -// -int8x8_t test_vld1_lane_s8(int8_t *a, int8x8_t b) { - return vld1_lane_s8(a, b, 7); -} - -// CHECK-LABEL: define dso_local <4 x i16> @test_vld1_lane_s16( -// CHECK-SAME: ptr noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[A]], align 2 -// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <4 x i16> [[TMP1]], i16 [[TMP2]], i32 3 -// CHECK-NEXT: ret <4 x i16> [[VLD1_LANE]] -// -int16x4_t test_vld1_lane_s16(int16_t *a, int16x4_t b) { - return vld1_lane_s16(a, b, 3); -} - -// CHECK-LABEL: define dso_local <2 x i32> @test_vld1_lane_s32( -// CHECK-SAME: ptr noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> -// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 -// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[TMP2]], i32 1 -// CHECK-NEXT: ret <2 x i32> [[VLD1_LANE]] -// -int32x2_t test_vld1_lane_s32(int32_t *a, int32x2_t b) { - return vld1_lane_s32(a, b, 1); -} - -// CHECK-LABEL: define dso_local <1 x i64> @test_vld1_lane_s64( -// CHECK-SAME: ptr noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> -// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[A]], align 8 -// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <1 x i64> [[TMP1]], i64 [[TMP2]], i32 0 -// CHECK-NEXT: ret <1 x i64> [[VLD1_LANE]] -// -int64x1_t test_vld1_lane_s64(int64_t *a, int64x1_t b) { - return vld1_lane_s64(a, b, 0); -} - -// CHECK-LABEL: define dso_local <4 x half> @test_vld1_lane_f16( -// CHECK-SAME: ptr noundef [[A:%.*]], <4 x half> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[B]] to <4 x i16> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half> -// CHECK-NEXT: [[TMP3:%.*]] = load half, ptr [[A]], align 2 -// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <4 x half> [[TMP2]], half [[TMP3]], i32 3 -// CHECK-NEXT: ret <4 x half> [[VLD1_LANE]] -// -float16x4_t test_vld1_lane_f16(float16_t *a, float16x4_t b) { - return vld1_lane_f16(a, b, 3); -} - -// CHECK-LABEL: define dso_local <2 x float> @test_vld1_lane_f32( -// CHECK-SAME: ptr noundef [[A:%.*]], <2 x float> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[B]] to <2 x i32> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float> -// CHECK-NEXT: [[TMP3:%.*]] = load float, ptr [[A]], align 4 -// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <2 x float> [[TMP2]], float [[TMP3]], i32 1 -// CHECK-NEXT: ret <2 x float> [[VLD1_LANE]] -// -float32x2_t test_vld1_lane_f32(float32_t *a, float32x2_t b) { - return vld1_lane_f32(a, b, 1); -} - -// CHECK-LABEL: define dso_local <1 x double> @test_vld1_lane_f64( -// CHECK-SAME: ptr noundef [[A:%.*]], <1 x double> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x double> [[B]] to i64 -// CHECK-NEXT: [[__S1_SROA_0_0_VEC_INSERT:%.*]] = insertelement <1 x i64> undef, i64 [[TMP0]], i64 0 -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[__S1_SROA_0_0_VEC_INSERT]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x double> -// CHECK-NEXT: [[TMP3:%.*]] = load double, ptr [[A]], align 8 -// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <1 x double> [[TMP2]], double [[TMP3]], i32 0 -// CHECK-NEXT: ret <1 x double> [[VLD1_LANE]] -// -float64x1_t test_vld1_lane_f64(float64_t *a, float64x1_t b) { - return vld1_lane_f64(a, b, 0); -} - -// CHECK-LABEL: define dso_local <8 x i8> @test_vld1_lane_mf8( -// CHECK-SAME: ptr noundef [[A:%.*]], <8 x i8> [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 -// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <8 x i8> [[B]], i8 [[TMP0]], i32 7 -// CHECK-NEXT: ret <8 x i8> [[VLD1_LANE]] -// -mfloat8x8_t test_vld1_lane_mf8(mfloat8_t *a, mfloat8x8_t b) { - return vld1_lane_mf8(a, b, 7); -} - -// CHECK-LABEL: define dso_local <8 x i8> @test_vld1_lane_p8( -// CHECK-SAME: ptr noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 -// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <8 x i8> [[B]], i8 [[TMP0]], i32 7 -// CHECK-NEXT: ret <8 x i8> [[VLD1_LANE]] -// -poly8x8_t test_vld1_lane_p8(poly8_t *a, poly8x8_t b) { - return vld1_lane_p8(a, b, 7); -} - -// CHECK-LABEL: define dso_local <4 x i16> @test_vld1_lane_p16( -// CHECK-SAME: ptr noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[A]], align 2 -// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <4 x i16> [[TMP1]], i16 [[TMP2]], i32 3 -// CHECK-NEXT: ret <4 x i16> [[VLD1_LANE]] -// -poly16x4_t test_vld1_lane_p16(poly16_t *a, poly16x4_t b) { - return vld1_lane_p16(a, b, 3); -} - -// CHECK-LABEL: define dso_local <1 x i64> @test_vld1_lane_p64( -// CHECK-SAME: ptr noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> -// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[A]], align 8 -// CHECK-NEXT: [[VLD1_LANE:%.*]] = insertelement <1 x i64> [[TMP1]], i64 [[TMP2]], i32 0 -// CHECK-NEXT: ret <1 x i64> [[VLD1_LANE]] -// -poly64x1_t test_vld1_lane_p64(poly64_t *a, poly64x1_t b) { - return vld1_lane_p64(a, b, 0); -} - // CHECK-LABEL: define dso_local %struct.int8x16x2_t @test_vld2q_lane_s8( // CHECK-SAME: ptr noundef [[PTR:%.*]], [2 x <16 x i8>] alignstack(16) [[SRC_COERCE:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] @@ -2011,7 +1270,6 @@ mfloat8x16x3_t test_vld3q_lane_mf8(mfloat8_t *a, mfloat8x16x3_t b) { return vld3q_lane_mf8(a, b, 15); } - // CHECK-LABEL: define dso_local %struct.poly8x16x3_t @test_vld3q_lane_p8( // CHECK-SAME: ptr noundef [[A:%.*]], [3 x <16 x i8>] alignstack(16) [[B_COERCE:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] diff --git a/clang/test/CodeGen/AArch64/neon/load.c b/clang/test/CodeGen/AArch64/neon/load.c new file mode 100644 index 0000000000000..d733590322a3b --- /dev/null +++ b/clang/test/CodeGen/AArch64/neon/load.c @@ -0,0 +1,2240 @@ +// REQUIRES: aarch64-registered-target || arm-registered-target + +// RUN: %clang_cc1_cg_arm64_neon -emit-llvm %s -disable-O0-optnone | opt -S -passes=sroa,instcombine | FileCheck %s --check-prefixes=ALL,LLVM +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_neon -fclangir -emit-llvm %s -disable-O0-optnone | opt -S -passes=sroa,instcombine | FileCheck %s --check-prefixes=ALL,LLVM %} +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_neon -fclangir -emit-cir %s -disable-O0-optnone | FileCheck %s --check-prefixes=ALL,CIR %} + +#include + +//===------------------------------------------------------===// +// 2.1.10.1. Stride +// https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#stride +//===------------------------------------------------------===// + +// ALL-LABEL: @test_vld1q_f16( +float16x8_t test_vld1q_f16(float16_t const *a) { +// CIR: cir.load align(2) {{.*}} : !cir.ptr>, !cir.vector<8 x !cir.f16> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <8 x half>, ptr [[A]], align 2 +// LLVM: ret <8 x half> [[TMP0]] + return vld1q_f16(a); +} + +// ALL-LABEL: @test_vld1q_f32( +float32x4_t test_vld1q_f32(float32_t const *a) { +// CIR: cir.load align(4) {{.*}} : !cir.ptr>, !cir.vector<4 x !cir.float> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <4 x float>, ptr [[A]], align 4 +// LLVM: ret <4 x float> [[TMP0]] + return vld1q_f32(a); +} + +// ALL-LABEL: @test_vld1q_f64( +float64x2_t test_vld1q_f64(float64_t const *a) { +// CIR: cir.load align(8) {{.*}} : !cir.ptr>, !cir.vector<2 x !cir.double> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <2 x double>, ptr [[A]], align 8 +// LLVM: ret <2 x double> [[TMP0]] + return vld1q_f64(a); +} + +// ALL-LABEL: @test_vld1q_mf8( +mfloat8x16_t test_vld1q_mf8(mfloat8_t const *a) { +// CIR: cir.load align(1) {{.*}} : !cir.ptr>, !cir.vector<16 x !u8i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <16 x i8>, ptr [[A]], align 1 +// LLVM: ret <16 x i8> [[TMP0]] + return vld1q_mf8(a); +} + +// ALL-LABEL: @test_vld1q_p16( +poly16x8_t test_vld1q_p16(poly16_t const *a) { +// CIR: cir.load align(2) {{.*}} : !cir.ptr>, !cir.vector<8 x !s16i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <8 x i16>, ptr [[A]], align 2 +// LLVM: ret <8 x i16> [[TMP0]] + return vld1q_p16(a); +} + +// ALL-LABEL: @test_vld1q_p64( +poly64x2_t test_vld1q_p64(poly64_t const * ptr) { +// CIR: cir.load align(8) {{.*}} : !cir.ptr>, !cir.vector<2 x !s64i> + +// LLVM-SAME: ptr {{.*}} [[PTR:%.*]]) +// LLVM: [[TMP0:%.*]] = load <2 x i64>, ptr [[PTR]], align 8 +// LLVM: ret <2 x i64> [[TMP0]] + return vld1q_p64(ptr); +} + +// ALL-LABEL: @test_vld1q_p8( +poly8x16_t test_vld1q_p8(poly8_t const *a) { +// CIR: cir.load align(1) {{.*}} : !cir.ptr>, !cir.vector<16 x !s8i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <16 x i8>, ptr [[A]], align 1 +// LLVM: ret <16 x i8> [[TMP0]] + return vld1q_p8(a); +} + +// ALL-LABEL: @test_vld1q_s16( +int16x8_t test_vld1q_s16(int16_t const *a) { +// CIR: cir.load align(2) {{.*}} : !cir.ptr>, !cir.vector<8 x !s16i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <8 x i16>, ptr [[A]], align 2 +// LLVM: ret <8 x i16> [[TMP0]] + return vld1q_s16(a); +} + +// ALL-LABEL: @test_vld1q_s32( +int32x4_t test_vld1q_s32(int32_t const *a) { +// CIR: cir.load align(4) {{.*}} : !cir.ptr>, !cir.vector<4 x !s32i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <4 x i32>, ptr [[A]], align 4 +// LLVM: ret <4 x i32> [[TMP0]] + return vld1q_s32(a); +} + +// ALL-LABEL: @test_vld1q_s64( +int64x2_t test_vld1q_s64(int64_t const *a) { +// CIR: cir.load align(8) {{.*}} : !cir.ptr>, !cir.vector<2 x !s64i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <2 x i64>, ptr [[A]], align 8 +// LLVM: ret <2 x i64> [[TMP0]] + return vld1q_s64(a); +} + +// ALL-LABEL: @test_vld1q_s8( +int8x16_t test_vld1q_s8(int8_t const *a) { +// CIR: cir.load align(1) {{.*}} : !cir.ptr>, !cir.vector<16 x !s8i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <16 x i8>, ptr [[A]], align 1 +// LLVM: ret <16 x i8> [[TMP0]] + return vld1q_s8(a); +} + +// ALL-LABEL: @test_vld1q_u16( +uint16x8_t test_vld1q_u16(uint16_t const *a) { +// CIR: cir.load align(2) {{.*}} : !cir.ptr>, !cir.vector<8 x !u16i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <8 x i16>, ptr [[A]], align 2 +// LLVM: ret <8 x i16> [[TMP0]] + return vld1q_u16(a); +} + +// ALL-LABEL: @test_vld1q_u32( +uint32x4_t test_vld1q_u32(uint32_t const *a) { +// CIR: cir.load align(4) {{.*}} : !cir.ptr>, !cir.vector<4 x !u32i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <4 x i32>, ptr [[A]], align 4 +// LLVM: ret <4 x i32> [[TMP0]] + return vld1q_u32(a); +} + +// ALL-LABEL: @test_vld1q_u64( +uint64x2_t test_vld1q_u64(uint64_t const *a) { +// CIR: cir.load align(8) {{.*}} : !cir.ptr>, !cir.vector<2 x !u64i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <2 x i64>, ptr [[A]], align 8 +// LLVM: ret <2 x i64> [[TMP0]] + return vld1q_u64(a); +} + +// ALL-LABEL: @test_vld1q_u8( +uint8x16_t test_vld1q_u8(uint8_t const *a) { +// CIR: cir.load align(1) {{.*}} : !cir.ptr>, !cir.vector<16 x !u8i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <16 x i8>, ptr [[A]], align 1 +// LLVM: ret <16 x i8> [[TMP0]] + return vld1q_u8(a); +} + +// ALL-LABEL: @test_vld1_f16( +float16x4_t test_vld1_f16(float16_t const *a) { +// CIR: cir.load align(2) {{.*}} : !cir.ptr>, !cir.vector<4 x !cir.f16> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <4 x half>, ptr [[A]], align 2 +// LLVM: ret <4 x half> [[TMP0]] + return vld1_f16(a); +} + +// ALL-LABEL: @test_vld1_f32( +float32x2_t test_vld1_f32(float32_t const *a) { +// CIR: cir.load align(4) {{.*}} : !cir.ptr>, !cir.vector<2 x !cir.float> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <2 x float>, ptr [[A]], align 4 +// LLVM: ret <2 x float> [[TMP0]] + return vld1_f32(a); +} + +// ALL-LABEL: @test_vld1_f64( +float64x1_t test_vld1_f64(float64_t const *a) { +// CIR: cir.load align(8) {{.*}} : !cir.ptr>, !cir.vector<1 x !cir.double> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <1 x double>, ptr [[A]], align 8 +// LLVM: ret <1 x double> [[TMP0]] + return vld1_f64(a); +} + +// ALL-LABEL: @test_vld1_mf8( +mfloat8x8_t test_vld1_mf8(mfloat8_t const *a) { +// CIR: cir.load align(1) {{.*}} : !cir.ptr>, !cir.vector<8 x !u8i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <8 x i8>, ptr [[A]], align 1 +// LLVM: ret <8 x i8> [[TMP0]] + return vld1_mf8(a); +} + +// ALL-LABEL: @test_vld1_p16( +poly16x4_t test_vld1_p16(poly16_t const *a) { +// CIR: cir.load align(2) {{.*}} : !cir.ptr>, !cir.vector<4 x !s16i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <4 x i16>, ptr [[A]], align 2 +// LLVM: ret <4 x i16> [[TMP0]] + return vld1_p16(a); +} + +// ALL-LABEL: @test_vld1_p64( +poly64x1_t test_vld1_p64(poly64_t const * ptr) { +// CIR: cir.load align(8) {{.*}} : !cir.ptr>, !cir.vector<1 x !s64i> + +// LLVM-SAME: ptr {{.*}} [[PTR:%.*]]) +// LLVM: [[TMP0:%.*]] = load <1 x i64>, ptr [[PTR]], align 8 +// LLVM: ret <1 x i64> [[TMP0]] + return vld1_p64(ptr); +} + +// ALL-LABEL: @test_vld1_p8( +poly8x8_t test_vld1_p8(poly8_t const *a) { +// CIR: cir.load align(1) {{.*}} : !cir.ptr>, !cir.vector<8 x !s8i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <8 x i8>, ptr [[A]], align 1 +// LLVM: ret <8 x i8> [[TMP0]] + return vld1_p8(a); +} + +// ALL-LABEL: @test_vld1_s16( +int16x4_t test_vld1_s16(int16_t const *a) { +// CIR: cir.load align(2) {{.*}} : !cir.ptr>, !cir.vector<4 x !s16i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <4 x i16>, ptr [[A]], align 2 +// LLVM: ret <4 x i16> [[TMP0]] + return vld1_s16(a); +} + +// ALL-LABEL: @test_vld1_s32( +int32x2_t test_vld1_s32(int32_t const *a) { +// CIR: cir.load align(4) {{.*}} : !cir.ptr>, !cir.vector<2 x !s32i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <2 x i32>, ptr [[A]], align 4 +// LLVM: ret <2 x i32> [[TMP0]] + return vld1_s32(a); +} + +// ALL-LABEL: @test_vld1_s64( +int64x1_t test_vld1_s64(int64_t const *a) { +// CIR: cir.load align(8) {{.*}} : !cir.ptr>, !cir.vector<1 x !s64i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <1 x i64>, ptr [[A]], align 8 +// LLVM: ret <1 x i64> [[TMP0]] + return vld1_s64(a); +} + +// ALL-LABEL: @test_vld1_s8( +int8x8_t test_vld1_s8(int8_t const *a) { +// CIR: cir.load align(1) {{.*}} : !cir.ptr>, !cir.vector<8 x !s8i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <8 x i8>, ptr [[A]], align 1 +// LLVM: ret <8 x i8> [[TMP0]] + return vld1_s8(a); +} + +// ALL-LABEL: @test_vld1_u16( +uint16x4_t test_vld1_u16(uint16_t const *a) { +// CIR: cir.load align(2) {{.*}} : !cir.ptr>, !cir.vector<4 x !u16i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <4 x i16>, ptr [[A]], align 2 +// LLVM: ret <4 x i16> [[TMP0]] + return vld1_u16(a); +} + +// ALL-LABEL: @test_vld1_u32( +uint32x2_t test_vld1_u32(uint32_t const *a) { +// CIR: cir.load align(4) {{.*}} : !cir.ptr>, !cir.vector<2 x !u32i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <2 x i32>, ptr [[A]], align 4 +// LLVM: ret <2 x i32> [[TMP0]] + return vld1_u32(a); +} + +// ALL-LABEL: @test_vld1_u64( +uint64x1_t test_vld1_u64(uint64_t const *a) { +// CIR: cir.load align(8) {{.*}} : !cir.ptr>, !cir.vector<1 x !u64i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <1 x i64>, ptr [[A]], align 8 +// LLVM: ret <1 x i64> [[TMP0]] + return vld1_u64(a); +} + +// ALL-LABEL: @test_vld1_u8( +uint8x8_t test_vld1_u8(uint8_t const *a) { +// CIR: cir.load align(1) {{.*}} : !cir.ptr>, !cir.vector<8 x !u8i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <8 x i8>, ptr [[A]], align 1 +// LLVM: ret <8 x i8> [[TMP0]] + return vld1_u8(a); +} + +// Loading through a `void *` gives the vector no more than byte alignment. + +// ALL-LABEL: @test_vld1_u8_void( +uint8x8_t test_vld1_u8_void(void *a) { +// CIR: cir.load align(1) {{.*}} : !cir.ptr>, !cir.vector<8 x !u8i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <8 x i8>, ptr [[A]], align 1 +// LLVM: ret <8 x i8> [[TMP0]] + return vld1_u8(a); +} + +// ALL-LABEL: @test_vld1_u16_void( +uint16x4_t test_vld1_u16_void(void *a) { +// CIR: cir.load align(1) {{.*}} : !cir.ptr>, !cir.vector<4 x !u16i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <4 x i16>, ptr [[A]], align 1 +// LLVM: ret <4 x i16> [[TMP0]] + return vld1_u16(a); +} + +// ALL-LABEL: @test_vld1_u32_void( +uint32x2_t test_vld1_u32_void(void *a) { +// CIR: cir.load align(1) {{.*}} : !cir.ptr>, !cir.vector<2 x !u32i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <2 x i32>, ptr [[A]], align 1 +// LLVM: ret <2 x i32> [[TMP0]] + return vld1_u32(a); +} + +// ALL-LABEL: @test_vld1_u64_void( +uint64x1_t test_vld1_u64_void(void *a) { +// CIR: cir.load align(1) {{.*}} : !cir.ptr>, !cir.vector<1 x !u64i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <1 x i64>, ptr [[A]], align 1 +// LLVM: ret <1 x i64> [[TMP0]] + return vld1_u64(a); +} + +// ALL-LABEL: @test_vld1_s8_void( +int8x8_t test_vld1_s8_void(void *a) { +// CIR: cir.load align(1) {{.*}} : !cir.ptr>, !cir.vector<8 x !s8i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <8 x i8>, ptr [[A]], align 1 +// LLVM: ret <8 x i8> [[TMP0]] + return vld1_s8(a); +} + +// ALL-LABEL: @test_vld1_s16_void( +int16x4_t test_vld1_s16_void(void *a) { +// CIR: cir.load align(1) {{.*}} : !cir.ptr>, !cir.vector<4 x !s16i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <4 x i16>, ptr [[A]], align 1 +// LLVM: ret <4 x i16> [[TMP0]] + return vld1_s16(a); +} + +// ALL-LABEL: @test_vld1_s32_void( +int32x2_t test_vld1_s32_void(void *a) { +// CIR: cir.load align(1) {{.*}} : !cir.ptr>, !cir.vector<2 x !s32i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <2 x i32>, ptr [[A]], align 1 +// LLVM: ret <2 x i32> [[TMP0]] + return vld1_s32(a); +} + +// ALL-LABEL: @test_vld1_s64_void( +int64x1_t test_vld1_s64_void(void *a) { +// CIR: cir.load align(1) {{.*}} : !cir.ptr>, !cir.vector<1 x !s64i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <1 x i64>, ptr [[A]], align 1 +// LLVM: ret <1 x i64> [[TMP0]] + return vld1_s64(a); +} + +// ALL-LABEL: @test_vld1_f16_void( +float16x4_t test_vld1_f16_void(void *a) { +// CIR: cir.load align(1) {{.*}} : !cir.ptr>, !cir.vector<4 x !cir.f16> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <4 x half>, ptr [[A]], align 1 +// LLVM: ret <4 x half> [[TMP0]] + return vld1_f16(a); +} + +// ALL-LABEL: @test_vld1_f32_void( +float32x2_t test_vld1_f32_void(void *a) { +// CIR: cir.load align(1) {{.*}} : !cir.ptr>, !cir.vector<2 x !cir.float> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <2 x float>, ptr [[A]], align 1 +// LLVM: ret <2 x float> [[TMP0]] + return vld1_f32(a); +} + +// ALL-LABEL: @test_vld1_f64_void( +float64x1_t test_vld1_f64_void(void *a) { +// CIR: cir.load align(1) {{.*}} : !cir.ptr>, !cir.vector<1 x !cir.double> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <1 x double>, ptr [[A]], align 1 +// LLVM: ret <1 x double> [[TMP0]] + return vld1_f64(a); +} + +// ALL-LABEL: @test_vld1_p8_void( +poly8x8_t test_vld1_p8_void(void *a) { +// CIR: cir.load align(1) {{.*}} : !cir.ptr>, !cir.vector<8 x !s8i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <8 x i8>, ptr [[A]], align 1 +// LLVM: ret <8 x i8> [[TMP0]] + return vld1_p8(a); +} + +// ALL-LABEL: @test_vld1_p16_void( +poly16x4_t test_vld1_p16_void(void *a) { +// CIR: cir.load align(1) {{.*}} : !cir.ptr>, !cir.vector<4 x !s16i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load <4 x i16>, ptr [[A]], align 1 +// LLVM: ret <4 x i16> [[TMP0]] + return vld1_p16(a); +} + +// ALL-LABEL: @test_vld1q_f16_x2( +float16x8x2_t test_vld1q_f16_x2(float16_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x2" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld1x2.v8f16.p0(ptr [[A]]) + return vld1q_f16_x2(a); +} + +// ALL-LABEL: @test_vld1q_f32_x2( +float32x4x2_t test_vld1q_f32_x2(float32_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x2" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <4 x float>, <4 x float> } @llvm.aarch64.neon.ld1x2.v4f32.p0(ptr [[A]]) + return vld1q_f32_x2(a); +} + +// ALL-LABEL: @test_vld1q_f64_x2( +float64x2x2_t test_vld1q_f64_x2(float64_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x2" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[VLD1XN:%.*]] = call { <2 x double>, <2 x double> } @llvm.aarch64.neon.ld1x2.v2f64.p0(ptr [[A]]) +// LLVM-DAG: [[VLD1XN_FCA_0_EXTRACT:%.*]] = extractvalue { <2 x double>, <2 x double> } [[VLD1XN]], 0 +// LLVM-DAG: [[VLD1XN_FCA_1_EXTRACT:%.*]] = extractvalue { <2 x double>, <2 x double> } [[VLD1XN]], 1 +// LLVM: [[DOTFCA_0_0_INSERT:%.*]] = insertvalue %struct.float64x2x2_t poison, <2 x double> [[VLD1XN_FCA_0_EXTRACT]], 0, 0 +// LLVM: [[DOTFCA_0_1_INSERT:%.*]] = insertvalue %struct.float64x2x2_t [[DOTFCA_0_0_INSERT]], <2 x double> [[VLD1XN_FCA_1_EXTRACT]], 0, 1 +// LLVM: ret %struct.float64x2x2_t [[DOTFCA_0_1_INSERT]] + return vld1q_f64_x2(a); +} + +// ALL-LABEL: @test_vld1q_mf8_x2( +mfloat8x16x2_t test_vld1q_mf8_x2(mfloat8_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x2" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld1x2.v16i8.p0(ptr [[A]]) +// LLVM-DAG: [[VLD1XN_FCA_0_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[VLD1XN]], 0 +// LLVM-DAG: [[VLD1XN_FCA_1_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[VLD1XN]], 1 +// LLVM: [[DOTFCA_0_0_INSERT:%.*]] = insertvalue %struct.mfloat8x16x2_t poison, <16 x i8> [[VLD1XN_FCA_0_EXTRACT]], 0, 0 +// LLVM: [[DOTFCA_0_1_INSERT:%.*]] = insertvalue %struct.mfloat8x16x2_t [[DOTFCA_0_0_INSERT]], <16 x i8> [[VLD1XN_FCA_1_EXTRACT]], 0, 1 +// LLVM: ret %struct.mfloat8x16x2_t [[DOTFCA_0_1_INSERT]] + return vld1q_mf8_x2(a); +} + +// ALL-LABEL: @test_vld1q_p16_x2( +poly16x8x2_t test_vld1q_p16_x2(poly16_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x2" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld1x2.v8i16.p0(ptr [[A]]) + return vld1q_p16_x2(a); +} + +// ALL-LABEL: @test_vld1q_p64_x2( +poly64x2x2_t test_vld1q_p64_x2(poly64_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x2" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld1x2.v2i64.p0(ptr [[A]]) +// LLVM-DAG: [[VLD1XN_FCA_0_EXTRACT:%.*]] = extractvalue { <2 x i64>, <2 x i64> } [[VLD1XN]], 0 +// LLVM-DAG: [[VLD1XN_FCA_1_EXTRACT:%.*]] = extractvalue { <2 x i64>, <2 x i64> } [[VLD1XN]], 1 +// LLVM: [[DOTFCA_0_0_INSERT:%.*]] = insertvalue %struct.poly64x2x2_t poison, <2 x i64> [[VLD1XN_FCA_0_EXTRACT]], 0, 0 +// LLVM: [[DOTFCA_0_1_INSERT:%.*]] = insertvalue %struct.poly64x2x2_t [[DOTFCA_0_0_INSERT]], <2 x i64> [[VLD1XN_FCA_1_EXTRACT]], 0, 1 +// LLVM: ret %struct.poly64x2x2_t [[DOTFCA_0_1_INSERT]] + return vld1q_p64_x2(a); +} + +// ALL-LABEL: @test_vld1q_p8_x2( +poly8x16x2_t test_vld1q_p8_x2(poly8_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x2" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld1x2.v16i8.p0(ptr [[A]]) + return vld1q_p8_x2(a); +} + +// ALL-LABEL: @test_vld1q_s16_x2( +int16x8x2_t test_vld1q_s16_x2(int16_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x2" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld1x2.v8i16.p0(ptr [[A]]) + return vld1q_s16_x2(a); +} + +// ALL-LABEL: @test_vld1q_s32_x2( +int32x4x2_t test_vld1q_s32_x2(int32_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x2" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld1x2.v4i32.p0(ptr [[A]]) + return vld1q_s32_x2(a); +} + +// ALL-LABEL: @test_vld1q_s64_x2( +int64x2x2_t test_vld1q_s64_x2(int64_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x2" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld1x2.v2i64.p0(ptr [[A]]) + return vld1q_s64_x2(a); +} + +// ALL-LABEL: @test_vld1q_s8_x2( +int8x16x2_t test_vld1q_s8_x2(int8_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x2" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld1x2.v16i8.p0(ptr [[A]]) + return vld1q_s8_x2(a); +} + +// ALL-LABEL: @test_vld1q_u16_x2( +uint16x8x2_t test_vld1q_u16_x2(uint16_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x2" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld1x2.v8i16.p0(ptr [[A]]) + return vld1q_u16_x2(a); +} + +// ALL-LABEL: @test_vld1q_u32_x2( +uint32x4x2_t test_vld1q_u32_x2(uint32_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x2" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld1x2.v4i32.p0(ptr [[A]]) + return vld1q_u32_x2(a); +} + +// ALL-LABEL: @test_vld1q_u64_x2( +uint64x2x2_t test_vld1q_u64_x2(uint64_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x2" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld1x2.v2i64.p0(ptr [[A]]) + return vld1q_u64_x2(a); +} + +// ALL-LABEL: @test_vld1q_u8_x2( +uint8x16x2_t test_vld1q_u8_x2(uint8_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x2" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld1x2.v16i8.p0(ptr [[A]]) + return vld1q_u8_x2(a); +} + +// ALL-LABEL: @test_vld1_f16_x2( +float16x4x2_t test_vld1_f16_x2(float16_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x2" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x2.v4f16.p0(ptr [[A]]) + return vld1_f16_x2(a); +} + +// ALL-LABEL: @test_vld1_f32_x2( +float32x2x2_t test_vld1_f32_x2(float32_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x2" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x2.v2f32.p0(ptr [[A]]) + return vld1_f32_x2(a); +} + +// ALL-LABEL: @test_vld1_f64_x2( +float64x1x2_t test_vld1_f64_x2(float64_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x2" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[VLD1XN:%.*]] = call { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld1x2.v1f64.p0(ptr [[A]]) +// LLVM-DAG: [[VLD1XN_FCA_0_EXTRACT:%.*]] = extractvalue { <1 x double>, <1 x double> } [[VLD1XN]], 0 +// LLVM-DAG: [[VLD1XN_FCA_1_EXTRACT:%.*]] = extractvalue { <1 x double>, <1 x double> } [[VLD1XN]], 1 +// LLVM: [[DOTFCA_0_0_INSERT:%.*]] = insertvalue %struct.float64x1x2_t poison, <1 x double> [[VLD1XN_FCA_0_EXTRACT]], 0, 0 +// LLVM: [[DOTFCA_0_1_INSERT:%.*]] = insertvalue %struct.float64x1x2_t [[DOTFCA_0_0_INSERT]], <1 x double> [[VLD1XN_FCA_1_EXTRACT]], 0, 1 +// LLVM: ret %struct.float64x1x2_t [[DOTFCA_0_1_INSERT]] + return vld1_f64_x2(a); +} + +// ALL-LABEL: @test_vld1_mf8_x2( +mfloat8x8x2_t test_vld1_mf8_x2(mfloat8_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x2" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld1x2.v8i8.p0(ptr [[A]]) +// LLVM-DAG: [[VLD1XN_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8> } [[VLD1XN]], 0 +// LLVM-DAG: [[VLD1XN_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8> } [[VLD1XN]], 1 +// LLVM: [[DOTFCA_0_0_INSERT:%.*]] = insertvalue %struct.mfloat8x8x2_t poison, <8 x i8> [[VLD1XN_FCA_0_EXTRACT]], 0, 0 +// LLVM: [[DOTFCA_0_1_INSERT:%.*]] = insertvalue %struct.mfloat8x8x2_t [[DOTFCA_0_0_INSERT]], <8 x i8> [[VLD1XN_FCA_1_EXTRACT]], 0, 1 +// LLVM: ret %struct.mfloat8x8x2_t [[DOTFCA_0_1_INSERT]] + return vld1_mf8_x2(a); +} + +// ALL-LABEL: @test_vld1_p16_x2( +poly16x4x2_t test_vld1_p16_x2(poly16_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x2" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x2.v4i16.p0(ptr [[A]]) + return vld1_p16_x2(a); +} + +// ALL-LABEL: @test_vld1_p64_x2( +poly64x1x2_t test_vld1_p64_x2(poly64_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x2" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld1x2.v1i64.p0(ptr [[A]]) +// LLVM-DAG: [[VLD1XN_FCA_0_EXTRACT:%.*]] = extractvalue { <1 x i64>, <1 x i64> } [[VLD1XN]], 0 +// LLVM-DAG: [[VLD1XN_FCA_1_EXTRACT:%.*]] = extractvalue { <1 x i64>, <1 x i64> } [[VLD1XN]], 1 +// LLVM: [[DOTFCA_0_0_INSERT:%.*]] = insertvalue %struct.poly64x1x2_t poison, <1 x i64> [[VLD1XN_FCA_0_EXTRACT]], 0, 0 +// LLVM: [[DOTFCA_0_1_INSERT:%.*]] = insertvalue %struct.poly64x1x2_t [[DOTFCA_0_0_INSERT]], <1 x i64> [[VLD1XN_FCA_1_EXTRACT]], 0, 1 +// LLVM: ret %struct.poly64x1x2_t [[DOTFCA_0_1_INSERT]] + return vld1_p64_x2(a); +} + +// ALL-LABEL: @test_vld1_p8_x2( +poly8x8x2_t test_vld1_p8_x2(poly8_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x2" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld1x2.v8i8.p0(ptr [[A]]) + return vld1_p8_x2(a); +} + +// ALL-LABEL: @test_vld1_s16_x2( +int16x4x2_t test_vld1_s16_x2(int16_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x2" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x2.v4i16.p0(ptr [[A]]) + return vld1_s16_x2(a); +} + +// ALL-LABEL: @test_vld1_s32_x2( +int32x2x2_t test_vld1_s32_x2(int32_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x2" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld1x2.v2i32.p0(ptr [[A]]) + return vld1_s32_x2(a); +} + +// ALL-LABEL: @test_vld1_s64_x2( +int64x1x2_t test_vld1_s64_x2(int64_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x2" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld1x2.v1i64.p0(ptr [[A]]) + return vld1_s64_x2(a); +} + +// ALL-LABEL: @test_vld1_s8_x2( +int8x8x2_t test_vld1_s8_x2(int8_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x2" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld1x2.v8i8.p0(ptr [[A]]) + return vld1_s8_x2(a); +} + +// ALL-LABEL: @test_vld1_u16_x2( +uint16x4x2_t test_vld1_u16_x2(uint16_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x2" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x2.v4i16.p0(ptr [[A]]) + return vld1_u16_x2(a); +} + +// ALL-LABEL: @test_vld1_u32_x2( +uint32x2x2_t test_vld1_u32_x2(uint32_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x2" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld1x2.v2i32.p0(ptr [[A]]) + return vld1_u32_x2(a); +} + +// ALL-LABEL: @test_vld1_u64_x2( +uint64x1x2_t test_vld1_u64_x2(uint64_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x2" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld1x2.v1i64.p0(ptr [[A]]) + return vld1_u64_x2(a); +} + +// ALL-LABEL: @test_vld1_u8_x2( +uint8x8x2_t test_vld1_u8_x2(uint8_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x2" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld1x2.v8i8.p0(ptr [[A]]) + return vld1_u8_x2(a); +} + +// ALL-LABEL: @test_vld1q_f16_x3( +float16x8x3_t test_vld1q_f16_x3(float16_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x3" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld1x3.v8f16.p0(ptr [[A]]) + return vld1q_f16_x3(a); +} + +// ALL-LABEL: @test_vld1q_f32_x3( +float32x4x3_t test_vld1q_f32_x3(float32_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x3" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld1x3.v4f32.p0(ptr [[A]]) + return vld1q_f32_x3(a); +} + +// ALL-LABEL: @test_vld1q_f64_x3( +float64x2x3_t test_vld1q_f64_x3(float64_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x3" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[VLD1XN:%.*]] = call { <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld1x3.v2f64.p0(ptr [[A]]) +// LLVM-DAG: [[VLD1XN_FCA_0_EXTRACT:%.*]] = extractvalue { <2 x double>, <2 x double>, <2 x double> } [[VLD1XN]], 0 +// LLVM-DAG: [[VLD1XN_FCA_1_EXTRACT:%.*]] = extractvalue { <2 x double>, <2 x double>, <2 x double> } [[VLD1XN]], 1 +// LLVM-DAG: [[VLD1XN_FCA_2_EXTRACT:%.*]] = extractvalue { <2 x double>, <2 x double>, <2 x double> } [[VLD1XN]], 2 +// LLVM: [[DOTFCA_0_0_INSERT:%.*]] = insertvalue %struct.float64x2x3_t poison, <2 x double> [[VLD1XN_FCA_0_EXTRACT]], 0, 0 +// LLVM: [[DOTFCA_0_1_INSERT:%.*]] = insertvalue %struct.float64x2x3_t [[DOTFCA_0_0_INSERT]], <2 x double> [[VLD1XN_FCA_1_EXTRACT]], 0, 1 +// LLVM: [[DOTFCA_0_2_INSERT:%.*]] = insertvalue %struct.float64x2x3_t [[DOTFCA_0_1_INSERT]], <2 x double> [[VLD1XN_FCA_2_EXTRACT]], 0, 2 +// LLVM: ret %struct.float64x2x3_t [[DOTFCA_0_2_INSERT]] + return vld1q_f64_x3(a); +} + +// ALL-LABEL: @test_vld1q_mf8_x3( +mfloat8x16x3_t test_vld1q_mf8_x3(mfloat8_t const *ptr) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x3" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[PTR:%.*]]) +// LLVM: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld1x3.v16i8.p0(ptr [[PTR]]) +// LLVM-DAG: [[VLD1XN_FCA_0_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], 0 +// LLVM-DAG: [[VLD1XN_FCA_1_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], 1 +// LLVM-DAG: [[VLD1XN_FCA_2_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], 2 +// LLVM: [[DOTFCA_0_0_INSERT:%.*]] = insertvalue %struct.mfloat8x16x3_t poison, <16 x i8> [[VLD1XN_FCA_0_EXTRACT]], 0, 0 +// LLVM: [[DOTFCA_0_1_INSERT:%.*]] = insertvalue %struct.mfloat8x16x3_t [[DOTFCA_0_0_INSERT]], <16 x i8> [[VLD1XN_FCA_1_EXTRACT]], 0, 1 +// LLVM: [[DOTFCA_0_2_INSERT:%.*]] = insertvalue %struct.mfloat8x16x3_t [[DOTFCA_0_1_INSERT]], <16 x i8> [[VLD1XN_FCA_2_EXTRACT]], 0, 2 +// LLVM: ret %struct.mfloat8x16x3_t [[DOTFCA_0_2_INSERT]] + return vld1q_mf8_x3(ptr); +} + +// ALL-LABEL: @test_vld1q_p16_x3( +poly16x8x3_t test_vld1q_p16_x3(poly16_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x3" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld1x3.v8i16.p0(ptr [[A]]) + return vld1q_p16_x3(a); +} + +// ALL-LABEL: @test_vld1q_p64_x3( +poly64x2x3_t test_vld1q_p64_x3(poly64_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x3" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld1x3.v2i64.p0(ptr [[A]]) +// LLVM-DAG: [[VLD1XN_FCA_0_EXTRACT:%.*]] = extractvalue { <2 x i64>, <2 x i64>, <2 x i64> } [[VLD1XN]], 0 +// LLVM-DAG: [[VLD1XN_FCA_1_EXTRACT:%.*]] = extractvalue { <2 x i64>, <2 x i64>, <2 x i64> } [[VLD1XN]], 1 +// LLVM-DAG: [[VLD1XN_FCA_2_EXTRACT:%.*]] = extractvalue { <2 x i64>, <2 x i64>, <2 x i64> } [[VLD1XN]], 2 +// LLVM: [[DOTFCA_0_0_INSERT:%.*]] = insertvalue %struct.poly64x2x3_t poison, <2 x i64> [[VLD1XN_FCA_0_EXTRACT]], 0, 0 +// LLVM: [[DOTFCA_0_1_INSERT:%.*]] = insertvalue %struct.poly64x2x3_t [[DOTFCA_0_0_INSERT]], <2 x i64> [[VLD1XN_FCA_1_EXTRACT]], 0, 1 +// LLVM: [[DOTFCA_0_2_INSERT:%.*]] = insertvalue %struct.poly64x2x3_t [[DOTFCA_0_1_INSERT]], <2 x i64> [[VLD1XN_FCA_2_EXTRACT]], 0, 2 +// LLVM: ret %struct.poly64x2x3_t [[DOTFCA_0_2_INSERT]] + return vld1q_p64_x3(a); +} + +// ALL-LABEL: @test_vld1q_p8_x3( +poly8x16x3_t test_vld1q_p8_x3(poly8_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x3" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld1x3.v16i8.p0(ptr [[A]]) + return vld1q_p8_x3(a); +} + +// ALL-LABEL: @test_vld1q_s16_x3( +int16x8x3_t test_vld1q_s16_x3(int16_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x3" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld1x3.v8i16.p0(ptr [[A]]) + return vld1q_s16_x3(a); +} + +// ALL-LABEL: @test_vld1q_s32_x3( +int32x4x3_t test_vld1q_s32_x3(int32_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x3" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld1x3.v4i32.p0(ptr [[A]]) + return vld1q_s32_x3(a); +} + +// ALL-LABEL: @test_vld1q_s64_x3( +int64x2x3_t test_vld1q_s64_x3(int64_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x3" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld1x3.v2i64.p0(ptr [[A]]) + return vld1q_s64_x3(a); +} + +// ALL-LABEL: @test_vld1q_s8_x3( +int8x16x3_t test_vld1q_s8_x3(int8_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x3" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld1x3.v16i8.p0(ptr [[A]]) + return vld1q_s8_x3(a); +} + +// ALL-LABEL: @test_vld1q_u16_x3( +uint16x8x3_t test_vld1q_u16_x3(uint16_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x3" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld1x3.v8i16.p0(ptr [[A]]) + return vld1q_u16_x3(a); +} + +// ALL-LABEL: @test_vld1q_u32_x3( +uint32x4x3_t test_vld1q_u32_x3(uint32_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x3" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld1x3.v4i32.p0(ptr [[A]]) + return vld1q_u32_x3(a); +} + +// ALL-LABEL: @test_vld1q_u64_x3( +uint64x2x3_t test_vld1q_u64_x3(uint64_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x3" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld1x3.v2i64.p0(ptr [[A]]) + return vld1q_u64_x3(a); +} + +// ALL-LABEL: @test_vld1q_u8_x3( +uint8x16x3_t test_vld1q_u8_x3(uint8_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x3" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld1x3.v16i8.p0(ptr [[A]]) + return vld1q_u8_x3(a); +} + +// ALL-LABEL: @test_vld1_f16_x3( +float16x4x3_t test_vld1_f16_x3(float16_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x3" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x3.v4f16.p0(ptr [[A]]) + return vld1_f16_x3(a); +} + +// ALL-LABEL: @test_vld1_f32_x3( +float32x2x3_t test_vld1_f32_x3(float32_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x3" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x3.v2f32.p0(ptr [[A]]) + return vld1_f32_x3(a); +} + +// ALL-LABEL: @test_vld1_f64_x3( +float64x1x3_t test_vld1_f64_x3(float64_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x3" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[VLD1XN:%.*]] = call { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld1x3.v1f64.p0(ptr [[A]]) +// LLVM-DAG: [[VLD1XN_FCA_0_EXTRACT:%.*]] = extractvalue { <1 x double>, <1 x double>, <1 x double> } [[VLD1XN]], 0 +// LLVM-DAG: [[VLD1XN_FCA_1_EXTRACT:%.*]] = extractvalue { <1 x double>, <1 x double>, <1 x double> } [[VLD1XN]], 1 +// LLVM-DAG: [[VLD1XN_FCA_2_EXTRACT:%.*]] = extractvalue { <1 x double>, <1 x double>, <1 x double> } [[VLD1XN]], 2 +// LLVM: [[DOTFCA_0_0_INSERT:%.*]] = insertvalue %struct.float64x1x3_t poison, <1 x double> [[VLD1XN_FCA_0_EXTRACT]], 0, 0 +// LLVM: [[DOTFCA_0_1_INSERT:%.*]] = insertvalue %struct.float64x1x3_t [[DOTFCA_0_0_INSERT]], <1 x double> [[VLD1XN_FCA_1_EXTRACT]], 0, 1 +// LLVM: [[DOTFCA_0_2_INSERT:%.*]] = insertvalue %struct.float64x1x3_t [[DOTFCA_0_1_INSERT]], <1 x double> [[VLD1XN_FCA_2_EXTRACT]], 0, 2 +// LLVM: ret %struct.float64x1x3_t [[DOTFCA_0_2_INSERT]] + return vld1_f64_x3(a); +} + +// ALL-LABEL: @test_vld1_mf8_x3( +mfloat8x8x3_t test_vld1_mf8_x3(mfloat8_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x3" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld1x3.v8i8.p0(ptr [[A]]) +// LLVM-DAG: [[VLD1XN_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], 0 +// LLVM-DAG: [[VLD1XN_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], 1 +// LLVM-DAG: [[VLD1XN_FCA_2_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], 2 +// LLVM: [[DOTFCA_0_0_INSERT:%.*]] = insertvalue %struct.mfloat8x8x3_t poison, <8 x i8> [[VLD1XN_FCA_0_EXTRACT]], 0, 0 +// LLVM: [[DOTFCA_0_1_INSERT:%.*]] = insertvalue %struct.mfloat8x8x3_t [[DOTFCA_0_0_INSERT]], <8 x i8> [[VLD1XN_FCA_1_EXTRACT]], 0, 1 +// LLVM: [[DOTFCA_0_2_INSERT:%.*]] = insertvalue %struct.mfloat8x8x3_t [[DOTFCA_0_1_INSERT]], <8 x i8> [[VLD1XN_FCA_2_EXTRACT]], 0, 2 +// LLVM: ret %struct.mfloat8x8x3_t [[DOTFCA_0_2_INSERT]] + return vld1_mf8_x3(a); +} + +// ALL-LABEL: @test_vld1_p16_x3( +poly16x4x3_t test_vld1_p16_x3(poly16_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x3" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x3.v4i16.p0(ptr [[A]]) + return vld1_p16_x3(a); +} + +// ALL-LABEL: @test_vld1_p64_x3( +poly64x1x3_t test_vld1_p64_x3(poly64_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x3" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld1x3.v1i64.p0(ptr [[A]]) +// LLVM-DAG: [[VLD1XN_FCA_0_EXTRACT:%.*]] = extractvalue { <1 x i64>, <1 x i64>, <1 x i64> } [[VLD1XN]], 0 +// LLVM-DAG: [[VLD1XN_FCA_1_EXTRACT:%.*]] = extractvalue { <1 x i64>, <1 x i64>, <1 x i64> } [[VLD1XN]], 1 +// LLVM-DAG: [[VLD1XN_FCA_2_EXTRACT:%.*]] = extractvalue { <1 x i64>, <1 x i64>, <1 x i64> } [[VLD1XN]], 2 +// LLVM: [[DOTFCA_0_0_INSERT:%.*]] = insertvalue %struct.poly64x1x3_t poison, <1 x i64> [[VLD1XN_FCA_0_EXTRACT]], 0, 0 +// LLVM: [[DOTFCA_0_1_INSERT:%.*]] = insertvalue %struct.poly64x1x3_t [[DOTFCA_0_0_INSERT]], <1 x i64> [[VLD1XN_FCA_1_EXTRACT]], 0, 1 +// LLVM: [[DOTFCA_0_2_INSERT:%.*]] = insertvalue %struct.poly64x1x3_t [[DOTFCA_0_1_INSERT]], <1 x i64> [[VLD1XN_FCA_2_EXTRACT]], 0, 2 +// LLVM: ret %struct.poly64x1x3_t [[DOTFCA_0_2_INSERT]] + return vld1_p64_x3(a); +} + +// ALL-LABEL: @test_vld1_p8_x3( +poly8x8x3_t test_vld1_p8_x3(poly8_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x3" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld1x3.v8i8.p0(ptr [[A]]) + return vld1_p8_x3(a); +} + +// ALL-LABEL: @test_vld1_s16_x3( +int16x4x3_t test_vld1_s16_x3(int16_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x3" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x3.v4i16.p0(ptr [[A]]) + return vld1_s16_x3(a); +} + +// ALL-LABEL: @test_vld1_s32_x3( +int32x2x3_t test_vld1_s32_x3(int32_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x3" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld1x3.v2i32.p0(ptr [[A]]) + return vld1_s32_x3(a); +} + +// ALL-LABEL: @test_vld1_s64_x3( +int64x1x3_t test_vld1_s64_x3(int64_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x3" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld1x3.v1i64.p0(ptr [[A]]) + return vld1_s64_x3(a); +} + +// ALL-LABEL: @test_vld1_s8_x3( +int8x8x3_t test_vld1_s8_x3(int8_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x3" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld1x3.v8i8.p0(ptr [[A]]) + return vld1_s8_x3(a); +} + +// ALL-LABEL: @test_vld1_u16_x3( +uint16x4x3_t test_vld1_u16_x3(uint16_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x3" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x3.v4i16.p0(ptr [[A]]) + return vld1_u16_x3(a); +} + +// ALL-LABEL: @test_vld1_u32_x3( +uint32x2x3_t test_vld1_u32_x3(uint32_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x3" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld1x3.v2i32.p0(ptr [[A]]) + return vld1_u32_x3(a); +} + +// ALL-LABEL: @test_vld1_u64_x3( +uint64x1x3_t test_vld1_u64_x3(uint64_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x3" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld1x3.v1i64.p0(ptr [[A]]) + return vld1_u64_x3(a); +} + +// ALL-LABEL: @test_vld1_u8_x3( +uint8x8x3_t test_vld1_u8_x3(uint8_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x3" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld1x3.v8i8.p0(ptr [[A]]) + return vld1_u8_x3(a); +} + +// ALL-LABEL: @test_vld1q_f16_x4( +float16x8x4_t test_vld1q_f16_x4(float16_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x4" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld1x4.v8f16.p0(ptr [[A]]) + return vld1q_f16_x4(a); +} + +// ALL-LABEL: @test_vld1q_f32_x4( +float32x4x4_t test_vld1q_f32_x4(float32_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x4" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld1x4.v4f32.p0(ptr [[A]]) + return vld1q_f32_x4(a); +} + +// ALL-LABEL: @test_vld1q_f64_x4( +float64x2x4_t test_vld1q_f64_x4(float64_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x4" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[VLD1XN:%.*]] = call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld1x4.v2f64.p0(ptr [[A]]) +// LLVM-DAG: [[VLD1XN_FCA_0_EXTRACT:%.*]] = extractvalue { <2 x double>, <2 x double>, <2 x double>, <2 x double> } [[VLD1XN]], 0 +// LLVM-DAG: [[VLD1XN_FCA_1_EXTRACT:%.*]] = extractvalue { <2 x double>, <2 x double>, <2 x double>, <2 x double> } [[VLD1XN]], 1 +// LLVM-DAG: [[VLD1XN_FCA_2_EXTRACT:%.*]] = extractvalue { <2 x double>, <2 x double>, <2 x double>, <2 x double> } [[VLD1XN]], 2 +// LLVM-DAG: [[VLD1XN_FCA_3_EXTRACT:%.*]] = extractvalue { <2 x double>, <2 x double>, <2 x double>, <2 x double> } [[VLD1XN]], 3 +// LLVM: [[DOTFCA_0_0_INSERT:%.*]] = insertvalue %struct.float64x2x4_t poison, <2 x double> [[VLD1XN_FCA_0_EXTRACT]], 0, 0 +// LLVM: [[DOTFCA_0_1_INSERT:%.*]] = insertvalue %struct.float64x2x4_t [[DOTFCA_0_0_INSERT]], <2 x double> [[VLD1XN_FCA_1_EXTRACT]], 0, 1 +// LLVM: [[DOTFCA_0_2_INSERT:%.*]] = insertvalue %struct.float64x2x4_t [[DOTFCA_0_1_INSERT]], <2 x double> [[VLD1XN_FCA_2_EXTRACT]], 0, 2 +// LLVM: [[DOTFCA_0_3_INSERT:%.*]] = insertvalue %struct.float64x2x4_t [[DOTFCA_0_2_INSERT]], <2 x double> [[VLD1XN_FCA_3_EXTRACT]], 0, 3 +// LLVM: ret %struct.float64x2x4_t [[DOTFCA_0_3_INSERT]] + return vld1q_f64_x4(a); +} + +// ALL-LABEL: @test_vld1q_mf8_x4( +mfloat8x16x4_t test_vld1q_mf8_x4(mfloat8_t const *ptr) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x4" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[PTR:%.*]]) +// LLVM: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld1x4.v16i8.p0(ptr [[PTR]]) +// LLVM-DAG: [[VLD1XN_FCA_0_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], 0 +// LLVM-DAG: [[VLD1XN_FCA_1_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], 1 +// LLVM-DAG: [[VLD1XN_FCA_2_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], 2 +// LLVM-DAG: [[VLD1XN_FCA_3_EXTRACT:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], 3 +// LLVM: [[DOTFCA_0_0_INSERT:%.*]] = insertvalue %struct.mfloat8x16x4_t poison, <16 x i8> [[VLD1XN_FCA_0_EXTRACT]], 0, 0 +// LLVM: [[DOTFCA_0_1_INSERT:%.*]] = insertvalue %struct.mfloat8x16x4_t [[DOTFCA_0_0_INSERT]], <16 x i8> [[VLD1XN_FCA_1_EXTRACT]], 0, 1 +// LLVM: [[DOTFCA_0_2_INSERT:%.*]] = insertvalue %struct.mfloat8x16x4_t [[DOTFCA_0_1_INSERT]], <16 x i8> [[VLD1XN_FCA_2_EXTRACT]], 0, 2 +// LLVM: [[DOTFCA_0_3_INSERT:%.*]] = insertvalue %struct.mfloat8x16x4_t [[DOTFCA_0_2_INSERT]], <16 x i8> [[VLD1XN_FCA_3_EXTRACT]], 0, 3 +// LLVM: ret %struct.mfloat8x16x4_t [[DOTFCA_0_3_INSERT]] + return vld1q_mf8_x4(ptr); +} + +// ALL-LABEL: @test_vld1q_p16_x4( +poly16x8x4_t test_vld1q_p16_x4(poly16_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x4" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld1x4.v8i16.p0(ptr [[A]]) + return vld1q_p16_x4(a); +} + +// ALL-LABEL: @test_vld1q_p64_x4( +poly64x2x4_t test_vld1q_p64_x4(poly64_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x4" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld1x4.v2i64.p0(ptr [[A]]) +// LLVM-DAG: [[VLD1XN_FCA_0_EXTRACT:%.*]] = extractvalue { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[VLD1XN]], 0 +// LLVM-DAG: [[VLD1XN_FCA_1_EXTRACT:%.*]] = extractvalue { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[VLD1XN]], 1 +// LLVM-DAG: [[VLD1XN_FCA_2_EXTRACT:%.*]] = extractvalue { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[VLD1XN]], 2 +// LLVM-DAG: [[VLD1XN_FCA_3_EXTRACT:%.*]] = extractvalue { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[VLD1XN]], 3 +// LLVM: [[DOTFCA_0_0_INSERT:%.*]] = insertvalue %struct.poly64x2x4_t poison, <2 x i64> [[VLD1XN_FCA_0_EXTRACT]], 0, 0 +// LLVM: [[DOTFCA_0_1_INSERT:%.*]] = insertvalue %struct.poly64x2x4_t [[DOTFCA_0_0_INSERT]], <2 x i64> [[VLD1XN_FCA_1_EXTRACT]], 0, 1 +// LLVM: [[DOTFCA_0_2_INSERT:%.*]] = insertvalue %struct.poly64x2x4_t [[DOTFCA_0_1_INSERT]], <2 x i64> [[VLD1XN_FCA_2_EXTRACT]], 0, 2 +// LLVM: [[DOTFCA_0_3_INSERT:%.*]] = insertvalue %struct.poly64x2x4_t [[DOTFCA_0_2_INSERT]], <2 x i64> [[VLD1XN_FCA_3_EXTRACT]], 0, 3 +// LLVM: ret %struct.poly64x2x4_t [[DOTFCA_0_3_INSERT]] + return vld1q_p64_x4(a); +} + +// ALL-LABEL: @test_vld1q_p8_x4( +poly8x16x4_t test_vld1q_p8_x4(poly8_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x4" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld1x4.v16i8.p0(ptr [[A]]) + return vld1q_p8_x4(a); +} + +// ALL-LABEL: @test_vld1q_s16_x4( +int16x8x4_t test_vld1q_s16_x4(int16_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x4" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld1x4.v8i16.p0(ptr [[A]]) + return vld1q_s16_x4(a); +} + +// ALL-LABEL: @test_vld1q_s32_x4( +int32x4x4_t test_vld1q_s32_x4(int32_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x4" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld1x4.v4i32.p0(ptr [[A]]) + return vld1q_s32_x4(a); +} + +// ALL-LABEL: @test_vld1q_s64_x4( +int64x2x4_t test_vld1q_s64_x4(int64_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x4" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld1x4.v2i64.p0(ptr [[A]]) + return vld1q_s64_x4(a); +} + +// ALL-LABEL: @test_vld1q_s8_x4( +int8x16x4_t test_vld1q_s8_x4(int8_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x4" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld1x4.v16i8.p0(ptr [[A]]) + return vld1q_s8_x4(a); +} + +// ALL-LABEL: @test_vld1q_u16_x4( +uint16x8x4_t test_vld1q_u16_x4(uint16_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x4" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld1x4.v8i16.p0(ptr [[A]]) + return vld1q_u16_x4(a); +} + +// ALL-LABEL: @test_vld1q_u32_x4( +uint32x4x4_t test_vld1q_u32_x4(uint32_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x4" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld1x4.v4i32.p0(ptr [[A]]) + return vld1q_u32_x4(a); +} + +// ALL-LABEL: @test_vld1q_u64_x4( +uint64x2x4_t test_vld1q_u64_x4(uint64_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x4" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld1x4.v2i64.p0(ptr [[A]]) + return vld1q_u64_x4(a); +} + +// ALL-LABEL: @test_vld1q_u8_x4( +uint8x16x4_t test_vld1q_u8_x4(uint8_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x4" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(16) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld1x4.v16i8.p0(ptr [[A]]) + return vld1q_u8_x4(a); +} + +// ALL-LABEL: @test_vld1_f16_x4( +float16x4x4_t test_vld1_f16_x4(float16_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x4" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x4.v4f16.p0(ptr [[A]]) + return vld1_f16_x4(a); +} + +// ALL-LABEL: @test_vld1_f32_x4( +float32x2x4_t test_vld1_f32_x4(float32_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x4" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x4.v2f32.p0(ptr [[A]]) + return vld1_f32_x4(a); +} + +// ALL-LABEL: @test_vld1_f64_x4( +float64x1x4_t test_vld1_f64_x4(float64_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x4" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[VLD1XN:%.*]] = call { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld1x4.v1f64.p0(ptr [[A]]) +// LLVM-DAG: [[VLD1XN_FCA_0_EXTRACT:%.*]] = extractvalue { <1 x double>, <1 x double>, <1 x double>, <1 x double> } [[VLD1XN]], 0 +// LLVM-DAG: [[VLD1XN_FCA_1_EXTRACT:%.*]] = extractvalue { <1 x double>, <1 x double>, <1 x double>, <1 x double> } [[VLD1XN]], 1 +// LLVM-DAG: [[VLD1XN_FCA_2_EXTRACT:%.*]] = extractvalue { <1 x double>, <1 x double>, <1 x double>, <1 x double> } [[VLD1XN]], 2 +// LLVM-DAG: [[VLD1XN_FCA_3_EXTRACT:%.*]] = extractvalue { <1 x double>, <1 x double>, <1 x double>, <1 x double> } [[VLD1XN]], 3 +// LLVM: [[DOTFCA_0_0_INSERT:%.*]] = insertvalue %struct.float64x1x4_t poison, <1 x double> [[VLD1XN_FCA_0_EXTRACT]], 0, 0 +// LLVM: [[DOTFCA_0_1_INSERT:%.*]] = insertvalue %struct.float64x1x4_t [[DOTFCA_0_0_INSERT]], <1 x double> [[VLD1XN_FCA_1_EXTRACT]], 0, 1 +// LLVM: [[DOTFCA_0_2_INSERT:%.*]] = insertvalue %struct.float64x1x4_t [[DOTFCA_0_1_INSERT]], <1 x double> [[VLD1XN_FCA_2_EXTRACT]], 0, 2 +// LLVM: [[DOTFCA_0_3_INSERT:%.*]] = insertvalue %struct.float64x1x4_t [[DOTFCA_0_2_INSERT]], <1 x double> [[VLD1XN_FCA_3_EXTRACT]], 0, 3 +// LLVM: ret %struct.float64x1x4_t [[DOTFCA_0_3_INSERT]] + return vld1_f64_x4(a); +} + +// ALL-LABEL: @test_vld1_mf8_x4( +mfloat8x8x4_t test_vld1_mf8_x4(mfloat8_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x4" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld1x4.v8i8.p0(ptr [[A]]) +// LLVM-DAG: [[VLD1XN_FCA_0_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], 0 +// LLVM-DAG: [[VLD1XN_FCA_1_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], 1 +// LLVM-DAG: [[VLD1XN_FCA_2_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], 2 +// LLVM-DAG: [[VLD1XN_FCA_3_EXTRACT:%.*]] = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], 3 +// LLVM: [[DOTFCA_0_0_INSERT:%.*]] = insertvalue %struct.mfloat8x8x4_t poison, <8 x i8> [[VLD1XN_FCA_0_EXTRACT]], 0, 0 +// LLVM: [[DOTFCA_0_1_INSERT:%.*]] = insertvalue %struct.mfloat8x8x4_t [[DOTFCA_0_0_INSERT]], <8 x i8> [[VLD1XN_FCA_1_EXTRACT]], 0, 1 +// LLVM: [[DOTFCA_0_2_INSERT:%.*]] = insertvalue %struct.mfloat8x8x4_t [[DOTFCA_0_1_INSERT]], <8 x i8> [[VLD1XN_FCA_2_EXTRACT]], 0, 2 +// LLVM: [[DOTFCA_0_3_INSERT:%.*]] = insertvalue %struct.mfloat8x8x4_t [[DOTFCA_0_2_INSERT]], <8 x i8> [[VLD1XN_FCA_3_EXTRACT]], 0, 3 +// LLVM: ret %struct.mfloat8x8x4_t [[DOTFCA_0_3_INSERT]] + return vld1_mf8_x4(a); +} + +// ALL-LABEL: @test_vld1_p16_x4( +poly16x4x4_t test_vld1_p16_x4(poly16_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x4" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x4.v4i16.p0(ptr [[A]]) + return vld1_p16_x4(a); +} + +// ALL-LABEL: @test_vld1_p64_x4( +poly64x1x4_t test_vld1_p64_x4(poly64_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x4" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld1x4.v1i64.p0(ptr [[A]]) +// LLVM-DAG: [[VLD1XN_FCA_0_EXTRACT:%.*]] = extractvalue { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } [[VLD1XN]], 0 +// LLVM-DAG: [[VLD1XN_FCA_1_EXTRACT:%.*]] = extractvalue { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } [[VLD1XN]], 1 +// LLVM-DAG: [[VLD1XN_FCA_2_EXTRACT:%.*]] = extractvalue { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } [[VLD1XN]], 2 +// LLVM-DAG: [[VLD1XN_FCA_3_EXTRACT:%.*]] = extractvalue { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } [[VLD1XN]], 3 +// LLVM: [[DOTFCA_0_0_INSERT:%.*]] = insertvalue %struct.poly64x1x4_t poison, <1 x i64> [[VLD1XN_FCA_0_EXTRACT]], 0, 0 +// LLVM: [[DOTFCA_0_1_INSERT:%.*]] = insertvalue %struct.poly64x1x4_t [[DOTFCA_0_0_INSERT]], <1 x i64> [[VLD1XN_FCA_1_EXTRACT]], 0, 1 +// LLVM: [[DOTFCA_0_2_INSERT:%.*]] = insertvalue %struct.poly64x1x4_t [[DOTFCA_0_1_INSERT]], <1 x i64> [[VLD1XN_FCA_2_EXTRACT]], 0, 2 +// LLVM: [[DOTFCA_0_3_INSERT:%.*]] = insertvalue %struct.poly64x1x4_t [[DOTFCA_0_2_INSERT]], <1 x i64> [[VLD1XN_FCA_3_EXTRACT]], 0, 3 +// LLVM: ret %struct.poly64x1x4_t [[DOTFCA_0_3_INSERT]] + return vld1_p64_x4(a); +} + +// ALL-LABEL: @test_vld1_p8_x4( +poly8x8x4_t test_vld1_p8_x4(poly8_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x4" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld1x4.v8i8.p0(ptr [[A]]) + return vld1_p8_x4(a); +} + +// ALL-LABEL: @test_vld1_s16_x4( +int16x4x4_t test_vld1_s16_x4(int16_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x4" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x4.v4i16.p0(ptr [[A]]) + return vld1_s16_x4(a); +} + +// ALL-LABEL: @test_vld1_s32_x4( +int32x2x4_t test_vld1_s32_x4(int32_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x4" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld1x4.v2i32.p0(ptr [[A]]) + return vld1_s32_x4(a); +} + +// ALL-LABEL: @test_vld1_s64_x4( +int64x1x4_t test_vld1_s64_x4(int64_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x4" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld1x4.v1i64.p0(ptr [[A]]) + return vld1_s64_x4(a); +} + +// ALL-LABEL: @test_vld1_s8_x4( +int8x8x4_t test_vld1_s8_x4(int8_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x4" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld1x4.v8i8.p0(ptr [[A]]) + return vld1_s8_x4(a); +} + +// ALL-LABEL: @test_vld1_u16_x4( +uint16x4x4_t test_vld1_u16_x4(uint16_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x4" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x4.v4i16.p0(ptr [[A]]) + return vld1_u16_x4(a); +} + +// ALL-LABEL: @test_vld1_u32_x4( +uint32x2x4_t test_vld1_u32_x4(uint32_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x4" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld1x4.v2i32.p0(ptr [[A]]) + return vld1_u32_x4(a); +} + +// ALL-LABEL: @test_vld1_u64_x4( +uint64x1x4_t test_vld1_u64_x4(uint64_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x4" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld1x4.v1i64.p0(ptr [[A]]) + return vld1_u64_x4(a); +} + +// ALL-LABEL: @test_vld1_u8_x4( +uint8x8x4_t test_vld1_u8_x4(uint8_t const *a) { +// CIR: [[VLD:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.ld1x4" {{.*}} : (!cir.ptr) -> [[STY:!rec_anon_struct[0-9]*]] +// CIR: cir.store align(8) [[VLD]], {{.*}} : [[STY]], !cir.ptr<[[STY]]> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld1x4.v8i8.p0(ptr [[A]]) + return vld1_u8_x4(a); +} + +// ALL-LABEL: @test_vld1q_lane_f16( +float16x8_t test_vld1q_lane_f16(float16_t *a, float16x8_t b) { +// CIR: [[IDX:%.*]] = cir.const #cir.int<7> : !s32i +// CIR: [[SCALAR:%.*]] = cir.load align(2) {{.*}} : !cir.ptr, !cir +// CIR: cir.vec.insert [[SCALAR]], {{.*}}[[IDX]] : !s32i] : !cir.vector<8 x !cir.f16> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]], <8 x half> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = load half, ptr [[A]], align 2 +// LLVM: [[VLD1_LANE:%.*]] = insertelement <8 x half> [[B]], half [[TMP0]], i64 7 +// LLVM: ret <8 x half> [[VLD1_LANE]] + return vld1q_lane_f16(a, b, 7); +} + +// ALL-LABEL: @test_vld1q_lane_f32( +float32x4_t test_vld1q_lane_f32(float32_t *a, float32x4_t b) { +// CIR: [[IDX:%.*]] = cir.const #cir.int<3> : !s32i +// CIR: [[SCALAR:%.*]] = cir.load align(4) {{.*}} : !cir.ptr, !cir +// CIR: cir.vec.insert [[SCALAR]], {{.*}}[[IDX]] : !s32i] : !cir.vector<4 x !cir.float> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]], <4 x float> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = load float, ptr [[A]], align 4 +// LLVM: [[VLD1_LANE:%.*]] = insertelement <4 x float> [[B]], float [[TMP0]], i64 3 +// LLVM: ret <4 x float> [[VLD1_LANE]] + return vld1q_lane_f32(a, b, 3); +} + +// ALL-LABEL: @test_vld1q_lane_f64( +float64x2_t test_vld1q_lane_f64(float64_t *a, float64x2_t b) { +// CIR: [[IDX:%.*]] = cir.const #cir.int<1> : !s32i +// CIR: [[SCALAR:%.*]] = cir.load align(8) {{.*}} : !cir.ptr, !cir +// CIR: cir.vec.insert [[SCALAR]], {{.*}}[[IDX]] : !s32i] : !cir.vector<2 x !cir.double> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]], <2 x double> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = load double, ptr [[A]], align 8 +// LLVM: [[VLD1_LANE:%.*]] = insertelement <2 x double> [[B]], double [[TMP0]], i64 1 +// LLVM: ret <2 x double> [[VLD1_LANE]] + return vld1q_lane_f64(a, b, 1); +} + +// ALL-LABEL: @test_vld1q_lane_mf8( +mfloat8x16_t test_vld1q_lane_mf8(mfloat8_t *a, mfloat8x16_t b) { +// CIR: [[IDX:%.*]] = cir.const #cir.int<15> : !s32i +// CIR: [[SCALAR:%.*]] = cir.load align(1) {{.*}} : !cir.ptr, !u8i +// CIR: cir.vec.insert [[SCALAR]], {{.*}}[[IDX]] : !s32i] : !cir.vector<16 x !u8i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]], <16 x i8> [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 +// LLVM: [[VLD1_LANE:%.*]] = insertelement <16 x i8> [[B]], i8 [[TMP0]], i64 15 +// LLVM: ret <16 x i8> [[VLD1_LANE]] + return vld1q_lane_mf8(a, b, 15); +} + +// ALL-LABEL: @test_vld1q_lane_p16( +poly16x8_t test_vld1q_lane_p16(poly16_t *a, poly16x8_t b) { +// CIR: [[IDX:%.*]] = cir.const #cir.int<7> : !s32i +// CIR: [[SCALAR:%.*]] = cir.load align(2) {{.*}} : !cir.ptr, !s16i +// CIR: cir.vec.insert [[SCALAR]], {{.*}}[[IDX]] : !s32i] : !cir.vector<8 x !s16i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]], <8 x i16> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = load i16, ptr [[A]], align 2 +// LLVM: [[VLD1_LANE:%.*]] = insertelement <8 x i16> [[B]], i16 [[TMP0]], i64 7 +// LLVM: ret <8 x i16> [[VLD1_LANE]] + return vld1q_lane_p16(a, b, 7); +} + +// ALL-LABEL: @test_vld1q_lane_p64( +poly64x2_t test_vld1q_lane_p64(poly64_t *a, poly64x2_t b) { +// CIR: [[IDX:%.*]] = cir.const #cir.int<1> : !s32i +// CIR: [[SCALAR:%.*]] = cir.load align(8) {{.*}} : !cir.ptr, !s64i +// CIR: cir.vec.insert [[SCALAR]], {{.*}}[[IDX]] : !s32i] : !cir.vector<2 x !s64i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]], <2 x i64> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = load i64, ptr [[A]], align 8 +// LLVM: [[VLD1_LANE:%.*]] = insertelement <2 x i64> [[B]], i64 [[TMP0]], i64 1 +// LLVM: ret <2 x i64> [[VLD1_LANE]] + return vld1q_lane_p64(a, b, 1); +} + +// ALL-LABEL: @test_vld1q_lane_p8( +poly8x16_t test_vld1q_lane_p8(poly8_t *a, poly8x16_t b) { +// CIR: [[IDX:%.*]] = cir.const #cir.int<15> : !s32i +// CIR: [[SCALAR:%.*]] = cir.load align(1) {{.*}} : !cir.ptr, !s8i +// CIR: cir.vec.insert [[SCALAR]], {{.*}}[[IDX]] : !s32i] : !cir.vector<16 x !s8i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]], <16 x i8> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 +// LLVM: [[VLD1_LANE:%.*]] = insertelement <16 x i8> [[B]], i8 [[TMP0]], i64 15 +// LLVM: ret <16 x i8> [[VLD1_LANE]] + return vld1q_lane_p8(a, b, 15); +} + +// ALL-LABEL: @test_vld1q_lane_s16( +int16x8_t test_vld1q_lane_s16(int16_t *a, int16x8_t b) { +// CIR: [[IDX:%.*]] = cir.const #cir.int<7> : !s32i +// CIR: [[SCALAR:%.*]] = cir.load align(2) {{.*}} : !cir.ptr, !s16i +// CIR: cir.vec.insert [[SCALAR]], {{.*}}[[IDX]] : !s32i] : !cir.vector<8 x !s16i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]], <8 x i16> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = load i16, ptr [[A]], align 2 +// LLVM: [[VLD1_LANE:%.*]] = insertelement <8 x i16> [[B]], i16 [[TMP0]], i64 7 +// LLVM: ret <8 x i16> [[VLD1_LANE]] + return vld1q_lane_s16(a, b, 7); +} + +// ALL-LABEL: @test_vld1q_lane_s32( +int32x4_t test_vld1q_lane_s32(int32_t *a, int32x4_t b) { +// CIR: [[IDX:%.*]] = cir.const #cir.int<3> : !s32i +// CIR: [[SCALAR:%.*]] = cir.load align(4) {{.*}} : !cir.ptr, !s32i +// CIR: cir.vec.insert [[SCALAR]], {{.*}}[[IDX]] : !s32i] : !cir.vector<4 x !s32i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]], <4 x i32> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 +// LLVM: [[VLD1_LANE:%.*]] = insertelement <4 x i32> [[B]], i32 [[TMP0]], i64 3 +// LLVM: ret <4 x i32> [[VLD1_LANE]] + return vld1q_lane_s32(a, b, 3); +} + +// ALL-LABEL: @test_vld1q_lane_s64( +int64x2_t test_vld1q_lane_s64(int64_t *a, int64x2_t b) { +// CIR: [[IDX:%.*]] = cir.const #cir.int<1> : !s32i +// CIR: [[SCALAR:%.*]] = cir.load align(8) {{.*}} : !cir.ptr, !s64i +// CIR: cir.vec.insert [[SCALAR]], {{.*}}[[IDX]] : !s32i] : !cir.vector<2 x !s64i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]], <2 x i64> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = load i64, ptr [[A]], align 8 +// LLVM: [[VLD1_LANE:%.*]] = insertelement <2 x i64> [[B]], i64 [[TMP0]], i64 1 +// LLVM: ret <2 x i64> [[VLD1_LANE]] + return vld1q_lane_s64(a, b, 1); +} + +// ALL-LABEL: @test_vld1q_lane_s8( +int8x16_t test_vld1q_lane_s8(int8_t *a, int8x16_t b) { +// CIR: [[IDX:%.*]] = cir.const #cir.int<15> : !s32i +// CIR: [[SCALAR:%.*]] = cir.load align(1) {{.*}} : !cir.ptr, !s8i +// CIR: cir.vec.insert [[SCALAR]], {{.*}}[[IDX]] : !s32i] : !cir.vector<16 x !s8i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]], <16 x i8> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 +// LLVM: [[VLD1_LANE:%.*]] = insertelement <16 x i8> [[B]], i8 [[TMP0]], i64 15 +// LLVM: ret <16 x i8> [[VLD1_LANE]] + return vld1q_lane_s8(a, b, 15); +} + +// ALL-LABEL: @test_vld1q_lane_u16( +uint16x8_t test_vld1q_lane_u16(uint16_t *a, uint16x8_t b) { +// CIR: [[IDX:%.*]] = cir.const #cir.int<7> : !s32i +// CIR: [[SCALAR:%.*]] = cir.load align(2) {{.*}} : !cir.ptr, !u16i +// CIR: cir.vec.insert [[SCALAR]], {{.*}}[[IDX]] : !s32i] : !cir.vector<8 x !u16i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]], <8 x i16> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = load i16, ptr [[A]], align 2 +// LLVM: [[VLD1_LANE:%.*]] = insertelement <8 x i16> [[B]], i16 [[TMP0]], i64 7 +// LLVM: ret <8 x i16> [[VLD1_LANE]] + return vld1q_lane_u16(a, b, 7); +} + +// ALL-LABEL: @test_vld1q_lane_u32( +uint32x4_t test_vld1q_lane_u32(uint32_t *a, uint32x4_t b) { +// CIR: [[IDX:%.*]] = cir.const #cir.int<3> : !s32i +// CIR: [[SCALAR:%.*]] = cir.load align(4) {{.*}} : !cir.ptr, !u32i +// CIR: cir.vec.insert [[SCALAR]], {{.*}}[[IDX]] : !s32i] : !cir.vector<4 x !u32i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]], <4 x i32> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 +// LLVM: [[VLD1_LANE:%.*]] = insertelement <4 x i32> [[B]], i32 [[TMP0]], i64 3 +// LLVM: ret <4 x i32> [[VLD1_LANE]] + return vld1q_lane_u32(a, b, 3); +} + +// ALL-LABEL: @test_vld1q_lane_u64( +uint64x2_t test_vld1q_lane_u64(uint64_t *a, uint64x2_t b) { +// CIR: [[IDX:%.*]] = cir.const #cir.int<1> : !s32i +// CIR: [[SCALAR:%.*]] = cir.load align(8) {{.*}} : !cir.ptr, !u64i +// CIR: cir.vec.insert [[SCALAR]], {{.*}}[[IDX]] : !s32i] : !cir.vector<2 x !u64i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]], <2 x i64> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = load i64, ptr [[A]], align 8 +// LLVM: [[VLD1_LANE:%.*]] = insertelement <2 x i64> [[B]], i64 [[TMP0]], i64 1 +// LLVM: ret <2 x i64> [[VLD1_LANE]] + return vld1q_lane_u64(a, b, 1); +} + +// ALL-LABEL: @test_vld1q_lane_u8( +uint8x16_t test_vld1q_lane_u8(uint8_t *a, uint8x16_t b) { +// CIR: [[IDX:%.*]] = cir.const #cir.int<15> : !s32i +// CIR: [[SCALAR:%.*]] = cir.load align(1) {{.*}} : !cir.ptr, !u8i +// CIR: cir.vec.insert [[SCALAR]], {{.*}}[[IDX]] : !s32i] : !cir.vector<16 x !u8i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]], <16 x i8> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 +// LLVM: [[VLD1_LANE:%.*]] = insertelement <16 x i8> [[B]], i8 [[TMP0]], i64 15 +// LLVM: ret <16 x i8> [[VLD1_LANE]] + return vld1q_lane_u8(a, b, 15); +} + +// ALL-LABEL: @test_vld1_lane_f16( +float16x4_t test_vld1_lane_f16(float16_t *a, float16x4_t b) { +// CIR: [[IDX:%.*]] = cir.const #cir.int<3> : !s32i +// CIR: [[SCALAR:%.*]] = cir.load align(2) {{.*}} : !cir.ptr, !cir +// CIR: cir.vec.insert [[SCALAR]], {{.*}}[[IDX]] : !s32i] : !cir.vector<4 x !cir.f16> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]], <4 x half> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = load half, ptr [[A]], align 2 +// LLVM: [[VLD1_LANE:%.*]] = insertelement <4 x half> [[B]], half [[TMP0]], i64 3 +// LLVM: ret <4 x half> [[VLD1_LANE]] + return vld1_lane_f16(a, b, 3); +} + +// ALL-LABEL: @test_vld1_lane_f32( +float32x2_t test_vld1_lane_f32(float32_t *a, float32x2_t b) { +// CIR: [[IDX:%.*]] = cir.const #cir.int<1> : !s32i +// CIR: [[SCALAR:%.*]] = cir.load align(4) {{.*}} : !cir.ptr, !cir +// CIR: cir.vec.insert [[SCALAR]], {{.*}}[[IDX]] : !s32i] : !cir.vector<2 x !cir.float> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]], <2 x float> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = load float, ptr [[A]], align 4 +// LLVM: [[VLD1_LANE:%.*]] = insertelement <2 x float> [[B]], float [[TMP0]], i64 1 +// LLVM: ret <2 x float> [[VLD1_LANE]] + return vld1_lane_f32(a, b, 1); +} + +// ALL-LABEL: @test_vld1_lane_f64( +float64x1_t test_vld1_lane_f64(float64_t *a, float64x1_t b) { +// CIR: [[IDX:%.*]] = cir.const #cir.int<0> : !s32i +// CIR: [[SCALAR:%.*]] = cir.load align(8) {{.*}} : !cir.ptr, !cir +// CIR: cir.vec.insert [[SCALAR]], {{.*}}[[IDX]] : !s32i] : !cir.vector<1 x !cir.double> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]], <1 x double> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = load double, ptr [[A]], align 8 +// LLVM: [[VLD1_LANE:%.*]] = insertelement <1 x double> poison, double [[TMP0]], i64 0 +// LLVM: ret <1 x double> [[VLD1_LANE]] + return vld1_lane_f64(a, b, 0); +} + +// ALL-LABEL: @test_vld1_lane_mf8( +mfloat8x8_t test_vld1_lane_mf8(mfloat8_t *a, mfloat8x8_t b) { +// CIR: [[IDX:%.*]] = cir.const #cir.int<7> : !s32i +// CIR: [[SCALAR:%.*]] = cir.load align(1) {{.*}} : !cir.ptr, !u8i +// CIR: cir.vec.insert [[SCALAR]], {{.*}}[[IDX]] : !s32i] : !cir.vector<8 x !u8i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]], <8 x i8> [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 +// LLVM: [[VLD1_LANE:%.*]] = insertelement <8 x i8> [[B]], i8 [[TMP0]], i64 7 +// LLVM: ret <8 x i8> [[VLD1_LANE]] + return vld1_lane_mf8(a, b, 7); +} + +// ALL-LABEL: @test_vld1_lane_p16( +poly16x4_t test_vld1_lane_p16(poly16_t *a, poly16x4_t b) { +// CIR: [[IDX:%.*]] = cir.const #cir.int<3> : !s32i +// CIR: [[SCALAR:%.*]] = cir.load align(2) {{.*}} : !cir.ptr, !s16i +// CIR: cir.vec.insert [[SCALAR]], {{.*}}[[IDX]] : !s32i] : !cir.vector<4 x !s16i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]], <4 x i16> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = load i16, ptr [[A]], align 2 +// LLVM: [[VLD1_LANE:%.*]] = insertelement <4 x i16> [[B]], i16 [[TMP0]], i64 3 +// LLVM: ret <4 x i16> [[VLD1_LANE]] + return vld1_lane_p16(a, b, 3); +} + +// ALL-LABEL: @test_vld1_lane_p64( +poly64x1_t test_vld1_lane_p64(poly64_t *a, poly64x1_t b) { +// CIR: [[IDX:%.*]] = cir.const #cir.int<0> : !s32i +// CIR: [[SCALAR:%.*]] = cir.load align(8) {{.*}} : !cir.ptr, !s64i +// CIR: cir.vec.insert [[SCALAR]], {{.*}}[[IDX]] : !s32i] : !cir.vector<1 x !s64i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]], <1 x i64> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = load i64, ptr [[A]], align 8 +// LLVM: [[VLD1_LANE:%.*]] = insertelement <1 x i64> poison, i64 [[TMP0]], i64 0 +// LLVM: ret <1 x i64> [[VLD1_LANE]] + return vld1_lane_p64(a, b, 0); +} + +// ALL-LABEL: @test_vld1_lane_p8( +poly8x8_t test_vld1_lane_p8(poly8_t *a, poly8x8_t b) { +// CIR: [[IDX:%.*]] = cir.const #cir.int<7> : !s32i +// CIR: [[SCALAR:%.*]] = cir.load align(1) {{.*}} : !cir.ptr, !s8i +// CIR: cir.vec.insert [[SCALAR]], {{.*}}[[IDX]] : !s32i] : !cir.vector<8 x !s8i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]], <8 x i8> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 +// LLVM: [[VLD1_LANE:%.*]] = insertelement <8 x i8> [[B]], i8 [[TMP0]], i64 7 +// LLVM: ret <8 x i8> [[VLD1_LANE]] + return vld1_lane_p8(a, b, 7); +} + +// ALL-LABEL: @test_vld1_lane_s16( +int16x4_t test_vld1_lane_s16(int16_t *a, int16x4_t b) { +// CIR: [[IDX:%.*]] = cir.const #cir.int<3> : !s32i +// CIR: [[SCALAR:%.*]] = cir.load align(2) {{.*}} : !cir.ptr, !s16i +// CIR: cir.vec.insert [[SCALAR]], {{.*}}[[IDX]] : !s32i] : !cir.vector<4 x !s16i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]], <4 x i16> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = load i16, ptr [[A]], align 2 +// LLVM: [[VLD1_LANE:%.*]] = insertelement <4 x i16> [[B]], i16 [[TMP0]], i64 3 +// LLVM: ret <4 x i16> [[VLD1_LANE]] + return vld1_lane_s16(a, b, 3); +} + +// ALL-LABEL: @test_vld1_lane_s32( +int32x2_t test_vld1_lane_s32(int32_t *a, int32x2_t b) { +// CIR: [[IDX:%.*]] = cir.const #cir.int<1> : !s32i +// CIR: [[SCALAR:%.*]] = cir.load align(4) {{.*}} : !cir.ptr, !s32i +// CIR: cir.vec.insert [[SCALAR]], {{.*}}[[IDX]] : !s32i] : !cir.vector<2 x !s32i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]], <2 x i32> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 +// LLVM: [[VLD1_LANE:%.*]] = insertelement <2 x i32> [[B]], i32 [[TMP0]], i64 1 +// LLVM: ret <2 x i32> [[VLD1_LANE]] + return vld1_lane_s32(a, b, 1); +} + +// ALL-LABEL: @test_vld1_lane_s64( +int64x1_t test_vld1_lane_s64(int64_t *a, int64x1_t b) { +// CIR: [[IDX:%.*]] = cir.const #cir.int<0> : !s32i +// CIR: [[SCALAR:%.*]] = cir.load align(8) {{.*}} : !cir.ptr, !s64i +// CIR: cir.vec.insert [[SCALAR]], {{.*}}[[IDX]] : !s32i] : !cir.vector<1 x !s64i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]], <1 x i64> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = load i64, ptr [[A]], align 8 +// LLVM: [[VLD1_LANE:%.*]] = insertelement <1 x i64> poison, i64 [[TMP0]], i64 0 +// LLVM: ret <1 x i64> [[VLD1_LANE]] + return vld1_lane_s64(a, b, 0); +} + +// ALL-LABEL: @test_vld1_lane_s8( +int8x8_t test_vld1_lane_s8(int8_t *a, int8x8_t b) { +// CIR: [[IDX:%.*]] = cir.const #cir.int<7> : !s32i +// CIR: [[SCALAR:%.*]] = cir.load align(1) {{.*}} : !cir.ptr, !s8i +// CIR: cir.vec.insert [[SCALAR]], {{.*}}[[IDX]] : !s32i] : !cir.vector<8 x !s8i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]], <8 x i8> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 +// LLVM: [[VLD1_LANE:%.*]] = insertelement <8 x i8> [[B]], i8 [[TMP0]], i64 7 +// LLVM: ret <8 x i8> [[VLD1_LANE]] + return vld1_lane_s8(a, b, 7); +} + +// ALL-LABEL: @test_vld1_lane_u16( +uint16x4_t test_vld1_lane_u16(uint16_t *a, uint16x4_t b) { +// CIR: [[IDX:%.*]] = cir.const #cir.int<3> : !s32i +// CIR: [[SCALAR:%.*]] = cir.load align(2) {{.*}} : !cir.ptr, !u16i +// CIR: cir.vec.insert [[SCALAR]], {{.*}}[[IDX]] : !s32i] : !cir.vector<4 x !u16i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]], <4 x i16> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = load i16, ptr [[A]], align 2 +// LLVM: [[VLD1_LANE:%.*]] = insertelement <4 x i16> [[B]], i16 [[TMP0]], i64 3 +// LLVM: ret <4 x i16> [[VLD1_LANE]] + return vld1_lane_u16(a, b, 3); +} + +// ALL-LABEL: @test_vld1_lane_u32( +uint32x2_t test_vld1_lane_u32(uint32_t *a, uint32x2_t b) { +// CIR: [[IDX:%.*]] = cir.const #cir.int<1> : !s32i +// CIR: [[SCALAR:%.*]] = cir.load align(4) {{.*}} : !cir.ptr, !u32i +// CIR: cir.vec.insert [[SCALAR]], {{.*}}[[IDX]] : !s32i] : !cir.vector<2 x !u32i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]], <2 x i32> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 +// LLVM: [[VLD1_LANE:%.*]] = insertelement <2 x i32> [[B]], i32 [[TMP0]], i64 1 +// LLVM: ret <2 x i32> [[VLD1_LANE]] + return vld1_lane_u32(a, b, 1); +} + +// ALL-LABEL: @test_vld1_lane_u64( +uint64x1_t test_vld1_lane_u64(uint64_t *a, uint64x1_t b) { +// CIR: [[IDX:%.*]] = cir.const #cir.int<0> : !s32i +// CIR: [[SCALAR:%.*]] = cir.load align(8) {{.*}} : !cir.ptr, !u64i +// CIR: cir.vec.insert [[SCALAR]], {{.*}}[[IDX]] : !s32i] : !cir.vector<1 x !u64i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]], <1 x i64> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = load i64, ptr [[A]], align 8 +// LLVM: [[VLD1_LANE:%.*]] = insertelement <1 x i64> poison, i64 [[TMP0]], i64 0 +// LLVM: ret <1 x i64> [[VLD1_LANE]] + return vld1_lane_u64(a, b, 0); +} + +// ALL-LABEL: @test_vld1_lane_u8( +uint8x8_t test_vld1_lane_u8(uint8_t *a, uint8x8_t b) { +// CIR: [[IDX:%.*]] = cir.const #cir.int<7> : !s32i +// CIR: [[SCALAR:%.*]] = cir.load align(1) {{.*}} : !cir.ptr, !u8i +// CIR: cir.vec.insert [[SCALAR]], {{.*}}[[IDX]] : !s32i] : !cir.vector<8 x !u8i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]], <8 x i8> {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 +// LLVM: [[VLD1_LANE:%.*]] = insertelement <8 x i8> [[B]], i8 [[TMP0]], i64 7 +// LLVM: ret <8 x i8> [[VLD1_LANE]] + return vld1_lane_u8(a, b, 7); +} + +// ALL-LABEL: @test_vld1q_dup_f16( +float16x8_t test_vld1q_dup_f16(float16_t *a) { +// CIR: cir.load align(16) {{.*}} : !cir.ptr>, !cir.vector<8 x !cir.f16> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load half, ptr [[A]], align 2 +// LLVM: [[TMP1:%.*]] = insertelement <8 x half> poison, half [[TMP0]], i64 0 +// LLVM: [[LANE:%.*]] = shufflevector <8 x half> [[TMP1]], <8 x half> poison, <8 x i32> zeroinitializer +// LLVM: ret <8 x half> [[LANE]] + return vld1q_dup_f16(a); +} + +// ALL-LABEL: @test_vld1q_dup_f32( +float32x4_t test_vld1q_dup_f32(float32_t *a) { +// CIR: cir.load align(16) {{.*}} : !cir.ptr>, !cir.vector<4 x !cir.float> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load float, ptr [[A]], align 4 +// LLVM: [[TMP1:%.*]] = insertelement <4 x float> poison, float [[TMP0]], i64 0 +// LLVM: [[LANE:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <4 x i32> zeroinitializer +// LLVM: ret <4 x float> [[LANE]] + return vld1q_dup_f32(a); +} + +// ALL-LABEL: @test_vld1q_dup_f64( +float64x2_t test_vld1q_dup_f64(float64_t *a) { +// CIR: cir.load align(16) {{.*}} : !cir.ptr>, !cir.vector<2 x !cir.double> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load double, ptr [[A]], align 8 +// LLVM: [[TMP1:%.*]] = insertelement <2 x double> poison, double [[TMP0]], i64 0 +// LLVM: [[LANE:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> poison, <2 x i32> zeroinitializer +// LLVM: ret <2 x double> [[LANE]] + return vld1q_dup_f64(a); +} + +// ALL-LABEL: @test_vld1q_dup_mf8( +mfloat8x16_t test_vld1q_dup_mf8(mfloat8_t *a) { +// CIR: [[SCALAR:%.*]] = cir.load align(1) {{.*}} : !cir.ptr, !u8i +// CIR: cir.vec.splat [[SCALAR]] : !u8i, !cir.vector<16 x !u8i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 +// LLVM: [[TMP1:%.*]] = insertelement <16 x i8> poison, i8 [[TMP0]], i64 0 +// LLVM: [[LANE:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> poison, <16 x i32> zeroinitializer +// LLVM: ret <16 x i8> [[LANE]] + return vld1q_dup_mf8(a); +} + +// ALL-LABEL: @test_vld1q_dup_p16( +poly16x8_t test_vld1q_dup_p16(poly16_t *a) { +// CIR: [[SCALAR:%.*]] = cir.load align(2) {{.*}} : !cir.ptr, !s16i +// CIR: cir.vec.splat [[SCALAR]] : !s16i, !cir.vector<8 x !s16i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load i16, ptr [[A]], align 2 +// LLVM: [[TMP1:%.*]] = insertelement <8 x i16> poison, i16 [[TMP0]], i64 0 +// LLVM: [[LANE:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> poison, <8 x i32> zeroinitializer +// LLVM: ret <8 x i16> [[LANE]] + return vld1q_dup_p16(a); +} + +// ALL-LABEL: @test_vld1q_dup_p64( +poly64x2_t test_vld1q_dup_p64(poly64_t *a) { +// CIR: [[SCALAR:%.*]] = cir.load align(8) {{.*}} : !cir.ptr, !s64i +// CIR: cir.vec.splat [[SCALAR]] : !s64i, !cir.vector<2 x !s64i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load i64, ptr [[A]], align 8 +// LLVM: [[TMP1:%.*]] = insertelement <2 x i64> poison, i64 [[TMP0]], i64 0 +// LLVM: [[LANE:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> poison, <2 x i32> zeroinitializer +// LLVM: ret <2 x i64> [[LANE]] + return vld1q_dup_p64(a); +} + +// ALL-LABEL: @test_vld1q_dup_p8( +poly8x16_t test_vld1q_dup_p8(poly8_t *a) { +// CIR: [[SCALAR:%.*]] = cir.load align(1) {{.*}} : !cir.ptr, !s8i +// CIR: cir.vec.splat [[SCALAR]] : !s8i, !cir.vector<16 x !s8i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 +// LLVM: [[TMP1:%.*]] = insertelement <16 x i8> poison, i8 [[TMP0]], i64 0 +// LLVM: [[LANE:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> poison, <16 x i32> zeroinitializer +// LLVM: ret <16 x i8> [[LANE]] + return vld1q_dup_p8(a); +} + +// ALL-LABEL: @test_vld1q_dup_s16( +int16x8_t test_vld1q_dup_s16(int16_t *a) { +// CIR: [[SCALAR:%.*]] = cir.load align(2) {{.*}} : !cir.ptr, !s16i +// CIR: cir.vec.splat [[SCALAR]] : !s16i, !cir.vector<8 x !s16i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load i16, ptr [[A]], align 2 +// LLVM: [[TMP1:%.*]] = insertelement <8 x i16> poison, i16 [[TMP0]], i64 0 +// LLVM: [[LANE:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> poison, <8 x i32> zeroinitializer +// LLVM: ret <8 x i16> [[LANE]] + return vld1q_dup_s16(a); +} + +// ALL-LABEL: @test_vld1q_dup_s32( +int32x4_t test_vld1q_dup_s32(int32_t *a) { +// CIR: [[SCALAR:%.*]] = cir.load align(4) {{.*}} : !cir.ptr, !s32i +// CIR: cir.vec.splat [[SCALAR]] : !s32i, !cir.vector<4 x !s32i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 +// LLVM: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i64 0 +// LLVM: [[LANE:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> zeroinitializer +// LLVM: ret <4 x i32> [[LANE]] + return vld1q_dup_s32(a); +} + +// ALL-LABEL: @test_vld1q_dup_s64( +int64x2_t test_vld1q_dup_s64(int64_t *a) { +// CIR: [[SCALAR:%.*]] = cir.load align(8) {{.*}} : !cir.ptr, !s64i +// CIR: cir.vec.splat [[SCALAR]] : !s64i, !cir.vector<2 x !s64i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load i64, ptr [[A]], align 8 +// LLVM: [[TMP1:%.*]] = insertelement <2 x i64> poison, i64 [[TMP0]], i64 0 +// LLVM: [[LANE:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> poison, <2 x i32> zeroinitializer +// LLVM: ret <2 x i64> [[LANE]] + return vld1q_dup_s64(a); +} + +// ALL-LABEL: @test_vld1q_dup_s8( +int8x16_t test_vld1q_dup_s8(int8_t *a) { +// CIR: [[SCALAR:%.*]] = cir.load align(1) {{.*}} : !cir.ptr, !s8i +// CIR: cir.vec.splat [[SCALAR]] : !s8i, !cir.vector<16 x !s8i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 +// LLVM: [[TMP1:%.*]] = insertelement <16 x i8> poison, i8 [[TMP0]], i64 0 +// LLVM: [[LANE:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> poison, <16 x i32> zeroinitializer +// LLVM: ret <16 x i8> [[LANE]] + return vld1q_dup_s8(a); +} + +// ALL-LABEL: @test_vld1q_dup_u16( +uint16x8_t test_vld1q_dup_u16(uint16_t *a) { +// CIR: [[SCALAR:%.*]] = cir.load align(2) {{.*}} : !cir.ptr, !u16i +// CIR: cir.vec.splat [[SCALAR]] : !u16i, !cir.vector<8 x !u16i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load i16, ptr [[A]], align 2 +// LLVM: [[TMP1:%.*]] = insertelement <8 x i16> poison, i16 [[TMP0]], i64 0 +// LLVM: [[LANE:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> poison, <8 x i32> zeroinitializer +// LLVM: ret <8 x i16> [[LANE]] + return vld1q_dup_u16(a); +} + +// ALL-LABEL: @test_vld1q_dup_u32( +uint32x4_t test_vld1q_dup_u32(uint32_t *a) { +// CIR: [[SCALAR:%.*]] = cir.load align(4) {{.*}} : !cir.ptr, !u32i +// CIR: cir.vec.splat [[SCALAR]] : !u32i, !cir.vector<4 x !u32i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 +// LLVM: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i64 0 +// LLVM: [[LANE:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> zeroinitializer +// LLVM: ret <4 x i32> [[LANE]] + return vld1q_dup_u32(a); +} + +// ALL-LABEL: @test_vld1q_dup_u64( +uint64x2_t test_vld1q_dup_u64(uint64_t *a) { +// CIR: [[SCALAR:%.*]] = cir.load align(8) {{.*}} : !cir.ptr, !u64i +// CIR: cir.vec.splat [[SCALAR]] : !u64i, !cir.vector<2 x !u64i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load i64, ptr [[A]], align 8 +// LLVM: [[TMP1:%.*]] = insertelement <2 x i64> poison, i64 [[TMP0]], i64 0 +// LLVM: [[LANE:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> poison, <2 x i32> zeroinitializer +// LLVM: ret <2 x i64> [[LANE]] + return vld1q_dup_u64(a); +} + +// ALL-LABEL: @test_vld1q_dup_u8( +uint8x16_t test_vld1q_dup_u8(uint8_t *a) { +// CIR: [[SCALAR:%.*]] = cir.load align(1) {{.*}} : !cir.ptr, !u8i +// CIR: cir.vec.splat [[SCALAR]] : !u8i, !cir.vector<16 x !u8i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 +// LLVM: [[TMP1:%.*]] = insertelement <16 x i8> poison, i8 [[TMP0]], i64 0 +// LLVM: [[LANE:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> poison, <16 x i32> zeroinitializer +// LLVM: ret <16 x i8> [[LANE]] + return vld1q_dup_u8(a); +} + +// ALL-LABEL: @test_vld1_dup_f16( +float16x4_t test_vld1_dup_f16(float16_t *a) { +// CIR: cir.load align(8) {{.*}} : !cir.ptr>, !cir.vector<4 x !cir.f16> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load half, ptr [[A]], align 2 +// LLVM: [[TMP1:%.*]] = insertelement <4 x half> poison, half [[TMP0]], i64 0 +// LLVM: [[LANE:%.*]] = shufflevector <4 x half> [[TMP1]], <4 x half> poison, <4 x i32> zeroinitializer +// LLVM: ret <4 x half> [[LANE]] + return vld1_dup_f16(a); +} + +// ALL-LABEL: @test_vld1_dup_f32( +float32x2_t test_vld1_dup_f32(float32_t *a) { +// CIR: cir.load align(8) {{.*}} : !cir.ptr>, !cir.vector<2 x !cir.float> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load float, ptr [[A]], align 4 +// LLVM: [[TMP1:%.*]] = insertelement <2 x float> poison, float [[TMP0]], i64 0 +// LLVM: [[LANE:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <2 x i32> zeroinitializer +// LLVM: ret <2 x float> [[LANE]] + return vld1_dup_f32(a); +} + +// ALL-LABEL: @test_vld1_dup_f64( +float64x1_t test_vld1_dup_f64(float64_t *a) { +// CIR: cir.load align(8) {{.*}} : !cir.ptr>, !cir.vector<1 x !cir.double> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load double, ptr [[A]], align 8 +// LLVM: [[TMP1:%.*]] = insertelement <1 x double> poison, double [[TMP0]], i64 0 +// LLVM: ret <1 x double> [[TMP1]] + return vld1_dup_f64(a); +} + +// ALL-LABEL: @test_vld1_dup_mf8( +mfloat8x8_t test_vld1_dup_mf8(mfloat8_t *a) { +// CIR: [[SCALAR:%.*]] = cir.load align(1) {{.*}} : !cir.ptr, !u8i +// CIR: cir.vec.splat [[SCALAR]] : !u8i, !cir.vector<8 x !u8i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 +// LLVM: [[TMP1:%.*]] = insertelement <8 x i8> poison, i8 [[TMP0]], i64 0 +// LLVM: [[LANE:%.*]] = shufflevector <8 x i8> [[TMP1]], <8 x i8> poison, <8 x i32> zeroinitializer +// LLVM: ret <8 x i8> [[LANE]] + return vld1_dup_mf8(a); +} + +// ALL-LABEL: @test_vld1_dup_p16( +poly16x4_t test_vld1_dup_p16(poly16_t *a) { +// CIR: [[SCALAR:%.*]] = cir.load align(2) {{.*}} : !cir.ptr, !s16i +// CIR: cir.vec.splat [[SCALAR]] : !s16i, !cir.vector<4 x !s16i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load i16, ptr [[A]], align 2 +// LLVM: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[TMP0]], i64 0 +// LLVM: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> poison, <4 x i32> zeroinitializer +// LLVM: ret <4 x i16> [[LANE]] + return vld1_dup_p16(a); +} + +// ALL-LABEL: @test_vld1_dup_p64( +poly64x1_t test_vld1_dup_p64(poly64_t *a) { +// CIR: [[SCALAR:%.*]] = cir.load align(8) {{.*}} : !cir.ptr, !s64i +// CIR: cir.vec.splat [[SCALAR]] : !s64i, !cir.vector<1 x !s64i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load i64, ptr [[A]], align 8 +// LLVM: [[TMP1:%.*]] = insertelement <1 x i64> poison, i64 [[TMP0]], i64 0 +// LLVM: ret <1 x i64> [[TMP1]] + return vld1_dup_p64(a); +} + +// ALL-LABEL: @test_vld1_dup_p8( +poly8x8_t test_vld1_dup_p8(poly8_t *a) { +// CIR: [[SCALAR:%.*]] = cir.load align(1) {{.*}} : !cir.ptr, !s8i +// CIR: cir.vec.splat [[SCALAR]] : !s8i, !cir.vector<8 x !s8i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 +// LLVM: [[TMP1:%.*]] = insertelement <8 x i8> poison, i8 [[TMP0]], i64 0 +// LLVM: [[LANE:%.*]] = shufflevector <8 x i8> [[TMP1]], <8 x i8> poison, <8 x i32> zeroinitializer +// LLVM: ret <8 x i8> [[LANE]] + return vld1_dup_p8(a); +} + +// ALL-LABEL: @test_vld1_dup_s16( +int16x4_t test_vld1_dup_s16(int16_t *a) { +// CIR: [[SCALAR:%.*]] = cir.load align(2) {{.*}} : !cir.ptr, !s16i +// CIR: cir.vec.splat [[SCALAR]] : !s16i, !cir.vector<4 x !s16i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load i16, ptr [[A]], align 2 +// LLVM: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[TMP0]], i64 0 +// LLVM: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> poison, <4 x i32> zeroinitializer +// LLVM: ret <4 x i16> [[LANE]] + return vld1_dup_s16(a); +} + +// ALL-LABEL: @test_vld1_dup_s32( +int32x2_t test_vld1_dup_s32(int32_t *a) { +// CIR: [[SCALAR:%.*]] = cir.load align(4) {{.*}} : !cir.ptr, !s32i +// CIR: cir.vec.splat [[SCALAR]] : !s32i, !cir.vector<2 x !s32i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 +// LLVM: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[TMP0]], i64 0 +// LLVM: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <2 x i32> zeroinitializer +// LLVM: ret <2 x i32> [[LANE]] + return vld1_dup_s32(a); +} + +// ALL-LABEL: @test_vld1_dup_s64( +int64x1_t test_vld1_dup_s64(int64_t *a) { +// CIR: [[SCALAR:%.*]] = cir.load align(8) {{.*}} : !cir.ptr, !s64i +// CIR: cir.vec.splat [[SCALAR]] : !s64i, !cir.vector<1 x !s64i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load i64, ptr [[A]], align 8 +// LLVM: [[TMP1:%.*]] = insertelement <1 x i64> poison, i64 [[TMP0]], i64 0 +// LLVM: ret <1 x i64> [[TMP1]] + return vld1_dup_s64(a); +} + +// ALL-LABEL: @test_vld1_dup_s8( +int8x8_t test_vld1_dup_s8(int8_t *a) { +// CIR: [[SCALAR:%.*]] = cir.load align(1) {{.*}} : !cir.ptr, !s8i +// CIR: cir.vec.splat [[SCALAR]] : !s8i, !cir.vector<8 x !s8i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 +// LLVM: [[TMP1:%.*]] = insertelement <8 x i8> poison, i8 [[TMP0]], i64 0 +// LLVM: [[LANE:%.*]] = shufflevector <8 x i8> [[TMP1]], <8 x i8> poison, <8 x i32> zeroinitializer +// LLVM: ret <8 x i8> [[LANE]] + return vld1_dup_s8(a); +} + +// ALL-LABEL: @test_vld1_dup_u16( +uint16x4_t test_vld1_dup_u16(uint16_t *a) { +// CIR: [[SCALAR:%.*]] = cir.load align(2) {{.*}} : !cir.ptr, !u16i +// CIR: cir.vec.splat [[SCALAR]] : !u16i, !cir.vector<4 x !u16i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load i16, ptr [[A]], align 2 +// LLVM: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[TMP0]], i64 0 +// LLVM: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> poison, <4 x i32> zeroinitializer +// LLVM: ret <4 x i16> [[LANE]] + return vld1_dup_u16(a); +} + +// ALL-LABEL: @test_vld1_dup_u32( +uint32x2_t test_vld1_dup_u32(uint32_t *a) { +// CIR: [[SCALAR:%.*]] = cir.load align(4) {{.*}} : !cir.ptr, !u32i +// CIR: cir.vec.splat [[SCALAR]] : !u32i, !cir.vector<2 x !u32i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load i32, ptr [[A]], align 4 +// LLVM: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[TMP0]], i64 0 +// LLVM: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <2 x i32> zeroinitializer +// LLVM: ret <2 x i32> [[LANE]] + return vld1_dup_u32(a); +} + +// ALL-LABEL: @test_vld1_dup_u64( +uint64x1_t test_vld1_dup_u64(uint64_t *a) { +// CIR: [[SCALAR:%.*]] = cir.load align(8) {{.*}} : !cir.ptr, !u64i +// CIR: cir.vec.splat [[SCALAR]] : !u64i, !cir.vector<1 x !u64i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load i64, ptr [[A]], align 8 +// LLVM: [[TMP1:%.*]] = insertelement <1 x i64> poison, i64 [[TMP0]], i64 0 +// LLVM: ret <1 x i64> [[TMP1]] + return vld1_dup_u64(a); +} + +// ALL-LABEL: @test_vld1_dup_u8( +uint8x8_t test_vld1_dup_u8(uint8_t *a) { +// CIR: [[SCALAR:%.*]] = cir.load align(1) {{.*}} : !cir.ptr, !u8i +// CIR: cir.vec.splat [[SCALAR]] : !u8i, !cir.vector<8 x !u8i> + +// LLVM-SAME: ptr {{.*}} [[A:%.*]]) +// LLVM: [[TMP0:%.*]] = load i8, ptr [[A]], align 1 +// LLVM: [[TMP1:%.*]] = insertelement <8 x i8> poison, i8 [[TMP0]], i64 0 +// LLVM: [[LANE:%.*]] = shufflevector <8 x i8> [[TMP1]], <8 x i8> poison, <8 x i32> zeroinitializer +// LLVM: ret <8 x i8> [[LANE]] + return vld1_dup_u8(a); +} diff --git a/clang/test/CodeGen/AArch64/poly64.c b/clang/test/CodeGen/AArch64/poly64.c index 233d70b537ac2..3e8bd82c963ff 100644 --- a/clang/test/CodeGen/AArch64/poly64.c +++ b/clang/test/CodeGen/AArch64/poly64.c @@ -192,26 +192,6 @@ poly64x2_t test_vcombine_p64(poly64x1_t low, poly64x1_t high) { return vcombine_p64(low, high); } -// CHECK-LABEL: define dso_local <1 x i64> @test_vld1_p64( -// CHECK-SAME: ptr noundef [[PTR:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <1 x i64>, ptr [[PTR]], align 8 -// CHECK-NEXT: ret <1 x i64> [[TMP0]] -// -poly64x1_t test_vld1_p64(poly64_t const * ptr) { - return vld1_p64(ptr); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vld1q_p64( -// CHECK-SAME: ptr noundef [[PTR:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr [[PTR]], align 8 -// CHECK-NEXT: ret <2 x i64> [[TMP0]] -// -poly64x2_t test_vld1q_p64(poly64_t const * ptr) { - return vld1q_p64(ptr); -} - // CHECK-LABEL: define dso_local %struct.poly64x1x2_t @test_vld2_p64( // CHECK-SAME: ptr noundef [[PTR:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] diff --git a/clang/test/CodeGen/arm-neon-vld.c b/clang/test/CodeGen/arm-neon-vld.c index 4ea44777345e3..2ec6c47815bb8 100644 --- a/clang/test/CodeGen/arm-neon-vld.c +++ b/clang/test/CodeGen/arm-neon-vld.c @@ -7,1010 +7,799 @@ // REQUIRES: aarch64-registered-target || arm-registered-target +// NOTE: the vld1_x2/x3/x4 and vld1q_x2/x3/x4 tests below are duplicated in +// clang/test/CodeGen/AArch64/neon/load.c; this file covers armv8 (32-bit) +// codegen for these intrinsics. The vld2/vld3/vld4 tests further down still +// cover both arm64 and armv8. + #include -// CHECK-LABEL: @test_vld1_f16_x2( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float16x4x2_t, align 8 +// CHECK-A32-LABEL: @test_vld1_f16_x2( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.float16x4x2_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.float16x4x2_t, align 8 -// CHECK: [[VLD1XN:%.*]] = call { <4 x [[HALF:half|i16]]>, <4 x [[HALF]]> } @llvm.{{aarch64.neon.ld1x2.v4f16.p0|arm.neon.vld1x2.v4i16.p0}}(ptr %a) -// CHECK: store { <4 x [[HALF]]>, <4 x [[HALF]]> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 16, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.float16x4x2_t, ptr [[RETVAL]], align 8 -// CHECK-A64: ret %struct.float16x4x2_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.float16x4x2_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.arm.neon.vld1x2.v4i16.p0(ptr %a) +// CHECK-A32: store { <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 16, i1 false) // CHECK-A32: ret void float16x4x2_t test_vld1_f16_x2(float16_t const *a) { return vld1_f16_x2(a); } -// CHECK-LABEL: @test_vld1_f16_x3( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float16x4x3_t, align 8 +// CHECK-A32-LABEL: @test_vld1_f16_x3( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.float16x4x3_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.float16x4x3_t, align 8 -// CHECK: [[VLD1XN:%.*]] = call { <4 x [[HALF:half|i16]]>, <4 x [[HALF]]>, <4 x [[HALF]]> } @llvm.{{aarch64.neon.ld1x3.v4f16.p0|arm.neon.vld1x3.v4i16.p0}}(ptr %a) -// CHECK: store { <4 x [[HALF]]>, <4 x [[HALF]]>, <4 x [[HALF]]> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 24, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.float16x4x3_t, ptr [[RETVAL]], align 8 -// CHECK-A64: ret %struct.float16x4x3_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.float16x4x3_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld1x3.v4i16.p0(ptr %a) +// CHECK-A32: store { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 24, i1 false) // CHECK-A32: ret void float16x4x3_t test_vld1_f16_x3(float16_t const *a) { return vld1_f16_x3(a); } -// CHECK-LABEL: @test_vld1_f16_x4( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float16x4x4_t, align 8 +// CHECK-A32-LABEL: @test_vld1_f16_x4( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.float16x4x4_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.float16x4x4_t, align 8 -// CHECK: [[VLD1XN:%.*]] = call { <4 x [[HALF:half|i16]]>, <4 x [[HALF]]>, <4 x [[HALF]]>, <4 x [[HALF]]> } @llvm.{{aarch64.neon.ld1x4.v4f16.p0|arm.neon.vld1x4.v4i16.p0}}(ptr %a) -// CHECK: store { <4 x [[HALF]]>, <4 x [[HALF]]>, <4 x [[HALF]]>, <4 x [[HALF]]> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 32, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.float16x4x4_t, ptr [[RETVAL]], align 8 -// CHECK-A64: ret %struct.float16x4x4_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.float16x4x4_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld1x4.v4i16.p0(ptr %a) +// CHECK-A32: store { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 32, i1 false) // CHECK-A32: ret void float16x4x4_t test_vld1_f16_x4(float16_t const *a) { return vld1_f16_x4(a); } -// CHECK-LABEL: @test_vld1_f32_x2( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float32x2x2_t, align 8 +// CHECK-A32-LABEL: @test_vld1_f32_x2( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.float32x2x2_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.float32x2x2_t, align 8 -// CHECK: [[VLD1XN:%.*]] = call { <2 x float>, <2 x float> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v2f32.p0(ptr %a) -// CHECK: store { <2 x float>, <2 x float> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 16, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.float32x2x2_t, ptr [[RETVAL]], align 8 -// CHECK-A64: ret %struct.float32x2x2_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.float32x2x2_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <2 x float>, <2 x float> } @llvm.arm.neon.vld1x2.v2f32.p0(ptr %a) +// CHECK-A32: store { <2 x float>, <2 x float> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 16, i1 false) // CHECK-A32: ret void float32x2x2_t test_vld1_f32_x2(float32_t const *a) { return vld1_f32_x2(a); } -// CHECK-LABEL: @test_vld1_f32_x3( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float32x2x3_t, align 8 +// CHECK-A32-LABEL: @test_vld1_f32_x3( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.float32x2x3_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.float32x2x3_t, align 8 -// CHECK: [[VLD1XN:%.*]] = call { <2 x float>, <2 x float>, <2 x float> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v2f32.p0(ptr %a) -// CHECK: store { <2 x float>, <2 x float>, <2 x float> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 24, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.float32x2x3_t, ptr [[RETVAL]], align 8 -// CHECK-A64: ret %struct.float32x2x3_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.float32x2x3_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <2 x float>, <2 x float>, <2 x float> } @llvm.arm.neon.vld1x3.v2f32.p0(ptr %a) +// CHECK-A32: store { <2 x float>, <2 x float>, <2 x float> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 24, i1 false) float32x2x3_t test_vld1_f32_x3(float32_t const *a) { return vld1_f32_x3(a); } -// CHECK-LABEL: @test_vld1_f32_x4( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float32x2x4_t, align 8 +// CHECK-A32-LABEL: @test_vld1_f32_x4( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.float32x2x4_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.float32x2x4_t, align 8 -// CHECK: [[VLD1XN:%.*]] = call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v2f32.p0(ptr %a) -// CHECK: store { <2 x float>, <2 x float>, <2 x float>, <2 x float> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 32, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.float32x2x4_t, ptr [[RETVAL]], align 8 -// CHECK-A64: ret %struct.float32x2x4_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.float32x2x4_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.arm.neon.vld1x4.v2f32.p0(ptr %a) +// CHECK-A32: store { <2 x float>, <2 x float>, <2 x float>, <2 x float> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 32, i1 false) // CHECK-A32: ret void float32x2x4_t test_vld1_f32_x4(float32_t const *a) { return vld1_f32_x4(a); } -// CHECK-LABEL: @test_vld1_p16_x2( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly16x4x2_t, align 8 +// CHECK-A32-LABEL: @test_vld1_p16_x2( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.poly16x4x2_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.poly16x4x2_t, align 8 -// CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v4i16.p0(ptr %a) -// CHECK: store { <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 16, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.poly16x4x2_t, ptr [[RETVAL]], align 8 -// CHECK-A64: ret %struct.poly16x4x2_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.poly16x4x2_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.arm.neon.vld1x2.v4i16.p0(ptr %a) +// CHECK-A32: store { <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 16, i1 false) // CHECK-A32: ret void poly16x4x2_t test_vld1_p16_x2(poly16_t const *a) { return vld1_p16_x2(a); } -// CHECK-LABEL: @test_vld1_p16_x3( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly16x4x3_t, align 8 +// CHECK-A32-LABEL: @test_vld1_p16_x3( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.poly16x4x3_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.poly16x4x3_t, align 8 -// CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v4i16.p0(ptr %a) -// CHECK: store { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 24, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.poly16x4x3_t, ptr [[RETVAL]], align 8 -// CHECK-A64: ret %struct.poly16x4x3_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.poly16x4x3_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld1x3.v4i16.p0(ptr %a) +// CHECK-A32: store { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 24, i1 false) // CHECK-A32: ret void poly16x4x3_t test_vld1_p16_x3(poly16_t const *a) { return vld1_p16_x3(a); } -// CHECK-LABEL: @test_vld1_p16_x4( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly16x4x4_t, align 8 +// CHECK-A32-LABEL: @test_vld1_p16_x4( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.poly16x4x4_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.poly16x4x4_t, align 8 -// CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v4i16.p0(ptr %a) -// CHECK: store { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 32, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.poly16x4x4_t, ptr [[RETVAL]], align 8 -// CHECK-A64: ret %struct.poly16x4x4_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.poly16x4x4_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld1x4.v4i16.p0(ptr %a) +// CHECK-A32: store { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 32, i1 false) // CHECK-A32: ret void poly16x4x4_t test_vld1_p16_x4(poly16_t const *a) { return vld1_p16_x4(a); } -// CHECK-LABEL: @test_vld1_p8_x2( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly8x8x2_t, align 8 +// CHECK-A32-LABEL: @test_vld1_p8_x2( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.poly8x8x2_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.poly8x8x2_t, align 8 -// CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v8i8.p0(ptr %a) -// CHECK: store { <8 x i8>, <8 x i8> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 16, i1 false) -// CHECK-A64: [[TMP4:%.*]] = load %struct.poly8x8x2_t, ptr [[RETVAL]], align 8 -// CHECK-A64: ret %struct.poly8x8x2_t [[TMP4]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.poly8x8x2_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8> } @llvm.arm.neon.vld1x2.v8i8.p0(ptr %a) +// CHECK-A32: store { <8 x i8>, <8 x i8> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 16, i1 false) // CHECK-A32: ret void poly8x8x2_t test_vld1_p8_x2(poly8_t const *a) { return vld1_p8_x2(a); } -// CHECK-LABEL: @test_vld1_p8_x3( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly8x8x3_t, align 8 +// CHECK-A32-LABEL: @test_vld1_p8_x3( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.poly8x8x3_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.poly8x8x3_t, align 8 -// CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v8i8.p0(ptr %a) -// CHECK: store { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 24, i1 false) -// CHECK-A64: [[TMP4:%.*]] = load %struct.poly8x8x3_t, ptr [[RETVAL]], align 8 -// CHECK-A64: ret %struct.poly8x8x3_t [[TMP4]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.poly8x8x3_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld1x3.v8i8.p0(ptr %a) +// CHECK-A32: store { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 24, i1 false) // CHECK-A32: ret void poly8x8x3_t test_vld1_p8_x3(poly8_t const *a) { return vld1_p8_x3(a); } -// CHECK-LABEL: @test_vld1_p8_x4( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly8x8x4_t, align 8 +// CHECK-A32-LABEL: @test_vld1_p8_x4( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.poly8x8x4_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.poly8x8x4_t, align 8 -// CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v8i8.p0(ptr %a) -// CHECK: store { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 32, i1 false) -// CHECK-A64: [[TMP4:%.*]] = load %struct.poly8x8x4_t, ptr [[RETVAL]], align 8 -// CHECK-A64: ret %struct.poly8x8x4_t [[TMP4]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.poly8x8x4_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld1x4.v8i8.p0(ptr %a) +// CHECK-A32: store { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 32, i1 false) // CHECK-A32: ret void poly8x8x4_t test_vld1_p8_x4(poly8_t const *a) { return vld1_p8_x4(a); } -// CHECK-LABEL: @test_vld1_s16_x2( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int16x4x2_t, align 8 +// CHECK-A32-LABEL: @test_vld1_s16_x2( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int16x4x2_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.int16x4x2_t, align 8 -// CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v4i16.p0(ptr %a) -// CHECK: store { <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 16, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.int16x4x2_t, ptr [[RETVAL]], align 8 -// CHECK-A64: ret %struct.int16x4x2_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.int16x4x2_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.arm.neon.vld1x2.v4i16.p0(ptr %a) +// CHECK-A32: store { <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 16, i1 false) // CHECK-A32: ret void int16x4x2_t test_vld1_s16_x2(int16_t const *a) { return vld1_s16_x2(a); } -// CHECK-LABEL: @test_vld1_s16_x3( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int16x4x3_t, align 8 +// CHECK-A32-LABEL: @test_vld1_s16_x3( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int16x4x3_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.int16x4x3_t, align 8 -// CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v4i16.p0(ptr %a) -// CHECK: store { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 24, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.int16x4x3_t, ptr [[RETVAL]], align 8 -// CHECK-A64: ret %struct.int16x4x3_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.int16x4x3_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld1x3.v4i16.p0(ptr %a) +// CHECK-A32: store { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 24, i1 false) // CHECK-A32: ret void int16x4x3_t test_vld1_s16_x3(int16_t const *a) { return vld1_s16_x3(a); } -// CHECK-LABEL: @test_vld1_s16_x4( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int16x4x4_t, align 8 +// CHECK-A32-LABEL: @test_vld1_s16_x4( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int16x4x4_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.int16x4x4_t, align 8 -// CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v4i16.p0(ptr %a) -// CHECK: store { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 32, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.int16x4x4_t, ptr [[RETVAL]], align 8 -// CHECK-A64: ret %struct.int16x4x4_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.int16x4x4_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld1x4.v4i16.p0(ptr %a) +// CHECK-A32: store { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 32, i1 false) // CHECK-A32: ret void int16x4x4_t test_vld1_s16_x4(int16_t const *a) { return vld1_s16_x4(a); } -// CHECK-LABEL: @test_vld1_s32_x2( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int32x2x2_t, align 8 +// CHECK-A32-LABEL: @test_vld1_s32_x2( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int32x2x2_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.int32x2x2_t, align 8 -// CHECK: [[VLD1XN:%.*]] = call { <2 x i32>, <2 x i32> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v2i32.p0(ptr %a) -// CHECK: store { <2 x i32>, <2 x i32> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 16, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.int32x2x2_t, ptr [[RETVAL]], align 8 -// CHECK-A64: ret %struct.int32x2x2_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.int32x2x2_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <2 x i32>, <2 x i32> } @llvm.arm.neon.vld1x2.v2i32.p0(ptr %a) +// CHECK-A32: store { <2 x i32>, <2 x i32> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 16, i1 false) // CHECK-A32: ret void int32x2x2_t test_vld1_s32_x2(int32_t const *a) { return vld1_s32_x2(a); } -// CHECK-LABEL: @test_vld1_s32_x3( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int32x2x3_t, align 8 +// CHECK-A32-LABEL: @test_vld1_s32_x3( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int32x2x3_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.int32x2x3_t, align 8 -// CHECK: [[VLD1XN:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v2i32.p0(ptr %a) -// CHECK: store { <2 x i32>, <2 x i32>, <2 x i32> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 24, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.int32x2x3_t, ptr [[RETVAL]], align 8 -// CHECK-A64: ret %struct.int32x2x3_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.int32x2x3_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm.neon.vld1x3.v2i32.p0(ptr %a) +// CHECK-A32: store { <2 x i32>, <2 x i32>, <2 x i32> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 24, i1 false) // CHECK-A32: ret void int32x2x3_t test_vld1_s32_x3(int32_t const *a) { return vld1_s32_x3(a); } -// CHECK-LABEL: @test_vld1_s32_x4( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int32x2x4_t, align 8 +// CHECK-A32-LABEL: @test_vld1_s32_x4( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int32x2x4_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.int32x2x4_t, align 8 -// CHECK: [[VLD1XN:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v2i32.p0(ptr %a) -// CHECK: store { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 32, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.int32x2x4_t, ptr [[RETVAL]], align 8 -// CHECK-A64: ret %struct.int32x2x4_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.int32x2x4_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm.neon.vld1x4.v2i32.p0(ptr %a) +// CHECK-A32: store { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 32, i1 false) // CHECK-A32: ret void int32x2x4_t test_vld1_s32_x4(int32_t const *a) { return vld1_s32_x4(a); } -// CHECK-LABEL: @test_vld1_s64_x2( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int64x1x2_t, align 8 +// CHECK-A32-LABEL: @test_vld1_s64_x2( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int64x1x2_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.int64x1x2_t, align 8 -// CHECK: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v1i64.p0(ptr %a) -// CHECK: store { <1 x i64>, <1 x i64> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 16, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.int64x1x2_t, ptr [[RETVAL]], align 8 -// CHECK-A64: ret %struct.int64x1x2_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.int64x1x2_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64> } @llvm.arm.neon.vld1x2.v1i64.p0(ptr %a) +// CHECK-A32: store { <1 x i64>, <1 x i64> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 16, i1 false) // CHECK-A32: ret void int64x1x2_t test_vld1_s64_x2(int64_t const *a) { return vld1_s64_x2(a); } -// CHECK-LABEL: @test_vld1_s64_x3( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int64x1x3_t, align 8 +// CHECK-A32-LABEL: @test_vld1_s64_x3( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int64x1x3_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.int64x1x3_t, align 8 -// CHECK: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v1i64.p0(ptr %a) -// CHECK: store { <1 x i64>, <1 x i64>, <1 x i64> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 24, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.int64x1x3_t, ptr [[RETVAL]], align 8 -// CHECK-A64: ret %struct.int64x1x3_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.int64x1x3_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm.neon.vld1x3.v1i64.p0(ptr %a) +// CHECK-A32: store { <1 x i64>, <1 x i64>, <1 x i64> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 24, i1 false) // CHECK-A32: ret void int64x1x3_t test_vld1_s64_x3(int64_t const *a) { return vld1_s64_x3(a); } -// CHECK-LABEL: @test_vld1_s64_x4( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int64x1x4_t, align 8 +// CHECK-A32-LABEL: @test_vld1_s64_x4( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int64x1x4_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.int64x1x4_t, align 8 -// CHECK: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v1i64.p0(ptr %a) -// CHECK: store { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 32, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.int64x1x4_t, ptr [[RETVAL]], align 8 -// CHECK-A64: ret %struct.int64x1x4_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.int64x1x4_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm.neon.vld1x4.v1i64.p0(ptr %a) +// CHECK-A32: store { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 32, i1 false) // CHECK-A32: ret void int64x1x4_t test_vld1_s64_x4(int64_t const *a) { return vld1_s64_x4(a); } -// CHECK-LABEL: @test_vld1_s8_x2( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int8x8x2_t, align 8 +// CHECK-A32-LABEL: @test_vld1_s8_x2( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int8x8x2_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.int8x8x2_t, align 8 -// CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v8i8.p0(ptr %a) -// CHECK: store { <8 x i8>, <8 x i8> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 16, i1 false) -// CHECK-A64: [[TMP4:%.*]] = load %struct.int8x8x2_t, ptr [[RETVAL]], align 8 -// CHECK-A64: ret %struct.int8x8x2_t [[TMP4]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.int8x8x2_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8> } @llvm.arm.neon.vld1x2.v8i8.p0(ptr %a) +// CHECK-A32: store { <8 x i8>, <8 x i8> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 16, i1 false) // CHECK-A32: ret void int8x8x2_t test_vld1_s8_x2(int8_t const *a) { return vld1_s8_x2(a); } -// CHECK-LABEL: @test_vld1_s8_x3( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int8x8x3_t, align 8 +// CHECK-A32-LABEL: @test_vld1_s8_x3( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int8x8x3_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.int8x8x3_t, align 8 -// CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v8i8.p0(ptr %a) -// CHECK: store { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 24, i1 false) -// CHECK-A64: [[TMP4:%.*]] = load %struct.int8x8x3_t, ptr [[RETVAL]], align 8 -// CHECK-A64: ret %struct.int8x8x3_t [[TMP4]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.int8x8x3_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld1x3.v8i8.p0(ptr %a) +// CHECK-A32: store { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 24, i1 false) // CHECK-A32: ret void int8x8x3_t test_vld1_s8_x3(int8_t const *a) { return vld1_s8_x3(a); } -// CHECK-LABEL: @test_vld1_s8_x4( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int8x8x4_t, align 8 +// CHECK-A32-LABEL: @test_vld1_s8_x4( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int8x8x4_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.int8x8x4_t, align 8 -// CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v8i8.p0(ptr %a) -// CHECK: store { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 32, i1 false) -// CHECK-A64: [[TMP4:%.*]] = load %struct.int8x8x4_t, ptr [[RETVAL]], align 8 -// CHECK-A64: ret %struct.int8x8x4_t [[TMP4]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.int8x8x4_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld1x4.v8i8.p0(ptr %a) +// CHECK-A32: store { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 32, i1 false) // CHECK-A32: ret void int8x8x4_t test_vld1_s8_x4(int8_t const *a) { return vld1_s8_x4(a); } -// CHECK-LABEL: @test_vld1_u16_x2( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint16x4x2_t, align 8 +// CHECK-A32-LABEL: @test_vld1_u16_x2( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint16x4x2_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.uint16x4x2_t, align 8 -// CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v4i16.p0(ptr %a) -// CHECK: store { <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 16, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.uint16x4x2_t, ptr [[RETVAL]], align 8 -// CHECK-A64: ret %struct.uint16x4x2_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.uint16x4x2_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16> } @llvm.arm.neon.vld1x2.v4i16.p0(ptr %a) +// CHECK-A32: store { <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 16, i1 false) // CHECK-A32: ret void uint16x4x2_t test_vld1_u16_x2(uint16_t const *a) { return vld1_u16_x2(a); } -// CHECK-LABEL: @test_vld1_u16_x3( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint16x4x3_t, align 8 +// CHECK-A32-LABEL: @test_vld1_u16_x3( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint16x4x3_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.uint16x4x3_t, align 8 -// CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v4i16.p0(ptr %a) -// CHECK: store { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 24, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.uint16x4x3_t, ptr [[RETVAL]], align 8 -// CHECK-A64: ret %struct.uint16x4x3_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.uint16x4x3_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld1x3.v4i16.p0(ptr %a) +// CHECK-A32: store { <4 x i16>, <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 24, i1 false) // CHECK-A32: ret void uint16x4x3_t test_vld1_u16_x3(uint16_t const *a) { return vld1_u16_x3(a); } -// CHECK-LABEL: @test_vld1_u16_x4( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint16x4x4_t, align 8 +// CHECK-A32-LABEL: @test_vld1_u16_x4( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint16x4x4_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.uint16x4x4_t, align 8 -// CHECK: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v4i16.p0(ptr %a) -// CHECK: store { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 32, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.uint16x4x4_t, ptr [[RETVAL]], align 8 -// CHECK-A64: ret %struct.uint16x4x4_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.uint16x4x4_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld1x4.v4i16.p0(ptr %a) +// CHECK-A32: store { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 32, i1 false) // CHECK-A32: ret void uint16x4x4_t test_vld1_u16_x4(uint16_t const *a) { return vld1_u16_x4(a); } -// CHECK-LABEL: @test_vld1_u32_x2( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint32x2x2_t, align 8 +// CHECK-A32-LABEL: @test_vld1_u32_x2( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint32x2x2_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.uint32x2x2_t, align 8 -// CHECK: [[VLD1XN:%.*]] = call { <2 x i32>, <2 x i32> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v2i32.p0(ptr %a) -// CHECK: store { <2 x i32>, <2 x i32> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 16, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.uint32x2x2_t, ptr [[RETVAL]], align 8 -// CHECK-A64: ret %struct.uint32x2x2_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.uint32x2x2_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <2 x i32>, <2 x i32> } @llvm.arm.neon.vld1x2.v2i32.p0(ptr %a) +// CHECK-A32: store { <2 x i32>, <2 x i32> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 16, i1 false) // CHECK-A32: ret void uint32x2x2_t test_vld1_u32_x2(uint32_t const *a) { return vld1_u32_x2(a); } -// CHECK-LABEL: @test_vld1_u32_x3( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint32x2x3_t, align 8 +// CHECK-A32-LABEL: @test_vld1_u32_x3( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint32x2x3_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.uint32x2x3_t, align 8 -// CHECK: [[VLD1XN:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v2i32.p0(ptr %a) -// CHECK: store { <2 x i32>, <2 x i32>, <2 x i32> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 24, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.uint32x2x3_t, ptr [[RETVAL]], align 8 -// CHECK-A64: ret %struct.uint32x2x3_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.uint32x2x3_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm.neon.vld1x3.v2i32.p0(ptr %a) +// CHECK-A32: store { <2 x i32>, <2 x i32>, <2 x i32> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 24, i1 false) // CHECK-A32: ret void uint32x2x3_t test_vld1_u32_x3(uint32_t const *a) { return vld1_u32_x3(a); } -// CHECK-LABEL: @test_vld1_u32_x4( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint32x2x4_t, align 8 +// CHECK-A32-LABEL: @test_vld1_u32_x4( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint32x2x4_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.uint32x2x4_t, align 8 -// CHECK: [[VLD1XN:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v2i32.p0(ptr %a) -// CHECK: store { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 32, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.uint32x2x4_t, ptr [[RETVAL]], align 8 -// CHECK-A64: ret %struct.uint32x2x4_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.uint32x2x4_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm.neon.vld1x4.v2i32.p0(ptr %a) +// CHECK-A32: store { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 32, i1 false) // CHECK-A32: ret void uint32x2x4_t test_vld1_u32_x4(uint32_t const *a) { return vld1_u32_x4(a); } -// CHECK-LABEL: @test_vld1_u64_x2( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint64x1x2_t, align 8 +// CHECK-A32-LABEL: @test_vld1_u64_x2( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint64x1x2_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.uint64x1x2_t, align 8 -// CHECK: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v1i64.p0(ptr %a) -// CHECK: store { <1 x i64>, <1 x i64> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 16, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.uint64x1x2_t, ptr [[RETVAL]], align 8 -// CHECK-A64: ret %struct.uint64x1x2_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.uint64x1x2_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64> } @llvm.arm.neon.vld1x2.v1i64.p0(ptr %a) +// CHECK-A32: store { <1 x i64>, <1 x i64> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 16, i1 false) // CHECK-A32: ret void uint64x1x2_t test_vld1_u64_x2(uint64_t const *a) { return vld1_u64_x2(a); } -// CHECK-LABEL: @test_vld1_u64_x3( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint64x1x3_t, align 8 +// CHECK-A32-LABEL: @test_vld1_u64_x3( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint64x1x3_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.uint64x1x3_t, align 8 -// CHECK: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v1i64.p0(ptr %a) -// CHECK: store { <1 x i64>, <1 x i64>, <1 x i64> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 24, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.uint64x1x3_t, ptr [[RETVAL]], align 8 -// CHECK-A64: ret %struct.uint64x1x3_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.uint64x1x3_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm.neon.vld1x3.v1i64.p0(ptr %a) +// CHECK-A32: store { <1 x i64>, <1 x i64>, <1 x i64> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 24, i1 false) // CHECK-A32: ret void uint64x1x3_t test_vld1_u64_x3(uint64_t const *a) { return vld1_u64_x3(a); } -// CHECK-LABEL: @test_vld1_u64_x4( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint64x1x4_t, align 8 +// CHECK-A32-LABEL: @test_vld1_u64_x4( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint64x1x4_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.uint64x1x4_t, align 8 -// CHECK: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v1i64.p0(ptr %a) -// CHECK: store { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 32, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.uint64x1x4_t, ptr [[RETVAL]], align 8 -// CHECK-A64: ret %struct.uint64x1x4_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.uint64x1x4_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm.neon.vld1x4.v1i64.p0(ptr %a) +// CHECK-A32: store { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 32, i1 false) // CHECK-A32: ret void uint64x1x4_t test_vld1_u64_x4(uint64_t const *a) { return vld1_u64_x4(a); } -// CHECK-LABEL: @test_vld1_u8_x2( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint8x8x2_t, align 8 +// CHECK-A32-LABEL: @test_vld1_u8_x2( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint8x8x2_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.uint8x8x2_t, align 8 -// CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v8i8.p0(ptr %a) -// CHECK: store { <8 x i8>, <8 x i8> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 16, i1 false) -// CHECK-A64: [[TMP4:%.*]] = load %struct.uint8x8x2_t, ptr [[RETVAL]], align 8 -// CHECK-A64: ret %struct.uint8x8x2_t [[TMP4]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.uint8x8x2_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8> } @llvm.arm.neon.vld1x2.v8i8.p0(ptr %a) +// CHECK-A32: store { <8 x i8>, <8 x i8> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 16, i1 false) // CHECK-A32: ret void uint8x8x2_t test_vld1_u8_x2(uint8_t const *a) { return vld1_u8_x2(a); } -// CHECK-LABEL: @test_vld1_u8_x3( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint8x8x3_t, align 8 +// CHECK-A32-LABEL: @test_vld1_u8_x3( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint8x8x3_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.uint8x8x3_t, align 8 -// CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v8i8.p0(ptr %a) -// CHECK: store { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 24, i1 false) -// CHECK-A64: [[TMP4:%.*]] = load %struct.uint8x8x3_t, ptr [[RETVAL]], align 8 -// CHECK-A64: ret %struct.uint8x8x3_t [[TMP4]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.uint8x8x3_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld1x3.v8i8.p0(ptr %a) +// CHECK-A32: store { <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 24, i1 false) // CHECK-A32: ret void uint8x8x3_t test_vld1_u8_x3(uint8_t const *a) { return vld1_u8_x3(a); } -// CHECK-LABEL: @test_vld1_u8_x4( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint8x8x4_t, align 8 +// CHECK-A32-LABEL: @test_vld1_u8_x4( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint8x8x4_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.uint8x8x4_t, align 8 -// CHECK: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v8i8.p0(ptr %a) -// CHECK: store { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], {{i64|i32}} 32, i1 false) -// CHECK-A64: [[TMP4:%.*]] = load %struct.uint8x8x4_t, ptr [[RETVAL]], align 8 -// CHECK-A64: ret %struct.uint8x8x4_t [[TMP4]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.uint8x8x4_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld1x4.v8i8.p0(ptr %a) +// CHECK-A32: store { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 32, i1 false) // CHECK-A32: ret void uint8x8x4_t test_vld1_u8_x4(uint8_t const *a) { return vld1_u8_x4(a); } -// CHECK-LABEL: @test_vld1q_f16_x2( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float16x8x2_t, align 16 +// CHECK-A32-LABEL: @test_vld1q_f16_x2( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.float16x8x2_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.float16x8x2_t, align {{16|8}} -// CHECK: [[VLD1XN:%.*]] = call { <8 x [[HALF:half|i16]]>, <8 x [[HALF]]> } @llvm.{{aarch64.neon.ld1x2.v8f16.p0|arm.neon.vld1x2.v8i16.p0}}(ptr %a) -// CHECK: store { <8 x [[HALF]]>, <8 x [[HALF]]> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 32, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.float16x8x2_t, ptr [[RETVAL]], align 16 -// CHECK-A64: ret %struct.float16x8x2_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.float16x8x2_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.arm.neon.vld1x2.v8i16.p0(ptr %a) +// CHECK-A32: store { <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 32, i1 false) // CHECK-A32: ret void float16x8x2_t test_vld1q_f16_x2(float16_t const *a) { return vld1q_f16_x2(a); } -// CHECK-LABEL: @test_vld1q_f16_x3( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float16x8x3_t, align 16 +// CHECK-A32-LABEL: @test_vld1q_f16_x3( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.float16x8x3_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.float16x8x3_t, align {{16|8}} -// CHECK: [[VLD1XN:%.*]] = call { <8 x [[HALF:half|i16]]>, <8 x [[HALF]]>, <8 x [[HALF]]> } @llvm.{{aarch64.neon.ld1x3.v8f16.p0|arm.neon.vld1x3.v8i16.p0}}(ptr %a) -// CHECK: store { <8 x [[HALF]]>, <8 x [[HALF]]>, <8 x [[HALF]]> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 48, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.float16x8x3_t, ptr [[RETVAL]], align 16 -// CHECK-A64: ret %struct.float16x8x3_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.float16x8x3_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld1x3.v8i16.p0(ptr %a) +// CHECK-A32: store { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 48, i1 false) // CHECK-A32: ret void float16x8x3_t test_vld1q_f16_x3(float16_t const *a) { return vld1q_f16_x3(a); } -// CHECK-LABEL: @test_vld1q_f16_x4( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float16x8x4_t, align 16 +// CHECK-A32-LABEL: @test_vld1q_f16_x4( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.float16x8x4_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.float16x8x4_t, align {{16|8}} -// CHECK: [[VLD1XN:%.*]] = call { <8 x [[HALF:half|i16]]>, <8 x [[HALF]]>, <8 x [[HALF]]>, <8 x [[HALF]]> } @llvm.{{aarch64.neon.ld1x4.v8f16.p0|arm.neon.vld1x4.v8i16.p0}}(ptr %a) -// CHECK: store { <8 x [[HALF]]>, <8 x [[HALF]]>, <8 x [[HALF]]>, <8 x [[HALF]]> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 64, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.float16x8x4_t, ptr [[RETVAL]], align 16 -// CHECK-A64: ret %struct.float16x8x4_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.float16x8x4_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld1x4.v8i16.p0(ptr %a) +// CHECK-A32: store { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 64, i1 false) // CHECK-A32: ret void float16x8x4_t test_vld1q_f16_x4(float16_t const *a) { return vld1q_f16_x4(a); } -// CHECK-LABEL: @test_vld1q_f32_x2( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float32x4x2_t, align 16 +// CHECK-A32-LABEL: @test_vld1q_f32_x2( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.float32x4x2_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.float32x4x2_t, align {{16|8}} -// CHECK: [[VLD1XN:%.*]] = call { <4 x float>, <4 x float> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v4f32.p0(ptr %a) -// CHECK: store { <4 x float>, <4 x float> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 32, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.float32x4x2_t, ptr [[RETVAL]], align 16 -// CHECK-A64: ret %struct.float32x4x2_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.float32x4x2_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <4 x float>, <4 x float> } @llvm.arm.neon.vld1x2.v4f32.p0(ptr %a) +// CHECK-A32: store { <4 x float>, <4 x float> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 32, i1 false) // CHECK-A32: ret void float32x4x2_t test_vld1q_f32_x2(float32_t const *a) { return vld1q_f32_x2(a); } -// CHECK-LABEL: @test_vld1q_f32_x3( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float32x4x3_t, align 16 +// CHECK-A32-LABEL: @test_vld1q_f32_x3( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.float32x4x3_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.float32x4x3_t, align {{16|8}} -// CHECK: [[VLD1XN:%.*]] = call { <4 x float>, <4 x float>, <4 x float> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v4f32.p0(ptr %a) -// CHECK: store { <4 x float>, <4 x float>, <4 x float> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 48, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.float32x4x3_t, ptr [[RETVAL]], align 16 -// CHECK-A64: ret %struct.float32x4x3_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.float32x4x3_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <4 x float>, <4 x float>, <4 x float> } @llvm.arm.neon.vld1x3.v4f32.p0(ptr %a) +// CHECK-A32: store { <4 x float>, <4 x float>, <4 x float> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 48, i1 false) // CHECK-A32: ret void float32x4x3_t test_vld1q_f32_x3(float32_t const *a) { return vld1q_f32_x3(a); } -// CHECK-LABEL: @test_vld1q_f32_x4( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.float32x4x4_t, align 16 +// CHECK-A32-LABEL: @test_vld1q_f32_x4( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.float32x4x4_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.float32x4x4_t, align {{16|8}} -// CHECK: [[VLD1XN:%.*]] = call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v4f32.p0(ptr %a) -// CHECK: store { <4 x float>, <4 x float>, <4 x float>, <4 x float> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 64, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.float32x4x4_t, ptr [[RETVAL]], align 16 -// CHECK-A64: ret %struct.float32x4x4_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.float32x4x4_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.arm.neon.vld1x4.v4f32.p0(ptr %a) +// CHECK-A32: store { <4 x float>, <4 x float>, <4 x float>, <4 x float> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 64, i1 false) // CHECK-A32: ret void float32x4x4_t test_vld1q_f32_x4(float32_t const *a) { return vld1q_f32_x4(a); } -// CHECK-LABEL: @test_vld1q_p16_x2( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly16x8x2_t, align 16 +// CHECK-A32-LABEL: @test_vld1q_p16_x2( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.poly16x8x2_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.poly16x8x2_t, align {{16|8}} -// CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v8i16.p0(ptr %a) -// CHECK: store { <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 32, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.poly16x8x2_t, ptr [[RETVAL]], align 16 -// CHECK-A64: ret %struct.poly16x8x2_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.poly16x8x2_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.arm.neon.vld1x2.v8i16.p0(ptr %a) +// CHECK-A32: store { <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 32, i1 false) // CHECK-A32: ret void poly16x8x2_t test_vld1q_p16_x2(poly16_t const *a) { return vld1q_p16_x2(a); } -// CHECK-LABEL: @test_vld1q_p16_x3( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly16x8x3_t, align 16 +// CHECK-A32-LABEL: @test_vld1q_p16_x3( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.poly16x8x3_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.poly16x8x3_t, align {{16|8}} -// CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v8i16.p0(ptr %a) -// CHECK: store { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 48, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.poly16x8x3_t, ptr [[RETVAL]], align 16 -// CHECK-A64: ret %struct.poly16x8x3_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.poly16x8x3_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld1x3.v8i16.p0(ptr %a) +// CHECK-A32: store { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 48, i1 false) // CHECK-A32: ret void poly16x8x3_t test_vld1q_p16_x3(poly16_t const *a) { return vld1q_p16_x3(a); } -// CHECK-LABEL: @test_vld1q_p16_x4( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly16x8x4_t, align 16 +// CHECK-A32-LABEL: @test_vld1q_p16_x4( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.poly16x8x4_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.poly16x8x4_t, align {{16|8}} -// CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v8i16.p0(ptr %a) -// CHECK: store { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 64, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.poly16x8x4_t, ptr [[RETVAL]], align 16 -// CHECK-A64: ret %struct.poly16x8x4_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.poly16x8x4_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld1x4.v8i16.p0(ptr %a) +// CHECK-A32: store { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 64, i1 false) // CHECK-A32: ret void poly16x8x4_t test_vld1q_p16_x4(poly16_t const *a) { return vld1q_p16_x4(a); } -// CHECK-LABEL: @test_vld1q_p8_x2( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly8x16x2_t, align 16 +// CHECK-A32-LABEL: @test_vld1q_p8_x2( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.poly8x16x2_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.poly8x16x2_t, align {{16|8}} -// CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v16i8.p0(ptr %a) -// CHECK: store { <16 x i8>, <16 x i8> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 32, i1 false) -// CHECK-A64: [[TMP4:%.*]] = load %struct.poly8x16x2_t, ptr [[RETVAL]], align 16 -// CHECK-A64: ret %struct.poly8x16x2_t [[TMP4]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.poly8x16x2_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8> } @llvm.arm.neon.vld1x2.v16i8.p0(ptr %a) +// CHECK-A32: store { <16 x i8>, <16 x i8> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 32, i1 false) // CHECK-A32: ret void poly8x16x2_t test_vld1q_p8_x2(poly8_t const *a) { return vld1q_p8_x2(a); } -// CHECK-LABEL: @test_vld1q_p8_x3( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly8x16x3_t, align 16 +// CHECK-A32-LABEL: @test_vld1q_p8_x3( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.poly8x16x3_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.poly8x16x3_t, align {{16|8}} -// CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v16i8.p0(ptr %a) -// CHECK: store { <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 48, i1 false) -// CHECK-A64: [[TMP4:%.*]] = load %struct.poly8x16x3_t, ptr [[RETVAL]], align 16 -// CHECK-A64: ret %struct.poly8x16x3_t [[TMP4]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.poly8x16x3_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld1x3.v16i8.p0(ptr %a) +// CHECK-A32: store { <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 48, i1 false) // CHECK-A32: ret void poly8x16x3_t test_vld1q_p8_x3(poly8_t const *a) { return vld1q_p8_x3(a); } -// CHECK-LABEL: @test_vld1q_p8_x4( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.poly8x16x4_t, align 16 +// CHECK-A32-LABEL: @test_vld1q_p8_x4( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.poly8x16x4_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.poly8x16x4_t, align {{16|8}} -// CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v16i8.p0(ptr %a) -// CHECK: store { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 64, i1 false) -// CHECK-A64: [[TMP4:%.*]] = load %struct.poly8x16x4_t, ptr [[RETVAL]], align 16 -// CHECK-A64: ret %struct.poly8x16x4_t [[TMP4]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.poly8x16x4_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld1x4.v16i8.p0(ptr %a) +// CHECK-A32: store { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 64, i1 false) // CHECK-A32: ret void poly8x16x4_t test_vld1q_p8_x4(poly8_t const *a) { return vld1q_p8_x4(a); } -// CHECK-LABEL: @test_vld1q_s16_x2( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int16x8x2_t, align 16 +// CHECK-A32-LABEL: @test_vld1q_s16_x2( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int16x8x2_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.int16x8x2_t, align {{16|8}} -// CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v8i16.p0(ptr %a) -// CHECK: store { <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 32, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.int16x8x2_t, ptr [[RETVAL]], align 16 -// CHECK-A64: ret %struct.int16x8x2_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.int16x8x2_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.arm.neon.vld1x2.v8i16.p0(ptr %a) +// CHECK-A32: store { <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 32, i1 false) // CHECK-A32: ret void int16x8x2_t test_vld1q_s16_x2(int16_t const *a) { return vld1q_s16_x2(a); } -// CHECK-LABEL: @test_vld1q_s16_x3( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int16x8x3_t, align 16 +// CHECK-A32-LABEL: @test_vld1q_s16_x3( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int16x8x3_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.int16x8x3_t, align {{16|8}} -// CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v8i16.p0(ptr %a) -// CHECK: store { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 48, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.int16x8x3_t, ptr [[RETVAL]], align 16 -// CHECK-A64: ret %struct.int16x8x3_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.int16x8x3_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld1x3.v8i16.p0(ptr %a) +// CHECK-A32: store { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 48, i1 false) // CHECK-A32: ret void int16x8x3_t test_vld1q_s16_x3(int16_t const *a) { return vld1q_s16_x3(a); } -// CHECK-LABEL: @test_vld1q_s16_x4( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int16x8x4_t, align 16 +// CHECK-A32-LABEL: @test_vld1q_s16_x4( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int16x8x4_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.int16x8x4_t, align {{16|8}} -// CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v8i16.p0(ptr %a) -// CHECK: store { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 64, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.int16x8x4_t, ptr [[RETVAL]], align 16 -// CHECK-A64: ret %struct.int16x8x4_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.int16x8x4_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld1x4.v8i16.p0(ptr %a) +// CHECK-A32: store { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 64, i1 false) // CHECK-A32: ret void int16x8x4_t test_vld1q_s16_x4(int16_t const *a) { return vld1q_s16_x4(a); } -// CHECK-LABEL: @test_vld1q_s32_x2( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int32x4x2_t, align 16 +// CHECK-A32-LABEL: @test_vld1q_s32_x2( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int32x4x2_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.int32x4x2_t, align {{16|8}} -// CHECK: [[VLD1XN:%.*]] = call { <4 x i32>, <4 x i32> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v4i32.p0(ptr %a) -// CHECK: store { <4 x i32>, <4 x i32> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 32, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.int32x4x2_t, ptr [[RETVAL]], align 16 -// CHECK-A64: ret %struct.int32x4x2_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.int32x4x2_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld1x2.v4i32.p0(ptr %a) +// CHECK-A32: store { <4 x i32>, <4 x i32> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 32, i1 false) // CHECK-A32: ret void int32x4x2_t test_vld1q_s32_x2(int32_t const *a) { return vld1q_s32_x2(a); } -// CHECK-LABEL: @test_vld1q_s32_x3( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int32x4x3_t, align 16 +// CHECK-A32-LABEL: @test_vld1q_s32_x3( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int32x4x3_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.int32x4x3_t, align {{16|8}} -// CHECK: [[VLD1XN:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v4i32.p0(ptr %a) -// CHECK: store { <4 x i32>, <4 x i32>, <4 x i32> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 48, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.int32x4x3_t, ptr [[RETVAL]], align 16 -// CHECK-A64: ret %struct.int32x4x3_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.int32x4x3_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld1x3.v4i32.p0(ptr %a) +// CHECK-A32: store { <4 x i32>, <4 x i32>, <4 x i32> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 48, i1 false) // CHECK-A32: ret void int32x4x3_t test_vld1q_s32_x3(int32_t const *a) { return vld1q_s32_x3(a); } -// CHECK-LABEL: @test_vld1q_s32_x4( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int32x4x4_t, align 16 +// CHECK-A32-LABEL: @test_vld1q_s32_x4( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int32x4x4_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.int32x4x4_t, align {{16|8}} -// CHECK: [[VLD1XN:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v4i32.p0(ptr %a) -// CHECK: store { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 64, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.int32x4x4_t, ptr [[RETVAL]], align 16 -// CHECK-A64: ret %struct.int32x4x4_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.int32x4x4_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld1x4.v4i32.p0(ptr %a) +// CHECK-A32: store { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 64, i1 false) // CHECK-A32: ret void int32x4x4_t test_vld1q_s32_x4(int32_t const *a) { return vld1q_s32_x4(a); } -// CHECK-LABEL: @test_vld1q_s64_x2( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int64x2x2_t, align 16 +// CHECK-A32-LABEL: @test_vld1q_s64_x2( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int64x2x2_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.int64x2x2_t, align {{16|8}} -// CHECK: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v2i64.p0(ptr %a) -// CHECK: store { <2 x i64>, <2 x i64> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 32, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.int64x2x2_t, ptr [[RETVAL]], align 16 -// CHECK-A64: ret %struct.int64x2x2_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.int64x2x2_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64> } @llvm.arm.neon.vld1x2.v2i64.p0(ptr %a) +// CHECK-A32: store { <2 x i64>, <2 x i64> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 32, i1 false) // CHECK-A32: ret void int64x2x2_t test_vld1q_s64_x2(int64_t const *a) { return vld1q_s64_x2(a); } -// CHECK-LABEL: @test_vld1q_s64_x3( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int64x2x3_t, align 16 +// CHECK-A32-LABEL: @test_vld1q_s64_x3( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int64x2x3_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.int64x2x3_t, align {{16|8}} -// CHECK: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v2i64.p0(ptr %a) -// CHECK: store { <2 x i64>, <2 x i64>, <2 x i64> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 48, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.int64x2x3_t, ptr [[RETVAL]], align 16 -// CHECK-A64: ret %struct.int64x2x3_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.int64x2x3_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.arm.neon.vld1x3.v2i64.p0(ptr %a) +// CHECK-A32: store { <2 x i64>, <2 x i64>, <2 x i64> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 48, i1 false) // CHECK-A32: ret void int64x2x3_t test_vld1q_s64_x3(int64_t const *a) { return vld1q_s64_x3(a); } -// CHECK-LABEL: @test_vld1q_s64_x4( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int64x2x4_t, align 16 +// CHECK-A32-LABEL: @test_vld1q_s64_x4( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int64x2x4_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.int64x2x4_t, align {{16|8}} -// CHECK: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v2i64.p0(ptr %a) -// CHECK: store { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 64, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.int64x2x4_t, ptr [[RETVAL]], align 16 -// CHECK-A64: ret %struct.int64x2x4_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.int64x2x4_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.arm.neon.vld1x4.v2i64.p0(ptr %a) +// CHECK-A32: store { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 64, i1 false) // CHECK-A32: ret void int64x2x4_t test_vld1q_s64_x4(int64_t const *a) { return vld1q_s64_x4(a); } -// CHECK-LABEL: @test_vld1q_s8_x2( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int8x16x2_t, align 16 +// CHECK-A32-LABEL: @test_vld1q_s8_x2( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int8x16x2_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.int8x16x2_t, align {{16|8}} -// CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v16i8.p0(ptr %a) -// CHECK: store { <16 x i8>, <16 x i8> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 32, i1 false) -// CHECK-A64: [[TMP4:%.*]] = load %struct.int8x16x2_t, ptr [[RETVAL]], align 16 -// CHECK-A64: ret %struct.int8x16x2_t [[TMP4]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.int8x16x2_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8> } @llvm.arm.neon.vld1x2.v16i8.p0(ptr %a) +// CHECK-A32: store { <16 x i8>, <16 x i8> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 32, i1 false) // CHECK-A32: ret void int8x16x2_t test_vld1q_s8_x2(int8_t const *a) { return vld1q_s8_x2(a); } -// CHECK-LABEL: @test_vld1q_s8_x3( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int8x16x3_t, align 16 +// CHECK-A32-LABEL: @test_vld1q_s8_x3( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int8x16x3_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.int8x16x3_t, align {{16|8}} -// CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v16i8.p0(ptr %a) -// CHECK: store { <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 48, i1 false) -// CHECK-A64: [[TMP4:%.*]] = load %struct.int8x16x3_t, ptr [[RETVAL]], align 16 -// CHECK-A64: ret %struct.int8x16x3_t [[TMP4]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.int8x16x3_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld1x3.v16i8.p0(ptr %a) +// CHECK-A32: store { <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 48, i1 false) // CHECK-A32: ret void int8x16x3_t test_vld1q_s8_x3(int8_t const *a) { return vld1q_s8_x3(a); } -// CHECK-LABEL: @test_vld1q_s8_x4( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.int8x16x4_t, align 16 +// CHECK-A32-LABEL: @test_vld1q_s8_x4( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.int8x16x4_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.int8x16x4_t, align {{16|8}} -// CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v16i8.p0(ptr %a) -// CHECK: store { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 64, i1 false) -// CHECK-A64: [[TMP4:%.*]] = load %struct.int8x16x4_t, ptr [[RETVAL]], align 16 -// CHECK-A64: ret %struct.int8x16x4_t [[TMP4]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.int8x16x4_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld1x4.v16i8.p0(ptr %a) +// CHECK-A32: store { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 64, i1 false) // CHECK-A32: ret void int8x16x4_t test_vld1q_s8_x4(int8_t const *a) { return vld1q_s8_x4(a); } -// CHECK-LABEL: @test_vld1q_u16_x2( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint16x8x2_t, align 16 +// CHECK-A32-LABEL: @test_vld1q_u16_x2( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint16x8x2_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.uint16x8x2_t, align {{16|8}} -// CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v8i16.p0(ptr %a) -// CHECK: store { <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 32, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.uint16x8x2_t, ptr [[RETVAL]], align 16 -// CHECK-A64: ret %struct.uint16x8x2_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.uint16x8x2_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16> } @llvm.arm.neon.vld1x2.v8i16.p0(ptr %a) +// CHECK-A32: store { <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 32, i1 false) // CHECK-A32: ret void uint16x8x2_t test_vld1q_u16_x2(uint16_t const *a) { return vld1q_u16_x2(a); } -// CHECK-LABEL: @test_vld1q_u16_x3( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint16x8x3_t, align 16 +// CHECK-A32-LABEL: @test_vld1q_u16_x3( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint16x8x3_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.uint16x8x3_t, align {{16|8}} -// CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v8i16.p0(ptr %a) -// CHECK: store { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 48, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.uint16x8x3_t, ptr [[RETVAL]], align 16 -// CHECK-A64: ret %struct.uint16x8x3_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.uint16x8x3_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld1x3.v8i16.p0(ptr %a) +// CHECK-A32: store { <8 x i16>, <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 48, i1 false) // CHECK-A32: ret void uint16x8x3_t test_vld1q_u16_x3(uint16_t const *a) { return vld1q_u16_x3(a); } -// CHECK-LABEL: @test_vld1q_u16_x4( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint16x8x4_t, align 16 +// CHECK-A32-LABEL: @test_vld1q_u16_x4( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint16x8x4_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.uint16x8x4_t, align {{16|8}} -// CHECK: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v8i16.p0(ptr %a) -// CHECK: store { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 64, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.uint16x8x4_t, ptr [[RETVAL]], align 16 -// CHECK-A64: ret %struct.uint16x8x4_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.uint16x8x4_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld1x4.v8i16.p0(ptr %a) +// CHECK-A32: store { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 64, i1 false) // CHECK-A32: ret void uint16x8x4_t test_vld1q_u16_x4(uint16_t const *a) { return vld1q_u16_x4(a); } -// CHECK-LABEL: @test_vld1q_u32_x2( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint32x4x2_t, align 16 +// CHECK-A32-LABEL: @test_vld1q_u32_x2( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint32x4x2_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.uint32x4x2_t, align {{16|8}} -// CHECK: [[VLD1XN:%.*]] = call { <4 x i32>, <4 x i32> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v4i32.p0(ptr %a) -// CHECK: store { <4 x i32>, <4 x i32> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 32, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.uint32x4x2_t, ptr [[RETVAL]], align 16 -// CHECK-A64: ret %struct.uint32x4x2_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.uint32x4x2_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld1x2.v4i32.p0(ptr %a) +// CHECK-A32: store { <4 x i32>, <4 x i32> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 32, i1 false) // CHECK-A32: ret void uint32x4x2_t test_vld1q_u32_x2(uint32_t const *a) { return vld1q_u32_x2(a); } -// CHECK-LABEL: @test_vld1q_u32_x3( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint32x4x3_t, align 16 +// CHECK-A32-LABEL: @test_vld1q_u32_x3( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint32x4x3_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.uint32x4x3_t, align {{16|8}} -// CHECK: [[VLD1XN:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v4i32.p0(ptr %a) -// CHECK: store { <4 x i32>, <4 x i32>, <4 x i32> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 48, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.uint32x4x3_t, ptr [[RETVAL]], align 16 -// CHECK-A64: ret %struct.uint32x4x3_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.uint32x4x3_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld1x3.v4i32.p0(ptr %a) +// CHECK-A32: store { <4 x i32>, <4 x i32>, <4 x i32> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 48, i1 false) // CHECK-A32: ret void uint32x4x3_t test_vld1q_u32_x3(uint32_t const *a) { return vld1q_u32_x3(a); } -// CHECK-LABEL: @test_vld1q_u32_x4( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint32x4x4_t, align 16 +// CHECK-A32-LABEL: @test_vld1q_u32_x4( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint32x4x4_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.uint32x4x4_t, align {{16|8}} -// CHECK: [[VLD1XN:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v4i32.p0(ptr %a) -// CHECK: store { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 64, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.uint32x4x4_t, ptr [[RETVAL]], align 16 -// CHECK-A64: ret %struct.uint32x4x4_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.uint32x4x4_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm.neon.vld1x4.v4i32.p0(ptr %a) +// CHECK-A32: store { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 64, i1 false) // CHECK-A32: ret void uint32x4x4_t test_vld1q_u32_x4(uint32_t const *a) { return vld1q_u32_x4(a); } -// CHECK-LABEL: @test_vld1q_u64_x2( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint64x2x2_t, align 16 +// CHECK-A32-LABEL: @test_vld1q_u64_x2( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint64x2x2_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.uint64x2x2_t, align {{16|8}} -// CHECK: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v2i64.p0(ptr %a) -// CHECK: store { <2 x i64>, <2 x i64> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 32, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.uint64x2x2_t, ptr [[RETVAL]], align 16 -// CHECK-A64: ret %struct.uint64x2x2_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.uint64x2x2_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64> } @llvm.arm.neon.vld1x2.v2i64.p0(ptr %a) +// CHECK-A32: store { <2 x i64>, <2 x i64> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 32, i1 false) // CHECK-A32: ret void uint64x2x2_t test_vld1q_u64_x2(uint64_t const *a) { return vld1q_u64_x2(a); } -// CHECK-LABEL: @test_vld1q_u64_x3( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint64x2x3_t, align 16 +// CHECK-A32-LABEL: @test_vld1q_u64_x3( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint64x2x3_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.uint64x2x3_t, align {{16|8}} -// CHECK: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v2i64.p0(ptr %a) -// CHECK: store { <2 x i64>, <2 x i64>, <2 x i64> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 48, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.uint64x2x3_t, ptr [[RETVAL]], align 16 -// CHECK-A64: ret %struct.uint64x2x3_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.uint64x2x3_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.arm.neon.vld1x3.v2i64.p0(ptr %a) +// CHECK-A32: store { <2 x i64>, <2 x i64>, <2 x i64> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 48, i1 false) // CHECK-A32: ret void uint64x2x3_t test_vld1q_u64_x3(uint64_t const *a) { return vld1q_u64_x3(a); } -// CHECK-LABEL: @test_vld1q_u64_x4( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint64x2x4_t, align 16 +// CHECK-A32-LABEL: @test_vld1q_u64_x4( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint64x2x4_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.uint64x2x4_t, align {{16|8}} -// CHECK: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v2i64.p0(ptr %a) -// CHECK: store { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 64, i1 false) -// CHECK-A64: [[TMP6:%.*]] = load %struct.uint64x2x4_t, ptr [[RETVAL]], align 16 -// CHECK-A64: ret %struct.uint64x2x4_t [[TMP6]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.uint64x2x4_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.arm.neon.vld1x4.v2i64.p0(ptr %a) +// CHECK-A32: store { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 64, i1 false) // CHECK-A32: ret void uint64x2x4_t test_vld1q_u64_x4(uint64_t const *a) { return vld1q_u64_x4(a); } -// CHECK-LABEL: @test_vld1q_u8_x2( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint8x16x2_t, align 16 +// CHECK-A32-LABEL: @test_vld1q_u8_x2( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint8x16x2_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.uint8x16x2_t, align {{16|8}} -// CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x2|arm.neon.vld1x2}}.v16i8.p0(ptr %a) -// CHECK: store { <16 x i8>, <16 x i8> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 32, i1 false) -// CHECK-A64: [[TMP4:%.*]] = load %struct.uint8x16x2_t, ptr [[RETVAL]], align 16 -// CHECK-A64: ret %struct.uint8x16x2_t [[TMP4]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.uint8x16x2_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8> } @llvm.arm.neon.vld1x2.v16i8.p0(ptr %a) +// CHECK-A32: store { <16 x i8>, <16 x i8> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 32, i1 false) // CHECK-A32: ret void uint8x16x2_t test_vld1q_u8_x2(uint8_t const *a) { return vld1q_u8_x2(a); } -// CHECK-LABEL: @test_vld1q_u8_x3( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint8x16x3_t, align 16 +// CHECK-A32-LABEL: @test_vld1q_u8_x3( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint8x16x3_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.uint8x16x3_t, align {{16|8}} -// CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x3|arm.neon.vld1x3}}.v16i8.p0(ptr %a) -// CHECK: store { <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 48, i1 false) -// CHECK-A64: [[TMP4:%.*]] = load %struct.uint8x16x3_t, ptr [[RETVAL]], align 16 -// CHECK-A64: ret %struct.uint8x16x3_t [[TMP4]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.uint8x16x3_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld1x3.v16i8.p0(ptr %a) +// CHECK-A32: store { <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 48, i1 false) // CHECK-A32: ret void uint8x16x3_t test_vld1q_u8_x3(uint8_t const *a) { return vld1q_u8_x3(a); } -// CHECK-LABEL: @test_vld1q_u8_x4( -// CHECK-A64: [[RETVAL:%.*]] = alloca %struct.uint8x16x4_t, align 16 +// CHECK-A32-LABEL: @test_vld1q_u8_x4( // CHECK-A32: ptr dead_on_unwind noalias writable sret(%struct.uint8x16x4_t) align 8 [[RETVAL:%.*]], -// CHECK: [[__RET:%.*]] = alloca %struct.uint8x16x4_t, align {{16|8}} -// CHECK: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.{{aarch64.neon.ld1x4|arm.neon.vld1x4}}.v16i8.p0(ptr %a) -// CHECK: store { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], ptr [[__RET]] -// CHECK: call void @llvm.memcpy.p0.p0.{{i64|i32}}(ptr align {{16|8}} [[RETVAL]], ptr align {{16|8}} [[__RET]], {{i64|i32}} 64, i1 false) -// CHECK-A64: [[TMP4:%.*]] = load %struct.uint8x16x4_t, ptr [[RETVAL]], align 16 -// CHECK-A64: ret %struct.uint8x16x4_t [[TMP4]] +// CHECK-A32: [[__RET:%.*]] = alloca %struct.uint8x16x4_t, align 8 +// CHECK-A32: [[VLD1XN:%.*]] = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld1x4.v16i8.p0(ptr %a) +// CHECK-A32: store { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[VLD1XN]], ptr [[__RET]] +// CHECK-A32: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[RETVAL]], ptr align 8 [[__RET]], i32 64, i1 false) // CHECK-A32: ret void uint8x16x4_t test_vld1q_u8_x4(uint8_t const *a) { return vld1q_u8_x4(a);