diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h index 557c6ef03d96b..0179cf8a1f592 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h +++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h @@ -89,9 +89,10 @@ class SelectionDAGISel : public MachineFunctionPass { /// not match or is not implemented, return true. The resultant operands /// (which will appear in the machine instruction) should be added to the /// OutOps vector. - virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, - unsigned ConstraintID, - std::vector &OutOps) { + virtual bool + SelectInlineAsmMemoryOperand(const SDValue &Op, + InlineAsm::ConstraintCode ConstraintID, + std::vector &OutOps) { return true; } diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h index 12b280d5b1a0b..f4feab4959322 100644 --- a/llvm/include/llvm/CodeGen/TargetLowering.h +++ b/llvm/include/llvm/CodeGen/TargetLowering.h @@ -4833,16 +4833,17 @@ class TargetLowering : public TargetLoweringBase { getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const; - virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const { + virtual InlineAsm::ConstraintCode + getInlineAsmMemConstraint(StringRef ConstraintCode) const { if (ConstraintCode == "m") - return InlineAsm::Constraint_m; + return InlineAsm::ConstraintCode::m; if (ConstraintCode == "o") - return InlineAsm::Constraint_o; + return InlineAsm::ConstraintCode::o; if (ConstraintCode == "X") - return InlineAsm::Constraint_X; + return InlineAsm::ConstraintCode::X; if (ConstraintCode == "p") - return InlineAsm::Constraint_p; - return InlineAsm::Constraint_Unknown; + return InlineAsm::ConstraintCode::p; + return InlineAsm::ConstraintCode::Unknown; } /// Try to replace an X constraint, which matches anything, with another that diff --git a/llvm/include/llvm/IR/InlineAsm.h b/llvm/include/llvm/IR/InlineAsm.h index 8a129337f5926..1df74bb28406b 100644 --- a/llvm/include/llvm/IR/InlineAsm.h +++ b/llvm/include/llvm/IR/InlineAsm.h @@ -217,48 +217,6 @@ class InlineAsm final : public Value { Extra_MayLoad = 8, Extra_MayStore = 16, Extra_IsConvergent = 32, - - // Memory constraint codes. - // These could be tablegenerated but there's little need to do that since - // there's plenty of space in the encoding to support the union of all - // constraint codes for all targets. - // Addresses are included here as they need to be treated the same by the - // backend, the only difference is that they are not used to actaully - // access memory by the instruction. - // TODO: convert to enum? - Constraint_Unknown = 0, - Constraint_es, - Constraint_i, - Constraint_k, - Constraint_m, - Constraint_o, - Constraint_v, - Constraint_A, - Constraint_Q, - Constraint_R, - Constraint_S, - Constraint_T, - Constraint_Um, - Constraint_Un, - Constraint_Uq, - Constraint_Us, - Constraint_Ut, - Constraint_Uv, - Constraint_Uy, - Constraint_X, - Constraint_Z, - Constraint_ZB, - Constraint_ZC, - Constraint_Zy, - - // Address constraints - Constraint_p, - Constraint_ZQ, - Constraint_ZR, - Constraint_ZS, - Constraint_ZT, - - Constraints_Max = Constraint_ZT, }; // Inline asm operands map to multiple SDNode / MachineInstr operands. @@ -274,6 +232,46 @@ class InlineAsm final : public Value { Func = 7, // Address operand of function call }; + // Memory constraint codes. + // Addresses are included here as they need to be treated the same by the + // backend, the only difference is that they are not used to actaully + // access memory by the instruction. + enum class ConstraintCode : uint32_t { + Unknown = 0, + es, + i, + k, + m, + o, + v, + A, + Q, + R, + S, + T, + Um, + Un, + Uq, + Us, + Ut, + Uv, + Uy, + X, + Z, + ZB, + ZC, + Zy, + + // Address constraints + p, + ZQ, + ZR, + ZS, + ZT, + + Max = ZT, + }; + // These are helper methods for dealing with flags in the INLINEASM SDNode // in the backend. // @@ -375,11 +373,14 @@ class InlineAsm final : public Value { return true; } - // TODO: convert to enum? - unsigned getMemoryConstraintID() const { + ConstraintCode getMemoryConstraintID() const { assert((isMemKind() || isFuncKind()) && "Not expected mem or function flag!"); - return getData(); + uint32_t D = getData(); + assert(D < static_cast(ConstraintCode::Max) && + D >= static_cast(ConstraintCode::Unknown) && + "unexpected value for memory constraint"); + return static_cast(D); } /// setMatchingOp - Augment an existing flag with information indicating @@ -403,12 +404,11 @@ class InlineAsm final : public Value { /// setMemConstraint - Augment an existing flag with the constraint code for /// a memory constraint. - void setMemConstraint(unsigned Constraint) { + void setMemConstraint(ConstraintCode C) { assert((isMemKind() || isFuncKind()) && "Flag is not a memory or function constraint!"); - assert(Constraint <= Constraints_Max && "Unknown constraint ID"); assert(getData() == 0 && "Mem constraint already set"); - setData(Constraint); + setData(static_cast(C)); } /// clearMemConstraint - Similar to setMemConstraint(0), but without the /// assertion checking that the constraint has not been set previously. @@ -443,63 +443,63 @@ class InlineAsm final : public Value { return Result; } - static StringRef getMemConstraintName(unsigned Constraint) { - switch (Constraint) { - case InlineAsm::Constraint_es: + static StringRef getMemConstraintName(ConstraintCode C) { + switch (C) { + case ConstraintCode::es: return "es"; - case InlineAsm::Constraint_i: + case ConstraintCode::i: return "i"; - case InlineAsm::Constraint_k: + case ConstraintCode::k: return "k"; - case InlineAsm::Constraint_m: + case ConstraintCode::m: return "m"; - case InlineAsm::Constraint_o: + case ConstraintCode::o: return "o"; - case InlineAsm::Constraint_v: + case ConstraintCode::v: return "v"; - case InlineAsm::Constraint_A: + case InlineAsm::Constraint::A: return "A"; - case InlineAsm::Constraint_Q: + case ConstraintCode::Q: return "Q"; - case InlineAsm::Constraint_R: + case ConstraintCode::R: return "R"; - case InlineAsm::Constraint_S: + case ConstraintCode::S: return "S"; - case InlineAsm::Constraint_T: + case ConstraintCode::T: return "T"; - case InlineAsm::Constraint_Um: + case ConstraintCode::Um: return "Um"; - case InlineAsm::Constraint_Un: + case ConstraintCode::Un: return "Un"; - case InlineAsm::Constraint_Uq: + case ConstraintCode::Uq: return "Uq"; - case InlineAsm::Constraint_Us: + case ConstraintCode::Us: return "Us"; - case InlineAsm::Constraint_Ut: + case ConstraintCode::Ut: return "Ut"; - case InlineAsm::Constraint_Uv: + case ConstraintCode::Uv: return "Uv"; - case InlineAsm::Constraint_Uy: + case ConstraintCode::Uy: return "Uy"; - case InlineAsm::Constraint_X: + case ConstraintCode::X: return "X"; - case InlineAsm::Constraint_Z: + case ConstraintCode::Z: return "Z"; - case InlineAsm::Constraint_ZB: + case ConstraintCode::ZB: return "ZB"; - case InlineAsm::Constraint_ZC: + case ConstraintCode::ZC: return "ZC"; - case InlineAsm::Constraint_Zy: + case ConstraintCode::Zy: return "Zy"; - case InlineAsm::Constraint_p: + case ConstraintCode::p: return "p"; - case InlineAsm::Constraint_ZQ: + case ConstraintCode::ZQ: return "ZQ"; - case InlineAsm::Constraint_ZR: + case ConstraintCode::ZR: return "ZR"; - case InlineAsm::Constraint_ZS: + case ConstraintCode::ZS: return "ZS"; - case InlineAsm::Constraint_ZT: + case ConstraintCode::ZT: return "ZT"; default: llvm_unreachable("Unknown memory constraint"); diff --git a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp index 9944ba1599768..00dba57fcb802 100644 --- a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp +++ b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp @@ -373,9 +373,9 @@ bool InlineAsmLowering::lowerInlineAsm( switch (OpInfo.Type) { case InlineAsm::isOutput: if (OpInfo.ConstraintType == TargetLowering::C_Memory) { - unsigned ConstraintID = + const InlineAsm::ConstraintCode ConstraintID = TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode); - assert(ConstraintID != InlineAsm::Constraint_Unknown && + assert(ConstraintID != InlineAsm::ConstraintCode::Unknown && "Failed to convert memory constraint code to constraint id."); // Add information to the INLINEASM instruction to know about this @@ -517,7 +517,7 @@ bool InlineAsmLowering::lowerInlineAsm( assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); - unsigned ConstraintID = + const InlineAsm::ConstraintCode ConstraintID = TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode); InlineAsm::Flag OpFlags(InlineAsm::Kind::Mem, 1); OpFlags.setMemConstraint(ConstraintID); diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp index 8cc3391e0d96a..d8467e2af8786 100644 --- a/llvm/lib/CodeGen/MachineInstr.cpp +++ b/llvm/lib/CodeGen/MachineInstr.cpp @@ -1778,7 +1778,7 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST, } if (F.isMemKind()) { - const unsigned MCID = F.getMemoryConstraintID(); + const InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID(); OS << ":" << InlineAsm::getMemConstraintName(MCID); } diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 738dd10633db6..720fc49441612 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -9281,9 +9281,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call, switch (OpInfo.Type) { case InlineAsm::isOutput: if (OpInfo.ConstraintType == TargetLowering::C_Memory) { - unsigned ConstraintID = + const InlineAsm::ConstraintCode ConstraintID = TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode); - assert(ConstraintID != InlineAsm::Constraint_Unknown && + assert(ConstraintID != InlineAsm::ConstraintCode::Unknown && "Failed to convert memory constraint code to constraint id."); // Add information to the INLINEASM node to know about this output. @@ -9413,9 +9413,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call, TLI.getPointerTy(DAG.getDataLayout()) && "Memory operands expect pointer values"); - unsigned ConstraintID = + const InlineAsm::ConstraintCode ConstraintID = TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode); - assert(ConstraintID != InlineAsm::Constraint_Unknown && + assert(ConstraintID != InlineAsm::ConstraintCode::Unknown && "Failed to convert memory constraint code to constraint id."); // Add information to the INLINEASM node to know about this input. @@ -9429,9 +9429,9 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call, } if (OpInfo.ConstraintType == TargetLowering::C_Address) { - unsigned ConstraintID = + const InlineAsm::ConstraintCode ConstraintID = TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode); - assert(ConstraintID != InlineAsm::Constraint_Unknown && + assert(ConstraintID != InlineAsm::ConstraintCode::Unknown && "Failed to convert memory constraint code to constraint id."); InlineAsm::Flag ResOpType(InlineAsm::Kind::Mem, 1); diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index a7873241df62e..91b9d77eed705 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -2101,7 +2101,8 @@ void SelectionDAGISel::SelectInlineAsmMemoryOperands(std::vector &Ops, // Otherwise, this is a memory operand. Ask the target to select it. std::vector SelOps; - unsigned ConstraintID = Flags.getMemoryConstraintID(); + const InlineAsm::ConstraintCode ConstraintID = + Flags.getMemoryConstraintID(); if (SelectInlineAsmMemoryOperand(InOps[i+1], ConstraintID, SelOps)) report_fatal_error("Could not match memory address. Inline asm" " failure!"); diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp index 686044ea572ac..bf1605f06bd88 100644 --- a/llvm/lib/CodeGen/TargetInstrInfo.cpp +++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp @@ -1622,7 +1622,7 @@ std::string TargetInstrInfo::createMIROperandComment( } if (F.isMemKind()) { - const unsigned MCID = F.getMemoryConstraintID(); + InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID(); OS << ":" << InlineAsm::getMemConstraintName(MCID); } diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp index 60a155a86667e..16ab662ca34aa 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp @@ -62,7 +62,7 @@ class AArch64DAGToDAGISel : public SelectionDAGISel { /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for /// inline asm expressions. bool SelectInlineAsmMemoryOperand(const SDValue &Op, - unsigned ConstraintID, + InlineAsm::ConstraintCode ConstraintID, std::vector &OutOps) override; template @@ -533,13 +533,14 @@ static bool isIntImmediateEq(SDValue N, const uint64_t ImmExpected) { #endif bool AArch64DAGToDAGISel::SelectInlineAsmMemoryOperand( - const SDValue &Op, unsigned ConstraintID, std::vector &OutOps) { + const SDValue &Op, const InlineAsm::ConstraintCode ConstraintID, + std::vector &OutOps) { switch(ConstraintID) { default: llvm_unreachable("Unexpected asm memory constraint"); - case InlineAsm::Constraint_m: - case InlineAsm::Constraint_o: - case InlineAsm::Constraint_Q: + case InlineAsm::ConstraintCode::m: + case InlineAsm::ConstraintCode::o: + case InlineAsm::ConstraintCode::Q: // We need to make sure that this one operand does not end up in XZR, thus // require the address to be in a PointerRegClass register. const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo(); diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h index 67c344318e0d3..f2696b6b97593 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h @@ -1169,9 +1169,10 @@ class AArch64TargetLowering : public TargetLowering { std::vector &Ops, SelectionDAG &DAG) const override; - unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override { + InlineAsm::ConstraintCode + getInlineAsmMemConstraint(StringRef ConstraintCode) const override { if (ConstraintCode == "Q") - return InlineAsm::Constraint_Q; + return InlineAsm::ConstraintCode::Q; // FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are // followed by llvm_unreachable so we'll leave them unimplemented in // the backend for now. diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp index 5f4fab0675824..acd2e4b052b65 100644 --- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -331,7 +331,8 @@ class ARMDAGToDAGISel : public SelectionDAGISel { /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for /// inline asm expressions. - bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, + bool SelectInlineAsmMemoryOperand(const SDValue &Op, + InlineAsm::ConstraintCode ConstraintID, std::vector &OutOps) override; // Form pairs of consecutive R, S, D, or Q registers. @@ -5864,23 +5865,22 @@ bool ARMDAGToDAGISel::tryInlineAsm(SDNode *N){ return true; } - -bool ARMDAGToDAGISel:: -SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, - std::vector &OutOps) { +bool ARMDAGToDAGISel::SelectInlineAsmMemoryOperand( + const SDValue &Op, InlineAsm::ConstraintCode ConstraintID, + std::vector &OutOps) { switch(ConstraintID) { default: llvm_unreachable("Unexpected asm memory constraint"); - case InlineAsm::Constraint_m: - case InlineAsm::Constraint_o: - case InlineAsm::Constraint_Q: - case InlineAsm::Constraint_Um: - case InlineAsm::Constraint_Un: - case InlineAsm::Constraint_Uq: - case InlineAsm::Constraint_Us: - case InlineAsm::Constraint_Ut: - case InlineAsm::Constraint_Uv: - case InlineAsm::Constraint_Uy: + case InlineAsm::ConstraintCode::m: + case InlineAsm::ConstraintCode::o: + case InlineAsm::ConstraintCode::Q: + case InlineAsm::ConstraintCode::Um: + case InlineAsm::ConstraintCode::Un: + case InlineAsm::ConstraintCode::Uq: + case InlineAsm::ConstraintCode::Us: + case InlineAsm::ConstraintCode::Ut: + case InlineAsm::ConstraintCode::Uv: + case InlineAsm::ConstraintCode::Uy: // Require the address to be in a register. That is safe for all ARM // variants and it is hard to do anything much smarter without knowing // how the operand is used. diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h index 2dd54602ef61b..efa8238676860 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.h +++ b/llvm/lib/Target/ARM/ARMISelLowering.h @@ -534,29 +534,29 @@ class VectorType; std::vector &Ops, SelectionDAG &DAG) const override; - unsigned + InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const override { if (ConstraintCode == "Q") - return InlineAsm::Constraint_Q; - else if (ConstraintCode.size() == 2) { + return InlineAsm::ConstraintCode::Q; + if (ConstraintCode.size() == 2) { if (ConstraintCode[0] == 'U') { switch(ConstraintCode[1]) { default: break; case 'm': - return InlineAsm::Constraint_Um; + return InlineAsm::ConstraintCode::Um; case 'n': - return InlineAsm::Constraint_Un; + return InlineAsm::ConstraintCode::Un; case 'q': - return InlineAsm::Constraint_Uq; + return InlineAsm::ConstraintCode::Uq; case 's': - return InlineAsm::Constraint_Us; + return InlineAsm::ConstraintCode::Us; case 't': - return InlineAsm::Constraint_Ut; + return InlineAsm::ConstraintCode::Ut; case 'v': - return InlineAsm::Constraint_Uv; + return InlineAsm::ConstraintCode::Uv; case 'y': - return InlineAsm::Constraint_Uy; + return InlineAsm::ConstraintCode::Uy; } } } diff --git a/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp b/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp index bbb1de40be634..214799aa31a9c 100644 --- a/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp +++ b/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp @@ -43,7 +43,8 @@ class AVRDAGToDAGISel : public SelectionDAGISel { bool selectIndexedLoad(SDNode *N); unsigned selectIndexedProgMemLoad(const LoadSDNode *LD, MVT VT, int Bank); - bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintCode, + bool SelectInlineAsmMemoryOperand(const SDValue &Op, + InlineAsm::ConstraintCode ConstraintCode, std::vector &OutOps) override; // Include the pieces autogenerated from the target description. @@ -200,9 +201,10 @@ unsigned AVRDAGToDAGISel::selectIndexedProgMemLoad(const LoadSDNode *LD, MVT VT, } bool AVRDAGToDAGISel::SelectInlineAsmMemoryOperand( - const SDValue &Op, unsigned ConstraintCode, std::vector &OutOps) { - assert((ConstraintCode == InlineAsm::Constraint_m || - ConstraintCode == InlineAsm::Constraint_Q) && + const SDValue &Op, InlineAsm::ConstraintCode ConstraintCode, + std::vector &OutOps) { + assert((ConstraintCode == InlineAsm::ConstraintCode::m || + ConstraintCode == InlineAsm::ConstraintCode::Q) && "Unexpected asm memory constraint"); MachineRegisterInfo &RI = MF->getRegInfo(); diff --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp b/llvm/lib/Target/AVR/AVRISelLowering.cpp index 2b73704090851..4f5a48bd05a4e 100644 --- a/llvm/lib/Target/AVR/AVRISelLowering.cpp +++ b/llvm/lib/Target/AVR/AVRISelLowering.cpp @@ -2521,13 +2521,13 @@ AVRTargetLowering::getConstraintType(StringRef Constraint) const { return TargetLowering::getConstraintType(Constraint); } -unsigned +InlineAsm::ConstraintCode AVRTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const { // Not sure if this is actually the right thing to do, but we got to do // *something* [agnat] switch (ConstraintCode[0]) { case 'Q': - return InlineAsm::Constraint_Q; + return InlineAsm::ConstraintCode::Q; } return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); } diff --git a/llvm/lib/Target/AVR/AVRISelLowering.h b/llvm/lib/Target/AVR/AVRISelLowering.h index b696bebe7136f..6815b519bebf7 100644 --- a/llvm/lib/Target/AVR/AVRISelLowering.h +++ b/llvm/lib/Target/AVR/AVRISelLowering.h @@ -133,7 +133,8 @@ class AVRTargetLowering : public TargetLowering { getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override; - unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override; + InlineAsm::ConstraintCode + getInlineAsmMemConstraint(StringRef ConstraintCode) const override; void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector &Ops, diff --git a/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp b/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp index 32fa4ea1e302b..1a3c9f14c1d5a 100644 --- a/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp +++ b/llvm/lib/Target/CSKY/CSKYISelDAGToDAG.cpp @@ -48,7 +48,8 @@ class CSKYDAGToDAGISel : public SelectionDAGISel { SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1); - bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, + bool SelectInlineAsmMemoryOperand(const SDValue &Op, + InlineAsm::ConstraintCode ConstraintID, std::vector &OutOps) override; #include "CSKYGenDAGISel.inc" @@ -383,9 +384,10 @@ SDNode *CSKYDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) { } bool CSKYDAGToDAGISel::SelectInlineAsmMemoryOperand( - const SDValue &Op, unsigned ConstraintID, std::vector &OutOps) { + const SDValue &Op, const InlineAsm::ConstraintCode ConstraintID, + std::vector &OutOps) { switch (ConstraintID) { - case InlineAsm::Constraint_m: + case InlineAsm::ConstraintCode::m: // We just support simple memory operands that have a single address // operand and need no special handling. OutOps.push_back(Op); diff --git a/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp b/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp index e33654ea3f186..c400c9a3fc992 100644 --- a/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp +++ b/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp @@ -227,7 +227,8 @@ class M68kDAGToDAGISel : public SelectionDAGISel { bool SelectPCD(SDNode *Parent, SDValue N, SDValue &Imm); bool SelectPCI(SDNode *Parent, SDValue N, SDValue &Imm, SDValue &Index); - bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, + bool SelectInlineAsmMemoryOperand(const SDValue &Op, + InlineAsm::ConstraintCode ConstraintID, std::vector &OutOps) override; // If Address Mode represents Frame Index store FI in Disp and @@ -953,7 +954,8 @@ bool M68kDAGToDAGISel::SelectARI(SDNode *Parent, SDValue N, SDValue &Base) { } bool M68kDAGToDAGISel::SelectInlineAsmMemoryOperand( - const SDValue &Op, unsigned ConstraintID, std::vector &OutOps) { + const SDValue &Op, InlineAsm::ConstraintCode ConstraintID, + std::vector &OutOps) { // In order to tell AsmPrinter the exact addressing mode we select here, which // might comprise of multiple SDValues (hence MachineOperands), a 32-bit // immediate value is prepended to the list of selected SDValues to indicate @@ -966,7 +968,7 @@ bool M68kDAGToDAGISel::SelectInlineAsmMemoryOperand( switch (ConstraintID) { // Generic memory operand. - case InlineAsm::Constraint_m: { + case InlineAsm::ConstraintCode::m: { // Try every supported (memory) addressing modes. SDValue Operands[4]; @@ -997,7 +999,7 @@ bool M68kDAGToDAGISel::SelectInlineAsmMemoryOperand( return true; } // 'Q': Address register indirect addressing. - case InlineAsm::Constraint_Q: { + case InlineAsm::ConstraintCode::Q: { SDValue AMKind, Base; // 'j' addressing mode. // TODO: Add support for 'o' and 'e' after their @@ -1009,7 +1011,7 @@ bool M68kDAGToDAGISel::SelectInlineAsmMemoryOperand( return true; } // 'U': Address register indirect w/ constant offset addressing. - case InlineAsm::Constraint_Um: { + case InlineAsm::ConstraintCode::Um: { SDValue AMKind, Base, Offset; // 'p' addressing mode. if (SelectARID(nullptr, Op, Offset, Base) && addKind(AMKind, AMK::p)) { diff --git a/llvm/lib/Target/M68k/M68kISelLowering.cpp b/llvm/lib/Target/M68k/M68kISelLowering.cpp index ae3c348a59999..82f6d7323cf60 100644 --- a/llvm/lib/Target/M68k/M68kISelLowering.cpp +++ b/llvm/lib/Target/M68k/M68kISelLowering.cpp @@ -204,11 +204,12 @@ M68kTargetLowering::getExceptionSelectorRegister(const Constant *) const { return M68k::D1; } -unsigned +InlineAsm::ConstraintCode M68kTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const { - return StringSwitch(ConstraintCode) - .Case("Q", InlineAsm::Constraint_Q) - .Case("U", InlineAsm::Constraint_Um) // We borrow Constraint_Um for 'U'. + return StringSwitch(ConstraintCode) + .Case("Q", InlineAsm::ConstraintCode::Q) + // We borrow ConstraintCode::Um for 'U'. + .Case("U", InlineAsm::ConstraintCode::Um) .Default(TargetLowering::getInlineAsmMemConstraint(ConstraintCode)); } diff --git a/llvm/lib/Target/M68k/M68kISelLowering.h b/llvm/lib/Target/M68k/M68kISelLowering.h index 5f279b3dcbd3e..37e66695fde90 100644 --- a/llvm/lib/Target/M68k/M68kISelLowering.h +++ b/llvm/lib/Target/M68k/M68kISelLowering.h @@ -187,7 +187,8 @@ class M68kTargetLowering : public TargetLowering { Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override; - unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override; + InlineAsm::ConstraintCode + getInlineAsmMemConstraint(StringRef ConstraintCode) const override; private: unsigned GetAlignedArgumentStackSize(unsigned StackSize, diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp index c6cefc000b3f7..d5c1ab4718dbd 100644 --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -2163,12 +2163,13 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) { } bool RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand( - const SDValue &Op, unsigned ConstraintID, std::vector &OutOps) { + const SDValue &Op, InlineAsm::ConstraintCode ConstraintID, + std::vector &OutOps) { // Always produce a register and immediate operand, as expected by // RISCVAsmPrinter::PrintAsmMemoryOperand. switch (ConstraintID) { - case InlineAsm::Constraint_o: - case InlineAsm::Constraint_m: { + case InlineAsm::ConstraintCode::o: + case InlineAsm::ConstraintCode::m: { SDValue Op0, Op1; bool Found = SelectAddrRegImm(Op, Op0, Op1); assert(Found && "SelectAddrRegImm should always succeed"); @@ -2177,7 +2178,7 @@ bool RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand( OutOps.push_back(Op1); return false; } - case InlineAsm::Constraint_A: + case InlineAsm::ConstraintCode::A: OutOps.push_back(Op); OutOps.push_back( CurDAG->getTargetConstant(0, SDLoc(Op), Subtarget->getXLenVT())); diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h index fbc1520a54ba0..b9117a4c5efea 100644 --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h @@ -43,7 +43,8 @@ class RISCVDAGToDAGISel : public SelectionDAGISel { void Select(SDNode *Node) override; - bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, + bool SelectInlineAsmMemoryOperand(const SDValue &Op, + InlineAsm::ConstraintCode ConstraintID, std::vector &OutOps) override; bool SelectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset); diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index a470ceae90ce5..a89961dccc70f 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -17418,13 +17418,13 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, return Res; } -unsigned +InlineAsm::ConstraintCode RISCVTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const { // Currently only support length 1 constraints. if (ConstraintCode.size() == 1) { switch (ConstraintCode[0]) { case 'A': - return InlineAsm::Constraint_A; + return InlineAsm::ConstraintCode::A; default: break; } diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h index 44d421c9cae73..271391826e35f 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.h +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h @@ -566,7 +566,8 @@ class RISCVTargetLowering : public TargetLowering { ConstraintType getConstraintType(StringRef Constraint) const override; - unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override; + InlineAsm::ConstraintCode + getInlineAsmMemConstraint(StringRef ConstraintCode) const override; std::pair getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp index 5ebb0a8239aa3..fed26111f60ec 100644 --- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -259,7 +259,7 @@ namespace { /// Implement addressing mode selection for inline asm expressions. bool SelectInlineAsmMemoryOperand(const SDValue &Op, - unsigned ConstraintID, + InlineAsm::ConstraintCode ConstraintID, std::vector &OutOps) override; void emitSpecialCodeForMain(); @@ -6323,18 +6323,18 @@ void X86DAGToDAGISel::Select(SDNode *Node) { SelectCode(Node); } -bool X86DAGToDAGISel:: -SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, - std::vector &OutOps) { +bool X86DAGToDAGISel::SelectInlineAsmMemoryOperand( + const SDValue &Op, InlineAsm::ConstraintCode ConstraintID, + std::vector &OutOps) { SDValue Op0, Op1, Op2, Op3, Op4; switch (ConstraintID) { default: llvm_unreachable("Unexpected asm memory constraint"); - case InlineAsm::Constraint_o: // offsetable ?? - case InlineAsm::Constraint_v: // not offsetable ?? - case InlineAsm::Constraint_m: // memory - case InlineAsm::Constraint_X: - case InlineAsm::Constraint_p: // address + case InlineAsm::ConstraintCode::o: // offsetable ?? + case InlineAsm::ConstraintCode::v: // not offsetable ?? + case InlineAsm::ConstraintCode::m: // memory + case InlineAsm::ConstraintCode::X: + case InlineAsm::ConstraintCode::p: // address if (!selectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4)) return true; break; diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h index 5689543fcd1fa..4d45a0a584421 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.h +++ b/llvm/lib/Target/X86/X86ISelLowering.h @@ -1279,10 +1279,10 @@ namespace llvm { std::vector &Ops, SelectionDAG &DAG) const override; - unsigned + InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const override { if (ConstraintCode == "v") - return InlineAsm::Constraint_v; + return InlineAsm::ConstraintCode::v; return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); }