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@topperc topperc Sep 22, 2023
If all uses aren't folded, then this would increase register pressure wouldn't it?
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@mgudim mgudim Sep 22, 2023
I just realized I should also include FP loads and stores.
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
topperc
@michaelmaitland michaelmaitland Sep 22, 2023
I think you already check `Opcode == ADDI` and `Operand0.isReg()` in `tryToFoldInstIntoUse`
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
mgudim
@michaelmaitland michaelmaitland Sep 22, 2023
Should this be an assert since we know this instruction is an ADDI?
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
topperc mgudim
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