diff --git a/llvm/include/llvm/Support/BlockFrequency.h b/llvm/include/llvm/Support/BlockFrequency.h
index 8b172ee486aab..52348b9cba7be 100644
--- a/llvm/include/llvm/Support/BlockFrequency.h
+++ b/llvm/include/llvm/Support/BlockFrequency.h
@@ -14,8 +14,10 @@
 #define LLVM_SUPPORT_BLOCKFREQUENCY_H
 
 #include <cassert>
+#include <climits>
 #include <cstdint>
 #include <optional>
+#include <utility>
 
 namespace llvm {
 
@@ -94,6 +96,32 @@ class BlockFrequency {
     return *this;
   }
 
+  /// Returns true if `this` is smaller or greater than `other` and the
+  /// magnitude of the difference is below the topmost `SignificantBits` of
+  /// `this`.
+  ///
+  /// The formula is related to comparing a "relative change" to a threshold.
+  /// When choosing the threshold as a negative power-of-two things can be
+  /// computed cheaply:
+  ///   with A = max(this->Frequency, Other.Frequency);
+  ///        B = min(Other.Frequency, this->Frequency); T = SignificantBits
+  ///   relative_change(A, B) = abs(A - B) / A
+  ///         (A - B) / A  <=  2**(-T)
+  ///   <=>   A - B        <=  2**(-T) * A
+  ///   <=>   A - B        <=  shr(A, T)
+  bool almostEqual(BlockFrequency Other, unsigned SignificantBits = 20) const {
+    assert(0 <= SignificantBits &&
+           SignificantBits < sizeof(Frequency) * CHAR_BIT &&
+           "invalid SignificantBits value");
+    uint64_t Max = Frequency;
+    uint64_t Min = Other.Frequency;
+    if (Max < Min)
+      std::swap(Min, Max);
+    uint64_t Diff = Max - Min;
+    uint64_t Threshold = Max >> SignificantBits;
+    return Diff <= Threshold;
+  }
+
   bool operator<(BlockFrequency RHS) const {
     return Frequency < RHS.Frequency;
   }
diff --git a/llvm/lib/CodeGen/MachineBlockPlacement.cpp b/llvm/lib/CodeGen/MachineBlockPlacement.cpp
index d0d3574b30bfd..7eabad2bcb1f4 100644
--- a/llvm/lib/CodeGen/MachineBlockPlacement.cpp
+++ b/llvm/lib/CodeGen/MachineBlockPlacement.cpp
@@ -1715,7 +1715,8 @@ MachineBasicBlock *MachineBlockPlacement::selectBestCandidateBlock(
 
   bool IsEHPad = WorkList[0]->isEHPad();
 
-  MachineBasicBlock *BestBlock = nullptr;
+  MachineBasicBlock *ChainEnd = *std::prev(Chain.end());
+  MachineBasicBlock *LayoutSucc = ChainEnd->getNextNode();
   BlockFrequency BestFreq;
   for (MachineBasicBlock *MBB : WorkList) {
     assert(MBB->isEHPad() == IsEHPad &&
@@ -1731,7 +1732,8 @@ MachineBasicBlock *MachineBlockPlacement::selectBestCandidateBlock(
     BlockFrequency CandidateFreq = MBFI->getBlockFreq(MBB);
     LLVM_DEBUG(dbgs() << "    " << getBlockName(MBB) << " -> "
                       << printBlockFreq(MBFI->getMBFI(), CandidateFreq)
-                      << " (freq)\n");
+                      << " (freq) is_layoutsucc " << (MBB == LayoutSucc)
+                      << '\n');
 
     // For ehpad, we layout the least probable first as to avoid jumping back
     // from least probable landingpads to more probable ones.
@@ -1751,12 +1753,27 @@ MachineBasicBlock *MachineBlockPlacement::selectBestCandidateBlock(
     //                 +-------------------------------------+
     //                 V                                     |
     // OuterLp -> OuterCleanup -> Resume     InnerLp -> InnerCleanup
-    if (BestBlock && (IsEHPad ^ (BestFreq >= CandidateFreq)))
+    if (BestFreq > BlockFrequency(0) && (IsEHPad ^ (BestFreq >= CandidateFreq)))
       continue;
 
-    BestBlock = MBB;
     BestFreq = CandidateFreq;
   }
+  // Perform a 2nd pass to make the output more stable: Check for blocks with
+  // almost the same frequency as `BestFreq` and prefer the one that is already
+  // a successor to `ChainEnd` first or whichever comes first in `WorkList`.
+  MachineBasicBlock *BestBlock = nullptr;
+  for (MachineBasicBlock *MBB : WorkList) {
+    // Give precedence to the layout successor otherwise the first candidate.
+    if (BestBlock != nullptr && MBB != LayoutSucc)
+      continue;
+    BlockChain &SuccChain = *BlockToChain[MBB];
+    if (&SuccChain == &Chain)
+      continue;
+    BlockFrequency CandidateFreq = MBFI->getBlockFreq(MBB);
+    if (!BestFreq.almostEqual(CandidateFreq))
+      continue;
+    BestBlock = MBB;
+  }
 
   return BestBlock;
 }
diff --git a/llvm/test/CodeGen/AArch64/cfi-fixup.ll b/llvm/test/CodeGen/AArch64/cfi-fixup.ll
index 9a4ad3bb07ee3..e746ea745b92a 100644
--- a/llvm/test/CodeGen/AArch64/cfi-fixup.ll
+++ b/llvm/test/CodeGen/AArch64/cfi-fixup.ll
@@ -8,13 +8,13 @@ define i32 @f0(i32 %x) #0 {
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    .cfi_offset w30, -16
 ; CHECK-NEXT:    .cfi_remember_state
-; CHECK-NEXT:    cbz w0, .LBB0_4
+; CHECK-NEXT:    cbz w0, .LBB0_6
 ; CHECK-NEXT:  // %bb.1: // %entry
 ; CHECK-NEXT:    cmp w0, #2
-; CHECK-NEXT:    b.eq .LBB0_5
+; CHECK-NEXT:    b.eq .LBB0_4
 ; CHECK-NEXT:  // %bb.2: // %entry
 ; CHECK-NEXT:    cmp w0, #1
-; CHECK-NEXT:    b.ne .LBB0_6
+; CHECK-NEXT:    b.ne .LBB0_5
 ; CHECK-NEXT:  // %bb.3: // %if.then2
 ; CHECK-NEXT:    bl g1
 ; CHECK-NEXT:    add w0, w0, #1
@@ -22,27 +22,27 @@ define i32 @f0(i32 %x) #0 {
 ; CHECK-NEXT:    .cfi_def_cfa_offset 0
 ; CHECK-NEXT:    .cfi_restore w30
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB0_4:
+; CHECK-NEXT:  .LBB0_4: // %if.then5
 ; CHECK-NEXT:    .cfi_restore_state
 ; CHECK-NEXT:    .cfi_remember_state
-; CHECK-NEXT:    mov w0, #1
+; CHECK-NEXT:    bl g0
+; CHECK-NEXT:    mov w8, #1 // =0x1
+; CHECK-NEXT:    sub w0, w8, w0
 ; CHECK-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    .cfi_def_cfa_offset 0
 ; CHECK-NEXT:    .cfi_restore w30
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB0_5: // %if.then5
+; CHECK-NEXT:  .LBB0_5: // %if.end7
 ; CHECK-NEXT:    .cfi_restore_state
 ; CHECK-NEXT:    .cfi_remember_state
-; CHECK-NEXT:    bl g0
-; CHECK-NEXT:    mov w8, #1
-; CHECK-NEXT:    sub w0, w8, w0
+; CHECK-NEXT:    mov w0, wzr
 ; CHECK-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    .cfi_def_cfa_offset 0
 ; CHECK-NEXT:    .cfi_restore w30
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB0_6: // %if.end7
+; CHECK-NEXT:  .LBB0_6:
 ; CHECK-NEXT:    .cfi_restore_state
-; CHECK-NEXT:    mov w0, wzr
+; CHECK-NEXT:    mov w0, #1 // =0x1
 ; CHECK-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    .cfi_def_cfa_offset 0
 ; CHECK-NEXT:    .cfi_restore w30
@@ -115,7 +115,7 @@ define i32 @f2(i32 %x) #0 {
 ; CHECK-NEXT:    cbz w0, .LBB2_2
 ; CHECK-NEXT:  // %bb.1: // %if.end
 ; CHECK-NEXT:    bl g1
-; CHECK-NEXT:    mov w8, #1
+; CHECK-NEXT:    mov w8, #1 // =0x1
 ; CHECK-NEXT:    sub w0, w8, w0
 ; CHECK-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    .cfi_def_cfa_offset 0
diff --git a/llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll b/llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
index ca51994b92203..f284df4d8a70b 100644
--- a/llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
+++ b/llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
@@ -1,10 +1,68 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
 
-; GCN-LABEL: {{^}}negated_cond:
-; GCN: .LBB0_2:
-; GCN:   v_cndmask_b32_e64
-; GCN:   v_cmp_ne_u32_e64
 define amdgpu_kernel void @negated_cond(ptr addrspace(1) %arg1) {
+; GCN-LABEL: negated_cond:
+; GCN:       ; %bb.0: ; %bb
+; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GCN-NEXT:    s_mov_b32 s7, 0xf000
+; GCN-NEXT:    s_mov_b32 s10, -1
+; GCN-NEXT:    s_mov_b32 s6, 0
+; GCN-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-NEXT:    s_mov_b64 s[8:9], s[4:5]
+; GCN-NEXT:    v_mov_b32_e32 v0, 0
+; GCN-NEXT:    s_branch .LBB0_2
+; GCN-NEXT:  .LBB0_1: ; %loop.exit.guard
+; GCN-NEXT:    ; in Loop: Header=BB0_2 Depth=1
+; GCN-NEXT:    s_and_b64 vcc, exec, s[14:15]
+; GCN-NEXT:    s_cbranch_vccnz .LBB0_9
+; GCN-NEXT:  .LBB0_2: ; %bb1
+; GCN-NEXT:    ; =>This Loop Header: Depth=1
+; GCN-NEXT:    ; Child Loop BB0_4 Depth 2
+; GCN-NEXT:    s_mov_b32 s11, s7
+; GCN-NEXT:    buffer_load_dword v1, off, s[8:11], 0
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    v_cmp_ne_u32_e64 s[2:3], 0, v1
+; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
+; GCN-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc
+; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 1, v1
+; GCN-NEXT:    s_mov_b32 s12, s6
+; GCN-NEXT:    s_branch .LBB0_4
+; GCN-NEXT:  .LBB0_3: ; %Flow1
+; GCN-NEXT:    ; in Loop: Header=BB0_4 Depth=2
+; GCN-NEXT:    s_andn2_b64 vcc, exec, s[16:17]
+; GCN-NEXT:    s_cbranch_vccz .LBB0_1
+; GCN-NEXT:  .LBB0_4: ; %bb2
+; GCN-NEXT:    ; Parent Loop BB0_2 Depth=1
+; GCN-NEXT:    ; => This Inner Loop Header: Depth=2
+; GCN-NEXT:    s_and_b64 vcc, exec, s[0:1]
+; GCN-NEXT:    s_lshl_b32 s12, s12, 5
+; GCN-NEXT:    s_cbranch_vccz .LBB0_6
+; GCN-NEXT:  ; %bb.5: ; in Loop: Header=BB0_4 Depth=2
+; GCN-NEXT:    s_mov_b64 s[14:15], s[2:3]
+; GCN-NEXT:    s_branch .LBB0_7
+; GCN-NEXT:  .LBB0_6: ; %bb3
+; GCN-NEXT:    ; in Loop: Header=BB0_4 Depth=2
+; GCN-NEXT:    s_add_i32 s12, s12, 1
+; GCN-NEXT:    s_mov_b64 s[14:15], -1
+; GCN-NEXT:  .LBB0_7: ; %Flow
+; GCN-NEXT:    ; in Loop: Header=BB0_4 Depth=2
+; GCN-NEXT:    s_andn2_b64 vcc, exec, s[14:15]
+; GCN-NEXT:    s_mov_b64 s[16:17], -1
+; GCN-NEXT:    s_cbranch_vccnz .LBB0_3
+; GCN-NEXT:  ; %bb.8: ; %bb4
+; GCN-NEXT:    ; in Loop: Header=BB0_4 Depth=2
+; GCN-NEXT:    s_ashr_i32 s13, s12, 31
+; GCN-NEXT:    s_lshl_b64 s[16:17], s[12:13], 2
+; GCN-NEXT:    s_mov_b64 s[14:15], 0
+; GCN-NEXT:    v_mov_b32_e32 v1, s16
+; GCN-NEXT:    v_mov_b32_e32 v2, s17
+; GCN-NEXT:    buffer_store_dword v0, v[1:2], s[4:7], 0 addr64
+; GCN-NEXT:    s_cmp_eq_u32 s12, 32
+; GCN-NEXT:    s_cselect_b64 s[16:17], -1, 0
+; GCN-NEXT:    s_branch .LBB0_3
+; GCN-NEXT:  .LBB0_9: ; %DummyReturnBlock
+; GCN-NEXT:    s_endpgm
 bb:
   br label %bb1
 
@@ -30,20 +88,51 @@ bb4:
   br i1 %tmp7, label %bb1, label %bb2
 }
 
-; GCN-LABEL: {{^}}negated_cond_dominated_blocks:
-; GCN:   s_cmp_lg_u32
-; GCN:   s_cselect_b64  [[CC1:[^,]+]], -1, 0
-; GCN:   s_branch [[BB1:.LBB[0-9]+_[0-9]+]]
-; GCN: [[BB0:.LBB[0-9]+_[0-9]+]]
-; GCN-NOT: v_cndmask_b32
-; GCN-NOT: v_cmp
-; GCN: [[BB1]]:
-; GCN:   s_mov_b64 vcc, [[CC1]]
-; GCN:   s_cbranch_vccz [[BB2:.LBB[0-9]+_[0-9]+]]
-; GCN:   s_mov_b64 vcc, exec
-; GCN:   s_cbranch_execnz [[BB0]]
-; GCN: [[BB2]]:
 define amdgpu_kernel void @negated_cond_dominated_blocks(ptr addrspace(1) %arg1) {
+; GCN-LABEL: negated_cond_dominated_blocks:
+; GCN:       ; %bb.0: ; %bb
+; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GCN-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GCN-NEXT:    s_mov_b32 s6, 0
+; GCN-NEXT:    s_mov_b32 s7, 0xf000
+; GCN-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-NEXT:    s_cmp_lg_u32 s0, 0
+; GCN-NEXT:    s_cselect_b64 s[0:1], -1, 0
+; GCN-NEXT:    s_and_b64 s[0:1], exec, s[0:1]
+; GCN-NEXT:    v_mov_b32_e32 v0, 0
+; GCN-NEXT:    s_mov_b32 s3, s6
+; GCN-NEXT:    s_branch .LBB1_2
+; GCN-NEXT:  .LBB1_1: ; %bb7
+; GCN-NEXT:    ; in Loop: Header=BB1_2 Depth=1
+; GCN-NEXT:    s_ashr_i32 s3, s2, 31
+; GCN-NEXT:    s_lshl_b64 s[8:9], s[2:3], 2
+; GCN-NEXT:    v_mov_b32_e32 v1, s8
+; GCN-NEXT:    v_mov_b32_e32 v2, s9
+; GCN-NEXT:    s_cmp_eq_u32 s2, 32
+; GCN-NEXT:    buffer_store_dword v0, v[1:2], s[4:7], 0 addr64
+; GCN-NEXT:    s_mov_b32 s3, s2
+; GCN-NEXT:    s_cbranch_scc1 .LBB1_6
+; GCN-NEXT:  .LBB1_2: ; %bb4
+; GCN-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GCN-NEXT:    s_mov_b64 vcc, s[0:1]
+; GCN-NEXT:    s_cbranch_vccz .LBB1_4
+; GCN-NEXT:  ; %bb.3: ; %bb6
+; GCN-NEXT:    ; in Loop: Header=BB1_2 Depth=1
+; GCN-NEXT:    s_add_i32 s2, s3, 1
+; GCN-NEXT:    s_mov_b64 vcc, exec
+; GCN-NEXT:    s_cbranch_execnz .LBB1_1
+; GCN-NEXT:    s_branch .LBB1_5
+; GCN-NEXT:  .LBB1_4: ; in Loop: Header=BB1_2 Depth=1
+; GCN-NEXT:    ; implicit-def: $sgpr2
+; GCN-NEXT:    s_mov_b64 vcc, 0
+; GCN-NEXT:  .LBB1_5: ; %bb5
+; GCN-NEXT:    ; in Loop: Header=BB1_2 Depth=1
+; GCN-NEXT:    s_lshl_b32 s2, s3, 5
+; GCN-NEXT:    s_or_b32 s2, s2, 1
+; GCN-NEXT:    s_branch .LBB1_1
+; GCN-NEXT:  .LBB1_6: ; %bb3
+; GCN-NEXT:    s_endpgm
 bb:
   br label %bb2
 
diff --git a/llvm/test/CodeGen/Generic/machine-function-splitter.ll b/llvm/test/CodeGen/Generic/machine-function-splitter.ll
index 364eadd64c755..cdbf0690356b6 100644
--- a/llvm/test/CodeGen/Generic/machine-function-splitter.ll
+++ b/llvm/test/CodeGen/Generic/machine-function-splitter.ll
@@ -523,7 +523,6 @@ define i32 @foo18(i32 %in) !prof !14 !section_prefix !15 {
 ; MFS-DEFAULTS-LABEL:        foo18
 ; MFS-DEFAULTS:              .section        .text.split.foo18
 ; MFS-DEFAULTS-NEXT:         foo18.cold:
-; MFS-DEFAULTS-SAME:           %common.ret
 ; MFS-DEFAULTS-X86-DAG:        jmp     qux
 ; MFS-DEFAULTS-X86-DAG:        jmp     bam
 ; MFS-DEFAULTS-AARCH64-NOT:    b       bar
diff --git a/llvm/test/CodeGen/Mips/indirect-jump-hazard/jumptables.ll b/llvm/test/CodeGen/Mips/indirect-jump-hazard/jumptables.ll
index b079169974d8b..ff863a19b4918 100644
--- a/llvm/test/CodeGen/Mips/indirect-jump-hazard/jumptables.ll
+++ b/llvm/test/CodeGen/Mips/indirect-jump-hazard/jumptables.ll
@@ -40,7 +40,7 @@ define ptr @_Z3fooi(i32 signext %Letter) {
 ; MIPS32R2-NEXT:    addiu $sp, $sp, -16
 ; MIPS32R2-NEXT:    .cfi_def_cfa_offset 16
 ; MIPS32R2-NEXT:    sltiu $1, $4, 7
-; MIPS32R2-NEXT:    beqz $1, $BB0_3
+; MIPS32R2-NEXT:    beqz $1, $BB0_9
 ; MIPS32R2-NEXT:    sw $4, 4($sp)
 ; MIPS32R2-NEXT:  $BB0_1: # %entry
 ; MIPS32R2-NEXT:    sll $1, $4, 2
@@ -54,39 +54,39 @@ define ptr @_Z3fooi(i32 signext %Letter) {
 ; MIPS32R2-NEXT:    addiu $1, $1, %lo($.str)
 ; MIPS32R2-NEXT:    j $BB0_10
 ; MIPS32R2-NEXT:    sw $1, 8($sp)
-; MIPS32R2-NEXT:  $BB0_3: # %sw.epilog
-; MIPS32R2-NEXT:    lui $1, %hi($.str.7)
-; MIPS32R2-NEXT:    addiu $1, $1, %lo($.str.7)
-; MIPS32R2-NEXT:    j $BB0_10
-; MIPS32R2-NEXT:    sw $1, 8($sp)
-; MIPS32R2-NEXT:  $BB0_4: # %sw.bb1
+; MIPS32R2-NEXT:  $BB0_3: # %sw.bb1
 ; MIPS32R2-NEXT:    lui $1, %hi($.str.1)
 ; MIPS32R2-NEXT:    addiu $1, $1, %lo($.str.1)
 ; MIPS32R2-NEXT:    j $BB0_10
 ; MIPS32R2-NEXT:    sw $1, 8($sp)
-; MIPS32R2-NEXT:  $BB0_5: # %sw.bb2
+; MIPS32R2-NEXT:  $BB0_4: # %sw.bb2
 ; MIPS32R2-NEXT:    lui $1, %hi($.str.2)
 ; MIPS32R2-NEXT:    addiu $1, $1, %lo($.str.2)
 ; MIPS32R2-NEXT:    j $BB0_10
 ; MIPS32R2-NEXT:    sw $1, 8($sp)
-; MIPS32R2-NEXT:  $BB0_6: # %sw.bb3
+; MIPS32R2-NEXT:  $BB0_5: # %sw.bb3
 ; MIPS32R2-NEXT:    lui $1, %hi($.str.3)
 ; MIPS32R2-NEXT:    addiu $1, $1, %lo($.str.3)
 ; MIPS32R2-NEXT:    j $BB0_10
 ; MIPS32R2-NEXT:    sw $1, 8($sp)
-; MIPS32R2-NEXT:  $BB0_7: # %sw.bb4
+; MIPS32R2-NEXT:  $BB0_6: # %sw.bb4
 ; MIPS32R2-NEXT:    lui $1, %hi($.str.4)
 ; MIPS32R2-NEXT:    addiu $1, $1, %lo($.str.4)
 ; MIPS32R2-NEXT:    j $BB0_10
 ; MIPS32R2-NEXT:    sw $1, 8($sp)
-; MIPS32R2-NEXT:  $BB0_8: # %sw.bb5
+; MIPS32R2-NEXT:  $BB0_7: # %sw.bb5
 ; MIPS32R2-NEXT:    lui $1, %hi($.str.5)
 ; MIPS32R2-NEXT:    addiu $1, $1, %lo($.str.5)
 ; MIPS32R2-NEXT:    j $BB0_10
 ; MIPS32R2-NEXT:    sw $1, 8($sp)
-; MIPS32R2-NEXT:  $BB0_9: # %sw.bb6
+; MIPS32R2-NEXT:  $BB0_8: # %sw.bb6
 ; MIPS32R2-NEXT:    lui $1, %hi($.str.6)
 ; MIPS32R2-NEXT:    addiu $1, $1, %lo($.str.6)
+; MIPS32R2-NEXT:    j $BB0_10
+; MIPS32R2-NEXT:    sw $1, 8($sp)
+; MIPS32R2-NEXT:  $BB0_9: # %sw.epilog
+; MIPS32R2-NEXT:    lui $1, %hi($.str.7)
+; MIPS32R2-NEXT:    addiu $1, $1, %lo($.str.7)
 ; MIPS32R2-NEXT:    sw $1, 8($sp)
 ; MIPS32R2-NEXT:  $BB0_10: # %return
 ; MIPS32R2-NEXT:    lw $2, 8($sp)
@@ -98,7 +98,7 @@ define ptr @_Z3fooi(i32 signext %Letter) {
 ; MIPS32R6-NEXT:    addiu $sp, $sp, -16
 ; MIPS32R6-NEXT:    .cfi_def_cfa_offset 16
 ; MIPS32R6-NEXT:    sltiu $1, $4, 7
-; MIPS32R6-NEXT:    beqz $1, $BB0_3
+; MIPS32R6-NEXT:    beqz $1, $BB0_9
 ; MIPS32R6-NEXT:    sw $4, 4($sp)
 ; MIPS32R6-NEXT:  $BB0_1: # %entry
 ; MIPS32R6-NEXT:    sll $1, $4, 2
@@ -112,39 +112,39 @@ define ptr @_Z3fooi(i32 signext %Letter) {
 ; MIPS32R6-NEXT:    addiu $1, $1, %lo($.str)
 ; MIPS32R6-NEXT:    j $BB0_10
 ; MIPS32R6-NEXT:    sw $1, 8($sp)
-; MIPS32R6-NEXT:  $BB0_3: # %sw.epilog
-; MIPS32R6-NEXT:    lui $1, %hi($.str.7)
-; MIPS32R6-NEXT:    addiu $1, $1, %lo($.str.7)
-; MIPS32R6-NEXT:    j $BB0_10
-; MIPS32R6-NEXT:    sw $1, 8($sp)
-; MIPS32R6-NEXT:  $BB0_4: # %sw.bb1
+; MIPS32R6-NEXT:  $BB0_3: # %sw.bb1
 ; MIPS32R6-NEXT:    lui $1, %hi($.str.1)
 ; MIPS32R6-NEXT:    addiu $1, $1, %lo($.str.1)
 ; MIPS32R6-NEXT:    j $BB0_10
 ; MIPS32R6-NEXT:    sw $1, 8($sp)
-; MIPS32R6-NEXT:  $BB0_5: # %sw.bb2
+; MIPS32R6-NEXT:  $BB0_4: # %sw.bb2
 ; MIPS32R6-NEXT:    lui $1, %hi($.str.2)
 ; MIPS32R6-NEXT:    addiu $1, $1, %lo($.str.2)
 ; MIPS32R6-NEXT:    j $BB0_10
 ; MIPS32R6-NEXT:    sw $1, 8($sp)
-; MIPS32R6-NEXT:  $BB0_6: # %sw.bb3
+; MIPS32R6-NEXT:  $BB0_5: # %sw.bb3
 ; MIPS32R6-NEXT:    lui $1, %hi($.str.3)
 ; MIPS32R6-NEXT:    addiu $1, $1, %lo($.str.3)
 ; MIPS32R6-NEXT:    j $BB0_10
 ; MIPS32R6-NEXT:    sw $1, 8($sp)
-; MIPS32R6-NEXT:  $BB0_7: # %sw.bb4
+; MIPS32R6-NEXT:  $BB0_6: # %sw.bb4
 ; MIPS32R6-NEXT:    lui $1, %hi($.str.4)
 ; MIPS32R6-NEXT:    addiu $1, $1, %lo($.str.4)
 ; MIPS32R6-NEXT:    j $BB0_10
 ; MIPS32R6-NEXT:    sw $1, 8($sp)
-; MIPS32R6-NEXT:  $BB0_8: # %sw.bb5
+; MIPS32R6-NEXT:  $BB0_7: # %sw.bb5
 ; MIPS32R6-NEXT:    lui $1, %hi($.str.5)
 ; MIPS32R6-NEXT:    addiu $1, $1, %lo($.str.5)
 ; MIPS32R6-NEXT:    j $BB0_10
 ; MIPS32R6-NEXT:    sw $1, 8($sp)
-; MIPS32R6-NEXT:  $BB0_9: # %sw.bb6
+; MIPS32R6-NEXT:  $BB0_8: # %sw.bb6
 ; MIPS32R6-NEXT:    lui $1, %hi($.str.6)
 ; MIPS32R6-NEXT:    addiu $1, $1, %lo($.str.6)
+; MIPS32R6-NEXT:    j $BB0_10
+; MIPS32R6-NEXT:    sw $1, 8($sp)
+; MIPS32R6-NEXT:  $BB0_9: # %sw.epilog
+; MIPS32R6-NEXT:    lui $1, %hi($.str.7)
+; MIPS32R6-NEXT:    addiu $1, $1, %lo($.str.7)
 ; MIPS32R6-NEXT:    sw $1, 8($sp)
 ; MIPS32R6-NEXT:  $BB0_10: # %return
 ; MIPS32R6-NEXT:    lw $2, 8($sp)
@@ -157,7 +157,7 @@ define ptr @_Z3fooi(i32 signext %Letter) {
 ; MIPS64R2-NEXT:    .cfi_def_cfa_offset 16
 ; MIPS64R2-NEXT:    dext $2, $4, 0, 32
 ; MIPS64R2-NEXT:    sltiu $1, $2, 7
-; MIPS64R2-NEXT:    beqz $1, .LBB0_3
+; MIPS64R2-NEXT:    beqz $1, .LBB0_9
 ; MIPS64R2-NEXT:    sw $4, 4($sp)
 ; MIPS64R2-NEXT:  .LBB0_1: # %entry
 ; MIPS64R2-NEXT:    dsll $1, $2, 3
@@ -179,16 +179,7 @@ define ptr @_Z3fooi(i32 signext %Letter) {
 ; MIPS64R2-NEXT:    daddiu $1, $1, %lo(.L.str)
 ; MIPS64R2-NEXT:    j .LBB0_10
 ; MIPS64R2-NEXT:    sd $1, 8($sp)
-; MIPS64R2-NEXT:  .LBB0_3: # %sw.epilog
-; MIPS64R2-NEXT:    lui $1, %highest(.L.str.7)
-; MIPS64R2-NEXT:    daddiu $1, $1, %higher(.L.str.7)
-; MIPS64R2-NEXT:    dsll $1, $1, 16
-; MIPS64R2-NEXT:    daddiu $1, $1, %hi(.L.str.7)
-; MIPS64R2-NEXT:    dsll $1, $1, 16
-; MIPS64R2-NEXT:    daddiu $1, $1, %lo(.L.str.7)
-; MIPS64R2-NEXT:    j .LBB0_10
-; MIPS64R2-NEXT:    sd $1, 8($sp)
-; MIPS64R2-NEXT:  .LBB0_4: # %sw.bb1
+; MIPS64R2-NEXT:  .LBB0_3: # %sw.bb1
 ; MIPS64R2-NEXT:    lui $1, %highest(.L.str.1)
 ; MIPS64R2-NEXT:    daddiu $1, $1, %higher(.L.str.1)
 ; MIPS64R2-NEXT:    dsll $1, $1, 16
@@ -197,7 +188,7 @@ define ptr @_Z3fooi(i32 signext %Letter) {
 ; MIPS64R2-NEXT:    daddiu $1, $1, %lo(.L.str.1)
 ; MIPS64R2-NEXT:    j .LBB0_10
 ; MIPS64R2-NEXT:    sd $1, 8($sp)
-; MIPS64R2-NEXT:  .LBB0_5: # %sw.bb2
+; MIPS64R2-NEXT:  .LBB0_4: # %sw.bb2
 ; MIPS64R2-NEXT:    lui $1, %highest(.L.str.2)
 ; MIPS64R2-NEXT:    daddiu $1, $1, %higher(.L.str.2)
 ; MIPS64R2-NEXT:    dsll $1, $1, 16
@@ -206,7 +197,7 @@ define ptr @_Z3fooi(i32 signext %Letter) {
 ; MIPS64R2-NEXT:    daddiu $1, $1, %lo(.L.str.2)
 ; MIPS64R2-NEXT:    j .LBB0_10
 ; MIPS64R2-NEXT:    sd $1, 8($sp)
-; MIPS64R2-NEXT:  .LBB0_6: # %sw.bb3
+; MIPS64R2-NEXT:  .LBB0_5: # %sw.bb3
 ; MIPS64R2-NEXT:    lui $1, %highest(.L.str.3)
 ; MIPS64R2-NEXT:    daddiu $1, $1, %higher(.L.str.3)
 ; MIPS64R2-NEXT:    dsll $1, $1, 16
@@ -215,7 +206,7 @@ define ptr @_Z3fooi(i32 signext %Letter) {
 ; MIPS64R2-NEXT:    daddiu $1, $1, %lo(.L.str.3)
 ; MIPS64R2-NEXT:    j .LBB0_10
 ; MIPS64R2-NEXT:    sd $1, 8($sp)
-; MIPS64R2-NEXT:  .LBB0_7: # %sw.bb4
+; MIPS64R2-NEXT:  .LBB0_6: # %sw.bb4
 ; MIPS64R2-NEXT:    lui $1, %highest(.L.str.4)
 ; MIPS64R2-NEXT:    daddiu $1, $1, %higher(.L.str.4)
 ; MIPS64R2-NEXT:    dsll $1, $1, 16
@@ -224,7 +215,7 @@ define ptr @_Z3fooi(i32 signext %Letter) {
 ; MIPS64R2-NEXT:    daddiu $1, $1, %lo(.L.str.4)
 ; MIPS64R2-NEXT:    j .LBB0_10
 ; MIPS64R2-NEXT:    sd $1, 8($sp)
-; MIPS64R2-NEXT:  .LBB0_8: # %sw.bb5
+; MIPS64R2-NEXT:  .LBB0_7: # %sw.bb5
 ; MIPS64R2-NEXT:    lui $1, %highest(.L.str.5)
 ; MIPS64R2-NEXT:    daddiu $1, $1, %higher(.L.str.5)
 ; MIPS64R2-NEXT:    dsll $1, $1, 16
@@ -233,13 +224,22 @@ define ptr @_Z3fooi(i32 signext %Letter) {
 ; MIPS64R2-NEXT:    daddiu $1, $1, %lo(.L.str.5)
 ; MIPS64R2-NEXT:    j .LBB0_10
 ; MIPS64R2-NEXT:    sd $1, 8($sp)
-; MIPS64R2-NEXT:  .LBB0_9: # %sw.bb6
+; MIPS64R2-NEXT:  .LBB0_8: # %sw.bb6
 ; MIPS64R2-NEXT:    lui $1, %highest(.L.str.6)
 ; MIPS64R2-NEXT:    daddiu $1, $1, %higher(.L.str.6)
 ; MIPS64R2-NEXT:    dsll $1, $1, 16
 ; MIPS64R2-NEXT:    daddiu $1, $1, %hi(.L.str.6)
 ; MIPS64R2-NEXT:    dsll $1, $1, 16
 ; MIPS64R2-NEXT:    daddiu $1, $1, %lo(.L.str.6)
+; MIPS64R2-NEXT:    j .LBB0_10
+; MIPS64R2-NEXT:    sd $1, 8($sp)
+; MIPS64R2-NEXT:  .LBB0_9: # %sw.epilog
+; MIPS64R2-NEXT:    lui $1, %highest(.L.str.7)
+; MIPS64R2-NEXT:    daddiu $1, $1, %higher(.L.str.7)
+; MIPS64R2-NEXT:    dsll $1, $1, 16
+; MIPS64R2-NEXT:    daddiu $1, $1, %hi(.L.str.7)
+; MIPS64R2-NEXT:    dsll $1, $1, 16
+; MIPS64R2-NEXT:    daddiu $1, $1, %lo(.L.str.7)
 ; MIPS64R2-NEXT:    sd $1, 8($sp)
 ; MIPS64R2-NEXT:  .LBB0_10: # %return
 ; MIPS64R2-NEXT:    ld $2, 8($sp)
@@ -252,7 +252,7 @@ define ptr @_Z3fooi(i32 signext %Letter) {
 ; MIPS64R6-NEXT:    .cfi_def_cfa_offset 16
 ; MIPS64R6-NEXT:    dext $2, $4, 0, 32
 ; MIPS64R6-NEXT:    sltiu $1, $2, 7
-; MIPS64R6-NEXT:    beqz $1, .LBB0_3
+; MIPS64R6-NEXT:    beqz $1, .LBB0_9
 ; MIPS64R6-NEXT:    sw $4, 4($sp)
 ; MIPS64R6-NEXT:  .LBB0_1: # %entry
 ; MIPS64R6-NEXT:    dsll $1, $2, 3
@@ -274,16 +274,7 @@ define ptr @_Z3fooi(i32 signext %Letter) {
 ; MIPS64R6-NEXT:    daddiu $1, $1, %lo(.L.str)
 ; MIPS64R6-NEXT:    j .LBB0_10
 ; MIPS64R6-NEXT:    sd $1, 8($sp)
-; MIPS64R6-NEXT:  .LBB0_3: # %sw.epilog
-; MIPS64R6-NEXT:    lui $1, %highest(.L.str.7)
-; MIPS64R6-NEXT:    daddiu $1, $1, %higher(.L.str.7)
-; MIPS64R6-NEXT:    dsll $1, $1, 16
-; MIPS64R6-NEXT:    daddiu $1, $1, %hi(.L.str.7)
-; MIPS64R6-NEXT:    dsll $1, $1, 16
-; MIPS64R6-NEXT:    daddiu $1, $1, %lo(.L.str.7)
-; MIPS64R6-NEXT:    j .LBB0_10
-; MIPS64R6-NEXT:    sd $1, 8($sp)
-; MIPS64R6-NEXT:  .LBB0_4: # %sw.bb1
+; MIPS64R6-NEXT:  .LBB0_3: # %sw.bb1
 ; MIPS64R6-NEXT:    lui $1, %highest(.L.str.1)
 ; MIPS64R6-NEXT:    daddiu $1, $1, %higher(.L.str.1)
 ; MIPS64R6-NEXT:    dsll $1, $1, 16
@@ -292,7 +283,7 @@ define ptr @_Z3fooi(i32 signext %Letter) {
 ; MIPS64R6-NEXT:    daddiu $1, $1, %lo(.L.str.1)
 ; MIPS64R6-NEXT:    j .LBB0_10
 ; MIPS64R6-NEXT:    sd $1, 8($sp)
-; MIPS64R6-NEXT:  .LBB0_5: # %sw.bb2
+; MIPS64R6-NEXT:  .LBB0_4: # %sw.bb2
 ; MIPS64R6-NEXT:    lui $1, %highest(.L.str.2)
 ; MIPS64R6-NEXT:    daddiu $1, $1, %higher(.L.str.2)
 ; MIPS64R6-NEXT:    dsll $1, $1, 16
@@ -301,7 +292,7 @@ define ptr @_Z3fooi(i32 signext %Letter) {
 ; MIPS64R6-NEXT:    daddiu $1, $1, %lo(.L.str.2)
 ; MIPS64R6-NEXT:    j .LBB0_10
 ; MIPS64R6-NEXT:    sd $1, 8($sp)
-; MIPS64R6-NEXT:  .LBB0_6: # %sw.bb3
+; MIPS64R6-NEXT:  .LBB0_5: # %sw.bb3
 ; MIPS64R6-NEXT:    lui $1, %highest(.L.str.3)
 ; MIPS64R6-NEXT:    daddiu $1, $1, %higher(.L.str.3)
 ; MIPS64R6-NEXT:    dsll $1, $1, 16
@@ -310,7 +301,7 @@ define ptr @_Z3fooi(i32 signext %Letter) {
 ; MIPS64R6-NEXT:    daddiu $1, $1, %lo(.L.str.3)
 ; MIPS64R6-NEXT:    j .LBB0_10
 ; MIPS64R6-NEXT:    sd $1, 8($sp)
-; MIPS64R6-NEXT:  .LBB0_7: # %sw.bb4
+; MIPS64R6-NEXT:  .LBB0_6: # %sw.bb4
 ; MIPS64R6-NEXT:    lui $1, %highest(.L.str.4)
 ; MIPS64R6-NEXT:    daddiu $1, $1, %higher(.L.str.4)
 ; MIPS64R6-NEXT:    dsll $1, $1, 16
@@ -319,7 +310,7 @@ define ptr @_Z3fooi(i32 signext %Letter) {
 ; MIPS64R6-NEXT:    daddiu $1, $1, %lo(.L.str.4)
 ; MIPS64R6-NEXT:    j .LBB0_10
 ; MIPS64R6-NEXT:    sd $1, 8($sp)
-; MIPS64R6-NEXT:  .LBB0_8: # %sw.bb5
+; MIPS64R6-NEXT:  .LBB0_7: # %sw.bb5
 ; MIPS64R6-NEXT:    lui $1, %highest(.L.str.5)
 ; MIPS64R6-NEXT:    daddiu $1, $1, %higher(.L.str.5)
 ; MIPS64R6-NEXT:    dsll $1, $1, 16
@@ -328,13 +319,22 @@ define ptr @_Z3fooi(i32 signext %Letter) {
 ; MIPS64R6-NEXT:    daddiu $1, $1, %lo(.L.str.5)
 ; MIPS64R6-NEXT:    j .LBB0_10
 ; MIPS64R6-NEXT:    sd $1, 8($sp)
-; MIPS64R6-NEXT:  .LBB0_9: # %sw.bb6
+; MIPS64R6-NEXT:  .LBB0_8: # %sw.bb6
 ; MIPS64R6-NEXT:    lui $1, %highest(.L.str.6)
 ; MIPS64R6-NEXT:    daddiu $1, $1, %higher(.L.str.6)
 ; MIPS64R6-NEXT:    dsll $1, $1, 16
 ; MIPS64R6-NEXT:    daddiu $1, $1, %hi(.L.str.6)
 ; MIPS64R6-NEXT:    dsll $1, $1, 16
 ; MIPS64R6-NEXT:    daddiu $1, $1, %lo(.L.str.6)
+; MIPS64R6-NEXT:    j .LBB0_10
+; MIPS64R6-NEXT:    sd $1, 8($sp)
+; MIPS64R6-NEXT:  .LBB0_9: # %sw.epilog
+; MIPS64R6-NEXT:    lui $1, %highest(.L.str.7)
+; MIPS64R6-NEXT:    daddiu $1, $1, %higher(.L.str.7)
+; MIPS64R6-NEXT:    dsll $1, $1, 16
+; MIPS64R6-NEXT:    daddiu $1, $1, %hi(.L.str.7)
+; MIPS64R6-NEXT:    dsll $1, $1, 16
+; MIPS64R6-NEXT:    daddiu $1, $1, %lo(.L.str.7)
 ; MIPS64R6-NEXT:    sd $1, 8($sp)
 ; MIPS64R6-NEXT:  .LBB0_10: # %return
 ; MIPS64R6-NEXT:    ld $2, 8($sp)
@@ -349,7 +349,7 @@ define ptr @_Z3fooi(i32 signext %Letter) {
 ; PIC-MIPS32R2-NEXT:    .cfi_def_cfa_offset 16
 ; PIC-MIPS32R2-NEXT:    addu $2, $2, $25
 ; PIC-MIPS32R2-NEXT:    sltiu $1, $4, 7
-; PIC-MIPS32R2-NEXT:    beqz $1, $BB0_3
+; PIC-MIPS32R2-NEXT:    beqz $1, $BB0_9
 ; PIC-MIPS32R2-NEXT:    sw $4, 4($sp)
 ; PIC-MIPS32R2-NEXT:  $BB0_1: # %entry
 ; PIC-MIPS32R2-NEXT:    sll $1, $4, 2
@@ -364,39 +364,39 @@ define ptr @_Z3fooi(i32 signext %Letter) {
 ; PIC-MIPS32R2-NEXT:    addiu $1, $1, %lo($.str)
 ; PIC-MIPS32R2-NEXT:    b $BB0_10
 ; PIC-MIPS32R2-NEXT:    sw $1, 8($sp)
-; PIC-MIPS32R2-NEXT:  $BB0_3: # %sw.epilog
-; PIC-MIPS32R2-NEXT:    lw $1, %got($.str.7)($2)
-; PIC-MIPS32R2-NEXT:    addiu $1, $1, %lo($.str.7)
-; PIC-MIPS32R2-NEXT:    b $BB0_10
-; PIC-MIPS32R2-NEXT:    sw $1, 8($sp)
-; PIC-MIPS32R2-NEXT:  $BB0_4: # %sw.bb1
+; PIC-MIPS32R2-NEXT:  $BB0_3: # %sw.bb1
 ; PIC-MIPS32R2-NEXT:    lw $1, %got($.str.1)($2)
 ; PIC-MIPS32R2-NEXT:    addiu $1, $1, %lo($.str.1)
 ; PIC-MIPS32R2-NEXT:    b $BB0_10
 ; PIC-MIPS32R2-NEXT:    sw $1, 8($sp)
-; PIC-MIPS32R2-NEXT:  $BB0_5: # %sw.bb2
+; PIC-MIPS32R2-NEXT:  $BB0_4: # %sw.bb2
 ; PIC-MIPS32R2-NEXT:    lw $1, %got($.str.2)($2)
 ; PIC-MIPS32R2-NEXT:    addiu $1, $1, %lo($.str.2)
 ; PIC-MIPS32R2-NEXT:    b $BB0_10
 ; PIC-MIPS32R2-NEXT:    sw $1, 8($sp)
-; PIC-MIPS32R2-NEXT:  $BB0_6: # %sw.bb3
+; PIC-MIPS32R2-NEXT:  $BB0_5: # %sw.bb3
 ; PIC-MIPS32R2-NEXT:    lw $1, %got($.str.3)($2)
 ; PIC-MIPS32R2-NEXT:    addiu $1, $1, %lo($.str.3)
 ; PIC-MIPS32R2-NEXT:    b $BB0_10
 ; PIC-MIPS32R2-NEXT:    sw $1, 8($sp)
-; PIC-MIPS32R2-NEXT:  $BB0_7: # %sw.bb4
+; PIC-MIPS32R2-NEXT:  $BB0_6: # %sw.bb4
 ; PIC-MIPS32R2-NEXT:    lw $1, %got($.str.4)($2)
 ; PIC-MIPS32R2-NEXT:    addiu $1, $1, %lo($.str.4)
 ; PIC-MIPS32R2-NEXT:    b $BB0_10
 ; PIC-MIPS32R2-NEXT:    sw $1, 8($sp)
-; PIC-MIPS32R2-NEXT:  $BB0_8: # %sw.bb5
+; PIC-MIPS32R2-NEXT:  $BB0_7: # %sw.bb5
 ; PIC-MIPS32R2-NEXT:    lw $1, %got($.str.5)($2)
 ; PIC-MIPS32R2-NEXT:    addiu $1, $1, %lo($.str.5)
 ; PIC-MIPS32R2-NEXT:    b $BB0_10
 ; PIC-MIPS32R2-NEXT:    sw $1, 8($sp)
-; PIC-MIPS32R2-NEXT:  $BB0_9: # %sw.bb6
+; PIC-MIPS32R2-NEXT:  $BB0_8: # %sw.bb6
 ; PIC-MIPS32R2-NEXT:    lw $1, %got($.str.6)($2)
 ; PIC-MIPS32R2-NEXT:    addiu $1, $1, %lo($.str.6)
+; PIC-MIPS32R2-NEXT:    b $BB0_10
+; PIC-MIPS32R2-NEXT:    sw $1, 8($sp)
+; PIC-MIPS32R2-NEXT:  $BB0_9: # %sw.epilog
+; PIC-MIPS32R2-NEXT:    lw $1, %got($.str.7)($2)
+; PIC-MIPS32R2-NEXT:    addiu $1, $1, %lo($.str.7)
 ; PIC-MIPS32R2-NEXT:    sw $1, 8($sp)
 ; PIC-MIPS32R2-NEXT:  $BB0_10: # %return
 ; PIC-MIPS32R2-NEXT:    lw $2, 8($sp)
@@ -411,7 +411,7 @@ define ptr @_Z3fooi(i32 signext %Letter) {
 ; PIC-MIPS32R6-NEXT:    .cfi_def_cfa_offset 16
 ; PIC-MIPS32R6-NEXT:    addu $2, $2, $25
 ; PIC-MIPS32R6-NEXT:    sltiu $1, $4, 7
-; PIC-MIPS32R6-NEXT:    beqz $1, $BB0_3
+; PIC-MIPS32R6-NEXT:    beqz $1, $BB0_9
 ; PIC-MIPS32R6-NEXT:    sw $4, 4($sp)
 ; PIC-MIPS32R6-NEXT:  $BB0_1: # %entry
 ; PIC-MIPS32R6-NEXT:    sll $1, $4, 2
@@ -426,39 +426,39 @@ define ptr @_Z3fooi(i32 signext %Letter) {
 ; PIC-MIPS32R6-NEXT:    addiu $1, $1, %lo($.str)
 ; PIC-MIPS32R6-NEXT:    b $BB0_10
 ; PIC-MIPS32R6-NEXT:    sw $1, 8($sp)
-; PIC-MIPS32R6-NEXT:  $BB0_3: # %sw.epilog
-; PIC-MIPS32R6-NEXT:    lw $1, %got($.str.7)($2)
-; PIC-MIPS32R6-NEXT:    addiu $1, $1, %lo($.str.7)
-; PIC-MIPS32R6-NEXT:    b $BB0_10
-; PIC-MIPS32R6-NEXT:    sw $1, 8($sp)
-; PIC-MIPS32R6-NEXT:  $BB0_4: # %sw.bb1
+; PIC-MIPS32R6-NEXT:  $BB0_3: # %sw.bb1
 ; PIC-MIPS32R6-NEXT:    lw $1, %got($.str.1)($2)
 ; PIC-MIPS32R6-NEXT:    addiu $1, $1, %lo($.str.1)
 ; PIC-MIPS32R6-NEXT:    b $BB0_10
 ; PIC-MIPS32R6-NEXT:    sw $1, 8($sp)
-; PIC-MIPS32R6-NEXT:  $BB0_5: # %sw.bb2
+; PIC-MIPS32R6-NEXT:  $BB0_4: # %sw.bb2
 ; PIC-MIPS32R6-NEXT:    lw $1, %got($.str.2)($2)
 ; PIC-MIPS32R6-NEXT:    addiu $1, $1, %lo($.str.2)
 ; PIC-MIPS32R6-NEXT:    b $BB0_10
 ; PIC-MIPS32R6-NEXT:    sw $1, 8($sp)
-; PIC-MIPS32R6-NEXT:  $BB0_6: # %sw.bb3
+; PIC-MIPS32R6-NEXT:  $BB0_5: # %sw.bb3
 ; PIC-MIPS32R6-NEXT:    lw $1, %got($.str.3)($2)
 ; PIC-MIPS32R6-NEXT:    addiu $1, $1, %lo($.str.3)
 ; PIC-MIPS32R6-NEXT:    b $BB0_10
 ; PIC-MIPS32R6-NEXT:    sw $1, 8($sp)
-; PIC-MIPS32R6-NEXT:  $BB0_7: # %sw.bb4
+; PIC-MIPS32R6-NEXT:  $BB0_6: # %sw.bb4
 ; PIC-MIPS32R6-NEXT:    lw $1, %got($.str.4)($2)
 ; PIC-MIPS32R6-NEXT:    addiu $1, $1, %lo($.str.4)
 ; PIC-MIPS32R6-NEXT:    b $BB0_10
 ; PIC-MIPS32R6-NEXT:    sw $1, 8($sp)
-; PIC-MIPS32R6-NEXT:  $BB0_8: # %sw.bb5
+; PIC-MIPS32R6-NEXT:  $BB0_7: # %sw.bb5
 ; PIC-MIPS32R6-NEXT:    lw $1, %got($.str.5)($2)
 ; PIC-MIPS32R6-NEXT:    addiu $1, $1, %lo($.str.5)
 ; PIC-MIPS32R6-NEXT:    b $BB0_10
 ; PIC-MIPS32R6-NEXT:    sw $1, 8($sp)
-; PIC-MIPS32R6-NEXT:  $BB0_9: # %sw.bb6
+; PIC-MIPS32R6-NEXT:  $BB0_8: # %sw.bb6
 ; PIC-MIPS32R6-NEXT:    lw $1, %got($.str.6)($2)
 ; PIC-MIPS32R6-NEXT:    addiu $1, $1, %lo($.str.6)
+; PIC-MIPS32R6-NEXT:    b $BB0_10
+; PIC-MIPS32R6-NEXT:    sw $1, 8($sp)
+; PIC-MIPS32R6-NEXT:  $BB0_9: # %sw.epilog
+; PIC-MIPS32R6-NEXT:    lw $1, %got($.str.7)($2)
+; PIC-MIPS32R6-NEXT:    addiu $1, $1, %lo($.str.7)
 ; PIC-MIPS32R6-NEXT:    sw $1, 8($sp)
 ; PIC-MIPS32R6-NEXT:  $BB0_10: # %return
 ; PIC-MIPS32R6-NEXT:    lw $2, 8($sp)
@@ -474,7 +474,7 @@ define ptr @_Z3fooi(i32 signext %Letter) {
 ; PIC-MIPS64R2-NEXT:    daddiu $2, $1, %lo(%neg(%gp_rel(_Z3fooi)))
 ; PIC-MIPS64R2-NEXT:    dext $3, $4, 0, 32
 ; PIC-MIPS64R2-NEXT:    sltiu $1, $3, 7
-; PIC-MIPS64R2-NEXT:    beqz $1, .LBB0_3
+; PIC-MIPS64R2-NEXT:    beqz $1, .LBB0_9
 ; PIC-MIPS64R2-NEXT:    sw $4, 4($sp)
 ; PIC-MIPS64R2-NEXT:  .LBB0_1: # %entry
 ; PIC-MIPS64R2-NEXT:    dsll $1, $3, 3
@@ -489,39 +489,39 @@ define ptr @_Z3fooi(i32 signext %Letter) {
 ; PIC-MIPS64R2-NEXT:    daddiu $1, $1, %got_ofst(.L.str)
 ; PIC-MIPS64R2-NEXT:    b .LBB0_10
 ; PIC-MIPS64R2-NEXT:    sd $1, 8($sp)
-; PIC-MIPS64R2-NEXT:  .LBB0_3: # %sw.epilog
-; PIC-MIPS64R2-NEXT:    ld $1, %got_page(.L.str.7)($2)
-; PIC-MIPS64R2-NEXT:    daddiu $1, $1, %got_ofst(.L.str.7)
-; PIC-MIPS64R2-NEXT:    b .LBB0_10
-; PIC-MIPS64R2-NEXT:    sd $1, 8($sp)
-; PIC-MIPS64R2-NEXT:  .LBB0_4: # %sw.bb1
+; PIC-MIPS64R2-NEXT:  .LBB0_3: # %sw.bb1
 ; PIC-MIPS64R2-NEXT:    ld $1, %got_page(.L.str.1)($2)
 ; PIC-MIPS64R2-NEXT:    daddiu $1, $1, %got_ofst(.L.str.1)
 ; PIC-MIPS64R2-NEXT:    b .LBB0_10
 ; PIC-MIPS64R2-NEXT:    sd $1, 8($sp)
-; PIC-MIPS64R2-NEXT:  .LBB0_5: # %sw.bb2
+; PIC-MIPS64R2-NEXT:  .LBB0_4: # %sw.bb2
 ; PIC-MIPS64R2-NEXT:    ld $1, %got_page(.L.str.2)($2)
 ; PIC-MIPS64R2-NEXT:    daddiu $1, $1, %got_ofst(.L.str.2)
 ; PIC-MIPS64R2-NEXT:    b .LBB0_10
 ; PIC-MIPS64R2-NEXT:    sd $1, 8($sp)
-; PIC-MIPS64R2-NEXT:  .LBB0_6: # %sw.bb3
+; PIC-MIPS64R2-NEXT:  .LBB0_5: # %sw.bb3
 ; PIC-MIPS64R2-NEXT:    ld $1, %got_page(.L.str.3)($2)
 ; PIC-MIPS64R2-NEXT:    daddiu $1, $1, %got_ofst(.L.str.3)
 ; PIC-MIPS64R2-NEXT:    b .LBB0_10
 ; PIC-MIPS64R2-NEXT:    sd $1, 8($sp)
-; PIC-MIPS64R2-NEXT:  .LBB0_7: # %sw.bb4
+; PIC-MIPS64R2-NEXT:  .LBB0_6: # %sw.bb4
 ; PIC-MIPS64R2-NEXT:    ld $1, %got_page(.L.str.4)($2)
 ; PIC-MIPS64R2-NEXT:    daddiu $1, $1, %got_ofst(.L.str.4)
 ; PIC-MIPS64R2-NEXT:    b .LBB0_10
 ; PIC-MIPS64R2-NEXT:    sd $1, 8($sp)
-; PIC-MIPS64R2-NEXT:  .LBB0_8: # %sw.bb5
+; PIC-MIPS64R2-NEXT:  .LBB0_7: # %sw.bb5
 ; PIC-MIPS64R2-NEXT:    ld $1, %got_page(.L.str.5)($2)
 ; PIC-MIPS64R2-NEXT:    daddiu $1, $1, %got_ofst(.L.str.5)
 ; PIC-MIPS64R2-NEXT:    b .LBB0_10
 ; PIC-MIPS64R2-NEXT:    sd $1, 8($sp)
-; PIC-MIPS64R2-NEXT:  .LBB0_9: # %sw.bb6
+; PIC-MIPS64R2-NEXT:  .LBB0_8: # %sw.bb6
 ; PIC-MIPS64R2-NEXT:    ld $1, %got_page(.L.str.6)($2)
 ; PIC-MIPS64R2-NEXT:    daddiu $1, $1, %got_ofst(.L.str.6)
+; PIC-MIPS64R2-NEXT:    b .LBB0_10
+; PIC-MIPS64R2-NEXT:    sd $1, 8($sp)
+; PIC-MIPS64R2-NEXT:  .LBB0_9: # %sw.epilog
+; PIC-MIPS64R2-NEXT:    ld $1, %got_page(.L.str.7)($2)
+; PIC-MIPS64R2-NEXT:    daddiu $1, $1, %got_ofst(.L.str.7)
 ; PIC-MIPS64R2-NEXT:    sd $1, 8($sp)
 ; PIC-MIPS64R2-NEXT:  .LBB0_10: # %return
 ; PIC-MIPS64R2-NEXT:    ld $2, 8($sp)
@@ -537,7 +537,7 @@ define ptr @_Z3fooi(i32 signext %Letter) {
 ; PIC-MIPS64R6-NEXT:    daddiu $2, $1, %lo(%neg(%gp_rel(_Z3fooi)))
 ; PIC-MIPS64R6-NEXT:    dext $3, $4, 0, 32
 ; PIC-MIPS64R6-NEXT:    sltiu $1, $3, 7
-; PIC-MIPS64R6-NEXT:    beqz $1, .LBB0_3
+; PIC-MIPS64R6-NEXT:    beqz $1, .LBB0_9
 ; PIC-MIPS64R6-NEXT:    sw $4, 4($sp)
 ; PIC-MIPS64R6-NEXT:  .LBB0_1: # %entry
 ; PIC-MIPS64R6-NEXT:    dsll $1, $3, 3
@@ -552,39 +552,39 @@ define ptr @_Z3fooi(i32 signext %Letter) {
 ; PIC-MIPS64R6-NEXT:    daddiu $1, $1, %got_ofst(.L.str)
 ; PIC-MIPS64R6-NEXT:    b .LBB0_10
 ; PIC-MIPS64R6-NEXT:    sd $1, 8($sp)
-; PIC-MIPS64R6-NEXT:  .LBB0_3: # %sw.epilog
-; PIC-MIPS64R6-NEXT:    ld $1, %got_page(.L.str.7)($2)
-; PIC-MIPS64R6-NEXT:    daddiu $1, $1, %got_ofst(.L.str.7)
-; PIC-MIPS64R6-NEXT:    b .LBB0_10
-; PIC-MIPS64R6-NEXT:    sd $1, 8($sp)
-; PIC-MIPS64R6-NEXT:  .LBB0_4: # %sw.bb1
+; PIC-MIPS64R6-NEXT:  .LBB0_3: # %sw.bb1
 ; PIC-MIPS64R6-NEXT:    ld $1, %got_page(.L.str.1)($2)
 ; PIC-MIPS64R6-NEXT:    daddiu $1, $1, %got_ofst(.L.str.1)
 ; PIC-MIPS64R6-NEXT:    b .LBB0_10
 ; PIC-MIPS64R6-NEXT:    sd $1, 8($sp)
-; PIC-MIPS64R6-NEXT:  .LBB0_5: # %sw.bb2
+; PIC-MIPS64R6-NEXT:  .LBB0_4: # %sw.bb2
 ; PIC-MIPS64R6-NEXT:    ld $1, %got_page(.L.str.2)($2)
 ; PIC-MIPS64R6-NEXT:    daddiu $1, $1, %got_ofst(.L.str.2)
 ; PIC-MIPS64R6-NEXT:    b .LBB0_10
 ; PIC-MIPS64R6-NEXT:    sd $1, 8($sp)
-; PIC-MIPS64R6-NEXT:  .LBB0_6: # %sw.bb3
+; PIC-MIPS64R6-NEXT:  .LBB0_5: # %sw.bb3
 ; PIC-MIPS64R6-NEXT:    ld $1, %got_page(.L.str.3)($2)
 ; PIC-MIPS64R6-NEXT:    daddiu $1, $1, %got_ofst(.L.str.3)
 ; PIC-MIPS64R6-NEXT:    b .LBB0_10
 ; PIC-MIPS64R6-NEXT:    sd $1, 8($sp)
-; PIC-MIPS64R6-NEXT:  .LBB0_7: # %sw.bb4
+; PIC-MIPS64R6-NEXT:  .LBB0_6: # %sw.bb4
 ; PIC-MIPS64R6-NEXT:    ld $1, %got_page(.L.str.4)($2)
 ; PIC-MIPS64R6-NEXT:    daddiu $1, $1, %got_ofst(.L.str.4)
 ; PIC-MIPS64R6-NEXT:    b .LBB0_10
 ; PIC-MIPS64R6-NEXT:    sd $1, 8($sp)
-; PIC-MIPS64R6-NEXT:  .LBB0_8: # %sw.bb5
+; PIC-MIPS64R6-NEXT:  .LBB0_7: # %sw.bb5
 ; PIC-MIPS64R6-NEXT:    ld $1, %got_page(.L.str.5)($2)
 ; PIC-MIPS64R6-NEXT:    daddiu $1, $1, %got_ofst(.L.str.5)
 ; PIC-MIPS64R6-NEXT:    b .LBB0_10
 ; PIC-MIPS64R6-NEXT:    sd $1, 8($sp)
-; PIC-MIPS64R6-NEXT:  .LBB0_9: # %sw.bb6
+; PIC-MIPS64R6-NEXT:  .LBB0_8: # %sw.bb6
 ; PIC-MIPS64R6-NEXT:    ld $1, %got_page(.L.str.6)($2)
 ; PIC-MIPS64R6-NEXT:    daddiu $1, $1, %got_ofst(.L.str.6)
+; PIC-MIPS64R6-NEXT:    b .LBB0_10
+; PIC-MIPS64R6-NEXT:    sd $1, 8($sp)
+; PIC-MIPS64R6-NEXT:  .LBB0_9: # %sw.epilog
+; PIC-MIPS64R6-NEXT:    ld $1, %got_page(.L.str.7)($2)
+; PIC-MIPS64R6-NEXT:    daddiu $1, $1, %got_ofst(.L.str.7)
 ; PIC-MIPS64R6-NEXT:    sd $1, 8($sp)
 ; PIC-MIPS64R6-NEXT:  .LBB0_10: # %return
 ; PIC-MIPS64R6-NEXT:    ld $2, 8($sp)
diff --git a/llvm/test/CodeGen/Mips/jump-table-mul.ll b/llvm/test/CodeGen/Mips/jump-table-mul.ll
index ef7452cf253fe..22f41f53d154b 100644
--- a/llvm/test/CodeGen/Mips/jump-table-mul.ll
+++ b/llvm/test/CodeGen/Mips/jump-table-mul.ll
@@ -8,15 +8,11 @@ define i64 @test(i64 %arg) {
 ; CHECK-NEXT:    lui $1, %hi(%neg(%gp_rel(test)))
 ; CHECK-NEXT:    daddu $2, $1, $25
 ; CHECK-NEXT:    sltiu $1, $4, 11
-; CHECK-NEXT:    beqz $1, .LBB0_3
+; CHECK-NEXT:    beqz $1, .LBB0_4
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:  .LBB0_1: # %entry
 ; CHECK-NEXT:    daddiu $1, $2, %lo(%neg(%gp_rel(test)))
 ; CHECK-NEXT:    dsll $2, $4, 3
-; Previously this dsll was the following sequence:
-;	daddiu	$2, $zero, 8
-;	dmult	$4, $2
-;	mflo	$2
 ; CHECK-NEXT:    ld $3, %got_page(.LJTI0_0)($1)
 ; CHECK-NEXT:    daddu $2, $2, $3
 ; CHECK-NEXT:    ld $2, %got_ofst(.LJTI0_0)($2)
@@ -26,12 +22,16 @@ define i64 @test(i64 %arg) {
 ; CHECK-NEXT:  .LBB0_2: # %sw.bb
 ; CHECK-NEXT:    jr $ra
 ; CHECK-NEXT:    daddiu $2, $zero, 1
-; CHECK-NEXT:  .LBB0_3: # %default
-; CHECK-NEXT:    jr $ra
-; CHECK-NEXT:    daddiu $2, $zero, 1234
-; CHECK-NEXT:  .LBB0_4: # %sw.bb1
+; CHECK-NEXT:  .LBB0_3: # %sw.bb1
 ; CHECK-NEXT:    jr $ra
 ; CHECK-NEXT:    daddiu $2, $zero, 0
+; CHECK-NEXT:  .LBB0_4: # %default
+; CHECK-NEXT:    jr $ra
+; CHECK-NEXT:    daddiu $2, $zero, 1234
+; Previously this dsll was the following sequence:
+;	daddiu	$2, $zero, 8
+;	dmult	$4, $2
+;	mflo	$2
 entry:
   switch i64 %arg, label %default [
     i64 0, label %sw.bb
@@ -54,13 +54,13 @@ sw.bb1:
 ; CHECK-NEXT: 	.p2align	3
 ; CHECK-LABEL: .LJTI0_0:
 ; CHECK-NEXT: 	.gpdword	.LBB0_2
-; CHECK-NEXT: 	.gpdword	.LBB0_3
-; CHECK-NEXT: 	.gpdword	.LBB0_3
+; CHECK-NEXT: 	.gpdword	.LBB0_4
+; CHECK-NEXT: 	.gpdword	.LBB0_4
 ; CHECK-NEXT: 	.gpdword	.LBB0_2
-; CHECK-NEXT: 	.gpdword	.LBB0_3
+; CHECK-NEXT: 	.gpdword	.LBB0_4
 ; CHECK-NEXT: 	.gpdword	.LBB0_2
-; CHECK-NEXT: 	.gpdword	.LBB0_3
-; CHECK-NEXT: 	.gpdword	.LBB0_3
-; CHECK-NEXT: 	.gpdword	.LBB0_3
-; CHECK-NEXT: 	.gpdword	.LBB0_3
 ; CHECK-NEXT: 	.gpdword	.LBB0_4
+; CHECK-NEXT: 	.gpdword	.LBB0_4
+; CHECK-NEXT: 	.gpdword	.LBB0_4
+; CHECK-NEXT: 	.gpdword	.LBB0_4
+; CHECK-NEXT: 	.gpdword	.LBB0_3
diff --git a/llvm/test/CodeGen/Mips/nacl-align.ll b/llvm/test/CodeGen/Mips/nacl-align.ll
index bca6c93de2624..964ddfc963c4e 100644
--- a/llvm/test/CodeGen/Mips/nacl-align.ll
+++ b/llvm/test/CodeGen/Mips/nacl-align.ll
@@ -44,9 +44,6 @@ default:
 ; CHECK-NEXT:    ${{BB[0-9]+_[0-9]+}}:
 ; CHECK-NEXT:        jr      $ra
 ; CHECK-NEXT:        addiu   $2, $zero, 111
-; CHECK-NEXT:    ${{BB[0-9]+_[0-9]+}}:
-; CHECK-NEXT:        jr      $ra
-; CHECK-NEXT:        addiu   $2, $zero, 555
 ; CHECK-NEXT:        .p2align  4
 ; CHECK-NEXT:    ${{BB[0-9]+_[0-9]+}}:
 ; CHECK-NEXT:        jr      $ra
@@ -55,6 +52,13 @@ default:
 ; CHECK-NEXT:    ${{BB[0-9]+_[0-9]+}}:
 ; CHECK-NEXT:        jr      $ra
 ; CHECK-NEXT:        addiu   $2, $zero, 333
+; CHECK-NEXT:        .p2align  4
+; CHECK-NEXT:    ${{BB[0-9]+_[0-9]+}}:
+; CHECK-NEXT:        jr      $ra
+; CHECK-NEXT:        addiu   $2, $zero, 444
+; CHECK-NEXT:    ${{BB[0-9]+_[0-9]+}}:
+; CHECK-NEXT:        jr      $ra
+; CHECK-NEXT:        addiu   $2, $zero, 555
 
 }
 
diff --git a/llvm/test/CodeGen/Mips/pseudo-jump-fill.ll b/llvm/test/CodeGen/Mips/pseudo-jump-fill.ll
index 31f077d57a933..afb79e55f4f90 100644
--- a/llvm/test/CodeGen/Mips/pseudo-jump-fill.ll
+++ b/llvm/test/CodeGen/Mips/pseudo-jump-fill.ll
@@ -12,7 +12,7 @@ define i32 @test(i32 signext %x, i32 signext %c) {
 ; CHECK-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; CHECK-NEXT:    addiur2 $5, $5, -1
 ; CHECK-NEXT:    sltiu $1, $5, 4
-; CHECK-NEXT:    beqz $1, $BB0_3
+; CHECK-NEXT:    beqz $1, $BB0_6
 ; CHECK-NEXT:    addu $3, $2, $25
 ; CHECK-NEXT:  $BB0_1: # %entry
 ; CHECK-NEXT:    li16 $2, 0
@@ -26,17 +26,17 @@ define i32 @test(i32 signext %x, i32 signext %c) {
 ; CHECK-NEXT:  $BB0_2: # %sw.bb2
 ; CHECK-NEXT:    addiur2 $2, $4, 1
 ; CHECK-NEXT:    jrc $ra
-; CHECK-NEXT:  $BB0_3:
-; CHECK-NEXT:    move $2, $4
-; CHECK-NEXT:    jrc $ra
-; CHECK-NEXT:  $BB0_4: # %sw.bb3
+; CHECK-NEXT:  $BB0_3: # %sw.bb3
 ; CHECK-NEXT:    addius5 $4, 2
 ; CHECK-NEXT:    move $2, $4
 ; CHECK-NEXT:    jrc $ra
-; CHECK-NEXT:  $BB0_5: # %sw.bb5
+; CHECK-NEXT:  $BB0_4: # %sw.bb5
 ; CHECK-NEXT:    addius5 $4, 3
 ; CHECK-NEXT:    move $2, $4
-; CHECK-NEXT:  $BB0_6: # %for.cond.cleanup
+; CHECK-NEXT:  $BB0_5: # %for.cond.cleanup
+; CHECK-NEXT:    jrc $ra
+; CHECK-NEXT:  $BB0_6:
+; CHECK-NEXT:    move $2, $4
 ; CHECK-NEXT:    jrc $ra
 entry:
   switch i32 %c, label %sw.epilog [
diff --git a/llvm/test/CodeGen/PowerPC/jump-tables-collapse-rotate.ll b/llvm/test/CodeGen/PowerPC/jump-tables-collapse-rotate.ll
index ccc9adbc2bdd1..efb356b7ed817 100644
--- a/llvm/test/CodeGen/PowerPC/jump-tables-collapse-rotate.ll
+++ b/llvm/test/CodeGen/PowerPC/jump-tables-collapse-rotate.ll
@@ -11,7 +11,7 @@ define dso_local zeroext i32 @test(i32 signext %l) nounwind {
 ; CHECK-NEXT:    addi r3, r3, -1
 ; CHECK-NEXT:    std r0, 48(r1)
 ; CHECK-NEXT:    cmplwi r3, 5
-; CHECK-NEXT:    bgt cr0, .LBB0_3
+; CHECK-NEXT:    bgt cr0, .LBB0_9
 ; CHECK-NEXT:  # %bb.1: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    rldic r3, r3, 2, 30
@@ -24,42 +24,41 @@ define dso_local zeroext i32 @test(i32 signext %l) nounwind {
 ; CHECK-NEXT:    li r3, 2
 ; CHECK-NEXT:    bl test1
 ; CHECK-NEXT:    nop
-; CHECK-NEXT:    b .LBB0_10
-; CHECK-NEXT:  .LBB0_3: # %sw.default
-; CHECK-NEXT:    li r3, 1
-; CHECK-NEXT:    bl test1
-; CHECK-NEXT:    nop
-; CHECK-NEXT:    bl test3
-; CHECK-NEXT:    nop
-; CHECK-NEXT:    b .LBB0_10
-; CHECK-NEXT:  .LBB0_4: # %sw.bb3
+; CHECK-NEXT:    b .LBB0_11
+; CHECK-NEXT:  .LBB0_3: # %sw.bb3
 ; CHECK-NEXT:    li r3, 3
-; CHECK-NEXT:    b .LBB0_9
-; CHECK-NEXT:  .LBB0_5: # %sw.bb5
+; CHECK-NEXT:    b .LBB0_8
+; CHECK-NEXT:  .LBB0_4: # %sw.bb5
 ; CHECK-NEXT:    li r3, 4
 ; CHECK-NEXT:    bl test2
 ; CHECK-NEXT:    nop
-; CHECK-NEXT:    bl test3
-; CHECK-NEXT:    nop
 ; CHECK-NEXT:    b .LBB0_10
-; CHECK-NEXT:  .LBB0_6: # %sw.bb8
+; CHECK-NEXT:  .LBB0_5: # %sw.bb8
 ; CHECK-NEXT:    li r3, 5
 ; CHECK-NEXT:    bl test4
 ; CHECK-NEXT:    nop
-; CHECK-NEXT:    b .LBB0_10
-; CHECK-NEXT:  .LBB0_7: # %sw.bb10
+; CHECK-NEXT:    b .LBB0_11
+; CHECK-NEXT:  .LBB0_6: # %sw.bb10
 ; CHECK-NEXT:    li r3, 66
 ; CHECK-NEXT:    bl test4
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    bl test1
 ; CHECK-NEXT:    nop
-; CHECK-NEXT:    b .LBB0_10
-; CHECK-NEXT:  .LBB0_8: # %sw.bb13
+; CHECK-NEXT:    b .LBB0_11
+; CHECK-NEXT:  .LBB0_7: # %sw.bb13
 ; CHECK-NEXT:    li r3, 66
-; CHECK-NEXT:  .LBB0_9: # %return
+; CHECK-NEXT:  .LBB0_8: # %return
 ; CHECK-NEXT:    bl test2
 ; CHECK-NEXT:    nop
+; CHECK-NEXT:    b .LBB0_11
+; CHECK-NEXT:  .LBB0_9: # %sw.default
+; CHECK-NEXT:    li r3, 1
+; CHECK-NEXT:    bl test1
+; CHECK-NEXT:    nop
 ; CHECK-NEXT:  .LBB0_10: # %return
+; CHECK-NEXT:    bl test3
+; CHECK-NEXT:    nop
+; CHECK-NEXT:  .LBB0_11: # %return
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    addi r1, r1, 32
 ; CHECK-NEXT:    ld r0, 16(r1)
diff --git a/llvm/test/CodeGen/PowerPC/p10-spill-crgt.ll b/llvm/test/CodeGen/PowerPC/p10-spill-crgt.ll
index eeadb73b9db2c..e97e17fc64782 100644
--- a/llvm/test/CodeGen/PowerPC/p10-spill-crgt.ll
+++ b/llvm/test/CodeGen/PowerPC/p10-spill-crgt.ll
@@ -155,11 +155,11 @@ define dso_local fastcc void @P10_Spill_CR_GT() unnamed_addr {
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    b .LBB0_25
 ; CHECK-NEXT:    .p2align 4
-; CHECK-NEXT:  .LBB0_26: # %bb62
+; CHECK-NEXT:  .LBB0_26: # %bb56
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    b .LBB0_26
 ; CHECK-NEXT:    .p2align 4
-; CHECK-NEXT:  .LBB0_27: # %bb56
+; CHECK-NEXT:  .LBB0_27: # %bb62
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    b .LBB0_27
 ; CHECK-NEXT:    .p2align 4
@@ -348,11 +348,11 @@ define dso_local fastcc void @P10_Spill_CR_GT() unnamed_addr {
 ; CHECK-BE-NEXT:    #
 ; CHECK-BE-NEXT:    b .LBB0_25
 ; CHECK-BE-NEXT:    .p2align 4
-; CHECK-BE-NEXT:  .LBB0_26: # %bb62
+; CHECK-BE-NEXT:  .LBB0_26: # %bb56
 ; CHECK-BE-NEXT:    #
 ; CHECK-BE-NEXT:    b .LBB0_26
 ; CHECK-BE-NEXT:    .p2align 4
-; CHECK-BE-NEXT:  .LBB0_27: # %bb56
+; CHECK-BE-NEXT:  .LBB0_27: # %bb62
 ; CHECK-BE-NEXT:    #
 ; CHECK-BE-NEXT:    b .LBB0_27
 ; CHECK-BE-NEXT:    .p2align 4
diff --git a/llvm/test/CodeGen/PowerPC/p10-spill-crlt.ll b/llvm/test/CodeGen/PowerPC/p10-spill-crlt.ll
index 32f3342243904..4b032781c3764 100644
--- a/llvm/test/CodeGen/PowerPC/p10-spill-crlt.ll
+++ b/llvm/test/CodeGen/PowerPC/p10-spill-crlt.ll
@@ -59,10 +59,10 @@ define dso_local void @P10_Spill_CR_LT() local_unnamed_addr {
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    plwz r3, call_1@PCREL(0), 1
 ; CHECK-NEXT:    cmplwi r3, 0
-; CHECK-NEXT:    bne- cr0, .LBB0_10
+; CHECK-NEXT:    bne- cr0, .LBB0_9
 ; CHECK-NEXT:  # %bb.5: # %bb30
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    bc 12, 4*cr3+eq, .LBB0_9
+; CHECK-NEXT:    bc 12, 4*cr3+eq, .LBB0_11
 ; CHECK-NEXT:  # %bb.6: # %bb32
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    rlwinm r30, r30, 0, 24, 22
@@ -72,10 +72,10 @@ define dso_local void @P10_Spill_CR_LT() local_unnamed_addr {
 ; CHECK-NEXT:    beq+ cr2, .LBB0_3
 ; CHECK-NEXT:  # %bb.7: # %bb37
 ; CHECK-NEXT:  .LBB0_8: # %bb22
-; CHECK-NEXT:  .LBB0_9: # %bb35
-; CHECK-NEXT:  .LBB0_10: # %bb27
+; CHECK-NEXT:  .LBB0_9: # %bb27
 ; CHECK-NEXT:    bc 4, 4*cr3+lt, .LBB0_12
-; CHECK-NEXT:  # %bb.11: # %bb28
+; CHECK-NEXT:  # %bb.10: # %bb28
+; CHECK-NEXT:  .LBB0_11: # %bb35
 ; CHECK-NEXT:  .LBB0_12: # %bb29
 ; CHECK-NEXT:  .LBB0_13: # %bb3
 ; CHECK-NEXT:  .LBB0_14: # %bb2
@@ -120,10 +120,10 @@ define dso_local void @P10_Spill_CR_LT() local_unnamed_addr {
 ; CHECK-BE-NEXT:    #
 ; CHECK-BE-NEXT:    lwz r3, call_1@toc@l(r30)
 ; CHECK-BE-NEXT:    cmplwi r3, 0
-; CHECK-BE-NEXT:    bne- cr0, .LBB0_10
+; CHECK-BE-NEXT:    bne- cr0, .LBB0_9
 ; CHECK-BE-NEXT:  # %bb.5: # %bb30
 ; CHECK-BE-NEXT:    #
-; CHECK-BE-NEXT:    bc 12, 4*cr3+eq, .LBB0_9
+; CHECK-BE-NEXT:    bc 12, 4*cr3+eq, .LBB0_11
 ; CHECK-BE-NEXT:  # %bb.6: # %bb32
 ; CHECK-BE-NEXT:    #
 ; CHECK-BE-NEXT:    rlwinm r29, r29, 0, 24, 22
@@ -134,10 +134,10 @@ define dso_local void @P10_Spill_CR_LT() local_unnamed_addr {
 ; CHECK-BE-NEXT:    beq+ cr2, .LBB0_3
 ; CHECK-BE-NEXT:  # %bb.7: # %bb37
 ; CHECK-BE-NEXT:  .LBB0_8: # %bb22
-; CHECK-BE-NEXT:  .LBB0_9: # %bb35
-; CHECK-BE-NEXT:  .LBB0_10: # %bb27
+; CHECK-BE-NEXT:  .LBB0_9: # %bb27
 ; CHECK-BE-NEXT:    bc 4, 4*cr3+lt, .LBB0_12
-; CHECK-BE-NEXT:  # %bb.11: # %bb28
+; CHECK-BE-NEXT:  # %bb.10: # %bb28
+; CHECK-BE-NEXT:  .LBB0_11: # %bb35
 ; CHECK-BE-NEXT:  .LBB0_12: # %bb29
 ; CHECK-BE-NEXT:  .LBB0_13: # %bb3
 ; CHECK-BE-NEXT:  .LBB0_14: # %bb2
diff --git a/llvm/test/CodeGen/PowerPC/p10-spill-crun.ll b/llvm/test/CodeGen/PowerPC/p10-spill-crun.ll
index 4ca2dc5dbe04d..fd049280c9f39 100644
--- a/llvm/test/CodeGen/PowerPC/p10-spill-crun.ll
+++ b/llvm/test/CodeGen/PowerPC/p10-spill-crun.ll
@@ -82,7 +82,7 @@ define dso_local void @P10_Spill_CR_UN(ptr %arg, ptr %arg1, i32 %arg2) local_unn
 ; CHECK-NEXT:    lwz r28, 0(r3)
 ; CHECK-NEXT:    bc 12, 4*cr5+lt, .LBB0_5
 ; CHECK-NEXT:  # %bb.4: # %bb37
-; CHECK-NEXT:    bc 4, 4*cr5+lt, .LBB0_14
+; CHECK-NEXT:    bc 4, 4*cr5+lt, .LBB0_12
 ; CHECK-NEXT:  .LBB0_5: # %bb42
 ; CHECK-NEXT:    paddi r3, 0, global_1@PCREL, 1
 ; CHECK-NEXT:    li r4, 0
@@ -95,10 +95,10 @@ define dso_local void @P10_Spill_CR_UN(ptr %arg, ptr %arg1, i32 %arg2) local_unn
 ; CHECK-NEXT:    lxsihzx v2, 0, r3
 ; CHECK-NEXT:    vextsh2d v2, v2
 ; CHECK-NEXT:    xscvsxdsp f0, v2
-; CHECK-NEXT:    bc 12, 4*cr2+lt, .LBB0_12
+; CHECK-NEXT:    bc 12, 4*cr2+lt, .LBB0_13
 ; CHECK-NEXT:  # %bb.6: # %bb42
 ; CHECK-NEXT:    xxspltidp vs1, 1069547520
-; CHECK-NEXT:    b .LBB0_13
+; CHECK-NEXT:    b .LBB0_14
 ; CHECK-NEXT:  .LBB0_7: # %bb19
 ; CHECK-NEXT:    setnbc r3, 4*cr2+un
 ; CHECK-NEXT:    paddi r4, 0, global_4@PCREL, 1
@@ -134,15 +134,15 @@ define dso_local void @P10_Spill_CR_UN(ptr %arg, ptr %arg1, i32 %arg2) local_unn
 ; CHECK-NEXT:    rlwimi r3, r4, 21, 11, 11
 ; CHECK-NEXT:    mtocrf 32, r3
 ; CHECK-NEXT:    b .LBB0_16
-; CHECK-NEXT:  .LBB0_12:
+; CHECK-NEXT:  .LBB0_12: # %bb41
+; CHECK-NEXT:    # implicit-def: $r3
+; CHECK-NEXT:    b .LBB0_15
+; CHECK-NEXT:  .LBB0_13:
 ; CHECK-NEXT:    xxspltidp vs1, 1071644672
-; CHECK-NEXT:  .LBB0_13: # %bb42
+; CHECK-NEXT:  .LBB0_14: # %bb42
 ; CHECK-NEXT:    xsmulsp f0, f1, f0
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    b .LBB0_15
-; CHECK-NEXT:  .LBB0_14: # %bb41
-; CHECK-NEXT:    # implicit-def: $r3
 ; CHECK-NEXT:  .LBB0_15: # %bb50
 ; CHECK-NEXT:    li r4, 0
 ; CHECK-NEXT:    xxspltidp vs3, -1082130432
@@ -232,7 +232,7 @@ define dso_local void @P10_Spill_CR_UN(ptr %arg, ptr %arg1, i32 %arg2) local_unn
 ; CHECK-BE-NEXT:    addis r3, r2, global_1@toc@ha
 ; CHECK-BE-NEXT:    bc 12, 4*cr5+lt, .LBB0_5
 ; CHECK-BE-NEXT:  # %bb.4: # %bb37
-; CHECK-BE-NEXT:    bc 4, 4*cr5+lt, .LBB0_14
+; CHECK-BE-NEXT:    bc 4, 4*cr5+lt, .LBB0_12
 ; CHECK-BE-NEXT:  .LBB0_5: # %bb42
 ; CHECK-BE-NEXT:    addi r3, r3, global_1@toc@l
 ; CHECK-BE-NEXT:    li r4, 0
@@ -247,10 +247,10 @@ define dso_local void @P10_Spill_CR_UN(ptr %arg, ptr %arg1, i32 %arg2) local_unn
 ; CHECK-BE-NEXT:    lxsihzx v2, 0, r3
 ; CHECK-BE-NEXT:    vextsh2d v2, v2
 ; CHECK-BE-NEXT:    xscvsxdsp f0, v2
-; CHECK-BE-NEXT:    bc 12, 4*cr2+lt, .LBB0_12
+; CHECK-BE-NEXT:    bc 12, 4*cr2+lt, .LBB0_13
 ; CHECK-BE-NEXT:  # %bb.6: # %bb42
 ; CHECK-BE-NEXT:    xxspltidp vs1, 1069547520
-; CHECK-BE-NEXT:    b .LBB0_13
+; CHECK-BE-NEXT:    b .LBB0_14
 ; CHECK-BE-NEXT:  .LBB0_7: # %bb19
 ; CHECK-BE-NEXT:    setnbc r3, 4*cr2+un
 ; CHECK-BE-NEXT:    addis r4, r2, global_4@toc@ha
@@ -292,15 +292,15 @@ define dso_local void @P10_Spill_CR_UN(ptr %arg, ptr %arg1, i32 %arg2) local_unn
 ; CHECK-BE-NEXT:    rlwimi r3, r4, 21, 11, 11
 ; CHECK-BE-NEXT:    mtocrf 32, r3
 ; CHECK-BE-NEXT:    b .LBB0_16
-; CHECK-BE-NEXT:  .LBB0_12:
+; CHECK-BE-NEXT:  .LBB0_12: # %bb41
+; CHECK-BE-NEXT:    # implicit-def: $r3
+; CHECK-BE-NEXT:    b .LBB0_15
+; CHECK-BE-NEXT:  .LBB0_13:
 ; CHECK-BE-NEXT:    xxspltidp vs1, 1071644672
-; CHECK-BE-NEXT:  .LBB0_13: # %bb42
+; CHECK-BE-NEXT:  .LBB0_14: # %bb42
 ; CHECK-BE-NEXT:    xsmulsp f0, f1, f0
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    b .LBB0_15
-; CHECK-BE-NEXT:  .LBB0_14: # %bb41
-; CHECK-BE-NEXT:    # implicit-def: $r3
 ; CHECK-BE-NEXT:  .LBB0_15: # %bb50
 ; CHECK-BE-NEXT:    li r4, 0
 ; CHECK-BE-NEXT:    xxspltidp vs3, -1082130432
diff --git a/llvm/test/CodeGen/PowerPC/pr43527.ll b/llvm/test/CodeGen/PowerPC/pr43527.ll
index 379bd6c070c77..d7c70ab7f066c 100644
--- a/llvm/test/CodeGen/PowerPC/pr43527.ll
+++ b/llvm/test/CodeGen/PowerPC/pr43527.ll
@@ -5,9 +5,9 @@
 define dso_local void @test(i64 %arg, i64 %arg1) {
 ; CHECK-LABEL: test:
 ; CHECK:       # %bb.0: # %bb
-; CHECK-NEXT:    bc 4, 4*cr5+lt, .LBB0_5
+; CHECK-NEXT:    bc 4, 4*cr5+lt, .LBB0_6
 ; CHECK-NEXT:  # %bb.1: # %bb3
-; CHECK-NEXT:    bc 12, 4*cr5+lt, .LBB0_6
+; CHECK-NEXT:    bc 12, 4*cr5+lt, .LBB0_5
 ; CHECK-NEXT:  # %bb.2: # %bb4
 ; CHECK-NEXT:    mflr r0
 ; CHECK-NEXT:    .cfi_def_cfa_offset 64
@@ -37,8 +37,8 @@ define dso_local void @test(i64 %arg, i64 %arg1) {
 ; CHECK-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload
 ; CHECK-NEXT:    mtlr r0
 ; CHECK-NEXT:    blr
-; CHECK-NEXT:  .LBB0_5: # %bb2
-; CHECK-NEXT:  .LBB0_6: # %bb14
+; CHECK-NEXT:  .LBB0_5: # %bb14
+; CHECK-NEXT:  .LBB0_6: # %bb2
 bb:
   br i1 undef, label %bb3, label %bb2
 
diff --git a/llvm/test/CodeGen/PowerPC/pr45448.ll b/llvm/test/CodeGen/PowerPC/pr45448.ll
index 0f8014df8adca..6b3d578f6b338 100644
--- a/llvm/test/CodeGen/PowerPC/pr45448.ll
+++ b/llvm/test/CodeGen/PowerPC/pr45448.ll
@@ -7,17 +7,17 @@ define hidden void @julia_tryparse_internal_45896() #0 {
 ; CHECK:       # %bb.0: # %top
 ; CHECK-NEXT:    ld r3, 0(r3)
 ; CHECK-NEXT:    cmpldi r3, 0
-; CHECK-NEXT:    beq cr0, .LBB0_3
+; CHECK-NEXT:    beq cr0, .LBB0_6
 ; CHECK-NEXT:  # %bb.1: # %top
 ; CHECK-NEXT:    cmpldi r3, 10
-; CHECK-NEXT:    beq cr0, .LBB0_4
+; CHECK-NEXT:    beq cr0, .LBB0_3
 ; CHECK-NEXT:  # %bb.2: # %top
-; CHECK-NEXT:  .LBB0_3: # %fail194
-; CHECK-NEXT:  .LBB0_4: # %L294
-; CHECK-NEXT:    bc 12, 4*cr5+lt, .LBB0_6
-; CHECK-NEXT:  # %bb.5: # %L294
+; CHECK-NEXT:  .LBB0_3: # %L294
+; CHECK-NEXT:    bc 12, 4*cr5+lt, .LBB0_5
+; CHECK-NEXT:  # %bb.4: # %L294
 ; CHECK-NEXT:    bc 4, 4*cr5+lt, .LBB0_7
-; CHECK-NEXT:  .LBB0_6: # %L1057.preheader
+; CHECK-NEXT:  .LBB0_5: # %L1057.preheader
+; CHECK-NEXT:  .LBB0_6: # %fail194
 ; CHECK-NEXT:  .LBB0_7: # %L670
 ; CHECK-NEXT:    li r5, -3
 ; CHECK-NEXT:    cmpdi r3, 0
diff --git a/llvm/test/CodeGen/RISCV/shrinkwrap-jump-table.ll b/llvm/test/CodeGen/RISCV/shrinkwrap-jump-table.ll
index 99780c5e0d444..75af75ce75ed9 100644
--- a/llvm/test/CodeGen/RISCV/shrinkwrap-jump-table.ll
+++ b/llvm/test/CodeGen/RISCV/shrinkwrap-jump-table.ll
@@ -14,7 +14,7 @@ define dso_local signext i32 @test_shrinkwrap_jump_table(ptr noundef %m) local_u
 ; CHECK-NEXT:    lw a1, 0(a0)
 ; CHECK-NEXT:    addi a1, a1, -1
 ; CHECK-NEXT:    li a2, 4
-; CHECK-NEXT:    bltu a2, a1, .LBB0_3
+; CHECK-NEXT:    bltu a2, a1, .LBB0_7
 ; CHECK-NEXT:  # %bb.1: # %entry
 ; CHECK-NEXT:    slli a1, a1, 2
 ; CHECK-NEXT:    lui a2, %hi(.LJTI0_0)
@@ -24,7 +24,15 @@ define dso_local signext i32 @test_shrinkwrap_jump_table(ptr noundef %m) local_u
 ; CHECK-NEXT:    jr a1
 ; CHECK-NEXT:  .LBB0_2: # %sw.bb
 ; CHECK-NEXT:    tail func1@plt
-; CHECK-NEXT:  .LBB0_3: # %sw.default
+; CHECK-NEXT:  .LBB0_3: # %sw.bb1
+; CHECK-NEXT:    tail func2@plt
+; CHECK-NEXT:  .LBB0_4: # %sw.bb3
+; CHECK-NEXT:    tail func3@plt
+; CHECK-NEXT:  .LBB0_5: # %sw.bb5
+; CHECK-NEXT:    tail func4@plt
+; CHECK-NEXT:  .LBB0_6: # %sw.bb7
+; CHECK-NEXT:    tail func5@plt
+; CHECK-NEXT:  .LBB0_7: # %sw.default
 ; CHECK-NEXT:    addi sp, sp, -16
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
@@ -34,14 +42,6 @@ define dso_local signext i32 @test_shrinkwrap_jump_table(ptr noundef %m) local_u
 ; CHECK-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    addi sp, sp, 16
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB0_4: # %sw.bb1
-; CHECK-NEXT:    tail func2@plt
-; CHECK-NEXT:  .LBB0_5: # %sw.bb3
-; CHECK-NEXT:    tail func3@plt
-; CHECK-NEXT:  .LBB0_6: # %sw.bb5
-; CHECK-NEXT:    tail func4@plt
-; CHECK-NEXT:  .LBB0_7: # %sw.bb7
-; CHECK-NEXT:    tail func5@plt
 entry:
   %0 = load i32, ptr %m, align 4
   switch i32 %0, label %sw.default [
diff --git a/llvm/test/CodeGen/Thumb2/bti-indirect-branches.ll b/llvm/test/CodeGen/Thumb2/bti-indirect-branches.ll
index 59e346588754a..ed895be96cd89 100644
--- a/llvm/test/CodeGen/Thumb2/bti-indirect-branches.ll
+++ b/llvm/test/CodeGen/Thumb2/bti-indirect-branches.ll
@@ -7,30 +7,30 @@ define internal i32 @table_switch(i32 %x) {
 ; CHECK-NEXT:    bti
 ; CHECK-NEXT:    subs r1, r0, #1
 ; CHECK-NEXT:    cmp r1, #3
-; CHECK-NEXT:    bhi .LBB0_4
+; CHECK-NEXT:    bhi .LBB0_6
 ; CHECK-NEXT:  @ %bb.1: @ %entry
 ; CHECK-NEXT:  .LCPI0_0:
 ; CHECK-NEXT:    tbb [pc, r1]
 ; CHECK-NEXT:  @ %bb.2:
 ; CHECK-NEXT:  .LJTI0_0:
-; CHECK-NEXT:    .byte (.LBB0_5-(.LCPI0_0+4))/2
-; CHECK-NEXT:    .byte (.LBB0_3-(.LCPI0_0+4))/2
-; CHECK-NEXT:    .byte (.LBB0_6-(.LCPI0_0+4))/2
 ; CHECK-NEXT:    .byte (.LBB0_7-(.LCPI0_0+4))/2
+; CHECK-NEXT:    .byte (.LBB0_3-(.LCPI0_0+4))/2
+; CHECK-NEXT:    .byte (.LBB0_4-(.LCPI0_0+4))/2
+; CHECK-NEXT:    .byte (.LBB0_5-(.LCPI0_0+4))/2
 ; CHECK-NEXT:    .p2align 1
 ; CHECK-NEXT:  .LBB0_3: @ %bb2
 ; CHECK-NEXT:    movs r0, #2
 ; CHECK-NEXT:    bx lr
-; CHECK-NEXT:  .LBB0_4: @ %sw.epilog
-; CHECK-NEXT:    movs r0, #0
-; CHECK-NEXT:  .LBB0_5: @ %return
-; CHECK-NEXT:    bx lr
-; CHECK-NEXT:  .LBB0_6: @ %bb3
+; CHECK-NEXT:  .LBB0_4: @ %bb3
 ; CHECK-NEXT:    movs r0, #3
 ; CHECK-NEXT:    bx lr
-; CHECK-NEXT:  .LBB0_7: @ %bb4
+; CHECK-NEXT:  .LBB0_5: @ %bb4
 ; CHECK-NEXT:    movs r0, #4
 ; CHECK-NEXT:    bx lr
+; CHECK-NEXT:  .LBB0_6: @ %sw.epilog
+; CHECK-NEXT:    movs r0, #0
+; CHECK-NEXT:  .LBB0_7: @ %return
+; CHECK-NEXT:    bx lr
 entry:
   switch i32 %x, label %sw.epilog [
     i32 1, label %bb1
@@ -93,23 +93,6 @@ declare void @consume_exception(ptr)
 declare i32 @__gxx_personality_v0(...)
 
 define internal i32 @exception_handling(i32 %0) personality ptr @__gxx_personality_v0 {
-; CHECK-LABEL: exception_handling:
-; CHECK:       @ %bb.0:
-; CHECK-NEXT:    bti
-; CHECK-NEXT:    .save  {r7, lr}
-; CHECK-NEXT:    push   {r7, lr}
-; CHECK-NEXT:  .Ltmp0:
-; CHECK-NEXT:    bl     may_throw
-; CHECK-NEXT:  .Ltmp1:
-; CHECK-NEXT:  @ %bb.1:
-; CHECK-NEXT:    movs   r0, #0
-; CHECK-NEXT:    pop    {r7, pc}
-; CHECK-NEXT:  .LBB2_2:
-; CHECK-NEXT:  .Ltmp2:
-; CHECK-NEXT:    bti
-; CHECK-NEXT:    bl     consume_exception
-; CHECK-NEXT:    movs   r0, #1
-; CHECK-NEXT:    pop    {r7, pc}
 entry:
   invoke void @may_throw()
           to label %return unwind label %lpad
diff --git a/llvm/test/CodeGen/Thumb2/constant-hoisting.ll b/llvm/test/CodeGen/Thumb2/constant-hoisting.ll
index 98fe30039259f..1aeecdf1e08f3 100644
--- a/llvm/test/CodeGen/Thumb2/constant-hoisting.ll
+++ b/llvm/test/CodeGen/Thumb2/constant-hoisting.ll
@@ -7,27 +7,27 @@ define i32 @test_values(i32 %a, i32 %b) minsize optsize {
 ; CHECK-V6M:         mov r2, r0
 ; CHECK-V6M-NEXT:    ldr r0, .LCPI0_0
 ; CHECK-V6M-NEXT:    cmp r2, #50
-; CHECK-V6M-NEXT:    beq .LBB0_5
-; CHECK-V6M-NEXT:    cmp r2, #1
 ; CHECK-V6M-NEXT:    beq .LBB0_7
+; CHECK-V6M-NEXT:    cmp r2, #1
+; CHECK-V6M-NEXT:    beq .LBB0_5
 ; CHECK-V6M-NEXT:    cmp r2, #30
-; CHECK-V6M-NEXT:    beq .LBB0_8
+; CHECK-V6M-NEXT:    beq .LBB0_6
 ; CHECK-V6M-NEXT:    cmp r2, #0
-; CHECK-V6M-NEXT:    bne .LBB0_6
+; CHECK-V6M-NEXT:    bne .LBB0_8
 ; CHECK-V6M-NEXT:    adds r0, r1, r0
 ; CHECK-V6M-NEXT:    bx lr
 ; CHECK-V6M-NEXT:  .LBB0_5:
 ; CHECK-V6M-NEXT:    adds r0, r0, r1
-; CHECK-V6M-NEXT:    adds r0, r0, #4
+; CHECK-V6M-NEXT:    adds r0, r0, #1
+; CHECK-V6M-NEXT:    bx lr
 ; CHECK-V6M-NEXT:  .LBB0_6:
+; CHECK-V6M-NEXT:    adds r0, r0, r1
+; CHECK-V6M-NEXT:    adds r0, r0, #2
 ; CHECK-V6M-NEXT:    bx lr
 ; CHECK-V6M-NEXT:  .LBB0_7:
 ; CHECK-V6M-NEXT:    adds r0, r0, r1
-; CHECK-V6M-NEXT:    adds r0, r0, #1
-; CHECK-V6M-NEXT:    bx lr
+; CHECK-V6M-NEXT:    adds r0, r0, #4
 ; CHECK-V6M-NEXT:  .LBB0_8:
-; CHECK-V6M-NEXT:    adds r0, r0, r1
-; CHECK-V6M-NEXT:    adds r0, r0, #2
 ; CHECK-V6M-NEXT:    bx lr
 ; CHECK-V6M-NEXT:    .p2align 2
 ; CHECK-V6M-NEXT:  .LCPI0_0:
diff --git a/llvm/test/CodeGen/VE/Scalar/br_jt.ll b/llvm/test/CodeGen/VE/Scalar/br_jt.ll
index bc7b26abe7e04..fd44a54a72738 100644
--- a/llvm/test/CodeGen/VE/Scalar/br_jt.ll
+++ b/llvm/test/CodeGen/VE/Scalar/br_jt.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
 ; RUN: llc < %s -mtriple=ve | FileCheck %s
 ; RUN: llc < %s -mtriple=ve -relocation-model=pic \
 ; RUN:     | FileCheck %s -check-prefix=PIC
@@ -11,22 +12,22 @@ define signext i32 @br_jt3(i32 signext %0) {
 ; CHECK-LABEL: br_jt3:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    and %s0, %s0, (32)0
-; CHECK-NEXT:    breq.w 1, %s0, .LBB{{[0-9]+}}_1
+; CHECK-NEXT:    breq.w 1, %s0, .LBB0_1
 ; CHECK-NEXT:  # %bb.2:
-; CHECK-NEXT:    breq.w 4, %s0, .LBB{{[0-9]+}}_5
+; CHECK-NEXT:    breq.w 4, %s0, .LBB0_5
 ; CHECK-NEXT:  # %bb.3:
-; CHECK-NEXT:    brne.w 2, %s0, .LBB{{[0-9]+}}_6
+; CHECK-NEXT:    brne.w 2, %s0, .LBB0_6
 ; CHECK-NEXT:  # %bb.4:
 ; CHECK-NEXT:    or %s0, 0, (0)1
 ; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    b.l.t (, %s10)
-; CHECK-NEXT:  .LBB{{[0-9]+}}_1:
-; CHECK-NEXT:    or %s0, 3, (0)1
+; CHECK-NEXT:  .LBB0_5:
+; CHECK-NEXT:    or %s0, 7, (0)1
+; CHECK-NEXT:  .LBB0_6:
 ; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    b.l.t (, %s10)
-; CHECK-NEXT:  .LBB{{[0-9]+}}_5:
-; CHECK-NEXT:    or %s0, 7, (0)1
-; CHECK-NEXT:  .LBB{{[0-9]+}}_6:
+; CHECK-NEXT:  .LBB0_1:
+; CHECK-NEXT:    or %s0, 3, (0)1
 ; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    b.l.t (, %s10)
 ;
@@ -42,14 +43,14 @@ define signext i32 @br_jt3(i32 signext %0) {
 ; PIC-NEXT:    or %s0, 0, (0)1
 ; PIC-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; PIC-NEXT:    b.l.t (, %s10)
-; PIC-NEXT:  .LBB0_1:
-; PIC-NEXT:    or %s0, 3, (0)1
-; PIC-NEXT:    adds.w.sx %s0, %s0, (0)1
-; PIC-NEXT:    b.l.t (, %s10)
 ; PIC-NEXT:  .LBB0_5:
 ; PIC-NEXT:    or %s0, 7, (0)1
 ; PIC-NEXT:  .LBB0_6:
 ; PIC-NEXT:    adds.w.sx %s0, %s0, (0)1
+; PIC-NEXT:    b.l.t (, %s10)
+; PIC-NEXT:  .LBB0_1:
+; PIC-NEXT:    or %s0, 3, (0)1
+; PIC-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; PIC-NEXT:    b.l.t (, %s10)
   switch i32 %0, label %4 [
     i32 1, label %5
@@ -78,7 +79,7 @@ define signext i32 @br_jt4(i32 signext %0) {
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    adds.w.sx %s1, -1, %s0
 ; CHECK-NEXT:    cmpu.w %s2, 3, %s1
-; CHECK-NEXT:    brgt.w 0, %s2, .LBB{{[0-9]+}}_2
+; CHECK-NEXT:    brgt.w 0, %s2, .LBB1_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    adds.w.sx %s0, %s1, (0)1
 ; CHECK-NEXT:    sll %s0, %s0, 2
@@ -87,7 +88,7 @@ define signext i32 @br_jt4(i32 signext %0) {
 ; CHECK-NEXT:    lea.sl %s1, .Lswitch.table.br_jt4@hi(, %s1)
 ; CHECK-NEXT:    ldl.sx %s0, (%s0, %s1)
 ; CHECK-NEXT:    b.l.t (, %s10)
-; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:  .LBB1_2:
 ; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    b.l.t (, %s10)
 ;
@@ -138,18 +139,18 @@ define signext i32 @br_jt7(i32 signext %0) {
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    adds.w.sx %s1, -1, %s0
 ; CHECK-NEXT:    cmpu.w %s2, 8, %s1
-; CHECK-NEXT:    brgt.w 0, %s2, .LBB{{[0-9]+}}_3
+; CHECK-NEXT:    brgt.w 0, %s2, .LBB2_3
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    and %s2, %s1, (48)0
 ; CHECK-NEXT:    lea %s3, 463
 ; CHECK-NEXT:    and %s3, %s3, (32)0
 ; CHECK-NEXT:    srl %s2, %s3, %s2
 ; CHECK-NEXT:    and %s2, 1, %s2
-; CHECK-NEXT:    brne.w 0, %s2, .LBB{{[0-9]+}}_2
-; CHECK-NEXT:  .LBB{{[0-9]+}}_3:
+; CHECK-NEXT:    brne.w 0, %s2, .LBB2_2
+; CHECK-NEXT:  .LBB2_3:
 ; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    b.l.t (, %s10)
-; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:  .LBB2_2:
 ; CHECK-NEXT:    adds.w.sx %s0, %s1, (0)1
 ; CHECK-NEXT:    sll %s0, %s0, 2
 ; CHECK-NEXT:    lea %s1, .Lswitch.table.br_jt7@lo
@@ -219,18 +220,18 @@ define signext i32 @br_jt8(i32 signext %0) {
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    adds.w.sx %s1, -1, %s0
 ; CHECK-NEXT:    cmpu.w %s2, 8, %s1
-; CHECK-NEXT:    brgt.w 0, %s2, .LBB{{[0-9]+}}_3
+; CHECK-NEXT:    brgt.w 0, %s2, .LBB3_3
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    and %s2, %s1, (48)0
 ; CHECK-NEXT:    lea %s3, 495
 ; CHECK-NEXT:    and %s3, %s3, (32)0
 ; CHECK-NEXT:    srl %s2, %s3, %s2
 ; CHECK-NEXT:    and %s2, 1, %s2
-; CHECK-NEXT:    brne.w 0, %s2, .LBB{{[0-9]+}}_2
-; CHECK-NEXT:  .LBB{{[0-9]+}}_3:
+; CHECK-NEXT:    brne.w 0, %s2, .LBB3_2
+; CHECK-NEXT:  .LBB3_3:
 ; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    b.l.t (, %s10)
-; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:  .LBB3_2:
 ; CHECK-NEXT:    adds.w.sx %s0, %s1, (0)1
 ; CHECK-NEXT:    sll %s0, %s0, 2
 ; CHECK-NEXT:    lea %s1, .Lswitch.table.br_jt8@lo
@@ -298,23 +299,23 @@ define signext i32 @br_jt3_m(i32 signext %0, i32 signext %1) {
 ; CHECK-LABEL: br_jt3_m:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    and %s0, %s0, (32)0
-; CHECK-NEXT:    breq.w 1, %s0, .LBB{{[0-9]+}}_1
+; CHECK-NEXT:    breq.w 1, %s0, .LBB4_1
 ; CHECK-NEXT:  # %bb.2:
-; CHECK-NEXT:    breq.w 4, %s0, .LBB{{[0-9]+}}_5
+; CHECK-NEXT:    breq.w 4, %s0, .LBB4_5
 ; CHECK-NEXT:  # %bb.3:
-; CHECK-NEXT:    brne.w 2, %s0, .LBB{{[0-9]+}}_6
+; CHECK-NEXT:    brne.w 2, %s0, .LBB4_6
 ; CHECK-NEXT:  # %bb.4:
 ; CHECK-NEXT:    or %s0, 0, (0)1
 ; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    b.l.t (, %s10)
-; CHECK-NEXT:  .LBB{{[0-9]+}}_1:
-; CHECK-NEXT:    or %s0, 3, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT:    b.l.t (, %s10)
-; CHECK-NEXT:  .LBB{{[0-9]+}}_5:
+; CHECK-NEXT:  .LBB4_5:
 ; CHECK-NEXT:    and %s0, %s1, (32)0
 ; CHECK-NEXT:    adds.w.sx %s0, 3, %s0
-; CHECK-NEXT:  .LBB{{[0-9]+}}_6:
+; CHECK-NEXT:  .LBB4_6:
+; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT:    b.l.t (, %s10)
+; CHECK-NEXT:  .LBB4_1:
+; CHECK-NEXT:    or %s0, 3, (0)1
 ; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    b.l.t (, %s10)
 ;
@@ -330,15 +331,15 @@ define signext i32 @br_jt3_m(i32 signext %0, i32 signext %1) {
 ; PIC-NEXT:    or %s0, 0, (0)1
 ; PIC-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; PIC-NEXT:    b.l.t (, %s10)
-; PIC-NEXT:  .LBB4_1:
-; PIC-NEXT:    or %s0, 3, (0)1
-; PIC-NEXT:    adds.w.sx %s0, %s0, (0)1
-; PIC-NEXT:    b.l.t (, %s10)
 ; PIC-NEXT:  .LBB4_5:
 ; PIC-NEXT:    and %s0, %s1, (32)0
 ; PIC-NEXT:    adds.w.sx %s0, 3, %s0
 ; PIC-NEXT:  .LBB4_6:
 ; PIC-NEXT:    adds.w.sx %s0, %s0, (0)1
+; PIC-NEXT:    b.l.t (, %s10)
+; PIC-NEXT:  .LBB4_1:
+; PIC-NEXT:    or %s0, 3, (0)1
+; PIC-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; PIC-NEXT:    b.l.t (, %s10)
   switch i32 %0, label %6 [
     i32 1, label %7
@@ -368,7 +369,7 @@ define signext i32 @br_jt4_m(i32 signext %0, i32 signext %1) {
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    adds.w.sx %s2, -1, %s0
 ; CHECK-NEXT:    cmpu.w %s3, 3, %s2
-; CHECK-NEXT:    brgt.w 0, %s3, .LBB{{[0-9]+}}_5
+; CHECK-NEXT:    brgt.w 0, %s3, .LBB5_5
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    adds.w.zx %s0, %s2, (0)1
 ; CHECK-NEXT:    sll %s0, %s0, 3
@@ -378,18 +379,18 @@ define signext i32 @br_jt4_m(i32 signext %0, i32 signext %1) {
 ; CHECK-NEXT:    ld %s2, (%s2, %s0)
 ; CHECK-NEXT:    or %s0, 3, (0)1
 ; CHECK-NEXT:    b.l.t (, %s2)
-; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:  .LBB5_2:
 ; CHECK-NEXT:    or %s0, 0, (0)1
 ; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    b.l.t (, %s10)
-; CHECK-NEXT:  .LBB{{[0-9]+}}_3:
+; CHECK-NEXT:  .LBB5_3:
 ; CHECK-NEXT:    or %s0, 4, (0)1
 ; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    b.l.t (, %s10)
-; CHECK-NEXT:  .LBB{{[0-9]+}}_4:
+; CHECK-NEXT:  .LBB5_4:
 ; CHECK-NEXT:    and %s0, %s1, (32)0
 ; CHECK-NEXT:    adds.w.sx %s0, 3, %s0
-; CHECK-NEXT:  .LBB{{[0-9]+}}_5:
+; CHECK-NEXT:  .LBB5_5:
 ; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    b.l.t (, %s10)
 ;
@@ -455,7 +456,7 @@ define signext i32 @br_jt7_m(i32 signext %0, i32 signext %1) {
 ; CHECK-NEXT:    and %s2, %s0, (32)0
 ; CHECK-NEXT:    adds.w.sx %s0, -1, %s2
 ; CHECK-NEXT:    cmpu.w %s3, 8, %s0
-; CHECK-NEXT:    brgt.w 0, %s3, .LBB{{[0-9]+}}_8
+; CHECK-NEXT:    brgt.w 0, %s3, .LBB6_8
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
 ; CHECK-NEXT:    sll %s0, %s0, 3
@@ -466,32 +467,32 @@ define signext i32 @br_jt7_m(i32 signext %0, i32 signext %1) {
 ; CHECK-NEXT:    and %s1, %s1, (32)0
 ; CHECK-NEXT:    or %s0, 3, (0)1
 ; CHECK-NEXT:    b.l.t (, %s3)
-; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:  .LBB6_2:
 ; CHECK-NEXT:    or %s0, 0, (0)1
 ; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    b.l.t (, %s10)
-; CHECK-NEXT:  .LBB{{[0-9]+}}_3:
+; CHECK-NEXT:  .LBB6_3:
 ; CHECK-NEXT:    or %s0, 4, (0)1
 ; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    b.l.t (, %s10)
-; CHECK-NEXT:  .LBB{{[0-9]+}}_4:
+; CHECK-NEXT:  .LBB6_4:
 ; CHECK-NEXT:    adds.w.sx %s0, 3, %s1
 ; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    b.l.t (, %s10)
-; CHECK-NEXT:  .LBB{{[0-9]+}}_8:
+; CHECK-NEXT:  .LBB6_8:
 ; CHECK-NEXT:    or %s0, 0, %s2
-; CHECK-NEXT:  .LBB{{[0-9]+}}_9:
+; CHECK-NEXT:  .LBB6_9:
 ; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    b.l.t (, %s10)
-; CHECK-NEXT:  .LBB{{[0-9]+}}_7:
+; CHECK-NEXT:  .LBB6_7:
 ; CHECK-NEXT:    or %s0, 11, (0)1
 ; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    b.l.t (, %s10)
-; CHECK-NEXT:  .LBB{{[0-9]+}}_6:
+; CHECK-NEXT:  .LBB6_6:
 ; CHECK-NEXT:    or %s0, 10, (0)1
 ; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    b.l.t (, %s10)
-; CHECK-NEXT:  .LBB{{[0-9]+}}_5:
+; CHECK-NEXT:  .LBB6_5:
 ; CHECK-NEXT:    adds.w.sx %s0, -2, %s1
 ; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    b.l.t (, %s10)
@@ -533,15 +534,15 @@ define signext i32 @br_jt7_m(i32 signext %0, i32 signext %1) {
 ; PIC-NEXT:    adds.w.sx %s0, 3, %s1
 ; PIC-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; PIC-NEXT:    b.l.t (, %s10)
-; PIC-NEXT:  .LBB6_2:
-; PIC-NEXT:    or %s0, 3, (0)1
-; PIC-NEXT:    adds.w.sx %s0, %s0, (0)1
-; PIC-NEXT:    b.l.t (, %s10)
 ; PIC-NEXT:  .LBB6_15:
 ; PIC-NEXT:    or %s0, 11, (0)1
 ; PIC-NEXT:  .LBB6_16:
 ; PIC-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; PIC-NEXT:    b.l.t (, %s10)
+; PIC-NEXT:  .LBB6_2:
+; PIC-NEXT:    or %s0, 3, (0)1
+; PIC-NEXT:    adds.w.sx %s0, %s0, (0)1
+; PIC-NEXT:    b.l.t (, %s10)
 ; PIC-NEXT:  .LBB6_13:
 ; PIC-NEXT:    or %s0, 0, (0)1
 ; PIC-NEXT:    adds.w.sx %s0, %s0, (0)1
@@ -591,7 +592,7 @@ define signext i32 @br_jt8_m(i32 signext %0, i32 signext %1) {
 ; CHECK-NEXT:    and %s2, %s0, (32)0
 ; CHECK-NEXT:    adds.w.sx %s0, -1, %s2
 ; CHECK-NEXT:    cmpu.w %s3, 8, %s0
-; CHECK-NEXT:    brgt.w 0, %s3, .LBB{{[0-9]+}}_9
+; CHECK-NEXT:    brgt.w 0, %s3, .LBB7_9
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
 ; CHECK-NEXT:    sll %s0, %s0, 3
@@ -602,37 +603,37 @@ define signext i32 @br_jt8_m(i32 signext %0, i32 signext %1) {
 ; CHECK-NEXT:    and %s1, %s1, (32)0
 ; CHECK-NEXT:    or %s0, 3, (0)1
 ; CHECK-NEXT:    b.l.t (, %s3)
-; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:  .LBB7_2:
 ; CHECK-NEXT:    or %s0, 0, (0)1
 ; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    b.l.t (, %s10)
-; CHECK-NEXT:  .LBB{{[0-9]+}}_3:
+; CHECK-NEXT:  .LBB7_3:
 ; CHECK-NEXT:    or %s0, 4, (0)1
 ; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    b.l.t (, %s10)
-; CHECK-NEXT:  .LBB{{[0-9]+}}_4:
+; CHECK-NEXT:  .LBB7_4:
 ; CHECK-NEXT:    adds.w.sx %s0, 3, %s1
 ; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    b.l.t (, %s10)
-; CHECK-NEXT:  .LBB{{[0-9]+}}_9:
-; CHECK-NEXT:    or %s0, 0, %s2
-; CHECK-NEXT:  .LBB{{[0-9]+}}_10:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT:    b.l.t (, %s10)
-; CHECK-NEXT:  .LBB{{[0-9]+}}_5:
+; CHECK-NEXT:  .LBB7_5:
 ; CHECK-NEXT:    adds.w.sx %s0, -5, %s1
 ; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    b.l.t (, %s10)
-; CHECK-NEXT:  .LBB{{[0-9]+}}_6:
+; CHECK-NEXT:  .LBB7_6:
 ; CHECK-NEXT:    adds.w.sx %s0, -2, %s1
 ; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    b.l.t (, %s10)
-; CHECK-NEXT:  .LBB{{[0-9]+}}_8:
+; CHECK-NEXT:  .LBB7_7:
+; CHECK-NEXT:    or %s0, 10, (0)1
+; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT:    b.l.t (, %s10)
+; CHECK-NEXT:  .LBB7_8:
 ; CHECK-NEXT:    or %s0, 11, (0)1
 ; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    b.l.t (, %s10)
-; CHECK-NEXT:  .LBB{{[0-9]+}}_7:
-; CHECK-NEXT:    or %s0, 10, (0)1
+; CHECK-NEXT:  .LBB7_9:
+; CHECK-NEXT:    or %s0, 0, %s2
+; CHECK-NEXT:  .LBB7_10:
 ; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    b.l.t (, %s10)
 ;
@@ -671,20 +672,20 @@ define signext i32 @br_jt8_m(i32 signext %0, i32 signext %1) {
 ; PIC-NEXT:  .LBB7_4:
 ; PIC-NEXT:    adds.w.sx %s0, 3, %s1
 ; PIC-NEXT:    br.l.t .LBB7_10
-; PIC-NEXT:  .LBB7_9:
-; PIC-NEXT:    or %s0, 0, %s2
-; PIC-NEXT:    br.l.t .LBB7_10
 ; PIC-NEXT:  .LBB7_5:
 ; PIC-NEXT:    adds.w.sx %s0, -5, %s1
 ; PIC-NEXT:    br.l.t .LBB7_10
 ; PIC-NEXT:  .LBB7_6:
 ; PIC-NEXT:    adds.w.sx %s0, -2, %s1
 ; PIC-NEXT:    br.l.t .LBB7_10
+; PIC-NEXT:  .LBB7_7:
+; PIC-NEXT:    or %s0, 10, (0)1
+; PIC-NEXT:    br.l.t .LBB7_10
 ; PIC-NEXT:  .LBB7_8:
 ; PIC-NEXT:    or %s0, 11, (0)1
 ; PIC-NEXT:    br.l.t .LBB7_10
-; PIC-NEXT:  .LBB7_7:
-; PIC-NEXT:    or %s0, 10, (0)1
+; PIC-NEXT:  .LBB7_9:
+; PIC-NEXT:    or %s0, 0, %s2
 ; PIC-NEXT:  .LBB7_10:
 ; PIC-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; PIC-NEXT:    ld %s16, 32(, %s11)
diff --git a/llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll b/llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll
index 6d596195fe7f6..332a4596eb337 100644
--- a/llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll
+++ b/llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
 ; RUN: llc < %s -mtriple=i386-apple-darwin | FileCheck %s
 ; Make sure xorl operands are 32-bit registers.
 
@@ -136,15 +137,6 @@ define void @_ZNK10wxDateTime6FormatEPKwRKNS_8TimeZoneE(ptr noalias sret(%struct
 ; CHECK-NEXT:    calll __ZN12wxStringBase10ConcatSelfEmPKwm
 ; CHECK-NEXT:  Ltmp11:
 ; CHECK-NEXT:    jmp LBB0_5
-; CHECK-NEXT:  LBB0_9: ## %bb5657
-; CHECK-NEXT:  Ltmp13:
-; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT:    movl %eax, {{[0-9]+}}(%esp)
-; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT:    movl %eax, (%esp)
-; CHECK-NEXT:    calll __ZNK10wxDateTime12GetDayOfYearERKNS_8TimeZoneE
-; CHECK-NEXT:  Ltmp14:
-; CHECK-NEXT:    jmp LBB0_25
 ; CHECK-NEXT:  LBB0_20: ## %bb5968
 ; CHECK-NEXT:  Ltmp2:
 ; CHECK-NEXT:    movl $0, {{[0-9]+}}(%esp)
@@ -153,6 +145,15 @@ define void @_ZNK10wxDateTime6FormatEPKwRKNS_8TimeZoneE(ptr noalias sret(%struct
 ; CHECK-NEXT:    calll __ZN8wxString6FormatEPKwz
 ; CHECK-NEXT:    subl $4, %esp
 ; CHECK-NEXT:  Ltmp3:
+; CHECK-NEXT:    jmp LBB0_25
+; CHECK-NEXT:  LBB0_9: ## %bb5657
+; CHECK-NEXT:  Ltmp13:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    movl %eax, {{[0-9]+}}(%esp)
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    movl %eax, (%esp)
+; CHECK-NEXT:    calll __ZNK10wxDateTime12GetDayOfYearERKNS_8TimeZoneE
+; CHECK-NEXT:  Ltmp14:
 ; CHECK-NEXT:  LBB0_25: ## %bb115.critedge.i
 ; CHECK-NEXT:    movl %esi, %eax
 ; CHECK-NEXT:    addl $28, %esp
diff --git a/llvm/test/CodeGen/X86/2009-08-12-badswitch.ll b/llvm/test/CodeGen/X86/2009-08-12-badswitch.ll
index 214da14322d51..5ad218f6cdc89 100644
--- a/llvm/test/CodeGen/X86/2009-08-12-badswitch.ll
+++ b/llvm/test/CodeGen/X86/2009-08-12-badswitch.ll
@@ -45,9 +45,6 @@ define internal fastcc i32 @foo(i64 %bar) nounwind ssp {
 ; CHECK-NEXT:  LBB0_3: ## %RRETURN_6
 ; CHECK-NEXT:    callq _f2
 ; CHECK-NEXT:    jmp LBB0_28
-; CHECK-NEXT:  LBB0_2: ## %RETURN
-; CHECK-NEXT:    callq _f1
-; CHECK-NEXT:    jmp LBB0_28
 ; CHECK-NEXT:  LBB0_4: ## %RRETURN_7
 ; CHECK-NEXT:    callq _f3
 ; CHECK-NEXT:    jmp LBB0_28
@@ -119,6 +116,9 @@ define internal fastcc i32 @foo(i64 %bar) nounwind ssp {
 ; CHECK-NEXT:    jmp LBB0_28
 ; CHECK-NEXT:  LBB0_27: ## %RRETURN_1
 ; CHECK-NEXT:    callq _f26
+; CHECK-NEXT:    jmp LBB0_28
+; CHECK-NEXT:  LBB0_2: ## %RETURN
+; CHECK-NEXT:    callq _f1
 ; CHECK-NEXT:  LBB0_28: ## %EXIT
 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    popq %rcx
diff --git a/llvm/test/CodeGen/X86/block-placement.ll b/llvm/test/CodeGen/X86/block-placement.ll
index a522f0e9828a0..5cdabc0a79b0d 100644
--- a/llvm/test/CodeGen/X86/block-placement.ll
+++ b/llvm/test/CodeGen/X86/block-placement.ll
@@ -1149,8 +1149,8 @@ define void @test_flow_unwind() personality i32 (...)* @pers {
 ; CHECK: %entry
 ; CHECK: %then
 ; CHECK: %exit
-; CHECK: %innerlp
 ; CHECK: %outerlp
+; CHECK: %innerlp
 ; CHECK: %outercleanup
 entry:
   %0 = invoke i32 @foo()
diff --git a/llvm/test/CodeGen/X86/callbr-asm-outputs.ll b/llvm/test/CodeGen/X86/callbr-asm-outputs.ll
index f5f0333983101..880f85cc7f17b 100644
--- a/llvm/test/CodeGen/X86/callbr-asm-outputs.ll
+++ b/llvm/test/CodeGen/X86/callbr-asm-outputs.ll
@@ -50,12 +50,12 @@ define i32 @test2(i32 %out1, i32 %out2) nounwind {
 ; CHECK-NEXT:  .LBB1_2: # Block address taken
 ; CHECK-NEXT:    # %if.then.label_true_crit_edge
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    jmp .LBB1_8
+; CHECK-NEXT:    jmp .LBB1_9
 ; CHECK-NEXT:  .LBB1_3: # %if.else
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    testl %esi, %edi
 ; CHECK-NEXT:    testl %esi, %edi
-; CHECK-NEXT:    jne .LBB1_9
+; CHECK-NEXT:    jne .LBB1_6
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:  .LBB1_4:
 ; CHECK-NEXT:    movl %esi, %eax
@@ -64,20 +64,20 @@ define i32 @test2(i32 %out1, i32 %out2) nounwind {
 ; CHECK-NEXT:    popl %esi
 ; CHECK-NEXT:    popl %edi
 ; CHECK-NEXT:    retl
-; CHECK-NEXT:  .LBB1_7: # Block address taken
-; CHECK-NEXT:    # %if.else.label_true_crit_edge
-; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:  .LBB1_8: # %label_true
-; CHECK-NEXT:    movl $-2, %eax
-; CHECK-NEXT:    jmp .LBB1_5
-; CHECK-NEXT:  .LBB1_9: # Block address taken
+; CHECK-NEXT:  .LBB1_6: # Block address taken
 ; CHECK-NEXT:    # %if.else.return_crit_edge
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:  .LBB1_6: # Block address taken
+; CHECK-NEXT:  .LBB1_7: # Block address taken
 ; CHECK-NEXT:    # %if.then.return_crit_edge
 ; CHECK-NEXT:    # Label of block must be emitted
 ; CHECK-NEXT:    movl $-1, %eax
 ; CHECK-NEXT:    jmp .LBB1_5
+; CHECK-NEXT:  .LBB1_8: # Block address taken
+; CHECK-NEXT:    # %if.else.label_true_crit_edge
+; CHECK-NEXT:    # Label of block must be emitted
+; CHECK-NEXT:  .LBB1_9: # %label_true
+; CHECK-NEXT:    movl $-2, %eax
+; CHECK-NEXT:    jmp .LBB1_5
 entry:
   %cmp = icmp slt i32 %out1, %out2
   br i1 %cmp, label %if.then, label %if.else
diff --git a/llvm/test/CodeGen/X86/dup-cost.ll b/llvm/test/CodeGen/X86/dup-cost.ll
index 523f0f1154e94..93af487c64ca0 100644
--- a/llvm/test/CodeGen/X86/dup-cost.ll
+++ b/llvm/test/CodeGen/X86/dup-cost.ll
@@ -1,14 +1,28 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
 
 ; Cold function, %dup should not be duplicated into predecessors.
 define i32 @cold(i32 %a, ptr %p, ptr %q) !prof !21 {
-; CHECK-LABEL: cold
-; CHECK:       %entry
-; CHECK:       %true1
-; CHECK:       %dup
-; CHECK:       %true2
-; CHECK:       %false1
-; CHECK:       %false2
+; CHECK-LABEL: cold:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cmpl $2, %edi
+; CHECK-NEXT:    jl .LBB0_2
+; CHECK-NEXT:  # %bb.1: # %true1
+; CHECK-NEXT:    movl (%rsi), %eax
+; CHECK-NEXT:    addl $2, %eax
+; CHECK-NEXT:  .LBB0_3: # %dup
+; CHECK-NEXT:    cmpl $5, %eax
+; CHECK-NEXT:    jl .LBB0_5
+; CHECK-NEXT:  # %bb.4: # %true2
+; CHECK-NEXT:    xorl %edi, %eax
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  .LBB0_5: # %false2
+; CHECK-NEXT:    andl %edi, %eax
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  .LBB0_2: # %false1
+; CHECK-NEXT:    movl (%rdx), %eax
+; CHECK-NEXT:    addl $-3, %eax
+; CHECK-NEXT:    jmp .LBB0_3
 entry:
   %cond1 = icmp sgt i32 %a, 1
   br i1 %cond1, label %true1, label %false1, !prof !30
@@ -44,12 +58,26 @@ exit:
 ; Same code as previous function, but with hot profile count.
 ; So %dup should be duplicated into predecessors.
 define i32 @hot(i32 %a, ptr %p, ptr %q) !prof !22 {
-; CHECK-LABEL: hot
-; CHECK:       %entry
-; CHECK:       %true1
-; CHECK:       %false2
-; CHECK:       %false1
-; CHECK:       %true2
+; CHECK-LABEL: hot:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cmpl $2, %edi
+; CHECK-NEXT:    jl .LBB1_2
+; CHECK-NEXT:  # %bb.1: # %true1
+; CHECK-NEXT:    movl (%rsi), %eax
+; CHECK-NEXT:    addl $2, %eax
+; CHECK-NEXT:    cmpl $5, %eax
+; CHECK-NEXT:    jge .LBB1_4
+; CHECK-NEXT:  .LBB1_5: # %false2
+; CHECK-NEXT:    andl %edi, %eax
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  .LBB1_2: # %false1
+; CHECK-NEXT:    movl (%rdx), %eax
+; CHECK-NEXT:    addl $-3, %eax
+; CHECK-NEXT:    cmpl $5, %eax
+; CHECK-NEXT:    jl .LBB1_5
+; CHECK-NEXT:  .LBB1_4: # %true2
+; CHECK-NEXT:    xorl %edi, %eax
+; CHECK-NEXT:    retq
 entry:
   %cond1 = icmp sgt i32 %a, 1
   br i1 %cond1, label %true1, label %false1, !prof !30
diff --git a/llvm/test/CodeGen/X86/mul-constant-result.ll b/llvm/test/CodeGen/X86/mul-constant-result.ll
index beb2dba05e85a..9b74ef08a8f54 100644
--- a/llvm/test/CodeGen/X86/mul-constant-result.ll
+++ b/llvm/test/CodeGen/X86/mul-constant-result.ll
@@ -28,7 +28,7 @@ define i32 @mult(i32, i32) local_unnamed_addr #0 {
 ; X86-NEXT:  .LBB0_4:
 ; X86-NEXT:    decl %ecx
 ; X86-NEXT:    cmpl $31, %ecx
-; X86-NEXT:    ja .LBB0_7
+; X86-NEXT:    ja .LBB0_12
 ; X86-NEXT:  # %bb.5:
 ; X86-NEXT:    jmpl *.LJTI0_0(,%ecx,4)
 ; X86-NEXT:  .LBB0_6:
@@ -36,27 +36,27 @@ define i32 @mult(i32, i32) local_unnamed_addr #0 {
 ; X86-NEXT:    popl %esi
 ; X86-NEXT:    .cfi_def_cfa_offset 4
 ; X86-NEXT:    retl
-; X86-NEXT:  .LBB0_7:
-; X86-NEXT:    .cfi_def_cfa_offset 8
-; X86-NEXT:    xorl %eax, %eax
 ; X86-NEXT:  .LBB0_8:
-; X86-NEXT:    popl %esi
-; X86-NEXT:    .cfi_def_cfa_offset 4
-; X86-NEXT:    retl
-; X86-NEXT:  .LBB0_10:
 ; X86-NEXT:    .cfi_def_cfa_offset 8
 ; X86-NEXT:    shll $2, %eax
 ; X86-NEXT:    popl %esi
 ; X86-NEXT:    .cfi_def_cfa_offset 4
 ; X86-NEXT:    retl
-; X86-NEXT:  .LBB0_12:
+; X86-NEXT:  .LBB0_10:
 ; X86-NEXT:    .cfi_def_cfa_offset 8
 ; X86-NEXT:    addl %eax, %eax
-; X86-NEXT:    jmp .LBB0_9
-; X86-NEXT:  .LBB0_13:
+; X86-NEXT:    jmp .LBB0_7
+; X86-NEXT:  .LBB0_11:
 ; X86-NEXT:    leal (,%eax,8), %ecx
 ; X86-NEXT:    jmp .LBB0_42
+; X86-NEXT:  .LBB0_12:
+; X86-NEXT:    xorl %eax, %eax
+; X86-NEXT:  .LBB0_13:
+; X86-NEXT:    popl %esi
+; X86-NEXT:    .cfi_def_cfa_offset 4
+; X86-NEXT:    retl
 ; X86-NEXT:  .LBB0_14:
+; X86-NEXT:    .cfi_def_cfa_offset 8
 ; X86-NEXT:    shll $3, %eax
 ; X86-NEXT:    popl %esi
 ; X86-NEXT:    .cfi_def_cfa_offset 4
@@ -64,13 +64,13 @@ define i32 @mult(i32, i32) local_unnamed_addr #0 {
 ; X86-NEXT:  .LBB0_16:
 ; X86-NEXT:    .cfi_def_cfa_offset 8
 ; X86-NEXT:    addl %eax, %eax
-; X86-NEXT:    jmp .LBB0_11
+; X86-NEXT:    jmp .LBB0_9
 ; X86-NEXT:  .LBB0_17:
 ; X86-NEXT:    leal (%eax,%eax,4), %ecx
 ; X86-NEXT:    jmp .LBB0_18
 ; X86-NEXT:  .LBB0_19:
 ; X86-NEXT:    shll $2, %eax
-; X86-NEXT:    jmp .LBB0_9
+; X86-NEXT:    jmp .LBB0_7
 ; X86-NEXT:  .LBB0_20:
 ; X86-NEXT:    leal (%eax,%eax,2), %ecx
 ; X86-NEXT:    jmp .LBB0_21
@@ -80,7 +80,7 @@ define i32 @mult(i32, i32) local_unnamed_addr #0 {
 ; X86-NEXT:    jmp .LBB0_23
 ; X86-NEXT:  .LBB0_24:
 ; X86-NEXT:    leal (%eax,%eax,4), %eax
-; X86-NEXT:    jmp .LBB0_9
+; X86-NEXT:    jmp .LBB0_7
 ; X86-NEXT:  .LBB0_25:
 ; X86-NEXT:    shll $4, %eax
 ; X86-NEXT:    popl %esi
@@ -109,7 +109,7 @@ define i32 @mult(i32, i32) local_unnamed_addr #0 {
 ; X86-NEXT:  .LBB0_30:
 ; X86-NEXT:    .cfi_def_cfa_offset 8
 ; X86-NEXT:    shll $2, %eax
-; X86-NEXT:    jmp .LBB0_11
+; X86-NEXT:    jmp .LBB0_9
 ; X86-NEXT:  .LBB0_31:
 ; X86-NEXT:    leal (%eax,%eax,4), %ecx
 ; X86-NEXT:  .LBB0_21:
@@ -128,10 +128,10 @@ define i32 @mult(i32, i32) local_unnamed_addr #0 {
 ; X86-NEXT:    jmp .LBB0_42
 ; X86-NEXT:  .LBB0_34:
 ; X86-NEXT:    shll $3, %eax
-; X86-NEXT:    jmp .LBB0_9
+; X86-NEXT:    jmp .LBB0_7
 ; X86-NEXT:  .LBB0_35:
 ; X86-NEXT:    leal (%eax,%eax,4), %eax
-; X86-NEXT:  .LBB0_11:
+; X86-NEXT:  .LBB0_9:
 ; X86-NEXT:    leal (%eax,%eax,4), %eax
 ; X86-NEXT:    popl %esi
 ; X86-NEXT:    .cfi_def_cfa_offset 4
@@ -143,7 +143,7 @@ define i32 @mult(i32, i32) local_unnamed_addr #0 {
 ; X86-NEXT:    jmp .LBB0_27
 ; X86-NEXT:  .LBB0_37:
 ; X86-NEXT:    leal (%eax,%eax,8), %eax
-; X86-NEXT:  .LBB0_9:
+; X86-NEXT:  .LBB0_7:
 ; X86-NEXT:    leal (%eax,%eax,2), %eax
 ; X86-NEXT:    popl %esi
 ; X86-NEXT:    .cfi_def_cfa_offset 4
@@ -199,41 +199,54 @@ define i32 @mult(i32, i32) local_unnamed_addr #0 {
 ; X64-HSW-NEXT:    cmovel %ecx, %eax
 ; X64-HSW-NEXT:    decl %edi
 ; X64-HSW-NEXT:    cmpl $31, %edi
-; X64-HSW-NEXT:    ja .LBB0_3
+; X64-HSW-NEXT:    ja .LBB0_8
 ; X64-HSW-NEXT:  # %bb.1:
 ; X64-HSW-NEXT:    jmpq *.LJTI0_0(,%rdi,8)
 ; X64-HSW-NEXT:  .LBB0_2:
 ; X64-HSW-NEXT:    addl %eax, %eax
 ; X64-HSW-NEXT:    # kill: def $eax killed $eax killed $rax
 ; X64-HSW-NEXT:    retq
-; X64-HSW-NEXT:  .LBB0_3:
-; X64-HSW-NEXT:    xorl %eax, %eax
 ; X64-HSW-NEXT:  .LBB0_4:
-; X64-HSW-NEXT:    # kill: def $eax killed $eax killed $rax
-; X64-HSW-NEXT:    retq
-; X64-HSW-NEXT:  .LBB0_6:
 ; X64-HSW-NEXT:    shll $2, %eax
 ; X64-HSW-NEXT:    # kill: def $eax killed $eax killed $rax
 ; X64-HSW-NEXT:    retq
-; X64-HSW-NEXT:  .LBB0_8:
+; X64-HSW-NEXT:  .LBB0_6:
 ; X64-HSW-NEXT:    addl %eax, %eax
-; X64-HSW-NEXT:  .LBB0_5:
+; X64-HSW-NEXT:  .LBB0_3:
 ; X64-HSW-NEXT:    leal (%rax,%rax,2), %eax
 ; X64-HSW-NEXT:    # kill: def $eax killed $eax killed $rax
 ; X64-HSW-NEXT:    retq
+; X64-HSW-NEXT:  .LBB0_33:
+; X64-HSW-NEXT:    leal (%rax,%rax,8), %ecx
+; X64-HSW-NEXT:    leal (%rcx,%rcx,2), %ecx
+; X64-HSW-NEXT:    jmp .LBB0_34
+; X64-HSW-NEXT:  .LBB0_8:
+; X64-HSW-NEXT:    xorl %eax, %eax
 ; X64-HSW-NEXT:  .LBB0_9:
-; X64-HSW-NEXT:    leal (,%rax,8), %ecx
-; X64-HSW-NEXT:    jmp .LBB0_38
+; X64-HSW-NEXT:    # kill: def $eax killed $eax killed $rax
+; X64-HSW-NEXT:    retq
 ; X64-HSW-NEXT:  .LBB0_10:
 ; X64-HSW-NEXT:    shll $3, %eax
 ; X64-HSW-NEXT:    # kill: def $eax killed $eax killed $rax
 ; X64-HSW-NEXT:    retq
 ; X64-HSW-NEXT:  .LBB0_12:
 ; X64-HSW-NEXT:    addl %eax, %eax
-; X64-HSW-NEXT:  .LBB0_7:
+; X64-HSW-NEXT:  .LBB0_5:
 ; X64-HSW-NEXT:    leal (%rax,%rax,4), %eax
 ; X64-HSW-NEXT:    # kill: def $eax killed $eax killed $rax
 ; X64-HSW-NEXT:    retq
+; X64-HSW-NEXT:  .LBB0_31:
+; X64-HSW-NEXT:    leal (%rax,%rax,4), %ecx
+; X64-HSW-NEXT:    leal (%rcx,%rcx,4), %ecx
+; X64-HSW-NEXT:    jmp .LBB0_34
+; X64-HSW-NEXT:  .LBB0_32:
+; X64-HSW-NEXT:    leal (%rax,%rax,8), %eax
+; X64-HSW-NEXT:    leal (%rax,%rax,2), %eax
+; X64-HSW-NEXT:    # kill: def $eax killed $eax killed $rax
+; X64-HSW-NEXT:    retq
+; X64-HSW-NEXT:  .LBB0_7:
+; X64-HSW-NEXT:    leal (,%rax,8), %ecx
+; X64-HSW-NEXT:    jmp .LBB0_38
 ; X64-HSW-NEXT:  .LBB0_13:
 ; X64-HSW-NEXT:    leal (%rax,%rax,4), %ecx
 ; X64-HSW-NEXT:    leal (%rax,%rcx,2), %eax
@@ -292,33 +305,6 @@ define i32 @mult(i32, i32) local_unnamed_addr #0 {
 ; X64-HSW-NEXT:  .LBB0_27:
 ; X64-HSW-NEXT:    leal (%rax,%rax,4), %ecx
 ; X64-HSW-NEXT:    leal (%rax,%rcx,4), %ecx
-; X64-HSW-NEXT:    jmp .LBB0_34
-; X64-HSW-NEXT:  .LBB0_28:
-; X64-HSW-NEXT:    leal (%rax,%rax,2), %ecx
-; X64-HSW-NEXT:    shll $3, %ecx
-; X64-HSW-NEXT:    jmp .LBB0_38
-; X64-HSW-NEXT:  .LBB0_29:
-; X64-HSW-NEXT:    shll $3, %eax
-; X64-HSW-NEXT:    leal (%rax,%rax,2), %eax
-; X64-HSW-NEXT:    # kill: def $eax killed $eax killed $rax
-; X64-HSW-NEXT:    retq
-; X64-HSW-NEXT:  .LBB0_30:
-; X64-HSW-NEXT:    leal (%rax,%rax,4), %eax
-; X64-HSW-NEXT:    leal (%rax,%rax,4), %eax
-; X64-HSW-NEXT:    # kill: def $eax killed $eax killed $rax
-; X64-HSW-NEXT:    retq
-; X64-HSW-NEXT:  .LBB0_31:
-; X64-HSW-NEXT:    leal (%rax,%rax,4), %ecx
-; X64-HSW-NEXT:    leal (%rcx,%rcx,4), %ecx
-; X64-HSW-NEXT:    jmp .LBB0_34
-; X64-HSW-NEXT:  .LBB0_32:
-; X64-HSW-NEXT:    leal (%rax,%rax,8), %eax
-; X64-HSW-NEXT:    leal (%rax,%rax,2), %eax
-; X64-HSW-NEXT:    # kill: def $eax killed $eax killed $rax
-; X64-HSW-NEXT:    retq
-; X64-HSW-NEXT:  .LBB0_33:
-; X64-HSW-NEXT:    leal (%rax,%rax,8), %ecx
-; X64-HSW-NEXT:    leal (%rcx,%rcx,2), %ecx
 ; X64-HSW-NEXT:  .LBB0_34:
 ; X64-HSW-NEXT:    addl %eax, %ecx
 ; X64-HSW-NEXT:    movl %ecx, %eax
@@ -340,6 +326,10 @@ define i32 @mult(i32, i32) local_unnamed_addr #0 {
 ; X64-HSW-NEXT:  .LBB0_37:
 ; X64-HSW-NEXT:    movl %eax, %ecx
 ; X64-HSW-NEXT:    shll $5, %ecx
+; X64-HSW-NEXT:    jmp .LBB0_38
+; X64-HSW-NEXT:  .LBB0_28:
+; X64-HSW-NEXT:    leal (%rax,%rax,2), %ecx
+; X64-HSW-NEXT:    shll $3, %ecx
 ; X64-HSW-NEXT:  .LBB0_38:
 ; X64-HSW-NEXT:    subl %eax, %ecx
 ; X64-HSW-NEXT:    movl %ecx, %eax
@@ -348,6 +338,16 @@ define i32 @mult(i32, i32) local_unnamed_addr #0 {
 ; X64-HSW-NEXT:  .LBB0_40:
 ; X64-HSW-NEXT:    shll $5, %eax
 ; X64-HSW-NEXT:    # kill: def $eax killed $eax killed $rax
+; X64-HSW-NEXT:    retq
+; X64-HSW-NEXT:  .LBB0_29:
+; X64-HSW-NEXT:    shll $3, %eax
+; X64-HSW-NEXT:    leal (%rax,%rax,2), %eax
+; X64-HSW-NEXT:    # kill: def $eax killed $eax killed $rax
+; X64-HSW-NEXT:    retq
+; X64-HSW-NEXT:  .LBB0_30:
+; X64-HSW-NEXT:    leal (%rax,%rax,4), %eax
+; X64-HSW-NEXT:    leal (%rax,%rax,4), %eax
+; X64-HSW-NEXT:    # kill: def $eax killed $eax killed $rax
 ; X64-HSW-NEXT:    retq
   %3 = icmp eq i32 %1, 0
   %4 = icmp sgt i32 %1, 1
diff --git a/llvm/test/CodeGen/X86/pic.ll b/llvm/test/CodeGen/X86/pic.ll
index 7c4db752b4e04..408ea9ad71bd9 100644
--- a/llvm/test/CodeGen/X86/pic.ll
+++ b/llvm/test/CodeGen/X86/pic.ll
@@ -231,19 +231,19 @@ bb12:
 ; CHECK-I686:	.long	 .LBB7_5@GOTOFF
 ; CHECK-I686:	.long	 .LBB7_8@GOTOFF
 ; CHECK-I686:	.long	 .LBB7_7@GOTOFF
+; CHECK-X32:	.long	.LBB7_2-.LJTI7_0
+; CHECK-X32:	.long	.LBB7_2-.LJTI7_0
+; CHECK-X32:	.long	.LBB7_4-.LJTI7_0
 ; CHECK-X32:	.long	.LBB7_3-.LJTI7_0
+; CHECK-X32:	.long	.LBB7_4-.LJTI7_0
+; CHECK-X32:	.long	.LBB7_6-.LJTI7_0
 ; CHECK-X32:	.long	.LBB7_3-.LJTI7_0
-; CHECK-X32:	.long	.LBB7_12-.LJTI7_0
-; CHECK-X32:	.long	.LBB7_8-.LJTI7_0
-; CHECK-X32:	.long	.LBB7_12-.LJTI7_0
-; CHECK-X32:	.long	.LBB7_10-.LJTI7_0
-; CHECK-X32:	.long	.LBB7_8-.LJTI7_0
-; CHECK-X32:	.long	.LBB7_9-.LJTI7_0
-; CHECK-X32:	.long	.LBB7_10-.LJTI7_0
-; CHECK-X32:	.long	.LBB7_9-.LJTI7_0
-; CHECK-X32:	.long	.LBB7_12-.LJTI7_0
-; CHECK-X32:	.long	.LBB7_14-.LJTI7_0
-; CHECK-X32:	.long	.LBB7_14-.LJTI7_0
+; CHECK-X32:	.long	.LBB7_5-.LJTI7_0
+; CHECK-X32:	.long	.LBB7_6-.LJTI7_0
+; CHECK-X32:	.long	.LBB7_5-.LJTI7_0
+; CHECK-X32:	.long	.LBB7_4-.LJTI7_0
+; CHECK-X32:	.long	.LBB7_7-.LJTI7_0
+; CHECK-X32:	.long	.LBB7_7-.LJTI7_0
 }
 
 declare void @foo1(...)
diff --git a/llvm/test/CodeGen/X86/pr38743.ll b/llvm/test/CodeGen/X86/pr38743.ll
index c05310090660d..ef1c87118c811 100644
--- a/llvm/test/CodeGen/X86/pr38743.ll
+++ b/llvm/test/CodeGen/X86/pr38743.ll
@@ -27,15 +27,15 @@ define void @pr38743(i32 %a0) #1 align 2 {
 ; CHECK-NEXT:    movw %ax, -{{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    movq .str.17(%rip), %rax
 ; CHECK-NEXT:    jmp .LBB0_4
-; CHECK-NEXT:  .LBB0_1: # %bb2
-; CHECK-NEXT:    movq .str.16+7(%rip), %rax
-; CHECK-NEXT:    movq %rax, -{{[0-9]+}}(%rsp)
-; CHECK-NEXT:    movq .str.16(%rip), %rax
-; CHECK-NEXT:    jmp .LBB0_4
 ; CHECK-NEXT:  .LBB0_3: # %bb8
 ; CHECK-NEXT:    movq .str.18+6(%rip), %rax
 ; CHECK-NEXT:    movq %rax, -{{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    movq .str.18(%rip), %rax
+; CHECK-NEXT:    jmp .LBB0_4
+; CHECK-NEXT:  .LBB0_1: # %bb2
+; CHECK-NEXT:    movq .str.16+7(%rip), %rax
+; CHECK-NEXT:    movq %rax, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT:    movq .str.16(%rip), %rax
 ; CHECK-NEXT:  .LBB0_4: # %bb12
 ; CHECK-NEXT:    movq %rax, -{{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    movq -{{[0-9]+}}(%rsp), %rax
diff --git a/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll b/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
index e9448a800fd95..c50a39c99fb6c 100644
--- a/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
+++ b/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
@@ -190,14 +190,14 @@ define ptr @SyFgets(ptr %line, i64 %length, i64 %fid) {
 ; CHECK-NEXT:    movl $0, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Folded Spill
 ; CHECK-NEXT:    movl $268, %ebp ## imm = 0x10C
 ; CHECK-NEXT:    jmp LBB0_20
-; CHECK-NEXT:  LBB0_39: ## %sw.bb566
-; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT:    movl $20, %ebp
-; CHECK-NEXT:    jmp LBB0_20
 ; CHECK-NEXT:  LBB0_19: ## %sw.bb243
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
 ; CHECK-NEXT:    movl $2, %ebp
 ; CHECK-NEXT:    jmp LBB0_20
+; CHECK-NEXT:  LBB0_39: ## %sw.bb566
+; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
+; CHECK-NEXT:    movl $20, %ebp
+; CHECK-NEXT:    jmp LBB0_20
 ; CHECK-NEXT:  LBB0_32: ## %if.end517.loopexitsplit
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
 ; CHECK-NEXT:    incq %rbx
diff --git a/llvm/test/CodeGen/X86/speculative-load-hardening-indirect.ll b/llvm/test/CodeGen/X86/speculative-load-hardening-indirect.ll
index 4d0599022d538..7c8618af83d3d 100644
--- a/llvm/test/CodeGen/X86/speculative-load-hardening-indirect.ll
+++ b/llvm/test/CodeGen/X86/speculative-load-hardening-indirect.ll
@@ -534,12 +534,6 @@ define dso_local i32 @test_switch_jumptable(i32 %idx) nounwind {
 ; X64-NEXT:    movl $7, %eax
 ; X64-NEXT:    orq %rcx, %rsp
 ; X64-NEXT:    retq
-; X64-NEXT:  .LBB6_2: # %bb0
-; X64-NEXT:    cmovbeq %rax, %rcx
-; X64-NEXT:    shlq $47, %rcx
-; X64-NEXT:    movl $2, %eax
-; X64-NEXT:    orq %rcx, %rsp
-; X64-NEXT:    retq
 ; X64-NEXT:  .LBB6_4: # Block address taken
 ; X64-NEXT:    # %bb2
 ; X64-NEXT:    cmpq $.LBB6_4, %rdx
@@ -564,6 +558,12 @@ define dso_local i32 @test_switch_jumptable(i32 %idx) nounwind {
 ; X64-NEXT:    movl $11, %eax
 ; X64-NEXT:    orq %rcx, %rsp
 ; X64-NEXT:    retq
+; X64-NEXT:  .LBB6_2: # %bb0
+; X64-NEXT:    cmovbeq %rax, %rcx
+; X64-NEXT:    shlq $47, %rcx
+; X64-NEXT:    movl $2, %eax
+; X64-NEXT:    orq %rcx, %rsp
+; X64-NEXT:    retq
 ;
 ; X64-PIC-LABEL: test_switch_jumptable:
 ; X64-PIC:       # %bb.0: # %entry
@@ -589,12 +589,6 @@ define dso_local i32 @test_switch_jumptable(i32 %idx) nounwind {
 ; X64-PIC-NEXT:    movl $7, %eax
 ; X64-PIC-NEXT:    orq %rcx, %rsp
 ; X64-PIC-NEXT:    retq
-; X64-PIC-NEXT:  .LBB6_2: # %bb0
-; X64-PIC-NEXT:    cmovbeq %rax, %rcx
-; X64-PIC-NEXT:    shlq $47, %rcx
-; X64-PIC-NEXT:    movl $2, %eax
-; X64-PIC-NEXT:    orq %rcx, %rsp
-; X64-PIC-NEXT:    retq
 ; X64-PIC-NEXT:  .LBB6_4: # Block address taken
 ; X64-PIC-NEXT:    # %bb2
 ; X64-PIC-NEXT:    leaq .LBB6_4(%rip), %rsi
@@ -622,6 +616,12 @@ define dso_local i32 @test_switch_jumptable(i32 %idx) nounwind {
 ; X64-PIC-NEXT:    movl $11, %eax
 ; X64-PIC-NEXT:    orq %rcx, %rsp
 ; X64-PIC-NEXT:    retq
+; X64-PIC-NEXT:  .LBB6_2: # %bb0
+; X64-PIC-NEXT:    cmovbeq %rax, %rcx
+; X64-PIC-NEXT:    shlq $47, %rcx
+; X64-PIC-NEXT:    movl $2, %eax
+; X64-PIC-NEXT:    orq %rcx, %rsp
+; X64-PIC-NEXT:    retq
 ;
 ; X64-RETPOLINE-LABEL: test_switch_jumptable:
 ; X64-RETPOLINE:       # %bb.0: # %entry
diff --git a/llvm/test/CodeGen/X86/switch.ll b/llvm/test/CodeGen/X86/switch.ll
index f5040f2b2bab5..264c5bf15aa28 100644
--- a/llvm/test/CodeGen/X86/switch.ll
+++ b/llvm/test/CodeGen/X86/switch.ll
@@ -284,8 +284,6 @@ define void @jt_is_better(i32 %x) {
 ; CHECK-NEXT:  .LBB4_3: # %bb1
 ; CHECK-NEXT:    movl $1, %edi
 ; CHECK-NEXT:    jmp g@PLT # TAILCALL
-; CHECK-NEXT:  .LBB4_7: # %return
-; CHECK-NEXT:    retq
 ; CHECK-NEXT:  .LBB4_4: # %bb2
 ; CHECK-NEXT:    movl $2, %edi
 ; CHECK-NEXT:    jmp g@PLT # TAILCALL
@@ -295,6 +293,8 @@ define void @jt_is_better(i32 %x) {
 ; CHECK-NEXT:  .LBB4_6: # %bb4
 ; CHECK-NEXT:    movl $4, %edi
 ; CHECK-NEXT:    jmp g@PLT # TAILCALL
+; CHECK-NEXT:  .LBB4_7: # %return
+; CHECK-NEXT:    retq
 ;
 ; NOOPT-LABEL: jt_is_better:
 ; NOOPT:       # %bb.0: # %entry
@@ -1880,13 +1880,6 @@ define void @left_leaning_weight_balanced_tree(i32 %x) {
 ; CHECK-NEXT:  # %bb.7: # %bb2
 ; CHECK-NEXT:    movl $2, %edi
 ; CHECK-NEXT:    jmp g@PLT # TAILCALL
-; CHECK-NEXT:  .LBB19_12: # %entry
-; CHECK-NEXT:    cmpl $50, %edi
-; CHECK-NEXT:    je .LBB19_17
-; CHECK-NEXT:  # %bb.13: # %entry
-; CHECK-NEXT:    cmpl $60, %edi
-; CHECK-NEXT:    je .LBB19_14
-; CHECK-NEXT:    jmp .LBB19_18
 ; CHECK-NEXT:  .LBB19_8: # %entry
 ; CHECK-NEXT:    cmpl $30, %edi
 ; CHECK-NEXT:    je .LBB19_16
@@ -1896,6 +1889,14 @@ define void @left_leaning_weight_balanced_tree(i32 %x) {
 ; CHECK-NEXT:  # %bb.10: # %bb4
 ; CHECK-NEXT:    movl $4, %edi
 ; CHECK-NEXT:    jmp g@PLT # TAILCALL
+; CHECK-NEXT:  .LBB19_12: # %entry
+; CHECK-NEXT:    cmpl $50, %edi
+; CHECK-NEXT:    je .LBB19_17
+; CHECK-NEXT:  # %bb.13: # %entry
+; CHECK-NEXT:    cmpl $60, %edi
+; CHECK-NEXT:    je .LBB19_14
+; CHECK-NEXT:  .LBB19_18: # %return
+; CHECK-NEXT:    retq
 ; CHECK-NEXT:  .LBB19_15: # %bb1
 ; CHECK-NEXT:    movl $1, %edi
 ; CHECK-NEXT:    jmp g@PLT # TAILCALL
@@ -1905,8 +1906,6 @@ define void @left_leaning_weight_balanced_tree(i32 %x) {
 ; CHECK-NEXT:  .LBB19_17: # %bb5
 ; CHECK-NEXT:    movl $5, %edi
 ; CHECK-NEXT:    jmp g@PLT # TAILCALL
-; CHECK-NEXT:  .LBB19_18: # %return
-; CHECK-NEXT:    retq
 ;
 ; NOOPT-LABEL: left_leaning_weight_balanced_tree:
 ; NOOPT:       # %bb.0: # %entry
diff --git a/llvm/test/CodeGen/X86/win-catchpad.ll b/llvm/test/CodeGen/X86/win-catchpad.ll
index 59612bfe9a535..d2067dd4e51c2 100644
--- a/llvm/test/CodeGen/X86/win-catchpad.ll
+++ b/llvm/test/CodeGen/X86/win-catchpad.ll
@@ -64,13 +64,13 @@ try.cont:
 ; X86: retl
 
 ; FIXME: These should be de-duplicated.
-; X86: [[restorebb2:LBB0_[0-9]+]]: # Block address taken
-; X86-NEXT:                        # %handler2
+; X86: [[restorebb1:LBB0_[0-9]+]]: # Block address taken
+; X86-NEXT:                        # %handler1
 ; X86-NEXT: addl $12, %ebp
 ; X86: jmp [[contbb]]
 
-; X86: [[restorebb1:LBB0_[0-9]+]]: # Block address taken
-; X86-NEXT:                        # %handler1
+; X86: [[restorebb2:LBB0_[0-9]+]]: # Block address taken
+; X86-NEXT:                        # %handler2
 ; X86-NEXT: addl $12, %ebp
 ; X86: jmp [[contbb]]
 
diff --git a/llvm/unittests/Support/BlockFrequencyTest.cpp b/llvm/unittests/Support/BlockFrequencyTest.cpp
index d0374b0a8c519..18bb407e7fbde 100644
--- a/llvm/unittests/Support/BlockFrequencyTest.cpp
+++ b/llvm/unittests/Support/BlockFrequencyTest.cpp
@@ -125,4 +125,45 @@ TEST(BlockFrequencyTest, SaturatingRightShift) {
   EXPECT_EQ(Freq.getFrequency(), 0x1ULL);
 }
 
+TEST(BlockFrequencyTest, AlmostEqual) {
+  EXPECT_FALSE(BlockFrequency(0x1234).almostEqual(BlockFrequency(0), 20));
+  EXPECT_FALSE(BlockFrequency(0x1234).almostEqual(BlockFrequency(0x1233), 20));
+  EXPECT_TRUE(BlockFrequency(0x1234).almostEqual(BlockFrequency(0x1234), 20));
+
+  EXPECT_FALSE(BlockFrequency(0).almostEqual(BlockFrequency(0x1234), 20));
+  EXPECT_FALSE(BlockFrequency(0x1233).almostEqual(BlockFrequency(0x1234), 20));
+  EXPECT_TRUE(BlockFrequency(0x1234).almostEqual(BlockFrequency(0x1234), 20));
+
+  EXPECT_FALSE(BlockFrequency(0x1235).almostEqual(BlockFrequency(0x1234), 20));
+  EXPECT_FALSE(BlockFrequency(0x1234).almostEqual(BlockFrequency(0x1235), 20));
+
+  EXPECT_TRUE(BlockFrequency(0x4129).almostEqual(BlockFrequency(0x4128), 1));
+  EXPECT_TRUE(BlockFrequency(0x4129).almostEqual(BlockFrequency(0x4128), 2));
+  EXPECT_TRUE(BlockFrequency(0x4129).almostEqual(BlockFrequency(0x4128), 8));
+  EXPECT_TRUE(BlockFrequency(0x4129).almostEqual(BlockFrequency(0x4128), 14));
+  EXPECT_FALSE(BlockFrequency(0x4129).almostEqual(BlockFrequency(0x4128), 15));
+  EXPECT_FALSE(BlockFrequency(0x4129).almostEqual(BlockFrequency(0x4128), 16));
+  EXPECT_FALSE(BlockFrequency(0x4129).almostEqual(BlockFrequency(0x4128), 63));
+
+  EXPECT_FALSE(
+      BlockFrequency(0x10000000000).almostEqual(BlockFrequency(0x10), 5));
+
+  BlockFrequency Max = BlockFrequency::max();
+  EXPECT_TRUE(BlockFrequency(Max).almostEqual(Max, 0));
+  EXPECT_TRUE(BlockFrequency(Max).almostEqual(Max, 1));
+  EXPECT_TRUE(BlockFrequency(Max).almostEqual(Max, 63));
+
+  BlockFrequency Zero = BlockFrequency(0);
+  EXPECT_TRUE(BlockFrequency(Max).almostEqual(Zero, 0));
+  EXPECT_FALSE(BlockFrequency(Max).almostEqual(Zero, 1));
+  EXPECT_FALSE(BlockFrequency(Max).almostEqual(Zero, 63));
+
+  EXPECT_TRUE(BlockFrequency(Zero).almostEqual(Max, 0));
+  EXPECT_FALSE(BlockFrequency(Zero).almostEqual(Max, 1));
+  EXPECT_FALSE(BlockFrequency(Zero).almostEqual(Max, 63));
+
+  EXPECT_TRUE(BlockFrequency(Zero).almostEqual(Zero, 0));
+  EXPECT_TRUE(BlockFrequency(Zero).almostEqual(Zero, 1));
+  EXPECT_TRUE(BlockFrequency(Zero).almostEqual(Zero, 63));
+}
 }