diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c index 92a6a59cba231..4896c0184507d 100644 --- a/clang/test/Driver/riscv-arch.c +++ b/clang/test/Driver/riscv-arch.c @@ -385,9 +385,9 @@ // RUN: not %clang --target=riscv32-unknown-elf -march=rv32izfa0p1 -menable-experimental-extensions -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-BADVERS %s // RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32izfa0p1' -// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.1 for experimental extension 'zfa' (this compiler supports 0.2) +// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.1 for experimental extension 'zfa' (this compiler supports 1.0) -// RUN: %clang --target=riscv32-unknown-elf -march=rv32izfa0p2 -menable-experimental-extensions -### %s \ +// RUN: %clang --target=riscv32-unknown-elf -march=rv32izfa1p0 -menable-experimental-extensions -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-GOODVERS %s // RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-zfa" diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 4dd83cfa0620b..4b9ec42320001 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -1002,12 +1002,12 @@ // CHECK-ZACAS-EXT: __riscv_zacas 1000000{{$}} // RUN: %clang --target=riscv32-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv32izfa0p2 -x c -E -dM %s \ +// RUN: -march=rv32izfa1p0 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s // RUN: %clang --target=riscv64-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv64izfa0p2 -x c -E -dM %s \ +// RUN: -march=rv64izfa1p0 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s -// CHECK-ZFA-EXT: __riscv_zfa 2000{{$}} +// CHECK-ZFA-EXT: __riscv_zfa 1000000{{$}} // RUN: %clang --target=riscv32 -menable-experimental-extensions \ // RUN: -march=rv32izfbfmin0p8 -x c -E -dM %s \ diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 8d12d58738c60..23edaa6f29941 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -197,7 +197,7 @@ The primary goal of experimental support is to assist in the process of ratifica LLVM implements the `1.0-rc1 draft specification `_. ``experimental-zfa`` - LLVM implements the `0.2 draft specification `__. + LLVM implements the `1.0 specification `__. ``experimental-zfbfmin``, ``experimental-zvfbfmin``, ``experimental-zvfbfwma`` LLVM implements assembler support for the `0.8.0 draft specification `_. diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 660bb4e70a5a7..f68a1cae73412 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -109,6 +109,7 @@ Changes to the PowerPC Backend Changes to the RISC-V Backend ----------------------------- +* The Zfa extension version was upgraded to 1.0. * Zihintntl extension version was upgraded to 1.0 and is no longer experimental. Changes to the WebAssembly Backend diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp index c4f50b7773b75..9c7670d35a7c8 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -166,7 +166,7 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = { {"zacas", RISCVExtensionVersion{1, 0}}, - {"zfa", RISCVExtensionVersion{0, 2}}, + {"zfa", RISCVExtensionVersion{1, 0}}, {"zfbfmin", RISCVExtensionVersion{0, 8}}, {"zicfilp", RISCVExtensionVersion{0, 2}}, diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td index 7c304dca9a253..07d07d765e61e 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td @@ -7,9 +7,8 @@ //===----------------------------------------------------------------------===// // // This file describes the RISC-V instructions from the standard 'Zfa' -// additional floating-point extension, version 0.1. -// This version is still experimental as the 'Zfa' extension hasn't been -// ratified yet. +// additional floating-point extension, version 1.0. +// This version is still experimental. // //===----------------------------------------------------------------------===// diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 29eaaee57868a..5c8812cd55a50 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -243,7 +243,7 @@ ; RV32ZIFENCEI: .attribute 5, "rv32i2p1_zifencei2p0" ; RV32ZICNTR: .attribute 5, "rv32i2p1_zicntr2p0_zicsr2p0" ; RV32ZIHPM: .attribute 5, "rv32i2p1_zicsr2p0_zihpm2p0" -; RV32ZFA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfa0p2" +; RV32ZFA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfa1p0" ; RV32ZVBB: .attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zvkb1p0_zvl32b1p0" ; RV32ZVBC: .attribute 5, "rv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0" ; RV32ZVKB: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkb1p0_zvl32b1p0" @@ -332,7 +332,7 @@ ; RV64ZIFENCEI: .attribute 5, "rv64i2p1_zifencei2p0" ; RV64ZICNTR: .attribute 5, "rv64i2p1_zicntr2p0_zicsr2p0" ; RV64ZIHPM: .attribute 5, "rv64i2p1_zicsr2p0_zihpm2p0" -; RV64ZFA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfa0p2" +; RV64ZFA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfa1p0" ; RV64ZVBB: .attribute 5, "rv64i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zvkb1p0_zvl32b1p0" ; RV64ZVBC: .attribute 5, "rv64i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0" ; RV64ZVKB: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkb1p0_zvl32b1p0" diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index bf40eda456edf..12c494dc896a0 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -261,8 +261,8 @@ .attribute arch, "rv32izifencei2p0" # CHECK: attribute 5, "rv32i2p1_zifencei2p0" -.attribute arch, "rv32izfa0p2" -# CHECK: attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfa0p2" +.attribute arch, "rv32izfa1p0" +# CHECK: attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfa1p0" .attribute arch, "rv32izicond1p0" # CHECK: attribute 5, "rv32i2p1_zicond1p0" diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp index e893e0d6f9168..4eeaab727c5c0 100644 --- a/llvm/unittests/Support/RISCVISAInfoTest.cpp +++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp @@ -729,7 +729,7 @@ Experimental extensions zicfilp 0.2 This is a long dummy description zicond 1.0 zacas 1.0 - zfa 0.2 + zfa 1.0 zfbfmin 0.8 ztso 0.1 zvbb 1.0